diff options
Diffstat (limited to 'test/MC/AArch64')
78 files changed, 14120 insertions, 24 deletions
diff --git a/test/MC/AArch64/adrp-relocation.s b/test/MC/AArch64/adrp-relocation.s new file mode 100644 index 000000000000..3bcef34e4f5d --- /dev/null +++ b/test/MC/AArch64/adrp-relocation.s @@ -0,0 +1,18 @@ +// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s| llvm-readobj -r - | FileCheck %s + .text +// These should produce an ADRP/ADD pair to calculate the address of +// testfn. The important point is that LLVM shouldn't think it can deal with the +// relocation on the ADRP itself (even though it knows everything about the +// relative offsets of testfn and foo) because its value depends on where this +// object file's .text section gets relocated in memory. + adrp x0, sym + adrp x0, :got:sym + adrp x0, :gottprel:sym + adrp x0, :tlsdesc:sym + + .global sym +sym: +// CHECK: R_AARCH64_ADR_PREL_PG_HI21 sym +// CHECK: R_AARCH64_ADR_GOT_PAGE sym +// CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym +// CHECK: R_AARCH64_TLSDESC_ADR_PAGE sym diff --git a/test/MC/AArch64/basic-a64-diagnostics.s b/test/MC/AArch64/basic-a64-diagnostics.s index 1e9024c5eede..2e6e0bbd387c 100644 --- a/test/MC/AArch64/basic-a64-diagnostics.s +++ b/test/MC/AArch64/basic-a64-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 < %s 2> %t +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t // RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s //------------------------------------------------------------------------------ @@ -2892,13 +2892,13 @@ movi wzr, #0x44444444 movi w3, #0xffff movi x9, #0x0000ffff00000000 -// CHECK-ERROR: error: invalid instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: movi wzr, #0x44444444 // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR: error: invalid instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: movi w3, #0xffff // CHECK-ERROR-NEXT: ^ -// CHECK-ERROR: error: invalid instruction +// CHECK-ERROR: error: invalid operand for instruction // CHECK-ERROR-NEXT: movi x9, #0x0000ffff00000000 // CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/basic-a64-instructions.s b/test/MC/AArch64/basic-a64-instructions.s index ad3064e5e524..a50efb33109d 100644 --- a/test/MC/AArch64/basic-a64-instructions.s +++ b/test/MC/AArch64/basic-a64-instructions.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+fp-armv8 < %s | FileCheck %s .globl _func // Check that the assembler can handle the documented syntax from the ARM ARM. diff --git a/test/MC/AArch64/basic-pic.s b/test/MC/AArch64/basic-pic.s new file mode 100644 index 000000000000..a10874dcca09 --- /dev/null +++ b/test/MC/AArch64/basic-pic.s @@ -0,0 +1,98 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o -| llvm-objdump -r - | FileCheck %s + +// CHECK: RELOCATION RECORDS FOR [.rela.text] + + .file "/home/espindola/llvm/llvm/test/CodeGen/AArch64/basic-pic.ll" + .text + .globl get_globalvar + .type get_globalvar,@function +get_globalvar: // @get_globalvar + .cfi_startproc +// BB#0: + adrp x0, :got:var + ldr x0, [x0, #:got_lo12:var] + ldr w0, [x0] + ret +.Ltmp0: + .size get_globalvar, .Ltmp0-get_globalvar + .cfi_endproc + +// CHECK: R_AARCH64_ADR_GOT_PAGE var +// CHECK: R_AARCH64_LD64_GOT_LO12_NC var + + .globl get_globalvaraddr + .type get_globalvaraddr,@function +get_globalvaraddr: // @get_globalvaraddr + .cfi_startproc +// BB#0: + adrp x0, :got:var + ldr x0, [x0, #:got_lo12:var] + ret +.Ltmp1: + .size get_globalvaraddr, .Ltmp1-get_globalvaraddr + .cfi_endproc +// CHECK: R_AARCH64_ADR_GOT_PAGE var +// CHECK: R_AARCH64_LD64_GOT_LO12_NC var + + .globl get_hiddenvar + .type get_hiddenvar,@function +get_hiddenvar: // @get_hiddenvar + .cfi_startproc +// BB#0: + adrp x0, hiddenvar + ldr w0, [x0, #:lo12:hiddenvar] + ret +.Ltmp2: + .size get_hiddenvar, .Ltmp2-get_hiddenvar + .cfi_endproc +// CHECK: R_AARCH64_ADR_PREL_PG_HI21 hiddenvar +// CHECK: R_AARCH64_LDST32_ABS_LO12_NC hiddenvar + + .globl get_hiddenvaraddr + .type get_hiddenvaraddr,@function +get_hiddenvaraddr: // @get_hiddenvaraddr + .cfi_startproc +// BB#0: + adrp x0, hiddenvar + add x0, x0, #:lo12:hiddenvar + ret +.Ltmp3: + .size get_hiddenvaraddr, .Ltmp3-get_hiddenvaraddr + .cfi_endproc +// CHECK: R_AARCH64_ADR_PREL_PG_HI21 hiddenvar +// CHECK: R_AARCH64_ADD_ABS_LO12_NC hiddenvar + + .globl get_func + .type get_func,@function +get_func: // @get_func + .cfi_startproc +// BB#0: + adrp x0, :got:get_func + ldr x0, [x0, #:got_lo12:get_func] + ret +.Ltmp4: + .size get_func, .Ltmp4-get_func + .cfi_endproc + +// Particularly important that the ADRP gets a relocation, LLVM tends to think +// it can relax it because it knows where get_func is. It can't! +// CHECK: R_AARCH64_ADR_GOT_PAGE get_func +// CHECK: R_AARCH64_LD64_GOT_LO12_NC get_func + + .type var,@object // @var + .bss + .globl var + .align 2 +var: + .word 0 // 0x0 + .size var, 4 + + .hidden hiddenvar // @hiddenvar + .type hiddenvar,@object + .globl hiddenvar + .align 2 +hiddenvar: + .word 0 // 0x0 + .size hiddenvar, 4 + + diff --git a/test/MC/AArch64/elf-extern.s b/test/MC/AArch64/elf-extern.s new file mode 100644 index 000000000000..dfa3fb002ed5 --- /dev/null +++ b/test/MC/AArch64/elf-extern.s @@ -0,0 +1,33 @@ +// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s + +// External symbols are a different concept to global variables but should still +// get relocations and so on when used. + + .file "<stdin>" + .text + .globl check_extern + .type check_extern,@function +check_extern: // @check_extern + .cfi_startproc +// BB#0: + sub sp, sp, #16 +.Ltmp2: + .cfi_def_cfa sp, 16 + str x30, [sp, #8] // 8-byte Folded Spill +.Ltmp3: + .cfi_offset x30, -8 + bl memcpy + mov x0, xzr + ldr x30, [sp, #8] // 8-byte Folded Reload + add sp, sp, #16 + ret +.Ltmp4: + .size check_extern, .Ltmp4-check_extern + .cfi_endproc + + +// CHECK: Relocations [ +// CHECK: Section (2) .rela.text { +// CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy +// CHECK: } +// CHECK: ] diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index 942920be4de2..bc43113fee03 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -40,7 +40,7 @@ define void @address() { ; OBJ: } ; OBJ: Relocations [ -; OBJ: Section (1) .text { +; OBJ: Section (2) .rela.text { ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16 diff --git a/test/MC/AArch64/elf-objdump.s b/test/MC/AArch64/elf-objdump.s index 51d444a36def..3b3aa65819d8 100644 --- a/test/MC/AArch64/elf-objdump.s +++ b/test/MC/AArch64/elf-objdump.s @@ -1,5 +1,5 @@ // 64 bit little endian -// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d +// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d - // We just want to see if llvm-objdump works at all. // CHECK: .text diff --git a/test/MC/AArch64/elf-reloc-addend.s b/test/MC/AArch64/elf-reloc-addend.s new file mode 100644 index 000000000000..0e7e2cafb721 --- /dev/null +++ b/test/MC/AArch64/elf-reloc-addend.s @@ -0,0 +1,8 @@ +// RUN: llvm-mc -triple=aarch64-linux-gnu -filetype=obj -o - %s | llvm-objdump -triple=aarch64-linux-gnu -r - | FileCheck %s + + add x0, x4, #:lo12:sym +// CHECK: 0 R_AARCH64_ADD_ABS_LO12_NC sym + add x3, x5, #:lo12:sym+1 +// CHECK: 4 R_AARCH64_ADD_ABS_LO12_NC sym+1 + add x3, x5, #:lo12:sym-1 +// CHECK: 8 R_AARCH64_ADD_ABS_LO12_NC sym-1 diff --git a/test/MC/AArch64/elf-reloc-addsubimm.s b/test/MC/AArch64/elf-reloc-addsubimm.s index 0321dda332c2..e37991bfba1c 100644 --- a/test/MC/AArch64/elf-reloc-addsubimm.s +++ b/test/MC/AArch64/elf-reloc-addsubimm.s @@ -4,7 +4,7 @@ add x2, x3, #:lo12:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-condbr.s b/test/MC/AArch64/elf-reloc-condbr.s index 684e75a33cb7..b70dfa70fb8e 100644 --- a/test/MC/AArch64/elf-reloc-condbr.s +++ b/test/MC/AArch64/elf-reloc-condbr.s @@ -4,7 +4,7 @@ b.eq somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 // OBJ-NEXT: } // OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s index de43c4feac98..d4c3a4eb50d0 100644 --- a/test/MC/AArch64/elf-reloc-ldrlit.s +++ b/test/MC/AArch64/elf-reloc-ldrlit.s @@ -7,7 +7,7 @@ prfm pldl3keep, some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-ldstunsimm.s b/test/MC/AArch64/elf-reloc-ldstunsimm.s index e1f841bd20f7..371e7e51f245 100644 --- a/test/MC/AArch64/elf-reloc-ldstunsimm.s +++ b/test/MC/AArch64/elf-reloc-ldstunsimm.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+fp-armv8 -filetype=obj %s -o - | \ // RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ldrb w0, [sp, #:lo12:some_label] @@ -8,7 +8,7 @@ str q0, [sp, #:lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-movw.s b/test/MC/AArch64/elf-reloc-movw.s index 8a7e532cdd23..333159562c0f 100644 --- a/test/MC/AArch64/elf-reloc-movw.s +++ b/test/MC/AArch64/elf-reloc-movw.s @@ -23,7 +23,7 @@ movn x19, #:abs_g2_s:some_label // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-pcreladdressing.s b/test/MC/AArch64/elf-reloc-pcreladdressing.s index b5f072712fd7..093891d931aa 100644 --- a/test/MC/AArch64/elf-reloc-pcreladdressing.s +++ b/test/MC/AArch64/elf-reloc-pcreladdressing.s @@ -8,7 +8,7 @@ ldr x0, [x5, #:got_lo12:some_label] // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0 // OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0 // OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0 diff --git a/test/MC/AArch64/elf-reloc-tstb.s b/test/MC/AArch64/elf-reloc-tstb.s index 037e89632e82..25c98163b584 100644 --- a/test/MC/AArch64/elf-reloc-tstb.s +++ b/test/MC/AArch64/elf-reloc-tstb.s @@ -5,7 +5,7 @@ tbnz w3, #15, somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/elf-reloc-uncondbrimm.s b/test/MC/AArch64/elf-reloc-uncondbrimm.s index bead07c12d2c..9ac66bd876a7 100644 --- a/test/MC/AArch64/elf-reloc-uncondbrimm.s +++ b/test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -5,7 +5,7 @@ bl somewhere // OBJ: Relocations [ -// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: Section (2) .rela.text { // OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0 // OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 // OBJ-NEXT: } diff --git a/test/MC/AArch64/gicv3-regs-diagnostics.s b/test/MC/AArch64/gicv3-regs-diagnostics.s index e891adbbb375..bc005b1d5304 100644 --- a/test/MC/AArch64/gicv3-regs-diagnostics.s +++ b/test/MC/AArch64/gicv3-regs-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s // Write-only mrs x10, icc_eoir1_el1 diff --git a/test/MC/AArch64/inline-asm-modifiers.s b/test/MC/AArch64/inline-asm-modifiers.s new file mode 100644 index 000000000000..cf34a952e90c --- /dev/null +++ b/test/MC/AArch64/inline-asm-modifiers.s @@ -0,0 +1,209 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -mattr=+fp-armv8 < %s | llvm-objdump -r - | FileCheck %s + + .file "<stdin>" + .text + .globl test_inline_modifier_L + .type test_inline_modifier_L,@function +test_inline_modifier_L: // @test_inline_modifier_L +// BB#0: + //APP + add x0, x0, #:lo12:var_simple + //NO_APP + //APP + ldr x0, [x0, #:got_lo12:var_got] + //NO_APP + //APP + add x0, x0, #:tlsdesc_lo12:var_tlsgd + //NO_APP + //APP + add x0, x0, #:dtprel_lo12:var_tlsld + //NO_APP + //APP + ldr x0, [x0, #:gottprel_lo12:var_tlsie] + //NO_APP + //APP + add x0, x0, #:tprel_lo12:var_tlsle + //NO_APP + ret +.Ltmp0: + .size test_inline_modifier_L, .Ltmp0-test_inline_modifier_L + +// CHECK: R_AARCH64_ADD_ABS_LO12_NC var_simple +// CHECK: R_AARCH64_LD64_GOT_LO12_NC var_got +// CHECK: R_AARCH64_TLSDESC_ADD_LO12_NC var_tlsgd +// CHECK: R_AARCH64_TLSLD_ADD_DTPREL_LO12 var_tlsld +// CHECK: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC var_tlsie +// CHECK: R_AARCH64_TLSLE_ADD_TPREL_LO12 var_tlsle + + .globl test_inline_modifier_G + .type test_inline_modifier_G,@function +test_inline_modifier_G: // @test_inline_modifier_G +// BB#0: + //APP + add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12 + //NO_APP + //APP + add x0, x0, #:tprel_hi12:var_tlsle, lsl #12 + //NO_APP + ret +.Ltmp1: + .size test_inline_modifier_G, .Ltmp1-test_inline_modifier_G + +// CHECK: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var_tlsld +// CHECK: R_AARCH64_TLSLE_ADD_TPREL_HI12 var_tlsle + + .globl test_inline_modifier_A + .type test_inline_modifier_A,@function +test_inline_modifier_A: // @test_inline_modifier_A +// BB#0: + //APP + adrp x0, var_simple + //NO_APP + //APP + adrp x0, :got:var_got + //NO_APP + //APP + adrp x0, :tlsdesc:var_tlsgd + //NO_APP + //APP + adrp x0, :gottprel:var_tlsie + //NO_APP + ret +.Ltmp2: + .size test_inline_modifier_A, .Ltmp2-test_inline_modifier_A +// CHECK: R_AARCH64_ADR_PREL_PG_HI21 var_simple +// CHECK: R_AARCH64_ADR_GOT_PAGE var_got +// CHECK: R_AARCH64_TLSDESC_ADR_PAGE var_tlsgd +// CHECK: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 var_tlsie + + .globl test_inline_modifier_wx + .type test_inline_modifier_wx,@function +test_inline_modifier_wx: // @test_inline_modifier_wx +// BB#0: + mov w2, w0 + //APP + add w2, w2, w2 + //NO_APP + mov w2, w0 + //APP + add w2, w2, w2 + //NO_APP + //APP + add x0, x0, x0 + //NO_APP + mov x0, x1 + //APP + add x0, x0, x0 + //NO_APP + mov x0, x1 + //APP + add w0, w0, w0 + //NO_APP + //APP + add x1, x1, x1 + //NO_APP + //APP + add w0, wzr, wzr + //NO_APP + //APP + add x0, xzr, xzr + //NO_APP + ret +.Ltmp3: + .size test_inline_modifier_wx, .Ltmp3-test_inline_modifier_wx + + .globl test_inline_modifier_bhsdq + .type test_inline_modifier_bhsdq,@function +test_inline_modifier_bhsdq: // @test_inline_modifier_bhsdq +// BB#0: + //APP + ldr b0, [sp] + //NO_APP + //APP + ldr h0, [sp] + //NO_APP + //APP + ldr s0, [sp] + //NO_APP + //APP + ldr d0, [sp] + //NO_APP + //APP + ldr q0, [sp] + //NO_APP + //APP + ldr b0, [sp] + //NO_APP + //APP + ldr h0, [sp] + //NO_APP + //APP + ldr s0, [sp] + //NO_APP + //APP + ldr d0, [sp] + //NO_APP + //APP + ldr q0, [sp] + //NO_APP + ret +.Ltmp4: + .size test_inline_modifier_bhsdq, .Ltmp4-test_inline_modifier_bhsdq + + .globl test_inline_modifier_c + .type test_inline_modifier_c,@function +test_inline_modifier_c: // @test_inline_modifier_c +// BB#0: + //APP + adr x0, 3 + //NO_APP + ret +.Ltmp5: + .size test_inline_modifier_c, .Ltmp5-test_inline_modifier_c + + .hidden var_simple // @var_simple + .type var_simple,@object + .bss + .globl var_simple + .align 2 +var_simple: + .word 0 // 0x0 + .size var_simple, 4 + + .type var_got,@object // @var_got + .globl var_got + .align 2 +var_got: + .word 0 // 0x0 + .size var_got, 4 + + .type var_tlsgd,@object // @var_tlsgd + .section .tbss,"awT",@nobits + .globl var_tlsgd + .align 2 +var_tlsgd: + .word 0 // 0x0 + .size var_tlsgd, 4 + + .type var_tlsld,@object // @var_tlsld + .globl var_tlsld + .align 2 +var_tlsld: + .word 0 // 0x0 + .size var_tlsld, 4 + + .type var_tlsie,@object // @var_tlsie + .globl var_tlsie + .align 2 +var_tlsie: + .word 0 // 0x0 + .size var_tlsie, 4 + + .type var_tlsle,@object // @var_tlsle + .globl var_tlsle + .align 2 +var_tlsle: + .word 0 // 0x0 + .size var_tlsle, 4 + + diff --git a/test/MC/AArch64/jump-table.s b/test/MC/AArch64/jump-table.s new file mode 100644 index 000000000000..578ebf4e6608 --- /dev/null +++ b/test/MC/AArch64/jump-table.s @@ -0,0 +1,59 @@ +// RUN: llvm-mc < %s -triple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s + + .file "<stdin>" + .text + .globl test_jumptable + .type test_jumptable,@function +test_jumptable: // @test_jumptable + .cfi_startproc +// BB#0: + ubfx w1, w0, #0, #32 + cmp w0, #4 + b.hi .LBB0_3 +// BB#1: + adrp x0, .LJTI0_0 + add x0, x0, #:lo12:.LJTI0_0 + ldr x0, [x0, x1, lsl #3] + br x0 +.LBB0_2: // %lbl1 + movz x0, #1 + ret +.LBB0_3: // %def + mov x0, xzr + ret +.LBB0_4: // %lbl2 + movz x0, #2 + ret +.LBB0_5: // %lbl3 + movz x0, #4 + ret +.LBB0_6: // %lbl4 + movz x0, #8 + ret +.Ltmp0: + .size test_jumptable, .Ltmp0-test_jumptable + .cfi_endproc + .section .rodata,"a",@progbits + .align 3 +.LJTI0_0: + .xword .LBB0_2 + .xword .LBB0_4 + .xword .LBB0_5 + .xword .LBB0_3 + .xword .LBB0_6 + + + +// First make sure we get a page/lo12 pair in .text to pick up the jump-table + +// CHECK: Relocations [ +// CHECK: Section ({{[0-9]+}}) .rela.text { +// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 .rodata +// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC .rodata +// CHECK: } + +// Also check the targets in .rodata are relocated +// CHECK: Section ({{[0-9]+}}) .rela.rodata { +// CHECK-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ABS64 .text +// CHECK: } +// CHECK: ] diff --git a/test/MC/AArch64/lit.local.cfg b/test/MC/AArch64/lit.local.cfg index cc02173c8ed4..75dba81bc0b5 100644 --- a/test/MC/AArch64/lit.local.cfg +++ b/test/MC/AArch64/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.ll', '.c', '.cpp', '.s'] - targets = set(config.root.targets_to_build.split()) if not 'AArch64' in targets: config.unsupported = True
\ No newline at end of file diff --git a/test/MC/AArch64/neon-2velem.s b/test/MC/AArch64/neon-2velem.s new file mode 100644 index 000000000000..cde792a2fb65 --- /dev/null +++ b/test/MC/AArch64/neon-2velem.s @@ -0,0 +1,271 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions with 2 vectors and an element +//------------------------------------------------------------------------------ + + mla v0.2s, v1.2s, v2.s[2] + mla v0.2s, v1.2s, v22.s[2] + mla v3.4s, v8.4s, v2.s[1] + mla v3.4s, v8.4s, v22.s[3] + +// CHECK: mla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x08,0x82,0x2f] +// CHECK: mla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x08,0x96,0x2f] +// CHECK: mla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x01,0xa2,0x6f] +// CHECK: mla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x09,0xb6,0x6f] + + mla v0.4h, v1.4h, v2.h[2] + mla v0.4h, v1.4h, v15.h[2] + mla v0.8h, v1.8h, v2.h[7] + mla v0.8h, v1.8h, v14.h[6] + +// CHECK: mla v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x00,0x62,0x2f] +// CHECK: mla v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x00,0x6f,0x2f] +// CHECK: mla v0.8h, v1.8h, v2.h[7] // encoding: [0x20,0x08,0x72,0x6f] +// CHECK: mla v0.8h, v1.8h, v14.h[6] // encoding: [0x20,0x08,0x6e,0x6f] + + mls v0.2s, v1.2s, v2.s[2] + mls v0.2s, v1.2s, v22.s[2] + mls v3.4s, v8.4s, v2.s[1] + mls v3.4s, v8.4s, v22.s[3] + +// CHECK: mls v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x48,0x82,0x2f] +// CHECK: mls v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x48,0x96,0x2f] +// CHECK: mls v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x41,0xa2,0x6f] +// CHECK: mls v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x49,0xb6,0x6f] + + mls v0.4h, v1.4h, v2.h[2] + mls v0.4h, v1.4h, v15.h[2] + mls v0.8h, v1.8h, v2.h[7] + mls v0.8h, v1.8h, v14.h[6] + +// CHECK: mls v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x40,0x62,0x2f] +// CHECK: mls v0.4h, v1.4h, v15.h[2] // encoding: [0x20,0x40,0x6f,0x2f] +// CHECK: mls v0.8h, v1.8h, v2.h[7] // encoding: [0x20,0x48,0x72,0x6f] +// CHECK: mls v0.8h, v1.8h, v14.h[6] // encoding: [0x20,0x48,0x6e,0x6f] + + fmla v0.2s, v1.2s, v2.s[2] + fmla v0.2s, v1.2s, v22.s[2] + fmla v3.4s, v8.4s, v2.s[1] + fmla v3.4s, v8.4s, v22.s[3] + fmla v0.2d, v1.2d, v2.d[1] + fmla v0.2d, v1.2d, v22.d[1] + +// CHECK: fmla v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x18,0x82,0x0f] +// CHECK: fmla v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x18,0x96,0x0f] +// CHECK: fmla v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x11,0xa2,0x4f] +// CHECK: fmla v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x19,0xb6,0x4f] +// CHECK: fmla v0.2d, v1.2d, v2.d[1] // encoding: [0x20,0x18,0xc2,0x4f] +// CHECK: fmla v0.2d, v1.2d, v22.d[1] // encoding: [0x20,0x18,0xd6,0x4f] + + fmls v0.2s, v1.2s, v2.s[2] + fmls v0.2s, v1.2s, v22.s[2] + fmls v3.4s, v8.4s, v2.s[1] + fmls v3.4s, v8.4s, v22.s[3] + fmls v0.2d, v1.2d, v2.d[1] + fmls v0.2d, v1.2d, v22.d[1] + +// CHECK: fmls v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x58,0x82,0x0f] +// CHECK: fmls v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x58,0x96,0x0f] +// CHECK: fmls v3.4s, v8.4s, v2.s[1] // encoding: [0x03,0x51,0xa2,0x4f] +// CHECK: fmls v3.4s, v8.4s, v22.s[3] // encoding: [0x03,0x59,0xb6,0x4f] +// CHECK: fmls v0.2d, v1.2d, v2.d[1] // encoding: [0x20,0x58,0xc2,0x4f] +// CHECK: fmls v0.2d, v1.2d, v22.d[1] // encoding: [0x20,0x58,0xd6,0x4f] + + smlal v0.4s, v1.4h, v2.h[2] + smlal v0.2d, v1.2s, v2.s[2] + smlal v0.2d, v1.2s, v22.s[2] + smlal2 v0.4s, v1.8h, v1.h[2] + smlal2 v0.2d, v1.4s, v1.s[2] + smlal2 v0.2d, v1.4s, v22.s[2] + +// CHECK: smlal v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x20,0x62,0x0f] +// CHECK: smlal v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x28,0x82,0x0f] +// CHECK: smlal v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x28,0x96,0x0f] +// CHECK: smlal2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x20,0x61,0x4f] +// CHECK: smlal2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x28,0x81,0x4f] +// CHECK: smlal2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x28,0x96,0x4f] + + smlsl v0.4s, v1.4h, v2.h[2] + smlsl v0.2d, v1.2s, v2.s[2] + smlsl v0.2d, v1.2s, v22.s[2] + smlsl2 v0.4s, v1.8h, v1.h[2] + smlsl2 v0.2d, v1.4s, v1.s[2] + smlsl2 v0.2d, v1.4s, v22.s[2] + +// CHECK: smlsl v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x60,0x62,0x0f] +// CHECK: smlsl v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x68,0x82,0x0f] +// CHECK: smlsl v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x68,0x96,0x0f] +// CHECK: smlsl2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x60,0x61,0x4f] +// CHECK: smlsl2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x68,0x81,0x4f] +// CHECK: smlsl2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x68,0x96,0x4f] + + sqdmlal v0.4s, v1.4h, v2.h[2] + sqdmlal v0.2d, v1.2s, v2.s[2] + sqdmlal v0.2d, v1.2s, v22.s[2] + sqdmlal2 v0.4s, v1.8h, v1.h[2] + sqdmlal2 v0.2d, v1.4s, v1.s[2] + sqdmlal2 v0.2d, v1.4s, v22.s[2] + +// CHECK: sqdmlal v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x30,0x62,0x0f] +// CHECK: sqdmlal v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x38,0x82,0x0f] +// CHECK: sqdmlal v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x38,0x96,0x0f] +// CHECK: sqdmlal2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x30,0x61,0x4f] +// CHECK: sqdmlal2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x38,0x81,0x4f] +// CHECK: sqdmlal2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x38,0x96,0x4f] + + umlal v0.4s, v1.4h, v2.h[2] + umlal v0.2d, v1.2s, v2.s[2] + umlal v0.2d, v1.2s, v22.s[2] + umlal2 v0.4s, v1.8h, v1.h[2] + umlal2 v0.2d, v1.4s, v1.s[2] + umlal2 v0.2d, v1.4s, v22.s[2] + +// CHECK: umlal v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x20,0x62,0x2f] +// CHECK: umlal v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x28,0x82,0x2f] +// CHECK: umlal v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x28,0x96,0x2f] +// CHECK: umlal2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x20,0x61,0x6f] +// CHECK: umlal2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x28,0x81,0x6f] +// CHECK: umlal2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x28,0x96,0x6f] + + umlsl v0.4s, v1.4h, v2.h[2] + umlsl v0.2d, v1.2s, v2.s[2] + umlsl v0.2d, v1.2s, v22.s[2] + umlsl2 v0.4s, v1.8h, v1.h[2] + umlsl2 v0.2d, v1.4s, v1.s[2] + umlsl2 v0.2d, v1.4s, v22.s[2] + +// CHECK: umlsl v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x60,0x62,0x2f] +// CHECK: umlsl v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x68,0x82,0x2f] +// CHECK: umlsl v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x68,0x96,0x2f] +// CHECK: umlsl2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x60,0x61,0x6f] +// CHECK: umlsl2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x68,0x81,0x6f] +// CHECK: umlsl2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x68,0x96,0x6f] + + sqdmlsl v0.4s, v1.4h, v2.h[2] + sqdmlsl v0.2d, v1.2s, v2.s[2] + sqdmlsl v0.2d, v1.2s, v22.s[2] + sqdmlsl2 v0.4s, v1.8h, v1.h[2] + sqdmlsl2 v0.2d, v1.4s, v1.s[2] + sqdmlsl2 v0.2d, v1.4s, v22.s[2] + +// CHECK: sqdmlsl v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0x70,0x62,0x0f] +// CHECK: sqdmlsl v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0x78,0x82,0x0f] +// CHECK: sqdmlsl v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0x78,0x96,0x0f] +// CHECK: sqdmlsl2 v0.4s, v1.8h, v1.h[2] // encoding: [0x20,0x70,0x61,0x4f] +// CHECK: sqdmlsl2 v0.2d, v1.4s, v1.s[2] // encoding: [0x20,0x78,0x81,0x4f] +// CHECK: sqdmlsl2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0x78,0x96,0x4f] + + mul v0.4h, v1.4h, v2.h[2] + mul v0.8h, v1.8h, v2.h[2] + mul v0.2s, v1.2s, v2.s[2] + mul v0.2s, v1.2s, v22.s[2] + mul v0.4s, v1.4s, v2.s[2] + mul v0.4s, v1.4s, v22.s[2] + +// CHECK: mul v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0x80,0x62,0x0f] +// CHECK: mul v0.8h, v1.8h, v2.h[2] // encoding: [0x20,0x80,0x62,0x4f] +// CHECK: mul v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x88,0x82,0x0f] +// CHECK: mul v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x88,0x96,0x0f] +// CHECK: mul v0.4s, v1.4s, v2.s[2] // encoding: [0x20,0x88,0x82,0x4f] +// CHECK: mul v0.4s, v1.4s, v22.s[2] // encoding: [0x20,0x88,0x96,0x4f] + + fmul v0.2s, v1.2s, v2.s[2] + fmul v0.2s, v1.2s, v22.s[2] + fmul v0.4s, v1.4s, v2.s[2] + fmul v0.4s, v1.4s, v22.s[2] + fmul v0.2d, v1.2d, v2.d[1] + fmul v0.2d, v1.2d, v22.d[1] + +// CHECK: fmul v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x98,0x82,0x0f] +// CHECK: fmul v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x98,0x96,0x0f] +// CHECK: fmul v0.4s, v1.4s, v2.s[2] // encoding: [0x20,0x98,0x82,0x4f] +// CHECK: fmul v0.4s, v1.4s, v22.s[2] // encoding: [0x20,0x98,0x96,0x4f] +// CHECK: fmul v0.2d, v1.2d, v2.d[1] // encoding: [0x20,0x98,0xc2,0x4f] +// CHECK: fmul v0.2d, v1.2d, v22.d[1] // encoding: [0x20,0x98,0xd6,0x4f] + + fmulx v0.2s, v1.2s, v2.s[2] + fmulx v0.2s, v1.2s, v22.s[2] + fmulx v0.4s, v1.4s, v2.s[2] + fmulx v0.4s, v1.4s, v22.s[2] + fmulx v0.2d, v1.2d, v2.d[1] + fmulx v0.2d, v1.2d, v22.d[1] + +// CHECK: fmulx v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0x98,0x82,0x2f] +// CHECK: fmulx v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0x98,0x96,0x2f] +// CHECK: fmulx v0.4s, v1.4s, v2.s[2] // encoding: [0x20,0x98,0x82,0x6f] +// CHECK: fmulx v0.4s, v1.4s, v22.s[2] // encoding: [0x20,0x98,0x96,0x6f] +// CHECK: fmulx v0.2d, v1.2d, v2.d[1] // encoding: [0x20,0x98,0xc2,0x6f] +// CHECK: fmulx v0.2d, v1.2d, v22.d[1] // encoding: [0x20,0x98,0xd6,0x6f] + + smull v0.4s, v1.4h, v2.h[2] + smull v0.2d, v1.2s, v2.s[2] + smull v0.2d, v1.2s, v22.s[2] + smull2 v0.4s, v1.8h, v2.h[2] + smull2 v0.2d, v1.4s, v2.s[2] + smull2 v0.2d, v1.4s, v22.s[2] + +// CHECK: smull v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0xa0,0x62,0x0f] +// CHECK: smull v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0xa8,0x82,0x0f] +// CHECK: smull v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0xa8,0x96,0x0f] +// CHECK: smull2 v0.4s, v1.8h, v2.h[2] // encoding: [0x20,0xa0,0x62,0x4f] +// CHECK: smull2 v0.2d, v1.4s, v2.s[2] // encoding: [0x20,0xa8,0x82,0x4f] +// CHECK: smull2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0xa8,0x96,0x4f] + + umull v0.4s, v1.4h, v2.h[2] + umull v0.2d, v1.2s, v2.s[2] + umull v0.2d, v1.2s, v22.s[2] + umull2 v0.4s, v1.8h, v2.h[2] + umull2 v0.2d, v1.4s, v2.s[2] + umull2 v0.2d, v1.4s, v22.s[2] + +// CHECK: umull v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0xa0,0x62,0x2f] +// CHECK: umull v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0xa8,0x82,0x2f] +// CHECK: umull v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0xa8,0x96,0x2f] +// CHECK: umull2 v0.4s, v1.8h, v2.h[2] // encoding: [0x20,0xa0,0x62,0x6f] +// CHECK: umull2 v0.2d, v1.4s, v2.s[2] // encoding: [0x20,0xa8,0x82,0x6f] +// CHECK: umull2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0xa8,0x96,0x6f] + + sqdmull v0.4s, v1.4h, v2.h[2] + sqdmull v0.2d, v1.2s, v2.s[2] + sqdmull v0.2d, v1.2s, v22.s[2] + sqdmull2 v0.4s, v1.8h, v2.h[2] + sqdmull2 v0.2d, v1.4s, v2.s[2] + sqdmull2 v0.2d, v1.4s, v22.s[2] + +// CHECK: sqdmull v0.4s, v1.4h, v2.h[2] // encoding: [0x20,0xb0,0x62,0x0f] +// CHECK: sqdmull v0.2d, v1.2s, v2.s[2] // encoding: [0x20,0xb8,0x82,0x0f] +// CHECK: sqdmull v0.2d, v1.2s, v22.s[2] // encoding: [0x20,0xb8,0x96,0x0f] +// CHECK: sqdmull2 v0.4s, v1.8h, v2.h[2] // encoding: [0x20,0xb0,0x62,0x4f] +// CHECK: sqdmull2 v0.2d, v1.4s, v2.s[2] // encoding: [0x20,0xb8,0x82,0x4f] +// CHECK: sqdmull2 v0.2d, v1.4s, v22.s[2] // encoding: [0x20,0xb8,0x96,0x4f] + + sqdmulh v0.4h, v1.4h, v2.h[2] + sqdmulh v0.8h, v1.8h, v2.h[2] + sqdmulh v0.2s, v1.2s, v2.s[2] + sqdmulh v0.2s, v1.2s, v22.s[2] + sqdmulh v0.4s, v1.4s, v2.s[2] + sqdmulh v0.4s, v1.4s, v22.s[2] + +// CHECK: sqdmulh v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0xc0,0x62,0x0f] +// CHECK: sqdmulh v0.8h, v1.8h, v2.h[2] // encoding: [0x20,0xc0,0x62,0x4f] +// CHECK: sqdmulh v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0xc8,0x82,0x0f] +// CHECK: sqdmulh v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0xc8,0x96,0x0f] +// CHECK: sqdmulh v0.4s, v1.4s, v2.s[2] // encoding: [0x20,0xc8,0x82,0x4f] +// CHECK: sqdmulh v0.4s, v1.4s, v22.s[2] // encoding: [0x20,0xc8,0x96,0x4f] + + sqrdmulh v0.4h, v1.4h, v2.h[2] + sqrdmulh v0.8h, v1.8h, v2.h[2] + sqrdmulh v0.2s, v1.2s, v2.s[2] + sqrdmulh v0.2s, v1.2s, v22.s[2] + sqrdmulh v0.4s, v1.4s, v2.s[2] + sqrdmulh v0.4s, v1.4s, v22.s[2] + +// CHECK: sqrdmulh v0.4h, v1.4h, v2.h[2] // encoding: [0x20,0xd0,0x62,0x0f] +// CHECK: sqrdmulh v0.8h, v1.8h, v2.h[2] // encoding: [0x20,0xd0,0x62,0x4f] +// CHECK: sqrdmulh v0.2s, v1.2s, v2.s[2] // encoding: [0x20,0xd8,0x82,0x0f] +// CHECK: sqrdmulh v0.2s, v1.2s, v22.s[2] // encoding: [0x20,0xd8,0x96,0x0f] +// CHECK: sqrdmulh v0.4s, v1.4s, v2.s[2] // encoding: [0x20,0xd8,0x82,0x4f] +// CHECK: sqrdmulh v0.4s, v1.4s, v22.s[2] // encoding: [0x20,0xd8,0x96,0x4f] diff --git a/test/MC/AArch64/neon-3vdiff.s b/test/MC/AArch64/neon-3vdiff.s new file mode 100644 index 000000000000..3ff86bfd6a40 --- /dev/null +++ b/test/MC/AArch64/neon-3vdiff.s @@ -0,0 +1,415 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions with 3 different vector data types +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Long +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Long - Variant 1 +//------------------------------------------------------------------------------ + + saddl v0.8h, v1.8b, v2.8b + saddl v0.4s, v1.4h, v2.4h + saddl v0.2d, v1.2s, v2.2s + +// CHECK: saddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x0e] +// CHECK: saddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x0e] +// CHECK: saddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x0e] + + saddl2 v0.4s, v1.8h, v2.8h + saddl2 v0.8h, v1.16b, v2.16b + saddl2 v0.2d, v1.4s, v2.4s + +// CHECK: saddl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x00,0x62,0x4e] +// CHECK: saddl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x00,0x22,0x4e] +// CHECK: saddl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x00,0xa2,0x4e] + + uaddl v0.8h, v1.8b, v2.8b + uaddl v0.4s, v1.4h, v2.4h + uaddl v0.2d, v1.2s, v2.2s + +// CHECK: uaddl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x00,0x22,0x2e] +// CHECK: uaddl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x00,0x62,0x2e] +// CHECK: uaddl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x00,0xa2,0x2e] + + uaddl2 v0.8h, v1.16b, v2.16b + uaddl2 v0.4s, v1.8h, v2.8h + uaddl2 v0.2d, v1.4s, v2.4s + +// CHECK: uaddl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x00,0x22,0x6e] +// CHECK: uaddl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x00,0x62,0x6e] +// CHECK: uaddl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x00,0xa2,0x6e] + + ssubl v0.8h, v1.8b, v2.8b + ssubl v0.4s, v1.4h, v2.4h + ssubl v0.2d, v1.2s, v2.2s + +// CHECK: ssubl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x20,0x22,0x0e] +// CHECK: ssubl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x20,0x62,0x0e] +// CHECK: ssubl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x20,0xa2,0x0e] + + ssubl2 v0.8h, v1.16b, v2.16b + ssubl2 v0.4s, v1.8h, v2.8h + ssubl2 v0.2d, v1.4s, v2.4s + +// CHECK: ssubl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x20,0x22,0x4e] +// CHECK: ssubl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x20,0x62,0x4e] +// CHECK: ssubl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x20,0xa2,0x4e] + + usubl v0.8h, v1.8b, v2.8b + usubl v0.4s, v1.4h, v2.4h + usubl v0.2d, v1.2s, v2.2s + +// CHECK: usubl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x20,0x22,0x2e] +// CHECK: usubl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x20,0x62,0x2e] +// CHECK: usubl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x20,0xa2,0x2e] + + usubl2 v0.8h, v1.16b, v2.16b + usubl2 v0.4s, v1.8h, v2.8h + usubl2 v0.2d, v1.4s, v2.4s + +// CHECK: usubl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x20,0x22,0x6e] +// CHECK: usubl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x20,0x62,0x6e] +// CHECK: usubl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x20,0xa2,0x6e] + + sabal v0.8h, v1.8b, v2.8b + sabal v0.4s, v1.4h, v2.4h + sabal v0.2d, v1.2s, v2.2s + +// CHECK: sabal v0.8h, v1.8b, v2.8b // encoding: [0x20,0x50,0x22,0x0e] +// CHECK: sabal v0.4s, v1.4h, v2.4h // encoding: [0x20,0x50,0x62,0x0e] +// CHECK: sabal v0.2d, v1.2s, v2.2s // encoding: [0x20,0x50,0xa2,0x0e] + + sabal2 v0.8h, v1.16b, v2.16b + sabal2 v0.4s, v1.8h, v2.8h + sabal2 v0.2d, v1.4s, v2.4s + +// CHECK: sabal2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x50,0x22,0x4e] +// CHECK: sabal2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x50,0x62,0x4e] +// CHECK: sabal2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x50,0xa2,0x4e] + + uabal v0.8h, v1.8b, v2.8b + uabal v0.4s, v1.4h, v2.4h + uabal v0.2d, v1.2s, v2.2s + +// CHECK: uabal v0.8h, v1.8b, v2.8b // encoding: [0x20,0x50,0x22,0x2e] +// CHECK: uabal v0.4s, v1.4h, v2.4h // encoding: [0x20,0x50,0x62,0x2e] +// CHECK: uabal v0.2d, v1.2s, v2.2s // encoding: [0x20,0x50,0xa2,0x2e] + + uabal2 v0.8h, v1.16b, v2.16b + uabal2 v0.4s, v1.8h, v2.8h + uabal2 v0.2d, v1.4s, v2.4s + +// CHECK: uabal2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x50,0x22,0x6e] +// CHECK: uabal2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x50,0x62,0x6e] +// CHECK: uabal2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x50,0xa2,0x6e] + + sabdl v0.8h, v1.8b, v2.8b + sabdl v0.4s, v1.4h, v2.4h + sabdl v0.2d, v1.2s, v2.2s + +// CHECK: sabdl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x70,0x22,0x0e] +// CHECK: sabdl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x70,0x62,0x0e] +// CHECK: sabdl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x70,0xa2,0x0e] + + sabdl2 v0.8h, v1.16b, v2.16b + sabdl2 v0.4s, v1.8h, v2.8h + sabdl2 v0.2d, v1.4s, v2.4s + +// CHECK: sabdl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x70,0x22,0x4e] +// CHECK: sabdl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x70,0x62,0x4e] +// CHECK: sabdl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x70,0xa2,0x4e] + + uabdl v0.8h, v1.8b, v2.8b + uabdl v0.4s, v1.4h, v2.4h + uabdl v0.2d, v1.2s, v2.2s + +// CHECK: uabdl v0.8h, v1.8b, v2.8b // encoding: [0x20,0x70,0x22,0x2e] +// CHECK: uabdl v0.4s, v1.4h, v2.4h // encoding: [0x20,0x70,0x62,0x2e] +// CHECK: uabdl v0.2d, v1.2s, v2.2s // encoding: [0x20,0x70,0xa2,0x2e] + + uabdl2 v0.8h, v1.16b, v2.16b + uabdl2 v0.4s, v1.8h, v2.8h + uabdl2 v0.2d, v1.4s, v2.4s + +// CHECK: uabdl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x70,0x22,0x6e] +// CHECK: uabdl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x70,0x62,0x6e] +// CHECK: uabdl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x70,0xa2,0x6e] + + smlal v0.8h, v1.8b, v2.8b + smlal v0.4s, v1.4h, v2.4h + smlal v0.2d, v1.2s, v2.2s + +// CHECK: smlal v0.8h, v1.8b, v2.8b // encoding: [0x20,0x80,0x22,0x0e] +// CHECK: smlal v0.4s, v1.4h, v2.4h // encoding: [0x20,0x80,0x62,0x0e] +// CHECK: smlal v0.2d, v1.2s, v2.2s // encoding: [0x20,0x80,0xa2,0x0e] + + smlal2 v0.8h, v1.16b, v2.16b + smlal2 v0.4s, v1.8h, v2.8h + smlal2 v0.2d, v1.4s, v2.4s + +// CHECK: smlal2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x80,0x22,0x4e] +// CHECK: smlal2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x80,0x62,0x4e] +// CHECK: smlal2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x80,0xa2,0x4e] + + umlal v0.8h, v1.8b, v2.8b + umlal v0.4s, v1.4h, v2.4h + umlal v0.2d, v1.2s, v2.2s + +// CHECK: umlal v0.8h, v1.8b, v2.8b // encoding: [0x20,0x80,0x22,0x2e] +// CHECK: umlal v0.4s, v1.4h, v2.4h // encoding: [0x20,0x80,0x62,0x2e] +// CHECK: umlal v0.2d, v1.2s, v2.2s // encoding: [0x20,0x80,0xa2,0x2e] + + umlal2 v0.8h, v1.16b, v2.16b + umlal2 v0.4s, v1.8h, v2.8h + umlal2 v0.2d, v1.4s, v2.4s + +// CHECK: umlal2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0x80,0x22,0x6e] +// CHECK: umlal2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x80,0x62,0x6e] +// CHECK: umlal2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x80,0xa2,0x6e] + + smlsl v0.8h, v1.8b, v2.8b + smlsl v0.4s, v1.4h, v2.4h + smlsl v0.2d, v1.2s, v2.2s + +// CHECK: smlsl v0.8h, v1.8b, v2.8b // encoding: [0x20,0xa0,0x22,0x0e] +// CHECK: smlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xa0,0x62,0x0e] +// CHECK: smlsl v0.2d, v1.2s, v2.2s // encoding: [0x20,0xa0,0xa2,0x0e] + + smlsl2 v0.8h, v1.16b, v2.16b + smlsl2 v0.4s, v1.8h, v2.8h + smlsl2 v0.2d, v1.4s, v2.4s + +// CHECK: smlsl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0xa0,0x22,0x4e] +// CHECK: smlsl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xa0,0x62,0x4e] +// CHECK: smlsl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xa0,0xa2,0x4e] + + umlsl v0.8h, v1.8b, v2.8b + umlsl v0.4s, v1.4h, v2.4h + umlsl v0.2d, v1.2s, v2.2s + +// CHECK: umlsl v0.8h, v1.8b, v2.8b // encoding: [0x20,0xa0,0x22,0x2e] +// CHECK: umlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xa0,0x62,0x2e] +// CHECK: umlsl v0.2d, v1.2s, v2.2s // encoding: [0x20,0xa0,0xa2,0x2e] + + umlsl2 v0.8h, v1.16b, v2.16b + umlsl2 v0.4s, v1.8h, v2.8h + umlsl2 v0.2d, v1.4s, v2.4s + +// CHECK: umlsl2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0xa0,0x22,0x6e] +// CHECK: umlsl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xa0,0x62,0x6e] +// CHECK: umlsl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xa0,0xa2,0x6e] + + smull v0.8h, v1.8b, v2.8b + smull v0.4s, v1.4h, v2.4h + smull v0.2d, v1.2s, v2.2s + +// CHECK: smull v0.8h, v1.8b, v2.8b // encoding: [0x20,0xc0,0x22,0x0e] +// CHECK: smull v0.4s, v1.4h, v2.4h // encoding: [0x20,0xc0,0x62,0x0e] +// CHECK: smull v0.2d, v1.2s, v2.2s // encoding: [0x20,0xc0,0xa2,0x0e] + + smull2 v0.8h, v1.16b, v2.16b + smull2 v0.4s, v1.8h, v2.8h + smull2 v0.2d, v1.4s, v2.4s + +// CHECK: smull2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0xc0,0x22,0x4e] +// CHECK: smull2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xc0,0x62,0x4e] +// CHECK: smull2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xc0,0xa2,0x4e] + + umull v0.8h, v1.8b, v2.8b + umull v0.4s, v1.4h, v2.4h + umull v0.2d, v1.2s, v2.2s + +// CHECK: umull v0.8h, v1.8b, v2.8b // encoding: [0x20,0xc0,0x22,0x2e] +// CHECK: umull v0.4s, v1.4h, v2.4h // encoding: [0x20,0xc0,0x62,0x2e] +// CHECK: umull v0.2d, v1.2s, v2.2s // encoding: [0x20,0xc0,0xa2,0x2e] + + umull2 v0.8h, v1.16b, v2.16b + umull2 v0.4s, v1.8h, v2.8h + umull2 v0.2d, v1.4s, v2.4s + +// CHECK: umull2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0xc0,0x22,0x6e] +// CHECK: umull2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xc0,0x62,0x6e] +// CHECK: umull2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xc0,0xa2,0x6e] + +//------------------------------------------------------------------------------ +// Long - Variant 2 +//------------------------------------------------------------------------------ + + sqdmlal v0.4s, v1.4h, v2.4h + sqdmlal v0.2d, v1.2s, v2.2s + +// CHECK: sqdmlal v0.4s, v1.4h, v2.4h // encoding: [0x20,0x90,0x62,0x0e] +// CHECK: sqdmlal v0.2d, v1.2s, v2.2s // encoding: [0x20,0x90,0xa2,0x0e] + + sqdmlal2 v0.4s, v1.8h, v2.8h + sqdmlal2 v0.2d, v1.4s, v2.4s + +// CHECK: sqdmlal2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0x90,0x62,0x4e] +// CHECK: sqdmlal2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0x90,0xa2,0x4e] + + sqdmlsl v0.4s, v1.4h, v2.4h + sqdmlsl v0.2d, v1.2s, v2.2s + +// CHECK: sqdmlsl v0.4s, v1.4h, v2.4h // encoding: [0x20,0xb0,0x62,0x0e] +// CHECK: sqdmlsl v0.2d, v1.2s, v2.2s // encoding: [0x20,0xb0,0xa2,0x0e] + + sqdmlsl2 v0.4s, v1.8h, v2.8h + sqdmlsl2 v0.2d, v1.4s, v2.4s + +// CHECK: sqdmlsl2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xb0,0x62,0x4e] +// CHECK: sqdmlsl2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xb0,0xa2,0x4e] + + sqdmull v0.4s, v1.4h, v2.4h + sqdmull v0.2d, v1.2s, v2.2s + +// CHECK: sqdmull v0.4s, v1.4h, v2.4h // encoding: [0x20,0xd0,0x62,0x0e] +// CHECK: sqdmull v0.2d, v1.2s, v2.2s // encoding: [0x20,0xd0,0xa2,0x0e] + + sqdmull2 v0.4s, v1.8h, v2.8h + sqdmull2 v0.2d, v1.4s, v2.4s + +// CHECK: sqdmull2 v0.4s, v1.8h, v2.8h // encoding: [0x20,0xd0,0x62,0x4e] +// CHECK: sqdmull2 v0.2d, v1.4s, v2.4s // encoding: [0x20,0xd0,0xa2,0x4e] + +//------------------------------------------------------------------------------ +// Long - Variant 3 +//------------------------------------------------------------------------------ + + pmull v0.8h, v1.8b, v2.8b + pmull v0.1q, v1.1d, v2.1d + +// CHECK: pmull v0.8h, v1.8b, v2.8b // encoding: [0x20,0xe0,0x22,0x0e] +// CHECK: pmull v0.1q, v1.1d, v2.1d // encoding: [0x20,0xe0,0xe2,0x0e] + + pmull2 v0.8h, v1.16b, v2.16b + pmull2 v0.1q, v1.2d, v2.2d + +// CHECK: pmull2 v0.8h, v1.16b, v2.16b // encoding: [0x20,0xe0,0x22,0x4e] +// CHECK: pmull2 v0.1q, v1.2d, v2.2d // encoding: [0x20,0xe0,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Widen +//------------------------------------------------------------------------------ + + saddw v0.8h, v1.8h, v2.8b + saddw v0.4s, v1.4s, v2.4h + saddw v0.2d, v1.2d, v2.2s + +// CHECK: saddw v0.8h, v1.8h, v2.8b // encoding: [0x20,0x10,0x22,0x0e] +// CHECK: saddw v0.4s, v1.4s, v2.4h // encoding: [0x20,0x10,0x62,0x0e] +// CHECK: saddw v0.2d, v1.2d, v2.2s // encoding: [0x20,0x10,0xa2,0x0e] + + saddw2 v0.8h, v1.8h, v2.16b + saddw2 v0.4s, v1.4s, v2.8h + saddw2 v0.2d, v1.2d, v2.4s + +// CHECK: saddw2 v0.8h, v1.8h, v2.16b // encoding: [0x20,0x10,0x22,0x4e] +// CHECK: saddw2 v0.4s, v1.4s, v2.8h // encoding: [0x20,0x10,0x62,0x4e] +// CHECK: saddw2 v0.2d, v1.2d, v2.4s // encoding: [0x20,0x10,0xa2,0x4e] + + uaddw v0.8h, v1.8h, v2.8b + uaddw v0.4s, v1.4s, v2.4h + uaddw v0.2d, v1.2d, v2.2s + +// CHECK: uaddw v0.8h, v1.8h, v2.8b // encoding: [0x20,0x10,0x22,0x2e] +// CHECK: uaddw v0.4s, v1.4s, v2.4h // encoding: [0x20,0x10,0x62,0x2e] +// CHECK: uaddw v0.2d, v1.2d, v2.2s // encoding: [0x20,0x10,0xa2,0x2e] + + uaddw2 v0.8h, v1.8h, v2.16b + uaddw2 v0.4s, v1.4s, v2.8h + uaddw2 v0.2d, v1.2d, v2.4s + +// CHECK: uaddw2 v0.8h, v1.8h, v2.16b // encoding: [0x20,0x10,0x22,0x6e] +// CHECK: uaddw2 v0.4s, v1.4s, v2.8h // encoding: [0x20,0x10,0x62,0x6e] +// CHECK: uaddw2 v0.2d, v1.2d, v2.4s // encoding: [0x20,0x10,0xa2,0x6e] + + ssubw v0.8h, v1.8h, v2.8b + ssubw v0.4s, v1.4s, v2.4h + ssubw v0.2d, v1.2d, v2.2s + +// CHECK: ssubw v0.8h, v1.8h, v2.8b // encoding: [0x20,0x30,0x22,0x0e] +// CHECK: ssubw v0.4s, v1.4s, v2.4h // encoding: [0x20,0x30,0x62,0x0e] +// CHECK: ssubw v0.2d, v1.2d, v2.2s // encoding: [0x20,0x30,0xa2,0x0e] + + ssubw2 v0.8h, v1.8h, v2.16b + ssubw2 v0.4s, v1.4s, v2.8h + ssubw2 v0.2d, v1.2d, v2.4s + +// CHECK: ssubw2 v0.8h, v1.8h, v2.16b // encoding: [0x20,0x30,0x22,0x4e] +// CHECK: ssubw2 v0.4s, v1.4s, v2.8h // encoding: [0x20,0x30,0x62,0x4e] +// CHECK: ssubw2 v0.2d, v1.2d, v2.4s // encoding: [0x20,0x30,0xa2,0x4e] + + usubw v0.8h, v1.8h, v2.8b + usubw v0.4s, v1.4s, v2.4h + usubw v0.2d, v1.2d, v2.2s + +// CHECK: usubw v0.8h, v1.8h, v2.8b // encoding: [0x20,0x30,0x22,0x2e] +// CHECK: usubw v0.4s, v1.4s, v2.4h // encoding: [0x20,0x30,0x62,0x2e] +// CHECK: usubw v0.2d, v1.2d, v2.2s // encoding: [0x20,0x30,0xa2,0x2e] + + usubw2 v0.8h, v1.8h, v2.16b + usubw2 v0.4s, v1.4s, v2.8h + usubw2 v0.2d, v1.2d, v2.4s + +// CHECK: usubw2 v0.8h, v1.8h, v2.16b // encoding: [0x20,0x30,0x22,0x6e] +// CHECK: usubw2 v0.4s, v1.4s, v2.8h // encoding: [0x20,0x30,0x62,0x6e] +// CHECK: usubw2 v0.2d, v1.2d, v2.4s // encoding: [0x20,0x30,0xa2,0x6e] + +//------------------------------------------------------------------------------ +// Narrow +//------------------------------------------------------------------------------ + + addhn v0.8b, v1.8h, v2.8h + addhn v0.4h, v1.4s, v2.4s + addhn v0.2s, v1.2d, v2.2d + +// CHECK: addhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x0e] +// CHECK: addhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x0e] +// CHECK: addhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x0e] + + addhn2 v0.16b, v1.8h, v2.8h + addhn2 v0.8h, v1.4s, v2.4s + addhn2 v0.4s, v1.2d, v2.2d + +// CHECK: addhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x4e] +// CHECK: addhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x4e] +// CHECK: addhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x4e] + + raddhn v0.8b, v1.8h, v2.8h + raddhn v0.4h, v1.4s, v2.4s + raddhn v0.2s, v1.2d, v2.2d + +// CHECK: raddhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x2e] +// CHECK: raddhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x2e] +// CHECK: raddhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x2e] + + raddhn2 v0.16b, v1.8h, v2.8h + raddhn2 v0.8h, v1.4s, v2.4s + raddhn2 v0.4s, v1.2d, v2.2d + +// CHECK: raddhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x6e] +// CHECK: raddhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x6e] +// CHECK: raddhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x6e] + + rsubhn v0.8b, v1.8h, v2.8h + rsubhn v0.4h, v1.4s, v2.4s + rsubhn v0.2s, v1.2d, v2.2d + +// CHECK: rsubhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x2e] +// CHECK: rsubhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x2e] +// CHECK: rsubhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x2e] + + rsubhn2 v0.16b, v1.8h, v2.8h + rsubhn2 v0.8h, v1.4s, v2.4s + rsubhn2 v0.4s, v1.2d, v2.2d + +// CHECK: rsubhn2 v0.16b, v1.8h, v2.8h // encoding: [0x20,0x60,0x22,0x6e] +// CHECK: rsubhn2 v0.8h, v1.4s, v2.4s // encoding: [0x20,0x60,0x62,0x6e] +// CHECK: rsubhn2 v0.4s, v1.2d, v2.2d // encoding: [0x20,0x60,0xa2,0x6e] diff --git a/test/MC/AArch64/neon-aba-abd.s b/test/MC/AArch64/neon-aba-abd.s new file mode 100644 index 000000000000..178eb26f64c2 --- /dev/null +++ b/test/MC/AArch64/neon-aba-abd.s @@ -0,0 +1,78 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Absolute Difference and Accumulate (Signed, Unsigned) +//---------------------------------------------------------------------- + uaba v0.8b, v1.8b, v2.8b + uaba v0.16b, v1.16b, v2.16b + uaba v0.4h, v1.4h, v2.4h + uaba v0.8h, v1.8h, v2.8h + uaba v0.2s, v1.2s, v2.2s + uaba v0.4s, v1.4s, v2.4s + +// CHECK: uaba v0.8b, v1.8b, v2.8b // encoding: [0x20,0x7c,0x22,0x2e] +// CHECK: uaba v0.16b, v1.16b, v2.16b // encoding: [0x20,0x7c,0x22,0x6e] +// CHECK: uaba v0.4h, v1.4h, v2.4h // encoding: [0x20,0x7c,0x62,0x2e] +// CHECK: uaba v0.8h, v1.8h, v2.8h // encoding: [0x20,0x7c,0x62,0x6e] +// CHECK: uaba v0.2s, v1.2s, v2.2s // encoding: [0x20,0x7c,0xa2,0x2e] +// CHECK: uaba v0.4s, v1.4s, v2.4s // encoding: [0x20,0x7c,0xa2,0x6e] + + + saba v0.8b, v1.8b, v2.8b + saba v0.16b, v1.16b, v2.16b + saba v0.4h, v1.4h, v2.4h + saba v0.8h, v1.8h, v2.8h + saba v0.2s, v1.2s, v2.2s + saba v0.4s, v1.4s, v2.4s + +// CHECK: saba v0.8b, v1.8b, v2.8b // encoding: [0x20,0x7c,0x22,0x0e] +// CHECK: saba v0.16b, v1.16b, v2.16b // encoding: [0x20,0x7c,0x22,0x4e] +// CHECK: saba v0.4h, v1.4h, v2.4h // encoding: [0x20,0x7c,0x62,0x0e] +// CHECK: saba v0.8h, v1.8h, v2.8h // encoding: [0x20,0x7c,0x62,0x4e] +// CHECK: saba v0.2s, v1.2s, v2.2s // encoding: [0x20,0x7c,0xa2,0x0e] +// CHECK: saba v0.4s, v1.4s, v2.4s // encoding: [0x20,0x7c,0xa2,0x4e] + +//---------------------------------------------------------------------- +// Vector Absolute Difference (Signed, Unsigned) +//---------------------------------------------------------------------- + uabd v0.8b, v1.8b, v2.8b + uabd v0.16b, v1.16b, v2.16b + uabd v0.4h, v1.4h, v2.4h + uabd v0.8h, v1.8h, v2.8h + uabd v0.2s, v1.2s, v2.2s + uabd v0.4s, v1.4s, v2.4s + +// CHECK: uabd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x74,0x22,0x2e] +// CHECK: uabd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x74,0x22,0x6e] +// CHECK: uabd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x74,0x62,0x2e] +// CHECK: uabd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x74,0x62,0x6e] +// CHECK: uabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x74,0xa2,0x2e] +// CHECK: uabd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x74,0xa2,0x6e] + + sabd v0.8b, v1.8b, v2.8b + sabd v0.16b, v1.16b, v2.16b + sabd v0.4h, v1.4h, v2.4h + sabd v0.8h, v1.8h, v2.8h + sabd v0.2s, v1.2s, v2.2s + sabd v0.4s, v1.4s, v2.4s + +// CHECK: sabd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x74,0x22,0x0e] +// CHECK: sabd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x74,0x22,0x4e] +// CHECK: sabd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x74,0x62,0x0e] +// CHECK: sabd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x74,0x62,0x4e] +// CHECK: sabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x74,0xa2,0x0e] +// CHECK: sabd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x74,0xa2,0x4e] + +//---------------------------------------------------------------------- +// Vector Absolute Difference (Floating Point) +//---------------------------------------------------------------------- + fabd v0.2s, v1.2s, v2.2s + fabd v31.4s, v15.4s, v16.4s + fabd v7.2d, v8.2d, v25.2d + +// CHECK: fabd v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x2e] +// CHECK: fabd v31.4s, v15.4s, v16.4s // encoding: [0xff,0xd5,0xb0,0x6e] +// CHECK: fabd v7.2d, v8.2d, v25.2d // encoding: [0x07,0xd5,0xf9,0x6e] + diff --git a/test/MC/AArch64/neon-across.s b/test/MC/AArch64/neon-across.s new file mode 100644 index 000000000000..8b1c2d421ba6 --- /dev/null +++ b/test/MC/AArch64/neon-across.s @@ -0,0 +1,101 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions across vector registers +//------------------------------------------------------------------------------ + + saddlv h0, v1.8b + saddlv h0, v1.16b + saddlv s0, v1.4h + saddlv s0, v1.8h + saddlv d0, v1.4s + +// CHECK: saddlv h0, v1.8b // encoding: [0x20,0x38,0x30,0x0e] +// CHECK: saddlv h0, v1.16b // encoding: [0x20,0x38,0x30,0x4e] +// CHECK: saddlv s0, v1.4h // encoding: [0x20,0x38,0x70,0x0e] +// CHECK: saddlv s0, v1.8h // encoding: [0x20,0x38,0x70,0x4e] +// CHECK: saddlv d0, v1.4s // encoding: [0x20,0x38,0xb0,0x4e] + + uaddlv h0, v1.8b + uaddlv h0, v1.16b + uaddlv s0, v1.4h + uaddlv s0, v1.8h + uaddlv d0, v1.4s + +// CHECK: uaddlv h0, v1.8b // encoding: [0x20,0x38,0x30,0x2e] +// CHECK: uaddlv h0, v1.16b // encoding: [0x20,0x38,0x30,0x6e] +// CHECK: uaddlv s0, v1.4h // encoding: [0x20,0x38,0x70,0x2e] +// CHECK: uaddlv s0, v1.8h // encoding: [0x20,0x38,0x70,0x6e] +// CHECK: uaddlv d0, v1.4s // encoding: [0x20,0x38,0xb0,0x6e] + + smaxv b0, v1.8b + smaxv b0, v1.16b + smaxv h0, v1.4h + smaxv h0, v1.8h + smaxv s0, v1.4s + +// CHECK: smaxv b0, v1.8b // encoding: [0x20,0xa8,0x30,0x0e] +// CHECK: smaxv b0, v1.16b // encoding: [0x20,0xa8,0x30,0x4e] +// CHECK: smaxv h0, v1.4h // encoding: [0x20,0xa8,0x70,0x0e] +// CHECK: smaxv h0, v1.8h // encoding: [0x20,0xa8,0x70,0x4e] +// CHECK: smaxv s0, v1.4s // encoding: [0x20,0xa8,0xb0,0x4e] + + sminv b0, v1.8b + sminv b0, v1.16b + sminv h0, v1.4h + sminv h0, v1.8h + sminv s0, v1.4s + +// CHECK: sminv b0, v1.8b // encoding: [0x20,0xa8,0x31,0x0e] +// CHECK: sminv b0, v1.16b // encoding: [0x20,0xa8,0x31,0x4e] +// CHECK: sminv h0, v1.4h // encoding: [0x20,0xa8,0x71,0x0e] +// CHECK: sminv h0, v1.8h // encoding: [0x20,0xa8,0x71,0x4e] +// CHECK: sminv s0, v1.4s // encoding: [0x20,0xa8,0xb1,0x4e] + + umaxv b0, v1.8b + umaxv b0, v1.16b + umaxv h0, v1.4h + umaxv h0, v1.8h + umaxv s0, v1.4s + +// CHECK: umaxv b0, v1.8b // encoding: [0x20,0xa8,0x30,0x2e] +// CHECK: umaxv b0, v1.16b // encoding: [0x20,0xa8,0x30,0x6e] +// CHECK: umaxv h0, v1.4h // encoding: [0x20,0xa8,0x70,0x2e] +// CHECK: umaxv h0, v1.8h // encoding: [0x20,0xa8,0x70,0x6e] +// CHECK: umaxv s0, v1.4s // encoding: [0x20,0xa8,0xb0,0x6e] + + uminv b0, v1.8b + uminv b0, v1.16b + uminv h0, v1.4h + uminv h0, v1.8h + uminv s0, v1.4s + +// CHECK: uminv b0, v1.8b // encoding: [0x20,0xa8,0x31,0x2e] +// CHECK: uminv b0, v1.16b // encoding: [0x20,0xa8,0x31,0x6e] +// CHECK: uminv h0, v1.4h // encoding: [0x20,0xa8,0x71,0x2e] +// CHECK: uminv h0, v1.8h // encoding: [0x20,0xa8,0x71,0x6e] +// CHECK: uminv s0, v1.4s // encoding: [0x20,0xa8,0xb1,0x6e] + + addv b0, v1.8b + addv b0, v1.16b + addv h0, v1.4h + addv h0, v1.8h + addv s0, v1.4s + +// CHECK: addv b0, v1.8b // encoding: [0x20,0xb8,0x31,0x0e] +// CHECK: addv b0, v1.16b // encoding: [0x20,0xb8,0x31,0x4e] +// CHECK: addv h0, v1.4h // encoding: [0x20,0xb8,0x71,0x0e] +// CHECK: addv h0, v1.8h // encoding: [0x20,0xb8,0x71,0x4e] +// CHECK: addv s0, v1.4s // encoding: [0x20,0xb8,0xb1,0x4e] + + fmaxnmv s0, v1.4s + fminnmv s0, v1.4s + fmaxv s0, v1.4s + fminv s0, v1.4s + +// CHECK: fmaxnmv s0, v1.4s // encoding: [0x20,0xc8,0x30,0x6e] +// CHECK: fminnmv s0, v1.4s // encoding: [0x20,0xc8,0xb0,0x6e] +// CHECK: fmaxv s0, v1.4s // encoding: [0x20,0xf8,0x30,0x6e] +// CHECK: fminv s0, v1.4s // encoding: [0x20,0xf8,0xb0,0x6e] diff --git a/test/MC/AArch64/neon-add-pairwise.s b/test/MC/AArch64/neon-add-pairwise.s new file mode 100644 index 000000000000..df9938b07e52 --- /dev/null +++ b/test/MC/AArch64/neon-add-pairwise.s @@ -0,0 +1,34 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Add Pairwise (Integer) +//------------------------------------------------------------------------------ + addp v0.8b, v1.8b, v2.8b + addp v0.16b, v1.16b, v2.16b + addp v0.4h, v1.4h, v2.4h + addp v0.8h, v1.8h, v2.8h + addp v0.2s, v1.2s, v2.2s + addp v0.4s, v1.4s, v2.4s + addp v0.2d, v1.2d, v2.2d + +// CHECK: addp v0.8b, v1.8b, v2.8b // encoding: [0x20,0xbc,0x22,0x0e] +// CHECK: addp v0.16b, v1.16b, v2.16b // encoding: [0x20,0xbc,0x22,0x4e] +// CHECK: addp v0.4h, v1.4h, v2.4h // encoding: [0x20,0xbc,0x62,0x0e] +// CHECK: addp v0.8h, v1.8h, v2.8h // encoding: [0x20,0xbc,0x62,0x4e] +// CHECK: addp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xbc,0xa2,0x0e] +// CHECK: addp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xbc,0xa2,0x4e] +// CHECK: addp v0.2d, v1.2d, v2.2d // encoding: [0x20,0xbc,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Add Pairwise (Floating Point +//------------------------------------------------------------------------------ + faddp v0.2s, v1.2s, v2.2s + faddp v0.4s, v1.4s, v2.4s + faddp v0.2d, v1.2d, v2.2d + +// CHECK: faddp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0x22,0x2e] +// CHECK: faddp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0x22,0x6e] +// CHECK: faddp v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0x62,0x6e] diff --git a/test/MC/AArch64/neon-add-sub-instructions.s b/test/MC/AArch64/neon-add-sub-instructions.s new file mode 100644 index 000000000000..68f169b3dd90 --- /dev/null +++ b/test/MC/AArch64/neon-add-sub-instructions.s @@ -0,0 +1,68 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Add +//------------------------------------------------------------------------------ + add v0.8b, v1.8b, v2.8b + add v0.16b, v1.16b, v2.16b + add v0.4h, v1.4h, v2.4h + add v0.8h, v1.8h, v2.8h + add v0.2s, v1.2s, v2.2s + add v0.4s, v1.4s, v2.4s + add v0.2d, v1.2d, v2.2d + +// CHECK: add v0.8b, v1.8b, v2.8b // encoding: [0x20,0x84,0x22,0x0e] +// CHECK: add v0.16b, v1.16b, v2.16b // encoding: [0x20,0x84,0x22,0x4e] +// CHECK: add v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x62,0x0e] +// CHECK: add v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x62,0x4e] +// CHECK: add v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0xa2,0x0e] +// CHECK: add v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0xa2,0x4e] +// CHECK: add v0.2d, v1.2d, v2.2d // encoding: [0x20,0x84,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Sub +//------------------------------------------------------------------------------ + sub v0.8b, v1.8b, v2.8b + sub v0.16b, v1.16b, v2.16b + sub v0.4h, v1.4h, v2.4h + sub v0.8h, v1.8h, v2.8h + sub v0.2s, v1.2s, v2.2s + sub v0.4s, v1.4s, v2.4s + sub v0.2d, v1.2d, v2.2d + +// CHECK: sub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x84,0x22,0x2e] +// CHECK: sub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x84,0x22,0x6e] +// CHECK: sub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x84,0x62,0x2e] +// CHECK: sub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x84,0x62,0x6e] +// CHECK: sub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x84,0xa2,0x2e] +// CHECK: sub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x84,0xa2,0x6e] +// CHECK: sub v0.2d, v1.2d, v2.2d // encoding: [0x20,0x84,0xe2,0x6e] + +//------------------------------------------------------------------------------ +// Vector Floating-Point Add +//------------------------------------------------------------------------------ + fadd v0.2s, v1.2s, v2.2s + fadd v0.4s, v1.4s, v2.4s + fadd v0.2d, v1.2d, v2.2d + +// CHECK: fadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0x22,0x0e] +// CHECK: fadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0x22,0x4e] +// CHECK: fadd v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0x62,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Floating-Point Sub +//------------------------------------------------------------------------------ + fsub v0.2s, v1.2s, v2.2s + fsub v0.4s, v1.4s, v2.4s + fsub v0.2d, v1.2d, v2.2d + +// CHECK: fsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0xd4,0xa2,0x0e] +// CHECK: fsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0xd4,0xa2,0x4e] +// CHECK: fsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0xd4,0xe2,0x4e] + + + diff --git a/test/MC/AArch64/neon-bitwise-instructions.s b/test/MC/AArch64/neon-bitwise-instructions.s new file mode 100644 index 000000000000..79d0a9b70b54 --- /dev/null +++ b/test/MC/AArch64/neon-bitwise-instructions.s @@ -0,0 +1,60 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Vector And +//------------------------------------------------------------------------------ + and v0.8b, v1.8b, v2.8b + and v0.16b, v1.16b, v2.16b + +// CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e] +// CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Orr +//------------------------------------------------------------------------------ + orr v0.8b, v1.8b, v2.8b + orr v0.16b, v1.16b, v2.16b + +// CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e] +// CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Eor +//------------------------------------------------------------------------------ + eor v0.8b, v1.8b, v2.8b + eor v0.16b, v1.16b, v2.16b + +// CHECK: eor v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x2e] +// CHECK: eor v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x6e] + + +//---------------------------------------------------------------------- +// Vector Bitwise +//---------------------------------------------------------------------- + + bit v0.8b, v1.8b, v2.8b + bit v0.16b, v1.16b, v2.16b + bif v0.8b, v1.8b, v2.8b + bif v0.16b, v1.16b, v2.16b + bsl v0.8b, v1.8b, v2.8b + bsl v0.16b, v1.16b, v2.16b + orn v0.8b, v1.8b, v2.8b + orn v0.16b, v1.16b, v2.16b + bic v0.8b, v1.8b, v2.8b + bic v0.16b, v1.16b, v2.16b + +// CHECK: bit v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x2e] +// CHECK: bit v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x6e] +// CHECK: bif v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x2e] +// CHECK: bif v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x6e] +// CHECK: bsl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x2e] +// CHECK: bsl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x6e] +// CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e] +// CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e] +// CHECK: bic v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x0e] +// CHECK: bic v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x4e] + diff --git a/test/MC/AArch64/neon-compare-instructions.s b/test/MC/AArch64/neon-compare-instructions.s new file mode 100644 index 000000000000..e4bc20258357 --- /dev/null +++ b/test/MC/AArch64/neon-compare-instructions.s @@ -0,0 +1,405 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal (Integer) +//---------------------------------------------------------------------- + + cmeq v0.8b, v15.8b, v17.8b + cmeq v1.16b, v31.16b, v8.16b + cmeq v15.4h, v16.4h, v17.4h + cmeq v5.8h, v6.8h, v7.8h + cmeq v29.2s, v27.2s, v28.2s + cmeq v9.4s, v7.4s, v8.4s + cmeq v3.2d, v31.2d, v21.2d + +// CHECK: cmeq v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x8d,0x31,0x2e] +// CHECK: cmeq v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x8f,0x28,0x6e] +// CHECK: cmeq v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x8e,0x71,0x2e] +// CHECK: cmeq v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x8c,0x67,0x6e] +// CHECK: cmeq v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x8f,0xbc,0x2e] +// CHECK: cmeq v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x8c,0xa8,0x6e] +// CHECK: cmeq v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x8f,0xf5,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Higher or Same (Unsigned Integer) +// Vector Compare Mask Less or Same (Unsigned Integer) +// CMLS is alias for CMHS with operands reversed. +//---------------------------------------------------------------------- + + cmhs v0.8b, v15.8b, v17.8b + cmhs v1.16b, v31.16b, v8.16b + cmhs v15.4h, v16.4h, v17.4h + cmhs v5.8h, v6.8h, v7.8h + cmhs v29.2s, v27.2s, v28.2s + cmhs v9.4s, v7.4s, v8.4s + cmhs v3.2d, v31.2d, v21.2d + + cmls v0.8b, v17.8b, v15.8b + cmls v1.16b, v8.16b, v31.16b + cmls v15.4h, v17.4h, v16.4h + cmls v5.8h, v7.8h, v6.8h + cmls v29.2s, v28.2s, v27.2s + cmls v9.4s, v8.4s, v7.4s + cmls v3.2d, v21.2d, v31.2d + +// CHECK: cmhs v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x3d,0x31,0x2e] +// CHECK: cmhs v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x6e] +// CHECK: cmhs v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x3e,0x71,0x2e] +// CHECK: cmhs v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x3c,0x67,0x6e] +// CHECK: cmhs v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x3f,0xbc,0x2e] +// CHECK: cmhs v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x3c,0xa8,0x6e] +// CHECK: cmhs v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x3f,0xf5,0x6e] +// CHECK: cmhs v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x3d,0x31,0x2e] +// CHECK: cmhs v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x6e] +// CHECK: cmhs v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x3e,0x71,0x2e] +// CHECK: cmhs v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x3c,0x67,0x6e] +// CHECK: cmhs v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x3f,0xbc,0x2e] +// CHECK: cmhs v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x3c,0xa8,0x6e] +// CHECK: cmhs v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x3f,0xf5,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal (Integer) +// Vector Compare Mask Less Than or Equal (Integer) +// CMLE is alias for CMGE with operands reversed. +//---------------------------------------------------------------------- + + cmge v0.8b, v15.8b, v17.8b + cmge v1.16b, v31.16b, v8.16b + cmge v15.4h, v16.4h, v17.4h + cmge v5.8h, v6.8h, v7.8h + cmge v29.2s, v27.2s, v28.2s + cmge v9.4s, v7.4s, v8.4s + cmge v3.2d, v31.2d, v21.2d + + cmle v0.8b, v17.8b, v15.8b + cmle v1.16b, v8.16b, v31.16b + cmle v15.4h, v17.4h, v16.4h + cmle v5.8h, v7.8h, v6.8h + cmle v29.2s, v28.2s, v27.2s + cmle v9.4s, v8.4s, v7.4s + cmle v3.2d, v21.2d, v31.2d + +// CHECK: cmge v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x3d,0x31,0x0e] +// CHECK: cmge v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x4e] +// CHECK: cmge v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x3e,0x71,0x0e] +// CHECK: cmge v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x3c,0x67,0x4e] +// CHECK: cmge v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x3f,0xbc,0x0e] +// CHECK: cmge v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x3c,0xa8,0x4e] +// CHECK: cmge v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x3f,0xf5,0x4e] +// CHECK: cmge v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x3d,0x31,0x0e] +// CHECK: cmge v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x3f,0x28,0x4e] +// CHECK: cmge v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x3e,0x71,0x0e] +// CHECK: cmge v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x3c,0x67,0x4e] +// CHECK: cmge v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x3f,0xbc,0x0e] +// CHECK: cmge v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x3c,0xa8,0x4e] +// CHECK: cmge v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x3f,0xf5,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Higher (Unsigned Integer) +// Vector Compare Mask Lower (Unsigned Integer) +// CMLO is alias for CMHI with operands reversed. +//---------------------------------------------------------------------- + + cmhi v0.8b, v15.8b, v17.8b + cmhi v1.16b, v31.16b, v8.16b + cmhi v15.4h, v16.4h, v17.4h + cmhi v5.8h, v6.8h, v7.8h + cmhi v29.2s, v27.2s, v28.2s + cmhi v9.4s, v7.4s, v8.4s + cmhi v3.2d, v31.2d, v21.2d + + cmlo v0.8b, v17.8b, v15.8b + cmlo v1.16b, v8.16b, v31.16b + cmlo v15.4h, v17.4h, v16.4h + cmlo v5.8h, v7.8h, v6.8h + cmlo v29.2s, v28.2s, v27.2s + cmlo v9.4s, v8.4s, v7.4s + cmlo v3.2d, v21.2d, v31.2d + +// CHECK: cmhi v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x35,0x31,0x2e] +// CHECK: cmhi v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x37,0x28,0x6e] +// CHECK: cmhi v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x36,0x71,0x2e] +// CHECK: cmhi v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x34,0x67,0x6e] +// CHECK: cmhi v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x37,0xbc,0x2e] +// CHECK: cmhi v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x34,0xa8,0x6e] +// CHECK: cmhi v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x37,0xf5,0x6e] +// CHECK: cmhi v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x35,0x31,0x2e] +// CHECK: cmhi v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x37,0x28,0x6e] +// CHECK: cmhi v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x36,0x71,0x2e] +// CHECK: cmhi v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x34,0x67,0x6e] +// CHECK: cmhi v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x37,0xbc,0x2e] +// CHECK: cmhi v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x34,0xa8,0x6e] +// CHECK: cmhi v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x37,0xf5,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than (Integer) +// Vector Compare Mask Less Than (Integer) +// CMLT is alias for CMGT with operands reversed. +//---------------------------------------------------------------------- + + cmgt v0.8b, v15.8b, v17.8b + cmgt v1.16b, v31.16b, v8.16b + cmgt v15.4h, v16.4h, v17.4h + cmgt v5.8h, v6.8h, v7.8h + cmgt v29.2s, v27.2s, v28.2s + cmgt v9.4s, v7.4s, v8.4s + cmgt v3.2d, v31.2d, v21.2d + + cmlt v0.8b, v17.8b, v15.8b + cmlt v1.16b, v8.16b, v31.16b + cmlt v15.4h, v17.4h, v16.4h + cmlt v5.8h, v7.8h, v6.8h + cmlt v29.2s, v28.2s, v27.2s + cmlt v9.4s, v8.4s, v7.4s + cmlt v3.2d, v21.2d, v31.2d + +// CHECK: cmgt v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x35,0x31,0x0e] +// CHECK: cmgt v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x37,0x28,0x4e] +// CHECK: cmgt v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x36,0x71,0x0e] +// CHECK: cmgt v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x34,0x67,0x4e] +// CHECK: cmgt v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x37,0xbc,0x0e] +// CHECK: cmgt v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x34,0xa8,0x4e] +// CHECK: cmgt v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x37,0xf5,0x4e] +// CHECK: cmgt v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x35,0x31,0x0e] +// CHECK: cmgt v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x37,0x28,0x4e] +// CHECK: cmgt v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x36,0x71,0x0e] +// CHECK: cmgt v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x34,0x67,0x4e] +// CHECK: cmgt v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x37,0xbc,0x0e] +// CHECK: cmgt v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x34,0xa8,0x4e] +// CHECK: cmgt v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x37,0xf5,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Bitwise Test (Integer) +//---------------------------------------------------------------------- + + cmtst v0.8b, v15.8b, v17.8b + cmtst v1.16b, v31.16b, v8.16b + cmtst v15.4h, v16.4h, v17.4h + cmtst v5.8h, v6.8h, v7.8h + cmtst v29.2s, v27.2s, v28.2s + cmtst v9.4s, v7.4s, v8.4s + cmtst v3.2d, v31.2d, v21.2d + +// CHECK: cmtst v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x8d,0x31,0x0e] +// CHECK: cmtst v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x8f,0x28,0x4e] +// CHECK: cmtst v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x8e,0x71,0x0e] +// CHECK: cmtst v5.8h, v6.8h, v7.8h // encoding: [0xc5,0x8c,0x67,0x4e] +// CHECK: cmtst v29.2s, v27.2s, v28.2s // encoding: [0x7d,0x8f,0xbc,0x0e] +// CHECK: cmtst v9.4s, v7.4s, v8.4s // encoding: [0xe9,0x8c,0xa8,0x4e] +// CHECK: cmtst v3.2d, v31.2d, v21.2d // encoding: [0xe3,0x8f,0xf5,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal (Floating Point) +//---------------------------------------------------------------------- + + fcmeq v0.2s, v31.2s, v16.2s + fcmeq v4.4s, v7.4s, v15.4s + fcmeq v29.2d, v2.2d, v5.2d + +// CHECK: fcmeq v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xe7,0x30,0x0e] +// CHECK: fcmeq v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xe4,0x2f,0x4e] +// CHECK: fcmeq v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xe4,0x65,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Or Equal (Floating Point) +// Vector Compare Mask Less Than Or Equal (Floating Point) +// FCMLE is alias for FCMGE with operands reversed. +//---------------------------------------------------------------------- + + fcmge v31.4s, v29.4s, v28.4s + fcmge v3.2s, v8.2s, v12.2s + fcmge v17.2d, v15.2d, v13.2d + fcmle v31.4s, v28.4s, v29.4s + fcmle v3.2s, v12.2s, v8.2s + fcmle v17.2d, v13.2d, v15.2d + +// CHECK: fcmge v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xe7,0x3c,0x6e] +// CHECK: fcmge v3.2s, v8.2s, v12.2s // encoding: [0x03,0xe5,0x2c,0x2e] +// CHECK: fcmge v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xe5,0x6d,0x6e] +// CHECK: fcmge v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xe7,0x3c,0x6e] +// CHECK: fcmge v3.2s, v8.2s, v12.2s // encoding: [0x03,0xe5,0x2c,0x2e] +// CHECK: fcmge v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xe5,0x6d,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than (Floating Point) +// Vector Compare Mask Less Than (Floating Point) +// FCMLT is alias for FCMGT with operands reversed. +//---------------------------------------------------------------------- + + fcmgt v0.2s, v31.2s, v16.2s + fcmgt v4.4s, v7.4s, v15.4s + fcmgt v29.2d, v2.2d, v5.2d + fcmlt v0.2s, v16.2s, v31.2s + fcmlt v4.4s, v15.4s, v7.4s + fcmlt v29.2d, v5.2d, v2.2d + +// CHECK: fcmgt v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xe7,0xb0,0x2e] +// CHECK: fcmgt v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xe4,0xaf,0x6e] +// CHECK: fcmgt v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xe4,0xe5,0x6e] +// CHECK: fcmgt v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xe7,0xb0,0x2e] +// CHECK: fcmgt v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xe4,0xaf,0x6e] +// CHECK: fcmgt v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xe4,0xe5,0x6e] + + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal to Zero (Integer) +//---------------------------------------------------------------------- + + cmeq v0.8b, v15.8b, #0 + cmeq v1.16b, v31.16b, #0 + cmeq v15.4h, v16.4h, #0 + cmeq v5.8h, v6.8h, #0 + cmeq v29.2s, v27.2s, #0 + cmeq v9.4s, v7.4s, #0 + cmeq v3.2d, v31.2d, #0 + +// CHECK: cmeq v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x0e] +// CHECK: cmeq v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x4e] +// CHECK: cmeq v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x0e] +// CHECK: cmeq v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x4e] +// CHECK: cmeq v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x0e] +// CHECK: cmeq v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x4e] +// CHECK: cmeq v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) +//---------------------------------------------------------------------- + cmge v0.8b, v15.8b, #0 + cmge v1.16b, v31.16b, #0 + cmge v15.4h, v16.4h, #0 + cmge v5.8h, v6.8h, #0 + cmge v29.2s, v27.2s, #0 + cmge v17.4s, v20.4s, #0 + cmge v3.2d, v31.2d, #0 + +// CHECK: cmge v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x2e] +// CHECK: cmge v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x6e] +// CHECK: cmge v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x2e] +// CHECK: cmge v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x6e] +// CHECK: cmge v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x2e] +// CHECK: cmge v17.4s, v20.4s, #0x0 // encoding: [0x91,0x8a,0xa0,0x6e] +// CHECK: cmge v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Zero (Signed Integer) +//---------------------------------------------------------------------- + + cmgt v0.8b, v15.8b, #0 + cmgt v1.16b, v31.16b, #0 + cmgt v15.4h, v16.4h, #0 + cmgt v5.8h, v6.8h, #0 + cmgt v29.2s, v27.2s, #0 + cmgt v9.4s, v7.4s, #0 + cmgt v3.2d, v31.2d, #0 + +// CHECK: cmgt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x89,0x20,0x0e] +// CHECK: cmgt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x8b,0x20,0x4e] +// CHECK: cmgt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x8a,0x60,0x0e] +// CHECK: cmgt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x88,0x60,0x4e] +// CHECK: cmgt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x8b,0xa0,0x0e] +// CHECK: cmgt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x88,0xa0,0x4e] +// CHECK: cmgt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x8b,0xe0,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than or Equal To Zero (Signed Integer) +//---------------------------------------------------------------------- + cmle v0.8b, v15.8b, #0 + cmle v1.16b, v31.16b, #0 + cmle v15.4h, v16.4h, #0 + cmle v5.8h, v6.8h, #0 + cmle v29.2s, v27.2s, #0 + cmle v9.4s, v7.4s, #0 + cmle v3.2d, v31.2d, #0 + +// CHECK: cmle v0.8b, v15.8b, #0x0 // encoding: [0xe0,0x99,0x20,0x2e] +// CHECK: cmle v1.16b, v31.16b, #0x0 // encoding: [0xe1,0x9b,0x20,0x6e] +// CHECK: cmle v15.4h, v16.4h, #0x0 // encoding: [0x0f,0x9a,0x60,0x2e] +// CHECK: cmle v5.8h, v6.8h, #0x0 // encoding: [0xc5,0x98,0x60,0x6e] +// CHECK: cmle v29.2s, v27.2s, #0x0 // encoding: [0x7d,0x9b,0xa0,0x2e] +// CHECK: cmle v9.4s, v7.4s, #0x0 // encoding: [0xe9,0x98,0xa0,0x6e] +// CHECK: cmle v3.2d, v31.2d, #0x0 // encoding: [0xe3,0x9b,0xe0,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than Zero (Signed Integer) +//---------------------------------------------------------------------- + cmlt v0.8b, v15.8b, #0 + cmlt v1.16b, v31.16b, #0 + cmlt v15.4h, v16.4h, #0 + cmlt v5.8h, v6.8h, #0 + cmlt v29.2s, v27.2s, #0 + cmlt v9.4s, v7.4s, #0 + cmlt v3.2d, v31.2d, #0 + +// CHECK: cmlt v0.8b, v15.8b, #0x0 // encoding: [0xe0,0xa9,0x20,0x0e] +// CHECK: cmlt v1.16b, v31.16b, #0x0 // encoding: [0xe1,0xab,0x20,0x4e] +// CHECK: cmlt v15.4h, v16.4h, #0x0 // encoding: [0x0f,0xaa,0x60,0x0e] +// CHECK: cmlt v5.8h, v6.8h, #0x0 // encoding: [0xc5,0xa8,0x60,0x4e] +// CHECK: cmlt v29.2s, v27.2s, #0x0 // encoding: [0x7d,0xab,0xa0,0x0e] +// CHECK: cmlt v9.4s, v7.4s, #0x0 // encoding: [0xe9,0xa8,0xa0,0x4e] +// CHECK: cmlt v3.2d, v31.2d, #0x0 // encoding: [0xe3,0xab,0xe0,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal to Zero (Floating Point) +//---------------------------------------------------------------------- + fcmeq v0.2s, v31.2s, #0.0 + fcmeq v4.4s, v7.4s, #0.0 + fcmeq v29.2d, v2.2d, #0.0 + +// CHECK: fcmeq v0.2s, v31.2s, #0.0 // encoding: [0xe0,0xdb,0xa0,0x0e] +// CHECK: fcmeq v4.4s, v7.4s, #0.0 // encoding: [0xe4,0xd8,0xa0,0x4e] +// CHECK: fcmeq v29.2d, v2.2d, #0.0 // encoding: [0x5d,0xd8,0xe0,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal to Zero (Floating Point) +//---------------------------------------------------------------------- + fcmge v31.4s, v29.4s, #0.0 + fcmge v3.2s, v8.2s, #0.0 + fcmge v17.2d, v15.2d, #0.0 + +// CHECK: fcmge v31.4s, v29.4s, #0.0 // encoding: [0xbf,0xcb,0xa0,0x6e] +// CHECK: fcmge v3.2s, v8.2s, #0.0 // encoding: [0x03,0xc9,0xa0,0x2e] +// CHECK: fcmge v17.2d, v15.2d, #0.0 // encoding: [0xf1,0xc9,0xe0,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Zero (Floating Point) +//---------------------------------------------------------------------- + fcmgt v0.2s, v31.2s, #0.0 + fcmgt v4.4s, v7.4s, #0.0 + fcmgt v29.2d, v2.2d, #0.0 + +// CHECK: fcmgt v0.2s, v31.2s, #0.0 // encoding: [0xe0,0xcb,0xa0,0x0e] +// CHECK: fcmgt v4.4s, v7.4s, #0.0 // encoding: [0xe4,0xc8,0xa0,0x4e] +// CHECK: fcmgt v29.2d, v2.2d, #0.0 // encoding: [0x5d,0xc8,0xe0,0x4e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than or Equal To Zero (Floating Point) +//---------------------------------------------------------------------- + fcmle v1.4s, v8.4s, #0.0 + fcmle v3.2s, v20.2s, #0.0 + fcmle v7.2d, v13.2d, #0.0 + +// CHECK: fcmle v1.4s, v8.4s, #0.0 // encoding: [0x01,0xd9,0xa0,0x6e] +// CHECK: fcmle v3.2s, v20.2s, #0.0 // encoding: [0x83,0xda,0xa0,0x2e] +// CHECK: fcmle v7.2d, v13.2d, #0.0 // encoding: [0xa7,0xd9,0xe0,0x6e] + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than Zero (Floating Point) +//---------------------------------------------------------------------- + fcmlt v16.2s, v2.2s, #0.0 + fcmlt v15.4s, v4.4s, #0.0 + fcmlt v5.2d, v29.2d, #0.0 + +// CHECK: fcmlt v16.2s, v2.2s, #0.0 // encoding: [0x50,0xe8,0xa0,0x0e] +// CHECK: fcmlt v15.4s, v4.4s, #0.0 // encoding: [0x8f,0xe8,0xa0,0x4e] +// CHECK: fcmlt v5.2d, v29.2d, #0.0 // encoding: [0xa5,0xeb,0xe0,0x4e] + + + + + + + + + diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s new file mode 100644 index 000000000000..2952dd5aac29 --- /dev/null +++ b/test/MC/AArch64/neon-crypto.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions for crypto +//------------------------------------------------------------------------------ + + aese v0.16b, v1.16b + aesd v0.16b, v1.16b + aesmc v0.16b, v1.16b + aesimc v0.16b, v1.16b + +// CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled +// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e] +// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e] +// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e] +// CHECK: aesimc v0.16b, v1.16b // encoding: [0x20,0x78,0x28,0x4e] + + sha1h s0, s1 + sha1su1 v0.4s, v1.4s + sha256su0 v0.4s, v1.4s + +// CHECK: sha1h s0, s1 // encoding: [0x20,0x08,0x28,0x5e] +// CHECK: sha1su1 v0.4s, v1.4s // encoding: [0x20,0x18,0x28,0x5e] +// CHECK: sha256su0 v0.4s, v1.4s // encoding: [0x20,0x28,0x28,0x5e] + + sha1c q0, s1, v2.4s + sha1p q0, s1, v2.4s + sha1m q0, s1, v2.4s + sha1su0 v0.4s, v1.4s, v2.4s + sha256h q0, q1, v2.4s + sha256h2 q0, q1, v2.4s + sha256su1 v0.4s, v1.4s, v2.4s + +// CHECK: sha1c q0, s1, v2.4s // encoding: [0x20,0x00,0x02,0x5e] +// CHECK: sha1p q0, s1, v2.4s // encoding: [0x20,0x10,0x02,0x5e] +// CHECK: sha1m q0, s1, v2.4s // encoding: [0x20,0x20,0x02,0x5e] +// CHECK: sha1su0 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x30,0x02,0x5e] +// CHECK: sha256h q0, q1, v2.4s // encoding: [0x20,0x40,0x02,0x5e] +// CHECK: sha256h2 q0, q1, v2.4s // encoding: [0x20,0x50,0x02,0x5e] +// CHECK: sha256su1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x60,0x02,0x5e] + diff --git a/test/MC/AArch64/neon-diagnostics.s b/test/MC/AArch64/neon-diagnostics.s new file mode 100644 index 000000000000..be6c163741f9 --- /dev/null +++ b/test/MC/AArch64/neon-diagnostics.s @@ -0,0 +1,7318 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + +//------------------------------------------------------------------------------ +// Vector Integer Add/sub +//------------------------------------------------------------------------------ + + // Mismatched vector types + add v0.16b, v1.8b, v2.8b + sub v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: add v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sub v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector Floating-Point Add/sub +//------------------------------------------------------------------------------ + + // Mismatched and invalid vector types + fadd v0.2d, v1.2s, v2.2s + fsub v0.4s, v1.2s, v2.4s + fsub v0.8b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fadd v0.2d, v1.2s, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsub v0.4s, v1.2s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsub v0.8b, v1.8b, v2.8b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Integer Mul +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + mul v0.16b, v1.8b, v2.8b + mul v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mul v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mul v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Floating-Point Mul/Div +//---------------------------------------------------------------------- + // Mismatched vector types + fmul v0.16b, v1.8b, v2.8b + fdiv v0.2s, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmul v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fdiv v0.2s, v1.2d, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector And Orr Eor Bsl Bit Bif, Orn, Bic, +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + and v0.8b, v1.16b, v2.8b + orr v0.4h, v1.4h, v2.4h + eor v0.2s, v1.2s, v2.2s + bsl v0.8b, v1.16b, v2.8b + bsl v0.2s, v1.2s, v2.2s + bit v0.2d, v1.2d, v2.2d + bif v0.4h, v1.4h, v2.4h + orn v0.8b, v1.16b, v2.16b + bic v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: and v0.8b, v1.16b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: orr v0.4h, v1.4h, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: eor v0.2s, v1.2s, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bsl v0.8b, v1.16b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bsl v0.2s, v1.2s, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bit v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bif v0.4h, v1.4h, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: orn v0.8b, v1.16b, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bic v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Integer Multiply-accumulate and Multiply-subtract +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + mla v0.16b, v1.8b, v2.8b + mls v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mla v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mls v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Floating-Point Multiply-accumulate and Multiply-subtract +//---------------------------------------------------------------------- + // Mismatched vector types + fmla v0.2s, v1.2d, v2.2d + fmls v0.16b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmla v0.2s, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmls v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Move Immediate Shifted +// Vector Move Inverted Immediate Shifted +// Vector Bitwise Bit Clear (AND NOT) - immediate +// Vector Bitwise OR - immedidate +//---------------------------------------------------------------------- + // out of range immediate (0 to 0xff) + movi v0.2s, #-1 + mvni v1.4s, #256 + // out of range shift (0, 8, 16, 24 and 0, 8) + bic v15.4h, #1, lsl #7 + orr v31.2s, #1, lsl #25 + movi v5.4h, #10, lsl #16 + // invalid vector type (2s, 4s, 4h, 8h) + movi v5.8b, #1, lsl #8 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v0.2s, #-1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mvni v1.4s, #256 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: bic v15.4h, #1, lsl #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: orr v31.2s, #1, lsl #25 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v5.4h, #10, lsl #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v5.8b, #1, lsl #8 +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Move Immediate Masked +// Vector Move Inverted Immediate Masked +//---------------------------------------------------------------------- + // out of range immediate (0 to 0xff) + movi v0.2s, #-1, msl #8 + mvni v7.4s, #256, msl #16 + // out of range shift (8, 16) + movi v3.2s, #1, msl #0 + mvni v17.4s, #255, msl #32 + // invalid vector type (2s, 4s) + movi v5.4h, #31, msl #8 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v0.2s, #-1, msl #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mvni v7.4s, #256, msl #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v3.2s, #1, msl #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mvni v17.4s, #255, msl #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v5.4h, #31, msl #8 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Immediate - per byte +//---------------------------------------------------------------------- + // out of range immediate (0 to 0xff) + movi v0.8b, #-1 + movi v1.16b, #256 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v0.8b, #-1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: movi v1.16b, #256 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Estimate +//---------------------------------------------------------------------- + + frecpe s19, h14 + frecpe d13, s13 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe s19, h14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe d13, s13 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Exponent +//---------------------------------------------------------------------- + + frecpx s18, h10 + frecpx d16, s19 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpx s18, h10 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpx d16, s19 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Square Root Estimate +//---------------------------------------------------------------------- + + frsqrte s22, h13 + frsqrte d21, s12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte s22, h13 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte d21, s12 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Move Immediate - bytemask, per doubleword +//--------------------------------------------------------------------- + // invalid bytemask (0x00 or 0xff) + movi v0.2d, #0x10ff00ff00ff00ff + +// CHECK:ERROR: error: invalid operand for instruction +// CHECK:ERROR: movi v0.2d, #0x10ff00ff00ff00ff +// CHECK:ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Move Immediate - bytemask, one doubleword +//---------------------------------------------------------------------- + // invalid bytemask (0x00 or 0xff) + movi v0.2d, #0xffff00ff001f00ff + +// CHECK:ERROR: error: invalid operand for instruction +// CHECK:ERROR: movi v0.2d, #0xffff00ff001f00ff +// CHECK:ERROR: ^ +//---------------------------------------------------------------------- +// Vector Floating Point Move Immediate +//---------------------------------------------------------------------- + // invalid vector type (2s, 4s, 2d) + fmov v0.4h, #1.0 + +// CHECK:ERROR: error: invalid operand for instruction +// CHECK:ERROR: fmov v0.4h, #1.0 +// CHECK:ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Move - register +//---------------------------------------------------------------------- + // invalid vector type (8b, 16b) + mov v0.2s, v31.8b +// CHECK:ERROR: error: invalid operand for instruction +// CHECK:ERROR: mov v0.2s, v31.8b +// CHECK:ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Absolute Difference and Accumulate (Signed, Unsigned) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types (2d) + saba v0.16b, v1.8b, v2.8b + uaba v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saba v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaba v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Absolute Difference and Accumulate (Signed, Unsigned) +// Vector Absolute Difference (Signed, Unsigned) + + // Mismatched and invalid vector types (2d) + uaba v0.16b, v1.8b, v2.8b + saba v0.2d, v1.2d, v2.2d + uabd v0.4s, v1.2s, v2.2s + sabd v0.4h, v1.8h, v8.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaba v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saba v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabd v0.4s, v1.2s, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabd v0.4h, v1.8h, v8.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Absolute Difference (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fabd v0.2s, v1.4s, v2.2d + fabd v0.4h, v1.4h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabd v0.2s, v1.4s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabd v0.4h, v1.4h, v2.4h +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Multiply (Polynomial) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + pmul v0.8b, v1.8b, v2.16b + pmul v0.2s, v1.2s, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmul v0.8b, v1.8b, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmul v0.2s, v1.2s, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Add and Sub +//---------------------------------------------------------------------- + + // Mismatched registers + add d0, s1, d2 + sub s1, d1, d2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: add d0, s1, d2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sub s1, d1, d2 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Reciprocal Step (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + frecps v0.4s, v1.2d, v2.4s + frecps v0.8h, v1.8h, v2.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecps v0.4s, v1.2d, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecps v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Reciprocal Square Root Step (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + frsqrts v0.2d, v1.2d, v2.2s + frsqrts v0.4h, v1.4h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrts v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrts v0.4h, v1.4h, v2.4h +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Absolute Compare Mask Less Than Or Equal (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + facge v0.2d, v1.2s, v2.2d + facge v0.4h, v1.4h, v2.4h + facle v0.8h, v1.4h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facge v0.2d, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facge v0.4h, v1.4h, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facle v0.8h, v1.4h, v2.4h +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Absolute Compare Mask Less Than (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + facgt v0.2d, v1.2d, v2.4s + facgt v0.8h, v1.8h, v2.8h + faclt v0.8b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facgt v0.2d, v1.2d, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facgt v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: faclt v0.8b, v1.8b, v2.8b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal (Integer) +//---------------------------------------------------------------------- + + // Mismatched vector types + cmeq c0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmeq c0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Higher or Same (Unsigned Integer) +// Vector Compare Mask Less or Same (Unsigned Integer) +// CMLS is alias for CMHS with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched vector types + cmhs c0.4h, v1.8b, v2.8b + cmls c0.16b, v1.16b, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmhs c0.4h, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmls c0.16b, v1.16b, v2.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal (Integer) +// Vector Compare Mask Less Than or Equal (Integer) +// CMLE is alias for CMGE with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched vector types + cmge c0.8h, v1.8b, v2.8b + cmle c0.4h, v1.2s, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmge c0.8h, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmle c0.4h, v1.2s, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Higher (Unsigned Integer) +// Vector Compare Mask Lower (Unsigned Integer) +// CMLO is alias for CMHI with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched vector types + cmhi c0.4s, v1.4s, v2.16b + cmlo c0.8b, v1.8b, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmhi c0.4s, v1.4s, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmlo c0.8b, v1.8b, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than (Integer) +// Vector Compare Mask Less Than (Integer) +// CMLT is alias for CMGT with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched vector types + cmgt c0.8b, v1.4s, v2.16b + cmlt c0.8h, v1.16b, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmgt c0.8b, v1.4s, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmlt c0.8h, v1.16b, v2.4s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Bitwise Test (Integer) +//---------------------------------------------------------------------- + + // Mismatched vector types + cmtst c0.16b, v1.16b, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmtst c0.16b, v1.16b, v2.4s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + fcmeq v0.2d, v1.2s, v2.2d + fcmeq v0.16b, v1.16b, v2.16b + fcmeq v0.8b, v1.4h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.2d, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.16b, v1.16b, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.8b, v1.4h, v2.4h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Or Equal (Floating Point) +// Vector Compare Mask Less Than Or Equal (Floating Point) +// FCMLE is alias for FCMGE with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + fcmge v31.4s, v29.2s, v28.4s + fcmge v3.8b, v8.2s, v12.2s + fcmle v17.8h, v15.2d, v13.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v31.4s, v29.2s, v28.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v3.8b, v8.2s, v12.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmle v17.8h, v15.2d, v13.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than (Floating Point) +// Vector Compare Mask Less Than (Floating Point) +// FCMLT is alias for FCMGT with operands reversed. +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + fcmgt v0.2d, v31.2s, v16.2s + fcmgt v4.4s, v7.4s, v15.4h + fcmlt v29.2d, v5.2d, v2.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt v0.2d, v31.2s, v16.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: fcmgt v4.4s, v7.4s, v15.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: fcmlt v29.2d, v5.2d, v2.16b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal to Zero (Integer) +//---------------------------------------------------------------------- + // Mismatched vector types and invalid imm + // Mismatched vector types + cmeq c0.2d, v1.2s, #0 + cmeq c0.2d, v1.2d, #1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmeq c0.2d, v1.2s, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmeq c0.2d, v1.2d, #1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal to Zero (Signed Integer) +//---------------------------------------------------------------------- + // Mismatched vector types and invalid imm + cmge c0.8h, v1.8b, #0 + cmge c0.4s, v1.4s, #-1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmge c0.8h, v1.8b, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmge c0.4s, v1.4s, #-1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Zero (Signed Integer) +//---------------------------------------------------------------------- + // Mismatched vector types and invalid imm + cmgt c0.8b, v1.4s, #0 + cmgt c0.8b, v1.8b, #-255 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmgt c0.8b, v1.4s, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmgt c0.8b, v1.8b, #-255 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than or Equal To Zero (Signed Integer) +//---------------------------------------------------------------------- + // Mismatched vector types and invalid imm + cmle c0.4h, v1.2s, #0 + cmle c0.16b, v1.16b, #16 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmle c0.4h, v1.2s, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmle c0.16b, v1.16b, #16 +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than Zero (Signed Integer) +//---------------------------------------------------------------------- + // Mismatched vector types and invalid imm + cmlt c0.8h, v1.16b, #0 + cmlt c0.8h, v1.8h, #-15 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmlt c0.8h, v1.16b, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmlt c0.8h, v1.8h, #-15 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Equal to Zero (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types, invalid imm + fcmeq v0.2d, v1.2s, #0.0 + fcmeq v0.16b, v1.16b, #0.0 + fcmeq v0.8b, v1.4h, #1.0 + fcmeq v0.8b, v1.4h, #1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.2d, v1.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.16b, v1.16b, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq v0.8b, v1.4h, #1.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: Expected floating-point immediate +// CHECK-ERROR: fcmeq v0.8b, v1.4h, #1 +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than or Equal to Zero (Floating Point) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types, invalid imm + fcmge v31.4s, v29.2s, #0.0 + fcmge v3.8b, v8.2s, #0.0 + fcmle v17.8h, v15.2d, #-1.0 + fcmle v17.8h, v15.2d, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v31.4s, v29.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmle v17.8h, v15.2d, #-1.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: Expected floating-point immediate +// CHECK-ERROR: fcmle v17.8h, v15.2d, #0 +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Compare Mask Greater Than Zero (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types, invalid imm + fcmgt v0.2d, v31.2s, #0.0 + fcmgt v4.4s, v7.4h, #0.0 + fcmlt v29.2d, v5.2d, #255.0 + fcmlt v29.2d, v5.2d, #255 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt v0.2d, v31.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: fcmlt v29.2d, v5.2d, #255.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: Expected floating-point immediate +// CHECK-ERROR: fcmlt v29.2d, v5.2d, #255 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than or Equal To Zero (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types, invalid imm + fcmge v31.4s, v29.2s, #0.0 + fcmge v3.8b, v8.2s, #0.0 + fcmle v17.2d, v15.2d, #15.0 + fcmle v17.2d, v15.2d, #15 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v31.4s, v29.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge v3.8b, v8.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: fcmle v17.2d, v15.2d, #15.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: Expected floating-point immediate +// CHECK-ERROR: fcmle v17.2d, v15.2d, #15 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Compare Mask Less Than Zero (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types, invalid imm + fcmgt v0.2d, v31.2s, #0.0 + fcmgt v4.4s, v7.4h, #0.0 + fcmlt v29.2d, v5.2d, #16.0 + fcmlt v29.2d, v5.2d, #2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt v0.2d, v31.2s, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt v4.4s, v7.4h, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected floating-point constant #0.0 or invalid register type +// CHECK-ERROR: fcmlt v29.2d, v5.2d, #16.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: Expected floating-point immediate +// CHECK-ERROR: fcmlt v29.2d, v5.2d, #2 +// CHECK-ERROR: ^ + +/----------------------------------------------------------------------- +// Vector Integer Halving Add (Signed) +// Vector Integer Halving Add (Unsigned) +// Vector Integer Halving Sub (Signed) +// Vector Integer Halving Sub (Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types (2d) + shadd v0.2d, v1.2d, v2.2d + uhadd v4.2s, v5.2s, v5.4h + shsub v11.4h, v12.8h, v13.4h + uhsub v31.16b, v29.8b, v28.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shadd v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uhadd v4.2s, v5.2s, v5.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shsub v11.4h, v12.8h, v13.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uhsub v31.16b, v29.8b, v28.8b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Integer Rouding Halving Add (Signed) +// Vector Integer Rouding Halving Add (Unsigned) +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types (2d) + srhadd v0.2s, v1.2s, v2.2d + urhadd v0.16b, v1.16b, v2.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srhadd v0.2s, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urhadd v0.16b, v1.16b, v2.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Integer Saturating Add (Signed) +// Vector Integer Saturating Add (Unsigned) +// Vector Integer Saturating Sub (Signed) +// Vector Integer Saturating Sub (Unsigned) +//---------------------------------------------------------------------- + + // Mismatched vector types + sqadd v0.2s, v1.2s, v2.2d + uqadd v31.8h, v1.4h, v2.4h + sqsub v10.8h, v1.16b, v2.16b + uqsub v31.8b, v1.8b, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqadd v0.2s, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqadd v31.8h, v1.4h, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqsub v10.8h, v1.16b, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqsub v31.8b, v1.8b, v2.4s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Add (Signed) +// Scalar Integer Saturating Add (Unsigned) +// Scalar Integer Saturating Sub (Signed) +// Scalar Integer Saturating Sub (Unsigned) +//---------------------------------------------------------------------- + + // Mismatched registers + sqadd d0, s31, d2 + uqadd s0, s1, d2 + sqsub b0, b2, s18 + uqsub h1, h2, d2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqadd d0, s31, d2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqadd s0, s1, d2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqsub b0, b2, s18 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqsub h1, h2, d2 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Doubling Multiply Half High (Signed) +//---------------------------------------------------------------------- + + sqdmulh h10, s11, h12 + sqdmulh s20, h21, s2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh h10, s11, h12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh s20, h21, s2 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------ +// Scalar Integer Saturating Rounding Doubling Multiply Half High (Signed) +//------------------------------------------------------------------------ + + sqrdmulh h10, s11, h12 + sqrdmulh s20, h21, s2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh h10, s11, h12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh s20, h21, s2 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Shift Left (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + // Mismatched vector types + sshl v0.4s, v15.2s, v16.2s + ushl v1.16b, v25.16b, v6.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshl v0.4s, v15.2s, v16.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushl v1.16b, v25.16b, v6.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Saturating Shift Left (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + // Mismatched vector types + sqshl v0.2s, v15.4s, v16.2d + uqshl v1.8b, v25.4h, v6.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.2s, v15.4s, v16.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v1.8b, v25.4h, v6.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Rouding Shift Left (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + // Mismatched vector types + srshl v0.8h, v15.8h, v16.16b + urshl v1.2d, v25.2d, v6.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshl v0.8h, v15.8h, v16.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshl v1.2d, v25.2d, v6.4s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Saturating Rouding Shift Left (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + // Mismatched vector types + sqrshl v0.2s, v15.8h, v16.16b + uqrshl v1.4h, v25.4h, v6.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshl v0.2s, v15.8h, v16.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshl v1.4h, v25.4h, v6.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Shift Left (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + sshl d0, d1, s2 + ushl b2, b0, b1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshl d0, d1, s2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushl b2, b0, b1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Shift Left (Signed, Unsigned) +//---------------------------------------------------------------------- + + // Mismatched vector types + sqshl b0, s1, b0 + uqshl h0, b1, h0 + sqshl s0, h1, s0 + uqshl d0, b1, d0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl b0, s1, b0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl h0, b1, h0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl s0, h1, s0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl d0, b1, d0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Integer Rouding Shift Left (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + srshl h0, h1, h2 + urshl s0, s1, s2 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshl h0, h1, h2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshl s0, s1, s2 +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Rounding Shift Left (Signed, Unsigned) +//---------------------------------------------------------------------- + + // Mismatched vector types + sqrshl b0, b1, s0 + uqrshl h0, h1, b0 + sqrshl s0, s1, h0 + uqrshl d0, d1, b0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshl b0, b1, s0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshl h0, h1, b0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshl s0, s1, h0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshl d0, d1, b0 +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Maximum (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + smax v0.2d, v1.2d, v2.2d + umax v0.4h, v1.4h, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smax v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umax v0.4h, v1.4h, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Minimum (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + smin v0.2d, v1.2d, v2.2d + umin v0.2s, v1.2s, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smin v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umin v0.2s, v1.2s, v2.8b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Maximum (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmax v0.2s, v1.2s, v2.4s + fmax v0.8b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmax v0.2s, v1.2s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmax v0.8b, v1.8b, v2.8b +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Minimum (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmin v0.4s, v1.4s, v2.2d + fmin v0.8h, v1.8h, v2.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmin v0.4s, v1.4s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmin v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector maxNum (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmaxnm v0.2s, v1.2s, v2.2d + fmaxnm v0.4h, v1.8h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnm v0.2s, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnm v0.4h, v1.8h, v2.4h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector minNum (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fminnm v0.4s, v1.2s, v2.4s + fminnm v0.16b, v0.16b, v0.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnm v0.4s, v1.2s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnm v0.16b, v0.16b, v0.16b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Maximum Pairwise (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + smaxp v0.2d, v1.2d, v2.2d + umaxp v0.4h, v1.4h, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smaxp v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umaxp v0.4h, v1.4h, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Minimum Pairwise (Signed, Unsigned) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + sminp v0.2d, v1.2d, v2.2d + uminp v0.2s, v1.2s, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sminp v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uminp v0.2s, v1.2s, v2.8b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Maximum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmaxp v0.2s, v1.2s, v2.4s + fmaxp v0.8b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxp v0.2s, v1.2s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxp v0.8b, v1.8b, v2.8b +// CHECK-ERROR: ^ +//---------------------------------------------------------------------- +// Vector Minimum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fminp v0.4s, v1.4s, v2.2d + fminp v0.8h, v1.8h, v2.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminp v0.4s, v1.4s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminp v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector maxNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmaxnmp v0.2s, v1.2s, v2.2d + fmaxnmp v0.4h, v1.8h, v2.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmp v0.2s, v1.2s, v2.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmp v0.4h, v1.8h, v2.4h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector minNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fminnmp v0.4s, v1.2s, v2.4s + fminnmp v0.16b, v0.16b, v0.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmp v0.4s, v1.2s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmp v0.16b, v0.16b, v0.16b +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Add Pairwise (Integer) +//---------------------------------------------------------------------- + + // Mismatched vector types + addp v0.16b, v1.8b, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addp v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Add Pairwise (Floating Point) +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + faddp v0.16b, v1.8b, v2.8b + faddp v0.2d, v1.2d, v2.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: faddp v0.16b, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: faddp v0.2d, v1.2d, v2.8h +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Vector Saturating Doubling Multiply High +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + sqdmulh v2.4h, v25.8h, v3.4h + sqdmulh v12.2d, v5.2d, v13.2d + sqdmulh v3.8b, v1.8b, v30.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v2.4h, v25.8h, v3.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v12.2d, v5.2d, v13.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v3.8b, v1.8b, v30.8b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Saturating Rouding Doubling Multiply High +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + sqrdmulh v2.2s, v25.4s, v3.4s + sqrdmulh v12.16b, v5.16b, v13.16b + sqrdmulh v3.4h, v1.4h, v30.2d + + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v2.2s, v25.4s, v3.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v12.16b, v5.16b, v13.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v3.4h, v1.4h, v30.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Multiply Extended +//---------------------------------------------------------------------- + // Mismatched and invalid vector types + fmulx v21.2s, v5.2s, v13.2d + fmulx v1.4h, v25.4h, v3.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx v21.2s, v5.2s, v13.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx v1.4h, v25.4h, v3.4h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector Shift Left by Immediate +//------------------------------------------------------------------------------ + // Mismatched vector types and out of range + shl v0.4s, v15,2s, #3 + shl v0.2d, v17.4s, #3 + shl v0.8b, v31.8b, #-1 + shl v0.8b, v31.8b, #8 + shl v0.4s, v21.4s, #32 + shl v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: expected comma before next operand +// CHECK-ERROR: shl v0.4s, v15,2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shl v0.2d, v17.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: shl v0.8b, v31.8b, #-1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: shl v0.8b, v31.8b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: shl v0.4s, v21.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: shl v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector Shift Left Long by Immediate +//---------------------------------------------------------------------- + // Mismatched vector types + sshll v0.4s, v15.2s, #3 + ushll v1.16b, v25.16b, #6 + sshll2 v0.2d, v3.8s, #15 + ushll2 v1.4s, v25.4s, #7 + + // Out of range + sshll v0.8h, v1.8b, #-1 + sshll v0.8h, v1.8b, #9 + ushll v0.4s, v1.4h, #17 + ushll v0.2d, v1.2s, #33 + sshll2 v0.8h, v1.16b, #9 + sshll2 v0.4s, v1.8h, #17 + ushll2 v0.2d, v1.4s, #33 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshll v0.4s, v15.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushll v1.16b, v25.16b, #6 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshll2 v0.2d, v3.8s, #15 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushll2 v1.4s, v25.4s, #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sshll v0.8h, v1.8b, #-1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sshll v0.8h, v1.8b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: ushll v0.4s, v1.4h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: ushll v0.2d, v1.2s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sshll2 v0.8h, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sshll2 v0.4s, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: ushll2 v0.2d, v1.4s, #33 +// CHECK-ERROR: ^ + + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + sshr v0.8b, v1.8h, #3 + sshr v0.4h, v1.4s, #3 + sshr v0.2s, v1.2d, #3 + sshr v0.16b, v1.16b, #9 + sshr v0.8h, v1.8h, #17 + sshr v0.4s, v1.4s, #33 + sshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + ushr v0.8b, v1.8h, #3 + ushr v0.4h, v1.4s, #3 + ushr v0.2s, v1.2d, #3 + ushr v0.16b, v1.16b, #9 + ushr v0.8h, v1.8h, #17 + ushr v0.4s, v1.4s, #33 + ushr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ushr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ushr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ushr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ushr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ushr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ssra v0.8b, v1.8h, #3 + ssra v0.4h, v1.4s, #3 + ssra v0.2s, v1.2d, #3 + ssra v0.16b, v1.16b, #9 + ssra v0.8h, v1.8h, #17 + ssra v0.4s, v1.4s, #33 + ssra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ssra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ssra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ssra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ssra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + usra v0.8b, v1.8h, #3 + usra v0.4h, v1.4s, #3 + usra v0.2s, v1.2d, #3 + usra v0.16b, v1.16b, #9 + usra v0.8h, v1.8h, #17 + usra v0.4s, v1.4s, #33 + usra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: usra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: usra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: usra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: usra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right by immediate +//------------------------------------------------------------------------------ + srshr v0.8b, v1.8h, #3 + srshr v0.4h, v1.4s, #3 + srshr v0.2s, v1.2d, #3 + srshr v0.16b, v1.16b, #9 + srshr v0.8h, v1.8h, #17 + srshr v0.4s, v1.4s, #33 + srshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: srshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: srshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: srshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vecotr rounding shift right by immediate +//------------------------------------------------------------------------------ + urshr v0.8b, v1.8h, #3 + urshr v0.4h, v1.4s, #3 + urshr v0.2s, v1.2d, #3 + urshr v0.16b, v1.16b, #9 + urshr v0.8h, v1.8h, #17 + urshr v0.4s, v1.4s, #33 + urshr v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urshr v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: urshr v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: urshr v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: urshr v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: urshr v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + srsra v0.8b, v1.8h, #3 + srsra v0.4h, v1.4s, #3 + srsra v0.2s, v1.2d, #3 + srsra v0.16b, v1.16b, #9 + srsra v0.8h, v1.8h, #17 + srsra v0.4s, v1.4s, #33 + srsra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: srsra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: srsra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: srsra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: srsra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srsra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ursra v0.8b, v1.8h, #3 + ursra v0.4h, v1.4s, #3 + ursra v0.2s, v1.2d, #3 + ursra v0.16b, v1.16b, #9 + ursra v0.8h, v1.8h, #17 + ursra v0.4s, v1.4s, #33 + ursra v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursra v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: ursra v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: ursra v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ursra v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ursra v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right and insert by immediate +//------------------------------------------------------------------------------ + sri v0.8b, v1.8h, #3 + sri v0.4h, v1.4s, #3 + sri v0.2s, v1.2d, #3 + sri v0.16b, v1.16b, #9 + sri v0.8h, v1.8h, #17 + sri v0.4s, v1.4s, #33 + sri v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sri v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sri v0.16b, v1.16b, #9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sri v0.8h, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sri v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sri v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift left and insert by immediate +//------------------------------------------------------------------------------ + sli v0.8b, v1.8h, #3 + sli v0.4h, v1.4s, #3 + sli v0.2s, v1.2d, #3 + sli v0.16b, v1.16b, #8 + sli v0.8h, v1.8h, #16 + sli v0.4s, v1.4s, #32 + sli v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sli v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sli v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sli v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sli v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sli v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left unsigned by immediate +//------------------------------------------------------------------------------ + sqshlu v0.8b, v1.8h, #3 + sqshlu v0.4h, v1.4s, #3 + sqshlu v0.2s, v1.2d, #3 + sqshlu v0.16b, v1.16b, #8 + sqshlu v0.8h, v1.8h, #16 + sqshlu v0.4s, v1.4s, #32 + sqshlu v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshlu v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshlu v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshlu v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshlu v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshlu v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + sqshl v0.8b, v1.8h, #3 + sqshl v0.4h, v1.4s, #3 + sqshl v0.2s, v1.2d, #3 + sqshl v0.16b, v1.16b, #8 + sqshl v0.8h, v1.8h, #16 + sqshl v0.4s, v1.4s, #32 + sqshl v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshl v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshl v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshl v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshl v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshl v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + uqshl v0.8b, v1.8h, #3 + uqshl v0.4h, v1.4s, #3 + uqshl v0.2s, v1.2d, #3 + uqshl v0.16b, v1.16b, #8 + uqshl v0.8h, v1.8h, #16 + uqshl v0.4s, v1.4s, #32 + uqshl v0.2d, v1.2d, #64 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.8b, v1.8h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.4h, v1.4s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshl v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: uqshl v0.16b, v1.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: uqshl v0.8h, v1.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: uqshl v0.4s, v1.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: uqshl v0.2d, v1.2d, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector shift right narrow by immediate +//------------------------------------------------------------------------------ + shrn v0.8b, v1.8b, #3 + shrn v0.4h, v1.4h, #3 + shrn v0.2s, v1.2s, #3 + shrn2 v0.16b, v1.8h, #17 + shrn2 v0.8h, v1.4s, #33 + shrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: shrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: shrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: shrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqshrun v0.8b, v1.8b, #3 + sqshrun v0.4h, v1.4h, #3 + sqshrun v0.2s, v1.2s, #3 + sqshrun2 v0.16b, v1.8h, #17 + sqshrun2 v0.8h, v1.4s, #33 + sqshrun2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrun v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrun2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrun2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrun2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector rounding shift right narrow by immediate +//------------------------------------------------------------------------------ + rshrn v0.8b, v1.8b, #3 + rshrn v0.4h, v1.4h, #3 + rshrn v0.2s, v1.2s, #3 + rshrn2 v0.16b, v1.8h, #17 + rshrn2 v0.8h, v1.4s, #33 + rshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: rshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: rshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: rshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqrshrun v0.8b, v1.8b, #3 + sqrshrun v0.4h, v1.4h, #3 + sqrshrun v0.2s, v1.2s, #3 + sqrshrun2 v0.16b, v1.8h, #17 + sqrshrun2 v0.8h, v1.4s, #33 + sqrshrun2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrun v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrun2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrun2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrun2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + sqshrn v0.8b, v1.8b, #3 + sqshrn v0.4h, v1.4h, #3 + sqshrn v0.2s, v1.2s, #3 + sqshrn2 v0.16b, v1.8h, #17 + sqshrn2 v0.8h, v1.4s, #33 + sqshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + uqshrn v0.8b, v1.8b, #3 + uqshrn v0.4h, v1.4h, #3 + uqshrn v0.2s, v1.2s, #3 + uqshrn2 v0.16b, v1.8h, #17 + uqshrn2 v0.8h, v1.4s, #33 + uqshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + sqrshrn v0.8b, v1.8b, #3 + sqrshrn v0.4h, v1.4h, #3 + sqrshrn v0.2s, v1.2s, #3 + sqrshrn2 v0.16b, v1.8h, #17 + sqrshrn2 v0.8h, v1.4s, #33 + sqrshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + uqrshrn v0.8b, v1.8b, #3 + uqrshrn v0.4h, v1.4h, #3 + uqrshrn v0.2s, v1.2s, #3 + uqrshrn2 v0.16b, v1.8h, #17 + uqrshrn2 v0.8h, v1.4s, #33 + uqrshrn2 v0.4s, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.8b, v1.8b, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.4h, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqrshrn v0.2s, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqrshrn2 v0.16b, v1.8h, #17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqrshrn2 v0.8h, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqrshrn2 v0.4s, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Fixed-point convert to floating-point +//------------------------------------------------------------------------------ + scvtf v0.2s, v1.2d, #3 + scvtf v0.4s, v1.4h, #3 + scvtf v0.2d, v1.2s, #3 + ucvtf v0.2s, v1.2s, #33 + ucvtf v0.4s, v1.4s, #33 + ucvtf v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.4s, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.2d, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ucvtf v0.2s, v1.2s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ucvtf v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ucvtf v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert to fixed-point +//------------------------------------------------------------------------------ + fcvtzs v0.2s, v1.2d, #3 + fcvtzs v0.4s, v1.4h, #3 + fcvtzs v0.2d, v1.2s, #3 + fcvtzu v0.2s, v1.2s, #33 + fcvtzu v0.4s, v1.4s, #33 + fcvtzu v0.2d, v1.2d, #65 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.2s, v1.2d, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.4s, v1.4h, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.2d, v1.2s, #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu v0.2s, v1.2s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu v0.4s, v1.4s, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzu v0.2d, v1.2d, #65 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector operation on 3 operands with different types +//---------------------------------------------------------------------- + + // Mismatched and invalid vector types + saddl v0.8h, v1.8h, v2.8b + saddl v0.4s, v1.4s, v2.4h + saddl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + saddl2 v0.4s, v1.8s, v2.8h + saddl2 v0.8h, v1.16h, v2.16b + saddl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + uaddl v0.8h, v1.8h, v2.8b + uaddl v0.4s, v1.4s, v2.4h + uaddl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + uaddl2 v0.8h, v1.16h, v2.16b + uaddl2 v0.4s, v1.8s, v2.8h + uaddl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + ssubl v0.8h, v1.8h, v2.8b + ssubl v0.4s, v1.4s, v2.4h + ssubl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + ssubl2 v0.8h, v1.16h, v2.16b + ssubl2 v0.4s, v1.8s, v2.8h + ssubl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + usubl v0.8h, v1.8h, v2.8b + usubl v0.4s, v1.4s, v2.4h + usubl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + usubl2 v0.8h, v1.16h, v2.16b + usubl2 v0.4s, v1.8s, v2.8h + usubl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + sabal v0.8h, v1.8h, v2.8b + sabal v0.4s, v1.4s, v2.4h + sabal v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + sabal2 v0.8h, v1.16h, v2.16b + sabal2 v0.4s, v1.8s, v2.8h + sabal2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabal2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + uabal v0.8h, v1.8h, v2.8b + uabal v0.4s, v1.4s, v2.4h + uabal v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + uabal2 v0.8h, v1.16h, v2.16b + uabal2 v0.4s, v1.8s, v2.8h + uabal2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabal2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + sabdl v0.8h, v1.8h, v2.8b + sabdl v0.4s, v1.4s, v2.4h + sabdl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + sabdl2 v0.8h, v1.16h, v2.16b + sabdl2 v0.4s, v1.8s, v2.8h + sabdl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sabdl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + uabdl v0.8h, v1.8h, v2.8b + uabdl v0.4s, v1.4s, v2.4h + uabdl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + uabdl2 v0.8h, v1.16h, v2.16b + uabdl2 v0.4s, v1.8s, v2.8h + uabdl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uabdl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + smlal v0.8h, v1.8h, v2.8b + smlal v0.4s, v1.4s, v2.4h + smlal v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + smlal2 v0.8h, v1.16h, v2.16b + smlal2 v0.4s, v1.8s, v2.8h + smlal2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + umlal v0.8h, v1.8h, v2.8b + umlal v0.4s, v1.4s, v2.4h + umlal v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + umlal2 v0.8h, v1.16h, v2.16b + umlal2 v0.4s, v1.8s, v2.8h + umlal2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + smlsl v0.8h, v1.8h, v2.8b + smlsl v0.4s, v1.4s, v2.4h + smlsl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + smlsl2 v0.8h, v1.16h, v2.16b + smlsl2 v0.4s, v1.8s, v2.8h + smlsl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + umlsl v0.8h, v1.8h, v2.8b + umlsl v0.4s, v1.4s, v2.4h + umlsl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + umlsl2 v0.8h, v1.16h, v2.16b + umlsl2 v0.4s, v1.8s, v2.8h + umlsl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + smull v0.8h, v1.8h, v2.8b + smull v0.4s, v1.4s, v2.4h + smull v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + smull2 v0.8h, v1.16h, v2.16b + smull2 v0.4s, v1.8s, v2.8h + smull2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + umull v0.8h, v1.8h, v2.8b + umull v0.4s, v1.4s, v2.4h + umull v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + umull2 v0.8h, v1.16h, v2.16b + umull2 v0.4s, v1.8s, v2.8h + umull2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Long - Variant 2 +//------------------------------------------------------------------------------ + + sqdmlal v0.4s, v1.4s, v2.4h + sqdmlal v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + sqdmlal2 v0.4s, v1.8s, v2.8h + sqdmlal2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + // Mismatched vector types + sqdmlal v0.8h, v1.8b, v2.8b + sqdmlal2 v0.8h, v1.16b, v2.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.8h, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.8h, v1.16b, v2.16b +// CHECK-ERROR: ^ + + sqdmlsl v0.4s, v1.4s, v2.4h + sqdmlsl v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + sqdmlsl2 v0.4s, v1.8s, v2.8h + sqdmlsl2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + // Mismatched vector types + sqdmlsl v0.8h, v1.8b, v2.8b + sqdmlsl2 v0.8h, v1.16b, v2.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.8h, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.8h, v1.16b, v2.16b +// CHECK-ERROR: ^ + + + sqdmull v0.4s, v1.4s, v2.4h + sqdmull v0.2d, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.4s, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.2d, v1.2d, v2.2s +// CHECK-ERROR: ^ + + sqdmull2 v0.4s, v1.8s, v2.8h + sqdmull2 v0.2d, v1.4d, v2.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.4s, v1.8s, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.2d, v1.4d, v2.4s +// CHECK-ERROR: ^ + + // Mismatched vector types + sqdmull v0.8h, v1.8b, v2.8b + sqdmull2 v0.8h, v1.16b, v2.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.8h, v1.8b, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.8h, v1.16b, v2.16b +// CHECK-ERROR: ^ + + +//------------------------------------------------------------------------------ +// Long - Variant 3 +//------------------------------------------------------------------------------ + + pmull v0.8h, v1.8h, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull v0.8h, v1.8h, v2.8b +// CHECK-ERROR: ^ + + pmull v0.1q, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull v0.1q, v1.2d, v2.2d +// CHECK-ERROR: ^ + + // Mismatched vector types + pmull v0.4s, v1.4h, v2.4h + pmull v0.2d, v1.2s, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull v0.4s, v1.4h, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull v0.2d, v1.2s, v2.2s +// CHECK-ERROR: ^ + + + pmull2 v0.8h, v1.16h, v2.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull2 v0.8h, v1.16h, v2.16b +// CHECK-ERROR: ^ + + pmull2 v0.q, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull2 v0.q, v1.2d, v2.2d +// CHECK-ERROR: ^ + + // Mismatched vector types + pmull2 v0.4s, v1.8h v2.8h + pmull2 v0.2d, v1.4s, v2.4s + +// CHECK-ERROR: error: expected comma before next operand +// CHECK-ERROR: pmull2 v0.4s, v1.8h v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: pmull2 v0.2d, v1.4s, v2.4s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Widen +//------------------------------------------------------------------------------ + + saddw v0.8h, v1.8h, v2.8h + saddw v0.4s, v1.4s, v2.4s + saddw v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw v0.4s, v1.4s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + + saddw2 v0.8h, v1.8h, v2.16h + saddw2 v0.4s, v1.4s, v2.8s + saddw2 v0.2d, v1.2d, v2.4d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw2 v0.8h, v1.8h, v2.16h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw2 v0.4s, v1.4s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddw2 v0.2d, v1.2d, v2.4d +// CHECK-ERROR: ^ + + uaddw v0.8h, v1.8h, v2.8h + uaddw v0.4s, v1.4s, v2.4s + uaddw v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw v0.4s, v1.4s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + + uaddw2 v0.8h, v1.8h, v2.16h + uaddw2 v0.4s, v1.4s, v2.8s + uaddw2 v0.2d, v1.2d, v2.4d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw2 v0.8h, v1.8h, v2.16h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw2 v0.4s, v1.4s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddw2 v0.2d, v1.2d, v2.4d +// CHECK-ERROR: ^ + + ssubw v0.8h, v1.8h, v2.8h + ssubw v0.4s, v1.4s, v2.4s + ssubw v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw v0.4s, v1.4s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + + ssubw2 v0.8h, v1.8h, v2.16h + ssubw2 v0.4s, v1.4s, v2.8s + ssubw2 v0.2d, v1.2d, v2.4d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw2 v0.8h, v1.8h, v2.16h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw2 v0.4s, v1.4s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ssubw2 v0.2d, v1.2d, v2.4d +// CHECK-ERROR: ^ + + usubw v0.8h, v1.8h, v2.8h + usubw v0.4s, v1.4s, v2.4s + usubw v0.2d, v1.2d, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw v0.8h, v1.8h, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw v0.4s, v1.4s, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw v0.2d, v1.2d, v2.2d +// CHECK-ERROR: ^ + + usubw2 v0.8h, v1.8h, v2.16h + usubw2 v0.4s, v1.4s, v2.8s + usubw2 v0.2d, v1.2d, v2.4d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw2 v0.8h, v1.8h, v2.16h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw2 v0.4s, v1.4s, v2.8s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usubw2 v0.2d, v1.2d, v2.4d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Narrow +//------------------------------------------------------------------------------ + + addhn v0.8b, v1.8h, v2.8d + addhn v0.4h, v1.4s, v2.4h + addhn v0.2s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn v0.8b, v1.8h, v2.8d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn v0.4h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn v0.2s, v1.2d, v2.2s +// CHECK-ERROR: ^ + + addhn2 v0.16b, v1.8h, v2.8b + addhn2 v0.8h, v1.4s, v2.4h + addhn2 v0.4s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn2 v0.16b, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn2 v0.8h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addhn2 v0.4s, v1.2d, v2.2s +// CHECK-ERROR: ^ + + raddhn v0.8b, v1.8h, v2.8b + raddhn v0.4h, v1.4s, v2.4h + raddhn v0.2s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn v0.8b, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn v0.4h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn v0.2s, v1.2d, v2.2s +// CHECK-ERROR: ^ + + raddhn2 v0.16b, v1.8h, v2.8b + raddhn2 v0.8h, v1.4s, v2.4h + raddhn2 v0.4s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn2 v0.16b, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn2 v0.8h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: raddhn2 v0.4s, v1.2d, v2.2s +// CHECK-ERROR: ^ + + rsubhn v0.8b, v1.8h, v2.8b + rsubhn v0.4h, v1.4s, v2.4h + rsubhn v0.2s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn v0.8b, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn v0.4h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn v0.2s, v1.2d, v2.2s +// CHECK-ERROR: ^ + + rsubhn2 v0.16b, v1.8h, v2.8b + rsubhn2 v0.8h, v1.4s, v2.4h + rsubhn2 v0.4s, v1.2d, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn2 v0.16b, v1.8h, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn2 v0.8h, v1.4s, v2.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rsubhn2 v0.4s, v1.2d, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Reduce Add Pairwise (Integer) +//---------------------------------------------------------------------- + // invalid vector types + addp s0, d1.2d + addp d0, d1.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addp s0, d1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addp d0, d1.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Reduce Add Pairwise (Floating Point) +//---------------------------------------------------------------------- + // invalid vector types + faddp s0, d1.2d + faddp d0, d1.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: faddp s0, d1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: faddp d0, d1.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Reduce Maximum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmaxp s0, v1.2d + fmaxp d31, v2.2s + fmaxp h3, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxp s0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxp d31, v2.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxp h3, v2.2s +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Scalar Reduce Minimum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fminp s0, v1.4h + fminp d31, v2.8h + fminp b3, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminp s0, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminp d31, v2.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminp b3, v2.2s +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Scalar Reduce maxNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmaxnmp s0, v1.8b + fmaxnmp d31, v2.16b + fmaxnmp v1.2s, v2.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmp s0, v1.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmp d31, v2.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: fmaxnmp v1.2s, v2.2s +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Reduce minNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fminnmp s0, v1.2d + fminnmp d31, v2.4s + fminnmp v1.4s, v2.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmp s0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmp d31, v2.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmp v1.4s, v2.2d +// CHECK-ERROR: ^ + + mla v0.2d, v1.2d, v16.d[1] + mla v0.2s, v1.2s, v2.s[4] + mla v0.4s, v1.4s, v2.s[4] + mla v0.2h, v1.2h, v2.h[1] + mla v0.4h, v1.4h, v2.h[8] + mla v0.8h, v1.8h, v2.h[8] + mla v0.4h, v1.4h, v16.h[2] + mla v0.8h, v1.8h, v16.h[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mla v0.2d, v1.2d, v16.d[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mla v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mla v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mla v0.2h, v1.2h, v2.h[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mla v0.4h, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mla v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mla v0.4h, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mla v0.8h, v1.8h, v16.h[2] +// CHECK-ERROR: ^ + + mls v0.2d, v1.2d, v16.d[1] + mls v0.2s, v1.2s, v2.s[4] + mls v0.4s, v1.4s, v2.s[4] + mls v0.2h, v1.2h, v2.h[1] + mls v0.4h, v1.4h, v2.h[8] + mls v0.8h, v1.8h, v2.h[8] + mls v0.4h, v1.4h, v16.h[2] + mls v0.8h, v1.8h, v16.h[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mls v0.2d, v1.2d, v16.d[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mls v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mls v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mls v0.2h, v1.2h, v2.h[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mls v0.4h, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mls v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mls v0.4h, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mls v0.8h, v1.8h, v16.h[2] +// CHECK-ERROR: ^ + + fmla v0.4h, v1.4h, v2.h[2] + fmla v0.8h, v1.8h, v2.h[2] + fmla v0.2s, v1.2s, v2.s[4] + fmla v0.2s, v1.2s, v22.s[4] + fmla v3.4s, v8.4s, v2.s[4] + fmla v3.4s, v8.4s, v22.s[4] + fmla v0.2d, v1.2d, v2.d[2] + fmla v0.2d, v1.2d, v22.d[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmla v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmla v0.8h, v1.8h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v3.4s, v8.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v3.4s, v8.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v0.2d, v1.2d, v2.d[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla v0.2d, v1.2d, v22.d[2] +// CHECK-ERROR: ^ + + fmls v0.4h, v1.4h, v2.h[2] + fmls v0.8h, v1.8h, v2.h[2] + fmls v0.2s, v1.2s, v2.s[4] + fmls v0.2s, v1.2s, v22.s[4] + fmls v3.4s, v8.4s, v2.s[4] + fmls v3.4s, v8.4s, v22.s[4] + fmls v0.2d, v1.2d, v2.d[2] + fmls v0.2d, v1.2d, v22.d[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmls v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmls v0.8h, v1.8h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v3.4s, v8.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v3.4s, v8.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v0.2d, v1.2d, v2.d[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmls v0.2d, v1.2d, v22.d[2] +// CHECK-ERROR: ^ + + smlal v0.4h, v1.4h, v2.h[2] + smlal v0.4s, v1.4h, v2.h[8] + smlal v0.4s, v1.4h, v16.h[2] + smlal v0.2s, v1.2s, v2.s[4] + smlal v0.2d, v1.2s, v2.s[4] + smlal v0.2d, v1.2s, v22.s[4] + smlal2 v0.4h, v1.8h, v1.h[2] + smlal2 v0.4s, v1.8h, v1.h[8] + smlal2 v0.4s, v1.8h, v16.h[2] + smlal2 v0.2s, v1.4s, v1.s[2] + smlal2 v0.2d, v1.4s, v1.s[4] + smlal2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlal2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlal2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + smlsl v0.4h, v1.4h, v2.h[2] + smlsl v0.4s, v1.4h, v2.h[8] + smlsl v0.4s, v1.4h, v16.h[2] + smlsl v0.2s, v1.2s, v2.s[4] + smlsl v0.2d, v1.2s, v2.s[4] + smlsl v0.2d, v1.2s, v22.s[4] + smlsl2 v0.4h, v1.8h, v1.h[2] + smlsl2 v0.4s, v1.8h, v1.h[8] + smlsl2 v0.4s, v1.8h, v16.h[2] + smlsl2 v0.2s, v1.4s, v1.s[2] + smlsl2 v0.2d, v1.4s, v1.s[4] + smlsl2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smlsl2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smlsl2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + umlal v0.4h, v1.4h, v2.h[2] + umlal v0.4s, v1.4h, v2.h[8] + umlal v0.4s, v1.4h, v16.h[2] + umlal v0.2s, v1.2s, v2.s[4] + umlal v0.2d, v1.2s, v2.s[4] + umlal v0.2d, v1.2s, v22.s[4] + umlal2 v0.4h, v1.8h, v1.h[2] + umlal2 v0.4s, v1.8h, v1.h[8] + umlal2 v0.4s, v1.8h, v16.h[2] + umlal2 v0.2s, v1.4s, v1.s[2] + umlal2 v0.2d, v1.4s, v1.s[4] + umlal2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlal2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlal2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + umlsl v0.4h, v1.4h, v2.h[2] + umlsl v0.4s, v1.4h, v2.h[8] + umlsl v0.4s, v1.4h, v16.h[2] + umlsl v0.2s, v1.2s, v2.s[4] + umlsl v0.2d, v1.2s, v2.s[4] + umlsl v0.2d, v1.2s, v22.s[4] + umlsl2 v0.4h, v1.8h, v1.h[2] + umlsl2 v0.4s, v1.8h, v1.h[8] + umlsl2 v0.4s, v1.8h, v16.h[2] + umlsl2 v0.2s, v1.4s, v1.s[2] + umlsl2 v0.2d, v1.4s, v1.s[4] + umlsl2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umlsl2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umlsl2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + sqdmlal v0.4h, v1.4h, v2.h[2] + sqdmlal v0.4s, v1.4h, v2.h[8] + sqdmlal v0.4s, v1.4h, v16.h[2] + sqdmlal v0.2s, v1.2s, v2.s[4] + sqdmlal v0.2d, v1.2s, v2.s[4] + sqdmlal v0.2d, v1.2s, v22.s[4] + sqdmlal2 v0.4h, v1.8h, v1.h[2] + sqdmlal2 v0.4s, v1.8h, v1.h[8] + sqdmlal2 v0.4s, v1.8h, v16.h[2] + sqdmlal2 v0.2s, v1.4s, v1.s[2] + sqdmlal2 v0.2d, v1.4s, v1.s[4] + sqdmlal2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + sqdmlsl v0.4h, v1.4h, v2.h[2] + sqdmlsl v0.4s, v1.4h, v2.h[8] + sqdmlsl v0.4s, v1.4h, v16.h[2] + sqdmlsl v0.2s, v1.2s, v2.s[4] + sqdmlsl v0.2d, v1.2s, v2.s[4] + sqdmlsl v0.2d, v1.2s, v22.s[4] + sqdmlsl2 v0.4h, v1.8h, v1.h[2] + sqdmlsl2 v0.4s, v1.8h, v1.h[8] + sqdmlsl2 v0.4s, v1.8h, v16.h[2] + sqdmlsl2 v0.2s, v1.4s, v1.s[2] + sqdmlsl2 v0.2d, v1.4s, v1.s[4] + sqdmlsl2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl v0.4s, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.4h, v1.8h, v1.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v1.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.4s, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl2 v0.2s, v1.4s, v1.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v1.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + mul v0.4h, v1.4h, v2.h[8] + mul v0.4h, v1.4h, v16.h[8] + mul v0.8h, v1.8h, v2.h[8] + mul v0.8h, v1.8h, v16.h[8] + mul v0.2s, v1.2s, v2.s[4] + mul v0.2s, v1.2s, v22.s[4] + mul v0.4s, v1.4s, v2.s[4] + mul v0.4s, v1.4s, v22.s[4] + mul v0.2d, v1.2d, v2.d[1] + +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.4h, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.4h, v1.4h, v16.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.8h, v1.8h, v16.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: mul v0.4s, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + fmul v0.4h, v1.4h, v2.h[4] + fmul v0.2s, v1.2s, v2.s[4] + fmul v0.2s, v1.2s, v22.s[4] + fmul v0.4s, v1.4s, v2.s[4] + fmul v0.4s, v1.4s, v22.s[4] + fmul v0.2d, v1.2d, v2.d[2] + fmul v0.2d, v1.2d, v22.d[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: mul v0.2d, v1.2d, v2.d[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmul v0.4h, v1.4h, v2.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.4s, v1.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.2d, v1.2d, v2.d[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul v0.2d, v1.2d, v22.d[2] +// CHECK-ERROR: ^ + + fmulx v0.4h, v1.4h, v2.h[4] + fmulx v0.2s, v1.2s, v2.s[4] + fmulx v0.2s, v1.2s, v22.s[4] + fmulx v0.4s, v1.4s, v2.s[4] + fmulx v0.4s, v1.4s, v22.s[4] + fmulx v0.2d, v1.2d, v2.d[2] + fmulx v0.2d, v1.2d, v22.d[2] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx v0.4h, v1.4h, v2.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.4s, v1.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.2d, v1.2d, v2.d[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx v0.2d, v1.2d, v22.d[2] +// CHECK-ERROR: ^ + + smull v0.4h, v1.4h, v2.h[2] + smull v0.4s, v1.4h, v2.h[8] + smull v0.4s, v1.4h, v16.h[4] + smull v0.2s, v1.2s, v2.s[2] + smull v0.2d, v1.2s, v2.s[4] + smull v0.2d, v1.2s, v22.s[4] + smull2 v0.4h, v1.8h, v2.h[2] + smull2 v0.4s, v1.8h, v2.h[8] + smull2 v0.4s, v1.8h, v16.h[4] + smull2 v0.2s, v1.4s, v2.s[2] + smull2 v0.2d, v1.4s, v2.s[4] + smull2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.4s, v1.4h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull v0.2s, v1.2s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.4h, v1.8h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull2 v0.4s, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.4s, v1.8h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smull2 v0.2s, v1.4s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull2 v0.2d, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: smull2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + umull v0.4h, v1.4h, v2.h[2] + umull v0.4s, v1.4h, v2.h[8] + umull v0.4s, v1.4h, v16.h[4] + umull v0.2s, v1.2s, v2.s[2] + umull v0.2d, v1.2s, v2.s[4] + umull v0.2d, v1.2s, v22.s[4] + umull2 v0.4h, v1.8h, v2.h[2] + umull2 v0.4s, v1.8h, v2.h[8] + umull2 v0.4s, v1.8h, v16.h[4] + umull2 v0.2s, v1.4s, v2.s[2] + umull2 v0.2d, v1.4s, v2.s[4] + umull2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.4s, v1.4h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull v0.2s, v1.2s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.4h, v1.8h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull2 v0.4s, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.4s, v1.8h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umull2 v0.2s, v1.4s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull2 v0.2d, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: umull2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + sqdmull v0.4h, v1.4h, v2.h[2] + sqdmull v0.4s, v1.4h, v2.h[8] + sqdmull v0.4s, v1.4h, v16.h[4] + sqdmull v0.2s, v1.2s, v2.s[2] + sqdmull v0.2d, v1.2s, v2.s[4] + sqdmull v0.2d, v1.2s, v22.s[4] + sqdmull2 v0.4h, v1.8h, v2.h[2] + sqdmull2 v0.4s, v1.8h, v2.h[8] + sqdmull2 v0.4s, v1.8h, v16.h[4] + sqdmull2 v0.2s, v1.4s, v2.s[2] + sqdmull2 v0.2d, v1.4s, v2.s[4] + sqdmull2 v0.2d, v1.4s, v22.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.4h, v1.4h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull v0.4s, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.4s, v1.4h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull v0.2s, v1.2s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull v0.2d, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull v0.2d, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.4h, v1.8h, v2.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.4s, v1.8h, v16.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull2 v0.2s, v1.4s, v2.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull2 v0.2d, v1.4s, v22.s[4] +// CHECK-ERROR: ^ + + sqdmulh v0.4h, v1.4h, v2.h[8] + sqdmulh v0.4h, v1.4h, v16.h[2] + sqdmulh v0.8h, v1.8h, v2.h[8] + sqdmulh v0.8h, v1.8h, v16.h[2] + sqdmulh v0.2s, v1.2s, v2.s[4] + sqdmulh v0.2s, v1.2s, v22.s[4] + sqdmulh v0.4s, v1.4s, v2.s[4] + sqdmulh v0.4s, v1.4s, v22.s[4] + sqdmulh v0.2d, v1.2d, v22.d[1] + +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.4h, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v0.4h, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v0.8h, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh v0.4s, v1.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh v0.2d, v1.2d, v22.d[1] +// CHECK-ERROR: ^ + + sqrdmulh v0.4h, v1.4h, v2.h[8] + sqrdmulh v0.4h, v1.4h, v16.h[2] + sqrdmulh v0.8h, v1.8h, v2.h[8] + sqrdmulh v0.8h, v1.8h, v16.h[2] + sqrdmulh v0.2s, v1.2s, v2.s[4] + sqrdmulh v0.2s, v1.2s, v22.s[4] + sqrdmulh v0.4s, v1.4s, v2.s[4] + sqrdmulh v0.4s, v1.4s, v22.s[4] + sqrdmulh v0.2d, v1.2d, v22.d[1] + +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v0.4h, v1.4h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v2.h[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v0.8h, v1.8h, v16.h[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.2s, v1.2s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v2.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh v0.4s, v1.4s, v22.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh v0.2d, v1.2d, v22.d[1] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Across vectors +//---------------------------------------------------------------------- + + saddlv b0, v1.8b + saddlv b0, v1.16b + saddlv h0, v1.4h + saddlv h0, v1.8h + saddlv s0, v1.2s + saddlv s0, v1.4s + saddlv d0, v1.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv b0, v1.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv b0, v1.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv h0, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv h0, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv s0, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlv d0, v1.2s +// CHECK-ERROR: ^ + + uaddlv b0, v1.8b + uaddlv b0, v1.16b + uaddlv h0, v1.4h + uaddlv h0, v1.8h + uaddlv s0, v1.2s + uaddlv s0, v1.4s + uaddlv d0, v1.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv b0, v1.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv b0, v1.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv h0, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv h0, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv s0, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlv d0, v1.2s +// CHECK-ERROR: ^ + + smaxv s0, v1.2s + sminv s0, v1.2s + umaxv s0, v1.2s + uminv s0, v1.2s + addv s0, v1.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smaxv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sminv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umaxv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uminv s0, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addv s0, v1.2s +// CHECK-ERROR: ^ + + smaxv d0, v1.2d + sminv d0, v1.2d + umaxv d0, v1.2d + uminv d0, v1.2d + addv d0, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: smaxv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sminv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: umaxv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uminv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: addv d0, v1.2d +// CHECK-ERROR: ^ + + fmaxnmv b0, v1.16b + fminnmv b0, v1.16b + fmaxv b0, v1.16b + fminv b0, v1.16b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmv b0, v1.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmv b0, v1.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxv b0, v1.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminv b0, v1.16b +// CHECK-ERROR: ^ + + fmaxnmv h0, v1.8h + fminnmv h0, v1.8h + fmaxv h0, v1.8h + fminv h0, v1.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmv h0, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmv h0, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxv h0, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminv h0, v1.8h +// CHECK-ERROR: ^ + + fmaxnmv d0, v1.2d + fminnmv d0, v1.2d + fmaxv d0, v1.2d + fminv d0, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxnmv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminnmv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmaxv d0, v1.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fminv d0, v1.2d +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating-point Multiply Extended +//---------------------------------------------------------------------- + + fmulx s20, h22, s15 + fmulx d23, d11, s1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx s20, h22, s15 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx d23, d11, s1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating-point Reciprocal Step +//---------------------------------------------------------------------- + + frecps s21, s16, h13 + frecps d22, s30, d21 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecps s21, s16, h13 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecps d22, s30, d21 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating-point Reciprocal Square Root Step +//---------------------------------------------------------------------- + + frsqrts s21, h5, s12 + frsqrts d8, s22, d18 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrts s21, h5, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrts d8, s22, d18 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector load/store multiple N-element structure (class SIMD lselem) +//---------------------------------------------------------------------- + ld1 {x3}, [x2] + ld1 {v4}, [x0] + ld1 {v32.16b}, [x0] + ld1 {v15.8h}, [x32] +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1 {x3}, [x2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1 {v4}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1 {v32.16b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v15.8h}, [x32] +// CHECK-ERROR: ^ + + ld1 {v0.16b, v2.16b}, [x0] + ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] + ld1 v0.8b, v1.8b}, [x0] + ld1 {v0.8h-v4.8h}, [x0] + ld1 {v1.8h-v1.8h}, [x0] + ld1 {v15.8h-v17.4h}, [x15] + ld1 {v0.8b-v2.8b, [x0] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld1 {v0.16b, v2.16b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: ld1 v0.8b, v1.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: ld1 {v0.8h-v4.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: ld1 {v1.8h-v1.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: ld1 {v15.8h-v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: '}' expected +// CHECK-ERROR: ld1 {v0.8b-v2.8b, [x0] +// CHECK-ERROR: ^ + + ld2 {v15.8h, v16.4h}, [x15] + ld2 {v0.8b, v2.8b}, [x0] + ld2 {v15.4h, v16.4h, v17.4h}, [x32] + ld2 {v15.8h-v16.4h}, [x15] + ld2 {v0.2d-v2.2d}, [x0] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld2 {v15.8h, v16.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld2 {v0.8b, v2.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2 {v15.4h, v16.4h, v17.4h}, [x32] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: ld2 {v15.8h-v16.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2 {v0.2d-v2.2d}, [x0] +// CHECK-ERROR: ^ + + ld3 {v15.8h, v16.8h, v17.4h}, [x15] + ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] + ld3 {v0.8b, v2.8b, v3.8b}, [x0] + ld3 {v15.8h-v17.4h}, [x15] + ld3 {v31.4s-v2.4s}, [sp] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld3 {v15.8h, v16.8h, v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld3 {v0.8b, v2.8b, v3.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: ld3 {v15.8h-v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld3 {v31.4s-v2.4s}, [sp] +// CHECK-ERROR: ^ + + ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] + ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] + ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] + ld4 {v15.8h-v18.4h}, [x15] + ld4 {v31.2s-v1.2s}, [x31] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: ld4 {v15.8h-v18.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld4 {v31.2s-v1.2s}, [x31] +// CHECK-ERROR: ^ + + st1 {x3}, [x2] + st1 {v4}, [x0] + st1 {v32.16b}, [x0] + st1 {v15.8h}, [x32] +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st1 {x3}, [x2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st1 {v4}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st1 {v32.16b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v15.8h}, [x32] +// CHECK-ERROR: ^ + + st1 {v0.16b, v2.16b}, [x0] + st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] + st1 v0.8b, v1.8b}, [x0] + st1 {v0.8h-v4.8h}, [x0] + st1 {v1.8h-v1.8h}, [x0] + st1 {v15.8h-v17.4h}, [x15] + st1 {v0.8b-v2.8b, [x0] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st1 {v0.16b, v2.16b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: '{' expected +// CHECK-ERROR: st1 v0.8b, v1.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: st1 {v0.8h-v4.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: st1 {v1.8h-v1.8h}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: st1 {v15.8h-v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: '}' expected +// CHECK-ERROR: st1 {v0.8b-v2.8b, [x0] +// CHECK-ERROR: ^ + + st2 {v15.8h, v16.4h}, [x15] + st2 {v0.8b, v2.8b}, [x0] + st2 {v15.4h, v16.4h, v17.4h}, [x30] + st2 {v15.8h-v16.4h}, [x15] + st2 {v0.2d-v2.2d}, [x0] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st2 {v15.8h, v16.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st2 {v0.8b, v2.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v15.4h, v16.4h, v17.4h}, [x30] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: st2 {v15.8h-v16.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v0.2d-v2.2d}, [x0] +// CHECK-ERROR: ^ + + st3 {v15.8h, v16.8h, v17.4h}, [x15] + st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] + st3 {v0.8b, v2.8b, v3.8b}, [x0] + st3 {v15.8h-v17.4h}, [x15] + st3 {v31.4s-v2.4s}, [sp] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st3 {v15.8h, v16.8h, v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st3 {v0.8b, v2.8b, v3.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: st3 {v15.8h-v17.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st3 {v31.4s-v2.4s}, [sp] +// CHECK-ERROR: ^ + + st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] + st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] + st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] + st4 {v15.8h-v18.4h}, [x15] + st4 {v31.2s-v1.2s}, [x31] +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: st4 {v15.8h-v18.4h}, [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st4 {v31.2s-v1.2s}, [x31] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Vector post-index load/store multiple N-element structure +// (class SIMD lselem-post) +//---------------------------------------------------------------------- + ld1 {v0.16b}, [x0], #8 + ld1 {v0.8h, v1.16h}, [x0], x1 + ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v0.16b}, [x0], #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1 {v0.8h, v1.16h}, [x0], x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: ^ + + ld2 {v0.16b, v1.16b}, [x0], #16 + ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 + ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2 {v0.16b, v1.16b}, [x0], #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld3 {v5.2s, v6.2s, v7.2s}, [x1], #48 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: ^ + + st1 {v0.16b}, [x0], #8 + st1 {v0.8h, v1.16h}, [x0], x1 + st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v0.16b}, [x0], #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: st1 {v0.8h, v1.16h}, [x0], x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], #24 + ^ + + st2 {v0.16b, v1.16b}, [x0], #16 + st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 + st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v0.16b, v1.16b}, [x0], #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st3 {v5.2s, v6.2s, v7.2s}, [x1], #48 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: st4 {v31.2d, v0.2d, v1.2d, v2.1d}, [x3], x1 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Load single N-element structure to all lanes of N consecutive +// registers (N = 1,2,3,4) +//------------------------------------------------------------------------------ + ld1r {x1}, [x0] + ld2r {v31.4s, v0.2s}, [sp] + ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] +// CHECK-ERROR: error: expected vector type register +// CHECK-ERROR: ld1r {x1}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld2r {v31.4s, v0.2s}, [sp] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld3r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid space between two vectors +// CHECK-ERROR: ld4r {v31.2s, v0.2s, v1.2d, v2.2s}, [sp] +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Load/Store single N-element structure to/from one lane of N consecutive +// registers (N = 1, 2,3,4) +//------------------------------------------------------------------------------ + ld1 {v0.b}[16], [x0] + ld2 {v15.h, v16.h}[8], [x15] + ld3 {v31.s, v0.s, v1.s}[-1], [sp] + ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] +// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: ld1 {v0.b}[16], [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ld2 {v15.h, v16.h}[8], [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: ld3 {v31.s, v0.s, v1.s}[-1], [sp] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] +// CHECK-ERROR: ^ + + st1 {v0.d}[16], [x0] + st2 {v31.s, v0.s}[3], [8] + st3 {v15.h, v16.h, v17.h}[-1], [x15] + st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] +// CHECK-ERROR:: error: lane number incompatible with layout +// CHECK-ERROR: st1 {v0.d}[16], [x0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v31.s, v0.s}[3], [8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[-1], [x15] +// CHECK-ERROR: ^ +// CHECK-ERROR: lane number incompatible with layout +// CHECK-ERROR: st4 {v0.d, v1.d, v2.d, v3.d}[2], [x0] +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Post-index of load single N-element structure to all lanes of N consecutive +// registers (N = 1,2,3,4) +//------------------------------------------------------------------------------ + ld1r {v15.8h}, [x15], #5 + ld2r {v0.2d, v1.2d}, [x0], #7 + ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1 + ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1r {v15.8h}, [x15], #5 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2r {v0.2d, v1.2d}, [x0], #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], sp +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Post-index of Load/Store single N-element structure to/from one lane of N +// consecutive registers (N = 1, 2,3,4) +//------------------------------------------------------------------------------ + ld1 {v0.b}[0], [x0], #2 + ld2 {v15.h, v16.h}[0], [x15], #3 + ld3 {v31.s, v0.s, v1.d}[0], [sp], x9 + ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld1 {v0.b}[0], [x0], #2 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld2 {v15.h, v16.h}[0], [x15], #3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected the same vector layout +// CHECK-ERROR: ld3 {v31.s, v0.s, v1.d}[0], [sp], x9 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #24 +// CHECK-ERROR: ^ + + st1 {v0.d}[0], [x0], #7 + st2 {v31.s, v0.s}[0], [sp], #6 + st3 {v15.h, v16.h, v17.h}[0], [x15], #8 + st4 {v0.b, v1.b, v2.b, v3.b}[1], [x0], #1 +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st1 {v0.d}[0], [x0], #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st2 {v31.s, v0.s}[0], [sp], #6 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st3 {v15.h, v16.h, v17.h}[0], [x15], #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: st4 {v0.b, v1.b, v2.b, v3.b}[1], [x0], #1 +// CHECK-ERROR: ^ + + + ins v2.b[16], w1 + ins v7.h[8], w14 + ins v20.s[5], w30 + ins v1.d[2], x7 + ins v2.b[3], b1 + ins v7.h[2], h14 + ins v20.s[1], s30 + ins v1.d[0], d7 + +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ins v2.b[16], w1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ins v7.h[8], w14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ins v20.s[5], w30 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: ins v1.d[2], x7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ins v2.b[3], b1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ins v7.h[2], h14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ins v20.s[1], s30 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ins v1.d[0], d7 +// CHECK-ERROR: ^ + + smov w1, v0.b[16] + smov w14, v6.h[8] + smov x1, v0.b[16] + smov x14, v6.h[8] + smov x20, v9.s[5] + smov w1, v0.d[0] + smov w14, v6.d[1] + smov x1, v0.d[0] + smov x14, v6.d[1] + smov x20, v9.d[0] + +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR smov w1, v0.b[16] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR smov w14, v6.h[8] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR smov x1, v0.b[16] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR smov x14, v6.h[8] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR smov x20, v9.s[5] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR smov w1, v0.d[0] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR smov w14, v6.d[1] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR smov x1, v0.d[0] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR smov x14, v6.d[1] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR smov x20, v9.d[0] +// CHECK-ERROR ^ + + umov w1, v0.b[16] + umov w14, v6.h[8] + umov w20, v9.s[5] + umov x7, v18.d[3] + umov w1, v0.d[0] + umov s20, v9.s[2] + umov d7, v18.d[1] + +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR umov w1, v0.b[16] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR umov w14, v6.h[8] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR umov w20, v9.s[5] +// CHECK-ERROR ^ +// CHECK-ERROR error: lane number incompatible with layout +// CHECK-ERROR umov x7, v18.d[3] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR umov w1, v0.d[0] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR umov s20, v9.s[2] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR umov d7, v18.d[1] +// CHECK-ERROR ^ + + Ins v1.h[2], v3.b[6] + Ins v6.h[7], v7.s[2] + Ins v15.d[0], v22.s[2] + Ins v0.d[0], v4.b[1] + +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR Ins v1.h[2], v3.b[6] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR Ins v6.h[7], v7.s[2] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR Ins v15.d[0], v22.s[2] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR Ins v0.d[0], v4.b[1] +// CHECK-ERROR ^ + + dup v1.8h, v2.b[2] + dup v11.4s, v7.h[7] + dup v17.2d, v20.s[0] + dup v1.16b, v2.h[2] + dup v11.8h, v7.s[3] + dup v17.4s, v20.d[0] + dup v5.2d, v1.b[1] + +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v1.8h, v2.b[2] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v11.4s, v7.h[7] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v17.2d, v20.s[0] +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v1.16b, v2.h[2] +// CHECK-ERROR ^ +// CHECK-ERROR invalid operand for instruction +// CHECK-ERROR dup v11.8h, v7.s[3] +// CHECK-ERROR ^ +// CHECK-ERROR invalid operand for instruction +// CHECK-ERROR dup v17.4s, v20.d[0] +// CHECK-ERROR ^ +// CHECK-ERROR invalid operand for instruction +// CHECK-ERROR dup v5.2d, v1.b[1] +// CHECK-ERROR ^ + + dup v1.8b, b1 + dup v11.4h, h14 + dup v17.2s, s30 + dup v1.16b, d2 + dup v11.8s, w16 + dup v17.4d, w28 + dup v5.2d, w0 + +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v1.8b, b1 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v11.4h, h14 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v17.2s, s30 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v1.16b, d2 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v11.8s, w16 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v17.4d, w28 +// CHECK-ERROR ^ +// CHECK-ERROR error: invalid operand for instruction +// CHECK-ERROR dup v5.2d, w0 +// CHECK-ERROR ^ + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Equal +//---------------------------------------------------------------------- + + cmeq b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmeq b20, d21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Equal To Zero +//---------------------------------------------------------------------- + + cmeq d20, b21, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmeq d20, b21, #0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Unsigned Higher Or Same +//---------------------------------------------------------------------- + + cmhs b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmhs b20, d21, d22 +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greather Than Or Equal +//---------------------------------------------------------------------- + + cmge b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmge b20, d21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greather Than Or Equal To Zero +//---------------------------------------------------------------------- + + cmge d20, b21, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmge d20, b21, #0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Unsigned Higher +//---------------------------------------------------------------------- + + cmhi b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmhi b20, d21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greater Than +//---------------------------------------------------------------------- + + cmgt b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmgt b20, d21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greater Than Zero +//---------------------------------------------------------------------- + + cmgt d20, b21, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmgt d20, b21, #0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Signed Less Than Or Equal To Zero +//---------------------------------------------------------------------- + + cmle d20, b21, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmle d20, b21, #0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Less Than Zero +//---------------------------------------------------------------------- + + cmlt d20, b21, #0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmlt d20, b21, #0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Test Bits +//---------------------------------------------------------------------- + + cmtst b20, d21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cmtst b20, d21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Equal +//---------------------------------------------------------------------- + + fcmeq s10, h11, s12 + fcmeq d20, s21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq s10, h11, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq d20, s21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Equal To Zero +//---------------------------------------------------------------------- + + fcmeq h10, s11, #0.0 + fcmeq d20, s21, #0.0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq h10, s11, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmeq d20, s21, #0.0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greater Than Or Equal +//---------------------------------------------------------------------- + + fcmge s10, h11, s12 + fcmge d20, s21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge s10, h11, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge d20, s21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero +//---------------------------------------------------------------------- + + fcmge h10, s11, #0.0 + fcmge d20, s21, #0.0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge h10, s11, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmge d20, s21, #0.0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greather Than +//---------------------------------------------------------------------- + + fcmgt s10, h11, s12 + fcmgt d20, s21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt s10, h11, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt d20, s21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greather Than Zero +//---------------------------------------------------------------------- + + fcmgt h10, s11, #0.0 + fcmgt d20, s21, #0.0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt h10, s11, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmgt d20, s21, #0.0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Less Than Or Equal To Zero +//---------------------------------------------------------------------- + + fcmle h10, s11, #0.0 + fcmle d20, s21, #0.0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmle h10, s11, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmle d20, s21, #0.0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Less Than +//---------------------------------------------------------------------- + + fcmlt h10, s11, #0.0 + fcmlt d20, s21, #0.0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmlt h10, s11, #0.0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcmlt d20, s21, #0.0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal +//---------------------------------------------------------------------- + + facge s10, h11, s12 + facge d20, s21, d22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facge s10, h11, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facge d20, s21, d22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Compare Mask Greater Than +//---------------------------------------------------------------------- + + facgt s10, h11, s12 + facgt d20, d21, s22 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facgt s10, h11, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: facgt d20, d21, s22 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Accumulated of Unsigned Value +//---------------------------------------------------------------------- + + suqadd b0, h1 + suqadd h0, s1 + suqadd s0, d1 + suqadd d0, b0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd b0, h1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd h0, s1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd s0, d1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd d0, b0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Saturating Accumulated of Signed Value +//---------------------------------------------------------------------- + + usqadd b0, h1 + usqadd h0, s1 + usqadd s0, d1 + usqadd d0, b1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd b0, h1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd h0, s1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd s0, d1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd d0, b1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Absolute Value +//---------------------------------------------------------------------- + + abs d29, s24 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs d29, s24 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Negate +//---------------------------------------------------------------------- + + neg d29, s24 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: neg d29, s24 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Add Long +//---------------------------------------------------------------------- + + sqdmlal s17, h27, s12 + sqdmlal d19, s24, d12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal s17, h27, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: sqdmlal d19, s24, d12 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Subtract Long +//---------------------------------------------------------------------- + + sqdmlsl s14, h12, s25 + sqdmlsl d12, s23, d13 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl s14, h12, s25 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: sqdmlsl d12, s23, d13 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply Long +//---------------------------------------------------------------------- + + sqdmull s12, h22, s12 + sqdmull d15, s22, d12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull s12, h22, s12 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: too few operands for instruction +// CHECK-ERROR: sqdmull d15, s22, d12 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Extract Unsigned Narrow +//---------------------------------------------------------------------- + + sqxtun b19, b14 + sqxtun h21, h15 + sqxtun s20, s12 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun b19, b14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun h21, h15 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun s20, s12 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Extract Signed Narrow +//---------------------------------------------------------------------- + + sqxtn b18, b18 + sqxtn h20, h17 + sqxtn s19, s14 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn b18, b18 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn h20, h17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn s19, s14 +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Scalar Unsigned Saturating Extract Narrow +//---------------------------------------------------------------------- + + uqxtn b18, b18 + uqxtn h20, h17 + uqxtn s19, s14 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn b18, b18 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn h20, h17 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn s19, s14 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Shift Right (Immediate) +//---------------------------------------------------------------------- + sshr d15, d16, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sshr d15, d16, #99 +// CHECK-ERROR: ^ + + sshr d15, s16, #31 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sshr d15, s16, #31 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Shift Right (Immediate) +//---------------------------------------------------------------------- + + ushr d10, d17, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ushr d10, d17, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Rounding Shift Right (Immediate) +//---------------------------------------------------------------------- + + srshr d19, d18, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srshr d19, d18, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unigned Rounding Shift Right (Immediate) +//---------------------------------------------------------------------- + + urshr d20, d23, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: urshr d20, d23, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + + ssra d18, d12, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ssra d18, d12, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + + usra d20, d13, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: usra d20, d13, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Rounding Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + + srsra d15, d11, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: srsra d15, d11, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Rounding Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + + ursra d18, d10, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ursra d18, d10, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Shift Left (Immediate) +//---------------------------------------------------------------------- + + shl d7, d10, #99 + +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: shl d7, d10, #99 +// CHECK-ERROR: ^ + + shl d7, s16, #31 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shl d7, s16, #31 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Shift Left (Immediate) +//---------------------------------------------------------------------- + + sqshl b11, b19, #99 + sqshl h13, h18, #99 + sqshl s14, s17, #99 + sqshl d15, d16, #99 + +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshl b11, b19, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshl h13, h18, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshl s14, s17, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshl d15, d16, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Unsigned Saturating Shift Left (Immediate) +//---------------------------------------------------------------------- + + uqshl b18, b15, #99 + uqshl h11, h18, #99 + uqshl s14, s19, #99 + uqshl d15, d12, #99 + +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: uqshl b18, b15, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: uqshl h11, h18, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: uqshl s14, s19, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: uqshl d15, d12, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Shift Left Unsigned (Immediate) +//---------------------------------------------------------------------- + + sqshlu b15, b18, #99 + sqshlu h19, h17, #99 + sqshlu s16, s14, #99 + sqshlu d11, d13, #99 + +// CHECK-ERROR: error: expected integer in range [0, 7] +// CHECK-ERROR: sqshlu b15, b18, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 15] +// CHECK-ERROR: sqshlu h19, h17, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 31] +// CHECK-ERROR: sqshlu s16, s14, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sqshlu d11, d13, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Shift Right And Insert (Immediate) +//---------------------------------------------------------------------- + + sri d10, d12, #99 + +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: sri d10, d12, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Shift Left And Insert (Immediate) +//---------------------------------------------------------------------- + + sli d10, d14, #99 + +// CHECK-ERROR: error: expected integer in range [0, 63] +// CHECK-ERROR: sli d10, d14, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + + sqshrn b10, h15, #99 + sqshrn h17, s10, #99 + sqshrn s18, d10, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrn b10, h15, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrn h17, s10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrn s18, d10, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Unsigned Saturating Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + + uqshrn b12, h10, #99 + uqshrn h10, s14, #99 + uqshrn s10, d12, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqshrn b12, h10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqshrn h10, s14, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqshrn s10, d12, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Rounded Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + + sqrshrn b10, h13, #99 + sqrshrn h15, s10, #99 + sqrshrn s15, d12, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrn b10, h13, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrn h15, s10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrn s15, d12, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Unsigned Saturating Rounded Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + + uqrshrn b10, h12, #99 + uqrshrn h12, s10, #99 + uqrshrn s10, d10, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: uqrshrn b10, h12, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: uqrshrn h12, s10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: uqrshrn s10, d10, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Shift Right Unsigned Narrow (Immediate) +//---------------------------------------------------------------------- + + sqshrun b15, h10, #99 + sqshrun h20, s14, #99 + sqshrun s10, d15, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqshrun b15, h10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqshrun h20, s14, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqshrun s10, d15, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) +//---------------------------------------------------------------------- + + sqrshrun b17, h10, #99 + sqrshrun h10, s13, #99 + sqrshrun s22, d16, #99 + +// CHECK-ERROR: error: expected integer in range [1, 8] +// CHECK-ERROR: sqrshrun b17, h10, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 16] +// CHECK-ERROR: sqrshrun h10, s13, #99 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: sqrshrun s22, d16, #99 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed Fixed-point Convert To Floating-Point (Immediate) +//---------------------------------------------------------------------- + + scvtf s22, s13, #0 + scvtf s22, s13, #33 + scvtf d21, d12, #65 + scvtf d21, s12, #31 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: scvtf s22, s13, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: scvtf s22, s13, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: scvtf d21, d12, #65 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf d21, s12, #31 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate) +//---------------------------------------------------------------------- + + ucvtf s22, s13, #34 + ucvtf d21, d14, #65 + ucvtf d21, s14, #64 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: ucvtf s22, s13, #34 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: ucvtf d21, d14, #65 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf d21, s14, #64 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Element reverse +//------------------------------------------------------------------------------ + rev64 v6.2d, v8.2d + rev32 v30.2s, v31.2s + rev32 v30.4s, v31.4s + rev32 v30.2d, v31.2d + rev16 v21.4h, v1.4h + rev16 v21.8h, v1.8h + rev16 v21.2s, v1.2s + rev16 v21.4s, v1.4s + rev16 v21.2d, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev64 v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.2s, v31.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.4s, v31.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev32 v30.2d, v31.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.4h, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.8h, v1.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.2s, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rev16 v21.2d, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer pairwise add long +//------------------------------------------------------------------------------ + + saddlp v3.8h, v21.8h + saddlp v8.8b, v5.8b + saddlp v9.8h, v1.4s + saddlp v0.4s, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v3.8h, v21.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v8.8b, v5.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v9.8h, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: saddlp v0.4s, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add long +//------------------------------------------------------------------------------ + + uaddlp v3.8h, v21.8h + uaddlp v8.8b, v5.8b + uaddlp v9.8h, v1.4s + uaddlp v0.4s, v1.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v3.8h, v21.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v8.8b, v5.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v9.8h, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uaddlp v0.4s, v1.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + sadalp v3.16b, v21.16b + sadalp v8.4h, v5.4h + sadalp v9.4s, v1.4s + sadalp v0.4h, v1.2s + sadalp v12.2d, v4.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v3.16b, v21.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v8.4h, v5.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v9.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v0.4h, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sadalp v12.2d, v4.8h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + uadalp v3.16b, v21.16b + uadalp v8.4h, v5.4h + uadalp v9.4s, v1.4s + uadalp v0.4h, v1.2s + uadalp v12.2d, v4.8h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v3.16b, v21.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v8.4h, v5.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v9.4s, v1.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v0.4h, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uadalp v12.2d, v4.8h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating accumulate of unsigned value +//------------------------------------------------------------------------------ + + suqadd v0.16b, v31.8b + suqadd v1.8b, v9.8h + suqadd v13.4h, v21.4s + suqadd v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: suqadd v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer saturating accumulate of signed value +//------------------------------------------------------------------------------ + + usqadd v0.16b, v31.8b + usqadd v2.8h, v4.4h + usqadd v13.4h, v21.4s + usqadd v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: usqadd v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer saturating absolute +//------------------------------------------------------------------------------ + + sqabs v0.16b, v31.8b + sqabs v2.8h, v4.4h + sqabs v6.4s, v8.2s + sqabs v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqabs v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating negate +//------------------------------------------------------------------------------ + + sqneg v0.16b, v31.8b + sqneg v2.8h, v4.4h + sqneg v6.4s, v8.2s + sqneg v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqneg v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer absolute +//------------------------------------------------------------------------------ + + abs v0.16b, v31.8b + abs v2.8h, v4.4h + abs v6.4s, v8.2s + abs v6.2d, v8.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v0.16b, v31.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v2.8h, v4.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v6.4s, v8.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: abs v6.2d, v8.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer count leading sign bits +//------------------------------------------------------------------------------ + + cls v0.2d, v31.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cls v0.2d, v31.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer count leading zeros +//------------------------------------------------------------------------------ + + clz v0.2d, v31.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: clz v0.2d, v31.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Population count +//------------------------------------------------------------------------------ + + cnt v2.8h, v4.8h + cnt v6.4s, v8.4s + cnt v6.2d, v8.2d + cnt v13.4h, v21.4h + cnt v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: cnt v4.2s, v0.2s +// CHECK-ERROR: ^ + + +//------------------------------------------------------------------------------ +// Bitwise NOT +//------------------------------------------------------------------------------ + + not v2.8h, v4.8h + not v6.4s, v8.4s + not v6.2d, v8.2d + not v13.4h, v21.4h + not v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: not v4.2s, v0.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Bitwise reverse +//------------------------------------------------------------------------------ + + rbit v2.8h, v4.8h + rbit v6.4s, v8.4s + rbit v6.2d, v8.2d + rbit v13.4h, v21.4h + rbit v4.2s, v0.2s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v6.4s, v8.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v6.2d, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: rbit v4.2s, v0.2s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point absolute +//------------------------------------------------------------------------------ + + fabs v0.16b, v31.16b + fabs v2.8h, v4.8h + fabs v1.8b, v9.8b + fabs v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabs v13.4h, v21.4h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point negate +//------------------------------------------------------------------------------ + + fneg v0.16b, v31.16b + fneg v2.8h, v4.8h + fneg v1.8b, v9.8b + fneg v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fneg v13.4h, v21.4h +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer extract and narrow +//------------------------------------------------------------------------------ + + xtn v0.16b, v31.8h + xtn v2.8h, v4.4s + xtn v6.4s, v8.2d + xtn2 v1.8b, v9.8h + xtn2 v13.4h, v21.4s + xtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: xtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and unsigned narrow +//------------------------------------------------------------------------------ + + sqxtun v0.16b, v31.8h + sqxtun v2.8h, v4.4s + sqxtun v6.4s, v8.2d + sqxtun2 v1.8b, v9.8h + sqxtun2 v13.4h, v21.4s + sqxtun2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtun2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and narrow +//------------------------------------------------------------------------------ + + sqxtn v0.16b, v31.8h + sqxtn v2.8h, v4.4s + sqxtn v6.4s, v8.2d + sqxtn2 v1.8b, v9.8h + sqxtn2 v13.4h, v21.4s + sqxtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqxtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Unsigned integer saturating extract and narrow +//------------------------------------------------------------------------------ + + uqxtn v0.16b, v31.8h + uqxtn v2.8h, v4.4s + uqxtn v6.4s, v8.2d + uqxtn2 v1.8b, v9.8h + uqxtn2 v13.4h, v21.4s + uqxtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v0.16b, v31.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v1.8b, v9.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: uqxtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Integer shift left long +//------------------------------------------------------------------------------ + + shll2 v2.8h, v4.16b, #7 + shll2 v6.4s, v8.8h, #15 + shll2 v6.2d, v8.4s, #31 + shll v2.8h, v4.16b, #8 + shll v6.4s, v8.8h, #16 + shll v6.2d, v8.4s, #32 + shll v2.8h, v4.8b, #8 + shll v6.4s, v8.4h, #16 + shll v6.2d, v8.2s, #32 + shll2 v2.8h, v4.8b, #5 + shll2 v6.4s, v8.4h, #14 + shll2 v6.2d, v8.2s, #1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v2.8h, v4.16b, #7 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.4s, v8.8h, #15 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.2d, v8.4s, #31 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v2.8h, v4.16b, #8 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v6.4s, v8.8h, #16 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll v6.2d, v8.4s, #32 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v2.8h, v4.8b, #5 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.4s, v8.4h, #14 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: shll2 v6.2d, v8.2s, #1 +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert downsize +//------------------------------------------------------------------------------ + + fcvtn v2.8h, v4.4s + fcvtn v6.4s, v8.2d + fcvtn2 v13.4h, v21.4s + fcvtn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn v2.8h, v4.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn2 v13.4h, v21.4s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert downsize with inexact +//------------------------------------------------------------------------------ + + fcvtxn v6.4s, v8.2d + fcvtxn2 v4.2s, v0.2d + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn v6.4s, v8.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn2 v4.2s, v0.2d +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point convert upsize +//------------------------------------------------------------------------------ + + fcvtl2 v9.4s, v1.4h + fcvtl2 v0.2d, v1.2s + fcvtl v12.4s, v4.8h + fcvtl v17.2d, v28.4s + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl2 v9.4s, v1.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl2 v0.2d, v1.2s +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl v12.4s, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtl v17.2d, v28.4s +// CHECK-ERROR: ^ + +//------------------------------------------------------------------------------ +// Floating-point round to integral +//------------------------------------------------------------------------------ + + frintn v0.16b, v31.16b + frintn v2.8h, v4.8h + frintn v1.8b, v9.8b + frintn v13.4h, v21.4h + + frinta v0.16b, v31.16b + frinta v2.8h, v4.8h + frinta v1.8b, v9.8b + frinta v13.4h, v21.4h + + frintp v0.16b, v31.16b + frintp v2.8h, v4.8h + frintp v1.8b, v9.8b + frintp v13.4h, v21.4h + + frintm v0.16b, v31.16b + frintm v2.8h, v4.8h + frintm v1.8b, v9.8b + frintm v13.4h, v21.4h + + frintx v0.16b, v31.16b + frintx v2.8h, v4.8h + frintx v1.8b, v9.8b + frintx v13.4h, v21.4h + + frintz v0.16b, v31.16b + frintz v2.8h, v4.8h + frintz v1.8b, v9.8b + frintz v13.4h, v21.4h + + frinti v0.16b, v31.16b + frinti v2.8h, v4.8h + frinti v1.8b, v9.8b + frinti v13.4h, v21.4h + + fcvtns v0.16b, v31.16b + fcvtns v2.8h, v4.8h + fcvtns v1.8b, v9.8b + fcvtns v13.4h, v21.4h + + fcvtnu v0.16b, v31.16b + fcvtnu v2.8h, v4.8h + fcvtnu v1.8b, v9.8b + fcvtnu v13.4h, v21.4h + + fcvtps v0.16b, v31.16b + fcvtps v2.8h, v4.8h + fcvtps v1.8b, v9.8b + fcvtps v13.4h, v21.4h + + fcvtpu v0.16b, v31.16b + fcvtpu v2.8h, v4.8h + fcvtpu v1.8b, v9.8b + fcvtpu v13.4h, v21.4h + + fcvtms v0.16b, v31.16b + fcvtms v2.8h, v4.8h + fcvtms v1.8b, v9.8b + fcvtms v13.4h, v21.4h + + fcvtmu v0.16b, v31.16b + fcvtmu v2.8h, v4.8h + fcvtmu v1.8b, v9.8b + fcvtmu v13.4h, v21.4h + + fcvtzs v0.16b, v31.16b + fcvtzs v2.8h, v4.8h + fcvtzs v1.8b, v9.8b + fcvtzs v13.4h, v21.4h + + fcvtzu v0.16b, v31.16b + fcvtzu v2.8h, v4.8h + fcvtzu v1.8b, v9.8b + fcvtzu v13.4h, v21.4h + + fcvtas v0.16b, v31.16b + fcvtas v2.8h, v4.8h + fcvtas v1.8b, v9.8b + fcvtas v13.4h, v21.4h + + fcvtau v0.16b, v31.16b + fcvtau v2.8h, v4.8h + fcvtau v1.8b, v9.8b + fcvtau v13.4h, v21.4h + + urecpe v0.16b, v31.16b + urecpe v2.8h, v4.8h + urecpe v1.8b, v9.8b + urecpe v13.4h, v21.4h + urecpe v1.2d, v9.2d + + ursqrte v0.16b, v31.16b + ursqrte v2.8h, v4.8h + ursqrte v1.8b, v9.8b + ursqrte v13.4h, v21.4h + ursqrte v1.2d, v9.2d + + scvtf v0.16b, v31.16b + scvtf v2.8h, v4.8h + scvtf v1.8b, v9.8b + scvtf v13.4h, v21.4h + + ucvtf v0.16b, v31.16b + ucvtf v2.8h, v4.8h + ucvtf v1.8b, v9.8b + ucvtf v13.4h, v21.4h + + frecpe v0.16b, v31.16b + frecpe v2.8h, v4.8h + frecpe v1.8b, v9.8b + frecpe v13.4h, v21.4h + + frsqrte v0.16b, v31.16b + frsqrte v2.8h, v4.8h + frsqrte v1.8b, v9.8b + frsqrte v13.4h, v21.4h + + fsqrt v0.16b, v31.16b + fsqrt v2.8h, v4.8h + fsqrt v1.8b, v9.8b + fsqrt v13.4h, v21.4h + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintn v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinta v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintp v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintm v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintx v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frintz v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frinti v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: urecpe v1.2d, v9.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ursqrte v1.2d, v9.2d +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: scvtf v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ucvtf v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frecpe v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: frsqrte v13.4h, v21.4h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v0.16b, v31.16b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v2.8h, v4.8h +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v1.8b, v9.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fsqrt v13.4h, v21.4h +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzs s21, s12, #0 + fcvtzs d21, d12, #65 + fcvtzs s21, d12, #1 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzs s21, s12, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzs d21, d12, #65 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs s21, d12, #1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzu s21, s12, #33 + fcvtzu d21, d12, #0 + fcvtzu s21, d12, #1 + +// CHECK-ERROR: error: expected integer in range [1, 32] +// CHECK-ERROR: fcvtzu s21, s12, #33 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected integer in range [1, 64] +// CHECK-ERROR: fcvtzu d21, d12, #0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu s21, d12, #1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Unsigned Saturating Extract Narrow +//---------------------------------------------------------------------- + + aese v0.8h, v1.8h + aese v0.4s, v1.4s + aese v0.2d, v1.2d + aesd v0.8h, v1.8h + aesmc v0.8h, v1.8h + aesimc v0.8h, v1.8h + +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.4s, v1.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aese v0.2d, v1.2d +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesd v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesmc v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: aesimc v0.8h, v1.8h +// CHECK: ^ + + sha1h b0, b1 + sha1h h0, h1 + sha1h d0, d1 + sha1h q0, q1 + sha1su1 v0.16b, v1.16b + sha1su1 v0.8h, v1.8h + sha1su1 v0.2d, v1.2d + sha256su0 v0.16b, v1.16b + +// CHECK: error: invalid operand for instruction +// CHECK: sha1h b0, b1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h h0, h1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h d0, d1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1h q0, q1 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.16b, v1.16b +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.8h, v1.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su1 v0.2d, v1.2d +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256su0 v0.16b, v1.16b +// CHECK: ^ + + sha1c q0, q1, v2.4s + sha1p q0, q1, v2.4s + sha1m q0, q1, v2.4s + sha1su0 v0.16b, v1.16b, v2.16b + sha1su0 v0.8h, v1.8h, v2.8h + sha1su0 v0.2d, v1.2d, v2.2d + sha256h q0, q1, q2 + sha256h v0.4s, v1.4s, v2.4s + sha256h2 q0, q1, q2 + sha256su1 v0.16b, v1.16b, v2.16b + +// CHECK: error: invalid operand for instruction +// CHECK: sha1c q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1p q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1m q0, q1, v2.4s +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.16b, v1.16b, v2.16b +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.8h, v1.8h, v2.8h +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha1su0 v0.2d, v1.2d, v2.2d +// CHECK: ^ +// CHECK: error: too few operands for instruction +// CHECK: sha256h q0, q1, q2 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256h v0.4s, v1.4s, v2.4s +// CHECK: ^ +// CHECK: error: too few operands for instruction +// CHECK: sha256h2 q0, q1, q2 +// CHECK: ^ +// CHECK: error: invalid operand for instruction +// CHECK: sha256su1 v0.16b, v1.16b, v2.16b +// CHECK: ^ + +//---------------------------------------------------------------------- +// Bitwise extract +//---------------------------------------------------------------------- + + ext v0.8b, v1.8b, v2.4h, #0x3 + ext v0.4h, v1.4h, v2.4h, #0x3 + ext v0.2s, v1.2s, v2.2s, #0x1 + ext v0.1d, v1.1d, v2.1d, #0x0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.8b, v1.8b, v2.4h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.4h, v1.4h, v2.4h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.2s, v1.2s, v2.2s, #0x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.1d, v1.1d, v2.1d, #0x0 +// CHECK-ERROR: ^ + + ext v0.16b, v1.16b, v2.8h, #0x3 + ext v0.8h, v1.8h, v2.8h, #0x3 + ext v0.4s, v1.4s, v2.4s, #0x1 + ext v0.2d, v1.2d, v2.2d, #0x0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.16b, v1.16b, v2.8h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.8h, v1.8h, v2.8h, #0x3 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.4s, v1.4s, v2.4s, #0x1 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: ext v0.2d, v1.2d, v2.2d, #0x0 +// CHECK-ERROR: ^ + + +//---------------------------------------------------------------------- +// Permutation with 3 vectors +//---------------------------------------------------------------------- + + uzp1 v0.16b, v1.8b, v2.8b + uzp1 v0.8b, v1.4b, v2.4b + uzp1 v0.8h, v1.4h, v2.4h + uzp1 v0.4h, v1.2h, v2.2h + uzp1 v0.4s, v1.2s, v2.2s + uzp1 v0.2s, v1.1s, v2.1s + uzp1 v0.2d, v1.1d, v2.1d + uzp1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4289:22: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4290:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4291:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4292:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4293:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4294:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4295:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4296:17: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + uzp2 v0.16b, v1.8b, v2.8b + uzp2 v0.8b, v1.4b, v2.4b + uzp2 v0.8h, v1.4h, v2.4h + uzp2 v0.4h, v1.2h, v2.2h + uzp2 v0.4s, v1.2s, v2.2s + uzp2 v0.2s, v1.1s, v2.1s + uzp2 v0.2d, v1.1d, v2.1d + uzp2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4298:22: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4299:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4300:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4301:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4302:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4303:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4304:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4305:17: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + zip1 v0.16b, v1.8b, v2.8b + zip1 v0.8b, v1.4b, v2.4b + zip1 v0.8h, v1.4h, v2.4h + zip1 v0.4h, v1.2h, v2.2h + zip1 v0.4s, v1.2s, v2.2s + zip1 v0.2s, v1.1s, v2.1s + zip1 v0.2d, v1.1d, v2.1d + zip1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4307:22: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4308:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4309:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4310:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4311:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4312:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4313:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4314:17: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + zip2 v0.16b, v1.8b, v2.8b + zip2 v0.8b, v1.4b, v2.4b + zip2 v0.8h, v1.4h, v2.4h + zip2 v0.4h, v1.2h, v2.2h + zip2 v0.4s, v1.2s, v2.2s + zip2 v0.2s, v1.1s, v2.1s + zip2 v0.2d, v1.1d, v2.1d + zip2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4316:22: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4317:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4318:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4319:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4320:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4321:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4322:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4323:17: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + trn1 v0.16b, v1.8b, v2.8b + trn1 v0.8b, v1.4b, v2.4b + trn1 v0.8h, v1.4h, v2.4h + trn1 v0.4h, v1.2h, v2.2h + trn1 v0.4s, v1.2s, v2.2s + trn1 v0.2s, v1.1s, v2.1s + trn1 v0.2d, v1.1d, v2.1d + trn1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4325:22: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4326:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4327:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4328:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4329:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4330:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4331:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4332:17: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + trn2 v0.16b, v1.8b, v2.8b + trn2 v0.8b, v1.4b, v2.4b + trn2 v0.8h, v1.4h, v2.4h + trn2 v0.4h, v1.2h, v2.2h + trn2 v0.4s, v1.2s, v2.2s + trn2 v0.2s, v1.1s, v2.1s + trn2 v0.2d, v1.1d, v2.1d + trn2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4334:22: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4335:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4336:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4337:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4338:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4339:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4340:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4341:17: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + +//---------------------------------------------------------------------- +// Permutation with 3 vectors +//---------------------------------------------------------------------- + + uzp1 v0.16b, v1.8b, v2.8b + uzp1 v0.8b, v1.4b, v2.4b + uzp1 v0.8h, v1.4h, v2.4h + uzp1 v0.4h, v1.2h, v2.2h + uzp1 v0.4s, v1.2s, v2.2s + uzp1 v0.2s, v1.1s, v2.1s + uzp1 v0.2d, v1.1d, v2.1d + uzp1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4289:22: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4290:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4291:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4292:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4293:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4294:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4295:21: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4296:17: error: invalid operand for instruction +// CHECK-ERROR uzp1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + uzp2 v0.16b, v1.8b, v2.8b + uzp2 v0.8b, v1.4b, v2.4b + uzp2 v0.8h, v1.4h, v2.4h + uzp2 v0.4h, v1.2h, v2.2h + uzp2 v0.4s, v1.2s, v2.2s + uzp2 v0.2s, v1.1s, v2.1s + uzp2 v0.2d, v1.1d, v2.1d + uzp2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4298:22: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4299:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4300:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4301:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4302:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4303:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4304:21: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4305:17: error: invalid operand for instruction +// CHECK-ERROR uzp2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + zip1 v0.16b, v1.8b, v2.8b + zip1 v0.8b, v1.4b, v2.4b + zip1 v0.8h, v1.4h, v2.4h + zip1 v0.4h, v1.2h, v2.2h + zip1 v0.4s, v1.2s, v2.2s + zip1 v0.2s, v1.1s, v2.1s + zip1 v0.2d, v1.1d, v2.1d + zip1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4307:22: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4308:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4309:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4310:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4311:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4312:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4313:21: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4314:17: error: invalid operand for instruction +// CHECK-ERROR zip1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + zip2 v0.16b, v1.8b, v2.8b + zip2 v0.8b, v1.4b, v2.4b + zip2 v0.8h, v1.4h, v2.4h + zip2 v0.4h, v1.2h, v2.2h + zip2 v0.4s, v1.2s, v2.2s + zip2 v0.2s, v1.1s, v2.1s + zip2 v0.2d, v1.1d, v2.1d + zip2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4316:22: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4317:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4318:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4319:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4320:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4321:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4322:21: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4323:17: error: invalid operand for instruction +// CHECK-ERROR zip2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + trn1 v0.16b, v1.8b, v2.8b + trn1 v0.8b, v1.4b, v2.4b + trn1 v0.8h, v1.4h, v2.4h + trn1 v0.4h, v1.2h, v2.2h + trn1 v0.4s, v1.2s, v2.2s + trn1 v0.2s, v1.1s, v2.1s + trn1 v0.2d, v1.1d, v2.1d + trn1 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4325:22: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4326:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4327:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4328:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4329:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4330:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4331:21: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4332:17: error: invalid operand for instruction +// CHECK-ERROR trn1 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + + trn2 v0.16b, v1.8b, v2.8b + trn2 v0.8b, v1.4b, v2.4b + trn2 v0.8h, v1.4h, v2.4h + trn2 v0.4h, v1.2h, v2.2h + trn2 v0.4s, v1.2s, v2.2s + trn2 v0.2s, v1.1s, v2.1s + trn2 v0.2d, v1.1d, v2.1d + trn2 v0.1d, v1.1d, v2.1d + +// CHECK-ERROR <stdin>:4334:22: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.16b, v1.8b, v2.8b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4335:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.8b, v1.4b, v2.4b +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4336:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.8h, v1.4h, v2.4h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4337:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.4h, v1.2h, v2.2h +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4338:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.4s, v1.2s, v2.2s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4339:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.2s, v1.1s, v2.1s +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4340:21: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.2d, v1.1d, v2.1d +// CHECK-ERROR ^ +// CHECK-ERROR <stdin>:4341:17: error: invalid operand for instruction +// CHECK-ERROR trn2 v0.1d, v1.1d, v2.1d +// CHECK-ERROR ^ + +//---------------------------------------------------------------------- +// Floating Point multiply (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmul s0, s1, v1.h[0] + fmul h0, h1, v1.s[0] + // invalid lane + fmul s2, s29, v10.s[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmul s0, s1, v1.h[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmul h0, h1, v1.s[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmul s2, s29, v10.s[4] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating Point multiply extended (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmulx d0, d1, v1.b[0] + fmulx h0, h1, v1.d[0] + // invalid lane + fmulx d2, d29, v10.d[3] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx d0, d1, v1.b[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmulx h0, h1, v1.d[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmulx d2, d29, v10.d[3] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating Point fused multiply-add (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmla b0, b1, v1.b[0] + fmla d30, s11, v1.d[1] + // invalid lane + fmla s16, s22, v16.s[5] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmla b0, b1, v1.b[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmla d30, s11, v1.d[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: fmla s16, s22, v16.s[5] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Floating Point fused multiply-subtract (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + fmls s29, h10, v28.s[1] + fmls h7, h17, v26.s[2] + // invalid lane + fmls d16, d22, v16.d[-1] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmls s29, h10, v28.s[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fmls h7, h17, v26.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: expected lane number +// CHECK-ERROR: fmls d16, d22, v16.d[-1] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed saturating doubling multiply-add long +// (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + sqdmlal s0, h0, v0.s[0] + sqdmlal s8, s9, v14.s[1] + // invalid lane + sqdmlal s4, s5, v1.s[5] + // invalid vector index + sqdmlal s0, h0, v17.h[0] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal s0, h0, v0.s[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal s8, s9, v14.s[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlal s4, s5, v1.s[5] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlal s0, h0, v17.h[0] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed saturating doubling multiply-subtract long +// (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + sqdmlsl s1, h1, v1.d[0] + sqdmlsl d1, h1, v13.s[0] + // invalid lane + sqdmlsl d1, s1, v13.s[4] + // invalid vector index + sqdmlsl s1, h1, v20.h[7] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl s1, h1, v1.d[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl d1, h1, v13.s[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmlsl d1, s1, v13.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmlsl s1, h1, v20.h[7] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed saturating doubling multiply long (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + // invalid lane + // invalid vector index + // mismatched and invalid vector types + sqdmull s1, h1, v1.s[1] + sqdmull s1, s1, v4.s[0] + // invalid lane + sqdmull s12, h17, v9.h[9] + // invalid vector index + sqdmull s1, h1, v16.h[5] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull s1, h1, v1.s[1] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull s1, s1, v4.s[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmull s12, h17, v9.h[9] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmull s1, h1, v16.h[5] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed saturating doubling multiply returning +// high half (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + sqdmulh h0, s1, v0.h[0] + sqdmulh s25, s26, v27.h[3] + // invalid lane + sqdmulh s25, s26, v27.s[4] + // invalid vector index + sqdmulh s0, h1, v30.h[0] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh h0, s1, v0.h[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh s25, s26, v27.h[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqdmulh s25, s26, v27.s[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqdmulh s0, h1, v30.h[0] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Signed saturating rounding doubling multiply +// returning high half (scalar, by element) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + sqrdmulh h31, h30, v14.s[2] + sqrdmulh s5, h6, v7.s[2] + // invalid lane + sqrdmulh h31, h30, v14.h[9] + // invalid vector index + sqrdmulh h31, h30, v20.h[4] + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh h31, h30, v14.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh s5, h6, v7.s[2] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: sqrdmulh h31, h30, v14.h[9] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: sqrdmulh h31, h30, v20.h[4] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Duplicate element (scalar) +//---------------------------------------------------------------------- + // mismatched and invalid vector types + dup b0, v1.d[0] + dup h0, v31.b[8] + dup s0, v2.h[4] + dup d0, v17.s[3] + // invalid lane + dup d0, v17.d[4] + dup s0, v1.s[7] + dup h0, v31.h[16] + dup b1, v3.b[16] +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: dup b0, v1.d[0] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: dup h0, v31.b[8] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: dup s0, v2.h[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: dup d0, v17.s[3] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: dup d0, v17.d[4] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: dup s0, v1.s[7] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: dup h0, v31.h[16] +// CHECK-ERROR: ^ +// CHECK-ERROR: error: lane number incompatible with layout +// CHECK-ERROR: dup b1, v3.b[16] +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Table look up +//---------------------------------------------------------------------- + + tbl v0.8b, {v1.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b + tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbl v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b +// CHECK-ERROR: ^ + + tbx v0.8b, {v1.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b + tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b, v3.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: tbx v0.8b, {v1.8b, v2.8b, v3.8b, v4.8b}, v2.8b +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid number of vectors +// CHECK-ERROR: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b, v5.16b}, v2.8b +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +// Odd +//---------------------------------------------------------------------- + + fcvtxn s0, s1 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtxn s0, s1 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Away +//---------------------------------------------------------------------- + + fcvtas s0, d0 + fcvtas d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtas d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Away +//---------------------------------------------------------------------- + + fcvtau s0, d0 + fcvtau d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtau d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtms s0, d0 + fcvtms d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtms d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtmu s0, d0 + fcvtmu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtmu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Even +//---------------------------------------------------------------------- + + fcvtns s0, d0 + fcvtns d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtns d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Even +//---------------------------------------------------------------------- + + fcvtnu s0, d0 + fcvtnu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtnu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtps s0, d0 + fcvtps d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtps d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtpu s0, d0 + fcvtpu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtpu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +//---------------------------------------------------------------------- + + fcvtzs s0, d0 + fcvtzs d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzs d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Zero +//---------------------------------------------------------------------- + + fcvtzu s0, d0 + fcvtzu d0, s0 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu s0, d0 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fcvtzu d0, s0 +// CHECK-ERROR: ^ + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Difference +//---------------------------------------------------------------------- + + + fabd s29, d24, s20 + fabd d29, s24, d20 + +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabd s29, d24, s20 +// CHECK-ERROR: ^ +// CHECK-ERROR: error: invalid operand for instruction +// CHECK-ERROR: fabd d29, s24, d20 +// CHECK-ERROR: ^ diff --git a/test/MC/AArch64/neon-extract.s b/test/MC/AArch64/neon-extract.s new file mode 100644 index 000000000000..2d58a75a4907 --- /dev/null +++ b/test/MC/AArch64/neon-extract.s @@ -0,0 +1,13 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions for bitwise extract +//------------------------------------------------------------------------------ + + ext v0.8b, v1.8b, v2.8b, #0x3 + ext v0.16b, v1.16b, v2.16b, #0x3 + +// CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 // encoding: [0x20,0x18,0x02,0x2e] +// CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 // encoding: [0x20,0x18,0x02,0x6e] diff --git a/test/MC/AArch64/neon-facge-facgt.s b/test/MC/AArch64/neon-facge-facgt.s new file mode 100644 index 000000000000..212eda2f2092 --- /dev/null +++ b/test/MC/AArch64/neon-facge-facgt.s @@ -0,0 +1,41 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Absolute Compare Mask Less Than Or Equal (Floating Point) +// FACLE is alias for FACGE with operands reversed +//---------------------------------------------------------------------- + facge v0.2s, v31.2s, v16.2s + facge v4.4s, v7.4s, v15.4s + facge v29.2d, v2.2d, v5.2d + facle v0.2s, v16.2s, v31.2s + facle v4.4s, v15.4s, v7.4s + facle v29.2d, v5.2d, v2.2d + +// CHECK: facge v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xef,0x30,0x2e] +// CHECK: facge v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xec,0x2f,0x6e] +// CHECK: facge v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xec,0x65,0x6e] +// CHECK: facge v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xef,0x30,0x2e] +// CHECK: facge v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xec,0x2f,0x6e] +// CHECK: facge v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xec,0x65,0x6e] + +//---------------------------------------------------------------------- +// Vector Absolute Compare Mask Less Than (Floating Point) +// FACLT is alias for FACGT with operands reversed +//---------------------------------------------------------------------- + facgt v31.4s, v29.4s, v28.4s + facgt v3.2s, v8.2s, v12.2s + facgt v17.2d, v15.2d, v13.2d + faclt v31.4s, v28.4s, v29.4s + faclt v3.2s, v12.2s, v8.2s + faclt v17.2d, v13.2d, v15.2d + +// CHECK: facgt v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xef,0xbc,0x6e] +// CHECK: facgt v3.2s, v8.2s, v12.2s // encoding: [0x03,0xed,0xac,0x2e] +// CHECK: facgt v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xed,0xed,0x6e] +// CHECK: facgt v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xef,0xbc,0x6e] +// CHECK: facgt v3.2s, v8.2s, v12.2s // encoding: [0x03,0xed,0xac,0x2e] +// CHECK: facgt v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xed,0xed,0x6e] + + diff --git a/test/MC/AArch64/neon-frsqrt-frecp.s b/test/MC/AArch64/neon-frsqrt-frecp.s new file mode 100644 index 000000000000..79fe5da5e76f --- /dev/null +++ b/test/MC/AArch64/neon-frsqrt-frecp.s @@ -0,0 +1,27 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Reciprocal Square Root Step (Floating Point) +//---------------------------------------------------------------------- + frsqrts v0.2s, v31.2s, v16.2s + frsqrts v4.4s, v7.4s, v15.4s + frsqrts v29.2d, v2.2d, v5.2d + +// CHECK: frsqrts v0.2s, v31.2s, v16.2s // encoding: [0xe0,0xff,0xb0,0x0e] +// CHECK: frsqrts v4.4s, v7.4s, v15.4s // encoding: [0xe4,0xfc,0xaf,0x4e] +// CHECK: frsqrts v29.2d, v2.2d, v5.2d // encoding: [0x5d,0xfc,0xe5,0x4e] + +//---------------------------------------------------------------------- +// Vector Reciprocal Step (Floating Point) +//---------------------------------------------------------------------- + frecps v31.4s, v29.4s, v28.4s + frecps v3.2s, v8.2s, v12.2s + frecps v17.2d, v15.2d, v13.2d + +// CHECK: frecps v31.4s, v29.4s, v28.4s // encoding: [0xbf,0xff,0x3c,0x4e] +// CHECK: frecps v3.2s, v8.2s, v12.2s // encoding: [0x03,0xfd,0x2c,0x0e] +// CHECK: frecps v17.2d, v15.2d, v13.2d // encoding: [0xf1,0xfd,0x6d,0x4e] + + diff --git a/test/MC/AArch64/neon-halving-add-sub.s b/test/MC/AArch64/neon-halving-add-sub.s new file mode 100644 index 000000000000..555f1b83b4f3 --- /dev/null +++ b/test/MC/AArch64/neon-halving-add-sub.s @@ -0,0 +1,74 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Halving Add (Signed) +//------------------------------------------------------------------------------ + shadd v0.8b, v1.8b, v2.8b + shadd v0.16b, v1.16b, v2.16b + shadd v0.4h, v1.4h, v2.4h + shadd v0.8h, v1.8h, v2.8h + shadd v0.2s, v1.2s, v2.2s + shadd v0.4s, v1.4s, v2.4s + +// CHECK: shadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x04,0x22,0x0e] +// CHECK: shadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x04,0x22,0x4e] +// CHECK: shadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x04,0x62,0x0e] +// CHECK: shadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x04,0x62,0x4e] +// CHECK: shadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x04,0xa2,0x0e] +// CHECK: shadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x04,0xa2,0x4e] + + +//------------------------------------------------------------------------------ +// Vector Integer Halving Add (Unsigned) +//------------------------------------------------------------------------------ + uhadd v0.8b, v1.8b, v2.8b + uhadd v0.16b, v1.16b, v2.16b + uhadd v0.4h, v1.4h, v2.4h + uhadd v0.8h, v1.8h, v2.8h + uhadd v0.2s, v1.2s, v2.2s + uhadd v0.4s, v1.4s, v2.4s + +// CHECK: uhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x04,0x22,0x2e] +// CHECK: uhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x04,0x22,0x6e] +// CHECK: uhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x04,0x62,0x2e] +// CHECK: uhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x04,0x62,0x6e] +// CHECK: uhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x04,0xa2,0x2e] +// CHECK: uhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x04,0xa2,0x6e] + +//------------------------------------------------------------------------------ +// Vector Integer Halving Sub (Signed) +//------------------------------------------------------------------------------ + shsub v0.8b, v1.8b, v2.8b + shsub v0.16b, v1.16b, v2.16b + shsub v0.4h, v1.4h, v2.4h + shsub v0.8h, v1.8h, v2.8h + shsub v0.2s, v1.2s, v2.2s + shsub v0.4s, v1.4s, v2.4s + +// CHECK: shsub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x24,0x22,0x0e] +// CHECK: shsub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x24,0x22,0x4e] +// CHECK: shsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x24,0x62,0x0e] +// CHECK: shsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x24,0x62,0x4e] +// CHECK: shsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x24,0xa2,0x0e] +// CHECK: shsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x24,0xa2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Halving Sub (Unsigned) +//------------------------------------------------------------------------------ + uhsub v0.8b, v1.8b, v2.8b + uhsub v0.16b, v1.16b, v2.16b + uhsub v0.4h, v1.4h, v2.4h + uhsub v0.8h, v1.8h, v2.8h + uhsub v0.2s, v1.2s, v2.2s + uhsub v0.4s, v1.4s, v2.4s + +// CHECK: uhsub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x24,0x22,0x2e] +// CHECK: uhsub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x24,0x22,0x6e] +// CHECK: uhsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x24,0x62,0x2e] +// CHECK: uhsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x24,0x62,0x6e] +// CHECK: uhsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x24,0xa2,0x2e] +// CHECK: uhsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x24,0xa2,0x6e] + diff --git a/test/MC/AArch64/neon-max-min-pairwise.s b/test/MC/AArch64/neon-max-min-pairwise.s new file mode 100644 index 000000000000..8d2dadb1997f --- /dev/null +++ b/test/MC/AArch64/neon-max-min-pairwise.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Maximum Pairwise (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + smaxp v0.8b, v1.8b, v2.8b + smaxp v0.16b, v1.16b, v2.16b + smaxp v0.4h, v1.4h, v2.4h + smaxp v0.8h, v1.8h, v2.8h + smaxp v0.2s, v1.2s, v2.2s + smaxp v0.4s, v1.4s, v2.4s + +// CHECK: smaxp v0.8b, v1.8b, v2.8b // encoding: [0x20,0xa4,0x22,0x0e] +// CHECK: smaxp v0.16b, v1.16b, v2.16b // encoding: [0x20,0xa4,0x22,0x4e] +// CHECK: smaxp v0.4h, v1.4h, v2.4h // encoding: [0x20,0xa4,0x62,0x0e] +// CHECK: smaxp v0.8h, v1.8h, v2.8h // encoding: [0x20,0xa4,0x62,0x4e] +// CHECK: smaxp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xa4,0xa2,0x0e] +// CHECK: smaxp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xa4,0xa2,0x4e] + + umaxp v0.8b, v1.8b, v2.8b + umaxp v0.16b, v1.16b, v2.16b + umaxp v0.4h, v1.4h, v2.4h + umaxp v0.8h, v1.8h, v2.8h + umaxp v0.2s, v1.2s, v2.2s + umaxp v0.4s, v1.4s, v2.4s + +// CHECK: umaxp v0.8b, v1.8b, v2.8b // encoding: [0x20,0xa4,0x22,0x2e] +// CHECK: umaxp v0.16b, v1.16b, v2.16b // encoding: [0x20,0xa4,0x22,0x6e] +// CHECK: umaxp v0.4h, v1.4h, v2.4h // encoding: [0x20,0xa4,0x62,0x2e] +// CHECK: umaxp v0.8h, v1.8h, v2.8h // encoding: [0x20,0xa4,0x62,0x6e] +// CHECK: umaxp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xa4,0xa2,0x2e] +// CHECK: umaxp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xa4,0xa2,0x6e] + +//---------------------------------------------------------------------- +// Vector Minimum Pairwise (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + sminp v0.8b, v1.8b, v2.8b + sminp v0.16b, v1.16b, v2.16b + sminp v0.4h, v1.4h, v2.4h + sminp v0.8h, v1.8h, v2.8h + sminp v0.2s, v1.2s, v2.2s + sminp v0.4s, v1.4s, v2.4s + +// CHECK: sminp v0.8b, v1.8b, v2.8b // encoding: [0x20,0xac,0x22,0x0e] +// CHECK: sminp v0.16b, v1.16b, v2.16b // encoding: [0x20,0xac,0x22,0x4e] +// CHECK: sminp v0.4h, v1.4h, v2.4h // encoding: [0x20,0xac,0x62,0x0e] +// CHECK: sminp v0.8h, v1.8h, v2.8h // encoding: [0x20,0xac,0x62,0x4e] +// CHECK: sminp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xac,0xa2,0x0e] +// CHECK: sminp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xac,0xa2,0x4e] + + uminp v0.8b, v1.8b, v2.8b + uminp v0.16b, v1.16b, v2.16b + uminp v0.4h, v1.4h, v2.4h + uminp v0.8h, v1.8h, v2.8h + uminp v0.2s, v1.2s, v2.2s + uminp v0.4s, v1.4s, v2.4s + +// CHECK: uminp v0.8b, v1.8b, v2.8b // encoding: [0x20,0xac,0x22,0x2e] +// CHECK: uminp v0.16b, v1.16b, v2.16b // encoding: [0x20,0xac,0x22,0x6e] +// CHECK: uminp v0.4h, v1.4h, v2.4h // encoding: [0x20,0xac,0x62,0x2e] +// CHECK: uminp v0.8h, v1.8h, v2.8h // encoding: [0x20,0xac,0x62,0x6e] +// CHECK: uminp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xac,0xa2,0x2e] +// CHECK: uminp v0.4s, v1.4s, v2.4s // encoding: [0x20,0xac,0xa2,0x6e] + +//---------------------------------------------------------------------- +// Vector Maximum Pairwise (Floating Point) +//---------------------------------------------------------------------- + fmaxp v0.2s, v1.2s, v2.2s + fmaxp v31.4s, v15.4s, v16.4s + fmaxp v7.2d, v8.2d, v25.2d + +// CHECK: fmaxp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xf4,0x22,0x2e] +// CHECK: fmaxp v31.4s, v15.4s, v16.4s // encoding: [0xff,0xf5,0x30,0x6e] +// CHECK: fmaxp v7.2d, v8.2d, v25.2d // encoding: [0x07,0xf5,0x79,0x6e] + +//---------------------------------------------------------------------- +// Vector Minimum Pairwise (Floating Point) +//---------------------------------------------------------------------- + fminp v10.2s, v15.2s, v22.2s + fminp v3.4s, v5.4s, v6.4s + fminp v17.2d, v13.2d, v2.2d + +// CHECK: fminp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x2e] +// CHECK: fminp v3.4s, v5.4s, v6.4s // encoding: [0xa3,0xf4,0xa6,0x6e] +// CHECK: fminp v17.2d, v13.2d, v2.2d // encoding: [0xb1,0xf5,0xe2,0x6e] + +//---------------------------------------------------------------------- +// Vector maxNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + fmaxnmp v0.2s, v1.2s, v2.2s + fmaxnmp v31.4s, v15.4s, v16.4s + fmaxnmp v7.2d, v8.2d, v25.2d + +// CHECK: fmaxnmp v0.2s, v1.2s, v2.2s // encoding: [0x20,0xc4,0x22,0x2e] +// CHECK: fmaxnmp v31.4s, v15.4s, v16.4s // encoding: [0xff,0xc5,0x30,0x6e] +// CHECK: fmaxnmp v7.2d, v8.2d, v25.2d // encoding: [0x07,0xc5,0x79,0x6e] + +//---------------------------------------------------------------------- +// Vector minNum Pairwise (Floating Point) +//---------------------------------------------------------------------- + fminnmp v10.2s, v15.2s, v22.2s + fminnmp v3.4s, v5.4s, v6.4s + fminnmp v17.2d, v13.2d, v2.2d + +// CHECK: fminnmp v10.2s, v15.2s, v22.2s // encoding: [0xea,0xc5,0xb6,0x2e] +// CHECK: fminnmp v3.4s, v5.4s, v6.4s // encoding: [0xa3,0xc4,0xa6,0x6e] +// CHECK: fminnmp v17.2d, v13.2d, v2.2d // encoding: [0xb1,0xc5,0xe2,0x6e] + diff --git a/test/MC/AArch64/neon-max-min.s b/test/MC/AArch64/neon-max-min.s new file mode 100644 index 000000000000..6d1efde5077f --- /dev/null +++ b/test/MC/AArch64/neon-max-min.s @@ -0,0 +1,110 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Maximum (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + smax v0.8b, v1.8b, v2.8b + smax v0.16b, v1.16b, v2.16b + smax v0.4h, v1.4h, v2.4h + smax v0.8h, v1.8h, v2.8h + smax v0.2s, v1.2s, v2.2s + smax v0.4s, v1.4s, v2.4s + +// CHECK: smax v0.8b, v1.8b, v2.8b // encoding: [0x20,0x64,0x22,0x0e] +// CHECK: smax v0.16b, v1.16b, v2.16b // encoding: [0x20,0x64,0x22,0x4e] +// CHECK: smax v0.4h, v1.4h, v2.4h // encoding: [0x20,0x64,0x62,0x0e] +// CHECK: smax v0.8h, v1.8h, v2.8h // encoding: [0x20,0x64,0x62,0x4e] +// CHECK: smax v0.2s, v1.2s, v2.2s // encoding: [0x20,0x64,0xa2,0x0e] +// CHECK: smax v0.4s, v1.4s, v2.4s // encoding: [0x20,0x64,0xa2,0x4e] + + umax v0.8b, v1.8b, v2.8b + umax v0.16b, v1.16b, v2.16b + umax v0.4h, v1.4h, v2.4h + umax v0.8h, v1.8h, v2.8h + umax v0.2s, v1.2s, v2.2s + umax v0.4s, v1.4s, v2.4s + +// CHECK: umax v0.8b, v1.8b, v2.8b // encoding: [0x20,0x64,0x22,0x2e] +// CHECK: umax v0.16b, v1.16b, v2.16b // encoding: [0x20,0x64,0x22,0x6e] +// CHECK: umax v0.4h, v1.4h, v2.4h // encoding: [0x20,0x64,0x62,0x2e] +// CHECK: umax v0.8h, v1.8h, v2.8h // encoding: [0x20,0x64,0x62,0x6e] +// CHECK: umax v0.2s, v1.2s, v2.2s // encoding: [0x20,0x64,0xa2,0x2e] +// CHECK: umax v0.4s, v1.4s, v2.4s // encoding: [0x20,0x64,0xa2,0x6e] + +//---------------------------------------------------------------------- +// Vector Minimum (Signed and Unsigned Integer) +//---------------------------------------------------------------------- + smin v0.8b, v1.8b, v2.8b + smin v0.16b, v1.16b, v2.16b + smin v0.4h, v1.4h, v2.4h + smin v0.8h, v1.8h, v2.8h + smin v0.2s, v1.2s, v2.2s + smin v0.4s, v1.4s, v2.4s + +// CHECK: smin v0.8b, v1.8b, v2.8b // encoding: [0x20,0x6c,0x22,0x0e] +// CHECK: smin v0.16b, v1.16b, v2.16b // encoding: [0x20,0x6c,0x22,0x4e] +// CHECK: smin v0.4h, v1.4h, v2.4h // encoding: [0x20,0x6c,0x62,0x0e] +// CHECK: smin v0.8h, v1.8h, v2.8h // encoding: [0x20,0x6c,0x62,0x4e] +// CHECK: smin v0.2s, v1.2s, v2.2s // encoding: [0x20,0x6c,0xa2,0x0e] +// CHECK: smin v0.4s, v1.4s, v2.4s // encoding: [0x20,0x6c,0xa2,0x4e] + + umin v0.8b, v1.8b, v2.8b + umin v0.16b, v1.16b, v2.16b + umin v0.4h, v1.4h, v2.4h + umin v0.8h, v1.8h, v2.8h + umin v0.2s, v1.2s, v2.2s + umin v0.4s, v1.4s, v2.4s + +// CHECK: umin v0.8b, v1.8b, v2.8b // encoding: [0x20,0x6c,0x22,0x2e] +// CHECK: umin v0.16b, v1.16b, v2.16b // encoding: [0x20,0x6c,0x22,0x6e] +// CHECK: umin v0.4h, v1.4h, v2.4h // encoding: [0x20,0x6c,0x62,0x2e] +// CHECK: umin v0.8h, v1.8h, v2.8h // encoding: [0x20,0x6c,0x62,0x6e] +// CHECK: umin v0.2s, v1.2s, v2.2s // encoding: [0x20,0x6c,0xa2,0x2e] +// CHECK: umin v0.4s, v1.4s, v2.4s // encoding: [0x20,0x6c,0xa2,0x6e] + +//---------------------------------------------------------------------- +// Vector Maximum (Floating Point) +//---------------------------------------------------------------------- + fmax v0.2s, v1.2s, v2.2s + fmax v31.4s, v15.4s, v16.4s + fmax v7.2d, v8.2d, v25.2d + +// CHECK: fmax v0.2s, v1.2s, v2.2s // encoding: [0x20,0xf4,0x22,0x0e] +// CHECK: fmax v31.4s, v15.4s, v16.4s // encoding: [0xff,0xf5,0x30,0x4e] +// CHECK: fmax v7.2d, v8.2d, v25.2d // encoding: [0x07,0xf5,0x79,0x4e] + +//---------------------------------------------------------------------- +// Vector Minimum (Floating Point) +//---------------------------------------------------------------------- + fmin v10.2s, v15.2s, v22.2s + fmin v3.4s, v5.4s, v6.4s + fmin v17.2d, v13.2d, v2.2d + +// CHECK: fmin v10.2s, v15.2s, v22.2s // encoding: [0xea,0xf5,0xb6,0x0e] +// CHECK: fmin v3.4s, v5.4s, v6.4s // encoding: [0xa3,0xf4,0xa6,0x4e] +// CHECK: fmin v17.2d, v13.2d, v2.2d // encoding: [0xb1,0xf5,0xe2,0x4e] + +//---------------------------------------------------------------------- +// Vector maxNum (Floating Point) +//---------------------------------------------------------------------- + fmaxnm v0.2s, v1.2s, v2.2s + fmaxnm v31.4s, v15.4s, v16.4s + fmaxnm v7.2d, v8.2d, v25.2d + +// CHECK: fmaxnm v0.2s, v1.2s, v2.2s // encoding: [0x20,0xc4,0x22,0x0e] +// CHECK: fmaxnm v31.4s, v15.4s, v16.4s // encoding: [0xff,0xc5,0x30,0x4e] +// CHECK: fmaxnm v7.2d, v8.2d, v25.2d // encoding: [0x07,0xc5,0x79,0x4e] + +//---------------------------------------------------------------------- +// Vector minNum (Floating Point) +//---------------------------------------------------------------------- + fminnm v10.2s, v15.2s, v22.2s + fminnm v3.4s, v5.4s, v6.4s + fminnm v17.2d, v13.2d, v2.2d + +// CHECK: fminnm v10.2s, v15.2s, v22.2s // encoding: [0xea,0xc5,0xb6,0x0e] +// CHECK: fminnm v3.4s, v5.4s, v6.4s // encoding: [0xa3,0xc4,0xa6,0x4e] +// CHECK: fminnm v17.2d, v13.2d, v2.2d // encoding: [0xb1,0xc5,0xe2,0x4e] + diff --git a/test/MC/AArch64/neon-mla-mls-instructions.s b/test/MC/AArch64/neon-mla-mls-instructions.s new file mode 100644 index 000000000000..3072e6f1200d --- /dev/null +++ b/test/MC/AArch64/neon-mla-mls-instructions.s @@ -0,0 +1,61 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Integer Multiply-accumulate +//---------------------------------------------------------------------- + mla v0.8b, v1.8b, v2.8b + mla v0.16b, v1.16b, v2.16b + mla v0.4h, v1.4h, v2.4h + mla v0.8h, v1.8h, v2.8h + mla v0.2s, v1.2s, v2.2s + mla v0.4s, v1.4s, v2.4s + +// CHECK: mla v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x0e] +// CHECK: mla v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x4e] +// CHECK: mla v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x0e] +// CHECK: mla v0.8h, v1.8h, v2.8h // encoding: [0x20,0x94,0x62,0x4e] +// CHECK: mla v0.2s, v1.2s, v2.2s // encoding: [0x20,0x94,0xa2,0x0e] +// CHECK: mla v0.4s, v1.4s, v2.4s // encoding: [0x20,0x94,0xa2,0x4e] + + +//---------------------------------------------------------------------- +// Vector Integer Multiply-subtract +//---------------------------------------------------------------------- + mls v0.8b, v1.8b, v2.8b + mls v0.16b, v1.16b, v2.16b + mls v0.4h, v1.4h, v2.4h + mls v0.8h, v1.8h, v2.8h + mls v0.2s, v1.2s, v2.2s + mls v0.4s, v1.4s, v2.4s + +// CHECK: mls v0.8b, v1.8b, v2.8b // encoding: [0x20,0x94,0x22,0x2e] +// CHECK: mls v0.16b, v1.16b, v2.16b // encoding: [0x20,0x94,0x22,0x6e] +// CHECK: mls v0.4h, v1.4h, v2.4h // encoding: [0x20,0x94,0x62,0x2e] +// CHECK: mls v0.8h, v1.8h, v2.8h // encoding: [0x20,0x94,0x62,0x6e] +// CHECK: mls v0.2s, v1.2s, v2.2s // encoding: [0x20,0x94,0xa2,0x2e] +// CHECK: mls v0.4s, v1.4s, v2.4s // encoding: [0x20,0x94,0xa2,0x6e] + +//---------------------------------------------------------------------- +// Vector Floating-Point Multiply-accumulate +//---------------------------------------------------------------------- + fmla v0.2s, v1.2s, v2.2s + fmla v0.4s, v1.4s, v2.4s + fmla v0.2d, v1.2d, v2.2d + +// CHECK: fmla v0.2s, v1.2s, v2.2s // encoding: [0x20,0xcc,0x22,0x0e] +// CHECK: fmla v0.4s, v1.4s, v2.4s // encoding: [0x20,0xcc,0x22,0x4e] +// CHECK: fmla v0.2d, v1.2d, v2.2d // encoding: [0x20,0xcc,0x62,0x4e] + +//---------------------------------------------------------------------- +// Vector Floating-Point Multiply-subtract +//---------------------------------------------------------------------- + fmls v0.2s, v1.2s, v2.2s + fmls v0.4s, v1.4s, v2.4s + fmls v0.2d, v1.2d, v2.2d + +// CHECK: fmls v0.2s, v1.2s, v2.2s // encoding: [0x20,0xcc,0xa2,0x0e] +// CHECK: fmls v0.4s, v1.4s, v2.4s // encoding: [0x20,0xcc,0xa2,0x4e] +// CHECK: fmls v0.2d, v1.2d, v2.2d // encoding: [0x20,0xcc,0xe2,0x4e] + diff --git a/test/MC/AArch64/neon-mov.s b/test/MC/AArch64/neon-mov.s new file mode 100644 index 000000000000..c2ca80322001 --- /dev/null +++ b/test/MC/AArch64/neon-mov.s @@ -0,0 +1,209 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//---------------------------------------------------------------------- +// Vector Move Immediate Shifted +//---------------------------------------------------------------------- + movi v0.2s, #1 + movi v1.2s, #0 + movi v15.2s, #1, lsl #8 + movi v16.2s, #1, lsl #16 + movi v31.2s, #1, lsl #24 + movi v0.4s, #1 + movi v0.4s, #1, lsl #8 + movi v0.4s, #1, lsl #16 + movi v0.4s, #1, lsl #24 + movi v0.4h, #1 + movi v0.4h, #1, lsl #8 + movi v0.8h, #1 + movi v0.8h, #1, lsl #8 + +// CHECK: movi v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x0f] +// CHECK: movi v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x0f] +// CHECK: movi v15.2s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f] +// CHECK: movi v16.2s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x0f] +// CHECK: movi v31.2s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f] +// CHECK: movi v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x4f] +// CHECK: movi v0.4s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x4f] +// CHECK: movi v0.4s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x4f] +// CHECK: movi v0.4s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x4f] +// CHECK: movi v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x0f] +// CHECK: movi v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f] +// CHECK: movi v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x4f] +// CHECK: movi v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f] + +//---------------------------------------------------------------------- +// Vector Move Inverted Immediate Shifted +//---------------------------------------------------------------------- + mvni v0.2s, #1 + mvni v1.2s, #0 + mvni v0.2s, #1, lsl #8 + mvni v0.2s, #1, lsl #16 + mvni v0.2s, #1, lsl #24 + mvni v0.4s, #1 + mvni v15.4s, #1, lsl #8 + mvni v16.4s, #1, lsl #16 + mvni v31.4s, #1, lsl #24 + mvni v0.4h, #1 + mvni v0.4h, #1, lsl #8 + mvni v0.8h, #1 + mvni v0.8h, #1, lsl #8 + +// CHECK: mvni v0.2s, #0x1 // encoding: [0x20,0x04,0x00,0x2f] +// CHECK: mvni v1.2s, #0x0 // encoding: [0x01,0x04,0x00,0x2f] +// CHECK: mvni v0.2s, #0x1, lsl #8 // encoding: [0x20,0x24,0x00,0x2f] +// CHECK: mvni v0.2s, #0x1, lsl #16 // encoding: [0x20,0x44,0x00,0x2f] +// CHECK: mvni v0.2s, #0x1, lsl #24 // encoding: [0x20,0x64,0x00,0x2f] +// CHECK: mvni v0.4s, #0x1 // encoding: [0x20,0x04,0x00,0x6f] +// CHECK: mvni v15.4s, #0x1, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f] +// CHECK: mvni v16.4s, #0x1, lsl #16 // encoding: [0x30,0x44,0x00,0x6f] +// CHECK: mvni v31.4s, #0x1, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f] +// CHECK: mvni v0.4h, #0x1 // encoding: [0x20,0x84,0x00,0x2f] +// CHECK: mvni v0.4h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f] +// CHECK: mvni v0.8h, #0x1 // encoding: [0x20,0x84,0x00,0x6f] +// CHECK: mvni v0.8h, #0x1, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f] + +//---------------------------------------------------------------------- +// Vector Bitwise Bit Clear (AND NOT) - immediate +//---------------------------------------------------------------------- + bic v0.2s, #1 + bic v1.2s, #0 + bic v0.2s, #1, lsl #8 + bic v0.2s, #1, lsl #16 + bic v0.2s, #1, lsl #24 + bic v0.4s, #1 + bic v0.4s, #1, lsl #8 + bic v0.4s, #1, lsl #16 + bic v0.4s, #1, lsl #24 + bic v15.4h, #1 + bic v16.4h, #1, lsl #8 + bic v0.8h, #1 + bic v31.8h, #1, lsl #8 + +// CHECK: bic v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x2f] +// CHECK: bic v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x2f] +// CHECK: bic v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x2f] +// CHECK: bic v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x2f] +// CHECK: bic v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x2f] +// CHECK: bic v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x6f] +// CHECK: bic v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x6f] +// CHECK: bic v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x6f] +// CHECK: bic v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x6f] +// CHECK: bic v15.4h, #0x1 // encoding: [0x2f,0x94,0x00,0x2f] +// CHECK: bic v16.4h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f] +// CHECK: bic v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x6f] +// CHECK: bic v31.8h, #0x1, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f] + +//---------------------------------------------------------------------- +// Vector Bitwise OR - immedidate +//---------------------------------------------------------------------- + orr v0.2s, #1 + orr v1.2s, #0 + orr v0.2s, #1, lsl #8 + orr v0.2s, #1, lsl #16 + orr v0.2s, #1, lsl #24 + orr v0.4s, #1 + orr v0.4s, #1, lsl #8 + orr v0.4s, #1, lsl #16 + orr v0.4s, #1, lsl #24 + orr v31.4h, #1 + orr v15.4h, #1, lsl #8 + orr v0.8h, #1 + orr v16.8h, #1, lsl #8 + +// CHECK: orr v0.2s, #0x1 // encoding: [0x20,0x14,0x00,0x0f] +// CHECK: orr v1.2s, #0x0 // encoding: [0x01,0x14,0x00,0x0f] +// CHECK: orr v0.2s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x0f] +// CHECK: orr v0.2s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x0f] +// CHECK: orr v0.2s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x0f] +// CHECK: orr v0.4s, #0x1 // encoding: [0x20,0x14,0x00,0x4f] +// CHECK: orr v0.4s, #0x1, lsl #8 // encoding: [0x20,0x34,0x00,0x4f] +// CHECK: orr v0.4s, #0x1, lsl #16 // encoding: [0x20,0x54,0x00,0x4f] +// CHECK: orr v0.4s, #0x1, lsl #24 // encoding: [0x20,0x74,0x00,0x4f] +// CHECK: orr v31.4h, #0x1 // encoding: [0x3f,0x94,0x00,0x0f] +// CHECK: orr v15.4h, #0x1, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f] +// CHECK: orr v0.8h, #0x1 // encoding: [0x20,0x94,0x00,0x4f] +// CHECK: orr v16.8h, #0x1, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f] + +//---------------------------------------------------------------------- +// Vector Move Immediate Masked +//---------------------------------------------------------------------- + movi v0.2s, #1, msl #8 + movi v1.2s, #1, msl #16 + movi v0.4s, #1, msl #8 + movi v31.4s, #1, msl #16 + +// CHECK: movi v0.2s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x0f] +// CHECK: movi v1.2s, #0x1, msl #16 // encoding: [0x21,0xd4,0x00,0x0f] +// CHECK: movi v0.4s, #0x1, msl #8 // encoding: [0x20,0xc4,0x00,0x4f] +// CHECK: movi v31.4s, #0x1, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f] + +//---------------------------------------------------------------------- +// Vector Move Inverted Immediate Masked +//---------------------------------------------------------------------- + mvni v1.2s, #0x1, msl #8 + mvni v0.2s, #0x1, msl #16 + mvni v31.4s, #0x1, msl #8 + mvni v0.4s, #0x1, msl #16 + +// CHECK: mvni v1.2s, #0x1, msl #8 // encoding: [0x21,0xc4,0x00,0x2f] +// CHECK: mvni v0.2s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x2f] +// CHECK: mvni v31.4s, #0x1, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f] +// CHECK: mvni v0.4s, #0x1, msl #16 // encoding: [0x20,0xd4,0x00,0x6f] + +//---------------------------------------------------------------------- +// Vector Immediate - per byte +//---------------------------------------------------------------------- + movi v0.8b, #0 + movi v31.8b, #0xff + movi v15.16b, #0xf + movi v31.16b, #0x1f + +// CHECK: movi v0.8b, #0x0 // encoding: [0x00,0xe4,0x00,0x0f] +// CHECK: movi v31.8b, #0xff // encoding: [0xff,0xe7,0x07,0x0f] +// CHECK: movi v15.16b, #0xf // encoding: [0xef,0xe5,0x00,0x4f] +// CHECK: movi v31.16b, #0x1f // encoding: [0xff,0xe7,0x00,0x4f] + +//---------------------------------------------------------------------- +// Vector Move Immediate - bytemask, per doubleword +//--------------------------------------------------------------------- + movi v0.2d, #0xff00ff00ff00ff00 + +// CHECK: movi v0.2d, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x6f] + +//---------------------------------------------------------------------- +// Vector Move Immediate - bytemask, one doubleword +//---------------------------------------------------------------------- + movi d0, #0xff00ff00ff00ff00 + +// CHECK: movi d0, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x2f] + +//---------------------------------------------------------------------- +// Vector Floating Point Move Immediate +//---------------------------------------------------------------------- + fmov v1.2s, #1.0 + fmov v15.4s, #1.0 + fmov v31.2d, #1.0 + +// CHECK: fmov v1.2s, #1.00000000 // encoding: [0x01,0xf6,0x03,0x0f] +// CHECK: fmov v15.4s, #1.00000000 // encoding: [0x0f,0xf6,0x03,0x4f] +// CHECK: fmov v31.2d, #1.00000000 // encoding: [0x1f,0xf6,0x03,0x6f] + + +//---------------------------------------------------------------------- +// Vector Move - register +//---------------------------------------------------------------------- + + // FIXME: these should all print with the "mov" syntax. + mov v0.8b, v31.8b + mov v15.16b, v16.16b + orr v0.8b, v31.8b, v31.8b + orr v15.16b, v16.16b, v16.16b + +// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] +// CHECK: orr v0.8b, v31.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e] +// CHECK: orr v15.16b, v16.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e] + diff --git a/test/MC/AArch64/neon-mul-div-instructions.s b/test/MC/AArch64/neon-mul-div-instructions.s new file mode 100644 index 000000000000..1fe6d2b819ce --- /dev/null +++ b/test/MC/AArch64/neon-mul-div-instructions.s @@ -0,0 +1,86 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Vector Integer Mul +//---------------------------------------------------------------------- + mul v0.8b, v1.8b, v2.8b + mul v0.16b, v1.16b, v2.16b + mul v0.4h, v1.4h, v2.4h + mul v0.8h, v1.8h, v2.8h + mul v0.2s, v1.2s, v2.2s + mul v0.4s, v1.4s, v2.4s + +// CHECK: mul v0.8b, v1.8b, v2.8b // encoding: [0x20,0x9c,0x22,0x0e] +// CHECK: mul v0.16b, v1.16b, v2.16b // encoding: [0x20,0x9c,0x22,0x4e] +// CHECK: mul v0.4h, v1.4h, v2.4h // encoding: [0x20,0x9c,0x62,0x0e] +// CHECK: mul v0.8h, v1.8h, v2.8h // encoding: [0x20,0x9c,0x62,0x4e] +// CHECK: mul v0.2s, v1.2s, v2.2s // encoding: [0x20,0x9c,0xa2,0x0e] +// CHECK: mul v0.4s, v1.4s, v2.4s // encoding: [0x20,0x9c,0xa2,0x4e] + + +//---------------------------------------------------------------------- +// Vector Floating-Point Mul +//---------------------------------------------------------------------- + fmul v0.2s, v1.2s, v2.2s + fmul v0.4s, v1.4s, v2.4s + fmul v0.2d, v1.2d, v2.2d + +// CHECK: fmul v0.2s, v1.2s, v2.2s // encoding: [0x20,0xdc,0x22,0x2e] +// CHECK: fmul v0.4s, v1.4s, v2.4s // encoding: [0x20,0xdc,0x22,0x6e] +// CHECK: fmul v0.2d, v1.2d, v2.2d // encoding: [0x20,0xdc,0x62,0x6e] + +//---------------------------------------------------------------------- +// Vector Floating-Point Div +//---------------------------------------------------------------------- + fdiv v0.2s, v1.2s, v2.2s + fdiv v0.4s, v1.4s, v2.4s + fdiv v0.2d, v1.2d, v2.2d + +// CHECK: fdiv v0.2s, v1.2s, v2.2s // encoding: [0x20,0xfc,0x22,0x2e] +// CHECK: fdiv v0.4s, v1.4s, v2.4s // encoding: [0x20,0xfc,0x22,0x6e] +// CHECK: fdiv v0.2d, v1.2d, v2.2d // encoding: [0x20,0xfc,0x62,0x6e] + +//---------------------------------------------------------------------- +// Vector Multiply (Polynomial) +//---------------------------------------------------------------------- + pmul v17.8b, v31.8b, v16.8b + pmul v0.16b, v1.16b, v2.16b + +// CHECK: pmul v17.8b, v31.8b, v16.8b // encoding: [0xf1,0x9f,0x30,0x2e] +// CHECK: pmul v0.16b, v1.16b, v2.16b // encoding: [0x20,0x9c,0x22,0x6e] + +//---------------------------------------------------------------------- +// Vector Saturating Doubling Multiply High +//---------------------------------------------------------------------- + sqdmulh v2.4h, v25.4h, v3.4h + sqdmulh v12.8h, v5.8h, v13.8h + sqdmulh v3.2s, v1.2s, v30.2s + +// CHECK: sqdmulh v2.4h, v25.4h, v3.4h // encoding: [0x22,0xb7,0x63,0x0e] +// CHECK: sqdmulh v12.8h, v5.8h, v13.8h // encoding: [0xac,0xb4,0x6d,0x4e] +// CHECK: sqdmulh v3.2s, v1.2s, v30.2s // encoding: [0x23,0xb4,0xbe,0x0e] + +//---------------------------------------------------------------------- +// Vector Saturating Rouding Doubling Multiply High +//---------------------------------------------------------------------- + sqrdmulh v2.4h, v25.4h, v3.4h + sqrdmulh v12.8h, v5.8h, v13.8h + sqrdmulh v3.2s, v1.2s, v30.2s + +// CHECK: sqrdmulh v2.4h, v25.4h, v3.4h // encoding: [0x22,0xb7,0x63,0x2e] +// CHECK: sqrdmulh v12.8h, v5.8h, v13.8h // encoding: [0xac,0xb4,0x6d,0x6e] +// CHECK: sqrdmulh v3.2s, v1.2s, v30.2s // encoding: [0x23,0xb4,0xbe,0x2e] + +//---------------------------------------------------------------------- +// Vector Multiply Extended +//---------------------------------------------------------------------- + fmulx v21.2s, v5.2s, v13.2s + fmulx v1.4s, v25.4s, v3.4s + fmulx v31.2d, v22.2d, v2.2d + +// CHECK: fmulx v21.2s, v5.2s, v13.2s // encoding: [0xb5,0xdc,0x2d,0x0e] +// CHECK: fmulx v1.4s, v25.4s, v3.4s // encoding: [0x21,0xdf,0x23,0x4e] +// CHECK: fmulx v31.2d, v22.2d, v2.2d // encoding: [0xdf,0xde,0x62,0x4e] + diff --git a/test/MC/AArch64/neon-perm.s b/test/MC/AArch64/neon-perm.s new file mode 100644 index 000000000000..20a4acde37fa --- /dev/null +++ b/test/MC/AArch64/neon-perm.s @@ -0,0 +1,103 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions for permute +//------------------------------------------------------------------------------ + + uzp1 v0.8b, v1.8b, v2.8b + uzp1 v0.16b, v1.16b, v2.16b + uzp1 v0.4h, v1.4h, v2.4h + uzp1 v0.8h, v1.8h, v2.8h + uzp1 v0.2s, v1.2s, v2.2s + uzp1 v0.4s, v1.4s, v2.4s + uzp1 v0.2d, v1.2d, v2.2d + +// CHECK: uzp1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x18,0x02,0x0e] +// CHECK: uzp1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x18,0x02,0x4e] +// CHECK: uzp1 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x18,0x42,0x0e] +// CHECK: uzp1 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x18,0x42,0x4e] +// CHECK: uzp1 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x18,0x82,0x0e] +// CHECK: uzp1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x18,0x82,0x4e] +// CHECK: uzp1 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x18,0xc2,0x4e] + + trn1 v0.8b, v1.8b, v2.8b + trn1 v0.16b, v1.16b, v2.16b + trn1 v0.4h, v1.4h, v2.4h + trn1 v0.8h, v1.8h, v2.8h + trn1 v0.2s, v1.2s, v2.2s + trn1 v0.4s, v1.4s, v2.4s + trn1 v0.2d, v1.2d, v2.2d + +// CHECK: trn1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x28,0x02,0x0e] +// CHECK: trn1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x28,0x02,0x4e] +// CHECK: trn1 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x28,0x42,0x0e] +// CHECK: trn1 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x28,0x42,0x4e] +// CHECK: trn1 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x28,0x82,0x0e] +// CHECK: trn1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x28,0x82,0x4e] +// CHECK: trn1 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x28,0xc2,0x4e] + + zip1 v0.8b, v1.8b, v2.8b + zip1 v0.16b, v1.16b, v2.16b + zip1 v0.4h, v1.4h, v2.4h + zip1 v0.8h, v1.8h, v2.8h + zip1 v0.2s, v1.2s, v2.2s + zip1 v0.4s, v1.4s, v2.4s + zip1 v0.2d, v1.2d, v2.2d + +// CHECK: zip1 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x38,0x02,0x0e] +// CHECK: zip1 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x38,0x02,0x4e] +// CHECK: zip1 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x38,0x42,0x0e] +// CHECK: zip1 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x38,0x42,0x4e] +// CHECK: zip1 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x38,0x82,0x0e] +// CHECK: zip1 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x38,0x82,0x4e] +// CHECK: zip1 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x38,0xc2,0x4e] + + uzp2 v0.8b, v1.8b, v2.8b + uzp2 v0.16b, v1.16b, v2.16b + uzp2 v0.4h, v1.4h, v2.4h + uzp2 v0.8h, v1.8h, v2.8h + uzp2 v0.2s, v1.2s, v2.2s + uzp2 v0.4s, v1.4s, v2.4s + uzp2 v0.2d, v1.2d, v2.2d + +// CHECK: uzp2 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x58,0x02,0x0e] +// CHECK: uzp2 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x58,0x02,0x4e] +// CHECK: uzp2 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x58,0x42,0x0e] +// CHECK: uzp2 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x58,0x42,0x4e] +// CHECK: uzp2 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x58,0x82,0x0e] +// CHECK: uzp2 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x58,0x82,0x4e] +// CHECK: uzp2 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x58,0xc2,0x4e] + + trn2 v0.8b, v1.8b, v2.8b + trn2 v0.16b, v1.16b, v2.16b + trn2 v0.4h, v1.4h, v2.4h + trn2 v0.8h, v1.8h, v2.8h + trn2 v0.2s, v1.2s, v2.2s + trn2 v0.4s, v1.4s, v2.4s + trn2 v0.2d, v1.2d, v2.2d + +// CHECK: trn2 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x68,0x02,0x0e] +// CHECK: trn2 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x68,0x02,0x4e] +// CHECK: trn2 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x68,0x42,0x0e] +// CHECK: trn2 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x68,0x42,0x4e] +// CHECK: trn2 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x68,0x82,0x0e] +// CHECK: trn2 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x68,0x82,0x4e] +// CHECK: trn2 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x68,0xc2,0x4e] + + zip2 v0.8b, v1.8b, v2.8b + zip2 v0.16b, v1.16b, v2.16b + zip2 v0.4h, v1.4h, v2.4h + zip2 v0.8h, v1.8h, v2.8h + zip2 v0.2s, v1.2s, v2.2s + zip2 v0.4s, v1.4s, v2.4s + zip2 v0.2d, v1.2d, v2.2d + +// CHECK: zip2 v0.8b, v1.8b, v2.8b // encoding: [0x20,0x78,0x02,0x0e] +// CHECK: zip2 v0.16b, v1.16b, v2.16b // encoding: [0x20,0x78,0x02,0x4e] +// CHECK: zip2 v0.4h, v1.4h, v2.4h // encoding: [0x20,0x78,0x42,0x0e] +// CHECK: zip2 v0.8h, v1.8h, v2.8h // encoding: [0x20,0x78,0x42,0x4e] +// CHECK: zip2 v0.2s, v1.2s, v2.2s // encoding: [0x20,0x78,0x82,0x0e] +// CHECK: zip2 v0.4s, v1.4s, v2.4s // encoding: [0x20,0x78,0x82,0x4e] +// CHECK: zip2 v0.2d, v1.2d, v2.2d // encoding: [0x20,0x78,0xc2,0x4e] diff --git a/test/MC/AArch64/neon-rounding-halving-add.s b/test/MC/AArch64/neon-rounding-halving-add.s new file mode 100644 index 000000000000..47ac21268020 --- /dev/null +++ b/test/MC/AArch64/neon-rounding-halving-add.s @@ -0,0 +1,39 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Rouding Halving Add (Signed) +//------------------------------------------------------------------------------ + srhadd v0.8b, v1.8b, v2.8b + srhadd v0.16b, v1.16b, v2.16b + srhadd v0.4h, v1.4h, v2.4h + srhadd v0.8h, v1.8h, v2.8h + srhadd v0.2s, v1.2s, v2.2s + srhadd v0.4s, v1.4s, v2.4s + +// CHECK: srhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x0e] +// CHECK: srhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x4e] +// CHECK: srhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x0e] +// CHECK: srhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x4e] +// CHECK: srhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x0e] +// CHECK: srhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Rouding Halving Add (Unsigned) +//------------------------------------------------------------------------------ + urhadd v0.8b, v1.8b, v2.8b + urhadd v0.16b, v1.16b, v2.16b + urhadd v0.4h, v1.4h, v2.4h + urhadd v0.8h, v1.8h, v2.8h + urhadd v0.2s, v1.2s, v2.2s + urhadd v0.4s, v1.4s, v2.4s + +// CHECK: urhadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x14,0x22,0x2e] +// CHECK: urhadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x14,0x22,0x6e] +// CHECK: urhadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x14,0x62,0x2e] +// CHECK: urhadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x14,0x62,0x6e] +// CHECK: urhadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x14,0xa2,0x2e] +// CHECK: urhadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x14,0xa2,0x6e] + diff --git a/test/MC/AArch64/neon-rounding-shift.s b/test/MC/AArch64/neon-rounding-shift.s new file mode 100644 index 000000000000..e70f766f2b62 --- /dev/null +++ b/test/MC/AArch64/neon-rounding-shift.s @@ -0,0 +1,45 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Rounding Shift Lef (Signed) +//------------------------------------------------------------------------------ + srshl v0.8b, v1.8b, v2.8b + srshl v0.16b, v1.16b, v2.16b + srshl v0.4h, v1.4h, v2.4h + srshl v0.8h, v1.8h, v2.8h + srshl v0.2s, v1.2s, v2.2s + srshl v0.4s, v1.4s, v2.4s + srshl v0.2d, v1.2d, v2.2d + +// CHECK: srshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x0e] +// CHECK: srshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x4e] +// CHECK: srshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x0e] +// CHECK: srshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x54,0x62,0x4e] +// CHECK: srshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x54,0xa2,0x0e] +// CHECK: srshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x54,0xa2,0x4e] +// CHECK: srshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x54,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Rounding Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + urshl v0.8b, v1.8b, v2.8b + urshl v0.16b, v1.16b, v2.16b + urshl v0.4h, v1.4h, v2.4h + urshl v0.8h, v1.8h, v2.8h + urshl v0.2s, v1.2s, v2.2s + urshl v0.4s, v1.4s, v2.4s + urshl v0.2d, v1.2d, v2.2d + +// CHECK: urshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x54,0x22,0x2e] +// CHECK: urshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x54,0x22,0x6e] +// CHECK: urshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x54,0x62,0x2e] +// CHECK: urshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x54,0x62,0x6e] +// CHECK: urshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x54,0xa2,0x2e] +// CHECK: urshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x54,0xa2,0x6e] +// CHECK: urshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x54,0xe2,0x6e] + + + diff --git a/test/MC/AArch64/neon-saturating-add-sub.s b/test/MC/AArch64/neon-saturating-add-sub.s new file mode 100644 index 000000000000..4a7ed1094262 --- /dev/null +++ b/test/MC/AArch64/neon-saturating-add-sub.s @@ -0,0 +1,82 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Add (Signed) +//------------------------------------------------------------------------------ + sqadd v0.8b, v1.8b, v2.8b + sqadd v0.16b, v1.16b, v2.16b + sqadd v0.4h, v1.4h, v2.4h + sqadd v0.8h, v1.8h, v2.8h + sqadd v0.2s, v1.2s, v2.2s + sqadd v0.4s, v1.4s, v2.4s + sqadd v0.2d, v1.2d, v2.2d + +// CHECK: sqadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x0c,0x22,0x0e] +// CHECK: sqadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x0c,0x22,0x4e] +// CHECK: sqadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x0c,0x62,0x0e] +// CHECK: sqadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x0c,0x62,0x4e] +// CHECK: sqadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x0c,0xa2,0x0e] +// CHECK: sqadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x0c,0xa2,0x4e] +// CHECK: sqadd v0.2d, v1.2d, v2.2d // encoding: [0x20,0x0c,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Add (Unsigned) +//------------------------------------------------------------------------------ + uqadd v0.8b, v1.8b, v2.8b + uqadd v0.16b, v1.16b, v2.16b + uqadd v0.4h, v1.4h, v2.4h + uqadd v0.8h, v1.8h, v2.8h + uqadd v0.2s, v1.2s, v2.2s + uqadd v0.4s, v1.4s, v2.4s + uqadd v0.2d, v1.2d, v2.2d + +// CHECK: uqadd v0.8b, v1.8b, v2.8b // encoding: [0x20,0x0c,0x22,0x2e] +// CHECK: uqadd v0.16b, v1.16b, v2.16b // encoding: [0x20,0x0c,0x22,0x6e] +// CHECK: uqadd v0.4h, v1.4h, v2.4h // encoding: [0x20,0x0c,0x62,0x2e] +// CHECK: uqadd v0.8h, v1.8h, v2.8h // encoding: [0x20,0x0c,0x62,0x6e] +// CHECK: uqadd v0.2s, v1.2s, v2.2s // encoding: [0x20,0x0c,0xa2,0x2e] +// CHECK: uqadd v0.4s, v1.4s, v2.4s // encoding: [0x20,0x0c,0xa2,0x6e] +// CHECK: uqadd v0.2d, v1.2d, v2.2d // encoding: [0x20,0x0c,0xe2,0x6e] + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Sub (Signed) +//------------------------------------------------------------------------------ + sqsub v0.8b, v1.8b, v2.8b + sqsub v0.16b, v1.16b, v2.16b + sqsub v0.4h, v1.4h, v2.4h + sqsub v0.8h, v1.8h, v2.8h + sqsub v0.2s, v1.2s, v2.2s + sqsub v0.4s, v1.4s, v2.4s + sqsub v0.2d, v1.2d, v2.2d + +// CHECK: sqsub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x2c,0x22,0x0e] +// CHECK: sqsub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x2c,0x22,0x4e] +// CHECK: sqsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x2c,0x62,0x0e] +// CHECK: sqsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x2c,0x62,0x4e] +// CHECK: sqsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x2c,0xa2,0x0e] +// CHECK: sqsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x2c,0xa2,0x4e] +// CHECK: sqsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0x2c,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Sub (Unsigned) +//------------------------------------------------------------------------------ + uqsub v0.8b, v1.8b, v2.8b + uqsub v0.16b, v1.16b, v2.16b + uqsub v0.4h, v1.4h, v2.4h + uqsub v0.8h, v1.8h, v2.8h + uqsub v0.2s, v1.2s, v2.2s + uqsub v0.4s, v1.4s, v2.4s + uqsub v0.2d, v1.2d, v2.2d + +// CHECK: uqsub v0.8b, v1.8b, v2.8b // encoding: [0x20,0x2c,0x22,0x2e] +// CHECK: uqsub v0.16b, v1.16b, v2.16b // encoding: [0x20,0x2c,0x22,0x6e] +// CHECK: uqsub v0.4h, v1.4h, v2.4h // encoding: [0x20,0x2c,0x62,0x2e] +// CHECK: uqsub v0.8h, v1.8h, v2.8h // encoding: [0x20,0x2c,0x62,0x6e] +// CHECK: uqsub v0.2s, v1.2s, v2.2s // encoding: [0x20,0x2c,0xa2,0x2e] +// CHECK: uqsub v0.4s, v1.4s, v2.4s // encoding: [0x20,0x2c,0xa2,0x6e] +// CHECK: uqsub v0.2d, v1.2d, v2.2d // encoding: [0x20,0x2c,0xe2,0x6e] + + diff --git a/test/MC/AArch64/neon-saturating-rounding-shift.s b/test/MC/AArch64/neon-saturating-rounding-shift.s new file mode 100644 index 000000000000..9215c1cabefd --- /dev/null +++ b/test/MC/AArch64/neon-saturating-rounding-shift.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Rounding Shift Lef (Signed) +//------------------------------------------------------------------------------ + sqrshl v0.8b, v1.8b, v2.8b + sqrshl v0.16b, v1.16b, v2.16b + sqrshl v0.4h, v1.4h, v2.4h + sqrshl v0.8h, v1.8h, v2.8h + sqrshl v0.2s, v1.2s, v2.2s + sqrshl v0.4s, v1.4s, v2.4s + sqrshl v0.2d, v1.2d, v2.2d + +// CHECK: sqrshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x5c,0x22,0x0e] +// CHECK: sqrshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x5c,0x22,0x4e] +// CHECK: sqrshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x5c,0x62,0x0e] +// CHECK: sqrshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x5c,0x62,0x4e] +// CHECK: sqrshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x5c,0xa2,0x0e] +// CHECK: sqrshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x5c,0xa2,0x4e] +// CHECK: sqrshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x5c,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Rounding Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + uqrshl v0.8b, v1.8b, v2.8b + uqrshl v0.16b, v1.16b, v2.16b + uqrshl v0.4h, v1.4h, v2.4h + uqrshl v0.8h, v1.8h, v2.8h + uqrshl v0.2s, v1.2s, v2.2s + uqrshl v0.4s, v1.4s, v2.4s + uqrshl v0.2d, v1.2d, v2.2d + +// CHECK: uqrshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x5c,0x22,0x2e] +// CHECK: uqrshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x5c,0x22,0x6e] +// CHECK: uqrshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x5c,0x62,0x2e] +// CHECK: uqrshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x5c,0x62,0x6e] +// CHECK: uqrshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x5c,0xa2,0x2e] +// CHECK: uqrshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x5c,0xa2,0x6e] +// CHECK: uqrshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x5c,0xe2,0x6e] + diff --git a/test/MC/AArch64/neon-saturating-shift.s b/test/MC/AArch64/neon-saturating-shift.s new file mode 100644 index 000000000000..9ae393a040b6 --- /dev/null +++ b/test/MC/AArch64/neon-saturating-shift.s @@ -0,0 +1,43 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Shift Lef (Signed) +//------------------------------------------------------------------------------ + sqshl v0.8b, v1.8b, v2.8b + sqshl v0.16b, v1.16b, v2.16b + sqshl v0.4h, v1.4h, v2.4h + sqshl v0.8h, v1.8h, v2.8h + sqshl v0.2s, v1.2s, v2.2s + sqshl v0.4s, v1.4s, v2.4s + sqshl v0.2d, v1.2d, v2.2d + +// CHECK: sqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x0e] +// CHECK: sqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x4e] +// CHECK: sqshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x4c,0x62,0x0e] +// CHECK: sqshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x4c,0x62,0x4e] +// CHECK: sqshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x4c,0xa2,0x0e] +// CHECK: sqshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x4c,0xa2,0x4e] +// CHECK: sqshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x4c,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Saturating Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + uqshl v0.8b, v1.8b, v2.8b + uqshl v0.16b, v1.16b, v2.16b + uqshl v0.4h, v1.4h, v2.4h + uqshl v0.8h, v1.8h, v2.8h + uqshl v0.2s, v1.2s, v2.2s + uqshl v0.4s, v1.4s, v2.4s + uqshl v0.2d, v1.2d, v2.2d + +// CHECK: uqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x2e] +// CHECK: uqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x6e] +// CHECK: uqshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x4c,0x62,0x2e] +// CHECK: uqshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x4c,0x62,0x6e] +// CHECK: uqshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x4c,0xa2,0x2e] +// CHECK: uqshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x4c,0xa2,0x6e] +// CHECK: uqshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x4c,0xe2,0x6e] + diff --git a/test/MC/AArch64/neon-scalar-abs.s b/test/MC/AArch64/neon-scalar-abs.s new file mode 100644 index 000000000000..d08756c0c10c --- /dev/null +++ b/test/MC/AArch64/neon-scalar-abs.s @@ -0,0 +1,35 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Absolute Value +//---------------------------------------------------------------------- + + abs d29, d24 + +// CHECK: abs d29, d24 // encoding: [0x1d,0xbb,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Difference +//---------------------------------------------------------------------- + + fabd s29, s24, s20 + fabd d29, d24, d20 + +// CHECK: fabd s29, s24, s20 // encoding: [0x1d,0xd7,0xb4,0x7e] +// CHECK: fabd d29, d24, d20 // encoding: [0x1d,0xd7,0xf4,0x7e] + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Absolute Value +//---------------------------------------------------------------------- + + sqabs b19, b14 + sqabs h21, h15 + sqabs s20, s12 + sqabs d18, d12 + +// CHECK: sqabs b19, b14 // encoding: [0xd3,0x79,0x20,0x5e] +// CHECK: sqabs h21, h15 // encoding: [0xf5,0x79,0x60,0x5e] +// CHECK: sqabs s20, s12 // encoding: [0x94,0x79,0xa0,0x5e] +// CHECK: sqabs d18, d12 // encoding: [0x92,0x79,0xe0,0x5e] diff --git a/test/MC/AArch64/neon-scalar-add-sub.s b/test/MC/AArch64/neon-scalar-add-sub.s new file mode 100644 index 000000000000..0a3eba732122 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-add-sub.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Scalar Integer Add +//------------------------------------------------------------------------------ + add d31, d0, d16 + +// CHECK: add d31, d0, d16 // encoding: [0x1f,0x84,0xf0,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Sub +//------------------------------------------------------------------------------ + sub d1, d7, d8 + +// CHECK: sub d1, d7, d8 // encoding: [0xe1,0x84,0xe8,0x7e] + diff --git a/test/MC/AArch64/neon-scalar-by-elem-mla.s b/test/MC/AArch64/neon-scalar-by-elem-mla.s new file mode 100644 index 000000000000..fec9d12d8b8d --- /dev/null +++ b/test/MC/AArch64/neon-scalar-by-elem-mla.s @@ -0,0 +1,44 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Floating Point fused multiply-add (scalar, by element) +//------------------------------------------------------------------------------ + fmla s0, s1, v1.s[0] + fmla s30, s11, v1.s[1] + fmla s4, s5, v7.s[2] + fmla s16, s22, v16.s[3] + fmla d0, d1, v1.d[0] + fmla d30, d11, v1.d[1] + +// CHECK: fmla s0, s1, v1.s[0] // encoding: [0x20,0x10,0x81,0x5f] +// CHECK: fmla s30, s11, v1.s[1] // encoding: [0x7e,0x11,0xa1,0x5f] +// CHECK: fmla s4, s5, v7.s[2] // encoding: [0xa4,0x18,0x87,0x5f] +// CHECK: fmla s16, s22, v16.s[3] // encoding: [0xd0,0x1a,0xb0,0x5f] +// CHECK: fmla d0, d1, v1.d[0] // encoding: [0x20,0x10,0xc1,0x5f] +// CHECK: fmla d30, d11, v1.d[1] // encoding: [0x7e,0x19,0xc1,0x5f] + +//------------------------------------------------------------------------------ +// Floating Point fused multiply-subtract (scalar, by element) +//------------------------------------------------------------------------------ + + fmls s2, s3, v4.s[0] + fmls s29, s10, v28.s[1] + fmls s5, s12, v23.s[2] + fmls s7, s17, v26.s[3] + fmls d0, d1, v1.d[0] + fmls d30, d11, v1.d[1] + +// CHECK: fmls s2, s3, v4.s[0] // encoding: [0x62,0x50,0x84,0x5f] +// CHECK: fmls s29, s10, v28.s[1] // encoding: [0x5d,0x51,0xbc,0x5f] +// CHECK: fmls s5, s12, v23.s[2] // encoding: [0x85,0x59,0x97,0x5f] +// CHECK: fmls s7, s17, v26.s[3] // encoding: [0x27,0x5a,0xba,0x5f] +// CHECK: fmls d0, d1, v1.d[0] // encoding: [0x20,0x50,0xc1,0x5f] +// CHECK: fmls d30, d11, v1.d[1] // encoding: [0x7e,0x59,0xc1,0x5f] + + + + + + + + diff --git a/test/MC/AArch64/neon-scalar-by-elem-mul.s b/test/MC/AArch64/neon-scalar-by-elem-mul.s new file mode 100644 index 000000000000..8b8a3f57a9ca --- /dev/null +++ b/test/MC/AArch64/neon-scalar-by-elem-mul.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Floating Point multiply (scalar, by element) +//------------------------------------------------------------------------------ + fmul s0, s1, v1.s[0] + fmul s30, s11, v1.s[1] + fmul s4, s5, v7.s[2] + fmul s16, s22, v16.s[3] + fmul d0, d1, v1.d[0] + fmul d30, d11, v1.d[1] + +// CHECK: fmul s0, s1, v1.s[0] // encoding: [0x20,0x90,0x81,0x5f] +// CHECK: fmul s30, s11, v1.s[1] // encoding: [0x7e,0x91,0xa1,0x5f] +// CHECK: fmul s4, s5, v7.s[2] // encoding: [0xa4,0x98,0x87,0x5f] +// CHECK: fmul s16, s22, v16.s[3] // encoding: [0xd0,0x9a,0xb0,0x5f] +// CHECK: fmul d0, d1, v1.d[0] // encoding: [0x20,0x90,0xc1,0x5f] +// CHECK: fmul d30, d11, v1.d[1] // encoding: [0x7e,0x99,0xc1,0x5f] + + +//------------------------------------------------------------------------------ +// Floating Point multiply extended (scalar, by element) +//------------------------------------------------------------------------------ + fmulx s6, s2, v8.s[0] + fmulx s7, s3, v13.s[1] + fmulx s9, s7, v9.s[2] + fmulx s13, s21, v10.s[3] + fmulx d15, d9, v7.d[0] + fmulx d13, d12, v11.d[1] + +// CHECK: fmulx s6, s2, v8.s[0] // encoding: [0x46,0x90,0x88,0x7f] +// CHECK: fmulx s7, s3, v13.s[1] // encoding: [0x67,0x90,0xad,0x7f] +// CHECK: fmulx s9, s7, v9.s[2] // encoding: [0xe9,0x98,0x89,0x7f] +// CHECK: fmulx s13, s21, v10.s[3] // encoding: [0xad,0x9a,0xaa,0x7f] +// CHECK: fmulx d15, d9, v7.d[0] // encoding: [0x2f,0x91,0xc7,0x7f] +// CHECK: fmulx d13, d12, v11.d[1] // encoding: [0x8d,0x99,0xcb,0x7f] + diff --git a/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s b/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s new file mode 100644 index 000000000000..e3d7e0514f9f --- /dev/null +++ b/test/MC/AArch64/neon-scalar-by-elem-saturating-mla.s @@ -0,0 +1,46 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//----------------------------------------------------------------------------- +// Signed saturating doubling multiply-add long (scalar, by element) +//----------------------------------------------------------------------------- + sqdmlal s0, h0, v0.h[0] + sqdmlal s7, h1, v4.h[3] + sqdmlal s11, h16, v8.h[4] + sqdmlal s30, h30, v15.h[7] + sqdmlal d0, s0, v3.s[0] + sqdmlal d30, s30, v30.s[3] + sqdmlal d8, s9, v14.s[1] + +// CHECK: sqdmlal s0, h0, v0.h[0] // encoding: [0x00,0x30,0x40,0x5f] +// CHECK: sqdmlal s7, h1, v4.h[3] // encoding: [0x27,0x30,0x74,0x5f] +// CHECK: sqdmlal s11, h16, v8.h[4] // encoding: [0x0b,0x3a,0x48,0x5f] +// CHECK: sqdmlal s30, h30, v15.h[7] // encoding: [0xde,0x3b,0x7f,0x5f] +// CHECK: sqdmlal d0, s0, v3.s[0] // encoding: [0x00,0x30,0x83,0x5f] +// CHECK: sqdmlal d30, s30, v30.s[3] // encoding: [0xde,0x3b,0xbe,0x5f] +// CHECK: sqdmlal d8, s9, v14.s[1] // encoding: [0x28,0x31,0xae,0x5f] + +//----------------------------------------------------------------------------- +// Signed saturating doubling multiply-subtract long (scalar, by element) +//----------------------------------------------------------------------------- + sqdmlsl s1, h1, v1.h[0] + sqdmlsl s8, h2, v5.h[1] + sqdmlsl s12, h13, v14.h[2] + sqdmlsl s29, h28, v11.h[7] + sqdmlsl d1, s1, v13.s[0] + sqdmlsl d31, s31, v31.s[2] + sqdmlsl d16, s18, v28.s[3] + +// CHECK: sqdmlsl s1, h1, v1.h[0] // encoding: [0x21,0x70,0x41,0x5f] +// CHECK: sqdmlsl s8, h2, v5.h[1] // encoding: [0x48,0x70,0x55,0x5f] +// CHECK: sqdmlsl s12, h13, v14.h[2] // encoding: [0xac,0x71,0x6e,0x5f] +// CHECK: sqdmlsl s29, h28, v11.h[7] // encoding: [0x9d,0x7b,0x7b,0x5f] +// CHECK: sqdmlsl d1, s1, v13.s[0] // encoding: [0x21,0x70,0x8d,0x5f] +// CHECK: sqdmlsl d31, s31, v31.s[2] // encoding: [0xff,0x7b,0x9f,0x5f] +// CHECK: sqdmlsl d16, s18, v28.s[3] // encoding: [0x50,0x7a,0xbc,0x5f] + + + + + + + diff --git a/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s b/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s new file mode 100644 index 000000000000..8a8405ef282e --- /dev/null +++ b/test/MC/AArch64/neon-scalar-by-elem-saturating-mul.s @@ -0,0 +1,58 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//----------------------------------------------------------------------------- +// Signed saturating doubling multiply long (scalar, by element) +//----------------------------------------------------------------------------- + sqdmull s1, h1, v1.h[1] + sqdmull s8, h2, v5.h[2] + sqdmull s12, h17, v9.h[3] + sqdmull s31, h31, v15.h[7] + sqdmull d1, s1, v4.s[0] + sqdmull d31, s31, v31.s[3] + sqdmull d9, s10, v15.s[0] + + +// CHECK: sqdmull s1, h1, v1.h[1] // encoding: [0x21,0xb0,0x51,0x5f] +// CHECK: sqdmull s8, h2, v5.h[2] // encoding: [0x48,0xb0,0x65,0x5f] +// CHECK: sqdmull s12, h17, v9.h[3] // encoding: [0x2c,0xb2,0x79,0x5f] +// CHECK: sqdmull s31, h31, v15.h[7] // encoding: [0xff,0xbb,0x7f,0x5f] +// CHECK: sqdmull d1, s1, v4.s[0] // encoding: [0x21,0xb0,0x84,0x5f] +// CHECK: sqdmull d31, s31, v31.s[3] // encoding: [0xff,0xbb,0xbf,0x5f] +// CHECK: sqdmull d9, s10, v15.s[0] // encoding: [0x49,0xb1,0x8f,0x5f] + +//----------------------------------------------------------------------------- +// Scalar Signed saturating doubling multiply returning +// high half (scalar, by element) +//----------------------------------------------------------------------------- + sqdmulh h0, h1, v0.h[0] + sqdmulh h10, h11, v10.h[4] + sqdmulh h20, h21, v15.h[7] + sqdmulh s25, s26, v27.s[3] + sqdmulh s2, s6, v7.s[0] + +// CHECK: sqdmulh h0, h1, v0.h[0] // encoding: [0x20,0xc0,0x40,0x5f] +// CHECK: sqdmulh h10, h11, v10.h[4] // encoding: [0x6a,0xc9,0x4a,0x5f] +// CHECK: sqdmulh h20, h21, v15.h[7] // encoding: [0xb4,0xca,0x7f,0x5f] +// CHECK: sqdmulh s25, s26, v27.s[3] // encoding: [0x59,0xcb,0xbb,0x5f] +// CHECK: sqdmulh s2, s6, v7.s[0] // encoding: [0xc2,0xc0,0x87,0x5f] + +//----------------------------------------------------------------------------- +// Signed saturating rounding doubling multiply returning +// high half (scalar, by element) +//----------------------------------------------------------------------------- + sqrdmulh h31, h30, v14.h[2] + sqrdmulh h1, h1, v1.h[4] + sqrdmulh h21, h22, v15.h[7] + sqrdmulh s5, s6, v7.s[2] + sqrdmulh s20, s26, v27.s[1] + +// CHECK: sqrdmulh h31, h30, v14.h[2] // encoding: [0xdf,0xd3,0x6e,0x5f] +// CHECK: sqrdmulh h1, h1, v1.h[4] // encoding: [0x21,0xd8,0x41,0x5f] +// CHECK: sqrdmulh h21, h22, v15.h[7] // encoding: [0xd5,0xda,0x7f,0x5f] +// CHECK: sqrdmulh s5, s6, v7.s[2] // encoding: [0xc5,0xd8,0x87,0x5f] +// CHECK: sqrdmulh s20, s26, v27.s[1] // encoding: [0x54,0xd3,0xbb,0x5f] + + + + + diff --git a/test/MC/AArch64/neon-scalar-compare.s b/test/MC/AArch64/neon-scalar-compare.s new file mode 100644 index 000000000000..55ade0efc258 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-compare.s @@ -0,0 +1,90 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Equal +//---------------------------------------------------------------------- + + cmeq d20, d21, d22 + +// CHECK: cmeq d20, d21, d22 // encoding: [0xb4,0x8e,0xf6,0x7e] + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Equal To Zero +//---------------------------------------------------------------------- + + cmeq d20, d21, #0x0 + +// CHECK: cmeq d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Compare Unsigned Higher Or Same +//---------------------------------------------------------------------- + + cmhs d20, d21, d22 + +// CHECK: cmhs d20, d21, d22 // encoding: [0xb4,0x3e,0xf6,0x7e] + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greather Than Or Equal +//---------------------------------------------------------------------- + + cmge d20, d21, d22 + +// CHECK: cmge d20, d21, d22 // encoding: [0xb4,0x3e,0xf6,0x5e] + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greather Than Or Equal To Zero +//---------------------------------------------------------------------- + + cmge d20, d21, #0x0 + +// CHECK: cmge d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x7e] + +//---------------------------------------------------------------------- +// Scalar Compare Unsigned Higher +//---------------------------------------------------------------------- + + cmhi d20, d21, d22 + +// CHECK: cmhi d20, d21, d22 // encoding: [0xb4,0x36,0xf6,0x7e] +//---------------------------------------------------------------------- +// Scalar Compare Signed Greater Than +//---------------------------------------------------------------------- + + cmgt d20, d21, d22 + +// CHECK: cmgt d20, d21, d22 // encoding: [0xb4,0x36,0xf6,0x5e] + +//---------------------------------------------------------------------- +// Scalar Compare Signed Greater Than Zero +//---------------------------------------------------------------------- + + cmgt d20, d21, #0x0 + +// CHECK: cmgt d20, d21, #0x0 // encoding: [0xb4,0x8a,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Compare Signed Less Than Or Equal To Zero +//---------------------------------------------------------------------- + + cmle d20, d21, #0x0 + +// CHECK: cmle d20, d21, #0x0 // encoding: [0xb4,0x9a,0xe0,0x7e] + +//---------------------------------------------------------------------- +// Scalar Compare Less Than Zero +//---------------------------------------------------------------------- + + cmlt d20, d21, #0x0 + +// CHECK: cmlt d20, d21, #0x0 // encoding: [0xb4,0xaa,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Compare Bitwise Test Bits +//---------------------------------------------------------------------- + + cmtst d20, d21, d22 + +// CHECK: cmtst d20, d21, d22 // encoding: [0xb4,0x8e,0xf6,0x5e] diff --git a/test/MC/AArch64/neon-scalar-cvt.s b/test/MC/AArch64/neon-scalar-cvt.s new file mode 100644 index 000000000000..97416daf0801 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-cvt.s @@ -0,0 +1,181 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Signed Integer Convert To Floating-point +//---------------------------------------------------------------------- + + scvtf s22, s13 + scvtf d21, d12 + +// CHECK: scvtf s22, s13 // encoding: [0xb6,0xd9,0x21,0x5e] +// CHECK: scvtf d21, d12 // encoding: [0x95,0xd9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Unsigned Integer Convert To Floating-point +//---------------------------------------------------------------------- + + ucvtf s22, s13 + ucvtf d21, d14 + +// CHECK: ucvtf s22, s13 // encoding: [0xb6,0xd9,0x21,0x7e] +// CHECK: ucvtf d21, d14 // encoding: [0xd5,0xd9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Signed Fixed-point Convert To Floating-Point (Immediate) +//---------------------------------------------------------------------- + + scvtf s22, s13, #32 + scvtf d21, d12, #64 + +// CHECK: scvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x5f] +// CHECK: scvtf d21, d12, #64 // encoding: [0x95,0xe5,0x40,0x5f] + +//---------------------------------------------------------------------- +// Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate) +//---------------------------------------------------------------------- + + ucvtf s22, s13, #32 + ucvtf d21, d14, #64 + +// CHECK: ucvtf s22, s13, #32 // encoding: [0xb6,0xe5,0x20,0x7f] +// CHECK: ucvtf d21, d14, #64 // encoding: [0xd5,0xe5,0x40,0x7f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzs s21, s12, #1 + fcvtzs d21, d12, #1 + +// CHECK: fcvtzs s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x5f] +// CHECK: fcvtzs d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x5f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +//---------------------------------------------------------------------- + + fcvtzu s21, s12, #1 + fcvtzu d21, d12, #1 + +// CHECK: fcvtzu s21, s12, #1 // encoding: [0x95,0xfd,0x3f,0x7f] +// CHECK: fcvtzu d21, d12, #1 // encoding: [0x95,0xfd,0x7f,0x7f] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +// Odd +//---------------------------------------------------------------------- + + fcvtxn s22, d13 + +// CHECK: fcvtxn s22, d13 // encoding: [0xb6,0x69,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Away +//---------------------------------------------------------------------- + + fcvtas s12, s13 + fcvtas d21, d14 + +// CHECK: fcvtas s12, s13 // encoding: [0xac,0xc9,0x21,0x5e] +// CHECK: fcvtas d21, d14 // encoding: [0xd5,0xc9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Away +//---------------------------------------------------------------------- + + fcvtau s12, s13 + fcvtau d21, d14 + +// CHECK: fcvtau s12, s13 // encoding: [0xac,0xc9,0x21,0x7e] +// CHECK: fcvtau d21, d14 // encoding: [0xd5,0xc9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtms s22, s13 + fcvtms d21, d14 + +// CHECK: fcvtms s22, s13 // encoding: [0xb6,0xb9,0x21,0x5e] +// CHECK: fcvtms d21, d14 // encoding: [0xd5,0xb9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Minus Infinity +//---------------------------------------------------------------------- + + fcvtmu s12, s13 + fcvtmu d21, d14 + +// CHECK: fcvtmu s12, s13 // encoding: [0xac,0xb9,0x21,0x7e] +// CHECK: fcvtmu d21, d14 // encoding: [0xd5,0xb9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +// With Ties To Even +//---------------------------------------------------------------------- + + fcvtns s22, s13 + fcvtns d21, d14 + +// CHECK: fcvtns s22, s13 // encoding: [0xb6,0xa9,0x21,0x5e] +// CHECK: fcvtns d21, d14 // encoding: [0xd5,0xa9,0x61,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding To +// Nearest With Ties To Even +//---------------------------------------------------------------------- + + fcvtnu s12, s13 + fcvtnu d21, d14 + +// CHECK: fcvtnu s12, s13 // encoding: [0xac,0xa9,0x21,0x7e] +// CHECK: fcvtnu d21, d14 // encoding: [0xd5,0xa9,0x61,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtps s22, s13 + fcvtps d21, d14 + +// CHECK: fcvtps s22, s13 // encoding: [0xb6,0xa9,0xa1,0x5e] +// CHECK: fcvtps d21, d14 // encoding: [0xd5,0xa9,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Positive Infinity +//---------------------------------------------------------------------- + + fcvtpu s12, s13 + fcvtpu d21, d14 + +// CHECK: fcvtpu s12, s13 // encoding: [0xac,0xa9,0xa1,0x7e] +// CHECK: fcvtpu d21, d14 // encoding: [0xd5,0xa9,0xe1,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +//---------------------------------------------------------------------- + + fcvtzs s12, s13 + fcvtzs d21, d14 + +// CHECK: fcvtzs s12, s13 // encoding: [0xac,0xb9,0xa1,0x5e] +// CHECK: fcvtzs d21, d14 // encoding: [0xd5,0xb9,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +// Zero +//---------------------------------------------------------------------- + + fcvtzu s12, s13 + fcvtzu d21, d14 + +// CHECK: fcvtzu s12, s13 // encoding: [0xac,0xb9,0xa1,0x7e] +// CHECK: fcvtzu d21, d14 // encoding: [0xd5,0xb9,0xe1,0x7e] diff --git a/test/MC/AArch64/neon-scalar-dup.s b/test/MC/AArch64/neon-scalar-dup.s new file mode 100644 index 000000000000..77c638df0952 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-dup.s @@ -0,0 +1,55 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Duplicate element (scalar) +//------------------------------------------------------------------------------ + dup b0, v0.b[15] + dup b1, v0.b[7] + dup b17, v0.b[0] + dup h5, v31.h[7] + dup h9, v1.h[4] + dup h11, v17.h[0] + dup s2, v2.s[3] + dup s4, v21.s[0] + dup s31, v21.s[2] + dup d3, v5.d[0] + dup d6, v5.d[1] + +// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] + +//------------------------------------------------------------------------------ +// Aliases for Duplicate element (scalar) +//------------------------------------------------------------------------------ + mov b0, v0.b[15] + mov b1, v0.b[7] + mov b17, v0.b[0] + mov h5, v31.h[7] + mov h9, v1.h[4] + mov h11, v17.h[0] + mov s2, v2.s[3] + mov s4, v21.s[0] + mov s31, v21.s[2] + mov d3, v5.d[0] + mov d6, v5.d[1] + +// CHECK: dup b0, v0.b[15] // encoding: [0x00,0x04,0x1f,0x5e] +// CHECK: dup b1, v0.b[7] // encoding: [0x01,0x04,0x0f,0x5e] +// CHECK: dup b17, v0.b[0] // encoding: [0x11,0x04,0x01,0x5e] +// CHECK: dup h5, v31.h[7] // encoding: [0xe5,0x07,0x1e,0x5e] +// CHECK: dup h9, v1.h[4] // encoding: [0x29,0x04,0x12,0x5e] +// CHECK: dup h11, v17.h[0] // encoding: [0x2b,0x06,0x02,0x5e] +// CHECK: dup s2, v2.s[3] // encoding: [0x42,0x04,0x1c,0x5e] +// CHECK: dup s4, v21.s[0] // encoding: [0xa4,0x06,0x04,0x5e] +// CHECK: dup s31, v21.s[2] // encoding: [0xbf,0x06,0x14,0x5e] +// CHECK: dup d3, v5.d[0] // encoding: [0xa3,0x04,0x08,0x5e] +// CHECK: dup d6, v5.d[1] // encoding: [0xa6,0x04,0x18,0x5e] diff --git a/test/MC/AArch64/neon-scalar-extract-narrow.s b/test/MC/AArch64/neon-scalar-extract-narrow.s new file mode 100644 index 000000000000..e25224e386f0 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-extract-narrow.s @@ -0,0 +1,40 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Extract Unsigned Narrow +//---------------------------------------------------------------------- + + sqxtun b19, h14 + sqxtun h21, s15 + sqxtun s20, d12 + +// CHECK: sqxtun b19, h14 // encoding: [0xd3,0x29,0x21,0x7e] +// CHECK: sqxtun h21, s15 // encoding: [0xf5,0x29,0x61,0x7e] +// CHECK: sqxtun s20, d12 // encoding: [0x94,0x29,0xa1,0x7e] + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Extract Signed Narrow +//---------------------------------------------------------------------- + + sqxtn b18, h18 + sqxtn h20, s17 + sqxtn s19, d14 + +// CHECK: sqxtn b18, h18 // encoding: [0x52,0x4a,0x21,0x5e] +// CHECK: sqxtn h20, s17 // encoding: [0x34,0x4a,0x61,0x5e] +// CHECK: sqxtn s19, d14 // encoding: [0xd3,0x49,0xa1,0x5e] + + +//---------------------------------------------------------------------- +// Scalar Unsigned Saturating Extract Narrow +//---------------------------------------------------------------------- + + uqxtn b18, h18 + uqxtn h20, s17 + uqxtn s19, d14 + +// CHECK: uqxtn b18, h18 // encoding: [0x52,0x4a,0x21,0x7e] +// CHECK: uqxtn h20, s17 // encoding: [0x34,0x4a,0x61,0x7e] +// CHECK: uqxtn s19, d14 // encoding: [0xd3,0x49,0xa1,0x7e] diff --git a/test/MC/AArch64/neon-scalar-fp-compare.s b/test/MC/AArch64/neon-scalar-fp-compare.s new file mode 100644 index 000000000000..a59ec0d1d6ed --- /dev/null +++ b/test/MC/AArch64/neon-scalar-fp-compare.s @@ -0,0 +1,103 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Equal +//---------------------------------------------------------------------- + + fcmeq s10, s11, s12 + fcmeq d20, d21, d22 + +// CHECK: fcmeq s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x5e] +// CHECK: fcmeq d20, d21, d22 // encoding: [0xb4,0xe6,0x76,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Equal To Zero +//---------------------------------------------------------------------- + + fcmeq s10, s11, #0.0 + fcmeq d20, d21, #0.0 + +// CHECK: fcmeq s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x5e] +// CHECK: fcmeq d20, d21, #0.0 // encoding: [0xb4,0xda,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greater Than Or Equal +//---------------------------------------------------------------------- + + fcmge s10, s11, s12 + fcmge d20, d21, d22 + +// CHECK: fcmge s10, s11, s12 // encoding: [0x6a,0xe5,0x2c,0x7e] +// CHECK: fcmge d20, d21, d22 // encoding: [0xb4,0xe6,0x76,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greater Than Or Equal To Zero +//---------------------------------------------------------------------- + + fcmge s10, s11, #0.0 + fcmge d20, d21, #0.0 + +// CHECK: fcmge s10, s11, #0.0 // encoding: [0x6a,0xc9,0xa0,0x7e] +// CHECK: fcmge d20, d21, #0.0 // encoding: [0xb4,0xca,0xe0,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greather Than +//---------------------------------------------------------------------- + + fcmgt s10, s11, s12 + fcmgt d20, d21, d22 + +// CHECK: fcmgt s10, s11, s12 // encoding: [0x6a,0xe5,0xac,0x7e] +// CHECK: fcmgt d20, d21, d22 // encoding: [0xb4,0xe6,0xf6,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Greather Than Zero +//---------------------------------------------------------------------- + + fcmgt s10, s11, #0.0 + fcmgt d20, d21, #0.0 + +// CHECK: fcmgt s10, s11, #0.0 // encoding: [0x6a,0xc9,0xa0,0x5e] +// CHECK: fcmgt d20, d21, #0.0 // encoding: [0xb4,0xca,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Less Than Or Equal To Zero +//---------------------------------------------------------------------- + + fcmle s10, s11, #0.0 + fcmle d20, d21, #0.0 + +// CHECK: fcmle s10, s11, #0.0 // encoding: [0x6a,0xd9,0xa0,0x7e] +// CHECK: fcmle d20, d21, #0.0 // encoding: [0xb4,0xda,0xe0,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Compare Mask Less Than +//---------------------------------------------------------------------- + + fcmlt s10, s11, #0.0 + fcmlt d20, d21, #0.0 + +// CHECK: fcmlt s10, s11, #0.0 // encoding: [0x6a,0xe9,0xa0,0x5e] +// CHECK: fcmlt d20, d21, #0.0 // encoding: [0xb4,0xea,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal +//---------------------------------------------------------------------- + + facge s10, s11, s12 + facge d20, d21, d22 + +// CHECK: facge s10, s11, s12 // encoding: [0x6a,0xed,0x2c,0x7e] +// CHECK: facge d20, d21, d22 // encoding: [0xb4,0xee,0x76,0x7e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Absolute Compare Mask Greater Than +//---------------------------------------------------------------------- + + facgt s10, s11, s12 + facgt d20, d21, d22 + +// CHECK: facgt s10, s11, s12 // encoding: [0x6a,0xed,0xac,0x7e] +// CHECK: facgt d20, d21, d22 // encoding: [0xb4,0xee,0xf6,0x7e] diff --git a/test/MC/AArch64/neon-scalar-mul.s b/test/MC/AArch64/neon-scalar-mul.s new file mode 100644 index 000000000000..e33bdad91a94 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-mul.s @@ -0,0 +1,63 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Doubling Multiply Half High +//---------------------------------------------------------------------- + + sqdmulh h10, h11, h12 + sqdmulh s20, s21, s2 + +// CHECK: sqdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x5e] +// CHECK: sqdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x5e] + +//---------------------------------------------------------------------- +// Scalar Integer Saturating Rounding Doubling Multiply Half High +//---------------------------------------------------------------------- + + sqrdmulh h10, h11, h12 + sqrdmulh s20, s21, s2 + +// CHECK: sqrdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x7e] +// CHECK: sqrdmulh s20, s21, s2 // encoding: [0xb4,0xb6,0xa2,0x7e] + +//---------------------------------------------------------------------- +// Floating-point Multiply Extended +//---------------------------------------------------------------------- + + fmulx s20, s22, s15 + fmulx d23, d11, d1 + +// CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e] +// CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Add Long +//---------------------------------------------------------------------- + + sqdmlal s17, h27, h12 + sqdmlal d19, s24, s12 + +// CHECK: sqdmlal s17, h27, h12 // encoding: [0x71,0x93,0x6c,0x5e] +// CHECK: sqdmlal d19, s24, s12 // encoding: [0x13,0x93,0xac,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply-Subtract Long +//---------------------------------------------------------------------- + + sqdmlsl s14, h12, h25 + sqdmlsl d12, s23, s13 + +// CHECK: sqdmlsl s14, h12, h25 // encoding: [0x8e,0xb1,0x79,0x5e] +// CHECK: sqdmlsl d12, s23, s13 // encoding: [0xec,0xb2,0xad,0x5e] + +//---------------------------------------------------------------------- +// Signed Saturating Doubling Multiply Long +//---------------------------------------------------------------------- + + sqdmull s12, h22, h12 + sqdmull d15, s22, s12 + +// CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e] +// CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e] diff --git a/test/MC/AArch64/neon-scalar-neg.s b/test/MC/AArch64/neon-scalar-neg.s new file mode 100644 index 000000000000..8e5d61dd2459 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-neg.s @@ -0,0 +1,25 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Negate +//---------------------------------------------------------------------- + + neg d29, d24 + +// CHECK: neg d29, d24 // encoding: [0x1d,0xbb,0xe0,0x7e] + +//---------------------------------------------------------------------- +// Scalar Signed Saturating Negate +//---------------------------------------------------------------------- + + sqneg b19, b14 + sqneg h21, h15 + sqneg s20, s12 + sqneg d18, d12 + +// CHECK: sqneg b19, b14 // encoding: [0xd3,0x79,0x20,0x7e] +// CHECK: sqneg h21, h15 // encoding: [0xf5,0x79,0x60,0x7e] +// CHECK: sqneg s20, s12 // encoding: [0x94,0x79,0xa0,0x7e] +// CHECK: sqneg d18, d12 // encoding: [0x92,0x79,0xe0,0x7e] diff --git a/test/MC/AArch64/neon-scalar-recip.s b/test/MC/AArch64/neon-scalar-recip.s new file mode 100644 index 000000000000..7a886f3b4a73 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-recip.s @@ -0,0 +1,53 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Floating-point Reciprocal Step +//---------------------------------------------------------------------- + + frecps s21, s16, s13 + frecps d22, d30, d21 + +// CHECK: frecps s21, s16, s13 // encoding: [0x15,0xfe,0x2d,0x5e] +// CHECK: frecps d22, d30, d21 // encoding: [0xd6,0xff,0x75,0x5e] + +//---------------------------------------------------------------------- +// Floating-point Reciprocal Square Root Step +//---------------------------------------------------------------------- + + frsqrts s21, s5, s12 + frsqrts d8, d22, d18 + +// CHECK: frsqrts s21, s5, s12 // encoding: [0xb5,0xfc,0xac,0x5e] +// CHECK: frsqrts d8, d22, d18 // encoding: [0xc8,0xfe,0xf2,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Estimate +//---------------------------------------------------------------------- + + frecpe s19, s14 + frecpe d13, d13 + +// CHECK: frecpe s19, s14 // encoding: [0xd3,0xd9,0xa1,0x5e] +// CHECK: frecpe d13, d13 // encoding: [0xad,0xd9,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Exponent +//---------------------------------------------------------------------- + + frecpx s18, s10 + frecpx d16, d19 + +// CHECK: frecpx s18, s10 // encoding: [0x52,0xf9,0xa1,0x5e] +// CHECK: frecpx d16, d19 // encoding: [0x70,0xfa,0xe1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Floating-point Reciprocal Square Root Estimate +//---------------------------------------------------------------------- + + frsqrte s22, s13 + frsqrte d21, d12 + +// CHECK: frsqrte s22, s13 // encoding: [0xb6,0xd9,0xa1,0x7e] +// CHECK: frsqrte d21, d12 // encoding: [0x95,0xd9,0xe1,0x7e] diff --git a/test/MC/AArch64/neon-scalar-reduce-pairwise.s b/test/MC/AArch64/neon-scalar-reduce-pairwise.s new file mode 100644 index 000000000000..403a940ec2f2 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-reduce-pairwise.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//---------------------------------------------------------------------- +// Scalar Reduce Add Pairwise (Integer) +//---------------------------------------------------------------------- + addp d0, v1.2d + +// CHECK: addp d0, v1.2d // encoding: [0x20,0xb8,0xf1,0x5e] + +//---------------------------------------------------------------------- +// Scalar Reduce Add Pairwise (Floating Point) +//---------------------------------------------------------------------- + faddp d20, v1.2d + +// CHECK: faddp d20, v1.2d // encoding: [0x34,0xd8,0x70,0x7e] + diff --git a/test/MC/AArch64/neon-scalar-rounding-shift.s b/test/MC/AArch64/neon-scalar-rounding-shift.s new file mode 100644 index 000000000000..6113e09af388 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-rounding-shift.s @@ -0,0 +1,17 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + + +//------------------------------------------------------------------------------ +// Scalar Integer Rounding Shift Lef (Signed) +//------------------------------------------------------------------------------ + srshl d17, d31, d8 + +// CHECK: srshl d17, d31, d8 // encoding: [0xf1,0x57,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Rounding Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + urshl d17, d31, d8 + +// CHECK: urshl d17, d31, d8 // encoding: [0xf1,0x57,0xe8,0x7e] + diff --git a/test/MC/AArch64/neon-scalar-saturating-add-sub.s b/test/MC/AArch64/neon-scalar-saturating-add-sub.s new file mode 100644 index 000000000000..0bf243495999 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-saturating-add-sub.s @@ -0,0 +1,81 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Add (Signed) +//------------------------------------------------------------------------------ + sqadd b0, b1, b2 + sqadd h10, h11, h12 + sqadd s20, s21, s2 + sqadd d17, d31, d8 + +// CHECK: sqadd b0, b1, b2 // encoding: [0x20,0x0c,0x22,0x5e] +// CHECK: sqadd h10, h11, h12 // encoding: [0x6a,0x0d,0x6c,0x5e] +// CHECK: sqadd s20, s21, s2 // encoding: [0xb4,0x0e,0xa2,0x5e] +// CHECK: sqadd d17, d31, d8 // encoding: [0xf1,0x0f,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Add (Unsigned) +//------------------------------------------------------------------------------ + uqadd b0, b1, b2 + uqadd h10, h11, h12 + uqadd s20, s21, s2 + uqadd d17, d31, d8 + +// CHECK: uqadd b0, b1, b2 // encoding: [0x20,0x0c,0x22,0x7e] +// CHECK: uqadd h10, h11, h12 // encoding: [0x6a,0x0d,0x6c,0x7e] +// CHECK: uqadd s20, s21, s2 // encoding: [0xb4,0x0e,0xa2,0x7e] +// CHECK: uqadd d17, d31, d8 // encoding: [0xf1,0x0f,0xe8,0x7e] + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Sub (Signed) +//------------------------------------------------------------------------------ + sqsub b0, b1, b2 + sqsub h10, h11, h12 + sqsub s20, s21, s2 + sqsub d17, d31, d8 + +// CHECK: sqsub b0, b1, b2 // encoding: [0x20,0x2c,0x22,0x5e] +// CHECK: sqsub h10, h11, h12 // encoding: [0x6a,0x2d,0x6c,0x5e] +// CHECK: sqsub s20, s21, s2 // encoding: [0xb4,0x2e,0xa2,0x5e] +// CHECK: sqsub d17, d31, d8 // encoding: [0xf1,0x2f,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Sub (Unsigned) +//------------------------------------------------------------------------------ + uqsub b0, b1, b2 + uqsub h10, h11, h12 + uqsub s20, s21, s2 + uqsub d17, d31, d8 + +// CHECK: uqsub b0, b1, b2 // encoding: [0x20,0x2c,0x22,0x7e] +// CHECK: uqsub h10, h11, h12 // encoding: [0x6a,0x2d,0x6c,0x7e] +// CHECK: uqsub s20, s21, s2 // encoding: [0xb4,0x2e,0xa2,0x7e] +// CHECK: uqsub d17, d31, d8 // encoding: [0xf1,0x2f,0xe8,0x7e] + +//---------------------------------------------------------------------- +// Signed Saturating Accumulated of Unsigned Value +//---------------------------------------------------------------------- + + suqadd b19, b14 + suqadd h20, h15 + suqadd s21, s12 + suqadd d18, d22 + +// CHECK: suqadd b19, b14 // encoding: [0xd3,0x39,0x20,0x5e] +// CHECK: suqadd h20, h15 // encoding: [0xf4,0x39,0x60,0x5e] +// CHECK: suqadd s21, s12 // encoding: [0x95,0x39,0xa0,0x5e] +// CHECK: suqadd d18, d22 // encoding: [0xd2,0x3a,0xe0,0x5e] + +//---------------------------------------------------------------------- +// Unsigned Saturating Accumulated of Signed Value +//---------------------------------------------------------------------- + + usqadd b19, b14 + usqadd h20, h15 + usqadd s21, s12 + usqadd d18, d22 + +// CHECK: usqadd b19, b14 // encoding: [0xd3,0x39,0x20,0x7e] +// CHECK: usqadd h20, h15 // encoding: [0xf4,0x39,0x60,0x7e] +// CHECK: usqadd s21, s12 // encoding: [0x95,0x39,0xa0,0x7e] +// CHECK: usqadd d18, d22 // encoding: [0xd2,0x3a,0xe0,0x7e] diff --git a/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s b/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s new file mode 100644 index 000000000000..b09a58923445 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-saturating-rounding-shift.s @@ -0,0 +1,28 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Rounding Shift Lef (Signed) +//------------------------------------------------------------------------------ + sqrshl b0, b1, b2 + sqrshl h10, h11, h12 + sqrshl s20, s21, s2 + sqrshl d17, d31, d8 + +// CHECK: sqrshl b0, b1, b2 // encoding: [0x20,0x5c,0x22,0x5e] +// CHECK: sqrshl h10, h11, h12 // encoding: [0x6a,0x5d,0x6c,0x5e] +// CHECK: sqrshl s20, s21, s2 // encoding: [0xb4,0x5e,0xa2,0x5e] +// CHECK: sqrshl d17, d31, d8 // encoding: [0xf1,0x5f,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Rounding Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + uqrshl b0, b1, b2 + uqrshl h10, h11, h12 + uqrshl s20, s21, s2 + uqrshl d17, d31, d8 + +// CHECK: uqrshl b0, b1, b2 // encoding: [0x20,0x5c,0x22,0x7e] +// CHECK: uqrshl h10, h11, h12 // encoding: [0x6a,0x5d,0x6c,0x7e] +// CHECK: uqrshl s20, s21, s2 // encoding: [0xb4,0x5e,0xa2,0x7e] +// CHECK: uqrshl d17, d31, d8 // encoding: [0xf1,0x5f,0xe8,0x7e] + diff --git a/test/MC/AArch64/neon-scalar-saturating-shift.s b/test/MC/AArch64/neon-scalar-saturating-shift.s new file mode 100644 index 000000000000..b53c9f072f35 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-saturating-shift.s @@ -0,0 +1,29 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Shift Lef (Signed) +//------------------------------------------------------------------------------ + sqshl b0, b1, b2 + sqshl h10, h11, h12 + sqshl s20, s21, s2 + sqshl d17, d31, d8 + +// CHECK: sqshl b0, b1, b2 // encoding: [0x20,0x4c,0x22,0x5e] +// CHECK: sqshl h10, h11, h12 // encoding: [0x6a,0x4d,0x6c,0x5e] +// CHECK: sqshl s20, s21, s2 // encoding: [0xb4,0x4e,0xa2,0x5e] +// CHECK: sqshl d17, d31, d8 // encoding: [0xf1,0x4f,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Saturating Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + uqshl b0, b1, b2 + uqshl h10, h11, h12 + uqshl s20, s21, s2 + uqshl d17, d31, d8 + +// CHECK: uqshl b0, b1, b2 // encoding: [0x20,0x4c,0x22,0x7e] +// CHECK: uqshl h10, h11, h12 // encoding: [0x6a,0x4d,0x6c,0x7e] +// CHECK: uqshl s20, s21, s2 // encoding: [0xb4,0x4e,0xa2,0x7e] +// CHECK: uqshl d17, d31, d8 // encoding: [0xf1,0x4f,0xe8,0x7e] + + diff --git a/test/MC/AArch64/neon-scalar-shift-imm.s b/test/MC/AArch64/neon-scalar-shift-imm.s new file mode 100644 index 000000000000..96cb815eafa8 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-shift-imm.s @@ -0,0 +1,186 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//---------------------------------------------------------------------- +// Scalar Signed Shift Right (Immediate) +//---------------------------------------------------------------------- + sshr d15, d16, #12 + +// CHECK: sshr d15, d16, #12 // encoding: [0x0f,0x06,0x74,0x5f] + +//---------------------------------------------------------------------- +// Scalar Unsigned Shift Right (Immediate) +//---------------------------------------------------------------------- + ushr d10, d17, #18 + +// CHECK: ushr d10, d17, #18 // encoding: [0x2a,0x06,0x6e,0x7f] + +//---------------------------------------------------------------------- +// Scalar Signed Rounding Shift Right (Immediate) +//---------------------------------------------------------------------- + srshr d19, d18, #7 + +// CHECK: srshr d19, d18, #7 // encoding: [0x53,0x26,0x79,0x5f] + +//---------------------------------------------------------------------- +// Scalar Unigned Rounding Shift Right (Immediate) +//---------------------------------------------------------------------- + urshr d20, d23, #31 + +// CHECK: urshr d20, d23, #31 // encoding: [0xf4,0x26,0x61,0x7f] + +//---------------------------------------------------------------------- +// Scalar Signed Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + ssra d18, d12, #21 + +// CHECK: ssra d18, d12, #21 // encoding: [0x92,0x15,0x6b,0x5f] + +//---------------------------------------------------------------------- +// Scalar Unsigned Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + usra d20, d13, #61 + +// CHECK: usra d20, d13, #61 // encoding: [0xb4,0x15,0x43,0x7f] + +//---------------------------------------------------------------------- +// Scalar Signed Rounding Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + srsra d15, d11, #19 + +// CHECK: srsra d15, d11, #19 // encoding: [0x6f,0x35,0x6d,0x5f] + +//---------------------------------------------------------------------- +// Scalar Unsigned Rounding Shift Right and Accumulate (Immediate) +//---------------------------------------------------------------------- + ursra d18, d10, #13 + +// CHECK: ursra d18, d10, #13 // encoding: [0x52,0x35,0x73,0x7f] + +//---------------------------------------------------------------------- +// Scalar Shift Left (Immediate) +//---------------------------------------------------------------------- + shl d7, d10, #12 + +// CHECK: shl d7, d10, #12 // encoding: [0x47,0x55,0x4c,0x5f] + +//---------------------------------------------------------------------- +// Signed Saturating Shift Left (Immediate) +//---------------------------------------------------------------------- + sqshl b11, b19, #7 + sqshl h13, h18, #11 + sqshl s14, s17, #22 + sqshl d15, d16, #51 + +// CHECK: sqshl b11, b19, #7 // encoding: [0x6b,0x76,0x0f,0x5f] +// CHECK: sqshl h13, h18, #11 // encoding: [0x4d,0x76,0x1b,0x5f] +// CHECK: sqshl s14, s17, #22 // encoding: [0x2e,0x76,0x36,0x5f] +// CHECK: sqshl d15, d16, #51 // encoding: [0x0f,0x76,0x73,0x5f] + +//---------------------------------------------------------------------- +// Unsigned Saturating Shift Left (Immediate) +//---------------------------------------------------------------------- + uqshl b18, b15, #6 + uqshl h11, h18, #7 + uqshl s14, s19, #18 + uqshl d15, d12, #19 + +// CHECK: uqshl b18, b15, #6 // encoding: [0xf2,0x75,0x0e,0x7f] +// CHECK: uqshl h11, h18, #7 // encoding: [0x4b,0x76,0x17,0x7f] +// CHECK: uqshl s14, s19, #18 // encoding: [0x6e,0x76,0x32,0x7f] +// CHECK: uqshl d15, d12, #19 // encoding: [0x8f,0x75,0x53,0x7f] + +//---------------------------------------------------------------------- +// Signed Saturating Shift Left Unsigned (Immediate) +//---------------------------------------------------------------------- + sqshlu b15, b18, #6 + sqshlu h19, h17, #6 + sqshlu s16, s14, #25 + sqshlu d11, d13, #32 + +// CHECK: sqshlu b15, b18, #6 // encoding: [0x4f,0x66,0x0e,0x7f] +// CHECK: sqshlu h19, h17, #6 // encoding: [0x33,0x66,0x16,0x7f] +// CHECK: sqshlu s16, s14, #25 // encoding: [0xd0,0x65,0x39,0x7f] +// CHECK: sqshlu d11, d13, #32 // encoding: [0xab,0x65,0x60,0x7f] + +//---------------------------------------------------------------------- +// Shift Right And Insert (Immediate) +//---------------------------------------------------------------------- + sri d10, d12, #14 + +// CHECK: sri d10, d12, #14 // encoding: [0x8a,0x45,0x72,0x7f] + +//---------------------------------------------------------------------- +// Shift Left And Insert (Immediate) +//---------------------------------------------------------------------- + sli d10, d14, #12 + +// CHECK: sli d10, d14, #12 // encoding: [0xca,0x55,0x4c,0x7f] + +//---------------------------------------------------------------------- +// Signed Saturating Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + sqshrn b10, h15, #5 + sqshrn h17, s10, #4 + sqshrn s18, d10, #31 + +// CHECK: sqshrn b10, h15, #5 // encoding: [0xea,0x95,0x0b,0x5f] +// CHECK: sqshrn h17, s10, #4 // encoding: [0x51,0x95,0x1c,0x5f] +// CHECK: sqshrn s18, d10, #31 // encoding: [0x52,0x95,0x21,0x5f] + +//---------------------------------------------------------------------- +// Unsigned Saturating Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + uqshrn b12, h10, #7 + uqshrn h10, s14, #5 + uqshrn s10, d12, #13 + +// CHECK: uqshrn b12, h10, #7 // encoding: [0x4c,0x95,0x09,0x7f] +// CHECK: uqshrn h10, s14, #5 // encoding: [0xca,0x95,0x1b,0x7f] +// CHECK: uqshrn s10, d12, #13 // encoding: [0x8a,0x95,0x33,0x7f] + +//---------------------------------------------------------------------- +// Signed Saturating Rounded Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + sqrshrn b10, h13, #2 + sqrshrn h15, s10, #6 + sqrshrn s15, d12, #9 + +// CHECK: sqrshrn b10, h13, #2 // encoding: [0xaa,0x9d,0x0e,0x5f] +// CHECK: sqrshrn h15, s10, #6 // encoding: [0x4f,0x9d,0x1a,0x5f] +// CHECK: sqrshrn s15, d12, #9 // encoding: [0x8f,0x9d,0x37,0x5f] + +//---------------------------------------------------------------------- +// Unsigned Saturating Rounded Shift Right Narrow (Immediate) +//---------------------------------------------------------------------- + uqrshrn b10, h12, #5 + uqrshrn h12, s10, #14 + uqrshrn s10, d10, #25 + +// CHECK: uqrshrn b10, h12, #5 // encoding: [0x8a,0x9d,0x0b,0x7f] +// CHECK: uqrshrn h12, s10, #14 // encoding: [0x4c,0x9d,0x12,0x7f] +// CHECK: uqrshrn s10, d10, #25 // encoding: [0x4a,0x9d,0x27,0x7f] + +//---------------------------------------------------------------------- +// Signed Saturating Shift Right Unsigned Narrow (Immediate) +//---------------------------------------------------------------------- + sqshrun b15, h10, #7 + sqshrun h20, s14, #3 + sqshrun s10, d15, #15 + +// CHECK: sqshrun b15, h10, #7 // encoding: [0x4f,0x85,0x09,0x7f] +// CHECK: sqshrun h20, s14, #3 // encoding: [0xd4,0x85,0x1d,0x7f] +// CHECK: sqshrun s10, d15, #15 // encoding: [0xea,0x85,0x31,0x7f] + +//---------------------------------------------------------------------- +// Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) +//---------------------------------------------------------------------- + + sqrshrun b17, h10, #6 + sqrshrun h10, s13, #15 + sqrshrun s22, d16, #31 + +// CHECK: sqrshrun b17, h10, #6 // encoding: [0x51,0x8d,0x0a,0x7f] +// CHECK: sqrshrun h10, s13, #15 // encoding: [0xaa,0x8d,0x11,0x7f] +// CHECK: sqrshrun s22, d16, #31 // encoding: [0x16,0x8e,0x21,0x7f] diff --git a/test/MC/AArch64/neon-scalar-shift.s b/test/MC/AArch64/neon-scalar-shift.s new file mode 100644 index 000000000000..366840a93159 --- /dev/null +++ b/test/MC/AArch64/neon-scalar-shift.s @@ -0,0 +1,16 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +//------------------------------------------------------------------------------ +// Scalar Integer Shift Lef (Signed) +//------------------------------------------------------------------------------ + sshl d17, d31, d8 + +// CHECK: sshl d17, d31, d8 // encoding: [0xf1,0x47,0xe8,0x5e] + +//------------------------------------------------------------------------------ +// Scalar Integer Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + ushl d17, d31, d8 + +// CHECK: ushl d17, d31, d8 // encoding: [0xf1,0x47,0xe8,0x7e] + diff --git a/test/MC/AArch64/neon-shift-left-long.s b/test/MC/AArch64/neon-shift-left-long.s new file mode 100644 index 000000000000..97604587424e --- /dev/null +++ b/test/MC/AArch64/neon-shift-left-long.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Integer shift left long (Signed) +//------------------------------------------------------------------------------ + sshll v0.8h, v1.8b, #3 + sshll v0.4s, v1.4h, #3 + sshll v0.2d, v1.2s, #3 + sshll2 v0.8h, v1.16b, #3 + sshll2 v0.4s, v1.8h, #3 + sshll2 v0.2d, v1.4s, #3 + +// CHECK: sshll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x0f] +// CHECK: sshll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x0f] +// CHECK: sshll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x0f] +// CHECK: sshll2 v0.8h, v1.16b, #3 // encoding: [0x20,0xa4,0x0b,0x4f] +// CHECK: sshll2 v0.4s, v1.8h, #3 // encoding: [0x20,0xa4,0x13,0x4f] +// CHECK: sshll2 v0.2d, v1.4s, #3 // encoding: [0x20,0xa4,0x23,0x4f] + +//------------------------------------------------------------------------------ +// Integer shift left long (Unsigned) +//------------------------------------------------------------------------------ + ushll v0.8h, v1.8b, #3 + ushll v0.4s, v1.4h, #3 + ushll v0.2d, v1.2s, #3 + ushll2 v0.8h, v1.16b, #3 + ushll2 v0.4s, v1.8h, #3 + ushll2 v0.2d, v1.4s, #3 + +// CHECK: ushll v0.8h, v1.8b, #3 // encoding: [0x20,0xa4,0x0b,0x2f] +// CHECK: ushll v0.4s, v1.4h, #3 // encoding: [0x20,0xa4,0x13,0x2f] +// CHECK: ushll v0.2d, v1.2s, #3 // encoding: [0x20,0xa4,0x23,0x2f] +// CHECK: ushll2 v0.8h, v1.16b, #3 // encoding: [0x20,0xa4,0x0b,0x6f] +// CHECK: ushll2 v0.4s, v1.8h, #3 // encoding: [0x20,0xa4,0x13,0x6f] +// CHECK: ushll2 v0.2d, v1.4s, #3 // encoding: [0x20,0xa4,0x23,0x6f] diff --git a/test/MC/AArch64/neon-shift.s b/test/MC/AArch64/neon-shift.s new file mode 100644 index 000000000000..614e6de16222 --- /dev/null +++ b/test/MC/AArch64/neon-shift.s @@ -0,0 +1,61 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Vector Integer Shift Lef (Signed) +//------------------------------------------------------------------------------ + sshl v0.8b, v1.8b, v2.8b + sshl v0.16b, v1.16b, v2.16b + sshl v0.4h, v1.4h, v2.4h + sshl v0.8h, v1.8h, v2.8h + sshl v0.2s, v1.2s, v2.2s + sshl v0.4s, v1.4s, v2.4s + sshl v0.2d, v1.2d, v2.2d + +// CHECK: sshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x0e] +// CHECK: sshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x4e] +// CHECK: sshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x44,0x62,0x0e] +// CHECK: sshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x44,0x62,0x4e] +// CHECK: sshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x44,0xa2,0x0e] +// CHECK: sshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x44,0xa2,0x4e] +// CHECK: sshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x44,0xe2,0x4e] + +//------------------------------------------------------------------------------ +// Vector Integer Shift Lef (Unsigned) +//------------------------------------------------------------------------------ + ushl v0.8b, v1.8b, v2.8b + ushl v0.16b, v1.16b, v2.16b + ushl v0.4h, v1.4h, v2.4h + ushl v0.8h, v1.8h, v2.8h + ushl v0.2s, v1.2s, v2.2s + ushl v0.4s, v1.4s, v2.4s + ushl v0.2d, v1.2d, v2.2d + +// CHECK: ushl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x44,0x22,0x2e] +// CHECK: ushl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x44,0x22,0x6e] +// CHECK: ushl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x44,0x62,0x2e] +// CHECK: ushl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x44,0x62,0x6e] +// CHECK: ushl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x44,0xa2,0x2e] +// CHECK: ushl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x44,0xa2,0x6e] +// CHECK: ushl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x44,0xe2,0x6e] + +//------------------------------------------------------------------------------ +// Vector Integer Shift Left by Immediate +//------------------------------------------------------------------------------ + shl v0.8b, v1.8b, #3 + shl v0.4h, v1.4h, #3 + shl v0.2s, v1.2s, #3 + shl v0.16b, v1.16b, #3 + shl v0.8h, v1.8h, #3 + shl v0.4s, v1.4s, #3 + shl v0.2d, v1.2d, #3 + +// CHECK: shl v0.8b, v1.8b, #3 // encoding: [0x20,0x54,0x0b,0x0f] +// CHECK: shl v0.4h, v1.4h, #3 // encoding: [0x20,0x54,0x13,0x0f] +// CHECK: shl v0.2s, v1.2s, #3 // encoding: [0x20,0x54,0x23,0x0f] +// CHECK: shl v0.16b, v1.16b, #3 // encoding: [0x20,0x54,0x0b,0x4f] +// CHECK: shl v0.8h, v1.8h, #3 // encoding: [0x20,0x54,0x13,0x4f] +// CHECK: shl v0.4s, v1.4s, #3 // encoding: [0x20,0x54,0x23,0x4f] +// CHECK: shl v0.2d, v1.2d, #3 // encoding: [0x20,0x54,0x43,0x4f] diff --git a/test/MC/AArch64/neon-simd-copy.s b/test/MC/AArch64/neon-simd-copy.s new file mode 100644 index 000000000000..f254d65b3b0c --- /dev/null +++ b/test/MC/AArch64/neon-simd-copy.s @@ -0,0 +1,135 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Insert element (vector, from main) +//------------------------------------------------------------------------------ + ins v2.b[2], w1 + ins v7.h[7], w14 + ins v20.s[0], w30 + ins v1.d[1], x7 + + mov v2.b[2], w1 + mov v7.h[7], w14 + mov v20.s[0], w30 + mov v1.d[1], x7 + +// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] + +// CHECK: ins v2.b[2], w1 // encoding: [0x22,0x1c,0x05,0x4e] +// CHECK: ins v7.h[7], w14 // encoding: [0xc7,0x1d,0x1e,0x4e] +// CHECK: ins v20.s[0], w30 // encoding: [0xd4,0x1f,0x04,0x4e] +// CHECK: ins v1.d[1], x7 // encoding: [0xe1,0x1c,0x18,0x4e] + + +//------------------------------------------------------------------------------ +// Signed integer move (main, from element) +//------------------------------------------------------------------------------ + smov w1, v0.b[15] + smov w14, v6.h[4] + smov x1, v0.b[15] + smov x14, v6.h[4] + smov x20, v9.s[2] + +// CHECK: smov w1, v0.b[15] // encoding: [0x01,0x2c,0x1f,0x0e] +// CHECK: smov w14, v6.h[4] // encoding: [0xce,0x2c,0x12,0x0e] +// CHECK: smov x1, v0.b[15] // encoding: [0x01,0x2c,0x1f,0x4e] +// CHECK: smov x14, v6.h[4] // encoding: [0xce,0x2c,0x12,0x4e] +// CHECK: smov x20, v9.s[2] // encoding: [0x34,0x2d,0x14,0x4e] + + +//------------------------------------------------------------------------------ +// Unsigned integer move (main, from element) +//------------------------------------------------------------------------------ + umov w1, v0.b[15] + umov w14, v6.h[4] + umov w20, v9.s[2] + umov x7, v18.d[1] + + mov w20, v9.s[2] + mov x7, v18.d[1] + +// CHECK: umov w1, v0.b[15] // encoding: [0x01,0x3c,0x1f,0x0e] +// CHECK: umov w14, v6.h[4] // encoding: [0xce,0x3c,0x12,0x0e] +// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] + +// CHECK: umov w20, v9.s[2] // encoding: [0x34,0x3d,0x14,0x0e] +// CHECK: umov x7, v18.d[1] // encoding: [0x47,0x3e,0x18,0x4e] + +//------------------------------------------------------------------------------ +// Insert element (vector, from element) +//------------------------------------------------------------------------------ + + ins v1.b[14], v3.b[6] + ins v6.h[7], v7.h[5] + ins v15.s[3], v22.s[2] + ins v0.d[0], v4.d[1] + + mov v1.b[14], v3.b[6] + mov v6.h[7], v7.h[5] + mov v15.s[3], v22.s[2] + mov v0.d[0], v4.d[1] + +// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] + +// CHECK: ins v1.b[14], v3.b[6] // encoding: [0x61,0x34,0x1d,0x6e] +// CHECK: ins v6.h[7], v7.h[5] // encoding: [0xe6,0x54,0x1e,0x6e] +// CHECK: ins v15.s[3], v22.s[2] // encoding: [0xcf,0x46,0x1c,0x6e] +// CHECK: ins v0.d[0], v4.d[1] // encoding: [0x80,0x44,0x08,0x6e] + +//------------------------------------------------------------------------------ +// Duplicate to all lanes( vector, from element) +//------------------------------------------------------------------------------ + dup v1.8b, v2.b[2] + dup v11.4h, v7.h[7] + dup v17.2s, v20.s[0] + dup v1.16b, v2.b[2] + dup v11.8h, v7.h[7] + dup v17.4s, v20.s[0] + dup v5.2d, v1.d[1] + +// CHECK: dup v1.8b, v2.b[2] // encoding: [0x41,0x04,0x05,0x0e] +// CHECK: dup v11.4h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x0e] +// CHECK: dup v17.2s, v20.s[0] // encoding: [0x91,0x06,0x04,0x0e] +// CHECK: dup v1.16b, v2.b[2] // encoding: [0x41,0x04,0x05,0x4e] +// CHECK: dup v11.8h, v7.h[7] // encoding: [0xeb,0x04,0x1e,0x4e] +// CHECK: dup v17.4s, v20.s[0] // encoding: [0x91,0x06,0x04,0x4e] +// CHECK: dup v5.2d, v1.d[1] // encoding: [0x25,0x04,0x18,0x4e] + +//------------------------------------------------------------------------------ +// Duplicate to all lanes( vector, from main) +//------------------------------------------------------------------------------ + dup v1.8b, w1 + dup v11.4h, w14 + dup v17.2s, w30 + dup v1.16b, w2 + dup v11.8h, w16 + dup v17.4s, w28 + dup v5.2d, x0 + +// CHECK: dup v1.8b, w1 // encoding: [0x21,0x0c,0x01,0x0e] +// CHECK: dup v11.4h, w14 // encoding: [0xcb,0x0d,0x02,0x0e] +// CHECK: dup v17.2s, w30 // encoding: [0xd1,0x0f,0x04,0x0e] +// CHECK: dup v1.16b, w2 // encoding: [0x41,0x0c,0x01,0x4e] +// CHECK: dup v11.8h, w16 // encoding: [0x0b,0x0e,0x02,0x4e] +// CHECK: dup v17.4s, w28 // encoding: [0x91,0x0f,0x04,0x4e] +// CHECK: dup v5.2d, x0 // encoding: [0x05,0x0c,0x08,0x4e] + + + + + + + + + + diff --git a/test/MC/AArch64/neon-simd-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-ldst-multi-elem.s new file mode 100644 index 000000000000..05fe4dac9138 --- /dev/null +++ b/test/MC/AArch64/neon-simd-ldst-multi-elem.s @@ -0,0 +1,463 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from one register +//------------------------------------------------------------------------------ + st1 {v0.16b}, [x0] + st1 {v15.8h}, [x15] + st1 {v31.4s}, [sp] + st1 {v0.2d}, [x0] + st1 {v0.8b}, [x0] + st1 {v15.4h}, [x15] + st1 {v31.2s}, [sp] + st1 {v0.1d}, [x0] +// CHECK: st1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x00,0x4c] +// CHECK: st1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x00,0x4c] +// CHECK: st1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x00,0x4c] +// CHECK: st1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x00,0x4c] +// CHECK: st1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x00,0x0c] +// CHECK: st1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x00,0x0c] +// CHECK: st1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x00,0x0c] +// CHECK: st1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from two consecutive registers +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b}, [x0] + st1 {v15.8h, v16.8h}, [x15] + st1 {v31.4s, v0.4s}, [sp] + st1 {v0.2d, v1.2d}, [x0] + st1 {v0.8b, v1.8b}, [x0] + st1 {v15.4h, v16.4h}, [x15] + st1 {v31.2s, v0.2s}, [sp] + st1 {v0.1d, v1.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + + st1 {v0.16b-v1.16b}, [x0] + st1 {v15.8h-v16.8h}, [x15] + st1 {v31.4s-v0.4s}, [sp] + st1 {v0.2d-v1.2d}, [x0] + st1 {v0.8b-v1.8b}, [x0] + st1 {v15.4h-v16.4h}, [x15] + st1 {v31.2s-v0.2s}, [sp] + st1 {v0.1d-v1.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from three consecutive registers +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b}, [x0] + st1 {v15.8h, v16.8h, v17.8h}, [x15] + st1 {v31.4s, v0.4s, v1.4s}, [sp] + st1 {v0.2d, v1.2d, v2.2d}, [x0] + st1 {v0.8b, v1.8b, v2.8b}, [x0] + st1 {v15.4h, v16.4h, v17.4h}, [x15] + st1 {v31.2s, v0.2s, v1.2s}, [sp] + st1 {v0.1d, v1.1d, v2.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + + st1 {v0.16b-v2.16b}, [x0] + st1 {v15.8h-v17.8h}, [x15] + st1 {v31.4s-v1.4s}, [sp] + st1 {v0.2d-v2.2d}, [x0] + st1 {v0.8b-v2.8b}, [x0] + st1 {v15.4h-v17.4h}, [x15] + st1 {v31.2s-v1.2s}, [sp] + st1 {v0.1d-v2.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from four consecutive registers +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] + st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] + st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] + st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] + st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] + st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + + st1 {v0.16b-v3.16b}, [x0] + st1 {v15.8h-v18.8h}, [x15] + st1 {v31.4s-v2.4s}, [sp] + st1 {v0.2d-v3.2d}, [x0] + st1 {v0.8b-v3.8b}, [x0] + st1 {v15.4h-v18.4h}, [x15] + st1 {v31.2s-v2.2s}, [sp] + st1 {v0.1d-v3.1d}, [x0] +// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x00,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x00,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x00,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x00,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x00,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x00,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x00,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 2-element structures from two consecutive registers +//------------------------------------------------------------------------------ + st2 {v0.16b, v1.16b}, [x0] + st2 {v15.8h, v16.8h}, [x15] + st2 {v31.4s, v0.4s}, [sp] + st2 {v0.2d, v1.2d}, [x0] + st2 {v0.8b, v1.8b}, [x0] + st2 {v15.4h, v16.4h}, [x15] + st2 {v31.2s, v0.2s}, [sp] +// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + + st2 {v0.16b-v1.16b}, [x0] + st2 {v15.8h-v16.8h}, [x15] + st2 {v31.4s-v0.4s}, [sp] + st2 {v0.2d-v1.2d}, [x0] + st2 {v0.8b-v1.8b}, [x0] + st2 {v15.4h-v16.4h}, [x15] + st2 {v31.2s-v0.2s}, [sp] +// CHECK: st2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x00,0x4c] +// CHECK: st2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x00,0x4c] +// CHECK: st2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x00,0x4c] +// CHECK: st2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x00,0x4c] +// CHECK: st2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x00,0x0c] +// CHECK: st2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x00,0x0c] +// CHECK: st2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 3-element structures from three consecutive registers +//------------------------------------------------------------------------------ + st3 {v0.16b, v1.16b, v2.16b}, [x0] + st3 {v15.8h, v16.8h, v17.8h}, [x15] + st3 {v31.4s, v0.4s, v1.4s}, [sp] + st3 {v0.2d, v1.2d, v2.2d}, [x0] + st3 {v0.8b, v1.8b, v2.8b}, [x0] + st3 {v15.4h, v16.4h, v17.4h}, [x15] + st3 {v31.2s, v0.2s, v1.2s}, [sp] +// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + + st3 {v0.16b-v2.16b}, [x0] + st3 {v15.8h-v17.8h}, [x15] + st3 {v31.4s-v1.4s}, [sp] + st3 {v0.2d-v2.2d}, [x0] + st3 {v0.8b-v2.8b}, [x0] + st3 {v15.4h-v17.4h}, [x15] + st3 {v31.2s-v1.2s}, [sp] +// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x00,0x4c] +// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x00,0x4c] +// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x00,0x4c] +// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x00,0x4c] +// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x00,0x0c] +// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x00,0x0c] +// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 4-element structures from four consecutive registers +//------------------------------------------------------------------------------ + st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] + st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] + st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] + st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] + st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + + st4 {v0.16b-v3.16b}, [x0] + st4 {v15.8h-v18.8h}, [x15] + st4 {v31.4s-v2.4s}, [sp] + st4 {v0.2d-v3.2d}, [x0] + st4 {v0.8b-v3.8b}, [x0] + st4 {v15.4h-v18.4h}, [x15] + st4 {v31.2s-v2.2s}, [sp] +// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x00,0x4c] +// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x00,0x4c] +// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x00,0x4c] +// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x00,0x4c] +// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x00,0x0c] +// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x00,0x0c] +// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x00,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures to one register +//------------------------------------------------------------------------------ + ld1 {v0.16b}, [x0] + ld1 {v15.8h}, [x15] + ld1 {v31.4s}, [sp] + ld1 {v0.2d}, [x0] + ld1 {v0.8b}, [x0] + ld1 {v15.4h}, [x15] + ld1 {v31.2s}, [sp] + ld1 {v0.1d}, [x0] +// CHECK: ld1 {v0.16b}, [x0] // encoding: [0x00,0x70,0x40,0x4c] +// CHECK: ld1 {v15.8h}, [x15] // encoding: [0xef,0x75,0x40,0x4c] +// CHECK: ld1 {v31.4s}, [sp] // encoding: [0xff,0x7b,0x40,0x4c] +// CHECK: ld1 {v0.2d}, [x0] // encoding: [0x00,0x7c,0x40,0x4c] +// CHECK: ld1 {v0.8b}, [x0] // encoding: [0x00,0x70,0x40,0x0c] +// CHECK: ld1 {v15.4h}, [x15] // encoding: [0xef,0x75,0x40,0x0c] +// CHECK: ld1 {v31.2s}, [sp] // encoding: [0xff,0x7b,0x40,0x0c] +// CHECK: ld1 {v0.1d}, [x0] // encoding: [0x00,0x7c,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures to two consecutive registers +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b}, [x0] + ld1 {v15.8h, v16.8h}, [x15] + ld1 {v31.4s, v0.4s}, [sp] + ld1 {v0.2d, v1.2d}, [x0] + ld1 {v0.8b, v1.8b}, [x0] + ld1 {v15.4h, v16.4h}, [x15] + ld1 {v31.2s, v0.2s}, [sp] + ld1 {v0.1d, v1.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + + ld1 {v0.16b-v1.16b}, [x0] + ld1 {v15.8h-v16.8h}, [x15] + ld1 {v31.4s-v0.4s}, [sp] + ld1 {v0.2d-v1.2d}, [x0] + ld1 {v0.8b-v1.8b}, [x0] + ld1 {v15.4h-v16.4h}, [x15] + ld1 {v31.2s-v0.2s}, [sp] + ld1 {v0.1d-v1.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xa0,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xa5,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xab,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xac,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xa0,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xa5,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xab,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d}, [x0] // encoding: [0x00,0xac,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures to three consecutive registers +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b}, [x0] + ld1 {v15.8h, v16.8h, v17.8h}, [x15] + ld1 {v31.4s, v0.4s, v1.4s}, [sp] + ld1 {v0.2d, v1.2d, v2.2d}, [x0] + ld1 {v0.8b, v1.8b, v2.8b}, [x0] + ld1 {v15.4h, v16.4h, v17.4h}, [x15] + ld1 {v31.2s, v0.2s, v1.2s}, [sp] + ld1 {v0.1d, v1.1d, v2.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + + ld1 {v0.16b-v2.16b}, [x0] + ld1 {v15.8h-v17.8h}, [x15] + ld1 {v31.4s-v1.4s}, [sp] + ld1 {v0.2d-v2.2d}, [x0] + ld1 {v0.8b-v2.8b}, [x0] + ld1 {v15.4h-v17.4h}, [x15] + ld1 {v31.2s-v1.2s}, [sp] + ld1 {v0.1d-v2.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x60,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x65,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x6b,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x6c,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x60,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x65,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x6b,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0] // encoding: [0x00,0x6c,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures to four consecutive registers +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] + ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] + ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] + ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] + ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] + ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + + ld1 {v0.16b-v3.16b}, [x0] + ld1 {v15.8h-v18.8h}, [x15] + ld1 {v31.4s-v2.4s}, [sp] + ld1 {v0.2d-v3.2d}, [x0] + ld1 {v0.8b-v3.8b}, [x0] + ld1 {v15.4h-v18.4h}, [x15] + ld1 {v31.2s-v2.2s}, [sp] + ld1 {v0.1d-v3.1d}, [x0] +// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x20,0x40,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x25,0x40,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x2b,0x40,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x2c,0x40,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x20,0x40,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x25,0x40,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x2b,0x40,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0] // encoding: [0x00,0x2c,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 4-element structures to two consecutive registers +//------------------------------------------------------------------------------ + ld2 {v0.16b, v1.16b}, [x0] + ld2 {v15.8h, v16.8h}, [x15] + ld2 {v31.4s, v0.4s}, [sp] + ld2 {v0.2d, v1.2d}, [x0] + ld2 {v0.8b, v1.8b}, [x0] + ld2 {v15.4h, v16.4h}, [x15] + ld2 {v31.2s, v0.2s}, [sp] +// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + + ld2 {v0.16b-v1.16b}, [x0] + ld2 {v15.8h-v16.8h}, [x15] + ld2 {v31.4s-v0.4s}, [sp] + ld2 {v0.2d-v1.2d}, [x0] + ld2 {v0.8b-v1.8b}, [x0] + ld2 {v15.4h-v16.4h}, [x15] + ld2 {v31.2s-v0.2s}, [sp] +// CHECK: ld2 {v0.16b, v1.16b}, [x0] // encoding: [0x00,0x80,0x40,0x4c] +// CHECK: ld2 {v15.8h, v16.8h}, [x15] // encoding: [0xef,0x85,0x40,0x4c] +// CHECK: ld2 {v31.4s, v0.4s}, [sp] // encoding: [0xff,0x8b,0x40,0x4c] +// CHECK: ld2 {v0.2d, v1.2d}, [x0] // encoding: [0x00,0x8c,0x40,0x4c] +// CHECK: ld2 {v0.8b, v1.8b}, [x0] // encoding: [0x00,0x80,0x40,0x0c] +// CHECK: ld2 {v15.4h, v16.4h}, [x15] // encoding: [0xef,0x85,0x40,0x0c] +// CHECK: ld2 {v31.2s, v0.2s}, [sp] // encoding: [0xff,0x8b,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 3-element structures to three consecutive registers +//------------------------------------------------------------------------------ + ld3 {v0.16b, v1.16b, v2.16b}, [x0] + ld3 {v15.8h, v16.8h, v17.8h}, [x15] + ld3 {v31.4s, v0.4s, v1.4s}, [sp] + ld3 {v0.2d, v1.2d, v2.2d}, [x0] + ld3 {v0.8b, v1.8b, v2.8b}, [x0] + ld3 {v15.4h, v16.4h, v17.4h}, [x15] + ld3 {v31.2s, v0.2s, v1.2s}, [sp] +// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + + ld3 {v0.16b-v2.16b}, [x0] + ld3 {v15.8h-v17.8h}, [x15] + ld3 {v31.4s-v1.4s}, [sp] + ld3 {v0.2d-v2.2d}, [x0] + ld3 {v0.8b-v2.8b}, [x0] + ld3 {v15.4h-v17.4h}, [x15] + ld3 {v31.2s-v1.2s}, [sp] +// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0x40,0x40,0x4c] +// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0x45,0x40,0x4c] +// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0x4b,0x40,0x4c] +// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0x4c,0x40,0x4c] +// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0x40,0x40,0x0c] +// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0x45,0x40,0x0c] +// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0x4b,0x40,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 4-element structures to four consecutive registers +//------------------------------------------------------------------------------ + ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] + ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] + ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] + ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] + ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] + + ld4 {v0.16b-v3.16b}, [x0] + ld4 {v15.8h-v18.8h}, [x15] + ld4 {v31.4s-v2.4s}, [sp] + ld4 {v0.2d-v3.2d}, [x0] + ld4 {v0.8b-v3.8b}, [x0] + ld4 {v15.4h-v18.4h}, [x15] + ld4 {v31.2s-v2.2s}, [sp] +// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0x00,0x40,0x4c] +// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0x05,0x40,0x4c] +// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0x0b,0x40,0x4c] +// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0x0c,0x40,0x4c] +// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0x00,0x40,0x0c] +// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0x05,0x40,0x0c] +// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0x0b,0x40,0x0c] diff --git a/test/MC/AArch64/neon-simd-ldst-one-elem.s b/test/MC/AArch64/neon-simd-ldst-one-elem.s new file mode 100644 index 000000000000..140d7525fee6 --- /dev/null +++ b/test/MC/AArch64/neon-simd-ldst-one-elem.s @@ -0,0 +1,325 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Load single 1-element structure to all lanes of 1 register +//------------------------------------------------------------------------------ + ld1r {v0.16b}, [x0] + ld1r {v15.8h}, [x15] + ld1r {v31.4s}, [sp] + ld1r {v0.2d}, [x0] + ld1r {v0.8b}, [x0] + ld1r {v15.4h}, [x15] + ld1r {v31.2s}, [sp] + ld1r {v0.1d}, [x0] +// CHECK: ld1r {v0.16b}, [x0] // encoding: [0x00,0xc0,0x40,0x4d] +// CHECK: ld1r {v15.8h}, [x15] // encoding: [0xef,0xc5,0x40,0x4d] +// CHECK: ld1r {v31.4s}, [sp] // encoding: [0xff,0xcb,0x40,0x4d] +// CHECK: ld1r {v0.2d}, [x0] // encoding: [0x00,0xcc,0x40,0x4d] +// CHECK: ld1r {v0.8b}, [x0] // encoding: [0x00,0xc0,0x40,0x0d] +// CHECK: ld1r {v15.4h}, [x15] // encoding: [0xef,0xc5,0x40,0x0d] +// CHECK: ld1r {v31.2s}, [sp] // encoding: [0xff,0xcb,0x40,0x0d] +// CHECK: ld1r {v0.1d}, [x0] // encoding: [0x00,0xcc,0x40,0x0d] + +//------------------------------------------------------------------------------ +// Load single N-element structure to all lanes of N consecutive +// registers (N = 2,3,4) +//------------------------------------------------------------------------------ + ld2r {v0.16b, v1.16b}, [x0] + ld2r {v15.8h, v16.8h}, [x15] + ld2r {v31.4s, v0.4s}, [sp] + ld2r {v0.2d, v1.2d}, [x0] + ld2r {v0.8b, v1.8b}, [x0] + ld2r {v15.4h, v16.4h}, [x15] + ld2r {v31.2s, v0.2s}, [sp] + ld2r {v31.1d, v0.1d}, [sp] +// CHECK: ld2r {v0.16b, v1.16b}, [x0] // encoding: [0x00,0xc0,0x60,0x4d] +// CHECK: ld2r {v15.8h, v16.8h}, [x15] // encoding: [0xef,0xc5,0x60,0x4d] +// CHECK: ld2r {v31.4s, v0.4s}, [sp] // encoding: [0xff,0xcb,0x60,0x4d] +// CHECK: ld2r {v0.2d, v1.2d}, [x0] // encoding: [0x00,0xcc,0x60,0x4d] +// CHECK: ld2r {v0.8b, v1.8b}, [x0] // encoding: [0x00,0xc0,0x60,0x0d] +// CHECK: ld2r {v15.4h, v16.4h}, [x15] // encoding: [0xef,0xc5,0x60,0x0d] +// CHECK: ld2r {v31.2s, v0.2s}, [sp] // encoding: [0xff,0xcb,0x60,0x0d] +// CHECK: ld2r {v31.1d, v0.1d}, [sp] // encoding: [0xff,0xcf,0x60,0x0d] + + ld3r {v0.16b, v1.16b, v2.16b}, [x0] + ld3r {v15.8h, v16.8h, v17.8h}, [x15] + ld3r {v31.4s, v0.4s, v1.4s}, [sp] + ld3r {v0.2d, v1.2d, v2.2d}, [x0] + ld3r {v0.8b, v1.8b, v2.8b}, [x0] + ld3r {v15.4h, v16.4h, v17.4h}, [x15] + ld3r {v31.2s, v0.2s, v1.2s}, [sp] + ld3r {v31.1d, v0.1d, v1.1d}, [sp] +// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0] // encoding: [0x00,0xe0,0x40,0x4d] +// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15] // encoding: [0xef,0xe5,0x40,0x4d] +// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp] // encoding: [0xff,0xeb,0x40,0x4d] +// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0] // encoding: [0x00,0xec,0x40,0x4d] +// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] // encoding: [0x00,0xe0,0x40,0x0d] +// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] // encoding: [0xef,0xe5,0x40,0x0d] +// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp] // encoding: [0xff,0xeb,0x40,0x0d] +// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp] // encoding: [0xff,0xef,0x40,0x0d] + + ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] + ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] + ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] + ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] + ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] + ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] + ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] + ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0] // encoding: [0x00,0xe0,0x60,0x4d] +// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15] // encoding: [0xef,0xe5,0x60,0x4d] +// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp] // encoding: [0xff,0xeb,0x60,0x4d] +// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] // encoding: [0x00,0xec,0x60,0x4d] +// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0] // encoding: [0x00,0xe0,0x60,0x0d] +// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15] // encoding: [0xef,0xe5,0x60,0x0d] +// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] // encoding: [0xff,0xeb,0x60,0x0d] +// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] // encoding: [0xff,0xef,0x60,0x0d] + +//------------------------------------------------------------------------------ +// Load single 1-element structure to one lane of 1 register. +//------------------------------------------------------------------------------ + ld1 {v0.b}[9], [x0] + ld1 {v15.h}[7], [x15] + ld1 {v31.s}[3], [sp] + ld1 {v0.d}[1], [x0] +// CHECK: ld1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x40,0x4d] +// CHECK: ld1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x40,0x4d] +// CHECK: ld1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x40,0x4d] +// CHECK: ld1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x40,0x4d] + +//------------------------------------------------------------------------------ +// Load single N-element structure to one lane of N consecutive registers +// (N = 2,3,4) +//------------------------------------------------------------------------------ + ld2 {v0.b, v1.b}[9], [x0] + ld2 {v15.h, v16.h}[7], [x15] + ld2 {v31.s, v0.s}[3], [sp] + ld2 {v0.d, v1.d}[1], [x0] +// CHECK: ld2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x60,0x4d] +// CHECK: ld2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x60,0x4d] +// CHECK: ld2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x60,0x4d] +// CHECK: ld2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x60,0x4d] + + ld3 {v0.b, v1.b, v2.b}[9], [x0] + ld3 {v15.h, v16.h, v17.h}[7], [x15] + ld3 {v31.s, v0.s, v1.s}[3], [sp] + ld3 {v0.d, v1.d, v2.d}[1], [x0] +// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x40,0x4d] +// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x40,0x4d] +// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x40,0x4d] +// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x40,0x4d] + + ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] + ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] + ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] + ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] +// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x60,0x4d] +// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x60,0x4d] +// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x60,0x4d] +// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x60,0x4d] + +//------------------------------------------------------------------------------ +// Store single 1-element structure from one lane of 1 register. +//------------------------------------------------------------------------------ + st1 {v0.b}[9], [x0] + st1 {v15.h}[7], [x15] + st1 {v31.s}[3], [sp] + st1 {v0.d}[1], [x0] +// CHECK: st1 {v0.b}[9], [x0] // encoding: [0x00,0x04,0x00,0x4d] +// CHECK: st1 {v15.h}[7], [x15] // encoding: [0xef,0x59,0x00,0x4d] +// CHECK: st1 {v31.s}[3], [sp] // encoding: [0xff,0x93,0x00,0x4d] +// CHECK: st1 {v0.d}[1], [x0] // encoding: [0x00,0x84,0x00,0x4d] + +//------------------------------------------------------------------------------ +// Store single N-element structure from one lane of N consecutive registers +// (N = 2,3,4) +//------------------------------------------------------------------------------ + st2 {v0.b, v1.b}[9], [x0] + st2 {v15.h, v16.h}[7], [x15] + st2 {v31.s, v0.s}[3], [sp] + st2 {v0.d, v1.d}[1], [x0] +// CHECK: st2 {v0.b, v1.b}[9], [x0] // encoding: [0x00,0x04,0x20,0x4d] +// CHECK: st2 {v15.h, v16.h}[7], [x15] // encoding: [0xef,0x59,0x20,0x4d] +// CHECK: st2 {v31.s, v0.s}[3], [sp] // encoding: [0xff,0x93,0x20,0x4d] +// CHECK: st2 {v0.d, v1.d}[1], [x0] // encoding: [0x00,0x84,0x20,0x4d] + + st3 {v0.b, v1.b, v2.b}[9], [x0] + st3 {v15.h, v16.h, v17.h}[7], [x15] + st3 {v31.s, v0.s, v1.s}[3], [sp] + st3 {v0.d, v1.d, v2.d}[1], [x0] +// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0] // encoding: [0x00,0x24,0x00,0x4d] +// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] // encoding: [0xef,0x79,0x00,0x4d] +// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp] // encoding: [0xff,0xb3,0x00,0x4d] +// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0] // encoding: [0x00,0xa4,0x00,0x4d] + + st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] + st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] + st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] + st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] +// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] // encoding: [0x00,0x24,0x20,0x4d] +// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15] // encoding: [0xef,0x79,0x20,0x4d] +// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp] // encoding: [0xff,0xb3,0x20,0x4d] +// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] // encoding: [0x00,0xa4,0x20,0x4d] + +//------------------------------------------------------------------------------ +// Post-index oad single 1-element structure to all lanes of 1 register +//------------------------------------------------------------------------------ + ld1r {v0.16b}, [x0], #1 + ld1r {v15.8h}, [x15], #2 + ld1r {v31.4s}, [sp], #4 + ld1r {v0.2d}, [x0], #8 + ld1r {v0.8b}, [x0], x0 + ld1r {v15.4h}, [x15], x1 + ld1r {v31.2s}, [sp], x2 + ld1r {v0.1d}, [x0], x3 +// CHECK: ld1r {v0.16b}, [x0], #1 // encoding: [0x00,0xc0,0xdf,0x4d] +// CHECK: ld1r {v15.8h}, [x15], #2 // encoding: [0xef,0xc5,0xdf,0x4d] +// CHECK: ld1r {v31.4s}, [sp], #4 // encoding: [0xff,0xcb,0xdf,0x4d] +// CHECK: ld1r {v0.2d}, [x0], #8 // encoding: [0x00,0xcc,0xdf,0x4d] +// CHECK: ld1r {v0.8b}, [x0], x0 // encoding: [0x00,0xc0,0xc0,0x0d] +// CHECK: ld1r {v15.4h}, [x15], x1 // encoding: [0xef,0xc5,0xc1,0x0d] +// CHECK: ld1r {v31.2s}, [sp], x2 // encoding: [0xff,0xcb,0xc2,0x0d] +// CHECK: ld1r {v0.1d}, [x0], x3 // encoding: [0x00,0xcc,0xc3,0x0d] + +//------------------------------------------------------------------------------ +// Post-index load single N-element structure to all lanes of N consecutive +// registers (N = 2,3,4) +//------------------------------------------------------------------------------ + ld2r {v0.16b, v1.16b}, [x0], #2 + ld2r {v15.8h, v16.8h}, [x15], #4 + ld2r {v31.4s, v0.4s}, [sp], #8 + ld2r {v0.2d, v1.2d}, [x0], #16 + ld2r {v0.8b, v1.8b}, [x0], x6 + ld2r {v15.4h, v16.4h}, [x15], x7 + ld2r {v31.2s, v0.2s}, [sp], x9 + ld2r {v31.1d, v0.1d}, [x0], x5 +// CHECK: ld2r {v0.16b, v1.16b}, [x0], #2 // encoding: [0x00,0xc0,0xff,0x4d] +// CHECK: ld2r {v15.8h, v16.8h}, [x15], #4 // encoding: [0xef,0xc5,0xff,0x4d] +// CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 // encoding: [0xff,0xcb,0xff,0x4d] +// CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 // encoding: [0x00,0xcc,0xff,0x4d] +// CHECK: ld2r {v0.8b, v1.8b}, [x0], x6 // encoding: [0x00,0xc0,0xe6,0x0d] +// CHECK: ld2r {v15.4h, v16.4h}, [x15], x7 // encoding: [0xef,0xc5,0xe7,0x0d] +// CHECK: ld2r {v31.2s, v0.2s}, [sp], x9 // encoding: [0xff,0xcb,0xe9,0x0d] +// CHECK: ld2r {v31.1d, v0.1d}, [x0], x5 // encoding: [0x1f,0xcc,0xe5,0x0d] + + ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 + ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 + ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 + ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 + ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 + ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 + ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 + ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 +// CHECK: ld3r {v0.16b, v1.16b, v2.16b}, [x0], x9 // encoding: [0x00,0xe0,0xc9,0x4d] +// CHECK: ld3r {v15.8h, v16.8h, v17.8h}, [x15], x6 // encoding: [0xef,0xe5,0xc6,0x4d] +// CHECK: ld3r {v31.4s, v0.4s, v1.4s}, [sp], x7 // encoding: [0xff,0xeb,0xc7,0x4d] +// CHECK: ld3r {v0.2d, v1.2d, v2.2d}, [x0], x5 // encoding: [0x00,0xec,0xc5,0x4d] +// CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 // encoding: [0x00,0xe0,0xdf,0x0d] +// CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 // encoding: [0xef,0xe5,0xdf,0x0d] +// CHECK: ld3r {v31.2s, v0.2s, v1.2s}, [sp], #12 // encoding: [0xff,0xeb,0xdf,0x0d] +// CHECK: ld3r {v31.1d, v0.1d, v1.1d}, [sp], #24 // encoding: [0xff,0xef,0xdf,0x0d] + + ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 + ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 + ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 + ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 + ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 + ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 + ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 + ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +// CHECK: ld4r {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], #4 // encoding: [0x00,0xe0,0xff,0x4d] +// CHECK: ld4r {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], #8 // encoding: [0xef,0xe5,0xff,0x4d] +// CHECK: ld4r {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #16 // encoding: [0xff,0xeb,0xff,0x4d] +// CHECK: ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #32 // encoding: [0x00,0xec,0xff,0x4d] +// CHECK: ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x5 // encoding: [0x00,0xe0,0xe5,0x0d] +// CHECK: ld4r {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x9 // encoding: [0xef,0xe5,0xe9,0x0d] +// CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 // encoding: [0xff,0xeb,0xfe,0x0d] +// CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 // encoding: [0xff,0xef,0xe7,0x0d] + +//------------------------------------------------------------------------------ +// Post-index load single 1-element structure to one lane of 1 register. +//------------------------------------------------------------------------------ + ld1 {v0.b}[9], [x0], #1 + ld1 {v15.h}[7], [x15], x9 + ld1 {v31.s}[3], [sp], x6 + ld1 {v0.d}[1], [x0], #8 +// CHECK: ld1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0xdf,0x4d] +// CHECK: ld1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0xc9,0x4d] +// CHECK: ld1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0xc6,0x4d] +// CHECK: ld1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0xdf,0x4d] + +//------------------------------------------------------------------------------ +// Post-index load single N-element structure to one lane of N consecutive +// registers (N = 2,3,4) +//------------------------------------------------------------------------------ + ld2 {v0.b, v1.b}[9], [x0], x3 + ld2 {v15.h, v16.h}[7], [x15], #4 + ld2 {v31.s, v0.s}[3], [sp], #8 + ld2 {v0.d, v1.d}[1], [x0], x0 +// CHECK: ld2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xe3,0x4d] +// CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xff,0x4d] +// CHECK: ld2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xff,0x4d] +// CHECK: ld2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xe0,0x4d] + + ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 + ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 + ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 + ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 +// CHECK: ld3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0xdf,0x4d] +// CHECK: ld3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0xdf,0x4d] +// CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0xc3,0x4d] +// CHECK: ld3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0xc6,0x4d] + + ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 + ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 + ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 + ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 +// CHECK: ld4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xe5,0x4d] +// CHECK: ld4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xe7,0x4d] +// CHECK: ld4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xff,0x4d] +// CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xff,0x4d] + +//------------------------------------------------------------------------------ +// Post-index store single 1-element structure from one lane of 1 register. +//------------------------------------------------------------------------------ + st1 {v0.b}[9], [x0], #1 + st1 {v15.h}[7], [x15], x9 + st1 {v31.s}[3], [sp], x6 + st1 {v0.d}[1], [x0], #8 +// CHECK: st1 {v0.b}[9], [x0], #1 // encoding: [0x00,0x04,0x9f,0x4d] +// CHECK: st1 {v15.h}[7], [x15], x9 // encoding: [0xef,0x59,0x89,0x4d] +// CHECK: st1 {v31.s}[3], [sp], x6 // encoding: [0xff,0x93,0x86,0x4d] +// CHECK: st1 {v0.d}[1], [x0], #8 // encoding: [0x00,0x84,0x9f,0x4d] + +//------------------------------------------------------------------------------ +// Post-index store single N-element structure from one lane of N consecutive +// registers (N = 2,3,4) +//------------------------------------------------------------------------------ + st2 {v0.b, v1.b}[9], [x0], x3 + st2 {v15.h, v16.h}[7], [x15], #4 + st2 {v31.s, v0.s}[3], [sp], #8 + st2 {v0.d, v1.d}[1], [x0], x0 +// CHECK: st2 {v0.b, v1.b}[9], [x0], x3 // encoding: [0x00,0x04,0xa3,0x4d] +// CHECK: st2 {v15.h, v16.h}[7], [x15], #4 // encoding: [0xef,0x59,0xbf,0x4d] +// CHECK: st2 {v31.s, v0.s}[3], [sp], #8 // encoding: [0xff,0x93,0xbf,0x4d] +// CHECK: st2 {v0.d, v1.d}[1], [x0], x0 // encoding: [0x00,0x84,0xa0,0x4d] + + st3 {v0.b, v1.b, v2.b}[9], [x0], #3 + st3 {v15.h, v16.h, v17.h}[7], [x15], #6 + st3 {v31.s, v0.s, v1.s}[3], [sp], x3 + st3 {v0.d, v1.d, v2.d}[1], [x0], x6 +// CHECK: st3 {v0.b, v1.b, v2.b}[9], [x0], #3 // encoding: [0x00,0x24,0x9f,0x4d] +// CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 // encoding: [0xef,0x79,0x9f,0x4d] +// CHECK: st3 {v31.s, v0.s, v1.s}[3], [sp], x3 // encoding: [0xff,0xb3,0x83,0x4d] +// CHECK: st3 {v0.d, v1.d, v2.d}[1], [x0], x6 // encoding: [0x00,0xa4,0x86,0x4d] + + st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 + st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 + st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 + st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 +// CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 // encoding: [0x00,0x24,0xa5,0x4d] +// CHECK: st4 {v15.h, v16.h, v17.h, v18.h}[7], [x15], x7 // encoding: [0xef,0x79,0xa7,0x4d] +// CHECK: st4 {v31.s, v0.s, v1.s, v2.s}[3], [sp], #16 // encoding: [0xff,0xb3,0xbf,0x4d] +// CHECK: st4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 // encoding: [0x00,0xa4,0xbf,0x4d] diff --git a/test/MC/AArch64/neon-simd-misc.s b/test/MC/AArch64/neon-simd-misc.s new file mode 100644 index 000000000000..9e0f9c5b4d95 --- /dev/null +++ b/test/MC/AArch64/neon-simd-misc.s @@ -0,0 +1,646 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + + +//------------------------------------------------------------------------------ +// Element reverse +//------------------------------------------------------------------------------ + rev64 v0.16b, v31.16b + rev64 v2.8h, v4.8h + rev64 v6.4s, v8.4s + rev64 v1.8b, v9.8b + rev64 v13.4h, v21.4h + rev64 v4.2s, v0.2s + +// CHECK: rev64 v0.16b, v31.16b // encoding: [0xe0,0x0b,0x20,0x4e] +// CHECK: rev64 v2.8h, v4.8h // encoding: [0x82,0x08,0x60,0x4e] +// CHECK: rev64 v6.4s, v8.4s // encoding: [0x06,0x09,0xa0,0x4e] +// CHECK: rev64 v1.8b, v9.8b // encoding: [0x21,0x09,0x20,0x0e] +// CHECK: rev64 v13.4h, v21.4h // encoding: [0xad,0x0a,0x60,0x0e] +// CHECK: rev64 v4.2s, v0.2s // encoding: [0x04,0x08,0xa0,0x0e] + + rev32 v30.16b, v31.16b + rev32 v4.8h, v7.8h + rev32 v21.8b, v1.8b + rev32 v0.4h, v9.4h + +// CHECK: rev32 v30.16b, v31.16b // encoding: [0xfe,0x0b,0x20,0x6e] +// CHECK: rev32 v4.8h, v7.8h // encoding: [0xe4,0x08,0x60,0x6e] +// CHECK: rev32 v21.8b, v1.8b // encoding: [0x35,0x08,0x20,0x2e] +// CHECK: rev32 v0.4h, v9.4h // encoding: [0x20,0x09,0x60,0x2e] + + rev16 v30.16b, v31.16b + rev16 v21.8b, v1.8b + +// CHECK: rev16 v30.16b, v31.16b // encoding: [0xfe,0x1b,0x20,0x4e] +// CHECK: rev16 v21.8b, v1.8b // encoding: [0x35,0x18,0x20,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer pairwise add long +//------------------------------------------------------------------------------ + + saddlp v3.8h, v21.16b + saddlp v8.4h, v5.8b + saddlp v9.4s, v1.8h + saddlp v0.2s, v1.4h + saddlp v12.2d, v4.4s + saddlp v17.1d, v28.2s + +// CHECK: saddlp v3.8h, v21.16b // encoding: [0xa3,0x2a,0x20,0x4e] +// CHECK: saddlp v8.4h, v5.8b // encoding: [0xa8,0x28,0x20,0x0e] +// CHECK: saddlp v9.4s, v1.8h // encoding: [0x29,0x28,0x60,0x4e] +// CHECK: saddlp v0.2s, v1.4h // encoding: [0x20,0x28,0x60,0x0e] +// CHECK: saddlp v12.2d, v4.4s // encoding: [0x8c,0x28,0xa0,0x4e] +// CHECK: saddlp v17.1d, v28.2s // encoding: [0x91,0x2b,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add long +//------------------------------------------------------------------------------ + + uaddlp v3.8h, v21.16b + uaddlp v8.4h, v5.8b + uaddlp v9.4s, v1.8h + uaddlp v0.2s, v1.4h + uaddlp v12.2d, v4.4s + uaddlp v17.1d, v28.2s + +// CHECK: uaddlp v3.8h, v21.16b // encoding: [0xa3,0x2a,0x20,0x6e] +// CHECK: uaddlp v8.4h, v5.8b // encoding: [0xa8,0x28,0x20,0x2e] +// CHECK: uaddlp v9.4s, v1.8h // encoding: [0x29,0x28,0x60,0x6e] +// CHECK: uaddlp v0.2s, v1.4h // encoding: [0x20,0x28,0x60,0x2e] +// CHECK: uaddlp v12.2d, v4.4s // encoding: [0x8c,0x28,0xa0,0x6e] +// CHECK: uaddlp v17.1d, v28.2s // encoding: [0x91,0x2b,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + sadalp v3.8h, v21.16b + sadalp v8.4h, v5.8b + sadalp v9.4s, v1.8h + sadalp v0.2s, v1.4h + sadalp v12.2d, v4.4s + sadalp v17.1d, v28.2s + +// CHECK: sadalp v3.8h, v21.16b // encoding: [0xa3,0x6a,0x20,0x4e] +// CHECK: sadalp v8.4h, v5.8b // encoding: [0xa8,0x68,0x20,0x0e] +// CHECK: sadalp v9.4s, v1.8h // encoding: [0x29,0x68,0x60,0x4e] +// CHECK: sadalp v0.2s, v1.4h // encoding: [0x20,0x68,0x60,0x0e] +// CHECK: sadalp v12.2d, v4.4s // encoding: [0x8c,0x68,0xa0,0x4e] +// CHECK: sadalp v17.1d, v28.2s // encoding: [0x91,0x6b,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer pairwise add and accumulate long +//------------------------------------------------------------------------------ + + uadalp v3.8h, v21.16b + uadalp v8.4h, v5.8b + uadalp v9.4s, v1.8h + uadalp v0.2s, v1.4h + uadalp v12.2d, v4.4s + uadalp v17.1d, v28.2s + +// CHECK: uadalp v3.8h, v21.16b // encoding: [0xa3,0x6a,0x20,0x6e] +// CHECK: uadalp v8.4h, v5.8b // encoding: [0xa8,0x68,0x20,0x2e] +// CHECK: uadalp v9.4s, v1.8h // encoding: [0x29,0x68,0x60,0x6e] +// CHECK: uadalp v0.2s, v1.4h // encoding: [0x20,0x68,0x60,0x2e] +// CHECK: uadalp v12.2d, v4.4s // encoding: [0x8c,0x68,0xa0,0x6e] +// CHECK: uadalp v17.1d, v28.2s // encoding: [0x91,0x6b,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer saturating accumulate of unsigned value +//------------------------------------------------------------------------------ + + suqadd v0.16b, v31.16b + suqadd v2.8h, v4.8h + suqadd v6.4s, v8.4s + suqadd v6.2d, v8.2d + suqadd v1.8b, v9.8b + suqadd v13.4h, v21.4h + suqadd v4.2s, v0.2s + +// CHECK: suqadd v0.16b, v31.16b // encoding: [0xe0,0x3b,0x20,0x4e] +// CHECK: suqadd v2.8h, v4.8h // encoding: [0x82,0x38,0x60,0x4e] +// CHECK: suqadd v6.4s, v8.4s // encoding: [0x06,0x39,0xa0,0x4e] +// CHECK: suqadd v6.2d, v8.2d // encoding: [0x06,0x39,0xe0,0x4e] +// CHECK: suqadd v1.8b, v9.8b // encoding: [0x21,0x39,0x20,0x0e] +// CHECK: suqadd v13.4h, v21.4h // encoding: [0xad,0x3a,0x60,0x0e] +// CHECK: suqadd v4.2s, v0.2s // encoding: [0x04,0x38,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer saturating accumulate of signed value +//------------------------------------------------------------------------------ + + usqadd v0.16b, v31.16b + usqadd v2.8h, v4.8h + usqadd v6.4s, v8.4s + usqadd v6.2d, v8.2d + usqadd v1.8b, v9.8b + usqadd v13.4h, v21.4h + usqadd v4.2s, v0.2s + +// CHECK: usqadd v0.16b, v31.16b // encoding: [0xe0,0x3b,0x20,0x6e] +// CHECK: usqadd v2.8h, v4.8h // encoding: [0x82,0x38,0x60,0x6e] +// CHECK: usqadd v6.4s, v8.4s // encoding: [0x06,0x39,0xa0,0x6e] +// CHECK: usqadd v6.2d, v8.2d // encoding: [0x06,0x39,0xe0,0x6e] +// CHECK: usqadd v1.8b, v9.8b // encoding: [0x21,0x39,0x20,0x2e] +// CHECK: usqadd v13.4h, v21.4h // encoding: [0xad,0x3a,0x60,0x2e] +// CHECK: usqadd v4.2s, v0.2s // encoding: [0x04,0x38,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer saturating absolute +//------------------------------------------------------------------------------ + + sqabs v0.16b, v31.16b + sqabs v2.8h, v4.8h + sqabs v6.4s, v8.4s + sqabs v6.2d, v8.2d + sqabs v1.8b, v9.8b + sqabs v13.4h, v21.4h + sqabs v4.2s, v0.2s + +// CHECK: sqabs v0.16b, v31.16b // encoding: [0xe0,0x7b,0x20,0x4e] +// CHECK: sqabs v2.8h, v4.8h // encoding: [0x82,0x78,0x60,0x4e] +// CHECK: sqabs v6.4s, v8.4s // encoding: [0x06,0x79,0xa0,0x4e] +// CHECK: sqabs v6.2d, v8.2d // encoding: [0x06,0x79,0xe0,0x4e] +// CHECK: sqabs v1.8b, v9.8b // encoding: [0x21,0x79,0x20,0x0e] +// CHECK: sqabs v13.4h, v21.4h // encoding: [0xad,0x7a,0x60,0x0e] +// CHECK: sqabs v4.2s, v0.2s // encoding: [0x04,0x78,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer saturating negate +//------------------------------------------------------------------------------ + + sqneg v0.16b, v31.16b + sqneg v2.8h, v4.8h + sqneg v6.4s, v8.4s + sqneg v6.2d, v8.2d + sqneg v1.8b, v9.8b + sqneg v13.4h, v21.4h + sqneg v4.2s, v0.2s + +// CHECK: sqneg v0.16b, v31.16b // encoding: [0xe0,0x7b,0x20,0x6e] +// CHECK: sqneg v2.8h, v4.8h // encoding: [0x82,0x78,0x60,0x6e] +// CHECK: sqneg v6.4s, v8.4s // encoding: [0x06,0x79,0xa0,0x6e] +// CHECK: sqneg v6.2d, v8.2d // encoding: [0x06,0x79,0xe0,0x6e] +// CHECK: sqneg v1.8b, v9.8b // encoding: [0x21,0x79,0x20,0x2e] +// CHECK: sqneg v13.4h, v21.4h // encoding: [0xad,0x7a,0x60,0x2e] +// CHECK: sqneg v4.2s, v0.2s // encoding: [0x04,0x78,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer absolute +//------------------------------------------------------------------------------ + + abs v0.16b, v31.16b + abs v2.8h, v4.8h + abs v6.4s, v8.4s + abs v6.2d, v8.2d + abs v1.8b, v9.8b + abs v13.4h, v21.4h + abs v4.2s, v0.2s + +// CHECK: abs v0.16b, v31.16b // encoding: [0xe0,0xbb,0x20,0x4e] +// CHECK: abs v2.8h, v4.8h // encoding: [0x82,0xb8,0x60,0x4e] +// CHECK: abs v6.4s, v8.4s // encoding: [0x06,0xb9,0xa0,0x4e] +// CHECK: abs v6.2d, v8.2d // encoding: [0x06,0xb9,0xe0,0x4e] +// CHECK: abs v1.8b, v9.8b // encoding: [0x21,0xb9,0x20,0x0e] +// CHECK: abs v13.4h, v21.4h // encoding: [0xad,0xba,0x60,0x0e] +// CHECK: abs v4.2s, v0.2s // encoding: [0x04,0xb8,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Integer negate +//------------------------------------------------------------------------------ + + neg v0.16b, v31.16b + neg v2.8h, v4.8h + neg v6.4s, v8.4s + neg v6.2d, v8.2d + neg v1.8b, v9.8b + neg v13.4h, v21.4h + neg v4.2s, v0.2s + +// CHECK: neg v0.16b, v31.16b // encoding: [0xe0,0xbb,0x20,0x6e] +// CHECK: neg v2.8h, v4.8h // encoding: [0x82,0xb8,0x60,0x6e] +// CHECK: neg v6.4s, v8.4s // encoding: [0x06,0xb9,0xa0,0x6e] +// CHECK: neg v6.2d, v8.2d // encoding: [0x06,0xb9,0xe0,0x6e] +// CHECK: neg v1.8b, v9.8b // encoding: [0x21,0xb9,0x20,0x2e] +// CHECK: neg v13.4h, v21.4h // encoding: [0xad,0xba,0x60,0x2e] +// CHECK: neg v4.2s, v0.2s // encoding: [0x04,0xb8,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer count leading sign bits +//------------------------------------------------------------------------------ + + cls v0.16b, v31.16b + cls v2.8h, v4.8h + cls v6.4s, v8.4s + cls v1.8b, v9.8b + cls v13.4h, v21.4h + cls v4.2s, v0.2s + +// CHECK: cls v0.16b, v31.16b // encoding: [0xe0,0x4b,0x20,0x4e] +// CHECK: cls v2.8h, v4.8h // encoding: [0x82,0x48,0x60,0x4e] +// CHECK: cls v6.4s, v8.4s // encoding: [0x06,0x49,0xa0,0x4e] +// CHECK: cls v1.8b, v9.8b // encoding: [0x21,0x49,0x20,0x0e] +// CHECK: cls v13.4h, v21.4h // encoding: [0xad,0x4a,0x60,0x0e] +// CHECK: cls v4.2s, v0.2s // encoding: [0x04,0x48,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Integer count leading zeros +//------------------------------------------------------------------------------ + + clz v0.16b, v31.16b + clz v2.8h, v4.8h + clz v6.4s, v8.4s + clz v1.8b, v9.8b + clz v13.4h, v21.4h + clz v4.2s, v0.2s + +// CHECK: clz v0.16b, v31.16b // encoding: [0xe0,0x4b,0x20,0x6e] +// CHECK: clz v2.8h, v4.8h // encoding: [0x82,0x48,0x60,0x6e] +// CHECK: clz v6.4s, v8.4s // encoding: [0x06,0x49,0xa0,0x6e] +// CHECK: clz v1.8b, v9.8b // encoding: [0x21,0x49,0x20,0x2e] +// CHECK: clz v13.4h, v21.4h // encoding: [0xad,0x4a,0x60,0x2e] +// CHECK: clz v4.2s, v0.2s // encoding: [0x04,0x48,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Population count +//------------------------------------------------------------------------------ + + cnt v0.16b, v31.16b + cnt v1.8b, v9.8b + +// CHECK: cnt v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x4e] +// CHECK: cnt v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x0e] + +//------------------------------------------------------------------------------ +// Bitwise NOT +//------------------------------------------------------------------------------ + + not v0.16b, v31.16b + not v1.8b, v9.8b + +// CHECK: not v0.16b, v31.16b // encoding: [0xe0,0x5b,0x20,0x6e] +// CHECK: not v1.8b, v9.8b // encoding: [0x21,0x59,0x20,0x2e] + +//------------------------------------------------------------------------------ +// Bitwise reverse +//------------------------------------------------------------------------------ + + rbit v0.16b, v31.16b + rbit v1.8b, v9.8b + +// CHECK: rbit v0.16b, v31.16b // encoding: [0xe0,0x5b,0x60,0x6e] +// CHECK: rbit v1.8b, v9.8b // encoding: [0x21,0x59,0x60,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point absolute +//------------------------------------------------------------------------------ + + fabs v6.4s, v8.4s + fabs v6.2d, v8.2d + fabs v4.2s, v0.2s + +// CHECK: fabs v6.4s, v8.4s // encoding: [0x06,0xf9,0xa0,0x4e] +// CHECK: fabs v6.2d, v8.2d // encoding: [0x06,0xf9,0xe0,0x4e] +// CHECK: fabs v4.2s, v0.2s // encoding: [0x04,0xf8,0xa0,0x0e] + +//------------------------------------------------------------------------------ +// Floating-point negate +//------------------------------------------------------------------------------ + + fneg v6.4s, v8.4s + fneg v6.2d, v8.2d + fneg v4.2s, v0.2s + +// CHECK: fneg v6.4s, v8.4s // encoding: [0x06,0xf9,0xa0,0x6e] +// CHECK: fneg v6.2d, v8.2d // encoding: [0x06,0xf9,0xe0,0x6e] +// CHECK: fneg v4.2s, v0.2s // encoding: [0x04,0xf8,0xa0,0x2e] + +//------------------------------------------------------------------------------ +// Integer extract and narrow +//------------------------------------------------------------------------------ + + xtn2 v0.16b, v31.8h + xtn2 v2.8h, v4.4s + xtn2 v6.4s, v8.2d + xtn v1.8b, v9.8h + xtn v13.4h, v21.4s + xtn v4.2s, v0.2d + +// CHECK: xtn2 v0.16b, v31.8h // encoding: [0xe0,0x2b,0x21,0x4e] +// CHECK: xtn2 v2.8h, v4.4s // encoding: [0x82,0x28,0x61,0x4e] +// CHECK: xtn2 v6.4s, v8.2d // encoding: [0x06,0x29,0xa1,0x4e] +// CHECK: xtn v1.8b, v9.8h // encoding: [0x21,0x29,0x21,0x0e] +// CHECK: xtn v13.4h, v21.4s // encoding: [0xad,0x2a,0x61,0x0e] +// CHECK: xtn v4.2s, v0.2d // encoding: [0x04,0x28,0xa1,0x0e] + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and unsigned narrow +//------------------------------------------------------------------------------ + + sqxtun2 v0.16b, v31.8h + sqxtun2 v2.8h, v4.4s + sqxtun2 v6.4s, v8.2d + sqxtun v1.8b, v9.8h + sqxtun v13.4h, v21.4s + sqxtun v4.2s, v0.2d + +// CHECK: sqxtun2 v0.16b, v31.8h // encoding: [0xe0,0x2b,0x21,0x6e] +// CHECK: sqxtun2 v2.8h, v4.4s // encoding: [0x82,0x28,0x61,0x6e] +// CHECK: sqxtun2 v6.4s, v8.2d // encoding: [0x06,0x29,0xa1,0x6e] +// CHECK: sqxtun v1.8b, v9.8h // encoding: [0x21,0x29,0x21,0x2e] +// CHECK: sqxtun v13.4h, v21.4s // encoding: [0xad,0x2a,0x61,0x2e] +// CHECK: sqxtun v4.2s, v0.2d // encoding: [0x04,0x28,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Signed integer saturating extract and narrow +//------------------------------------------------------------------------------ + + sqxtn2 v0.16b, v31.8h + sqxtn2 v2.8h, v4.4s + sqxtn2 v6.4s, v8.2d + sqxtn v1.8b, v9.8h + sqxtn v13.4h, v21.4s + sqxtn v4.2s, v0.2d + +// CHECK: sqxtn2 v0.16b, v31.8h // encoding: [0xe0,0x4b,0x21,0x4e] +// CHECK: sqxtn2 v2.8h, v4.4s // encoding: [0x82,0x48,0x61,0x4e] +// CHECK: sqxtn2 v6.4s, v8.2d // encoding: [0x06,0x49,0xa1,0x4e] +// CHECK: sqxtn v1.8b, v9.8h // encoding: [0x21,0x49,0x21,0x0e] +// CHECK: sqxtn v13.4h, v21.4s // encoding: [0xad,0x4a,0x61,0x0e] +// CHECK: sqxtn v4.2s, v0.2d // encoding: [0x04,0x48,0xa1,0x0e] + +//------------------------------------------------------------------------------ +// Unsigned integer saturating extract and narrow +//------------------------------------------------------------------------------ + + uqxtn2 v0.16b, v31.8h + uqxtn2 v2.8h, v4.4s + uqxtn2 v6.4s, v8.2d + uqxtn v1.8b, v9.8h + uqxtn v13.4h, v21.4s + uqxtn v4.2s, v0.2d + +// CHECK: uqxtn2 v0.16b, v31.8h // encoding: [0xe0,0x4b,0x21,0x6e] +// CHECK: uqxtn2 v2.8h, v4.4s // encoding: [0x82,0x48,0x61,0x6e] +// CHECK: uqxtn2 v6.4s, v8.2d // encoding: [0x06,0x49,0xa1,0x6e] +// CHECK: uqxtn v1.8b, v9.8h // encoding: [0x21,0x49,0x21,0x2e] +// CHECK: uqxtn v13.4h, v21.4s // encoding: [0xad,0x4a,0x61,0x2e] +// CHECK: uqxtn v4.2s, v0.2d // encoding: [0x04,0x48,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Integer shift left long +//------------------------------------------------------------------------------ + + shll2 v2.8h, v4.16b, #8 + shll2 v6.4s, v8.8h, #16 + shll2 v6.2d, v8.4s, #32 + shll v2.8h, v4.8b, #8 + shll v6.4s, v8.4h, #16 + shll v6.2d, v8.2s, #32 + +// CHECK: shll2 v2.8h, v4.16b, #8 // encoding: [0x82,0x38,0x21,0x6e] +// CHECK: shll2 v6.4s, v8.8h, #16 // encoding: [0x06,0x39,0x61,0x6e] +// CHECK: shll2 v6.2d, v8.4s, #32 // encoding: [0x06,0x39,0xa1,0x6e] +// CHECK: shll v2.8h, v4.8b, #8 // encoding: [0x82,0x38,0x21,0x2e] +// CHECK: shll v6.4s, v8.4h, #16 // encoding: [0x06,0x39,0x61,0x2e] +// CHECK: shll v6.2d, v8.2s, #32 // encoding: [0x06,0x39,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert downsize +//------------------------------------------------------------------------------ + + fcvtn2 v2.8h, v4.4s + fcvtn2 v6.4s, v8.2d + fcvtn v13.4h, v21.4s + fcvtn v4.2s, v0.2d + +// CHECK: fcvtn2 v2.8h, v4.4s // encoding: [0x82,0x68,0x21,0x4e] +// CHECK: fcvtn2 v6.4s, v8.2d // encoding: [0x06,0x69,0x61,0x4e] +// CHECK: fcvtn v13.4h, v21.4s // encoding: [0xad,0x6a,0x21,0x0e] +// CHECK: fcvtn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x0e] + +//------------------------------------------------------------------------------ +// Floating-point convert downsize with inexact +//------------------------------------------------------------------------------ + + fcvtxn2 v6.4s, v8.2d + fcvtxn v4.2s, v0.2d + +// CHECK: fcvtxn2 v6.4s, v8.2d // encoding: [0x06,0x69,0x61,0x6e] +// CHECK: fcvtxn v4.2s, v0.2d // encoding: [0x04,0x68,0x61,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert upsize +//------------------------------------------------------------------------------ + + fcvtl v9.4s, v1.4h + fcvtl v0.2d, v1.2s + fcvtl2 v12.4s, v4.8h + fcvtl2 v17.2d, v28.4s + +// CHECK: fcvtl v9.4s, v1.4h // encoding: [0x29,0x78,0x21,0x0e] +// CHECK: fcvtl v0.2d, v1.2s // encoding: [0x20,0x78,0x61,0x0e] +// CHECK: fcvtl2 v12.4s, v4.8h // encoding: [0x8c,0x78,0x21,0x4e] +// CHECK: fcvtl2 v17.2d, v28.4s // encoding: [0x91,0x7b,0x61,0x4e] + +//------------------------------------------------------------------------------ +// Floating-point round to integral +//------------------------------------------------------------------------------ + + frintn v6.4s, v8.4s + frintn v6.2d, v8.2d + frintn v4.2s, v0.2s + +// CHECK: frintn v6.4s, v8.4s // encoding: [0x06,0x89,0x21,0x4e] +// CHECK: frintn v6.2d, v8.2d // encoding: [0x06,0x89,0x61,0x4e] +// CHECK: frintn v4.2s, v0.2s // encoding: [0x04,0x88,0x21,0x0e] + + frinta v6.4s, v8.4s + frinta v6.2d, v8.2d + frinta v4.2s, v0.2s + +// CHECK: frinta v6.4s, v8.4s // encoding: [0x06,0x89,0x21,0x6e] +// CHECK: frinta v6.2d, v8.2d // encoding: [0x06,0x89,0x61,0x6e] +// CHECK: frinta v4.2s, v0.2s // encoding: [0x04,0x88,0x21,0x2e] + + frintp v6.4s, v8.4s + frintp v6.2d, v8.2d + frintp v4.2s, v0.2s + +// CHECK: frintp v6.4s, v8.4s // encoding: [0x06,0x89,0xa1,0x4e] +// CHECK: frintp v6.2d, v8.2d // encoding: [0x06,0x89,0xe1,0x4e] +// CHECK: frintp v4.2s, v0.2s // encoding: [0x04,0x88,0xa1,0x0e] + + frintm v6.4s, v8.4s + frintm v6.2d, v8.2d + frintm v4.2s, v0.2s + +// CHECK: frintm v6.4s, v8.4s // encoding: [0x06,0x99,0x21,0x4e] +// CHECK: frintm v6.2d, v8.2d // encoding: [0x06,0x99,0x61,0x4e] +// CHECK: frintm v4.2s, v0.2s // encoding: [0x04,0x98,0x21,0x0e] + + frintx v6.4s, v8.4s + frintx v6.2d, v8.2d + frintx v4.2s, v0.2s + +// CHECK: frintx v6.4s, v8.4s // encoding: [0x06,0x99,0x21,0x6e] +// CHECK: frintx v6.2d, v8.2d // encoding: [0x06,0x99,0x61,0x6e] +// CHECK: frintx v4.2s, v0.2s // encoding: [0x04,0x98,0x21,0x2e] + + frintz v6.4s, v8.4s + frintz v6.2d, v8.2d + frintz v4.2s, v0.2s + +// CHECK: frintz v6.4s, v8.4s // encoding: [0x06,0x99,0xa1,0x4e] +// CHECK: frintz v6.2d, v8.2d // encoding: [0x06,0x99,0xe1,0x4e] +// CHECK: frintz v4.2s, v0.2s // encoding: [0x04,0x98,0xa1,0x0e] + + frinti v6.4s, v8.4s + frinti v6.2d, v8.2d + frinti v4.2s, v0.2s + +// CHECK: frinti v6.4s, v8.4s // encoding: [0x06,0x99,0xa1,0x6e] +// CHECK: frinti v6.2d, v8.2d // encoding: [0x06,0x99,0xe1,0x6e] +// CHECK: frinti v4.2s, v0.2s // encoding: [0x04,0x98,0xa1,0x2e] + +//------------------------------------------------------------------------------ +// Floating-point convert to integer +//------------------------------------------------------------------------------ + + fcvtns v6.4s, v8.4s + fcvtns v6.2d, v8.2d + fcvtns v4.2s, v0.2s + +// CHECK: fcvtns v6.4s, v8.4s // encoding: [0x06,0xa9,0x21,0x4e] +// CHECK: fcvtns v6.2d, v8.2d // encoding: [0x06,0xa9,0x61,0x4e] +// CHECK: fcvtns v4.2s, v0.2s // encoding: [0x04,0xa8,0x21,0x0e] + + fcvtnu v6.4s, v8.4s + fcvtnu v6.2d, v8.2d + fcvtnu v4.2s, v0.2s + +// CHECK: fcvtnu v6.4s, v8.4s // encoding: [0x06,0xa9,0x21,0x6e] +// CHECK: fcvtnu v6.2d, v8.2d // encoding: [0x06,0xa9,0x61,0x6e] +// CHECK: fcvtnu v4.2s, v0.2s // encoding: [0x04,0xa8,0x21,0x2e] + + fcvtps v6.4s, v8.4s + fcvtps v6.2d, v8.2d + fcvtps v4.2s, v0.2s + +// CHECK: fcvtps v6.4s, v8.4s // encoding: [0x06,0xa9,0xa1,0x4e] +// CHECK: fcvtps v6.2d, v8.2d // encoding: [0x06,0xa9,0xe1,0x4e] +// CHECK: fcvtps v4.2s, v0.2s // encoding: [0x04,0xa8,0xa1,0x0e] + + fcvtpu v6.4s, v8.4s + fcvtpu v6.2d, v8.2d + fcvtpu v4.2s, v0.2s + +// CHECK: fcvtpu v6.4s, v8.4s // encoding: [0x06,0xa9,0xa1,0x6e] +// CHECK: fcvtpu v6.2d, v8.2d // encoding: [0x06,0xa9,0xe1,0x6e] +// CHECK: fcvtpu v4.2s, v0.2s // encoding: [0x04,0xa8,0xa1,0x2e] + + fcvtms v6.4s, v8.4s + fcvtms v6.2d, v8.2d + fcvtms v4.2s, v0.2s + +// CHECK: fcvtms v6.4s, v8.4s // encoding: [0x06,0xb9,0x21,0x4e] +// CHECK: fcvtms v6.2d, v8.2d // encoding: [0x06,0xb9,0x61,0x4e] +// CHECK: fcvtms v4.2s, v0.2s // encoding: [0x04,0xb8,0x21,0x0e] + + fcvtmu v6.4s, v8.4s + fcvtmu v6.2d, v8.2d + fcvtmu v4.2s, v0.2s + +// CHECK: fcvtmu v6.4s, v8.4s // encoding: [0x06,0xb9,0x21,0x6e] +// CHECK: fcvtmu v6.2d, v8.2d // encoding: [0x06,0xb9,0x61,0x6e] +// CHECK: fcvtmu v4.2s, v0.2s // encoding: [0x04,0xb8,0x21,0x2e] + + fcvtzs v6.4s, v8.4s + fcvtzs v6.2d, v8.2d + fcvtzs v4.2s, v0.2s + +// CHECK: fcvtzs v6.4s, v8.4s // encoding: [0x06,0xb9,0xa1,0x4e] +// CHECK: fcvtzs v6.2d, v8.2d // encoding: [0x06,0xb9,0xe1,0x4e] +// CHECK: fcvtzs v4.2s, v0.2s // encoding: [0x04,0xb8,0xa1,0x0e] + + + fcvtzu v6.4s, v8.4s + fcvtzu v6.2d, v8.2d + fcvtzu v4.2s, v0.2s + +// CHECK: fcvtzu v6.4s, v8.4s // encoding: [0x06,0xb9,0xa1,0x6e] +// CHECK: fcvtzu v6.2d, v8.2d // encoding: [0x06,0xb9,0xe1,0x6e] +// CHECK: fcvtzu v4.2s, v0.2s // encoding: [0x04,0xb8,0xa1,0x2e] + + fcvtas v6.4s, v8.4s + fcvtas v6.2d, v8.2d + fcvtas v4.2s, v0.2s + +// CHECK: fcvtas v6.4s, v8.4s // encoding: [0x06,0xc9,0x21,0x4e] +// CHECK: fcvtas v6.2d, v8.2d // encoding: [0x06,0xc9,0x61,0x4e] +// CHECK: fcvtas v4.2s, v0.2s // encoding: [0x04,0xc8,0x21,0x0e] + + fcvtau v6.4s, v8.4s + fcvtau v6.2d, v8.2d + fcvtau v4.2s, v0.2s + +// CHECK: fcvtau v6.4s, v8.4s // encoding: [0x06,0xc9,0x21,0x6e] +// CHECK: fcvtau v6.2d, v8.2d // encoding: [0x06,0xc9,0x61,0x6e] +// CHECK: fcvtau v4.2s, v0.2s // encoding: [0x04,0xc8,0x21,0x2e] + + urecpe v6.4s, v8.4s + urecpe v4.2s, v0.2s + +// CHECK: urecpe v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x4e] +// CHECK: urecpe v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x0e] + + ursqrte v6.4s, v8.4s + ursqrte v4.2s, v0.2s + +// CHECK: ursqrte v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x6e] +// CHECK: ursqrte v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x2e] + + scvtf v6.4s, v8.4s + scvtf v6.2d, v8.2d + scvtf v4.2s, v0.2s + +// CHECK: scvtf v6.4s, v8.4s // encoding: [0x06,0xd9,0x21,0x4e] +// CHECK: scvtf v6.2d, v8.2d // encoding: [0x06,0xd9,0x61,0x4e] +// CHECK: scvtf v4.2s, v0.2s // encoding: [0x04,0xd8,0x21,0x0e] + + ucvtf v6.4s, v8.4s + ucvtf v6.2d, v8.2d + ucvtf v4.2s, v0.2s + +// CHECK: ucvtf v6.4s, v8.4s // encoding: [0x06,0xd9,0x21,0x6e] +// CHECK: ucvtf v6.2d, v8.2d // encoding: [0x06,0xd9,0x61,0x6e] +// CHECK: ucvtf v4.2s, v0.2s // encoding: [0x04,0xd8,0x21,0x2e] + + frecpe v6.4s, v8.4s + frecpe v6.2d, v8.2d + frecpe v4.2s, v0.2s + +// CHECK: frecpe v6.4s, v8.4s // encoding: [0x06,0xd9,0xa1,0x4e] +// CHECK: frecpe v6.2d, v8.2d // encoding: [0x06,0xd9,0xe1,0x4e] +// CHECK: frecpe v4.2s, v0.2s // encoding: [0x04,0xd8,0xa1,0x0e] + + frsqrte v6.4s, v8.4s + frsqrte v6.2d, v8.2d + frsqrte v4.2s, v0.2s + +// CHECK: frsqrte v6.4s, v8.4s // encoding: [0x06,0xd9,0xa1,0x6e] +// CHECK: frsqrte v6.2d, v8.2d // encoding: [0x06,0xd9,0xe1,0x6e] +// CHECK: frsqrte v4.2s, v0.2s // encoding: [0x04,0xd8,0xa1,0x2e] + + fsqrt v6.4s, v8.4s + fsqrt v6.2d, v8.2d + fsqrt v4.2s, v0.2s + +// CHECK: fsqrt v6.4s, v8.4s // encoding: [0x06,0xf9,0xa1,0x6e] +// CHECK: fsqrt v6.2d, v8.2d // encoding: [0x06,0xf9,0xe1,0x6e] +// CHECK: fsqrt v4.2s, v0.2s // encoding: [0x04,0xf8,0xa1,0x2e] + + diff --git a/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s new file mode 100644 index 000000000000..8dc271e38d2c --- /dev/null +++ b/test/MC/AArch64/neon-simd-post-ldst-multi-elem.s @@ -0,0 +1,389 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from one register (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b}, [x0], x1 + ld1 {v15.8h}, [x15], x2 + ld1 {v31.4s}, [sp], #16 + ld1 {v0.2d}, [x0], #16 + ld1 {v0.8b}, [x0], x2 + ld1 {v15.4h}, [x15], x3 + ld1 {v31.2s}, [sp], #8 + ld1 {v0.1d}, [x0], #8 +// CHECK: ld1 {v0.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x70,0xc1,0x4c] +// CHECK: ld1 {v15.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x75,0xc2,0x4c] +// CHECK: ld1 {v31.4s}, [sp], #16 +// CHECK: // encoding: [0xff,0x7b,0xdf,0x4c] +// CHECK: ld1 {v0.2d}, [x0], #16 +// CHECK: // encoding: [0x00,0x7c,0xdf,0x4c] +// CHECK: ld1 {v0.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x70,0xc2,0x0c] +// CHECK: ld1 {v15.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x75,0xc3,0x0c] +// CHECK: ld1 {v31.2s}, [sp], #8 +// CHECK: // encoding: [0xff,0x7b,0xdf,0x0c] +// CHECK: ld1 {v0.1d}, [x0], #8 +// CHECK: // encoding: [0x00,0x7c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b}, [x0], x1 + ld1 {v15.8h, v16.8h}, [x15], x2 + ld1 {v31.4s, v0.4s}, [sp], #32 + ld1 {v0.2d, v1.2d}, [x0], #32 + ld1 {v0.8b, v1.8b}, [x0], x2 + ld1 {v15.4h, v16.4h}, [x15], x3 + ld1 {v31.2s, v0.2s}, [sp], #16 + ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: ld1 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0xa0,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0xa5,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0xab,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0xac,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0xa0,0xc2,0x0c] +// CHECK: ld1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0xa5,0xc3,0x0c] +// CHECK: ld1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0xab,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: // encoding: [0x00,0xac,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 + ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 + ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 + ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 + ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 + ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 + ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: ld1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x60,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x65,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x6b,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x6c,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x60,0xc2,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x65,0xc3,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x6b,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: // encoding: [0x00,0x6c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 1-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 + ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: ld1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x20,0xc1,0x4c] +// CHECK: ld1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x25,0xc2,0x4c] +// CHECK: ld1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x2b,0xdf,0x4c] +// CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x2c,0xdf,0x4c] +// CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x20,0xc3,0x0c] +// CHECK: ld1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x25,0xc4,0x0c] +// CHECK: ld1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x2b,0xdf,0x0c] +// CHECK: ld1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: // encoding: [0x00,0x2c,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 2-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld2 {v0.16b, v1.16b}, [x0], x1 + ld2 {v15.8h, v16.8h}, [x15], x2 + ld2 {v31.4s, v0.4s}, [sp], #32 + ld2 {v0.2d, v1.2d}, [x0], #32 + ld2 {v0.8b, v1.8b}, [x0], x2 + ld2 {v15.4h, v16.4h}, [x15], x3 + ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x80,0xc1,0x4c] +// CHECK: ld2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x85,0xc2,0x4c] +// CHECK: ld2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0x8b,0xdf,0x4c] +// CHECK: ld2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0x8c,0xdf,0x4c] +// CHECK: ld2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x80,0xc2,0x0c] +// CHECK: ld2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x85,0xc3,0x0c] +// CHECK: ld2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0x8b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 3-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 + ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 + ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 + ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 + ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 + ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: ld3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x40,0xc1,0x4c] +// CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x45,0xc2,0x4c] +// CHECK: ld3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x4b,0xdf,0x4c] +// CHECK: ld3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x4c,0xdf,0x4c] +// CHECK: ld3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x40,0xc2,0x0c] +// CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x45,0xc3,0x0c] +// CHECK: ld3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x4b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Load multiple 4-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x00,0xc1,0x4c] +// CHECK: ld4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x05,0xc2,0x4c] +// CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x0b,0xdf,0x4c] +// CHECK: ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x0c,0xdf,0x4c] +// CHECK: ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x00,0xc3,0x0c] +// CHECK: ld4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x05,0xc4,0x0c] +// CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x0b,0xdf,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from one register (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b}, [x0], x1 + st1 {v15.8h}, [x15], x2 + st1 {v31.4s}, [sp], #16 + st1 {v0.2d}, [x0], #16 + st1 {v0.8b}, [x0], x2 + st1 {v15.4h}, [x15], x3 + st1 {v31.2s}, [sp], #8 + st1 {v0.1d}, [x0], #8 +// CHECK: st1 {v0.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x70,0x81,0x4c] +// CHECK: st1 {v15.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x75,0x82,0x4c] +// CHECK: st1 {v31.4s}, [sp], #16 +// CHECK: // encoding: [0xff,0x7b,0x9f,0x4c] +// CHECK: st1 {v0.2d}, [x0], #16 +// CHECK: // encoding: [0x00,0x7c,0x9f,0x4c] +// CHECK: st1 {v0.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x70,0x82,0x0c] +// CHECK: st1 {v15.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x75,0x83,0x0c] +// CHECK: st1 {v31.2s}, [sp], #8 +// CHECK: // encoding: [0xff,0x7b,0x9f,0x0c] +// CHECK: st1 {v0.1d}, [x0], #8 +// CHECK: // encoding: [0x00,0x7c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b}, [x0], x1 + st1 {v15.8h, v16.8h}, [x15], x2 + st1 {v31.4s, v0.4s}, [sp], #32 + st1 {v0.2d, v1.2d}, [x0], #32 + st1 {v0.8b, v1.8b}, [x0], x2 + st1 {v15.4h, v16.4h}, [x15], x3 + st1 {v31.2s, v0.2s}, [sp], #16 + st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: st1 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0xa0,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0xa5,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0xab,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0xac,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0xa0,0x82,0x0c] +// CHECK: st1 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0xa5,0x83,0x0c] +// CHECK: st1 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0xab,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d}, [x0], #16 +// CHECK: // encoding: [0x00,0xac,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 + st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 + st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 + st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 + st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 + st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 + st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: st1 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x60,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x65,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x6b,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x6c,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x60,0x82,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x65,0x83,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x6b,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d}, [x0], #24 +// CHECK: // encoding: [0x00,0x6c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 1-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 + st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: st1 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x20,0x81,0x4c] +// CHECK: st1 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x25,0x82,0x4c] +// CHECK: st1 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x2b,0x9f,0x4c] +// CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x2c,0x9f,0x4c] +// CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x20,0x83,0x0c] +// CHECK: st1 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x25,0x84,0x0c] +// CHECK: st1 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x2b,0x9f,0x0c] +// CHECK: st1 {v0.1d, v1.1d, v2.1d, v3.1d}, [x0], #32 +// CHECK: // encoding: [0x00,0x2c,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 2-element structures from two consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st2 {v0.16b, v1.16b}, [x0], x1 + st2 {v15.8h, v16.8h}, [x15], x2 + st2 {v31.4s, v0.4s}, [sp], #32 + st2 {v0.2d, v1.2d}, [x0], #32 + st2 {v0.8b, v1.8b}, [x0], x2 + st2 {v15.4h, v16.4h}, [x15], x3 + st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: st2 {v0.16b, v1.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x80,0x81,0x4c] +// CHECK: st2 {v15.8h, v16.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x85,0x82,0x4c] +// CHECK: st2 {v31.4s, v0.4s}, [sp], #32 +// CHECK: // encoding: [0xff,0x8b,0x9f,0x4c] +// CHECK: st2 {v0.2d, v1.2d}, [x0], #32 +// CHECK: // encoding: [0x00,0x8c,0x9f,0x4c] +// CHECK: st2 {v0.8b, v1.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x80,0x82,0x0c] +// CHECK: st2 {v15.4h, v16.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x85,0x83,0x0c] +// CHECK: st2 {v31.2s, v0.2s}, [sp], #16 +// CHECK: // encoding: [0xff,0x8b,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 3-element structures from three consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 + st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 + st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 + st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 + st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 + st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 + st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: st3 {v0.16b, v1.16b, v2.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x40,0x81,0x4c] +// CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x45,0x82,0x4c] +// CHECK: st3 {v31.4s, v0.4s, v1.4s}, [sp], #48 +// CHECK: // encoding: [0xff,0x4b,0x9f,0x4c] +// CHECK: st3 {v0.2d, v1.2d, v2.2d}, [x0], #48 +// CHECK: // encoding: [0x00,0x4c,0x9f,0x4c] +// CHECK: st3 {v0.8b, v1.8b, v2.8b}, [x0], x2 +// CHECK: // encoding: [0x00,0x40,0x82,0x0c] +// CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15], x3 +// CHECK: // encoding: [0xef,0x45,0x83,0x0c] +// CHECK: st3 {v31.2s, v0.2s, v1.2s}, [sp], #24 +// CHECK: // encoding: [0xff,0x4b,0x9f,0x0c] + +//------------------------------------------------------------------------------ +// Store multiple 4-element structures from four consecutive registers +// (post-index) +//------------------------------------------------------------------------------ + st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 + st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 + st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 + st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 + st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 + st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 + st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x0], x1 +// CHECK: // encoding: [0x00,0x00,0x81,0x4c] +// CHECK: st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x15], x2 +// CHECK: // encoding: [0xef,0x05,0x82,0x4c] +// CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +// CHECK: // encoding: [0xff,0x0b,0x9f,0x4c] +// CHECK: st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0], #64 +// CHECK: // encoding: [0x00,0x0c,0x9f,0x4c] +// CHECK: st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +// CHECK: // encoding: [0x00,0x00,0x83,0x0c] +// CHECK: st4 {v15.4h, v16.4h, v17.4h, v18.4h}, [x15], x4 +// CHECK: // encoding: [0xef,0x05,0x84,0x0c] +// CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], #32 +// CHECK: // encoding: [0xff,0x0b,0x9f,0x0c] diff --git a/test/MC/AArch64/neon-simd-shift.s b/test/MC/AArch64/neon-simd-shift.s new file mode 100644 index 000000000000..a16432324efc --- /dev/null +++ b/test/MC/AArch64/neon-simd-shift.s @@ -0,0 +1,434 @@ +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + sshr v0.8b, v1.8b, #3 + sshr v0.4h, v1.4h, #3 + sshr v0.2s, v1.2s, #3 + sshr v0.16b, v1.16b, #3 + sshr v0.8h, v1.8h, #3 + sshr v0.4s, v1.4s, #3 + sshr v0.2d, v1.2d, #3 +// CHECK: sshr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x0f] +// CHECK: sshr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x0f] +// CHECK: sshr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x0f] +// CHECK: sshr v0.16b, v1.16b, #3 // encoding: [0x20,0x04,0x0d,0x4f] +// CHECK: sshr v0.8h, v1.8h, #3 // encoding: [0x20,0x04,0x1d,0x4f] +// CHECK: sshr v0.4s, v1.4s, #3 // encoding: [0x20,0x04,0x3d,0x4f] +// CHECK: sshr v0.2d, v1.2d, #3 // encoding: [0x20,0x04,0x7d,0x4f] + +//------------------------------------------------------------------------------ +// Vector shift right by immediate +//------------------------------------------------------------------------------ + ushr v0.8b, v1.8b, #3 + ushr v0.4h, v1.4h, #3 + ushr v0.2s, v1.2s, #3 + ushr v0.16b, v1.16b, #3 + ushr v0.8h, v1.8h, #3 + ushr v0.4s, v1.4s, #3 + ushr v0.2d, v1.2d, #3 + +// CHECK: ushr v0.8b, v1.8b, #3 // encoding: [0x20,0x04,0x0d,0x2f] +// CHECK: ushr v0.4h, v1.4h, #3 // encoding: [0x20,0x04,0x1d,0x2f] +// CHECK: ushr v0.2s, v1.2s, #3 // encoding: [0x20,0x04,0x3d,0x2f] +// CHECK: ushr v0.16b, v1.16b, #3 // encoding: [0x20,0x04,0x0d,0x6f] +// CHECK: ushr v0.8h, v1.8h, #3 // encoding: [0x20,0x04,0x1d,0x6f] +// CHECK: ushr v0.4s, v1.4s, #3 // encoding: [0x20,0x04,0x3d,0x6f] +// CHECK: ushr v0.2d, v1.2d, #3 // encoding: [0x20,0x04,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ssra v0.8b, v1.8b, #3 + ssra v0.4h, v1.4h, #3 + ssra v0.2s, v1.2s, #3 + ssra v0.16b, v1.16b, #3 + ssra v0.8h, v1.8h, #3 + ssra v0.4s, v1.4s, #3 + ssra v0.2d, v1.2d, #3 + +// CHECK: ssra v0.8b, v1.8b, #3 // encoding: [0x20,0x14,0x0d,0x0f] +// CHECK: ssra v0.4h, v1.4h, #3 // encoding: [0x20,0x14,0x1d,0x0f] +// CHECK: ssra v0.2s, v1.2s, #3 // encoding: [0x20,0x14,0x3d,0x0f] +// CHECK: ssra v0.16b, v1.16b, #3 // encoding: [0x20,0x14,0x0d,0x4f] +// CHECK: ssra v0.8h, v1.8h, #3 // encoding: [0x20,0x14,0x1d,0x4f] +// CHECK: ssra v0.4s, v1.4s, #3 // encoding: [0x20,0x14,0x3d,0x4f] +// CHECK: ssra v0.2d, v1.2d, #3 // encoding: [0x20,0x14,0x7d,0x4f] + +//------------------------------------------------------------------------------ +// Vector shift right and accumulate by immediate +//------------------------------------------------------------------------------ + usra v0.8b, v1.8b, #3 + usra v0.4h, v1.4h, #3 + usra v0.2s, v1.2s, #3 + usra v0.16b, v1.16b, #3 + usra v0.8h, v1.8h, #3 + usra v0.4s, v1.4s, #3 + usra v0.2d, v1.2d, #3 + +// CHECK: usra v0.8b, v1.8b, #3 // encoding: [0x20,0x14,0x0d,0x2f] +// CHECK: usra v0.4h, v1.4h, #3 // encoding: [0x20,0x14,0x1d,0x2f] +// CHECK: usra v0.2s, v1.2s, #3 // encoding: [0x20,0x14,0x3d,0x2f] +// CHECK: usra v0.16b, v1.16b, #3 // encoding: [0x20,0x14,0x0d,0x6f] +// CHECK: usra v0.8h, v1.8h, #3 // encoding: [0x20,0x14,0x1d,0x6f] +// CHECK: usra v0.4s, v1.4s, #3 // encoding: [0x20,0x14,0x3d,0x6f] +// CHECK: usra v0.2d, v1.2d, #3 // encoding: [0x20,0x14,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Vector rounding shift right by immediate +//------------------------------------------------------------------------------ + srshr v0.8b, v1.8b, #3 + srshr v0.4h, v1.4h, #3 + srshr v0.2s, v1.2s, #3 + srshr v0.16b, v1.16b, #3 + srshr v0.8h, v1.8h, #3 + srshr v0.4s, v1.4s, #3 + srshr v0.2d, v1.2d, #3 + +// CHECK: srshr v0.8b, v1.8b, #3 // encoding: [0x20,0x24,0x0d,0x0f] +// CHECK: srshr v0.4h, v1.4h, #3 // encoding: [0x20,0x24,0x1d,0x0f] +// CHECK: srshr v0.2s, v1.2s, #3 // encoding: [0x20,0x24,0x3d,0x0f] +// CHECK: srshr v0.16b, v1.16b, #3 // encoding: [0x20,0x24,0x0d,0x4f] +// CHECK: srshr v0.8h, v1.8h, #3 // encoding: [0x20,0x24,0x1d,0x4f] +// CHECK: srshr v0.4s, v1.4s, #3 // encoding: [0x20,0x24,0x3d,0x4f] +// CHECK: srshr v0.2d, v1.2d, #3 // encoding: [0x20,0x24,0x7d,0x4f] + + +//------------------------------------------------------------------------------ +// Vecotr rounding shift right by immediate +//------------------------------------------------------------------------------ + urshr v0.8b, v1.8b, #3 + urshr v0.4h, v1.4h, #3 + urshr v0.2s, v1.2s, #3 + urshr v0.16b, v1.16b, #3 + urshr v0.8h, v1.8h, #3 + urshr v0.4s, v1.4s, #3 + urshr v0.2d, v1.2d, #3 + +// CHECK: urshr v0.8b, v1.8b, #3 // encoding: [0x20,0x24,0x0d,0x2f] +// CHECK: urshr v0.4h, v1.4h, #3 // encoding: [0x20,0x24,0x1d,0x2f] +// CHECK: urshr v0.2s, v1.2s, #3 // encoding: [0x20,0x24,0x3d,0x2f] +// CHECK: urshr v0.16b, v1.16b, #3 // encoding: [0x20,0x24,0x0d,0x6f] +// CHECK: urshr v0.8h, v1.8h, #3 // encoding: [0x20,0x24,0x1d,0x6f] +// CHECK: urshr v0.4s, v1.4s, #3 // encoding: [0x20,0x24,0x3d,0x6f] +// CHECK: urshr v0.2d, v1.2d, #3 // encoding: [0x20,0x24,0x7d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + srsra v0.8b, v1.8b, #3 + srsra v0.4h, v1.4h, #3 + srsra v0.2s, v1.2s, #3 + srsra v0.16b, v1.16b, #3 + srsra v0.8h, v1.8h, #3 + srsra v0.4s, v1.4s, #3 + srsra v0.2d, v1.2d, #3 + +// CHECK: srsra v0.8b, v1.8b, #3 // encoding: [0x20,0x34,0x0d,0x0f] +// CHECK: srsra v0.4h, v1.4h, #3 // encoding: [0x20,0x34,0x1d,0x0f] +// CHECK: srsra v0.2s, v1.2s, #3 // encoding: [0x20,0x34,0x3d,0x0f] +// CHECK: srsra v0.16b, v1.16b, #3 // encoding: [0x20,0x34,0x0d,0x4f] +// CHECK: srsra v0.8h, v1.8h, #3 // encoding: [0x20,0x34,0x1d,0x4f] +// CHECK: srsra v0.4s, v1.4s, #3 // encoding: [0x20,0x34,0x3d,0x4f] +// CHECK: srsra v0.2d, v1.2d, #3 // encoding: [0x20,0x34,0x7d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector rounding shift right and accumulate by immediate +//------------------------------------------------------------------------------ + ursra v0.8b, v1.8b, #3 + ursra v0.4h, v1.4h, #3 + ursra v0.2s, v1.2s, #3 + ursra v0.16b, v1.16b, #3 + ursra v0.8h, v1.8h, #3 + ursra v0.4s, v1.4s, #3 + ursra v0.2d, v1.2d, #3 + +// CHECK: ursra v0.8b, v1.8b, #3 // encoding: [0x20,0x34,0x0d,0x2f] +// CHECK: ursra v0.4h, v1.4h, #3 // encoding: [0x20,0x34,0x1d,0x2f] +// CHECK: ursra v0.2s, v1.2s, #3 // encoding: [0x20,0x34,0x3d,0x2f] +// CHECK: ursra v0.16b, v1.16b, #3 // encoding: [0x20,0x34,0x0d,0x6f] +// CHECK: ursra v0.8h, v1.8h, #3 // encoding: [0x20,0x34,0x1d,0x6f] +// CHECK: ursra v0.4s, v1.4s, #3 // encoding: [0x20,0x34,0x3d,0x6f] +// CHECK: ursra v0.2d, v1.2d, #3 // encoding: [0x20,0x34,0x7d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift right and insert by immediate +//------------------------------------------------------------------------------ + sri v0.8b, v1.8b, #3 + sri v0.4h, v1.4h, #3 + sri v0.2s, v1.2s, #3 + sri v0.16b, v1.16b, #3 + sri v0.8h, v1.8h, #3 + sri v0.4s, v1.4s, #3 + sri v0.2d, v1.2d, #3 + +// CHECK: sri v0.8b, v1.8b, #3 // encoding: [0x20,0x44,0x0d,0x2f] +// CHECK: sri v0.4h, v1.4h, #3 // encoding: [0x20,0x44,0x1d,0x2f] +// CHECK: sri v0.2s, v1.2s, #3 // encoding: [0x20,0x44,0x3d,0x2f] +// CHECK: sri v0.16b, v1.16b, #3 // encoding: [0x20,0x44,0x0d,0x6f] +// CHECK: sri v0.8h, v1.8h, #3 // encoding: [0x20,0x44,0x1d,0x6f] +// CHECK: sri v0.4s, v1.4s, #3 // encoding: [0x20,0x44,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift left and insert by immediate +//------------------------------------------------------------------------------ + sli v0.8b, v1.8b, #3 + sli v0.4h, v1.4h, #3 + sli v0.2s, v1.2s, #3 + sli v0.16b, v1.16b, #3 + sli v0.8h, v1.8h, #3 + sli v0.4s, v1.4s, #3 + sli v0.2d, v1.2d, #3 + +// CHECK: sli v0.8b, v1.8b, #3 // encoding: [0x20,0x54,0x0b,0x2f] +// CHECK: sli v0.4h, v1.4h, #3 // encoding: [0x20,0x54,0x13,0x2f] +// CHECK: sli v0.2s, v1.2s, #3 // encoding: [0x20,0x54,0x23,0x2f] +// CHECK: sli v0.16b, v1.16b, #3 // encoding: [0x20,0x54,0x0b,0x6f] +// CHECK: sli v0.8h, v1.8h, #3 // encoding: [0x20,0x54,0x13,0x6f] +// CHECK: sli v0.4s, v1.4s, #3 // encoding: [0x20,0x54,0x23,0x6f] +// CHECK: sli v0.2d, v1.2d, #3 // encoding: [0x20,0x54,0x43,0x6f] + +//------------------------------------------------------------------------------ +// Vector saturating shift left unsigned by immediate +//------------------------------------------------------------------------------ + sqshlu v0.8b, v1.8b, #3 + sqshlu v0.4h, v1.4h, #3 + sqshlu v0.2s, v1.2s, #3 + sqshlu v0.16b, v1.16b, #3 + sqshlu v0.8h, v1.8h, #3 + sqshlu v0.4s, v1.4s, #3 + sqshlu v0.2d, v1.2d, #3 + +// CHECK: sqshlu v0.8b, v1.8b, #3 // encoding: [0x20,0x64,0x0b,0x2f] +// CHECK: sqshlu v0.4h, v1.4h, #3 // encoding: [0x20,0x64,0x13,0x2f] +// CHECK: sqshlu v0.2s, v1.2s, #3 // encoding: [0x20,0x64,0x23,0x2f] +// CHECK: sqshlu v0.16b, v1.16b, #3 // encoding: [0x20,0x64,0x0b,0x6f] +// CHECK: sqshlu v0.8h, v1.8h, #3 // encoding: [0x20,0x64,0x13,0x6f] +// CHECK: sqshlu v0.4s, v1.4s, #3 // encoding: [0x20,0x64,0x23,0x6f] +// CHECK: sqshlu v0.2d, v1.2d, #3 // encoding: [0x20,0x64,0x43,0x6f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + sqshl v0.8b, v1.8b, #3 + sqshl v0.4h, v1.4h, #3 + sqshl v0.2s, v1.2s, #3 + sqshl v0.16b, v1.16b, #3 + sqshl v0.8h, v1.8h, #3 + sqshl v0.4s, v1.4s, #3 + sqshl v0.2d, v1.2d, #3 + +// CHECK: sqshl v0.8b, v1.8b, #3 // encoding: [0x20,0x74,0x0b,0x0f] +// CHECK: sqshl v0.4h, v1.4h, #3 // encoding: [0x20,0x74,0x13,0x0f] +// CHECK: sqshl v0.2s, v1.2s, #3 // encoding: [0x20,0x74,0x23,0x0f] +// CHECK: sqshl v0.16b, v1.16b, #3 // encoding: [0x20,0x74,0x0b,0x4f] +// CHECK: sqshl v0.8h, v1.8h, #3 // encoding: [0x20,0x74,0x13,0x4f] +// CHECK: sqshl v0.4s, v1.4s, #3 // encoding: [0x20,0x74,0x23,0x4f] +// CHECK: sqshl v0.2d, v1.2d, #3 // encoding: [0x20,0x74,0x43,0x4f] + + + +//------------------------------------------------------------------------------ +// Vector saturating shift left by immediate +//------------------------------------------------------------------------------ + uqshl v0.8b, v1.8b, #3 + uqshl v0.4h, v1.4h, #3 + uqshl v0.2s, v1.2s, #3 + uqshl v0.16b, v1.16b, #3 + uqshl v0.8h, v1.8h, #3 + uqshl v0.4s, v1.4s, #3 + uqshl v0.2d, v1.2d, #3 + +// CHECK: uqshl v0.8b, v1.8b, #3 // encoding: [0x20,0x74,0x0b,0x2f] +// CHECK: uqshl v0.4h, v1.4h, #3 // encoding: [0x20,0x74,0x13,0x2f] +// CHECK: uqshl v0.2s, v1.2s, #3 // encoding: [0x20,0x74,0x23,0x2f] +// CHECK: uqshl v0.16b, v1.16b, #3 // encoding: [0x20,0x74,0x0b,0x6f] +// CHECK: uqshl v0.8h, v1.8h, #3 // encoding: [0x20,0x74,0x13,0x6f] +// CHECK: uqshl v0.4s, v1.4s, #3 // encoding: [0x20,0x74,0x23,0x6f] +// CHECK: uqshl v0.2d, v1.2d, #3 // encoding: [0x20,0x74,0x43,0x6f] + + +//------------------------------------------------------------------------------ +// Vector shift right narrow by immediate +//------------------------------------------------------------------------------ + shrn v0.8b, v1.8h, #3 + shrn v0.4h, v1.4s, #3 + shrn v0.2s, v1.2d, #3 + shrn2 v0.16b, v1.8h, #3 + shrn2 v0.8h, v1.4s, #3 + shrn2 v0.4s, v1.2d, #3 + +// CHECK: shrn v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x0f] +// CHECK: shrn v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x0f] +// CHECK: shrn v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x0f] +// CHECK: shrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x4f] +// CHECK: shrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x4f] +// CHECK: shrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x4f] + +//------------------------------------------------------------------------------ +// Vector saturating shift right unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqshrun v0.8b, v1.8h, #3 + sqshrun v0.4h, v1.4s, #3 + sqshrun v0.2s, v1.2d, #3 + sqshrun2 v0.16b, v1.8h, #3 + sqshrun2 v0.8h, v1.4s, #3 + sqshrun2 v0.4s, v1.2d, #3 + +// CHECK: sqshrun v0.8b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x2f] +// CHECK: sqshrun v0.4h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x2f] +// CHECK: sqshrun v0.2s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x2f] +// CHECK: sqshrun2 v0.16b, v1.8h, #3 // encoding: [0x20,0x84,0x0d,0x6f] +// CHECK: sqshrun2 v0.8h, v1.4s, #3 // encoding: [0x20,0x84,0x1d,0x6f] +// CHECK: sqshrun2 v0.4s, v1.2d, #3 // encoding: [0x20,0x84,0x3d,0x6f] + +//------------------------------------------------------------------------------ +// Vector rounding shift right narrow by immediate +//------------------------------------------------------------------------------ + rshrn v0.8b, v1.8h, #3 + rshrn v0.4h, v1.4s, #3 + rshrn v0.2s, v1.2d, #3 + rshrn2 v0.16b, v1.8h, #3 + rshrn2 v0.8h, v1.4s, #3 + rshrn2 v0.4s, v1.2d, #3 + +// CHECK: rshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x0f] +// CHECK: rshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x0f] +// CHECK: rshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x0f] +// CHECK: rshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x4f] +// CHECK: rshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x4f] +// CHECK: rshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded unsigned narrow by immediate +//------------------------------------------------------------------------------ + sqrshrun v0.8b, v1.8h, #3 + sqrshrun v0.4h, v1.4s, #3 + sqrshrun v0.2s, v1.2d, #3 + sqrshrun2 v0.16b, v1.8h, #3 + sqrshrun2 v0.8h, v1.4s, #3 + sqrshrun2 v0.4s, v1.2d, #3 + +// CHECK: sqrshrun v0.8b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x2f] +// CHECK: sqrshrun v0.4h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x2f] +// CHECK: sqrshrun v0.2s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x2f] +// CHECK: sqrshrun2 v0.16b, v1.8h, #3 // encoding: [0x20,0x8c,0x0d,0x6f] +// CHECK: sqrshrun2 v0.8h, v1.4s, #3 // encoding: [0x20,0x8c,0x1d,0x6f] +// CHECK: sqrshrun2 v0.4s, v1.2d, #3 // encoding: [0x20,0x8c,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + sqshrn v0.8b, v1.8h, #3 + sqshrn v0.4h, v1.4s, #3 + sqshrn v0.2s, v1.2d, #3 + sqshrn2 v0.16b, v1.8h, #3 + sqshrn2 v0.8h, v1.4s, #3 + sqshrn2 v0.4s, v1.2d, #3 + +// CHECK: sqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x0f] +// CHECK: sqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x0f] +// CHECK: sqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x0f] +// CHECK: sqshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x4f] +// CHECK: sqshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x4f] +// CHECK: sqshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right narrow by immediate +//------------------------------------------------------------------------------ + uqshrn v0.8b, v1.8h, #3 + uqshrn v0.4h, v1.4s, #3 + uqshrn v0.2s, v1.2d, #3 + uqshrn2 v0.16b, v1.8h, #3 + uqshrn2 v0.8h, v1.4s, #3 + uqshrn2 v0.4s, v1.2d, #3 + +// CHECK: uqshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x2f] +// CHECK: uqshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x2f] +// CHECK: uqshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x2f] +// CHECK: uqshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x94,0x0d,0x6f] +// CHECK: uqshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x94,0x1d,0x6f] +// CHECK: uqshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x94,0x3d,0x6f] + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + sqrshrn v0.8b, v1.8h, #3 + sqrshrn v0.4h, v1.4s, #3 + sqrshrn v0.2s, v1.2d, #3 + sqrshrn2 v0.16b, v1.8h, #3 + sqrshrn2 v0.8h, v1.4s, #3 + sqrshrn2 v0.4s, v1.2d, #3 + +// CHECK: sqrshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x0f] +// CHECK: sqrshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x0f] +// CHECK: sqrshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x0f] +// CHECK: sqrshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x4f] +// CHECK: sqrshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x4f] +// CHECK: sqrshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x4f] + + +//------------------------------------------------------------------------------ +// Vector saturating shift right rounded narrow by immediate +//------------------------------------------------------------------------------ + uqrshrn v0.8b, v1.8h, #3 + uqrshrn v0.4h, v1.4s, #3 + uqrshrn v0.2s, v1.2d, #3 + uqrshrn2 v0.16b, v1.8h, #3 + uqrshrn2 v0.8h, v1.4s, #3 + uqrshrn2 v0.4s, v1.2d, #3 + +// CHECK: uqrshrn v0.8b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x2f] +// CHECK: uqrshrn v0.4h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x2f] +// CHECK: uqrshrn v0.2s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x2f] +// CHECK: uqrshrn2 v0.16b, v1.8h, #3 // encoding: [0x20,0x9c,0x0d,0x6f] +// CHECK: uqrshrn2 v0.8h, v1.4s, #3 // encoding: [0x20,0x9c,0x1d,0x6f] +// CHECK: uqrshrn2 v0.4s, v1.2d, #3 // encoding: [0x20,0x9c,0x3d,0x6f] + + +//------------------------------------------------------------------------------ +// Fixed-point convert to floating-point +//------------------------------------------------------------------------------ + scvtf v0.2s, v1.2s, #3 + scvtf v0.4s, v1.4s, #3 + scvtf v0.2d, v1.2d, #3 + ucvtf v0.2s, v1.2s, #3 + ucvtf v0.4s, v1.4s, #3 + ucvtf v0.2d, v1.2d, #3 + +// CHECK: scvtf v0.2s, v1.2s, #3 // encoding: [0x20,0xe4,0x3d,0x0f] +// CHECK: scvtf v0.4s, v1.4s, #3 // encoding: [0x20,0xe4,0x3d,0x4f] +// CHECK: scvtf v0.2d, v1.2d, #3 // encoding: [0x20,0xe4,0x7d,0x4f] +// CHECK: ucvtf v0.2s, v1.2s, #3 // encoding: [0x20,0xe4,0x3d,0x2f] +// CHECK: ucvtf v0.4s, v1.4s, #3 // encoding: [0x20,0xe4,0x3d,0x6f] +// CHECK: ucvtf v0.2d, v1.2d, #3 // encoding: [0x20,0xe4,0x7d,0x6f] + +//------------------------------------------------------------------------------ +// Floating-point convert to fixed-point +//------------------------------------------------------------------------------ + fcvtzs v0.2s, v1.2s, #3 + fcvtzs v0.4s, v1.4s, #3 + fcvtzs v0.2d, v1.2d, #3 + fcvtzu v0.2s, v1.2s, #3 + fcvtzu v0.4s, v1.4s, #3 + fcvtzu v0.2d, v1.2d, #3 + + +// CHECK: fcvtzs v0.2s, v1.2s, #3 // encoding: [0x20,0xfc,0x3d,0x0f] +// CHECK: fcvtzs v0.4s, v1.4s, #3 // encoding: [0x20,0xfc,0x3d,0x4f] +// CHECK: fcvtzs v0.2d, v1.2d, #3 // encoding: [0x20,0xfc,0x7d,0x4f] +// CHECK: fcvtzu v0.2s, v1.2s, #3 // encoding: [0x20,0xfc,0x3d,0x2f] +// CHECK: fcvtzu v0.4s, v1.4s, #3 // encoding: [0x20,0xfc,0x3d,0x6f] +// CHECK: fcvtzu v0.2d, v1.2d, #3 // encoding: [0x20,0xfc,0x7d,0x6f] + diff --git a/test/MC/AArch64/neon-tbl.s b/test/MC/AArch64/neon-tbl.s new file mode 100644 index 000000000000..ff3e86b1c9b9 --- /dev/null +++ b/test/MC/AArch64/neon-tbl.s @@ -0,0 +1,56 @@ +// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s + +// Check that the assembler can handle the documented syntax for AArch64 + +//------------------------------------------------------------------------------ +// Instructions across vector registers +//------------------------------------------------------------------------------ + + tbl v0.8b, {v1.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b + tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b + tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b + +// CHECK: tbl v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x00,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x20,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x40,0x02,0x0e] +// CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x60,0x02,0x0e] +// CHECK: tbl v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x63,0x02,0x0e] + + tbl v0.16b, {v1.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b + tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b + tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b + +// CHECK: tbl v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x00,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x20,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x40,0x02,0x4e] +// CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x60,0x02,0x4e] +// CHECK: tbl v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x63,0x02,0x4e] + + tbx v0.8b, {v1.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b + tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b + tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b + +// CHECK: tbx v0.8b, {v1.16b}, v2.8b // encoding: [0x20,0x10,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b}, v2.8b // encoding: [0x20,0x30,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b // encoding: [0x20,0x50,0x02,0x0e] +// CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.8b // encoding: [0x20,0x70,0x02,0x0e] +// CHECK: tbx v0.8b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.8b // encoding: [0xe0,0x73,0x02,0x0e] + + tbx v0.16b, {v1.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b + tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b + tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b + +// CHECK: tbx v0.16b, {v1.16b}, v2.16b // encoding: [0x20,0x10,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b}, v2.16b // encoding: [0x20,0x30,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b // encoding: [0x20,0x50,0x02,0x4e] +// CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b, v4.16b}, v2.16b // encoding: [0x20,0x70,0x02,0x4e] +// CHECK: tbx v0.16b, {v30.16b, v31.16b, v0.16b, v1.16b}, v2.16b // encoding: [0xc0,0x73,0x02,0x4e] + diff --git a/test/MC/AArch64/noneon-diagnostics.s b/test/MC/AArch64/noneon-diagnostics.s new file mode 100644 index 000000000000..ea786c0ba678 --- /dev/null +++ b/test/MC/AArch64/noneon-diagnostics.s @@ -0,0 +1,28 @@ +// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=-neon < %s 2> %t +// RUN: FileCheck --check-prefix=CHECK-ERROR < %t %s + + fmla v3.4s, v12.4s, v17.4s + fmla v1.2d, v30.2d, v20.2d + fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmla v1.2d, v30.2d, v20.2d +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmla v9.2s, v9.2s, v0.2s +// CHECK-ERROR-NEXT: ^ + + fmls v3.4s, v12.4s, v17.4s + fmls v1.2d, v30.2d, v20.2d + fmls v9.2s, v9.2s, v0.2s +// CHECK-ERROR: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmls v1.2d, v30.2d, v20.2d +// CHECK-ERROR-NEXT: ^ +// CHECK-ERROR-NEXT: error: instruction requires a CPU feature not currently enabled +// CHECK-ERROR-NEXT: fmls v9.2s, v9.2s, v0.2s +// CHECK-ERROR-NEXT: ^ diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index d0e336ecaf23..f99cb41fe5e9 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -17,7 +17,7 @@ // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 // CHECK-ELF: Relocations [ -// CHECK-ELF-NEXT: Section (1) .text { +// CHECK-ELF-NEXT: Section (2) .rela.text { // CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]] // CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] // CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] @@ -30,11 +30,11 @@ movn w8, #:dtprel_g1:var // CHECK: movz x5, #:dtprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-NEXT: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] +// CHECK: movn x6, #:dtprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-NEXT: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] +// CHECK: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-NEXT: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] +// CHECK: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 // CHECK-ELF-NEXT: 0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] diff --git a/test/MC/AArch64/trace-regs-diagnostics.s b/test/MC/AArch64/trace-regs-diagnostics.s index 82ec7c0c745d..41331e7703c8 100644 --- a/test/MC/AArch64/trace-regs-diagnostics.s +++ b/test/MC/AArch64/trace-regs-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s +// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2>&1 | FileCheck %s // Write-only mrs x12, trcoslar mrs x10, trclar |