diff options
Diffstat (limited to 'test/MC/Disassembler')
50 files changed, 883 insertions, 10 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0f6aeb7052b9..ade29525937d 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,7 +1,16 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# CHECK: addpl r4, pc, #19, #8 +0x4c 0x45 0x8f 0x52 + # CHECK: b #0 -0xfe 0xff 0xff 0xea +0x00 0x00 0x00 0xea + +# CHECK: bl #7732 +0x8d 0x07 0x00 0xeb + +# CHECK: bleq #-4 +0xff 0xff 0xff 0x0b # CHECK: bfc r8, #0, #16 0x1f 0x80 0xcf 0xe7 @@ -12,6 +21,12 @@ # CHECK: mov pc, lr 0x0e 0xf0 0xa0 0xe1 +# CHECK: mov pc, #255, #2 +0xff 0xf1 0xa0 0xe3 + +# CHECK: movw r7, #4096 +0x00 0x70 0x01 0xe3 + # CHECK: cmn r0, #1 0x01 0x00 0x70 0xe3 @@ -36,6 +51,9 @@ # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 +# CHECK: ldr r5, [r7, -r10, lsl #2] +0x0a 0x51 0x17 0xe7 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 @@ -54,7 +72,7 @@ # CHECK: movt r8, #65535 0xff 0x8f 0x4f 0xe3 -# CHECK: mvnspl r7, #245, 2 +# CHECK: mvnspl r7, #245, #2 0xf5 0x71 0xf0 0x53 # CHECK-NOT: orr r7, r8, r7, rrx #0 @@ -64,9 +82,12 @@ # CHECK: pkhbt r8, r9, r10, lsl #4 0x1a 0x82 0x89 0xe6 -# CHECK-NOT: pkhbtls pc, r11, r11, lsl #0 -# CHECK: pkhbtls pc, r11, r11 -0x1b 0xf0 0x8b 0x96 +# CHECK-NOT: pkhbtls r10, r11, r11, lsl #0 +# CHECK: pkhbtls r10, r11, r11 +0x1b 0xa0 0x8b 0x96 + +# CHECK: pkhtbmi lr, r1, r6, asr #21 +0xd6 0xea 0x81 0x46 # CHECK: pop {r0, r2, r4, r6, r8, r10} 0x55 0x05 0xbd 0xe8 @@ -130,3 +151,136 @@ # CHECK: msr cpsr_fc, r0 0x00 0xf0 0x29 0xe1 + +# CHECK: msrmi cpsr_c, #241, #8 +0xf1 0xf4 0x21 0x43 + +# CHECK: rsbs r6, r7, r8 +0x08 0x60 0x77 0xe0 + +# CHECK: blxeq r5 +0x35 0xff 0x2f 0x01 + +# CHECK: bx r12 +0x1c 0xff 0x2f 0xe1 + +# CHECK: uqadd16mi r6, r11, r8 +0x18 0x60 0x6b 0x46 + +# CHECK: str r0, [sp, #4] +0x04 0x00 0x8d 0xe5 + +# CHECK: str r1, [sp] +0x00 0x10 0x8d 0xe5 + +# CHECK: ldr r3, [pc, #144] +0x90 0x30 0x9f 0xe5 + +# CHECK: ldr r3, [r0, #-4] +0x4 0x30 0x10 0xe5 + +# CHECK: ldr r5, [sp, r0, lsl #1]! +0x80 0x50 0xbd 0xe7 + +# CHECK: ldr r5, [r7], -r0, lsr #2 +0x20 0x51 0x17 0xe6 + +# CHECK: strdeq r2, r3, [r0], -r8 +0xf8 0x24 0x00 0x00 + +# CHECK: ldrdeq r2, r3, [r0], -r12 +0xdc 0x24 0x00 0x00 + +# CHECK: ldrbt r3, [r4], -r5, lsl #12 +0x05 0x36 0x74 0xe6 + +# CHECK: vcmpe.f64 d8, #0 +0xc0 0x8b 0xb5 0xee + +# CHECK: vldmdb r2!, {s7, s8, s9, s10, s11} +0x05 0x3a 0x72 0xed + +# CHECK: vldr.32 s23, [r2, #660] +0xa5 0xba 0xd2 0xed + +# CHECK: strtvc r5, [r3], r0, lsr #20 +0x20 0x5a 0xa3 0x76 + +# CHECK: stmiblo sp, {r0, r4, r8, r11, r12, pc} +0x11 0x99 0x8d 0x39 + +# CHECK: ldmdb sp, {r0, r4, r8, r11, r12, pc} +0x11 0x99 0x1d 0xe9 + +# CHECK: swpge r3, r2, [r6] +0x92 0x30 0x06 0xa1 + +# CHECK: umull r1, r2, r3, r4 +0x93 0x14 0x82 0xe0 + +# CHECK: pld [pc, #-0] +0x00 0xf0 0x1f 0xf5 + +# CHECK: pli [pc, #-0] +0x00 0xf0 0x5f 0xf4 + +# CHECK: pli [r3, r1, lsl #2] +0x01 0xf1 0xd3 0xf6 + +# CHECK: stc p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xec + +# CHECK: stc2 p2, cr4, [r9], {157} +0x9d 0x42 0x89 0xfc + +# CHECK: blx #60 +0x0f 0x00 0x00 0xfa + +# CHECK-NOT: adcs r10, r8, r0, asr #6 +# CHECK: adcshi r10, r8, r0, asr #6 +0x40 0xa3 0xb8 0x80 + +# CHECK: adcshi r10, r8, r0, asr r3 +0x50 0xa3 0xb8 0x80 + +# CHECK: streq r1, [sp], #-1567 +0x1f 0x16 0xd 0x4 + +# CHECK: mrchs p2, #3, r11, c13, c6, #6 +0xd6 0xb2 0x7d 0x2e + +# CHECK: smlsldx r4, r12, r11, r4 +0x7b 0x44 0x4c 0xe7 + +# CHECK: lsl r3, r2, r1 +0x12 0x31 0xa0 0xe1 + +# CHECK: sxtab r9, r8, r5 +0x75 0x90 0xa8 0xe6 + +# CHECK: sxtb r9, r5, ror #8 +0x75 0x94 0xaf 0xe6 + +# CHECK: bfc r5, #0, #16 +0x1f 0x50 0xcf 0xe7 + +# CHECK: bfi r5, r6, #0, #16 +0x16 0x50 0xcf 0xe7 + +# CHECK: sbfx r5, r6, #8, #8 +0x56 0x54 0xa7 0xe7 + +# CHECK: rsb pc, r5, r0 +0x00 0xf0 0x65 0xe0 + +# CHECK: uqadd8 r5, r6, r7 +0x97 0x5f 0x66 0xe6 + +# CHECK: uqsax r5, r6, r7 +0x57 0x5f 0x66 0xe6 + +# CHECK: smmlareq r0, r0, r0, r0 +0x30 0x00 0x50 0x07 + +# CHECK: nop +0x00 0xf0 0x20 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt new file mode 100644 index 000000000000..ca0c1abb77b7 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE; +0x16 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt new file mode 100644 index 000000000000..66c43c219780 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if cond = '1110' then UNDEFINED +0x6f 0xde diff --git a/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt new file mode 100644 index 000000000000..10748e9b1269 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-CPS2p-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# invalid imod value (0b01) +0xc0 0x67 0x4 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt new file mode 100644 index 000000000000..5202217b6a71 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# invalid (imod, M, iflags) combination +0x93 0x1c 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt new file mode 100644 index 000000000000..0a4be6826ccd --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0xbf 0xf3 0x51 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt new file mode 100644 index 000000000000..afa2baff615d --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. +# Reject invalid encodings. +# +# See also A8.6.42 DSB +# All other encodings of option are reserved. It is IMPLEMENTATION DEFINED whether options +# other than SY are implemented. All unsupported and reserved options must execute as a full +# system DSB operation, but software must not rely on this behavior. +0x40 0xf0 0x7f 0xf5 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt new file mode 100644 index 000000000000..b966a9d773c2 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined. +0x92 0xb4 0x1f 0xdc + diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt new file mode 100644 index 000000000000..7a35c2d6ce0f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == 15 || n == t) then UNPREDICTABLE +0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt new file mode 100644 index 000000000000..da2e6bed8615 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.66 LDRD (immediate) +# if Rn = '1111' then SEE LDRD (literal) +# A8.6.67 LDRD (literal) +# Inst{21} = 0 +0xff 0xe9 0x0 0xeb diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt new file mode 100644 index 000000000000..fb2ce20d2c91 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# The bytes have Inst{4} = 1, so it's not an LDRT Encoding A2 instruction. +0x10 0x51 0x37 0xe6 + + diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt new file mode 100644 index 000000000000..ad79986b2549 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR_PRE/POST has encoding Inst{4} = 0. +0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt new file mode 100644 index 000000000000..36c1124bced5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if m == 15 then UNPREDICTABLE +0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt new file mode 100644 index 000000000000..23a0b85f3615 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRrs-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# LDR (register) has encoding Inst{4} = 0. +0xba 0xae 0x9f 0x57 diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt new file mode 100644 index 000000000000..20293ada7983 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.89 LSL (register) +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x12 0xf1 0xa0 0xe1 diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt new file mode 100644 index 000000000000..d39b9c1d608e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C +0x1b 0x1b 0xa0 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt new file mode 100644 index 000000000000..0b8a0776cc41 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 then UNPREDICTABLE +0x00 0xf0 0x41 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt new file mode 100644 index 000000000000..f82d3cb0b10f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.97 MOV (register) +0x2 0xd0 0xbc 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt new file mode 100644 index 000000000000..3165ff794f97 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# A8.6.89 LSL (register): Inst{7-4} = 0b0001 +0x93 0x42 0xa0 0xd1 diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt new file mode 100644 index 000000000000..cfbba43fd514 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. +# The instruction is UNPREDICTABLE, and is not a valid intruction. +# +# See also +# A8.6.88 LSL (immediate) +# A8.6.98 MOV (shifted register), and +# I.1 Instruction encoding diagrams and pseudocode +0x2 0xd1 0xbc 0xf1 + + diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt new file mode 100644 index 000000000000..e9d5deb04349 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate) +# The hints instructions have more specific encodings, so if mask == 0, +# we should reject this as an invalid instruction. +0xa7 0xf1 0x20 0x3 diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt new file mode 100644 index 000000000000..1fdfa8299c78 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction +# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction +0x32 0xb1 0x99 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt new file mode 100644 index 000000000000..e7992ae6342e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt @@ -0,0 +1,9 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE; +0x5f 0xf8 0xe4 0x30 diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt new file mode 100644 index 000000000000..1ecd87df07c2 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if d == 15 || n == 15 then UNPREDICTABLE; +0x5f 0x54 0xa7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt new file mode 100644 index 000000000000..c3dcf83fbd21 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.167 +# if d == 15 || n == 15 | m == 15 then UNPREDICTABLE +0x1b 0x68 0xf 0x97 diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt new file mode 100644 index 000000000000..fdca9f9eaec6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=0 Name=PHI Format=(42) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# Unknown format +# +# B6.1.10 SRS +# Inst{19-8} = 0xd05 +# Inst{7-5} = 0b000 +0x83 0x1c 0xc5 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt new file mode 100644 index 000000000000..9cc8351b781f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.183 SSAT +# if d == 15 || n == 15 then UNPREDICTABLE; +0x1a 0xf4 0xa0 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt new file mode 100644 index 000000000000..0000c60ce4b8 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if BitCount(registers) < 1 then UNPREDICTABLE +0x00 0xc7 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt new file mode 100644 index 000000000000..5209323fa847 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if t == 15 then UNPREDICTABLE +0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt new file mode 100644 index 000000000000..4ec681daf954 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.223 SXTB +# if d == 15 || m == 15 then UNPREDICTABLE; +0x75 0xf4 0xaf 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt new file mode 100644 index 000000000000..7a3ef3328aa6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.244 UMAAL +# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x98 0xbf 0x4f 0xf0 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt new file mode 100644 index 000000000000..d3f508a1dabd --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt @@ -0,0 +1,12 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# DPFrm with bad reg specifier(s) +# +# if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; +0x9f 0x5f 0x66 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt new file mode 100644 index 000000000000..56d9ad704a01 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| 1: 1: 0: 0| 0: 0: 1: 1| 1: 1: 0: 1| +# ------------------------------------------------------------------------------------------------- +# +# 'a' == 1 and data_size == 8 is invalid +0x3d 0x3c 0xa0 0xf4 diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt new file mode 100644 index 000000000000..5fd02517991a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.315 VLD3 (single 3-element structure to all lanes) +# The a bit must be encoded as 0. +0xa2 0xf9 0x92 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt new file mode 100644 index 000000000000..887b983eddb3 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VLDMSDB_UPD-arm.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# core registers out of range +0xa5 0xba 0x72 0xed diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt new file mode 100644 index 000000000000..eed012b0be60 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# Qm -> bit[0] == 0, otherwise UNDEFINED +0xdb 0xe0 0x40 0xf2 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt new file mode 100644 index 000000000000..506250c3bc2a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.393 VST2 (multiple 2-element structures) +# type == '1001' and align == '11' ==> UNDEFINED +0xb3 0x9 0x3 0xf4 diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt new file mode 100644 index 000000000000..d0bc51ebaf39 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -0,0 +1,11 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.16 B +# if cond<3:1> == '111' then SEE "Related Encodings" +0xaf 0xf7 0x44 0x8b diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt new file mode 100644 index 000000000000..9befbd6b6fba --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# The unpriviledged Load/Store cannot have SP or PC as Rt. +0x10 0xf8 0x3 0xfe diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt new file mode 100644 index 000000000000..598efd1bc7c6 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 1| 0: 0: 1: 0| 1: 0: 0: 0| 1: 0: 0: 0| 0: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if t == t2 then UNPREDICTABLE +0xd2 0xe8 0x7f 0x88 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt new file mode 100644 index 000000000000..a501eb9cd541 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rt = '1111' then SEE "Unallocated memory hints" +0xb3 0xf9 0xdf 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt new file mode 100644 index 000000000000..f886a6f074b1 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" +0x35 0xf9 0x00 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt new file mode 100644 index 000000000000..c8f8ec294ec1 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 1| 1: 1: 1: 0| 0: 1: 0: 0| 0: 1: 0: 0| 0: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if wback && (n == t || n == t2) then UNPREDICTABLE +0xe4 0xe9 0x02 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt new file mode 100644 index 000000000000..35ea6511647f --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 1: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t then UNPREDICTABLE +0xc2 0xe8 0x42 0x8f diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt new file mode 100644 index 000000000000..9b0cf24ffb16 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| +# ------------------------------------------------------------------------------------------------- +# +# if d == n || d == t || d == t2 then UNPREDICTABLE +mc-input.txt:1:1: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt new file mode 100644 index 000000000000..129a2704d5c5 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} + +# Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| +# ------------------------------------------------------------------------------------------------- +# +# if Rn == '1111' then UNDEFINED +0x4f 0xf8 0xff 0xeb diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index eb9adb7b6c2f..cfb5949284ce 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -21,6 +21,12 @@ # CHECK: vld4.8 {d4, d6, d8, d10}, [r2] 0x0f 0x41 0x22 0xf4 +# CHECK: vld1.32 {d3[], d4[]}, [r0, :32]! +0xbd 0x3c 0xa0 0xf4 + +# CHECK: vld4.16 {d3[], d4[], d5[], d6[]}, [r0, :64]! +0x7d 0x3f 0xa0 0xf4 + # CHECK: vmov d0, d15 0x1f 0x01 0x2f 0xf2 @@ -59,3 +65,27 @@ # CHECK: vmov.f64 d0, #5.000000e-01 0x00 0x0b 0xb6 0xee + +# CHECK: vpop {d8} +0x02 0x8b 0xbd 0xec + +# CHECK: vorr.i32 q15, #0x4F0000 +0x5f 0xe5 0xc4 0xf2 + +# CHECK: vbic.i32 q2, #0xA900 +0x79 0x43 0x82 0xf3 + +# CHECK: vst2.32 {d16, d18}, [r2, :64], r2 +0x92 0x9 0x42 0xf4 + +# CHECK: vmov.s8 r0, d8[1] +0x30 0x0b 0x58 0xee + +# CHECK: vmov r1, r0, d11 +0x1b 0x1b 0x50 0xec + +# CHECK: usada8mi r8, r9, r5, r9 +0x19 0x95 0x88 0x47 + +# CHECK: vext.8 q4, q2, q1, #4 +0x42 0x84 0xb4 0xf2 diff --git a/test/MC/Disassembler/ARM/thumb-printf.txt b/test/MC/Disassembler/ARM/thumb-printf.txt new file mode 100644 index 000000000000..6c2c500630d5 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-printf.txt @@ -0,0 +1,77 @@ +# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s + +# CHECK: push {r0, r1, r2, r3} +# CHECK-NEXT: push {r4, r5, r7, lr} +# CHECK-NEXT: add r7, sp, #8 +# CHECK-NEXT: sub sp, #4 +# CHECK-NEXT: add r3, sp, #20 +# CHECK-NEXT: ldr r5, [r3], #4 +# CHECK-NEXT: str r3, [sp] +# CHECK-NEXT: ldr r3, #52 +# CHECK-NEXT: add r3, pc +# CHECK-NEXT: ldr r0, [r3] +# CHECK-NEXT: ldr r4, [r0] +# CHECK-NEXT: ldr r0, #48 +# CHECK-NEXT: add r0, pc +# CHECK-NEXT: ldr r0, [r0] +# CHECK-NEXT: ldr r0, [r0] +# CHECK-NEXT: blx #191548 +# CHECK-NEXT: cbnz r0, #6 +# CHECK-NEXT: ldr r1, #40 +# CHECK-NEXT: add r1, pc +# CHECK-NEXT: ldr r1, [r1] +# CHECK-NEXT: b #0 +# CHECK-NEXT: mov r1, r0 +# CHECK-NEXT: mov r0, r4 +# CHECK-NEXT: mov r2, r5 +# CHECK-NEXT: ldr r3, [sp] +# CHECK-NEXT: bl #-8390 +# Data bytes (corresponds to an invalid instruction) +# But not: sub.w sp, r7, #8 +# CHECK-NEXT: pop.w {r4, r5, r7, lr} +# CHECK-NEXT: add sp, #16 +# CHECK-NEXT: bx lr +# CHECK-NEXT: nop +# CHECK-NEXT: movs r3, #142 +# CHECK-NEXT: movs r5, r0 +# CHECK-NEXT: adds r1, #122 +# CHECK-NEXT: movs r5, r0 +# CHECK-NEXT: adds r1, #104 +# CHECK-NEXT: movs r5, r0 +0x0f 0xb4 +0xb0 0xb5 +0x02 0xaf +0x81 0xb0 +0x05 0xab +0x53 0xf8 0x04 0x5b +0x00 0x93 +0x0d 0x4b +0x7b 0x44 +0x18 0x68 +0x04 0x68 +0x0c 0x48 +0x78 0x44 +0x00 0x68 +0x00 0x68 +0x2e 0xf0 0x1e 0xee +0x18 0xb9 +0x0a 0x49 +0x79 0x44 +0x09 0x68 +0x00 0xe0 +0x01 0x46 +0x20 0x46 +0x2a 0x46 +0x00 0x9b +0xfd 0xf7 0x9d 0xff +# 0xa7 0xf1 0x08 0x0d +0xbd 0xe8 0xb0 0x40 +0x04 0xb0 +0x70 0x47 +0x00 0xbf +0x8e 0x23 +0x05 0x00 +0x7a 0x31 +0x05 0x00 +0x68 0x31 +0x05 0x00 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 6dab1237a118..774dbe4b42e5 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -6,11 +6,14 @@ # CHECK: adcs r0, r0, #1 0x50 0xf1 0x01 0x00 -# CHECK: b #34 +# CHECK: b #30 0x0f 0xe0 -# CHECK: b.w #-12 -0xff 0xf7 0xf8 0xaf +# CHECK: bgt.w #-16 +0x3f 0xf7 0xf8 0xaf + +# CHECK: bfc r0, #10, #10 +0x6f 0xf3 0x93 0x20 # CHECK: bfi r2, r10, #0, #1 0x6a 0xf3 0x00 0x02 @@ -27,14 +30,26 @@ # CHECK: ldmia r0!, {r1} 0x02 0xc8 +# CHECK: ldr r5, #432 +0x6c 0x4d + +# CHECK: str r0, [r3] +0x18 0x60 + +# CHECK: str r0, [r3, #4] +0x58 0x60 + +# CHECK: str r2, [r5, r3] +0xea 0x50 + # CHECK: ldrb.w r8, #-24 0x1f 0xf8 0x18 0x80 # CHECK: ldrd r0, r1, [r7, #64]! 0xf7 0xe9 0x10 0x01 -# CHECK: lsls.w r0, pc, #1 -0x5f 0xea 0x4f 0x00 +# CHECK: lsls.w r0, r5, #1 +0x5f 0xea 0x45 0x00 # CHECK: mov r11, r7 0xbb 0x46 @@ -118,3 +133,132 @@ # CHECK: msr cpsr_fc, r0 0x80 0xf3 0x00 0x89 + +# CHECK: blx #-4 +0xff 0xf7 0xfe 0xef + +# CHECK: vpush {d8, d9, d10} +0x2d 0xed 0x06 0x8b + +# CHECK: vcmpe.f64 d8, #0 +0xb5 0xee 0xc0 0x8b + +# CHECK: stmdb.w sp, {r0, r2, r3, r8, r11, lr} +0x0d 0xe9 0x0d 0x49 + +# CHECK: stmia r5!, {r0, r1, r2, r3, r4} +0x1f 0xc5 + +# CHECK: ldmia r5, {r0, r1, r2, r3, r4, r5} +0x3f 0xcd + +# CHECK: ldmia r5!, {r0, r1, r2, r3, r4} +0x1f 0xcd + +# CHECK: addw r0, pc, #1050 +0x0f 0xf2 0x1a 0x40 + +# CHECK: ldrd r3, r8, [r11, #-60] +0x5b 0xe9 0x0f 0x38 + +# CHECK: ldrex r8, [r2] +0x52 0xe8 0x00 0x8f + +# CHECK: ldrexd r8, r9, [r2] +0xd2 0xe8 0x7f 0x89 + +# CHECK: strexd r1, r7, r8, [r2] +0xc2 0xe8 0x71 0x78 + +# CHECK: tbh [r5, r4, lsl #1] +0xd5 0xe8 0x14 0xf0 + +# CHECK: tbb [r5, r4] +0xd5 0xe8 0x04 0xf0 + +# CHECK: ldr.w r4, [sp, r4, lsl #3] +0x5d 0xf8 0x34 0x40 + +# CHECK: ldr.w r5, [r6, #30] +0xd6 0xf8 0x1e 0x50 + +# CHECK: ldrh.w r5, [r6, #30] +0xb6 0xf8 0x1e 0x50 + +# CHECK: ldrt r5, [r6, #30] +0x56 0xf8 0x1e 0x5e + +# CHECK: ldr r5, [r6, #-30] +0x56 0xf8 0x1e 0x5c + +# CHECK: sel r7, r3, r5 +0xa3 0xfa 0x85 0xf7 + +# CHECK: lsl.w r7, r3, r5 +0x03 0xfa 0x05 0xf7 + +# CHECK: adds.w r7, r3, r5 +0x13 0xeb 0x05 0x07 + +# CHECK: smlabt r4, r3, r2, r1 +0x13 0xfb 0x12 0x14 + +# CHECK: smmulr r7, r8, r9 +0x58 0xfb 0x19 0xf7 + +# CHECK: umull r1, r2, r3, r4 +0xa3 0xfb 0x04 0x12 + +# CHECK: pld [r5, r0, lsl #1] +0x15 0xf8 0x10 0xf0 + +# CHECK: pld [pc, #-16] +0x1f 0xf8 0x10 0xf0 + +# CHECK: pld [r5, #30] +0x95 0xf8 0x1e 0xf0 + +# CHECK: stc2 p12, cr15, [r9], {137} +0x89 0xfc 0x89 0xfc + +# CHECK: vmov r1, r0, d11 +0x50 0xec 0x1b 0x1b + +# CHECK: dsb nsh +0xbf 0xf3 0x47 0x8f + +# CHECK: isb +0xbf 0xf3 0x6f 0x8f + +# CHECK: asrs r1, r0, #32 +0x1 0x10 + +# CHECK: lsr.w r10, r0, #32 +0x4f 0xea 0x10 0x0a + +# CHECK: blx sp +0xe8 0x47 + +# CHECK: bx lr +0x70 0x47 + +# CHECK: bx pc +0x78 0x47 + +# CHECK: svc #230 +0xe6 0xdf + +# CHECK: rfedb lr +0x1e 0xe8 0x00 0xc0 + +# CHECK: mov.w r3, #4294967295 +0x4f 0xf0 0xff 0x33 + +# CHECK: mov pc, sp +0xef 0x46 + +# CHECK: nop +0x00 0xbf + +# CHECK: nop.w +0xaf 0xf3 0x00 0x80 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 13a19d2ca4c3..08fb4c55b385 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -66,3 +66,9 @@ # CHECK: movw $47416, -66(%rbp) 0x66 0xc7 0x45 0xbe 0x38 0xb9 + +# CHECK: vaddpd %ymm13, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x58 0xc5 + +# CHECK: vaddps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x58 0xc3 |