diff options
Diffstat (limited to 'test')
1743 files changed, 66988 insertions, 9329 deletions
diff --git a/test/Analysis/BasicAA/invariant_load.ll b/test/Analysis/BasicAA/invariant_load.ll index cd6ddb92d210..09b54013a06b 100644 --- a/test/Analysis/BasicAA/invariant_load.ll +++ b/test/Analysis/BasicAA/invariant_load.ll @@ -10,10 +10,10 @@ define i32 @foo(i32* nocapture %p, i8* nocapture %q) { entry: - %0 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + %0 = load i32* %p, align 4, !invariant.load !3 %conv = trunc i32 %0 to i8 - store i8 %conv, i8* %q, align 1, !tbaa !1 - %1 = load i32* %p, align 4, !tbaa !0, !invariant.load !3 + store i8 %conv, i8* %q, align 1 + %1 = load i32* %p, align 4, !invariant.load !3 %add = add nsw i32 %1, 1 ret i32 %add @@ -23,7 +23,4 @@ entry: ; CHECK: %add = add nsw i32 %0, 1 } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} !3 = metadata !{} diff --git a/test/Analysis/BasicAA/phi-spec-order.ll b/test/Analysis/BasicAA/phi-spec-order.ll index 27d47bcd5bf3..4172d0963f34 100644 --- a/test/Analysis/BasicAA/phi-spec-order.ll +++ b/test/Analysis/BasicAA/phi-spec-order.ll @@ -24,23 +24,23 @@ for.body4: ; preds = %for.body4, %for.con %lsr.iv46 = bitcast [16000 x double]* %lsr.iv4 to <4 x double>* %lsr.iv12 = bitcast [16000 x double]* %lsr.iv1 to <4 x double>* %scevgep11 = getelementptr <4 x double>* %lsr.iv46, i64 -2 - %i6 = load <4 x double>* %scevgep11, align 32, !tbaa !0 + %i6 = load <4 x double>* %scevgep11, align 32 %add = fadd <4 x double> %i6, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> - store <4 x double> %add, <4 x double>* %lsr.iv12, align 32, !tbaa !0 + store <4 x double> %add, <4 x double>* %lsr.iv12, align 32 %scevgep10 = getelementptr <4 x double>* %lsr.iv46, i64 -1 - %i7 = load <4 x double>* %scevgep10, align 32, !tbaa !0 + %i7 = load <4 x double>* %scevgep10, align 32 %add.4 = fadd <4 x double> %i7, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> %scevgep9 = getelementptr <4 x double>* %lsr.iv12, i64 1 - store <4 x double> %add.4, <4 x double>* %scevgep9, align 32, !tbaa !0 - %i8 = load <4 x double>* %lsr.iv46, align 32, !tbaa !0 + store <4 x double> %add.4, <4 x double>* %scevgep9, align 32 + %i8 = load <4 x double>* %lsr.iv46, align 32 %add.8 = fadd <4 x double> %i8, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> %scevgep8 = getelementptr <4 x double>* %lsr.iv12, i64 2 - store <4 x double> %add.8, <4 x double>* %scevgep8, align 32, !tbaa !0 + store <4 x double> %add.8, <4 x double>* %scevgep8, align 32 %scevgep7 = getelementptr <4 x double>* %lsr.iv46, i64 1 - %i9 = load <4 x double>* %scevgep7, align 32, !tbaa !0 + %i9 = load <4 x double>* %scevgep7, align 32 %add.12 = fadd <4 x double> %i9, <double 1.000000e+00, double 1.000000e+00, double 1.000000e+00, double 1.000000e+00> %scevgep3 = getelementptr <4 x double>* %lsr.iv12, i64 3 - store <4 x double> %add.12, <4 x double>* %scevgep3, align 32, !tbaa !0 + store <4 x double> %add.12, <4 x double>* %scevgep3, align 32 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep11, <4 x double>* %scevgep7 ; CHECK: NoAlias:{{[ \t]+}}<4 x double>* %scevgep10, <4 x double>* %scevgep7 @@ -65,7 +65,3 @@ for.end: ; preds = %for.body4 for.end10: ; preds = %for.end ret i32 0 } - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/CostModel/ARM/cast.ll b/test/Analysis/CostModel/ARM/cast.ll index ba9d84cf3e23..0cdd61cac4f7 100644 --- a/test/Analysis/CostModel/ARM/cast.ll +++ b/test/Analysis/CostModel/ARM/cast.ll @@ -175,9 +175,9 @@ define i32 @casts() { %rext_5 = zext <4 x i16> undef to <4 x i64> ; Vector cast cost of instructions lowering the cast to the stack. - ; CHECK: cost of 19 {{.*}} trunc + ; CHECK: cost of 3 {{.*}} trunc %r74 = trunc <8 x i32> undef to <8 x i8> - ; CHECK: cost of 38 {{.*}} trunc + ; CHECK: cost of 6 {{.*}} trunc %r75 = trunc <16 x i32> undef to <16 x i8> ; Floating point truncation costs. diff --git a/test/Analysis/CostModel/ARM/divrem.ll b/test/Analysis/CostModel/ARM/divrem.ll new file mode 100644 index 000000000000..c4ac59b59e0a --- /dev/null +++ b/test/Analysis/CostModel/ARM/divrem.ll @@ -0,0 +1,450 @@ +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -mcpu=cortex-a9 | FileCheck %s + +define <2 x i8> @sdiv_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: sdiv_v2_i8 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @sdiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: sdiv_v2_i16 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @sdiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: sdiv_v2_i32 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @sdiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: sdiv_v2_i64 + ; CHECK: cost of 40 {{.*}} sdiv + + %1 = sdiv <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @sdiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: sdiv_v4_i8 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @sdiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: sdiv_v4_i16 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @sdiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: sdiv_v4_i32 + ; CHECK: cost of 80 {{.*}} sdiv + + %1 = sdiv <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @sdiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: sdiv_v4_i64 + ; CHECK: cost of 80 {{.*}} sdiv + + %1 = sdiv <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @sdiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: sdiv_v8_i8 + ; CHECK: cost of 10 {{.*}} sdiv + + %1 = sdiv <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @sdiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: sdiv_v8_i16 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @sdiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: sdiv_v8_i32 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @sdiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: sdiv_v8_i64 + ; CHECK: cost of 160 {{.*}} sdiv + + %1 = sdiv <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @sdiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: sdiv_v16_i8 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @sdiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: sdiv_v16_i16 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @sdiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: sdiv_v16_i32 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @sdiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: sdiv_v16_i64 + ; CHECK: cost of 320 {{.*}} sdiv + + %1 = sdiv <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @udiv_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: udiv_v2_i8 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @udiv_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: udiv_v2_i16 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @udiv_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: udiv_v2_i32 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @udiv_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: udiv_v2_i64 + ; CHECK: cost of 40 {{.*}} udiv + + %1 = udiv <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @udiv_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: udiv_v4_i8 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @udiv_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: udiv_v4_i16 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @udiv_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: udiv_v4_i32 + ; CHECK: cost of 80 {{.*}} udiv + + %1 = udiv <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @udiv_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: udiv_v4_i64 + ; CHECK: cost of 80 {{.*}} udiv + + %1 = udiv <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @udiv_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: udiv_v8_i8 + ; CHECK: cost of 10 {{.*}} udiv + + %1 = udiv <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @udiv_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: udiv_v8_i16 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @udiv_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: udiv_v8_i32 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @udiv_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: udiv_v8_i64 + ; CHECK: cost of 160 {{.*}} udiv + + %1 = udiv <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @udiv_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: udiv_v16_i8 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @udiv_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: udiv_v16_i16 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @udiv_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: udiv_v16_i32 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @udiv_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: udiv_v16_i64 + ; CHECK: cost of 320 {{.*}} udiv + + %1 = udiv <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @srem_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: srem_v2_i8 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @srem_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: srem_v2_i16 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @srem_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: srem_v2_i32 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @srem_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: srem_v2_i64 + ; CHECK: cost of 40 {{.*}} srem + + %1 = srem <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @srem_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: srem_v4_i8 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @srem_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: srem_v4_i16 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @srem_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: srem_v4_i32 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @srem_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: srem_v4_i64 + ; CHECK: cost of 80 {{.*}} srem + + %1 = srem <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @srem_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: srem_v8_i8 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @srem_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: srem_v8_i16 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @srem_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: srem_v8_i32 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @srem_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: srem_v8_i64 + ; CHECK: cost of 160 {{.*}} srem + + %1 = srem <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @srem_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: srem_v16_i8 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @srem_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: srem_v16_i16 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @srem_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: srem_v16_i32 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @srem_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: srem_v16_i64 + ; CHECK: cost of 320 {{.*}} srem + + %1 = srem <16 x i64> %a, %b + ret <16 x i64> %1 +} +define <2 x i8> @urem_v2_i8(<2 x i8> %a, <2 x i8> %b) { + ; CHECK: urem_v2_i8 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i8> %a, %b + ret <2 x i8> %1 +} +define <2 x i16> @urem_v2_i16(<2 x i16> %a, <2 x i16> %b) { + ; CHECK: urem_v2_i16 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i16> %a, %b + ret <2 x i16> %1 +} +define <2 x i32> @urem_v2_i32(<2 x i32> %a, <2 x i32> %b) { + ; CHECK: urem_v2_i32 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i32> %a, %b + ret <2 x i32> %1 +} +define <2 x i64> @urem_v2_i64(<2 x i64> %a, <2 x i64> %b) { + ; CHECK: urem_v2_i64 + ; CHECK: cost of 40 {{.*}} urem + + %1 = urem <2 x i64> %a, %b + ret <2 x i64> %1 +} +define <4 x i8> @urem_v4_i8(<4 x i8> %a, <4 x i8> %b) { + ; CHECK: urem_v4_i8 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i8> %a, %b + ret <4 x i8> %1 +} +define <4 x i16> @urem_v4_i16(<4 x i16> %a, <4 x i16> %b) { + ; CHECK: urem_v4_i16 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i16> %a, %b + ret <4 x i16> %1 +} +define <4 x i32> @urem_v4_i32(<4 x i32> %a, <4 x i32> %b) { + ; CHECK: urem_v4_i32 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i32> %a, %b + ret <4 x i32> %1 +} +define <4 x i64> @urem_v4_i64(<4 x i64> %a, <4 x i64> %b) { + ; CHECK: urem_v4_i64 + ; CHECK: cost of 80 {{.*}} urem + + %1 = urem <4 x i64> %a, %b + ret <4 x i64> %1 +} +define <8 x i8> @urem_v8_i8(<8 x i8> %a, <8 x i8> %b) { + ; CHECK: urem_v8_i8 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i8> %a, %b + ret <8 x i8> %1 +} +define <8 x i16> @urem_v8_i16(<8 x i16> %a, <8 x i16> %b) { + ; CHECK: urem_v8_i16 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i16> %a, %b + ret <8 x i16> %1 +} +define <8 x i32> @urem_v8_i32(<8 x i32> %a, <8 x i32> %b) { + ; CHECK: urem_v8_i32 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i32> %a, %b + ret <8 x i32> %1 +} +define <8 x i64> @urem_v8_i64(<8 x i64> %a, <8 x i64> %b) { + ; CHECK: urem_v8_i64 + ; CHECK: cost of 160 {{.*}} urem + + %1 = urem <8 x i64> %a, %b + ret <8 x i64> %1 +} +define <16 x i8> @urem_v16_i8(<16 x i8> %a, <16 x i8> %b) { + ; CHECK: urem_v16_i8 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i8> %a, %b + ret <16 x i8> %1 +} +define <16 x i16> @urem_v16_i16(<16 x i16> %a, <16 x i16> %b) { + ; CHECK: urem_v16_i16 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i16> %a, %b + ret <16 x i16> %1 +} +define <16 x i32> @urem_v16_i32(<16 x i32> %a, <16 x i32> %b) { + ; CHECK: urem_v16_i32 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i32> %a, %b + ret <16 x i32> %1 +} +define <16 x i64> @urem_v16_i64(<16 x i64> %a, <16 x i64> %b) { + ; CHECK: urem_v16_i64 + ; CHECK: cost of 320 {{.*}} urem + + %1 = urem <16 x i64> %a, %b + ret <16 x i64> %1 +} diff --git a/test/Analysis/CostModel/X86/arith.ll b/test/Analysis/CostModel/X86/arith.ll index 85b442533f41..92f5a1ec3a00 100644 --- a/test/Analysis/CostModel/X86/arith.ll +++ b/test/Analysis/CostModel/X86/arith.ll @@ -66,9 +66,9 @@ define void @avx2mull() { ; CHECK: fmul define i32 @fmul(i32 %arg) { - ;CHECK: cost of 1 {{.*}} fmul + ;CHECK: cost of 2 {{.*}} fmul %A = fmul <4 x float> undef, undef - ;CHECK: cost of 1 {{.*}} fmul + ;CHECK: cost of 2 {{.*}} fmul %B = fmul <8 x float> undef, undef ret i32 undef } diff --git a/test/Analysis/CostModel/X86/loop_v2.ll b/test/Analysis/CostModel/X86/loop_v2.ll index 260a60676ab7..348444eb0833 100644 --- a/test/Analysis/CostModel/X86/loop_v2.ll +++ b/test/Analysis/CostModel/X86/loop_v2.ll @@ -20,10 +20,10 @@ vector.body: ; preds = %vector.body, %vecto ;CHECK: cost of 1 {{.*}} extract %6 = extractelement <2 x i64> %3, i32 1 %7 = getelementptr inbounds i32* %A, i64 %6 - %8 = load i32* %5, align 4, !tbaa !0 + %8 = load i32* %5, align 4 ;CHECK: cost of 1 {{.*}} insert %9 = insertelement <2 x i32> undef, i32 %8, i32 0 - %10 = load i32* %7, align 4, !tbaa !0 + %10 = load i32* %7, align 4 ;CHECK: cost of 1 {{.*}} insert %11 = insertelement <2 x i32> %9, i32 %10, i32 1 %12 = add nsw <2 x i32> %11, %vec.phi @@ -37,7 +37,3 @@ for.end: ; preds = %vector.body %16 = add i32 %14, %15 ret i32 %16 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/CostModel/X86/sitofp.ll b/test/Analysis/CostModel/X86/sitofp.ll new file mode 100644 index 000000000000..338d97416526 --- /dev/null +++ b/test/Analysis/CostModel/X86/sitofp.ll @@ -0,0 +1,281 @@ +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +define <2 x double> @sitofpv2i8v2double(<2 x i8> %a) { + ; SSE2: sitofpv2i8v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i8> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i8v4double(<4 x i8> %a) { + ; SSE2: sitofpv4i8v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i8> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i8v8double(<8 x i8> %a) { + ; SSE2: sitofpv8i8v8double + ; SSE2: cost of 80 {{.*}} sitofp +%1 = sitofp <8 x i8> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i8v16double(<16 x i8> %a) { + ; SSE2: sitofpv16i8v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i8> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i8v32double(<32 x i8> %a) { + ; SSE2: sitofpv32i8v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i8> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i16v2double(<2 x i16> %a) { + ; SSE2: sitofpv2i16v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i16> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i16v4double(<4 x i16> %a) { + ; SSE2: sitofpv4i16v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i16> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i16v8double(<8 x i16> %a) { + ; SSE2: sitofpv8i16v8double + ; SSE2: cost of 80 {{.*}} sitofp + %1 = sitofp <8 x i16> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i16v16double(<16 x i16> %a) { + ; SSE2: sitofpv16i16v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i16> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i16v32double(<32 x i16> %a) { + ; SSE2: sitofpv32i16v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i16> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i32v2double(<2 x i32> %a) { + ; SSE2: sitofpv2i32v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i32> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i32v4double(<4 x i32> %a) { + ; SSE2: sitofpv4i32v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i32> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i32v8double(<8 x i32> %a) { + ; SSE2: sitofpv8i32v8double + ; SSE2: cost of 80 {{.*}} sitofp + %1 = sitofp <8 x i32> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i32v16double(<16 x i32> %a) { + ; SSE2: sitofpv16i32v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i32> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i32v32double(<32 x i32> %a) { + ; SSE2: sitofpv32i32v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i32> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @sitofpv2i64v2double(<2 x i64> %a) { + ; SSE2: sitofpv2i64v2double + ; SSE2: cost of 20 {{.*}} sitofp + %1 = sitofp <2 x i64> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @sitofpv4i64v4double(<4 x i64> %a) { + ; SSE2: sitofpv4i64v4double + ; SSE2: cost of 40 {{.*}} sitofp + %1 = sitofp <4 x i64> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @sitofpv8i64v8double(<8 x i64> %a) { + %1 = sitofp <8 x i64> %a to <8 x double> + ; SSE2: sitofpv8i64v8double + ; SSE2: cost of 80 {{.*}} sitofp + ret <8 x double> %1 +} + +define <16 x double> @sitofpv16i64v16double(<16 x i64> %a) { + ; SSE2: sitofpv16i64v16double + ; SSE2: cost of 160 {{.*}} sitofp + %1 = sitofp <16 x i64> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @sitofpv32i64v32double(<32 x i64> %a) { + ; SSE2: sitofpv32i64v32double + ; SSE2: cost of 320 {{.*}} sitofp + %1 = sitofp <32 x i64> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x float> @sitofpv2i8v2float(<2 x i8> %a) { + ; SSE2: sitofpv2i8v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i8> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i8v4float(<4 x i8> %a) { + ; SSE2: sitofpv4i8v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i8> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i8v8float(<8 x i8> %a) { + ; SSE2: sitofpv8i8v8float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <8 x i8> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i8v16float(<16 x i8> %a) { + ; SSE2: sitofpv16i8v16float + ; SSE2: cost of 8 {{.*}} sitofp + %1 = sitofp <16 x i8> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i8v32float(<32 x i8> %a) { + ; SSE2: sitofpv32i8v32float + ; SSE2: cost of 16 {{.*}} sitofp + %1 = sitofp <32 x i8> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i16v2float(<2 x i16> %a) { + ; SSE2: sitofpv2i16v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i16> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i16v4float(<4 x i16> %a) { + ; SSE2: sitofpv4i16v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i16> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i16v8float(<8 x i16> %a) { + ; SSE2: sitofpv8i16v8float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <8 x i16> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i16v16float(<16 x i16> %a) { + ; SSE2: sitofpv16i16v16float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <16 x i16> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i16v32float(<32 x i16> %a) { + ; SSE2: sitofpv32i16v32float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <32 x i16> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i32v2float(<2 x i32> %a) { + ; SSE2: sitofpv2i32v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i32> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i32v4float(<4 x i32> %a) { + ; SSE2: sitofpv4i32v4float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <4 x i32> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i32v8float(<8 x i32> %a) { + ; SSE2: sitofpv8i32v8float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <8 x i32> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i32v16float(<16 x i32> %a) { + ; SSE2: sitofpv16i32v16float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <16 x i32> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i32v32float(<32 x i32> %a) { + ; SSE2: sitofpv32i32v32float + ; SSE2: cost of 120 {{.*}} sitofp + %1 = sitofp <32 x i32> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @sitofpv2i64v2float(<2 x i64> %a) { + ; SSE2: sitofpv2i64v2float + ; SSE2: cost of 15 {{.*}} sitofp + %1 = sitofp <2 x i64> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @sitofpv4i64v4float(<4 x i64> %a) { + ; SSE2: sitofpv4i64v4float + ; SSE2: cost of 30 {{.*}} sitofp + %1 = sitofp <4 x i64> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @sitofpv8i64v8float(<8 x i64> %a) { + ; SSE2: sitofpv8i64v8float + ; SSE2: cost of 60 {{.*}} sitofp + %1 = sitofp <8 x i64> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @sitofpv16i64v16float(<16 x i64> %a) { + ; SSE2: sitofpv16i64v16float + ; SSE2: cost of 120 {{.*}} sitofp + %1 = sitofp <16 x i64> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @sitofpv32i64v32float(<32 x i64> %a) { + ; SSE2: sitofpv32i64v32float + ; SSE2: cost of 240 {{.*}} sitofp + %1 = sitofp <32 x i64> %a to <32 x float> + ret <32 x float> %1 +} diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll index f35eea87164c..d96a92fe2a8a 100644 --- a/test/Analysis/CostModel/X86/testshiftashr.ll +++ b/test/Analysis/CostModel/X86/testshiftashr.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: sarl %cl @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: sarq %cl @@ -373,7 +373,7 @@ define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 8 {{.*}} ashr ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: psrad $3 %0 = ashr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +443,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: sarq $3 diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll index 8d6ef3874208..7bc8d89e4ad8 100644 --- a/test/Analysis/CostModel/X86/testshiftlshr.ll +++ b/test/Analysis/CostModel/X86/testshiftlshr.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 320 {{.*}} lshr ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: shrl %cl @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 320 {{.*}} lshr ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: shrq %cl @@ -372,8 +372,7 @@ entry: define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c - ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 8 {{.*}} lshr ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: psrld $3 %0 = lshr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +442,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 16 {{.*}} lshr ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: psrlq $3 diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll index f45a69879210..40effd02922c 100644 --- a/test/Analysis/CostModel/X86/testshiftshl.ll +++ b/test/Analysis/CostModel/X86/testshiftshl.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 80 {{.*}} shl ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: pmuludq @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 320 {{.*}} shl ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: shlq %cl @@ -372,8 +372,7 @@ entry: define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c - ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 8 {{.*}} shl ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: pslld $3 %0 = shl %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +442,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 16 {{.*}} shl ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: psllq $3 diff --git a/test/Analysis/CostModel/X86/uitofp.ll b/test/Analysis/CostModel/X86/uitofp.ll new file mode 100644 index 000000000000..a41a04df84ec --- /dev/null +++ b/test/Analysis/CostModel/X86/uitofp.ll @@ -0,0 +1,368 @@ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=core2 < %s | FileCheck --check-prefix=SSE2-CODEGEN %s +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -cost-model -analyze < %s | FileCheck --check-prefix=SSE2 %s + +; In X86TargetTransformInfo::getCastInstrCost we have code that depends on +; getSimpleVT on a value type. On AVX2 we execute this code. Make sure we exit +; early if the type is not a simple value type before we call this function. +; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -cost-model -analyze < %s + +define <2 x double> @uitofpv2i8v2double(<2 x i8> %a) { + ; SSE2: uitofpv2i8v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i8v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i8> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i8v4double(<4 x i8> %a) { + ; SSE2: uitofpv4i8v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i8v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i8> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i8v8double(<8 x i8> %a) { + ; SSE2: uitofpv8i8v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i8v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd +%1 = uitofp <8 x i8> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i8v16double(<16 x i8> %a) { + ; SSE2: uitofpv16i8v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i8v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i8> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i8v32double(<32 x i8> %a) { + ; SSE2: uitofpv32i8v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i8v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i8> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i16v2double(<2 x i16> %a) { + ; SSE2: uitofpv2i16v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i16v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i16> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i16v4double(<4 x i16> %a) { + ; SSE2: uitofpv4i16v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i16v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i16> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i16v8double(<8 x i16> %a) { + ; SSE2: uitofpv8i16v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i16v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <8 x i16> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i16v16double(<16 x i16> %a) { + ; SSE2: uitofpv16i16v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i16v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i16> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i16v32double(<32 x i16> %a) { + ; SSE2: uitofpv32i16v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i16v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i16> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i32v2double(<2 x i32> %a) { + ; SSE2: uitofpv2i32v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i32v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i32> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i32v4double(<4 x i32> %a) { + ; SSE2: uitofpv4i32v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i32v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i32> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i32v8double(<8 x i32> %a) { + ; SSE2: uitofpv8i32v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i32v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <8 x i32> %a to <8 x double> + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i32v16double(<16 x i32> %a) { + ; SSE2: uitofpv16i32v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i32v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i32> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i32v32double(<32 x i32> %a) { + ; SSE2: uitofpv32i32v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i32v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i32> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x double> @uitofpv2i64v2double(<2 x i64> %a) { + ; SSE2: uitofpv2i64v2double + ; SSE2: cost of 20 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv2i64v2double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <2 x i64> %a to <2 x double> + ret <2 x double> %1 +} + +define <4 x double> @uitofpv4i64v4double(<4 x i64> %a) { + ; SSE2: uitofpv4i64v4double + ; SSE2: cost of 40 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv4i64v4double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <4 x i64> %a to <4 x double> + ret <4 x double> %1 +} + +define <8 x double> @uitofpv8i64v8double(<8 x i64> %a) { + %1 = uitofp <8 x i64> %a to <8 x double> + ; SSE2: uitofpv8i64v8double + ; SSE2: cost of 80 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv8i64v8double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + ret <8 x double> %1 +} + +define <16 x double> @uitofpv16i64v16double(<16 x i64> %a) { + ; SSE2: uitofpv16i64v16double + ; SSE2: cost of 160 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv16i64v16double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <16 x i64> %a to <16 x double> + ret <16 x double> %1 +} + +define <32 x double> @uitofpv32i64v32double(<32 x i64> %a) { + ; SSE2: uitofpv32i64v32double + ; SSE2: cost of 320 {{.*}} uitofp + ; SSE2-CODEGEN: uitofpv32i64v32double + ; SSE2-CODEGEN: movapd LCPI + ; SSE2-CODEGEN: subpd + ; SSE2-CODEGEN: addpd + %1 = uitofp <32 x i64> %a to <32 x double> + ret <32 x double> %1 +} + +define <2 x float> @uitofpv2i8v2float(<2 x i8> %a) { + ; SSE2: uitofpv2i8v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i8> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i8v4float(<4 x i8> %a) { + ; SSE2: uitofpv4i8v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i8> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i8v8float(<8 x i8> %a) { + ; SSE2: uitofpv8i8v8float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <8 x i8> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i8v16float(<16 x i8> %a) { + ; SSE2: uitofpv16i8v16float + ; SSE2: cost of 8 {{.*}} uitofp + %1 = uitofp <16 x i8> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i8v32float(<32 x i8> %a) { + ; SSE2: uitofpv32i8v32float + ; SSE2: cost of 16 {{.*}} uitofp + %1 = uitofp <32 x i8> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i16v2float(<2 x i16> %a) { + ; SSE2: uitofpv2i16v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i16> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i16v4float(<4 x i16> %a) { + ; SSE2: uitofpv4i16v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i16> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i16v8float(<8 x i16> %a) { + ; SSE2: uitofpv8i16v8float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <8 x i16> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i16v16float(<16 x i16> %a) { + ; SSE2: uitofpv16i16v16float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <16 x i16> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i16v32float(<32 x i16> %a) { + ; SSE2: uitofpv32i16v32float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <32 x i16> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i32v2float(<2 x i32> %a) { + ; SSE2: uitofpv2i32v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i32> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i32v4float(<4 x i32> %a) { + ; SSE2: uitofpv4i32v4float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <4 x i32> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i32v8float(<8 x i32> %a) { + ; SSE2: uitofpv8i32v8float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <8 x i32> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i32v16float(<16 x i32> %a) { + ; SSE2: uitofpv16i32v16float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <16 x i32> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i32v32float(<32 x i32> %a) { + ; SSE2: uitofpv32i32v32float + ; SSE2: cost of 120 {{.*}} uitofp + %1 = uitofp <32 x i32> %a to <32 x float> + ret <32 x float> %1 +} + +define <2 x float> @uitofpv2i64v2float(<2 x i64> %a) { + ; SSE2: uitofpv2i64v2float + ; SSE2: cost of 15 {{.*}} uitofp + %1 = uitofp <2 x i64> %a to <2 x float> + ret <2 x float> %1 +} + +define <4 x float> @uitofpv4i64v4float(<4 x i64> %a) { + ; SSE2: uitofpv4i64v4float + ; SSE2: cost of 30 {{.*}} uitofp + %1 = uitofp <4 x i64> %a to <4 x float> + ret <4 x float> %1 +} + +define <8 x float> @uitofpv8i64v8float(<8 x i64> %a) { + ; SSE2: uitofpv8i64v8float + ; SSE2: cost of 60 {{.*}} uitofp + %1 = uitofp <8 x i64> %a to <8 x float> + ret <8 x float> %1 +} + +define <16 x float> @uitofpv16i64v16float(<16 x i64> %a) { + ; SSE2: uitofpv16i64v16float + ; SSE2: cost of 120 {{.*}} uitofp + %1 = uitofp <16 x i64> %a to <16 x float> + ret <16 x float> %1 +} + +define <32 x float> @uitofpv32i64v32float(<32 x i64> %a) { + ; SSE2: uitofpv32i64v32float + ; SSE2: cost of 240 {{.*}} uitofp + %1 = uitofp <32 x i64> %a to <32 x float> + ret <32 x float> %1 +} + diff --git a/test/Analysis/CostModel/X86/vectorized-loop.ll b/test/Analysis/CostModel/X86/vectorized-loop.ll index 25b11145c661..af7d1df8a570 100644 --- a/test/Analysis/CostModel/X86/vectorized-loop.ll +++ b/test/Analysis/CostModel/X86/vectorized-loop.ll @@ -54,14 +54,14 @@ for.body: ; preds = %middle.block, %for. %13 = add nsw i64 %indvars.iv, 2 %arrayidx = getelementptr inbounds i32* %B, i64 %13 ;CHECK: cost of 1 {{.*}} load - %14 = load i32* %arrayidx, align 4, !tbaa !0 + %14 = load i32* %arrayidx, align 4 ;CHECK: cost of 1 {{.*}} mul %mul = mul nsw i32 %14, 5 %arrayidx2 = getelementptr inbounds i32* %A, i64 %indvars.iv ;CHECK: cost of 1 {{.*}} load - %15 = load i32* %arrayidx2, align 4, !tbaa !0 + %15 = load i32* %arrayidx2, align 4 %add3 = add nsw i32 %15, %mul - store i32 %add3, i32* %arrayidx2, align 4, !tbaa !0 + store i32 %add3, i32* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 ;CHECK: cost of 0 {{.*}} trunc %16 = trunc i64 %indvars.iv.next to i32 @@ -73,7 +73,3 @@ for.end: ; preds = %middle.block, %for. ;CHECK: cost of 0 {{.*}} ret ret i32 undef } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/GlobalsModRef/volatile-instrs.ll b/test/Analysis/GlobalsModRef/volatile-instrs.ll index 49bce670b7f7..46d3d768bd07 100644 --- a/test/Analysis/GlobalsModRef/volatile-instrs.ll +++ b/test/Analysis/GlobalsModRef/volatile-instrs.ll @@ -22,13 +22,9 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, define i32 @main() nounwind uwtable ssp { main_entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) - %0 = load volatile i32* getelementptr inbounds (%struct.anon* @b, i64 0, i32 0), align 4, !tbaa !0 - store i32 %0, i32* @c, align 4, !tbaa !0 + %0 = load volatile i32* getelementptr inbounds (%struct.anon* @b, i64 0, i32 0), align 4 + store i32 %0, i32* @c, align 4 tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* bitcast (%struct.anon* @b to i8*), i8* bitcast (%struct.anon* @a to i8*), i64 12, i32 4, i1 false) nounwind %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([4 x i8]* @.str, i64 0, i64 0), i32 %0) nounwind ret i32 0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg b/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg new file mode 100644 index 000000000000..c6106e4746f2 --- /dev/null +++ b/test/Analysis/MemoryDependenceAnalysis/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.ll'] diff --git a/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll new file mode 100644 index 000000000000..3c957708d705 --- /dev/null +++ b/test/Analysis/MemoryDependenceAnalysis/memdep_requires_dominator_tree.ll @@ -0,0 +1,19 @@ +; RUN: opt -memdep -gvn < %s + +define void @__memdep_requires_dominator_tree(i32* nocapture %bufUInt, i32* nocapture %pattern) nounwind { +entry: + br label %for.body + +for.exit: ; preds = %for.body + ret void + +for.body: ; preds = %for.body, %entry + %i.01 = phi i32 [ 0, %entry ], [ %tmp8.7, %for.body ] + %arrayidx = getelementptr i32* %bufUInt, i32 %i.01 + %arrayidx5 = getelementptr i32* %pattern, i32 %i.01 + %tmp6 = load i32* %arrayidx5, align 4 + store i32 %tmp6, i32* %arrayidx, align 4 + %tmp8.7 = add i32 %i.01, 8 + %cmp.7 = icmp ult i32 %tmp8.7, 1024 + br i1 %cmp.7, label %for.body, label %for.exit +} diff --git a/test/Analysis/Profiling/lit.local.cfg b/test/Analysis/Profiling/lit.local.cfg index 444b7dc27410..d40fa4f9d3ab 100644 --- a/test/Analysis/Profiling/lit.local.cfg +++ b/test/Analysis/Profiling/lit.local.cfg @@ -7,10 +7,5 @@ def getRoot(config): root = getRoot(config) -# Most profiling tests rely on a JIT being present to gather their data; AArch64 -# doesn't have any JIT at present so they will fail when run there. -if root.host_arch in ['AArch64']: - config.unsupported = True - if 'hexagon' in root.target_triple: config.unsupported = True diff --git a/test/Analysis/RegionInfo/unreachable_bb.ll b/test/Analysis/RegionInfo/unreachable_bb.ll new file mode 100644 index 000000000000..626ccbe304c3 --- /dev/null +++ b/test/Analysis/RegionInfo/unreachable_bb.ll @@ -0,0 +1,29 @@ +; RUN: opt -regions -analyze < %s | FileCheck %s + +; We should not crash if there are some bbs that are not reachable. +define void @f() { +entry: + br label %for.pre + +notintree: ; No predecessors! + br label %ret + +for.pre: ; preds = %entry + br label %for + +for: ; preds = %for.inc, %for.pre + %indvar = phi i64 [ 0, %for.pre ], [ %indvar.next, %for.inc ] + %exitcond = icmp ne i64 %indvar, 200 + br i1 %exitcond, label %for.inc, label %ret + +for.inc: ; preds = %for + %indvar.next = add i64 %indvar, 1 + br label %for + +ret: ; preds = %for, %notintree + ret void +} + +; CHECK: [0] entry => <Function Return> +; CHECK: [1] for => ret + diff --git a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll index 138c015f12ca..b88e33f2bb8a 100644 --- a/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll +++ b/test/Analysis/ScalarEvolution/2012-03-26-LoadConstant.ll @@ -15,24 +15,24 @@ entry: lbl_818: ; preds = %for.end, %entry call void (...)* @func_27() - store i32 0, i32* @g_814, align 4, !tbaa !0 + store i32 0, i32* @g_814, align 4 br label %for.cond for.cond: ; preds = %for.body, %lbl_818 - %0 = load i32* @g_814, align 4, !tbaa !0 + %0 = load i32* @g_814, align 4 %cmp = icmp sle i32 %0, 0 br i1 %cmp, label %for.body, label %for.end for.body: ; preds = %for.cond %idxprom = sext i32 %0 to i64 %arrayidx = getelementptr inbounds [0 x i32]* getelementptr inbounds ([1 x [0 x i32]]* @g_244, i32 0, i64 0), i32 0, i64 %idxprom - %1 = load i32* %arrayidx, align 1, !tbaa !0 - store i32 %1, i32* @func_21_l_773, align 4, !tbaa !0 - store i32 1, i32* @g_814, align 4, !tbaa !0 + %1 = load i32* %arrayidx, align 1 + store i32 %1, i32* @func_21_l_773, align 4 + store i32 1, i32* @g_814, align 4 br label %for.cond for.end: ; preds = %for.cond - %2 = load i32* @func_21_l_773, align 4, !tbaa !0 + %2 = load i32* @func_21_l_773, align 4 %tobool = icmp ne i32 %2, 0 br i1 %tobool, label %lbl_818, label %if.end @@ -41,7 +41,3 @@ if.end: ; preds = %for.end } declare void @func_27(...) - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll new file mode 100644 index 000000000000..ee527639b3d1 --- /dev/null +++ b/test/Analysis/TypeBasedAliasAnalysis/tbaa-path.ll @@ -0,0 +1,392 @@ +; RUN: opt < %s -tbaa -basicaa -struct-path-tbaa -aa-eval -evaluate-tbaa -print-no-aliases -print-may-aliases -disable-output 2>&1 | FileCheck %s +; RUN: opt < %s -tbaa -basicaa -struct-path-tbaa -gvn -S | FileCheck %s --check-prefix=OPT +; Generated from clang/test/CodeGen/tbaa.cpp with "-O1 -struct-path-tbaa -disable-llvm-optzns". + +%struct.StructA = type { i16, i32, i16, i32 } +%struct.StructB = type { i16, %struct.StructA, i32 } +%struct.StructS = type { i16, i32 } +%struct.StructS2 = type { i16, i32 } +%struct.StructC = type { i16, %struct.StructB, i32 } +%struct.StructD = type { i16, %struct.StructB, i32, i8 } + +define i32 @_Z1gPjP7StructAy(i32* %s, %struct.StructA* %A, i64 %count) #0 { +entry: +; Access to i32* and &(A->f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f32, align 4, !tbaa !8 <-> store i32 1, i32* %0, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %s.addr = alloca i32*, align 8 + %A.addr = alloca %struct.StructA*, align 8 + %count.addr = alloca i64, align 8 + store i32* %s, i32** %s.addr, align 8, !tbaa !0 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load i32** %s.addr, align 8, !tbaa !0 + store i32 1, i32* %0, align 4, !tbaa !6 + %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 1 + store i32 4, i32* %f32, align 4, !tbaa !8 + %2 = load i32** %s.addr, align 8, !tbaa !0 + %3 = load i32* %2, align 4, !tbaa !6 + ret i32 %3 +} + +define i32 @_Z2g2PjP7StructAy(i32* %s, %struct.StructA* %A, i64 %count) #0 { +entry: +; Access to i32* and &(A->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !8 <-> store i32 1, i32* %0, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %s.addr = alloca i32*, align 8 + %A.addr = alloca %struct.StructA*, align 8 + %count.addr = alloca i64, align 8 + store i32* %s, i32** %s.addr, align 8, !tbaa !0 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load i32** %s.addr, align 8, !tbaa !0 + store i32 1, i32* %0, align 4, !tbaa !6 + %1 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructA* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !11 + %2 = load i32** %s.addr, align 8, !tbaa !0 + %3 = load i32* %2, align 4, !tbaa !6 + ret i32 %3 +} + +define i32 @_Z2g3P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f321 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !12 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g4P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f16 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !14 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g5P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructB* %1, i32 0, i32 2 + store i32 4, i32* %f321, align 4, !tbaa !15 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g6P7StructAP7StructBy(%struct.StructA* %A, %struct.StructB* %B, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(B->a.f32_2). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f32_2, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %B.addr = alloca %struct.StructB*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructB* %B, %struct.StructB** %B.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructB** %B.addr, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %1, i32 0, i32 1 + %f32_2 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 3 + store i32 4, i32* %f32_2, align 4, !tbaa !16 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g7P7StructAP7StructSy(%struct.StructA* %A, %struct.StructS* %S, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(S->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %S.addr = alloca %struct.StructS*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !17 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g8P7StructAP7StructSy(%struct.StructA* %A, %struct.StructS* %S, i64 %count) #0 { +entry: +; Access to &(A->f32) and &(S->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %A.addr = alloca %struct.StructA*, align 8 + %S.addr = alloca %struct.StructS*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructA* %A, %struct.StructA** %A.addr, align 8, !tbaa !0 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructA* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !8 + %1 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructS* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !19 + %2 = load %struct.StructA** %A.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructA* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !8 + ret i32 %3 +} + +define i32 @_Z2g9P7StructSP8StructS2y(%struct.StructS* %S, %struct.StructS2* %S2, i64 %count) #0 { +entry: +; Access to &(S->f32) and &(S2->f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f321, align 4, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %S.addr = alloca %struct.StructS*, align 8 + %S2.addr = alloca %struct.StructS2*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !17 + %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 1 + store i32 4, i32* %f321, align 4, !tbaa !20 + %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f322 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1 + %3 = load i32* %f322, align 4, !tbaa !17 + ret i32 %3 +} + +define i32 @_Z3g10P7StructSP8StructS2y(%struct.StructS* %S, %struct.StructS2* %S2, i64 %count) #0 { +entry: +; Access to &(S->f32) and &(S2->f16). +; CHECK: Function +; CHECK: NoAlias: store i16 4, i16* %f16, align 2, !tbaa !10 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i16 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %S.addr = alloca %struct.StructS*, align 8 + %S2.addr = alloca %struct.StructS2*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructS* %S, %struct.StructS** %S.addr, align 8, !tbaa !0 + store %struct.StructS2* %S2, %struct.StructS2** %S2.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f32 = getelementptr inbounds %struct.StructS* %0, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !17 + %1 = load %struct.StructS2** %S2.addr, align 8, !tbaa !0 + %f16 = getelementptr inbounds %struct.StructS2* %1, i32 0, i32 0 + store i16 4, i16* %f16, align 2, !tbaa !22 + %2 = load %struct.StructS** %S.addr, align 8, !tbaa !0 + %f321 = getelementptr inbounds %struct.StructS* %2, i32 0, i32 1 + %3 = load i32* %f321, align 4, !tbaa !17 + ret i32 %3 +} + +define i32 @_Z3g11P7StructCP7StructDy(%struct.StructC* %C, %struct.StructD* %D, i64 %count) #0 { +entry: +; Access to &(C->b.a.f32) and &(D->b.a.f32). +; CHECK: Function +; CHECK: NoAlias: store i32 4, i32* %f323, align 4, !tbaa !12 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; Remove a load and propogate the value from store. +; OPT: ret i32 1 + %C.addr = alloca %struct.StructC*, align 8 + %D.addr = alloca %struct.StructD*, align 8 + %count.addr = alloca i64, align 8 + store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0 + store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1 + %a = getelementptr inbounds %struct.StructB* %b, i32 0, i32 1 + %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !23 + %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0 + %b1 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1 + %a2 = getelementptr inbounds %struct.StructB* %b1, i32 0, i32 1 + %f323 = getelementptr inbounds %struct.StructA* %a2, i32 0, i32 1 + store i32 4, i32* %f323, align 4, !tbaa !25 + %2 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b4 = getelementptr inbounds %struct.StructC* %2, i32 0, i32 1 + %a5 = getelementptr inbounds %struct.StructB* %b4, i32 0, i32 1 + %f326 = getelementptr inbounds %struct.StructA* %a5, i32 0, i32 1 + %3 = load i32* %f326, align 4, !tbaa !23 + ret i32 %3 +} + +define i32 @_Z3g12P7StructCP7StructDy(%struct.StructC* %C, %struct.StructD* %D, i64 %count) #0 { +entry: +; Access to &(b1->a.f32) and &(b2->a.f32). +; CHECK: Function +; CHECK: MayAlias: store i32 4, i32* %f325, align 4, !tbaa !6 <-> store i32 1, i32* %f32, align 4, !tbaa !6 +; OPT: define +; OPT: store i32 1 +; OPT: store i32 4 +; OPT: %[[RET:.*]] = load i32* +; OPT: ret i32 %[[RET]] + %C.addr = alloca %struct.StructC*, align 8 + %D.addr = alloca %struct.StructD*, align 8 + %count.addr = alloca i64, align 8 + %b1 = alloca %struct.StructB*, align 8 + %b2 = alloca %struct.StructB*, align 8 + store %struct.StructC* %C, %struct.StructC** %C.addr, align 8, !tbaa !0 + store %struct.StructD* %D, %struct.StructD** %D.addr, align 8, !tbaa !0 + store i64 %count, i64* %count.addr, align 8, !tbaa !4 + %0 = load %struct.StructC** %C.addr, align 8, !tbaa !0 + %b = getelementptr inbounds %struct.StructC* %0, i32 0, i32 1 + store %struct.StructB* %b, %struct.StructB** %b1, align 8, !tbaa !0 + %1 = load %struct.StructD** %D.addr, align 8, !tbaa !0 + %b3 = getelementptr inbounds %struct.StructD* %1, i32 0, i32 1 + store %struct.StructB* %b3, %struct.StructB** %b2, align 8, !tbaa !0 + %2 = load %struct.StructB** %b1, align 8, !tbaa !0 + %a = getelementptr inbounds %struct.StructB* %2, i32 0, i32 1 + %f32 = getelementptr inbounds %struct.StructA* %a, i32 0, i32 1 + store i32 1, i32* %f32, align 4, !tbaa !12 + %3 = load %struct.StructB** %b2, align 8, !tbaa !0 + %a4 = getelementptr inbounds %struct.StructB* %3, i32 0, i32 1 + %f325 = getelementptr inbounds %struct.StructA* %a4, i32 0, i32 1 + store i32 4, i32* %f325, align 4, !tbaa !12 + %4 = load %struct.StructB** %b1, align 8, !tbaa !0 + %a6 = getelementptr inbounds %struct.StructB* %4, i32 0, i32 1 + %f327 = getelementptr inbounds %struct.StructA* %a6, i32 0, i32 1 + %5 = load i32* %f327, align 4, !tbaa !12 + ret i32 %5 +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!0 = metadata !{metadata !1, metadata !1, i64 0} +!1 = metadata !{metadata !"any pointer", metadata !2} +!2 = metadata !{metadata !"omnipotent char", metadata !3} +!3 = metadata !{metadata !"Simple C/C++ TBAA"} +!4 = metadata !{metadata !5, metadata !5, i64 0} +!5 = metadata !{metadata !"long long", metadata !2} +!6 = metadata !{metadata !7, metadata !7, i64 0} +!7 = metadata !{metadata !"int", metadata !2} +!8 = metadata !{metadata !9, metadata !7, i64 4} +!9 = metadata !{metadata !"_ZTS7StructA", metadata !10, i64 0, metadata !7, i64 4, metadata !10, i64 8, metadata !7, i64 12} +!10 = metadata !{metadata !"short", metadata !2} +!11 = metadata !{metadata !9, metadata !10, i64 0} +!12 = metadata !{metadata !13, metadata !7, i64 8} +!13 = metadata !{metadata !"_ZTS7StructB", metadata !10, i64 0, metadata !9, i64 4, metadata !7, i64 20} +!14 = metadata !{metadata !13, metadata !10, i64 4} +!15 = metadata !{metadata !13, metadata !7, i64 20} +!16 = metadata !{metadata !13, metadata !7, i64 16} +!17 = metadata !{metadata !18, metadata !7, i64 4} +!18 = metadata !{metadata !"_ZTS7StructS", metadata !10, i64 0, metadata !7, i64 4} +!19 = metadata !{metadata !18, metadata !10, i64 0} +!20 = metadata !{metadata !21, metadata !7, i64 4} +!21 = metadata !{metadata !"_ZTS8StructS2", metadata !10, i64 0, metadata !7, i64 4} +!22 = metadata !{metadata !21, metadata !10, i64 0} +!23 = metadata !{metadata !24, metadata !7, i64 12} +!24 = metadata !{metadata !"_ZTS7StructC", metadata !10, i64 0, metadata !13, i64 4, metadata !7, i64 28} +!25 = metadata !{metadata !26, metadata !7, i64 12} +!26 = metadata !{metadata !"_ZTS7StructD", metadata !10, i64 0, metadata !13, i64 4, metadata !7, i64 28, metadata !2, i64 32} diff --git a/test/CodeGen/AArch64/adrp-relocation.ll b/test/CodeGen/AArch64/adrp-relocation.ll index c33b442624a5..cf411166a3a0 100644 --- a/test/CodeGen/AArch64/adrp-relocation.ll +++ b/test/CodeGen/AArch64/adrp-relocation.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | elf-dump | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -filetype=obj < %s | llvm-readobj -s -r | FileCheck %s define i64 @testfn() nounwind { entry: @@ -19,17 +19,9 @@ entry: ; relative offsets of testfn and foo) because its value depends on where this ; object file's .text section gets relocated in memory. -; CHECK: .rela.text - -; CHECK: # Relocation 0 -; CHECK-NEXT: (('r_offset', 0x0000000000000010) -; CHECK-NEXT: ('r_sym', 0x00000007) -; CHECK-NEXT: ('r_type', 0x00000113) -; CHECK-NEXT: ('r_addend', 0x0000000000000000) -; CHECK-NEXT: ), -; CHECK-NEXT: Relocation 1 -; CHECK-NEXT: (('r_offset', 0x0000000000000014) -; CHECK-NEXT: ('r_sym', 0x00000007) -; CHECK-NEXT: ('r_type', 0x00000115) -; CHECK-NEXT: ('r_addend', 0x0000000000000000) -; CHECK-NEXT: ), +; CHECK: Relocations [ +; CHECK-NEXT: Section (1) .text { +; CHECK-NEXT: 0x10 R_AARCH64_ADR_PREL_PG_HI21 testfn 0x0 +; CHECK-NEXT: 0x14 R_AARCH64_ADD_ABS_LO12_NC testfn 0x0 +; CHECK-NEXT: } +; CHECK-NEXT: ] diff --git a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll index 3c03e47147b0..9888a742e32b 100644 --- a/test/CodeGen/AArch64/atomic-ops-not-barriers.ll +++ b/test/CodeGen/AArch64/atomic-ops-not-barriers.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s define i32 @foo(i32* %var, i1 %cond) { ; CHECK: foo: @@ -9,7 +9,9 @@ simple_ver: store i32 %newval, i32* %var br label %somewhere atomic_ver: - %val = atomicrmw add i32* %var, i32 -1 seq_cst + fence seq_cst + %val = atomicrmw add i32* %var, i32 -1 monotonic + fence seq_cst br label %somewhere ; CHECK: dmb ; CHECK: ldxr diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index f3c16171cc83..5e87f21a217d 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -8,18 +8,18 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_add_i8: %old = atomicrmw add i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -27,19 +27,19 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_add_i16: - %old = atomicrmw add i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -47,8 +47,8 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_add_i32: - %old = atomicrmw add i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -57,9 +57,9 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -67,8 +67,8 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_add_i64: - %old = atomicrmw add i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw add i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -79,7 +79,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { ; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -87,8 +87,8 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_sub_i8: - %old = atomicrmw sub i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -99,7 +99,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -107,8 +107,8 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_sub_i16: - %old = atomicrmw sub i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -117,9 +117,9 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -127,19 +127,19 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_sub_i32: - %old = atomicrmw sub i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw sub i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -148,18 +148,18 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_sub_i64: %old = atomicrmw sub i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -167,8 +167,8 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_and_i8: - %old = atomicrmw and i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i8* @var8, i8 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -177,9 +177,9 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -187,8 +187,8 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_and_i16: - %old = atomicrmw and i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -199,7 +199,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -208,18 +208,18 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_and_i32: %old = atomicrmw and i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -227,19 +227,19 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_and_i64: - %old = atomicrmw and i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw and i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -248,18 +248,18 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_or_i8: %old = atomicrmw or i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -267,8 +267,8 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_or_i16: - %old = atomicrmw or i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -279,7 +279,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -287,19 +287,19 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_or_i32: - %old = atomicrmw or i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -307,8 +307,8 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_or_i64: - %old = atomicrmw or i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw or i64* @var64, i64 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -317,9 +317,9 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -327,19 +327,19 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_xor_i8: - %old = atomicrmw xor i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -347,8 +347,8 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_xor_i16: - %old = atomicrmw xor i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -357,9 +357,9 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -368,18 +368,18 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_xor_i32: %old = atomicrmw xor i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0 -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -387,8 +387,8 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_xor_i64: - %old = atomicrmw xor i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xor i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -399,7 +399,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { ; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -407,8 +407,8 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i8: - %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -418,7 +418,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { ; function there. ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -427,17 +427,17 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i16: %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -445,8 +445,8 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i32: - %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -454,9 +454,9 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { ; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -464,18 +464,18 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_xchg_i64: - %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw xchg i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -484,20 +484,20 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_min_i8: - %old = atomicrmw min i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -505,8 +505,8 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_min_i16: - %old = atomicrmw min i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i16* @var16, i16 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -516,9 +516,9 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt -; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -526,8 +526,8 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_min_i32: - %old = atomicrmw min i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw min i32* @var32, i32 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -539,7 +539,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -548,19 +548,19 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_min_i64: %old = atomicrmw min i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -569,19 +569,19 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_max_i8: %old = atomicrmw max i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -589,20 +589,20 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_max_i16: - %old = atomicrmw max i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], sxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -610,8 +610,8 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_max_i32: - %old = atomicrmw max i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i32* @var32, i32 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -621,9 +621,9 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lt -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -631,8 +631,8 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_max_i64: - %old = atomicrmw max i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw max i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -644,7 +644,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lt ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -652,8 +652,8 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_umin_i8: - %old = atomicrmw umin i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 @@ -665,7 +665,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -673,20 +673,20 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_umin_i16: - %old = atomicrmw umin i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], uxth ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -695,19 +695,19 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_umin_i32: %old = atomicrmw umin i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -715,20 +715,20 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_umin_i64: - %old = atomicrmw umin i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umin i64* @var64, i64 %offset acq_rel +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]] ; x0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -736,20 +736,20 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { ; CHECK: test_atomic_load_umax_i8: - %old = atomicrmw umax i8* @var8, i8 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i8* @var8, i8 %offset acq_rel +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]], uxtb ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -757,8 +757,8 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { ; CHECK: test_atomic_load_umax_i16: - %old = atomicrmw umax i16* @var16, i16 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 @@ -770,7 +770,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -779,19 +779,19 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { ; CHECK: test_atomic_load_umax_i32: %old = atomicrmw umax i32* @var32, i32 %offset seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 ; CHECK: .LBB{{[0-9]+}}_1: -; CHECK-NEXT: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w0, w[[OLD]] ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, lo -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -799,8 +799,8 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { ; CHECK: test_atomic_load_umax_i64: - %old = atomicrmw umax i64* @var64, i64 %offset seq_cst -; CHECK: dmb ish + %old = atomicrmw umax i64* @var64, i64 %offset release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -810,9 +810,9 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { ; function there. ; CHECK-NEXT: cmp x0, x[[OLD]] ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, lo -; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] +; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1 -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -820,13 +820,13 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i8: - %old = cmpxchg i8* @var8, i8 %wanted, i8 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 @@ -834,7 +834,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { ; As above, w1 is a reasonable guess. ; CHECK: stxrb [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i8 %old @@ -843,20 +843,20 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i16: %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var16 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]: -; CHECK-NEXT: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]] +; CHECK-NEXT: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]] ; w0 below is a reasonable guess but could change: it certainly comes into the ; function there. ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK: stxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK: stlxrh [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i16 %old @@ -864,8 +864,8 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i32: - %old = cmpxchg i32* @var32, i32 %wanted, i32 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var32 @@ -876,9 +876,9 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { ; CHECK-NEXT: cmp w[[OLD]], w0 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]] ; As above, w1 is a reasonable guess. -; CHECK: stxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] +; CHECK: stlxr [[STATUS:w[0-9]+]], w1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i32 %old @@ -886,8 +886,8 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; CHECK: test_atomic_cmpxchg_i64: - %old = cmpxchg i64* @var64, i64 %wanted, i64 %new seq_cst -; CHECK: dmb ish + %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var64 @@ -900,7 +900,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { ; As above, w1 is a reasonable guess. ; CHECK: stxr [[STATUS:w[0-9]+]], x1, [x[[ADDR]]] ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]] -; CHECK: dmb ish +; CHECK-NOT: dmb ; CHECK: mov x0, x[[OLD]] ret i64 %old @@ -933,19 +933,26 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { define i8 @test_atomic_load_acquire_i8() nounwind { ; CHECK: test_atomic_load_acquire_i8: %val = load atomic i8* @var8 acquire, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], #:lo12:var8 - +; CHECK-NOT: dmb ; CHECK: ldarb w0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i8 %val } define i8 @test_atomic_load_seq_cst_i8() nounwind { ; CHECK: test_atomic_load_seq_cst_i8: %val = load atomic i8* @var8 seq_cst, align 1 -; CHECK: adrp x[[HIADDR:[0-9]+]], var8 -; CHECK: ldrb w0, [x[[HIADDR]], #:lo12:var8] -; CHECK: dmb ish +; CHECK-NOT: dmb +; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb +; CHECK: ldarb w0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i8 %val } @@ -954,6 +961,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind { %val = load atomic i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK-NOT: dmb ; CHECK: ldrh w0, [x[[HIADDR]], #:lo12:var16] ; CHECK-NOT: dmb @@ -976,9 +984,13 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind define i64 @test_atomic_load_seq_cst_i64() nounwind { ; CHECK: test_atomic_load_seq_cst_i64: %val = load atomic i64* @var64 seq_cst, align 8 -; CHECK: adrp x[[HIADDR:[0-9]+]], var64 -; CHECK: ldr x0, [x[[HIADDR]], #:lo12:var64] -; CHECK: dmb ish +; CHECK-NOT: dmb +; CHECK: adrp [[HIADDR:x[0-9]+]], var64 +; CHECK-NOT: dmb +; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK-NOT: dmb +; CHECK: ldar x0, [x[[ADDR]]] +; CHECK-NOT: dmb ret i64 %val } @@ -1005,20 +1017,26 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) define void @test_atomic_store_release_i8(i8 %val) nounwind { ; CHECK: test_atomic_store_release_i8: store atomic i8 %val, i8* @var8 release, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] - +; CHECK-NOT: dmb ret void } define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { ; CHECK: test_atomic_store_seq_cst_i8: store atomic i8 %val, i8* @var8 seq_cst, align 1 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var8 +; CHECK-NOT: dmb ; CHECK: stlrb w0, [x[[ADDR]]] -; CHECK: dmb ish +; CHECK-NOT: dmb ret void } @@ -1026,9 +1044,11 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { ; CHECK: test_atomic_store_monotonic_i16: store atomic i16 %val, i16* @var16 monotonic, align 2 +; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 +; CHECK-NOT: dmb ; CHECK: strh w0, [x[[HIADDR]], #:lo12:var16] - +; CHECK-NOT: dmb ret void } @@ -1039,7 +1059,9 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va %addr = inttoptr i64 %addr_int to i32* store atomic i32 %val, i32* %addr monotonic, align 4 +; CHECK-NOT: dmb ; CHECK: str w2, [x0, x1] +; CHECK-NOT: dmb ret void } @@ -1047,9 +1069,12 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va define void @test_atomic_store_release_i64(i64 %val) nounwind { ; CHECK: test_atomic_store_release_i64: store atomic i64 %val, i64* @var64 release, align 8 +; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 +; CHECK-NOT: dmb ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], #:lo12:var64 +; CHECK-NOT: dmb ; CHECK: stlr x0, [x[[ADDR]]] - +; CHECK-NOT: dmb ret void } diff --git a/test/CodeGen/AArch64/blockaddress.ll b/test/CodeGen/AArch64/blockaddress.ll index 3d0a5cf96bcd..5e85057a3c3b 100644 --- a/test/CodeGen/AArch64/blockaddress.ll +++ b/test/CodeGen/AArch64/blockaddress.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -code-model=large -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-LARGE %s @addr = global i8* null @@ -13,6 +14,14 @@ define void @test_blockaddress() { ; CHECK: ldr [[NEWDEST:x[0-9]+]] ; CHECK: br [[NEWDEST]] +; CHECK-LARGE: movz [[ADDR_REG:x[0-9]+]], #:abs_g3:[[DEST_LBL:.Ltmp[0-9]+]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g2_nc:[[DEST_LBL]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g1_nc:[[DEST_LBL]] +; CHECK-LARGE: movk [[ADDR_REG]], #:abs_g0_nc:[[DEST_LBL]] +; CHECK-LARGE: str [[ADDR_REG]], +; CHECK-LARGE: ldr [[NEWDEST:x[0-9]+]] +; CHECK-LARGE: br [[NEWDEST]] + block: ret void } diff --git a/test/CodeGen/AArch64/code-model-large-abs.ll b/test/CodeGen/AArch64/code-model-large-abs.ll new file mode 100644 index 000000000000..a365568e11ee --- /dev/null +++ b/test/CodeGen/AArch64/code-model-large-abs.ll @@ -0,0 +1,61 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large < %s | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define i8* @global_addr() { +; CHECK: global_addr: + ret i8* @var8 + ; The movz/movk calculation should end up returned directly in x0. +; CHECK: movz x0, #:abs_g3:var8 +; CHECK: movk x0, #:abs_g2_nc:var8 +; CHECK: movk x0, #:abs_g1_nc:var8 +; CHECK: movk x0, #:abs_g0_nc:var8 +; CHECK-NEXT: ret +} + +define i8 @global_i8() { +; CHECK: global_i8: + %val = load i8* @var8 + ret i8 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var8 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var8 +; CHECK: ldrb w0, [x[[ADDR_REG]]] +} + +define i16 @global_i16() { +; CHECK: global_i16: + %val = load i16* @var16 + ret i16 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16 +; CHECK: ldrh w0, [x[[ADDR_REG]]] +} + +define i32 @global_i32() { +; CHECK: global_i32: + %val = load i32* @var32 + ret i32 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var32 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var32 +; CHECK: ldr w0, [x[[ADDR_REG]]] +} + +define i64 @global_i64() { +; CHECK: global_i64: + %val = load i64* @var64 + ret i64 %val +; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var64 +; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var64 +; CHECK: ldr x0, [x[[ADDR_REG]]] +} diff --git a/test/CodeGen/AArch64/elf-extern.ll b/test/CodeGen/AArch64/elf-extern.ll index ee89d8d94ba4..8bf1b2ff4fa9 100644 --- a/test/CodeGen/AArch64/elf-extern.ll +++ b/test/CodeGen/AArch64/elf-extern.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s ; External symbols are a different concept to global variables but should still ; get relocations and so on when used. @@ -10,12 +10,8 @@ define i32 @check_extern() { ret i32 0 } -; CHECK: .rela.text -; CHECK: ('r_sym', 0x00000009) -; CHECK-NEXT: ('r_type', 0x0000011b) - -; CHECK: .symtab -; CHECK: Symbol 9 -; CHECK-NEXT: memcpy - - +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_AARCH64_CALL26 memcpy +; CHECK: } +; CHECK: ] diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll index 3d3d8676818a..bc0acc253388 100644 --- a/test/CodeGen/AArch64/extern-weak.ll +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -o - < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s declare extern_weak i32 @var() @@ -11,6 +12,12 @@ define i32()* @foo() { ; CHECK: ldr x0, [{{x[0-9]+}}, #:lo12:.LCPI0_0] + ; In the large model, the usual relocations are absolute and can + ; materialise 0. +; CHECK-LARGE: movz x0, #:abs_g3:var +; CHECK-LARGE: movk x0, #:abs_g2_nc:var +; CHECK-LARGE: movk x0, #:abs_g1_nc:var +; CHECK-LARGE: movk x0, #:abs_g0_nc:var } @@ -24,6 +31,13 @@ define i32* @bar() { ; CHECK: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, #:lo12:.LCPI1_0] ; CHECK: add x0, [[BASE]], #20 ret i32* %addr + + ; In the large model, the usual relocations are absolute and can + ; materialise 0. +; CHECK-LARGE: movz x0, #:abs_g3:arr_var +; CHECK-LARGE: movk x0, #:abs_g2_nc:arr_var +; CHECK-LARGE: movk x0, #:abs_g1_nc:arr_var +; CHECK-LARGE: movk x0, #:abs_g0_nc:arr_var } @defined_weak_var = internal unnamed_addr global i32 0 @@ -32,4 +46,9 @@ define i32* @wibble() { ret i32* @defined_weak_var ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var ; CHECK: add x0, [[BASE]], #:lo12:defined_weak_var + +; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var +; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var }
\ No newline at end of file diff --git a/test/CodeGen/AArch64/jump-table.ll b/test/CodeGen/AArch64/jump-table.ll index dcf9f4ed455c..3c7f5f9ec1b0 100644 --- a/test/CodeGen/AArch64/jump-table.ll +++ b/test/CodeGen/AArch64/jump-table.ll @@ -1,5 +1,6 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | elf-dump | FileCheck %s -check-prefix=CHECK-ELF +; RUN: llc -code-model=large -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck --check-prefix=CHECK-LARGE %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -filetype=obj | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-ELF define i32 @test_jumptable(i32 %in) { ; CHECK: test_jumptable @@ -15,6 +16,13 @@ define i32 @test_jumptable(i32 %in) { ; CHECK: ldr [[DEST:x[0-9]+]], [x[[JT]], {{x[0-9]+}}, lsl #3] ; CHECK: br [[DEST]] +; CHECK-LARGE: movz x[[JTADDR:[0-9]+]], #:abs_g3:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g2_nc:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g1_nc:.LJTI0_0 +; CHECK-LARGE: movk x[[JTADDR]], #:abs_g0_nc:.LJTI0_0 +; CHECK-LARGE: ldr [[DEST:x[0-9]+]], [x[[JTADDR]], {{x[0-9]+}}, lsl #3] +; CHECK-LARGE: br [[DEST]] + def: ret i32 0 @@ -44,13 +52,15 @@ lbl4: ; ELF tests: ; First make sure we get a page/lo12 pair in .text to pick up the jump-table -; CHECK-ELF: .rela.text -; CHECK-ELF: ('r_sym', 0x00000008) -; CHECK-ELF-NEXT: ('r_type', 0x00000113) -; CHECK-ELF: ('r_sym', 0x00000008) -; CHECK-ELF-NEXT: ('r_type', 0x00000115) + +; CHECK-ELF: Relocations [ +; CHECK-ELF: Section ({{[0-9]+}}) .text { +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 .rodata +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC .rodata +; CHECK-ELF: } ; Also check the targets in .rodata are relocated -; CHECK-ELF: .rela.rodata -; CHECK-ELF: ('r_sym', 0x00000005) -; CHECK-ELF-NEXT: ('r_type', 0x00000101)
\ No newline at end of file +; CHECK-ELF: Section ({{[0-9]+}}) .rodata { +; CHECK-ELF-NEXT: 0x{{[0-9,A-F]+}} R_AARCH64_ABS64 .text +; CHECK-ELF: } +; CHECK-ELF: ] diff --git a/test/CodeGen/AArch64/literal_pools.ll b/test/CodeGen/AArch64/literal_pools.ll index e09084148fdf..9cfa8c5426e4 100644 --- a/test/CodeGen/AArch64/literal_pools.ll +++ b/test/CodeGen/AArch64/literal_pools.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK-LARGE %s @var32 = global i32 0 @var64 = global i64 0 @@ -13,21 +14,45 @@ define void @foo() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]] + %val64_lit32 = and i64 %val64, 305402420 store volatile i64 %val64_lit32, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]] + %val64_lit32signed = and i64 %val64, -12345678 store volatile i64 %val64_lit32signed, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldrsw {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldrsw {{x[0-9]+}}, [x[[LITADDR]]] + %val64_lit64 = and i64 %val64, 1234567898765432 store volatile i64 %val64_lit64, i64* @var64 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]] ; CHECK: ldr {{x[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{x[0-9]+}}, [x[[LITADDR]]] + ret void } @@ -42,6 +67,14 @@ define void @floating_lits() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] ; CHECK: ldr {{s[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] ; CHECK: fadd + +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{s[0-9]+}}, [x[[LITADDR]]] +; CHECK-LARGE: fadd + store float %newfloat, float* @varfloat %doubleval = load double* @vardouble @@ -49,6 +82,13 @@ define void @floating_lits() { ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI1_[0-9]+]] ; CHECK: ldr {{d[0-9]+}}, [x[[LITBASE]], #:lo12:[[CURLIT]]] ; CHECK: fadd + +; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI1_[0-9]+]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]] +; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]] +; CHECK-LARGE: ldr {{d[0-9]+}}, [x[[LITADDR]]] + store double %newdouble, double* @vardouble ret void diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 91a9903f3852..112512ff59a5 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -79,7 +79,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] !2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} !5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index 36d15757c314..b253fefe87c4 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -1,36 +1,47 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ ; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=CORTEXA8 %s ; This tests that the extpected ARM attributes are emitted. ; -; BASIC: .ARM.attributes -; BASIC-NEXT: 0x70000003 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x0000003c -; BASIC-NEXT: 0x00000022 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: 0x00000001 -; BASIC-NEXT: 0x00000000 -; BASIC-NEXT: '41210000 00616561 62690001 17000000 060a0741 08010902 14011501 17031801 1901' +; BASIC: Section { +; BASIC: Name: .ARM.attributes +; BASIC-NEXT: Type: SHT_ARM_ATTRIBUTES +; BASIC-NEXT: Flags [ (0x0) +; BASIC-NEXT: ] +; BASIC-NEXT: Address: 0x0 +; BASIC-NEXT: Offset: 0x3C +; BASIC-NEXT: Size: 34 +; BASIC-NEXT: Link: 0 +; BASIC-NEXT: Info: 0 +; BASIC-NEXT: AddressAlignment: 1 +; BASIC-NEXT: EntrySize: 0 +; BASIC-NEXT: SectionData ( +; BASIC-NEXT: 0000: 41210000 00616561 62690001 17000000 +; BASIC-NEXT: 0010: 060A0741 08010902 14011501 17031801 +; BASIC-NEXT: 0020: 1901 +; BASIC-NEXT: ) -; CORTEXA8: .ARM.attributes -; CORTEXA8-NEXT: 0x70000003 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x0000003c -; CORTEXA8-NEXT: 0x0000002f -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: 0x00000001 -; CORTEXA8-NEXT: 0x00000000 -; CORTEXA8-NEXT: '412e0000 00616561 62690001 24000000 05434f52 5445582d 41380006 0a074108 0109020a 02140115 01170318 011901' +; CORTEXA8: Name: .ARM.attributes +; CORTEXA8-NEXT: Type: SHT_ARM_ATTRIBUTES +; CORTEXA8-NEXT: Flags [ (0x0) +; CORTEXA8-NEXT: ] +; CORTEXA8-NEXT: Address: 0x0 +; CORTEXA8-NEXT: Offset: 0x3C +; CORTEXA8-NEXT: Size: 47 +; CORTEXA8-NEXT: Link: 0 +; CORTEXA8-NEXT: Info: 0 +; CORTEXA8-NEXT: AddressAlignment: 1 +; CORTEXA8-NEXT: EntrySize: 0 +; CORTEXA8-NEXT: SectionData ( +; CORTEXA8-NEXT: 0000: 412E0000 00616561 62690001 24000000 +; CORTEXA8-NEXT: 0010: 05434F52 5445582D 41380006 0A074108 +; CORTEXA8-NEXT: 0020: 0109020A 02140115 01170318 011901 +; CORTEXA8-NEXT: ) define i32 @f(i64 %z) { ret i32 0 diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll index 94a05412f5d4..9eecd045bfa0 100644 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +; RUN: llvm-readobj -s -sr -sd | FileCheck -check-prefix=OBJ %s target triple = "armv7-none-linux-gnueabi" @@ -9,32 +9,17 @@ define arm_aapcs_vfpcc i32 @barf() nounwind { entry: %0 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind ret i32 %0 -; OBJ: '.text' -; OBJ-NEXT: 'sh_type' -; OBJ-NEXT: 'sh_flags' -; OBJ-NEXT: 'sh_addr' -; OBJ-NEXT: 'sh_offset' -; OBJ-NEXT: 'sh_size' -; OBJ-NEXT: 'sh_link' -; OBJ-NEXT: 'sh_info' -; OBJ-NEXT: 'sh_addralign' -; OBJ-NEXT: 'sh_entsize' -; OBJ-NEXT: '_section_data', '00482de9 000000e3 000040e3 feffffeb 0088bde8' - -; OBJ: Relocation 0 -; OBJ-NEXT: 'r_offset', 0x00000004 -; OBJ-NEXT: 'r_sym', 0x000009 -; OBJ-NEXT: 'r_type', 0x2b - -; OBJ: Relocation 1 -; OBJ-NEXT: 'r_offset', 0x00000008 -; OBJ-NEXT: 'r_sym' -; OBJ-NEXT: 'r_type', 0x2c - -; OBJ: # Relocation 2 -; OBJ-NEXT: 'r_offset', 0x0000000c -; OBJ-NEXT: 'r_sym', 0x00000a -; OBJ-NEXT: 'r_type', 0x1c +; OBJ: Section { +; OBJ: Name: .text +; OBJ: Relocations [ +; OBJ-NEXT: 0x4 R_ARM_MOVW_ABS_NC a +; OBJ-NEXT: 0x8 R_ARM_MOVT_ABS +; OBJ-NEXT: 0xC R_ARM_CALL foo +; OBJ-NEXT: ] +; OBJ-NEXT: SectionData ( +; OBJ-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB +; OBJ-NEXT: 0010: 0088BDE8 +; OBJ-NEXT: ) } diff --git a/test/CodeGen/ARM/2010-12-08-tpsoft.ll b/test/CodeGen/ARM/2010-12-08-tpsoft.ll index b8ed8199d398..1351a26756ef 100644 --- a/test/CodeGen/ARM/2010-12-08-tpsoft.ll +++ b/test/CodeGen/ARM/2010-12-08-tpsoft.ll @@ -1,9 +1,9 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ ; RUN: FileCheck -check-prefix=ELFASM %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=ELFOBJ %s +; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ %s -;; Make sure that bl __aeabi_read_tp is materiazlied and fixed up correctly +;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly ;; in the obj case. @i = external thread_local global i32 @@ -24,19 +24,13 @@ bb: ; preds = %entry ; ELFASM: bl __aeabi_read_tp -; ELFOBJ: '.text' -; ELFOBJ-NEXT: 'sh_type' -; ELFOBJ-NEXT: 'sh_flags' -; ELFOBJ-NEXT: 'sh_addr' -; ELFOBJ-NEXT: 'sh_offset' -; ELFOBJ-NEXT: 'sh_size' -; ELFOBJ-NEXT: 'sh_link' -; ELFOBJ-NEXT: 'sh_info' -; ELFOBJ-NEXT: 'sh_addralign' -; ELFOBJ-NEXT: 'sh_entsize' -;;; BL __aeabi_read_tp is ---+ -;;; V -; ELFOBJ-NEXT: 00482de9 3c009fe5 00109fe7 feffffeb +; ELFOBJ: Sections [ +; ELFOBJ: Section { +; ELFOBJ: Name: .text +; ELFOBJ: SectionData ( +;;; BL __aeabi_read_tp is ---------+ +;;; V +; ELFOBJ-NEXT: 0000: 00482DE9 3C009FE5 00109FE7 FEFFFFEB bb1: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index 1272a257931d..f13bc1214a5a 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +; RUN: llvm-readobj -s -t | FileCheck -check-prefix=OBJ %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -o - | \ ; RUN: FileCheck -check-prefix=ASM %s @@ -15,17 +15,20 @@ ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals +; OBJ: Sections [ +; OBJ: Section { +; OBJ: Index: 4 +; OBJ-NEXT: Name: .bss -; OBJ: Section 4 -; OBJ-NEXT: '.bss' - -; OBJ: 'array00' -; OBJ-NEXT: 'st_value', 0x00000000 -; OBJ-NEXT: 'st_size', 0x00000050 -; OBJ-NEXT: 'st_bind', 0x0 -; OBJ-NEXT: 'st_type', 0x1 -; OBJ-NEXT: 'st_other', 0x00 -; OBJ-NEXT: 'st_shndx', 0x0004 +; OBJ: Symbols [ +; OBJ: Symbol { +; OBJ: Name: array00 +; OBJ-NEXT: Value: 0x0 +; OBJ-NEXT: Size: 80 +; OBJ-NEXT: Binding: Local +; OBJ-NEXT: Type: Object +; OBJ-NEXT: Other: 0 +; OBJ-NEXT: Section: .bss define i32 @main(i32 %argc) nounwind { %1 = load i32* @sum, align 4 diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 1d1b89a34f9a..98c0af35ef9a 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -79,7 +79,7 @@ entry: !0 = metadata !{i32 786478, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5} !5 = metadata !{i32 786468, metadata !1, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 266609b8ce69..7a7ca8e0d8d9 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -74,7 +74,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !40, metadata !41, metadata !41, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/ARM/2011-12-14-machine-sink.ll b/test/CodeGen/ARM/2011-12-14-machine-sink.ll index 1b21f7571d8e..9334bf36d805 100644 --- a/test/CodeGen/ARM/2011-12-14-machine-sink.ll +++ b/test/CodeGen/ARM/2011-12-14-machine-sink.ll @@ -15,13 +15,13 @@ for.cond: ; preds = %for.body, %entry for.body: ; preds = %for.cond %v.5 = select i1 undef, i32 undef, i32 0 - %0 = load i8* undef, align 1, !tbaa !0 + %0 = load i8* undef, align 1 %conv88 = zext i8 %0 to i32 %sub89 = sub nsw i32 0, %conv88 %v.8 = select i1 undef, i32 undef, i32 %sub89 - %1 = load i8* null, align 1, !tbaa !0 + %1 = load i8* null, align 1 %conv108 = zext i8 %1 to i32 - %2 = load i8* undef, align 1, !tbaa !0 + %2 = load i8* undef, align 1 %conv110 = zext i8 %2 to i32 %sub111 = sub nsw i32 %conv108, %conv110 %cmp112 = icmp slt i32 %sub111, 0 @@ -44,6 +44,3 @@ if.end299: ; preds = %for.body, %for.cond %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] ret i32 %s.10 } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll index 926daafbb7f1..0f1c452b8678 100644 --- a/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll +++ b/test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll @@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2 br i1 %tmp, label %bb4, label %bb67 bb4: ; preds = %bb3 - %tmp5 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp5 = load <4 x i32>* undef, align 16 %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> @@ -41,9 +41,9 @@ bb4: ; preds = %bb3 %tmp24 = trunc i128 %tmp23 to i64 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 - %tmp27 = load float* undef, align 4, !tbaa !2 + %tmp27 = load float* undef, align 4 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 - %tmp29 = load <4 x i32>* undef, align 16, !tbaa !0 + %tmp29 = load <4 x i32>* undef, align 16 %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> @@ -52,10 +52,10 @@ bb4: ; preds = %bb3 %tmp35 = fmul <4 x float> %tmp34, undef %tmp36 = fmul <4 x float> %tmp35, undef %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp38 = load float* undef, align 4, !tbaa !2 + %tmp38 = load float* undef, align 4 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp41 = load float* undef, align 4, !tbaa !2 + %tmp41 = load float* undef, align 4 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp44 = fmul <4 x float> %tmp33, %tmp43 @@ -64,10 +64,10 @@ bb4: ; preds = %bb3 %tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp48 = fadd <4 x float> undef, %tmp47 %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind - %tmp50 = load float* undef, align 4, !tbaa !2 + %tmp50 = load float* undef, align 4 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind - %tmp54 = load float* %tmp52, align 4, !tbaa !2 + %tmp54 = load float* %tmp52, align 4 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind @@ -99,7 +99,3 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} -!2 = metadata !{metadata !"float", metadata !0} diff --git a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll index f1c85f1b41f5..61623ec1b6a4 100644 --- a/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll +++ b/test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll @@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi" ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { bb: - %tmp = load <2 x float>* undef, align 8, !tbaa !0 + %tmp = load <2 x float>* undef, align 8 %tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 @@ -70,6 +70,3 @@ entry: declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll index 5f24e427c229..a9e2ebb7fe12 100644 --- a/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll +++ b/test/CodeGen/ARM/2012-01-26-CopyPropKills.ll @@ -56,9 +56,9 @@ bb3: ; preds = %bb2 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> - %tmp42 = load <4 x float>* null, align 16, !tbaa !0 + %tmp42 = load <4 x float>* null, align 16 %tmp43 = fmul <4 x float> %tmp42, %tmp41 - %tmp44 = load <4 x float>* undef, align 16, !tbaa !0 + %tmp44 = load <4 x float>* undef, align 16 %tmp45 = fadd <4 x float> undef, %tmp43 %tmp46 = fadd <4 x float> undef, %tmp45 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> @@ -108,7 +108,7 @@ bb3: ; preds = %bb2 %tmp89 = fmul <4 x float> undef, %tmp88 %tmp90 = fadd <4 x float> %tmp89, undef %tmp91 = fadd <4 x float> undef, %tmp90 - store <4 x float> %tmp91, <4 x float>* undef, align 16, !tbaa !0 + store <4 x float> %tmp91, <4 x float>* undef, align 16 unreachable bb92: ; preds = %bb2 @@ -116,6 +116,3 @@ bb92: ; preds = %bb2 } declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll b/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll index 33ad187926bf..0843fdc4e75e 100644 --- a/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll +++ b/test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll @@ -9,16 +9,13 @@ define arm_aapcs_vfpcc void @foo() nounwind align 2 { ; <label>:1 ; preds = %0 %2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1> %3 = bitcast <2 x i64> %2 to <4 x float> - store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0 - store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0 - store <4 x float> %3, <4 x float>* undef, align 16, !tbaa !0 + store <4 x float> zeroinitializer, <4 x float>* undef, align 16 + store <4 x float> zeroinitializer, <4 x float>* undef, align 16 + store <4 x float> %3, <4 x float>* undef, align 16 %4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2 - store <4 x float> %4, <4 x float>* undef, align 16, !tbaa !0 + store <4 x float> %4, <4 x float>* undef, align 16 unreachable ; <label>:5 ; preds = %0 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-04-10-DAGCombine.ll b/test/CodeGen/ARM/2012-04-10-DAGCombine.ll index 6f50f279b5de..089dc9153afa 100644 --- a/test/CodeGen/ARM/2012-04-10-DAGCombine.ll +++ b/test/CodeGen/ARM/2012-04-10-DAGCombine.ll @@ -20,12 +20,9 @@ bb5: ; preds = %bb4 %tmp15 = shufflevector <2 x float> %tmp14, <2 x float> undef, <4 x i32> zeroinitializer %tmp16 = fmul <4 x float> zeroinitializer, %tmp15 %tmp17 = fadd <4 x float> %tmp16, %arg - store <4 x float> %tmp17, <4 x float>* undef, align 8, !tbaa !0 + store <4 x float> %tmp17, <4 x float>* undef, align 8 br label %bb18 bb18: ; preds = %bb5, %bb4 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index ca0964a05933..a288015d6016 100644 --- a/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -26,18 +26,14 @@ ; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: - store volatile i32 65540, i32* %p1, align 4, !tbaa !0 - %0 = load volatile i32* %p2, align 4, !tbaa !0 + store volatile i32 65540, i32* %p1, align 4 + %0 = load volatile i32* %p2, align 4 ret i32 %0 } define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: - store i32 65540, i32* %p1, align 4, !tbaa !0 - %0 = load i32* %p2, align 4, !tbaa !0 + store i32 65540, i32* %p1, align 4 + %0 = load i32* %p2, align 4 ret i32 %0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll index e4ad45bf526e..adb5c7e4b259 100644 --- a/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll +++ b/test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll @@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %45 = fmul <4 x float> undef, undef %46 = fmul <4 x float> %45, %43 %47 = fmul <4 x float> undef, %44 - %48 = load <4 x float>* undef, align 8, !tbaa !1 + %48 = load <4 x float>* undef, align 8 %49 = bitcast <4 x float> %48 to <2 x i64> %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1> %51 = bitcast <1 x i64> %50 to <2 x float> @@ -145,10 +145,10 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable %61 = fmul <4 x float> %59, %60 %62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01> %63 = fadd <4 x float> %47, %62 - store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1 + store <4 x float> %46, <4 x float>* undef, align 8 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind - store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1 + store <4 x float> %63, <4 x float>* undef, align 8 unreachable ; <label>:64 ; preds = %41, %40 @@ -170,5 +170,3 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable declare arm_aapcs_vfpcc void @bar(%0*, float) !0 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll index 38b9e0e8f086..05abdeda0f19 100644 --- a/test/CodeGen/ARM/2013-01-21-PR14992.ll +++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll @@ -6,11 +6,11 @@ ;CHECK: foo: define i32 @foo(i32* %a) nounwind optsize { entry: - %0 = load i32* %a, align 4, !tbaa !0 + %0 = load i32* %a, align 4 %arrayidx1 = getelementptr inbounds i32* %a, i32 1 - %1 = load i32* %arrayidx1, align 4, !tbaa !0 + %1 = load i32* %arrayidx1, align 4 %arrayidx2 = getelementptr inbounds i32* %a, i32 2 - %2 = load i32* %arrayidx2, align 4, !tbaa !0 + %2 = load i32* %arrayidx2, align 4 %add.ptr = getelementptr inbounds i32* %a, i32 3 ;Make sure we do not have a duplicated register in the front of the reg list ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, @@ -22,7 +22,3 @@ entry: } declare void @bar(i32*) optsize - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll new file mode 100644 index 000000000000..4a5ca9db0e50 --- /dev/null +++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -0,0 +1,73 @@ +;PR15293: ARM codegen ice - expected larger existing stack allocation +;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s + +;CHECK: foo: +;CHECK: sub sp, sp, #8 +;CHECK: push {r11, lr} +;CHECK: str r0, [sp, #12] +;CHECK: add r0, sp, #12 +;CHECK: bl fooUseParam +;CHECK: pop {r11, lr} +;CHECK: add sp, sp, #8 +;CHECK: mov pc, lr + +;CHECK: foo2: +;CHECK: sub sp, sp, #16 +;CHECK: push {r11, lr} +;CHECK: str r0, [sp, #12] +;CHECK: add r0, sp, #12 +;CHECK: str r2, [sp, #16] +;CHECK: bl fooUseParam +;CHECK: add r0, sp, #16 +;CHECK: bl fooUseParam +;CHECK: pop {r11, lr} +;CHECK: add sp, sp, #16 +;CHECK: mov pc, lr + +;CHECK: doFoo: +;CHECK: push {r11, lr} +;CHECK: ldr r0, +;CHECK: ldr r0, [r0] +;CHECK: bl foo +;CHECK: pop {r11, lr} +;CHECK: mov pc, lr + + +;CHECK: doFoo2: +;CHECK: push {r11, lr} +;CHECK: ldr r0, +;CHECK: mov r1, #0 +;CHECK: ldr r0, [r0] +;CHECK: mov r2, r0 +;CHECK: bl foo2 +;CHECK: pop {r11, lr} +;CHECK: mov pc, lr + + +%artz = type { i32 } +@static_val = constant %artz { i32 777 } + +declare void @fooUseParam(%artz* ) + +define void @foo(%artz* byval %s) { + call void @fooUseParam(%artz* %s) + ret void +} + +define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) { + call void @fooUseParam(%artz* %s) + call void @fooUseParam(%artz* %s2) + ret void +} + + +define void @doFoo() { + call void @foo(%artz* byval @static_val) + ret void +} + +define void @doFoo2() { + call void @foo2(%artz* byval @static_val, i32 0, %artz* byval @static_val) + ret void +} + diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll new file mode 100644 index 000000000000..38d515f9227f --- /dev/null +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll @@ -0,0 +1,95 @@ +;Check 5.5 Parameter Passing --> Stage C --> C.4 statement, when NSAA is not +;equal to SP. +; +; Our purpose: make NSAA != SP, and only after start to use GPRs. +; +;Co-Processor register candidates may be either in VFP or in stack, so after +;all VFP are allocated, stack is used. We can use stack without GPR allocation +;in that case, passing 9 f64 params, for example. +;First eight params goes to d0-d7, ninth one goes to the stack. +;Now, as 10th parameter, we pass i32, and it must go to R0. +; +;5.5 Parameter Passing, Stage C: +; +;C.2.cp If the argument is a CPRC then any co-processor registers in that class +;that are unallocated are marked as unavailable. The NSAA is adjusted upwards +;until it is correctly aligned for the argument and the argument is copied to +;the memory at the adjusted NSAA. The NSAA is further incremented by the size +;of the argument. The argument has now been allocated. +;... +;C.4 If the size in words of the argument is not more than r4 minus NCRN, the +;argument is copied into core registers, starting at the NCRN. The NCRN is +;incremented by the number of registers used. Successive registers hold the +;parts of the argument they would hold if its value were loaded into those +;registers from memory using an LDM instruction. The argument has now been +;allocated. +; +;What is actually checked here: +;Here we check that i32 param goes to r0. +; +;Current test-case was produced with command: +;arm-linux-gnueabihf-clang -mcpu=cortex-a9 params-to-GPR.c -S -O1 -emit-llvm +; +;// params-to-GRP.c: +; +;void fooUseI32(unsigned); +; +;void foo(long double p0, +; long double p1, +; long double p2, +; long double p3, +; long double p4, +; long double p5, +; long double p6, +; long double p7, +; long double p8, +; unsigned p9) { +; fooUseI32(p9); +;} +; +;void doFoo() { +; foo( 1,2,3,4,5,6,7,8,9, 43 ); +;} + +;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s +; +;CHECK: foo: +;CHECK-NOT: mov r0 +;CHECK-NOT: ldr r0 +;CHECK: bl fooUseI32 +;CHECK: doFoo: +;CHECK: movs r0, #43 +;CHECK: bl foo + +define void @foo(double %p0, ; --> D0 + double %p1, ; --> D1 + double %p2, ; --> D2 + double %p3, ; --> D3 + double %p4, ; --> D4 + double %p5, ; --> D5 + double %p6, ; --> D6 + double %p7, ; --> D7 + double %p8, ; --> Stack + i32 %p9) #0 { ; --> R0, not Stack+8 +entry: + tail call void @fooUseI32(i32 %p9) + ret void +} + +declare void @fooUseI32(i32) + +define void @doFoo() { +entry: + tail call void @foo(double 23.0, ; --> D0 + double 23.1, ; --> D1 + double 23.2, ; --> D2 + double 23.3, ; --> D3 + double 23.4, ; --> D4 + double 23.5, ; --> D5 + double 23.6, ; --> D6 + double 23.7, ; --> D7 + double 23.8, ; --> Stack + i32 43) ; --> R0, not Stack+8 + ret void +} + diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll new file mode 100644 index 000000000000..446403d79cac --- /dev/null +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C5-vs-VFP.ll @@ -0,0 +1,61 @@ +;Check 5.5 Parameter Passing --> Stage C --> C.5 statement, when NSAA is not +;equal to SP. +; +; Our purpose: make NSAA != SP, and only after start to use GPRs, then pass +; byval parameter and check that it goes to stack only. +; +;Co-Processor register candidates may be either in VFP or in stack, so after +;all VFP are allocated, stack is used. We can use stack without GPR allocation +;in that case, passing 9 f64 params, for example. +;First eight params goes to d0-d7, ninth one goes to the stack. +;Now, as 10th parameter, we pass i32, and it must go to R0. +; +;For more information, +;please, read 5.5 Parameter Passing, Stage C, stages C.2.cp, C.4 and C.5 +; +; +;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s + +%struct_t = type { i32, i32, i32, i32 } +@static_val = constant %struct_t { i32 777, i32 888, i32 999, i32 1000 } +declare void @fooUseStruct(%struct_t*) + +define void @foo2(double %p0, ; --> D0 + double %p1, ; --> D1 + double %p2, ; --> D2 + double %p3, ; --> D3 + double %p4, ; --> D4 + double %p5, ; --> D5 + double %p6, ; --> D6 + double %p7, ; --> D7 + double %p8, ; --> Stack + i32 %p9, ; --> R0 + %struct_t* byval %p10) ; --> Stack+8 +{ +entry: +;CHECK: push.w {r11, lr} +;CHECK-NOT: stm +;CHECK: add r0, sp, #16 +;CHECK: bl fooUseStruct + call void @fooUseStruct(%struct_t* %p10) + + ret void +} + +define void @doFoo2() { +entry: +;CHECK-NOT: ldm + tail call void @foo2(double 23.0, ; --> D0 + double 23.1, ; --> D1 + double 23.2, ; --> D2 + double 23.3, ; --> D3 + double 23.4, ; --> D4 + double 23.5, ; --> D5 + double 23.6, ; --> D6 + double 23.7, ; --> D7 + double 23.8, ; --> Stack + i32 43, ; --> R0, not Stack+8 + %struct_t* byval @static_val) ; --> Stack+8, not R1 + ret void +} + diff --git a/test/CodeGen/ARM/2013-04-05-overridden-loads-PR14824.ll b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll index 2561686c1f83..459992818749 100644 --- a/test/CodeGen/ARM/2013-04-05-overridden-loads-PR14824.ll +++ b/test/CodeGen/ARM/2013-04-18-load-overlap-PR14824.ll @@ -1,18 +1,17 @@ ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp | FileCheck %s -; The test is presented by Jiangning Liu. -;CHECK-NOT: vldmia +; PR14824. The test is presented by Jiangning Liu. If the ld/st optimization algorithm is changed, this test case may fail. +; Also if the machine code for ld/st optimizor is changed, this test case may fail. If so, remove this test. define void @sample_test(<8 x i64> * %secondSource, <8 x i64> * %source, <8 x i64> * %dest) nounwind { +; CHECK: sample_test +; CHECK-NOT: vldmia +; CHECK: add entry: + +; Load %source %s0 = load <8 x i64> * %source, align 64 - %s1 = load <8 x i64> * %secondSource, align 64 - %s2 = bitcast <8 x i64> %s0 to i512 - %data.i.i.48.extract.shift = lshr i512 %s2, 384 - %data.i.i.48.extract.trunc = trunc i512 %data.i.i.48.extract.shift to i64 %arrayidx64 = getelementptr inbounds <8 x i64> * %source, i32 6 %s120 = load <8 x i64> * %arrayidx64, align 64 - %arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6 - %s121 = load <8 x i64> * %arrayidx67, align 64 %s122 = bitcast <8 x i64> %s120 to i512 %data.i.i677.48.extract.shift = lshr i512 %s122, 384 %data.i.i677.48.extract.trunc = trunc i512 %data.i.i677.48.extract.shift to i64 @@ -32,6 +31,11 @@ entry: %s128 = insertelement <8 x i64> %s127, i64 %data.i.i677.32.extract.trunc, i32 5 %s129 = insertelement <8 x i64> %s128, i64 %data.i.i677.16.extract.trunc, i32 6 %s130 = insertelement <8 x i64> %s129, i64 %data.i.i677.56.extract.trunc, i32 7 + +; Load %secondSource + %s1 = load <8 x i64> * %secondSource, align 64 + %arrayidx67 = getelementptr inbounds <8 x i64> * %secondSource, i32 6 + %s121 = load <8 x i64> * %arrayidx67, align 64 %s131 = bitcast <8 x i64> %s121 to i512 %data.i1.i676.48.extract.shift = lshr i512 %s131, 384 %data.i1.i676.48.extract.trunc = trunc i512 %data.i1.i676.48.extract.shift to i64 @@ -51,34 +55,16 @@ entry: %s137 = insertelement <8 x i64> %s136, i64 %data.i1.i676.32.extract.trunc, i32 5 %s138 = insertelement <8 x i64> %s137, i64 %data.i1.i676.16.extract.trunc, i32 6 %s139 = insertelement <8 x i64> %s138, i64 %data.i1.i676.56.extract.trunc, i32 7 + +; Operations about %Source and %secondSource %vecinit28.i.i699 = shufflevector <8 x i64> %s139, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 undef, i32 undef, i32 undef> %vecinit35.i.i700 = shufflevector <8 x i64> %vecinit28.i.i699, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef> %vecinit42.i.i701 = shufflevector <8 x i64> %vecinit35.i.i700, <8 x i64> %s139, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef> %vecinit49.i.i702 = shufflevector <8 x i64> %vecinit42.i.i701, <8 x i64> %s130, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> %arrayidx72 = getelementptr inbounds <8 x i64> * %dest, i32 6 store <8 x i64> %vecinit49.i.i702, <8 x i64> * %arrayidx72, align 64 - %arrayidx75 = getelementptr inbounds <8 x i64> * %source, i32 7 - %s140 = load <8 x i64> * %arrayidx75, align 64 %arrayidx78 = getelementptr inbounds <8 x i64> * %secondSource, i32 7 %s141 = load <8 x i64> * %arrayidx78, align 64 - %s142 = bitcast <8 x i64> %s140 to i512 - %data.i.i650.32.extract.shift = lshr i512 %s142, 256 - %data.i.i650.32.extract.trunc = trunc i512 %data.i.i650.32.extract.shift to i64 - %s143 = insertelement <8 x i64> undef, i64 %data.i.i650.32.extract.trunc, i32 0 - %s144 = insertelement <8 x i64> %s143, i64 %data.i.i650.32.extract.trunc, i32 1 - %data.i.i650.16.extract.shift = lshr i512 %s142, 128 - %data.i.i650.16.extract.trunc = trunc i512 %data.i.i650.16.extract.shift to i64 - %s145 = insertelement <8 x i64> %s144, i64 %data.i.i650.16.extract.trunc, i32 2 - %data.i.i650.8.extract.shift = lshr i512 %s142, 64 - %data.i.i650.8.extract.trunc = trunc i512 %data.i.i650.8.extract.shift to i64 - %s146 = insertelement <8 x i64> %s145, i64 %data.i.i650.8.extract.trunc, i32 3 - %s147 = insertelement <8 x i64> %s146, i64 %data.i.i650.8.extract.trunc, i32 4 - %data.i.i650.48.extract.shift = lshr i512 %s142, 384 - %data.i.i650.48.extract.trunc = trunc i512 %data.i.i650.48.extract.shift to i64 - %s148 = insertelement <8 x i64> %s147, i64 %data.i.i650.48.extract.trunc, i32 5 - %s149 = insertelement <8 x i64> %s148, i64 %data.i.i650.16.extract.trunc, i32 6 - %data.i.i650.0.extract.trunc = trunc i512 %s142 to i64 - %s150 = insertelement <8 x i64> %s149, i64 %data.i.i650.0.extract.trunc, i32 7 %s151 = bitcast <8 x i64> %s141 to i512 %data.i1.i649.32.extract.shift = lshr i512 %s151, 256 %data.i1.i649.32.extract.trunc = trunc i512 %data.i1.i649.32.extract.shift to i64 @@ -90,21 +76,7 @@ entry: %data.i1.i649.8.extract.shift = lshr i512 %s151, 64 %data.i1.i649.8.extract.trunc = trunc i512 %data.i1.i649.8.extract.shift to i64 %s155 = insertelement <8 x i64> %s154, i64 %data.i1.i649.8.extract.trunc, i32 3 - %s156 = insertelement <8 x i64> %s155, i64 %data.i1.i649.8.extract.trunc, i32 4 - %data.i1.i649.48.extract.shift = lshr i512 %s151, 384 - %data.i1.i649.48.extract.trunc = trunc i512 %data.i1.i649.48.extract.shift to i64 - %s157 = insertelement <8 x i64> %s156, i64 %data.i1.i649.48.extract.trunc, i32 5 - %s158 = insertelement <8 x i64> %s157, i64 %data.i1.i649.16.extract.trunc, i32 6 - %data.i1.i649.0.extract.trunc = trunc i512 %s151 to i64 - %s159 = insertelement <8 x i64> %s158, i64 %data.i1.i649.0.extract.trunc, i32 7 - %vecinit7.i.i669 = shufflevector <8 x i64> %s159, <8 x i64> %s150, <8 x i32> <i32 0, i32 9, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - %vecinit14.i.i670 = shufflevector <8 x i64> %vecinit7.i.i669, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 10, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> - %vecinit21.i.i671 = shufflevector <8 x i64> %vecinit14.i.i670, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 2, i32 11, i32 undef, i32 undef, i32 undef, i32 undef> - %vecinit28.i.i672 = shufflevector <8 x i64> %vecinit21.i.i671, <8 x i64> %s150, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 undef, i32 undef, i32 undef> - %vecinit35.i.i673 = shufflevector <8 x i64> %vecinit28.i.i672, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 13, i32 undef, i32 undef> - %vecinit42.i.i674 = shufflevector <8 x i64> %vecinit35.i.i673, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 14, i32 undef> - %vecinit49.i.i675 = shufflevector <8 x i64> %vecinit42.i.i674, <8 x i64> %s159, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15> %arrayidx83 = getelementptr inbounds <8 x i64> * %dest, i32 7 - store <8 x i64> %vecinit49.i.i675, <8 x i64> * %arrayidx83, align 64 + store <8 x i64> %s155, <8 x i64> * %arrayidx83, align 64 ret void } diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll new file mode 100644 index 000000000000..de5fd31e2f2d --- /dev/null +++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll @@ -0,0 +1,28 @@ +;Check 5.5 Parameter Passing --> Stage C --> C.1.cp statement for VA functions. +;Note: There are no VFP CPRCs in a variadic procedure. +;Check that after %C was sent to stack, we set Next Core Register Number to R4. + +;This test is simplified IR version of +;test-suite/SingleSource/UnitTests/2002-05-02-ManyArguments.c + +;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s + +@.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1 + +;CHECK: printfn: +define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { +entry: + %conv = sext i16 %b to i32 + %conv1 = sext i8 %E to i32 + %call = tail call i32 (i8*, ...)* @printf( + i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), ; --> R0 + i32 %a, ; --> R1 + i32 %conv, ; --> R2 + double %C, ; --> SP, NCRN := R4 +;CHECK: str r2, [sp, #8] + i32 %conv1) ; --> SP+8 + ret void +} + +declare i32 @printf(i8* nocapture, ...) + diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll new file mode 100644 index 000000000000..6db71fed958e --- /dev/null +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP.ll @@ -0,0 +1,48 @@ +;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules. +;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4 +;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s + +%st_t = type { i32, i32 } +@static_val = constant %st_t { i32 777, i32 888} + +declare void @fooUseStruct(%st_t*) + +define void @foo(double %vfp0, ; --> D0, NSAA=SP + double %vfp1, ; --> D1, NSAA=SP + double %vfp2, ; --> D2, NSAA=SP + double %vfp3, ; --> D3, NSAA=SP + double %vfp4, ; --> D4, NSAA=SP + double %vfp5, ; --> D5, NSAA=SP + double %vfp6, ; --> D6, NSAA=SP + double %vfp7, ; --> D7, NSAA=SP + double %vfp8, ; --> SP, NSAA=SP+8 (!) + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval %p1, ; --> R1, R2, NSAA=SP+8 + i32 %p2, ; --> R3, NSAA=SP+8 + i32 %p3) #0 { ; --> SP+4, NSAA=SP+12 +entry: + ;CHECK: sub sp, #8 + ;CHECK: push.w {r11, lr} + ;CHECK: add r0, sp, #16 + ;CHECK: str r2, [sp, #20] + ;CHECK: str r1, [sp, #16] + ;CHECK: bl fooUseStruct + call void @fooUseStruct(%st_t* %p1) + ret void +} + +define void @doFoo() { +entry: + call void @foo(double 23.0, + double 23.1, + double 23.2, + double 23.3, + double 23.4, + double 23.5, + double 23.6, + double 23.7, + double 23.8, + i32 0, %st_t* byval @static_val, i32 1, i32 2) + ret void +} + diff --git a/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll new file mode 100644 index 000000000000..212bbc2ee9c8 --- /dev/null +++ b/test/CodeGen/ARM/2013-05-02-AAPCS-ByVal-Structs-C4-C5-VFP2.ll @@ -0,0 +1,45 @@ +;Check AAPCS, 5.5 Parameters Passing, C4 and C5 rules. +;Check case when NSAA != 0, and NCRN < R4, NCRN+ParamSize > R4 +;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s + +%st_t = type { i32, i32, i32, i32 } +@static_val = constant %st_t { i32 777, i32 888, i32 787, i32 878} + +define void @foo(double %vfp0, ; --> D0, NSAA=SP + double %vfp1, ; --> D1, NSAA=SP + double %vfp2, ; --> D2, NSAA=SP + double %vfp3, ; --> D3, NSAA=SP + double %vfp4, ; --> D4, NSAA=SP + double %vfp5, ; --> D5, NSAA=SP + double %vfp6, ; --> D6, NSAA=SP + double %vfp7, ; --> D7, NSAA=SP + double %vfp8, ; --> SP, NSAA=SP+8 (!) + i32 %p0, ; --> R0, NSAA=SP+8 + %st_t* byval %p1, ; --> SP+8, 4 words NSAA=SP+24 + i32 %p2) #0 { ; --> SP+24, NSAA=SP+24 + +entry: + ;CHECK: push.w {r11, lr} + ;CHECK: ldr r0, [sp, #32] + ;CHECK: bl fooUseI32 + call void @fooUseI32(i32 %p2) + ret void +} + +declare void @fooUseI32(i32) + +define void @doFoo() { +entry: + call void @foo(double 23.0, + double 23.1, + double 23.2, + double 23.3, + double 23.4, + double 23.5, + double 23.6, + double 23.7, + double 23.8, + i32 0, %st_t* byval @static_val, i32 1) + ret void +} + diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll new file mode 100644 index 000000000000..abc6e0d11144 --- /dev/null +++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll @@ -0,0 +1,71 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s +; rdar://13782395 + +define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { +; CHECK: t1: +; CHECK: Block address taken +; CHECK-NOT: Address of block that was removed by CodeGen + store i8* blockaddress(@t1, %cond_true), i8** %retaddr + %tmp2 = icmp eq i32 %a, 0 + br i1 %tmp2, label %cond_false, label %cond_true + +cond_true: + %tmp5 = add i32 %b, 1 + ret i32 %tmp5 + +cond_false: + %tmp7 = add i32 %b, -1 + ret i32 %tmp7 +} + +define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) { +; CHECK: t2: +; CHECK: Block address taken +; CHECK: %cond_true +; CHECK: add +; CHECK: bx lr + store i8* blockaddress(@t2, %cond_true), i8** %retaddr + %tmp2 = icmp sgt i32 %c, 10 + %tmp5 = icmp slt i32 %d, 4 + %tmp8 = and i1 %tmp5, %tmp2 + %tmp13 = add i32 %b, %a + br i1 %tmp8, label %cond_true, label %UnifiedReturnBlock + +cond_true: + %tmp15 = add i32 %tmp13, %c + %tmp1821 = sub i32 %tmp15, %d + ret i32 %tmp1821 + +UnifiedReturnBlock: + ret i32 %tmp13 +} + +define hidden fastcc void @t3(i8** %retaddr) { +; CHECK: t3: +; CHECK: Block address taken +; CHECK-NOT: Address of block that was removed by CodeGen +bb: + store i8* blockaddress(@t3, %KBBlockZero_return_1), i8** %retaddr + br i1 undef, label %bb77, label %bb7.i + +bb7.i: ; preds = %bb35 + br label %bb2.i + +KBBlockZero_return_1: ; preds = %KBBlockZero.exit + unreachable + +KBBlockZero_return_0: ; preds = %KBBlockZero.exit + unreachable + +bb77: ; preds = %bb26, %bb12, %bb + ret void + +bb2.i: ; preds = %bb6.i350, %bb7.i + br i1 undef, label %bb6.i350, label %KBBlockZero.exit + +bb6.i350: ; preds = %bb2.i + br label %bb2.i + +KBBlockZero.exit: ; preds = %bb2.i + indirectbr i8* undef, [label %KBBlockZero_return_1, label %KBBlockZero_return_0] +} diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll index c5d00a0f8a4c..c14f5302d311 100644 --- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -91,7 +91,7 @@ entry: ; CHECK: t4 ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: if.then -; CHECK-NOT movs +; CHECK-NOT: movs %0 = load double* %q, align 4 %cmp = fcmp olt double %0, 1.000000e+01 %incdec.ptr1 = getelementptr inbounds i32* %p, i32 1 diff --git a/test/CodeGen/ARM/commute-movcc.ll b/test/CodeGen/ARM/commute-movcc.ll index 769ba55eb9eb..fbc25b45b6ff 100644 --- a/test/CodeGen/ARM/commute-movcc.ll +++ b/test/CodeGen/ARM/commute-movcc.ll @@ -32,7 +32,7 @@ for.body: ; preds = %entry, %if.end8 %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ] %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ] %arrayidx = getelementptr inbounds i32* %a, i32 %i.012 - %0 = load i32* %arrayidx, align 4, !tbaa !0 + %0 = load i32* %arrayidx, align 4 %mul = mul i32 %0, %0 %sub = add nsw i32 %i.012, -5 %cmp2 = icmp eq i32 %sub, %Pref @@ -53,7 +53,7 @@ if.else: ; preds = %for.body if.end8: ; preds = %if.else, %if.then %BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ] %BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ] - store i32 %mul, i32* %arrayidx, align 4, !tbaa !0 + store i32 %mul, i32* %arrayidx, align 4 %inc = add i32 %i.012, 1 %cmp = icmp eq i32 %inc, 11 br i1 %cmp, label %for.end, label %for.body @@ -61,7 +61,3 @@ if.end8: ; preds = %if.else, %if.then for.end: ; preds = %if.end8 ret i32 %BestIdx.1 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll new file mode 100644 index 000000000000..e9e0fe3239a7 --- /dev/null +++ b/test/CodeGen/ARM/dagcombine-concatvector.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s + +; PR15525 +; CHECK: test1: +; CHECK: ldr.w [[REG:r[0-9]+]], [sp] +; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2 +; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]] +; CHECK-NEXT: vst1.8 {{{d[0-9]+}}, {{d[0-9]+}}}, [r0] +; CHECK-NEXT: bx lr +define void @test1(i8* %arg, [4 x i64] %vec.coerce) { +bb: + %tmp = extractvalue [4 x i64] %vec.coerce, 0 + %tmp2 = bitcast i64 %tmp to <8 x i8> + %tmp3 = shufflevector <8 x i8> %tmp2, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %tmp4 = extractvalue [4 x i64] %vec.coerce, 1 + %tmp5 = bitcast i64 %tmp4 to <8 x i8> + %tmp6 = shufflevector <8 x i8> %tmp5, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + %tmp7 = shufflevector <16 x i8> %tmp6, <16 x i8> %tmp3, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + tail call void @llvm.arm.neon.vst1.v16i8(i8* %arg, <16 x i8> %tmp7, i32 2) + ret void +} + +declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 33c8e9daae69..c162260dcd0c 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -31,7 +31,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !30, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !30, null, null, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index 95e6cf2554a0..38945ac2ea7b 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -40,7 +40,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index e3e4d068932e..e4040fa02caa 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -60,7 +60,7 @@ declare i32 @puts(i8* nocapture) nounwind !0 = metadata !{i32 786478, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, null, null, metadata !42, null, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, null, null, metadata !42, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index 038c2296cdbe..1de6ffaeec7d 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -39,7 +39,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !50, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index f3af0b93c69c..186894232eaf 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -65,7 +65,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !47, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, null, null, metadata !47, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index ae02a245b432..ba83f797e2ce 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -41,7 +41,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, null, null, metadata !16, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !2, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, null, null, metadata !16, null, null, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/ARM/ehabi-filters.ll b/test/CodeGen/ARM/ehabi-filters.ll index c42839d9fe3d..4c92a2975d39 100644 --- a/test/CodeGen/ARM/ehabi-filters.ll +++ b/test/CodeGen/ARM/ehabi-filters.ll @@ -19,7 +19,7 @@ define i32 @main() { entry: %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind %0 = bitcast i8* %exception.i to i32* - store i32 42, i32* %0, align 4, !tbaa !0 + store i32 42, i32* %0, align 4 invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn to label %unreachable.i unwind label %lpad.i @@ -71,7 +71,3 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll b/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll new file mode 100644 index 000000000000..11f3e6db0fe5 --- /dev/null +++ b/test/CodeGen/ARM/ehabi-mc-compact-pr0.ll @@ -0,0 +1,49 @@ +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -r - \ +; RUN: | FileCheck %s --check-prefix=CHECK-RELOC + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -filetype=obj -o - %s \ +; RUN: | llvm-objdump -r - \ +; RUN: | FileCheck %s --check-prefix=CHECK-RELOC + +define void @_Z4testv() { +entry: + tail call void @_Z15throw_exceptionv() + ret void +} + +declare void @_Z15throw_exceptionv() + +; CHECK-NOT: section .ARM.extab +; CHECK: section .text +; CHECK-NOT: section .ARM.extab +; CHECK: section .ARM.exidx +; CHECK-NEXT: 0000 00000000 80849b80 +; CHECK-NOT: section .ARM.extab + +; CHECK-FP-ELIM-NOT: section .ARM.extab +; CHECK-FP-ELIM: section .text +; CHECK-FP-ELIM-NOT: section .ARM.extab +; CHECK-FP-ELIM: section .ARM.exidx +; CHECK-FP-ELIM-NEXT: 0000 00000000 b0808480 +; CHECK-FP-ELIM-NOT: section .ARM.extab + +; CHECK-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-RELOC-NEXT: 0 R_ARM_PREL31 .text +; CHECK-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 diff --git a/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll b/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll new file mode 100644 index 000000000000..79dba084c044 --- /dev/null +++ b/test/CodeGen/ARM/ehabi-mc-compact-pr1.ll @@ -0,0 +1,62 @@ +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -r - \ +; RUN: | FileCheck %s --check-prefix=CHECK-RELOC + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -filetype=obj -o - %s \ +; RUN: | llvm-objdump -r - \ +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM-RELOC + +define i32 @_Z3addiiiiiiii(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) { +entry: + %add = add nsw i32 %b, %a + %add1 = add nsw i32 %add, %c + %add2 = add nsw i32 %add1, %d + tail call void @_Z15throw_exceptioni(i32 %add2) + %add3 = add nsw i32 %f, %e + %add4 = add nsw i32 %add3, %g + %add5 = add nsw i32 %add4, %h + tail call void @_Z15throw_exceptioni(i32 %add5) + %add6 = add nsw i32 %add5, %add2 + ret i32 %add6 +} + +declare void @_Z15throw_exceptioni(i32) + +; CHECK-NOT: section .ARM.extab +; CHECK: section .text +; CHECK: section .ARM.extab +; CHECK-NEXT: 0000 419b0181 b0b08384 +; CHECK: section .ARM.exidx +; CHECK-NEXT: 0000 00000000 00000000 +; CHECK-NOT: section .ARM.extab + +; CHECK-FP-ELIM-NOT: section .ARM.extab +; CHECK-FP-ELIM: section .text +; CHECK-FP-ELIM-NOT: section .ARM.extab +; CHECK-FP-ELIM: section .ARM.exidx +; CHECK-FP-ELIM-NEXT: 0000 00000000 b0838480 +; CHECK-FP-ELIM-NOT: section .ARM.extab + +; CHECK-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-RELOC-NEXT: 0 R_ARM_PREL31 .text +; CHECK-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr1 + +; CHECK-FP-ELIM-RELOC: RELOCATION RECORDS FOR [.ARM.exidx] +; CHECK-FP-ELIM-RELOC-NEXT: 0 R_ARM_PREL31 .text +; CHECK-FP-ELIM-RELOC-NEXT: 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 diff --git a/test/CodeGen/ARM/ehabi-mc-section-group.ll b/test/CodeGen/ARM/ehabi-mc-section-group.ll index 5e4b5096c494..616aa1ba46e7 100644 --- a/test/CodeGen/ARM/ehabi-mc-section-group.ll +++ b/test/CodeGen/ARM/ehabi-mc-section-group.ll @@ -8,7 +8,7 @@ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ ; RUN: -filetype=obj -o - %s \ -; RUN: | elf-dump --dump-section-data \ +; RUN: | llvm-readobj -s -sd \ ; RUN: | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" @@ -68,12 +68,21 @@ declare void @__cxa_end_catch() declare void @_ZSt9terminatev() -; CHECK: # Section 1 -; CHECK-NEXT: (('sh_name', 0x0000002f) # '.group' -; CHECK: ('_section_data', '01000000 0a000000 0c000000 0e000000') -; CHECK: # Section 10 -; CHECK-NEXT: (('sh_name', 0x000000e1) # '.text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_' -; CHECK: # Section 12 -; CHECK-NEXT: (('sh_name', 0x000000d7) # '.ARM.extab.text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_' -; CHECK: # Section 14 -; CHECK-NEXT: (('sh_name', 0x00000065) # '.ARM.exidx.text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_' +; CHECK: Section { +; CHECK: Index: 1 +; CHECK-NEXT: Name: .group (47) +; CHECK: SectionData ( +; CHECK-NEXT: 0000: 01000000 09000000 0B000000 0D000000 +; CHECK-NEXT: ) + +; CHECK: Section { +; CHECK: Index: 9 +; CHECK-NEXT: Name: .text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_ (214) + +; CHECK: Section { +; CHECK: Index: 11 +; CHECK-NEXT: Name: .ARM.extab.text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_ (204) + +; CHECK: Section { +; CHECK: Index: 13 +; CHECK-NEXT: Name: .ARM.exidx.text._Z4testIidEvT_S0_S0_S0_S0_T0_S1_S1_S1_S1_ (90) diff --git a/test/CodeGen/ARM/ehabi-mc-section.ll b/test/CodeGen/ARM/ehabi-mc-section.ll index fc51b240ff3d..4e6e46829148 100644 --- a/test/CodeGen/ARM/ehabi-mc-section.ll +++ b/test/CodeGen/ARM/ehabi-mc-section.ll @@ -1,8 +1,14 @@ -; RUN: llc -mtriple arm-unknown-linux-gnueabi \ +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ ; RUN: -filetype=obj -o - %s \ ; RUN: | llvm-objdump -s - \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM define void @_Z4testiiiiiddddd(i32 %u1, i32 %u2, i32 %u3, i32 %u4, i32 %u5, double %v1, double %v2, double %v3, double %v4, double %v5) section ".test_section" { entry: @@ -54,6 +60,12 @@ declare void @_ZSt9terminatev() ; CHECK: section .test_section ; CHECK: section .ARM.extab.test_section -; CHECK-NEXT: 0000 00000000 b0b0b000 +; CHECK-NEXT: 0000 00000000 c9409b01 b0818484 ; CHECK: section .ARM.exidx.test_section ; CHECK-NEXT: 0000 00000000 00000000 + +; CHECK-FP-ELIM: section .test_section +; CHECK-FP-ELIM: section .ARM.extab.test_section +; CHECK-FP-ELIM-NEXT: 0000 00000000 84c90501 b0b0b0a8 +; CHECK-FP-ELIM: section .ARM.exidx.test_section +; CHECK-FP-ELIM-NEXT: 0000 00000000 00000000 diff --git a/test/CodeGen/ARM/ehabi-mc-sh_link.ll b/test/CodeGen/ARM/ehabi-mc-sh_link.ll index f90e5f384c1e..ac0a0fc9309a 100644 --- a/test/CodeGen/ARM/ehabi-mc-sh_link.ll +++ b/test/CodeGen/ARM/ehabi-mc-sh_link.ll @@ -7,7 +7,7 @@ ; RUN: llc -mtriple arm-unknown-linux-gnueabi \ ; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ ; RUN: -filetype=obj -o - %s \ -; RUN: | elf-dump --dump-section-data \ +; RUN: | llvm-readobj -s \ ; RUN: | FileCheck %s define void @test1() nounwind { @@ -20,28 +20,39 @@ entry: ret void } -; CHECK: # Section 1 -; CHECK-NEXT: (('sh_name', 0x00000010) # '.text' +; CHECK: Sections [ +; CHECK: Section { +; CHECK: Index: 1 +; CHECK-NEXT: Name: .text (16) -; CHECK: (('sh_name', 0x00000005) # '.ARM.exidx' -; CHECK-NEXT: ('sh_type', 0x70000001) -; CHECK-NEXT: ('sh_flags', 0x00000082) -; CHECK-NEXT: ('sh_addr', 0x00000000) -; CHECK-NEXT: ('sh_offset', 0x0000005c) -; CHECK-NEXT: ('sh_size', 0x00000008) -; CHECK-NEXT: ('sh_link', 0x00000001) -; CHECK-NEXT: ('sh_info', 0x00000000) -; CHECK-NEXT: ('sh_addralign', 0x00000004) +; CHECK: Section { +; CHECK: Name: .ARM.exidx (5) +; CHECK-NEXT: Type: SHT_ARM_EXIDX +; CHECK-NEXT: Flags [ (0x82) +; CHECK-NEXT: SHF_ALLOC +; CHECK-NEXT: SHF_LINK_ORDER +; CHECK-NEXT: ] +; CHECK-NEXT: Address: 0x0 +; CHECK-NEXT: Offset: 0x5C +; CHECK-NEXT: Size: 8 +; CHECK-NEXT: Link: 1 +; CHECK-NEXT: Info: 0 +; CHECK-NEXT: AddressAlignment: 4 -; CHECK: # Section 7 -; CHECK-NEXT: (('sh_name', 0x00000039) # '.test_section' +; CHECK: Section { +; CHECK: Index: 7 +; CHECK-NEXT: Name: .test_section (57) -; CHECK: (('sh_name', 0x0000002f) # '.ARM.exidx.test_section' -; CHECK-NEXT: ('sh_type', 0x70000001) -; CHECK-NEXT: ('sh_flags', 0x00000082) -; CHECK-NEXT: ('sh_addr', 0x00000000) -; CHECK-NEXT: ('sh_offset', 0x00000068) -; CHECK-NEXT: ('sh_size', 0x00000008) -; CHECK-NEXT: ('sh_link', 0x00000007) -; CHECK-NEXT: ('sh_info', 0x00000000) -; CHECK-NEXT: ('sh_addralign', 0x00000004) +; CHECK: Section { +; CHECK: Name: .ARM.exidx.test_section (47) +; CHECK-NEXT: Type: SHT_ARM_EXIDX +; CHECK-NEXT: Flags [ (0x82) +; CHECK-NEXT: SHF_ALLOC +; CHECK-NEXT: SHF_LINK_ORDER +; CHECK-NEXT: ] +; CHECK-NEXT: Address: 0x0 +; CHECK-NEXT: Offset: 0x68 +; CHECK-NEXT: Size: 8 +; CHECK-NEXT: Link: 7 +; CHECK-NEXT: Info: 0 +; CHECK-NEXT: AddressAlignment: 4 diff --git a/test/CodeGen/ARM/ehabi-mc.ll b/test/CodeGen/ARM/ehabi-mc.ll index 0dc2ef7838f0..83b8425af7c4 100644 --- a/test/CodeGen/ARM/ehabi-mc.ll +++ b/test/CodeGen/ARM/ehabi-mc.ll @@ -1,8 +1,14 @@ -; RUN: llc -mtriple arm-unknown-linux-gnueabi \ +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ +; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ +; RUN: -disable-fp-elim -filetype=obj -o - %s \ +; RUN: | llvm-objdump -s - \ +; RUN: | FileCheck %s --check-prefix=CHECK + +; RUN: llc -mtriple armv7-unknown-linux-gnueabi \ ; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \ ; RUN: -filetype=obj -o - %s \ ; RUN: | llvm-objdump -s - \ -; RUN: | FileCheck %s +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM define void @_Z4testiiiiiddddd(i32 %u1, i32 %u2, i32 %u3, i32 %u4, i32 %u5, double %v1, double %v2, double %v3, double %v4, double %v5) { entry: @@ -54,6 +60,12 @@ declare void @_ZSt9terminatev() ; CHECK: section .text ; CHECK: section .ARM.extab -; CHECK-NEXT: 0000 00000000 b0b0b000 +; CHECK-NEXT: 0000 00000000 c9409b01 b0818484 ; CHECK: section .ARM.exidx ; CHECK-NEXT: 0000 00000000 00000000 + +; CHECK-FP-ELIM: section .text +; CHECK-FP-ELIM: section .ARM.extab +; CHECK-FP-ELIM-NEXT: 0000 00000000 84c90501 b0b0b0a8 +; CHECK-FP-ELIM: section .ARM.exidx +; CHECK-FP-ELIM-NEXT: 0000 00000000 00000000 diff --git a/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll b/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll new file mode 100644 index 000000000000..00027119f9e0 --- /dev/null +++ b/test/CodeGen/ARM/gpr-paired-spill-thumbinst.ll @@ -0,0 +1,30 @@ +; REQUIRES: asserts +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -debug -o /dev/null < %s 2>&1 | FileCheck %s + +; This test makes sure spills of 64-bit pairs in Thumb mode actually +; generate thumb instructions. Previously we were inserting an ARM +; STMIA which happened to have the same encoding. + +define void @foo(i64* %addr) { + %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + + ; Make sure we are actually creating the Thumb versions of the spill + ; instructions. +; CHECK: t2STRDi8 +; CHECK: t2LDRDi8 + + store volatile i64 %val1, i64* %addr + store volatile i64 %val2, i64* %addr + store volatile i64 %val3, i64* %addr + store volatile i64 %val4, i64* %addr + store volatile i64 %val5, i64* %addr + store volatile i64 %val6, i64* %addr + store volatile i64 %val7, i64* %addr + ret void +} diff --git a/test/CodeGen/ARM/gpr-paired-spill.ll b/test/CodeGen/ARM/gpr-paired-spill.ll new file mode 100644 index 000000000000..ef3e5a54a2db --- /dev/null +++ b/test/CodeGen/ARM/gpr-paired-spill.ll @@ -0,0 +1,44 @@ +; RUN: llc -mtriple=armv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD +; RUN: llc -mtriple=armv4-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITHOUT-LDRD +; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-WITH-LDRD + +define void @foo(i64* %addr) { + %val1 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val2 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val3 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val4 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val5 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val6 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + %val7 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr) + + ; Key point is that enough 64-bit paired GPR values are live that + ; one of them has to be spilled. This used to cause an abort because + ; an LDMIA was created with both a FrameIndex and an offset, which + ; is not allowed. + +; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8] +; CHECK-WITH-LDRD: strd {{r[0-9]+}}, {{r[0-9]+}}, [sp] + +; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp, #8] +; CHECK-WITH-LDRD: ldrd {{r[0-9]+}}, {{r[0-9]+}}, [sp] + + ; We also want to ensure the register scavenger is working (i.e. an + ; offset from sp can be generated), so we need two spills. +; CHECK-WITHOUT-LDRD: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}} +; CHECK-WITHOUT-LDRD: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}} +; CHECK-WITHOUT-LDRD: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}} + + ; In principle LLVM may have to recalculate the offset. At the moment + ; it reuses the original though. +; CHECK-WITHOUT-LDRD: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}} +; CHECK-WITHOUT-LDRD: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}} + + store volatile i64 %val1, i64* %addr + store volatile i64 %val2, i64* %addr + store volatile i64 %val3, i64* %addr + store volatile i64 %val4, i64* %addr + store volatile i64 %val5, i64* %addr + store volatile i64 %val6, i64* %addr + store volatile i64 %val7, i64* %addr + ret void +} diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll index 5b4cf9d81606..9b0f3e54e88a 100644 --- a/test/CodeGen/ARM/lsr-unfolded-offset.ll +++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -26,8 +26,8 @@ outer.loop: ; preds = %for.inc69, %entry %0 = phi i32 [ %inc71, %for.inc69 ], [ 0, %entry ] %offset = getelementptr %struct.partition_entry* %part, i32 %0, i32 2 %len = getelementptr %struct.partition_entry* %part, i32 %0, i32 3 - %tmp5 = load i64* %offset, align 4, !tbaa !0 - %tmp15 = load i64* %len, align 4, !tbaa !0 + %tmp5 = load i64* %offset, align 4 + %tmp15 = load i64* %len, align 4 %add = add nsw i64 %tmp15, %tmp5 br label %inner.loop @@ -40,8 +40,8 @@ inner.loop: ; preds = %for.inc, %outer.loo if.end: ; preds = %inner.loop %len39 = getelementptr %struct.partition_entry* %part, i32 %1, i32 3 %offset28 = getelementptr %struct.partition_entry* %part, i32 %1, i32 2 - %tmp29 = load i64* %offset28, align 4, !tbaa !0 - %tmp40 = load i64* %len39, align 4, !tbaa !0 + %tmp29 = load i64* %offset28, align 4 + %tmp40 = load i64* %len39, align 4 %add41 = add nsw i64 %tmp40, %tmp29 %cmp44 = icmp sge i64 %tmp29, %tmp5 %cmp47 = icmp slt i64 %tmp29, %add @@ -74,7 +74,3 @@ for.end72: ; preds = %for.inc69, %entry %overlap.0.lcssa = phi i32 [ 0, %entry ], [ %overlap.4, %for.inc69 ] ret i32 %overlap.0.lcssa } - -!0 = metadata !{metadata !"long long", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll new file mode 100644 index 000000000000..4b15326008a4 --- /dev/null +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -0,0 +1,30 @@ +; REQUIRES: asserts +; RUN: llc < %s -march=thumb -mcpu=swift -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; +; Loop counter copies should be eliminated. +; There is also a MUL here, but we don't care where it is scheduled. +; CHECK: postinc +; CHECK: *** Final schedule for BB#2 *** +; CHECK: t2LDRs +; CHECK: t2ADDrr +; CHECK: t2CMPrr +; CHECK: COPY +define i32 @postinc(i32 %a, i32* nocapture %d, i32 %s) nounwind { +entry: + %cmp4 = icmp eq i32 %a, 0 + br i1 %cmp4, label %for.end, label %for.body + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i32 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %s.05 = phi i32 [ %mul, %for.body ], [ 0, %entry ] + %indvars.iv.next = add i32 %indvars.iv, %s + %arrayidx = getelementptr inbounds i32* %d, i32 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %mul = mul nsw i32 %0, %s.05 + %exitcond = icmp eq i32 %indvars.iv.next, %a + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + %s.0.lcssa = phi i32 [ 0, %entry ], [ %mul, %for.body ] + ret i32 %s.0.lcssa +} diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll new file mode 100644 index 000000000000..bf2770b15b01 --- /dev/null +++ b/test/CodeGen/ARM/neon_vabs.ll @@ -0,0 +1,91 @@ +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s + +define <4 x i32> @test1(<4 x i32> %a) nounwind { +; CHECK: test1: +; CHECK: vabs.s32 q + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> + %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg + ret <4 x i32> %abs +} + +define <4 x i32> @test2(<4 x i32> %a) nounwind { +; CHECK: test2: +; CHECK: vabs.s32 q + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sge <4 x i32> %a, zeroinitializer + %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg + ret <4 x i32> %abs +} + +define <8 x i16> @test3(<8 x i16> %a) nounwind { +; CHECK: test3: +; CHECK: vabs.s16 q + %tmp1neg = sub <8 x i16> zeroinitializer, %a + %b = icmp sgt <8 x i16> %a, zeroinitializer + %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg + ret <8 x i16> %abs +} + +define <16 x i8> @test4(<16 x i8> %a) nounwind { +; CHECK: test4: +; CHECK: vabs.s8 q + %tmp1neg = sub <16 x i8> zeroinitializer, %a + %b = icmp slt <16 x i8> %a, zeroinitializer + %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a + ret <16 x i8> %abs +} + +define <4 x i32> @test5(<4 x i32> %a) nounwind { +; CHECK: test5: +; CHECK: vabs.s32 q + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sle <4 x i32> %a, zeroinitializer + %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a + ret <4 x i32> %abs +} + +define <2 x i32> @test6(<2 x i32> %a) nounwind { +; CHECK: test6: +; CHECK: vabs.s32 d + %tmp1neg = sub <2 x i32> zeroinitializer, %a + %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1> + %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg + ret <2 x i32> %abs +} + +define <2 x i32> @test7(<2 x i32> %a) nounwind { +; CHECK: test7: +; CHECK: vabs.s32 d + %tmp1neg = sub <2 x i32> zeroinitializer, %a + %b = icmp sge <2 x i32> %a, zeroinitializer + %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg + ret <2 x i32> %abs +} + +define <4 x i16> @test8(<4 x i16> %a) nounwind { +; CHECK: test8: +; CHECK: vabs.s16 d + %tmp1neg = sub <4 x i16> zeroinitializer, %a + %b = icmp sgt <4 x i16> %a, zeroinitializer + %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg + ret <4 x i16> %abs +} + +define <8 x i8> @test9(<8 x i8> %a) nounwind { +; CHECK: test9: +; CHECK: vabs.s8 d + %tmp1neg = sub <8 x i8> zeroinitializer, %a + %b = icmp slt <8 x i8> %a, zeroinitializer + %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a + ret <8 x i8> %abs +} + +define <2 x i32> @test10(<2 x i32> %a) nounwind { +; CHECK: test10: +; CHECK: vabs.s32 d + %tmp1neg = sub <2 x i32> zeroinitializer, %a + %b = icmp sle <2 x i32> %a, zeroinitializer + %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a + ret <2 x i32> %abs +} diff --git a/test/CodeGen/ARM/nop_concat_vectors.ll b/test/CodeGen/ARM/nop_concat_vectors.ll new file mode 100644 index 000000000000..c81090095a99 --- /dev/null +++ b/test/CodeGen/ARM/nop_concat_vectors.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s + +;CHECK: _foo +;CHECK-NOT: vld1.32 +;CHECK-NOT: vst1.32 +;CHECK: bx +define void @foo(<16 x i8>* %J) { + %A = load <16 x i8>* %J + %T1 = shufflevector <16 x i8> %A, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> + %T2 = shufflevector <8 x i8> %T1, <8 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + store <16 x i8> %T2, <16 x i8>* %J + ret void +} diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll index f93ffe7b339a..94578d82fddc 100644 --- a/test/CodeGen/ARM/private.ll +++ b/test/CodeGen/ARM/private.ll @@ -1,10 +1,11 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llc < %s -mtriple=arm-linux-gnueabi > %t -; RUN: grep .Lfoo: %t -; RUN: egrep bl.*\.Lfoo %t -; RUN: grep .Lbaz: %t -; RUN: grep long.*\.Lbaz %t +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; CHECK: .Lfoo: +; CHECK: bar: +; CHECK: bl .Lfoo +; CHECK: .long .Lbaz +; CHECK: .Lbaz: define private void @foo() { ret void diff --git a/test/CodeGen/ARM/returned-ext.ll b/test/CodeGen/ARM/returned-ext.ll new file mode 100644 index 000000000000..670b12f249d4 --- /dev/null +++ b/test/CodeGen/ARM/returned-ext.ll @@ -0,0 +1,178 @@ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D + +declare i16 @identity16(i16 returned %x) +declare i32 @identity32(i32 returned %x) +declare zeroext i16 @retzext16(i16 returned %x) +declare i16 @paramzext16(i16 zeroext returned %x) +declare zeroext i16 @bothzext16(i16 zeroext returned %x) + +; The zeroext param attribute below is meant to have no effect +define i16 @test_identity(i16 zeroext %x) { +entry: +; CHECKELF: test_identity: +; CHECKELF: mov [[SAVEX:r[0-9]+]], r0 +; CHECKELF: bl identity16 +; CHECKELF: uxth r0, r0 +; CHECKELF: bl identity32 +; CHECKELF: mov r0, [[SAVEX]] +; CHECKT2D: test_identity: +; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 +; CHECKT2D: blx _identity16 +; CHECKT2D: uxth r0, r0 +; CHECKT2D: blx _identity32 +; CHECKT2D: mov r0, [[SAVEX]] + %call = tail call i16 @identity16(i16 %x) + %b = zext i16 %call to i32 + %call2 = tail call i32 @identity32(i32 %b) + ret i16 %x +} + +; FIXME: This ought not to require register saving but currently does because +; x is not considered equal to %call (see SelectionDAGBuilder.cpp) +define i16 @test_matched_ret(i16 %x) { +entry: +; CHECKELF: test_matched_ret: + +; This shouldn't be required +; CHECKELF: mov [[SAVEX:r[0-9]+]], r0 + +; CHECKELF: bl retzext16 +; CHECKELF-NOT: uxth r0, {{r[0-9]+}} +; CHECKELF: bl identity32 + +; This shouldn't be required +; CHECKELF: mov r0, [[SAVEX]] + +; CHECKT2D: test_matched_ret: + +; This shouldn't be required +; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 + +; CHECKT2D: blx _retzext16 +; CHECKT2D-NOT: uxth r0, {{r[0-9]+}} +; CHECKT2D: blx _identity32 + +; This shouldn't be required +; CHECKT2D: mov r0, [[SAVEX]] + + %call = tail call i16 @retzext16(i16 %x) + %b = zext i16 %call to i32 + %call2 = tail call i32 @identity32(i32 %b) + ret i16 %x +} + +define i16 @test_mismatched_ret(i16 %x) { +entry: +; CHECKELF: test_mismatched_ret: +; CHECKELF: mov [[SAVEX:r[0-9]+]], r0 +; CHECKELF: bl retzext16 +; CHECKELF: sxth r0, {{r[0-9]+}} +; CHECKELF: bl identity32 +; CHECKELF: mov r0, [[SAVEX]] +; CHECKT2D: test_mismatched_ret: +; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 +; CHECKT2D: blx _retzext16 +; CHECKT2D: sxth r0, {{r[0-9]+}} +; CHECKT2D: blx _identity32 +; CHECKT2D: mov r0, [[SAVEX]] + %call = tail call i16 @retzext16(i16 %x) + %b = sext i16 %call to i32 + %call2 = tail call i32 @identity32(i32 %b) + ret i16 %x +} + +define i16 @test_matched_paramext(i16 %x) { +entry: +; CHECKELF: test_matched_paramext: +; CHECKELF: uxth r0, r0 +; CHECKELF: bl paramzext16 +; CHECKELF: uxth r0, r0 +; CHECKELF: bl identity32 +; CHECKELF: b paramzext16 +; CHECKT2D: test_matched_paramext: +; CHECKT2D: uxth r0, r0 +; CHECKT2D: blx _paramzext16 +; CHECKT2D: uxth r0, r0 +; CHECKT2D: blx _identity32 +; CHECKT2D: b.w _paramzext16 + %call = tail call i16 @paramzext16(i16 %x) + %b = zext i16 %call to i32 + %call2 = tail call i32 @identity32(i32 %b) + %call3 = tail call i16 @paramzext16(i16 %call) + ret i16 %call3 +} + +; FIXME: This theoretically ought to optimize to exact same output as the +; version above, but doesn't currently (see SelectionDAGBuilder.cpp) +define i16 @test_matched_paramext2(i16 %x) { +entry: + +; Since there doesn't seem to be an unambiguous optimal selection and +; scheduling of uxth and mov instructions below in lieu of the 'returned' +; optimization, don't bother checking: just verify that the calls are made +; in the correct order as a basic sanity check + +; CHECKELF: test_matched_paramext2: +; CHECKELF: bl paramzext16 +; CHECKELF: bl identity32 +; CHECKELF: b paramzext16 +; CHECKT2D: test_matched_paramext2: +; CHECKT2D: blx _paramzext16 +; CHECKT2D: blx _identity32 +; CHECKT2D: b.w _paramzext16 + %call = tail call i16 @paramzext16(i16 %x) + +; Should make no difference if %x is used below rather than %call, but it does + %b = zext i16 %x to i32 + + %call2 = tail call i32 @identity32(i32 %b) + %call3 = tail call i16 @paramzext16(i16 %call) + ret i16 %call3 +} + +define i16 @test_matched_bothext(i16 %x) { +entry: +; CHECKELF: test_matched_bothext: +; CHECKELF: uxth r0, r0 +; CHECKELF: bl bothzext16 +; CHECKELF-NOT: uxth r0, r0 + +; FIXME: Tail call should be OK here +; CHECKELF: bl identity32 + +; CHECKT2D: test_matched_bothext: +; CHECKT2D: uxth r0, r0 +; CHECKT2D: blx _bothzext16 +; CHECKT2D-NOT: uxth r0, r0 + +; FIXME: Tail call should be OK here +; CHECKT2D: blx _identity32 + + %call = tail call i16 @bothzext16(i16 %x) + %b = zext i16 %x to i32 + %call2 = tail call i32 @identity32(i32 %b) + ret i16 %call +} + +define i16 @test_mismatched_bothext(i16 %x) { +entry: +; CHECKELF: test_mismatched_bothext: +; CHECKELF: mov [[SAVEX:r[0-9]+]], r0 +; CHECKELF: uxth r0, {{r[0-9]+}} +; CHECKELF: bl bothzext16 +; CHECKELF: sxth r0, [[SAVEX]] +; CHECKELF: bl identity32 +; CHECKELF: mov r0, [[SAVEX]] +; CHECKT2D: test_mismatched_bothext: +; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 +; CHECKT2D: uxth r0, {{r[0-9]+}} +; CHECKT2D: blx _bothzext16 +; CHECKT2D: sxth r0, [[SAVEX]] +; CHECKT2D: blx _identity32 +; CHECKT2D: mov r0, [[SAVEX]] + %call = tail call i16 @bothzext16(i16 %x) + %b = sext i16 %x to i32 + %call2 = tail call i32 @identity32(i32 %b) + ret i16 %x +} diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll index e015bf098ff8..eb4d0bab929e 100644 --- a/test/CodeGen/ARM/tail-dup.ll +++ b/test/CodeGen/ARM/tail-dup.ll @@ -11,19 +11,19 @@ define i32 @fn(i32* nocapture %opcodes) nounwind readonly ssp { entry: - %0 = load i32* %opcodes, align 4, !tbaa !0 + %0 = load i32* %opcodes, align 4 %arrayidx = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %0 br label %indirectgoto INCREMENT: ; preds = %indirectgoto %inc = add nsw i32 %result.0, 1 - %1 = load i32* %opcodes.addr.0, align 4, !tbaa !0 + %1 = load i32* %opcodes.addr.0, align 4 %arrayidx2 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %1 br label %indirectgoto DECREMENT: ; preds = %indirectgoto %dec = add nsw i32 %result.0, -1 - %2 = load i32* %opcodes.addr.0, align 4, !tbaa !0 + %2 = load i32* %opcodes.addr.0, align 4 %arrayidx4 = getelementptr inbounds [3 x i8*]* @fn.codetable, i32 0, i32 %2 br label %indirectgoto @@ -38,7 +38,3 @@ indirectgoto: ; preds = %DECREMENT, %INCREME RETURN: ; preds = %indirectgoto ret i32 %result.0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/this-return.ll b/test/CodeGen/ARM/this-return.ll new file mode 100644 index 000000000000..f06e4a4f8ddc --- /dev/null +++ b/test/CodeGen/ARM/this-return.ll @@ -0,0 +1,105 @@ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D + +%struct.A = type { i8 } +%struct.B = type { i32 } +%struct.C = type { %struct.B } +%struct.D = type { %struct.B } +%struct.E = type { %struct.B, %struct.B } + +declare %struct.A* @A_ctor_base(%struct.A* returned) +declare %struct.B* @B_ctor_base(%struct.B* returned, i32) +declare %struct.B* @B_ctor_complete(%struct.B* returned, i32) + +declare %struct.A* @A_ctor_base_nothisret(%struct.A*) +declare %struct.B* @B_ctor_base_nothisret(%struct.B*, i32) +declare %struct.B* @B_ctor_complete_nothisret(%struct.B*, i32) + +define %struct.C* @C_ctor_base(%struct.C* returned %this, i32 %x) { +entry: +; CHECKELF: C_ctor_base: +; CHECKELF-NOT: mov {{r[0-9]+}}, r0 +; CHECKELF: bl A_ctor_base +; CHECKELF-NOT: mov r0, {{r[0-9]+}} +; CHECKELF: b B_ctor_base +; CHECKT2D: C_ctor_base: +; CHECKT2D-NOT: mov {{r[0-9]+}}, r0 +; CHECKT2D: blx _A_ctor_base +; CHECKT2D-NOT: mov r0, {{r[0-9]+}} +; CHECKT2D: b.w _B_ctor_base + %0 = bitcast %struct.C* %this to %struct.A* + %call = tail call %struct.A* @A_ctor_base(%struct.A* %0) + %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %call2 = tail call %struct.B* @B_ctor_base(%struct.B* %1, i32 %x) + ret %struct.C* %this +} + +define %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) { +entry: +; CHECKELF: C_ctor_base_nothisret: +; CHECKELF: mov [[SAVETHIS:r[0-9]+]], r0 +; CHECKELF: bl A_ctor_base_nothisret +; CHECKELF: mov r0, [[SAVETHIS]] +; CHECKELF-NOT: b B_ctor_base_nothisret +; CHECKT2D: C_ctor_base_nothisret: +; CHECKT2D: mov [[SAVETHIS:r[0-9]+]], r0 +; CHECKT2D: blx _A_ctor_base_nothisret +; CHECKT2D: mov r0, [[SAVETHIS]] +; CHECKT2D-NOT: b.w _B_ctor_base_nothisret + %0 = bitcast %struct.C* %this to %struct.A* + %call = tail call %struct.A* @A_ctor_base_nothisret(%struct.A* %0) + %1 = getelementptr inbounds %struct.C* %this, i32 0, i32 0 + %call2 = tail call %struct.B* @B_ctor_base_nothisret(%struct.B* %1, i32 %x) + ret %struct.C* %this +} + +define %struct.C* @C_ctor_complete(%struct.C* %this, i32 %x) { +entry: +; CHECKELF: C_ctor_complete: +; CHECKELF: b C_ctor_base +; CHECKT2D: C_ctor_complete: +; CHECKT2D: b.w _C_ctor_base + %call = tail call %struct.C* @C_ctor_base(%struct.C* %this, i32 %x) + ret %struct.C* %this +} + +define %struct.C* @C_ctor_complete_nothisret(%struct.C* %this, i32 %x) { +entry: +; CHECKELF: C_ctor_complete_nothisret: +; CHECKELF-NOT: b C_ctor_base_nothisret +; CHECKT2D: C_ctor_complete_nothisret: +; CHECKT2D-NOT: b.w _C_ctor_base_nothisret + %call = tail call %struct.C* @C_ctor_base_nothisret(%struct.C* %this, i32 %x) + ret %struct.C* %this +} + +define %struct.D* @D_ctor_base(%struct.D* %this, i32 %x) { +entry: +; CHECKELF: D_ctor_base: +; CHECKELF-NOT: mov {{r[0-9]+}}, r0 +; CHECKELF: bl B_ctor_complete +; CHECKELF-NOT: mov r0, {{r[0-9]+}} +; CHECKELF: b B_ctor_complete +; CHECKT2D: D_ctor_base: +; CHECKT2D-NOT: mov {{r[0-9]+}}, r0 +; CHECKT2D: blx _B_ctor_complete +; CHECKT2D-NOT: mov r0, {{r[0-9]+}} +; CHECKT2D: b.w _B_ctor_complete + %b = getelementptr inbounds %struct.D* %this, i32 0, i32 0 + %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) + %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) + ret %struct.D* %this +} + +define %struct.E* @E_ctor_base(%struct.E* %this, i32 %x) { +entry: +; CHECKELF: E_ctor_base: +; CHECKELF-NOT: b B_ctor_complete +; CHECKT2D: E_ctor_base: +; CHECKT2D-NOT: b.w _B_ctor_complete + %b = getelementptr inbounds %struct.E* %this, i32 0, i32 0 + %call = tail call %struct.B* @B_ctor_complete(%struct.B* %b, i32 %x) + %b2 = getelementptr inbounds %struct.E* %this, i32 0, i32 1 + %call2 = tail call %struct.B* @B_ctor_complete(%struct.B* %b2, i32 %x) + ret %struct.E* %this +} diff --git a/test/CodeGen/ARM/v1-constant-fold.ll b/test/CodeGen/ARM/v1-constant-fold.ll new file mode 100644 index 000000000000..b86d5db29c4b --- /dev/null +++ b/test/CodeGen/ARM/v1-constant-fold.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+v7,+vfp3,-neon | FileCheck %s + +; PR15611. Check that we don't crash when constant folding v1i32 types. + +; CHECK: foo: +define void @foo(i32 %arg) { +bb: + %tmp = insertelement <4 x i32> undef, i32 %arg, i32 0 + %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 1 + %tmp2 = insertelement <4 x i32> %tmp1, i32 0, i32 2 + %tmp3 = insertelement <4 x i32> %tmp2, i32 0, i32 3 + %tmp4 = add <4 x i32> %tmp3, <i32 -1, i32 -1, i32 -1, i32 -1> +; CHECK: bl bar + tail call void @bar(<4 x i32> %tmp4) + ret void +} + +declare void @bar(<4 x i32>) diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll new file mode 100644 index 000000000000..0d45c40b8814 --- /dev/null +++ b/test/CodeGen/ARM/vcvt-cost.ll @@ -0,0 +1,153 @@ +; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8 +; instructions as expensive. If lowering is improved the cost model needs to +; change. +; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST +%T0_5 = type <8 x i8> +%T1_5 = type <8 x i32> +; CHECK: func_cvt5: +define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { +; CHECK: vmovl.s8 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 + %v0 = load %T0_5* %loadaddr +; COST: func_cvt5 +; COST: cost of 3 {{.*}} sext + %r = sext %T0_5 %v0 to %T1_5 + store %T1_5 %r, %T1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TA0_5 = type <8 x i8> +%TA1_5 = type <8 x i32> +; CHECK: func_cvt1: +define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { +; CHECK: vmovl.u8 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 + %v0 = load %TA0_5* %loadaddr +; COST: func_cvt1 +; COST: cost of 3 {{.*}} zext + %r = zext %TA0_5 %v0 to %TA1_5 + store %TA1_5 %r, %TA1_5* %storeaddr + ret void +} + +%T0_51 = type <8 x i32> +%T1_51 = type <8 x i8> +; CHECK: func_cvt51: +define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { +; CHECK: vmovn.i32 +; CHECK: vmovn.i32 +; CHECK: vmovn.i16 + %v0 = load %T0_51* %loadaddr +; COST: func_cvt51 +; COST: cost of 3 {{.*}} trunc + %r = trunc %T0_51 %v0 to %T1_51 + store %T1_51 %r, %T1_51* %storeaddr + ret void +} + +%TT0_5 = type <16 x i8> +%TT1_5 = type <16 x i32> +; CHECK: func_cvt52: +define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 +; CHECK: vmovl.s16 + %v0 = load %TT0_5* %loadaddr +; COST: func_cvt52 +; COST: cost of 6 {{.*}} sext + %r = sext %TT0_5 %v0 to %TT1_5 + store %TT1_5 %r, %TT1_5* %storeaddr + ret void +} +;; We currently estimate the cost of this instruction as expensive. If lowering +;; is improved the cost needs to change. +%TTA0_5 = type <16 x i8> +%TTA1_5 = type <16 x i32> +; CHECK: func_cvt12: +define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 +; CHECK: vmovl.u16 + %v0 = load %TTA0_5* %loadaddr +; COST: func_cvt12 +; COST: cost of 6 {{.*}} zext + %r = zext %TTA0_5 %v0 to %TTA1_5 + store %TTA1_5 %r, %TTA1_5* %storeaddr + ret void +} + +%TT0_51 = type <16 x i32> +%TT1_51 = type <16 x i8> +; CHECK: func_cvt512: +define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { +; CHECK: vmovn.i32 +; CHECK: vmovn.i32 +; CHECK: vmovn.i32 +; CHECK: vmovn.i32 +; CHECK: vmovn.i16 +; CHECK: vmovn.i16 + %v0 = load %TT0_51* %loadaddr +; COST: func_cvt512 +; COST: cost of 6 {{.*}} trunc + %r = trunc %TT0_51 %v0 to %TT1_51 + store %TT1_51 %r, %TT1_51* %storeaddr + ret void +} + +; CHECK: sext_v4i16_v4i64: +define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 + %v0 = load <4 x i16>* %loadaddr +; COST: sext_v4i16_v4i64 +; COST: cost of 3 {{.*}} sext + %r = sext <4 x i16> %v0 to <4 x i64> + store <4 x i64> %r, <4 x i64>* %storeaddr + ret void +} + +; CHECK: zext_v4i16_v4i64: +define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 + %v0 = load <4 x i16>* %loadaddr +; COST: zext_v4i16_v4i64 +; COST: cost of 3 {{.*}} zext + %r = zext <4 x i16> %v0 to <4 x i64> + store <4 x i64> %r, <4 x i64>* %storeaddr + ret void +} + +; CHECK: sext_v8i16_v8i64: +define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 +; CHECK: vmovl.s32 + %v0 = load <8 x i16>* %loadaddr +; COST: sext_v8i16_v8i64 +; COST: cost of 6 {{.*}} sext + %r = sext <8 x i16> %v0 to <8 x i64> + store <8 x i64> %r, <8 x i64>* %storeaddr + ret void +} + +; CHECK: zext_v8i16_v8i64: +define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 +; CHECK: vmovl.u32 + %v0 = load <8 x i16>* %loadaddr +; COST: zext_v8i16_v8i64 +; COST: cost of 6 {{.*}} zext + %r = zext <8 x i16> %v0 to <8 x i64> + store <8 x i64> %r, <8 x i64>* %storeaddr + ret void +} + diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index e67b4788a37d..c078f493094b 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -156,175 +156,3 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone - -; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8 -; instructions as expensive. If lowering is improved the cost model needs to -; change. -; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST -%T0_5 = type <8 x i8> -%T1_5 = type <8 x i32> -; CHECK: func_cvt5: -define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { -; CHECK: vmovl.s8 -; CHECK: vmovl.s16 -; CHECK: vmovl.s16 - %v0 = load %T0_5* %loadaddr -; COST: func_cvt5 -; COST: cost of 3 {{.*}} sext - %r = sext %T0_5 %v0 to %T1_5 - store %T1_5 %r, %T1_5* %storeaddr - ret void -} -;; We currently estimate the cost of this instruction as expensive. If lowering -;; is improved the cost needs to change. -%TA0_5 = type <8 x i8> -%TA1_5 = type <8 x i32> -; CHECK: func_cvt1: -define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { -; CHECK: vmovl.u8 -; CHECK: vmovl.u16 -; CHECK: vmovl.u16 - %v0 = load %TA0_5* %loadaddr -; COST: func_cvt1 -; COST: cost of 3 {{.*}} zext - %r = zext %TA0_5 %v0 to %TA1_5 - store %TA1_5 %r, %TA1_5* %storeaddr - ret void -} -;; We currently estimate the cost of this instruction as expensive. If lowering -;; is improved the cost needs to change. -%T0_51 = type <8 x i32> -%T1_51 = type <8 x i8> -; CHECK: func_cvt51: -define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb - %v0 = load %T0_51* %loadaddr -; COST: func_cvt51 -; COST: cost of 19 {{.*}} trunc - %r = trunc %T0_51 %v0 to %T1_51 - store %T1_51 %r, %T1_51* %storeaddr - ret void -} -;; We currently estimate the cost of this instruction as expensive. If lowering -;; is improved the cost needs to change. -%TT0_5 = type <16 x i8> -%TT1_5 = type <16 x i32> -; CHECK: func_cvt52: -define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { -; CHECK: vmovl.s16 -; CHECK: vmovl.s16 -; CHECK: vmovl.s16 -; CHECK: vmovl.s16 - %v0 = load %TT0_5* %loadaddr -; COST: func_cvt52 -; COST: cost of 6 {{.*}} sext - %r = sext %TT0_5 %v0 to %TT1_5 - store %TT1_5 %r, %TT1_5* %storeaddr - ret void -} -;; We currently estimate the cost of this instruction as expensive. If lowering -;; is improved the cost needs to change. -%TTA0_5 = type <16 x i8> -%TTA1_5 = type <16 x i32> -; CHECK: func_cvt12: -define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { -; CHECK: vmovl.u16 -; CHECK: vmovl.u16 -; CHECK: vmovl.u16 -; CHECK: vmovl.u16 - %v0 = load %TTA0_5* %loadaddr -; COST: func_cvt12 -; COST: cost of 6 {{.*}} zext - %r = zext %TTA0_5 %v0 to %TTA1_5 - store %TTA1_5 %r, %TTA1_5* %storeaddr - ret void -} -;; We currently estimate the cost of this instruction as expensive. If lowering -;; is improved the cost needs to change. -%TT0_51 = type <16 x i32> -%TT1_51 = type <16 x i8> -; CHECK: func_cvt512: -define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb -; CHECK: strb - %v0 = load %TT0_51* %loadaddr -; COST: func_cvt512 -; COST: cost of 38 {{.*}} trunc - %r = trunc %TT0_51 %v0 to %TT1_51 - store %TT1_51 %r, %TT1_51* %storeaddr - ret void -} - -; CHECK: sext_v4i16_v4i64: -define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { -; CHECK: vmovl.s32 -; CHECK: vmovl.s32 - %v0 = load <4 x i16>* %loadaddr -; COST: sext_v4i16_v4i64 -; COST: cost of 3 {{.*}} sext - %r = sext <4 x i16> %v0 to <4 x i64> - store <4 x i64> %r, <4 x i64>* %storeaddr - ret void -} - -; CHECK: zext_v4i16_v4i64: -define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { -; CHECK: vmovl.u32 -; CHECK: vmovl.u32 - %v0 = load <4 x i16>* %loadaddr -; COST: zext_v4i16_v4i64 -; COST: cost of 3 {{.*}} zext - %r = zext <4 x i16> %v0 to <4 x i64> - store <4 x i64> %r, <4 x i64>* %storeaddr - ret void -} - -; CHECK: sext_v8i16_v8i64: -define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { -; CHECK: vmovl.s32 -; CHECK: vmovl.s32 -; CHECK: vmovl.s32 -; CHECK: vmovl.s32 - %v0 = load <8 x i16>* %loadaddr -; COST: sext_v8i16_v8i64 -; COST: cost of 6 {{.*}} sext - %r = sext <8 x i16> %v0 to <8 x i64> - store <8 x i64> %r, <8 x i64>* %storeaddr - ret void -} - -; CHECK: zext_v8i16_v8i64: -define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { -; CHECK: vmovl.u32 -; CHECK: vmovl.u32 -; CHECK: vmovl.u32 -; CHECK: vmovl.u32 - %v0 = load <8 x i16>* %loadaddr -; COST: zext_v8i16_v8i64 -; COST: cost of 6 {{.*}} zext - %r = zext <8 x i16> %v0 to <8 x i64> - store <8 x i64> %r, <8 x i64>* %storeaddr - ret void -} - diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 3009e50c532b..07ba230757be 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -7,7 +7,7 @@ ; CHECK-NOT: vmul define void @t0() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -23,7 +23,7 @@ declare void @foo_int32x2_t(<2 x i32>) ; CHECK-NOT: vmul define void @t1() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00> @@ -39,7 +39,7 @@ declare void @foo_uint32x2_t(<2 x i32>) ; CHECK: vmul define void @t2() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000> @@ -53,7 +53,7 @@ entry: ; CHECK: vmul define void @t3() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000> @@ -67,7 +67,7 @@ entry: ; CHECK-NOT: vmul define void @t4() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1 %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000> @@ -81,7 +81,7 @@ entry: ; CHECK-NOT: vmul define void @t5() nounwind { entry: - %tmp = load float* @in, align 4, !tbaa !0 + %tmp = load float* @in, align 4 %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2 @@ -93,7 +93,3 @@ entry: } declare void @foo_int32x4_t(<4 x i32>) - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 7fddbed1ed51..e6f1338b8539 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -11,7 +11,7 @@ declare void @foo_int32x4_t(<4 x i32>) ; CHECK-NOT: {{vdiv|vmul}} define void @t1() nounwind { entry: - %tmp = load i32* @iin, align 4, !tbaa !3 + %tmp = load i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -27,7 +27,7 @@ declare void @foo_float32x2_t(<2 x float>) ; CHECK-NOT: {{vdiv|vmul}} define void @t2() nounwind { entry: - %tmp = load i32* @uin, align 4, !tbaa !3 + %tmp = load i32* @uin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float> @@ -41,7 +41,7 @@ entry: ; CHECK: {{vdiv|vmul}} define void @t3() nounwind { entry: - %tmp = load i32* @iin, align 4, !tbaa !3 + %tmp = load i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -55,7 +55,7 @@ entry: ; CHECK: {{vdiv|vmul}} define void @t4() nounwind { entry: - %tmp = load i32* @iin, align 4, !tbaa !3 + %tmp = load i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -69,7 +69,7 @@ entry: ; CHECK-NOT: {{vdiv|vmul}} define void @t5() nounwind { entry: - %tmp = load i32* @iin, align 4, !tbaa !3 + %tmp = load i32* @iin, align 4 %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float> @@ -83,7 +83,7 @@ entry: ; CHECK-NOT: {{vdiv|vmul}} define void @t6() nounwind { entry: - %tmp = load i32* @iin, align 4, !tbaa !3 + %tmp = load i32* @iin, align 4 %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0 %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1 %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2 @@ -95,8 +95,3 @@ entry: } declare void @foo_float32x4_t(<4 x float>) - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"int", metadata !1} diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 74628f0c5ce6..eb5ad8f0c3d0 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -599,3 +599,27 @@ for.end179: ; preds = %for.cond.loopexit, declare <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i16> @llvm.arm.neon.vqsubu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone declare <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16>) nounwind readnone + +; vmull lowering would create a zext(v4i8 load()) instead of a zextload(v4i8), +; creating an illegal type during legalization and causing an assert. +; PR15970 +define void @no_illegal_types_vmull_sext(<4 x i32> %a) { +entry: + %wide.load283.i = load <4 x i8>* undef, align 1 + %0 = sext <4 x i8> %wide.load283.i to <4 x i32> + %1 = sub nsw <4 x i32> %0, %a + %2 = mul nsw <4 x i32> %1, %1 + %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2 + store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4 + ret void +} +define void @no_illegal_types_vmull_zext(<4 x i32> %a) { +entry: + %wide.load283.i = load <4 x i8>* undef, align 1 + %0 = zext <4 x i8> %wide.load283.i to <4 x i32> + %1 = sub nsw <4 x i32> %0, %a + %2 = mul nsw <4 x i32> %1, %1 + %predphi290.v.i = select <4 x i1> undef, <4 x i32> undef, <4 x i32> %2 + store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4 + ret void +} diff --git a/test/CodeGen/Generic/annotate.ll b/test/CodeGen/Generic/annotate.ll new file mode 100644 index 000000000000..c617eb09258c --- /dev/null +++ b/test/CodeGen/Generic/annotate.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s + +; PR15253 + +@.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata" +@.str1 = private unnamed_addr constant [4 x i8] c"t.c\00", section "llvm.metadata" + + +define i32 @foo(i32 %a) { +entry: + %0 = call i32 @llvm.annotation.i32(i32 %a, i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), i32 2) + ret i32 %0 +} + +declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1 diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll index d889389b7c53..d3fc20467aa8 100644 --- a/test/CodeGen/Generic/crash.ll +++ b/test/CodeGen/Generic/crash.ll @@ -51,7 +51,7 @@ for.body.i: ; preds = %for.body.i, %entry func_74.exit.for.cond29.thread_crit_edge: ; preds = %for.body.i %f13576.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1 - store i8 0, i8* %f13576.pre, align 4, !tbaa !0 + store i8 0, i8* %f13576.pre, align 4 br label %lbl_468 lbl_468: ; preds = %lbl_468, %func_74.exit.for.cond29.thread_crit_edge @@ -63,6 +63,3 @@ lbl_468: ; preds = %lbl_468, %func_74.e for.end74: ; preds = %lbl_468 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Generic/ptr-annotate.ll b/test/CodeGen/Generic/ptr-annotate.ll new file mode 100644 index 000000000000..ac5bd5533e9e --- /dev/null +++ b/test/CodeGen/Generic/ptr-annotate.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s + +; PR15253 + +%struct.mystruct = type { i32 } + +@.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata" +@.str1 = private unnamed_addr constant [4 x i8] c"t.c\00", section "llvm.metadata" + +define void @foo() { +entry: + %m = alloca i8, align 4 + %0 = call i8* @llvm.ptr.annotation.p0i8(i8* %m, i8* getelementptr inbounds ([4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8]* @.str1, i32 0, i32 0), i32 2) + store i8 1, i8* %0, align 4 + ret void +} + +declare i8* @llvm.ptr.annotation.p0i8(i8*, i8*, i8*, i32) #1 diff --git a/test/CodeGen/Hexagon/absimm.ll b/test/CodeGen/Hexagon/absimm.ll new file mode 100644 index 000000000000..b8f5edc26470 --- /dev/null +++ b/test/CodeGen/Hexagon/absimm.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate absolute addressing mode instructions +; with immediate value. + +define i32 @f1(i32 %i) nounwind { +; CHECK: memw(##786432){{ *}}={{ *}}r{{[0-9]+}} +entry: + store volatile i32 %i, i32* inttoptr (i32 786432 to i32*), align 262144 + ret i32 %i +} + +define i32* @f2(i32* nocapture %i) nounwind { +entry: +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(##786432) + %0 = load volatile i32* inttoptr (i32 786432 to i32*), align 262144 + %1 = inttoptr i32 %0 to i32* + ret i32* %1 + } diff --git a/test/CodeGen/Hexagon/always-ext.ll b/test/CodeGen/Hexagon/always-ext.ll new file mode 100644 index 000000000000..9c8d708ba877 --- /dev/null +++ b/test/CodeGen/Hexagon/always-ext.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s + +; Check that we don't generate an invalid packet with too many instructions +; due to a store that has a must-extend operand. + +; CHECK: CuSuiteAdd.exit.us +; CHECK: { +; CHECK-NOT: call abort +; CHECK: memw(##0) +; CHECK: memw(r{{[0-9+]}}<<#2+##4) +; CHECK: } + +%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111 = type { i8*, void (%struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*)*, i32, i32, i8*, [23 x i32]* } +%struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112 = type { i32, [1024 x %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111*], i32 } + +@__func__.CuSuiteAdd = external unnamed_addr constant [11 x i8], align 8 +@.str24 = external unnamed_addr constant [140 x i8], align 8 + +declare void @_Assert() + +define void @CuSuiteAddSuite() nounwind { +entry: + br i1 undef, label %for.body.us, label %for.end + +for.body.us: ; preds = %entry + %0 = load %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** null, align 4 + %1 = load i32* undef, align 4 + %cmp.i.us = icmp slt i32 %1, 1024 + br i1 %cmp.i.us, label %CuSuiteAdd.exit.us, label %cond.false6.i.us + +cond.false6.i.us: ; preds = %for.body.us + tail call void @_Assert() nounwind + unreachable + +CuSuiteAdd.exit.us: ; preds = %for.body.us + %arrayidx.i.us = getelementptr inbounds %struct.CuSuite.2.29.32.38.41.44.53.56.68.86.112* null, i32 0, i32 1, i32 %1 + store %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111* %0, %struct.CuTest.1.28.31.37.40.43.52.55.67.85.111** %arrayidx.i.us, align 4 + call void @llvm.trap() + unreachable + +for.end: ; preds = %entry + ret void +} + +declare void @llvm.trap() noreturn nounwind diff --git a/test/CodeGen/Hexagon/cmp_pred2.ll b/test/CodeGen/Hexagon/cmp_pred2.ll new file mode 100644 index 000000000000..a20b9f09b6e0 --- /dev/null +++ b/test/CodeGen/Hexagon/cmp_pred2.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s +; Make sure that the assembler mapped compare instructions are correctly generated. + +@c = common global i32 0, align 4 + +define i32 @test1(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ge +; CHECK: cmp.gt +entry: + %cmp = icmp slt i32 %a, 100 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test2(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.lt +; CHECK: cmp.gt +entry: + %cmp = icmp sge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add nsw i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test4(i32 %a, i32 %b) nounwind { +; CHECK-NOT: cmp.ltu +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, %b + br i1 %cmp, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} + +define i32 @test5(i32 %a, i32 %b) nounwind { +; CHECK: cmp.gtu +entry: + %cmp = icmp uge i32 %a, 29999 + br i1 %cmp, label %if.then, label %entry.if.end_crit_edge + +entry.if.end_crit_edge: + %.pre = load i32* @c, align 4 + br label %if.end + +if.then: + %sub = add i32 %a, -10 + store i32 %sub, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %sub, %if.then ] + ret i32 %0 +} diff --git a/test/CodeGen/Hexagon/cmpb_pred.ll b/test/CodeGen/Hexagon/cmpb_pred.ll index 1e6144701fee..0960da1fa060 100644 --- a/test/CodeGen/Hexagon/cmpb_pred.ll +++ b/test/CodeGen/Hexagon/cmpb_pred.ll @@ -16,7 +16,7 @@ entry: define i32 @Func_3b(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1, !tbaa !0 + %1 = load i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp ne i8 %1, %2 %selv = zext i1 %cmp to i32 @@ -35,7 +35,7 @@ entry: define i32 @Func_3d(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1, !tbaa !0 + %1 = load i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp eq i8 %1, %2 %selv = zext i1 %cmp to i32 @@ -45,7 +45,7 @@ entry: define i32 @Func_3e(i32) nounwind readonly { entry: ; CHECK-NOT: mux - %1 = load i8* @Enum_global, align 1, !tbaa !0 + %1 = load i8* @Enum_global, align 1 %2 = trunc i32 %0 to i8 %cmp = icmp eq i8 %1, %2 %selv = zext i1 %cmp to i32 @@ -87,6 +87,3 @@ entry: %selv = zext i1 %cmp to i32 ret i32 %selv } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/combine_ir.ll b/test/CodeGen/Hexagon/combine_ir.ll index 921ce9928e6d..8b99ef715546 100644 --- a/test/CodeGen/Hexagon/combine_ir.ll +++ b/test/CodeGen/Hexagon/combine_ir.ll @@ -6,12 +6,7 @@ define void @word(i32* nocapture %a) nounwind { entry: %0 = load i32* %a, align 4, !tbaa !0 %1 = zext i32 %0 to i64 - %add.ptr = getelementptr inbounds i32* %a, i32 1 - %2 = load i32* %add.ptr, align 4, !tbaa !0 - %3 = zext i32 %2 to i64 - %4 = shl nuw i64 %3, 32 - %ins = or i64 %4, %1 - tail call void @bar(i64 %ins) nounwind + tail call void @bar(i64 %1) nounwind ret void } diff --git a/test/CodeGen/Hexagon/hwloop-const.ll b/test/CodeGen/Hexagon/hwloop-const.ll index a621c58c63ed..8204ddea3490 100644 --- a/test/CodeGen/Hexagon/hwloop-const.ll +++ b/test/CodeGen/Hexagon/hwloop-const.ll @@ -15,9 +15,9 @@ entry: for.body: ; preds = %for.body, %entry %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %arrayidx = getelementptr inbounds [25000 x i32]* @b, i32 0, i32 %i.02 - store i32 %i.02, i32* %arrayidx, align 4, !tbaa !0 + store i32 %i.02, i32* %arrayidx, align 4 %arrayidx1 = getelementptr inbounds [25000 x i32]* @a, i32 0, i32 %i.02 - store i32 %i.02, i32* %arrayidx1, align 4, !tbaa !0 + store i32 %i.02, i32* %arrayidx1, align 4 %inc = add nsw i32 %i.02, 1 %exitcond = icmp eq i32 %inc, 25000 br i1 %exitcond, label %for.end, label %for.body @@ -25,7 +25,3 @@ for.body: ; preds = %for.body, %entry for.end: ; preds = %for.body ret i32 0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll index c2e8153b7dff..17fe7b982d8f 100644 --- a/test/CodeGen/Hexagon/hwloop-dbg.ll +++ b/test/CodeGen/Hexagon/hwloop-dbg.ll @@ -19,8 +19,8 @@ for.body: ; preds = %for.body, %entry %b.addr.01 = phi i32* [ %b, %entry ], [ %incdec.ptr, %for.body ] %incdec.ptr = getelementptr inbounds i32* %b.addr.01, i32 1, !dbg !21 tail call void @llvm.dbg.value(metadata !{i32* %incdec.ptr}, i64 0, metadata !14), !dbg !21 - %0 = load i32* %b.addr.01, align 4, !dbg !21, !tbaa !23 - store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21, !tbaa !23 + %0 = load i32* %b.addr.01, align 4, !dbg !21 + store i32 %0, i32* %arrayidx.phi, align 4, !dbg !21 %inc = add nsw i32 %i.02, 1, !dbg !26 tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !15), !dbg !26 %exitcond = icmp eq i32 %inc, 10, !dbg !19 @@ -57,8 +57,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !20 = metadata !{i32 786443, metadata !16, i32 3, i32 3, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] !21 = metadata !{i32 4, i32 5, metadata !22, null} !22 = metadata !{i32 786443, metadata !20, i32 3, i32 28, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/usr2/kparzysz/s.hex/t/hwloop-dbg.c] -!23 = metadata !{metadata !"int", metadata !24} -!24 = metadata !{metadata !"omnipotent char", metadata !25} -!25 = metadata !{metadata !"Simple C/C++ TBAA"} !26 = metadata !{i32 3, i32 23, metadata !20, null} !27 = metadata !{i32 6, i32 1, metadata !16, null} diff --git a/test/CodeGen/Hexagon/memops2.ll b/test/CodeGen/Hexagon/memops2.ll index b1b25445c029..d6d1a50bcefa 100644 --- a/test/CodeGen/Hexagon/memops2.ll +++ b/test/CodeGen/Hexagon/memops2.ll @@ -6,11 +6,11 @@ define void @f(i16* nocapture %p) nounwind { entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 %add.ptr = getelementptr inbounds i16* %p, i32 10 - %0 = load i16* %add.ptr, align 2, !tbaa !0 + %0 = load i16* %add.ptr, align 2 %conv2 = zext i16 %0 to i32 %sub = add nsw i32 %conv2, 65535 %conv1 = trunc i32 %sub to i16 - store i16 %conv1, i16* %add.ptr, align 2, !tbaa !0 + store i16 %conv1, i16* %add.ptr, align 2 ret void } @@ -19,14 +19,10 @@ entry: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}#1 %add.ptr.sum = add i32 %i, 10 %add.ptr1 = getelementptr inbounds i16* %p, i32 %add.ptr.sum - %0 = load i16* %add.ptr1, align 2, !tbaa !0 + %0 = load i16* %add.ptr1, align 2 %conv3 = zext i16 %0 to i32 %sub = add nsw i32 %conv3, 65535 %conv2 = trunc i32 %sub to i16 - store i16 %conv2, i16* %add.ptr1, align 2, !tbaa !0 + store i16 %conv2, i16* %add.ptr1, align 2 ret void } - -!0 = metadata !{metadata !"short", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/memops3.ll b/test/CodeGen/Hexagon/memops3.ll index 5b8bd6c87bfb..d9e4e8f53709 100644 --- a/test/CodeGen/Hexagon/memops3.ll +++ b/test/CodeGen/Hexagon/memops3.ll @@ -6,11 +6,11 @@ define void @f(i8* nocapture %p) nounwind { entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 %add.ptr = getelementptr inbounds i8* %p, i32 10 - %0 = load i8* %add.ptr, align 1, !tbaa !0 + %0 = load i8* %add.ptr, align 1 %conv = zext i8 %0 to i32 %sub = add nsw i32 %conv, 255 %conv1 = trunc i32 %sub to i8 - store i8 %conv1, i8* %add.ptr, align 1, !tbaa !0 + store i8 %conv1, i8* %add.ptr, align 1 ret void } @@ -19,13 +19,10 @@ entry: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}#1 %add.ptr.sum = add i32 %i, 10 %add.ptr1 = getelementptr inbounds i8* %p, i32 %add.ptr.sum - %0 = load i8* %add.ptr1, align 1, !tbaa !0 + %0 = load i8* %add.ptr1, align 1 %conv = zext i8 %0 to i32 %sub = add nsw i32 %conv, 255 %conv2 = trunc i32 %sub to i8 - store i8 %conv2, i8* %add.ptr1, align 1, !tbaa !0 + store i8 %conv2, i8* %add.ptr1, align 1 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/remove_lsr.ll b/test/CodeGen/Hexagon/remove_lsr.ll index 79b5f4ae7c43..3128dbb8b21b 100644 --- a/test/CodeGen/Hexagon/remove_lsr.ll +++ b/test/CodeGen/Hexagon/remove_lsr.ll @@ -46,17 +46,17 @@ for.body: ; preds = %for.body, %entry %1 = trunc i64 %val.021 to i32 %2 = trunc i64 %0 to i32 %3 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv3, i32 %1, i32 %2) - store i32 %3, i32* %lsr.iv3335, align 4, !tbaa !0 + store i32 %3, i32* %lsr.iv3335, align 4 %conv8 = sext i8 %predicate_1.023 to i32 %4 = lshr i64 %val.021, 32 %5 = trunc i64 %4 to i32 %6 = lshr i64 %0, 32 %7 = trunc i64 %6 to i32 %8 = tail call i32 @llvm.hexagon.C2.mux(i32 %conv8, i32 %5, i32 %7) - store i32 %8, i32* %lsr.iv2931, align 4, !tbaa !0 + store i32 %8, i32* %lsr.iv2931, align 4 %srcval = load i64* %lsr.iv27, align 8 - %9 = load i8* %lsr.iv40, align 1, !tbaa !1 - %10 = load i8* %lsr.iv37, align 1, !tbaa !1 + %9 = load i8* %lsr.iv40, align 1 + %10 = load i8* %lsr.iv37, align 1 %lftr.wideiv = trunc i32 %lsr.iv42 to i8 %exitcond = icmp eq i8 %lftr.wideiv, 32 %scevgep26 = getelementptr %union.vect64* %lsr.iv, i32 1 @@ -74,7 +74,3 @@ for.end: ; preds = %for.body declare i64 @llvm.hexagon.A2.vsubhs(i64, i64) nounwind readnone declare i32 @llvm.hexagon.C2.mux(i32, i32, i32) nounwind readnone - -!0 = metadata !{metadata !"long", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Hexagon/union-1.ll b/test/CodeGen/Hexagon/union-1.ll new file mode 100644 index 000000000000..7c6da744ec51 --- /dev/null +++ b/test/CodeGen/Hexagon/union-1.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; CHECK: word +; CHECK-NOT: combine(#0 +; CHECK: jump bar + +define void @word(i32* nocapture %a) nounwind { +entry: + %0 = load i32* %a, align 4, !tbaa !0 + %1 = zext i32 %0 to i64 + %add.ptr = getelementptr inbounds i32* %a, i32 1 + %2 = load i32* %add.ptr, align 4, !tbaa !0 + %3 = zext i32 %2 to i64 + %4 = shl nuw i64 %3, 32 + %ins = or i64 %4, %1 + tail call void @bar(i64 %ins) nounwind + ret void +} + +declare void @bar(i64) + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index d79ea9193d28..fc7ef862a328 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -59,23 +59,23 @@ if.end: ; preds = %if.else, %if.then ; CHECK: lw $25, %call16(printf) %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ] - %tmp7 = load i32* %0, align 4, !tbaa !0 + %tmp7 = load i32* %0, align 4 %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4 %3 = bitcast i8* %arrayidx9 to i32* - %tmp10 = load i32* %3, align 4, !tbaa !0 + %tmp10 = load i32* %3, align 4 %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8 %4 = bitcast i8* %arrayidx12 to i32* - %tmp13 = load i32* %4, align 4, !tbaa !0 - %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0 + %tmp13 = load i32* %4, align 4 + %tmp16 = load i32* %.pre-phi, align 4 %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16 %5 = bitcast i8* %arrayidx18 to i32* - %tmp19 = load i32* %5, align 4, !tbaa !0 + %tmp19 = load i32* %5, align 4 %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20 %6 = bitcast i8* %arrayidx21 to i32* - %tmp22 = load i32* %6, align 4, !tbaa !0 + %tmp22 = load i32* %6, align 4 %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24 %7 = bitcast i8* %arrayidx24 to i32* - %tmp25 = load i32* %7, align 4, !tbaa !0 + %tmp25 = load i32* %7, align 4 %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind ret i32 0 } @@ -83,7 +83,3 @@ if.end: ; preds = %if.else, %if.then declare void @foo3(i32*) declare i32 @printf(i8* nocapture, ...) nounwind - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll index 398d1b78bd43..c470d1ce2ce5 100644 --- a/test/CodeGen/Mips/divrem.ll +++ b/test/CodeGen/Mips/divrem.ll @@ -32,7 +32,7 @@ entry: define i32 @sdivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind { entry: %rem = srem i32 %a0, %a1 - store i32 %rem, i32* %r, align 4, !tbaa !0 + store i32 %rem, i32* %r, align 4 %div = sdiv i32 %a0, %a1 ret i32 %div } @@ -41,11 +41,7 @@ entry: define i32 @udivrem1(i32 %a0, i32 %a1, i32* nocapture %r) nounwind { entry: %rem = urem i32 %a0, %a1 - store i32 %rem, i32* %r, align 4, !tbaa !0 + store i32 %rem, i32* %r, align 4 %div = udiv i32 %a0, %a1 ret i32 %div } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll new file mode 100644 index 000000000000..9f2f0661f997 --- /dev/null +++ b/test/CodeGen/Mips/dsp-patterns-cmp-vselect.ll @@ -0,0 +1,641 @@ +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s + +; CHECK: select_v2q15_eq_: +; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.ph ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp eq <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2q15_lt_: +; CHECK: cmp.lt.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp slt <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2q15_le_: +; CHECK: cmp.le.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v2q15_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp sle <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2q15_ne_: +; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.ph ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v2q15_ne_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp ne <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2q15_gt_: +; CHECK: cmp.le.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v2q15_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp sgt <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2q15_ge_: +; CHECK: cmp.lt.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v2q15_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp sge <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_eq_: +; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.qb ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v4ui8_eq_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp eq <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_lt_: +; CHECK: cmpu.lt.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v4ui8_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp ult <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_le_: +; CHECK: cmpu.le.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, $6, $7 + +define { i32 } @select_v4ui8_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp ule <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_ne_: +; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.qb ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v4ui8_ne_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp ne <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_gt_: +; CHECK: cmpu.le.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v4ui8_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp ugt <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4ui8_ge_: +; CHECK: cmpu.lt.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, $7, $6 + +define { i32 } @select_v4ui8_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp uge <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2ui16_lt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v2ui16_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp ult <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2ui16_le_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v2ui16_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp ule <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2ui16_gt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v2ui16_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp ugt <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v2ui16_ge_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v2ui16_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %2 = bitcast i32 %a2.coerce to <2 x i16> + %3 = bitcast i32 %a3.coerce to <2 x i16> + %cmp = icmp uge <2 x i16> %0, %1 + %or = select <2 x i1> %cmp, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4i8_lt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v4i8_lt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp slt <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4i8_le_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v4i8_le_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp sle <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4i8_gt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v4i8_gt_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp sgt <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: select_v4i8_ge_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @select_v4i8_ge_(i32 %a0.coerce, i32 %a1.coerce, i32 %a2.coerce, i32 %a3.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %2 = bitcast i32 %a2.coerce to <4 x i8> + %3 = bitcast i32 %a3.coerce to <4 x i8> + %cmp = icmp sge <4 x i8> %0, %1 + %or = select <4 x i1> %cmp, <4 x i8> %2, <4 x i8> %3 + %4 = bitcast <4 x i8> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_eq_: +; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_eq_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp eq <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_lt_: +; CHECK: cmp.lt.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_lt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp slt <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_le_: +; CHECK: cmp.le.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_le_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp sle <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_ne_: +; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_ne_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp ne <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_gt_: +; CHECK: cmp.le.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_gt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp sgt <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2q15_ge_: +; CHECK: cmp.lt.ph $4, $5 +; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v2q15_ge_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp sge <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_eq_: +; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_eq_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp eq <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_lt_: +; CHECK: cmpu.lt.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_lt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp ult <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_le_: +; CHECK: cmpu.le.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_le_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp ule <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_ne_: +; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}} +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_ne_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp ne <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_gt_: +; CHECK: cmpu.le.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_gt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp ugt <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4ui8_ge_: +; CHECK: cmpu.lt.qb $4, $5 +; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}} + +define { i32 } @compare_v4ui8_ge_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp uge <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2ui16_lt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v2ui16_lt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp ult <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2ui16_le_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v2ui16_le_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp ule <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2ui16_gt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v2ui16_gt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp ugt <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v2ui16_ge_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v2ui16_ge_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %1 = bitcast i32 %a1.coerce to <2 x i16> + %cmp = icmp uge <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp to <2 x i16> + %2 = bitcast <2 x i16> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4i8_lt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v4i8_lt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp slt <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4i8_le_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v4i8_le_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp sle <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4i8_gt_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v4i8_gt_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp sgt <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; CHECK: compare_v4i8_ge_: +; CHECK-NOT: cmp +; CHECK-NOT: pick + +define { i32 } @compare_v4i8_ge_(i32 %a0.coerce, i32 %a1.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %1 = bitcast i32 %a1.coerce to <4 x i8> + %cmp = icmp sge <4 x i8> %0, %1 + %sext = sext <4 x i1> %cmp to <4 x i8> + %2 = bitcast <4 x i8> %sext to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} diff --git a/test/CodeGen/Mips/dsp-patterns.ll b/test/CodeGen/Mips/dsp-patterns.ll index 0752f69c3e9e..eeb7140ca2cb 100644 --- a/test/CodeGen/Mips/dsp-patterns.ll +++ b/test/CodeGen/Mips/dsp-patterns.ll @@ -1,7 +1,8 @@ -; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s +; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1 +; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2 -; CHECK: test_lbux: -; CHECK: lbux ${{[0-9]+}} +; R1: test_lbux: +; R1: lbux ${{[0-9]+}} define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) { entry: @@ -10,8 +11,8 @@ entry: ret i8 %0 } -; CHECK: test_lhx: -; CHECK: lhx ${{[0-9]+}} +; R1: test_lhx: +; R1: lhx ${{[0-9]+}} define signext i16 @test_lhx(i16* nocapture %b, i32 %i) { entry: @@ -20,8 +21,8 @@ entry: ret i16 %0 } -; CHECK: test_lwx: -; CHECK: lwx ${{[0-9]+}} +; R1: test_lwx: +; R1: lwx ${{[0-9]+}} define i32 @test_lwx(i32* nocapture %b, i32 %i) { entry: @@ -29,3 +30,232 @@ entry: %0 = load i32* %add.ptr, align 4 ret i32 %0 } + +; R1: test_add_v2q15_: +; R1: addq.ph ${{[0-9]+}} + +define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %add = add <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %add to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_sub_v2q15_: +; R1: subq.ph ${{[0-9]+}} + +define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %sub = sub <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %sub to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R2: test_mul_v2q15_: +; R2: mul.ph ${{[0-9]+}} + +; mul.ph is an R2 instruction. Check that multiply node gets expanded. +; R1: test_mul_v2q15_: +; R1: mul ${{[0-9]+}} +; R1: mul ${{[0-9]+}} + +define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %mul = mul <2 x i16> %0, %1 + %2 = bitcast <2 x i16> %mul to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_add_v4i8_: +; R1: addu.qb ${{[0-9]+}} + +define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %add = add <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %add to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_sub_v4i8_: +; R1: subu.qb ${{[0-9]+}} + +define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %sub = sub <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %sub to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded. +; R2: test_mul_v4i8_: +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} +; R2: mul ${{[0-9]+}} + +define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %1 = bitcast i32 %b.coerce to <4 x i8> + %mul = mul <4 x i8> %0, %1 + %2 = bitcast <4 x i8> %mul to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0 + ret { i32 } %.fca.0.insert +} + +; R1: test_addsc: +; R1: addsc ${{[0-9]+}} +; R1: addwc ${{[0-9]+}} + +define i64 @test_addsc(i64 %a, i64 %b) { +entry: + %add = add nsw i64 %b, %a + ret i64 %add +} + +; R1: shift1_v2i16_shl_: +; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15 + +define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %shl = shl <2 x i16> %0, <i16 15, i16 15> + %1 = bitcast <2 x i16> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; R1: shift1_v2i16_sra_: +; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15 + +define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %shr = ashr <2 x i16> %0, <i16 15, i16 15> + %1 = bitcast <2 x i16> %shr to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; R1: shift1_v2ui16_srl_: +; R1-NOT: shrl.ph +; R2: shift1_v2ui16_srl_: +; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15 + +define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <2 x i16> + %shr = lshr <2 x i16> %0, <i16 15, i16 15> + %1 = bitcast <2 x i16> %shr to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; R1: shift1_v4i8_shl_: +; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7 + +define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %shl = shl <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7> + %1 = bitcast <4 x i8> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; R1: shift1_v4i8_sra_: +; R1-NOT: shra.qb +; R2: shift1_v4i8_sra_: +; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7 + +define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %shr = ashr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7> + %1 = bitcast <4 x i8> %shr to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; R1: shift1_v4ui8_srl_: +; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7 + +define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) { +entry: + %0 = bitcast i32 %a0.coerce to <4 x i8> + %shr = lshr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7> + %1 = bitcast <4 x i8> %shr to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if splat element size is not 16-bit. +; +; R1: test_vector_splat_imm_v2q15: +; R1-NOT: shll.ph + +define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %shl = shl <2 x i16> %0, <i16 0, i16 2> + %1 = bitcast <2 x i16> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if splat element size is not 8-bit. +; +; R1: test_vector_splat_imm_v4i8: +; R1-NOT: shll.qb + +define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %shl = shl <4 x i8> %0, <i8 0, i8 2, i8 0, i8 2> + %1 = bitcast <4 x i8> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field. +; +; R1: test_shift_amount_v2q15: +; R1-NOT: shll.ph + +define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %shl = shl <2 x i16> %0, <i16 16, i16 16> + %1 = bitcast <2 x i16> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} + +; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field. +; +; R1: test_shift_amount_v4i8: +; R1-NOT: shll.qb + +define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <4 x i8> + %shl = shl <4 x i8> %0, <i8 8, i8 8, i8 8, i8 8> + %1 = bitcast <4 x i8> %shl to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0 + ret { i32 } %.fca.0.insert +} diff --git a/test/CodeGen/Mips/dsp-r1.ll b/test/CodeGen/Mips/dsp-r1.ll index c9dc8cfd0be0..acdd17d1afd4 100644 --- a/test/CodeGen/Mips/dsp-r1.ll +++ b/test/CodeGen/Mips/dsp-r1.ll @@ -772,6 +772,7 @@ entry: %0 = bitcast i32 %a0.coerce to <4 x i8> %1 = bitcast i32 %a1.coerce to <4 x i8> + tail call void @llvm.mips.wrdsp(i32 %i0, i32 16) %2 = tail call <4 x i8> @llvm.mips.pick.qb(<4 x i8> %0, <4 x i8> %1) %3 = bitcast <4 x i8> %2 to i32 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 @@ -786,6 +787,7 @@ entry: %0 = bitcast i32 %a0.coerce to <2 x i16> %1 = bitcast i32 %a1.coerce to <2 x i16> + tail call void @llvm.mips.wrdsp(i32 %i0, i32 16) %2 = tail call <2 x i16> @llvm.mips.pick.ph(<2 x i16> %0, <2 x i16> %1) %3 = bitcast <2 x i16> %2 to i32 %.fca.0.insert = insertvalue { i32 } undef, i32 %3, 0 @@ -808,14 +810,6 @@ entry: declare <2 x i16> @llvm.mips.packrl.ph(<2 x i16>, <2 x i16>) nounwind readnone -define i32 @test__builtin_mips_rddsp1(i32 %i0) nounwind readonly { -entry: -; CHECK: rddsp ${{[0-9]+}} - - %0 = tail call i32 @llvm.mips.rddsp(i32 31) - ret i32 %0 -} - define { i32 } @test__builtin_mips_shll_qb1(i32 %i0, i32 %a0.coerce) nounwind { entry: ; CHECK: shll.qb @@ -1232,6 +1226,7 @@ declare i32 @llvm.mips.lwx(i8*, i32) nounwind readonly define i32 @test__builtin_mips_wrdsp1(i32 %i0, i32 %a0) nounwind { entry: ; CHECK: wrdsp ${{[0-9]+}} +; CHECK: rddsp ${{[0-9]+}} tail call void @llvm.mips.wrdsp(i32 %a0, i32 31) %0 = tail call i32 @llvm.mips.rddsp(i32 31) diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index d14150a68a56..fc9e2ef21a8b 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -18,7 +18,7 @@ entry: %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind %0 = bitcast i8* %exception to double* - store double 3.200000e+00, double* %0, align 8, !tbaa !0 + store double 3.200000e+00, double* %0, align 8 invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn to label %unreachable unwind label %lpad @@ -39,7 +39,7 @@ catch: ; preds = %lpad %4 = bitcast i8* %3 to double* %exn.scalar = load double* %4, align 8 %add = fadd double %exn.scalar, %i2 - store double %add, double* @g1, align 8, !tbaa !0 + store double %add, double* @g1, align 8 tail call void @__cxa_end_catch() nounwind ret void @@ -61,7 +61,3 @@ declare void @__cxa_throw(i8*, i8*, i8*) declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/fpneeded.ll b/test/CodeGen/Mips/fpneeded.ll new file mode 100644 index 000000000000..623883a0d5c0 --- /dev/null +++ b/test/CodeGen/Mips/fpneeded.ll @@ -0,0 +1,149 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32 + +@x = global float 1.000000e+00, align 4 +@y = global float 2.000000e+00, align 4 +@zz = common global float 0.000000e+00, align 4 +@z = common global float 0.000000e+00, align 4 + +define float @fv() #0 { +entry: + ret float 1.000000e+00 +} + +; 32: .set nomips16 # @fv +; 32: .ent fv +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end fv + +define double @dv() #0 { +entry: + ret double 2.000000e+00 +} + +; 32: .set nomips16 # @dv +; 32: .ent dv +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end dv + +define void @vf(float %x) #0 { +entry: + %x.addr = alloca float, align 4 + store float %x, float* %x.addr, align 4 + ret void +} + +; 32: .set nomips16 # @vf +; 32: .ent vf +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end vf + +define void @vd(double %x) #0 { +entry: + %x.addr = alloca double, align 8 + store double %x, double* %x.addr, align 8 + ret void +} + +; 32: .set nomips16 # @vd +; 32: .ent vd +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end vd + +define void @foo1() #0 { +entry: + store float 1.000000e+00, float* @zz, align 4 + %0 = load float* @y, align 4 + %1 = load float* @x, align 4 + %add = fadd float %0, %1 + store float %add, float* @z, align 4 + ret void +} + +; 32: .set nomips16 # @foo1 +; 32: .ent foo1 +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end foo1 + +define void @foo2() #0 { +entry: + %0 = load float* @x, align 4 + call void @vf(float %0) + ret void +} + + +; 32: .set nomips16 # @foo2 +; 32: .ent foo2 +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end foo2 + +define void @foo3() #0 { +entry: + %call = call float @fv() + store float %call, float* @x, align 4 + ret void +} + +; 32: .set nomips16 # @foo3 +; 32: .ent foo3 +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end foo3 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +define void @vv() #0 { +entry: + ret void +} + +; 32: .set mips16 # @vv +; 32: .ent vv + +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end vv + + + diff --git a/test/CodeGen/Mips/fpnotneeded.ll b/test/CodeGen/Mips/fpnotneeded.ll new file mode 100644 index 000000000000..dc2ec10817f3 --- /dev/null +++ b/test/CodeGen/Mips/fpnotneeded.ll @@ -0,0 +1,77 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32 + +@i = global i32 1, align 4 +@f = global float 1.000000e+00, align 4 + +define void @vv() #0 { +entry: + ret void +} + +; 32: .set mips16 # @vv +; 32: .ent vv + +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end vv + +define i32 @iv() #0 { +entry: + %0 = load i32* @i, align 4 + ret i32 %0 +} + +; 32: .set mips16 # @iv +; 32: .ent iv + +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end iv + +define void @vif(i32 %i, float %f) #0 { +entry: + %i.addr = alloca i32, align 4 + %f.addr = alloca float, align 4 + store i32 %i, i32* %i.addr, align 4 + store float %f, float* %f.addr, align 4 + ret void +} + +; 32: .set mips16 # @vif +; 32: .ent vif + +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end vif + +define void @foo() #0 { +entry: + store float 2.000000e+00, float* @f, align 4 + ret void +} + +; 32: .set mips16 # @foo +; 32: .ent foo + +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + + +define float @fv() #0 { +entry: + ret float 1.000000e+00 +} + +; 32: .set nomips16 # @fv +; 32: .ent fv +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end fv diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index 1c7c4437b892..a08a0243b8b9 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -1,5 +1,6 @@ ; RUN: llc -march=mipsel < %s | FileCheck %s +; Simple memory @g1 = external global i32 define i32 @f1(i32 %x) nounwind { @@ -21,3 +22,42 @@ entry: ret i32 %0 } +; "D": Second word of double word. This works for any memory element +; double or single. +; CHECK: #APP +; CHECK-NEXT: lw ${{[0-9]+}},4(${{[0-9]+}}); +; CHECK-NEXT: #NO_APP + +; No "D": First word of double word. This works for any memory element +; double or single. +; CHECK: #APP +; CHECK-NEXT: lw ${{[0-9]+}},0(${{[0-9]+}}); +; CHECK-NEXT: #NO_APP + +;int b[8] = {0,1,2,3,4,5,6,7}; +;int main() +;{ +; int i; +; +; // The first word. Notice, no 'D' +; { asm ( +; "lw %0,%1;\n" +; : "=r" (i) : "m" (*(b+4)));} +; +; // The second word +; { asm ( +; "lw %0,%D1;\n" +; : "=r" (i) "m" (*(b+4)));} +;} + +@b = common global [20 x i32] zeroinitializer, align 4 + +define void @main() { +entry: + tail call void asm sideeffect " lw $0,${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3)) + tail call void asm sideeffect " lw $0,${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32]* @b, i32 0, i32 3)) + ret void +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/Mips/mips16_32_1.ll b/test/CodeGen/Mips/mips16_32_1.ll new file mode 100644 index 000000000000..6f4826ea9600 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_1.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s + +define void @foo() #0 { +entry: + ret void +} + +; CHECK: .set mips16 # @foo +; CHECK: .ent foo +; CHECK: save {{.+}} +; CHECK: restore {{.+}} +; CHECK: .end foo +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_10.ll b/test/CodeGen/Mips/mips16_32_10.ll new file mode 100644 index 000000000000..330dbfec63b9 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_10.ll @@ -0,0 +1,59 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 + +define void @foo() #0 { +entry: + ret void +} +; 16: .set nomips16 # @foo +; 16: .ent foo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end foo + +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set mips16 # @nofoo +; 16: .ent nofoo + +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end nofoo + +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set nomips16 # @main +; 16: .ent main +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end main + + + + + + + + + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "nomips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_3.ll b/test/CodeGen/Mips/mips16_32_3.ll new file mode 100644 index 000000000000..8874a8872534 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_3.ll @@ -0,0 +1,70 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 16: .set mips16 # @foo +; 16: .ent foo +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end foo +; 32: .set mips16 # @foo +; 32: .ent foo +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set nomips16 # @nofoo +; 16: .ent nofoo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end nofoo +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set mips16 # @main +; 16: .ent main +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end main +; 32: .set nomips16 # @main +; 32: .ent main +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: addiu $2, $zero, 0 +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end main + +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_4.ll b/test/CodeGen/Mips/mips16_32_4.ll new file mode 100644 index 000000000000..cdaed6c71be0 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_4.ll @@ -0,0 +1,65 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 16: .set mips16 # @foo +; 16: .ent foo +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end foo +; 32: .set mips16 # @foo +; 32: .ent foo +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set nomips16 # @nofoo +; 16: .ent nofoo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end nofoo +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set mips16 # @main +; 16: .ent main +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end main +; 32: .set mips16 # @main +; 32: .ent main +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end main + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_5.ll b/test/CodeGen/Mips/mips16_32_5.ll new file mode 100644 index 000000000000..45e0bf49ddd2 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_5.ll @@ -0,0 +1,80 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 16: .set mips16 # @foo +; 16: .ent foo +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end foo +; 32: .set mips16 # @foo +; 32: .ent foo +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set nomips16 # @nofoo +; 16: .ent nofoo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end nofoo +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set nomips16 # @main +; 16: .ent main +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: addiu $2, $zero, 0 +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end main + +; 32: .set nomips16 # @main +; 32: .ent main +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: addiu $2, $zero, 0 +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end main + + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_6.ll b/test/CodeGen/Mips/mips16_32_6.ll new file mode 100644 index 000000000000..f4b8e7a91adc --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_6.ll @@ -0,0 +1,86 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 16: .set mips16 # @foo +; 16: .ent foo +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end foo +; 32: .set nomips16 # @foo +; 32: .ent foo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set nomips16 # @nofoo +; 16: .ent nofoo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end nofoo +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set nomips16 # @main +; 16: .ent main +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: addiu $2, $zero, 0 +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end main + +; 32: .set nomips16 # @main +; 32: .ent main +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: addiu $2, $zero, 0 +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end main + + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_7.ll b/test/CodeGen/Mips/mips16_32_7.ll new file mode 100644 index 000000000000..f8726eadc70c --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_7.ll @@ -0,0 +1,76 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 16: .set mips16 # @foo +; 16: .ent foo +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end foo +; 32: .set nomips16 # @foo +; 32: .ent foo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 16: .set nomips16 # @nofoo +; 16: .ent nofoo +; 16: .set noreorder +; 16: .set nomacro +; 16: .set noat +; 16: jr $ra +; 16: nop +; 16: .set at +; 16: .set macro +; 16: .set reorder +; 16: .end nofoo +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 16: .set mips16 # @main +; 16: .ent main +; 16: save {{.+}} +; 16: restore {{.+}} +; 16: .end main + +; 32: .set mips16 # @main +; 32: .ent main +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end main + + + + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_8.ll b/test/CodeGen/Mips/mips16_32_8.ll new file mode 100644 index 000000000000..e51f296f9df3 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_8.ll @@ -0,0 +1,74 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +@x = global float 1.000000e+00, align 4 +@y = global float 0x4007333340000000, align 4 +@i = common global i32 0, align 4 +@f = common global float 0.000000e+00, align 4 +@.str = private unnamed_addr constant [8 x i8] c"f = %f\0A\00", align 1 +@.str1 = private unnamed_addr constant [11 x i8] c"hello %i \0A\00", align 1 +@.str2 = private unnamed_addr constant [13 x i8] c"goodbye %i \0A\00", align 1 + +define void @foo() #0 { +entry: + store i32 10, i32* @i, align 4 + ret void +} + +; 32: .set mips16 # @foo +; 32: .ent foo +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo + +define void @nofoo() #1 { +entry: + store i32 20, i32* @i, align 4 + %0 = load float* @x, align 4 + %1 = load float* @y, align 4 + %add = fadd float %0, %1 + store float %add, float* @f, align 4 + %2 = load float* @f, align 4 + %conv = fpext float %2 to double + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), double %conv) + ret void +} + +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: add.s {{.+}} +; 32: mfc1 {{.+}} +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +declare i32 @printf(i8*, ...) #2 + +define i32 @main() #3 { +entry: + call void @foo() + %0 = load i32* @i, align 4 + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str1, i32 0, i32 0), i32 %0) + call void @nofoo() + %1 = load i32* @i, align 4 + %call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str2, i32 0, i32 0), i32 %1) + ret i32 0 +} + +; 32: .set nomips16 # @main +; 32: .ent main +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end main + +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/mips16_32_9.ll b/test/CodeGen/Mips/mips16_32_9.ll new file mode 100644 index 000000000000..f5ff36849015 --- /dev/null +++ b/test/CodeGen/Mips/mips16_32_9.ll @@ -0,0 +1,51 @@ +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 + +define void @foo() #0 { +entry: + ret void +} + +; 32: .set mips16 # @foo +; 32: .ent foo +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end foo +define void @nofoo() #1 { +entry: + ret void +} + +; 32: .set nomips16 # @nofoo +; 32: .ent nofoo +; 32: .set noreorder +; 32: .set nomacro +; 32: .set noat +; 32: jr $ra +; 32: nop +; 32: .set at +; 32: .set macro +; 32: .set reorder +; 32: .end nofoo +define i32 @main() #2 { +entry: + ret i32 0 +} + +; 32: .set mips16 # @main +; 32: .ent main +; 32: save {{.+}} +; 32: restore {{.+}} +; 32: .end main + + + + + + + + + + +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index 40115befc45d..06e2a86ad176 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -130,8 +130,8 @@ define i32 @sel12(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK: c.eq.d ; CHECK: movt - %tmp = load double* @d2, align 8, !tbaa !0 - %tmp1 = load double* @d3, align 8, !tbaa !0 + %tmp = load double* @d2, align 8 + %tmp1 = load double* @d3, align 8 %cmp = fcmp oeq double %tmp, %tmp1 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -141,8 +141,8 @@ define i32 @sel13(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK: c.olt.d ; CHECK: movt - %tmp = load double* @d2, align 8, !tbaa !0 - %tmp1 = load double* @d3, align 8, !tbaa !0 + %tmp = load double* @d2, align 8 + %tmp1 = load double* @d3, align 8 %cmp = fcmp olt double %tmp, %tmp1 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond @@ -152,13 +152,9 @@ define i32 @sel14(i32 %f0, i32 %f1) nounwind readonly { entry: ; CHECK: c.ule.d ; CHECK: movf - %tmp = load double* @d2, align 8, !tbaa !0 - %tmp1 = load double* @d3, align 8, !tbaa !0 + %tmp = load double* @d2, align 8 + %tmp1 = load double* @d3, align 8 %cmp = fcmp ogt double %tmp, %tmp1 %cond = select i1 %cmp, i32 %f0, i32 %f1 ret i32 %cond } - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/spill-copy-acreg.ll b/test/CodeGen/Mips/spill-copy-acreg.ll new file mode 100644 index 000000000000..6563a5cffd91 --- /dev/null +++ b/test/CodeGen/Mips/spill-copy-acreg.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=mipsel -mattr=+dsp < %s + +@g1 = common global i64 0, align 8 +@g2 = common global i64 0, align 8 +@g3 = common global i64 0, align 8 + +define i64 @test_acreg_copy(i32 %a0, i32 %a1, i32 %a2, i32 %a3) { +entry: + %0 = load i64* @g1, align 8 + %1 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a0, i32 %a1) + %2 = tail call i64 @llvm.mips.maddu(i64 %0, i32 %a2, i32 %a3) + store i64 %1, i64* @g1, align 8 + store i64 %2, i64* @g2, align 8 + tail call void @foo1() + store i64 %2, i64* @g3, align 8 + ret i64 %1 +} + +declare i64 @llvm.mips.maddu(i64, i32, i32) + +declare void @foo1() + +@g4 = common global <2 x i16> zeroinitializer, align 4 +@g5 = common global <2 x i16> zeroinitializer, align 4 +@g6 = common global <2 x i16> zeroinitializer, align 4 + +define { i32 } @test_ccond_spill(i32 %a.coerce, i32 %b.coerce) { +entry: + %0 = bitcast i32 %a.coerce to <2 x i16> + %1 = bitcast i32 %b.coerce to <2 x i16> + %cmp3 = icmp slt <2 x i16> %0, %1 + %sext = sext <2 x i1> %cmp3 to <2 x i16> + store <2 x i16> %sext, <2 x i16>* @g4, align 4 + tail call void @foo1() + %2 = load <2 x i16>* @g5, align 4 + %3 = load <2 x i16>* @g6, align 4 + %or = select <2 x i1> %cmp3, <2 x i16> %2, <2 x i16> %3 + %4 = bitcast <2 x i16> %or to i32 + %.fca.0.insert = insertvalue { i32 } undef, i32 %4, 0 + ret { i32 } %.fca.0.insert +} diff --git a/test/CodeGen/Mips/tnaked.ll b/test/CodeGen/Mips/tnaked.ll new file mode 100644 index 000000000000..f5bdd915b28c --- /dev/null +++ b/test/CodeGen/Mips/tnaked.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + + +define void @tnaked() #0 { +entry: + ret void +} + +; CHECK: .ent tnaked +; CHECK: tnaked: +; CHECK-NOT: .frame {{.*}} +; CHECK-NOT: .mask {{.*}} +; CHECK-NOT: .fmask {{.*}} +; CHECK-NOT: addiu $sp, $sp, -8 + +define void @tnonaked() #1 { +entry: + ret void +} + +; CHECK: .ent tnonaked +; CHECK: tnonaked: +; CHECK: .frame $fp,8,$ra +; CHECK: .mask 0x40000000,-4 +; CHECK: .fmask 0x00000000,0 +; CHECK: addiu $sp, $sp, -8 + +attributes #0 = { naked noinline nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll index 79ed6091f887..e0e93e2e7682 100644 --- a/test/CodeGen/Mips/zeroreg.ll +++ b/test/CodeGen/Mips/zeroreg.ll @@ -6,7 +6,7 @@ define i32 @foo0(i32 %s) nounwind readonly { entry: ; CHECK: movn ${{[0-9]+}}, $zero %tobool = icmp ne i32 %s, 0 - %0 = load i32* @g1, align 4, !tbaa !0 + %0 = load i32* @g1, align 4 %cond = select i1 %tobool, i32 0, i32 %0 ret i32 %cond } @@ -15,11 +15,7 @@ define i32 @foo1(i32 %s) nounwind readonly { entry: ; CHECK: movz ${{[0-9]+}}, $zero %tobool = icmp ne i32 %s, 0 - %0 = load i32* @g1, align 4, !tbaa !0 + %0 = load i32* @g1, align 4 %cond = select i1 %tobool, i32 %0, i32 0 ret i32 %cond } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/NVPTX/generic-to-nvvm.ll b/test/CodeGen/NVPTX/generic-to-nvvm.ll new file mode 100644 index 000000000000..c9cb2f71f425 --- /dev/null +++ b/test/CodeGen/NVPTX/generic-to-nvvm.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" + +; Ensure global variables in address space 0 are promoted to address space 1 + +; CHECK: .global .align 4 .u32 myglobal = 42; +@myglobal = internal global i32 42, align 4 +; CHECK: .global .align 4 .u32 myconst = 42; +@myconst = internal constant i32 42, align 4 + + +define void @foo(i32* %a, i32* %b) { +; CHECK: cvta.global.u32 + %ld1 = load i32* @myglobal +; CHECK: cvta.global.u32 + %ld2 = load i32* @myconst + store i32 %ld1, i32* %a + store i32 %ld2, i32* %b + ret void +} + + +!nvvm.annotations = !{!0} +!0 = metadata !{void (i32*, i32*)* @foo, metadata !"kernel", i32 1} diff --git a/test/CodeGen/NVPTX/i1-global.ll b/test/CodeGen/NVPTX/i1-global.ll new file mode 100644 index 000000000000..0595325977e1 --- /dev/null +++ b/test/CodeGen/NVPTX/i1-global.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" + + +; CHECK: .visible .global .align 1 .u8 mypred +@mypred = addrspace(1) global i1 true, align 1 + + +define void @foo(i1 %p, i32* %out) { + %ld = load i1 addrspace(1)* @mypred + %val = zext i1 %ld to i32 + store i32 %val, i32* %out + ret void +} + + +!nvvm.annotations = !{!0} +!0 = metadata !{void (i1, i32*)* @foo, metadata !"kernel", i32 1} diff --git a/test/CodeGen/NVPTX/i1-param.ll b/test/CodeGen/NVPTX/i1-param.ll new file mode 100644 index 000000000000..fabd61a25d2f --- /dev/null +++ b/test/CodeGen/NVPTX/i1-param.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" + +; Make sure predicate (i1) operands to kernels get expanded out to .u8 + +; CHECK: .entry foo +; CHECK: .param .u8 foo_param_0 +; CHECK: .param .u32 foo_param_1 +define void @foo(i1 %p, i32* %out) { + %val = zext i1 %p to i32 + store i32 %val, i32* %out + ret void +} + + +!nvvm.annotations = !{!0} +!0 = metadata !{void (i1, i32*)* @foo, metadata !"kernel", i32 1} diff --git a/test/CodeGen/NVPTX/intrinsics.ll b/test/CodeGen/NVPTX/intrinsics.ll index 8b0357be87cb..1676f20643d2 100644 --- a/test/CodeGen/NVPTX/intrinsics.ll +++ b/test/CodeGen/NVPTX/intrinsics.ll @@ -15,5 +15,12 @@ define ptx_device double @test_fabs(double %d) { ret double %x } +define float @test_nvvm_sqrt(float %a) { + %val = call float @llvm.nvvm.sqrt.f(float %a) + ret float %val +} + + declare float @llvm.fabs.f32(float) declare double @llvm.fabs.f64(double) +declare float @llvm.nvvm.sqrt.f(float) diff --git a/test/CodeGen/NVPTX/refl1.ll b/test/CodeGen/NVPTX/refl1.ll new file mode 100644 index 000000000000..5a9dac152e41 --- /dev/null +++ b/test/CodeGen/NVPTX/refl1.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -drvcuda | FileCheck %s + +; Function Attrs: nounwind +; CHECK: .entry foo +define void @foo(float* nocapture %a) #0 { + %val = load float* %a + %tan = tail call fastcc float @__nv_fast_tanf(float %val) + store float %tan, float* %a + ret void +} + +; Function Attrs: nounwind readnone +declare float @llvm.nvvm.sin.approx.ftz.f(float) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.nvvm.cos.approx.ftz.f(float) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.nvvm.div.approx.ftz.f(float, float) #1 + +; Function Attrs: alwaysinline inlinehint nounwind readnone +; CHECK: .func (.param .b32 func_retval0) __nv_fast_tanf +define internal fastcc float @__nv_fast_tanf(float %a) #2 { +entry: + %0 = tail call float @llvm.nvvm.sin.approx.ftz.f(float %a) + %1 = tail call float @llvm.nvvm.cos.approx.ftz.f(float %a) + %2 = tail call float @llvm.nvvm.div.approx.ftz.f(float %0, float %1) + ret float %2 +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { alwaysinline inlinehint nounwind readnone } + +!nvvm.annotations = !{!0} + +!0 = metadata !{void (float*)* @foo, metadata !"kernel", i32 1} diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll index ea7de9847ea7..40f46fda468d 100644 --- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 | grep lwzx +; RUN: llc < %s -march=ppc64 | FileCheck %s %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] } %struct.__mutex_t = type { i32 } @@ -11,6 +11,10 @@ entry: %tmp = load i32* %ttype, align 4 ; <i32> [#uses=1] %tmp1 = call i32 (...)* @bork( i32 %tmp ) ; <i32> [#uses=0] ret void + +; CHECK: @foo +; CHECK: lwzx +; CHECK: blr } declare i32 @bork(...) diff --git a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll index 47d985c5f755..3acd01dcb273 100644 --- a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll +++ b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll @@ -47,11 +47,11 @@ for.body4.us: ; preds = %for.body4.lr.ph.us, %sext = shl i64 %sub5.us, 32 %idxprom.us = ashr exact i64 %sext, 32 %arrayidx.us = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us - %2 = load float* %arrayidx.us, align 4, !tbaa !5 + %2 = load float* %arrayidx.us, align 4 %arrayidx7.us = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv - %3 = load float* %arrayidx7.us, align 4, !tbaa !5 + %3 = load float* %arrayidx7.us, align 4 %add8.us = fadd float %3, %2 - store float %add8.us, float* %arrayidx7.us, align 4, !tbaa !5 + store float %add8.us, float* %arrayidx7.us, align 4 %indvars.iv.next = add i64 %indvars.iv, %1 %4 = trunc i64 %indvars.iv.next to i32 %cmp3.us = icmp slt i32 %4, 32000 @@ -82,11 +82,11 @@ for.body4.us.1: ; preds = %for.body4.us.1, %fo %sext23 = shl i64 %sub5.us.1, 32 %idxprom.us.1 = ashr exact i64 %sext23, 32 %arrayidx.us.1 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.1 - %5 = load float* %arrayidx.us.1, align 4, !tbaa !5 + %5 = load float* %arrayidx.us.1, align 4 %arrayidx7.us.1 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.1 - %6 = load float* %arrayidx7.us.1, align 4, !tbaa !5 + %6 = load float* %arrayidx7.us.1, align 4 %add8.us.1 = fadd float %6, %5 - store float %add8.us.1, float* %arrayidx7.us.1, align 4, !tbaa !5 + store float %add8.us.1, float* %arrayidx7.us.1, align 4 %indvars.iv.next.1 = add i64 %indvars.iv.1, %1 %7 = trunc i64 %indvars.iv.next.1 to i32 %cmp3.us.1 = icmp slt i32 %7, 32000 @@ -104,11 +104,11 @@ for.body4.us.2: ; preds = %for.body4.us.2, %fo %sext24 = shl i64 %sub5.us.2, 32 %idxprom.us.2 = ashr exact i64 %sext24, 32 %arrayidx.us.2 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.2 - %8 = load float* %arrayidx.us.2, align 4, !tbaa !5 + %8 = load float* %arrayidx.us.2, align 4 %arrayidx7.us.2 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.2 - %9 = load float* %arrayidx7.us.2, align 4, !tbaa !5 + %9 = load float* %arrayidx7.us.2, align 4 %add8.us.2 = fadd float %9, %8 - store float %add8.us.2, float* %arrayidx7.us.2, align 4, !tbaa !5 + store float %add8.us.2, float* %arrayidx7.us.2, align 4 %indvars.iv.next.2 = add i64 %indvars.iv.2, %1 %10 = trunc i64 %indvars.iv.next.2 to i32 %cmp3.us.2 = icmp slt i32 %10, 32000 @@ -126,11 +126,11 @@ for.body4.us.3: ; preds = %for.body4.us.3, %fo %sext25 = shl i64 %sub5.us.3, 32 %idxprom.us.3 = ashr exact i64 %sext25, 32 %arrayidx.us.3 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.3 - %11 = load float* %arrayidx.us.3, align 4, !tbaa !5 + %11 = load float* %arrayidx.us.3, align 4 %arrayidx7.us.3 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.3 - %12 = load float* %arrayidx7.us.3, align 4, !tbaa !5 + %12 = load float* %arrayidx7.us.3, align 4 %add8.us.3 = fadd float %12, %11 - store float %add8.us.3, float* %arrayidx7.us.3, align 4, !tbaa !5 + store float %add8.us.3, float* %arrayidx7.us.3, align 4 %indvars.iv.next.3 = add i64 %indvars.iv.3, %1 %13 = trunc i64 %indvars.iv.next.3 to i32 %cmp3.us.3 = icmp slt i32 %13, 32000 @@ -148,11 +148,11 @@ for.body4.us.4: ; preds = %for.body4.us.4, %fo %sext26 = shl i64 %sub5.us.4, 32 %idxprom.us.4 = ashr exact i64 %sext26, 32 %arrayidx.us.4 = getelementptr inbounds [32000 x float]* @b, i64 0, i64 %idxprom.us.4 - %14 = load float* %arrayidx.us.4, align 4, !tbaa !5 + %14 = load float* %arrayidx.us.4, align 4 %arrayidx7.us.4 = getelementptr inbounds [32000 x float]* @a, i64 0, i64 %indvars.iv.4 - %15 = load float* %arrayidx7.us.4, align 4, !tbaa !5 + %15 = load float* %arrayidx7.us.4, align 4 %add8.us.4 = fadd float %15, %14 - store float %add8.us.4, float* %arrayidx7.us.4, align 4, !tbaa !5 + store float %add8.us.4, float* %arrayidx7.us.4, align 4 %indvars.iv.next.4 = add i64 %indvars.iv.4, %1 %16 = trunc i64 %indvars.iv.next.4 to i32 %cmp3.us.4 = icmp slt i32 %16, 32000 @@ -183,9 +183,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, declare i32 @puts(i8* nocapture) nounwind -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} !3 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!4 = metadata !{metadata !"int", metadata !1} -!5 = metadata !{metadata !"float", metadata !1} diff --git a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll index 52bf6c7e5017..4a1a51237ffd 100644 --- a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll +++ b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll @@ -35,7 +35,7 @@ entry: for.body: ; preds = %for.end17, %entry %nl.041 = phi i32 [ 0, %entry ], [ %inc22, %for.end17 ] - %0 = load float* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0, i64 0), align 16, !tbaa !5 + %0 = load float* getelementptr inbounds ([256 x [256 x float]]* @aa, i64 0, i64 0, i64 0), align 16 br label %for.cond5.preheader for.cond5.preheader: ; preds = %for.inc15, %for.body @@ -51,7 +51,7 @@ for.body7: ; preds = %for.body7, %for.con %xindex.234 = phi i32 [ %xindex.138, %for.cond5.preheader ], [ %xindex.3.15, %for.body7 ] %yindex.233 = phi i32 [ %yindex.137, %for.cond5.preheader ], [ %yindex.3.15, %for.body7 ] %arrayidx9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv - %1 = load float* %arrayidx9, align 16, !tbaa !5 + %1 = load float* %arrayidx9, align 16 %cmp10 = fcmp ogt float %1, %max.235 %2 = trunc i64 %indvars.iv to i32 %yindex.3 = select i1 %cmp10, i32 %2, i32 %yindex.233 @@ -60,7 +60,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3 = select i1 %cmp10, float %1, float %max.235 %indvars.iv.next45 = or i64 %indvars.iv, 1 %arrayidx9.1 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next45 - %4 = load float* %arrayidx9.1, align 4, !tbaa !5 + %4 = load float* %arrayidx9.1, align 4 %cmp10.1 = fcmp ogt float %4, %max.3 %5 = trunc i64 %indvars.iv.next45 to i32 %yindex.3.1 = select i1 %cmp10.1, i32 %5, i32 %yindex.3 @@ -68,7 +68,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.1 = select i1 %cmp10.1, float %4, float %max.3 %indvars.iv.next.146 = or i64 %indvars.iv, 2 %arrayidx9.2 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.146 - %6 = load float* %arrayidx9.2, align 8, !tbaa !5 + %6 = load float* %arrayidx9.2, align 8 %cmp10.2 = fcmp ogt float %6, %max.3.1 %7 = trunc i64 %indvars.iv.next.146 to i32 %yindex.3.2 = select i1 %cmp10.2, i32 %7, i32 %yindex.3.1 @@ -76,7 +76,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.2 = select i1 %cmp10.2, float %6, float %max.3.1 %indvars.iv.next.247 = or i64 %indvars.iv, 3 %arrayidx9.3 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.247 - %8 = load float* %arrayidx9.3, align 4, !tbaa !5 + %8 = load float* %arrayidx9.3, align 4 %cmp10.3 = fcmp ogt float %8, %max.3.2 %9 = trunc i64 %indvars.iv.next.247 to i32 %yindex.3.3 = select i1 %cmp10.3, i32 %9, i32 %yindex.3.2 @@ -84,7 +84,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.3 = select i1 %cmp10.3, float %8, float %max.3.2 %indvars.iv.next.348 = or i64 %indvars.iv, 4 %arrayidx9.4 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.348 - %10 = load float* %arrayidx9.4, align 16, !tbaa !5 + %10 = load float* %arrayidx9.4, align 16 %cmp10.4 = fcmp ogt float %10, %max.3.3 %11 = trunc i64 %indvars.iv.next.348 to i32 %yindex.3.4 = select i1 %cmp10.4, i32 %11, i32 %yindex.3.3 @@ -92,7 +92,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.4 = select i1 %cmp10.4, float %10, float %max.3.3 %indvars.iv.next.449 = or i64 %indvars.iv, 5 %arrayidx9.5 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.449 - %12 = load float* %arrayidx9.5, align 4, !tbaa !5 + %12 = load float* %arrayidx9.5, align 4 %cmp10.5 = fcmp ogt float %12, %max.3.4 %13 = trunc i64 %indvars.iv.next.449 to i32 %yindex.3.5 = select i1 %cmp10.5, i32 %13, i32 %yindex.3.4 @@ -100,7 +100,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.5 = select i1 %cmp10.5, float %12, float %max.3.4 %indvars.iv.next.550 = or i64 %indvars.iv, 6 %arrayidx9.6 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.550 - %14 = load float* %arrayidx9.6, align 8, !tbaa !5 + %14 = load float* %arrayidx9.6, align 8 %cmp10.6 = fcmp ogt float %14, %max.3.5 %15 = trunc i64 %indvars.iv.next.550 to i32 %yindex.3.6 = select i1 %cmp10.6, i32 %15, i32 %yindex.3.5 @@ -108,7 +108,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.6 = select i1 %cmp10.6, float %14, float %max.3.5 %indvars.iv.next.651 = or i64 %indvars.iv, 7 %arrayidx9.7 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.651 - %16 = load float* %arrayidx9.7, align 4, !tbaa !5 + %16 = load float* %arrayidx9.7, align 4 %cmp10.7 = fcmp ogt float %16, %max.3.6 %17 = trunc i64 %indvars.iv.next.651 to i32 %yindex.3.7 = select i1 %cmp10.7, i32 %17, i32 %yindex.3.6 @@ -116,7 +116,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.7 = select i1 %cmp10.7, float %16, float %max.3.6 %indvars.iv.next.752 = or i64 %indvars.iv, 8 %arrayidx9.8 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.752 - %18 = load float* %arrayidx9.8, align 16, !tbaa !5 + %18 = load float* %arrayidx9.8, align 16 %cmp10.8 = fcmp ogt float %18, %max.3.7 %19 = trunc i64 %indvars.iv.next.752 to i32 %yindex.3.8 = select i1 %cmp10.8, i32 %19, i32 %yindex.3.7 @@ -124,7 +124,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.8 = select i1 %cmp10.8, float %18, float %max.3.7 %indvars.iv.next.853 = or i64 %indvars.iv, 9 %arrayidx9.9 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.853 - %20 = load float* %arrayidx9.9, align 4, !tbaa !5 + %20 = load float* %arrayidx9.9, align 4 %cmp10.9 = fcmp ogt float %20, %max.3.8 %21 = trunc i64 %indvars.iv.next.853 to i32 %yindex.3.9 = select i1 %cmp10.9, i32 %21, i32 %yindex.3.8 @@ -132,7 +132,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.9 = select i1 %cmp10.9, float %20, float %max.3.8 %indvars.iv.next.954 = or i64 %indvars.iv, 10 %arrayidx9.10 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.954 - %22 = load float* %arrayidx9.10, align 8, !tbaa !5 + %22 = load float* %arrayidx9.10, align 8 %cmp10.10 = fcmp ogt float %22, %max.3.9 %23 = trunc i64 %indvars.iv.next.954 to i32 %yindex.3.10 = select i1 %cmp10.10, i32 %23, i32 %yindex.3.9 @@ -140,7 +140,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.10 = select i1 %cmp10.10, float %22, float %max.3.9 %indvars.iv.next.1055 = or i64 %indvars.iv, 11 %arrayidx9.11 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1055 - %24 = load float* %arrayidx9.11, align 4, !tbaa !5 + %24 = load float* %arrayidx9.11, align 4 %cmp10.11 = fcmp ogt float %24, %max.3.10 %25 = trunc i64 %indvars.iv.next.1055 to i32 %yindex.3.11 = select i1 %cmp10.11, i32 %25, i32 %yindex.3.10 @@ -148,7 +148,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.11 = select i1 %cmp10.11, float %24, float %max.3.10 %indvars.iv.next.1156 = or i64 %indvars.iv, 12 %arrayidx9.12 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1156 - %26 = load float* %arrayidx9.12, align 16, !tbaa !5 + %26 = load float* %arrayidx9.12, align 16 %cmp10.12 = fcmp ogt float %26, %max.3.11 %27 = trunc i64 %indvars.iv.next.1156 to i32 %yindex.3.12 = select i1 %cmp10.12, i32 %27, i32 %yindex.3.11 @@ -156,7 +156,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.12 = select i1 %cmp10.12, float %26, float %max.3.11 %indvars.iv.next.1257 = or i64 %indvars.iv, 13 %arrayidx9.13 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1257 - %28 = load float* %arrayidx9.13, align 4, !tbaa !5 + %28 = load float* %arrayidx9.13, align 4 %cmp10.13 = fcmp ogt float %28, %max.3.12 %29 = trunc i64 %indvars.iv.next.1257 to i32 %yindex.3.13 = select i1 %cmp10.13, i32 %29, i32 %yindex.3.12 @@ -164,7 +164,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.13 = select i1 %cmp10.13, float %28, float %max.3.12 %indvars.iv.next.1358 = or i64 %indvars.iv, 14 %arrayidx9.14 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1358 - %30 = load float* %arrayidx9.14, align 8, !tbaa !5 + %30 = load float* %arrayidx9.14, align 8 %cmp10.14 = fcmp ogt float %30, %max.3.13 %31 = trunc i64 %indvars.iv.next.1358 to i32 %yindex.3.14 = select i1 %cmp10.14, i32 %31, i32 %yindex.3.13 @@ -172,7 +172,7 @@ for.body7: ; preds = %for.body7, %for.con %max.3.14 = select i1 %cmp10.14, float %30, float %max.3.13 %indvars.iv.next.1459 = or i64 %indvars.iv, 15 %arrayidx9.15 = getelementptr inbounds [256 x [256 x float]]* @aa, i64 0, i64 %indvars.iv42, i64 %indvars.iv.next.1459 - %32 = load float* %arrayidx9.15, align 4, !tbaa !5 + %32 = load float* %arrayidx9.15, align 4 %cmp10.15 = fcmp ogt float %32, %max.3.14 %33 = trunc i64 %indvars.iv.next.1459 to i32 %yindex.3.15 = select i1 %cmp10.15, i32 %33, i32 %yindex.3.14 @@ -208,7 +208,7 @@ for.end23: ; preds = %for.end17 %add29 = fadd float %add, 1.000000e+00 %add31 = fadd float %add29, %conv18 %add32 = fadd float %add31, 1.000000e+00 - store float %add32, float* @temp, align 4, !tbaa !5 + store float %add32, float* @temp, align 4 tail call void @check(i32 -1) ret i32 0 } @@ -217,9 +217,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, declare i32 @puts(i8* nocapture) nounwind -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} !3 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!4 = metadata !{metadata !"int", metadata !1} -!5 = metadata !{metadata !"float", metadata !1} diff --git a/test/CodeGen/PowerPC/bdzlr.ll b/test/CodeGen/PowerPC/bdzlr.ll new file mode 100644 index 000000000000..656a85860df0 --- /dev/null +++ b/test/CodeGen/PowerPC/bdzlr.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.lua_TValue.17.692 = type { %union.Value.16.691, i32 } +%union.Value.16.691 = type { %union.GCObject.15.690* } +%union.GCObject.15.690 = type { %struct.lua_State.14.689 } +%struct.lua_State.14.689 = type { %union.GCObject.15.690*, i8, i8, i8, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.global_State.10.685*, %struct.CallInfo.11.686*, i32*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.CallInfo.11.686*, %struct.CallInfo.11.686*, i32, i32, i16, i16, i8, i8, i32, i32, void (%struct.lua_State.14.689*, %struct.lua_Debug.12.687*)*, %struct.lua_TValue.17.692, %struct.lua_TValue.17.692, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.lua_longjmp.13.688*, i64 } +%struct.global_State.10.685 = type { %struct.stringtable.0.675, i8* (i8*, i8*, i64, i64)*, i8*, i8, i8, i32, %union.GCObject.15.690*, %union.GCObject.15.690**, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.Mbuffer.1.676, i64, i64, i64, i64, i32, i32, i32 (%struct.lua_State.14.689*)*, %struct.lua_TValue.17.692, %struct.lua_State.14.689*, %struct.UpVal.3.678, [9 x %struct.Table.7.682*], [17 x %union.TString.9.684*] } +%struct.stringtable.0.675 = type { %union.GCObject.15.690**, i32, i32 } +%struct.Mbuffer.1.676 = type { i8*, i64, i64 } +%struct.UpVal.3.678 = type { %union.GCObject.15.690*, i8, i8, %struct.lua_TValue.17.692*, %union.anon.2.677 } +%union.anon.2.677 = type { %struct.lua_TValue.17.692 } +%struct.Table.7.682 = type { %union.GCObject.15.690*, i8, i8, i8, i8, %struct.Table.7.682*, %struct.lua_TValue.17.692*, %struct.Node.6.681*, %struct.Node.6.681*, %union.GCObject.15.690*, i32 } +%struct.Node.6.681 = type { %struct.lua_TValue.17.692, %union.TKey.5.680 } +%union.TKey.5.680 = type { %struct.anon.0.4.679 } +%struct.anon.0.4.679 = type { %union.Value.16.691, i32, %struct.Node.6.681* } +%union.TString.9.684 = type { %struct.anon.1.8.683 } +%struct.anon.1.8.683 = type { %union.GCObject.15.690*, i8, i8, i8, i32, i64 } +%struct.CallInfo.11.686 = type { %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, i32*, i32, i32 } +%struct.lua_Debug.12.687 = type { i32, i8*, i8*, i8*, i8*, i32, i32, i32, i32, [60 x i8], i32 } +%struct.lua_longjmp.13.688 = type opaque + +define void @lua_xmove(i32 signext %n) #0 { +entry: + br i1 undef, label %for.end, label %if.end + +if.end: ; preds = %entry + br i1 undef, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %if.end + br label %for.body + +for.body: ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph + %0 = phi %struct.lua_TValue.17.692* [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ] + %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ] + %tt = getelementptr inbounds %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1 + %1 = load i32* %tt, align 4, !tbaa !0 + store i32 %1, i32* undef, align 4, !tbaa !0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge + +for.body.for.body_crit_edge: ; preds = %for.body + %.pre = load %struct.lua_TValue.17.692** undef, align 8, !tbaa !3 + br label %for.body + +for.end: ; preds = %for.body, %if.end, %entry + ret void + +; CHECK: @lua_xmove +; CHECK: bnelr +; CHECK: bnelr +; CHECK: bdzlr +; CHECK-NOT: blr +} + +attributes #0 = { nounwind } + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"any pointer", metadata !1} diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index 3e98dbd254d9..f1cbc5afa8ac 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC32 -; RUN: llc -O0 -disable-fp-elim -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 +; RUN: llc -O0 -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=PPC64 declare void @foo() @@ -13,15 +13,19 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC64: mfcr 12 -; PPC64-NEXT: stw 12, 8(1) +; PPC64: stw 12, 8(1) +; PPC64: stdu 1, -[[AMT:[0-9]+]](1) +; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64-NEXT: mtcrf 32, 12 +; PPC64: mtcrf 32, 12 define i32 @test_cr234() nounwind { entry: @@ -33,17 +37,21 @@ entry: ret i32 %1 } +; PPC32: stw 31, -4(1) +; PPC32: stwu 1, -32(1) ; PPC32: mfcr 12 -; PPC32-NEXT: stw 12, {{[0-9]+}}(31) -; PPC32: lwz 12, {{[0-9]+}}(31) +; PPC32-NEXT: stw 12, 24(31) +; PPC32: lwz 12, 24(31) ; PPC32-NEXT: mtcrf 32, 12 ; PPC32-NEXT: mtcrf 16, 12 ; PPC32-NEXT: mtcrf 8, 12 ; PPC64: mfcr 12 -; PPC64-NEXT: stw 12, 8(1) +; PPC64: stw 12, 8(1) +; PPC64: stdu 1, -[[AMT:[0-9]+]](1) +; PPC64: addi 1, 1, [[AMT]] ; PPC64: lwz 12, 8(1) -; PPC64-NEXT: mtcrf 32, 12 -; PPC64-NEXT: mtcrf 16, 12 -; PPC64-NEXT: mtcrf 8, 12 +; PPC64: mtcrf 32, 12 +; PPC64: mtcrf 16, 12 +; PPC64: mtcrf 8, 12 diff --git a/test/CodeGen/PowerPC/ctrloop-s000.ll b/test/CodeGen/PowerPC/ctrloop-s000.ll index dcea06f29e7c..4d8ef50501f2 100644 --- a/test/CodeGen/PowerPC/ctrloop-s000.ll +++ b/test/CodeGen/PowerPC/ctrloop-s000.ll @@ -36,100 +36,100 @@ for.cond1.preheader: ; preds = %for.end, %entry for.body3: ; preds = %for.body3, %for.cond1.preheader %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next.15, %for.body3 ] %arrayidx = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv - %0 = load double* %arrayidx, align 32, !tbaa !0 + %0 = load double* %arrayidx, align 32 %add = fadd double %0, 1.000000e+00 %arrayidx5 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv - store double %add, double* %arrayidx5, align 32, !tbaa !0 + store double %add, double* %arrayidx5, align 32 %indvars.iv.next11 = or i64 %indvars.iv, 1 %arrayidx.1 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next11 - %1 = load double* %arrayidx.1, align 8, !tbaa !0 + %1 = load double* %arrayidx.1, align 8 %add.1 = fadd double %1, 1.000000e+00 %arrayidx5.1 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next11 - store double %add.1, double* %arrayidx5.1, align 8, !tbaa !0 + store double %add.1, double* %arrayidx5.1, align 8 %indvars.iv.next.112 = or i64 %indvars.iv, 2 %arrayidx.2 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.112 - %2 = load double* %arrayidx.2, align 16, !tbaa !0 + %2 = load double* %arrayidx.2, align 16 %add.2 = fadd double %2, 1.000000e+00 %arrayidx5.2 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.112 - store double %add.2, double* %arrayidx5.2, align 16, !tbaa !0 + store double %add.2, double* %arrayidx5.2, align 16 %indvars.iv.next.213 = or i64 %indvars.iv, 3 %arrayidx.3 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.213 - %3 = load double* %arrayidx.3, align 8, !tbaa !0 + %3 = load double* %arrayidx.3, align 8 %add.3 = fadd double %3, 1.000000e+00 %arrayidx5.3 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.213 - store double %add.3, double* %arrayidx5.3, align 8, !tbaa !0 + store double %add.3, double* %arrayidx5.3, align 8 %indvars.iv.next.314 = or i64 %indvars.iv, 4 %arrayidx.4 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.314 - %4 = load double* %arrayidx.4, align 32, !tbaa !0 + %4 = load double* %arrayidx.4, align 32 %add.4 = fadd double %4, 1.000000e+00 %arrayidx5.4 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.314 - store double %add.4, double* %arrayidx5.4, align 32, !tbaa !0 + store double %add.4, double* %arrayidx5.4, align 32 %indvars.iv.next.415 = or i64 %indvars.iv, 5 %arrayidx.5 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.415 - %5 = load double* %arrayidx.5, align 8, !tbaa !0 + %5 = load double* %arrayidx.5, align 8 %add.5 = fadd double %5, 1.000000e+00 %arrayidx5.5 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.415 - store double %add.5, double* %arrayidx5.5, align 8, !tbaa !0 + store double %add.5, double* %arrayidx5.5, align 8 %indvars.iv.next.516 = or i64 %indvars.iv, 6 %arrayidx.6 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.516 - %6 = load double* %arrayidx.6, align 16, !tbaa !0 + %6 = load double* %arrayidx.6, align 16 %add.6 = fadd double %6, 1.000000e+00 %arrayidx5.6 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.516 - store double %add.6, double* %arrayidx5.6, align 16, !tbaa !0 + store double %add.6, double* %arrayidx5.6, align 16 %indvars.iv.next.617 = or i64 %indvars.iv, 7 %arrayidx.7 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.617 - %7 = load double* %arrayidx.7, align 8, !tbaa !0 + %7 = load double* %arrayidx.7, align 8 %add.7 = fadd double %7, 1.000000e+00 %arrayidx5.7 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.617 - store double %add.7, double* %arrayidx5.7, align 8, !tbaa !0 + store double %add.7, double* %arrayidx5.7, align 8 %indvars.iv.next.718 = or i64 %indvars.iv, 8 %arrayidx.8 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.718 - %8 = load double* %arrayidx.8, align 32, !tbaa !0 + %8 = load double* %arrayidx.8, align 32 %add.8 = fadd double %8, 1.000000e+00 %arrayidx5.8 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.718 - store double %add.8, double* %arrayidx5.8, align 32, !tbaa !0 + store double %add.8, double* %arrayidx5.8, align 32 %indvars.iv.next.819 = or i64 %indvars.iv, 9 %arrayidx.9 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.819 - %9 = load double* %arrayidx.9, align 8, !tbaa !0 + %9 = load double* %arrayidx.9, align 8 %add.9 = fadd double %9, 1.000000e+00 %arrayidx5.9 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.819 - store double %add.9, double* %arrayidx5.9, align 8, !tbaa !0 + store double %add.9, double* %arrayidx5.9, align 8 %indvars.iv.next.920 = or i64 %indvars.iv, 10 %arrayidx.10 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.920 - %10 = load double* %arrayidx.10, align 16, !tbaa !0 + %10 = load double* %arrayidx.10, align 16 %add.10 = fadd double %10, 1.000000e+00 %arrayidx5.10 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.920 - store double %add.10, double* %arrayidx5.10, align 16, !tbaa !0 + store double %add.10, double* %arrayidx5.10, align 16 %indvars.iv.next.1021 = or i64 %indvars.iv, 11 %arrayidx.11 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1021 - %11 = load double* %arrayidx.11, align 8, !tbaa !0 + %11 = load double* %arrayidx.11, align 8 %add.11 = fadd double %11, 1.000000e+00 %arrayidx5.11 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1021 - store double %add.11, double* %arrayidx5.11, align 8, !tbaa !0 + store double %add.11, double* %arrayidx5.11, align 8 %indvars.iv.next.1122 = or i64 %indvars.iv, 12 %arrayidx.12 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1122 - %12 = load double* %arrayidx.12, align 32, !tbaa !0 + %12 = load double* %arrayidx.12, align 32 %add.12 = fadd double %12, 1.000000e+00 %arrayidx5.12 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1122 - store double %add.12, double* %arrayidx5.12, align 32, !tbaa !0 + store double %add.12, double* %arrayidx5.12, align 32 %indvars.iv.next.1223 = or i64 %indvars.iv, 13 %arrayidx.13 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1223 - %13 = load double* %arrayidx.13, align 8, !tbaa !0 + %13 = load double* %arrayidx.13, align 8 %add.13 = fadd double %13, 1.000000e+00 %arrayidx5.13 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1223 - store double %add.13, double* %arrayidx5.13, align 8, !tbaa !0 + store double %add.13, double* %arrayidx5.13, align 8 %indvars.iv.next.1324 = or i64 %indvars.iv, 14 %arrayidx.14 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1324 - %14 = load double* %arrayidx.14, align 16, !tbaa !0 + %14 = load double* %arrayidx.14, align 16 %add.14 = fadd double %14, 1.000000e+00 %arrayidx5.14 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1324 - store double %add.14, double* %arrayidx5.14, align 16, !tbaa !0 + store double %add.14, double* %arrayidx5.14, align 16 %indvars.iv.next.1425 = or i64 %indvars.iv, 15 %arrayidx.15 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1425 - %15 = load double* %arrayidx.15, align 8, !tbaa !0 + %15 = load double* %arrayidx.15, align 8 %add.15 = fadd double %15, 1.000000e+00 %arrayidx5.15 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1425 - store double %add.15, double* %arrayidx5.15, align 8, !tbaa !0 + store double %add.15, double* %arrayidx5.15, align 8 %indvars.iv.next.15 = add i64 %indvars.iv, 16 %lftr.wideiv.15 = trunc i64 %indvars.iv.next.15 to i32 %exitcond.15 = icmp eq i32 %lftr.wideiv.15, 16000 @@ -150,7 +150,3 @@ for.end8: ; preds = %for.end } declare i32 @dummy(double*, double*, double*, double*, double*, [256 x double]*, [256 x double]*, [256 x double]*, double) - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/ctrloop-sums.ll b/test/CodeGen/PowerPC/ctrloop-sums.ll index eae8c38eee0e..d9965f280e72 100644 --- a/test/CodeGen/PowerPC/ctrloop-sums.ll +++ b/test/CodeGen/PowerPC/ctrloop-sums.ll @@ -24,7 +24,7 @@ for.body3.us: ; preds = %for.body3.us, %for. %indvars.iv = phi i64 [ 0, %for.body3.lr.ph.us ], [ %indvars.iv.next, %for.body3.us ] %Result.111.us = phi i32 [ %Result.014.us, %for.body3.lr.ph.us ], [ %add.us, %for.body3.us ] %arrayidx5.us = getelementptr inbounds [100 x i32]* %Array, i64 %indvars.iv16, i64 %indvars.iv - %0 = load i32* %arrayidx5.us, align 4, !tbaa !0 + %0 = load i32* %arrayidx5.us, align 4 %add.us = add nsw i32 %0, %Result.111.us %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 @@ -60,7 +60,7 @@ for.body: ; preds = %for.body, %entry %0 = trunc i64 %indvars.iv33 to i32 %sub = sub i32 0, %0 %arrayidx2 = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv33, i64 %indvars.iv33 - store i32 %sub, i32* %arrayidx2, align 4, !tbaa !0 + store i32 %sub, i32* %arrayidx2, align 4 %indvars.iv.next34 = add i64 %indvars.iv33, 1 %lftr.wideiv35 = trunc i64 %indvars.iv.next34 to i32 %exitcond36 = icmp eq i32 %lftr.wideiv35, 100 @@ -81,7 +81,7 @@ if.then: ; preds = %for.body8 %3 = add i64 %indvars.iv, %indvars.iv29 %arrayidx13 = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv29, i64 %indvars.iv %4 = trunc i64 %3 to i32 - store i32 %4, i32* %arrayidx13, align 4, !tbaa !0 + store i32 %4, i32* %arrayidx13, align 4 br label %for.inc14 for.inc14: ; preds = %for.body8, %if.then @@ -106,7 +106,7 @@ for.body3.us.i: ; preds = %for.body3.lr.ph.us. %indvars.iv.i = phi i64 [ 0, %for.body3.lr.ph.us.i ], [ %indvars.iv.next.i, %for.body3.us.i ] %Result.111.us.i = phi i32 [ %Result.014.us.i, %for.body3.lr.ph.us.i ], [ %add.us.i, %for.body3.us.i ] %arrayidx5.us.i = getelementptr inbounds [100 x [100 x i32]]* %Array, i64 0, i64 %indvars.iv16.i, i64 %indvars.iv.i - %5 = load i32* %arrayidx5.us.i, align 4, !tbaa !0 + %5 = load i32* %arrayidx5.us.i, align 4 %add.us.i = add nsw i32 %5, %Result.111.us.i %indvars.iv.next.i = add i64 %indvars.iv.i, 1 %lftr.wideiv = trunc i64 %indvars.iv.next.i to i32 @@ -128,7 +128,3 @@ SumArray.exit: ; preds = %for.inc6.us.i } declare i32 @printf(i8* nocapture, ...) nounwind - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll index 4b6f7b94af4a..f11e332d5fbc 100644 --- a/test/CodeGen/PowerPC/ctrloops.ll +++ b/test/CodeGen/PowerPC/ctrloops.ll @@ -10,9 +10,9 @@ entry: for.body: ; preds = %for.body, %entry %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %0 = load volatile i32* @a, align 4, !tbaa !0 + %0 = load volatile i32* @a, align 4 %add = add nsw i32 %0, %c - store volatile i32 %add, i32* @a, align 4, !tbaa !0 + store volatile i32 %add, i32* @a, align 4 %inc = add nsw i32 %i.01, 1 %exitcond = icmp eq i32 %inc, 2048 br i1 %exitcond, label %for.end, label %for.body @@ -34,9 +34,9 @@ entry: for.body: ; preds = %entry, %for.body %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %0 = load volatile i32* @a, align 4, !tbaa !0 + %0 = load volatile i32* @a, align 4 %add = add nsw i32 %0, %c - store volatile i32 %add, i32* @a, align 4, !tbaa !0 + store volatile i32 %add, i32* @a, align 4 %inc = add nsw i32 %i.02, 1 %exitcond = icmp eq i32 %inc, %d br i1 %exitcond, label %for.end, label %for.body @@ -58,9 +58,9 @@ entry: for.body: ; preds = %entry, %for.body %i.02 = phi i32 [ %inc, %for.body ], [ 0, %entry ] %mul = mul nsw i32 %i.02, %c - %0 = load volatile i32* @a, align 4, !tbaa !0 + %0 = load volatile i32* @a, align 4 %add = add nsw i32 %0, %mul - store volatile i32 %add, i32* @a, align 4, !tbaa !0 + store volatile i32 %add, i32* @a, align 4 %inc = add nsw i32 %i.02, 1 %exitcond = icmp eq i32 %inc, %d br i1 %exitcond, label %for.end, label %for.body @@ -73,7 +73,3 @@ for.end: ; preds = %for.body, %entry ; CHECK-NOT: cmplwi ; CHECK: bdnz } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/early-ret.ll b/test/CodeGen/PowerPC/early-ret.ll new file mode 100644 index 000000000000..7d3e225a1e29 --- /dev/null +++ b/test/CodeGen/PowerPC/early-ret.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @foo(i32* %P) #0 { +entry: + %tobool = icmp eq i32* %P, null + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + store i32 0, i32* %P, align 4 + br label %if.end + +if.end: ; preds = %entry, %if.then + ret void + +; CHECK: @foo +; CHECK: beqlr +; CHECK: blr +} + +define void @bar(i32* %P, i32* %Q) #0 { +entry: + %tobool = icmp eq i32* %P, null + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + store i32 0, i32* %P, align 4 + %tobool1 = icmp eq i32* %Q, null + br i1 %tobool1, label %if.end3, label %if.then2 + +if.then2: ; preds = %if.then + store i32 1, i32* %Q, align 4 + br label %if.end3 + +if.else: ; preds = %entry + store i32 0, i32* %Q, align 4 + br label %if.end3 + +if.end3: ; preds = %if.then, %if.then2, %if.else + ret void + +; CHECK: @bar +; CHECK: beqlr +; CHECK: blr +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/early-ret2.ll b/test/CodeGen/PowerPC/early-ret2.ll new file mode 100644 index 000000000000..a274e2c2658f --- /dev/null +++ b/test/CodeGen/PowerPC/early-ret2.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @_Z8example3iPiS_() #0 { +entry: + br i1 undef, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %entry + br i1 undef, label %while.end, label %while.body + +while.body: ; preds = %while.body, %while.body.lr.ph + br i1 false, label %while.end, label %while.body, !llvm.vectorizer.already_vectorized !0 + +while.end: ; preds = %while.body, %while.body.lr.ph, %entry + ret void + +; CHECK: @_Z8example3iPiS_ +; CHECK: bnelr +} + +attributes #0 = { noinline nounwind } + +!0 = metadata !{} + diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll index 27496f7937e6..a173c9154041 100644 --- a/test/CodeGen/PowerPC/fma.ll +++ b/test/CodeGen/PowerPC/fma.ll @@ -1,22 +1,30 @@ -; RUN: llc < %s -march=ppc32 -fp-contract=fast | \ -; RUN: egrep "fn?madd|fn?msub" | count 8 +; RUN: llc < %s -march=ppc32 -fp-contract=fast | FileCheck %s define double @test_FMADD1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E +; CHECK: test_FMADD1: +; CHECK: fmadd +; CHECK-NEXT: blr } define double @test_FMADD2(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fadd double %D, %C ; <double> [#uses=1] ret double %E +; CHECK: test_FMADD2: +; CHECK: fmadd +; CHECK-NEXT: blr } define double @test_FMSUB(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %D, %C ; <double> [#uses=1] ret double %E +; CHECK: test_FMSUB: +; CHECK: fmsub +; CHECK-NEXT: blr } define double @test_FNMADD1(double %A, double %B, double %C) { @@ -24,6 +32,9 @@ define double @test_FNMADD1(double %A, double %B, double %C) { %E = fadd double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F +; CHECK: test_FNMADD1: +; CHECK: fnmadd +; CHECK-NEXT: blr } define double @test_FNMADD2(double %A, double %B, double %C) { @@ -31,12 +42,18 @@ define double @test_FNMADD2(double %A, double %B, double %C) { %E = fadd double %C, %D ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F +; CHECK: test_FNMADD2: +; CHECK: fnmadd +; CHECK-NEXT: blr } define double @test_FNMSUB1(double %A, double %B, double %C) { %D = fmul double %A, %B ; <double> [#uses=1] %E = fsub double %C, %D ; <double> [#uses=1] ret double %E +; CHECK: test_FNMSUB1: +; CHECK: fnmsub +; CHECK-NEXT: blr } define double @test_FNMSUB2(double %A, double %B, double %C) { @@ -44,6 +61,9 @@ define double @test_FNMSUB2(double %A, double %B, double %C) { %E = fsub double %D, %C ; <double> [#uses=1] %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] ret double %F +; CHECK: test_FNMSUB2: +; CHECK: fnmsub +; CHECK-NEXT: blr } define float @test_FNMSUBS(float %A, float %B, float %C) { @@ -51,4 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) { %E = fsub float %D, %C ; <float> [#uses=1] %F = fsub float -0.000000e+00, %E ; <float> [#uses=1] ret float %F +; CHECK: test_FNMSUBS: +; CHECK: fnmsubs +; CHECK-NEXT: blr } diff --git a/test/CodeGen/PowerPC/fold-zero.ll b/test/CodeGen/PowerPC/fold-zero.ll new file mode 100644 index 000000000000..c7ec6fade53e --- /dev/null +++ b/test/CodeGen/PowerPC/fold-zero.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @test1(i1 %a, i32 %c) nounwind { + %x = select i1 %a, i32 %c, i32 0 + ret i32 %x + +; CHECK: @test1 +; CHECK-NOT: li {{[0-9]+}}, 0 +; CHECK: isel 3, 0, +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/fsel.ll b/test/CodeGen/PowerPC/fsel.ll new file mode 100644 index 000000000000..8cd43e616bf6 --- /dev/null +++ b/test/CodeGen/PowerPC/fsel.ll @@ -0,0 +1,137 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -enable-no-infs-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=CHECK-FM %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define double @zerocmp1(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp ult double %a, 0.000000e+00 + %z.y = select i1 %cmp, double %z, double %y + ret double %z.y + +; CHECK: @zerocmp1 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @zerocmp1 +; CHECK-FM: fsel 1, 1, 2, 3 +; CHECK-FM: blr +} + +define double @zerocmp2(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp ogt double %a, 0.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z + +; CHECK: @zerocmp2 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @zerocmp2 +; CHECK-FM: fneg [[REG:[0-9]+]], 1 +; CHECK-FM: fsel 1, [[REG]], 3, 2 +; CHECK-FM: blr +} + +define double @zerocmp3(double %a, double %y, double %z) #0 { +entry: + %cmp = fcmp oeq double %a, 0.000000e+00 + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z + +; CHECK: @zerocmp3 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @zerocmp3 +; CHECK-FM: fsel [[REG:[0-9]+]], 1, 2, 3 +; CHECK-FM: fneg [[REG2:[0-9]+]], 1 +; CHECK-FM: fsel 1, [[REG2]], [[REG]], 3 +; CHECK-FM: blr +} + +define double @min1(double %a, double %b) #0 { +entry: + %cmp = fcmp ole double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond + +; CHECK: @min1 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @min1 +; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1 +; CHECK-FM: fsel 1, [[REG]], 1, 2 +; CHECK-FM: blr +} + +define double @max1(double %a, double %b) #0 { +entry: + %cmp = fcmp oge double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond + +; CHECK: @max1 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @max1 +; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 +; CHECK-FM: fsel 1, [[REG]], 1, 2 +; CHECK-FM: blr +} + +define double @cmp1(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp ult double %a, %b + %z.y = select i1 %cmp, double %z, double %y + ret double %z.y + +; CHECK: @cmp1 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @cmp1 +; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 +; CHECK-FM: fsel 1, [[REG]], 3, 4 +; CHECK-FM: blr +} + +define double @cmp2(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp ogt double %a, %b + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z + +; CHECK: @cmp2 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @cmp2 +; CHECK-FM: fsub [[REG:[0-9]+]], 2, 1 +; CHECK-FM: fsel 1, [[REG]], 4, 3 +; CHECK-FM: blr +} + +define double @cmp3(double %a, double %b, double %y, double %z) #0 { +entry: + %cmp = fcmp oeq double %a, %b + %y.z = select i1 %cmp, double %y, double %z + ret double %y.z + +; CHECK: @cmp3 +; CHECK-NOT: fsel +; CHECK: blr + +; CHECK-FM: @cmp3 +; CHECK-FM: fsub [[REG:[0-9]+]], 1, 2 +; CHECK-FM: fsel [[REG2:[0-9]+]], [[REG]], 3, 4 +; CHECK-FM: fneg [[REG3:[0-9]+]], [[REG]] +; CHECK-FM: fsel 1, [[REG3]], [[REG2]], 4 +; CHECK-FM: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/ifcvt.ll b/test/CodeGen/PowerPC/ifcvt.ll new file mode 100644 index 000000000000..9c966c95b72d --- /dev/null +++ b/test/CodeGen/PowerPC/ifcvt.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) { +entry: + %sext82 = shl i32 %d, 16 + %conv29 = ashr exact i32 %sext82, 16 + %cmp = icmp slt i32 %sext82, 0 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %sw.epilog + %and33 = and i32 %conv29, 32767 + %sub34 = sub nsw i32 %a, %and33 + br label %cond.end + +cond.false: ; preds = %sw.epilog + %add37 = add nsw i32 %conv29, %a + br label %cond.end + +; CHECK: @test +; CHECK: add [[REG:[0-9]+]], +; CHECK: subf [[REG2:[0-9]+]], +; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]], + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ] + %sext83 = shl i32 %cond, 16 + %conv39 = ashr exact i32 %sext83, 16 + %add41 = sub i32 %b, %a + %sub43 = add i32 %add41, %conv39 + ret i32 %sub43 +} + diff --git a/test/CodeGen/PowerPC/lbzux.ll b/test/CodeGen/PowerPC/lbzux.ll index 98951306fd8e..f3158b32f390 100644 --- a/test/CodeGen/PowerPC/lbzux.ll +++ b/test/CodeGen/PowerPC/lbzux.ll @@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-linux-gnu" define fastcc void @allocateSpace(i1 %cond1, i1 %cond2) nounwind { entry: - %0 = load i8** undef, align 8, !tbaa !0 + %0 = load i8** undef, align 8 br i1 undef, label %return, label %lor.lhs.false lor.lhs.false: ; preds = %entry @@ -43,7 +43,3 @@ return: ; preds = %if.then45, %lor.lhs ; CHECK: @allocateSpace ; CHECK: lbzux } - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/lsa.ll b/test/CodeGen/PowerPC/lsa.ll new file mode 100644 index 000000000000..8a6338ef5a02 --- /dev/null +++ b/test/CodeGen/PowerPC/lsa.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define signext i32 @foo() #0 { +entry: + %v = alloca [8200 x i32], align 4 + %w = alloca [8200 x i32], align 4 + %q = alloca [8200 x i32], align 4 + %0 = bitcast [8200 x i32]* %v to i8* + call void @llvm.lifetime.start(i64 32800, i8* %0) #0 + %1 = bitcast [8200 x i32]* %w to i8* + call void @llvm.lifetime.start(i64 32800, i8* %1) #0 + %2 = bitcast [8200 x i32]* %q to i8* + call void @llvm.lifetime.start(i64 32800, i8* %2) #0 + %arraydecay = getelementptr inbounds [8200 x i32]* %q, i64 0, i64 0 + %arraydecay1 = getelementptr inbounds [8200 x i32]* %v, i64 0, i64 0 + %arraydecay2 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 0 + call void @bar(i32* %arraydecay, i32* %arraydecay1, i32* %arraydecay2) #0 + %3 = load i32* %arraydecay2, align 4 + %arrayidx3 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 1 + %4 = load i32* %arrayidx3, align 4 + +; CHECK: @foo +; CHECK-NOT: lwzx +; CHECK: lwz {{[0-9]+}}, 4([[REG:[0-9]+]]) +; CHECK: lwz {{[0-9]+}}, 0([[REG]]) +; CHECK: blr + + %add = add nsw i32 %4, %3 + call void @llvm.lifetime.end(i64 32800, i8* %2) #0 + call void @llvm.lifetime.end(i64 32800, i8* %1) #0 + call void @llvm.lifetime.end(i64 32800, i8* %0) #0 + ret i32 %add +} + +declare void @llvm.lifetime.start(i64, i8* nocapture) #0 + +declare void @bar(i32*, i32*, i32*) + +declare void @llvm.lifetime.end(i64, i8* nocapture) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/PowerPC/mcm-obj-2.ll b/test/CodeGen/PowerPC/mcm-obj-2.ll index 2dd1718ba75a..bc60b3baf2bb 100644 --- a/test/CodeGen/PowerPC/mcm-obj-2.ll +++ b/test/CodeGen/PowerPC/mcm-obj-2.ll @@ -1,5 +1,5 @@ ; RUN: llc -O1 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: llvm-readobj -r | FileCheck %s ; FIXME: When asm-parse is available, could make this an assembly test. @@ -19,18 +19,11 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing function-scoped variable si. ; -; CHECK: Relocation 0 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]] -; CHECK-NEXT: 'r_type', 0x00000032 -; CHECK: Relocation 1 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM2]] -; CHECK-NEXT: 'r_type', 0x00000030 -; CHECK: Relocation 2 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM2]] -; CHECK-NEXT: 'r_type', 0x00000030 +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] @gi = global i32 5, align 4 @@ -45,18 +38,9 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing file-scope variable gi. ; -; CHECK: Relocation 3 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]] -; CHECK-NEXT: 'r_type', 0x00000032 -; CHECK: Relocation 4 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM3]] -; CHECK-NEXT: 'r_type', 0x00000030 -; CHECK: Relocation 5 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM3]] -; CHECK-NEXT: 'r_type', 0x00000030 +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]] define double @test_double_const() nounwind { entry: @@ -66,12 +50,5 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing a constant. ; -; CHECK: Relocation 6 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]] -; CHECK-NEXT: 'r_type', 0x00000032 -; CHECK: Relocation 7 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM4]] -; CHECK-NEXT: 'r_type', 0x00000030 - +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]] +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]] diff --git a/test/CodeGen/PowerPC/mcm-obj.ll b/test/CodeGen/PowerPC/mcm-obj.ll index 117c3b334346..720c5fb6dd65 100644 --- a/test/CodeGen/PowerPC/mcm-obj.ll +++ b/test/CodeGen/PowerPC/mcm-obj.ll @@ -1,7 +1,7 @@ ; RUN: llc -O0 -mcpu=pwr7 -code-model=medium -filetype=obj %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=MEDIUM %s +; RUN: llvm-readobj -r | FileCheck -check-prefix=MEDIUM %s ; RUN: llc -O0 -mcpu=pwr7 -code-model=large -filetype=obj %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=LARGE %s +; RUN: llvm-readobj -r | FileCheck -check-prefix=LARGE %s ; FIXME: When asm-parse is available, could make this an assembly test. @@ -21,25 +21,15 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing external variable ei. ; -; MEDIUM: '.rela.text' -; MEDIUM: Relocation 0 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 1 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM1]] -; MEDIUM-NEXT: 'r_type', 0x00000040 +; MEDIUM: Relocations [ +; MEDIUM: Section (1) .text { +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] ; -; LARGE: '.rela.text' -; LARGE: Relocation 0 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM1:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 1 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM1]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE: Relocations [ +; LARGE: Section (1) .text { +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM1:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM1]] @test_fn_static.si = internal global i32 0, align 4 @@ -54,26 +44,14 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing function-scoped variable si. ; -; MEDIUM: Relocation 2 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 3 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM2]] -; MEDIUM-NEXT: 'r_type', 0x00000030 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM2]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing function-scoped variable si. ; -; LARGE: Relocation 2 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM2:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 3 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM2]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM2:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM2]] @gi = global i32 5, align 4 @@ -88,26 +66,14 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing file-scope variable gi. ; -; MEDIUM: Relocation 4 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 5 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM3]] -; MEDIUM-NEXT: 'r_type', 0x00000030 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM3]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing file-scope variable gi. ; -; LARGE: Relocation 4 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM3:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 5 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM3]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM3:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM3]] define double @test_double_const() nounwind { entry: @@ -117,26 +83,14 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO for ; accessing a constant. ; -; MEDIUM: Relocation 6 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 7 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM4]] -; MEDIUM-NEXT: 'r_type', 0x00000030 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM4]] ; ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing a constant. ; -; LARGE: Relocation 6 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM4:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 7 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM4]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM4:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM4]] define signext i32 @test_jump_table(i32 signext %i) nounwind { entry: @@ -185,23 +139,11 @@ sw.epilog: ; preds = %sw.bb3, %sw.default ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing a jump table address. ; -; MEDIUM: Relocation 8 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 9 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM5]] -; MEDIUM-NEXT: 'r_type', 0x00000040 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]] ; -; LARGE: Relocation 8 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM5:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 9 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM5]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM5:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM5]] @ti = common global i32 0, align 4 @@ -216,23 +158,11 @@ entry: ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing tentatively declared variable ti. ; -; MEDIUM: Relocation 10 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 11 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM6]] -; MEDIUM-NEXT: 'r_type', 0x00000040 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]] ; -; LARGE: Relocation 10 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM6:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 11 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM6]] -; LARGE-NEXT: 'r_type', 0x00000040 +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]] define i8* @test_fnaddr() nounwind { entry: @@ -248,21 +178,8 @@ declare signext i32 @foo(i32 signext) ; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for ; accessing function address foo. ; -; MEDIUM: Relocation 12 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]] -; MEDIUM-NEXT: 'r_type', 0x00000032 -; MEDIUM: Relocation 13 -; MEDIUM-NEXT: 'r_offset' -; MEDIUM-NEXT: 'r_sym', 0x[[SYM7]] -; MEDIUM-NEXT: 'r_type', 0x00000040 +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]] +; MEDIUM-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]] ; -; LARGE: Relocation 12 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM7:[0-9]+]] -; LARGE-NEXT: 'r_type', 0x00000032 -; LARGE: Relocation 13 -; LARGE-NEXT: 'r_offset' -; LARGE-NEXT: 'r_sym', 0x[[SYM7]] -; LARGE-NEXT: 'r_type', 0x00000040 - +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM7:[^ ]+]] +; LARGE-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM7]] diff --git a/test/CodeGen/PowerPC/optcmp.ll b/test/CodeGen/PowerPC/optcmp.ll new file mode 100644 index 000000000000..523f329303bf --- /dev/null +++ b/test/CodeGen/PowerPC/optcmp.ll @@ -0,0 +1,143 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 -disable-ppc-cmp-opt=0 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 { +entry: + %sub = sub nsw i32 %a, %b + store i32 %sub, i32* %c, align 4, !tbaa !0 + %cmp = icmp sgt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond + +; CHECK: @foo +; CHECK-NOT: subf. +} + +define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 { +entry: + %shl = shl i32 %a, %b + store i32 %shl, i32* %c, align 4, !tbaa !0 + %cmp = icmp sgt i32 %shl, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv + +; CHECK: @foo2 +; CHECK-NOT: slw. +} + +define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %a, %b + store i64 %sub, i64* %c, align 8, !tbaa !3 + %cmp = icmp sgt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @fool +; CHECK: subf. [[REG:[0-9]+]], 4, 3 +; CHECK: isel 3, 3, 4, 1 +; CHECK: std [[REG]], 0(5) +} + +define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %a, %b + store i64 %sub, i64* %c, align 8, !tbaa !3 + %cmp = icmp sle i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @foolb +; CHECK: subf. [[REG:[0-9]+]], 4, 3 +; CHECK: isel 3, 4, 3, 1 +; CHECK: std [[REG]], 0(5) +} + +define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %b, %a + store i64 %sub, i64* %c, align 8, !tbaa !3 + %cmp = icmp sgt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @foolc +; CHECK: subf. [[REG:[0-9]+]], 3, 4 +; CHECK: isel 3, 3, 4, 0 +; CHECK: std [[REG]], 0(5) +} + +define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %b, %a + store i64 %sub, i64* %c, align 8, !tbaa !3 + %cmp = icmp eq i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @foold +; CHECK: subf. [[REG:[0-9]+]], 3, 4 +; CHECK: isel 3, 3, 4, 2 +; CHECK: std [[REG]], 0(5) +} + +define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %sub = sub nsw i64 %a, %b + store i64 %sub, i64* %c, align 8, !tbaa !3 + %cmp = icmp eq i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond + +; CHECK: @foold2 +; CHECK: subf. [[REG:[0-9]+]], 4, 3 +; CHECK: isel 3, 3, 4, 2 +; CHECK: std [[REG]], 0(5) +} + +define i64 @foo2l(i64 %a, i64 %b, i64* nocapture %c) #0 { +entry: + %shl = shl i64 %a, %b + store i64 %shl, i64* %c, align 8, !tbaa !3 + %cmp = icmp sgt i64 %shl, 0 + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 + +; CHECK: @foo2l +; CHECK: sld. 4, 3, 4 +; CHECK: std 4, 0(5) +} + +define double @food(double %a, double %b, double* nocapture %c) #0 { +entry: + %sub = fsub double %a, %b + store double %sub, double* %c, align 8, !tbaa !3 + %cmp = fcmp ogt double %a, %b + %cond = select i1 %cmp, double %a, double %b + ret double %cond + +; CHECK: @food +; CHECK-NOT: fsub. 0, 1, 2 +; CHECK: stfd 0, 0(5) +} + +define float @foof(float %a, float %b, float* nocapture %c) #0 { +entry: + %sub = fsub float %a, %b + store float %sub, float* %c, align 4, !tbaa !3 + %cmp = fcmp ogt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond + +; CHECK: @foof +; CHECK-NOT: fsubs. 0, 1, 2 +; CHECK: stfs 0, 0(5) +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} +!3 = metadata !{metadata !"long", metadata !1} +!4 = metadata !{metadata !"any pointer", metadata !1} + diff --git a/test/CodeGen/PowerPC/pr15359.ll b/test/CodeGen/PowerPC/pr15359.ll index 12fa3e5ffbdd..df02dfcb5c1e 100644 --- a/test/CodeGen/PowerPC/pr15359.ll +++ b/test/CodeGen/PowerPC/pr15359.ll @@ -1,5 +1,5 @@ ; RUN: llc -O0 -mcpu=pwr7 -filetype=obj %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: llvm-readobj -t | FileCheck %s target datalayout = "E-p:64:64:64-S0-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f128:128:128-v64:64:64-v128:128:128-a0:0:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -14,7 +14,9 @@ entry: ; Verify that nextIdx has symbol type TLS. ; -; CHECK: '.symtab' -; CHECK: 'nextIdx' -; CHECK: 'st_type', 0x6 - +; CHECK: Symbol { +; CHECK: Name: nextIdx +; CHECK-NEXT: Value: +; CHECK-NEXT: Size: +; CHECK-NEXT: Binding: +; CHECK-NEXT: Type: TLS diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll index b210a6bda8bf..2b5e1c9a289b 100644 --- a/test/CodeGen/PowerPC/rounding-ops.ll +++ b/test/CodeGen/PowerPC/rounding-ops.ll @@ -107,9 +107,10 @@ define double @test10(double %x) nounwind { declare double @trunc(double) nounwind readnone -define float @test11(float %x) nounwind { +define void @test11(float %x, float* %y) nounwind { %call = tail call float @rintf(float %x) nounwind readnone - ret float %call + store float %call, float* %y + ret void ; CHECK: test11: ; CHECK-NOT: frin @@ -125,9 +126,10 @@ define float @test11(float %x) nounwind { declare float @rintf(float) nounwind readnone -define double @test12(double %x) nounwind { +define void @test12(double %x, double* %y) nounwind { %call = tail call double @rint(double %x) nounwind readnone - ret double %call + store double %call, double* %y + ret void ; CHECK: test12: ; CHECK-NOT: frin diff --git a/test/CodeGen/PowerPC/s000-alias-misched.ll b/test/CodeGen/PowerPC/s000-alias-misched.ll index d03ee8738eea..3570a11b6271 100644 --- a/test/CodeGen/PowerPC/s000-alias-misched.ll +++ b/test/CodeGen/PowerPC/s000-alias-misched.ll @@ -37,34 +37,34 @@ for.body4: ; preds = %for.body4, %for.con %arrayidx = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv %arrayidx6 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv %0 = bitcast double* %arrayidx to <1 x double>* - %1 = load <1 x double>* %0, align 32, !tbaa !0 + %1 = load <1 x double>* %0, align 32 %add = fadd <1 x double> %1, <double 1.000000e+00> %2 = bitcast double* %arrayidx6 to <1 x double>* - store <1 x double> %add, <1 x double>* %2, align 32, !tbaa !0 + store <1 x double> %add, <1 x double>* %2, align 32 %indvars.iv.next.322 = or i64 %indvars.iv, 4 %arrayidx.4 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.322 %arrayidx6.4 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.322 %3 = bitcast double* %arrayidx.4 to <1 x double>* - %4 = load <1 x double>* %3, align 32, !tbaa !0 + %4 = load <1 x double>* %3, align 32 %add.4 = fadd <1 x double> %4, <double 1.000000e+00> %5 = bitcast double* %arrayidx6.4 to <1 x double>* - store <1 x double> %add.4, <1 x double>* %5, align 32, !tbaa !0 + store <1 x double> %add.4, <1 x double>* %5, align 32 %indvars.iv.next.726 = or i64 %indvars.iv, 8 %arrayidx.8 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.726 %arrayidx6.8 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.726 %6 = bitcast double* %arrayidx.8 to <1 x double>* - %7 = load <1 x double>* %6, align 32, !tbaa !0 + %7 = load <1 x double>* %6, align 32 %add.8 = fadd <1 x double> %7, <double 1.000000e+00> %8 = bitcast double* %arrayidx6.8 to <1 x double>* - store <1 x double> %add.8, <1 x double>* %8, align 32, !tbaa !0 + store <1 x double> %add.8, <1 x double>* %8, align 32 %indvars.iv.next.1130 = or i64 %indvars.iv, 12 %arrayidx.12 = getelementptr inbounds [16000 x double]* @Y, i64 0, i64 %indvars.iv.next.1130 %arrayidx6.12 = getelementptr inbounds [16000 x double]* @X, i64 0, i64 %indvars.iv.next.1130 %9 = bitcast double* %arrayidx.12 to <1 x double>* - %10 = load <1 x double>* %9, align 32, !tbaa !0 + %10 = load <1 x double>* %9, align 32 %add.12 = fadd <1 x double> %10, <double 1.000000e+00> %11 = bitcast double* %arrayidx6.12 to <1 x double>* - store <1 x double> %add.12, <1 x double>* %11, align 32, !tbaa !0 + store <1 x double> %add.12, <1 x double>* %11, align 32 %indvars.iv.next.15 = add i64 %indvars.iv, 16 %lftr.wideiv.15 = trunc i64 %indvars.iv.next.15 to i32 %exitcond.15 = icmp eq i32 %lftr.wideiv.15, 16000 @@ -95,7 +95,3 @@ for.end10: ; preds = %for.end declare i64 @clock() nounwind declare signext i32 @dummy(double*, double*, double*, double*, double*, [256 x double]*, [256 x double]*, [256 x double]*, double) - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/stubs.ll b/test/CodeGen/PowerPC/stubs.ll index cfcc50b7a876..694f208198a1 100644 --- a/test/CodeGen/PowerPC/stubs.ll +++ b/test/CodeGen/PowerPC/stubs.ll @@ -6,16 +6,16 @@ entry: } ; CHECK: _test1: -; CHECK: bl ___floatditf$stub +; CHECK: bl L___floatditf$stub ; CHECK: .section __TEXT,__symbol_stub1,symbol_stubs,pure_instructions,16 -; CHECK: ___floatditf$stub: +; CHECK: L___floatditf$stub: ; CHECK: .indirect_symbol ___floatditf -; CHECK: lis r11, ha16(___floatditf$lazy_ptr) -; CHECK: lwzu r12, lo16(___floatditf$lazy_ptr)(r11) +; CHECK: lis r11, ha16(L___floatditf$lazy_ptr) +; CHECK: lwzu r12, lo16(L___floatditf$lazy_ptr)(r11) ; CHECK: mtctr r12 ; CHECK: bctr ; CHECK: .section __DATA,__la_symbol_ptr,lazy_symbol_pointers -; CHECK: ___floatditf$lazy_ptr: +; CHECK: L___floatditf$lazy_ptr: ; CHECK: .indirect_symbol ___floatditf ; CHECK: .long dyld_stub_binding_helper diff --git a/test/CodeGen/PowerPC/stwu-gta.ll b/test/CodeGen/PowerPC/stwu-gta.ll index 4febe7e2fe7e..980c1d502853 100644 --- a/test/CodeGen/PowerPC/stwu-gta.ll +++ b/test/CodeGen/PowerPC/stwu-gta.ll @@ -8,15 +8,11 @@ target triple = "powerpc-unknown-linux" define void @_GLOBAL__I_a() nounwind section ".text.startup" { entry: - store i32 5, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 0), align 4, !tbaa !0 - store i32 6, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 1), align 4, !tbaa !0 + store i32 5, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 0), align 4 + store i32 6, i32* getelementptr inbounds (%class.Two.0.5* @foo, i32 0, i32 1), align 4 ret void } ; CHECK: @_GLOBAL__I_a ; CHECK-NOT: stwux ; CHECK: stwu - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/stwu8.ll b/test/CodeGen/PowerPC/stwu8.ll index e0bd04345439..b220af2df4a4 100644 --- a/test/CodeGen/PowerPC/stwu8.ll +++ b/test/CodeGen/PowerPC/stwu8.ll @@ -14,7 +14,7 @@ entry: %_M_header.i.i.i.i.i.i = getelementptr inbounds %class.spell_checker.21.103.513.538* %this, i64 0, i32 0, i32 0, i32 0, i32 1 %0 = bitcast %"struct.std::_Rb_tree_node_base.17.99.509.534"* %_M_header.i.i.i.i.i.i to i8* call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 40, i32 4, i1 false) nounwind - store %"struct.std::_Rb_tree_node_base.17.99.509.534"* %_M_header.i.i.i.i.i.i, %"struct.std::_Rb_tree_node_base.17.99.509.534"** undef, align 8, !tbaa !0 + store %"struct.std::_Rb_tree_node_base.17.99.509.534"* %_M_header.i.i.i.i.i.i, %"struct.std::_Rb_tree_node_base.17.99.509.534"** undef, align 8 unreachable } @@ -22,7 +22,3 @@ entry: ; CHECK: stwu declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/PowerPC/tls-gd-obj.ll b/test/CodeGen/PowerPC/tls-gd-obj.ll index 00b537d5325b..ffc0db0d14cb 100644 --- a/test/CodeGen/PowerPC/tls-gd-obj.ll +++ b/test/CodeGen/PowerPC/tls-gd-obj.ll @@ -1,5 +1,5 @@ ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: llvm-readobj -r | FileCheck %s ; Test correct relocation generation for thread-local storage using ; the general dynamic model and integrated assembly. @@ -21,21 +21,11 @@ entry: ; and R_PPC64_TLSGD for accessing external variable a, and R_PPC64_REL24 ; for the call to __tls_get_addr. ; -; CHECK: '.rela.text' -; CHECK: Relocation 0 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9a-f]+]] -; CHECK-NEXT: 'r_type', 0x00000052 -; CHECK: Relocation 1 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x00000050 -; CHECK: Relocation 2 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x0000006b -; CHECK: Relocation 3 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x{{[0-9a-f]+}} -; CHECK-NEXT: 'r_type', 0x0000000a - +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_HA a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSGD16_LO a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSGD a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_REL24 __tls_get_addr +; CHECK: } +; CHECK: ] diff --git a/test/CodeGen/PowerPC/tls-ie-obj.ll b/test/CodeGen/PowerPC/tls-ie-obj.ll index 3600cc52ba54..0f7a35295234 100644 --- a/test/CodeGen/PowerPC/tls-ie-obj.ll +++ b/test/CodeGen/PowerPC/tls-ie-obj.ll @@ -1,5 +1,5 @@ ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: llvm-readobj -r | FileCheck %s ; Test correct relocation generation for thread-local storage ; using the initial-exec model and integrated assembly. @@ -20,17 +20,10 @@ entry: ; Verify generation of R_PPC64_GOT_TPREL16_DS and R_PPC64_TLS for ; accessing external variable a. ; -; CHECK: '.rela.text' -; CHECK: Relocation 0 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9a-f]+]] -; CHECK-NEXT: 'r_type', 0x0000005a -; CHECK: Relocation 1 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x00000058 -; CHECK: Relocation 2 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x00000043 - +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLS a +; CHECK: } +; CHECK: ] diff --git a/test/CodeGen/PowerPC/tls-ld-obj.ll b/test/CodeGen/PowerPC/tls-ld-obj.ll index c521ae405f46..29ee87684552 100644 --- a/test/CodeGen/PowerPC/tls-ld-obj.ll +++ b/test/CodeGen/PowerPC/tls-ld-obj.ll @@ -1,5 +1,5 @@ ; RUN: llc -mcpu=pwr7 -O0 -filetype=obj -relocation-model=pic %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s +; RUN: llvm-readobj -r | FileCheck %s ; Test correct relocation generation for thread-local storage using ; the local dynamic model. @@ -22,29 +22,13 @@ entry: ; accessing external variable a, and R_PPC64_REL24 for the call to ; __tls_get_addr. ; -; CHECK: '.rela.text' -; CHECK: Relocation 0 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1:[0-9a-f]+]] -; CHECK-NEXT: 'r_type', 0x00000056 -; CHECK: Relocation 1 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x00000054 -; CHECK: Relocation 2 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x0000006c -; CHECK: Relocation 3 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x{{[0-9a-f]+}} -; CHECK-NEXT: 'r_type', 0x0000000a -; CHECK: Relocation 4 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x0000004d -; CHECK: Relocation 5 -; CHECK-NEXT: 'r_offset' -; CHECK-NEXT: 'r_sym', 0x[[SYM1]] -; CHECK-NEXT: 'r_type', 0x0000004b - +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_HA a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TLSLD16_LO a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_TLSLD a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_REL24 __tls_get_addr +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_HA a +; CHECK: 0x{{[0-9,A-F]+}} R_PPC64_DTPREL16_LO a +; CHECK: } +; CHECK: ] diff --git a/test/CodeGen/R600/README b/test/CodeGen/R600/README new file mode 100644 index 000000000000..96998bba28f2 --- /dev/null +++ b/test/CodeGen/R600/README @@ -0,0 +1,21 @@ ++==============================================================================+ +| How to organize the lit tests | ++==============================================================================+ + +- If you write a test for matching a single DAG opcode or intrinsic, it should + go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll) + +- If you write a test that matches several DAG opcodes and checks for a single + ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g. + bfi_int.ll + +- For all other tests, use your best judgement for organizing tests and naming + the files. + ++==============================================================================+ +| Naming conventions | ++==============================================================================+ + +- Use dash '-' and not underscore '_' to separate words in file names, unless + the file is named after a DAG opcode or ISA instruction that has an + underscore '_' in its name. diff --git a/test/CodeGen/R600/add.v4i32.ll b/test/CodeGen/R600/add.ll index ac4a87417bde..185998b26095 100644 --- a/test/CodeGen/R600/add.v4i32.ll +++ b/test/CodeGen/R600/add.ll @@ -1,9 +1,9 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: ADD_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/alu-split.ll b/test/CodeGen/R600/alu-split.ll index afefcd9f78b0..48496f6febf6 100644 --- a/test/CodeGen/R600/alu-split.ll +++ b/test/CodeGen/R600/alu-split.ll @@ -4,6 +4,7 @@ ;CHECK: ALU ;CHECK: ALU ;CHECK-NOT: ALU +;CHECK: CF_END define void @main() #0 { main_body: diff --git a/test/CodeGen/R600/and.v4i32.ll b/test/CodeGen/R600/and.ll index 662085e2d673..166af2d8d128 100644 --- a/test/CodeGen/R600/and.v4i32.ll +++ b/test/CodeGen/R600/and.ll @@ -1,9 +1,9 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: AND_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: AND_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/bfe_uint.ll b/test/CodeGen/R600/bfe_uint.ll new file mode 100644 index 000000000000..92570c315299 --- /dev/null +++ b/test/CodeGen/R600/bfe_uint.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @bfe_def +; CHECK: BFE_UINT +define void @bfe_def(i32 addrspace(1)* %out, i32 %x) { +entry: + %0 = lshr i32 %x, 5 + %1 = and i32 %0, 15 ; 0xf + store i32 %1, i32 addrspace(1)* %out + ret void +} + +; This program could be implemented using a BFE_UINT instruction, however +; since the lshr constant + number of bits in the mask is >= 32, it can also be +; implmented with a LSHR instruction, which is better, because LSHR has less +; operands and requires less constants. + +; CHECK: @bfe_shift +; CHECK-NOT: BFE_UINT +define void @bfe_shift(i32 addrspace(1)* %out, i32 %x) { +entry: + %0 = lshr i32 %x, 16 + %1 = and i32 %0, 65535 ; 0xffff + store i32 %1, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll new file mode 100644 index 000000000000..4244dcf3c77b --- /dev/null +++ b/test/CodeGen/R600/bfi_int.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s + +; BFI_INT Definition pattern from ISA docs +; (y & x) | (z & ~x) +; +; R600-CHECK: @bfi_def +; R600-CHECK: BFI_INT +; SI-CHECK: @bfi_def +; SI-CHECK: V_BFI_B32 +define void @bfi_def(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { +entry: + %0 = xor i32 %x, -1 + %1 = and i32 %z, %0 + %2 = and i32 %y, %x + %3 = or i32 %1, %2 + store i32 %3, i32 addrspace(1)* %out + ret void +} + +; SHA-256 Ch function +; z ^ (x & (y ^ z)) +; R600-CHECK: @bfi_sha256_ch +; R600-CHECK: BFI_INT +; SI-CHECK: @bfi_sha256_ch +; SI-CHECK: V_BFI_B32 +define void @bfi_sha256_ch(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { +entry: + %0 = xor i32 %y, %z + %1 = and i32 %x, %0 + %2 = xor i32 %z, %1 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; SHA-256 Ma function +; ((x & z) | (y & (x | z))) +; R600-CHECK: @bfi_sha256_ma +; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV.x}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; SI-CHECK: V_XOR_B32_e32 [[DST:VGPR[0-9]+]], {{VGPR[0-9]+, VGPR[0-9]+}} +; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{VGPR[0-9]+, VGPR[0-9]+}} + +define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) { +entry: + %0 = and i32 %x, %z + %1 = or i32 %x, %z + %2 = and i32 %y, %1 + %3 = or i32 %0, %2 + store i32 %3, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/call_fs.ll b/test/CodeGen/R600/call_fs.ll new file mode 100644 index 000000000000..e152bf6d559d --- /dev/null +++ b/test/CodeGen/R600/call_fs.ll @@ -0,0 +1,15 @@ + +; RUN: llc < %s -march=r600 -mcpu=redwood -show-mc-encoding -o - | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=rv710 -show-mc-encoding -o - | FileCheck --check-prefix=R600-CHECK %s + +; EG-CHECK: @call_fs +; EG-CHECK: CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x84] +; R600-CHECK: @call_fs +; R600-CHECK:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89] + + +define void @call_fs() #0 { + ret void +} + +attributes #0 = { "ShaderType"="1" } ; Vertex Shader diff --git a/test/CodeGen/R600/cf_end.ll b/test/CodeGen/R600/cf_end.ll new file mode 100644 index 000000000000..138004df6df9 --- /dev/null +++ b/test/CodeGen/R600/cf_end.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=caicos --show-mc-encoding | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=cayman --show-mc-encoding | FileCheck --check-prefix=CM-CHECK %s + +; EG-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x80] +; CM-CHECK: CF_END ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88] +define void @eop() { + ret void +} diff --git a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll index fd958b365961..6607c1218b56 100644 --- a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll +++ b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll @@ -8,7 +8,7 @@ ; CHECK: @sint -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) { entry: @@ -22,7 +22,7 @@ entry: } ;CHECK: @uint -;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) { entry: diff --git a/test/CodeGen/R600/disconnected-predset-break-bug.ll b/test/CodeGen/R600/disconnected-predset-break-bug.ll index 09baee7a1dcd..012c17b8fe4b 100644 --- a/test/CodeGen/R600/disconnected-predset-break-bug.ll +++ b/test/CodeGen/R600/disconnected-predset-break-bug.ll @@ -6,7 +6,7 @@ ; CHECK: @loop_ge ; CHECK: LOOP_START_DX10 -; CHECK: PRED_SET +; CHECK: ALU_PUSH_BEFORE ; CHECK-NEXT: JUMP ; CHECK-NEXT: LOOP_BREAK define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) nounwind { diff --git a/test/CodeGen/R600/elf.ll b/test/CodeGen/R600/elf.ll new file mode 100644 index 000000000000..f460f13d53e0 --- /dev/null +++ b/test/CodeGen/R600/elf.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=SI -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=SI -o - | FileCheck --check-prefix=CONFIG-CHECK %s + +; ELF-CHECK: Format: ELF32 +; ELF-CHECK: Name: .AMDGPU.config +; ELF-CHECK: Type: SHT_PROGBITS + +; CONFIG-CHECK: .section .AMDGPU.config +; CONFIG-CHECK-NEXT: .long 45096 +; CONFIG-CHECK-NEXT: .long 0 +define void @test(i32 %p) #0 { + %i = add i32 %p, 2 + %r = bitcast i32 %i to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #0 = { "ShaderType"="0" } ; Pixel Shader diff --git a/test/CodeGen/R600/elf.r600.ll b/test/CodeGen/R600/elf.r600.ll new file mode 100644 index 000000000000..0590efb0915f --- /dev/null +++ b/test/CodeGen/R600/elf.r600.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood -filetype=obj | llvm-readobj -s - | FileCheck --check-prefix=ELF-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=redwood -o - | FileCheck --check-prefix=CONFIG-CHECK %s + +; ELF-CHECK: Format: ELF32 +; ELF-CHECK: Name: .AMDGPU.config + +; CONFIG-CHECK: .section .AMDGPU.config +; CONFIG-CHECK-NEXT: .long 166100 +; CONFIG-CHECK-NEXT: .long 258 +; CONFIG-CHECK-NEXT: .long 165900 +; CONFIG-CHECK-NEXT: .long 0 +define void @test(float addrspace(1)* %out, i32 %p) { + %i = add i32 %p, 2 + %r = bitcast i32 %i to float + store float %r, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index 0407533eaa5f..85f2882289fa 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MOV T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}} +;CHECK: MOV * T{{[0-9]+\.[XYZW], \|T[0-9]+\.[XYZW]\|}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index d7d1b6572c41..9a672329e75c 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: @fadd_f32 +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { +define void @fadd_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fadd float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fadd_v4f32 +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fadd <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fadd.v4f32.ll b/test/CodeGen/R600/fadd.v4f32.ll deleted file mode 100644 index 85dbfd52cbb3..000000000000 --- a/test/CodeGen/R600/fadd.v4f32.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 - %a = load <4 x float> addrspace(1) * %in - %b = load <4 x float> addrspace(1) * %b_ptr - %result = fadd <4 x float> %a, %b - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/fcmp-cnd.ll b/test/CodeGen/R600/fcmp-cnd.ll index a94cfb5cf2fe..7373a214790e 100644 --- a/test/CodeGen/R600/fcmp-cnd.ll +++ b/test/CodeGen/R600/fcmp-cnd.ll @@ -2,7 +2,7 @@ ;Not checking arguments 2 and 3 to CNDE, because they may change between ;registers and literal.x depending on what the optimizer does. -;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(i32 addrspace(1)* %out, float addrspace(1)* %in) { entry: diff --git a/test/CodeGen/R600/fcmp.ll b/test/CodeGen/R600/fcmp.ll index 37f621d23958..dc3a779dd609 100644 --- a/test/CodeGen/R600/fcmp.ll +++ b/test/CodeGen/R600/fcmp.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ; CHECK: @fcmp_sext -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fcmp_sext(i32 addrspace(1)* %out, float addrspace(1)* %in) { entry: @@ -19,7 +19,8 @@ entry: ; SET* + FP_TO_SINT ; CHECK: @fcmp_br -; CHECK: SET{{[N]*}}E_DX10 T{{[0-9]+\.[XYZW], [a-zA-Z0-9, .]+}}(5.0 +; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}} +; CHECK-NEXT {{[0-9]+(5.0}} define void @fcmp_br(i32 addrspace(1)* %out, float %in) { entry: diff --git a/test/CodeGen/R600/fdiv.v4f32.ll b/test/CodeGen/R600/fdiv.ll index 79e677f541f5..2e68e36be4d8 100644 --- a/test/CodeGen/R600/fdiv.v4f32.ll +++ b/test/CodeGen/R600/fdiv.ll @@ -1,13 +1,13 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/floor.ll b/test/CodeGen/R600/floor.ll index 845330f28419..877d69a65b43 100644 --- a/test/CodeGen/R600/floor.ll +++ b/test/CodeGen/R600/floor.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: FLOOR T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/fmad.ll b/test/CodeGen/R600/fmad.ll index a3d4d0ff0db7..62001edc3aa5 100644 --- a/test/CodeGen/R600/fmad.ll +++ b/test/CodeGen/R600/fmad.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MULADD_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULADD_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/fmax.ll b/test/CodeGen/R600/fmax.ll index 3708f0b9eed2..8b704e56484b 100644 --- a/test/CodeGen/R600/fmax.ll +++ b/test/CodeGen/R600/fmax.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MAX T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/fmin.ll b/test/CodeGen/R600/fmin.ll index 19d59ab3061e..5e34b7c8902e 100644 --- a/test/CodeGen/R600/fmin.ll +++ b/test/CodeGen/R600/fmin.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MIN T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll index eb1d523c0bb4..c29294632dc0 100644 --- a/test/CodeGen/R600/fmul.ll +++ b/test/CodeGen/R600/fmul.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: @fmul_f32 +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test() { +define void @fmul_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fmul float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fmul_v4f32 +; CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fmul <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fmul.v4f32.ll b/test/CodeGen/R600/fmul.v4f32.ll index 6d44a0c5c782..74a58f74026a 100644 --- a/test/CodeGen/R600/fmul.v4f32.ll +++ b/test/CodeGen/R600/fmul.v4f32.ll @@ -1,9 +1,9 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: MUL_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll new file mode 100644 index 000000000000..f5716e1d47e6 --- /dev/null +++ b/test/CodeGen/R600/fp_to_sint.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @fp_to_sint_v4i32 +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fp_to_sint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %value = load <4 x float> addrspace(1) * %in + %result = fptosi <4 x float> %value to <4 x i32> + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fp_to_uint.ll b/test/CodeGen/R600/fp_to_uint.ll new file mode 100644 index 000000000000..1c3c0c62cf50 --- /dev/null +++ b/test/CodeGen/R600/fp_to_uint.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @fp_to_uint_v4i32 +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: FLT_TO_UINT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fp_to_uint_v4i32(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %value = load <4 x float> addrspace(1) * %in + %result = fptoui <4 x float> %value to <4 x i32> + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 591aa52676a4..f784cde46cd2 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; CHECK: @fsub_f32 +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -define void @test() { +define void @fsub_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fsub float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fsub_v4f32 +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fsub <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/fsub.v4f32.ll b/test/CodeGen/R600/fsub.v4f32.ll deleted file mode 100644 index 612a57e4b609..000000000000 --- a/test/CodeGen/R600/fsub.v4f32.ll +++ /dev/null @@ -1,15 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 - %a = load <4 x float> addrspace(1) * %in - %b = load <4 x float> addrspace(1) * %b_ptr - %result = fsub <4 x float> %a, %b - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/i8_to_double_to_float.ll b/test/CodeGen/R600/i8-to-double-to-float.ll index 39f33227fa4b..604746627666 100644 --- a/test/CodeGen/R600/i8_to_double_to_float.ll +++ b/test/CodeGen/R600/i8-to-double-to-float.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test(float addrspace(1)* %out, i8 addrspace(1)* %in) { %1 = load i8 addrspace(1)* %in diff --git a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll index 71705a64f50e..e3005fe82da1 100644 --- a/test/CodeGen/R600/icmp-select-sete-reverse-args.ll +++ b/test/CodeGen/R600/icmp-select-sete-reverse-args.ll @@ -3,7 +3,7 @@ ;Test that a select with reversed True/False values is correctly lowered ;to a SETNE_INT. There should only be one SETNE_INT instruction. -;CHECK: SETNE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SETNE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;CHECK-NOT: SETNE_INT define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { diff --git a/test/CodeGen/R600/imm.ll b/test/CodeGen/R600/imm.ll new file mode 100644 index 000000000000..979efb00e7bd --- /dev/null +++ b/test/CodeGen/R600/imm.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +; Use a 64-bit value with lo bits that can be represented as an inline constant +; CHECK: @i64_imm_inline_lo +; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5 +; CHECK: V_MOV_B32_e32 [[LO_VGPR:VGPR[0-9]+]], [[LO]] +; CHECK: BUFFER_STORE_DWORDX2 [[LO_VGPR]]_ +define void @i64_imm_inline_lo(i64 addrspace(1) *%out) { +entry: + store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005 + ret void +} + +; Use a 64-bit value with hi bits that can be represented as an inline constant +; CHECK: @i64_imm_inline_hi +; CHECK: S_MOV_B32 [[HI:SGPR[0-9]+]], 5 +; CHECK: V_MOV_B32_e32 [[HI_VGPR:VGPR[0-9]+]], [[HI]] +; CHECK: BUFFER_STORE_DWORDX2 {{VGPR[0-9]+}}_[[HI_VGPR]] +define void @i64_imm_inline_hi(i64 addrspace(1) *%out) { +entry: + store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678 + ret void +} diff --git a/test/CodeGen/R600/jump_address.ll b/test/CodeGen/R600/jump-address.ll index cd35bffb1304..ae9c8bba4fd6 100644 --- a/test/CodeGen/R600/jump_address.ll +++ b/test/CodeGen/R600/jump-address.ll @@ -1,6 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: JUMP @4 +; CHECK: JUMP @3 +; CHECK: EXPORT +; CHECK-NOT: EXPORT define void @main() #0 { main_body: diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll index e69f64e0e142..21e5d4c4de9a 100644 --- a/test/CodeGen/R600/literals.ll +++ b/test/CodeGen/R600/literals.ll @@ -7,7 +7,8 @@ ; ADD_INT literal.x REG, 5 ; CHECK: @i32_literal -; CHECK: ADD_INT {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} 5 +; CHECK: ADD_INT * {{[A-Z0-9,. ]*}}literal.x +; CHECK-NEXT: 5 define void @i32_literal(i32 addrspace(1)* %out, i32 %in) { entry: %0 = add i32 5, %in @@ -22,7 +23,8 @@ entry: ; ADD literal.x REG, 5.0 ; CHECK: @float_literal -; CHECK: ADD {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} {{[0-9]+}}(5.0 +; CHECK: ADD * {{[A-Z0-9,. ]*}}literal.x +; CHECK-NEXT: 1084227584(5.0 define void @float_literal(float addrspace(1)* %out, float %in) { entry: %0 = fadd float 5.0, %in @@ -30,3 +32,168 @@ entry: ret void } +; CHECK: @main +; CHECK: -2147483648 +; CHECK-NEXT-NOT: -2147483648 + +define void @main() #0 { +main_body: + %0 = call float @llvm.R600.load.input(i32 4) + %1 = call float @llvm.R600.load.input(i32 5) + %2 = call float @llvm.R600.load.input(i32 6) + %3 = call float @llvm.R600.load.input(i32 7) + %4 = call float @llvm.R600.load.input(i32 8) + %5 = call float @llvm.R600.load.input(i32 9) + %6 = call float @llvm.R600.load.input(i32 10) + %7 = call float @llvm.R600.load.input(i32 11) + %8 = call float @llvm.R600.load.input(i32 12) + %9 = call float @llvm.R600.load.input(i32 13) + %10 = call float @llvm.R600.load.input(i32 14) + %11 = call float @llvm.R600.load.input(i32 15) + %12 = load <4 x float> addrspace(8)* null + %13 = extractelement <4 x float> %12, i32 0 + %14 = fsub float -0.000000e+00, %13 + %15 = fadd float %0, %14 + %16 = load <4 x float> addrspace(8)* null + %17 = extractelement <4 x float> %16, i32 1 + %18 = fsub float -0.000000e+00, %17 + %19 = fadd float %1, %18 + %20 = load <4 x float> addrspace(8)* null + %21 = extractelement <4 x float> %20, i32 2 + %22 = fsub float -0.000000e+00, %21 + %23 = fadd float %2, %22 + %24 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %25 = extractelement <4 x float> %24, i32 0 + %26 = fmul float %25, %0 + %27 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %28 = extractelement <4 x float> %27, i32 1 + %29 = fmul float %28, %0 + %30 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %31 = extractelement <4 x float> %30, i32 2 + %32 = fmul float %31, %0 + %33 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %34 = extractelement <4 x float> %33, i32 3 + %35 = fmul float %34, %0 + %36 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %37 = extractelement <4 x float> %36, i32 0 + %38 = fmul float %37, %1 + %39 = fadd float %38, %26 + %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %41 = extractelement <4 x float> %40, i32 1 + %42 = fmul float %41, %1 + %43 = fadd float %42, %29 + %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %45 = extractelement <4 x float> %44, i32 2 + %46 = fmul float %45, %1 + %47 = fadd float %46, %32 + %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %49 = extractelement <4 x float> %48, i32 3 + %50 = fmul float %49, %1 + %51 = fadd float %50, %35 + %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %53 = extractelement <4 x float> %52, i32 0 + %54 = fmul float %53, %2 + %55 = fadd float %54, %39 + %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %57 = extractelement <4 x float> %56, i32 1 + %58 = fmul float %57, %2 + %59 = fadd float %58, %43 + %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %61 = extractelement <4 x float> %60, i32 2 + %62 = fmul float %61, %2 + %63 = fadd float %62, %47 + %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %65 = extractelement <4 x float> %64, i32 3 + %66 = fmul float %65, %2 + %67 = fadd float %66, %51 + %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %69 = extractelement <4 x float> %68, i32 0 + %70 = fmul float %69, %3 + %71 = fadd float %70, %55 + %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %73 = extractelement <4 x float> %72, i32 1 + %74 = fmul float %73, %3 + %75 = fadd float %74, %59 + %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %77 = extractelement <4 x float> %76, i32 2 + %78 = fmul float %77, %3 + %79 = fadd float %78, %63 + %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %81 = extractelement <4 x float> %80, i32 3 + %82 = fmul float %81, %3 + %83 = fadd float %82, %67 + %84 = insertelement <4 x float> undef, float %15, i32 0 + %85 = insertelement <4 x float> %84, float %19, i32 1 + %86 = insertelement <4 x float> %85, float %23, i32 2 + %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 3 + %88 = insertelement <4 x float> undef, float %15, i32 0 + %89 = insertelement <4 x float> %88, float %19, i32 1 + %90 = insertelement <4 x float> %89, float %23, i32 2 + %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3 + %92 = call float @llvm.AMDGPU.dp4(<4 x float> %87, <4 x float> %91) + %93 = call float @fabs(float %92) + %94 = call float @llvm.AMDGPU.rsq(float %93) + %95 = fmul float %15, %94 + %96 = fmul float %19, %94 + %97 = fmul float %23, %94 + %98 = insertelement <4 x float> undef, float %4, i32 0 + %99 = insertelement <4 x float> %98, float %5, i32 1 + %100 = insertelement <4 x float> %99, float %6, i32 2 + %101 = insertelement <4 x float> %100, float 0.000000e+00, i32 3 + %102 = insertelement <4 x float> undef, float %4, i32 0 + %103 = insertelement <4 x float> %102, float %5, i32 1 + %104 = insertelement <4 x float> %103, float %6, i32 2 + %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3 + %106 = call float @llvm.AMDGPU.dp4(<4 x float> %101, <4 x float> %105) + %107 = call float @fabs(float %106) + %108 = call float @llvm.AMDGPU.rsq(float %107) + %109 = fmul float %4, %108 + %110 = fmul float %5, %108 + %111 = fmul float %6, %108 + %112 = insertelement <4 x float> undef, float %95, i32 0 + %113 = insertelement <4 x float> %112, float %96, i32 1 + %114 = insertelement <4 x float> %113, float %97, i32 2 + %115 = insertelement <4 x float> %114, float 0.000000e+00, i32 3 + %116 = insertelement <4 x float> undef, float %109, i32 0 + %117 = insertelement <4 x float> %116, float %110, i32 1 + %118 = insertelement <4 x float> %117, float %111, i32 2 + %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3 + %120 = call float @llvm.AMDGPU.dp4(<4 x float> %115, <4 x float> %119) + %121 = fsub float -0.000000e+00, %120 + %122 = fcmp uge float 0.000000e+00, %121 + %123 = select i1 %122, float 0.000000e+00, float %121 + %124 = insertelement <4 x float> undef, float %8, i32 0 + %125 = insertelement <4 x float> %124, float %9, i32 1 + %126 = insertelement <4 x float> %125, float 5.000000e-01, i32 2 + %127 = insertelement <4 x float> %126, float 1.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %127, i32 60, i32 1) + %128 = insertelement <4 x float> undef, float %71, i32 0 + %129 = insertelement <4 x float> %128, float %75, i32 1 + %130 = insertelement <4 x float> %129, float %79, i32 2 + %131 = insertelement <4 x float> %130, float %83, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %131, i32 0, i32 2) + %132 = insertelement <4 x float> undef, float %123, i32 0 + %133 = insertelement <4 x float> %132, float %96, i32 1 + %134 = insertelement <4 x float> %133, float %97, i32 2 + %135 = insertelement <4 x float> %134, float 0.000000e+00, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %135, i32 1, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.R600.load.input(i32) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +; Function Attrs: readonly +declare float @fabs(float) #2 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #1 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } +attributes #2 = { readonly } diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll index 693eb27457c2..cc0732b3fffd 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.mul.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll index fac957f7eeec..ff22a6919677 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.trunc.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.trunc.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: TRUNC T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: TRUNC * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll index bf0cdaa2fa3a..e45722c3fa67 100644 --- a/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll +++ b/test/CodeGen/R600/llvm.SI.fs.interp.constant.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: S_MOV_B32 ;CHECK-NEXT: V_INTERP_MOV_F32 diff --git a/test/CodeGen/R600/llvm.SI.sample.ll b/test/CodeGen/R600/llvm.SI.sample.ll index c724395b98c2..de06354a5646 100644 --- a/test/CodeGen/R600/llvm.SI.sample.ll +++ b/test/CodeGen/R600/llvm.SI.sample.ll @@ -1,21 +1,21 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE_C -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE -;CHECK: IMAGE_SAMPLE +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 15 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 3 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 2 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 1 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 4 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 5 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 9 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+}}, 6 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 10 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+}}, 12 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 7 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 11 +;CHECK: IMAGE_SAMPLE_C {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 13 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+_VGPR[0-9]+_VGPR[0-9]+}}, 14 +;CHECK: IMAGE_SAMPLE {{VGPR[0-9]+}}, 8 define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 @@ -34,54 +34,88 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 - %res1 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v1, + %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1, <8 x i32> undef, <4 x i32> undef, i32 1) - %res2 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v2, + %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2, <8 x i32> undef, <4 x i32> undef, i32 2) - %res3 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v3, + %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3, <8 x i32> undef, <4 x i32> undef, i32 3) - %res4 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v4, + %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4, <8 x i32> undef, <4 x i32> undef, i32 4) - %res5 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v5, + %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5, <8 x i32> undef, <4 x i32> undef, i32 5) - %res6 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v6, + %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6, <8 x i32> undef, <4 x i32> undef, i32 6) - %res7 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v7, + %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7, <8 x i32> undef, <4 x i32> undef, i32 7) - %res8 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v8, + %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8, <8 x i32> undef, <4 x i32> undef, i32 8) - %res9 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v9, + %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9, <8 x i32> undef, <4 x i32> undef, i32 9) - %res10 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v10, + %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10, <8 x i32> undef, <4 x i32> undef, i32 10) - %res11 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v11, + %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11, <8 x i32> undef, <4 x i32> undef, i32 11) - %res12 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v12, + %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12, <8 x i32> undef, <4 x i32> undef, i32 12) - %res13 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v13, + %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13, <8 x i32> undef, <4 x i32> undef, i32 13) - %res14 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v14, + %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14, <8 x i32> undef, <4 x i32> undef, i32 14) - %res15 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v15, + %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15, <8 x i32> undef, <4 x i32> undef, i32 15) - %res16 = call <4 x float> @llvm.SI.sample.(i32 15, <4 x i32> %v16, + %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16, <8 x i32> undef, <4 x i32> undef, i32 16) %e1 = extractelement <4 x float> %res1, i32 0 - %e2 = extractelement <4 x float> %res2, i32 0 - %e3 = extractelement <4 x float> %res3, i32 0 - %e4 = extractelement <4 x float> %res4, i32 0 - %e5 = extractelement <4 x float> %res5, i32 0 - %e6 = extractelement <4 x float> %res6, i32 0 - %e7 = extractelement <4 x float> %res7, i32 0 - %e8 = extractelement <4 x float> %res8, i32 0 - %e9 = extractelement <4 x float> %res9, i32 0 - %e10 = extractelement <4 x float> %res10, i32 0 - %e11 = extractelement <4 x float> %res11, i32 0 - %e12 = extractelement <4 x float> %res12, i32 0 - %e13 = extractelement <4 x float> %res13, i32 0 - %e14 = extractelement <4 x float> %res14, i32 0 - %e15 = extractelement <4 x float> %res15, i32 0 - %e16 = extractelement <4 x float> %res16, i32 0 + %e2 = extractelement <4 x float> %res2, i32 1 + %e3 = extractelement <4 x float> %res3, i32 2 + %e4 = extractelement <4 x float> %res4, i32 3 + %t0 = extractelement <4 x float> %res5, i32 0 + %t1 = extractelement <4 x float> %res5, i32 1 + %e5 = fadd float %t0, %t1 + %t2 = extractelement <4 x float> %res6, i32 0 + %t3 = extractelement <4 x float> %res6, i32 2 + %e6 = fadd float %t2, %t3 + %t4 = extractelement <4 x float> %res7, i32 0 + %t5 = extractelement <4 x float> %res7, i32 3 + %e7 = fadd float %t4, %t5 + %t6 = extractelement <4 x float> %res8, i32 1 + %t7 = extractelement <4 x float> %res8, i32 2 + %e8 = fadd float %t6, %t7 + %t8 = extractelement <4 x float> %res9, i32 1 + %t9 = extractelement <4 x float> %res9, i32 3 + %e9 = fadd float %t8, %t9 + %t10 = extractelement <4 x float> %res10, i32 2 + %t11 = extractelement <4 x float> %res10, i32 3 + %e10 = fadd float %t10, %t11 + %t12 = extractelement <4 x float> %res11, i32 0 + %t13 = extractelement <4 x float> %res11, i32 1 + %t14 = extractelement <4 x float> %res11, i32 2 + %t15 = fadd float %t12, %t13 + %e11 = fadd float %t14, %t15 + %t16 = extractelement <4 x float> %res12, i32 0 + %t17 = extractelement <4 x float> %res12, i32 1 + %t18 = extractelement <4 x float> %res12, i32 3 + %t19 = fadd float %t16, %t17 + %e12 = fadd float %t18, %t19 + %t20 = extractelement <4 x float> %res13, i32 0 + %t21 = extractelement <4 x float> %res13, i32 2 + %t22 = extractelement <4 x float> %res13, i32 3 + %t23 = fadd float %t20, %t21 + %e13 = fadd float %t22, %t23 + %t24 = extractelement <4 x float> %res14, i32 1 + %t25 = extractelement <4 x float> %res14, i32 2 + %t26 = extractelement <4 x float> %res14, i32 3 + %t27 = fadd float %t24, %t25 + %e14 = fadd float %t26, %t27 + %t28 = extractelement <4 x float> %res15, i32 0 + %t29 = extractelement <4 x float> %res15, i32 1 + %t30 = extractelement <4 x float> %res15, i32 2 + %t31 = extractelement <4 x float> %res15, i32 3 + %t32 = fadd float %t28, %t29 + %t33 = fadd float %t30, %t31 + %e15 = fadd float %t32, %t33 + %e16 = extractelement <4 x float> %res16, i32 3 %s1 = fadd float %e1, %e2 %s2 = fadd float %s1, %e3 %s3 = fadd float %s2, %e4 @@ -101,6 +135,6 @@ define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { ret void } -declare <4 x float> @llvm.SI.sample.(i32, <4 x i32>, <8 x i32>, <4 x i32>, i32) readnone +declare <4 x float> @llvm.SI.sample.(<4 x i32>, <8 x i32>, <4 x i32>, i32) readnone declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/llvm.cos.ll b/test/CodeGen/R600/llvm.cos.ll index dc120bfb00c2..9b2816707042 100644 --- a/test/CodeGen/R600/llvm.cos.ll +++ b/test/CodeGen/R600/llvm.cos.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: COS T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: COS * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll index b4ce9f429f16..91b774282906 100644 --- a/test/CodeGen/R600/llvm.pow.ll +++ b/test/CodeGen/R600/llvm.pow.ll @@ -1,8 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: LOG_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;CHECK-NEXT: EXP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/llvm.sin.ll b/test/CodeGen/R600/llvm.sin.ll index 5cd6998c9370..803dc2d6debc 100644 --- a/test/CodeGen/R600/llvm.sin.ll +++ b/test/CodeGen/R600/llvm.sin.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: SIN T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/load.constant_addrspace.f32.ll b/test/CodeGen/R600/load.constant_addrspace.f32.ll deleted file mode 100644 index 93627283bb94..000000000000 --- a/test/CodeGen/R600/load.constant_addrspace.f32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @test(float addrspace(1)* %out, float addrspace(2)* %in) { - %1 = load float addrspace(2)* %in - store float %1, float addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/load.i8.ll b/test/CodeGen/R600/load.i8.ll deleted file mode 100644 index b070dcd52049..000000000000 --- a/test/CodeGen/R600/load.i8.ll +++ /dev/null @@ -1,10 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} - -define void @test(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { - %1 = load i8 addrspace(1)* %in - %2 = zext i8 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll new file mode 100644 index 000000000000..b03245ae87b3 --- /dev/null +++ b/test/CodeGen/R600/load.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; Load an i8 value from the global address space. +; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} + +define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { + %1 = load i8 addrspace(1)* %in + %2 = zext i8 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; Load a f32 value from the constant address space. +; CHECK: VTX_READ_32 T{{[0-9]+\.X, T[0-9]+\.X}} + +define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { + %1 = load float addrspace(2)* %in + store float %1, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/loop-address.ll b/test/CodeGen/R600/loop-address.ll new file mode 100644 index 000000000000..8a5458b89809 --- /dev/null +++ b/test/CodeGen/R600/loop-address.ll @@ -0,0 +1,41 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: TEX +;CHECK: ALU_PUSH +;CHECK: JUMP @4 +;CHECK: ELSE @16 +;CHECK: TEX +;CHECK: LOOP_START_DX10 @15 +;CHECK: LOOP_BREAK @14 +;CHECK: POP @16 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64" +target triple = "r600--" + +define void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 { +entry: + %cmp5 = icmp sgt i32 %iterations, 0 + br i1 %cmp5, label %for.body, label %for.end + +for.body: ; preds = %for.body, %entry + %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ] + %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ] + %i.07 = add nsw i32 %i.07.in, -1 + %arrayidx = getelementptr inbounds i32 addrspace(1)* %out, i32 %ai.06 + store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4 + %add = add nsw i32 %ai.06, 1 + %exitcond = icmp eq i32 %add, %iterations + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + ret void +} + +attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" } + +!opencl.kernels = !{!0, !1, !2, !3} + +!0 = metadata !{void (i32 addrspace(1)*, i32)* @loop_ge} +!1 = metadata !{null} +!2 = metadata !{null} +!3 = metadata !{null} diff --git a/test/CodeGen/R600/lshl.ll b/test/CodeGen/R600/lshl.ll index 423adb9da900..fb698da62719 100644 --- a/test/CodeGen/R600/lshl.ll +++ b/test/CodeGen/R600/lshl.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_LSHLREV_B32_e32 VGPR0, 1, VGPR0 diff --git a/test/CodeGen/R600/lshr.ll b/test/CodeGen/R600/lshr.ll index 551eac1d76bf..e0ed3ac07866 100644 --- a/test/CodeGen/R600/lshr.ll +++ b/test/CodeGen/R600/lshr.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_LSHRREV_B32_e32 VGPR0, 1, VGPR0 diff --git a/test/CodeGen/R600/mul.ll b/test/CodeGen/R600/mul.ll new file mode 100644 index 000000000000..7278e9039840 --- /dev/null +++ b/test/CodeGen/R600/mul.ll @@ -0,0 +1,16 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; mul24 and mad24 are affected +;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: MULLO_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr + %result = mul <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/mulhu.ll b/test/CodeGen/R600/mulhu.ll index 28744e00c3cf..bc17a597873e 100644 --- a/test/CodeGen/R600/mulhu.ll +++ b/test/CodeGen/R600/mulhu.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_MOV_B32_e32 VGPR1, -1431655765 ;CHECK-NEXT: V_MUL_HI_U32 VGPR0, VGPR0, VGPR1, 0, 0, 0, 0, 0 diff --git a/test/CodeGen/R600/or.ll b/test/CodeGen/R600/or.ll new file mode 100644 index 000000000000..b0dbb021e822 --- /dev/null +++ b/test/CodeGen/R600/or.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @or_v4i32 +; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: OR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = or <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/predicates.ll b/test/CodeGen/R600/predicates.ll index eb8b052b6f72..0d3eeef26307 100644 --- a/test/CodeGen/R600/predicates.ll +++ b/test/CodeGen/R600/predicates.ll @@ -4,8 +4,8 @@ ; when it is legal to do so. ; CHECK: @simple_if -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, -; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel define void @simple_if(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 @@ -22,9 +22,9 @@ ENDIF: } ; CHECK: @simple_if_else -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel define void @simple_if_else(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 @@ -46,11 +46,11 @@ ENDIF: ; CHECK: @nested_if ; CHECK: ALU_PUSH_BEFORE -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec ; CHECK: JUMP -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, -; CHECK: LSHL T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel ; CHECK: POP +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel define void @nested_if(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 @@ -73,12 +73,12 @@ ENDIF: ; CHECK: @nested_if_else ; CHECK: ALU_PUSH_BEFORE -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Exec ; CHECK: JUMP -; CHECK: PRED_SET{{[EGN][ET]*}}_INT Pred, -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel -; CHECK: LSH{{[LR] T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, 0(0.000000e+00) Pred_sel ; CHECK: POP +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec +; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel +; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel define void @nested_if_else(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sgt i32 %in, 0 diff --git a/test/CodeGen/R600/pv.ll b/test/CodeGen/R600/pv.ll new file mode 100644 index 000000000000..37c3d9d7d6d1 --- /dev/null +++ b/test/CodeGen/R600/pv.ll @@ -0,0 +1,244 @@ +; RUN: llc < %s -march=r600 | FileCheck %s + +;CHECK: DOT4 * T{{[0-9]\.W}} (MASKED) +;CHECK-NEXT: CNDGE T{{[0-9].[XYZW]}}, PV.x + +define void @main() #0 { +main_body: + %0 = call float @llvm.R600.load.input(i32 4) + %1 = call float @llvm.R600.load.input(i32 5) + %2 = call float @llvm.R600.load.input(i32 6) + %3 = call float @llvm.R600.load.input(i32 7) + %4 = call float @llvm.R600.load.input(i32 8) + %5 = call float @llvm.R600.load.input(i32 9) + %6 = call float @llvm.R600.load.input(i32 10) + %7 = call float @llvm.R600.load.input(i32 11) + %8 = call float @llvm.R600.load.input(i32 12) + %9 = call float @llvm.R600.load.input(i32 13) + %10 = call float @llvm.R600.load.input(i32 14) + %11 = call float @llvm.R600.load.input(i32 15) + %12 = call float @llvm.R600.load.input(i32 16) + %13 = call float @llvm.R600.load.input(i32 17) + %14 = call float @llvm.R600.load.input(i32 18) + %15 = call float @llvm.R600.load.input(i32 19) + %16 = call float @llvm.R600.load.input(i32 20) + %17 = call float @llvm.R600.load.input(i32 21) + %18 = call float @llvm.R600.load.input(i32 22) + %19 = call float @llvm.R600.load.input(i32 23) + %20 = call float @llvm.R600.load.input(i32 24) + %21 = call float @llvm.R600.load.input(i32 25) + %22 = call float @llvm.R600.load.input(i32 26) + %23 = call float @llvm.R600.load.input(i32 27) + %24 = call float @llvm.R600.load.input(i32 28) + %25 = call float @llvm.R600.load.input(i32 29) + %26 = call float @llvm.R600.load.input(i32 30) + %27 = call float @llvm.R600.load.input(i32 31) + %28 = load <4 x float> addrspace(8)* null + %29 = extractelement <4 x float> %28, i32 0 + %30 = fmul float %0, %29 + %31 = load <4 x float> addrspace(8)* null + %32 = extractelement <4 x float> %31, i32 1 + %33 = fmul float %0, %32 + %34 = load <4 x float> addrspace(8)* null + %35 = extractelement <4 x float> %34, i32 2 + %36 = fmul float %0, %35 + %37 = load <4 x float> addrspace(8)* null + %38 = extractelement <4 x float> %37, i32 3 + %39 = fmul float %0, %38 + %40 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %41 = extractelement <4 x float> %40, i32 0 + %42 = fmul float %1, %41 + %43 = fadd float %42, %30 + %44 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %45 = extractelement <4 x float> %44, i32 1 + %46 = fmul float %1, %45 + %47 = fadd float %46, %33 + %48 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %49 = extractelement <4 x float> %48, i32 2 + %50 = fmul float %1, %49 + %51 = fadd float %50, %36 + %52 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %53 = extractelement <4 x float> %52, i32 3 + %54 = fmul float %1, %53 + %55 = fadd float %54, %39 + %56 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %57 = extractelement <4 x float> %56, i32 0 + %58 = fmul float %2, %57 + %59 = fadd float %58, %43 + %60 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %61 = extractelement <4 x float> %60, i32 1 + %62 = fmul float %2, %61 + %63 = fadd float %62, %47 + %64 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %65 = extractelement <4 x float> %64, i32 2 + %66 = fmul float %2, %65 + %67 = fadd float %66, %51 + %68 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %69 = extractelement <4 x float> %68, i32 3 + %70 = fmul float %2, %69 + %71 = fadd float %70, %55 + %72 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %73 = extractelement <4 x float> %72, i32 0 + %74 = fmul float %3, %73 + %75 = fadd float %74, %59 + %76 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %77 = extractelement <4 x float> %76, i32 1 + %78 = fmul float %3, %77 + %79 = fadd float %78, %63 + %80 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %81 = extractelement <4 x float> %80, i32 2 + %82 = fmul float %3, %81 + %83 = fadd float %82, %67 + %84 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %85 = extractelement <4 x float> %84, i32 3 + %86 = fmul float %3, %85 + %87 = fadd float %86, %71 + %88 = insertelement <4 x float> undef, float %4, i32 0 + %89 = insertelement <4 x float> %88, float %5, i32 1 + %90 = insertelement <4 x float> %89, float %6, i32 2 + %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 3 + %92 = insertelement <4 x float> undef, float %4, i32 0 + %93 = insertelement <4 x float> %92, float %5, i32 1 + %94 = insertelement <4 x float> %93, float %6, i32 2 + %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 3 + %96 = call float @llvm.AMDGPU.dp4(<4 x float> %91, <4 x float> %95) + %97 = call float @fabs(float %96) + %98 = call float @llvm.AMDGPU.rsq(float %97) + %99 = fmul float %4, %98 + %100 = fmul float %5, %98 + %101 = fmul float %6, %98 + %102 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %103 = extractelement <4 x float> %102, i32 0 + %104 = fmul float %103, %8 + %105 = fadd float %104, %20 + %106 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %107 = extractelement <4 x float> %106, i32 1 + %108 = fmul float %107, %9 + %109 = fadd float %108, %21 + %110 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %111 = extractelement <4 x float> %110, i32 2 + %112 = fmul float %111, %10 + %113 = fadd float %112, %22 + %114 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00) + %115 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00) + %116 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00) + %117 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) + %118 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %119 = extractelement <4 x float> %118, i32 0 + %120 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %121 = extractelement <4 x float> %120, i32 1 + %122 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %123 = extractelement <4 x float> %122, i32 2 + %124 = insertelement <4 x float> undef, float %99, i32 0 + %125 = insertelement <4 x float> %124, float %100, i32 1 + %126 = insertelement <4 x float> %125, float %101, i32 2 + %127 = insertelement <4 x float> %126, float 0.000000e+00, i32 3 + %128 = insertelement <4 x float> undef, float %119, i32 0 + %129 = insertelement <4 x float> %128, float %121, i32 1 + %130 = insertelement <4 x float> %129, float %123, i32 2 + %131 = insertelement <4 x float> %130, float 0.000000e+00, i32 3 + %132 = call float @llvm.AMDGPU.dp4(<4 x float> %127, <4 x float> %131) + %133 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %134 = extractelement <4 x float> %133, i32 0 + %135 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %136 = extractelement <4 x float> %135, i32 1 + %137 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %138 = extractelement <4 x float> %137, i32 2 + %139 = insertelement <4 x float> undef, float %99, i32 0 + %140 = insertelement <4 x float> %139, float %100, i32 1 + %141 = insertelement <4 x float> %140, float %101, i32 2 + %142 = insertelement <4 x float> %141, float 0.000000e+00, i32 3 + %143 = insertelement <4 x float> undef, float %134, i32 0 + %144 = insertelement <4 x float> %143, float %136, i32 1 + %145 = insertelement <4 x float> %144, float %138, i32 2 + %146 = insertelement <4 x float> %145, float 0.000000e+00, i32 3 + %147 = call float @llvm.AMDGPU.dp4(<4 x float> %142, <4 x float> %146) + %148 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %149 = extractelement <4 x float> %148, i32 0 + %150 = fmul float %149, %8 + %151 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %152 = extractelement <4 x float> %151, i32 1 + %153 = fmul float %152, %9 + %154 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %155 = extractelement <4 x float> %154, i32 2 + %156 = fmul float %155, %10 + %157 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %158 = extractelement <4 x float> %157, i32 0 + %159 = fmul float %158, %12 + %160 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %161 = extractelement <4 x float> %160, i32 1 + %162 = fmul float %161, %13 + %163 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %164 = extractelement <4 x float> %163, i32 2 + %165 = fmul float %164, %14 + %166 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %167 = extractelement <4 x float> %166, i32 0 + %168 = fmul float %167, %16 + %169 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %170 = extractelement <4 x float> %169, i32 1 + %171 = fmul float %170, %17 + %172 = load <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %173 = extractelement <4 x float> %172, i32 2 + %174 = fmul float %173, %18 + %175 = fcmp uge float %132, 0.000000e+00 + %176 = select i1 %175, float %132, float 0.000000e+00 + %177 = fcmp uge float %147, 0.000000e+00 + %178 = select i1 %177, float %147, float 0.000000e+00 + %179 = call float @llvm.pow.f32(float %178, float %24) + %180 = fcmp ult float %132, 0.000000e+00 + %181 = select i1 %180, float 0.000000e+00, float %179 + %182 = fadd float %150, %105 + %183 = fadd float %153, %109 + %184 = fadd float %156, %113 + %185 = fmul float %176, %159 + %186 = fadd float %185, %182 + %187 = fmul float %176, %162 + %188 = fadd float %187, %183 + %189 = fmul float %176, %165 + %190 = fadd float %189, %184 + %191 = fmul float %181, %168 + %192 = fadd float %191, %186 + %193 = fmul float %181, %171 + %194 = fadd float %193, %188 + %195 = fmul float %181, %174 + %196 = fadd float %195, %190 + %197 = call float @llvm.AMDIL.clamp.(float %192, float 0.000000e+00, float 1.000000e+00) + %198 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00) + %199 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00) + %200 = insertelement <4 x float> undef, float %75, i32 0 + %201 = insertelement <4 x float> %200, float %79, i32 1 + %202 = insertelement <4 x float> %201, float %83, i32 2 + %203 = insertelement <4 x float> %202, float %87, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %203, i32 60, i32 1) + %204 = insertelement <4 x float> undef, float %197, i32 0 + %205 = insertelement <4 x float> %204, float %198, i32 1 + %206 = insertelement <4 x float> %205, float %199, i32 2 + %207 = insertelement <4 x float> %206, float %117, i32 3 + call void @llvm.R600.store.swizzle(<4 x float> %207, i32 0, i32 2) + ret void +} + +; Function Attrs: readnone +declare float @llvm.R600.load.input(i32) #1 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 + +; Function Attrs: readonly +declare float @fabs(float) #2 + +; Function Attrs: readnone +declare float @llvm.AMDGPU.rsq(float) #1 + +; Function Attrs: readnone +declare float @llvm.AMDIL.clamp.(float, float, float) #1 + +; Function Attrs: nounwind readonly +declare float @llvm.pow.f32(float, float) #3 + +declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) + +attributes #0 = { "ShaderType"="1" } +attributes #1 = { readnone } +attributes #2 = { readonly } +attributes #3 = { nounwind readonly } diff --git a/test/CodeGen/R600/r600-encoding.ll b/test/CodeGen/R600/r600-encoding.ll new file mode 100644 index 000000000000..c8040a1b4cd5 --- /dev/null +++ b/test/CodeGen/R600/r600-encoding.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600-CHECK %s + +; The earliest R600 GPUs have a slightly different encoding than the rest of +; the VLIW4/5 GPUs. + +; EG-CHECK: @test +; EG-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}] + +; R600-CHECK: @test +; R600-CHECK: MUL_IEEE {{[ *TXYZW.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] + +define void @test() { +entry: + %0 = call float @llvm.R600.load.input(i32 0) + %1 = call float @llvm.R600.load.input(i32 1) + %2 = fmul float %0, %1 + call void @llvm.AMDGPU.store.output(float %2, i32 0) + ret void +} + +declare float @llvm.R600.load.input(i32) readnone + +declare void @llvm.AMDGPU.store.output(float, i32) diff --git a/test/CodeGen/R600/reciprocal.ll b/test/CodeGen/R600/reciprocal.ll index 6838c1ae3662..27839296703f 100644 --- a/test/CodeGen/R600/reciprocal.ll +++ b/test/CodeGen/R600/reciprocal.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -;CHECK: RECIP_IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @test() { %r0 = call float @llvm.R600.load.input(i32 0) diff --git a/test/CodeGen/R600/sdiv.ll b/test/CodeGen/R600/sdiv.ll index 3556facfbab3..3dd10c8a61c1 100644 --- a/test/CodeGen/R600/sdiv.ll +++ b/test/CodeGen/R600/sdiv.ll @@ -9,7 +9,7 @@ ; This was fixed by adding an additional pattern in R600Instructions.td to ; match this pattern with a CNDGE_INT. -; CHECK: RETURN +; CHECK: CF_END define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32 addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/selectcc_cnde.ll b/test/CodeGen/R600/selectcc-cnd.ll index f0a0f512ba15..d7287b487896 100644 --- a/test/CodeGen/R600/selectcc_cnde.ll +++ b/test/CodeGen/R600/selectcc-cnd.ll @@ -1,7 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK-NOT: SETE -;CHECK: CNDE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1.0, literal.x, [-0-9]+\(2.0}} +;CHECK: CNDE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1.0, literal.x, +;CHECK-NEXT: {{[-0-9]+\(2.0}} define void @test(float addrspace(1)* %out, float addrspace(1)* %in) { %1 = load float addrspace(1)* %in %2 = fcmp oeq float %1, 0.0 diff --git a/test/CodeGen/R600/selectcc_cnde_int.ll b/test/CodeGen/R600/selectcc-cnde-int.ll index b38078e26db6..768dc7dbf418 100644 --- a/test/CodeGen/R600/selectcc_cnde_int.ll +++ b/test/CodeGen/R600/selectcc-cnde-int.ll @@ -1,7 +1,8 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s ;CHECK-NOT: SETE_INT -;CHECK: CNDE_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], 1, literal.x, 2}} +;CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, literal.x, +;CHECK-NEXT: 2 define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %1 = load i32 addrspace(1)* %in %2 = icmp eq i32 %1, 0 diff --git a/test/CodeGen/R600/selectcc-icmp-select-float.ll b/test/CodeGen/R600/selectcc-icmp-select-float.ll index 359ca1e6f8ce..6743800490b3 100644 --- a/test/CodeGen/R600/selectcc-icmp-select-float.ll +++ b/test/CodeGen/R600/selectcc-icmp-select-float.ll @@ -2,7 +2,8 @@ ; Note additional optimizations may cause this SGT to be replaced with a ; CND* instruction. -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], literal.x, -1}} +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: -1 ; Test a selectcc with i32 LHS/RHS and float True/False define void @test(float addrspace(1)* %out, i32 addrspace(1)* %in) { diff --git a/test/CodeGen/R600/set-dx10.ll b/test/CodeGen/R600/set-dx10.ll index 54febcf0e68e..eb6e9d2f2ba5 100644 --- a/test/CodeGen/R600/set-dx10.ll +++ b/test/CodeGen/R600/set-dx10.ll @@ -5,7 +5,8 @@ ; SET*DX10 instructions. ; CHECK: @fcmp_une_select_fptosi -; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_une_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp une float %in, 5.0 @@ -17,7 +18,8 @@ entry: } ; CHECK: @fcmp_une_select_i32 -; CHECK: SETNE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETNE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_une_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp une float %in, 5.0 @@ -27,7 +29,8 @@ entry: } ; CHECK: @fcmp_ueq_select_fptosi -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ueq_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ueq float %in, 5.0 @@ -39,7 +42,8 @@ entry: } ; CHECK: @fcmp_ueq_select_i32 -; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ueq_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ueq float %in, 5.0 @@ -49,7 +53,8 @@ entry: } ; CHECK: @fcmp_ugt_select_fptosi -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ugt_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ugt float %in, 5.0 @@ -61,7 +66,8 @@ entry: } ; CHECK: @fcmp_ugt_select_i32 -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ugt_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ugt float %in, 5.0 @@ -71,7 +77,8 @@ entry: } ; CHECK: @fcmp_uge_select_fptosi -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_uge_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp uge float %in, 5.0 @@ -83,7 +90,8 @@ entry: } ; CHECK: @fcmp_uge_select_i32 -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, 1084227584(5.000000e+00) +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, T{{[0-9]+\.[XYZW]}}, literal.x, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_uge_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp uge float %in, 5.0 @@ -93,7 +101,8 @@ entry: } ; CHECK: @fcmp_ule_select_fptosi -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ule_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 @@ -105,7 +114,8 @@ entry: } ; CHECK: @fcmp_ule_select_i32 -; CHECK: SETGE_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGE_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ule_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 @@ -115,7 +125,8 @@ entry: } ; CHECK: @fcmp_ult_select_fptosi -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ult_select_fptosi(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 @@ -127,7 +138,8 @@ entry: } ; CHECK: @fcmp_ult_select_i32 -; CHECK: SETGT_DX10 T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGT_DX10 * T{{[0-9]+\.[XYZW]}}, literal.x, T{{[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @fcmp_ult_select_i32(i32 addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 diff --git a/test/CodeGen/R600/setcc.v4i32.ll b/test/CodeGen/R600/setcc.ll index 0752f2e63dbf..0752f2e63dbf 100644 --- a/test/CodeGen/R600/setcc.v4i32.ll +++ b/test/CodeGen/R600/setcc.ll diff --git a/test/CodeGen/R600/seto.ll b/test/CodeGen/R600/seto.ll index 5ab4b87d570c..4622203ffdbc 100644 --- a/test/CodeGen/R600/seto.ll +++ b/test/CodeGen/R600/seto.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_CMP_O_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 diff --git a/test/CodeGen/R600/setuo.ll b/test/CodeGen/R600/setuo.ll index 320835576d41..0bf5801b1c33 100644 --- a/test/CodeGen/R600/setuo.ll +++ b/test/CodeGen/R600/setuo.ll @@ -1,4 +1,4 @@ -;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s ;CHECK: V_CMP_U_F32_e64 SGPR0_SGPR1, VGPR0, VGPR0, 0, 0, 0, 0 diff --git a/test/CodeGen/R600/shl.ll b/test/CodeGen/R600/shl.ll new file mode 100644 index 000000000000..43cc1e26fc01 --- /dev/null +++ b/test/CodeGen/R600/shl.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @shl_v4i32 +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = shl <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/sint_to_fp.ll b/test/CodeGen/R600/sint_to_fp.ll new file mode 100644 index 000000000000..91a8eb7f57b4 --- /dev/null +++ b/test/CodeGen/R600/sint_to_fp.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @sint_to_fp_v4i32 +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: INT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @sint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %value = load <4 x i32> addrspace(1) * %in + %result = sitofp <4 x i32> %value to <4 x float> + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll new file mode 100644 index 000000000000..972542d346f4 --- /dev/null +++ b/test/CodeGen/R600/sra.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @ashr_v4i32 +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ASHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = ashr <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/srl.ll b/test/CodeGen/R600/srl.ll new file mode 100644 index 000000000000..5f63600b75f0 --- /dev/null +++ b/test/CodeGen/R600/srl.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @lshr_v4i32 +; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: LSHR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = lshr <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll new file mode 100644 index 000000000000..4d673f3ea326 --- /dev/null +++ b/test/CodeGen/R600/store.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s +; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s + +; floating-point store +; EG-CHECK: @store_f32 +; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; SI-CHECK: @store_f32 +; SI-CHECK: BUFFER_STORE_DWORD + +define void @store_f32(float addrspace(1)* %out, float %in) { + store float %in, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/store.r600.ll b/test/CodeGen/R600/store.r600.ll new file mode 100644 index 000000000000..5ffb7f1809f8 --- /dev/null +++ b/test/CodeGen/R600/store.r600.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s + +; XXX: Merge this test into store.ll once it is supported on SI + +; v4i32 store +; EG-CHECK: @store_v4i32 +; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 + +define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %1 = load <4 x i32> addrspace(1) * %in + store <4 x i32> %1, <4 x i32> addrspace(1)* %out + ret void +} + +; v4f32 store +; EG-CHECK: @store_v4f32 +; EG-CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 +define void @store_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %1 = load <4 x float> addrspace(1) * %in + store <4 x float> %1, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/store.v4f32.ll b/test/CodeGen/R600/store.v4f32.ll deleted file mode 100644 index 8b0d24445971..000000000000 --- a/test/CodeGen/R600/store.v4f32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %1 = load <4 x float> addrspace(1) * %in - store <4 x float> %1, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/store.v4i32.ll b/test/CodeGen/R600/store.v4i32.ll deleted file mode 100644 index a659815ddeba..000000000000 --- a/test/CodeGen/R600/store.v4i32.ll +++ /dev/null @@ -1,9 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: RAT_WRITE_CACHELESS_128 T{{[0-9]+\.XYZW, T[0-9]+\.X}}, 1 - -define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %1 = load <4 x i32> addrspace(1) * %in - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll new file mode 100644 index 000000000000..12bfba39753e --- /dev/null +++ b/test/CodeGen/R600/sub.ll @@ -0,0 +1,15 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 + %a = load <4 x i32> addrspace(1) * %in + %b = load <4 x i32> addrspace(1) * %b_ptr + %result = sub <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/udiv.v4i32.ll b/test/CodeGen/R600/udiv.ll index 47657a6be75e..b81e3667ce89 100644 --- a/test/CodeGen/R600/udiv.v4i32.ll +++ b/test/CodeGen/R600/udiv.ll @@ -3,7 +3,7 @@ ;The code generated by udiv is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets ;a v4i32 udiv -;CHECK: RETURN +;CHECK: CF_END define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/uint_to_fp.ll b/test/CodeGen/R600/uint_to_fp.ll new file mode 100644 index 000000000000..9054fc4c2cc8 --- /dev/null +++ b/test/CodeGen/R600/uint_to_fp.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @uint_to_fp_v4i32 +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: UINT_TO_FLT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @uint_to_fp_v4i32(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %value = load <4 x i32> addrspace(1) * %in + %result = uitofp <4 x i32> %value to <4 x float> + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/unsupported-cc.ll b/test/CodeGen/R600/unsupported-cc.ll index b48c59151831..b311f4cfa7f9 100644 --- a/test/CodeGen/R600/unsupported-cc.ll +++ b/test/CodeGen/R600/unsupported-cc.ll @@ -3,7 +3,8 @@ ; These tests are for condition codes that are not supported by the hardware ; CHECK: @slt -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 5(7.006492e-45) +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 5(7.006492e-45) define void @slt(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp slt i32 %in, 5 @@ -13,7 +14,8 @@ entry: } ; CHECK: @ult_i32 -; CHECK: SETGT_UINT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 5(7.006492e-45) +; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 5(7.006492e-45) define void @ult_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp ult i32 %in, 5 @@ -23,7 +25,8 @@ entry: } ; CHECK: @ult_float -; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @ult_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ult float %in, 5.0 @@ -33,7 +36,8 @@ entry: } ; CHECK: @olt -; CHECK: SETGT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +;CHECK-NEXT: 1084227584(5.000000e+00) define void @olt(float addrspace(1)* %out, float %in) { entry: %0 = fcmp olt float %in, 5.0 @@ -43,7 +47,8 @@ entry: } ; CHECK: @sle -; CHECK: SETGT_INT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 6(8.407791e-45) +; CHECK: SETGT_INT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 6(8.407791e-45) define void @sle(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp sle i32 %in, 5 @@ -53,7 +58,8 @@ entry: } ; CHECK: @ule_i32 -; CHECK: SETGT_UINT T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 6(8.407791e-45) +; CHECK: SETGT_UINT * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 6(8.407791e-45) define void @ule_i32(i32 addrspace(1)* %out, i32 %in) { entry: %0 = icmp ule i32 %in, 5 @@ -63,7 +69,8 @@ entry: } ; CHECK: @ule_float -; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT: 1084227584(5.000000e+00) define void @ule_float(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ule float %in, 5.0 @@ -73,7 +80,8 @@ entry: } ; CHECK: @ole -; CHECK: SETGE T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, 1084227584(5.000000e+00) +; CHECK: SETGE * T{{[0-9]+\.[XYZW]}}, literal.x, {{T[0-9]+\.[XYZW]}}, +; CHECK-NEXT:1084227584(5.000000e+00) define void @ole(float addrspace(1)* %out, float %in) { entry: %0 = fcmp ole float %in, 5.0 diff --git a/test/CodeGen/R600/urecip.ll b/test/CodeGen/R600/urecip.ll new file mode 100644 index 000000000000..dad02dd76f0a --- /dev/null +++ b/test/CodeGen/R600/urecip.ll @@ -0,0 +1,12 @@ +;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s + +;CHECK: V_RCP_IFLAG_F32_e32 + +define void @test(i32 %p, i32 %q) { + %i = udiv i32 %p, %q + %r = bitcast i32 %i to float + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) + ret void +} + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/R600/urem.v4i32.ll b/test/CodeGen/R600/urem.ll index 2e7388caa6ce..a2cc0bd2e84e 100644 --- a/test/CodeGen/R600/urem.v4i32.ll +++ b/test/CodeGen/R600/urem.ll @@ -3,7 +3,7 @@ ;The code generated by urem is long and complex and may frequently change. ;The goal of this test is to make sure the ISel doesn't fail when it gets ;a v4i32 urem -;CHECK: RETURN +;CHECK: CF_END define void @test(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 diff --git a/test/CodeGen/R600/vec4-expand.ll b/test/CodeGen/R600/vec4-expand.ll deleted file mode 100644 index 8f62bc692908..000000000000 --- a/test/CodeGen/R600/vec4-expand.ll +++ /dev/null @@ -1,53 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; CHECK: @fp_to_sint -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fp_to_sint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %value = load <4 x float> addrspace(1) * %in - %result = fptosi <4 x float> %value to <4 x i32> - store <4 x i32> %result, <4 x i32> addrspace(1)* %out - ret void -} - -; CHECK: @fp_to_uint -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @fp_to_uint(<4 x i32> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %value = load <4 x float> addrspace(1) * %in - %result = fptoui <4 x float> %value to <4 x i32> - store <4 x i32> %result, <4 x i32> addrspace(1)* %out - ret void -} - -; CHECK: @sint_to_fp -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @sint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %value = load <4 x i32> addrspace(1) * %in - %result = sitofp <4 x i32> %value to <4 x float> - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} - -; CHECK: @uint_to_fp -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @uint_to_fp(<4 x float> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %value = load <4 x i32> addrspace(1) * %in - %result = uitofp <4 x i32> %value to <4 x float> - store <4 x float> %result, <4 x float> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll new file mode 100644 index 000000000000..6e459df847e7 --- /dev/null +++ b/test/CodeGen/R600/vselect.ll @@ -0,0 +1,17 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @test_select_v4i32 +; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { +entry: + %0 = load <4 x i32> addrspace(1)* %in0 + %1 = load <4 x i32> addrspace(1)* %in1 + %cmp = icmp ne <4 x i32> %0, %1 + %result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1 + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/R600/xor.ll b/test/CodeGen/R600/xor.ll new file mode 100644 index 000000000000..cf612e0a1fbe --- /dev/null +++ b/test/CodeGen/R600/xor.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +; CHECK: @xor_v4i32 +; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: XOR_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @xor_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { + %result = xor <4 x i32> %a, %b + store <4 x i32> %result, <4 x i32> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/SPARC/64abi.ll b/test/CodeGen/SPARC/64abi.ll new file mode 100644 index 000000000000..ec9713572141 --- /dev/null +++ b/test/CodeGen/SPARC/64abi.ll @@ -0,0 +1,378 @@ +; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler | FileCheck %s + +; CHECK: intarg +; The save/restore frame is not strictly necessary here, but we would need to +; refer to %o registers instead. +; CHECK: save %sp, -128, %sp +; CHECK: stb %i0, [%i4] +; CHECK: stb %i1, [%i4] +; CHECK: sth %i2, [%i4] +; CHECK: st %i3, [%i4] +; CHECK: stx %i4, [%i4] +; CHECK: st %i5, [%i4] +; CHECK: ld [%fp+2227], [[R:%[gilo][0-7]]] +; CHECK: st [[R]], [%i4] +; CHECK: ldx [%fp+2231], [[R:%[gilo][0-7]]] +; CHECK: stx [[R]], [%i4] +; CHECK: restore +define void @intarg(i8 %a0, ; %i0 + i8 %a1, ; %i1 + i16 %a2, ; %i2 + i32 %a3, ; %i3 + i8* %a4, ; %i4 + i32 %a5, ; %i5 + i32 signext %a6, ; [%fp+BIAS+176] + i8* %a7) { ; [%fp+BIAS+184] + store i8 %a0, i8* %a4 + store i8 %a1, i8* %a4 + %p16 = bitcast i8* %a4 to i16* + store i16 %a2, i16* %p16 + %p32 = bitcast i8* %a4 to i32* + store i32 %a3, i32* %p32 + %pp = bitcast i8* %a4 to i8** + store i8* %a4, i8** %pp + store i32 %a5, i32* %p32 + store i32 %a6, i32* %p32 + store i8* %a7, i8** %pp + ret void +} + +; CHECK: call_intarg +; 16 saved + 8 args. +; CHECK: save %sp, -192, %sp +; Sign-extend and store the full 64 bits. +; CHECK: sra %i0, 0, [[R:%[gilo][0-7]]] +; CHECK: stx [[R]], [%sp+2223] +; Use %o0-%o5 for outgoing arguments +; CHECK: or %g0, 5, %o5 +; CHECK: call intarg +; CHECK-NOT: add %sp +; CHECK: restore +define void @call_intarg(i32 %i0, i8* %i1) { + call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1) + ret void +} + +; CHECK: floatarg +; CHECK: save %sp, -128, %sp +; CHECK: fstod %f1, +; CHECK: faddd %f2, +; CHECK: faddd %f4, +; CHECK: faddd %f6, +; CHECK: ld [%fp+2307], [[F:%f[0-9]+]] +; CHECK: fadds %f31, [[F]] +define double @floatarg(float %a0, ; %f1 + double %a1, ; %d2 + double %a2, ; %d4 + double %a3, ; %d6 + float %a4, ; %f9 + float %a5, ; %f11 + float %a6, ; %f13 + float %a7, ; %f15 + float %a8, ; %f17 + float %a9, ; %f19 + float %a10, ; %f21 + float %a11, ; %f23 + float %a12, ; %f25 + float %a13, ; %f27 + float %a14, ; %f29 + float %a15, ; %f31 + float %a16, ; [%fp+BIAS+256] (using 8 bytes) + double %a17) { ; [%fp+BIAS+264] (using 8 bytes) + %d0 = fpext float %a0 to double + %s1 = fadd double %a1, %d0 + %s2 = fadd double %a2, %s1 + %s3 = fadd double %a3, %s2 + %s16 = fadd float %a15, %a16 + %d16 = fpext float %s16 to double + %s17 = fadd double %d16, %s3 + ret double %s17 +} + +; CHECK: call_floatarg +; CHECK: save %sp, -272, %sp +; Store 4 bytes, right-aligned in slot. +; CHECK: st %f1, [%sp+2307] +; Store 8 bytes in full slot. +; CHECK: std %f2, [%sp+2311] +; CHECK: fmovd %f2, %f4 +; CHECK: call floatarg +; CHECK-NOT: add %sp +; CHECK: restore +define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) { + %r = call double @floatarg(float %f5, double %d2, double %d2, double %d2, + float %f5, float %f5, float %f5, float %f5, + float %f5, float %f5, float %f5, float %f5, + float %f5, float %f5, float %f5, float %f5, + float %f1, double %d2) + store double %r, double* %p + ret void +} + +; CHECK: mixedarg +; CHECK: fstod %f3 +; CHECK: faddd %f6 +; CHECK: faddd %f16 +; CHECK: ldx [%fp+2231] +; CHECK: ldx [%fp+2247] +define void @mixedarg(i8 %a0, ; %i0 + float %a1, ; %f3 + i16 %a2, ; %i2 + double %a3, ; %d6 + i13 %a4, ; %i4 + float %a5, ; %f11 + i64 %a6, ; [%fp+BIAS+176] + double *%a7, ; [%fp+BIAS+184] + double %a8, ; %d16 + i16* %a9) { ; [%fp+BIAS+200] + %d1 = fpext float %a1 to double + %s3 = fadd double %a3, %d1 + %s8 = fadd double %a8, %s3 + store double %s8, double* %a7 + store i16 %a2, i16* %a9 + ret void +} + +; CHECK: call_mixedarg +; CHECK: stx %i2, [%sp+2247] +; CHECK: stx %i0, [%sp+2223] +; CHECK: fmovd %f2, %f6 +; CHECK: fmovd %f2, %f16 +; CHECK: call mixedarg +; CHECK-NOT: add %sp +; CHECK: restore +define void @call_mixedarg(i64 %i0, double %f2, i16* %i2) { + call void @mixedarg(i8 undef, + float undef, + i16 undef, + double %f2, + i13 undef, + float undef, + i64 %i0, + double* undef, + double %f2, + i16* %i2) + ret void +} + +; The inreg attribute is used to indicate 32-bit sized struct elements that +; share an 8-byte slot. +; CHECK: inreg_fi +; CHECK: fstoi %f1 +; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]] +; CHECK: sub [[R]], +define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0 + float inreg %a1) { ; %f1 + %b1 = fptosi float %a1 to i32 + %rv = sub i32 %a0, %b1 + ret i32 %rv +} + +; CHECK: call_inreg_fi +; Allocate space for 6 arguments, even when only 2 are used. +; CHECK: save %sp, -176, %sp +; CHECK: sllx %i1, 32, %o0 +; CHECK: fmovs %f5, %f1 +; CHECK: call inreg_fi +define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) { + %x = call i32 @inreg_fi(i32 %i1, float %f5) + ret void +} + +; CHECK: inreg_ff +; CHECK: fsubs %f0, %f1, %f1 +define float @inreg_ff(float inreg %a0, ; %f0 + float inreg %a1) { ; %f1 + %rv = fsub float %a0, %a1 + ret float %rv +} + +; CHECK: call_inreg_ff +; CHECK: fmovs %f3, %f0 +; CHECK: fmovs %f5, %f1 +; CHECK: call inreg_ff +define void @call_inreg_ff(i32* %p, float %f3, float %f5) { + %x = call float @inreg_ff(float %f3, float %f5) + ret void +} + +; CHECK: inreg_if +; CHECK: fstoi %f0 +; CHECK: sub %i0 +define i32 @inreg_if(float inreg %a0, ; %f0 + i32 inreg %a1) { ; low bits of %i0 + %b0 = fptosi float %a0 to i32 + %rv = sub i32 %a1, %b0 + ret i32 %rv +} + +; CHECK: call_inreg_if +; CHECK: fmovs %f3, %f0 +; CHECK: or %g0, %i2, %o0 +; CHECK: call inreg_if +define void @call_inreg_if(i32* %p, float %f3, i32 %i2) { + %x = call i32 @inreg_if(float %f3, i32 %i2) + ret void +} + +; The frontend shouldn't do this. Just pass i64 instead. +; CHECK: inreg_ii +; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]] +; CHECK: sub %i0, [[R]], %i0 +define i32 @inreg_ii(i32 inreg %a0, ; high bits of %i0 + i32 inreg %a1) { ; low bits of %i0 + %rv = sub i32 %a1, %a0 + ret i32 %rv +} + +; CHECK: call_inreg_ii +; CHECK: srl %i2, 0, [[R2:%[gilo][0-7]]] +; CHECK: sllx %i1, 32, [[R1:%[gilo][0-7]]] +; CHECK: or [[R1]], [[R2]], %o0 +; CHECK: call inreg_ii +define void @call_inreg_ii(i32* %p, i32 %i1, i32 %i2) { + %x = call i32 @inreg_ii(i32 %i1, i32 %i2) + ret void +} + +; Structs up to 32 bytes in size can be returned in registers. +; CHECK: ret_i64_pair +; CHECK: ldx [%i2], %i0 +; CHECK: ldx [%i3], %i1 +define { i64, i64 } @ret_i64_pair(i32 %a0, i32 %a1, i64* %p, i64* %q) { + %r1 = load i64* %p + %rv1 = insertvalue { i64, i64 } undef, i64 %r1, 0 + store i64 0, i64* %p + %r2 = load i64* %q + %rv2 = insertvalue { i64, i64 } %rv1, i64 %r2, 1 + ret { i64, i64 } %rv2 +} + +; CHECK: call_ret_i64_pair +; CHECK: call ret_i64_pair +; CHECK: stx %o0, [%i0] +; CHECK: stx %o1, [%i0] +define void @call_ret_i64_pair(i64* %i0) { + %rv = call { i64, i64 } @ret_i64_pair(i32 undef, i32 undef, + i64* undef, i64* undef) + %e0 = extractvalue { i64, i64 } %rv, 0 + store i64 %e0, i64* %i0 + %e1 = extractvalue { i64, i64 } %rv, 1 + store i64 %e1, i64* %i0 + ret void +} + +; This is not a C struct, each member uses 8 bytes. +; CHECK: ret_i32_float_pair +; CHECK: ld [%i2], %i0 +; CHECK: ld [%i3], %f3 +define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1, + i32* %p, float* %q) { + %r1 = load i32* %p + %rv1 = insertvalue { i32, float } undef, i32 %r1, 0 + store i32 0, i32* %p + %r2 = load float* %q + %rv2 = insertvalue { i32, float } %rv1, float %r2, 1 + ret { i32, float } %rv2 +} + +; CHECK: call_ret_i32_float_pair +; CHECK: call ret_i32_float_pair +; CHECK: st %o0, [%i0] +; CHECK: st %f3, [%i1] +define void @call_ret_i32_float_pair(i32* %i0, float* %i1) { + %rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef, + i32* undef, float* undef) + %e0 = extractvalue { i32, float } %rv, 0 + store i32 %e0, i32* %i0 + %e1 = extractvalue { i32, float } %rv, 1 + store float %e1, float* %i1 + ret void +} + +; This is a C struct, each member uses 4 bytes. +; CHECK: ret_i32_float_packed +; CHECK: ld [%i2], [[R:%[gilo][0-7]]] +; CHECK: sllx [[R]], 32, %i0 +; CHECK: ld [%i3], %f1 +define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1, + i32* %p, float* %q) { + %r1 = load i32* %p + %rv1 = insertvalue { i32, float } undef, i32 %r1, 0 + store i32 0, i32* %p + %r2 = load float* %q + %rv2 = insertvalue { i32, float } %rv1, float %r2, 1 + ret { i32, float } %rv2 +} + +; CHECK: call_ret_i32_float_packed +; CHECK: call ret_i32_float_packed +; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]] +; CHECK: st [[R]], [%i0] +; CHECK: st %f1, [%i1] +define void @call_ret_i32_float_packed(i32* %i0, float* %i1) { + %rv = call { i32, float } @ret_i32_float_packed(i32 undef, i32 undef, + i32* undef, float* undef) + %e0 = extractvalue { i32, float } %rv, 0 + store i32 %e0, i32* %i0 + %e1 = extractvalue { i32, float } %rv, 1 + store float %e1, float* %i1 + ret void +} + +; The C frontend should use i64 to return { i32, i32 } structs, but verify that +; we don't miscompile thi case where both struct elements are placed in %i0. +; CHECK: ret_i32_packed +; CHECK: ld [%i2], [[R1:%[gilo][0-7]]] +; CHECK: ld [%i3], [[R2:%[gilo][0-7]]] +; CHECK: sllx [[R2]], 32, [[R3:%[gilo][0-7]]] +; CHECK: or [[R3]], [[R1]], %i0 +define inreg { i32, i32 } @ret_i32_packed(i32 %a0, i32 %a1, + i32* %p, i32* %q) { + %r1 = load i32* %p + %rv1 = insertvalue { i32, i32 } undef, i32 %r1, 1 + store i32 0, i32* %p + %r2 = load i32* %q + %rv2 = insertvalue { i32, i32 } %rv1, i32 %r2, 0 + ret { i32, i32 } %rv2 +} + +; CHECK: call_ret_i32_packed +; CHECK: call ret_i32_packed +; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]] +; CHECK: st [[R]], [%i0] +; CHECK: st %o0, [%i1] +define void @call_ret_i32_packed(i32* %i0, i32* %i1) { + %rv = call { i32, i32 } @ret_i32_packed(i32 undef, i32 undef, + i32* undef, i32* undef) + %e0 = extractvalue { i32, i32 } %rv, 0 + store i32 %e0, i32* %i0 + %e1 = extractvalue { i32, i32 } %rv, 1 + store i32 %e1, i32* %i1 + ret void +} + +; The return value must be sign-extended to 64 bits. +; CHECK: ret_sext +; CHECK: sra %i0, 0, %i0 +define signext i32 @ret_sext(i32 %a0) { + ret i32 %a0 +} + +; CHECK: ret_zext +; CHECK: srl %i0, 0, %i0 +define zeroext i32 @ret_zext(i32 %a0) { + ret i32 %a0 +} + +; CHECK: ret_nosext +; CHECK-NOT: sra +define signext i32 @ret_nosext(i32 signext %a0) { + ret i32 %a0 +} + +; CHECK: ret_nozext +; CHECK-NOT: srl +define signext i32 @ret_nozext(i32 signext %a0) { + ret i32 %a0 +} diff --git a/test/CodeGen/SPARC/64bit.ll b/test/CodeGen/SPARC/64bit.ll index 0d4e191c9509..2bbf7deb1684 100644 --- a/test/CodeGen/SPARC/64bit.ll +++ b/test/CodeGen/SPARC/64bit.ll @@ -66,6 +66,12 @@ define i64 @ret_bigimm() { ret i64 6800754272627607872 } +; CHECK: ret_bigimm2 +; CHECK: sethi 1048576 +define i64 @ret_bigimm2() { + ret i64 4611686018427387904 ; 0x4000000000000000 +} + ; CHECK: reg_reg_alu ; CHECK: add %i0, %i1, [[R0:%[goli][0-7]]] ; CHECK: sub [[R0]], %i2, [[R1:%[goli][0-7]]] @@ -144,3 +150,34 @@ define void @stores(i64* %p, i32* %q, i16* %r, i8* %s) { ret void } + +; CHECK: promote_shifts +; CHECK: ldub [%i0], [[R:%[goli][0-7]]] +; CHECK: sll [[R]], [[R]], %i0 +define i8 @promote_shifts(i8* %p) { + %L24 = load i8* %p + %L32 = load i8* %p + %B36 = shl i8 %L24, %L32 + ret i8 %B36 +} + +; CHECK: multiply +; CHECK: mulx %i0, %i1, %i0 +define i64 @multiply(i64 %a, i64 %b) { + %r = mul i64 %a, %b + ret i64 %r +} + +; CHECK: signed_divide +; CHECK: sdivx %i0, %i1, %i0 +define i64 @signed_divide(i64 %a, i64 %b) { + %r = sdiv i64 %a, %b + ret i64 %r +} + +; CHECK: unsigned_divide +; CHECK: udivx %i0, %i1, %i0 +define i64 @unsigned_divide(i64 %a, i64 %b) { + %r = udiv i64 %a, %b + ret i64 %r +} diff --git a/test/CodeGen/SPARC/constpool.ll b/test/CodeGen/SPARC/constpool.ll new file mode 100644 index 000000000000..d93a53b3ac04 --- /dev/null +++ b/test/CodeGen/SPARC/constpool.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=medium | FileCheck --check-prefix=abs44 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=large | FileCheck --check-prefix=abs64 %s +; RUN: llc < %s -march=sparc -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v8pic32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v9pic32 %s + +define float @floatCP() { +entry: + ret float 1.000000e+00 +} + +; abs32: floatCP +; abs32: sethi %hi(.LCPI0_0), %[[R:[gilo][0-7]]] +; abs32: ld [%[[R]]+%lo(.LCPI0_0)], %f +; abs32: jmp %i7+8 + +; abs44: floatCP +; abs44: sethi %h44(.LCPI0_0), %[[R1:[gilo][0-7]]] +; abs44: add %[[R1]], %m44(.LCPI0_0), %[[R2:[gilo][0-7]]] +; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] +; abs44: ld [%[[R3]]+%l44(.LCPI0_0)], %f1 +; abs44: jmp %i7+8 + +; abs64: floatCP +; abs64: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]] +; abs64: add %[[R1]], %lo(.LCPI0_0), %[[R2:[gilo][0-7]]] +; abs64: sethi %hh(.LCPI0_0), %[[R3:[gilo][0-7]]] +; abs64: add %[[R3]], %hm(.LCPI0_0), %[[R4:[gilo][0-7]]] +; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] +; abs64: ld [%[[R5]]+%[[R2]]], %f1 +; abs64: jmp %i7+8 + +; v8pic32: floatCP +; v8pic32: _GLOBAL_OFFSET_TABLE_ +; v8pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]] +; v8pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] +; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] +; v8pic32: ld [%[[Gaddr]]], %f0 +; v8pic32: jmp %i7+8 + +; v9pic32: floatCP +; v9pic32: _GLOBAL_OFFSET_TABLE_ +; v9pic32: sethi %hi(.LCPI0_0), %[[R1:[gilo][0-7]]] +; v9pic32: add %[[R1]], %lo(.LCPI0_0), %[[Goffs:[gilo][0-7]]] +; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] +; v9pic32: ld [%[[Gaddr]]], %f1 +; v9pic32: jmp %i7+8 diff --git a/test/CodeGen/SPARC/globals.ll b/test/CodeGen/SPARC/globals.ll new file mode 100644 index 000000000000..8d8de58f7ccf --- /dev/null +++ b/test/CodeGen/SPARC/globals.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -march=sparc -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=small | FileCheck --check-prefix=abs32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=medium | FileCheck --check-prefix=abs44 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=static -code-model=large | FileCheck --check-prefix=abs64 %s +; RUN: llc < %s -march=sparc -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v8pic32 %s +; RUN: llc < %s -march=sparcv9 -relocation-model=pic -code-model=medium | FileCheck --check-prefix=v9pic32 %s + +@G = external global i8 + +define zeroext i8 @loadG() { + %tmp = load i8* @G + ret i8 %tmp +} + +; abs32: loadG +; abs32: sethi %hi(G), %[[R:[gilo][0-7]]] +; abs32: ldub [%[[R]]+%lo(G)], %i0 +; abs32: jmp %i7+8 + +; abs44: loadG +; abs44: sethi %h44(G), %[[R1:[gilo][0-7]]] +; abs44: add %[[R1]], %m44(G), %[[R2:[gilo][0-7]]] +; abs44: sllx %[[R2]], 12, %[[R3:[gilo][0-7]]] +; abs44: ldub [%[[R3]]+%l44(G)], %i0 +; abs44: jmp %i7+8 + +; abs64: loadG +; abs64: sethi %hi(G), %[[R1:[gilo][0-7]]] +; abs64: add %[[R1]], %lo(G), %[[R2:[gilo][0-7]]] +; abs64: sethi %hh(G), %[[R3:[gilo][0-7]]] +; abs64: add %[[R3]], %hm(G), %[[R4:[gilo][0-7]]] +; abs64: sllx %[[R4]], 32, %[[R5:[gilo][0-7]]] +; abs64: ldub [%[[R5]]+%[[R2]]], %i0 +; abs64: jmp %i7+8 + +; v8pic32: loadG +; v8pic32: _GLOBAL_OFFSET_TABLE_ +; v8pic32: sethi %hi(G), %[[R1:[gilo][0-7]]] +; v8pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]] +; v8pic32: ld [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] +; v8pic32: ldub [%[[Gaddr]]], %i0 +; v8pic32: jmp %i7+8 + +; v9pic32: loadG +; v9pic32: _GLOBAL_OFFSET_TABLE_ +; v9pic32: sethi %hi(G), %[[R1:[gilo][0-7]]] +; v9pic32: add %[[R1]], %lo(G), %[[Goffs:[gilo][0-7]]] +; v9pic32: ldx [%[[GOT:[gilo][0-7]]]+%[[Goffs]]], %[[Gaddr:[gilo][0-7]]] +; v9pic32: ldub [%[[Gaddr]]], %i0 +; v9pic32: jmp %i7+8 diff --git a/test/CodeGen/SPARC/varargs.ll b/test/CodeGen/SPARC/varargs.ll new file mode 100644 index 000000000000..b13f90e6ca71 --- /dev/null +++ b/test/CodeGen/SPARC/varargs.ll @@ -0,0 +1,75 @@ +; RUN: llc < %s -disable-block-placement | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128" +target triple = "sparcv9-sun-solaris" + +; CHECK: varargsfunc +; 128 byte save ares + 1 alloca rounded up to 16 bytes alignment. +; CHECK: save %sp, -144, %sp +; Store the ... arguments to the argument array. The order is not important. +; CHECK: stx %i5, [%fp+2215] +; CHECK: stx %i4, [%fp+2207] +; CHECK: stx %i3, [%fp+2199] +; CHECK: stx %i2, [%fp+2191] +; Store the address of the ... args to %ap at %fp+BIAS+128-8 +; add %fp, 2191, [[R:[gilo][0-7]]] +; stx [[R]], [%fp+2039] +define double @varargsfunc(i8* nocapture %fmt, double %sum, ...) { +entry: + %ap = alloca i8*, align 4 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + br label %for.cond + +for.cond: + %fmt.addr.0 = phi i8* [ %fmt, %entry ], [ %incdec.ptr, %for.cond.backedge ] + %sum.addr.0 = phi double [ %sum, %entry ], [ %sum.addr.0.be, %for.cond.backedge ] + %incdec.ptr = getelementptr inbounds i8* %fmt.addr.0, i64 1 + %0 = load i8* %fmt.addr.0, align 1 + %conv = sext i8 %0 to i32 + switch i32 %conv, label %sw.default [ + i32 105, label %sw.bb + i32 102, label %sw.bb3 + ] + +; CHECK: sw.bb +; ldx [%fp+2039], %[[AP:[gilo][0-7]]] +; add %[[AP]], 4, %[[AP2:[gilo][0-7]]] +; stx %[[AP2]], [%fp+2039] +; ld [%[[AP]]] +sw.bb: + %1 = va_arg i8** %ap, i32 + %conv2 = sitofp i32 %1 to double + br label %for.cond.backedge + +; CHECK: sw.bb3 +; ldx [%fp+2039], %[[AP:[gilo][0-7]]] +; add %[[AP]], 8, %[[AP2:[gilo][0-7]]] +; stx %[[AP2]], [%fp+2039] +; ldd [%[[AP]]] +sw.bb3: + %2 = va_arg i8** %ap, double + br label %for.cond.backedge + +for.cond.backedge: + %.pn = phi double [ %2, %sw.bb3 ], [ %conv2, %sw.bb ] + %sum.addr.0.be = fadd double %.pn, %sum.addr.0 + br label %for.cond + +sw.default: + ret double %sum.addr.0 +} + +declare void @llvm.va_start(i8*) + +@.str = private unnamed_addr constant [4 x i8] c"abc\00", align 1 + +; CHECK: call_1d +; The fixed-arg double goes in %d2, the second goes in %o2. +; CHECK: sethi 1048576 +; CHECK: , %o2 +; CHECK: , %f2 +define i32 @call_1d() #0 { +entry: + %call = call double (i8*, double, ...)* @varargsfunc(i8* undef, double 1.000000e+00, double 2.000000e+00) + ret i32 1 +} diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll new file mode 100644 index 000000000000..c125ffa71a71 --- /dev/null +++ b/test/CodeGen/SystemZ/addr-01.ll @@ -0,0 +1,107 @@ +; Test selection of addresses with indices in cases where the address +; is used once. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; A simple index address. +define void @f1(i64 %addr, i64 %index) { +; CHECK: f1: +; CHECK: lb %r0, 0(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %addr, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; An address with an index and a displacement (order 1). +define void @f2(i64 %addr, i64 %index) { +; CHECK: f2: +; CHECK: lb %r0, 100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, %index + %add2 = add i64 %add1, 100 + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; An address with an index and a displacement (order 2). +define void @f3(i64 %addr, i64 %index) { +; CHECK: f3: +; CHECK: lb %r0, 100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, 100 + %add2 = add i64 %add1, %index + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; An address with an index and a subtracted displacement (order 1). +define void @f4(i64 %addr, i64 %index) { +; CHECK: f4: +; CHECK: lb %r0, -100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, %index + %add2 = sub i64 %add1, 100 + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; An address with an index and a subtracted displacement (order 2). +define void @f5(i64 %addr, i64 %index) { +; CHECK: f5: +; CHECK: lb %r0, -100(%r3,%r2) +; CHECK: br %r14 + %add1 = sub i64 %addr, 100 + %add2 = add i64 %add1, %index + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; An address with an index and a displacement added using OR. +define void @f6(i64 %addr, i64 %index) { +; CHECK: f6: +; CHECK: nill %r2, 65528 +; CHECK: lb %r0, 6(%r3,%r2) +; CHECK: br %r14 + %aligned = and i64 %addr, -8 + %or = or i64 %aligned, 6 + %add = add i64 %or, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; Like f6, but without the masking. This OR doesn't count as a displacement. +define void @f7(i64 %addr, i64 %index) { +; CHECK: f7: +; CHECK: oill %r2, 6 +; CHECK: lb %r0, 0(%r3,%r2) +; CHECK: br %r14 + %or = or i64 %addr, 6 + %add = add i64 %or, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + ret void +} + +; Like f6, but with the OR applied after the index. We don't know anything +; about the alignment of %add here. +define void @f8(i64 %addr, i64 %index) { +; CHECK: f8: +; CHECK: nill %r2, 65528 +; CHECK: agr %r2, %r3 +; CHECK: oill %r2, 6 +; CHECK: lb %r0, 0(%r2) +; CHECK: br %r14 + %aligned = and i64 %addr, -8 + %add = add i64 %aligned, %index + %or = or i64 %add, 6 + %ptr = inttoptr i64 %or to i8 * + %a = load volatile i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/addr-02.ll b/test/CodeGen/SystemZ/addr-02.ll new file mode 100644 index 000000000000..6772c1d41800 --- /dev/null +++ b/test/CodeGen/SystemZ/addr-02.ll @@ -0,0 +1,116 @@ +; addr-01.ll in which the address is also used in a non-address context. +; The assumption here is that we should match complex addresses where +; possible, but this might well need to change in future. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; A simple index address. +define void @f1(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f1: +; CHECK: lb %r0, 0(%r3,%r2) +; CHECK: br %r14 + %add = add i64 %addr, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; An address with an index and a displacement (order 1). +define void @f2(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f2: +; CHECK: lb %r0, 100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, %index + %add2 = add i64 %add1, 100 + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; An address with an index and a displacement (order 2). +define void @f3(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f3: +; CHECK: lb %r0, 100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, 100 + %add2 = add i64 %add1, %index + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; An address with an index and a subtracted displacement (order 1). +define void @f4(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f4: +; CHECK: lb %r0, -100(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %addr, %index + %add2 = sub i64 %add1, 100 + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; An address with an index and a subtracted displacement (order 2). +define void @f5(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f5: +; CHECK: lb %r0, -100(%r3,%r2) +; CHECK: br %r14 + %add1 = sub i64 %addr, 100 + %add2 = add i64 %add1, %index + %ptr = inttoptr i64 %add2 to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; An address with an index and a displacement added using OR. +define void @f6(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f6: +; CHECK: nill %r2, 65528 +; CHECK: lb %r0, 6(%r3,%r2) +; CHECK: br %r14 + %aligned = and i64 %addr, -8 + %or = or i64 %aligned, 6 + %add = add i64 %or, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; Like f6, but without the masking. This OR doesn't count as a displacement. +define void @f7(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f7: +; CHECK: oill %r2, 6 +; CHECK: lb %r0, 0(%r3,%r2) +; CHECK: br %r14 + %or = or i64 %addr, 6 + %add = add i64 %or, %index + %ptr = inttoptr i64 %add to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} + +; Like f6, but with the OR applied after the index. We don't know anything +; about the alignment of %add here. +define void @f8(i64 %addr, i64 %index, i8 **%dst) { +; CHECK: f8: +; CHECK: nill %r2, 65528 +; CHECK: agr %r2, %r3 +; CHECK: oill %r2, 6 +; CHECK: lb %r0, 0(%r2) +; CHECK: br %r14 + %aligned = and i64 %addr, -8 + %add = add i64 %aligned, %index + %or = or i64 %add, 6 + %ptr = inttoptr i64 %or to i8 * + %a = load volatile i8 *%ptr + store volatile i8 *%ptr, i8 **%dst + ret void +} diff --git a/test/CodeGen/SystemZ/addr-03.ll b/test/CodeGen/SystemZ/addr-03.ll new file mode 100644 index 000000000000..dbdb9f15b4f1 --- /dev/null +++ b/test/CodeGen/SystemZ/addr-03.ll @@ -0,0 +1,48 @@ +; Test constant addresses, unlikely as they are. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1() { +; CHECK: f1: +; CHECK: lb %r0, 0 +; CHECK: br %r14 + %ptr = inttoptr i64 0 to i8 * + %val = load volatile i8 *%ptr + ret void +} + +define void @f2() { +; CHECK: f2: +; CHECK: lb %r0, -524288 +; CHECK: br %r14 + %ptr = inttoptr i64 -524288 to i8 * + %val = load volatile i8 *%ptr + ret void +} + +define void @f3() { +; CHECK: f3: +; CHECK-NOT: lb %r0, -524289 +; CHECK: br %r14 + %ptr = inttoptr i64 -524289 to i8 * + %val = load volatile i8 *%ptr + ret void +} + +define void @f4() { +; CHECK: f4: +; CHECK: lb %r0, 524287 +; CHECK: br %r14 + %ptr = inttoptr i64 524287 to i8 * + %val = load volatile i8 *%ptr + ret void +} + +define void @f5() { +; CHECK: f5: +; CHECK-NOT: lb %r0, 524288 +; CHECK: br %r14 + %ptr = inttoptr i64 524288 to i8 * + %val = load volatile i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/alloca-01.ll b/test/CodeGen/SystemZ/alloca-01.ll new file mode 100644 index 000000000000..1852c9135059 --- /dev/null +++ b/test/CodeGen/SystemZ/alloca-01.ll @@ -0,0 +1,81 @@ +; Test variable-sized allocas and addresses based on them in cases where +; stack arguments are needed. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP + +declare i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 %f, i64 %g) + +; Allocate %length bytes and take addresses based on the result. +; There are two stack arguments, so an offset of 160 + 2 * 8 == 176 +; is added to the copy of %r15. +define i64 @f1(i64 %length, i64 %index) { +; The full allocation sequence is: +; +; la %r0, 7(%r2) 1 +; nill %r0, 0xfff8 1 +; lgr %r1, %r15 2 +; sgr %r1, %r0 1 2 +; lgr %r15, %r1 2 +; +; The third instruction does not depend on the first two, so check for +; two fully-ordered sequences. +; +; FIXME: a better sequence would be: +; +; lgr %r1, %r15 +; sgr %r1, %r2 +; nill %r1, 0xfff8 +; lgr %r15, %r1 +; +; CHECK1: f1: +; CHECK1: la %r0, 7(%r2) +; CHECK1: nill %r0, 65528 +; CHECK1: sgr %r1, %r0 +; CHECK1: lgr %r15, %r1 +; +; CHECK2: f1: +; CHECK2: lgr %r1, %r15 +; CHECK2: sgr %r1, %r0 +; CHECK2: lgr %r15, %r1 +; +; CHECK-A: f1: +; CHECK-A: lgr %r15, %r1 +; CHECK-A: la %r2, 176(%r1) +; +; CHECK-B: f1: +; CHECK-B: lgr %r15, %r1 +; CHECK-B: la %r3, 177(%r1) +; +; CHECK-C: f1: +; CHECK-C: lgr %r15, %r1 +; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}}) +; +; CHECK-D: f1: +; CHECK-D: lgr %r15, %r1 +; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}}) +; +; CHECK-E: f1: +; CHECK-E: lgr %r15, %r1 +; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}}) +; +; CHECK-FP: f1: +; CHECK-FP: lgr %r11, %r15 +; CHECK-FP: lmg %r6, %r15, 224(%r11) + %a = alloca i8, i64 %length + %b = getelementptr i8 *%a, i64 1 + %cindex = add i64 %index, 3919 + %c = getelementptr i8 *%a, i64 %cindex + %dindex = add i64 %index, 3920 + %d = getelementptr i8 *%a, i64 %dindex + %eindex = add i64 %index, 4095 + %e = getelementptr i8 *%a, i64 %eindex + %count = call i64 @bar(i8 *%a, i8 *%b, i8 *%c, i8 *%d, i8 *%e, i64 0, i64 0) + %res = add i64 %count, 1 + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/alloca-02.ll b/test/CodeGen/SystemZ/alloca-02.ll new file mode 100644 index 000000000000..fbb095f4d12d --- /dev/null +++ b/test/CodeGen/SystemZ/alloca-02.ll @@ -0,0 +1,49 @@ +; Make sure that the alloca offset isn't lost when the alloca result is +; used directly in a load or store. There must always be an LA or LAY. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-A +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-B +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-C +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-D + +declare i64 @bar(i8 *%a) + +define i64 @f1(i64 %length, i64 %index) { +; CHECK-A: f1: +; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]] +; CHECK-A: la %r2, 160([[ADDR]]) +; CHECK-A: mvi 0(%r2), 0 +; +; CHECK-B: f1: +; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]] +; CHECK-B: la %r2, 160([[ADDR]]) +; CHECK-B: mvi 4095(%r2), 1 +; +; CHECK-C: f1: +; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]] +; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) +; CHECK-C: mvi 0([[TMP]]), 2 +; +; CHECK-D: f1: +; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]] +; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) +; CHECK-D: mvi 4095([[TMP]]), 3 +; +; CHECK-E: f1: +; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]] +; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]]) +; CHECK-E: mviy 4096([[TMP]]), 4 + %a = alloca i8, i64 %length + store i8 0, i8 *%a + %b = getelementptr i8 *%a, i64 4095 + store i8 1, i8 *%b + %c = getelementptr i8 *%a, i64 %index + store i8 2, i8 *%c + %d = getelementptr i8 *%c, i64 4095 + store i8 3, i8 *%d + %e = getelementptr i8 *%d, i64 1 + store i8 4, i8 *%e + %count = call i64 @bar(i8 *%a) + %res = add i64 %count, 1 + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/and-01.ll b/test/CodeGen/SystemZ/and-01.ll new file mode 100644 index 000000000000..8dd106b7c015 --- /dev/null +++ b/test/CodeGen/SystemZ/and-01.ll @@ -0,0 +1,129 @@ +; Test 32-bit ANDs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check NR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: nr %r2, %r3 +; CHECK: br %r14 + %and = and i32 %a, %b + ret i32 %and +} + +; Check the low end of the N range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: n %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %and = and i32 %a, %b + ret i32 %and +} + +; Check the high end of the aligned N range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: n %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the next word up, which should use NY instead of N. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: ny %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the high end of the aligned NY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: ny %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: n %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the high end of the negative aligned NY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: ny %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the low end of the NY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: ny %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: n %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check that N allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} + +; Check that NY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %and = and i32 %a, %b + ret i32 %and +} diff --git a/test/CodeGen/SystemZ/and-02.ll b/test/CodeGen/SystemZ/and-02.ll new file mode 100644 index 000000000000..a0fff81492ad --- /dev/null +++ b/test/CodeGen/SystemZ/and-02.ll @@ -0,0 +1,93 @@ +; Test 32-bit ANDs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful NILF value. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: nilf %r2, 1 +; CHECK: br %r14 + %and = and i32 %a, 1 + ret i32 %and +} + +; Check the highest 16-bit constant that must be handled by NILF. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: nilf %r2, 65534 +; CHECK: br %r14 + %and = and i32 %a, 65534 + ret i32 %and +} + +; ANDs of 0xffff are zero extensions from i16. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: llhr %r2, %r2 +; CHECK: br %r14 + %and = and i32 %a, 65535 + ret i32 %and +} + +; Check the next value up, which must again use NILF. +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: nilf %r2, 65536 +; CHECK: br %r14 + %and = and i32 %a, 65536 + ret i32 %and +} + +; Check the lowest useful NILH value. (LLHR is used instead of NILH of 0.) +define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK: nilh %r2, 1 +; CHECK: br %r14 + %and = and i32 %a, 131071 + ret i32 %and +} + +; Check the highest useful NILF value. +define i32 @f6(i32 %a) { +; CHECK: f6: +; CHECK: nilf %r2, 4294901758 +; CHECK: br %r14 + %and = and i32 %a, -65538 + ret i32 %and +} + +; Check the highest useful NILH value, which is one up from the above. +define i32 @f7(i32 %a) { +; CHECK: f7: +; CHECK: nilh %r2, 65534 +; CHECK: br %r14 + %and = and i32 %a, -65537 + ret i32 %and +} + +; Check the low end of the NILL range, which is one up again. +define i32 @f8(i32 %a) { +; CHECK: f8: +; CHECK: nill %r2, 0 +; CHECK: br %r14 + %and = and i32 %a, -65536 + ret i32 %and +} + +; Check the next value up. +define i32 @f9(i32 %a) { +; CHECK: f9: +; CHECK: nill %r2, 1 +; CHECK: br %r14 + %and = and i32 %a, -65535 + ret i32 %and +} + +; Check the highest useful NILL value. +define i32 @f10(i32 %a) { +; CHECK: f10: +; CHECK: nill %r2, 65534 +; CHECK: br %r14 + %and = and i32 %a, -2 + ret i32 %and +} diff --git a/test/CodeGen/SystemZ/and-03.ll b/test/CodeGen/SystemZ/and-03.ll new file mode 100644 index 000000000000..3fe8d3cf3bf8 --- /dev/null +++ b/test/CodeGen/SystemZ/and-03.ll @@ -0,0 +1,94 @@ +; Test 64-bit ANDs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check NGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: ngr %r2, %r3 +; CHECK: br %r14 + %and = and i64 %a, %b + ret i64 %and +} + +; Check NG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: ng %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %and = and i64 %a, %b + ret i64 %and +} + +; Check the high end of the aligned NG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: ng %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: ng %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} + +; Check the high end of the negative aligned NG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: ng %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} + +; Check the low end of the NG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: ng %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: ng %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} + +; Check that NG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %and = and i64 %a, %b + ret i64 %and +} diff --git a/test/CodeGen/SystemZ/and-04.ll b/test/CodeGen/SystemZ/and-04.ll new file mode 100644 index 000000000000..62def60026e1 --- /dev/null +++ b/test/CodeGen/SystemZ/and-04.ll @@ -0,0 +1,180 @@ +; Test 64-bit ANDs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no 64-bit AND instruction for a mask of 1. +; FIXME: we ought to be able to require "ngr %r2, %r0", but at the moment, +; two-address optimisations force "ngr %r0, %r2; lgr %r2, %r0" instead. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: lghi %r0, 1 +; CHECK: ngr +; CHECK: br %r14 + %and = and i64 %a, 1 + ret i64 %and +} + +; Likewise 0xfffe. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llill %r0, 65534 +; CHECK: ngr +; CHECK: br %r14 + %and = and i64 %a, 65534 + ret i64 %and +} + +; ...but 0xffff is a 16-bit zero extension. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: llghr %r2, %r2 +; CHECK: br %r14 + %and = and i64 %a, 65535 + ret i64 %and +} + +; Check the next value up, which again has no dedicated instruction. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK: llilh %r0, 1 +; CHECK: ngr +; CHECK: br %r14 + %and = and i64 %a, 65536 + ret i64 %and +} + +; Check 0xfffffffe. +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK: lilf %r0, 4294967294 +; CHECK: ngr +; CHECK: br %r14 + %and = and i64 %a, 4294967294 + ret i64 %and +} + +; Check the next value up, which is a 32-bit zero extension. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK: llgfr %r2, %r2 +; CHECK: br %r14 + %and = and i64 %a, 4294967295 + ret i64 %and +} + +; Check the lowest useful NIHF value (0x00000001_ffffffff). +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK: nihf %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 8589934591 + ret i64 %and +} + +; Check the low end of the NIHH range (0x0000ffff_ffffffff). +define i64 @f8(i64 %a) { +; CHECK: f8: +; CHECK: nihh %r2, 0 +; CHECK: br %r14 + %and = and i64 %a, 281474976710655 + ret i64 %and +} + +; Check the highest useful NIHH value (0xfffeffff_ffffffff). +define i64 @f9(i64 %a) { +; CHECK: f9: +; CHECK: nihh %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, -281474976710657 + ret i64 %and +} + +; Check the highest useful NIHF value (0xfffefffe_ffffffff). +define i64 @f10(i64 %a) { +; CHECK: f10: +; CHECK: nihf %r2, 4294901758 +; CHECK: br %r14 + %and = and i64 %a, -281479271677953 + ret i64 %and +} + +; Check the low end of the NIHL range (0xffff0000_ffffffff). +define i64 @f11(i64 %a) { +; CHECK: f11: +; CHECK: nihl %r2, 0 +; CHECK: br %r14 + %and = and i64 %a, -281470681743361 + ret i64 %and +} + +; Check the highest useful NIHL value (0xfffffffe_ffffffff). +define i64 @f12(i64 %a) { +; CHECK: f12: +; CHECK: nihl %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, -4294967297 + ret i64 %and +} + +; Check the low end of the NILF range (0xffffffff_00000000). +define i64 @f13(i64 %a) { +; CHECK: f13: +; CHECK: nilf %r2, 0 +; CHECK: br %r14 + %and = and i64 %a, -4294967296 + ret i64 %and +} + +; Check the low end of the NILH range (0xffffffff_0000ffff). +define i64 @f14(i64 %a) { +; CHECK: f14: +; CHECK: nilh %r2, 0 +; CHECK: br %r14 + %and = and i64 %a, -4294901761 + ret i64 %and +} + +; Check the next value up, which must use NILF. +define i64 @f15(i64 %a) { +; CHECK: f15: +; CHECK: nilf %r2, 65536 +; CHECK: br %r14 + %and = and i64 %a, -4294901760 + ret i64 %and +} + +; Check the maximum useful NILF value (0xffffffff_fffefffe). +define i64 @f16(i64 %a) { +; CHECK: f16: +; CHECK: nilf %r2, 4294901758 +; CHECK: br %r14 + %and = and i64 %a, -65538 + ret i64 %and +} + +; Check the highest useful NILH value, which is one greater than the above. +define i64 @f17(i64 %a) { +; CHECK: f17: +; CHECK: nilh %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, -65537 + ret i64 %and +} + +; Check the low end of the NILL range, which is one greater again. +define i64 @f18(i64 %a) { +; CHECK: f18: +; CHECK: nill %r2, 0 +; CHECK: br %r14 + %and = and i64 %a, -65536 + ret i64 %and +} + +; Check the highest useful NILL value. +define i64 @f19(i64 %a) { +; CHECK: f19: +; CHECK: nill %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, -2 + ret i64 %and +} diff --git a/test/CodeGen/SystemZ/and-05.ll b/test/CodeGen/SystemZ/and-05.ll new file mode 100644 index 000000000000..457391165d5e --- /dev/null +++ b/test/CodeGen/SystemZ/and-05.ll @@ -0,0 +1,165 @@ +; Test ANDs of a constant into a byte of memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful constant, expressed as a signed integer. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: ni 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %and = and i8 %val, -255 + store i8 %and, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a signed integer. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %and = and i8 %val, -2 + store i8 %and, i8 *%ptr + ret void +} + +; Check the lowest useful constant, expressed as an unsigned integer. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: ni 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %and = and i8 %val, 1 + store i8 %and, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a unsigned integer. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %and = and i8 %val, 254 + store i8 %and, i8 *%ptr + ret void +} + +; Check the high end of the NI range. +define void @f5(i8 *%src) { +; CHECK: f5: +; CHECK: ni 4095(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the next byte up, which should use NIY instead of NI. +define void @f6(i8 *%src) { +; CHECK: f6: +; CHECK: niy 4096(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the high end of the NIY range. +define void @f7(i8 *%src) { +; CHECK: f7: +; CHECK: niy 524287(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i8 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, 524288 +; CHECK: ni 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the high end of the negative NIY range. +define void @f9(i8 *%src) { +; CHECK: f9: +; CHECK: niy -1(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the low end of the NIY range. +define void @f10(i8 *%src) { +; CHECK: f10: +; CHECK: niy -524288(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f11(i8 *%src) { +; CHECK: f11: +; CHECK: agfi %r2, -524289 +; CHECK: ni 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check that NI does not allow an index +define void @f12(i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: agr %r2, %r3 +; CHECK: ni 4095(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} + +; Check that NIY does not allow an index +define void @f13(i64 %src, i64 %index) { +; CHECK: f13: +; CHECK: agr %r2, %r3 +; CHECK: niy 4096(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %and = and i8 %val, 127 + store i8 %and, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/and-06.ll b/test/CodeGen/SystemZ/and-06.ll new file mode 100644 index 000000000000..bbb5e7b7b9dd --- /dev/null +++ b/test/CodeGen/SystemZ/and-06.ll @@ -0,0 +1,108 @@ +; Test that we can use NI for byte operations that are expressed as i32 +; or i64 operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Zero extension to 32 bits, negative constant. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %and = and i32 %ext, -2 + %trunc = trunc i32 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, negative constant. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %and = and i64 %ext, -2 + %trunc = trunc i64 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 32 bits, positive constant. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %and = and i32 %ext, 254 + %trunc = trunc i32 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, positive constant. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %and = and i64 %ext, 254 + %trunc = trunc i64 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, negative constant. +define void @f5(i8 *%ptr) { +; CHECK: f5: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %and = and i32 %ext, -2 + %trunc = trunc i32 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, negative constant. +define void @f6(i8 *%ptr) { +; CHECK: f6: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %and = and i64 %ext, -2 + %trunc = trunc i64 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, positive constant. +define void @f7(i8 *%ptr) { +; CHECK: f7: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %and = and i32 %ext, 254 + %trunc = trunc i32 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, positive constant. +define void @f8(i8 *%ptr) { +; CHECK: f8: +; CHECK: ni 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %and = and i64 %ext, 254 + %trunc = trunc i64 %and to i8 + store i8 %trunc, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/args-01.ll b/test/CodeGen/SystemZ/args-01.ll new file mode 100644 index 000000000000..a6b80c54db51 --- /dev/null +++ b/test/CodeGen/SystemZ/args-01.ll @@ -0,0 +1,74 @@ +; Test the handling of GPR, FPR and stack arguments when no extension +; type is given. This type of argument is used for passing structures, etc. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-DOUBLE +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK + +declare void @bar(i8, i16, i32, i64, float, double, fp128, i64, + float, double, i8, i16, i32, i64, float, double, fp128) + +; There are two indirect fp128 slots, one at offset 224 (the first available +; byte after the outgoing arguments) and one immediately after it at 240. +; These slots should be set up outside the glued call sequence, so would +; normally use %f0/%f2 as the first available 128-bit pair. This choice +; is hard-coded in the FP128 tests. +; +; The order of the CHECK-INT loads doesn't matter. The same goes for the +; CHECK_FP128-* stores and the CHECK-STACK stores. It would be OK to reorder +; them in response to future code changes. +define void @foo() { +; CHECK-INT: foo: +; CHECK-INT: lhi %r2, 1 +; CHECK-INT: lhi %r3, 2 +; CHECK-INT: lhi %r4, 3 +; CHECK-INT: lghi %r5, 4 +; CHECK-INT: la %r6, {{224|240}}(%r15) +; CHECK-INT: brasl %r14, bar@PLT +; +; CHECK-FLOAT: foo: +; CHECK-FLOAT: lzer %f0 +; CHECK-FLOAT: lcebr %f4, %f0 +; CHECK-FLOAT: brasl %r14, bar@PLT +; +; CHECK-DOUBLE: foo: +; CHECK-DOUBLE: lzdr %f2 +; CHECK-DOUBLE: lcdbr %f6, %f2 +; CHECK-DOUBLE: brasl %r14, bar@PLT +; +; CHECK-FP128-1: foo: +; CHECK-FP128-1: aghi %r15, -256 +; CHECK-FP128-1: lzxr %f0 +; CHECK-FP128-1: std %f0, 224(%r15) +; CHECK-FP128-1: std %f2, 232(%r15) +; CHECK-FP128-1: brasl %r14, bar@PLT +; +; CHECK-FP128-2: foo: +; CHECK-FP128-2: aghi %r15, -256 +; CHECK-FP128-2: lzxr %f0 +; CHECK-FP128-2: std %f0, 240(%r15) +; CHECK-FP128-2: std %f2, 248(%r15) +; CHECK-FP128-2: brasl %r14, bar@PLT +; +; CHECK-STACK: foo: +; CHECK-STACK: aghi %r15, -256 +; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15) +; CHECK-STACK: stg [[REGISTER]], 216(%r15) +; CHECK-STACK: mvghi 208(%r15), 0 +; CHECK-STACK: mvhi 204(%r15), 0 +; CHECK-STACK: mvghi 192(%r15), 9 +; CHECK-STACK: mvhi 188(%r15), 8 +; CHECK-STACK: mvhi 180(%r15), 7 +; CHECK-STACK: mvhi 172(%r15), 6 +; CHECK-STACK: mvghi 160(%r15), 5 +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (i8 1, i16 2, i32 3, i64 4, float 0.0, double 0.0, + fp128 0xL00000000000000000000000000000000, i64 5, + float -0.0, double -0.0, i8 6, i16 7, i32 8, i64 9, float 0.0, + double 0.0, fp128 0xL00000000000000000000000000000000) + ret void +} diff --git a/test/CodeGen/SystemZ/args-02.ll b/test/CodeGen/SystemZ/args-02.ll new file mode 100644 index 000000000000..9ea111c2e021 --- /dev/null +++ b/test/CodeGen/SystemZ/args-02.ll @@ -0,0 +1,76 @@ +; Test the handling of GPR, FPR and stack arguments when integers are +; sign-extended. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-DOUBLE +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK + +declare void @bar(i8 signext, i16 signext, i32 signext, i64, float, double, + fp128, i64, float, double, i8 signext, i16 signext, + i32 signext, i64, float, double, fp128) + +; There are two indirect fp128 slots, one at offset 224 (the first available +; byte after the outgoing arguments) and one immediately after it at 240. +; These slots should be set up outside the glued call sequence, so would +; normally use %f0/%f2 as the first available 128-bit pair. This choice +; is hard-coded in the FP128 tests. +; +; The order of the CHECK-INT loads doesn't matter. The same goes for the +; CHECK_FP128-* stores and the CHECK-STACK stores. It would be OK to reorder +; them in response to future code changes. +define void @foo() { +; CHECK-INT: foo: +; CHECK-INT: lghi %r2, -1 +; CHECK-INT: lghi %r3, -2 +; CHECK-INT: lghi %r4, -3 +; CHECK-INT: lghi %r5, -4 +; CHECK-INT: la %r6, {{224|240}}(%r15) +; CHECK-INT: brasl %r14, bar@PLT +; +; CHECK-FLOAT: foo: +; CHECK-FLOAT: lzer %f0 +; CHECK-FLOAT: lcebr %f4, %f0 +; CHECK-FLOAT: brasl %r14, bar@PLT +; +; CHECK-DOUBLE: foo: +; CHECK-DOUBLE: lzdr %f2 +; CHECK-DOUBLE: lcdbr %f6, %f2 +; CHECK-DOUBLE: brasl %r14, bar@PLT +; +; CHECK-FP128-1: foo: +; CHECK-FP128-1: aghi %r15, -256 +; CHECK-FP128-1: lzxr %f0 +; CHECK-FP128-1: std %f0, 224(%r15) +; CHECK-FP128-1: std %f2, 232(%r15) +; CHECK-FP128-1: brasl %r14, bar@PLT +; +; CHECK-FP128-2: foo: +; CHECK-FP128-2: aghi %r15, -256 +; CHECK-FP128-2: lzxr %f0 +; CHECK-FP128-2: std %f0, 240(%r15) +; CHECK-FP128-2: std %f2, 248(%r15) +; CHECK-FP128-2: brasl %r14, bar@PLT +; +; CHECK-STACK: foo: +; CHECK-STACK: aghi %r15, -256 +; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15) +; CHECK-STACK: stg [[REGISTER]], 216(%r15) +; CHECK-STACK: mvghi 208(%r15), 0 +; CHECK-STACK: mvhi 204(%r15), 0 +; CHECK-STACK: mvghi 192(%r15), -9 +; CHECK-STACK: mvghi 184(%r15), -8 +; CHECK-STACK: mvghi 176(%r15), -7 +; CHECK-STACK: mvghi 168(%r15), -6 +; CHECK-STACK: mvghi 160(%r15), -5 +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (i8 -1, i16 -2, i32 -3, i64 -4, float 0.0, double 0.0, + fp128 0xL00000000000000000000000000000000, i64 -5, + float -0.0, double -0.0, i8 -6, i16 -7, i32 -8, i64 -9, + float 0.0, double 0.0, + fp128 0xL00000000000000000000000000000000) + ret void +} diff --git a/test/CodeGen/SystemZ/args-03.ll b/test/CodeGen/SystemZ/args-03.ll new file mode 100644 index 000000000000..f954d584fcf4 --- /dev/null +++ b/test/CodeGen/SystemZ/args-03.ll @@ -0,0 +1,78 @@ +; Test the handling of GPR, FPR and stack arguments when integers are +; zero-extended. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-INT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FLOAT +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-DOUBLE +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-FP128-2 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-STACK + +declare void @bar(i8 zeroext, i16 zeroext, i32 zeroext, i64, float, double, + fp128, i64, float, double, i8 zeroext, i16 zeroext, + i32 zeroext, i64, float, double, fp128) + +; There are two indirect fp128 slots, one at offset 224 (the first available +; byte after the outgoing arguments) and one immediately after it at 240. +; These slots should be set up outside the glued call sequence, so would +; normally use %f0/%f2 as the first available 128-bit pair. This choice +; is hard-coded in the FP128 tests. +; +; The order of the CHECK-INT loads doesn't matter. The same goes for the +; CHECK_FP128-* stores and the CHECK-STACK stores. It would be OK to reorder +; them in response to future code changes. +define void @foo() { +; CHECK-INT: foo: +; CHECK-INT: lghi %r2, 255 +; CHECK-INT: llill %r3, 65534 +; CHECK-INT: llilf %r4, 4294967293 +; CHECK-INT: lghi %r5, -4 +; CHECK-INT: la %r6, {{224|240}}(%r15) +; CHECK-INT: brasl %r14, bar@PLT +; +; CHECK-FLOAT: foo: +; CHECK-FLOAT: lzer %f0 +; CHECK-FLOAT: lcebr %f4, %f0 +; CHECK-FLOAT: brasl %r14, bar@PLT +; +; CHECK-DOUBLE: foo: +; CHECK-DOUBLE: lzdr %f2 +; CHECK-DOUBLE: lcdbr %f6, %f2 +; CHECK-DOUBLE: brasl %r14, bar@PLT +; +; CHECK-FP128-1: foo: +; CHECK-FP128-1: aghi %r15, -256 +; CHECK-FP128-1: lzxr %f0 +; CHECK-FP128-1: std %f0, 224(%r15) +; CHECK-FP128-1: std %f2, 232(%r15) +; CHECK-FP128-1: brasl %r14, bar@PLT +; +; CHECK-FP128-2: foo: +; CHECK-FP128-2: aghi %r15, -256 +; CHECK-FP128-2: lzxr %f0 +; CHECK-FP128-2: std %f0, 240(%r15) +; CHECK-FP128-2: std %f2, 248(%r15) +; CHECK-FP128-2: brasl %r14, bar@PLT +; +; CHECK-STACK: foo: +; CHECK-STACK: aghi %r15, -256 +; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15) +; CHECK-STACK: stg [[REGISTER]], 216(%r15) +; CHECK-STACK: llilf [[AT184:%r[0-5]+]], 4294967288 +; CHECK-STACK: stg [[AT184]], 184(%r15) +; CHECK-STACK: llill [[AT176:%r[0-5]+]], 65529 +; CHECK-STACK: stg [[AT176]], 176(%r15) +; CHECK-STACK: mvghi 208(%r15), 0 +; CHECK-STACK: mvhi 204(%r15), 0 +; CHECK-STACK: mvghi 192(%r15), -9 +; CHECK-STACK: mvghi 168(%r15), 250 +; CHECK-STACK: mvghi 160(%r15), -5 +; CHECK-STACK: brasl %r14, bar@PLT + + call void @bar (i8 -1, i16 -2, i32 -3, i64 -4, float 0.0, double 0.0, + fp128 0xL00000000000000000000000000000000, i64 -5, + float -0.0, double -0.0, i8 -6, i16 -7, i32 -8, i64 -9, + float 0.0, double 0.0, + fp128 0xL00000000000000000000000000000000) + ret void +} diff --git a/test/CodeGen/SystemZ/args-04.ll b/test/CodeGen/SystemZ/args-04.ll new file mode 100644 index 000000000000..8340494ff4dc --- /dev/null +++ b/test/CodeGen/SystemZ/args-04.ll @@ -0,0 +1,126 @@ +; Test incoming GPR, FPR and stack arguments when no extension type is given. +; This type of argument is used for passing structures, etc. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Do some arithmetic so that we can see the register being used. +define i8 @f1(i8 %r2) { +; CHECK: f1: +; CHECK: ahi %r2, 1 +; CHECK: br %r14 + %y = add i8 %r2, 1 + ret i8 %y +} + +define i16 @f2(i8 %r2, i16 %r3) { +; CHECK: f2: +; CHECK: {{lr|lgr}} %r2, %r3 +; CHECK: br %r14 + ret i16 %r3 +} + +define i32 @f3(i8 %r2, i16 %r3, i32 %r4) { +; CHECK: f3: +; CHECK: {{lr|lgr}} %r2, %r4 +; CHECK: br %r14 + ret i32 %r4 +} + +define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) { +; CHECK: f4: +; CHECK: {{lr|lgr}} %r2, %r5 +; CHECK: br %r14 + ret i64 %r5 +} + +; Do some arithmetic so that we can see the register being used. +define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) { +; CHECK: f5: +; CHECK: aebr %f0, %f0 +; CHECK: br %r14 + %y = fadd float %f0, %f0 + ret float %y +} + +define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) { +; CHECK: f6: +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + ret double %f2 +} + +; fp128s are passed indirectly. Do some arithmetic so that the value +; must be interpreted as a float, rather than as a block of memory to +; be copied. +define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6) { +; CHECK: f7: +; CHECK: ld %f0, 0(%r6) +; CHECK: ld %f2, 8(%r6) +; CHECK: axbr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %y = fadd fp128 %r6, %r6 + store fp128 %y, fp128 *%r2 + ret void +} + +define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1) { +; CHECK: f8: +; CHECK: lg %r2, 160(%r15) +; CHECK: br %r14 + ret i64 %s1 +} + +define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1, float %f4) { +; CHECK: f9: +; CHECK: ler %f0, %f4 +; CHECK: br %r14 + ret float %f4 +} + +define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1, float %f4, double %f6) { +; CHECK: f10: +; CHECK: ldr %f0, %f6 +; CHECK: br %r14 + ret double %f6 +} + +define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) { +; CHECK: f11: +; CHECK: lg %r2, 168(%r15) +; CHECK: br %r14 + ret i64 %s2 +} + +; Floats are passed right-justified. +define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2, + float %s3) { +; CHECK: f12: +; CHECK: le %f0, 180(%r15) +; CHECK: br %r14 + ret float %s3 +} + +; Test a case where the fp128 address is passed on the stack. +define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2, + fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2, + float %s3, fp128 %s4) { +; CHECK: f13: +; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15) +; CHECK: ld %f0, 0([[REGISTER]]) +; CHECK: ld %f2, 8([[REGISTER]]) +; CHECK: axbr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %y = fadd fp128 %s4, %s4 + store fp128 %y, fp128 *%r2 + ret void +} diff --git a/test/CodeGen/SystemZ/args-05.ll b/test/CodeGen/SystemZ/args-05.ll new file mode 100644 index 000000000000..9fa193a68e57 --- /dev/null +++ b/test/CodeGen/SystemZ/args-05.ll @@ -0,0 +1,47 @@ +; Test that we take advantage of signext and zeroext annotations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Zero extension of something that is already zero-extended. +define void @f1(i32 zeroext %r2, i64 *%r3) { +; CHECK: f1: +; CHECK-NOT: %r2 +; CHECK: stg %r2, 0(%r3) +; CHECK: br %r14 + %conv = zext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Sign extension of something that is already sign-extended. +define void @f2(i32 signext %r2, i64 *%r3) { +; CHECK: f2: +; CHECK-NOT: %r2 +; CHECK: stg %r2, 0(%r3) +; CHECK: br %r14 + %conv = sext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Sign extension of something that is already zero-extended. +define void @f3(i32 zeroext %r2, i64 *%r3) { +; CHECK: f3: +; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2 +; CHECK: stg [[REGISTER]], 0(%r3) +; CHECK: br %r14 + %conv = sext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} + +; Zero extension of something that is already sign-extended. +define void @f4(i32 signext %r2, i64 *%r3) { +; CHECK: f4: +; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2 +; CHECK: stg [[REGISTER]], 0(%r3) +; CHECK: br %r14 + %conv = zext i32 %r2 to i64 + store i64 %conv, i64* %r3 + ret void +} diff --git a/test/CodeGen/SystemZ/args-06.ll b/test/CodeGen/SystemZ/args-06.ll new file mode 100644 index 000000000000..b2f8bee2c6b5 --- /dev/null +++ b/test/CodeGen/SystemZ/args-06.ll @@ -0,0 +1,76 @@ +; Test the padding of unextended integer stack parameters. These are used +; to pass structures. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) { +; CHECK: f1: +; CHECK: ar %r2, %r3 +; CHECK: ar %r2, %r4 +; CHECK: ar %r2, %r5 +; CHECK: ar %r2, %r6 +; CHECK: lb {{%r[0-5]}}, 167(%r15) +; CHECK: lb {{%r[0-5]}}, 175(%r15) +; CHECK: br %r14 + %addb = add i8 %a, %b + %addc = add i8 %addb, %c + %addd = add i8 %addc, %d + %adde = add i8 %addd, %e + %addf = add i8 %adde, %f + %addg = add i8 %addf, %g + ret i8 %addg +} + +define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) { +; CHECK: f2: +; CHECK: ar %r2, %r3 +; CHECK: ar %r2, %r4 +; CHECK: ar %r2, %r5 +; CHECK: ar %r2, %r6 +; CHECK: lh {{%r[0-5]}}, 166(%r15) +; CHECK: lh {{%r[0-5]}}, 174(%r15) +; CHECK: br %r14 + %addb = add i16 %a, %b + %addc = add i16 %addb, %c + %addd = add i16 %addc, %d + %adde = add i16 %addd, %e + %addf = add i16 %adde, %f + %addg = add i16 %addf, %g + ret i16 %addg +} + +define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) { +; CHECK: f3: +; CHECK: ar %r2, %r3 +; CHECK: ar %r2, %r4 +; CHECK: ar %r2, %r5 +; CHECK: ar %r2, %r6 +; CHECK: a %r2, 164(%r15) +; CHECK: a %r2, 172(%r15) +; CHECK: br %r14 + %addb = add i32 %a, %b + %addc = add i32 %addb, %c + %addd = add i32 %addc, %d + %adde = add i32 %addd, %e + %addf = add i32 %adde, %f + %addg = add i32 %addf, %g + ret i32 %addg +} + +define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) { +; CHECK: f4: +; CHECK: agr %r2, %r3 +; CHECK: agr %r2, %r4 +; CHECK: agr %r2, %r5 +; CHECK: agr %r2, %r6 +; CHECK: ag %r2, 160(%r15) +; CHECK: ag %r2, 168(%r15) +; CHECK: br %r14 + %addb = add i64 %a, %b + %addc = add i64 %addb, %c + %addd = add i64 %addc, %d + %adde = add i64 %addd, %e + %addf = add i64 %adde, %f + %addg = add i64 %addf, %g + ret i64 %addg +} diff --git a/test/CodeGen/SystemZ/asm-01.ll b/test/CodeGen/SystemZ/asm-01.ll new file mode 100644 index 000000000000..016d04c614cb --- /dev/null +++ b/test/CodeGen/SystemZ/asm-01.ll @@ -0,0 +1,61 @@ +; Test the "Q" asm constraint, which accepts addresses that have a base +; and a 12-bit displacement. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest range. +define void @f1(i64 %base) { +; CHECK: f1: +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %addr = inttoptr i64 %base to i64 * + call void asm "blah $0", "=*Q" (i64 *%addr) + ret void +} + +; Check the next lowest byte. +define void @f2(i64 %base) { +; CHECK: f2: +; CHECK: aghi %r2, -1 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, -1 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*Q" (i64 *%addr) + ret void +} + +; Check the highest range. +define void @f3(i64 %base) { +; CHECK: f3: +; CHECK: blah 4095(%r2) +; CHECK: br %r14 + %add = add i64 %base, 4095 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*Q" (i64 *%addr) + ret void +} + +; Check the next highest byte. +define void @f4(i64 %base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, 4096 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*Q" (i64 *%addr) + ret void +} + +; Check that indices aren't allowed +define void @f5(i64 %base, i64 %index) { +; CHECK: f5: +; CHECK: agr %r2, %r3 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, %index + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*Q" (i64 *%addr) + ret void +} diff --git a/test/CodeGen/SystemZ/asm-02.ll b/test/CodeGen/SystemZ/asm-02.ll new file mode 100644 index 000000000000..12d8bec161ce --- /dev/null +++ b/test/CodeGen/SystemZ/asm-02.ll @@ -0,0 +1,52 @@ +; Test the "R" asm constraint, which accepts addresses that have a base, +; an index and a 12-bit displacement. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest range. +define void @f1(i64 %base) { +; CHECK: f1: +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %addr = inttoptr i64 %base to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; Check the next lowest byte. +define void @f2(i64 %base) { +; CHECK: f2: +; CHECK: aghi %r2, -1 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, -1 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; Check the highest range. +define void @f3(i64 %base) { +; CHECK: f3: +; CHECK: blah 4095(%r2) +; CHECK: br %r14 + %add = add i64 %base, 4095 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; Check the next highest byte. +define void @f4(i64 %base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %add = add i64 %base, 4096 + %addr = inttoptr i64 %add to i64 * + call void asm "blah $0", "=*R" (i64 *%addr) + ret void +} + +; FIXME: at the moment the precise constraint is not passed down to +; target code, so we must conservatively treat "R" as "Q". diff --git a/test/CodeGen/SystemZ/asm-03.ll b/test/CodeGen/SystemZ/asm-03.ll new file mode 100644 index 000000000000..a6f3f2a5cb60 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-03.ll @@ -0,0 +1,16 @@ +; Test the "S" asm constraint, which accepts addresses that have a base +; and a 20-bit displacement. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i64 %base) { +; CHECK: f1: +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %addr = inttoptr i64 %base to i64 * + call void asm "blah $0", "=*S" (i64 *%addr) + ret void +} + +; FIXME: at the moment the precise constraint is not passed down to +; target code, so we must conservatively treat "S" as "Q". diff --git a/test/CodeGen/SystemZ/asm-04.ll b/test/CodeGen/SystemZ/asm-04.ll new file mode 100644 index 000000000000..0560949eb069 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-04.ll @@ -0,0 +1,16 @@ +; Test the "T" asm constraint, which accepts addresses that have a base, +; an index and a 20-bit displacement. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i64 %base) { +; CHECK: f1: +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %addr = inttoptr i64 %base to i64 * + call void asm "blah $0", "=*T" (i64 *%addr) + ret void +} + +; FIXME: at the moment the precise constraint is not passed down to +; target code, so we must conservatively treat "T" as "Q". diff --git a/test/CodeGen/SystemZ/asm-05.ll b/test/CodeGen/SystemZ/asm-05.ll new file mode 100644 index 000000000000..dae90b09eafe --- /dev/null +++ b/test/CodeGen/SystemZ/asm-05.ll @@ -0,0 +1,15 @@ +; Test the "m" asm constraint, which is equivalent to "T". +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i64 %base) { +; CHECK: f1: +; CHECK: blah 0(%r2) +; CHECK: br %r14 + %addr = inttoptr i64 %base to i64 * + call void asm "blah $0", "=*m" (i64 *%addr) + ret void +} + +; FIXME: at the moment the precise constraint is not passed down to +; target code, so we must conservatively treat "m" as "Q". diff --git a/test/CodeGen/SystemZ/asm-06.ll b/test/CodeGen/SystemZ/asm-06.ll new file mode 100644 index 000000000000..c0e24a366486 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-06.ll @@ -0,0 +1,39 @@ +; Test the GPR constraint "a", which forbids %r0. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i64 @f1() { +; CHECK: f1: +; CHECK: lhi %r1, 1 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i8 1) + ret i64 %val +} + +define i64 @f2() { +; CHECK: f2: +; CHECK: lhi %r1, 2 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i16 2) + ret i64 %val +} + +define i64 @f3() { +; CHECK: f3: +; CHECK: lhi %r1, 3 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i32 3) + ret i64 %val +} + +define i64 @f4() { +; CHECK: f4: +; CHECK: lghi %r1, 4 +; CHECK: blah %r2 %r1 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,a" (i64 4) + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/asm-07.ll b/test/CodeGen/SystemZ/asm-07.ll new file mode 100644 index 000000000000..e07286d9a4d6 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-07.ll @@ -0,0 +1,39 @@ +; Test the GPR constraint "r". +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i64 @f1() { +; CHECK: f1: +; CHECK: lhi %r0, 1 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,r" (i8 1) + ret i64 %val +} + +define i64 @f2() { +; CHECK: f2: +; CHECK: lhi %r0, 2 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,r" (i16 2) + ret i64 %val +} + +define i64 @f3() { +; CHECK: f3: +; CHECK: lhi %r0, 3 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,r" (i32 3) + ret i64 %val +} + +define i64 @f4() { +; CHECK: f4: +; CHECK: lghi %r0, 4 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=r,r" (i64 4) + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/asm-08.ll b/test/CodeGen/SystemZ/asm-08.ll new file mode 100644 index 000000000000..15abc4d0d2ed --- /dev/null +++ b/test/CodeGen/SystemZ/asm-08.ll @@ -0,0 +1,39 @@ +; Test the GPR constraint "d", which is equivalent to "r". +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i64 @f1() { +; CHECK: f1: +; CHECK: lhi %r0, 1 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=d,d" (i8 1) + ret i64 %val +} + +define i64 @f2() { +; CHECK: f2: +; CHECK: lhi %r0, 2 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=d,d" (i16 2) + ret i64 %val +} + +define i64 @f3() { +; CHECK: f3: +; CHECK: lhi %r0, 3 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=d,d" (i32 3) + ret i64 %val +} + +define i64 @f4() { +; CHECK: f4: +; CHECK: lghi %r0, 4 +; CHECK: blah %r2 %r0 +; CHECK: br %r14 + %val = call i64 asm "blah $0 $1", "=d,d" (i64 4) + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/asm-09.ll b/test/CodeGen/SystemZ/asm-09.ll new file mode 100644 index 000000000000..1541170924b7 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-09.ll @@ -0,0 +1,83 @@ +; Test matching operands with the GPR constraint "r". +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i32 *%dst) { +; CHECK: f1: +; CHECK: lhi %r0, 100 +; CHECK: blah %r0 +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = call i32 asm "blah $0", "=r,0" (i8 100) + store i32 %val, i32 *%dst + ret void +} + +define void @f2(i32 *%dst) { +; CHECK: f2: +; CHECK: lhi %r0, 101 +; CHECK: blah %r0 +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = call i32 asm "blah $0", "=r,0" (i16 101) + store i32 %val, i32 *%dst + ret void +} + +define void @f3(i32 *%dst) { +; CHECK: f3: +; CHECK: lhi %r0, 102 +; CHECK: blah %r0 +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = call i32 asm "blah $0", "=r,0" (i32 102) + store i32 %val, i32 *%dst + ret void +} + +; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103". +define void @f4(i32 *%dst) { +; CHECK: f4: +; CHECK: blah %r0 +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = call i32 asm "blah $0", "=r,0" (i64 103) + store i32 %val, i32 *%dst + ret void +} + +define i64 @f5() { +; CHECK: f5: +; CHECK: lghi %r2, 104 +; CHECK: blah %r2 +; CHECK: br %r14 + %val = call i64 asm "blah $0", "=r,0" (i8 104) + ret i64 %val +} + +define i64 @f6() { +; CHECK: f6: +; CHECK: lghi %r2, 105 +; CHECK: blah %r2 +; CHECK: br %r14 + %val = call i64 asm "blah $0", "=r,0" (i16 105) + ret i64 %val +} + +define i64 @f7() { +; CHECK: f7: +; CHECK: lghi %r2, 106 +; CHECK: blah %r2 +; CHECK: br %r14 + %val = call i64 asm "blah $0", "=r,0" (i32 106) + ret i64 %val +} + +define i64 @f8() { +; CHECK: f8: +; CHECK: lghi %r2, 107 +; CHECK: blah %r2 +; CHECK: br %r14 + %val = call i64 asm "blah $0", "=r,0" (i64 107) + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/asm-10.ll b/test/CodeGen/SystemZ/asm-10.ll new file mode 100644 index 000000000000..676c2028b056 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-10.ll @@ -0,0 +1,30 @@ +; Test the FPR constraint "f". +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define float @f1() { +; CHECK: f1: +; CHECK: lzer %f1 +; CHECK: blah %f0 %f1 +; CHECK: br %r14 + %val = call float asm "blah $0 $1", "=&f,f" (float 0.0) + ret float %val +} + +define double @f2() { +; CHECK: f2: +; CHECK: lzdr %f1 +; CHECK: blah %f0 %f1 +; CHECK: br %r14 + %val = call double asm "blah $0 $1", "=&f,f" (double 0.0) + ret double %val +} + +define double @f3() { +; CHECK: f3: +; CHECK: lzxr %f1 +; CHECK: blah %f0 %f1 +; CHECK: br %r14 + %val = call double asm "blah $0 $1", "=&f,f" (fp128 0xL00000000000000000000000000000000) + ret double %val +} diff --git a/test/CodeGen/SystemZ/asm-11.ll b/test/CodeGen/SystemZ/asm-11.ll new file mode 100644 index 000000000000..9bd8d7c33f01 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-11.ll @@ -0,0 +1,41 @@ +; Test the "I" constraint (8-bit unsigned constants). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the first valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: lhi [[REG:%r[0-5]]], -1 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 -1) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 0 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0) + ret i32 %val +} + +; Test the last valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: blah %r2 255 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255) + ret i32 %val +} + +; Test 1 above the last valid value. +define i32 @f4() { +; CHECK: f4: +; CHECK: lhi [[REG:%r[0-5]]], 256 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rI" (i32 256) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/asm-12.ll b/test/CodeGen/SystemZ/asm-12.ll new file mode 100644 index 000000000000..dd920f11fdec --- /dev/null +++ b/test/CodeGen/SystemZ/asm-12.ll @@ -0,0 +1,41 @@ +; Test the "J" constraint (12-bit unsigned constants). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the first valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: lhi [[REG:%r[0-5]]], -1 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 -1) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 0 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0) + ret i32 %val +} + +; Test the last valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: blah %r2 4095 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095) + ret i32 %val +} + +; Test 1 above the last valid value. +define i32 @f4() { +; CHECK: f4: +; CHECK: lhi [[REG:%r[0-5]]], 4096 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4096) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/asm-13.ll b/test/CodeGen/SystemZ/asm-13.ll new file mode 100644 index 000000000000..af3fdb361533 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-13.ll @@ -0,0 +1,41 @@ +; Test the "K" constraint (16-bit signed constants). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the first valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: iilf [[REG:%r[0-5]]], 4294934527 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32769) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 -32768 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768) + ret i32 %val +} + +; Test the last valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: blah %r2 32767 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767) + ret i32 %val +} + +; Test 1 above the last valid value. +define i32 @f4() { +; CHECK: f4: +; CHECK: llill [[REG:%r[0-5]]], 32768 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32768) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/asm-14.ll b/test/CodeGen/SystemZ/asm-14.ll new file mode 100644 index 000000000000..b6b28d6b32fc --- /dev/null +++ b/test/CodeGen/SystemZ/asm-14.ll @@ -0,0 +1,41 @@ +; Test the "L" constraint (20-bit signed constants). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the first valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: iilf [[REG:%r[0-5]]], 4294443007 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524289) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 -524288 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288) + ret i32 %val +} + +; Test the last valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: blah %r2 524287 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287) + ret i32 %val +} + +; Test 1 above the last valid value. +define i32 @f4() { +; CHECK: f4: +; CHECK: llilh [[REG:%r[0-5]]], 8 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524288) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/asm-15.ll b/test/CodeGen/SystemZ/asm-15.ll new file mode 100644 index 000000000000..4d0e2b4c3be3 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-15.ll @@ -0,0 +1,32 @@ +; Test the "M" constraint (0x7fffffff) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: iilf [[REG:%r[0-5]]], 2147483646 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 2147483647 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647) + ret i32 %val +} + +; Test 1 above the valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: llilh [[REG:%r[0-5]]], 32768 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483648) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/asm-16.ll b/test/CodeGen/SystemZ/asm-16.ll new file mode 100644 index 000000000000..4d0e2b4c3be3 --- /dev/null +++ b/test/CodeGen/SystemZ/asm-16.ll @@ -0,0 +1,32 @@ +; Test the "M" constraint (0x7fffffff) +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 1 below the valid value. +define i32 @f1() { +; CHECK: f1: +; CHECK: iilf [[REG:%r[0-5]]], 2147483646 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483646) + ret i32 %val +} + +; Test the first valid value. +define i32 @f2() { +; CHECK: f2: +; CHECK: blah %r2 2147483647 +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647) + ret i32 %val +} + +; Test 1 above the valid value. +define i32 @f3() { +; CHECK: f3: +; CHECK: llilh [[REG:%r[0-5]]], 32768 +; CHECK: blah %r2 [[REG]] +; CHECK: br %r14 + %val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483648) + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/atomic-load-01.ll b/test/CodeGen/SystemZ/atomic-load-01.ll new file mode 100644 index 000000000000..3e86bcf78ae6 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-load-01.ll @@ -0,0 +1,13 @@ +; Test 8-bit atomic loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that loads are handled. +; The CS-based sequence is probably far too conservative. +define i8 @f1(i8 *%src) { +; CHECK: f1: +; CHECK: cs +; CHECK: br %r14 + %val = load atomic i8 *%src seq_cst, align 1 + ret i8 %val +} diff --git a/test/CodeGen/SystemZ/atomic-load-02.ll b/test/CodeGen/SystemZ/atomic-load-02.ll new file mode 100644 index 000000000000..d6168cedb8a8 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-load-02.ll @@ -0,0 +1,13 @@ +; Test 16-bit atomic loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that loads are handled. +; The CS-based sequence is probably far too conservative. +define i16 @f1(i16 *%src) { +; CHECK: f1: +; CHECK: cs +; CHECK: br %r14 + %val = load atomic i16 *%src seq_cst, align 2 + ret i16 %val +} diff --git a/test/CodeGen/SystemZ/atomic-load-03.ll b/test/CodeGen/SystemZ/atomic-load-03.ll new file mode 100644 index 000000000000..fcf0cf3d5a90 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-load-03.ll @@ -0,0 +1,14 @@ +; Test 32-bit atomic loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that loads are handled. +; Using CS is probably too conservative. +define i32 @f1(i32 %dummy, i32 *%src) { +; CHECK: f1: +; CHECK: lhi %r2, 0 +; CHECK: cs %r2, %r2, 0(%r3) +; CHECK: br %r14 + %val = load atomic i32 *%src seq_cst, align 4 + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/atomic-load-04.ll b/test/CodeGen/SystemZ/atomic-load-04.ll new file mode 100644 index 000000000000..9593d35fef0c --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-load-04.ll @@ -0,0 +1,14 @@ +; Test 64-bit atomic loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that loads are handled. +; Using CSG is probably too conservative. +define i64 @f1(i64 %dummy, i64 *%src) { +; CHECK: f1: +; CHECK: lghi %r2, 0 +; CHECK: csg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %val = load atomic i64 *%src seq_cst, align 8 + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/atomic-store-01.ll b/test/CodeGen/SystemZ/atomic-store-01.ll new file mode 100644 index 000000000000..b316e5cd6309 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-store-01.ll @@ -0,0 +1,13 @@ +; Test 8-bit atomic stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that stores are handled. +; The CS-based sequence is probably far too conservative. +define void @f1(i8 %val, i8 *%src) { +; CHECK: f1: +; CHECK: cs +; CHECK: br %r14 + store atomic i8 %val, i8 *%src seq_cst, align 1 + ret void +} diff --git a/test/CodeGen/SystemZ/atomic-store-02.ll b/test/CodeGen/SystemZ/atomic-store-02.ll new file mode 100644 index 000000000000..c76171431883 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-store-02.ll @@ -0,0 +1,13 @@ +; Test 16-bit atomic stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that stores are handled. +; The CS-based sequence is probably far too conservative. +define void @f1(i16 %val, i16 *%src) { +; CHECK: f1: +; CHECK: cs +; CHECK: br %r14 + store atomic i16 %val, i16 *%src seq_cst, align 2 + ret void +} diff --git a/test/CodeGen/SystemZ/atomic-store-03.ll b/test/CodeGen/SystemZ/atomic-store-03.ll new file mode 100644 index 000000000000..6e2996313db6 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-store-03.ll @@ -0,0 +1,16 @@ +; Test 32-bit atomic stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that stores are handled. +; Using CS is probably too conservative. +define void @f1(i32 %val, i32 *%src) { +; CHECK: f1: +; CHECK: l %r0, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: cs %r0, %r2, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + store atomic i32 %val, i32 *%src seq_cst, align 4 + ret void +} diff --git a/test/CodeGen/SystemZ/atomic-store-04.ll b/test/CodeGen/SystemZ/atomic-store-04.ll new file mode 100644 index 000000000000..7a611c8cf081 --- /dev/null +++ b/test/CodeGen/SystemZ/atomic-store-04.ll @@ -0,0 +1,16 @@ +; Test 64-bit atomic stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is just a placeholder to make sure that stores are handled. +; Using CS is probably too conservative. +define void @f1(i64 %val, i64 *%src) { +; CHECK: f1: +; CHECK: lg %r0, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: csg %r0, %r2, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + store atomic i64 %val, i64 *%src seq_cst, align 8 + ret void +} diff --git a/test/CodeGen/SystemZ/atomicrmw-add-01.ll b/test/CodeGen/SystemZ/atomicrmw-add-01.ll new file mode 100644 index 000000000000..2a84857f836d --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-add-01.ll @@ -0,0 +1,132 @@ +; Test 8-bit atomic additions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check addition of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: ar [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We add 0x80000000 to the rotated word. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: afi [[ROT]], -2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check addition of -1. We add 0xff000000 to the rotated word. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: afi [[ROT]], -16777216 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 -1 seq_cst + ret i8 %res +} + +; Check addition of 1. We add 0x01000000 to the rotated word. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: afi [[ROT]], 16777216 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We add 0x7f000000 to the rotated word. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: afi [[ROT]], 2130706432 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check addition of a large unsigned value. We add 0xfe000000 to the +; rotated word, expressed as a negative AFI operand. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: afi [[ROT]], -33554432 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i8 *%src, i8 254 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-add-02.ll b/test/CodeGen/SystemZ/atomicrmw-add-02.ll new file mode 100644 index 000000000000..3dd482dd323d --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-add-02.ll @@ -0,0 +1,132 @@ +; Test 16-bit atomic additions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check addition of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: ar [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We add 0x80000000 to the rotated word. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: afi [[ROT]], -2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check addition of -1. We add 0xffff0000 to the rotated word. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: afi [[ROT]], -65536 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 -1 seq_cst + ret i16 %res +} + +; Check addition of 1. We add 0x00010000 to the rotated word. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: afi [[ROT]], 65536 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We add 0x7fff0000 to the rotated word. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: afi [[ROT]], 2147418112 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check addition of a large unsigned value. We add 0xfffe0000 to the +; rotated word, expressed as a negative AFI operand. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: afi [[ROT]], -131072 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw add i16 *%src, i16 65534 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-add-03.ll b/test/CodeGen/SystemZ/atomicrmw-add-03.ll new file mode 100644 index 000000000000..01eb8e0d7464 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-add-03.ll @@ -0,0 +1,94 @@ +; Test 32-bit atomic additions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check addition of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lr %r0, %r2 +; CHECK: ar %r0, %r4 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check addition of 1, which can use AHI. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lr %r0, %r2 +; CHECK: ahi %r0, 1 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check the high end of the AHI range. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: ahi %r0, 32767 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 32767 seq_cst + ret i32 %res +} + +; Check the next value up, which must use AFI. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: afi %r0, 32768 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 32768 seq_cst + ret i32 %res +} + +; Check the high end of the AFI range. +define i32 @f5(i32 %dummy, i32 *%src) { +; CHECK: f5: +; CHECK: afi %r0, 2147483647 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 2147483647 seq_cst + ret i32 %res +} + +; Check the next value up, which gets treated as a negative operand. +define i32 @f6(i32 %dummy, i32 *%src) { +; CHECK: f6: +; CHECK: afi %r0, -2147483648 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 2147483648 seq_cst + ret i32 %res +} + +; Check addition of -1, which can use AHI. +define i32 @f7(i32 %dummy, i32 *%src) { +; CHECK: f7: +; CHECK: ahi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 -1 seq_cst + ret i32 %res +} + +; Check the low end of the AHI range. +define i32 @f8(i32 %dummy, i32 *%src) { +; CHECK: f8: +; CHECK: ahi %r0, -32768 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 -32768 seq_cst + ret i32 %res +} + +; Check the next value down, which must use AFI instead. +define i32 @f9(i32 %dummy, i32 *%src) { +; CHECK: f9: +; CHECK: afi %r0, -32769 +; CHECK: br %r14 + %res = atomicrmw add i32 *%src, i32 -32769 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-add-04.ll b/test/CodeGen/SystemZ/atomicrmw-add-04.ll new file mode 100644 index 000000000000..6b1d20bd080e --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-add-04.ll @@ -0,0 +1,112 @@ +; Test 64-bit atomic additions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check addition of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: agr %r0, %r4 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check addition of 1, which can use AGHI. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: aghi %r0, 1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the high end of the AGHI range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: aghi %r0, 32767 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 32767 seq_cst + ret i64 %res +} + +; Check the next value up, which must use AGFI. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r0, 32768 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 32768 seq_cst + ret i64 %res +} + +; Check the high end of the AGFI range. +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: agfi %r0, 2147483647 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 2147483647 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register addition. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: agr +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 2147483648 seq_cst + ret i64 %res +} + +; Check addition of -1, which can use AGHI. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 -1 seq_cst + ret i64 %res +} + +; Check the low end of the AGHI range. +define i64 @f8(i64 %dummy, i64 *%src) { +; CHECK: f8: +; CHECK: aghi %r0, -32768 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 -32768 seq_cst + ret i64 %res +} + +; Check the next value down, which must use AGFI instead. +define i64 @f9(i64 %dummy, i64 *%src) { +; CHECK: f9: +; CHECK: agfi %r0, -32769 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 -32769 seq_cst + ret i64 %res +} + +; Check the low end of the AGFI range. +define i64 @f10(i64 %dummy, i64 *%src) { +; CHECK: f10: +; CHECK: agfi %r0, -2147483648 +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst + ret i64 %res +} + +; Check the next value down, which must use a register addition. +define i64 @f11(i64 %dummy, i64 *%src) { +; CHECK: f11: +; CHECK: agr +; CHECK: br %r14 + %res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-and-01.ll b/test/CodeGen/SystemZ/atomicrmw-and-01.ll new file mode 100644 index 000000000000..ebbce8e7872b --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-and-01.ll @@ -0,0 +1,133 @@ +; Test 8-bit atomic ANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check AND of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: oilf %r3, 16777215 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We AND the rotated word with 0x80ffffff. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nilh [[ROT]], 33023 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: nilh [[ROT]], 65279 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 -2 seq_cst + ret i8 %res +} + +; Check ANDs of 1. We AND the rotated word with 0x01ffffff. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: nilh [[ROT]], 511 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We AND the rotated word with 0x7fffffff. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: nilh [[ROT]], 32767 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check ANDs of a large unsigned value. We AND the rotated word with +; 0xfdffffff. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: nilh [[ROT]], 65023 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i8 *%src, i8 253 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-and-02.ll b/test/CodeGen/SystemZ/atomicrmw-and-02.ll new file mode 100644 index 000000000000..b63ca4ab4407 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-and-02.ll @@ -0,0 +1,133 @@ +; Test 16-bit atomic ANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check AND of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: oill %r3, 65535 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We AND the rotated word with 0x8000ffff. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nilh [[ROT]], 32768 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: nilh [[ROT]], 65534 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 -2 seq_cst + ret i16 %res +} + +; Check ANDs of 1. We AND the rotated word with 0x0001ffff. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: nilh [[ROT]], 1 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We AND the rotated word with 0x7fffffff. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: nilh [[ROT]], 32767 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check ANDs of a large unsigned value. We AND the rotated word with +; 0xfffdffff. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: nilh [[ROT]], 65533 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw and i16 *%src, i16 65533 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-and-03.ll b/test/CodeGen/SystemZ/atomicrmw-and-03.ll new file mode 100644 index 000000000000..ec69edcf1a47 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-and-03.ll @@ -0,0 +1,85 @@ +; Test 32-bit atomic ANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ANDs of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: nr %r0, %r4 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check ANDs of 1. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: nilf %r0, 1 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check ANDs of the low end of the NILH range. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: nilh %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 65535 seq_cst + ret i32 %res +} + +; Check the next value up, which must use NILF. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: nilf %r0, 65536 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 65536 seq_cst + ret i32 %res +} + +; Check the largest useful NILL value. +define i32 @f5(i32 %dummy, i32 *%src) { +; CHECK: f5: +; CHECK: nill %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 -2 seq_cst + ret i32 %res +} + +; Check the low end of the NILL range. +define i32 @f6(i32 %dummy, i32 *%src) { +; CHECK: f6: +; CHECK: nill %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 -65536 seq_cst + ret i32 %res +} + +; Check the largest useful NILH value, which is one less than the above. +define i32 @f7(i32 %dummy, i32 *%src) { +; CHECK: f7: +; CHECK: nilh %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 -65537 seq_cst + ret i32 %res +} + +; Check the highest useful NILF value, which is one less than the above. +define i32 @f8(i32 %dummy, i32 *%src) { +; CHECK: f8: +; CHECK: nilf %r0, 4294901758 +; CHECK: br %r14 + %res = atomicrmw and i32 *%src, i32 -65538 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-and-04.ll b/test/CodeGen/SystemZ/atomicrmw-and-04.ll new file mode 100644 index 000000000000..71f29baa0e6f --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-and-04.ll @@ -0,0 +1,157 @@ +; Test 64-bit atomic ANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ANDs of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: ngr %r0, %r4 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check ANDs of 1, which must be done using a register. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the low end of the NIHF range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: nihf %r0, 0 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 4294967295 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 4294967296 seq_cst + ret i64 %res +} + +; Check the low end of the NIHH range. +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: nihh %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst + ret i64 %res +} + +; Check the highest useful NILL value. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: nill %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -2 seq_cst + ret i64 %res +} + +; Check the low end of the NILL range. +define i64 @f8(i64 %dummy, i64 *%src) { +; CHECK: f8: +; CHECK: nill %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -65536 seq_cst + ret i64 %res +} + +; Check the highest useful NILH value, which is one less than the above. +define i64 @f9(i64 %dummy, i64 *%src) { +; CHECK: f9: +; CHECK: nilh %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -65537 seq_cst + ret i64 %res +} + +; Check the highest useful NILF value, which is one less than the above. +define i64 @f10(i64 %dummy, i64 *%src) { +; CHECK: f10: +; CHECK: nilf %r0, 4294901758 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -65538 seq_cst + ret i64 %res +} + +; Check the low end of the NILH range. +define i64 @f11(i64 %dummy, i64 *%src) { +; CHECK: f11: +; CHECK: nilh %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst + ret i64 %res +} + +; Check the low end of the NILF range. +define i64 @f12(i64 %dummy, i64 *%src) { +; CHECK: f12: +; CHECK: nilf %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst + ret i64 %res +} + +; Check the highest useful NIHL value, which is one less than the above. +define i64 @f13(i64 %dummy, i64 *%src) { +; CHECK: f13: +; CHECK: nihl %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst + ret i64 %res +} + +; Check the low end of the NIHL range. +define i64 @f14(i64 %dummy, i64 *%src) { +; CHECK: f14: +; CHECK: nihl %r0, 0 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst + ret i64 %res +} + +; Check the highest useful NIHH value, which is 1<<32 less than the above. +define i64 @f15(i64 %dummy, i64 *%src) { +; CHECK: f15: +; CHECK: nihh %r0, 65534 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst + ret i64 %res +} + +; Check the highest useful NIHF value, which is 1<<32 less than the above. +define i64 @f16(i64 %dummy, i64 *%src) { +; CHECK: f16: +; CHECK: nihf %r0, 4294901758 +; CHECK: br %r14 + %res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll new file mode 100644 index 000000000000..c6ec77e91b3d --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-01.ll @@ -0,0 +1,228 @@ +; Test 8-bit atomic min/max operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check signed minimum. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: cr [[ROT]], %r3 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 39, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw min i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check signed maximum. +define i8 @f2(i8 *%src, i8 %b) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: cr [[ROT]], %r3 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 39, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw max i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check unsigned minimum. +define i8 @f3(i8 *%src, i8 %b) { +; CHECK: f3: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: clr [[ROT]], %r3 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 39, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umin i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check unsigned maximum. +define i8 @f4(i8 *%src, i8 %b) { +; CHECK: f4: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: clr [[ROT]], %r3 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 39, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umax i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the lowest useful signed minimum value. We need to load 0x81000000 +; into the source register. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: llilh [[SRC2:%r[0-9]+]], 33024 +; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw min i8 *%src, i8 -127 seq_cst + ret i8 %res +} + +; Check the highest useful signed maximum value. We need to load 0x7e000000 +; into the source register. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: llilh [[SRC2:%r[0-9]+]], 32256 +; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw max i8 *%src, i8 126 seq_cst + ret i8 %res +} + +; Check the lowest useful unsigned minimum value. We need to load 0x01000000 +; into the source register. +define i8 @f7(i8 *%src) { +; CHECK: f7: +; CHECK: llilh [[SRC2:%r[0-9]+]], 256 +; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f7: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f7: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umin i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the highest useful unsigned maximum value. We need to load 0xfe000000 +; into the source register. +define i8 @f8(i8 *%src) { +; CHECK: f8: +; CHECK: llilh [[SRC2:%r[0-9]+]], 65024 +; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f8: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f8: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umax i8 *%src, i8 254 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll new file mode 100644 index 000000000000..9612e99b7387 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-02.ll @@ -0,0 +1,228 @@ +; Test 8-bit atomic min/max operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check signed minimum. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: cr [[ROT]], %r3 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 47, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw min i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check signed maximum. +define i16 @f2(i16 *%src, i16 %b) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: cr [[ROT]], %r3 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 47, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: cr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw max i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check unsigned minimum. +define i16 @f3(i16 *%src, i16 %b) { +; CHECK: f3: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: clr [[ROT]], %r3 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 47, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umin i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check unsigned maximum. +define i16 @f4(i16 *%src, i16 %b) { +; CHECK: f4: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: clr [[ROT]], %r3 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: risbg [[ROT]], %r3, 32, 47, 0 +; CHECK: [[KEEP]]: +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umax i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the lowest useful signed minimum value. We need to load 0x80010000 +; into the source register. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: llilh [[SRC2:%r[0-9]+]], 32769 +; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw min i16 *%src, i16 -32767 seq_cst + ret i16 %res +} + +; Check the highest useful signed maximum value. We need to load 0x7ffe0000 +; into the source register. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: llilh [[SRC2:%r[0-9]+]], 32766 +; CHECK: cr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw max i16 *%src, i16 32766 seq_cst + ret i16 %res +} + +; Check the lowest useful unsigned maximum value. We need to load 0x00010000 +; into the source register. +define i16 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: llilh [[SRC2:%r[0-9]+]], 1 +; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f7: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f7: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umin i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the highest useful unsigned maximum value. We need to load 0xfffe0000 +; into the source register. +define i16 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: llilh [[SRC2:%r[0-9]+]], 65534 +; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]] +; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f8: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f8: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw umax i16 *%src, i16 65534 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll new file mode 100644 index 000000000000..b5809bdc1693 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll @@ -0,0 +1,176 @@ +; Test 32-bit atomic minimum and maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check signed minium. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cr %r2, %r4 +; CHECK: lr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lr [[NEW]], %r4 +; CHECK: cs %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw min i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check signed maximum. +define i32 @f2(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cr %r2, %r4 +; CHECK: lr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: lr [[NEW]], %r4 +; CHECK: cs %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw max i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check unsigned minimum. +define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f3: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: clr %r2, %r4 +; CHECK: lr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lr [[NEW]], %r4 +; CHECK: cs %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw umin i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check unsigned maximum. +define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f4: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: clr %r2, %r4 +; CHECK: lr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: lr [[NEW]], %r4 +; CHECK: cs %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw umax i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the aligned CS range. +define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f5: +; CHECK: l %r2, 4092(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word up, which requires CSY. +define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f6: +; CHECK: ly %r2, 4096(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the aligned CSY range. +define i32 @f7(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f7: +; CHECK: ly %r2, 524284(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word up, which needs separate address logic. +define i32 @f8(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f8: +; CHECK: agfi %r3, 524288 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the negative aligned CSY range. +define i32 @f9(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f9: +; CHECK: ly %r2, -4(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the low end of the CSY range. +define i32 @f10(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f10: +; CHECK: ly %r2, -524288(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word down, which needs separate address logic. +define i32 @f11(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f11: +; CHECK: agfi %r3, -524292 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check that indexed addresses are not allowed. +define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) { +; CHECK: f12: +; CHECK: agr %r3, %r4 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i32 * + %res = atomicrmw min i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check that constants are forced into a register. +define i32 @f13(i32 %dummy, i32 *%ptr) { +; CHECK: f13: +; CHECK: lhi [[LIMIT:%r[0-9]+]], 42 +; CHECK: l %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cr %r2, [[LIMIT]] +; CHECK: lr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lr [[NEW]], [[LIMIT]] +; CHECK: cs %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw min i32 *%ptr, i32 42 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll new file mode 100644 index 000000000000..68978547d3e9 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll @@ -0,0 +1,143 @@ +; Test 64-bit atomic minimum and maximum. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check signed minium. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cgr %r2, %r4 +; CHECK: lgr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lgr [[NEW]], %r4 +; CHECK: csg %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw min i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check signed maximum. +define i64 @f2(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f2: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cgr %r2, %r4 +; CHECK: lgr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: lgr [[NEW]], %r4 +; CHECK: csg %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw max i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check unsigned minimum. +define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f3: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: clgr %r2, %r4 +; CHECK: lgr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lgr [[NEW]], %r4 +; CHECK: csg %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw umin i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check unsigned maximum. +define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f4: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: clgr %r2, %r4 +; CHECK: lgr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}he [[KEEP:\..*]] +; CHECK: lgr [[NEW]], %r4 +; CHECK: csg %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw umax i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check the high end of the aligned CSG range. +define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f5: +; CHECK: lg %r2, 524280(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %res = atomicrmw min i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the next doubleword up, which requires separate address logic. +define i64 @f6(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %res = atomicrmw min i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the low end of the CSG range. +define i64 @f7(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f7: +; CHECK: lg %r2, -524288(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %res = atomicrmw min i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the next doubleword down, which requires separate address logic. +define i64 @f8(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f8: +; CHECK: agfi %r3, -524296 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %res = atomicrmw min i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check that indexed addresses are not allowed. +define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) { +; CHECK: f9: +; CHECK: agr %r3, %r4 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i64 * + %res = atomicrmw min i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check that constants are forced into a register. +define i64 @f10(i64 %dummy, i64 *%ptr) { +; CHECK: f10: +; CHECK: lghi [[LIMIT:%r[0-9]+]], 42 +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LOOP:\.[^:]*]]: +; CHECK: cgr %r2, [[LIMIT]] +; CHECK: lgr [[NEW:%r[0-9]+]], %r2 +; CHECK: j{{g?}}le [[KEEP:\..*]] +; CHECK: lgr [[NEW]], [[LIMIT]] +; CHECK: csg %r2, [[NEW]], 0(%r3) +; CHECK: j{{g?}}lh [[LOOP]] +; CHECK: br %r14 + %res = atomicrmw min i64 *%ptr, i64 42 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-01.ll b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll new file mode 100644 index 000000000000..1ede3b465be2 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-nand-01.ll @@ -0,0 +1,139 @@ +; Test 8-bit atomic NANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check NAND of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nr [[ROT]], %r3 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: oilf %r3, 16777215 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We AND the rotated word with 0x80ffffff. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nilh [[ROT]], 33023 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: nilh [[ROT]], 65279 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 -2 seq_cst + ret i8 %res +} + +; Check NANDs of 1. We AND the rotated word with 0x01ffffff. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: nilh [[ROT]], 511 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We AND the rotated word with 0x7fffffff. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: nilh [[ROT]], 32767 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check NANDs of a large unsigned value. We AND the rotated word with +; 0xfdffffff. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: nilh [[ROT]], 65023 +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i8 *%src, i8 253 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-02.ll b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll new file mode 100644 index 000000000000..d5cf864a3f79 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-nand-02.ll @@ -0,0 +1,139 @@ +; Test 16-bit atomic NANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check NAND of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used, and that the low bits are set to 1. This sequence is +; independent of the other loop prologue instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nr [[ROT]], %r3 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: oill %r3, 65535 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We AND the rotated word with 0x8000ffff. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: nilh [[ROT]], 32768 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: nilh [[ROT]], 65534 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 -2 seq_cst + ret i16 %res +} + +; Check ANDs of 1. We AND the rotated word with 0x0001ffff. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: nilh [[ROT]], 1 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We AND the rotated word with 0x7fffffff. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: nilh [[ROT]], 32767 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check NANDs of a large unsigned value. We AND the rotated word with +; 0xfffdffff. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: nilh [[ROT]], 65533 +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw nand i16 *%src, i16 65533 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-03.ll b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll new file mode 100644 index 000000000000..cc2a0866b391 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-nand-03.ll @@ -0,0 +1,93 @@ +; Test 32-bit atomic NANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check NANDs of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: nr %r0, %r4 +; CHECK: xilf %r0, 4294967295 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check NANDs of 1. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: nilf %r0, 1 +; CHECK: xilf %r0, 4294967295 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check NANDs of the low end of the NILH range. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: nilh %r0, 0 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 65535 seq_cst + ret i32 %res +} + +; Check the next value up, which must use NILF. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: nilf %r0, 65536 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 65536 seq_cst + ret i32 %res +} + +; Check the largest useful NILL value. +define i32 @f5(i32 %dummy, i32 *%src) { +; CHECK: f5: +; CHECK: nill %r0, 65534 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 -2 seq_cst + ret i32 %res +} + +; Check the low end of the NILL range. +define i32 @f6(i32 %dummy, i32 *%src) { +; CHECK: f6: +; CHECK: nill %r0, 0 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 -65536 seq_cst + ret i32 %res +} + +; Check the largest useful NILH value, which is one less than the above. +define i32 @f7(i32 %dummy, i32 *%src) { +; CHECK: f7: +; CHECK: nilh %r0, 65534 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 -65537 seq_cst + ret i32 %res +} + +; Check the highest useful NILF value, which is one less than the above. +define i32 @f8(i32 %dummy, i32 *%src) { +; CHECK: f8: +; CHECK: nilf %r0, 4294901758 +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw nand i32 *%src, i32 -65538 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-nand-04.ll b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll new file mode 100644 index 000000000000..0c857d97fe83 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-nand-04.ll @@ -0,0 +1,183 @@ +; Test 64-bit atomic NANDs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check NANDs of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: ngr %r0, %r4 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check NANDs of 1, which must be done using a register. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the low end of the NIHF range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: nihf %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 4294967295 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst + ret i64 %res +} + +; Check the low end of the NIHH range. +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: nihh %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 281474976710655 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: ngr +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst + ret i64 %res +} + +; Check the highest useful NILL value. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: nill %r0, 65534 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -2 seq_cst + ret i64 %res +} + +; Check the low end of the NILL range. +define i64 @f8(i64 %dummy, i64 *%src) { +; CHECK: f8: +; CHECK: nill %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -65536 seq_cst + ret i64 %res +} + +; Check the highest useful NILH value, which is one less than the above. +define i64 @f9(i64 %dummy, i64 *%src) { +; CHECK: f9: +; CHECK: nilh %r0, 65534 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -65537 seq_cst + ret i64 %res +} + +; Check the highest useful NILF value, which is one less than the above. +define i64 @f10(i64 %dummy, i64 *%src) { +; CHECK: f10: +; CHECK: nilf %r0, 4294901758 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -65538 seq_cst + ret i64 %res +} + +; Check the low end of the NILH range. +define i64 @f11(i64 %dummy, i64 *%src) { +; CHECK: f11: +; CHECK: nilh %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -4294901761 seq_cst + ret i64 %res +} + +; Check the low end of the NILF range. +define i64 @f12(i64 %dummy, i64 *%src) { +; CHECK: f12: +; CHECK: nilf %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -4294967296 seq_cst + ret i64 %res +} + +; Check the highest useful NIHL value, which is one less than the above. +define i64 @f13(i64 %dummy, i64 *%src) { +; CHECK: f13: +; CHECK: nihl %r0, 65534 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -4294967297 seq_cst + ret i64 %res +} + +; Check the low end of the NIHL range. +define i64 @f14(i64 %dummy, i64 *%src) { +; CHECK: f14: +; CHECK: nihl %r0, 0 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -281470681743361 seq_cst + ret i64 %res +} + +; Check the highest useful NIHH value, which is 1<<32 less than the above. +define i64 @f15(i64 %dummy, i64 *%src) { +; CHECK: f15: +; CHECK: nihh %r0, 65534 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -281474976710657 seq_cst + ret i64 %res +} + +; Check the highest useful NIHF value, which is 1<<32 less than the above. +define i64 @f16(i64 %dummy, i64 *%src) { +; CHECK: f16: +; CHECK: nihf %r0, 4294901758 +; CHECK: lcgr %r0, %r0 +; CHECK: aghi %r0, -1 +; CHECK: br %r14 + %res = atomicrmw nand i64 *%src, i64 -281479271677953 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-or-01.ll b/test/CodeGen/SystemZ/atomicrmw-or-01.ll new file mode 100644 index 000000000000..31303b769237 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-or-01.ll @@ -0,0 +1,132 @@ +; Test 8-bit atomic ORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check OR of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: or [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We OR the rotated word with 0x80000000. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: oilh [[ROT]], 32768 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfe000000. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: oilh [[ROT]], 65024 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 -2 seq_cst + ret i8 %res +} + +; Check ORs of 1. We OR the rotated word with 0x01000000. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: oilh [[ROT]], 256 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We OR the rotated word with 0x7f000000. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: oilh [[ROT]], 32512 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check ORs of a large unsigned value. We OR the rotated word with +; 0xfd000000. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: oilh [[ROT]], 64768 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i8 *%src, i8 253 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-or-02.ll b/test/CodeGen/SystemZ/atomicrmw-or-02.ll new file mode 100644 index 000000000000..9880d0b9859f --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-or-02.ll @@ -0,0 +1,132 @@ +; Test 16-bit atomic ORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check OR of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: or [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We OR the rotated word with 0x80000000. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: oilh [[ROT]], 32768 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfffe0000. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: oilh [[ROT]], 65534 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 -2 seq_cst + ret i16 %res +} + +; Check ORs of 1. We OR the rotated word with 0x00010000. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: oilh [[ROT]], 1 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We OR the rotated word with 0x7fff0000. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: oilh [[ROT]], 32767 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check ORs of a large unsigned value. We OR the rotated word with +; 0xfffd0000. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: oilh [[ROT]], 65533 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw or i16 *%src, i16 65533 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-or-03.ll b/test/CodeGen/SystemZ/atomicrmw-or-03.ll new file mode 100644 index 000000000000..33fd21b04c6c --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-or-03.ll @@ -0,0 +1,85 @@ +; Test 32-bit atomic ORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ORs of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: or %r0, %r4 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check the lowest useful OILL value. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: oill %r0, 1 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check the high end of the OILL range. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: oill %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 65535 seq_cst + ret i32 %res +} + +; Check the lowest useful OILH value, which is the next value up. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: oilh %r0, 1 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 65536 seq_cst + ret i32 %res +} + +; Check the lowest useful OILF value, which is the next value up. +define i32 @f5(i32 %dummy, i32 *%src) { +; CHECK: f5: +; CHECK: oilf %r0, 65537 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 65537 seq_cst + ret i32 %res +} + +; Check the high end of the OILH range. +define i32 @f6(i32 %dummy, i32 *%src) { +; CHECK: f6: +; CHECK: oilh %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 -65536 seq_cst + ret i32 %res +} + +; Check the next value up, which must use OILF. +define i32 @f7(i32 %dummy, i32 *%src) { +; CHECK: f7: +; CHECK: oilf %r0, 4294901761 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 -65535 seq_cst + ret i32 %res +} + +; Check the largest useful OILF value. +define i32 @f8(i32 %dummy, i32 *%src) { +; CHECK: f8: +; CHECK: oilf %r0, 4294967294 +; CHECK: br %r14 + %res = atomicrmw or i32 *%src, i32 -2 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-or-04.ll b/test/CodeGen/SystemZ/atomicrmw-or-04.ll new file mode 100644 index 000000000000..a74f6f9dd501 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-or-04.ll @@ -0,0 +1,158 @@ +; Test 64-bit atomic ORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ORs of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: ogr %r0, %r4 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check the lowest useful OILL value. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: oill %r0, 1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the high end of the OILL range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: oill %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 65535 seq_cst + ret i64 %res +} + +; Check the lowest useful OILH value, which is the next value up. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: oilh %r0, 1 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 65536 seq_cst + ret i64 %res +} + +; Check the lowest useful OILF value, which is the next value up again. +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: oilf %r0, 65537 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 65537 seq_cst + ret i64 %res +} + +; Check the high end of the OILH range. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: oilh %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 4294901760 seq_cst + ret i64 %res +} + +; Check the next value up, which must use OILF. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: oilf %r0, 4294901761 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 4294901761 seq_cst + ret i64 %res +} + +; Check the high end of the OILF range. +define i64 @f8(i64 %dummy, i64 *%src) { +; CHECK: f8: +; CHECK: oilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 4294967295 seq_cst + ret i64 %res +} + +; Check the lowest useful OIHL value, which is one greater than above. +define i64 @f9(i64 %dummy, i64 *%src) { +; CHECK: f9: +; CHECK: oihl %r0, 1 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 4294967296 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. (We could use +; combinations of OIH* and OIL* instead, but that isn't implemented.) +define i64 @f10(i64 %dummy, i64 *%src) { +; CHECK: f10: +; CHECK: ogr +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 4294967297 seq_cst + ret i64 %res +} + +; Check the high end of the OIHL range. +define i64 @f11(i64 %dummy, i64 *%src) { +; CHECK: f11: +; CHECK: oihl %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst + ret i64 %res +} + +; Check the lowest useful OIHH value, which is 1<<32 greater than above. +define i64 @f12(i64 %dummy, i64 *%src) { +; CHECK: f12: +; CHECK: oihh %r0, 1 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst + ret i64 %res +} + +; Check the lowest useful OIHF value, which is 1<<32 greater again. +define i64 @f13(i64 %dummy, i64 *%src) { +; CHECK: f13: +; CHECK: oihf %r0, 65537 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst + ret i64 %res +} + +; Check the high end of the OIHH range. +define i64 @f14(i64 %dummy, i64 *%src) { +; CHECK: f14: +; CHECK: oihh %r0, 65535 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f15(i64 %dummy, i64 *%src) { +; CHECK: f15: +; CHECK: ogr +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst + ret i64 %res +} + +; Check the high end of the OIHF range. +define i64 @f16(i64 %dummy, i64 *%src) { +; CHECK: f16: +; CHECK: oihf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-01.ll b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll new file mode 100644 index 000000000000..d073dc5ec29f --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-sub-01.ll @@ -0,0 +1,132 @@ +; Test 8-bit atomic subtractions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check subtraction of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: sr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We add 0x80000000 to the rotated word. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: afi [[ROT]], -2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check subtraction of -1. We add 0x01000000 to the rotated word. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: afi [[ROT]], 16777216 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 -1 seq_cst + ret i8 %res +} + +; Check subtraction of -1. We add 0xff000000 to the rotated word. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: afi [[ROT]], -16777216 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We add 0x81000000 to the rotated word. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: afi [[ROT]], -2130706432 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check subtraction of a large unsigned value. We add 0x02000000 to the +; rotated word. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: afi [[ROT]], 33554432 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i8 *%src, i8 254 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-02.ll b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll new file mode 100644 index 000000000000..449d92ff3b30 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-sub-02.ll @@ -0,0 +1,132 @@ +; Test 16-bit atomic subtractions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check subtraction of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: sr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We add 0x80000000 to the rotated word. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: afi [[ROT]], -2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check subtraction of -1. We add 0x00010000 to the rotated word. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: afi [[ROT]], 65536 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 -1 seq_cst + ret i16 %res +} + +; Check subtraction of 1. We add 0xffff0000 to the rotated word. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: afi [[ROT]], -65536 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We add 0x80010000 to the rotated word. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: afi [[ROT]], -2147418112 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check subtraction of a large unsigned value. We add 0x00020000 to the +; rotated word. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: afi [[ROT]], 131072 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw sub i16 *%src, i16 65534 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-03.ll b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll new file mode 100644 index 000000000000..da07fb57ef72 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-sub-03.ll @@ -0,0 +1,94 @@ +; Test 32-bit atomic subtractions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check subtraction of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lr %r0, %r2 +; CHECK: sr %r0, %r4 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check subtraction of 1, which can use AHI. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lr %r0, %r2 +; CHECK: ahi %r0, -1 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check the low end of the AHI range. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: ahi %r0, -32768 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 32768 seq_cst + ret i32 %res +} + +; Check the next value down, which must use AFI. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: afi %r0, -32769 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 32769 seq_cst + ret i32 %res +} + +; Check the low end of the AFI range. +define i32 @f5(i32 %dummy, i32 *%src) { +; CHECK: f5: +; CHECK: afi %r0, -2147483648 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst + ret i32 %res +} + +; Check the next value up, which gets treated as a positive operand. +define i32 @f6(i32 %dummy, i32 *%src) { +; CHECK: f6: +; CHECK: afi %r0, 2147483647 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst + ret i32 %res +} + +; Check subtraction of -1, which can use AHI. +define i32 @f7(i32 %dummy, i32 *%src) { +; CHECK: f7: +; CHECK: ahi %r0, 1 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 -1 seq_cst + ret i32 %res +} + +; Check the high end of the AHI range. +define i32 @f8(i32 %dummy, i32 *%src) { +; CHECK: f8: +; CHECK: ahi %r0, 32767 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 -32767 seq_cst + ret i32 %res +} + +; Check the next value down, which must use AFI instead. +define i32 @f9(i32 %dummy, i32 *%src) { +; CHECK: f9: +; CHECK: afi %r0, 32768 +; CHECK: br %r14 + %res = atomicrmw sub i32 *%src, i32 -32768 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-sub-04.ll b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll new file mode 100644 index 000000000000..26f75afe85f4 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-sub-04.ll @@ -0,0 +1,112 @@ +; Test 64-bit atomic subtractions. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check subtraction of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: sgr %r0, %r4 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check subtraction of 1, which can use AGHI. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: aghi %r0, -1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the low end of the AGHI range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: aghi %r0, -32768 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 32768 seq_cst + ret i64 %res +} + +; Check the next value up, which must use AGFI. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r0, -32769 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 32769 seq_cst + ret i64 %res +} + +; Check the low end of the AGFI range. +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: agfi %r0, -2147483648 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register operation. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: sgr +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst + ret i64 %res +} + +; Check subtraction of -1, which can use AGHI. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: aghi %r0, 1 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 -1 seq_cst + ret i64 %res +} + +; Check the high end of the AGHI range. +define i64 @f8(i64 %dummy, i64 *%src) { +; CHECK: f8: +; CHECK: aghi %r0, 32767 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 -32767 seq_cst + ret i64 %res +} + +; Check the next value down, which must use AGFI instead. +define i64 @f9(i64 %dummy, i64 *%src) { +; CHECK: f9: +; CHECK: agfi %r0, 32768 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 -32768 seq_cst + ret i64 %res +} + +; Check the high end of the AGFI range. +define i64 @f10(i64 %dummy, i64 *%src) { +; CHECK: f10: +; CHECK: agfi %r0, 2147483647 +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst + ret i64 %res +} + +; Check the next value down, which must use a register operation. +define i64 @f11(i64 %dummy, i64 *%src) { +; CHECK: f11: +; CHECK: sgr +; CHECK: br %r14 + %res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll new file mode 100644 index 000000000000..e33597b7297d --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-01.ll @@ -0,0 +1,55 @@ +; Test 8-bit atomic exchange. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT + +; Check exchange with a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before +; being used in the RISBG (in contrast to things like atomic addition, +; which shift %r3 left so that %b is at the high end of the word). +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: risbg [[ROT]], %r3, 32, 39, 24 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT: f1: +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: rll +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: risbg {{%r[0-9]+}}, %r3, 32, 39, 24 +; CHECK-SHIFT: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT: rll +; CHECK-SHIFT: br %r14 + %res = atomicrmw xchg i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check exchange with a constant. We should force the constant into +; a register and use the sequence above. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: lhi [[VALUE:%r[0-9]+]], 88 +; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24 +; CHECK: br %r14 +; +; CHECK-SHIFT: f2: +; CHECK-SHIFT: br %r14 + %res = atomicrmw xchg i8 *%src, i8 88 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll new file mode 100644 index 000000000000..31f802625a32 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-02.ll @@ -0,0 +1,55 @@ +; Test 16-bit atomic exchange. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT + +; Check exchange with a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before +; being used in the RISBG (in contrast to things like atomic addition, +; which shift %r3 left so that %b is at the high end of the word). +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: risbg [[ROT]], %r3, 32, 47, 16 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT: f1: +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: rll +; CHECK-SHIFT-NOT: %r3 +; CHECK-SHIFT: risbg {{%r[0-9]+}}, %r3, 32, 47, 16 +; CHECK-SHIFT: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT: rll +; CHECK-SHIFT: br %r14 + %res = atomicrmw xchg i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check exchange with a constant. We should force the constant into +; a register and use the sequence above. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: lhi [[VALUE:%r[0-9]+]], -25536 +; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16 +; CHECK: br %r14 +; +; CHECK-SHIFT: f2: +; CHECK-SHIFT: br %r14 + %res = atomicrmw xchg i16 *%src, i16 40000 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll new file mode 100644 index 000000000000..37581ab9d602 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-03.ll @@ -0,0 +1,122 @@ +; Test 32-bit atomic exchange. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register exchange. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: cs %r2, %r4, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xchg i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the aligned CS range. +define i32 @f2(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f2: +; CHECK: l %r2, 4092(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word up, which requires CSY. +define i32 @f3(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f3: +; CHECK: ly %r2, 4096(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the aligned CSY range. +define i32 @f4(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f4: +; CHECK: ly %r2, 524284(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word up, which needs separate address logic. +define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f5: +; CHECK: agfi %r3, 524288 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the high end of the negative aligned CSY range. +define i32 @f6(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f6: +; CHECK: ly %r2, -4(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the low end of the CSY range. +define i32 @f7(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f7: +; CHECK: ly %r2, -524288(%r3) +; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check the next word down, which needs separate address logic. +define i32 @f8(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f8: +; CHECK: agfi %r3, -524292 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check that indexed addresses are not allowed. +define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) { +; CHECK: f9: +; CHECK: agr %r3, %r4 +; CHECK: l %r2, 0(%r3) +; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i32 * + %res = atomicrmw xchg i32 *%ptr, i32 %b seq_cst + ret i32 %res +} + +; Check exchange of a constant. We should force it into a register and +; use the sequence above. +define i32 @f10(i32 %dummy, i32 *%src) { +; CHECK: f10: +; CHECK: llill [[VALUE:%r[0-9+]]], 40000 +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: cs %r2, [[VALUE]], 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xchg i32 *%src, i32 40000 seq_cst + ret i32 %res +} + diff --git a/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll new file mode 100644 index 000000000000..a68295ea8b04 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xchg-04.ll @@ -0,0 +1,88 @@ +; Test 64-bit atomic exchange. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register exchange. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: csg %r2, %r4, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xchg i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check the high end of the aligned CSG range. +define i64 @f2(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f2: +; CHECK: lg %r2, 524280(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the next doubleword up, which requires separate address logic. +define i64 @f3(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f3: +; CHECK: agfi %r3, 524288 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the low end of the CSG range. +define i64 @f4(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f4: +; CHECK: lg %r2, -524288(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check the next doubleword down, which requires separate address logic. +define i64 @f5(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f5: +; CHECK: agfi %r3, -524296 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check that indexed addresses are not allowed. +define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) { +; CHECK: f6: +; CHECK: agr %r3, %r4 +; CHECK: lg %r2, 0(%r3) +; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3) +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i64 * + %res = atomicrmw xchg i64 *%ptr, i64 %b seq_cst + ret i64 %res +} + +; Check exchange of a constant. We should force it into a register and +; use the sequence above. +define i64 @f7(i64 %dummy, i64 *%ptr) { +; CHECK: f7: +; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000 +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: csg %r2, [[VALUE]], 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xchg i64 *%ptr, i64 3000000000 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-01.ll b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll new file mode 100644 index 000000000000..13cdf02f486c --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xor-01.ll @@ -0,0 +1,132 @@ +; Test 8-bit atomic XORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check XOR of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i8 @f1(i8 *%src, i8 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: xr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 24 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 %b seq_cst + ret i8 %res +} + +; Check the minimum signed value. We XOR the rotated word with 0x80000000. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: xilf [[ROT]], 2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 -128 seq_cst + ret i8 %res +} + +; Check XORs of -1. We XOR the rotated word with 0xff000000. +define i8 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: xilf [[ROT]], 4278190080 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 -1 seq_cst + ret i8 %res +} + +; Check XORs of 1. We XOR the rotated word with 0x01000000. +define i8 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: xilf [[ROT]], 16777216 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 1 seq_cst + ret i8 %res +} + +; Check the maximum signed value. We XOR the rotated word with 0x7f000000. +define i8 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: xilf [[ROT]], 2130706432 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 127 seq_cst + ret i8 %res +} + +; Check XORs of a large unsigned value. We XOR the rotated word with +; 0xfd000000. +define i8 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: xilf [[ROT]], 4244635648 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i8 *%src, i8 253 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-02.ll b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll new file mode 100644 index 000000000000..4faa64f8e837 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xor-02.ll @@ -0,0 +1,132 @@ +; Test 16-bit atomic XORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1 +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2 + +; Check XOR of a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT1 makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. +; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word +; before being used. This shift is independent of the other loop prologue +; instructions. +define i16 @f1(i16 *%src, i16 %b) { +; CHECK: f1: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: xr [[ROT]], %r3 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}}) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f1: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f1: +; CHECK-SHIFT2: sll %r3, 16 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3 +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: rll +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 %b seq_cst + ret i16 %res +} + +; Check the minimum signed value. We XOR the rotated word with 0x80000000. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK: nill %r2, 65532 +; CHECK: l [[OLD:%r[0-9]+]], 0(%r2) +; CHECK: [[LABEL:\.[^:]*]]: +; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0([[SHIFT]]) +; CHECK: xilf [[ROT]], 2147483648 +; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]]) +; CHECK: cs [[OLD]], [[NEW]], 0(%r2) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK: br %r14 +; +; CHECK-SHIFT1: f2: +; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3 +; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]]) +; CHECK-SHIFT1: rll +; CHECK-SHIFT1: br %r14 +; +; CHECK-SHIFT2: f2: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 -32768 seq_cst + ret i16 %res +} + +; Check XORs of -1. We XOR the rotated word with 0xffff0000. +define i16 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: xilf [[ROT]], 4294901760 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f3: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f3: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 -1 seq_cst + ret i16 %res +} + +; Check XORs of 1. We XOR the rotated word with 0x00010000. +define i16 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: xilf [[ROT]], 65536 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f4: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f4: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 1 seq_cst + ret i16 %res +} + +; Check the maximum signed value. We XOR the rotated word with 0x7fff0000. +define i16 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: xilf [[ROT]], 2147418112 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f5: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f5: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 32767 seq_cst + ret i16 %res +} + +; Check XORs of a large unsigned value. We XOR the rotated word with +; 0xfffd0000. +define i16 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: xilf [[ROT]], 4294770688 +; CHECK: br %r14 +; +; CHECK-SHIFT1: f6: +; CHECK-SHIFT1: br %r14 +; CHECK-SHIFT2: f6: +; CHECK-SHIFT2: br %r14 + %res = atomicrmw xor i16 *%src, i16 65533 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-03.ll b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll new file mode 100644 index 000000000000..23884f888e13 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xor-03.ll @@ -0,0 +1,49 @@ +; Test 32-bit atomic XORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check XORs of a variable. +define i32 @f1(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f1: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: xr %r0, %r4 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xor i32 *%src, i32 %b seq_cst + ret i32 %res +} + +; Check the lowest useful constant. +define i32 @f2(i32 %dummy, i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lr %r0, %r2 +; CHECK: xilf %r0, 1 +; CHECK: cs %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xor i32 *%src, i32 1 seq_cst + ret i32 %res +} + +; Check an arbitrary constant. +define i32 @f3(i32 %dummy, i32 *%src) { +; CHECK: f3: +; CHECK: xilf %r0, 3000000000 +; CHECK: br %r14 + %res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst + ret i32 %res +} + +; Check bitwise negation. +define i32 @f4(i32 %dummy, i32 *%src) { +; CHECK: f4: +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw xor i32 *%src, i32 -1 seq_cst + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/atomicrmw-xor-04.ll b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll new file mode 100644 index 000000000000..21130fb47776 --- /dev/null +++ b/test/CodeGen/SystemZ/atomicrmw-xor-04.ll @@ -0,0 +1,77 @@ +; Test 64-bit atomic XORs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check XORs of a variable. +define i64 @f1(i64 %dummy, i64 *%src, i64 %b) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: xgr %r0, %r4 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 %b seq_cst + ret i64 %res +} + +; Check the lowest useful XILF value. +define i64 @f2(i64 %dummy, i64 *%src) { +; CHECK: f2: +; CHECK: lg %r2, 0(%r3) +; CHECK: [[LABEL:\.[^ ]*]]: +; CHECK: lgr %r0, %r2 +; CHECK: xilf %r0, 1 +; CHECK: csg %r2, %r0, 0(%r3) +; CHECK: j{{g?}}lh [[LABEL]] +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 1 seq_cst + ret i64 %res +} + +; Check the high end of the XILF range. +define i64 @f3(i64 %dummy, i64 *%src) { +; CHECK: f3: +; CHECK: xilf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst + ret i64 %res +} + +; Check the lowest useful XIHF value, which is one greater than above. +define i64 @f4(i64 %dummy, i64 *%src) { +; CHECK: f4: +; CHECK: xihf %r0, 1 +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. (We could use +; combinations of XIH* and XIL* instead, but that isn't implemented.) +define i64 @f5(i64 %dummy, i64 *%src) { +; CHECK: f5: +; CHECK: xgr +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst + ret i64 %res +} + +; Check the high end of the XIHF range. +define i64 @f6(i64 %dummy, i64 *%src) { +; CHECK: f6: +; CHECK: xihf %r0, 4294967295 +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst + ret i64 %res +} + +; Check the next value up, which must use a register. +define i64 @f7(i64 %dummy, i64 *%src) { +; CHECK: f7: +; CHECK: xgr +; CHECK: br %r14 + %res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/branch-01.ll b/test/CodeGen/SystemZ/branch-01.ll new file mode 100644 index 000000000000..8ff91ac38e80 --- /dev/null +++ b/test/CodeGen/SystemZ/branch-01.ll @@ -0,0 +1,14 @@ +; Test a simple unconditional jump. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i8 *%dest) { +; CHECK: f1: +; CHECK: .L[[LABEL:.*]]: +; CHECK: mvi 0(%r2), 1 +; CHECK: j{{g?}} .L[[LABEL]] + br label %loop +loop: + store volatile i8 1, i8 *%dest + br label %loop +} diff --git a/test/CodeGen/SystemZ/branch-02.ll b/test/CodeGen/SystemZ/branch-02.ll new file mode 100644 index 000000000000..cde9b568b38c --- /dev/null +++ b/test/CodeGen/SystemZ/branch-02.ll @@ -0,0 +1,94 @@ +; Test all condition-code masks that are relevant for signed integer +; comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(i32 *%src, i32 %target) { +; CHECK: f1: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}e .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp eq i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f2(i32 *%src, i32 %target) { +; CHECK: f2: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}lh .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp ne i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f3(i32 *%src, i32 %target) { +; CHECK: f3: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}le .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp sle i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f4(i32 *%src, i32 %target) { +; CHECK: f4: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}l .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp slt i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f5(i32 *%src, i32 %target) { +; CHECK: f5: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}h .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp sgt i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f6(i32 *%src, i32 %target) { +; CHECK: f6: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: c %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}he .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp sge i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} diff --git a/test/CodeGen/SystemZ/branch-03.ll b/test/CodeGen/SystemZ/branch-03.ll new file mode 100644 index 000000000000..1e447d034a39 --- /dev/null +++ b/test/CodeGen/SystemZ/branch-03.ll @@ -0,0 +1,63 @@ +; Test all condition-code masks that are relevant for unsigned integer +; comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +define void @f1(i32 *%src, i32 %target) { +; CHECK: f1: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: cl %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}le .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp ule i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f2(i32 *%src, i32 %target) { +; CHECK: f2: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: cl %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}l .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp ult i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f3(i32 *%src, i32 %target) { +; CHECK: f3: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: cl %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}h .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp ugt i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f4(i32 *%src, i32 %target) { +; CHECK: f4: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: cl %r3, 0(%r2) +; CHECK-NEXT: j{{g?}}he .L[[LABEL]] + br label %loop +loop: + %val = load volatile i32 *%src + %cond = icmp uge i32 %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} diff --git a/test/CodeGen/SystemZ/branch-04.ll b/test/CodeGen/SystemZ/branch-04.ll new file mode 100644 index 000000000000..3d4175041db2 --- /dev/null +++ b/test/CodeGen/SystemZ/branch-04.ll @@ -0,0 +1,218 @@ +; Test all condition-code masks that are relevant for floating-point +; comparisons. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define void @f1(float *%src, float %target) { +; CHECK: f1: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}e .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp oeq float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f2(float *%src, float %target) { +; CHECK: f2: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}lh .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp one float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f3(float *%src, float %target) { +; CHECK: f3: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}le .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ole float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f4(float *%src, float %target) { +; CHECK: f4: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}l .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp olt float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f5(float *%src, float %target) { +; CHECK: f5: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}h .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ogt float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f6(float *%src, float %target) { +; CHECK: f6: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}he .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp oge float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f7(float *%src, float %target) { +; CHECK: f7: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}nlh .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ueq float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f8(float *%src, float %target) { +; CHECK: f8: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}ne .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp une float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f9(float *%src, float %target) { +; CHECK: f9: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}nh .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ule float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f10(float *%src, float %target) { +; CHECK: f10: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}nhe .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ult float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f11(float *%src, float %target) { +; CHECK: f11: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}nle .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ugt float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +define void @f12(float *%src, float %target) { +; CHECK: f12: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}nl .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp uge float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +; "jno" == "jump if no overflow", which corresponds to "jump if ordered" +; rather than "jump if not ordered" after a floating-point comparison. +define void @f13(float *%src, float %target) { +; CHECK: f13: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}no .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp ord float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} + +; "jo" == "jump if overflow", which corresponds to "jump if not ordered" +; rather than "jump if ordered" after a floating-point comparison. +define void @f14(float *%src, float %target) { +; CHECK: f14: +; CHECK: .cfi_startproc +; CHECK: .L[[LABEL:.*]]: +; CHECK: ceb %f0, 0(%r2) +; CHECK-NEXT: j{{g?}}o .L[[LABEL]] + br label %loop +loop: + %val = load volatile float *%src + %cond = fcmp uno float %target, %val + br i1 %cond, label %loop, label %exit +exit: + ret void +} diff --git a/test/CodeGen/SystemZ/branch-05.ll b/test/CodeGen/SystemZ/branch-05.ll new file mode 100644 index 000000000000..d149e0b7013b --- /dev/null +++ b/test/CodeGen/SystemZ/branch-05.ll @@ -0,0 +1,58 @@ +; Test indirect jumps. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +define i32 @f1(i32 %x, i32 %y, i32 %op) { +; CHECK: f1: +; CHECK: ahi %r4, -1 +; CHECK: clfi %r4, 5 +; CHECK-NEXT: j{{g?}}g +; CHECK: llgfr [[OP64:%r[0-5]]], %r4 +; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 +; CHECK: larl [[BASE:%r[1-5]]] +; CHECK: lg [[TARGET:%r[1-5]]], 0([[BASE]],[[INDEX]]) +; CHECK: br [[TARGET]] +entry: + switch i32 %op, label %exit [ + i32 1, label %b.add + i32 2, label %b.sub + i32 3, label %b.and + i32 4, label %b.or + i32 5, label %b.xor + i32 6, label %b.mul + ] + +b.add: + %add = add i32 %x, %y + br label %exit + +b.sub: + %sub = sub i32 %x, %y + br label %exit + +b.and: + %and = and i32 %x, %y + br label %exit + +b.or: + %or = or i32 %x, %y + br label %exit + +b.xor: + %xor = xor i32 %x, %y + br label %exit + +b.mul: + %mul = mul i32 %x, %y + br label %exit + +exit: + %res = phi i32 [ %x, %entry ], + [ %add, %b.add ], + [ %sub, %b.sub ], + [ %and, %b.and ], + [ %or, %b.or ], + [ %xor, %b.xor ], + [ %mul, %b.mul ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/bswap-01.ll b/test/CodeGen/SystemZ/bswap-01.ll new file mode 100644 index 000000000000..952903df50f9 --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-01.ll @@ -0,0 +1,24 @@ +; Test byteswaps between registers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i32 @llvm.bswap.i32(i32 %a) +declare i64 @llvm.bswap.i64(i64 %a) + +; Check 32-bit register-to-register byteswaps. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2 +; CHECk: br %r14 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check 64-bit register-to-register byteswaps. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: lrvgr %r2, %r2 +; CHECk: br %r14 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} diff --git a/test/CodeGen/SystemZ/bswap-02.ll b/test/CodeGen/SystemZ/bswap-02.ll new file mode 100644 index 000000000000..e9b7eb5f055b --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-02.ll @@ -0,0 +1,87 @@ +; Test 32-bit byteswaps from memory to registers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i32 @llvm.bswap.i32(i32 %a) + +; Check LRV with no displacement. +define i32 @f1(i32 *%src) { +; CHECK: f1: +; CHECK: lrv %r2, 0(%r2) +; CHECK: br %r14 + %a = load i32 *%src + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check the high end of the aligned LRV range. +define i32 @f2(i32 *%src) { +; CHECK: f2: +; CHECK: lrv %r2, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f3(i32 *%src) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: lrv %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check the high end of the negative aligned LRV range. +define i32 @f4(i32 *%src) { +; CHECK: f4: +; CHECK: lrv %r2, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check the low end of the LRV range. +define i32 @f5(i32 *%src) { +; CHECK: f5: +; CHECK: lrv %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, -524292 +; CHECK: lrv %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} + +; Check that LRV allows an index. +define i32 @f7(i64 %src, i64 %index) { +; CHECK: f7: +; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %a = load i32 *%ptr + %swapped = call i32 @llvm.bswap.i32(i32 %a) + ret i32 %swapped +} diff --git a/test/CodeGen/SystemZ/bswap-03.ll b/test/CodeGen/SystemZ/bswap-03.ll new file mode 100644 index 000000000000..2e6bcdce2651 --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-03.ll @@ -0,0 +1,87 @@ +; Test 64-bit byteswaps from memory to registers. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @llvm.bswap.i64(i64 %a) + +; Check LRVG with no displacement. +define i64 @f1(i64 *%src) { +; CHECK: f1: +; CHECK: lrvg %r2, 0(%r2) +; CHECK: br %r14 + %a = load i64 *%src + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check the high end of the aligned LRVG range. +define i64 @f2(i64 *%src) { +; CHECK: f2: +; CHECK: lrvg %r2, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 *%src) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: lrvg %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check the high end of the negative aligned LRVG range. +define i64 @f4(i64 *%src) { +; CHECK: f4: +; CHECK: lrvg %r2, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check the low end of the LRVG range. +define i64 @f5(i64 *%src) { +; CHECK: f5: +; CHECK: lrvg %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, -524296 +; CHECK: lrvg %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} + +; Check that LRVG allows an index. +define i64 @f7(i64 %src, i64 %index) { +; CHECK: f7: +; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %a = load i64 *%ptr + %swapped = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %swapped +} diff --git a/test/CodeGen/SystemZ/bswap-04.ll b/test/CodeGen/SystemZ/bswap-04.ll new file mode 100644 index 000000000000..192327bd256c --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-04.ll @@ -0,0 +1,87 @@ +; Test 32-bit byteswaps from registers to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i32 @llvm.bswap.i32(i32 %a) + +; Check STRV with no displacement. +define void @f1(i32 *%src, i32 %a) { +; CHECK: f1: +; CHECK: strv %r3, 0(%r2) +; CHECK: br %r14 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%src + ret void +} + +; Check the high end of the aligned STRV range. +define void @f2(i32 *%src, i32 %a) { +; CHECK: f2: +; CHECK: strv %r3, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f3(i32 *%src, i32 %a) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: strv %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} + +; Check the high end of the negative aligned STRV range. +define void @f4(i32 *%src, i32 %a) { +; CHECK: f4: +; CHECK: strv %r3, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} + +; Check the low end of the STRV range. +define void @f5(i32 *%src, i32 %a) { +; CHECK: f5: +; CHECK: strv %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i32 *%src, i32 %a) { +; CHECK: f6: +; CHECK: agfi %r2, -524292 +; CHECK: strv %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} + +; Check that STRV allows an index. +define void @f7(i64 %src, i64 %index, i32 %a) { +; CHECK: f7: +; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %swapped = call i32 @llvm.bswap.i32(i32 %a) + store i32 %swapped, i32 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/bswap-05.ll b/test/CodeGen/SystemZ/bswap-05.ll new file mode 100644 index 000000000000..e58cb80c3981 --- /dev/null +++ b/test/CodeGen/SystemZ/bswap-05.ll @@ -0,0 +1,87 @@ +; Test 64-bit byteswaps from registers to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @llvm.bswap.i64(i64 %a) + +; Check STRVG with no displacement. +define void @f1(i64 *%src, i64 %a) { +; CHECK: f1: +; CHECK: strvg %r3, 0(%r2) +; CHECK: br %r14 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%src + ret void +} + +; Check the high end of the aligned STRVG range. +define void @f2(i64 *%src, i64 %a) { +; CHECK: f2: +; CHECK: strvg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f3(i64 *%src, i64 %a) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: strvg %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} + +; Check the high end of the negative aligned STRVG range. +define void @f4(i64 *%src, i64 %a) { +; CHECK: f4: +; CHECK: strvg %r3, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} + +; Check the low end of the STRVG range. +define void @f5(i64 *%src, i64 %a) { +; CHECK: f5: +; CHECK: strvg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i64 *%src, i64 %a) { +; CHECK: f6: +; CHECK: agfi %r2, -524296 +; CHECK: strvg %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} + +; Check that STRVG allows an index. +define void @f7(i64 %src, i64 %index, i64 %a) { +; CHECK: f7: +; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %swapped = call i64 @llvm.bswap.i64(i64 %a) + store i64 %swapped, i64 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/call-01.ll b/test/CodeGen/SystemZ/call-01.ll new file mode 100644 index 000000000000..1b9172bdd819 --- /dev/null +++ b/test/CodeGen/SystemZ/call-01.ll @@ -0,0 +1,18 @@ +; Test direct calls. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i64 @bar() + +; We must allocate 160 bytes for the callee and save and restore %r14. +define i64 @f1() { +; CHECK: f1: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: aghi %r15, -160 +; CHECK: brasl %r14, bar@PLT +; CHECK: lmg %r14, %r15, 272(%r15) +; CHECK: br %r14 + %ret = call i64 @bar() + %inc = add i64 %ret, 1 + ret i64 %inc +} diff --git a/test/CodeGen/SystemZ/call-02.ll b/test/CodeGen/SystemZ/call-02.ll new file mode 100644 index 000000000000..07dd67bab1b6 --- /dev/null +++ b/test/CodeGen/SystemZ/call-02.ll @@ -0,0 +1,16 @@ +; Test indirect calls. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; We must allocate 160 bytes for the callee and save and restore %r14. +define i64 @f1(i64() *%bar) { +; CHECK: f1: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: aghi %r15, -160 +; CHECK: basr %r14, %r2 +; CHECK: lmg %r14, %r15, 272(%r15) +; CHECK: br %r14 + %ret = call i64 %bar() + %inc = add i64 %ret, 1 + ret i64 %inc +} diff --git a/test/CodeGen/SystemZ/cmpxchg-01.ll b/test/CodeGen/SystemZ/cmpxchg-01.ll new file mode 100644 index 000000000000..477bcb00e9bd --- /dev/null +++ b/test/CodeGen/SystemZ/cmpxchg-01.ll @@ -0,0 +1,56 @@ +; Test 8-bit compare and swap. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT + +; Check compare and swap with a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before +; being used in the RISBG (in contrast to things like atomic addition, +; which shift %r3 left so that %b is at the high end of the word). +define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) { +; CHECK-MAIN: f1: +; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3 +; CHECK-MAIN: nill %r3, 65532 +; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3) +; CHECK-MAIN: [[LOOP:\.[^ ]*]]: +; CHECK-MAIN: rll %r2, [[OLD]], 8([[SHIFT]]) +; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0 +; CHECK-MAIN: cr %r2, %r4 +; CHECK-MAIN: j{{g?}}lh [[EXIT:\.[^ ]*]] +; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0 +; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}}) +; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3) +; CHECK-MAIN: j{{g?}}lh [[LOOP]] +; CHECK-MAIN: [[EXIT]]: +; CHECK-MAIN-NOT: %r2 +; CHECK-MAIN: br %r14 +; +; CHECK-SHIFT: f1: +; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3 +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT: rll +; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -8([[NEGSHIFT]]) + %res = cmpxchg i8 *%src, i8 %cmp, i8 %swap seq_cst + ret i8 %res +} + +; Check compare and swap with constants. We should force the constants into +; registers and use the sequence above. +define i8 @f2(i8 *%src) { +; CHECK: f2: +; CHECK: lhi [[CMP:%r[0-9]+]], 42 +; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0 +; CHECK: risbg +; CHECK: br %r14 +; +; CHECK-SHIFT: f2: +; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88 +; CHECK-SHIFT: risbg +; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0 +; CHECK-SHIFT: br %r14 + %res = cmpxchg i8 *%src, i8 42, i8 88 seq_cst + ret i8 %res +} diff --git a/test/CodeGen/SystemZ/cmpxchg-02.ll b/test/CodeGen/SystemZ/cmpxchg-02.ll new file mode 100644 index 000000000000..cc3452320b3d --- /dev/null +++ b/test/CodeGen/SystemZ/cmpxchg-02.ll @@ -0,0 +1,56 @@ +; Test 16-bit compare and swap. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT + +; Check compare and swap with a variable. +; - CHECK is for the main loop. +; - CHECK-SHIFT makes sure that the negated shift count used by the second +; RLL is set up correctly. The negation is independent of the NILL and L +; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before +; being used in the RISBG (in contrast to things like atomic addition, +; which shift %r3 left so that %b is at the high end of the word). +define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) { +; CHECK-MAIN: f1: +; CHECK-MAIN: sllg [[SHIFT:%r[1-9]+]], %r3, 3 +; CHECK-MAIN: nill %r3, 65532 +; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0(%r3) +; CHECK-MAIN: [[LOOP:\.[^ ]*]]: +; CHECK-MAIN: rll %r2, [[OLD]], 16([[SHIFT]]) +; CHECK-MAIN: risbg %r4, %r2, 32, 47, 0 +; CHECK-MAIN: cr %r2, %r4 +; CHECK-MAIN: j{{g?}}lh [[EXIT:\.[^ ]*]] +; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0 +; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}}) +; CHECK-MAIN: cs [[OLD]], [[NEW]], 0(%r3) +; CHECK-MAIN: j{{g?}}lh [[LOOP]] +; CHECK-MAIN: [[EXIT]]: +; CHECK-MAIN-NOT: %r2 +; CHECK-MAIN: br %r14 +; +; CHECK-SHIFT: f1: +; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3 +; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]] +; CHECK-SHIFT: rll +; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -16([[NEGSHIFT]]) + %res = cmpxchg i16 *%src, i16 %cmp, i16 %swap seq_cst + ret i16 %res +} + +; Check compare and swap with constants. We should force the constants into +; registers and use the sequence above. +define i16 @f2(i16 *%src) { +; CHECK: f2: +; CHECK: lhi [[CMP:%r[0-9]+]], 42 +; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0 +; CHECK: risbg +; CHECK: br %r14 +; +; CHECK-SHIFT: f2: +; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88 +; CHECK-SHIFT: risbg +; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0 +; CHECK-SHIFT: br %r14 + %res = cmpxchg i16 *%src, i16 42, i16 88 seq_cst + ret i16 %res +} diff --git a/test/CodeGen/SystemZ/cmpxchg-03.ll b/test/CodeGen/SystemZ/cmpxchg-03.ll new file mode 100644 index 000000000000..45e224eda84c --- /dev/null +++ b/test/CodeGen/SystemZ/cmpxchg-03.ll @@ -0,0 +1,131 @@ +; Test 32-bit compare and swap. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the CS range. +define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f1: +; CHECK: cs %r2, %r3, 0(%r4) +; CHECK: br %r14 + %val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the high end of the aligned CS range. +define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f2: +; CHECK: cs %r2, %r3, 4092(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the next word up, which should use CSY instead of CS. +define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f3: +; CHECK: csy %r2, %r3, 4096(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the high end of the aligned CSY range. +define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f4: +; CHECK: csy %r2, %r3, 524284(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f5: +; CHECK: agfi %r4, 524288 +; CHECK: cs %r2, %r3, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the high end of the negative aligned CSY range. +define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f6: +; CHECK: csy %r2, %r3, -4(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the low end of the CSY range. +define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f7: +; CHECK: csy %r2, %r3, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) { +; CHECK: f8: +; CHECK: agfi %r4, -524292 +; CHECK: cs %r2, %r3, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check that CS does not allow an index. +define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: agr %r4, %r5 +; CHECK: cs %r2, %r3, 0(%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %ptr = inttoptr i64 %add1 to i32 * + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check that CSY does not allow an index. +define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: agr %r4, %r5 +; CHECK: csy %r2, %r3, 4096(%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 %swap seq_cst + ret i32 %val +} + +; Check that a constant %cmp value is loaded into a register first. +define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) { +; CHECK: f11: +; CHECK: lhi %r2, 1001 +; CHECK: cs %r2, %r3, 0(%r4) +; CHECK: br %r14 + %val = cmpxchg i32 *%ptr, i32 1001, i32 %swap seq_cst + ret i32 %val +} + +; Check that a constant %swap value is loaded into a register first. +define i32 @f12(i32 %cmp, i32 *%ptr) { +; CHECK: f12: +; CHECK: lhi [[SWAP:%r[0-9]+]], 1002 +; CHECK: cs %r2, [[SWAP]], 0(%r3) +; CHECK: br %r14 + %val = cmpxchg i32 *%ptr, i32 %cmp, i32 1002 seq_cst + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/cmpxchg-04.ll b/test/CodeGen/SystemZ/cmpxchg-04.ll new file mode 100644 index 000000000000..f8969ee08449 --- /dev/null +++ b/test/CodeGen/SystemZ/cmpxchg-04.ll @@ -0,0 +1,98 @@ +; Test 64-bit compare and swap. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check CSG without a displacement. +define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f1: +; CHECK: csg %r2, %r3, 0(%r4) +; CHECK: br %r14 + %val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check the high end of the aligned CSG range. +define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f2: +; CHECK: csg %r2, %r3, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f3: +; CHECK: agfi %r4, 524288 +; CHECK: csg %r2, %r3, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check the high end of the negative aligned CSG range. +define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f4: +; CHECK: csg %r2, %r3, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check the low end of the CSG range. +define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f5: +; CHECK: csg %r2, %r3, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) { +; CHECK: f6: +; CHECK: agfi %r4, -524296 +; CHECK: csg %r2, %r3, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check that CSG does not allow an index. +define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) { +; CHECK: f7: +; CHECK: agr %r4, %r5 +; CHECK: csg %r2, %r3, 0(%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %ptr = inttoptr i64 %add1 to i64 * + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 %swap seq_cst + ret i64 %val +} + +; Check that a constant %cmp value is loaded into a register first. +define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) { +; CHECK: f8: +; CHECK: lghi %r2, 1001 +; CHECK: csg %r2, %r3, 0(%r4) +; CHECK: br %r14 + %val = cmpxchg i64 *%ptr, i64 1001, i64 %swap seq_cst + ret i64 %val +} + +; Check that a constant %swap value is loaded into a register first. +define i64 @f9(i64 %cmp, i64 *%ptr) { +; CHECK: f9: +; CHECK: lghi [[SWAP:%r[0-9]+]], 1002 +; CHECK: csg %r2, [[SWAP]], 0(%r3) +; CHECK: br %r14 + %val = cmpxchg i64 *%ptr, i64 %cmp, i64 1002 seq_cst + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/fp-abs-01.ll b/test/CodeGen/SystemZ/fp-abs-01.ll new file mode 100644 index 000000000000..81b3fb273d14 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-abs-01.ll @@ -0,0 +1,40 @@ +; Test floating-point absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +declare float @llvm.fabs.f32(float %f) +define float @f1(float %f) { +; CHECK: f1: +; CHECK: lpebr %f0, %f0 +; CHECK: br %r14 + %res = call float @llvm.fabs.f32(float %f) + ret float %res +} + +; Test f64. +declare double @llvm.fabs.f64(double %f) +define double @f2(double %f) { +; CHECK: f2: +; CHECK: lpdbr %f0, %f0 +; CHECK: br %r14 + %res = call double @llvm.fabs.f64(double %f) + ret double %res +} + +; Test f128. With the loads and stores, a pure absolute would probably +; be better implemented using an NI on the upper byte. Do some extra +; processing so that using FPRs is unequivocally better. +declare fp128 @llvm.fabs.f128(fp128 %f) +define void @f3(fp128 *%ptr, fp128 *%ptr2) { +; CHECK: f3: +; CHECK: lpxbr +; CHECK: dxbr +; CHECK: br %r14 + %orig = load fp128 *%ptr + %abs = call fp128 @llvm.fabs.f128(fp128 %orig) + %op2 = load fp128 *%ptr2 + %res = fdiv fp128 %abs, %op2 + store fp128 %res, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-abs-02.ll b/test/CodeGen/SystemZ/fp-abs-02.ll new file mode 100644 index 000000000000..513d49c7acf5 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-abs-02.ll @@ -0,0 +1,43 @@ +; Test negated floating-point absolute. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +declare float @llvm.fabs.f32(float %f) +define float @f1(float %f) { +; CHECK: f1: +; CHECK: lnebr %f0, %f0 +; CHECK: br %r14 + %abs = call float @llvm.fabs.f32(float %f) + %res = fsub float -0.0, %abs + ret float %res +} + +; Test f64. +declare double @llvm.fabs.f64(double %f) +define double @f2(double %f) { +; CHECK: f2: +; CHECK: lndbr %f0, %f0 +; CHECK: br %r14 + %abs = call double @llvm.fabs.f64(double %f) + %res = fsub double -0.0, %abs + ret double %res +} + +; Test f128. With the loads and stores, a pure negative-absolute would +; probably be better implemented using an OI on the upper byte. Do some +; extra processing so that using FPRs is unequivocally better. +declare fp128 @llvm.fabs.f128(fp128 %f) +define void @f3(fp128 *%ptr, fp128 *%ptr2) { +; CHECK: f3: +; CHECK: lnxbr +; CHECK: dxbr +; CHECK: br %r14 + %orig = load fp128 *%ptr + %abs = call fp128 @llvm.fabs.f128(fp128 %orig) + %negabs = fsub fp128 0xL00000000000000008000000000000000, %abs + %op2 = load fp128 *%ptr2 + %res = fdiv fp128 %negabs, %op2 + store fp128 %res, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-add-01.ll b/test/CodeGen/SystemZ/fp-add-01.ll new file mode 100644 index 000000000000..7ce0777b8870 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-add-01.ll @@ -0,0 +1,71 @@ +; Test 32-bit floating-point addition. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register addition. +define float @f1(float %f1, float %f2) { +; CHECK: f1: +; CHECK: aebr %f0, %f2 +; CHECK: br %r14 + %res = fadd float %f1, %f2 + ret float %res +} + +; Check the low end of the AEB range. +define float @f2(float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: aeb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load float *%ptr + %res = fadd float %f1, %f2 + ret float %res +} + +; Check the high end of the aligned AEB range. +define float @f3(float %f1, float *%base) { +; CHECK: f3: +; CHECK: aeb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %res = fadd float %f1, %f2 + ret float %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f4(float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: aeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %res = fadd float %f1, %f2 + ret float %res +} + +; Check negative displacements, which also need separate address logic. +define float @f5(float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: aeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %res = fadd float %f1, %f2 + ret float %res +} + +; Check that AEB allows indices. +define float @f6(float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: aeb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %res = fadd float %f1, %f2 + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-add-02.ll b/test/CodeGen/SystemZ/fp-add-02.ll new file mode 100644 index 000000000000..08eb90efbfaa --- /dev/null +++ b/test/CodeGen/SystemZ/fp-add-02.ll @@ -0,0 +1,71 @@ +; Test 64-bit floating-point addition. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register addition. +define double @f1(double %f1, double %f2) { +; CHECK: f1: +; CHECK: adbr %f0, %f2 +; CHECK: br %r14 + %res = fadd double %f1, %f2 + ret double %res +} + +; Check the low end of the ADB range. +define double @f2(double %f1, double *%ptr) { +; CHECK: f2: +; CHECK: adb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load double *%ptr + %res = fadd double %f1, %f2 + ret double %res +} + +; Check the high end of the aligned ADB range. +define double @f3(double %f1, double *%base) { +; CHECK: f3: +; CHECK: adb %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %res = fadd double %f1, %f2 + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %f1, double *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: adb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %res = fadd double %f1, %f2 + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(double %f1, double *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: adb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %res = fadd double %f1, %f2 + ret double %res +} + +; Check that ADB allows indices. +define double @f6(double %f1, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: adb %f0, 800(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %res = fadd double %f1, %f2 + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-add-03.ll b/test/CodeGen/SystemZ/fp-add-03.ll new file mode 100644 index 000000000000..13ffb023b6fb --- /dev/null +++ b/test/CodeGen/SystemZ/fp-add-03.ll @@ -0,0 +1,20 @@ +; Test 128-bit floating-point addition. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no memory form of 128-bit addition. +define void @f1(fp128 *%ptr, float %f2) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: ld %f1, 0(%r2) +; CHECK: ld %f3, 8(%r2) +; CHECK: axbr %f1, %f0 +; CHECK: std %f1, 0(%r2) +; CHECK: std %f3, 8(%r2) +; CHECK: br %r14 + %f1 = load fp128 *%ptr + %f2x = fpext float %f2 to fp128 + %sum = fadd fp128 %f1, %f2x + store fp128 %sum, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-cmp-01.ll b/test/CodeGen/SystemZ/fp-cmp-01.ll new file mode 100644 index 000000000000..b80a71595e87 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-cmp-01.ll @@ -0,0 +1,89 @@ +; Test 32-bit floating-point comparison. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparison with registers. +define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) { +; CHECK: f1: +; CHECK: cebr %f0, %f2 +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the low end of the CEB range. +define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: ceb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %f2 = load float *%ptr + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the high end of the aligned CEB range. +define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) { +; CHECK: f3: +; CHECK: ceb %f0, 4092(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r4, 4096 +; CHECK: ceb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check negative displacements, which also need separate address logic. +define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r4, -4 +; CHECK: ceb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check that CEB allows indices. +define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r5, 2 +; CHECK: ceb %f0, 400(%r1,%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %cond = fcmp oeq float %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/fp-cmp-02.ll b/test/CodeGen/SystemZ/fp-cmp-02.ll new file mode 100644 index 000000000000..8227308ce810 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-cmp-02.ll @@ -0,0 +1,89 @@ +; Test 64-bit floating-point comparison. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparison with registers. +define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) { +; CHECK: f1: +; CHECK: cdbr %f0, %f2 +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the low end of the CDB range. +define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) { +; CHECK: f2: +; CHECK: cdb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %f2 = load double *%ptr + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the high end of the aligned CDB range. +define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) { +; CHECK: f3: +; CHECK: cdb %f0, 4088(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) { +; CHECK: f4: +; CHECK: aghi %r4, 4096 +; CHECK: cdb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check negative displacements, which also need separate address logic. +define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) { +; CHECK: f5: +; CHECK: aghi %r4, -8 +; CHECK: cdb %f0, 0(%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} + +; Check that CDB allows indices. +define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r5, 3 +; CHECK: cdb %f0, 800(%r1,%r4) +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %cond = fcmp oeq double %f1, %f2 + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/fp-cmp-03.ll b/test/CodeGen/SystemZ/fp-cmp-03.ll new file mode 100644 index 000000000000..fd12c93e27a5 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-cmp-03.ll @@ -0,0 +1,20 @@ +; Test 128-bit floating-point comparison. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no memory form of 128-bit comparison. +define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: ld %f1, 0(%r4) +; CHECK: ld %f3, 8(%r4) +; CHECK: cxbr %f1, %f0 +; CHECK-NEXT: j{{g?}}e +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + %f2x = fpext float %f2 to fp128 + %f1 = load fp128 *%ptr + %cond = fcmp oeq fp128 %f1, %f2x + %res = select i1 %cond, i64 %a, i64 %b + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/fp-const-01.ll b/test/CodeGen/SystemZ/fp-const-01.ll new file mode 100644 index 000000000000..65209d661e97 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-01.ll @@ -0,0 +1,30 @@ +; Test loads of floating-point zero. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +define float @f1() { +; CHECK: f1: +; CHECK: lzer %f0 +; CHECK: br %r14 + ret float 0.0 +} + +; Test f64. +define double @f2() { +; CHECK: f2: +; CHECK: lzdr %f0 +; CHECK: br %r14 + ret double 0.0 +} + +; Test f128. +define void @f3(fp128 *%x) { +; CHECK: f3: +; CHECK: lzxr %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + store fp128 0xL00000000000000000000000000000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-const-02.ll b/test/CodeGen/SystemZ/fp-const-02.ll new file mode 100644 index 000000000000..2dedf54e6f7d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-02.ll @@ -0,0 +1,31 @@ +; Test loads of negative floating-point zero. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +define float @f1() { +; CHECK: f1: +; CHECK: lzer [[REGISTER:%f[0-5]+]] +; CHECK: lcebr %f0, [[REGISTER]] +; CHECK: br %r14 + ret float -0.0 +} + +; Test f64. +define double @f2() { +; CHECK: f2: +; CHECK: lzdr [[REGISTER:%f[0-5]+]] +; CHECK: lcdbr %f0, [[REGISTER]] +; CHECK: br %r14 + ret double -0.0 +} + +; Test f128. +define void @f3(fp128 *%x) { +; CHECK: f3: +; CHECK: lzxr [[REGISTER:%f[0-5]+]] +; CHECK: lcxbr %f0, [[REGISTER]] +; CHECK: br %r14 + store fp128 0xL00000000000000008000000000000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-const-03.ll b/test/CodeGen/SystemZ/fp-const-03.ll new file mode 100644 index 000000000000..4c287e4c08a3 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-03.ll @@ -0,0 +1,14 @@ +; Test loads of 32-bit floating-point constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define float @f1() { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}} +; CHECK: le %f0, 0([[REGISTER]]) +; CHECK: br %r14 +; +; CONST: .long 1065353217 + ret float 0x3ff0000020000000 +} diff --git a/test/CodeGen/SystemZ/fp-const-04.ll b/test/CodeGen/SystemZ/fp-const-04.ll new file mode 100644 index 000000000000..847c380e3b98 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-04.ll @@ -0,0 +1,15 @@ +; Test loads of 64-bit floating-point constants that can be represented +; as 32-bit constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define double @f1() { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}} +; CHECK: ldeb %f0, 0([[REGISTER]]) +; CHECK: br %r14 +; +; CONST: .long 1065353217 + ret double 0x3ff0000020000000 +} diff --git a/test/CodeGen/SystemZ/fp-const-05.ll b/test/CodeGen/SystemZ/fp-const-05.ll new file mode 100644 index 000000000000..48f84ce5bee8 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-05.ll @@ -0,0 +1,18 @@ +; Test loads of 128-bit floating-point constants that can be represented +; as 32-bit constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define void @f1(fp128 *%x) { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}} +; CHECK: lxeb %f0, 0([[REGISTER]]) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 +; +; CONST: .long 1065353217 + store fp128 0xL00000000000000003fff000002000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-const-06.ll b/test/CodeGen/SystemZ/fp-const-06.ll new file mode 100644 index 000000000000..1da3d5eafaae --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-06.ll @@ -0,0 +1,14 @@ +; Test loads of 64-bit floating-point constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define double @f1() { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}} +; CHECK: ld %f0, 0([[REGISTER]]) +; CHECK: br %r14 +; +; CONST: .quad 4607182419068452864 + ret double 0x3ff0000010000000 +} diff --git a/test/CodeGen/SystemZ/fp-const-07.ll b/test/CodeGen/SystemZ/fp-const-07.ll new file mode 100644 index 000000000000..5a108452a8e0 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-07.ll @@ -0,0 +1,18 @@ +; Test loads of 128-bit floating-point constants that can be represented +; as 64-bit constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define void @f1(fp128 *%x) { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}} +; CHECK: lxdb %f0, 0([[REGISTER]]) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 +; +; CONST: .quad 4607182419068452864 + store fp128 0xL00000000000000003fff000001000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-const-08.ll b/test/CodeGen/SystemZ/fp-const-08.ll new file mode 100644 index 000000000000..6a8a1ab3f9b7 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-08.ll @@ -0,0 +1,21 @@ +; Test loads of 128-bit floating-point constants. This value would actually +; fit within the x86 80-bit format, so the test make sure we don't try to +; extend from an f80. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define void @f1(fp128 *%x) { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}} +; CHECK: ld %f0, 0([[REGISTER]]) +; CHECK: ld %f2, 8([[REGISTER]]) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 +; +; CONST: .quad 4611404543450677248 +; CONST: .quad 576460752303423488 + store fp128 0xL08000000000000003fff000000000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-const-09.ll b/test/CodeGen/SystemZ/fp-const-09.ll new file mode 100644 index 000000000000..435dcbacc19d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-const-09.ll @@ -0,0 +1,20 @@ +; Test loads of 128-bit floating-point constants in which the low bit of +; the significand is set. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST + +define void @f1(fp128 *%x) { +; CHECK: f1: +; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}} +; CHECK: ld %f0, 0([[REGISTER]]) +; CHECK: ld %f2, 8([[REGISTER]]) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 +; +; CONST: .quad 4611404543450677248 +; CONST: .quad 1 + store fp128 0xL00000000000000013fff000000000000, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-01.ll b/test/CodeGen/SystemZ/fp-conv-01.ll new file mode 100644 index 000000000000..6c8ef4899776 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-01.ll @@ -0,0 +1,61 @@ +; Test floating-point truncations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f64->f32. +define float @f1(double %d1, double %d2) { +; CHECK: f1: +; CHECK: ledbr %f0, %f2 +; CHECK: br %r14 + %res = fptrunc double %d2 to float + ret float %res +} + +; Test f128->f32. +define float @f2(fp128 *%ptr) { +; CHECK: f2: +; CHECK: lexbr %f0, %f0 +; CHECK: br %r14 + %val = load fp128 *%ptr + %res = fptrunc fp128 %val to float + ret float %res +} + +; Make sure that we don't use %f0 as the destination of LEXBR when %f2 +; is still live. +define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) { +; CHECK: f3: +; CHECK: lexbr %f1, %f1 +; CHECK: aebr %f1, %f2 +; CHECK: ste %f1, 0(%r2) +; CHECK: br %r14 + %val = load fp128 *%ptr + %conv = fptrunc fp128 %val to float + %res = fadd float %conv, %d2 + store float %res, float *%dst + ret void +} + +; Test f128->f64. +define double @f4(fp128 *%ptr) { +; CHECK: f4: +; CHECK: ldxbr %f0, %f0 +; CHECK: br %r14 + %val = load fp128 *%ptr + %res = fptrunc fp128 %val to double + ret double %res +} + +; Like f3, but for f128->f64. +define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) { +; CHECK: f5: +; CHECK: ldxbr %f1, %f1 +; CHECK: adbr %f1, %f2 +; CHECK: std %f1, 0(%r2) +; CHECK: br %r14 + %val = load fp128 *%ptr + %conv = fptrunc fp128 %val to double + %res = fadd double %conv, %d2 + store double %res, double *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-02.ll b/test/CodeGen/SystemZ/fp-conv-02.ll new file mode 100644 index 000000000000..f284e1dc2ae4 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-02.ll @@ -0,0 +1,71 @@ +; Test extensions of f32 to f64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register extension. +define double @f1(float %val) { +; CHECK: f1: +; CHECK: ldebr %f0, %f0 +; CHECK: br %r14 + %res = fpext float %val to double + ret double %res +} + +; Check the low end of the LDEB range. +define double @f2(float *%ptr) { +; CHECK: f2: +; CHECK: ldeb %f0, 0(%r2) +; CHECK: br %r14 + %val = load float *%ptr + %res = fpext float %val to double + ret double %res +} + +; Check the high end of the aligned LDEB range. +define double @f3(float *%base) { +; CHECK: f3: +; CHECK: ldeb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %val = load float *%ptr + %res = fpext float %val to double + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: ldeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %val = load float *%ptr + %res = fpext float %val to double + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: ldeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %val = load float *%ptr + %res = fpext float %val to double + ret double %res +} + +; Check that LDEB allows indices. +define double @f6(float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: ldeb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %val = load float *%ptr2 + %res = fpext float %val to double + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-conv-03.ll b/test/CodeGen/SystemZ/fp-conv-03.ll new file mode 100644 index 000000000000..703a141e3e12 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-03.ll @@ -0,0 +1,89 @@ +; Test extensions of f32 to f128. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register extension. +define void @f1(fp128 *%dst, float %val) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the low end of the LXEB range. +define void @f2(fp128 *%dst, float *%ptr) { +; CHECK: f2: +; CHECK: lxeb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %val = load float *%ptr + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the high end of the aligned LXEB range. +define void @f3(fp128 *%dst, float *%base) { +; CHECK: f3: +; CHECK: lxeb %f0, 4092(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %val = load float *%ptr + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f4(fp128 *%dst, float *%base) { +; CHECK: f4: +; CHECK: aghi %r3, 4096 +; CHECK: lxeb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %val = load float *%ptr + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f5(fp128 *%dst, float *%base) { +; CHECK: f5: +; CHECK: aghi %r3, -4 +; CHECK: lxeb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %val = load float *%ptr + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check that LXEB allows indices. +define void @f6(fp128 *%dst, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r4, 2 +; CHECK: lxeb %f0, 400(%r1,%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %val = load float *%ptr2 + %res = fpext float %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-04.ll b/test/CodeGen/SystemZ/fp-conv-04.ll new file mode 100644 index 000000000000..b7b516693430 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-04.ll @@ -0,0 +1,89 @@ +; Test extensions of f64 to f128. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register extension. +define void @f1(fp128 *%dst, double %val) { +; CHECK: f1: +; CHECK: lxdbr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the low end of the LXDB range. +define void @f2(fp128 *%dst, double *%ptr) { +; CHECK: f2: +; CHECK: lxdb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %val = load double *%ptr + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the high end of the aligned LXDB range. +define void @f3(fp128 *%dst, double *%base) { +; CHECK: f3: +; CHECK: lxdb %f0, 4088(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %val = load double *%ptr + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f4(fp128 *%dst, double *%base) { +; CHECK: f4: +; CHECK: aghi %r3, 4096 +; CHECK: lxdb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %val = load double *%ptr + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f5(fp128 *%dst, double *%base) { +; CHECK: f5: +; CHECK: aghi %r3, -8 +; CHECK: lxdb %f0, 0(%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %val = load double *%ptr + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} + +; Check that LXDB allows indices. +define void @f6(fp128 *%dst, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r4, 3 +; CHECK: lxdb %f0, 800(%r1,%r3) +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %val = load double *%ptr2 + %res = fpext double %val to fp128 + store fp128 %res, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-05.ll b/test/CodeGen/SystemZ/fp-conv-05.ll new file mode 100644 index 000000000000..2d887324c3e6 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-05.ll @@ -0,0 +1,33 @@ +; Test conversions of signed i32s to floating-point values. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check i32->f32. +define float @f1(i32 %i) { +; CHECK: f1: +; CHECK: cefbr %f0, %r2 +; CHECK: br %r14 + %conv = sitofp i32 %i to float + ret float %conv +} + +; Check i32->f64. +define double @f2(i32 %i) { +; CHECK: f2: +; CHECK: cdfbr %f0, %r2 +; CHECK: br %r14 + %conv = sitofp i32 %i to double + ret double %conv +} + +; Check i32->f128. +define void @f3(i32 %i, fp128 *%dst) { +; CHECK: f3: +; CHECK: cxfbr %f0, %r2 +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %conv = sitofp i32 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-06.ll b/test/CodeGen/SystemZ/fp-conv-06.ll new file mode 100644 index 000000000000..1b39b67d49b8 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-06.ll @@ -0,0 +1,37 @@ +; Test conversions of unsigned i32s to floating-point values. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check i32->f32. There is no native instruction, so we must promote +; to i64 first. +define float @f1(i32 %i) { +; CHECK: f1: +; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2 +; CHECK: cegbr %f0, [[REGISTER]] +; CHECK: br %r14 + %conv = uitofp i32 %i to float + ret float %conv +} + +; Check i32->f64. +define double @f2(i32 %i) { +; CHECK: f2: +; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2 +; CHECK: cdgbr %f0, [[REGISTER]] +; CHECK: br %r14 + %conv = uitofp i32 %i to double + ret double %conv +} + +; Check i32->f128. +define void @f3(i32 %i, fp128 *%dst) { +; CHECK: f3: +; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2 +; CHECK: cxgbr %f0, [[REGISTER]] +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %conv = uitofp i32 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-07.ll b/test/CodeGen/SystemZ/fp-conv-07.ll new file mode 100644 index 000000000000..0ebbd37d512d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-07.ll @@ -0,0 +1,33 @@ +; Test conversions of signed i64s to floating-point values. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test i64->f32. +define float @f1(i64 %i) { +; CHECK: f1: +; CHECK: cegbr %f0, %r2 +; CHECK: br %r14 + %conv = sitofp i64 %i to float + ret float %conv +} + +; Test i64->f64. +define double @f2(i64 %i) { +; CHECK: f2: +; CHECK: cdgbr %f0, %r2 +; CHECK: br %r14 + %conv = sitofp i64 %i to double + ret double %conv +} + +; Test i64->f128. +define void @f3(i64 %i, fp128 *%dst) { +; CHECK: f3: +; CHECK: cxgbr %f0, %r2 +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %conv = sitofp i64 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-08.ll b/test/CodeGen/SystemZ/fp-conv-08.ll new file mode 100644 index 000000000000..20c4e30f0796 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-08.ll @@ -0,0 +1,35 @@ +; Test conversions of unsigned i64s to floating-point values. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test i64->f32. There's no native support for unsigned i64-to-fp conversions, +; but we should be able to implement them using signed i64-to-fp conversions. +define float @f1(i64 %i) { +; CHECK: f1: +; CHECK: cegbr +; CHECK: aebr +; CHECK: br %r14 + %conv = uitofp i64 %i to float + ret float %conv +} + +; Test i64->f64. +define double @f2(i64 %i) { +; CHECK: f2: +; CHECK: ldgr +; CHECL: adbr +; CHECK: br %r14 + %conv = uitofp i64 %i to double + ret double %conv +} + +; Test i64->f128. +define void @f3(i64 %i, fp128 *%dst) { +; CHECK: f3: +; CHECK: cxgbr +; CHECK: axbr +; CHECK: br %r14 + %conv = uitofp i64 %i to fp128 + store fp128 %conv, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-conv-09.ll b/test/CodeGen/SystemZ/fp-conv-09.ll new file mode 100644 index 000000000000..e3c0352cf84e --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-09.ll @@ -0,0 +1,33 @@ +; Test conversion of floating-point values to signed i32s. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32->i32. +define i32 @f1(float %f) { +; CHECK: f1: +; CHECK: cfebr %r2, 5, %f0 +; CHECK: br %r14 + %conv = fptosi float %f to i32 + ret i32 %conv +} + +; Test f64->i32. +define i32 @f2(double %f) { +; CHECK: f2: +; CHECK: cfdbr %r2, 5, %f0 +; CHECK: br %r14 + %conv = fptosi double %f to i32 + ret i32 %conv +} + +; Test f128->i32. +define i32 @f3(fp128 *%src) { +; CHECK: f3: +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: cfxbr %r2, 5, %f0 +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptosi fp128 %f to i32 + ret i32 %conv +} diff --git a/test/CodeGen/SystemZ/fp-conv-10.ll b/test/CodeGen/SystemZ/fp-conv-10.ll new file mode 100644 index 000000000000..bb8878bacee8 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-10.ll @@ -0,0 +1,45 @@ +; Test conversion of floating-point values to unsigned i32s. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; z10 doesn't have native support for unsigned fp-to-i32 conversions; +; they were added in z196 as the Convert to Logical family of instructions. +; Promoting to i64 doesn't generate an inexact condition for values that are +; outside the i32 range but in the i64 range, so use the default expansion. + +; Test f32->i32. +define i32 @f1(float %f) { +; CHECK: f1: +; CHECK: cebr +; CHECK: sebr +; CHECK: cfebr +; CHECK: xilf +; CHECK: br %r14 + %conv = fptoui float %f to i32 + ret i32 %conv +} + +; Test f64->i32. +define i32 @f2(double %f) { +; CHECK: f2: +; CHECK: cdbr +; CHECK: sdbr +; CHECK: cfdbr +; CHECK: xilf +; CHECK: br %r14 + %conv = fptoui double %f to i32 + ret i32 %conv +} + +; Test f128->i32. +define i32 @f3(fp128 *%src) { +; CHECK: f3: +; CHECK: cxbr +; CHECK: sxbr +; CHECK: cfxbr +; CHECK: xilf +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptoui fp128 %f to i32 + ret i32 %conv +} diff --git a/test/CodeGen/SystemZ/fp-conv-11.ll b/test/CodeGen/SystemZ/fp-conv-11.ll new file mode 100644 index 000000000000..2a36cb955cb5 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-11.ll @@ -0,0 +1,33 @@ +; Test conversion of floating-point values to signed i64s. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32->i64. +define i64 @f1(float %f) { +; CHECK: f1: +; CHECK: cgebr %r2, 5, %f0 +; CHECK: br %r14 + %conv = fptosi float %f to i64 + ret i64 %conv +} + +; Test f64->i64. +define i64 @f2(double %f) { +; CHECK: f2: +; CHECK: cgdbr %r2, 5, %f0 +; CHECK: br %r14 + %conv = fptosi double %f to i64 + ret i64 %conv +} + +; Test f128->i64. +define i64 @f3(fp128 *%src) { +; CHECK: f3: +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: cgxbr %r2, 5, %f0 +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptosi fp128 %f to i64 + ret i64 %conv +} diff --git a/test/CodeGen/SystemZ/fp-conv-12.ll b/test/CodeGen/SystemZ/fp-conv-12.ll new file mode 100644 index 000000000000..4445b14ee8ef --- /dev/null +++ b/test/CodeGen/SystemZ/fp-conv-12.ll @@ -0,0 +1,44 @@ +; Test conversion of floating-point values to unsigned i64s. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; z10 doesn't have native support for unsigned fp-to-i64 conversions; +; they were added in z196 as the Convert to Logical family of instructions. +; Convert via signed i64s instead. + +; Test f32->i64. +define i64 @f1(float %f) { +; CHECK: f1: +; CHECK: cebr +; CHECK: sebr +; CHECK: cgebr +; CHECK: xihf +; CHECK: br %r14 + %conv = fptoui float %f to i64 + ret i64 %conv +} + +; Test f64->i64. +define i64 @f2(double %f) { +; CHECK: f2: +; CHECK: cdbr +; CHECK: sdbr +; CHECK: cgdbr +; CHECK: xihf +; CHECK: br %r14 + %conv = fptoui double %f to i64 + ret i64 %conv +} + +; Test f128->i64. +define i64 @f3(fp128 *%src) { +; CHECK: f3: +; CHECK: cxbr +; CHECK: sxbr +; CHECK: cgxbr +; CHECK: xihf +; CHECK: br %r14 + %f = load fp128 *%src + %conv = fptoui fp128 %f to i64 + ret i64 %conv +} diff --git a/test/CodeGen/SystemZ/fp-copysign-01.ll b/test/CodeGen/SystemZ/fp-copysign-01.ll new file mode 100644 index 000000000000..458d475bdf3c --- /dev/null +++ b/test/CodeGen/SystemZ/fp-copysign-01.ll @@ -0,0 +1,128 @@ +; Test copysign operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare float @copysignf(float, float) readnone +declare double @copysign(double, double) readnone +; FIXME: not really the correct prototype for SystemZ. +declare fp128 @copysignl(fp128, fp128) readnone + +; Test f32 copies in which the sign comes from an f32. +define float @f1(float %a, float %b) { +; CHECK: f1: +; CHECK-NOT: %f2 +; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: br %r14 + %res = call float @copysignf(float %a, float %b) readnone + ret float %res +} + +; Test f32 copies in which the sign comes from an f64. +define float @f2(float %a, double %bd) { +; CHECK: f2: +; CHECK-NOT: %f2 +; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: br %r14 + %b = fptrunc double %bd to float + %res = call float @copysignf(float %a, float %b) readnone + ret float %res +} + +; Test f32 copies in which the sign comes from an f128. +define float @f3(float %a, fp128 *%bptr) { +; CHECK: f3: +; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2) +; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) +; CHECK: cpsdr %f0, %f0, [[BHIGH]] +; CHECK: br %r14 + %bl = load volatile fp128 *%bptr + %b = fptrunc fp128 %bl to float + %res = call float @copysignf(float %a, float %b) readnone + ret float %res +} + +; Test f64 copies in which the sign comes from an f32. +define double @f4(double %a, float %bf) { +; CHECK: f4: +; CHECK-NOT: %f2 +; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: br %r14 + %b = fpext float %bf to double + %res = call double @copysign(double %a, double %b) readnone + ret double %res +} + +; Test f64 copies in which the sign comes from an f64. +define double @f5(double %a, double %b) { +; CHECK: f5: +; CHECK-NOT: %f2 +; CHECK: cpsdr %f0, %f0, %f2 +; CHECK: br %r14 + %res = call double @copysign(double %a, double %b) readnone + ret double %res +} + +; Test f64 copies in which the sign comes from an f128. +define double @f6(double %a, fp128 *%bptr) { +; CHECK: f6: +; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2) +; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2) +; CHECK: cpsdr %f0, %f0, [[BHIGH]] +; CHECK: br %r14 + %bl = load volatile fp128 *%bptr + %b = fptrunc fp128 %bl to double + %res = call double @copysign(double %a, double %b) readnone + ret double %res +} + +; Test f128 copies in which the sign comes from an f32. We shouldn't +; need any register shuffling here; %a should be tied to %c, with CPSDR +; just changing the high register. +define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) { +; CHECK: f7: +; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) +; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) +; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0 +; CHECK: std [[AHIGH]], 0(%r2) +; CHECK: std [[ALOW]], 8(%r2) +; CHECK: br %r14 + %a = load volatile fp128 *%aptr + %b = fpext float %bf to fp128 + %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone + store fp128 %c, fp128 *%cptr + ret void +} + +; As above, but the sign comes from an f64. +define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) { +; CHECK: f8: +; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) +; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) +; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0 +; CHECK: std [[AHIGH]], 0(%r2) +; CHECK: std [[ALOW]], 8(%r2) +; CHECK: br %r14 + %a = load volatile fp128 *%aptr + %b = fpext double %bd to fp128 + %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone + store fp128 %c, fp128 *%cptr + ret void +} + +; As above, but the sign comes from an f128. Don't require the low part +; of %b to be loaded, since it isn't used. +define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) { +; CHECK: f9: +; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3) +; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3) +; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4) +; CHECK: cpsdr [[AHIGH]], [[AHIGH]], [[BHIGH]] +; CHECK: std [[AHIGH]], 0(%r2) +; CHECK: std [[ALOW]], 8(%r2) +; CHECK: br %r14 + %a = load volatile fp128 *%aptr + %b = load volatile fp128 *%bptr + %c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone + store fp128 %c, fp128 *%cptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-div-01.ll b/test/CodeGen/SystemZ/fp-div-01.ll new file mode 100644 index 000000000000..080d45eb2bfb --- /dev/null +++ b/test/CodeGen/SystemZ/fp-div-01.ll @@ -0,0 +1,71 @@ +; Test 32-bit floating-point division. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register division. +define float @f1(float %f1, float %f2) { +; CHECK: f1: +; CHECK: debr %f0, %f2 +; CHECK: br %r14 + %res = fdiv float %f1, %f2 + ret float %res +} + +; Check the low end of the DEB range. +define float @f2(float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: deb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load float *%ptr + %res = fdiv float %f1, %f2 + ret float %res +} + +; Check the high end of the aligned DEB range. +define float @f3(float %f1, float *%base) { +; CHECK: f3: +; CHECK: deb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %res = fdiv float %f1, %f2 + ret float %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f4(float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: deb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %res = fdiv float %f1, %f2 + ret float %res +} + +; Check negative displacements, which also need separate address logic. +define float @f5(float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: deb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %res = fdiv float %f1, %f2 + ret float %res +} + +; Check that DEB allows indices. +define float @f6(float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: deb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %res = fdiv float %f1, %f2 + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-div-02.ll b/test/CodeGen/SystemZ/fp-div-02.ll new file mode 100644 index 000000000000..c5cae15a824b --- /dev/null +++ b/test/CodeGen/SystemZ/fp-div-02.ll @@ -0,0 +1,71 @@ +; Test 64-bit floating-point division. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register division. +define double @f1(double %f1, double %f2) { +; CHECK: f1: +; CHECK: ddbr %f0, %f2 +; CHECK: br %r14 + %res = fdiv double %f1, %f2 + ret double %res +} + +; Check the low end of the DDB range. +define double @f2(double %f1, double *%ptr) { +; CHECK: f2: +; CHECK: ddb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load double *%ptr + %res = fdiv double %f1, %f2 + ret double %res +} + +; Check the high end of the aligned DDB range. +define double @f3(double %f1, double *%base) { +; CHECK: f3: +; CHECK: ddb %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %res = fdiv double %f1, %f2 + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %f1, double *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: ddb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %res = fdiv double %f1, %f2 + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(double %f1, double *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: ddb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %res = fdiv double %f1, %f2 + ret double %res +} + +; Check that DDB allows indices. +define double @f6(double %f1, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: ddb %f0, 800(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %res = fdiv double %f1, %f2 + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-div-03.ll b/test/CodeGen/SystemZ/fp-div-03.ll new file mode 100644 index 000000000000..18f2d7449a80 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-div-03.ll @@ -0,0 +1,20 @@ +; Test 128-bit floating-point division. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no memory form of 128-bit division. +define void @f1(fp128 *%ptr, float %f2) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: ld %f1, 0(%r2) +; CHECK: ld %f3, 8(%r2) +; CHECK: dxbr %f1, %f0 +; CHECK: std %f1, 0(%r2) +; CHECK: std %f3, 8(%r2) +; CHECK: br %r14 + %f1 = load fp128 *%ptr + %f2x = fpext float %f2 to fp128 + %sum = fdiv fp128 %f1, %f2x + store fp128 %sum, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-move-01.ll b/test/CodeGen/SystemZ/fp-move-01.ll new file mode 100644 index 000000000000..73cd978c5975 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-01.ll @@ -0,0 +1,30 @@ +; Test moves between FPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32 moves. +define float @f1(float %a, float %b) { +; CHECK: f1: +; CHECK: ler %f0, %f2 + ret float %b +} + +; Test f64 moves. +define double @f2(double %a, double %b) { +; CHECK: f2: +; CHECK: ldr %f0, %f2 + ret double %b +} + +; Test f128 moves. Since f128s are passed by reference, we need to force +; a copy by other means. +define void @f3(fp128 *%x) { +; CHECK: f3: +; CHECK: lxr +; CHECK: axbr + %val = load volatile fp128 *%x + %sum = fadd fp128 %val, %val + store volatile fp128 %sum, fp128 *%x + store volatile fp128 %val, fp128 *%x + ret void +} diff --git a/test/CodeGen/SystemZ/fp-move-02.ll b/test/CodeGen/SystemZ/fp-move-02.ll new file mode 100644 index 000000000000..9d87797c8f92 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-02.ll @@ -0,0 +1,103 @@ +; Test moves between FPRs and GPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high +; 32 bits of the FPR. +define float @f1(i32 %a) { +; CHECK: f1: +; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32 +; CHECK: ldgr %f0, [[REGISTER]] + %res = bitcast i32 %a to float + ret float %res +} + +; Like f1, but create a situation where the shift can be folded with +; surrounding code. +define float @f2(i64 %big) { +; CHECK: f2: +; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 31 +; CHECK: ldgr %f0, [[REGISTER]] + %shift = lshr i64 %big, 1 + %a = trunc i64 %shift to i32 + %res = bitcast i32 %a to float + ret float %res +} + +; Another example of the same thing. +define float @f3(i64 %big) { +; CHECK: f3: +; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 2 +; CHECK: ldgr %f0, [[REGISTER]] + %shift = ashr i64 %big, 30 + %a = trunc i64 %shift to i32 + %res = bitcast i32 %a to float + ret float %res +} + +; Like f1, but the value to transfer is already in the high 32 bits. +define float @f4(i64 %big) { +; CHECK: f4: +; CHECK-NOT: %r2 +; CHECK: nilf %r2, 0 +; CHECK-NOT: %r2 +; CHECK: ldgr %f0, %r2 + %shift = ashr i64 %big, 32 + %a = trunc i64 %shift to i32 + %res = bitcast i32 %a to float + ret float %res +} + +; Test 64-bit moves from GPRs to FPRs. +define double @f5(i64 %a) { +; CHECK: f5: +; CHECK: ldgr %f0, %r2 + %res = bitcast i64 %a to double + ret double %res +} + +; Test 128-bit moves from GPRs to FPRs. i128 isn't a legitimate type, +; so this goes through memory. +define void @f6(fp128 *%a, i128 *%b) { +; CHECK: f6: +; CHECK: lg +; CHECK: lg +; CHECK: stg +; CHECK: stg + %val = load i128 *%b + %res = bitcast i128 %val to fp128 + store fp128 %res, fp128 *%a + ret void +} + +; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should +; be moved into the low 32 bits of the GPR. +define i32 @f7(float %a) { +; CHECK: f7: +; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0 +; CHECK: srlg %r2, [[REGISTER]], 32 + %res = bitcast float %a to i32 + ret i32 %res +} + +; Test 64-bit moves from FPRs to GPRs. +define i64 @f8(double %a) { +; CHECK: f8: +; CHECK: lgdr %r2, %f0 + %res = bitcast double %a to i64 + ret i64 %res +} + +; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6. +define void @f9(fp128 *%a, i128 *%b) { +; CHECK: f9: +; CHECK: ld +; CHECK: ld +; CHECK: std +; CHECK: std + %val = load fp128 *%a + %res = bitcast fp128 %val to i128 + store i128 %res, i128 *%b + ret void +} + diff --git a/test/CodeGen/SystemZ/fp-move-03.ll b/test/CodeGen/SystemZ/fp-move-03.ll new file mode 100644 index 000000000000..37dbdfad7b87 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-03.ll @@ -0,0 +1,110 @@ +; Test 32-bit floating-point loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test the low end of the LE range. +define float @f1(float *%src) { +; CHECK: f1: +; CHECK: le %f0, 0(%r2) +; CHECK: br %r14 + %val = load float *%src + ret float %val +} + +; Test the high end of the LE range. +define float @f2(float *%src) { +; CHECK: f2: +; CHECK: le %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 1023 + %val = load float *%ptr + ret float %val +} + +; Check the next word up, which should use LEY instead of LE. +define float @f3(float *%src) { +; CHECK: f3: +; CHECK: ley %f0, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 1024 + %val = load float *%ptr + ret float %val +} + +; Check the high end of the aligned LEY range. +define float @f4(float *%src) { +; CHECK: f4: +; CHECK: ley %f0, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 131071 + %val = load float *%ptr + ret float %val +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f5(float *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: le %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 131072 + %val = load float *%ptr + ret float %val +} + +; Check the high end of the negative aligned LEY range. +define float @f6(float *%src) { +; CHECK: f6: +; CHECK: ley %f0, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -1 + %val = load float *%ptr + ret float %val +} + +; Check the low end of the LEY range. +define float @f7(float *%src) { +; CHECK: f7: +; CHECK: ley %f0, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -131072 + %val = load float *%ptr + ret float %val +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f8(float *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524292 +; CHECK: le %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -131073 + %val = load float *%ptr + ret float %val +} + +; Check that LE allows an index. +define float @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: le %f0, 4092({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to float * + %val = load float *%ptr + ret float %val +} + +; Check that LEY allows an index. +define float @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to float * + %val = load float *%ptr + ret float %val +} diff --git a/test/CodeGen/SystemZ/fp-move-04.ll b/test/CodeGen/SystemZ/fp-move-04.ll new file mode 100644 index 000000000000..72e90d1fffd1 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-04.ll @@ -0,0 +1,110 @@ +; Test 64-bit floating-point loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test the low end of the LD range. +define double @f1(double *%src) { +; CHECK: f1: +; CHECK: ld %f0, 0(%r2) +; CHECK: br %r14 + %val = load double *%src + ret double %val +} + +; Test the high end of the LD range. +define double @f2(double *%src) { +; CHECK: f2: +; CHECK: ld %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 511 + %val = load double *%ptr + ret double %val +} + +; Check the next doubleword up, which should use LDY instead of LD. +define double @f3(double *%src) { +; CHECK: f3: +; CHECK: ldy %f0, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 512 + %val = load double *%ptr + ret double %val +} + +; Check the high end of the aligned LDY range. +define double @f4(double *%src) { +; CHECK: f4: +; CHECK: ldy %f0, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 65535 + %val = load double *%ptr + ret double %val +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f5(double *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: ld %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 65536 + %val = load double *%ptr + ret double %val +} + +; Check the high end of the negative aligned LDY range. +define double @f6(double *%src) { +; CHECK: f6: +; CHECK: ldy %f0, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -1 + %val = load double *%ptr + ret double %val +} + +; Check the low end of the LDY range. +define double @f7(double *%src) { +; CHECK: f7: +; CHECK: ldy %f0, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -65536 + %val = load double *%ptr + ret double %val +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f8(double *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524296 +; CHECK: ld %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -65537 + %val = load double *%ptr + ret double %val +} + +; Check that LD allows an index. +define double @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: ld %f0, 4095({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to double * + %val = load double *%ptr + ret double %val +} + +; Check that LDY allows an index. +define double @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: ldy %f0, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to double * + %val = load double *%ptr + ret double %val +} diff --git a/test/CodeGen/SystemZ/fp-move-05.ll b/test/CodeGen/SystemZ/fp-move-05.ll new file mode 100644 index 000000000000..66ad048fbed7 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-05.ll @@ -0,0 +1,151 @@ +; Test 128-bit floating-point loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check loads with no offset. +define double @f1(i64 %src) { +; CHECK: f1: +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: br %r14 + %ptr = inttoptr i64 %src to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the highest aligned offset that allows LD for both halves. +define double @f2(i64 %src) { +; CHECK: f2: +; CHECK: ld %f0, 4080(%r2) +; CHECK: ld %f2, 4088(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4080 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the next doubleword up, which requires a mixture of LD and LDY. +define double @f3(i64 %src) { +; CHECK: f3: +; CHECK: ld %f0, 4088(%r2) +; CHECK: ldy %f2, 4096(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4088 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the next doubleword after that, which requires LDY for both halves. +define double @f4(i64 %src) { +; CHECK: f4: +; CHECK: ldy %f0, 4096(%r2) +; CHECK: ldy %f2, 4104(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4096 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the highest aligned offset that allows LDY for both halves. +define double @f5(i64 %src) { +; CHECK: f5: +; CHECK: ldy %f0, 524272(%r2) +; CHECK: ldy %f2, 524280(%r2) +; CHECK: br %r14 + %add = add i64 %src, 524272 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the next doubleword up, which requires separate address logic. +; Other sequences besides this one would be OK. +define double @f6(i64 %src) { +; CHECK: f6: +; CHECK: lay %r1, 524280(%r2) +; CHECK: ld %f0, 0(%r1) +; CHECK: ld %f2, 8(%r1) +; CHECK: br %r14 + %add = add i64 %src, 524280 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the highest aligned negative offset, which needs a combination of +; LDY and LD. +define double @f7(i64 %src) { +; CHECK: f7: +; CHECK: ldy %f0, -8(%r2) +; CHECK: ld %f2, 0(%r2) +; CHECK: br %r14 + %add = add i64 %src, -8 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the next doubleword down, which requires LDY for both halves. +define double @f8(i64 %src) { +; CHECK: f8: +; CHECK: ldy %f0, -16(%r2) +; CHECK: ldy %f2, -8(%r2) +; CHECK: br %r14 + %add = add i64 %src, -16 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the lowest offset that allows LDY for both halves. +define double @f9(i64 %src) { +; CHECK: f9: +; CHECK: ldy %f0, -524288(%r2) +; CHECK: ldy %f2, -524280(%r2) +; CHECK: br %r14 + %add = add i64 %src, -524288 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check the next doubleword down, which requires separate address logic. +; Other sequences besides this one would be OK. +define double @f10(i64 %src) { +; CHECK: f10: +; CHECK: agfi %r2, -524296 +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: br %r14 + %add = add i64 %src, -524296 + %ptr = inttoptr i64 %add to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} + +; Check that indices are allowed. +define double @f11(i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}}) +; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4088 + %ptr = inttoptr i64 %add2 to fp128 * + %val = load fp128 *%ptr + %trunc = fptrunc fp128 %val to double + ret double %trunc +} diff --git a/test/CodeGen/SystemZ/fp-move-06.ll b/test/CodeGen/SystemZ/fp-move-06.ll new file mode 100644 index 000000000000..b660c2ac223d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-06.ll @@ -0,0 +1,110 @@ +; Test 32-bit floating-point stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test the low end of the STE range. +define void @f1(float *%ptr, float %val) { +; CHECK: f1: +; CHECK: ste %f0, 0(%r2) +; CHECK: br %r14 + store float %val, float *%ptr + ret void +} + +; Test the high end of the STE range. +define void @f2(float *%src, float %val) { +; CHECK: f2: +; CHECK: ste %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 1023 + store float %val, float *%ptr + ret void +} + +; Check the next word up, which should use STEY instead of STE. +define void @f3(float *%src, float %val) { +; CHECK: f3: +; CHECK: stey %f0, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 1024 + store float %val, float *%ptr + ret void +} + +; Check the high end of the aligned STEY range. +define void @f4(float *%src, float %val) { +; CHECK: f4: +; CHECK: stey %f0, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 131071 + store float %val, float *%ptr + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f5(float *%src, float %val) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: ste %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 131072 + store float %val, float *%ptr + ret void +} + +; Check the high end of the negative aligned STEY range. +define void @f6(float *%src, float %val) { +; CHECK: f6: +; CHECK: stey %f0, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -1 + store float %val, float *%ptr + ret void +} + +; Check the low end of the STEY range. +define void @f7(float *%src, float %val) { +; CHECK: f7: +; CHECK: stey %f0, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -131072 + store float %val, float *%ptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(float *%src, float %val) { +; CHECK: f8: +; CHECK: agfi %r2, -524292 +; CHECK: ste %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%src, i64 -131073 + store float %val, float *%ptr + ret void +} + +; Check that STE allows an index. +define void @f9(i64 %src, i64 %index, float %val) { +; CHECK: f9: +; CHECK: ste %f0, 4092({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to float * + store float %val, float *%ptr + ret void +} + +; Check that STEY allows an index. +define void @f10(i64 %src, i64 %index, float %val) { +; CHECK: f10: +; CHECK: stey %f0, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to float * + store float %val, float *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-move-07.ll b/test/CodeGen/SystemZ/fp-move-07.ll new file mode 100644 index 000000000000..0cb0474157d0 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-07.ll @@ -0,0 +1,110 @@ +; Test 64-bit floating-point stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test the low end of the STD range. +define void @f1(double *%src, double %val) { +; CHECK: f1: +; CHECK: std %f0, 0(%r2) +; CHECK: br %r14 + store double %val, double *%src + ret void +} + +; Test the high end of the STD range. +define void @f2(double *%src, double %val) { +; CHECK: f2: +; CHECK: std %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 511 + store double %val, double *%ptr + ret void +} + +; Check the next doubleword up, which should use STDY instead of STD. +define void @f3(double *%src, double %val) { +; CHECK: f3: +; CHECK: stdy %f0, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 512 + store double %val, double *%ptr + ret void +} + +; Check the high end of the aligned STDY range. +define void @f4(double *%src, double %val) { +; CHECK: f4: +; CHECK: stdy %f0, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 65535 + store double %val, double *%ptr + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f5(double *%src, double %val) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: std %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 65536 + store double %val, double *%ptr + ret void +} + +; Check the high end of the negative aligned STDY range. +define void @f6(double *%src, double %val) { +; CHECK: f6: +; CHECK: stdy %f0, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -1 + store double %val, double *%ptr + ret void +} + +; Check the low end of the STDY range. +define void @f7(double *%src, double %val) { +; CHECK: f7: +; CHECK: stdy %f0, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -65536 + store double %val, double *%ptr + ret void +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(double *%src, double %val) { +; CHECK: f8: +; CHECK: agfi %r2, -524296 +; CHECK: std %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%src, i64 -65537 + store double %val, double *%ptr + ret void +} + +; Check that STD allows an index. +define void @f9(i64 %src, i64 %index, double %val) { +; CHECK: f9: +; CHECK: std %f0, 4095({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to double * + store double %val, double *%ptr + ret void +} + +; Check that STDY allows an index. +define void @f10(i64 %src, i64 %index, double %val) { +; CHECK: f10: +; CHECK: stdy %f0, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to double * + store double %val, double *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-move-08.ll b/test/CodeGen/SystemZ/fp-move-08.ll new file mode 100644 index 000000000000..448d2ace1762 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-move-08.ll @@ -0,0 +1,151 @@ +; Test 128-bit floating-point stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check stores with no offset. +define void @f1(i64 %src, double %val) { +; CHECK: f1: +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %ptr = inttoptr i64 %src to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the highest aligned offset that allows STD for both halves. +define void @f2(i64 %src, double %val) { +; CHECK: f2: +; CHECK: std %f0, 4080(%r2) +; CHECK: std %f2, 4088(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4080 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the next doubleword up, which requires a mixture of STD and STDY. +define void @f3(i64 %src, double %val) { +; CHECK: f3: +; CHECK: std %f0, 4088(%r2) +; CHECK: stdy %f2, 4096(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4088 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the next doubleword after that, which requires STDY for both halves. +define void @f4(i64 %src, double %val) { +; CHECK: f4: +; CHECK: stdy %f0, 4096(%r2) +; CHECK: stdy %f2, 4104(%r2) +; CHECK: br %r14 + %add = add i64 %src, 4096 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the highest aligned offset that allows STDY for both halves. +define void @f5(i64 %src, double %val) { +; CHECK: f5: +; CHECK: stdy %f0, 524272(%r2) +; CHECK: stdy %f2, 524280(%r2) +; CHECK: br %r14 + %add = add i64 %src, 524272 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the next doubleword up, which requires separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i64 %src, double %val) { +; CHECK: f6: +; CHECK: lay %r1, 524280(%r2) +; CHECK: std %f0, 0(%r1) +; CHECK: std %f2, 8(%r1) +; CHECK: br %r14 + %add = add i64 %src, 524280 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the highest aligned negative offset, which needs a combination of +; STDY and STD. +define void @f7(i64 %src, double %val) { +; CHECK: f7: +; CHECK: stdy %f0, -8(%r2) +; CHECK: std %f2, 0(%r2) +; CHECK: br %r14 + %add = add i64 %src, -8 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the next doubleword down, which requires STDY for both halves. +define void @f8(i64 %src, double %val) { +; CHECK: f8: +; CHECK: stdy %f0, -16(%r2) +; CHECK: stdy %f2, -8(%r2) +; CHECK: br %r14 + %add = add i64 %src, -16 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the lowest offset that allows STDY for both halves. +define void @f9(i64 %src, double %val) { +; CHECK: f9: +; CHECK: stdy %f0, -524288(%r2) +; CHECK: stdy %f2, -524280(%r2) +; CHECK: br %r14 + %add = add i64 %src, -524288 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check the next doubleword down, which requires separate address logic. +; Other sequences besides this one would be OK. +define void @f10(i64 %src, double %val) { +; CHECK: f10: +; CHECK: agfi %r2, -524296 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %add = add i64 %src, -524296 + %ptr = inttoptr i64 %add to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} + +; Check that indices are allowed. +define void @f11(i64 %src, i64 %index, double %val) { +; CHECK: f11: +; CHECK: std %f0, 4088({{%r2,%r3|%r3,%r2}}) +; CHECK: stdy %f2, 4096({{%r2,%r3|%r3,%r2}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4088 + %ptr = inttoptr i64 %add2 to fp128 * + %ext = fpext double %val to fp128 + store fp128 %ext, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-mul-01.ll b/test/CodeGen/SystemZ/fp-mul-01.ll new file mode 100644 index 000000000000..68c78ee2da6b --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-01.ll @@ -0,0 +1,71 @@ +; Test multiplication of two f32s, producing an f32 result. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register multiplication. +define float @f1(float %f1, float %f2) { +; CHECK: f1: +; CHECK: meebr %f0, %f2 +; CHECK: br %r14 + %res = fmul float %f1, %f2 + ret float %res +} + +; Check the low end of the MEEB range. +define float @f2(float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: meeb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load float *%ptr + %res = fmul float %f1, %f2 + ret float %res +} + +; Check the high end of the aligned MEEB range. +define float @f3(float %f1, float *%base) { +; CHECK: f3: +; CHECK: meeb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %res = fmul float %f1, %f2 + ret float %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f4(float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: meeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %res = fmul float %f1, %f2 + ret float %res +} + +; Check negative displacements, which also need separate address logic. +define float @f5(float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: meeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %res = fmul float %f1, %f2 + ret float %res +} + +; Check that MEEB allows indices. +define float @f6(float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: meeb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %res = fmul float %f1, %f2 + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-02.ll b/test/CodeGen/SystemZ/fp-mul-02.ll new file mode 100644 index 000000000000..ec51a4c1d679 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-02.ll @@ -0,0 +1,83 @@ +; Test multiplication of two f32s, producing an f64 result. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register multiplication. +define double @f1(float %f1, float %f2) { +; CHECK: f1: +; CHECK: mdebr %f0, %f2 +; CHECK: br %r14 + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} + +; Check the low end of the MDEB range. +define double @f2(float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: mdeb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load float *%ptr + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} + +; Check the high end of the aligned MDEB range. +define double @f3(float %f1, float *%base) { +; CHECK: f3: +; CHECK: mdeb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: mdeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: mdeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} + +; Check that MDEB allows indices. +define double @f6(float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: mdeb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %f1x = fpext float %f1 to double + %f2x = fpext float %f2 to double + %res = fmul double %f1x, %f2x + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-03.ll b/test/CodeGen/SystemZ/fp-mul-03.ll new file mode 100644 index 000000000000..9849247deccb --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-03.ll @@ -0,0 +1,71 @@ +; Test multiplication of two f64s, producing an f64 result. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register multiplication. +define double @f1(double %f1, double %f2) { +; CHECK: f1: +; CHECK: mdbr %f0, %f2 +; CHECK: br %r14 + %res = fmul double %f1, %f2 + ret double %res +} + +; Check the low end of the MDB range. +define double @f2(double %f1, double *%ptr) { +; CHECK: f2: +; CHECK: mdb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load double *%ptr + %res = fmul double %f1, %f2 + ret double %res +} + +; Check the high end of the aligned MDB range. +define double @f3(double %f1, double *%base) { +; CHECK: f3: +; CHECK: mdb %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %res = fmul double %f1, %f2 + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %f1, double *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: mdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %res = fmul double %f1, %f2 + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(double %f1, double *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: mdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %res = fmul double %f1, %f2 + ret double %res +} + +; Check that MDB allows indices. +define double @f6(double %f1, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: mdb %f0, 800(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %res = fmul double %f1, %f2 + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-04.ll b/test/CodeGen/SystemZ/fp-mul-04.ll new file mode 100644 index 000000000000..712ead85cbd4 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-04.ll @@ -0,0 +1,103 @@ +; Test multiplication of two f64s, producing an f128 result. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register multiplication. "mxdbr %f0, %f2" is not valid from LLVM's +; point of view, because %f2 is the low register of the FP128 %f0. Pass the +; multiplier in %f4 instead. +define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) { +; CHECK: f1: +; CHECK: mxdbr %f0, %f4 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} + +; Check the low end of the MXDB range. +define void @f2(double %f1, double *%ptr, fp128 *%dst) { +; CHECK: f2: +; CHECK: mxdb %f0, 0(%r2) +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %f2 = load double *%ptr + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} + +; Check the high end of the aligned MXDB range. +define void @f3(double %f1, double *%base, fp128 *%dst) { +; CHECK: f3: +; CHECK: mxdb %f0, 4088(%r2) +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f4(double %f1, double *%base, fp128 *%dst) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: mxdb %f0, 0(%r2) +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f5(double %f1, double *%base, fp128 *%dst) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: mxdb %f0, 0(%r2) +; CHECK: std %f0, 0(%r3) +; CHECK: std %f2, 8(%r3) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} + +; Check that MXDB allows indices. +define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: mxdb %f0, 800(%r1,%r2) +; CHECK: std %f0, 0(%r4) +; CHECK: std %f2, 8(%r4) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %f1x = fpext double %f1 to fp128 + %f2x = fpext double %f2 to fp128 + %res = fmul fp128 %f1x, %f2x + store fp128 %res, fp128 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/fp-mul-05.ll b/test/CodeGen/SystemZ/fp-mul-05.ll new file mode 100644 index 000000000000..df5bc4e70755 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-05.ll @@ -0,0 +1,20 @@ +; Test multiplication of two f128s. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no memory form of 128-bit multiplication. +define void @f1(fp128 *%ptr, float %f2) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: ld %f1, 0(%r2) +; CHECK: ld %f3, 8(%r2) +; CHECK: mxbr %f1, %f0 +; CHECK: std %f1, 0(%r2) +; CHECK: std %f3, 8(%r2) +; CHECK: br %r14 + %f1 = load fp128 *%ptr + %f2x = fpext float %f2 to fp128 + %diff = fmul fp128 %f1, %f2x + store fp128 %diff, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-mul-06.ll b/test/CodeGen/SystemZ/fp-mul-06.ll new file mode 100644 index 000000000000..8124c680371d --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-06.ll @@ -0,0 +1,102 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare float @llvm.fma.f32(float %f1, float %f2, float %f3) + +define float @f1(float %f1, float %f2, float %acc) { +; CHECK: f1: +; CHECK: maebr %f4, %f0, %f2 +; CHECK: ler %f0, %f4 +; CHECK: br %r14 + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f2(float %f1, float *%ptr, float %acc) { +; CHECK: f2: +; CHECK: maeb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f3(float %f1, float *%base, float %acc) { +; CHECK: f3: +; CHECK: maeb %f2, %f0, 4092(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f4(float %f1, float *%base, float %acc) { +; The important thing here is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: maeb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f5(float %f1, float *%base, float %acc) { +; Here too the important thing is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: maeb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f6(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: maeb %f2, %f0, 0(%r1,%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 %index + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f7(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f7: +; CHECK: sllg %r1, %r3, 2 +; CHECK: maeb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}}) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 1023 + %ptr = getelementptr float *%base, i64 %index2 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} + +define float @f8(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f8: +; CHECK: sllg %r1, %r3, 2 +; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}}) +; CHECK: maeb %f2, %f0, 0(%r1) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 1024 + %ptr = getelementptr float *%base, i64 %index2 + %f2 = load float *%ptr + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %acc) + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-07.ll b/test/CodeGen/SystemZ/fp-mul-07.ll new file mode 100644 index 000000000000..b8e44830f331 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-07.ll @@ -0,0 +1,102 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare double @llvm.fma.f64(double %f1, double %f2, double %f3) + +define double @f1(double %f1, double %f2, double %acc) { +; CHECK: f1: +; CHECK: madbr %f4, %f0, %f2 +; CHECK: ldr %f0, %f4 +; CHECK: br %r14 + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f2(double %f1, double *%ptr, double %acc) { +; CHECK: f2: +; CHECK: madb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f3(double %f1, double *%base, double %acc) { +; CHECK: f3: +; CHECK: madb %f2, %f0, 4088(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f4(double %f1, double *%base, double %acc) { +; The important thing here is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: madb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f5(double %f1, double *%base, double %acc) { +; Here too the important thing is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: madb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f6(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: madb %f2, %f0, 0(%r1,%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 %index + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f7(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f7: +; CHECK: sllg %r1, %r3, 3 +; CHECK: madb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}}) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 511 + %ptr = getelementptr double *%base, i64 %index2 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} + +define double @f8(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f8: +; CHECK: sllg %r1, %r3, 3 +; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}}) +; CHECK: madb %f2, %f0, 0(%r1) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 512 + %ptr = getelementptr double *%base, i64 %index2 + %f2 = load double *%ptr + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-08.ll b/test/CodeGen/SystemZ/fp-mul-08.ll new file mode 100644 index 000000000000..5c1474063a16 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-08.ll @@ -0,0 +1,110 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare float @llvm.fma.f32(float %f1, float %f2, float %f3) + +define float @f1(float %f1, float %f2, float %acc) { +; CHECK: f1: +; CHECK: msebr %f4, %f0, %f2 +; CHECK: ler %f0, %f4 +; CHECK: br %r14 + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f2(float %f1, float *%ptr, float %acc) { +; CHECK: f2: +; CHECK: mseb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f3(float %f1, float *%base, float %acc) { +; CHECK: f3: +; CHECK: mseb %f2, %f0, 4092(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f4(float %f1, float *%base, float %acc) { +; The important thing here is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: mseb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f5(float %f1, float *%base, float %acc) { +; Here too the important thing is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: mseb %f2, %f0, 0(%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f6(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: mseb %f2, %f0, 0(%r1,%r2) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 %index + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f7(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f7: +; CHECK: sllg %r1, %r3, 2 +; CHECK: mseb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}}) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 1023 + %ptr = getelementptr float *%base, i64 %index2 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} + +define float @f8(float %f1, float *%base, i64 %index, float %acc) { +; CHECK: f8: +; CHECK: sllg %r1, %r3, 2 +; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}}) +; CHECK: mseb %f2, %f0, 0(%r1) +; CHECK: ler %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 1024 + %ptr = getelementptr float *%base, i64 %index2 + %f2 = load float *%ptr + %negacc = fsub float -0.0, %acc + %res = call float @llvm.fma.f32 (float %f1, float %f2, float %negacc) + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-09.ll b/test/CodeGen/SystemZ/fp-mul-09.ll new file mode 100644 index 000000000000..bcae1e35e6eb --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-09.ll @@ -0,0 +1,110 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare double @llvm.fma.f64(double %f1, double %f2, double %f3) + +define double @f1(double %f1, double %f2, double %acc) { +; CHECK: f1: +; CHECK: msdbr %f4, %f0, %f2 +; CHECK: ldr %f0, %f4 +; CHECK: br %r14 + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f2(double %f1, double *%ptr, double %acc) { +; CHECK: f2: +; CHECK: msdb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f3(double %f1, double *%base, double %acc) { +; CHECK: f3: +; CHECK: msdb %f2, %f0, 4088(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f4(double %f1, double *%base, double %acc) { +; The important thing here is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: msdb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f5(double %f1, double *%base, double %acc) { +; Here too the important thing is that we don't generate an out-of-range +; displacement. Other sequences besides this one would be OK. +; +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: msdb %f2, %f0, 0(%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f6(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: msdb %f2, %f0, 0(%r1,%r2) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 %index + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f7(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f7: +; CHECK: sllg %r1, %r3, 3 +; CHECK: msdb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}}) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 511 + %ptr = getelementptr double *%base, i64 %index2 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} + +define double @f8(double %f1, double *%base, i64 %index, double %acc) { +; CHECK: f8: +; CHECK: sllg %r1, %r3, 3 +; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}}) +; CHECK: msdb %f2, %f0, 0(%r1) +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %index2 = add i64 %index, 512 + %ptr = getelementptr double *%base, i64 %index2 + %f2 = load double *%ptr + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-neg-01.ll b/test/CodeGen/SystemZ/fp-neg-01.ll new file mode 100644 index 000000000000..09a4a53e41d1 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-neg-01.ll @@ -0,0 +1,38 @@ +; Test floating-point negation. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +define float @f1(float %f) { +; CHECK: f1: +; CHECK: lcebr %f0, %f0 +; CHECK: br %r14 + %res = fsub float -0.0, %f + ret float %res +} + +; Test f64. +define double @f2(double %f) { +; CHECK: f2: +; CHECK: lcdbr %f0, %f0 +; CHECK: br %r14 + %res = fsub double -0.0, %f + ret double %res +} + +; Test f128. With the loads and stores, a pure negation would probably +; be better implemented using an XI on the upper byte. Do some extra +; processing so that using FPRs is unequivocally better. +define void @f3(fp128 *%ptr, fp128 *%ptr2) { +; CHECK: f3: +; CHECK: lcxbr +; CHECK: dxbr +; CHECK: br %r14 + %orig = load fp128 *%ptr + %negzero = fpext float -0.0 to fp128 + %neg = fsub fp128 0xL00000000000000008000000000000000, %orig + %op2 = load fp128 *%ptr2 + %res = fdiv fp128 %neg, %op2 + store fp128 %res, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-round-01.ll b/test/CodeGen/SystemZ/fp-round-01.ll new file mode 100644 index 000000000000..20325c336648 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-round-01.ll @@ -0,0 +1,36 @@ +; Test rint()-like rounding, with non-integer values triggering an +; inexact condition. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test f32. +declare float @llvm.rint.f32(float %f) +define float @f1(float %f) { +; CHECK: f1: +; CHECK: fiebr %f0, 0, %f0 +; CHECK: br %r14 + %res = call float @llvm.rint.f32(float %f) + ret float %res +} + +; Test f64. +declare double @llvm.rint.f64(double %f) +define double @f2(double %f) { +; CHECK: f2: +; CHECK: fidbr %f0, 0, %f0 +; CHECK: br %r14 + %res = call double @llvm.rint.f64(double %f) + ret double %res +} + +; Test f128. +declare fp128 @llvm.rint.f128(fp128 %f) +define void @f3(fp128 *%ptr) { +; CHECK: f3: +; CHECK: fixbr %f0, 0, %f0 +; CHECK: br %r14 + %src = load fp128 *%ptr + %res = call fp128 @llvm.rint.f128(fp128 %src) + store fp128 %res, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-sqrt-01.ll b/test/CodeGen/SystemZ/fp-sqrt-01.ll new file mode 100644 index 000000000000..7ed27f56d0d0 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sqrt-01.ll @@ -0,0 +1,73 @@ +; Test 32-bit square root. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare float @llvm.sqrt.f32(float %f) + +; Check register square root. +define float @f1(float %val) { +; CHECK: f1: +; CHECK: sqebr %f0, %f0 +; CHECK: br %r14 + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} + +; Check the low end of the SQEB range. +define float @f2(float *%ptr) { +; CHECK: f2: +; CHECK: sqeb %f0, 0(%r2) +; CHECK: br %r14 + %val = load float *%ptr + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} + +; Check the high end of the aligned SQEB range. +define float @f3(float *%base) { +; CHECK: f3: +; CHECK: sqeb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %val = load float *%ptr + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f4(float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: sqeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %val = load float *%ptr + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} + +; Check negative displacements, which also need separate address logic. +define float @f5(float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: sqeb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %val = load float *%ptr + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} + +; Check that SQEB allows indices. +define float @f6(float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: sqeb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %val = load float *%ptr2 + %res = call float @llvm.sqrt.f32(float %val) + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-sqrt-02.ll b/test/CodeGen/SystemZ/fp-sqrt-02.ll new file mode 100644 index 000000000000..22a91ad2f4f7 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sqrt-02.ll @@ -0,0 +1,73 @@ +; Test 64-bit square root. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare double @llvm.sqrt.f64(double %f) + +; Check register square root. +define double @f1(double %val) { +; CHECK: f1: +; CHECK: sqdbr %f0, %f0 +; CHECK: br %r14 + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} + +; Check the low end of the SQDB range. +define double @f2(double *%ptr) { +; CHECK: f2: +; CHECK: sqdb %f0, 0(%r2) +; CHECK: br %r14 + %val = load double *%ptr + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} + +; Check the high end of the aligned SQDB range. +define double @f3(double *%base) { +; CHECK: f3: +; CHECK: sqdb %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %val = load double *%ptr + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: sqdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %val = load double *%ptr + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(double *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: sqdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %val = load double *%ptr + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} + +; Check that SQDB allows indices. +define double @f6(double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: sqdb %f0, 800(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %val = load double *%ptr2 + %res = call double @llvm.sqrt.f64(double %val) + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-sqrt-03.ll b/test/CodeGen/SystemZ/fp-sqrt-03.ll new file mode 100644 index 000000000000..1b49af41254f --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sqrt-03.ll @@ -0,0 +1,20 @@ +; Test 128-bit square root. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare fp128 @llvm.sqrt.f128(fp128 %f) + +; There's no memory form of SQXBR. +define void @f1(fp128 *%ptr) { +; CHECK: f1: +; CHECK: ld %f0, 0(%r2) +; CHECK: ld %f2, 8(%r2) +; CHECK: sqxbr %f0, %f0 +; CHECK: std %f0, 0(%r2) +; CHECK: std %f2, 8(%r2) +; CHECK: br %r14 + %orig = load fp128 *%ptr + %sqrt = call fp128 @llvm.sqrt.f128(fp128 %orig) + store fp128 %sqrt, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/fp-sub-01.ll b/test/CodeGen/SystemZ/fp-sub-01.ll new file mode 100644 index 000000000000..b03f04bd017e --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sub-01.ll @@ -0,0 +1,71 @@ +; Test 32-bit floating-point subtraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register subtraction. +define float @f1(float %f1, float %f2) { +; CHECK: f1: +; CHECK: sebr %f0, %f2 +; CHECK: br %r14 + %res = fsub float %f1, %f2 + ret float %res +} + +; Check the low end of the SEB range. +define float @f2(float %f1, float *%ptr) { +; CHECK: f2: +; CHECK: seb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load float *%ptr + %res = fsub float %f1, %f2 + ret float %res +} + +; Check the high end of the aligned SEB range. +define float @f3(float %f1, float *%base) { +; CHECK: f3: +; CHECK: seb %f0, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1023 + %f2 = load float *%ptr + %res = fsub float %f1, %f2 + ret float %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define float @f4(float %f1, float *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: seb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 1024 + %f2 = load float *%ptr + %res = fsub float %f1, %f2 + ret float %res +} + +; Check negative displacements, which also need separate address logic. +define float @f5(float %f1, float *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -4 +; CHECK: seb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr float *%base, i64 -1 + %f2 = load float *%ptr + %res = fsub float %f1, %f2 + ret float %res +} + +; Check that SEB allows indices. +define float @f6(float %f1, float *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 2 +; CHECK: seb %f0, 400(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr float *%base, i64 %index + %ptr2 = getelementptr float *%ptr1, i64 100 + %f2 = load float *%ptr2 + %res = fsub float %f1, %f2 + ret float %res +} diff --git a/test/CodeGen/SystemZ/fp-sub-02.ll b/test/CodeGen/SystemZ/fp-sub-02.ll new file mode 100644 index 000000000000..bf9848c2fd51 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sub-02.ll @@ -0,0 +1,71 @@ +; Test 64-bit floating-point subtraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register subtraction. +define double @f1(double %f1, double %f2) { +; CHECK: f1: +; CHECK: sdbr %f0, %f2 +; CHECK: br %r14 + %res = fsub double %f1, %f2 + ret double %res +} + +; Check the low end of the SDB range. +define double @f2(double %f1, double *%ptr) { +; CHECK: f2: +; CHECK: sdb %f0, 0(%r2) +; CHECK: br %r14 + %f2 = load double *%ptr + %res = fsub double %f1, %f2 + ret double %res +} + +; Check the high end of the aligned SDB range. +define double @f3(double %f1, double *%base) { +; CHECK: f3: +; CHECK: sdb %f0, 4088(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 511 + %f2 = load double *%ptr + %res = fsub double %f1, %f2 + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %f1, double *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: sdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 512 + %f2 = load double *%ptr + %res = fsub double %f1, %f2 + ret double %res +} + +; Check negative displacements, which also need separate address logic. +define double @f5(double %f1, double *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -8 +; CHECK: sdb %f0, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr double *%base, i64 -1 + %f2 = load double *%ptr + %res = fsub double %f1, %f2 + ret double %res +} + +; Check that SDB allows indices. +define double @f6(double %f1, double *%base, i64 %index) { +; CHECK: f6: +; CHECK: sllg %r1, %r3, 3 +; CHECK: sdb %f0, 800(%r1,%r2) +; CHECK: br %r14 + %ptr1 = getelementptr double *%base, i64 %index + %ptr2 = getelementptr double *%ptr1, i64 100 + %f2 = load double *%ptr2 + %res = fsub double %f1, %f2 + ret double %res +} diff --git a/test/CodeGen/SystemZ/fp-sub-03.ll b/test/CodeGen/SystemZ/fp-sub-03.ll new file mode 100644 index 000000000000..82bb94dd28b3 --- /dev/null +++ b/test/CodeGen/SystemZ/fp-sub-03.ll @@ -0,0 +1,20 @@ +; Test 128-bit floating-point subtraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; There is no memory form of 128-bit subtraction. +define void @f1(fp128 *%ptr, float %f2) { +; CHECK: f1: +; CHECK: lxebr %f0, %f0 +; CHECK: ld %f1, 0(%r2) +; CHECK: ld %f3, 8(%r2) +; CHECK: sxbr %f1, %f0 +; CHECK: std %f1, 0(%r2) +; CHECK: std %f3, 8(%r2) +; CHECK: br %r14 + %f1 = load fp128 *%ptr + %f2x = fpext float %f2 to fp128 + %sum = fsub fp128 %f1, %f2x + store fp128 %sum, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-01.ll b/test/CodeGen/SystemZ/frame-01.ll new file mode 100644 index 000000000000..0d343128c4cd --- /dev/null +++ b/test/CodeGen/SystemZ/frame-01.ll @@ -0,0 +1,110 @@ +; Test the allocation of frames in cases where we do not need to save +; registers in the prologue. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; The CFA offset is 160 (the caller-allocated part of the frame) + 168. +define void @f1(i64 %x) { +; CHECK: f1: +; CHECK: aghi %r15, -168 +; CHECK: .cfi_def_cfa_offset 328 +; CHECK: stg %r2, 160(%r15) +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %y = alloca i64, align 8 + store volatile i64 %x, i64* %y + ret void +} + +; Check frames of size 32760, which is the largest size that can be both +; allocated and freed using AGHI. This size is big enough to require +; an emergency spill slot at 160(%r15), for instructions with unsigned +; 12-bit offsets that end up being out of range. Fill the remaining +; 32760 - 168 bytes by allocating (32760 - 168) / 8 = 4074 doublewords. +define void @f2(i64 %x) { +; CHECK: f2: +; CHECK: aghi %r15, -32760 +; CHECK: .cfi_def_cfa_offset 32920 +; CHECK: stg %r2, 168(%r15) +; CHECK: aghi %r15, 32760 +; CHECK: br %r14 + %y = alloca [4074 x i64], align 8 + %ptr = getelementptr inbounds [4074 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; Allocate one more doubleword. This is the one frame size that we can +; allocate using AGHI but must free using AGFI. +define void @f3(i64 %x) { +; CHECK: f3: +; CHECK: aghi %r15, -32768 +; CHECK: .cfi_def_cfa_offset 32928 +; CHECK: stg %r2, 168(%r15) +; CHECK: agfi %r15, 32768 +; CHECK: br %r14 + %y = alloca [4075 x i64], align 8 + %ptr = getelementptr inbounds [4075 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; Allocate another doubleword on top of that. The allocation and free +; must both use AGFI. +define void @f4(i64 %x) { +; CHECK: f4: +; CHECK: agfi %r15, -32776 +; CHECK: .cfi_def_cfa_offset 32936 +; CHECK: stg %r2, 168(%r15) +; CHECK: agfi %r15, 32776 +; CHECK: br %r14 + %y = alloca [4076 x i64], align 8 + %ptr = getelementptr inbounds [4076 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; The largest size that can be both allocated and freed using AGFI. +; At this point the frame is too big to represent properly in the CFI. +define void @f5(i64 %x) { +; CHECK: f5: +; CHECK: agfi %r15, -2147483640 +; CHECK: stg %r2, 168(%r15) +; CHECK: agfi %r15, 2147483640 +; CHECK: br %r14 + %y = alloca [268435434 x i64], align 8 + %ptr = getelementptr inbounds [268435434 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; The only frame size that can be allocated using a single AGFI but which +; must be freed using two instructions. +define void @f6(i64 %x) { +; CHECK: f6: +; CHECK: agfi %r15, -2147483648 +; CHECK: stg %r2, 168(%r15) +; CHECK: agfi %r15, 2147483640 +; CHECK: aghi %r15, 8 +; CHECK: br %r14 + %y = alloca [268435435 x i64], align 8 + %ptr = getelementptr inbounds [268435435 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; The smallest frame size that needs two instructions to both allocate +; and free the frame. +define void @f7(i64 %x) { +; CHECK: f7: +; CHECK: agfi %r15, -2147483648 +; CHECK: aghi %r15, -8 +; CHECK: stg %r2, 168(%r15) +; CHECK: agfi %r15, 2147483640 +; CHECK: aghi %r15, 16 +; CHECK: br %r14 + %y = alloca [268435436 x i64], align 8 + %ptr = getelementptr inbounds [268435436 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-02.ll b/test/CodeGen/SystemZ/frame-02.ll new file mode 100644 index 000000000000..589703ec0e74 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-02.ll @@ -0,0 +1,257 @@ +; Test saving and restoring of call-saved FPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This function should require all FPRs, but no other spill slots. +; We need to save and restore 8 of the 16 FPRs, so the frame size +; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160 +; (the caller-allocated part of the frame) + 224. +define void @f1(float *%ptr) { +; CHECK: f1: +; CHECK: aghi %r15, -224 +; CHECK: .cfi_def_cfa_offset 384 +; CHECK: std %f8, 216(%r15) +; CHECK: std %f9, 208(%r15) +; CHECK: std %f10, 200(%r15) +; CHECK: std %f11, 192(%r15) +; CHECK: std %f12, 184(%r15) +; CHECK: std %f13, 176(%r15) +; CHECK: std %f14, 168(%r15) +; CHECK: std %f15, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK: .cfi_offset %f15, -224 +; ...main function body... +; CHECK: ld %f8, 216(%r15) +; CHECK: ld %f9, 208(%r15) +; CHECK: ld %f10, 200(%r15) +; CHECK: ld %f11, 192(%r15) +; CHECK: ld %f12, 184(%r15) +; CHECK: ld %f13, 176(%r15) +; CHECK: ld %f14, 168(%r15) +; CHECK: ld %f15, 160(%r15) +; CHECK: aghi %r15, 224 +; CHECK: br %r14 + %l0 = load volatile float *%ptr + %l1 = load volatile float *%ptr + %l2 = load volatile float *%ptr + %l3 = load volatile float *%ptr + %l4 = load volatile float *%ptr + %l5 = load volatile float *%ptr + %l6 = load volatile float *%ptr + %l7 = load volatile float *%ptr + %l8 = load volatile float *%ptr + %l9 = load volatile float *%ptr + %l10 = load volatile float *%ptr + %l11 = load volatile float *%ptr + %l12 = load volatile float *%ptr + %l13 = load volatile float *%ptr + %l14 = load volatile float *%ptr + %l15 = load volatile float *%ptr + %add0 = fadd float %l0, %l0 + %add1 = fadd float %l1, %add0 + %add2 = fadd float %l2, %add1 + %add3 = fadd float %l3, %add2 + %add4 = fadd float %l4, %add3 + %add5 = fadd float %l5, %add4 + %add6 = fadd float %l6, %add5 + %add7 = fadd float %l7, %add6 + %add8 = fadd float %l8, %add7 + %add9 = fadd float %l9, %add8 + %add10 = fadd float %l10, %add9 + %add11 = fadd float %l11, %add10 + %add12 = fadd float %l12, %add11 + %add13 = fadd float %l13, %add12 + %add14 = fadd float %l14, %add13 + %add15 = fadd float %l15, %add14 + store volatile float %add0, float *%ptr + store volatile float %add1, float *%ptr + store volatile float %add2, float *%ptr + store volatile float %add3, float *%ptr + store volatile float %add4, float *%ptr + store volatile float %add5, float *%ptr + store volatile float %add6, float *%ptr + store volatile float %add7, float *%ptr + store volatile float %add8, float *%ptr + store volatile float %add9, float *%ptr + store volatile float %add10, float *%ptr + store volatile float %add11, float *%ptr + store volatile float %add12, float *%ptr + store volatile float %add13, float *%ptr + store volatile float %add14, float *%ptr + store volatile float %add15, float *%ptr + ret void +} + +; Like f1, but requires one fewer FPR. We allocate in numerical order, +; so %f15 is the one that gets dropped. +define void @f2(float *%ptr) { +; CHECK: f2: +; CHECK: aghi %r15, -216 +; CHECK: .cfi_def_cfa_offset 376 +; CHECK: std %f8, 208(%r15) +; CHECK: std %f9, 200(%r15) +; CHECK: std %f10, 192(%r15) +; CHECK: std %f11, 184(%r15) +; CHECK: std %f12, 176(%r15) +; CHECK: std %f13, 168(%r15) +; CHECK: std %f14, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 208(%r15) +; CHECK: ld %f9, 200(%r15) +; CHECK: ld %f10, 192(%r15) +; CHECK: ld %f11, 184(%r15) +; CHECK: ld %f12, 176(%r15) +; CHECK: ld %f13, 168(%r15) +; CHECK: ld %f14, 160(%r15) +; CHECK: aghi %r15, 216 +; CHECK: br %r14 + %l0 = load volatile float *%ptr + %l1 = load volatile float *%ptr + %l2 = load volatile float *%ptr + %l3 = load volatile float *%ptr + %l4 = load volatile float *%ptr + %l5 = load volatile float *%ptr + %l6 = load volatile float *%ptr + %l7 = load volatile float *%ptr + %l8 = load volatile float *%ptr + %l9 = load volatile float *%ptr + %l10 = load volatile float *%ptr + %l11 = load volatile float *%ptr + %l12 = load volatile float *%ptr + %l13 = load volatile float *%ptr + %l14 = load volatile float *%ptr + %add0 = fadd float %l0, %l0 + %add1 = fadd float %l1, %add0 + %add2 = fadd float %l2, %add1 + %add3 = fadd float %l3, %add2 + %add4 = fadd float %l4, %add3 + %add5 = fadd float %l5, %add4 + %add6 = fadd float %l6, %add5 + %add7 = fadd float %l7, %add6 + %add8 = fadd float %l8, %add7 + %add9 = fadd float %l9, %add8 + %add10 = fadd float %l10, %add9 + %add11 = fadd float %l11, %add10 + %add12 = fadd float %l12, %add11 + %add13 = fadd float %l13, %add12 + %add14 = fadd float %l14, %add13 + store volatile float %add0, float *%ptr + store volatile float %add1, float *%ptr + store volatile float %add2, float *%ptr + store volatile float %add3, float *%ptr + store volatile float %add4, float *%ptr + store volatile float %add5, float *%ptr + store volatile float %add6, float *%ptr + store volatile float %add7, float *%ptr + store volatile float %add8, float *%ptr + store volatile float %add9, float *%ptr + store volatile float %add10, float *%ptr + store volatile float %add11, float *%ptr + store volatile float %add12, float *%ptr + store volatile float %add13, float *%ptr + store volatile float %add14, float *%ptr + ret void +} + +; Like f1, but should require only one call-saved FPR. +define void @f3(float *%ptr) { +; CHECK: f3: +; CHECK: aghi %r15, -168 +; CHECK: .cfi_def_cfa_offset 328 +; CHECK: std %f8, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK-NOT: %f9 +; CHECK-NOT: %f10 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 160(%r15) +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %l0 = load volatile float *%ptr + %l1 = load volatile float *%ptr + %l2 = load volatile float *%ptr + %l3 = load volatile float *%ptr + %l4 = load volatile float *%ptr + %l5 = load volatile float *%ptr + %l6 = load volatile float *%ptr + %l7 = load volatile float *%ptr + %l8 = load volatile float *%ptr + %add0 = fadd float %l0, %l0 + %add1 = fadd float %l1, %add0 + %add2 = fadd float %l2, %add1 + %add3 = fadd float %l3, %add2 + %add4 = fadd float %l4, %add3 + %add5 = fadd float %l5, %add4 + %add6 = fadd float %l6, %add5 + %add7 = fadd float %l7, %add6 + %add8 = fadd float %l8, %add7 + store volatile float %add0, float *%ptr + store volatile float %add1, float *%ptr + store volatile float %add2, float *%ptr + store volatile float %add3, float *%ptr + store volatile float %add4, float *%ptr + store volatile float %add5, float *%ptr + store volatile float %add6, float *%ptr + store volatile float %add7, float *%ptr + store volatile float %add8, float *%ptr + ret void +} + +; This function should use all call-clobbered FPRs but no call-saved ones. +; It shouldn't need to create a frame. +define void @f4(float *%ptr) { +; CHECK: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: %f8 +; CHECK-NOT: %f9 +; CHECK-NOT: %f10 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; CHECK: br %r14 + %l0 = load volatile float *%ptr + %l1 = load volatile float *%ptr + %l2 = load volatile float *%ptr + %l3 = load volatile float *%ptr + %l4 = load volatile float *%ptr + %l5 = load volatile float *%ptr + %l6 = load volatile float *%ptr + %l7 = load volatile float *%ptr + %add0 = fadd float %l0, %l0 + %add1 = fadd float %l1, %add0 + %add2 = fadd float %l2, %add1 + %add3 = fadd float %l3, %add2 + %add4 = fadd float %l4, %add3 + %add5 = fadd float %l5, %add4 + %add6 = fadd float %l6, %add5 + %add7 = fadd float %l7, %add6 + store volatile float %add0, float *%ptr + store volatile float %add1, float *%ptr + store volatile float %add2, float *%ptr + store volatile float %add3, float *%ptr + store volatile float %add4, float *%ptr + store volatile float %add5, float *%ptr + store volatile float %add6, float *%ptr + store volatile float %add7, float *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-03.ll b/test/CodeGen/SystemZ/frame-03.ll new file mode 100644 index 000000000000..3c4a49977a12 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-03.ll @@ -0,0 +1,259 @@ +; Like frame-02.ll, but with doubles rather than floats. Internally this +; uses a different register class, but the set of saved and restored +; registers should be the same. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This function should require all FPRs, but no other spill slots. +; We need to save and restore 8 of the 16 FPRs, so the frame size +; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160 +; (the caller-allocated part of the frame) + 224. +define void @f1(double *%ptr) { +; CHECK: f1: +; CHECK: aghi %r15, -224 +; CHECK: .cfi_def_cfa_offset 384 +; CHECK: std %f8, 216(%r15) +; CHECK: std %f9, 208(%r15) +; CHECK: std %f10, 200(%r15) +; CHECK: std %f11, 192(%r15) +; CHECK: std %f12, 184(%r15) +; CHECK: std %f13, 176(%r15) +; CHECK: std %f14, 168(%r15) +; CHECK: std %f15, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK: .cfi_offset %f15, -224 +; ...main function body... +; CHECK: ld %f8, 216(%r15) +; CHECK: ld %f9, 208(%r15) +; CHECK: ld %f10, 200(%r15) +; CHECK: ld %f11, 192(%r15) +; CHECK: ld %f12, 184(%r15) +; CHECK: ld %f13, 176(%r15) +; CHECK: ld %f14, 168(%r15) +; CHECK: ld %f15, 160(%r15) +; CHECK: aghi %r15, 224 +; CHECK: br %r14 + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %l9 = load volatile double *%ptr + %l10 = load volatile double *%ptr + %l11 = load volatile double *%ptr + %l12 = load volatile double *%ptr + %l13 = load volatile double *%ptr + %l14 = load volatile double *%ptr + %l15 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + %add8 = fadd double %l8, %add7 + %add9 = fadd double %l9, %add8 + %add10 = fadd double %l10, %add9 + %add11 = fadd double %l11, %add10 + %add12 = fadd double %l12, %add11 + %add13 = fadd double %l13, %add12 + %add14 = fadd double %l14, %add13 + %add15 = fadd double %l15, %add14 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + store volatile double %add8, double *%ptr + store volatile double %add9, double *%ptr + store volatile double %add10, double *%ptr + store volatile double %add11, double *%ptr + store volatile double %add12, double *%ptr + store volatile double %add13, double *%ptr + store volatile double %add14, double *%ptr + store volatile double %add15, double *%ptr + ret void +} + +; Like f1, but requires one fewer FPR. We allocate in numerical order, +; so %f15 is the one that gets dropped. +define void @f2(double *%ptr) { +; CHECK: f2: +; CHECK: aghi %r15, -216 +; CHECK: .cfi_def_cfa_offset 376 +; CHECK: std %f8, 208(%r15) +; CHECK: std %f9, 200(%r15) +; CHECK: std %f10, 192(%r15) +; CHECK: std %f11, 184(%r15) +; CHECK: std %f12, 176(%r15) +; CHECK: std %f13, 168(%r15) +; CHECK: std %f14, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 208(%r15) +; CHECK: ld %f9, 200(%r15) +; CHECK: ld %f10, 192(%r15) +; CHECK: ld %f11, 184(%r15) +; CHECK: ld %f12, 176(%r15) +; CHECK: ld %f13, 168(%r15) +; CHECK: ld %f14, 160(%r15) +; CHECK: aghi %r15, 216 +; CHECK: br %r14 + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %l9 = load volatile double *%ptr + %l10 = load volatile double *%ptr + %l11 = load volatile double *%ptr + %l12 = load volatile double *%ptr + %l13 = load volatile double *%ptr + %l14 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + %add8 = fadd double %l8, %add7 + %add9 = fadd double %l9, %add8 + %add10 = fadd double %l10, %add9 + %add11 = fadd double %l11, %add10 + %add12 = fadd double %l12, %add11 + %add13 = fadd double %l13, %add12 + %add14 = fadd double %l14, %add13 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + store volatile double %add8, double *%ptr + store volatile double %add9, double *%ptr + store volatile double %add10, double *%ptr + store volatile double %add11, double *%ptr + store volatile double %add12, double *%ptr + store volatile double %add13, double *%ptr + store volatile double %add14, double *%ptr + ret void +} + +; Like f1, but should require only one call-saved FPR. +define void @f3(double *%ptr) { +; CHECK: f3: +; CHECK: aghi %r15, -168 +; CHECK: .cfi_def_cfa_offset 328 +; CHECK: std %f8, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK-NOT: %f9 +; CHECK-NOT: %f10 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 160(%r15) +; CHECK: aghi %r15, 168 +; CHECK: br %r14 + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + %add8 = fadd double %l8, %add7 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + store volatile double %add8, double *%ptr + ret void +} + +; This function should use all call-clobbered FPRs but no call-saved ones. +; It shouldn't need to create a frame. +define void @f4(double *%ptr) { +; CHECK: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: %f8 +; CHECK-NOT: %f9 +; CHECK-NOT: %f10 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; CHECK: br %r14 + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-04.ll b/test/CodeGen/SystemZ/frame-04.ll new file mode 100644 index 000000000000..360f85cde322 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-04.ll @@ -0,0 +1,187 @@ +; Like frame-02.ll, but with long doubles rather than floats. Some of the +; cases are slightly different because we need to allocate pairs of FPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This function should require all FPRs, but no other spill slots. +; We need to save and restore 8 of the 16 FPRs, so the frame size +; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160 +; (the caller-allocated part of the frame) + 224. +define void @f1(fp128 *%ptr) { +; CHECK: f1: +; CHECK: aghi %r15, -224 +; CHECK: .cfi_def_cfa_offset 384 +; CHECK: std %f8, 216(%r15) +; CHECK: std %f9, 208(%r15) +; CHECK: std %f10, 200(%r15) +; CHECK: std %f11, 192(%r15) +; CHECK: std %f12, 184(%r15) +; CHECK: std %f13, 176(%r15) +; CHECK: std %f14, 168(%r15) +; CHECK: std %f15, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f13, -208 +; CHECK: .cfi_offset %f14, -216 +; CHECK: .cfi_offset %f15, -224 +; ...main function body... +; CHECK: ld %f8, 216(%r15) +; CHECK: ld %f9, 208(%r15) +; CHECK: ld %f10, 200(%r15) +; CHECK: ld %f11, 192(%r15) +; CHECK: ld %f12, 184(%r15) +; CHECK: ld %f13, 176(%r15) +; CHECK: ld %f14, 168(%r15) +; CHECK: ld %f15, 160(%r15) +; CHECK: aghi %r15, 224 +; CHECK: br %r14 + %l0 = load volatile fp128 *%ptr + %l1 = load volatile fp128 *%ptr + %l4 = load volatile fp128 *%ptr + %l5 = load volatile fp128 *%ptr + %l8 = load volatile fp128 *%ptr + %l9 = load volatile fp128 *%ptr + %l12 = load volatile fp128 *%ptr + %l13 = load volatile fp128 *%ptr + %add0 = fadd fp128 %l0, %l0 + %add1 = fadd fp128 %l1, %add0 + %add4 = fadd fp128 %l4, %add1 + %add5 = fadd fp128 %l5, %add4 + %add8 = fadd fp128 %l8, %add5 + %add9 = fadd fp128 %l9, %add8 + %add12 = fadd fp128 %l12, %add9 + %add13 = fadd fp128 %l13, %add12 + store volatile fp128 %add0, fp128 *%ptr + store volatile fp128 %add1, fp128 *%ptr + store volatile fp128 %add4, fp128 *%ptr + store volatile fp128 %add5, fp128 *%ptr + store volatile fp128 %add8, fp128 *%ptr + store volatile fp128 %add9, fp128 *%ptr + store volatile fp128 %add12, fp128 *%ptr + store volatile fp128 %add13, fp128 *%ptr + ret void +} + +; Like f1, but requires one fewer FPR pair. We allocate in numerical order, +; so %f13+%f15 is the pair that gets dropped. +define void @f2(fp128 *%ptr) { +; CHECK: f2: +; CHECK: aghi %r15, -208 +; CHECK: .cfi_def_cfa_offset 368 +; CHECK: std %f8, 200(%r15) +; CHECK: std %f9, 192(%r15) +; CHECK: std %f10, 184(%r15) +; CHECK: std %f11, 176(%r15) +; CHECK: std %f12, 168(%r15) +; CHECK: std %f14, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f9, -176 +; CHECK: .cfi_offset %f10, -184 +; CHECK: .cfi_offset %f11, -192 +; CHECK: .cfi_offset %f12, -200 +; CHECK: .cfi_offset %f14, -208 +; CHECK-NOT: %f13 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 200(%r15) +; CHECK: ld %f9, 192(%r15) +; CHECK: ld %f10, 184(%r15) +; CHECK: ld %f11, 176(%r15) +; CHECK: ld %f12, 168(%r15) +; CHECK: ld %f14, 160(%r15) +; CHECK: aghi %r15, 208 +; CHECK: br %r14 + %l0 = load volatile fp128 *%ptr + %l1 = load volatile fp128 *%ptr + %l4 = load volatile fp128 *%ptr + %l5 = load volatile fp128 *%ptr + %l8 = load volatile fp128 *%ptr + %l9 = load volatile fp128 *%ptr + %l12 = load volatile fp128 *%ptr + %add0 = fadd fp128 %l0, %l0 + %add1 = fadd fp128 %l1, %add0 + %add4 = fadd fp128 %l4, %add1 + %add5 = fadd fp128 %l5, %add4 + %add8 = fadd fp128 %l8, %add5 + %add9 = fadd fp128 %l9, %add8 + %add12 = fadd fp128 %l12, %add9 + store volatile fp128 %add0, fp128 *%ptr + store volatile fp128 %add1, fp128 *%ptr + store volatile fp128 %add4, fp128 *%ptr + store volatile fp128 %add5, fp128 *%ptr + store volatile fp128 %add8, fp128 *%ptr + store volatile fp128 %add9, fp128 *%ptr + store volatile fp128 %add12, fp128 *%ptr + ret void +} + +; Like f1, but requires only one call-saved FPR pair. We allocate in +; numerical order so the pair should be %f8+%f10. +define void @f3(fp128 *%ptr) { +; CHECK: f3: +; CHECK: aghi %r15, -176 +; CHECK: .cfi_def_cfa_offset 336 +; CHECK: std %f8, 168(%r15) +; CHECK: std %f10, 160(%r15) +; CHECK: .cfi_offset %f8, -168 +; CHECK: .cfi_offset %f10, -176 +; CHECK-NOT: %f9 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; ...main function body... +; CHECK: ld %f8, 168(%r15) +; CHECK: ld %f10, 160(%r15) +; CHECK: aghi %r15, 176 +; CHECK: br %r14 + %l0 = load volatile fp128 *%ptr + %l1 = load volatile fp128 *%ptr + %l4 = load volatile fp128 *%ptr + %l5 = load volatile fp128 *%ptr + %l8 = load volatile fp128 *%ptr + %add0 = fadd fp128 %l0, %l0 + %add1 = fadd fp128 %l1, %add0 + %add4 = fadd fp128 %l4, %add1 + %add5 = fadd fp128 %l5, %add4 + %add8 = fadd fp128 %l8, %add5 + store volatile fp128 %add0, fp128 *%ptr + store volatile fp128 %add1, fp128 *%ptr + store volatile fp128 %add4, fp128 *%ptr + store volatile fp128 %add5, fp128 *%ptr + store volatile fp128 %add8, fp128 *%ptr + ret void +} + +; This function should use all call-clobbered FPRs but no call-saved ones. +; It shouldn't need to create a frame. +define void @f4(fp128 *%ptr) { +; CHECK: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: %f8 +; CHECK-NOT: %f9 +; CHECK-NOT: %f10 +; CHECK-NOT: %f11 +; CHECK-NOT: %f12 +; CHECK-NOT: %f13 +; CHECK-NOT: %f14 +; CHECK-NOT: %f15 +; CHECK: br %r14 + %l0 = load volatile fp128 *%ptr + %l1 = load volatile fp128 *%ptr + %l4 = load volatile fp128 *%ptr + %l5 = load volatile fp128 *%ptr + %add0 = fadd fp128 %l0, %l0 + %add1 = fadd fp128 %l1, %add0 + %add4 = fadd fp128 %l4, %add1 + %add5 = fadd fp128 %l5, %add4 + store volatile fp128 %add0, fp128 *%ptr + store volatile fp128 %add1, fp128 *%ptr + store volatile fp128 %add4, fp128 *%ptr + store volatile fp128 %add5, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-05.ll b/test/CodeGen/SystemZ/frame-05.ll new file mode 100644 index 000000000000..3a159fcd5941 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-05.ll @@ -0,0 +1,219 @@ +; Test saving and restoring of call-saved GPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This function should require all GPRs, but no other spill slots. The caller +; allocates room for the GPR save slots, so we shouldn't need to allocate any +; extra space. +; +; The function only modifies the low 32 bits of each register, which in +; itself would allow STM and LM to be used instead of STMG and LMG. +; However, the ABI defines the offset of each register, so we always +; use the 64-bit form. +; +; Use a different address for the final store, so that we can check that +; %r15 isn't referenced again until after that. +define void @f1(i32 *%ptr) { +; CHECK: f1: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r6, -112 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK: st {{.*}}, 4(%r2) +; CHECK: lmg %r6, %r15, 48(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l6 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l11 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add3 = add i32 %l3, %add1 + %add4 = add i32 %l4, %add3 + %add5 = add i32 %l5, %add4 + %add6 = add i32 %l6, %add5 + %add7 = add i32 %l7, %add6 + %add8 = add i32 %l8, %add7 + %add9 = add i32 %l9, %add8 + %add10 = add i32 %l10, %add9 + %add11 = add i32 %l11, %add10 + %add12 = add i32 %l12, %add11 + %add13 = add i32 %l13, %add12 + %add14 = add i32 %l14, %add13 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add3, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add6, i32 *%ptr + store volatile i32 %add7, i32 *%ptr + store volatile i32 %add8, i32 *%ptr + store volatile i32 %add9, i32 *%ptr + store volatile i32 %add10, i32 *%ptr + store volatile i32 %add11, i32 *%ptr + store volatile i32 %add12, i32 *%ptr + store volatile i32 %add13, i32 *%ptr + %final = getelementptr i32 *%ptr, i32 1 + store volatile i32 %add14, i32 *%final + ret void +} + +; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs +; from %r14 down, so that the STMG/LMG sequences aren't any longer than +; they need to be. +define void @f2(i32 *%ptr) { +; CHECK: f2: +; CHECK: stmg %r7, %r15, 56(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK: st {{.*}}, 4(%r2) +; CHECK: lmg %r7, %r15, 56(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l11 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add3 = add i32 %l3, %add1 + %add4 = add i32 %l4, %add3 + %add5 = add i32 %l5, %add4 + %add7 = add i32 %l7, %add5 + %add8 = add i32 %l8, %add7 + %add9 = add i32 %l9, %add8 + %add10 = add i32 %l10, %add9 + %add11 = add i32 %l11, %add10 + %add12 = add i32 %l12, %add11 + %add13 = add i32 %l13, %add12 + %add14 = add i32 %l14, %add13 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add3, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add7, i32 *%ptr + store volatile i32 %add8, i32 *%ptr + store volatile i32 %add9, i32 *%ptr + store volatile i32 %add10, i32 *%ptr + store volatile i32 %add11, i32 *%ptr + store volatile i32 %add12, i32 *%ptr + store volatile i32 %add13, i32 *%ptr + %final = getelementptr i32 *%ptr, i32 1 + store volatile i32 %add14, i32 *%final + ret void +} + +; Like f1, but only needs one call-saved GPR, which ought to be %r14. +define void @f3(i32 *%ptr) { +; CHECK: f3: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK-NOT: %r7 +; CHECK-NOT: %r8 +; CHECK-NOT: %r9 +; CHECK-NOT: %r10 +; CHECK-NOT: %r11 +; CHECK-NOT: %r12 +; CHECK-NOT: %r13 +; CHECK: st {{.*}}, 4(%r2) +; CHECK: lmg %r14, %r15, 112(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add3 = add i32 %l3, %add1 + %add4 = add i32 %l4, %add3 + %add5 = add i32 %l5, %add4 + %add14 = add i32 %l14, %add5 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add3, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + %final = getelementptr i32 *%ptr, i32 1 + store volatile i32 %add14, i32 *%final + ret void +} + +; This function should use all call-clobbered GPRs but no call-saved ones. +; It shouldn't need to touch the stack at all. +define void @f4(i32 *%ptr) { +; CHECK: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK-NOT: %r7 +; CHECK-NOT: %r8 +; CHECK-NOT: %r9 +; CHECK-NOT: %r10 +; CHECK-NOT: %r11 +; CHECK-NOT: %r12 +; CHECK-NOT: %r13 +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add3 = add i32 %l3, %add1 + %add4 = add i32 %l4, %add3 + %add5 = add i32 %l5, %add4 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add3, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + %final = getelementptr i32 *%ptr, i32 1 + store volatile i32 %add5, i32 *%final + ret void +} diff --git a/test/CodeGen/SystemZ/frame-06.ll b/test/CodeGen/SystemZ/frame-06.ll new file mode 100644 index 000000000000..4c361f1e9fc9 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-06.ll @@ -0,0 +1,216 @@ +; Like frame-05.ll, but with i64s rather than i32s. Internally this +; uses a different register class, but the set of saved and restored +; registers should be the same. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This function should require all GPRs, but no other spill slots. The caller +; allocates room for the GPR save slots, so we shouldn't need to allocate any +; extra space. +; +; Use a different address for the final store, so that we can check that +; %r15 isn't referenced again until after that. +define void @f1(i64 *%ptr) { +; CHECK: f1: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r6, -112 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK: stg {{.*}}, 8(%r2) +; CHECK: lmg %r6, %r15, 48(%r15) +; CHECK: br %r14 + %l0 = load volatile i64 *%ptr + %l1 = load volatile i64 *%ptr + %l3 = load volatile i64 *%ptr + %l4 = load volatile i64 *%ptr + %l5 = load volatile i64 *%ptr + %l6 = load volatile i64 *%ptr + %l7 = load volatile i64 *%ptr + %l8 = load volatile i64 *%ptr + %l9 = load volatile i64 *%ptr + %l10 = load volatile i64 *%ptr + %l11 = load volatile i64 *%ptr + %l12 = load volatile i64 *%ptr + %l13 = load volatile i64 *%ptr + %l14 = load volatile i64 *%ptr + %add0 = add i64 %l0, %l0 + %add1 = add i64 %l1, %add0 + %add3 = add i64 %l3, %add1 + %add4 = add i64 %l4, %add3 + %add5 = add i64 %l5, %add4 + %add6 = add i64 %l6, %add5 + %add7 = add i64 %l7, %add6 + %add8 = add i64 %l8, %add7 + %add9 = add i64 %l9, %add8 + %add10 = add i64 %l10, %add9 + %add11 = add i64 %l11, %add10 + %add12 = add i64 %l12, %add11 + %add13 = add i64 %l13, %add12 + %add14 = add i64 %l14, %add13 + store volatile i64 %add0, i64 *%ptr + store volatile i64 %add1, i64 *%ptr + store volatile i64 %add3, i64 *%ptr + store volatile i64 %add4, i64 *%ptr + store volatile i64 %add5, i64 *%ptr + store volatile i64 %add6, i64 *%ptr + store volatile i64 %add7, i64 *%ptr + store volatile i64 %add8, i64 *%ptr + store volatile i64 %add9, i64 *%ptr + store volatile i64 %add10, i64 *%ptr + store volatile i64 %add11, i64 *%ptr + store volatile i64 %add12, i64 *%ptr + store volatile i64 %add13, i64 *%ptr + %final = getelementptr i64 *%ptr, i64 1 + store volatile i64 %add14, i64 *%final + ret void +} + +; Like f1, but requires one fewer GPR. We allocate the call-saved GPRs +; from %r14 down, so that the STMG/LMG sequences aren't any longer than +; they need to be. +define void @f2(i64 *%ptr) { +; CHECK: f2: +; CHECK: stmg %r7, %r15, 56(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK: stg {{.*}}, 8(%r2) +; CHECK: lmg %r7, %r15, 56(%r15) +; CHECK: br %r14 + %l0 = load volatile i64 *%ptr + %l1 = load volatile i64 *%ptr + %l3 = load volatile i64 *%ptr + %l4 = load volatile i64 *%ptr + %l5 = load volatile i64 *%ptr + %l7 = load volatile i64 *%ptr + %l8 = load volatile i64 *%ptr + %l9 = load volatile i64 *%ptr + %l10 = load volatile i64 *%ptr + %l11 = load volatile i64 *%ptr + %l12 = load volatile i64 *%ptr + %l13 = load volatile i64 *%ptr + %l14 = load volatile i64 *%ptr + %add0 = add i64 %l0, %l0 + %add1 = add i64 %l1, %add0 + %add3 = add i64 %l3, %add1 + %add4 = add i64 %l4, %add3 + %add5 = add i64 %l5, %add4 + %add7 = add i64 %l7, %add5 + %add8 = add i64 %l8, %add7 + %add9 = add i64 %l9, %add8 + %add10 = add i64 %l10, %add9 + %add11 = add i64 %l11, %add10 + %add12 = add i64 %l12, %add11 + %add13 = add i64 %l13, %add12 + %add14 = add i64 %l14, %add13 + store volatile i64 %add0, i64 *%ptr + store volatile i64 %add1, i64 *%ptr + store volatile i64 %add3, i64 *%ptr + store volatile i64 %add4, i64 *%ptr + store volatile i64 %add5, i64 *%ptr + store volatile i64 %add7, i64 *%ptr + store volatile i64 %add8, i64 *%ptr + store volatile i64 %add9, i64 *%ptr + store volatile i64 %add10, i64 *%ptr + store volatile i64 %add11, i64 *%ptr + store volatile i64 %add12, i64 *%ptr + store volatile i64 %add13, i64 *%ptr + %final = getelementptr i64 *%ptr, i64 1 + store volatile i64 %add14, i64 *%final + ret void +} + +; Like f1, but only needs one call-saved GPR, which ought to be %r14. +define void @f3(i64 *%ptr) { +; CHECK: f3: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK-NOT: %r15 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK-NOT: %r7 +; CHECK-NOT: %r8 +; CHECK-NOT: %r9 +; CHECK-NOT: %r10 +; CHECK-NOT: %r11 +; CHECK-NOT: %r12 +; CHECK-NOT: %r13 +; CHECK: stg {{.*}}, 8(%r2) +; CHECK: lmg %r14, %r15, 112(%r15) +; CHECK: br %r14 + %l0 = load volatile i64 *%ptr + %l1 = load volatile i64 *%ptr + %l3 = load volatile i64 *%ptr + %l4 = load volatile i64 *%ptr + %l5 = load volatile i64 *%ptr + %l14 = load volatile i64 *%ptr + %add0 = add i64 %l0, %l0 + %add1 = add i64 %l1, %add0 + %add3 = add i64 %l3, %add1 + %add4 = add i64 %l4, %add3 + %add5 = add i64 %l5, %add4 + %add14 = add i64 %l14, %add5 + store volatile i64 %add0, i64 *%ptr + store volatile i64 %add1, i64 *%ptr + store volatile i64 %add3, i64 *%ptr + store volatile i64 %add4, i64 *%ptr + store volatile i64 %add5, i64 *%ptr + %final = getelementptr i64 *%ptr, i64 1 + store volatile i64 %add14, i64 *%final + ret void +} + +; This function should use all call-clobbered GPRs but no call-saved ones. +; It shouldn't need to touch the stack at all. +define void @f4(i64 *%ptr) { +; CHECK: f4: +; CHECK-NOT: %r15 +; CHECK-NOT: %r6 +; CHECK-NOT: %r7 +; CHECK-NOT: %r8 +; CHECK-NOT: %r9 +; CHECK-NOT: %r10 +; CHECK-NOT: %r11 +; CHECK-NOT: %r12 +; CHECK-NOT: %r13 +; CHECK: br %r14 + %l0 = load volatile i64 *%ptr + %l1 = load volatile i64 *%ptr + %l3 = load volatile i64 *%ptr + %l4 = load volatile i64 *%ptr + %l5 = load volatile i64 *%ptr + %add0 = add i64 %l0, %l0 + %add1 = add i64 %l1, %add0 + %add3 = add i64 %l3, %add1 + %add4 = add i64 %l4, %add3 + %add5 = add i64 %l5, %add4 + store volatile i64 %add0, i64 *%ptr + store volatile i64 %add1, i64 *%ptr + store volatile i64 %add3, i64 *%ptr + store volatile i64 %add4, i64 *%ptr + %final = getelementptr i64 *%ptr, i64 1 + store volatile i64 %add5, i64 *%final + ret void +} diff --git a/test/CodeGen/SystemZ/frame-07.ll b/test/CodeGen/SystemZ/frame-07.ll new file mode 100644 index 000000000000..cfe9f868c07b --- /dev/null +++ b/test/CodeGen/SystemZ/frame-07.ll @@ -0,0 +1,249 @@ +; Test the saving and restoring of FPRs in large frames. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +; Test a frame size that requires some FPRs to be saved and loaded using +; the 20-bit STDY and LDY while others can use the 12-bit STD and LD. +; The frame is big enough to require an emergency spill slot at 160(%r15), +; as well as the 8 FPR save slots. Get a frame of size 4128 by allocating +; (4128 - 168 - 8 * 8) / 8 = 487 extra doublewords. +define void @f1(double *%ptr, i64 %x) { +; CHECK-NOFP: f1: +; CHECK-NOFP: aghi %r15, -4128 +; CHECK-NOFP: .cfi_def_cfa_offset 4288 +; CHECK-NOFP: stdy %f8, 4120(%r15) +; CHECK-NOFP: stdy %f9, 4112(%r15) +; CHECK-NOFP: stdy %f10, 4104(%r15) +; CHECK-NOFP: stdy %f11, 4096(%r15) +; CHECK-NOFP: std %f12, 4088(%r15) +; CHECK-NOFP: std %f13, 4080(%r15) +; CHECK-NOFP: std %f14, 4072(%r15) +; CHECK-NOFP: std %f15, 4064(%r15) +; CHECK-NOFP: .cfi_offset %f8, -168 +; CHECK-NOFP: .cfi_offset %f9, -176 +; CHECK-NOFP: .cfi_offset %f10, -184 +; CHECK-NOFP: .cfi_offset %f11, -192 +; CHECK-NOFP: .cfi_offset %f12, -200 +; CHECK-NOFP: .cfi_offset %f13, -208 +; CHECK-NOFP: .cfi_offset %f14, -216 +; CHECK-NOFP: .cfi_offset %f15, -224 +; ...main function body... +; CHECK-NOFP: ldy %f8, 4120(%r15) +; CHECK-NOFP: ldy %f9, 4112(%r15) +; CHECK-NOFP: ldy %f10, 4104(%r15) +; CHECK-NOFP: ldy %f11, 4096(%r15) +; CHECK-NOFP: ld %f12, 4088(%r15) +; CHECK-NOFP: ld %f13, 4080(%r15) +; CHECK-NOFP: ld %f14, 4072(%r15) +; CHECK-NOFP: ld %f15, 4064(%r15) +; CHECK-NOFP: aghi %r15, 4128 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f1: +; CHECK-FP: stmg %r11, %r15, 88(%r15) +; CHECK-FP: aghi %r15, -4128 +; CHECK-FP: .cfi_def_cfa_offset 4288 +; CHECK-FP: lgr %r11, %r15 +; CHECK-FP: .cfi_def_cfa_register %r11 +; CHECK-FP: stdy %f8, 4120(%r11) +; CHECK-FP: stdy %f9, 4112(%r11) +; CHECK-FP: stdy %f10, 4104(%r11) +; CHECK-FP: stdy %f11, 4096(%r11) +; CHECK-FP: std %f12, 4088(%r11) +; CHECK-FP: std %f13, 4080(%r11) +; CHECK-FP: std %f14, 4072(%r11) +; CHECK-FP: std %f15, 4064(%r11) +; ...main function body... +; CHECK-FP: ldy %f8, 4120(%r11) +; CHECK-FP: ldy %f9, 4112(%r11) +; CHECK-FP: ldy %f10, 4104(%r11) +; CHECK-FP: ldy %f11, 4096(%r11) +; CHECK-FP: ld %f12, 4088(%r11) +; CHECK-FP: ld %f13, 4080(%r11) +; CHECK-FP: ld %f14, 4072(%r11) +; CHECK-FP: ld %f15, 4064(%r11) +; CHECK-FP: lmg %r11, %r15, 4216(%r11) +; CHECK-FP: br %r14 + %y = alloca [487 x i64], align 8 + %elem = getelementptr inbounds [487 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %elem + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %l9 = load volatile double *%ptr + %l10 = load volatile double *%ptr + %l11 = load volatile double *%ptr + %l12 = load volatile double *%ptr + %l13 = load volatile double *%ptr + %l14 = load volatile double *%ptr + %l15 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + %add8 = fadd double %l8, %add7 + %add9 = fadd double %l9, %add8 + %add10 = fadd double %l10, %add9 + %add11 = fadd double %l11, %add10 + %add12 = fadd double %l12, %add11 + %add13 = fadd double %l13, %add12 + %add14 = fadd double %l14, %add13 + %add15 = fadd double %l15, %add14 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + store volatile double %add8, double *%ptr + store volatile double %add9, double *%ptr + store volatile double %add10, double *%ptr + store volatile double %add11, double *%ptr + store volatile double %add12, double *%ptr + store volatile double %add13, double *%ptr + store volatile double %add14, double *%ptr + store volatile double %add15, double *%ptr + ret void +} + +; Test a frame size that requires some FPRs to be saved and loaded using +; an indexed STD and LD while others can use the 20-bit STDY and LDY. +; The index can be any call-clobbered GPR except %r0. +; +; Don't require the accesses to share the same LLILH; that would be a +; good optimisation but is really a different test. +; +; As above, get a frame of size 524320 by allocating +; (524320 - 168 - 8 * 8) / 8 = 65511 extra doublewords. +define void @f2(double *%ptr, i64 %x) { +; CHECK-NOFP: f2: +; CHECK-NOFP: agfi %r15, -524320 +; CHECK-NOFP: .cfi_def_cfa_offset 524480 +; CHECK-NOFP: llilh [[INDEX:%r[1-5]]], 8 +; CHECK-NOFP: std %f8, 24([[INDEX]],%r15) +; CHECK-NOFP: std %f9, 16({{%r[1-5]}},%r15) +; CHECK-NOFP: std %f10, 8({{%r[1-5]}},%r15) +; CHECK-NOFP: std %f11, 0({{%r[1-5]}},%r15) +; CHECK-NOFP: stdy %f12, 524280(%r15) +; CHECK-NOFP: stdy %f13, 524272(%r15) +; CHECK-NOFP: stdy %f14, 524264(%r15) +; CHECK-NOFP: stdy %f15, 524256(%r15) +; CHECK-NOFP: .cfi_offset %f8, -168 +; CHECK-NOFP: .cfi_offset %f9, -176 +; CHECK-NOFP: .cfi_offset %f10, -184 +; CHECK-NOFP: .cfi_offset %f11, -192 +; CHECK-NOFP: .cfi_offset %f12, -200 +; CHECK-NOFP: .cfi_offset %f13, -208 +; CHECK-NOFP: .cfi_offset %f14, -216 +; CHECK-NOFP: .cfi_offset %f15, -224 +; ...main function body... +; CHECK-NOFP: ld %f8, 24({{%r[1-5]}},%r15) +; CHECK-NOFP: ld %f9, 16({{%r[1-5]}},%r15) +; CHECK-NOFP: ld %f10, 8({{%r[1-5]}},%r15) +; CHECK-NOFP: ld %f11, 0({{%r[1-5]}},%r15) +; CHECK-NOFP: ldy %f12, 524280(%r15) +; CHECK-NOFP: ldy %f13, 524272(%r15) +; CHECK-NOFP: ldy %f14, 524264(%r15) +; CHECK-NOFP: ldy %f15, 524256(%r15) +; CHECK-NOFP: agfi %r15, 524320 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f2: +; CHECK-FP: stmg %r11, %r15, 88(%r15) +; CHECK-FP: agfi %r15, -524320 +; CHECK-FP: .cfi_def_cfa_offset 524480 +; CHECK-FP: llilh [[INDEX:%r[1-5]]], 8 +; CHECK-FP: std %f8, 24([[INDEX]],%r11) +; CHECK-FP: std %f9, 16({{%r[1-5]}},%r11) +; CHECK-FP: std %f10, 8({{%r[1-5]}},%r11) +; CHECK-FP: std %f11, 0({{%r[1-5]}},%r11) +; CHECK-FP: stdy %f12, 524280(%r11) +; CHECK-FP: stdy %f13, 524272(%r11) +; CHECK-FP: stdy %f14, 524264(%r11) +; CHECK-FP: stdy %f15, 524256(%r11) +; CHECK-FP: .cfi_offset %f8, -168 +; CHECK-FP: .cfi_offset %f9, -176 +; CHECK-FP: .cfi_offset %f10, -184 +; CHECK-FP: .cfi_offset %f11, -192 +; CHECK-FP: .cfi_offset %f12, -200 +; CHECK-FP: .cfi_offset %f13, -208 +; CHECK-FP: .cfi_offset %f14, -216 +; CHECK-FP: .cfi_offset %f15, -224 +; ...main function body... +; CHECK-FP: ld %f8, 24({{%r[1-5]}},%r11) +; CHECK-FP: ld %f9, 16({{%r[1-5]}},%r11) +; CHECK-FP: ld %f10, 8({{%r[1-5]}},%r11) +; CHECK-FP: ld %f11, 0({{%r[1-5]}},%r11) +; CHECK-FP: ldy %f12, 524280(%r11) +; CHECK-FP: ldy %f13, 524272(%r11) +; CHECK-FP: ldy %f14, 524264(%r11) +; CHECK-FP: ldy %f15, 524256(%r11) +; CHECK-FP: aghi %r11, 128 +; CHECK-FP: lmg %r11, %r15, 524280(%r11) +; CHECK-FP: br %r14 + %y = alloca [65511 x i64], align 8 + %elem = getelementptr inbounds [65511 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %elem + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %l9 = load volatile double *%ptr + %l10 = load volatile double *%ptr + %l11 = load volatile double *%ptr + %l12 = load volatile double *%ptr + %l13 = load volatile double *%ptr + %l14 = load volatile double *%ptr + %l15 = load volatile double *%ptr + %add0 = fadd double %l0, %l0 + %add1 = fadd double %l1, %add0 + %add2 = fadd double %l2, %add1 + %add3 = fadd double %l3, %add2 + %add4 = fadd double %l4, %add3 + %add5 = fadd double %l5, %add4 + %add6 = fadd double %l6, %add5 + %add7 = fadd double %l7, %add6 + %add8 = fadd double %l8, %add7 + %add9 = fadd double %l9, %add8 + %add10 = fadd double %l10, %add9 + %add11 = fadd double %l11, %add10 + %add12 = fadd double %l12, %add11 + %add13 = fadd double %l13, %add12 + %add14 = fadd double %l14, %add13 + %add15 = fadd double %l15, %add14 + store volatile double %add0, double *%ptr + store volatile double %add1, double *%ptr + store volatile double %add2, double *%ptr + store volatile double %add3, double *%ptr + store volatile double %add4, double *%ptr + store volatile double %add5, double *%ptr + store volatile double %add6, double *%ptr + store volatile double %add7, double *%ptr + store volatile double %add8, double *%ptr + store volatile double %add9, double *%ptr + store volatile double %add10, double *%ptr + store volatile double %add11, double *%ptr + store volatile double %add12, double *%ptr + store volatile double %add13, double *%ptr + store volatile double %add14, double *%ptr + store volatile double %add15, double *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-08.ll b/test/CodeGen/SystemZ/frame-08.ll new file mode 100644 index 000000000000..6cf6378268f4 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-08.ll @@ -0,0 +1,277 @@ +; Test the saving and restoring of GPRs in large frames. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; This is the largest frame size that can use a plain LMG for %r6 and above. +; It is big enough to require an emergency spill slot at 160(%r15), +; so get a frame of size 524232 by allocating (524232 - 168) / 8 = 65508 +; extra doublewords. +define void @f1(i32 *%ptr, i64 %x) { +; CHECK: f1: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK: .cfi_offset %r6, -112 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524232 +; CHECK: .cfi_def_cfa_offset 524392 +; ...main function body... +; CHECK-NOT: ag +; CHECK: lmg %r6, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l6 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l11 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add6 = add i32 %l6, %add5 + %add7 = add i32 %l7, %add6 + %add8 = add i32 %l8, %add7 + %add9 = add i32 %l9, %add8 + %add10 = add i32 %l10, %add9 + %add11 = add i32 %l11, %add10 + %add12 = add i32 %l12, %add11 + %add13 = add i32 %l13, %add12 + %add14 = add i32 %l14, %add13 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add6, i32 *%ptr + store volatile i32 %add7, i32 *%ptr + store volatile i32 %add8, i32 *%ptr + store volatile i32 %add9, i32 *%ptr + store volatile i32 %add10, i32 *%ptr + store volatile i32 %add11, i32 *%ptr + store volatile i32 %add12, i32 *%ptr + store volatile i32 %add13, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [65508 x i64], align 8 + %entry = getelementptr inbounds [65508 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} + +; This is the largest frame size that can use a plain LMG for %r14 and above +; It is big enough to require an emergency spill slot at 160(%r15), +; so get a frame of size 524168 by allocating (524168 - 168) / 8 = 65500 +; extra doublewords. +define void @f2(i32 *%ptr, i64 %x) { +; CHECK: f2: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524168 +; CHECK: .cfi_def_cfa_offset 524328 +; ...main function body... +; CHECK-NOT: ag +; CHECK: lmg %r14, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add14 = add i32 %l14, %add5 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [65500 x i64], align 8 + %entry = getelementptr inbounds [65500 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} + +; Like f1 but with a frame that is 8 bytes bigger. This is the smallest +; frame size that needs two instructions to perform the final LMG for +; %r6 and above. +define void @f3(i32 *%ptr, i64 %x) { +; CHECK: f3: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK: .cfi_offset %r6, -112 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524240 +; CHECK: .cfi_def_cfa_offset 524400 +; ...main function body... +; CHECK: aghi %r15, 8 +; CHECK: lmg %r6, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l6 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l11 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add6 = add i32 %l6, %add5 + %add7 = add i32 %l7, %add6 + %add8 = add i32 %l8, %add7 + %add9 = add i32 %l9, %add8 + %add10 = add i32 %l10, %add9 + %add11 = add i32 %l11, %add10 + %add12 = add i32 %l12, %add11 + %add13 = add i32 %l13, %add12 + %add14 = add i32 %l14, %add13 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add6, i32 *%ptr + store volatile i32 %add7, i32 *%ptr + store volatile i32 %add8, i32 *%ptr + store volatile i32 %add9, i32 *%ptr + store volatile i32 %add10, i32 *%ptr + store volatile i32 %add11, i32 *%ptr + store volatile i32 %add12, i32 *%ptr + store volatile i32 %add13, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [65509 x i64], align 8 + %entry = getelementptr inbounds [65509 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} + +; Like f2 but with a frame that is 8 bytes bigger. This is the smallest +; frame size that needs two instructions to perform the final LMG for +; %r14 and %r15. +define void @f4(i32 *%ptr, i64 %x) { +; CHECK: f4: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524176 +; CHECK: .cfi_def_cfa_offset 524336 +; ...main function body... +; CHECK: aghi %r15, 8 +; CHECK: lmg %r14, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add14 = add i32 %l14, %add5 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [65501 x i64], align 8 + %entry = getelementptr inbounds [65501 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} + +; This is the largest frame size for which the prepatory increment for +; "lmg %r14, %r15, ..." can be done using AGHI. +define void @f5(i32 *%ptr, i64 %x) { +; CHECK: f5: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -556928 +; CHECK: .cfi_def_cfa_offset 557088 +; ...main function body... +; CHECK: aghi %r15, 32760 +; CHECK: lmg %r14, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add14 = add i32 %l14, %add5 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [69595 x i64], align 8 + %entry = getelementptr inbounds [69595 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} + +; This is the smallest frame size for which the prepatory increment for +; "lmg %r14, %r15, ..." needs to be done using AGFI. +define void @f6(i32 *%ptr, i64 %x) { +; CHECK: f6: +; CHECK: stmg %r14, %r15, 112(%r15) +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -556936 +; CHECK: .cfi_def_cfa_offset 557096 +; ...main function body... +; CHECK: agfi %r15, 32768 +; CHECK: lmg %r14, %r15, 524280(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add4 = add i32 %l4, %add1 + %add5 = add i32 %l5, %add4 + %add14 = add i32 %l14, %add5 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add14, i32 *%ptr + %y = alloca [69596 x i64], align 8 + %entry = getelementptr inbounds [69596 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %entry + ret void +} diff --git a/test/CodeGen/SystemZ/frame-09.ll b/test/CodeGen/SystemZ/frame-09.ll new file mode 100644 index 000000000000..eac633623c5f --- /dev/null +++ b/test/CodeGen/SystemZ/frame-09.ll @@ -0,0 +1,153 @@ +; Test the handling of the frame pointer (%r11). +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck %s + +; We should always initialise %r11 when FP elimination is disabled. +; We don't need to allocate any more than the caller-provided 160-byte +; area though. +define i32 @f1(i32 %x) { +; CHECK: f1: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r15, -40 +; CHECK-NOT: ag +; CHECK: lgr %r11, %r15 +; CHECK: .cfi_def_cfa_register %r11 +; CHECK: lmg %r11, %r15, 88(%r11) +; CHECK: br %r14 + %y = add i32 %x, 1 + ret i32 %y +} + +; Make sure that frame accesses after the initial allocation are relative +; to %r11 rather than %r15. +define void @f2(i64 %x) { +; CHECK: f2: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r15, -40 +; CHECK: aghi %r15, -168 +; CHECK: .cfi_def_cfa_offset 328 +; CHECK: lgr %r11, %r15 +; CHECK: .cfi_def_cfa_register %r11 +; CHECK: stg %r2, 160(%r11) +; CHECK: lmg %r11, %r15, 256(%r11) +; CHECK: br %r14 + %y = alloca i64, align 8 + store volatile i64 %x, i64* %y + ret void +} + +; This function should require all GPRs but no other spill slots. +; It shouldn't need to allocate its own frame. +define void @f3(i32 *%ptr) { +; CHECK: f3: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK-NOT: %r15 +; CHECK-NOT: %r11 +; CHECK: .cfi_offset %r6, -112 +; CHECK: .cfi_offset %r7, -104 +; CHECK: .cfi_offset %r8, -96 +; CHECK: .cfi_offset %r9, -88 +; CHECK: .cfi_offset %r10, -80 +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r12, -64 +; CHECK: .cfi_offset %r13, -56 +; CHECK: .cfi_offset %r14, -48 +; CHECK: .cfi_offset %r15, -40 +; CHECK-NOT: ag +; CHECK: lgr %r11, %r15 +; CHECK: .cfi_def_cfa_register %r11 +; ...main function body... +; CHECK-NOT: %r15 +; CHECK-NOT: %r11 +; CHECK: st {{.*}}, 4(%r2) +; CHECK: lmg %r6, %r15, 48(%r11) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l6 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %add0 = add i32 %l0, %l0 + %add1 = add i32 %l1, %add0 + %add3 = add i32 %l3, %add1 + %add4 = add i32 %l4, %add3 + %add5 = add i32 %l5, %add4 + %add6 = add i32 %l6, %add5 + %add7 = add i32 %l7, %add6 + %add8 = add i32 %l8, %add7 + %add9 = add i32 %l9, %add8 + %add10 = add i32 %l10, %add9 + %add12 = add i32 %l12, %add10 + %add13 = add i32 %l13, %add12 + %add14 = add i32 %l14, %add13 + store volatile i32 %add0, i32 *%ptr + store volatile i32 %add1, i32 *%ptr + store volatile i32 %add3, i32 *%ptr + store volatile i32 %add4, i32 *%ptr + store volatile i32 %add5, i32 *%ptr + store volatile i32 %add6, i32 *%ptr + store volatile i32 %add7, i32 *%ptr + store volatile i32 %add8, i32 *%ptr + store volatile i32 %add9, i32 *%ptr + store volatile i32 %add10, i32 *%ptr + store volatile i32 %add12, i32 *%ptr + store volatile i32 %add13, i32 *%ptr + %final = getelementptr i32 *%ptr, i32 1 + store volatile i32 %add14, i32 *%final + ret void +} + +; The largest frame for which the LMG is in range. This frame has an +; emergency spill slot at 160(%r11), so create a frame of size 524192 +; by allocating (524192 - 168) / 8 = 65503 doublewords. +define void @f4(i64 %x) { +; CHECK: f4: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524192 +; CHECK: .cfi_def_cfa_offset 524352 +; CHECK: lgr %r11, %r15 +; CHECK: .cfi_def_cfa_register %r11 +; CHECK: stg %r2, 168(%r11) +; CHECK-NOT: ag +; CHECK: lmg %r11, %r15, 524280(%r11) +; CHECK: br %r14 + %y = alloca [65503 x i64], align 8 + %ptr = getelementptr inbounds [65503 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; The next frame size larger than f4. +define void @f5(i64 %x) { +; CHECK: f5: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: .cfi_offset %r11, -72 +; CHECK: .cfi_offset %r15, -40 +; CHECK: agfi %r15, -524200 +; CHECK: .cfi_def_cfa_offset 524360 +; CHECK: lgr %r11, %r15 +; CHECK: .cfi_def_cfa_register %r11 +; CHECK: stg %r2, 168(%r11) +; CHECK: aghi %r11, 8 +; CHECK: lmg %r11, %r15, 524280(%r11) +; CHECK: br %r14 + %y = alloca [65504 x i64], align 8 + %ptr = getelementptr inbounds [65504 x i64]* %y, i64 0, i64 0 + store volatile i64 %x, i64* %ptr + ret void +} + +; The tests above establish that %r11 is handled like %r15 for LMG. +; Rely on the %r15-based tests in frame-08.ll for other cases. diff --git a/test/CodeGen/SystemZ/frame-10.ll b/test/CodeGen/SystemZ/frame-10.ll new file mode 100644 index 000000000000..399a4125933d --- /dev/null +++ b/test/CodeGen/SystemZ/frame-10.ll @@ -0,0 +1,14 @@ +; Test the stacksave builtin. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare i8 *@llvm.stacksave() + +define void @f1(i8 **%dest) { +; CHECK: f1: +; CHECK: stg %r15, 0(%r2) +; CHECK: br %r14 + %addr = call i8 *@llvm.stacksave() + store volatile i8 *%addr, i8 **%dest + ret void +} diff --git a/test/CodeGen/SystemZ/frame-11.ll b/test/CodeGen/SystemZ/frame-11.ll new file mode 100644 index 000000000000..84222056e6d0 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-11.ll @@ -0,0 +1,18 @@ +; Test the stackrestore builtin. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +declare void @llvm.stackrestore(i8 *) + +; we should use a frame pointer and tear down the frame based on %r11 +; rather than %r15. +define void @f1(i8 *%src) { +; CHECK: f1: +; CHECK: stmg %r11, %r15, 88(%r15) +; CHECK: lgr %r11, %r15 +; CHECK: lgr %r15, %r2 +; CHECK: lmg %r11, %r15, 88(%r11) +; CHECK: br %r14 + call void @llvm.stackrestore(i8 *%src) + ret void +} diff --git a/test/CodeGen/SystemZ/frame-13.ll b/test/CodeGen/SystemZ/frame-13.ll new file mode 100644 index 000000000000..fa6b845ea6f2 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-13.ll @@ -0,0 +1,299 @@ +; Test the handling of base + 12-bit displacement addresses for large frames, +; in cases where no 20-bit form exists. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +; This file tests what happens when a displacement is converted from +; being relative to the start of a frame object to being relative to +; the frame itself. In some cases the test is only possible if two +; objects are allocated. +; +; Rather than rely on a particular order for those objects, the tests +; instead allocate two objects of the same size and apply the test to +; both of them. For consistency, all tests follow this model, even if +; one object would actually be enough. + +; First check the highest in-range offset after conversion, which is 4092 +; for word-addressing instructions like MVHI. +; +; The last in-range doubleword offset is 4088. Since the frame has an +; emergency spill slot at 160(%r15), the amount that we need to allocate +; in order to put another object at offset 4088 is (4088 - 168) / 4 = 980 +; words. +define void @f1() { +; CHECK-NOFP: f1: +; CHECK-NOFP: mvhi 4092(%r15), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f1: +; CHECK-FP: mvhi 4092(%r11), 42 +; CHECK-FP: br %r14 + %region1 = alloca [980 x i32], align 8 + %region2 = alloca [980 x i32], align 8 + %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 1 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Test the first out-of-range offset. We cannot use an index register here. +define void @f2() { +; CHECK-NOFP: f2: +; CHECK-NOFP: lay %r1, 4096(%r15) +; CHECK-NOFP: mvhi 0(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f2: +; CHECK-FP: lay %r1, 4096(%r11) +; CHECK-FP: mvhi 0(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [980 x i32], align 8 + %region2 = alloca [980 x i32], align 8 + %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Test the next offset after that. +define void @f3() { +; CHECK-NOFP: f3: +; CHECK-NOFP: lay %r1, 4096(%r15) +; CHECK-NOFP: mvhi 4(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f3: +; CHECK-FP: lay %r1, 4096(%r11) +; CHECK-FP: mvhi 4(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [980 x i32], align 8 + %region2 = alloca [980 x i32], align 8 + %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 3 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Add 4096 bytes (1024 words) to the size of each object and repeat. +define void @f4() { +; CHECK-NOFP: f4: +; CHECK-NOFP: lay %r1, 4096(%r15) +; CHECK-NOFP: mvhi 4092(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f4: +; CHECK-FP: lay %r1, 4096(%r11) +; CHECK-FP: mvhi 4092(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2004 x i32], align 8 + %region2 = alloca [2004 x i32], align 8 + %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 1 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; ...as above. +define void @f5() { +; CHECK-NOFP: f5: +; CHECK-NOFP: lay %r1, 8192(%r15) +; CHECK-NOFP: mvhi 0(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f5: +; CHECK-FP: lay %r1, 8192(%r11) +; CHECK-FP: mvhi 0(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2004 x i32], align 8 + %region2 = alloca [2004 x i32], align 8 + %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 2 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; ...as above. +define void @f6() { +; CHECK-NOFP: f6: +; CHECK-NOFP: lay %r1, 8192(%r15) +; CHECK-NOFP: mvhi 4(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f6: +; CHECK-FP: lay %r1, 8192(%r11) +; CHECK-FP: mvhi 4(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2004 x i32], align 8 + %region2 = alloca [2004 x i32], align 8 + %ptr1 = getelementptr inbounds [2004 x i32]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [2004 x i32]* %region2, i64 0, i64 3 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Now try an offset of 4092 from the start of the object, with the object +; being at offset 8192. This time we need objects of (8192 - 168) / 4 = 2006 +; words. +define void @f7() { +; CHECK-NOFP: f7: +; CHECK-NOFP: lay %r1, 8192(%r15) +; CHECK-NOFP: mvhi 4092(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f7: +; CHECK-FP: lay %r1, 8192(%r11) +; CHECK-FP: mvhi 4092(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2006 x i32], align 8 + %region2 = alloca [2006 x i32], align 8 + %ptr1 = getelementptr inbounds [2006 x i32]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2006 x i32]* %region2, i64 0, i64 1023 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Keep the object-relative offset the same but bump the size of the +; objects by one doubleword. +define void @f8() { +; CHECK-NOFP: f8: +; CHECK-NOFP: lay %r1, 12288(%r15) +; CHECK-NOFP: mvhi 4(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f8: +; CHECK-FP: lay %r1, 12288(%r11) +; CHECK-FP: mvhi 4(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2008 x i32], align 8 + %region2 = alloca [2008 x i32], align 8 + %ptr1 = getelementptr inbounds [2008 x i32]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2008 x i32]* %region2, i64 0, i64 1023 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Check a case where the original displacement is out of range. The backend +; should force an LAY from the outset. We don't yet do any kind of anchor +; optimization, so there should be no offset on the MVHI itself. +define void @f9() { +; CHECK-NOFP: f9: +; CHECK-NOFP: lay %r1, 12296(%r15) +; CHECK-NOFP: mvhi 0(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f9: +; CHECK-FP: lay %r1, 12296(%r11) +; CHECK-FP: mvhi 0(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [2008 x i32], align 8 + %region2 = alloca [2008 x i32], align 8 + %ptr1 = getelementptr inbounds [2008 x i32]* %region1, i64 0, i64 1024 + %ptr2 = getelementptr inbounds [2008 x i32]* %region2, i64 0, i64 1024 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + ret void +} + +; Repeat f2 in a case that needs the emergency spill slot (because all +; call-clobbered registers are live and no call-saved ones have been +; allocated). +define void @f10(i32 *%vptr) { +; CHECK-NOFP: f10: +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: lay [[REGISTER]], 4096(%r15) +; CHECK-NOFP: mvhi 0([[REGISTER]]), 42 +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f10: +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: lay [[REGISTER]], 4096(%r11) +; CHECK-FP: mvhi 0([[REGISTER]]), 42 +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i3 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %region1 = alloca [980 x i32], align 8 + %region2 = alloca [980 x i32], align 8 + %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i3, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + ret void +} + +; And again with maximum register pressure. The only spill slot that the +; NOFP case needs is the emergency one, so the offsets are the same as for f2. +; However, the FP case uses %r11 as the frame pointer and must therefore +; spill a second register. This leads to an extra displacement of 8. +define void @f11(i32 *%vptr) { +; CHECK-NOFP: f11: +; CHECK-NOFP: stmg %r6, %r15, +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: lay [[REGISTER]], 4096(%r15) +; CHECK-NOFP: mvhi 0([[REGISTER]]), 42 +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: lmg %r6, %r15, +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f11: +; CHECK-FP: stmg %r6, %r15, +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: lay [[REGISTER]], 4096(%r11) +; CHECK-FP: mvhi 8([[REGISTER]]), 42 +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: lmg %r6, %r15, +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i3 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %i6 = load volatile i32 *%vptr + %i7 = load volatile i32 *%vptr + %i8 = load volatile i32 *%vptr + %i9 = load volatile i32 *%vptr + %i10 = load volatile i32 *%vptr + %i11 = load volatile i32 *%vptr + %i12 = load volatile i32 *%vptr + %i13 = load volatile i32 *%vptr + %i14 = load volatile i32 *%vptr + %region1 = alloca [980 x i32], align 8 + %region2 = alloca [980 x i32], align 8 + %ptr1 = getelementptr inbounds [980 x i32]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [980 x i32]* %region2, i64 0, i64 2 + store volatile i32 42, i32 *%ptr1 + store volatile i32 42, i32 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i3, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + store volatile i32 %i6, i32 *%vptr + store volatile i32 %i7, i32 *%vptr + store volatile i32 %i8, i32 *%vptr + store volatile i32 %i9, i32 *%vptr + store volatile i32 %i10, i32 *%vptr + store volatile i32 %i11, i32 *%vptr + store volatile i32 %i12, i32 *%vptr + store volatile i32 %i13, i32 *%vptr + store volatile i32 %i14, i32 *%vptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-14.ll b/test/CodeGen/SystemZ/frame-14.ll new file mode 100644 index 000000000000..d8ff0a54a761 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-14.ll @@ -0,0 +1,322 @@ +; Test the handling of base + displacement addresses for large frames, +; in cases where both 12-bit and 20-bit displacements are allowed. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +; This file tests what happens when a displacement is converted from +; being relative to the start of a frame object to being relative to +; the frame itself. In some cases the test is only possible if two +; objects are allocated. +; +; Rather than rely on a particular order for those objects, the tests +; instead allocate two objects of the same size and apply the test to +; both of them. For consistency, all tests follow this model, even if +; one object would actually be enough. + +; First check the highest offset that is in range of the 12-bit form. +; +; The last in-range doubleword offset is 4088. Since the frame has an +; emergency spill slot at 160(%r15), the amount that we need to allocate +; in order to put another object at offset 4088 is 4088 - 168 = 3920 bytes. +define void @f1() { +; CHECK-NOFP: f1: +; CHECK-NOFP: mvi 4095(%r15), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f1: +; CHECK-FP: mvi 4095(%r11), 42 +; CHECK-FP: br %r14 + %region1 = alloca [3920 x i8], align 8 + %region2 = alloca [3920 x i8], align 8 + %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 7 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Test the first offset that is out-of-range of the 12-bit form. +define void @f2() { +; CHECK-NOFP: f2: +; CHECK-NOFP: mviy 4096(%r15), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f2: +; CHECK-FP: mviy 4096(%r11), 42 +; CHECK-FP: br %r14 + %region1 = alloca [3920 x i8], align 8 + %region2 = alloca [3920 x i8], align 8 + %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 8 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Test the last offset that is in range of the 20-bit form. +; +; The last in-range doubleword offset is 524280, so by the same reasoning +; as above, we need to allocate objects of 524280 - 168 = 524122 bytes. +define void @f3() { +; CHECK-NOFP: f3: +; CHECK-NOFP: mviy 524287(%r15), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f3: +; CHECK-FP: mviy 524287(%r11), 42 +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 7 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Test the first out-of-range offset. We can't use an index register here, +; and the offset is also out of LAY's range, so expect a constant load +; followed by an addition. +define void @f4() { +; CHECK-NOFP: f4: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: mvi 0(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f4: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: mvi 0(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Add 4095 to the previous offset, to test the other end of the MVI range. +; The instruction will actually be STCY before frame lowering. +define void @f5() { +; CHECK-NOFP: f5: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: mvi 4095(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f5: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: mvi 4095(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4103 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4103 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Test the next offset after that, which uses MVIY instead of MVI. +define void @f6() { +; CHECK-NOFP: f6: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: mviy 4096(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f6: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: mviy 4096(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4104 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4104 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Now try an offset of 524287 from the start of the object, with the +; object being at offset 1048576 (1 << 20). The backend prefers to create +; anchors 0x10000 bytes apart, so that the high part can be loaded using +; LLILH while still using MVI in more cases than 0x40000 anchors would. +define void @f7() { +; CHECK-NOFP: f7: +; CHECK-NOFP: llilh %r1, 23 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: mviy 65535(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f7: +; CHECK-FP: llilh %r1, 23 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: mviy 65535(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [1048408 x i8], align 8 + %region2 = alloca [1048408 x i8], align 8 + %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Keep the object-relative offset the same but bump the size of the +; objects by one doubleword. +define void @f8() { +; CHECK-NOFP: f8: +; CHECK-NOFP: llilh %r1, 24 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: mvi 7(%r1), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f8: +; CHECK-FP: llilh %r1, 24 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: mvi 7(%r1), 42 +; CHECK-FP: br %r14 + %region1 = alloca [1048416 x i8], align 8 + %region2 = alloca [1048416 x i8], align 8 + %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524287 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Check a case where the original displacement is out of range. The backend +; should force separate address logic from the outset. We don't yet do any +; kind of anchor optimization, so there should be no offset on the MVI itself. +; +; Before frame lowering this is an LA followed by the AGFI seen below. +; The LA then gets lowered into the LLILH/LA form. The exact sequence +; isn't that important though. +define void @f9() { +; CHECK-NOFP: f9: +; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16 +; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15) +; CHECK-NOFP: agfi [[R2]], 524288 +; CHECK-NOFP: mvi 0([[R2]]), 42 +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f9: +; CHECK-FP: llilh [[R1:%r[1-5]]], 16 +; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11) +; CHECK-FP: agfi [[R2]], 524288 +; CHECK-FP: mvi 0([[R2]]), 42 +; CHECK-FP: br %r14 + %region1 = alloca [1048416 x i8], align 8 + %region2 = alloca [1048416 x i8], align 8 + %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524288 + %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524288 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + ret void +} + +; Repeat f4 in a case that needs the emergency spill slot (because all +; call-clobbered registers are live and no call-saved ones have been +; allocated). +define void @f10(i32 *%vptr) { +; CHECK-NOFP: f10: +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: llilh [[REGISTER]], 8 +; CHECK-NOFP: agr [[REGISTER]], %r15 +; CHECK-NOFP: mvi 0([[REGISTER]]), 42 +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f10: +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: llilh [[REGISTER]], 8 +; CHECK-FP: agr [[REGISTER]], %r11 +; CHECK-FP: mvi 0([[REGISTER]]), 42 +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i3 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i3, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + ret void +} + +; And again with maximum register pressure. The only spill slot that the +; NOFP case needs is the emergency one, so the offsets are the same as for f4. +; However, the FP case uses %r11 as the frame pointer and must therefore +; spill a second register. This leads to an extra displacement of 8. +define void @f11(i32 *%vptr) { +; CHECK-NOFP: f11: +; CHECK-NOFP: stmg %r6, %r15, +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: llilh [[REGISTER]], 8 +; CHECK-NOFP: agr [[REGISTER]], %r15 +; CHECK-NOFP: mvi 0([[REGISTER]]), 42 +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: lmg %r6, %r15, +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f11: +; CHECK-FP: stmg %r6, %r15, +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: llilh [[REGISTER]], 8 +; CHECK-FP: agr [[REGISTER]], %r11 +; CHECK-FP: mvi 8([[REGISTER]]), 42 +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: lmg %r6, %r15, +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i3 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %i6 = load volatile i32 *%vptr + %i7 = load volatile i32 *%vptr + %i8 = load volatile i32 *%vptr + %i9 = load volatile i32 *%vptr + %i10 = load volatile i32 *%vptr + %i11 = load volatile i32 *%vptr + %i12 = load volatile i32 *%vptr + %i13 = load volatile i32 *%vptr + %i14 = load volatile i32 *%vptr + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 42, i8 *%ptr1 + store volatile i8 42, i8 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i3, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + store volatile i32 %i6, i32 *%vptr + store volatile i32 %i7, i32 *%vptr + store volatile i32 %i8, i32 *%vptr + store volatile i32 %i9, i32 *%vptr + store volatile i32 %i10, i32 *%vptr + store volatile i32 %i11, i32 *%vptr + store volatile i32 %i12, i32 *%vptr + store volatile i32 %i13, i32 *%vptr + store volatile i32 %i14, i32 *%vptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-15.ll b/test/CodeGen/SystemZ/frame-15.ll new file mode 100644 index 000000000000..bc87e174d0b6 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-15.ll @@ -0,0 +1,352 @@ +; Test the handling of base + index + 12-bit displacement addresses for +; large frames, in cases where no 20-bit form exists. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +declare void @foo(float *%ptr1, float *%ptr2) + +; This file tests what happens when a displacement is converted from +; being relative to the start of a frame object to being relative to +; the frame itself. In some cases the test is only possible if two +; objects are allocated. +; +; Rather than rely on a particular order for those objects, the tests +; instead allocate two objects of the same size and apply the test to +; both of them. For consistency, all tests follow this model, even if +; one object would actually be enough. + +; First check the highest in-range offset after conversion, which is 4092 +; for word-addressing instructions like LDEB. +; +; The last in-range doubleword offset is 4088. Since the frame has an +; emergency spill slot at 160(%r15), the amount that we need to allocate +; in order to put another object at offset 4088 is (4088 - 168) / 4 = 980 +; words. +define void @f1(double *%dst) { +; CHECK-NOFP: f1: +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f1: +; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11) +; CHECK-FP: br %r14 + %region1 = alloca [980 x float], align 8 + %region2 = alloca [980 x float], align 8 + %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 1 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Test the first out-of-range offset. +define void @f2(double *%dst) { +; CHECK-NOFP: f2: +; CHECK-NOFP: lghi %r1, 4096 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f2: +; CHECK-FP: lghi %r1, 4096 +; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [980 x float], align 8 + %region2 = alloca [980 x float], align 8 + %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Test the next offset after that. +define void @f3(double *%dst) { +; CHECK-NOFP: f3: +; CHECK-NOFP: lghi %r1, 4096 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f3: +; CHECK-FP: lghi %r1, 4096 +; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [980 x float], align 8 + %region2 = alloca [980 x float], align 8 + %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 3 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Add 4096 bytes (1024 words) to the size of each object and repeat. +define void @f4(double *%dst) { +; CHECK-NOFP: f4: +; CHECK-NOFP: lghi %r1, 4096 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f4: +; CHECK-FP: lghi %r1, 4096 +; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [2004 x float], align 8 + %region2 = alloca [2004 x float], align 8 + %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 1 + %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 1 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; ...as above. +define void @f5(double *%dst) { +; CHECK-NOFP: f5: +; CHECK-NOFP: lghi %r1, 8192 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f5: +; CHECK-FP: lghi %r1, 8192 +; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [2004 x float], align 8 + %region2 = alloca [2004 x float], align 8 + %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 2 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; ...as above. +define void @f6(double *%dst) { +; CHECK-NOFP: f6: +; CHECK-NOFP: lghi %r1, 8192 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f6: +; CHECK-FP: lghi %r1, 8192 +; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [2004 x float], align 8 + %region2 = alloca [2004 x float], align 8 + %start1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2004 x float]* %region1, i64 0, i64 3 + %ptr2 = getelementptr inbounds [2004 x float]* %region2, i64 0, i64 3 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Now try an offset of 4092 from the start of the object, with the object +; being at offset 8192. This time we need objects of (8192 - 168) / 4 = 2006 +; words. +define void @f7(double *%dst) { +; CHECK-NOFP: f7: +; CHECK-NOFP: lghi %r1, 8192 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f7: +; CHECK-FP: lghi %r1, 8192 +; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [2006 x float], align 8 + %region2 = alloca [2006 x float], align 8 + %start1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2006 x float]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2006 x float]* %region2, i64 0, i64 1023 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Keep the object-relative offset the same but bump the size of the +; objects by one doubleword. +define void @f8(double *%dst) { +; CHECK-NOFP: f8: +; CHECK-NOFP: lghi %r1, 12288 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f8: +; CHECK-FP: lghi %r1, 12288 +; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [2008 x float], align 8 + %region2 = alloca [2008 x float], align 8 + %start1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 1023 + %ptr2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 1023 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Check a case where the original displacement is out of range. The backend +; should force an LAY from the outset. We don't yet do any kind of anchor +; optimization, so there should be no offset on the LDEB itself. +define void @f9(double *%dst) { +; CHECK-NOFP: f9: +; CHECK-NOFP: lay %r1, 12296(%r15) +; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f9: +; CHECK-FP: lay %r1, 12296(%r11) +; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1) +; CHECK-FP: br %r14 + %region1 = alloca [2008 x float], align 8 + %region2 = alloca [2008 x float], align 8 + %start1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [2008 x float]* %region1, i64 0, i64 1024 + %ptr2 = getelementptr inbounds [2008 x float]* %region2, i64 0, i64 1024 + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} + +; Repeat f2 in a case that needs the emergency spill slot, because all +; call-clobbered and allocated call-saved registers are live. Note that +; %vptr and %dst are copied to call-saved registers, freeing up %r2 and +; %r3 during the main test. +define void @f10(i32 *%vptr, double *%dst) { +; CHECK-NOFP: f10: +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: lghi [[REGISTER]], 4096 +; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15) +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f10: +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: lghi [[REGISTER]], 4096 +; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11) +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: br %r14 + %region1 = alloca [980 x float], align 8 + %region2 = alloca [980 x float], align 8 + %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %ptr1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2 + %ptr2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i2 = load volatile i32 *%vptr + %i3 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %i14 = load volatile i32 *%vptr + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i2, i32 *%vptr + store volatile i32 %i3, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + store volatile i32 %i14, i32 *%vptr + ret void +} + +; Repeat f2 in a case where the index register is already occupied. +define void @f11(double *%dst, i64 %index) { +; CHECK-NOFP: f11: +; CHECK-NOFP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3 +; CHECK-NOFP: lay %r1, 4096(%r15) +; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f11: +; CHECK-FP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3 +; CHECK-FP: lay %r1, 4096(%r11) +; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1) +; CHECK-FP: br %r14 + %region1 = alloca [980 x float], align 8 + %region2 = alloca [980 x float], align 8 + %start1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 0 + %start2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 0 + call void @foo(float *%start1, float *%start2) + %elem1 = getelementptr inbounds [980 x float]* %region1, i64 0, i64 2 + %elem2 = getelementptr inbounds [980 x float]* %region2, i64 0, i64 2 + %base1 = ptrtoint float *%elem1 to i64 + %base2 = ptrtoint float *%elem2 to i64 + %addr1 = add i64 %base1, %index + %addr2 = add i64 %base2, %index + %ptr1 = inttoptr i64 %addr1 to float * + %ptr2 = inttoptr i64 %addr2 to float * + %float1 = load float *%ptr1 + %float2 = load float *%ptr2 + %double1 = fpext float %float1 to double + %double2 = fpext float %float2 to double + store volatile double %double1, double *%dst + store volatile double %double2, double *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/frame-16.ll b/test/CodeGen/SystemZ/frame-16.ll new file mode 100644 index 000000000000..cc5529f920ca --- /dev/null +++ b/test/CodeGen/SystemZ/frame-16.ll @@ -0,0 +1,327 @@ +; Test the handling of base + index + displacement addresses for large frames, +; in cases where both 12-bit and 20-bit displacements are allowed. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-NOFP %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -disable-fp-elim | FileCheck -check-prefix=CHECK-FP %s + +; This file tests what happens when a displacement is converted from +; being relative to the start of a frame object to being relative to +; the frame itself. In some cases the test is only possible if two +; objects are allocated. +; +; Rather than rely on a particular order for those objects, the tests +; instead allocate two objects of the same size and apply the test to +; both of them. For consistency, all tests follow this model, even if +; one object would actually be enough. + +; First check the highest offset that is in range of the 12-bit form. +; +; The last in-range doubleword offset is 4088. Since the frame has an +; emergency spill slot at 160(%r15), the amount that we need to allocate +; in order to put another object at offset 4088 is 4088 - 168 = 3920 bytes. +define void @f1(i8 %byte) { +; CHECK-NOFP: f1: +; CHECK-NOFP: stc %r2, 4095(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f1: +; CHECK-FP: stc %r2, 4095(%r11) +; CHECK-FP: br %r14 + %region1 = alloca [3920 x i8], align 8 + %region2 = alloca [3920 x i8], align 8 + %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 7 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Test the first offset that is out-of-range of the 12-bit form. +define void @f2(i8 %byte) { +; CHECK-NOFP: f2: +; CHECK-NOFP: stcy %r2, 4096(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f2: +; CHECK-FP: stcy %r2, 4096(%r11) +; CHECK-FP: br %r14 + %region1 = alloca [3920 x i8], align 8 + %region2 = alloca [3920 x i8], align 8 + %ptr1 = getelementptr inbounds [3920 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [3920 x i8]* %region2, i64 0, i64 8 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Test the last offset that is in range of the 20-bit form. +; +; The last in-range doubleword offset is 524280, so by the same reasoning +; as above, we need to allocate objects of 524280 - 168 = 524122 bytes. +define void @f3(i8 %byte) { +; CHECK-NOFP: f3: +; CHECK-NOFP: stcy %r2, 524287(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f3: +; CHECK-FP: stcy %r2, 524287(%r11) +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 7 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 7 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Test the first out-of-range offset. We can't use an index register here, +; and the offset is also out of LAY's range, so expect a constant load +; followed by an addition. +define void @f4(i8 %byte) { +; CHECK-NOFP: f4: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: stc %r2, 0(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f4: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: stc %r2, 0(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Add 4095 to the previous offset, to test the other end of the STC range. +; The instruction will actually be STCY before frame lowering. +define void @f5(i8 %byte) { +; CHECK-NOFP: f5: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: stc %r2, 4095(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f5: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: stc %r2, 4095(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4103 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4103 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Test the next offset after that, which uses STCY instead of STC. +define void @f6(i8 %byte) { +; CHECK-NOFP: f6: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: stcy %r2, 4096(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f6: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: stcy %r2, 4096(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 4104 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 4104 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Now try an offset of 524287 from the start of the object, with the +; object being at offset 1048576 (1 << 20). The backend prefers to create +; anchors 0x10000 bytes apart, so that the high part can be loaded using +; LLILH while still using STC in more cases than 0x40000 anchors would. +define void @f7(i8 %byte) { +; CHECK-NOFP: f7: +; CHECK-NOFP: llilh %r1, 23 +; CHECK-NOFP: stcy %r2, 65535(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f7: +; CHECK-FP: llilh %r1, 23 +; CHECK-FP: stcy %r2, 65535(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [1048408 x i8], align 8 + %region2 = alloca [1048408 x i8], align 8 + %ptr1 = getelementptr inbounds [1048408 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048408 x i8]* %region2, i64 0, i64 524287 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Keep the object-relative offset the same but bump the size of the +; objects by one doubleword. +define void @f8(i8 %byte) { +; CHECK-NOFP: f8: +; CHECK-NOFP: llilh %r1, 24 +; CHECK-NOFP: stc %r2, 7(%r1,%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f8: +; CHECK-FP: llilh %r1, 24 +; CHECK-FP: stc %r2, 7(%r1,%r11) +; CHECK-FP: br %r14 + %region1 = alloca [1048416 x i8], align 8 + %region2 = alloca [1048416 x i8], align 8 + %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524287 + %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524287 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Check a case where the original displacement is out of range. The backend +; should force separate address logic from the outset. We don't yet do any +; kind of anchor optimization, so there should be no offset on the STC itself. +; +; Before frame lowering this is an LA followed by the AGFI seen below. +; The LA then gets lowered into the LLILH/LA form. The exact sequence +; isn't that important though. +define void @f9(i8 %byte) { +; CHECK-NOFP: f9: +; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16 +; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15) +; CHECK-NOFP: agfi [[R2]], 524288 +; CHECK-NOFP: stc %r2, 0([[R2]]) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f9: +; CHECK-FP: llilh [[R1:%r[1-5]]], 16 +; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11) +; CHECK-FP: agfi [[R2]], 524288 +; CHECK-FP: stc %r2, 0([[R2]]) +; CHECK-FP: br %r14 + %region1 = alloca [1048416 x i8], align 8 + %region2 = alloca [1048416 x i8], align 8 + %ptr1 = getelementptr inbounds [1048416 x i8]* %region1, i64 0, i64 524288 + %ptr2 = getelementptr inbounds [1048416 x i8]* %region2, i64 0, i64 524288 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} + +; Repeat f4 in a case that needs the emergency spill slot (because all +; call-clobbered registers are live and no call-saved ones have been +; allocated). +define void @f10(i32 *%vptr, i8 %byte) { +; CHECK-NOFP: f10: +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: llilh [[REGISTER]], 8 +; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15) +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f10: +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: llilh [[REGISTER]], 8 +; CHECK-FP: stc %r3, 0([[REGISTER]],%r11) +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + ret void +} + +; And again with maximum register pressure. The only spill slot that the +; NOFP case needs is the emergency one, so the offsets are the same as for f4. +; However, the FP case uses %r11 as the frame pointer and must therefore +; spill a second register. This leads to an extra displacement of 8. +define void @f11(i32 *%vptr, i8 %byte) { +; CHECK-NOFP: f11: +; CHECK-NOFP: stmg %r6, %r15, +; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r15) +; CHECK-NOFP: llilh [[REGISTER]], 8 +; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15) +; CHECK-NOFP: lg [[REGISTER]], 160(%r15) +; CHECK-NOFP: lmg %r6, %r15, +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f11: +; CHECK-FP: stmg %r6, %r15, +; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], 160(%r11) +; CHECK-FP: llilh [[REGISTER]], 8 +; CHECK-FP: stc %r3, 8([[REGISTER]],%r11) +; CHECK-FP: lg [[REGISTER]], 160(%r11) +; CHECK-FP: lmg %r6, %r15, +; CHECK-FP: br %r14 + %i0 = load volatile i32 *%vptr + %i1 = load volatile i32 *%vptr + %i4 = load volatile i32 *%vptr + %i5 = load volatile i32 *%vptr + %i6 = load volatile i32 *%vptr + %i7 = load volatile i32 *%vptr + %i8 = load volatile i32 *%vptr + %i9 = load volatile i32 *%vptr + %i10 = load volatile i32 *%vptr + %i11 = load volatile i32 *%vptr + %i12 = load volatile i32 *%vptr + %i13 = load volatile i32 *%vptr + %i14 = load volatile i32 *%vptr + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 8 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 8 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + store volatile i32 %i0, i32 *%vptr + store volatile i32 %i1, i32 *%vptr + store volatile i32 %i4, i32 *%vptr + store volatile i32 %i5, i32 *%vptr + store volatile i32 %i6, i32 *%vptr + store volatile i32 %i7, i32 *%vptr + store volatile i32 %i8, i32 *%vptr + store volatile i32 %i9, i32 *%vptr + store volatile i32 %i10, i32 *%vptr + store volatile i32 %i11, i32 *%vptr + store volatile i32 %i12, i32 *%vptr + store volatile i32 %i13, i32 *%vptr + store volatile i32 %i14, i32 *%vptr + ret void +} + +; Repeat f4 in a case where the index register is already occupied. +define void @f12(i8 %byte, i64 %index) { +; CHECK-NOFP: f12: +; CHECK-NOFP: llilh %r1, 8 +; CHECK-NOFP: agr %r1, %r15 +; CHECK-NOFP: stc %r2, 0(%r3,%r1) +; CHECK-NOFP: br %r14 +; +; CHECK-FP: f12: +; CHECK-FP: llilh %r1, 8 +; CHECK-FP: agr %r1, %r11 +; CHECK-FP: stc %r2, 0(%r3,%r1) +; CHECK-FP: br %r14 + %region1 = alloca [524112 x i8], align 8 + %region2 = alloca [524112 x i8], align 8 + %index1 = add i64 %index, 8 + %ptr1 = getelementptr inbounds [524112 x i8]* %region1, i64 0, i64 %index1 + %ptr2 = getelementptr inbounds [524112 x i8]* %region2, i64 0, i64 %index1 + store volatile i8 %byte, i8 *%ptr1 + store volatile i8 %byte, i8 *%ptr2 + ret void +} diff --git a/test/CodeGen/SystemZ/frame-17.ll b/test/CodeGen/SystemZ/frame-17.ll new file mode 100644 index 000000000000..613d9f879558 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-17.ll @@ -0,0 +1,177 @@ +; Test spilling of FPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; We need to save and restore 8 of the 16 FPRs and allocate an additional +; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly +; 160 + 8 * 8 = 232. +define void @f1(float *%ptr) { +; CHECK: f1: +; CHECK: aghi %r15, -232 +; CHECK: std %f8, 224(%r15) +; CHECK: std %f9, 216(%r15) +; CHECK: std %f10, 208(%r15) +; CHECK: std %f11, 200(%r15) +; CHECK: std %f12, 192(%r15) +; CHECK: std %f13, 184(%r15) +; CHECK: std %f14, 176(%r15) +; CHECK: std %f15, 168(%r15) +; CHECK-NOT: 160(%r15) +; CHECK: ste [[REGISTER:%f[0-9]+]], 164(%r15) +; CHECK-NOT: 160(%r15) +; CHECK: le [[REGISTER]], 164(%r15) +; CHECK-NOT: 160(%r15) +; CHECK: ld %f8, 224(%r15) +; CHECK: ld %f9, 216(%r15) +; CHECK: ld %f10, 208(%r15) +; CHECK: ld %f11, 200(%r15) +; CHECK: ld %f12, 192(%r15) +; CHECK: ld %f13, 184(%r15) +; CHECK: ld %f14, 176(%r15) +; CHECK: ld %f15, 168(%r15) +; CHECK: aghi %r15, 232 +; CHECK: br %r14 + %l0 = load volatile float *%ptr + %l1 = load volatile float *%ptr + %l2 = load volatile float *%ptr + %l3 = load volatile float *%ptr + %l4 = load volatile float *%ptr + %l5 = load volatile float *%ptr + %l6 = load volatile float *%ptr + %l7 = load volatile float *%ptr + %l8 = load volatile float *%ptr + %l9 = load volatile float *%ptr + %l10 = load volatile float *%ptr + %l11 = load volatile float *%ptr + %l12 = load volatile float *%ptr + %l13 = load volatile float *%ptr + %l14 = load volatile float *%ptr + %l15 = load volatile float *%ptr + %lx = load volatile float *%ptr + store volatile float %lx, float *%ptr + store volatile float %l15, float *%ptr + store volatile float %l14, float *%ptr + store volatile float %l13, float *%ptr + store volatile float %l12, float *%ptr + store volatile float %l11, float *%ptr + store volatile float %l10, float *%ptr + store volatile float %l9, float *%ptr + store volatile float %l8, float *%ptr + store volatile float %l7, float *%ptr + store volatile float %l6, float *%ptr + store volatile float %l5, float *%ptr + store volatile float %l4, float *%ptr + store volatile float %l3, float *%ptr + store volatile float %l2, float *%ptr + store volatile float %l1, float *%ptr + store volatile float %l0, float *%ptr + ret void +} + +; Same for doubles, except that the full spill slot is used. +define void @f2(double *%ptr) { +; CHECK: f2: +; CHECK: aghi %r15, -232 +; CHECK: std %f8, 224(%r15) +; CHECK: std %f9, 216(%r15) +; CHECK: std %f10, 208(%r15) +; CHECK: std %f11, 200(%r15) +; CHECK: std %f12, 192(%r15) +; CHECK: std %f13, 184(%r15) +; CHECK: std %f14, 176(%r15) +; CHECK: std %f15, 168(%r15) +; CHECK: std [[REGISTER:%f[0-9]+]], 160(%r15) +; CHECK: ld [[REGISTER]], 160(%r15) +; CHECK: ld %f8, 224(%r15) +; CHECK: ld %f9, 216(%r15) +; CHECK: ld %f10, 208(%r15) +; CHECK: ld %f11, 200(%r15) +; CHECK: ld %f12, 192(%r15) +; CHECK: ld %f13, 184(%r15) +; CHECK: ld %f14, 176(%r15) +; CHECK: ld %f15, 168(%r15) +; CHECK: aghi %r15, 232 +; CHECK: br %r14 + %l0 = load volatile double *%ptr + %l1 = load volatile double *%ptr + %l2 = load volatile double *%ptr + %l3 = load volatile double *%ptr + %l4 = load volatile double *%ptr + %l5 = load volatile double *%ptr + %l6 = load volatile double *%ptr + %l7 = load volatile double *%ptr + %l8 = load volatile double *%ptr + %l9 = load volatile double *%ptr + %l10 = load volatile double *%ptr + %l11 = load volatile double *%ptr + %l12 = load volatile double *%ptr + %l13 = load volatile double *%ptr + %l14 = load volatile double *%ptr + %l15 = load volatile double *%ptr + %lx = load volatile double *%ptr + store volatile double %lx, double *%ptr + store volatile double %l15, double *%ptr + store volatile double %l14, double *%ptr + store volatile double %l13, double *%ptr + store volatile double %l12, double *%ptr + store volatile double %l11, double *%ptr + store volatile double %l10, double *%ptr + store volatile double %l9, double *%ptr + store volatile double %l8, double *%ptr + store volatile double %l7, double *%ptr + store volatile double %l6, double *%ptr + store volatile double %l5, double *%ptr + store volatile double %l4, double *%ptr + store volatile double %l3, double *%ptr + store volatile double %l2, double *%ptr + store volatile double %l1, double *%ptr + store volatile double %l0, double *%ptr + ret void +} + +; The long double case needs a 16-byte spill slot. +define void @f3(fp128 *%ptr) { +; CHECK: f3: +; CHECK: aghi %r15, -240 +; CHECK: std %f8, 232(%r15) +; CHECK: std %f9, 224(%r15) +; CHECK: std %f10, 216(%r15) +; CHECK: std %f11, 208(%r15) +; CHECK: std %f12, 200(%r15) +; CHECK: std %f13, 192(%r15) +; CHECK: std %f14, 184(%r15) +; CHECK: std %f15, 176(%r15) +; CHECK: std [[REGISTER1:%f[0-9]+]], 160(%r15) +; CHECK: std [[REGISTER2:%f[0-9]+]], 168(%r15) +; CHECK: ld [[REGISTER1]], 160(%r15) +; CHECK: ld [[REGISTER2]], 168(%r15) +; CHECK: ld %f8, 232(%r15) +; CHECK: ld %f9, 224(%r15) +; CHECK: ld %f10, 216(%r15) +; CHECK: ld %f11, 208(%r15) +; CHECK: ld %f12, 200(%r15) +; CHECK: ld %f13, 192(%r15) +; CHECK: ld %f14, 184(%r15) +; CHECK: ld %f15, 176(%r15) +; CHECK: aghi %r15, 240 +; CHECK: br %r14 + %l0 = load volatile fp128 *%ptr + %l1 = load volatile fp128 *%ptr + %l4 = load volatile fp128 *%ptr + %l5 = load volatile fp128 *%ptr + %l8 = load volatile fp128 *%ptr + %l9 = load volatile fp128 *%ptr + %l12 = load volatile fp128 *%ptr + %l13 = load volatile fp128 *%ptr + %lx = load volatile fp128 *%ptr + store volatile fp128 %lx, fp128 *%ptr + store volatile fp128 %l13, fp128 *%ptr + store volatile fp128 %l12, fp128 *%ptr + store volatile fp128 %l9, fp128 *%ptr + store volatile fp128 %l8, fp128 *%ptr + store volatile fp128 %l5, fp128 *%ptr + store volatile fp128 %l4, fp128 *%ptr + store volatile fp128 %l1, fp128 *%ptr + store volatile fp128 %l0, fp128 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/frame-18.ll b/test/CodeGen/SystemZ/frame-18.ll new file mode 100644 index 000000000000..a9977ed04b42 --- /dev/null +++ b/test/CodeGen/SystemZ/frame-18.ll @@ -0,0 +1,91 @@ +; Test spilling of GPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame +; size should be exactly 160 + 8 = 168. +define void @f1(i32 *%ptr) { +; CHECK: f1: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK: aghi %r15, -168 +; CHECK-NOT: 160(%r15) +; CHECK: st [[REGISTER:%r[0-9]+]], 164(%r15) +; CHECK-NOT: 160(%r15) +; CHECK: l [[REGISTER]], 164(%r15) +; CHECK-NOT: 160(%r15) +; CHECK: lmg %r6, %r15, 216(%r15) +; CHECK: br %r14 + %l0 = load volatile i32 *%ptr + %l1 = load volatile i32 *%ptr + %l3 = load volatile i32 *%ptr + %l4 = load volatile i32 *%ptr + %l5 = load volatile i32 *%ptr + %l6 = load volatile i32 *%ptr + %l7 = load volatile i32 *%ptr + %l8 = load volatile i32 *%ptr + %l9 = load volatile i32 *%ptr + %l10 = load volatile i32 *%ptr + %l11 = load volatile i32 *%ptr + %l12 = load volatile i32 *%ptr + %l13 = load volatile i32 *%ptr + %l14 = load volatile i32 *%ptr + %lx = load volatile i32 *%ptr + store volatile i32 %lx, i32 *%ptr + store volatile i32 %l14, i32 *%ptr + store volatile i32 %l13, i32 *%ptr + store volatile i32 %l12, i32 *%ptr + store volatile i32 %l11, i32 *%ptr + store volatile i32 %l10, i32 *%ptr + store volatile i32 %l9, i32 *%ptr + store volatile i32 %l8, i32 *%ptr + store volatile i32 %l7, i32 *%ptr + store volatile i32 %l6, i32 *%ptr + store volatile i32 %l5, i32 *%ptr + store volatile i32 %l4, i32 *%ptr + store volatile i32 %l3, i32 *%ptr + store volatile i32 %l1, i32 *%ptr + store volatile i32 %l0, i32 *%ptr + ret void +} + +; Same for i64, except that the full spill slot is used. +define void @f2(i64 *%ptr) { +; CHECK: f2: +; CHECK: stmg %r6, %r15, 48(%r15) +; CHECK: aghi %r15, -168 +; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15) +; CHECK: lg [[REGISTER]], 160(%r15) +; CHECK: lmg %r6, %r15, 216(%r15) +; CHECK: br %r14 + %l0 = load volatile i64 *%ptr + %l1 = load volatile i64 *%ptr + %l3 = load volatile i64 *%ptr + %l4 = load volatile i64 *%ptr + %l5 = load volatile i64 *%ptr + %l6 = load volatile i64 *%ptr + %l7 = load volatile i64 *%ptr + %l8 = load volatile i64 *%ptr + %l9 = load volatile i64 *%ptr + %l10 = load volatile i64 *%ptr + %l11 = load volatile i64 *%ptr + %l12 = load volatile i64 *%ptr + %l13 = load volatile i64 *%ptr + %l14 = load volatile i64 *%ptr + %lx = load volatile i64 *%ptr + store volatile i64 %lx, i64 *%ptr + store volatile i64 %l14, i64 *%ptr + store volatile i64 %l13, i64 *%ptr + store volatile i64 %l12, i64 *%ptr + store volatile i64 %l11, i64 *%ptr + store volatile i64 %l10, i64 *%ptr + store volatile i64 %l9, i64 *%ptr + store volatile i64 %l8, i64 *%ptr + store volatile i64 %l7, i64 *%ptr + store volatile i64 %l6, i64 *%ptr + store volatile i64 %l5, i64 *%ptr + store volatile i64 %l4, i64 *%ptr + store volatile i64 %l3, i64 *%ptr + store volatile i64 %l1, i64 *%ptr + store volatile i64 %l0, i64 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/insert-01.ll b/test/CodeGen/SystemZ/insert-01.ll new file mode 100644 index 000000000000..98ddf56959bf --- /dev/null +++ b/test/CodeGen/SystemZ/insert-01.ll @@ -0,0 +1,230 @@ +; Test insertions of memory into the low byte of an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check a plain insertion with (or (and ... -0xff) (zext (load ....))). +; The whole sequence can be performed by IC. +define i32 @f1(i32 %orig, i8 *%ptr) { +; CHECK: f1: +; CHECK-NOT: ni +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = and i32 %orig, -256 + %or = or i32 %ptr1, %ptr2 + ret i32 %or +} + +; Like f1, but with the operands reversed. +define i32 @f2(i32 %orig, i8 *%ptr) { +; CHECK: f2: +; CHECK-NOT: ni +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = and i32 %orig, -256 + %or = or i32 %ptr2, %ptr1 + ret i32 %or +} + +; Check a case where more bits than lower 8 are masked out of the +; register value. We can use IC but must keep the original mask. +define i32 @f3(i32 %orig, i8 *%ptr) { +; CHECK: f3: +; CHECK: nill %r2, 65024 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = and i32 %orig, -512 + %or = or i32 %ptr1, %ptr2 + ret i32 %or +} + +; Like f3, but with the operands reversed. +define i32 @f4(i32 %orig, i8 *%ptr) { +; CHECK: f4: +; CHECK: nill %r2, 65024 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = and i32 %orig, -512 + %or = or i32 %ptr2, %ptr1 + ret i32 %or +} + +; Check a case where the low 8 bits are cleared by a shift left. +define i32 @f5(i32 %orig, i8 *%ptr) { +; CHECK: f5: +; CHECK: sll %r2, 8 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = shl i32 %orig, 8 + %or = or i32 %ptr1, %ptr2 + ret i32 %or +} + +; Like f5, but with the operands reversed. +define i32 @f6(i32 %orig, i8 *%ptr) { +; CHECK: f6: +; CHECK: sll %r2, 8 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %ptr1 = shl i32 %orig, 8 + %or = or i32 %ptr2, %ptr1 + ret i32 %or +} + +; Check insertions into a constant. +define i32 @f7(i32 %orig, i8 *%ptr) { +; CHECK: f7: +; CHECK: lhi %r2, 256 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %or = or i32 %ptr2, 256 + ret i32 %or +} + +; Like f7, but with the operands reversed. +define i32 @f8(i32 %orig, i8 *%ptr) { +; CHECK: f8: +; CHECK: lhi %r2, 256 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i32 + %or = or i32 256, %ptr2 + ret i32 %or +} + +; Check the high end of the IC range. +define i32 @f9(i32 %orig, i8 *%src) { +; CHECK: f9: +; CHECK: ic %r2, 4095(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the next byte up, which should use ICY instead of IC. +define i32 @f10(i32 %orig, i8 *%src) { +; CHECK: f10: +; CHECK: icy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the high end of the ICY range. +define i32 @f11(i32 %orig, i8 *%src) { +; CHECK: f11: +; CHECK: icy %r2, 524287(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f12(i32 %orig, i8 *%src) { +; CHECK: f12: +; CHECK: agfi %r3, 524288 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the high end of the negative ICY range. +define i32 @f13(i32 %orig, i8 *%src) { +; CHECK: f13: +; CHECK: icy %r2, -1(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the low end of the ICY range. +define i32 @f14(i32 %orig, i8 *%src) { +; CHECK: f14: +; CHECK: icy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f15(i32 %orig, i8 *%src) { +; CHECK: f15: +; CHECK: agfi %r3, -524289 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check that IC allows an index. +define i32 @f16(i32 %orig, i8 *%src, i64 %index) { +; CHECK: f16: +; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %ptr1 = getelementptr i8 *%src, i64 %index + %ptr2 = getelementptr i8 *%ptr1, i64 4095 + %val = load i8 *%ptr2 + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} + +; Check that ICY allows an index. +define i32 @f17(i32 %orig, i8 *%src, i64 %index) { +; CHECK: f17: +; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %ptr1 = getelementptr i8 *%src, i64 %index + %ptr2 = getelementptr i8 *%ptr1, i64 4096 + %val = load i8 *%ptr2 + %src2 = zext i8 %val to i32 + %src1 = and i32 %orig, -256 + %or = or i32 %src2, %src1 + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/insert-02.ll b/test/CodeGen/SystemZ/insert-02.ll new file mode 100644 index 000000000000..471889dede6a --- /dev/null +++ b/test/CodeGen/SystemZ/insert-02.ll @@ -0,0 +1,230 @@ +; Test insertions of memory into the low byte of an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check a plain insertion with (or (and ... -0xff) (zext (load ....))). +; The whole sequence can be performed by IC. +define i64 @f1(i64 %orig, i8 *%ptr) { +; CHECK: f1: +; CHECK-NOT: ni +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = and i64 %orig, -256 + %or = or i64 %ptr1, %ptr2 + ret i64 %or +} + +; Like f1, but with the operands reversed. +define i64 @f2(i64 %orig, i8 *%ptr) { +; CHECK: f2: +; CHECK-NOT: ni +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = and i64 %orig, -256 + %or = or i64 %ptr2, %ptr1 + ret i64 %or +} + +; Check a case where more bits than lower 8 are masked out of the +; register value. We can use IC but must keep the original mask. +define i64 @f3(i64 %orig, i8 *%ptr) { +; CHECK: f3: +; CHECK: nill %r2, 65024 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = and i64 %orig, -512 + %or = or i64 %ptr1, %ptr2 + ret i64 %or +} + +; Like f3, but with the operands reversed. +define i64 @f4(i64 %orig, i8 *%ptr) { +; CHECK: f4: +; CHECK: nill %r2, 65024 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = and i64 %orig, -512 + %or = or i64 %ptr2, %ptr1 + ret i64 %or +} + +; Check a case where the low 8 bits are cleared by a shift left. +define i64 @f5(i64 %orig, i8 *%ptr) { +; CHECK: f5: +; CHECK: sllg %r2, %r2, 8 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = shl i64 %orig, 8 + %or = or i64 %ptr1, %ptr2 + ret i64 %or +} + +; Like f5, but with the operands reversed. +define i64 @f6(i64 %orig, i8 *%ptr) { +; CHECK: f6: +; CHECK: sllg %r2, %r2, 8 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %ptr1 = shl i64 %orig, 8 + %or = or i64 %ptr2, %ptr1 + ret i64 %or +} + +; Check insertions into a constant. +define i64 @f7(i64 %orig, i8 *%ptr) { +; CHECK: f7: +; CHECK: lghi %r2, 256 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %or = or i64 %ptr2, 256 + ret i64 %or +} + +; Like f7, but with the operands reversed. +define i64 @f8(i64 %orig, i8 *%ptr) { +; CHECK: f8: +; CHECK: lghi %r2, 256 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %val = load i8 *%ptr + %ptr2 = zext i8 %val to i64 + %or = or i64 256, %ptr2 + ret i64 %or +} + +; Check the high end of the IC range. +define i64 @f9(i64 %orig, i8 *%src) { +; CHECK: f9: +; CHECK: ic %r2, 4095(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the next byte up, which should use ICY instead of IC. +define i64 @f10(i64 %orig, i8 *%src) { +; CHECK: f10: +; CHECK: icy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the high end of the ICY range. +define i64 @f11(i64 %orig, i8 *%src) { +; CHECK: f11: +; CHECK: icy %r2, 524287(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f12(i64 %orig, i8 *%src) { +; CHECK: f12: +; CHECK: agfi %r3, 524288 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the high end of the negative ICY range. +define i64 @f13(i64 %orig, i8 *%src) { +; CHECK: f13: +; CHECK: icy %r2, -1(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the low end of the ICY range. +define i64 @f14(i64 %orig, i8 *%src) { +; CHECK: f14: +; CHECK: icy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f15(i64 %orig, i8 *%src) { +; CHECK: f15: +; CHECK: agfi %r3, -524289 +; CHECK: ic %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check that IC allows an index. +define i64 @f16(i64 %orig, i8 *%src, i64 %index) { +; CHECK: f16: +; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %ptr1 = getelementptr i8 *%src, i64 %index + %ptr2 = getelementptr i8 *%ptr1, i64 4095 + %val = load i8 *%ptr2 + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} + +; Check that ICY allows an index. +define i64 @f17(i64 %orig, i8 *%src, i64 %index) { +; CHECK: f17: +; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %ptr1 = getelementptr i8 *%src, i64 %index + %ptr2 = getelementptr i8 *%ptr1, i64 4096 + %val = load i8 *%ptr2 + %src2 = zext i8 %val to i64 + %src1 = and i64 %orig, -256 + %or = or i64 %src2, %src1 + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/insert-03.ll b/test/CodeGen/SystemZ/insert-03.ll new file mode 100644 index 000000000000..261eabd1be7d --- /dev/null +++ b/test/CodeGen/SystemZ/insert-03.ll @@ -0,0 +1,71 @@ +; Test insertions of 16-bit constants into one half of an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful IILL value. (We use NILL rather than IILL +; to clear 16 bits.) +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK-NOT: ni +; CHECK: iill %r2, 1 +; CHECK: br %r14 + %and = and i32 %a, 4294901760 + %or = or i32 %and, 1 + ret i32 %or +} + +; Check a middle value. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK-NOT: ni +; CHECK: iill %r2, 32769 +; CHECK: br %r14 + %and = and i32 %a, -65536 + %or = or i32 %and, 32769 + ret i32 %or +} + +; Check the highest useful IILL value. (We use OILL rather than IILL +; to set 16 bits.) +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK-NOT: ni +; CHECK: iill %r2, 65534 +; CHECK: br %r14 + %and = and i32 %a, 4294901760 + %or = or i32 %and, 65534 + ret i32 %or +} + +; Check the lowest useful IILH value. +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK-NOT: ni +; CHECK: iilh %r2, 1 +; CHECK: br %r14 + %and = and i32 %a, 65535 + %or = or i32 %and, 65536 + ret i32 %or +} + +; Check a middle value. +define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK-NOT: ni +; CHECK: iilh %r2, 32767 +; CHECK: br %r14 + %and = and i32 %a, 65535 + %or = or i32 %and, 2147418112 + ret i32 %or +} + +; Check the highest useful IILH value. +define i32 @f6(i32 %a) { +; CHECK: f6: +; CHECK-NOT: ni +; CHECK: iilh %r2, 65534 +; CHECK: br %r14 + %and = and i32 %a, 65535 + %or = or i32 %and, -131072 + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/insert-04.ll b/test/CodeGen/SystemZ/insert-04.ll new file mode 100644 index 000000000000..07f88b9859eb --- /dev/null +++ b/test/CodeGen/SystemZ/insert-04.ll @@ -0,0 +1,137 @@ +; Test insertions of 16-bit constants into an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful IILL value. (We use NILL rather than IILL +; to clear 16 bits.) +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK-NOT: ni +; CHECK: iill %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 18446744073709486080 + %or = or i64 %and, 1 + ret i64 %or +} + +; Check a middle value. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK-NOT: ni +; CHECK: iill %r2, 32769 +; CHECK: br %r14 + %and = and i64 %a, -65536 + %or = or i64 %and, 32769 + ret i64 %or +} + +; Check the highest useful IILL value. (We use OILL rather than IILL +; to set 16 bits.) +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: ni +; CHECK: iill %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, 18446744073709486080 + %or = or i64 %and, 65534 + ret i64 %or +} + +; Check the lowest useful IILH value. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK-NOT: ni +; CHECK: iilh %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414649855 + %or = or i64 %and, 65536 + ret i64 %or +} + +; Check a middle value. +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK-NOT: ni +; CHECK: iilh %r2, 32767 +; CHECK: br %r14 + %and = and i64 %a, -4294901761 + %or = or i64 %and, 2147418112 + ret i64 %or +} + +; Check the highest useful IILH value. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK-NOT: ni +; CHECK: iilh %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414649855 + %or = or i64 %and, 4294836224 + ret i64 %or +} + +; Check the lowest useful IIHL value. +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK-NOT: ni +; CHECK: iihl %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 18446462603027808255 + %or = or i64 %and, 4294967296 + ret i64 %or +} + +; Check a middle value. +define i64 @f8(i64 %a) { +; CHECK: f8: +; CHECK-NOT: ni +; CHECK: iihl %r2, 32767 +; CHECK: br %r14 + %and = and i64 %a, -281470681743361 + %or = or i64 %and, 140733193388032 + ret i64 %or +} + +; Check the highest useful IIHL value. +define i64 @f9(i64 %a) { +; CHECK: f9: +; CHECK-NOT: ni +; CHECK: iihl %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, 18446462603027808255 + %or = or i64 %and, 281466386776064 + ret i64 %or +} + +; Check the lowest useful IIHH value. +define i64 @f10(i64 %a) { +; CHECK: f10: +; CHECK-NOT: ni +; CHECK: iihh %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 281474976710655 + %or = or i64 %and, 281474976710656 + ret i64 %or +} + +; Check a middle value. +define i64 @f11(i64 %a) { +; CHECK: f11: +; CHECK-NOT: ni +; CHECK: iihh %r2, 32767 +; CHECK: br %r14 + %and = and i64 %a, 281474976710655 + %or = or i64 %and, 9223090561878065152 + ret i64 %or +} + +; Check the highest useful IIHH value. +define i64 @f12(i64 %a) { +; CHECK: f12: +; CHECK-NOT: ni +; CHECK: iihh %r2, 65534 +; CHECK: br %r14 + %and = and i64 %a, 281474976710655 + %or = or i64 %and, 18446181123756130304 + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/insert-05.ll b/test/CodeGen/SystemZ/insert-05.ll new file mode 100644 index 000000000000..da51676b99cf --- /dev/null +++ b/test/CodeGen/SystemZ/insert-05.ll @@ -0,0 +1,224 @@ +; Test insertions of 32-bit constants into one half of an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Prefer LHI over IILF for signed 16-bit constants. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK-NOT: ni +; CHECK: lhi %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 1 + ret i64 %or +} + +; Check the high end of the LHI range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK-NOT: ni +; CHECK: lhi %r2, 32767 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 32767 + ret i64 %or +} + +; Check the next value up, which should use IILF instead. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: ni +; CHECK: iilf %r2, 32768 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 32768 + ret i64 %or +} + +; Check a value in which the lower 16 bits are clear. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK-NOT: ni +; CHECK: iilf %r2, 65536 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 65536 + ret i64 %or +} + +; Check the highest useful IILF value (-0x8001). +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK-NOT: ni +; CHECK: iilf %r2, 4294934527 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 4294934527 + ret i64 %or +} + +; Check the next value up, which should use LHI instead. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK-NOT: ni +; CHECK: lhi %r2, -32768 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 4294934528 + ret i64 %or +} + +; Check the highest useful LHI value. (We use OILF for -1 instead, although +; LHI might be better there too.) +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK-NOT: ni +; CHECK: lhi %r2, -2 +; CHECK: br %r14 + %and = and i64 %a, 18446744069414584320 + %or = or i64 %and, 4294967294 + ret i64 %or +} + +; Check that SRLG is still used if some of the high bits are known to be 0 +; (and so might be removed from the mask). +define i64 @f8(i64 %a) { +; CHECK: f8: +; CHECK: srlg %r2, %r2, 1 +; CHECK-NEXT: iilf %r2, 32768 +; CHECK: br %r14 + %shifted = lshr i64 %a, 1 + %and = and i64 %shifted, 18446744069414584320 + %or = or i64 %and, 32768 + ret i64 %or +} + +; Repeat f8 with addition, which is known to be equivalent to OR in this case. +define i64 @f9(i64 %a) { +; CHECK: f9: +; CHECK: srlg %r2, %r2, 1 +; CHECK-NEXT: iilf %r2, 32768 +; CHECK: br %r14 + %shifted = lshr i64 %a, 1 + %and = and i64 %shifted, 18446744069414584320 + %or = add i64 %and, 32768 + ret i64 %or +} + +; Repeat f8 with already-zero bits removed from the mask. +define i64 @f10(i64 %a) { +; CHECK: f10: +; CHECK: srlg %r2, %r2, 1 +; CHECK-NEXT: iilf %r2, 32768 +; CHECK: br %r14 + %shifted = lshr i64 %a, 1 + %and = and i64 %shifted, 9223372032559808512 + %or = or i64 %and, 32768 + ret i64 %or +} + +; Repeat f10 with addition, which is known to be equivalent to OR in this case. +define i64 @f11(i64 %a) { +; CHECK: f11: +; CHECK: srlg %r2, %r2, 1 +; CHECK-NEXT: iilf %r2, 32768 +; CHECK: br %r14 + %shifted = lshr i64 %a, 1 + %and = and i64 %shifted, 9223372032559808512 + %or = add i64 %and, 32768 + ret i64 %or +} + +; Check the lowest useful IIHF value. +define i64 @f12(i64 %a) { +; CHECK: f12: +; CHECK-NOT: ni +; CHECK: iihf %r2, 1 +; CHECK: br %r14 + %and = and i64 %a, 4294967295 + %or = or i64 %and, 4294967296 + ret i64 %or +} + +; Check a value in which the lower 16 bits are clear. +define i64 @f13(i64 %a) { +; CHECK: f13: +; CHECK-NOT: ni +; CHECK: iihf %r2, 2147483648 +; CHECK: br %r14 + %and = and i64 %a, 4294967295 + %or = or i64 %and, 9223372036854775808 + ret i64 %or +} + +; Check the highest useful IIHF value (0xfffffffe). +define i64 @f14(i64 %a) { +; CHECK: f14: +; CHECK-NOT: ni +; CHECK: iihf %r2, 4294967294 +; CHECK: br %r14 + %and = and i64 %a, 4294967295 + %or = or i64 %and, 18446744065119617024 + ret i64 %or +} + +; Check a case in which some of the low 32 bits are known to be clear, +; and so could be removed from the AND mask. +define i64 @f15(i64 %a) { +; CHECK: f15: +; CHECK: sllg %r2, %r2, 1 +; CHECK-NEXT: iihf %r2, 1 +; CHECK: br %r14 + %shifted = shl i64 %a, 1 + %and = and i64 %shifted, 4294967295 + %or = or i64 %and, 4294967296 + ret i64 %or +} + +; Repeat f15 with the zero bits explicitly removed from the mask. +define i64 @f16(i64 %a) { +; CHECK: f16: +; CHECK: sllg %r2, %r2, 1 +; CHECK-NEXT: iihf %r2, 1 +; CHECK: br %r14 + %shifted = shl i64 %a, 1 + %and = and i64 %shifted, 4294967294 + %or = or i64 %and, 4294967296 + ret i64 %or +} + +; Check concatenation of two i32s. +define i64 @f17(i32 %a) { +; CHECK: f17: +; CHECK: msr %r2, %r2 +; CHECK-NEXT: iihf %r2, 1 +; CHECK: br %r14 + %mul = mul i32 %a, %a + %ext = zext i32 %mul to i64 + %or = or i64 %ext, 4294967296 + ret i64 %or +} + +; Repeat f17 with the operands reversed. +define i64 @f18(i32 %a) { +; CHECK: f18: +; CHECK: msr %r2, %r2 +; CHECK-NEXT: iihf %r2, 1 +; CHECK: br %r14 + %mul = mul i32 %a, %a + %ext = zext i32 %mul to i64 + %or = or i64 4294967296, %ext + ret i64 %or +} + +; The truncation here isn't free; we need an explicit zero extension. +define i64 @f19(i32 %a) { +; CHECK: f19: +; CHECK: llgcr %r2, %r2 +; CHECK: oihl %r2, 1 +; CHECK: br %r14 + %trunc = trunc i32 %a to i8 + %ext = zext i8 %trunc to i64 + %or = or i64 %ext, 4294967296 + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/insert-06.ll b/test/CodeGen/SystemZ/insert-06.ll new file mode 100644 index 000000000000..4a13ef47c888 --- /dev/null +++ b/test/CodeGen/SystemZ/insert-06.ll @@ -0,0 +1,167 @@ +; Test insertions of i32s into the low half of an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Insertion of an i32 can be done using LR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK-NOT: {{%r[23]}} +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %low = zext i32 %b to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %high, %low + ret i64 %res +} + +; ... and again with the operands reversed. +define i64 @f2(i64 %a, i32 %b) { +; CHECK: f2: +; CHECK-NOT: {{%r[23]}} +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %low = zext i32 %b to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %low, %high + ret i64 %res +} + +; Like f1, but with "in register" zero extension. +define i64 @f3(i64 %a, i64 %b) { +; CHECK: f3: +; CHECK-NOT: {{%r[23]}} +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %low = and i64 %b, 4294967295 + %high = and i64 %a, -4294967296 + %res = or i64 %high, %low + ret i64 %res +} + +; ... and again with the operands reversed. +define i64 @f4(i64 %a, i64 %b) { +; CHECK: f4: +; CHECK-NOT: {{%r[23]}} +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %low = and i64 %b, 4294967295 + %high = and i64 %a, -4294967296 + %res = or i64 %low, %high + ret i64 %res +} + +; Unary operations can be done directly into the low half. +define i64 @f5(i64 %a, i32 %b) { +; CHECK: f5: +; CHECK-NOT: {{%r[23]}} +; CHECK: lcr %r2, %r3 +; CHECK: br %r14 + %neg = sub i32 0, %b + %low = zext i32 %neg to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %high, %low + ret i64 %res +} + +; ...likewise three-operand binary operations like RLL. +define i64 @f6(i64 %a, i32 %b) { +; CHECK: f6: +; CHECK-NOT: {{%r[23]}} +; CHECK: rll %r2, %r3, 1 +; CHECK: br %r14 + %parta = shl i32 %b, 1 + %partb = lshr i32 %b, 31 + %rot = or i32 %parta, %partb + %low = zext i32 %rot to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %low, %high + ret i64 %res +} + +; Loads can be done directly into the low half. The range of L is checked +; in the move tests. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK-NOT: {{%r[23]}} +; CHECK: l %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %low = zext i32 %b to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %high, %low + ret i64 %res +} + +; ...likewise extending loads. +define i64 @f8(i64 %a, i8 *%src) { +; CHECK: f8: +; CHECK-NOT: {{%r[23]}} +; CHECK: lb %r2, 0(%r3) +; CHECK: br %r14 + %byte = load i8 *%src + %b = sext i8 %byte to i32 + %low = zext i32 %b to i64 + %high = and i64 %a, -4294967296 + %res = or i64 %high, %low + ret i64 %res +} + +; Check a case like f1 in which there is no AND. We simply know from context +; that the upper half of one OR operand and the lower half of the other are +; both clear. +define i64 @f9(i64 %a, i32 %b) { +; CHECK: f9: +; CHECK: sllg %r2, %r2, 32 +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %shift = shl i64 %a, 32 + %low = zext i32 %b to i64 + %or = or i64 %shift, %low + ret i64 %or +} + +; ...and again with the operands reversed. +define i64 @f10(i64 %a, i32 %b) { +; CHECK: f10: +; CHECK: sllg %r2, %r2, 32 +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %shift = shl i64 %a, 32 + %low = zext i32 %b to i64 + %or = or i64 %low, %shift + ret i64 %or +} + +; Like f9, but with "in register" zero extension. +define i64 @f11(i64 %a, i64 %b) { +; CHECK: f11: +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %shift = shl i64 %a, 32 + %low = and i64 %b, 4294967295 + %or = or i64 %shift, %low + ret i64 %or +} + +; ...and again with the operands reversed. +define i64 @f12(i64 %a, i64 %b) { +; CHECK: f12: +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %shift = shl i64 %a, 32 + %low = and i64 %b, 4294967295 + %or = or i64 %low, %shift + ret i64 %or +} + +; Like f9, but for larger shifts than 32. +define i64 @f13(i64 %a, i32 %b) { +; CHECK: f13: +; CHECK: sllg %r2, %r2, 60 +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + %shift = shl i64 %a, 60 + %low = zext i32 %b to i64 + %or = or i64 %shift, %low + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/int-add-01.ll b/test/CodeGen/SystemZ/int-add-01.ll new file mode 100644 index 000000000000..d12ac229774e --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-01.ll @@ -0,0 +1,131 @@ +; Test 32-bit addition in which the second operand is a sign-extended +; i16 memory value. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the AH range. +define i32 @f1(i32 %lhs, i16 *%src) { +; CHECK: f1: +; CHECK: ah %r2, 0(%r3) +; CHECK: br %r14 + %half = load i16 *%src + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned AH range. +define i32 @f2(i32 %lhs, i16 *%src) { +; CHECK: f2: +; CHECK: ah %r2, 4094(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2047 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which should use AHY instead of AH. +define i32 @f3(i32 %lhs, i16 *%src) { +; CHECK: f3: +; CHECK: ahy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2048 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned AHY range. +define i32 @f4(i32 %lhs, i16 *%src) { +; CHECK: f4: +; CHECK: ahy %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i32 %lhs, i16 *%src) { +; CHECK: f5: +; CHECK: agfi %r3, 524288 +; CHECK: ah %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the negative aligned AHY range. +define i32 @f6(i32 %lhs, i16 *%src) { +; CHECK: f6: +; CHECK: ahy %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the low end of the AHY range. +define i32 @f7(i32 %lhs, i16 *%src) { +; CHECK: f7: +; CHECK: ahy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 %lhs, i16 *%src) { +; CHECK: f8: +; CHECK: agfi %r3, -524290 +; CHECK: ah %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check that AH allows an index. +define i32 @f9(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: ah %r2, 4094({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} + +; Check that AHY allows an index. +define i32 @f10(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: ahy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = add i32 %lhs, %rhs + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/int-add-02.ll b/test/CodeGen/SystemZ/int-add-02.ll new file mode 100644 index 000000000000..568ad1c4471d --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-02.ll @@ -0,0 +1,129 @@ +; Test 32-bit addition in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check AR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: ar %r2, %r3 +; CHECK: br %r14 + %add = add i32 %a, %b + ret i32 %add +} + +; Check the low end of the A range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: a %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %add = add i32 %a, %b + ret i32 %add +} + +; Check the high end of the aligned A range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: a %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the next word up, which should use AY instead of A. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: ay %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the high end of the aligned AY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: ay %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: a %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the high end of the negative aligned AY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: ay %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the low end of the AY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: ay %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: a %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check that A allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} + +; Check that AY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %add = add i32 %a, %b + ret i32 %add +} diff --git a/test/CodeGen/SystemZ/int-add-03.ll b/test/CodeGen/SystemZ/int-add-03.ll new file mode 100644 index 000000000000..46103575b7b2 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-03.ll @@ -0,0 +1,102 @@ +; Test additions between an i64 and a sign-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check AGFR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK: agfr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check AGF with no displacement. +define i64 @f2(i64 %a, i32 *%src) { +; CHECK: f2: +; CHECK: agf %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the aligned AGF range. +define i64 @f3(i64 %a, i32 *%src) { +; CHECK: f3: +; CHECK: agf %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i32 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: agf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the negative aligned AGF range. +define i64 @f5(i64 %a, i32 *%src) { +; CHECK: f5: +; CHECK: agf %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the low end of the AGF range. +define i64 @f6(i64 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agf %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524292 +; CHECK: agf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check that AGF allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: agf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} diff --git a/test/CodeGen/SystemZ/int-add-04.ll b/test/CodeGen/SystemZ/int-add-04.ll new file mode 100644 index 000000000000..1c2dc76781ce --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-04.ll @@ -0,0 +1,102 @@ +; Test additions between an i64 and a zero-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ALGFR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK: algfr %r2, %r3 +; CHECK: br %r14 + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check ALGF with no displacement. +define i64 @f2(i64 %a, i32 *%src) { +; CHECK: f2: +; CHECK: algf %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the aligned ALGF range. +define i64 @f3(i64 %a, i32 *%src) { +; CHECK: f3: +; CHECK: algf %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i32 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: algf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the negative aligned ALGF range. +define i64 @f5(i64 %a, i32 *%src) { +; CHECK: f5: +; CHECK: algf %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the low end of the ALGF range. +define i64 @f6(i64 %a, i32 *%src) { +; CHECK: f6: +; CHECK: algf %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524292 +; CHECK: algf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check that ALGF allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} diff --git a/test/CodeGen/SystemZ/int-add-05.ll b/test/CodeGen/SystemZ/int-add-05.ll new file mode 100644 index 000000000000..ae32cc4ad01a --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-05.ll @@ -0,0 +1,94 @@ +; Test 64-bit addition in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check AGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: agr %r2, %r3 +; CHECK: br %r14 + %add = add i64 %a, %b + ret i64 %add +} + +; Check AG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: ag %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %add = add i64 %a, %b + ret i64 %add +} + +; Check the high end of the aligned AG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: ag %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: ag %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} + +; Check the high end of the negative aligned AG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: ag %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} + +; Check the low end of the AG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: ag %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: ag %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} + +; Check that AG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %add = add i64 %a, %b + ret i64 %add +} diff --git a/test/CodeGen/SystemZ/int-add-06.ll b/test/CodeGen/SystemZ/int-add-06.ll new file mode 100644 index 000000000000..3a9c698dd241 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-06.ll @@ -0,0 +1,93 @@ +; Test 32-bit addition in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check additions of 1. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: ahi %r2, 1 +; CHECK: br %r14 + %add = add i32 %a, 1 + ret i32 %add +} + +; Check the high end of the AHI range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: ahi %r2, 32767 +; CHECK: br %r14 + %add = add i32 %a, 32767 + ret i32 %add +} + +; Check the next value up, which must use AFI instead. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: afi %r2, 32768 +; CHECK: br %r14 + %add = add i32 %a, 32768 + ret i32 %add +} + +; Check the high end of the signed 32-bit range. +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: afi %r2, 2147483647 +; CHECK: br %r14 + %add = add i32 %a, 2147483647 + ret i32 %add +} + +; Check the next value up, which is treated as a negative value. +define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK: afi %r2, -2147483648 +; CHECK: br %r14 + %add = add i32 %a, 2147483648 + ret i32 %add +} + +; Check the high end of the negative AHI range. +define i32 @f6(i32 %a) { +; CHECK: f6: +; CHECK: ahi %r2, -1 +; CHECK: br %r14 + %add = add i32 %a, -1 + ret i32 %add +} + +; Check the low end of the AHI range. +define i32 @f7(i32 %a) { +; CHECK: f7: +; CHECK: ahi %r2, -32768 +; CHECK: br %r14 + %add = add i32 %a, -32768 + ret i32 %add +} + +; Check the next value down, which must use AFI instead. +define i32 @f8(i32 %a) { +; CHECK: f8: +; CHECK: afi %r2, -32769 +; CHECK: br %r14 + %add = add i32 %a, -32769 + ret i32 %add +} + +; Check the low end of the signed 32-bit range. +define i32 @f9(i32 %a) { +; CHECK: f9: +; CHECK: afi %r2, -2147483648 +; CHECK: br %r14 + %add = add i32 %a, -2147483648 + ret i32 %add +} + +; Check the next value down, which is treated as a positive value. +define i32 @f10(i32 %a) { +; CHECK: f10: +; CHECK: afi %r2, 2147483647 +; CHECK: br %r14 + %add = add i32 %a, -2147483649 + ret i32 %add +} diff --git a/test/CodeGen/SystemZ/int-add-07.ll b/test/CodeGen/SystemZ/int-add-07.ll new file mode 100644 index 000000000000..a065bb2ee137 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-07.ll @@ -0,0 +1,131 @@ +; Test 64-bit addition in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check additions of 1. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: {{aghi %r2, 1|la %r[0-5], 1\(%r2\)}} +; CHECK: br %r14 + %add = add i64 %a, 1 + ret i64 %add +} + +; Check the high end of the AGHI range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: aghi %r2, 32767 +; CHECK: br %r14 + %add = add i64 %a, 32767 + ret i64 %add +} + +; Check the next value up, which must use AGFI instead. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: {{agfi %r2, 32768|lay %r[0-5], 32768\(%r2\)}} +; CHECK: br %r14 + %add = add i64 %a, 32768 + ret i64 %add +} + +; Check the high end of the AGFI range. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK: agfi %r2, 2147483647 +; CHECK: br %r14 + %add = add i64 %a, 2147483647 + ret i64 %add +} + +; Check the next value up, which must use ALGFI instead. +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK: algfi %r2, 2147483648 +; CHECK: br %r14 + %add = add i64 %a, 2147483648 + ret i64 %add +} + +; Check the high end of the ALGFI range. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK: algfi %r2, 4294967295 +; CHECK: br %r14 + %add = add i64 %a, 4294967295 + ret i64 %add +} + +; Check the next value up, which must be loaded into a register first. +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK: llihl %r0, 1 +; CHECK: agr +; CHECK: br %r14 + %add = add i64 %a, 4294967296 + ret i64 %add +} + +; Check the high end of the negative AGHI range. +define i64 @f8(i64 %a) { +; CHECK: f8: +; CHECK: aghi %r2, -1 +; CHECK: br %r14 + %add = add i64 %a, -1 + ret i64 %add +} + +; Check the low end of the AGHI range. +define i64 @f9(i64 %a) { +; CHECK: f9: +; CHECK: aghi %r2, -32768 +; CHECK: br %r14 + %add = add i64 %a, -32768 + ret i64 %add +} + +; Check the next value down, which must use AGFI instead. +define i64 @f10(i64 %a) { +; CHECK: f10: +; CHECK: {{agfi %r2, -32769|lay %r[0-5]+, -32769\(%r2\)}} +; CHECK: br %r14 + %add = add i64 %a, -32769 + ret i64 %add +} + +; Check the low end of the AGFI range. +define i64 @f11(i64 %a) { +; CHECK: f11: +; CHECK: agfi %r2, -2147483648 +; CHECK: br %r14 + %add = add i64 %a, -2147483648 + ret i64 %add +} + +; Check the next value down, which must use SLGFI instead. +define i64 @f12(i64 %a) { +; CHECK: f12: +; CHECK: slgfi %r2, 2147483649 +; CHECK: br %r14 + %add = add i64 %a, -2147483649 + ret i64 %add +} + +; Check the low end of the SLGFI range. +define i64 @f13(i64 %a) { +; CHECK: f13: +; CHECK: slgfi %r2, 4294967295 +; CHECK: br %r14 + %add = add i64 %a, -4294967295 + ret i64 %add +} + +; Check the next value down, which must use register addition instead. +define i64 @f14(i64 %a) { +; CHECK: f14: +; CHECK: llihf %r0, 4294967295 +; CHECK: agr +; CHECK: br %r14 + %add = add i64 %a, -4294967296 + ret i64 %add +} diff --git a/test/CodeGen/SystemZ/int-add-08.ll b/test/CodeGen/SystemZ/int-add-08.ll new file mode 100644 index 000000000000..b1f820fe3d84 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-08.ll @@ -0,0 +1,110 @@ +; Test 128-bit addition in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register addition. +define void @f1(i128 *%ptr) { +; CHECK: f1: +; CHECK: algr +; CHECK: alcgr +; CHECK: br %r14 + %value = load i128 *%ptr + %add = add i128 %value, %value + store i128 %add, i128 *%ptr + ret void +} + +; Test memory addition with no offset. Making the load of %a volatile +; should force the memory operand to be %b. +define void @f2(i128 *%aptr, i64 %addr) { +; CHECK: f2: +; CHECK: alg {{%r[0-5]}}, 8(%r3) +; CHECK: alcg {{%r[0-5]}}, 0(%r3) +; CHECK: br %r14 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + +; Test the highest aligned offset that is in range of both ALG and ALCG. +define void @f3(i128 *%aptr, i64 %base) { +; CHECK: f3: +; CHECK: alg {{%r[0-5]}}, 524280(%r3) +; CHECK: alcg {{%r[0-5]}}, 524272(%r3) +; CHECK: br %r14 + %addr = add i64 %base, 524272 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + +; Test the next doubleword up, which requires separate address logic for ALG. +define void @f4(i128 *%aptr, i64 %base) { +; CHECK: f4: +; CHECK: lgr [[BASE:%r[1-5]]], %r3 +; CHECK: agfi [[BASE]], 524288 +; CHECK: alg {{%r[0-5]}}, 0([[BASE]]) +; CHECK: alcg {{%r[0-5]}}, 524280(%r3) +; CHECK: br %r14 + %addr = add i64 %base, 524280 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + +; Test the next doubleword after that, which requires separate logic for +; both instructions. It would be better to create an anchor at 524288 +; that both instructions can use, but that isn't implemented yet. +define void @f5(i128 *%aptr, i64 %base) { +; CHECK: f5: +; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: br %r14 + %addr = add i64 %base, 524288 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + +; Test the lowest displacement that is in range of both ALG and ALCG. +define void @f6(i128 *%aptr, i64 %base) { +; CHECK: f6: +; CHECK: alg {{%r[0-5]}}, -524280(%r3) +; CHECK: alcg {{%r[0-5]}}, -524288(%r3) +; CHECK: br %r14 + %addr = add i64 %base, -524288 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + +; Test the next doubleword down, which is out of range of the ALCG. +define void @f7(i128 *%aptr, i64 %base) { +; CHECK: f7: +; CHECK: alg {{%r[0-5]}}, -524288(%r3) +; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: br %r14 + %addr = add i64 %base, -524296 + %bptr = inttoptr i64 %addr to i128 * + %a = load volatile i128 *%aptr + %b = load i128 *%bptr + %add = add i128 %a, %b + store i128 %add, i128 *%aptr + ret void +} + diff --git a/test/CodeGen/SystemZ/int-add-09.ll b/test/CodeGen/SystemZ/int-add-09.ll new file mode 100644 index 000000000000..bfe63389f189 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-09.ll @@ -0,0 +1,56 @@ +; Test 128-bit addition in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check additions of 1. The XOR ensures that we don't instead load the +; constant into a register and use memory addition. +define void @f1(i128 *%aptr) { +; CHECK: f1: +; CHECK: algfi {{%r[0-5]}}, 1 +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 128 + %add = add i128 %xor, 1 + store i128 %add, i128 *%aptr + ret void +} + +; Check the high end of the ALGFI range. +define void @f2(i128 *%aptr) { +; CHECK: f2: +; CHECK: algfi {{%r[0-5]}}, 4294967295 +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 128 + %add = add i128 %xor, 4294967295 + store i128 %add, i128 *%aptr + ret void +} + +; Check the next value up, which must use register addition. +define void @f3(i128 *%aptr) { +; CHECK: f3: +; CHECK: algr +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 128 + %add = add i128 %xor, 4294967296 + store i128 %add, i128 *%aptr + ret void +} + +; Check addition of -1, which must also use register addition. +define void @f4(i128 *%aptr) { +; CHECK: f4: +; CHECK: algr +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 128 + %add = add i128 %xor, -1 + store i128 %add, i128 *%aptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-add-10.ll b/test/CodeGen/SystemZ/int-add-10.ll new file mode 100644 index 000000000000..17cfdbe33771 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-10.ll @@ -0,0 +1,165 @@ +; Test 128-bit addition in which the second operand is a zero-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register additions. The XOR ensures that we don't instead zero-extend +; %b into a register and use memory addition. +define void @f1(i128 *%aptr, i32 %b) { +; CHECK: f1: +; CHECK: algfr {{%r[0-5]}}, %r3 +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Like f1, but using an "in-register" extension. +define void @f2(i128 *%aptr, i64 %b) { +; CHECK: f2: +; CHECK: algfr {{%r[0-5]}}, %r3 +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %trunc = trunc i64 %b to i32 + %bext = zext i32 %trunc to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Test register addition in cases where the second operand is zero extended +; from i64 rather than i32, but is later masked to i32 range. +define void @f3(i128 *%aptr, i64 %b) { +; CHECK: f3: +; CHECK: algfr {{%r[0-5]}}, %r3 +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %bext = zext i64 %b to i128 + %and = and i128 %bext, 4294967295 + %add = add i128 %xor, %and + store i128 %add, i128 *%aptr + ret void +} + +; Test ALGF with no offset. +define void @f4(i128 *%aptr, i32 *%bsrc) { +; CHECK: f4: +; CHECK: algf {{%r[0-5]}}, 0(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %b = load i32 *%bsrc + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check the high end of the ALGF range. +define void @f5(i128 *%aptr, i32 *%bsrc) { +; CHECK: f5: +; CHECK: algf {{%r[0-5]}}, 524284(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i64 131071 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check the next word up, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i128 *%aptr, i32 *%bsrc) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: algf {{%r[0-5]}}, 0(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i64 131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check the high end of the negative aligned ALGF range. +define void @f7(i128 *%aptr, i32 *%bsrc) { +; CHECK: f7: +; CHECK: algf {{%r[0-5]}}, -4(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -1 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check the low end of the ALGF range. +define void @f8(i128 *%aptr, i32 *%bsrc) { +; CHECK: f8: +; CHECK: algf {{%r[0-5]}}, -524288(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i128 *%aptr, i32 *%bsrc) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: algf {{%r[0-5]}}, 0(%r3) +; CHECK: alcgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -131073 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} + +; Check that ALGF allows an index. +define void @f10(i128 *%aptr, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %add = add i128 %xor, %bext + store i128 %add, i128 *%aptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-add-11.ll b/test/CodeGen/SystemZ/int-add-11.ll new file mode 100644 index 000000000000..47a776ecf6ec --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-11.ll @@ -0,0 +1,128 @@ +; Test 32-bit additions of constants to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check additions of 1. +define void @f1(i32 *%ptr) { +; CHECK: f1: +; CHECK: asi 0(%r2), 1 +; CHECK: br %r14 + %val = load i32 *%ptr + %add = add i32 %val, 127 + store i32 %add, i32 *%ptr + ret void +} + +; Check the high end of the constant range. +define void @f2(i32 *%ptr) { +; CHECK: f2: +; CHECK: asi 0(%r2), 127 +; CHECK: br %r14 + %val = load i32 *%ptr + %add = add i32 %val, 127 + store i32 %add, i32 *%ptr + ret void +} + +; Check the next constant up, which must use an addition and a store. +; Both L/AHI and LHI/A would be OK. +define void @f3(i32 *%ptr) { +; CHECK: f3: +; CHECK-NOT: asi +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = load i32 *%ptr + %add = add i32 %val, 128 + store i32 %add, i32 *%ptr + ret void +} + +; Check the low end of the constant range. +define void @f4(i32 *%ptr) { +; CHECK: f4: +; CHECK: asi 0(%r2), -128 +; CHECK: br %r14 + %val = load i32 *%ptr + %add = add i32 %val, -128 + store i32 %add, i32 *%ptr + ret void +} + +; Check the next value down, with the same comment as f3. +define void @f5(i32 *%ptr) { +; CHECK: f5: +; CHECK-NOT: asi +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %val = load i32 *%ptr + %add = add i32 %val, -129 + store i32 %add, i32 *%ptr + ret void +} + +; Check the high end of the aligned ASI range. +define void @f6(i32 *%base) { +; CHECK: f6: +; CHECK: asi 524284(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131071 + %val = load i32 *%ptr + %add = add i32 %val, 1 + store i32 %add, i32 *%ptr + ret void +} + +; Check the next word up, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f7(i32 *%base) { +; CHECK: f7: +; CHECK: agfi %r2, 524288 +; CHECK: asi 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131072 + %val = load i32 *%ptr + %add = add i32 %val, 1 + store i32 %add, i32 *%ptr + ret void +} + +; Check the low end of the ASI range. +define void @f8(i32 *%base) { +; CHECK: f8: +; CHECK: asi -524288(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131072 + %val = load i32 *%ptr + %add = add i32 %val, 1 + store i32 %add, i32 *%ptr + ret void +} + +; Check the next word down, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i32 *%base) { +; CHECK: f9: +; CHECK: agfi %r2, -524292 +; CHECK: asi 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131073 + %val = load i32 *%ptr + %add = add i32 %val, 1 + store i32 %add, i32 *%ptr + ret void +} + +; Check that ASI does not allow indices. +define void @f10(i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: agr %r2, %r3 +; CHECK: asi 4(%r2), 1 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4 + %ptr = inttoptr i64 %add2 to i32 * + %val = load i32 *%ptr + %add = add i32 %val, 1 + store i32 %add, i32 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-add-12.ll b/test/CodeGen/SystemZ/int-add-12.ll new file mode 100644 index 000000000000..ae1c1f735fa7 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-12.ll @@ -0,0 +1,128 @@ +; Test 64-bit additions of constants to memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check additions of 1. +define void @f1(i64 *%ptr) { +; CHECK: f1: +; CHECK: agsi 0(%r2), 1 +; CHECK: br %r14 + %val = load i64 *%ptr + %add = add i64 %val, 127 + store i64 %add, i64 *%ptr + ret void +} + +; Check the high end of the constant range. +define void @f2(i64 *%ptr) { +; CHECK: f2: +; CHECK: agsi 0(%r2), 127 +; CHECK: br %r14 + %val = load i64 *%ptr + %add = add i64 %val, 127 + store i64 %add, i64 *%ptr + ret void +} + +; Check the next constant up, which must use an addition and a store. +; Both LG/AGHI and LGHI/AG would be OK. +define void @f3(i64 *%ptr) { +; CHECK: f3: +; CHECK-NOT: agsi +; CHECK: stg %r0, 0(%r2) +; CHECK: br %r14 + %val = load i64 *%ptr + %add = add i64 %val, 128 + store i64 %add, i64 *%ptr + ret void +} + +; Check the low end of the constant range. +define void @f4(i64 *%ptr) { +; CHECK: f4: +; CHECK: agsi 0(%r2), -128 +; CHECK: br %r14 + %val = load i64 *%ptr + %add = add i64 %val, -128 + store i64 %add, i64 *%ptr + ret void +} + +; Check the next value down, with the same comment as f3. +define void @f5(i64 *%ptr) { +; CHECK: f5: +; CHECK-NOT: agsi +; CHECK: stg %r0, 0(%r2) +; CHECK: br %r14 + %val = load i64 *%ptr + %add = add i64 %val, -129 + store i64 %add, i64 *%ptr + ret void +} + +; Check the high end of the aligned AGSI range. +define void @f6(i64 *%base) { +; CHECK: f6: +; CHECK: agsi 524280(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65535 + %val = load i64 *%ptr + %add = add i64 %val, 1 + store i64 %add, i64 *%ptr + ret void +} + +; Check the next doubleword up, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f7(i64 *%base) { +; CHECK: f7: +; CHECK: agfi %r2, 524288 +; CHECK: agsi 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65536 + %val = load i64 *%ptr + %add = add i64 %val, 1 + store i64 %add, i64 *%ptr + ret void +} + +; Check the low end of the AGSI range. +define void @f8(i64 *%base) { +; CHECK: f8: +; CHECK: agsi -524288(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65536 + %val = load i64 *%ptr + %add = add i64 %val, 1 + store i64 %add, i64 *%ptr + ret void +} + +; Check the next doubleword down, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i64 *%base) { +; CHECK: f9: +; CHECK: agfi %r2, -524296 +; CHECK: agsi 0(%r2), 1 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65537 + %val = load i64 *%ptr + %add = add i64 %val, 1 + store i64 %add, i64 *%ptr + ret void +} + +; Check that AGSI does not allow indices. +define void @f10(i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: agr %r2, %r3 +; CHECK: agsi 8(%r2), 1 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 8 + %ptr = inttoptr i64 %add2 to i64 * + %val = load i64 *%ptr + %add = add i64 %val, 1 + store i64 %add, i64 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-cmp-01.ll b/test/CodeGen/SystemZ/int-cmp-01.ll new file mode 100644 index 000000000000..aa432f0b04fb --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-01.ll @@ -0,0 +1,151 @@ +; Test 32-bit signed comparison in which the second operand is sign-extended +; from an i16 memory value. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the CH range. +define void @f1(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f1: +; CHECK: ch %r2, 0(%r3) +; CHECK: br %r14 + %half = load i16 *%src + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the high end of the aligned CH range. +define void @f2(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f2: +; CHECK: ch %r2, 4094(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2047 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the next halfword up, which should use CHY instead of CH. +define void @f3(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f3: +; CHECK: chy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2048 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the high end of the aligned CHY range. +define void @f4(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f4: +; CHECK: chy %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f5(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f5: +; CHECK: agfi %r3, 524288 +; CHECK: ch %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the high end of the negative aligned CHY range. +define void @f6(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f6: +; CHECK: chy %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the low end of the CHY range. +define void @f7(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f7: +; CHECK: chy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i32 %lhs, i16 *%src, i32 *%dst) { +; CHECK: f8: +; CHECK: agfi %r3, -524290 +; CHECK: ch %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check that CH allows an index. +define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) { +; CHECK: f9: +; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} + +; Check that CHY allows an index. +define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) { +; CHECK: f10: +; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %cond = icmp slt i32 %lhs, %rhs + %res = select i1 %cond, i32 100, i32 200 + store i32 %res, i32 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/int-cmp-02.ll b/test/CodeGen/SystemZ/int-cmp-02.ll new file mode 100644 index 000000000000..c158fb4af77f --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-02.ll @@ -0,0 +1,162 @@ +; Test 32-bit signed comparison in which the second operand is a variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register comparison. +define double @f1(double %a, double %b, i32 %i1, i32 %i2) { +; CHECK: f1: +; CHECK: cr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the C range. +define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { +; CHECK: f2: +; CHECK: c %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned C range. +define double @f3(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f3: +; CHECK: c %r2, 4092(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1023 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which should use CY instead of C. +define double @f4(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f4: +; CHECK: cy %r2, 4096(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1024 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CY range. +define double @f5(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f5: +; CHECK: cy %r2, 524284(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131071 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f6(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: c %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131072 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CY range. +define double @f7(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f7: +; CHECK: cy %r2, -4(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CY range. +define double @f8(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f8: +; CHECK: cy %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131072 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f9(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: c %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131073 + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that C allows an index. +define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CY allows an index. +define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { +; CHECK: f11: +; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %i2 = load i32 *%ptr + %cond = icmp slt i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-03.ll b/test/CodeGen/SystemZ/int-cmp-03.ll new file mode 100644 index 000000000000..4203bee6ac44 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-03.ll @@ -0,0 +1,162 @@ +; Test 32-bit unsigned comparison in which the second operand is a variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register comparison. +define double @f1(double %a, double %b, i32 %i1, i32 %i2) { +; CHECK: f1: +; CHECK: clr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CL range. +define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) { +; CHECK: f2: +; CHECK: cl %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CL range. +define double @f3(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f3: +; CHECK: cl %r2, 4092(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1023 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which should use CLY instead of CL. +define double @f4(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f4: +; CHECK: cly %r2, 4096(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1024 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CLY range. +define double @f5(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f5: +; CHECK: cly %r2, 524284(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131071 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f6(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: cl %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131072 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CLY range. +define double @f7(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f7: +; CHECK: cly %r2, -4(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CLY range. +define double @f8(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f8: +; CHECK: cly %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131072 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f9(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: cl %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131073 + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CL allows an index. +define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLY allows an index. +define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) { +; CHECK: f11: +; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %i2 = load i32 *%ptr + %cond = icmp ult i32 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-04.ll b/test/CodeGen/SystemZ/int-cmp-04.ll new file mode 100644 index 000000000000..d0625fbddbae --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-04.ll @@ -0,0 +1,107 @@ +; Test 64-bit signed comparison in which the second operand is sign-extended +; from an i16 memory value. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check CGH with no displacement. +define void @f1(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f1: +; CHECK: cgh %r2, 0(%r3) +; CHECK: br %r14 + %half = load i16 *%src + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check the high end of the aligned CGH range. +define void @f2(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f2: +; CHECK: cgh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f3(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f3: +; CHECK: agfi %r3, 524288 +; CHECK: cgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check the high end of the negative aligned CGH range. +define void @f4(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f4: +; CHECK: cgh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check the low end of the CGH range. +define void @f5(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f5: +; CHECK: cgh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i64 %lhs, i16 *%src, i64 *%dst) { +; CHECK: f6: +; CHECK: agfi %r3, -524290 +; CHECK: cgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} + +; Check that CGH allows an index. +define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) { +; CHECK: f7: +; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i64 + %cond = icmp slt i64 %lhs, %rhs + %res = select i1 %cond, i64 100, i64 200 + store i64 %res, i64 *%dst + ret void +} diff --git a/test/CodeGen/SystemZ/int-cmp-05.ll b/test/CodeGen/SystemZ/int-cmp-05.ll new file mode 100644 index 000000000000..2ab64d5319a8 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-05.ll @@ -0,0 +1,203 @@ +; Test 64-bit comparison in which the second operand is a sign-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check signed register comparison. +define double @f1(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f1: +; CHECK: cgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned register comparison, which can't use CGFR. +define double @f2(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f2: +; CHECK-NOT: cgfr +; CHECK: br %r14 + %i2 = sext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check register equality. +define double @f3(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f3: +; CHECK: cgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = sext i32 %unext to i64 + %cond = icmp eq i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check register inequality. +define double @f4(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f4: +; CHECK: cgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = sext i32 %unext to i64 + %cond = icmp ne i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparisonn with memory. +define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f5: +; CHECK: cgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison with memory. +define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f6: +; CHECK-NOT: cgf +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check memory equality. +define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f7: +; CHECK: cgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp eq i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check memory inequality. +define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f8: +; CHECK: cgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp ne i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CGF range. +define double @f9(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f9: +; CHECK: cgf %r2, 524284(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131071 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f10(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f10: +; CHECK: agfi %r3, 524288 +; CHECK: cgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131072 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CGF range. +define double @f11(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f11: +; CHECK: cgf %r2, -4(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGF range. +define double @f12(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f12: +; CHECK: cgf %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131072 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f13(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f13: +; CHECK: agfi %r3, -524292 +; CHECK: cgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131073 + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CGF allows an index. +define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) { +; CHECK: f14: +; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %unext = load i32 *%ptr + %i2 = sext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-06.ll b/test/CodeGen/SystemZ/int-cmp-06.ll new file mode 100644 index 000000000000..26f6dbfe6f22 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-06.ll @@ -0,0 +1,253 @@ +; Test 64-bit comparison in which the second operand is a zero-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check unsigned register comparison. +define double @f1(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f1: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and again with a different representation. +define double @f2(double %a, double %b, i64 %i1, i64 %unext) { +; CHECK: f2: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = and i64 %unext, 4294967295 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed register comparison, which can't use CLGFR. +define double @f3(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f3: +; CHECK-NOT: clgfr +; CHECK: br %r14 + %i2 = zext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and again with a different representation +define double @f4(double %a, double %b, i64 %i1, i64 %unext) { +; CHECK: f4: +; CHECK-NOT: clgfr +; CHECK: br %r14 + %i2 = and i64 %unext, 4294967295 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check register equality. +define double @f5(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f5: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = zext i32 %unext to i64 + %cond = icmp eq i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and again with a different representation +define double @f6(double %a, double %b, i64 %i1, i64 %unext) { +; CHECK: f6: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = and i64 %unext, 4294967295 + %cond = icmp eq i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check register inequality. +define double @f7(double %a, double %b, i64 %i1, i32 %unext) { +; CHECK: f7: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = zext i32 %unext to i64 + %cond = icmp ne i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and again with a different representation +define double @f8(double %a, double %b, i64 %i1, i64 %unext) { +; CHECK: f8: +; CHECK: clgfr %r2, %r3 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = and i64 %unext, 4294967295 + %cond = icmp ne i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparisonn with memory. +define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f9: +; CHECK: clgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison with memory. +define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f10: +; CHECK-NOT: clgf +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check memory equality. +define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f11: +; CHECK: clgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp eq i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check memory inequality. +define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) { +; CHECK: f12: +; CHECK: clgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ne i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CLGF range. +define double @f13(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f13: +; CHECK: clgf %r2, 524284(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131071 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f14(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f14: +; CHECK: agfi %r3, 524288 +; CHECK: clgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 131072 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CLGF range. +define double @f15(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f15: +; CHECK: clgf %r2, -4(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CLGF range. +define double @f16(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f16: +; CHECK: clgf %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131072 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f17(double %a, double %b, i64 %i1, i32 *%base) { +; CHECK: f17: +; CHECK: agfi %r3, -524292 +; CHECK: clgf %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -131073 + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLGF allows an index. +define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) { +; CHECK: f18: +; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %unext = load i32 *%ptr + %i2 = zext i32 %unext to i64 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-07.ll b/test/CodeGen/SystemZ/int-cmp-07.ll new file mode 100644 index 000000000000..1a6f6226dd9f --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-07.ll @@ -0,0 +1,118 @@ +; Test 64-bit signed comparison in which the second operand is a variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check CGR. +define double @f1(double %a, double %b, i64 %i1, i64 %i2) { +; CHECK: f1: +; CHECK: cgr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check CG with no displacement. +define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { +; CHECK: f2: +; CHECK: cg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CG range. +define double @f3(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f3: +; CHECK: cg %r2, 524280(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65535 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: cg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65536 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CG range. +define double @f5(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f5: +; CHECK: cg %r2, -8(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -1 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CG range. +define double @f6(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f6: +; CHECK: cg %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65536 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f7(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: cg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65537 + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CG allows an index. +define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { +; CHECK: f8: +; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %i2 = load i64 *%ptr + %cond = icmp slt i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-08.ll b/test/CodeGen/SystemZ/int-cmp-08.ll new file mode 100644 index 000000000000..6e9a13e9cede --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-08.ll @@ -0,0 +1,118 @@ +; Test 64-bit unsigned comparison in which the second operand is a variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check CLGR. +define double @f1(double %a, double %b, i64 %i1, i64 %i2) { +; CHECK: f1: +; CHECK: clgr %r2, %r3 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check CLG with no displacement. +define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) { +; CHECK: f2: +; CHECK: clg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the aligned CLG range. +define double @f3(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f3: +; CHECK: clg %r2, 524280(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65535 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f4(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: clg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 65536 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative aligned CLG range. +define double @f5(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f5: +; CHECK: clg %r2, -8(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -1 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CLG range. +define double @f6(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f6: +; CHECK: clg %r2, -524288(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65536 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f7(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: clg %r2, 0(%r3) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -65537 + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLG allows an index. +define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) { +; CHECK: f8: +; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %i2 = load i64 *%ptr + %cond = icmp ult i64 %i1, %i2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-09.ll b/test/CodeGen/SystemZ/int-cmp-09.ll new file mode 100644 index 000000000000..bb7213c6a436 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-09.ll @@ -0,0 +1,135 @@ +; Test 32-bit signed comparison in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparisons with 0. +define double @f1(double %a, double %b, i32 %i1) { +; CHECK: f1: +; CHECK: chi %r2, 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 1. +define double @f2(double %a, double %b, i32 %i1) { +; CHECK: f2: +; CHECK: chi %r2, 1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CHI range. +define double @f3(double %a, double %b, i32 %i1) { +; CHECK: f3: +; CHECK: chi %r2, 32767 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use CFI. +define double @f4(double %a, double %b, i32 %i1) { +; CHECK: f4: +; CHECK: cfi %r2, 32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 32-bit range. +define double @f5(double %a, double %b, i32 %i1) { +; CHECK: f5: +; CHECK: cfi %r2, 2147483647 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i32 %i1, 2147483647 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which should be treated as a negative value. +define double @f6(double %a, double %b, i32 %i1) { +; CHECK: f6: +; CHECK: cfi %r2, -2147483648 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i32 %i1, 2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative CHI range. +define double @f7(double %a, double %b, i32 %i1) { +; CHECK: f7: +; CHECK: chi %r2, -1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CHI range. +define double @f8(double %a, double %b, i32 %i1) { +; CHECK: f8: +; CHECK: chi %r2, -32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use CFI instead. +define double @f9(double %a, double %b, i32 %i1) { +; CHECK: f9: +; CHECK: cfi %r2, -32769 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i32 %i1, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 32-bit range. +define double @f10(double %a, double %b, i32 %i1) { +; CHECK: f10: +; CHECK: cfi %r2, -2147483648 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i32 %i1, -2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which should be treated as a positive value. +define double @f11(double %a, double %b, i32 %i1) { +; CHECK: f11: +; CHECK: cfi %r2, 2147483647 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i32 %i1, -2147483649 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-10.ll b/test/CodeGen/SystemZ/int-cmp-10.ll new file mode 100644 index 000000000000..f2d3ccd64af6 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-10.ll @@ -0,0 +1,28 @@ +; Test 32-bit unsigned comparisons in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check a value near the low end of the range. We use CFI for comparisons +; with zero, or things that are equivalent to them. +define double @f1(double %a, double %b, i32 %i1) { +; CHECK: f1: +; CHECK: clfi %r2, 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ugt i32 %i1, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check a value near the high end of the range. +define double @f2(double %a, double %b, i32 %i1) { +; CHECK: f2: +; CHECK: clfi %r2, 4294967280 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i32 %i1, 4294967280 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-11.ll b/test/CodeGen/SystemZ/int-cmp-11.ll new file mode 100644 index 000000000000..1bfb0c61cb90 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-11.ll @@ -0,0 +1,135 @@ +; Test 64-bit signed comparisons in which the second operand is a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparisons with 0. +define double @f1(double %a, double %b, i64 %i1) { +; CHECK: f1: +; CHECK: cghi %r2, 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 1. +define double @f2(double %a, double %b, i64 %i1) { +; CHECK: f2: +; CHECK: cghi %r2, 1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGHI range. +define double @f3(double %a, double %b, i64 %i1) { +; CHECK: f3: +; CHECK: cghi %r2, 32767 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use CGFI. +define double @f4(double %a, double %b, i64 %i1) { +; CHECK: f4: +; CHECK: cgfi %r2, 32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGFI range. +define double @f5(double %a, double %b, i64 %i1) { +; CHECK: f5: +; CHECK: cgfi %r2, 2147483647 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 2147483647 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use register comparison. +define double @f6(double %a, double %b, i64 %i1) { +; CHECK: f6: +; CHECK: cgr +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, 2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative CGHI range. +define double @f7(double %a, double %b, i64 %i1) { +; CHECK: f7: +; CHECK: cghi %r2, -1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGHI range. +define double @f8(double %a, double %b, i64 %i1) { +; CHECK: f8: +; CHECK: cghi %r2, -32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use CGFI instead. +define double @f9(double %a, double %b, i64 %i1) { +; CHECK: f9: +; CHECK: cgfi %r2, -32769 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGFI range. +define double @f10(double %a, double %b, i64 %i1) { +; CHECK: f10: +; CHECK: cgfi %r2, -2147483648 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, -2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use register comparison. +define double @f11(double %a, double %b, i64 %i1) { +; CHECK: f11: +; CHECK: cgr +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp slt i64 %i1, -2147483649 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-12.ll b/test/CodeGen/SystemZ/int-cmp-12.ll new file mode 100644 index 000000000000..0288730c3a80 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-12.ll @@ -0,0 +1,40 @@ +; Test 64-bit unsigned comparisons in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check a value near the low end of the range. We use CGFI for comparisons +; with zero, or things that are equivalent to them. +define double @f1(double %a, double %b, i64 %i1) { +; CHECK: f1: +; CHECK: clgfi %r2, 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ugt i64 %i1, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLGFI range. +define double @f2(double %a, double %b, i64 %i1) { +; CHECK: f2: +; CHECK: clgfi %r2, 4294967295 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i64 %i1, 4294967295 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use a register comparison. +define double @f3(double %a, double %b, i64 %i1) { +; CHECK: f3: +; CHECK: clgr %r2, +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ult i64 %i1, 4294967296 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-13.ll b/test/CodeGen/SystemZ/int-cmp-13.ll new file mode 100644 index 000000000000..c180831debb0 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-13.ll @@ -0,0 +1,147 @@ +; Test 64-bit equality comparisons in which the second operand is a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparisons with 0. +define double @f1(double %a, double %b, i64 %i1) { +; CHECK: f1: +; CHECK: cghi %r2, 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGHI range. +define double @f2(double %a, double %b, i64 %i1) { +; CHECK: f2: +; CHECK: cghi %r2, 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use CGFI. +define double @f3(double %a, double %b, i64 %i1) { +; CHECK: f3: +; CHECK: cgfi %r2, 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGFI range. +define double @f4(double %a, double %b, i64 %i1) { +; CHECK: f4: +; CHECK: cgfi %r2, 2147483647 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 2147483647 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which should use CLGFI instead. +define double @f5(double %a, double %b, i64 %i1) { +; CHECK: f5: +; CHECK: clgfi %r2, 2147483648 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLGFI range. +define double @f6(double %a, double %b, i64 %i1) { +; CHECK: f6: +; CHECK: clgfi %r2, 4294967295 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 4294967295 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use a register comparison. +define double @f7(double %a, double %b, i64 %i1) { +; CHECK: f7: +; CHECK: cgr %r2, +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, 4294967296 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative CGHI range. +define double @f8(double %a, double %b, i64 %i1) { +; CHECK: f8: +; CHECK: cghi %r2, -1 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGHI range. +define double @f9(double %a, double %b, i64 %i1) { +; CHECK: f9: +; CHECK: cghi %r2, -32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use CGFI instead. +define double @f10(double %a, double %b, i64 %i1) { +; CHECK: f10: +; CHECK: cgfi %r2, -32769 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGFI range. +define double @f11(double %a, double %b, i64 %i1) { +; CHECK: f11: +; CHECK: cgfi %r2, -2147483648 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, -2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use register comparison. +define double @f12(double %a, double %b, i64 %i1) { +; CHECK: f12: +; CHECK: cgr +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp eq i64 %i1, -2147483649 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-14.ll b/test/CodeGen/SystemZ/int-cmp-14.ll new file mode 100644 index 000000000000..6a7e0e6d552a --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-14.ll @@ -0,0 +1,147 @@ +; Test 64-bit inequality comparisons in which the second operand is a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparisons with 0. +define double @f1(double %a, double %b, i64 %i1) { +; CHECK: f1: +; CHECK: cghi %r2, 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGHI range. +define double @f2(double %a, double %b, i64 %i1) { +; CHECK: f2: +; CHECK: cghi %r2, 32767 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use CGFI. +define double @f3(double %a, double %b, i64 %i1) { +; CHECK: f3: +; CHECK: cgfi %r2, 32768 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGFI range. +define double @f4(double %a, double %b, i64 %i1) { +; CHECK: f4: +; CHECK: cgfi %r2, 2147483647 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 2147483647 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which should use CLGFI instead. +define double @f5(double %a, double %b, i64 %i1) { +; CHECK: f5: +; CHECK: clgfi %r2, 2147483648 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLGFI range. +define double @f6(double %a, double %b, i64 %i1) { +; CHECK: f6: +; CHECK: clgfi %r2, 4294967295 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 4294967295 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which must use a register comparison. +define double @f7(double %a, double %b, i64 %i1) { +; CHECK: f7: +; CHECK: cgr %r2, +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, 4294967296 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative CGHI range. +define double @f8(double %a, double %b, i64 %i1) { +; CHECK: f8: +; CHECK: cghi %r2, -1 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGHI range. +define double @f9(double %a, double %b, i64 %i1) { +; CHECK: f9: +; CHECK: cghi %r2, -32768 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use CGFI instead. +define double @f10(double %a, double %b, i64 %i1) { +; CHECK: f10: +; CHECK: cgfi %r2, -32769 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CGFI range. +define double @f11(double %a, double %b, i64 %i1) { +; CHECK: f11: +; CHECK: cgfi %r2, -2147483648 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, -2147483648 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which must use register comparison. +define double @f12(double %a, double %b, i64 %i1) { +; CHECK: f12: +; CHECK: cgr +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %cond = icmp ne i64 %i1, -2147483649 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-15.ll b/test/CodeGen/SystemZ/int-cmp-15.ll new file mode 100644 index 000000000000..6bb7e2b3ac3d --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-15.ll @@ -0,0 +1,241 @@ +; Test 8-bit unsigned comparisons between memory and constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ordered comparisons near the low end of the unsigned 8-bit range. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp ugt i8 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons near the high end of the unsigned 8-bit range. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 254 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for negative bytes. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp slt i8 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and an alternative form. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp sle i8 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for non-negative bytes. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp sge i8 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and an alternative form. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp sgt i8 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons at the low end of the signed 8-bit range. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp eq i8 %val, -128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons at the low end of the unsigned 8-bit range. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp eq i8 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons at the high end of the signed 8-bit range. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp eq i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons at the high end of the unsigned 8-bit range. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %cond = icmp eq i8 %val, 255 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLI range. +define double @f11(double %a, double %b, i8 *%src) { +; CHECK: f11: +; CHECK: cli 4095(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next byte up, which should use CLIY instead of CLI. +define double @f12(double %a, double %b, i8 *%src) { +; CHECK: f12: +; CHECK: cliy 4096(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLIY range. +define double @f13(double %a, double %b, i8 *%src) { +; CHECK: f13: +; CHECK: cliy 524287(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f14(double %a, double %b, i8 *%src) { +; CHECK: f14: +; CHECK: agfi %r2, 524288 +; CHECK: cli 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the negative CLIY range. +define double @f15(double %a, double %b, i8 *%src) { +; CHECK: f15: +; CHECK: cliy -1(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the CLIY range. +define double @f16(double %a, double %b, i8 *%src) { +; CHECK: f16: +; CHECK: cliy -524288(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define double @f17(double %a, double %b, i8 *%src) { +; CHECK: f17: +; CHECK: agfi %r2, -524289 +; CHECK: cli 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLI does not allow an index +define double @f18(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f18: +; CHECK: agr %r2, %r3 +; CHECK: cli 4095(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLIY does not allow an index +define double @f19(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f19: +; CHECK: agr %r2, %r3 +; CHECK: cliy 4096(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %base, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %cond = icmp ult i8 %val, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-16.ll b/test/CodeGen/SystemZ/int-cmp-16.ll new file mode 100644 index 000000000000..8af854efaabf --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-16.ll @@ -0,0 +1,133 @@ +; Test 32-bit equality comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 8-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp eq i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 8-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp eq i32 %ext, 255 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp eq i32 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp eq i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 8-bit range, using sign extension. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 8-bit range, using sign extension. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, -128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp eq i32 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-17.ll b/test/CodeGen/SystemZ/int-cmp-17.ll new file mode 100644 index 000000000000..d4d5e98b8358 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-17.ll @@ -0,0 +1,133 @@ +; Test 32-bit inequality comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 8-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ne i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 8-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ne i32 %ext, 255 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ne i32 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ne i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 8-bit range, using sign extension. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 8-bit range, using sign extension. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, -128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ne i32 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-18.ll b/test/CodeGen/SystemZ/int-cmp-18.ll new file mode 100644 index 000000000000..9822dc212248 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-18.ll @@ -0,0 +1,133 @@ +; Test 64-bit equality comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 8-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp eq i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 8-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp eq i64 %ext, 255 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp eq i64 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp eq i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 8-bit range, using sign extension. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 8-bit range, using sign extension. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, -128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp eq i64 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-19.ll b/test/CodeGen/SystemZ/int-cmp-19.ll new file mode 100644 index 000000000000..7d29dbcedcd6 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-19.ll @@ -0,0 +1,133 @@ +; Test 64-bit inequality comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 8-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ne i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 8-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ne i64 %ext, 255 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ne i64 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ne i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK: cli 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 8-bit range, using sign extension. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, 127 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 255 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 8-bit range, using sign extension. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, -128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ne i64 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-20.ll b/test/CodeGen/SystemZ/int-cmp-20.ll new file mode 100644 index 000000000000..8fffbc86a737 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-20.ll @@ -0,0 +1,220 @@ +; Test 32-bit ordered comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check unsigned comparison near the low end of the CLI range, using zero +; extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ugt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the low end of the CLI range, using sign +; extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ugt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLI range, using zero +; extension. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ult i32 %ext, 254 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLI range, using sign +; extension. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ult i32 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison above the high end of the CLI range, using zero +; extension. The condition is always true. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp ult i32 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; When using unsigned comparison with sign extension, equality with values +; in the range [128, MAX-129] is impossible, and ordered comparisons with +; those values are effectively sign tests. Since such comparisons are +; unlikely to occur in practice, we don't bother optimizing the second case, +; and simply ignore CLI for this range. First check the low end of the range. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ult i32 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and then the high end. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp ult i32 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp sgt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLI range, using sign +; extension. This cannot use CLI. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp sgt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp slt i32 %ext, 254 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLI range, using sign +; extension. This cannot use CLI. +define double @f11(double %a, double %b, i8 *%ptr) { +; CHECK: f11: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp slt i32 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CLI range, using zero +; extension. The condition is always true. +define double @f12(double %a, double %b, i8 *%ptr) { +; CHECK: f12: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %cond = icmp slt i32 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for nonnegative values. +define double @f13(double %a, double %b, i8 *%ptr) { +; CHECK: f13: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp sge i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and another form +define double @f14(double %a, double %b, i8 *%ptr) { +; CHECK: f14: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp sgt i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for negative values. +define double @f15(double %a, double %b, i8 *%ptr) { +; CHECK: f15: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp slt i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and another form +define double @f16(double %a, double %b, i8 *%ptr) { +; CHECK: f16: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %cond = icmp sle i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-21.ll b/test/CodeGen/SystemZ/int-cmp-21.ll new file mode 100644 index 000000000000..43447b8fda07 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-21.ll @@ -0,0 +1,220 @@ +; Test 64-bit ordered comparisons that are really between a memory byte +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check unsigned comparison near the low end of the CLI range, using zero +; extension. +define double @f1(double %a, double %b, i8 *%ptr) { +; CHECK: f1: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ugt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the low end of the CLI range, using sign +; extension. +define double @f2(double %a, double %b, i8 *%ptr) { +; CHECK: f2: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ugt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLI range, using zero +; extension. +define double @f3(double %a, double %b, i8 *%ptr) { +; CHECK: f3: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ult i64 %ext, 254 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLI range, using sign +; extension. +define double @f4(double %a, double %b, i8 *%ptr) { +; CHECK: f4: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ult i64 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison above the high end of the CLI range, using zero +; extension. The condition is always true. +define double @f5(double %a, double %b, i8 *%ptr) { +; CHECK: f5: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp ult i64 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; When using unsigned comparison with sign extension, equality with values +; in the range [128, MAX-129] is impossible, and ordered comparisons with +; those values are effectively sign tests. Since such comparisons are +; unlikely to occur in practice, we don't bother optimizing the second case, +; and simply ignore CLI for this range. First check the low end of the range. +define double @f6(double %a, double %b, i8 *%ptr) { +; CHECK: f6: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ult i64 %ext, 128 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and then the high end. +define double @f7(double %a, double %b, i8 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp ult i64 %ext, -129 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f8(double %a, double %b, i8 *%ptr) { +; CHECK: f8: +; CHECK: cli 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp sgt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLI range, using sign +; extension. This cannot use CLI. +define double @f9(double %a, double %b, i8 *%ptr) { +; CHECK: f9: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp sgt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f10(double %a, double %b, i8 *%ptr) { +; CHECK: f10: +; CHECK: cli 0(%r2), 254 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp slt i64 %ext, 254 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLI range, using sign +; extension. This cannot use CLI. +define double @f11(double %a, double %b, i8 *%ptr) { +; CHECK: f11: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp slt i64 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CLI range, using zero +; extension. The condition is always true. +define double @f12(double %a, double %b, i8 *%ptr) { +; CHECK: f12: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %cond = icmp slt i64 %ext, 256 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for nonnegative values. +define double @f13(double %a, double %b, i8 *%ptr) { +; CHECK: f13: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp sge i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and another form +define double @f14(double %a, double %b, i8 *%ptr) { +; CHECK: f14: +; CHECK: cli 0(%r2), 128 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp sgt i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check tests for negative values. +define double @f15(double %a, double %b, i8 *%ptr) { +; CHECK: f15: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp slt i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and another form +define double @f16(double %a, double %b, i8 *%ptr) { +; CHECK: f16: +; CHECK: cli 0(%r2), 127 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %cond = icmp sle i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-22.ll b/test/CodeGen/SystemZ/int-cmp-22.ll new file mode 100644 index 000000000000..513d4be2f423 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-22.ll @@ -0,0 +1,128 @@ +; Test 16-bit signed ordered comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check comparisons with 0. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: chhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 1. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: chhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check a value near the high end of the signed 16-bit range. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK: chhsi 0(%r2), 32766 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 32766 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK: chhsi 0(%r2), -1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check a value near the low end of the 16-bit signed range. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK: chhsi 0(%r2), -32766 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, -32766 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CHHSI range. +define double @f6(double %a, double %b, i16 %i1, i16 *%base) { +; CHECK: f6: +; CHECK: chhsi 4094(%r3), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 2047 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next halfword up, which needs separate address logic, +define double @f7(double %a, double %b, i16 *%base) { +; CHECK: f7: +; CHECK: aghi %r2, 4096 +; CHECK: chhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 2048 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f8(double %a, double %b, i16 *%base) { +; CHECK: f8: +; CHECK: aghi %r2, -2 +; CHECK: chhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 -1 + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CHHSI does not allow indices. +define double @f9(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f9: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: chhsi 0({{%r[23]}}), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i16 * + %val = load i16 *%ptr + %cond = icmp slt i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-23.ll b/test/CodeGen/SystemZ/int-cmp-23.ll new file mode 100644 index 000000000000..40e13310d55c --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-23.ll @@ -0,0 +1,89 @@ +; Test 16-bit unsigned comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check a value near the low end of the unsigned 16-bit range. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ugt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check a value near the high end of the unsigned 16-bit range. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ult i16 %val, 65534 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLHHSI range. +define double @f3(double %a, double %b, i16 %i1, i16 *%base) { +; CHECK: f3: +; CHECK: clhhsi 4094(%r3), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 2047 + %val = load i16 *%ptr + %cond = icmp ugt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next halfword up, which needs separate address logic, +define double @f4(double %a, double %b, i16 *%base) { +; CHECK: f4: +; CHECK: aghi %r2, 4096 +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 2048 + %val = load i16 *%ptr + %cond = icmp ugt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f5(double %a, double %b, i16 *%base) { +; CHECK: f5: +; CHECK: aghi %r2, -2 +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i16 *%base, i64 -1 + %val = load i16 *%ptr + %cond = icmp ugt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLHHSI does not allow indices. +define double @f6(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f6: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: clhhsi 0({{%r[23]}}), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i16 * + %val = load i16 *%ptr + %cond = icmp ugt i16 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-24.ll b/test/CodeGen/SystemZ/int-cmp-24.ll new file mode 100644 index 000000000000..46186cd74b53 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-24.ll @@ -0,0 +1,55 @@ +; Test 16-bit equality comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the unsigned 16-bit range. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp eq i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the unsigned 16-bit range. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp eq i16 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp eq i16 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp eq i16 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-25.ll b/test/CodeGen/SystemZ/int-cmp-25.ll new file mode 100644 index 000000000000..a3a223fa3448 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-25.ll @@ -0,0 +1,55 @@ +; Test 16-bit inequality comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the unsigned 16-bit range. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ne i16 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the unsigned 16-bit range. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ne i16 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ne i16 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}lh +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i16 *%ptr + %cond = icmp ne i16 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-26.ll b/test/CodeGen/SystemZ/int-cmp-26.ll new file mode 100644 index 000000000000..31330b2a6397 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-26.ll @@ -0,0 +1,133 @@ +; Test 32-bit equality comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 16-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp eq i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 16-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp eq i32 %ext, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp eq i32 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp eq i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range, using sign extension. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range, using sign extension. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp eq i32 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-27.ll b/test/CodeGen/SystemZ/int-cmp-27.ll new file mode 100644 index 000000000000..7cbea3d92526 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-27.ll @@ -0,0 +1,133 @@ +; Test 32-bit inequality comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 16-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ne i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 16-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ne i32 %ext, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ne i32 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ne i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range, using sign extension. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range, using sign extension. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ne i32 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-28.ll b/test/CodeGen/SystemZ/int-cmp-28.ll new file mode 100644 index 000000000000..629eb4f06013 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-28.ll @@ -0,0 +1,133 @@ +; Test 64-bit equality comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 16-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp eq i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 16-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp eq i64 %ext, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp eq i64 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp eq i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range, using sign extension. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range, using sign extension. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp eq i64 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-29.ll b/test/CodeGen/SystemZ/int-cmp-29.ll new file mode 100644 index 000000000000..de41dd782d21 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-29.ll @@ -0,0 +1,133 @@ +; Test 64-bit inequality comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the 16-bit unsigned range, with zero extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ne i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the 16-bit unsigned range, with zero extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ne i64 %ext, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, with zero extension. The condition is always false. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ne i64 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, with zero extension. +; This condition is also always false. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ne i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with 0, using sign extension. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK: clhhsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the signed 16-bit range, using sign extension. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK: clhhsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, using sign extension. +; The condition is always false. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check comparisons with -1, using sign extension. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the low end of the signed 16-bit range, using sign extension. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: clhhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, using sign extension. +; The condition is always false. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ne i64 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-30.ll b/test/CodeGen/SystemZ/int-cmp-30.ll new file mode 100644 index 000000000000..713ad8ef841d --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-30.ll @@ -0,0 +1,225 @@ +; Test 32-bit ordered comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check unsigned comparison near the low end of the CLHHSI range, using zero +; extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ugt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the low end of the CLHHSI range, using sign +; extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ugt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLHHSI range, using zero +; extension. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ult i32 %ext, 65534 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLHHSI range, using sign +; extension. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ult i32 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison above the high end of the CLHHSI range, using zero +; extension. The condition is always true. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp ult i32 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; When using unsigned comparison with sign extension, equality with values +; in the range [32768, MAX-32769] is impossible, and ordered comparisons with +; those values are effectively sign tests. Since such comparisons are +; unlikely to occur in practice, we don't bother optimizing the second case, +; and simply ignore CLHHSI for this range. First check the low end of the +; range. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ult i32 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and then the high end. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp ult i32 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLHHSI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp sgt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLHHSI range, using sign +; extension. This should use CHHSI instead. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: chhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp sgt i32 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLHHSI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp slt i32 %ext, 65534 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLHHSI range, using sign +; extension. This should use CHHSI instead. +define double @f11(double %a, double %b, i16 *%ptr) { +; CHECK: f11: +; CHECK: chhsi 0(%r2), -2 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp slt i32 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CLHHSI range, using zero +; extension. The condition is always true. +define double @f12(double %a, double %b, i16 *%ptr) { +; CHECK: f12: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i32 + %cond = icmp slt i32 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CHHSI range, using sign +; extension. +define double @f13(double %a, double %b, i16 *%ptr) { +; CHECK: f13: +; CHECK: chhsi 0(%r2), 32766 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp slt i32 %ext, 32766 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CHHSI range, using sign +; extension. This condition is always true. +define double @f14(double %a, double %b, i16 *%ptr) { +; CHECK: f14: +; CHECK-NOT: chhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp slt i32 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CHHSI range, using sign +; extension. +define double @f15(double %a, double %b, i16 *%ptr) { +; CHECK: f15: +; CHECK: chhsi 0(%r2), -32767 +; CHECK-NEXT: j{{g?}}g +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp sgt i32 %ext, -32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison below the low end of the CHHSI range, using sign +; extension. This condition is always true. +define double @f16(double %a, double %b, i16 *%ptr) { +; CHECK: f16: +; CHECK-NOT: chhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i32 + %cond = icmp sgt i32 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-31.ll b/test/CodeGen/SystemZ/int-cmp-31.ll new file mode 100644 index 000000000000..cabe9b83a135 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-31.ll @@ -0,0 +1,225 @@ +; Test 64-bit ordered comparisons that are really between a memory halfword +; and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check unsigned comparison near the low end of the CLHHSI range, using zero +; extension. +define double @f1(double %a, double %b, i16 *%ptr) { +; CHECK: f1: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ugt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the low end of the CLHHSI range, using sign +; extension. +define double @f2(double %a, double %b, i16 *%ptr) { +; CHECK: f2: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ugt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLHHSI range, using zero +; extension. +define double @f3(double %a, double %b, i16 *%ptr) { +; CHECK: f3: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ult i64 %ext, 65534 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison near the high end of the CLHHSI range, using sign +; extension. +define double @f4(double %a, double %b, i16 *%ptr) { +; CHECK: f4: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ult i64 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check unsigned comparison above the high end of the CLHHSI range, using zero +; extension. The condition is always true. +define double @f5(double %a, double %b, i16 *%ptr) { +; CHECK: f5: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp ult i64 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; When using unsigned comparison with sign extension, equality with values +; in the range [32768, MAX-32769] is impossible, and ordered comparisons with +; those values are effectively sign tests. Since such comparisons are +; unlikely to occur in practice, we don't bother optimizing the second case, +; and simply ignore CLHHSI for this range. First check the low end of the +; range. +define double @f6(double %a, double %b, i16 *%ptr) { +; CHECK: f6: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ult i64 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; ...and then the high end. +define double @f7(double %a, double %b, i16 *%ptr) { +; CHECK: f7: +; CHECK-NOT: clhhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp ult i64 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLHHSI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f8(double %a, double %b, i16 *%ptr) { +; CHECK: f8: +; CHECK: clhhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp sgt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CLHHSI range, using sign +; extension. This should use CHHSI instead. +define double @f9(double %a, double %b, i16 *%ptr) { +; CHECK: f9: +; CHECK: chhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp sgt i64 %ext, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLHHSI range, using zero +; extension. This is equivalent to unsigned comparison. +define double @f10(double %a, double %b, i16 *%ptr) { +; CHECK: f10: +; CHECK: clhhsi 0(%r2), 65534 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp slt i64 %ext, 65534 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CLHHSI range, using sign +; extension. This should use CHHSI instead. +define double @f11(double %a, double %b, i16 *%ptr) { +; CHECK: f11: +; CHECK: chhsi 0(%r2), -2 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp slt i64 %ext, -2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CLHHSI range, using zero +; extension. The condition is always true. +define double @f12(double %a, double %b, i16 *%ptr) { +; CHECK: f12: +; CHECK-NOT: cli +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = zext i16 %val to i64 + %cond = icmp slt i64 %ext, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the high end of the CHHSI range, using sign +; extension. +define double @f13(double %a, double %b, i16 *%ptr) { +; CHECK: f13: +; CHECK: chhsi 0(%r2), 32766 +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp slt i64 %ext, 32766 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison above the high end of the CHHSI range, using sign +; extension. This condition is always true. +define double @f14(double %a, double %b, i16 *%ptr) { +; CHECK: f14: +; CHECK-NOT: chhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp slt i64 %ext, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison near the low end of the CHHSI range, using sign +; extension. +define double @f15(double %a, double %b, i16 *%ptr) { +; CHECK: f15: +; CHECK: chhsi 0(%r2), -32767 +; CHECK-NEXT: j{{g?}}g +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp sgt i64 %ext, -32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check signed comparison below the low end of the CHHSI range, using sign +; extension. This condition is always true. +define double @f16(double %a, double %b, i16 *%ptr) { +; CHECK: f16: +; CHECK-NOT: chhsi +; CHECK: br %r14 + %val = load i16 *%ptr + %ext = sext i16 %val to i64 + %cond = icmp sgt i64 %ext, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-32.ll b/test/CodeGen/SystemZ/int-cmp-32.ll new file mode 100644 index 000000000000..4bdeebb35c99 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-32.ll @@ -0,0 +1,237 @@ +; Test 32-bit signed comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ordered comparisons with 0. +define double @f1(double %a, double %b, i32 *%ptr) { +; CHECK: f1: +; CHECK: chsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with 1. +define double @f2(double %a, double %b, i32 *%ptr) { +; CHECK: f2: +; CHECK: chsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the high end of the signed 16-bit range. +define double @f3(double %a, double %b, i32 *%ptr) { +; CHECK: f3: +; CHECK: chsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CHSI. +define double @f4(double %a, double %b, i32 *%ptr) { +; CHECK: f4: +; CHECK-NOT: chsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with -1. +define double @f5(double %a, double %b, i32 *%ptr) { +; CHECK: f5: +; CHECK: chsi 0(%r2), -1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the low end of the 16-bit signed range. +define double @f6(double %a, double %b, i32 *%ptr) { +; CHECK: f6: +; CHECK: chsi 0(%r2), -32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which can't use CHSI. +define double @f7(double %a, double %b, i32 *%ptr) { +; CHECK: f7: +; CHECK-NOT: chsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 0. +define double @f8(double %a, double %b, i32 *%ptr) { +; CHECK: f8: +; CHECK: chsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 1. +define double @f9(double %a, double %b, i32 *%ptr) { +; CHECK: f9: +; CHECK: chsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the high end of the signed 16-bit range. +define double @f10(double %a, double %b, i32 *%ptr) { +; CHECK: f10: +; CHECK: chsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CHSI. +define double @f11(double %a, double %b, i32 *%ptr) { +; CHECK: f11: +; CHECK-NOT: chsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with -1. +define double @f12(double %a, double %b, i32 *%ptr) { +; CHECK: f12: +; CHECK: chsi 0(%r2), -1 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the low end of the 16-bit signed range. +define double @f13(double %a, double %b, i32 *%ptr) { +; CHECK: f13: +; CHECK: chsi 0(%r2), -32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which should be treated as a positive value. +define double @f14(double %a, double %b, i32 *%ptr) { +; CHECK: f14: +; CHECK-NOT: chsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CHSI range. +define double @f15(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f15: +; CHECK: chsi 4092(%r3), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1023 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic, +define double @f16(double %a, double %b, i32 *%base) { +; CHECK: f16: +; CHECK: aghi %r2, 4096 +; CHECK: chsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1024 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f17(double %a, double %b, i32 *%base) { +; CHECK: f17: +; CHECK: aghi %r2, -4 +; CHECK: chsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CHSI does not allow indices. +define double @f18(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f18: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: chsi 0({{%r[23]}}), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i32 * + %val = load i32 *%ptr + %cond = icmp slt i32 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-33.ll b/test/CodeGen/SystemZ/int-cmp-33.ll new file mode 100644 index 000000000000..0144806d4465 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-33.ll @@ -0,0 +1,139 @@ +; Test 32-bit unsigned comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ordered comparisons with a constant near the low end of the unsigned +; 16-bit range. +define double @f1(double %a, double %b, i32 *%ptr) { +; CHECK: f1: +; CHECK: clfhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp ugt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the high end of the unsigned 16-bit range. +define double @f2(double %a, double %b, i32 *%ptr) { +; CHECK: f2: +; CHECK: clfhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp ult i32 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CLFHSI. +define double @f3(double %a, double %b, i32 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clfhsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp ult i32 %val, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 32768, the lowest value for which +; we prefer CLFHSI to CHSI. +define double @f4(double %a, double %b, i32 *%ptr) { +; CHECK: f4: +; CHECK: clfhsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the high end of the unsigned 16-bit range. +define double @f5(double %a, double %b, i32 *%ptr) { +; CHECK: f5: +; CHECK: clfhsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CLFHSI. +define double @f6(double %a, double %b, i32 *%ptr) { +; CHECK: f6: +; CHECK-NOT: clfhsi +; CHECK: br %r14 + %val = load i32 *%ptr + %cond = icmp eq i32 %val, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLFHSI range. +define double @f7(double %a, double %b, i32 %i1, i32 *%base) { +; CHECK: f7: +; CHECK: clfhsi 4092(%r3), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1023 + %val = load i32 *%ptr + %cond = icmp ugt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next word up, which needs separate address logic, +define double @f8(double %a, double %b, i32 *%base) { +; CHECK: f8: +; CHECK: aghi %r2, 4096 +; CHECK: clfhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 1024 + %val = load i32 *%ptr + %cond = icmp ugt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f9(double %a, double %b, i32 *%base) { +; CHECK: f9: +; CHECK: aghi %r2, -4 +; CHECK: clfhsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i32 *%base, i64 -1 + %val = load i32 *%ptr + %cond = icmp ugt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLFHSI does not allow indices. +define double @f10(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: clfhsi 0({{%r[23]}}), 1 +; CHECK-NEXT: j{{g?}}h +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i32 * + %val = load i32 *%ptr + %cond = icmp ugt i32 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-34.ll b/test/CodeGen/SystemZ/int-cmp-34.ll new file mode 100644 index 000000000000..b10bd4e08031 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-34.ll @@ -0,0 +1,237 @@ +; Test 64-bit signed comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ordered comparisons with 0. +define double @f1(double %a, double %b, i64 *%ptr) { +; CHECK: f1: +; CHECK: cghsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with 1. +define double @f2(double %a, double %b, i64 *%ptr) { +; CHECK: f2: +; CHECK: cghsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the high end of the signed 16-bit range. +define double @f3(double %a, double %b, i64 *%ptr) { +; CHECK: f3: +; CHECK: cghsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CGHSI. +define double @f4(double %a, double %b, i64 *%ptr) { +; CHECK: f4: +; CHECK-NOT: cghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with -1. +define double @f5(double %a, double %b, i64 *%ptr) { +; CHECK: f5: +; CHECK: cghsi 0(%r2), -1 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the low end of the 16-bit signed range. +define double @f6(double %a, double %b, i64 *%ptr) { +; CHECK: f6: +; CHECK: cghsi 0(%r2), -32768 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which should be treated as a positive value. +define double @f7(double %a, double %b, i64 *%ptr) { +; CHECK: f7: +; CHECK-NOT: cghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 0. +define double @f8(double %a, double %b, i64 *%ptr) { +; CHECK: f8: +; CHECK: cghsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 1. +define double @f9(double %a, double %b, i64 *%ptr) { +; CHECK: f9: +; CHECK: cghsi 0(%r2), 1 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the high end of the signed 16-bit range. +define double @f10(double %a, double %b, i64 *%ptr) { +; CHECK: f10: +; CHECK: cghsi 0(%r2), 32767 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 32767 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CGHSI. +define double @f11(double %a, double %b, i64 *%ptr) { +; CHECK: f11: +; CHECK-NOT: cghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with -1. +define double @f12(double %a, double %b, i64 *%ptr) { +; CHECK: f12: +; CHECK: cghsi 0(%r2), -1 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, -1 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the low end of the 16-bit signed range. +define double @f13(double %a, double %b, i64 *%ptr) { +; CHECK: f13: +; CHECK: cghsi 0(%r2), -32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, -32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value down, which should be treated as a positive value. +define double @f14(double %a, double %b, i64 *%ptr) { +; CHECK: f14: +; CHECK-NOT: cghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, -32769 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CGHSI range. +define double @f15(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f15: +; CHECK: cghsi 4088(%r3), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 511 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword up, which needs separate address logic, +define double @f16(double %a, double %b, i64 *%base) { +; CHECK: f16: +; CHECK: aghi %r2, 4096 +; CHECK: cghsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 512 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f17(double %a, double %b, i64 *%base) { +; CHECK: f17: +; CHECK: aghi %r2, -8 +; CHECK: cghsi 0(%r2), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -1 + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CGHSI does not allow indices. +define double @f18(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f18: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: cghsi 0({{%r[23]}}), 0 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i64 * + %val = load i64 *%ptr + %cond = icmp slt i64 %val, 0 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-35.ll b/test/CodeGen/SystemZ/int-cmp-35.ll new file mode 100644 index 000000000000..9934906ba8d4 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-35.ll @@ -0,0 +1,139 @@ +; Test 64-bit unsigned comparisons between memory and a constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check ordered comparisons with a constant near the low end of the unsigned +; 16-bit range. +define double @f1(double %a, double %b, i64 *%ptr) { +; CHECK: f1: +; CHECK: clghsi 0(%r2), 2 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check ordered comparisons with the high end of the unsigned 16-bit range. +define double @f2(double %a, double %b, i64 *%ptr) { +; CHECK: f2: +; CHECK: clghsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CLGHSI. +define double @f3(double %a, double %b, i64 *%ptr) { +; CHECK: f3: +; CHECK-NOT: clghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with 32768, the lowest value for which +; we prefer CLGHSI to CGHSI. +define double @f4(double %a, double %b, i64 *%ptr) { +; CHECK: f4: +; CHECK: clghsi 0(%r2), 32768 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 32768 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check equality comparisons with the high end of the unsigned 16-bit range. +define double @f5(double %a, double %b, i64 *%ptr) { +; CHECK: f5: +; CHECK: clghsi 0(%r2), 65535 +; CHECK-NEXT: j{{g?}}e +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 65535 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next value up, which can't use CLGHSI. +define double @f6(double %a, double %b, i64 *%ptr) { +; CHECK: f6: +; CHECK-NOT: clghsi +; CHECK: br %r14 + %val = load i64 *%ptr + %cond = icmp eq i64 %val, 65536 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the high end of the CLGHSI range. +define double @f7(double %a, double %b, i64 %i1, i64 *%base) { +; CHECK: f7: +; CHECK: clghsi 4088(%r3), 2 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 511 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check the next doubleword up, which needs separate address logic, +define double @f8(double %a, double %b, i64 *%base) { +; CHECK: f8: +; CHECK: aghi %r2, 4096 +; CHECK: clghsi 0(%r2), 2 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 512 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check negative offsets, which also need separate address logic. +define double @f9(double %a, double %b, i64 *%base) { +; CHECK: f9: +; CHECK: aghi %r2, -8 +; CHECK: clghsi 0(%r2), 2 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %ptr = getelementptr i64 *%base, i64 -1 + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 2 + %res = select i1 %cond, double %a, double %b + ret double %res +} + +; Check that CLGHSI does not allow indices. +define double @f10(double %a, double %b, i64 %base, i64 %index) { +; CHECK: f10: +; CHECK: agr {{%r2, %r3|%r3, %r2}} +; CHECK: clghsi 0({{%r[23]}}), 2 +; CHECK-NEXT: j{{g?}}l +; CHECK: ldr %f0, %f2 +; CHECK: br %r14 + %add = add i64 %base, %index + %ptr = inttoptr i64 %add to i64 * + %val = load i64 *%ptr + %cond = icmp ult i64 %val, 2 + %res = select i1 %cond, double %a, double %b + ret double %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-36.ll b/test/CodeGen/SystemZ/int-cmp-36.ll new file mode 100644 index 000000000000..0813594325e4 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-36.ll @@ -0,0 +1,81 @@ +; Test 32-bit comparisons in which the second operand is sign-extended +; from a PC-relative i16. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i16 1 + +; Check signed comparison. +define i32 @f1(i32 %src1) { +; CHECK: f1: +; CHECK: chrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i32 + %cond = icmp slt i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check unsigned comparison, which cannot use CHRL. +define i32 @f2(i32 %src1) { +; CHECK: f2: +; CHECK-NOT: chrl +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i32 + %cond = icmp ult i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check equality. +define i32 @f3(i32 %src1) { +; CHECK: f3: +; CHECK: chrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i32 + %cond = icmp eq i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check inequality. +define i32 @f4(i32 %src1) { +; CHECK: f4: +; CHECK: chrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i32 + %cond = icmp ne i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-37.ll b/test/CodeGen/SystemZ/int-cmp-37.ll new file mode 100644 index 000000000000..aebd1f610d27 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-37.ll @@ -0,0 +1,81 @@ +; Test 32-bit comparisons in which the second operand is zero-extended +; from a PC-relative i16. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i16 1 + +; Check unsigned comparison. +define i32 @f1(i32 %src1) { +; CHECK: f1: +; CHECK: clhrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i32 + %cond = icmp ult i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check signed comparison. +define i32 @f2(i32 %src1) { +; CHECK: f2: +; CHECK-NOT: clhrl +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i32 + %cond = icmp slt i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check equality. +define i32 @f3(i32 %src1) { +; CHECK: f3: +; CHECK: clhrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i32 + %cond = icmp eq i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check inequality. +define i32 @f4(i32 %src1) { +; CHECK: f4: +; CHECK: clhrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i32 + %cond = icmp ne i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-38.ll b/test/CodeGen/SystemZ/int-cmp-38.ll new file mode 100644 index 000000000000..347073027554 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-38.ll @@ -0,0 +1,78 @@ +; Test 32-bit comparisons in which the second operand is a PC-relative +; variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i32 1 + +; Check signed comparisons. +define i32 @f1(i32 %src1) { +; CHECK: f1: +; CHECK: crl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %src2 = load i32 *@g + %cond = icmp slt i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check unsigned comparisons. +define i32 @f2(i32 %src1) { +; CHECK: f2: +; CHECK: clrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %src2 = load i32 *@g + %cond = icmp ult i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; Check equality, which can use CRL or CLRL. +define i32 @f3(i32 %src1) { +; CHECK: f3: +; CHECK: c{{l?}}rl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %src2 = load i32 *@g + %cond = icmp eq i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} + +; ...likewise inequality. +define i32 @f4(i32 %src1) { +; CHECK: f4: +; CHECK: c{{l?}}rl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %src2 = load i32 *@g + %cond = icmp ne i32 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i32 %src1, %src1 + br label %exit +exit: + %res = phi i32 [ %src1, %entry ], [ %mul, %mulb ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-39.ll b/test/CodeGen/SystemZ/int-cmp-39.ll new file mode 100644 index 000000000000..1129dce84a44 --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-39.ll @@ -0,0 +1,81 @@ +; Test 64-bit comparisons in which the second operand is sign-extended +; from a PC-relative i16. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i16 1 + +; Check signed comparison. +define i64 @f1(i64 %src1) { +; CHECK: f1: +; CHECK: cghrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i64 + %cond = icmp slt i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check unsigned comparison, which cannot use CHRL. +define i64 @f2(i64 %src1) { +; CHECK: f2: +; CHECK-NOT: cghrl +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i64 + %cond = icmp ult i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check equality. +define i64 @f3(i64 %src1) { +; CHECK: f3: +; CHECK: cghrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i64 + %cond = icmp eq i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check inequality. +define i64 @f4(i64 %src1) { +; CHECK: f4: +; CHECK: cghrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = sext i16 %val to i64 + %cond = icmp ne i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-40.ll b/test/CodeGen/SystemZ/int-cmp-40.ll new file mode 100644 index 000000000000..8d9fd9aa140a --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-40.ll @@ -0,0 +1,81 @@ +; Test 64-bit comparisons in which the second operand is zero-extended +; from a PC-relative i16. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i16 1 + +; Check unsigned comparison. +define i64 @f1(i64 %src1) { +; CHECK: f1: +; CHECK: clghrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i64 + %cond = icmp ult i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check signed comparison. +define i64 @f2(i64 %src1) { +; CHECK: f2: +; CHECK-NOT: clghrl +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i64 + %cond = icmp slt i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check equality. +define i64 @f3(i64 %src1) { +; CHECK: f3: +; CHECK: clghrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i64 + %cond = icmp eq i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check inequality. +define i64 @f4(i64 %src1) { +; CHECK: f4: +; CHECK: clghrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i16 *@g + %src2 = zext i16 %val to i64 + %cond = icmp ne i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-41.ll b/test/CodeGen/SystemZ/int-cmp-41.ll new file mode 100644 index 000000000000..0808bffe6d3e --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-41.ll @@ -0,0 +1,81 @@ +; Test 64-bit comparisons in which the second operand is sign-extended +; from a PC-relative i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i32 1 + +; Check signed comparison. +define i64 @f1(i64 %src1) { +; CHECK: f1: +; CHECK: cgfrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = sext i32 %val to i64 + %cond = icmp slt i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check unsigned comparison, which cannot use CHRL. +define i64 @f2(i64 %src1) { +; CHECK: f2: +; CHECK-NOT: cgfrl +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = sext i32 %val to i64 + %cond = icmp ult i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check equality. +define i64 @f3(i64 %src1) { +; CHECK: f3: +; CHECK: cgfrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = sext i32 %val to i64 + %cond = icmp eq i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check inequality. +define i64 @f4(i64 %src1) { +; CHECK: f4: +; CHECK: cgfrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = sext i32 %val to i64 + %cond = icmp ne i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-42.ll b/test/CodeGen/SystemZ/int-cmp-42.ll new file mode 100644 index 000000000000..5c67581dc29a --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-42.ll @@ -0,0 +1,81 @@ +; Test 64-bit comparisons in which the second operand is zero-extended +; from a PC-relative i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i32 1 + +; Check unsigned comparison. +define i64 @f1(i64 %src1) { +; CHECK: f1: +; CHECK: clgfrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = zext i32 %val to i64 + %cond = icmp ult i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check signed comparison. +define i64 @f2(i64 %src1) { +; CHECK: f2: +; CHECK-NOT: clgfrl +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = zext i32 %val to i64 + %cond = icmp slt i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check equality. +define i64 @f3(i64 %src1) { +; CHECK: f3: +; CHECK: clgfrl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = zext i32 %val to i64 + %cond = icmp eq i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check inequality. +define i64 @f4(i64 %src1) { +; CHECK: f4: +; CHECK: clgfrl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %val = load i32 *@g + %src2 = zext i32 %val to i64 + %cond = icmp ne i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/int-cmp-43.ll b/test/CodeGen/SystemZ/int-cmp-43.ll new file mode 100644 index 000000000000..f387293b2b1b --- /dev/null +++ b/test/CodeGen/SystemZ/int-cmp-43.ll @@ -0,0 +1,78 @@ +; Test 64-bit comparisons in which the second operand is a PC-relative +; variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@g = global i64 1 + +; Check signed comparisons. +define i64 @f1(i64 %src1) { +; CHECK: f1: +; CHECK: cgrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %src2 = load i64 *@g + %cond = icmp slt i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check unsigned comparisons. +define i64 @f2(i64 %src1) { +; CHECK: f2: +; CHECK: clgrl %r2, g +; CHECK-NEXT: j{{g?}}l +; CHECK: br %r14 +entry: + %src2 = load i64 *@g + %cond = icmp ult i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; Check equality, which can use CRL or CLRL. +define i64 @f3(i64 %src1) { +; CHECK: f3: +; CHECK: c{{l?}}grl %r2, g +; CHECK-NEXT: j{{g?}}e +; CHECK: br %r14 +entry: + %src2 = load i64 *@g + %cond = icmp eq i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} + +; ...likewise inequality. +define i64 @f4(i64 %src1) { +; CHECK: f4: +; CHECK: c{{l?}}grl %r2, g +; CHECK-NEXT: j{{g?}}lh +; CHECK: br %r14 +entry: + %src2 = load i64 *@g + %cond = icmp ne i64 %src1, %src2 + br i1 %cond, label %exit, label %mulb +mulb: + %mul = mul i64 %src1, %src1 + br label %exit +exit: + %res = phi i64 [ %src1, %entry ], [ %mul, %mulb ] + ret i64 %res +} diff --git a/test/CodeGen/SystemZ/int-const-01.ll b/test/CodeGen/SystemZ/int-const-01.ll new file mode 100644 index 000000000000..a580154e6b57 --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-01.ll @@ -0,0 +1,91 @@ +; Test loading of 32-bit constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check 0. +define i32 @f1() { +; CHECK: f1: +; CHECK: lhi %r2, 0 +; CHECK: br %r14 + ret i32 0 +} + +; Check the high end of the LHI range. +define i32 @f2() { +; CHECK: f2: +; CHECK: lhi %r2, 32767 +; CHECK: br %r14 + ret i32 32767 +} + +; Check the next value up, which must use LLILL instead. +define i32 @f3() { +; CHECK: f3: +; CHECK: llill %r2, 32768 +; CHECK: br %r14 + ret i32 32768 +} + +; Check the high end of the LLILL range. +define i32 @f4() { +; CHECK: f4: +; CHECK: llill %r2, 65535 +; CHECK: br %r14 + ret i32 65535 +} + +; Check the first useful LLILH value, which is the next one up. +define i32 @f5() { +; CHECK: f5: +; CHECK: llilh %r2, 1 +; CHECK: br %r14 + ret i32 65536 +} + +; Check the first useful IILF value, which is the next one up again. +define i32 @f6() { +; CHECK: f6: +; CHECK: iilf %r2, 65537 +; CHECK: br %r14 + ret i32 65537 +} + +; Check the high end of the LLILH range. +define i32 @f7() { +; CHECK: f7: +; CHECK: llilh %r2, 65535 +; CHECK: br %r14 + ret i32 -65536 +} + +; Check the next value up, which must use IILF. +define i32 @f8() { +; CHECK: f8: +; CHECK: iilf %r2, 4294901761 +; CHECK: br %r14 + ret i32 -65535 +} + +; Check the highest useful IILF value, 0xffff7fff +define i32 @f9() { +; CHECK: f9: +; CHECK: iilf %r2, 4294934527 +; CHECK: br %r14 + ret i32 -32769 +} + +; Check the next value up, which should use LHI. +define i32 @f10() { +; CHECK: f10: +; CHECK: lhi %r2, -32768 +; CHECK: br %r14 + ret i32 -32768 +} + +; Check -1. +define i32 @f11() { +; CHECK: f11: +; CHECK: lhi %r2, -1 +; CHECK: br %r14 + ret i32 -1 +} diff --git a/test/CodeGen/SystemZ/int-const-02.ll b/test/CodeGen/SystemZ/int-const-02.ll new file mode 100644 index 000000000000..b345e3f2a2a1 --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-02.ll @@ -0,0 +1,251 @@ +; Test loading of 64-bit constants. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check 0. +define i64 @f1() { +; CHECK: f1: +; CHECK: lghi %r2, 0 +; CHECK-NEXT: br %r14 + ret i64 0 +} + +; Check the high end of the LGHI range. +define i64 @f2() { +; CHECK: f2: +; CHECK: lghi %r2, 32767 +; CHECK-NEXT: br %r14 + ret i64 32767 +} + +; Check the next value up, which must use LLILL instead. +define i64 @f3() { +; CHECK: f3: +; CHECK: llill %r2, 32768 +; CHECK-NEXT: br %r14 + ret i64 32768 +} + +; Check the high end of the LLILL range. +define i64 @f4() { +; CHECK: f4: +; CHECK: llill %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 65535 +} + +; Check the first useful LLILH value, which is the next one up. +define i64 @f5() { +; CHECK: f5: +; CHECK: llilh %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 65536 +} + +; Check the first useful LGFI value, which is the next one up again. +define i64 @f6() { +; CHECK: f6: +; CHECK: lgfi %r2, 65537 +; CHECK-NEXT: br %r14 + ret i64 65537 +} + +; Check the high end of the LGFI range. +define i64 @f7() { +; CHECK: f7: +; CHECK: lgfi %r2, 2147483647 +; CHECK-NEXT: br %r14 + ret i64 2147483647 +} + +; Check the next value up, which should use LLILH instead. +define i64 @f8() { +; CHECK: f8: +; CHECK: llilh %r2, 32768 +; CHECK-NEXT: br %r14 + ret i64 2147483648 +} + +; Check the next value up again, which should use LLILF. +define i64 @f9() { +; CHECK: f9: +; CHECK: llilf %r2, 2147483649 +; CHECK-NEXT: br %r14 + ret i64 2147483649 +} + +; Check the high end of the LLILH range. +define i64 @f10() { +; CHECK: f10: +; CHECK: llilh %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 4294901760 +} + +; Check the next value up, which must use LLILF. +define i64 @f11() { +; CHECK: f11: +; CHECK: llilf %r2, 4294901761 +; CHECK-NEXT: br %r14 + ret i64 4294901761 +} + +; Check the high end of the LLILF range. +define i64 @f12() { +; CHECK: f12: +; CHECK: llilf %r2, 4294967295 +; CHECK-NEXT: br %r14 + ret i64 4294967295 +} + +; Check the lowest useful LLIHL value, which is the next one up. +define i64 @f13() { +; CHECK: f13: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 4294967296 +} + +; Check the next value up, which must use a combination of two instructions. +define i64 @f14() { +; CHECK: f14: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oill %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 4294967297 +} + +; Check the high end of the OILL range. +define i64 @f15() { +; CHECK: f15: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oill %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 4295032831 +} + +; Check the next value up, which should use OILH instead. +define i64 @f16() { +; CHECK: f16: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oilh %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 4295032832 +} + +; Check the next value up again, which should use OILF. +define i64 @f17() { +; CHECK: f17: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oilf %r2, 65537 +; CHECK-NEXT: br %r14 + ret i64 4295032833 +} + +; Check the high end of the OILH range. +define i64 @f18() { +; CHECK: f18: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oilh %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 8589869056 +} + +; Check the high end of the OILF range. +define i64 @f19() { +; CHECK: f19: +; CHECK: llihl %r2, 1 +; CHECK-NEXT: oilf %r2, 4294967295 +; CHECK-NEXT: br %r14 + ret i64 8589934591 +} + +; Check the high end of the LLIHL range. +define i64 @f20() { +; CHECK: f20: +; CHECK: llihl %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 281470681743360 +} + +; Check the lowest useful LLIHH value, which is 1<<32 greater than the above. +define i64 @f21() { +; CHECK: f21: +; CHECK: llihh %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 281474976710656 +} + +; Check the lowest useful LLIHF value, which is 1<<32 greater again. +define i64 @f22() { +; CHECK: f22: +; CHECK: llihf %r2, 65537 +; CHECK-NEXT: br %r14 + ret i64 281479271677952 +} + +; Check the highest end of the LLIHH range. +define i64 @f23() { +; CHECK: f23: +; CHECK: llihh %r2, 65535 +; CHECK-NEXT: br %r14 + ret i64 -281474976710656 +} + +; Check the next value up, which must use OILL too. +define i64 @f24() { +; CHECK: f24: +; CHECK: llihh %r2, 65535 +; CHECK-NEXT: oill %r2, 1 +; CHECK-NEXT: br %r14 + ret i64 -281474976710655 +} + +; Check the high end of the LLIHF range. +define i64 @f25() { +; CHECK: f25: +; CHECK: llihf %r2, 4294967295 +; CHECK-NEXT: br %r14 + ret i64 -4294967296 +} + +; Check -1. +define i64 @f26() { +; CHECK: f26: +; CHECK: lghi %r2, -1 +; CHECK-NEXT: br %r14 + ret i64 -1 +} + +; Check the low end of the LGHI range. +define i64 @f27() { +; CHECK: f27: +; CHECK: lghi %r2, -32768 +; CHECK-NEXT: br %r14 + ret i64 -32768 +} + +; Check the next value down, which must use LGFI instead. +define i64 @f28() { +; CHECK: f28: +; CHECK: lgfi %r2, -32769 +; CHECK-NEXT: br %r14 + ret i64 -32769 +} + +; Check the low end of the LGFI range. +define i64 @f29() { +; CHECK: f29: +; CHECK: lgfi %r2, -2147483648 +; CHECK-NEXT: br %r14 + ret i64 -2147483648 +} + +; Check the next value down, which needs a two-instruction sequence. +define i64 @f30() { +; CHECK: f30: +; CHECK: llihf %r2, 4294967295 +; CHECK-NEXT: oilf %r2, 2147483647 +; CHECK-NEXT: br %r14 + ret i64 -2147483649 +} diff --git a/test/CodeGen/SystemZ/int-const-03.ll b/test/CodeGen/SystemZ/int-const-03.ll new file mode 100644 index 000000000000..807b7e463ced --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-03.ll @@ -0,0 +1,166 @@ +; Test moves of integers to byte memory locations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the unsigned range. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: mvi 0(%r2), 0 +; CHECK: br %r14 + store i8 0, i8 *%ptr + ret void +} + +; Check the high end of the signed range. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: mvi 0(%r2), 127 +; CHECK: br %r14 + store i8 127, i8 *%ptr + ret void +} + +; Check the next value up. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: mvi 0(%r2), 128 +; CHECK: br %r14 + store i8 -128, i8 *%ptr + ret void +} + +; Check the high end of the unsigned range. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: mvi 0(%r2), 255 +; CHECK: br %r14 + store i8 255, i8 *%ptr + ret void +} + +; Check -1. +define void @f5(i8 *%ptr) { +; CHECK: f5: +; CHECK: mvi 0(%r2), 255 +; CHECK: br %r14 + store i8 -1, i8 *%ptr + ret void +} + +; Check the low end of the signed range. +define void @f6(i8 *%ptr) { +; CHECK: f6: +; CHECK: mvi 0(%r2), 128 +; CHECK: br %r14 + store i8 -128, i8 *%ptr + ret void +} + +; Check the next value down. +define void @f7(i8 *%ptr) { +; CHECK: f7: +; CHECK: mvi 0(%r2), 127 +; CHECK: br %r14 + store i8 -129, i8 *%ptr + ret void +} + +; Check the high end of the MVI range. +define void @f8(i8 *%src) { +; CHECK: f8: +; CHECK: mvi 4095(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + store i8 42, i8 *%ptr + ret void +} + +; Check the next byte up, which should use MVIY instead of MVI. +define void @f9(i8 *%src) { +; CHECK: f9: +; CHECK: mviy 4096(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + store i8 42, i8 *%ptr + ret void +} + +; Check the high end of the MVIY range. +define void @f10(i8 *%src) { +; CHECK: f10: +; CHECK: mviy 524287(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + store i8 42, i8 *%ptr + ret void +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f11(i8 *%src) { +; CHECK: f11: +; CHECK: agfi %r2, 524288 +; CHECK: mvi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + store i8 42, i8 *%ptr + ret void +} + +; Check the high end of the negative MVIY range. +define void @f12(i8 *%src) { +; CHECK: f12: +; CHECK: mviy -1(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + store i8 42, i8 *%ptr + ret void +} + +; Check the low end of the MVIY range. +define void @f13(i8 *%src) { +; CHECK: f13: +; CHECK: mviy -524288(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + store i8 42, i8 *%ptr + ret void +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f14(i8 *%src) { +; CHECK: f14: +; CHECK: agfi %r2, -524289 +; CHECK: mvi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + store i8 42, i8 *%ptr + ret void +} + +; Check that MVI does not allow an index +define void @f15(i64 %src, i64 %index) { +; CHECK: f15: +; CHECK: agr %r2, %r3 +; CHECK: mvi 4095(%r2), 42 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + store i8 42, i8 *%ptr + ret void +} + +; Check that MVIY does not allow an index +define void @f16(i64 %src, i64 %index) { +; CHECK: f16: +; CHECK: agr %r2, %r3 +; CHECK: mviy 4096(%r2), 42 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + store i8 42, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-const-04.ll b/test/CodeGen/SystemZ/int-const-04.ll new file mode 100644 index 000000000000..41c7306c89aa --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-04.ll @@ -0,0 +1,111 @@ +; Test moves of integers to 2-byte memory locations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the unsigned range. +define void @f1(i16 *%ptr) { +; CHECK: f1: +; CHECK: mvhhi 0(%r2), 0 +; CHECK: br %r14 + store i16 0, i16 *%ptr + ret void +} + +; Check the high end of the signed range. +define void @f2(i16 *%ptr) { +; CHECK: f2: +; CHECK: mvhhi 0(%r2), 32767 +; CHECK: br %r14 + store i16 32767, i16 *%ptr + ret void +} + +; Check the next value up. +define void @f3(i16 *%ptr) { +; CHECK: f3: +; CHECK: mvhhi 0(%r2), -32768 +; CHECK: br %r14 + store i16 -32768, i16 *%ptr + ret void +} + +; Check the high end of the unsigned range. +define void @f4(i16 *%ptr) { +; CHECK: f4: +; CHECK: mvhhi 0(%r2), -1 +; CHECK: br %r14 + store i16 65535, i16 *%ptr + ret void +} + +; Check -1. +define void @f5(i16 *%ptr) { +; CHECK: f5: +; CHECK: mvhhi 0(%r2), -1 +; CHECK: br %r14 + store i16 -1, i16 *%ptr + ret void +} + +; Check the low end of the signed range. +define void @f6(i16 *%ptr) { +; CHECK: f6: +; CHECK: mvhhi 0(%r2), -32768 +; CHECK: br %r14 + store i16 -32768, i16 *%ptr + ret void +} + +; Check the next value down. +define void @f7(i16 *%ptr) { +; CHECK: f7: +; CHECK: mvhhi 0(%r2), 32767 +; CHECK: br %r14 + store i16 -32769, i16 *%ptr + ret void +} + +; Check the high end of the MVHHI range. +define void @f8(i16 *%a) { +; CHECK: f8: +; CHECK: mvhhi 4094(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i16 *%a, i64 2047 + store i16 42, i16 *%ptr + ret void +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i16 *%a) { +; CHECK: f9: +; CHECK: aghi %r2, 4096 +; CHECK: mvhhi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i16 *%a, i64 2048 + store i16 42, i16 *%ptr + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f10(i16 *%a) { +; CHECK: f10: +; CHECK: aghi %r2, -2 +; CHECK: mvhhi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i16 *%a, i64 -1 + store i16 42, i16 *%ptr + ret void +} + +; Check that MVHHI does not allow an index +define void @f11(i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: agr %r2, %r3 +; CHECK: mvhhi 0(%r2), 42 +; CHECK: br %r14 + %add = add i64 %src, %index + %ptr = inttoptr i64 %add to i16 * + store i16 42, i16 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-const-05.ll b/test/CodeGen/SystemZ/int-const-05.ll new file mode 100644 index 000000000000..b85fd6b68207 --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-05.ll @@ -0,0 +1,102 @@ +; Test moves of integers to 4-byte memory locations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check moves of zero. +define void @f1(i32 *%a) { +; CHECK: f1: +; CHECK: mvhi 0(%r2), 0 +; CHECK: br %r14 + store i32 0, i32 *%a + ret void +} + +; Check the high end of the signed 16-bit range. +define void @f2(i32 *%a) { +; CHECK: f2: +; CHECK: mvhi 0(%r2), 32767 +; CHECK: br %r14 + store i32 32767, i32 *%a + ret void +} + +; Check the next value up, which can't use MVHI. +define void @f3(i32 *%a) { +; CHECK: f3: +; CHECK-NOT: mvhi +; CHECK: br %r14 + store i32 32768, i32 *%a + ret void +} + +; Check moves of -1. +define void @f4(i32 *%a) { +; CHECK: f4: +; CHECK: mvhi 0(%r2), -1 +; CHECK: br %r14 + store i32 -1, i32 *%a + ret void +} + +; Check the low end of the MVHI range. +define void @f5(i32 *%a) { +; CHECK: f5: +; CHECK: mvhi 0(%r2), -32768 +; CHECK: br %r14 + store i32 -32768, i32 *%a + ret void +} + +; Check the next value down, which can't use MVHI. +define void @f6(i32 *%a) { +; CHECK: f6: +; CHECK-NOT: mvhi +; CHECK: br %r14 + store i32 -32769, i32 *%a + ret void +} + +; Check the high end of the MVHI range. +define void @f7(i32 *%a) { +; CHECK: f7: +; CHECK: mvhi 4092(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i32 *%a, i64 1023 + store i32 42, i32 *%ptr + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i32 *%a) { +; CHECK: f8: +; CHECK: aghi %r2, 4096 +; CHECK: mvhi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i32 *%a, i64 1024 + store i32 42, i32 *%ptr + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f9(i32 *%a) { +; CHECK: f9: +; CHECK: aghi %r2, -4 +; CHECK: mvhi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i32 *%a, i64 -1 + store i32 42, i32 *%ptr + ret void +} + +; Check that MVHI does not allow an index +define void @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: agr %r2, %r3 +; CHECK: mvhi 0(%r2), 42 +; CHECK: br %r14 + %add = add i64 %src, %index + %ptr = inttoptr i64 %add to i32 * + store i32 42, i32 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-const-06.ll b/test/CodeGen/SystemZ/int-const-06.ll new file mode 100644 index 000000000000..9f14347cf880 --- /dev/null +++ b/test/CodeGen/SystemZ/int-const-06.ll @@ -0,0 +1,102 @@ +; Test moves of integers to 8-byte memory locations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check moves of zero. +define void @f1(i64 *%a) { +; CHECK: f1: +; CHECK: mvghi 0(%r2), 0 +; CHECK: br %r14 + store i64 0, i64 *%a + ret void +} + +; Check the high end of the signed 16-bit range. +define void @f2(i64 *%a) { +; CHECK: f2: +; CHECK: mvghi 0(%r2), 32767 +; CHECK: br %r14 + store i64 32767, i64 *%a + ret void +} + +; Check the next value up, which can't use MVGHI. +define void @f3(i64 *%a) { +; CHECK: f3: +; CHECK-NOT: mvghi +; CHECK: br %r14 + store i64 32768, i64 *%a + ret void +} + +; Check moves of -1. +define void @f4(i64 *%a) { +; CHECK: f4: +; CHECK: mvghi 0(%r2), -1 +; CHECK: br %r14 + store i64 -1, i64 *%a + ret void +} + +; Check the low end of the MVGHI range. +define void @f5(i64 *%a) { +; CHECK: f5: +; CHECK: mvghi 0(%r2), -32768 +; CHECK: br %r14 + store i64 -32768, i64 *%a + ret void +} + +; Check the next value down, which can't use MVGHI. +define void @f6(i64 *%a) { +; CHECK: f6: +; CHECK-NOT: mvghi +; CHECK: br %r14 + store i64 -32769, i64 *%a + ret void +} + +; Check the high end of the MVGHI range. +define void @f7(i64 *%a) { +; CHECK: f7: +; CHECK: mvghi 4088(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i64 *%a, i64 511 + store i64 42, i64 *%ptr + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i64 *%a) { +; CHECK: f8: +; CHECK: aghi %r2, 4096 +; CHECK: mvghi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i64 *%a, i64 512 + store i64 42, i64 *%ptr + ret void +} + +; Check negative displacements, which also need separate address logic. +define void @f9(i64 *%a) { +; CHECK: f9: +; CHECK: aghi %r2, -8 +; CHECK: mvghi 0(%r2), 42 +; CHECK: br %r14 + %ptr = getelementptr i64 *%a, i64 -1 + store i64 42, i64 *%ptr + ret void +} + +; Check that MVGHI does not allow an index +define void @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: agr %r2, %r3 +; CHECK: mvghi 0(%r2), 42 +; CHECK: br %r14 + %add = add i64 %src, %index + %ptr = inttoptr i64 %add to i64 * + store i64 42, i64 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-conv-01.ll b/test/CodeGen/SystemZ/int-conv-01.ll new file mode 100644 index 000000000000..643ac6ae2510 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-01.ll @@ -0,0 +1,105 @@ +; Test sign extensions from a byte to an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: lbr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i32 %a to i8 + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; ...and again with an i64. +define i32 @f2(i64 %a) { +; CHECK: f2: +; CHECK: lbr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i64 %a to i8 + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check LB with no displacement. +define i32 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: lb %r2, 0(%r2) +; CHECK: br %r14 + %byte = load i8 *%src + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check the high end of the LB range. +define i32 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: lb %r2, 524287(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lb %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check the high end of the negative LB range. +define i32 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: lb %r2, -1(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check the low end of the LB range. +define i32 @f7(i8 *%src) { +; CHECK: f7: +; CHECK: lb %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i8 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524289 +; CHECK: lb %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} + +; Check that LB allows an index +define i32 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: lb %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i8 * + %byte = load i8 *%ptr + %ext = sext i8 %byte to i32 + ret i32 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-02.ll b/test/CodeGen/SystemZ/int-conv-02.ll new file mode 100644 index 000000000000..86144d3e6450 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-02.ll @@ -0,0 +1,114 @@ +; Test zero extensions from a byte to an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: llcr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i32 %a to i8 + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; ...and again with an i64. +define i32 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llcr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i64 %a to i8 + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check ANDs that are equivalent to zero extension. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: llcr %r2, %r2 +; CHECk: br %r14 + %ext = and i32 %a, 255 + ret i32 %ext +} + +; Check LLC with no displacement. +define i32 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: llc %r2, 0(%r2) +; CHECK: br %r14 + %byte = load i8 *%src + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check the high end of the LLC range. +define i32 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: llc %r2, 524287(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: llc %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check the high end of the negative LLC range. +define i32 @f7(i8 *%src) { +; CHECK: f7: +; CHECK: llc %r2, -1(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check the low end of the LLC range. +define i32 @f8(i8 *%src) { +; CHECK: f8: +; CHECK: llc %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i8 *%src) { +; CHECK: f9: +; CHECK: agfi %r2, -524289 +; CHECK: llc %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} + +; Check that LLC allows an index +define i32 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: llc %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i8 * + %byte = load i8 *%ptr + %ext = zext i8 %byte to i32 + ret i32 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-03.ll b/test/CodeGen/SystemZ/int-conv-03.ll new file mode 100644 index 000000000000..73b8dbb43a13 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-03.ll @@ -0,0 +1,105 @@ +; Test sign extensions from a byte to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i32 %a) { +; CHECK: f1: +; CHECK: lgbr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i32 %a to i8 + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: lgbr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i64 %a to i8 + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check LGB with no displacement. +define i64 @f3(i8 *%src) { +; CHECK: f3: +; CHECK: lgb %r2, 0(%r2) +; CHECK: br %r14 + %byte = load i8 *%src + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check the high end of the LGB range. +define i64 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: lgb %r2, 524287(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lgb %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check the high end of the negative LGB range. +define i64 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: lgb %r2, -1(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check the low end of the LGB range. +define i64 @f7(i8 *%src) { +; CHECK: f7: +; CHECK: lgb %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i8 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524289 +; CHECK: lgb %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} + +; Check that LGB allows an index +define i64 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: lgb %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i8 * + %byte = load i8 *%ptr + %ext = sext i8 %byte to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-04.ll b/test/CodeGen/SystemZ/int-conv-04.ll new file mode 100644 index 000000000000..4cec5242e880 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-04.ll @@ -0,0 +1,114 @@ +; Test zero extensions from a byte to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i32 %a) { +; CHECK: f1: +; CHECK: llgcr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i32 %a to i8 + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llgcr %r2, %r2 +; CHECk: br %r14 + %byte = trunc i64 %a to i8 + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check ANDs that are equivalent to zero extension. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: llgcr %r2, %r2 +; CHECk: br %r14 + %ext = and i64 %a, 255 + ret i64 %ext +} + +; Check LLGC with no displacement. +define i64 @f4(i8 *%src) { +; CHECK: f4: +; CHECK: llgc %r2, 0(%r2) +; CHECK: br %r14 + %byte = load i8 *%src + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check the high end of the LLGC range. +define i64 @f5(i8 *%src) { +; CHECK: f5: +; CHECK: llgc %r2, 524287(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i8 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: llgc %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check the high end of the negative LLGC range. +define i64 @f7(i8 *%src) { +; CHECK: f7: +; CHECK: llgc %r2, -1(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check the low end of the LLGC range. +define i64 @f8(i8 *%src) { +; CHECK: f8: +; CHECK: llgc %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f9(i8 *%src) { +; CHECK: f9: +; CHECK: agfi %r2, -524289 +; CHECK: llgc %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} + +; Check that LLGC allows an index +define i64 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: llgc %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i8 * + %byte = load i8 *%ptr + %ext = zext i8 %byte to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-05.ll b/test/CodeGen/SystemZ/int-conv-05.ll new file mode 100644 index 000000000000..5358f7d9228a --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-05.ll @@ -0,0 +1,140 @@ +; Test sign extensions from a halfword to an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: lhr %r2, %r2 +; CHECk: br %r14 + %half = trunc i32 %a to i16 + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; ...and again with an i64. +define i32 @f2(i64 %a) { +; CHECK: f2: +; CHECK: lhr %r2, %r2 +; CHECk: br %r14 + %half = trunc i64 %a to i16 + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the low end of the LH range. +define i32 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: lh %r2, 0(%r2) +; CHECK: br %r14 + %half = load i16 *%src + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the high end of the LH range. +define i32 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: lh %r2, 4094(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2047 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the next halfword up, which needs LHY rather than LH. +define i32 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: lhy %r2, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2048 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the high end of the LHY range. +define i32 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: lhy %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: agfi %r2, 524288 +; CHECK: lh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the high end of the negative LHY range. +define i32 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: lhy %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the low end of the LHY range. +define i32 @f9(i16 *%src) { +; CHECK: f9: +; CHECK: lhy %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f10(i16 *%src) { +; CHECK: f10: +; CHECK: agfi %r2, -524290 +; CHECK: lh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check that LH allows an index +define i32 @f11(i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: lh %r2, 4094(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} + +; Check that LH allows an index +define i32 @f12(i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: lhy %r2, 4096(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = sext i16 %half to i32 + ret i32 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-06.ll b/test/CodeGen/SystemZ/int-conv-06.ll new file mode 100644 index 000000000000..64af612d65f5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-06.ll @@ -0,0 +1,114 @@ +; Test zero extensions from a halfword to an i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: llhr %r2, %r2 +; CHECk: br %r14 + %half = trunc i32 %a to i16 + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; ...and again with an i64. +define i32 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llhr %r2, %r2 +; CHECk: br %r14 + %half = trunc i64 %a to i16 + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check ANDs that are equivalent to zero extension. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: llhr %r2, %r2 +; CHECk: br %r14 + %ext = and i32 %a, 65535 + ret i32 %ext +} + +; Check LLH with no displacement. +define i32 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: llh %r2, 0(%r2) +; CHECK: br %r14 + %half = load i16 *%src + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check the high end of the LLH range. +define i32 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: llh %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: llh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check the high end of the negative LLH range. +define i32 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: llh %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check the low end of the LLH range. +define i32 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: llh %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i16 *%src) { +; CHECK: f9: +; CHECK: agfi %r2, -524290 +; CHECK: llh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} + +; Check that LLH allows an index +define i32 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: llh %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = zext i16 %half to i32 + ret i32 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-07.ll b/test/CodeGen/SystemZ/int-conv-07.ll new file mode 100644 index 000000000000..041caa244c8e --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-07.ll @@ -0,0 +1,105 @@ +; Test sign extensions from a halfword to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: lghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i64 %a to i16 + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i32 %a) { +; CHECK: f2: +; CHECK: lghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i32 %a to i16 + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check LGH with no displacement. +define i64 @f3(i16 *%src) { +; CHECK: f3: +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %half = load i16 *%src + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the LGH range. +define i64 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: lgh %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the negative LGH range. +define i64 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: lgh %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the low end of the LGH range. +define i64 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: lgh %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524290 +; CHECK: lgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} + +; Check that LGH allows an index. +define i64 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: lgh %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = sext i16 %half to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-08.ll b/test/CodeGen/SystemZ/int-conv-08.ll new file mode 100644 index 000000000000..3d7f96675da9 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-08.ll @@ -0,0 +1,114 @@ +; Test zero extensions from a halfword to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i32 %a) { +; CHECK: f1: +; CHECK: llghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i32 %a to i16 + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llghr %r2, %r2 +; CHECk: br %r14 + %half = trunc i64 %a to i16 + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check ANDs that are equivalent to zero extension. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: llghr %r2, %r2 +; CHECk: br %r14 + %ext = and i64 %a, 65535 + ret i64 %ext +} + +; Check LLGH with no displacement. +define i64 @f4(i16 *%src) { +; CHECK: f4: +; CHECK: llgh %r2, 0(%r2) +; CHECK: br %r14 + %half = load i16 *%src + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the LLGH range. +define i64 @f5(i16 *%src) { +; CHECK: f5: +; CHECK: llgh %r2, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i16 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: llgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check the high end of the negative LLGH range. +define i64 @f7(i16 *%src) { +; CHECK: f7: +; CHECK: llgh %r2, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check the low end of the LLGH range. +define i64 @f8(i16 *%src) { +; CHECK: f8: +; CHECK: llgh %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f9(i16 *%src) { +; CHECK: f9: +; CHECK: agfi %r2, -524290 +; CHECK: llgh %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} + +; Check that LLGH allows an index +define i64 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: llgh %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %ext = zext i16 %half to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-09.ll b/test/CodeGen/SystemZ/int-conv-09.ll new file mode 100644 index 000000000000..6e93886895d5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-09.ll @@ -0,0 +1,104 @@ +; Test sign extensions from an i32 to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i32 %a) { +; CHECK: f1: +; CHECK: lgfr %r2, %r2 +; CHECk: br %r14 + %ext = sext i32 %a to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: lgfr %r2, %r2 +; CHECk: br %r14 + %word = trunc i64 %a to i32 + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check LGF with no displacement. +define i64 @f3(i32 *%src) { +; CHECK: f3: +; CHECK: lgf %r2, 0(%r2) +; CHECK: br %r14 + %word = load i32 *%src + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check the high end of the LGF range. +define i64 @f4(i32 *%src) { +; CHECK: f4: +; CHECK: lgf %r2, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f5(i32 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: lgf %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check the high end of the negative LGF range. +define i64 @f6(i32 *%src) { +; CHECK: f6: +; CHECK: lgf %r2, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check the low end of the LGF range. +define i64 @f7(i32 *%src) { +; CHECK: f7: +; CHECK: lgf %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i32 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524292 +; CHECK: lgf %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} + +; Check that LGF allows an index. +define i64 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: lgf %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %word = load i32 *%ptr + %ext = sext i32 %word to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-conv-10.ll b/test/CodeGen/SystemZ/int-conv-10.ll new file mode 100644 index 000000000000..918bc1de8fa5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-conv-10.ll @@ -0,0 +1,113 @@ +; Test zero extensions from an i32 to an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register extension, starting with an i32. +define i64 @f1(i32 %a) { +; CHECK: f1: +; CHECK: llgfr %r2, %r2 +; CHECk: br %r14 + %ext = zext i32 %a to i64 + ret i64 %ext +} + +; ...and again with an i64. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: llgfr %r2, %r2 +; CHECk: br %r14 + %word = trunc i64 %a to i32 + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check ANDs that are equivalent to zero extension. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: llgfr %r2, %r2 +; CHECk: br %r14 + %ext = and i64 %a, 4294967295 + ret i64 %ext +} + +; Check LLGF with no displacement. +define i64 @f4(i32 *%src) { +; CHECK: f4: +; CHECK: llgf %r2, 0(%r2) +; CHECK: br %r14 + %word = load i32 *%src + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check the high end of the LLGF range. +define i64 @f5(i32 *%src) { +; CHECK: f5: +; CHECK: llgf %r2, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: llgf %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check the high end of the negative LLGF range. +define i64 @f7(i32 *%src) { +; CHECK: f7: +; CHECK: llgf %r2, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check the low end of the LLGF range. +define i64 @f8(i32 *%src) { +; CHECK: f8: +; CHECK: llgf %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f9(i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r2, -524292 +; CHECK: llgf %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} + +; Check that LLGF allows an index. +define i64 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: llgf %r2, 524287(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %word = load i32 *%ptr + %ext = zext i32 %word to i64 + ret i64 %ext +} diff --git a/test/CodeGen/SystemZ/int-div-01.ll b/test/CodeGen/SystemZ/int-div-01.ll new file mode 100644 index 000000000000..492ece91497e --- /dev/null +++ b/test/CodeGen/SystemZ/int-div-01.ll @@ -0,0 +1,190 @@ +; Test 32-bit signed division and remainder. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register division. The result is in the second of the two registers. +define void @f1(i32 *%dest, i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: lgfr %r1, %r3 +; CHECK: dsgfr %r0, %r4 +; CHECK: st %r1, 0(%r2) +; CHECK: br %r14 + %div = sdiv i32 %a, %b + store i32 %div, i32 *%dest + ret void +} + +; Test register remainder. The result is in the first of the two registers. +define void @f2(i32 *%dest, i32 %a, i32 %b) { +; CHECK: f2: +; CHECK: lgfr %r1, %r3 +; CHECK: dsgfr %r0, %r4 +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %rem = srem i32 %a, %b + store i32 %rem, i32 *%dest + ret void +} + +; Test that division and remainder use a single instruction. +define i32 @f3(i32 %dummy, i32 %a, i32 %b) { +; CHECK: f3: +; CHECK-NOT: %r2 +; CHECK: lgfr %r3, %r3 +; CHECK-NOT: %r2 +; CHECK: dsgfr %r2, %r4 +; CHECK-NOT: dsgfr +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %div = sdiv i32 %a, %b + %rem = srem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Check that the sign extension of the dividend is elided when the argument +; is already sign-extended. +define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) { +; CHECK: f4: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgfr %r2, %r4 +; CHECK-NOT: dsgfr +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %div = sdiv i32 %a, %b + %rem = srem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Test that memory dividends are loaded using sign extension (LGF). +define i32 @f5(i32 %dummy, i32 *%src, i32 %b) { +; CHECK: f5: +; CHECK-NOT: %r2 +; CHECK: lgf %r3, 0(%r3) +; CHECK-NOT: %r2 +; CHECK: dsgfr %r2, %r4 +; CHECK-NOT: dsgfr +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %a = load i32 *%src + %div = sdiv i32 %a, %b + %rem = srem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Test memory division with no displacement. +define void @f6(i32 *%dest, i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: lgfr %r1, %r3 +; CHECK: dsgf %r0, 0(%r4) +; CHECK: st %r1, 0(%r2) +; CHECK: br %r14 + %b = load i32 *%src + %div = sdiv i32 %a, %b + store i32 %div, i32 *%dest + ret void +} + +; Test memory remainder with no displacement. +define void @f7(i32 *%dest, i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: lgfr %r1, %r3 +; CHECK: dsgf %r0, 0(%r4) +; CHECK: st %r0, 0(%r2) +; CHECK: br %r14 + %b = load i32 *%src + %rem = srem i32 %a, %b + store i32 %rem, i32 *%dest + ret void +} + +; Test both memory division and memory remainder. +define i32 @f8(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK-NOT: %r2 +; CHECK: lgfr %r3, %r3 +; CHECK-NOT: %r2 +; CHECK: dsgf %r2, 0(%r4) +; CHECK-NOT: {{dsgf|dsgfr}} +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %b = load i32 *%src + %div = sdiv i32 %a, %b + %rem = srem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Check the high end of the DSGF range. +define i32 @f9(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: dsgf %r2, 524284(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f10(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f10: +; CHECK: agfi %r4, 524288 +; CHECK: dsgf %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} + +; Check the high end of the negative aligned DSGF range. +define i32 @f11(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f11: +; CHECK: dsgf %r2, -4(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} + +; Check the low end of the DSGF range. +define i32 @f12(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f12: +; CHECK: dsgf %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f13(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f13: +; CHECK: agfi %r4, -524292 +; CHECK: dsgf %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} + +; Check that DSGF allows an index. +define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) { +; CHECK: f14: +; CHECK: dsgf %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %rem = srem i32 %a, %b + ret i32 %rem +} diff --git a/test/CodeGen/SystemZ/int-div-02.ll b/test/CodeGen/SystemZ/int-div-02.ll new file mode 100644 index 000000000000..7954384d2962 --- /dev/null +++ b/test/CodeGen/SystemZ/int-div-02.ll @@ -0,0 +1,166 @@ +; Test 32-bit unsigned division and remainder. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register division. The result is in the second of the two registers. +define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) { +; CHECK: f1: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlr %r2, %r4 +; CHECK: st %r3, 0(%r5) +; CHECK: br %r14 + %div = udiv i32 %a, %b + store i32 %div, i32 *%dest + ret void +} + +; Test register remainder. The result is in the first of the two registers. +define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) { +; CHECK: f2: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlr %r2, %r4 +; CHECK: st %r2, 0(%r5) +; CHECK: br %r14 + %rem = urem i32 %a, %b + store i32 %rem, i32 *%dest + ret void +} + +; Test that division and remainder use a single instruction. +define i32 @f3(i32 %dummy1, i32 %a, i32 %b) { +; CHECK: f3: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlr %r2, %r4 +; CHECK-NOT: dlr +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %div = udiv i32 %a, %b + %rem = urem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Test memory division with no displacement. +define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) { +; CHECK: f4: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dl %r2, 0(%r4) +; CHECK: st %r3, 0(%r5) +; CHECK: br %r14 + %b = load i32 *%src + %div = udiv i32 %a, %b + store i32 %div, i32 *%dest + ret void +} + +; Test memory remainder with no displacement. +define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) { +; CHECK: f5: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dl %r2, 0(%r4) +; CHECK: st %r2, 0(%r5) +; CHECK: br %r14 + %b = load i32 *%src + %rem = urem i32 %a, %b + store i32 %rem, i32 *%dest + ret void +} + +; Test both memory division and memory remainder. +define i32 @f6(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK-NOT: %r3 +; CHECK: {{llill|lhi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dl %r2, 0(%r4) +; CHECK-NOT: {{dl|dlr}} +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %b = load i32 *%src + %div = udiv i32 %a, %b + %rem = urem i32 %a, %b + %or = or i32 %rem, %div + ret i32 %or +} + +; Check the high end of the DL range. +define i32 @f7(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: dl %r2, 524284(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: agfi %r4, 524288 +; CHECK: dl %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} + +; Check the high end of the negative aligned DL range. +define i32 @f9(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: dl %r2, -4(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} + +; Check the low end of the DL range. +define i32 @f10(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f10: +; CHECK: dl %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f11(i32 %dummy, i32 %a, i32 *%src) { +; CHECK: f11: +; CHECK: agfi %r4, -524292 +; CHECK: dl %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} + +; Check that DL allows an index. +define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: dl %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %rem = urem i32 %a, %b + ret i32 %rem +} diff --git a/test/CodeGen/SystemZ/int-div-03.ll b/test/CodeGen/SystemZ/int-div-03.ll new file mode 100644 index 000000000000..b950f2b02035 --- /dev/null +++ b/test/CodeGen/SystemZ/int-div-03.ll @@ -0,0 +1,189 @@ +; Test 64-bit signed division and remainder when the divisor is +; a signed-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register division. The result is in the second of the two registers. +define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) { +; CHECK: f1: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgfr %r2, %r4 +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %div = sdiv i64 %a, %bext + store i64 %div, i64 *%dest + ret void +} + +; Test register remainder. The result is in the first of the two registers. +define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) { +; CHECK: f2: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgfr %r2, %r4 +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + store i64 %rem, i64 *%dest + ret void +} + +; Test that division and remainder use a single instruction. +define i64 @f3(i64 %dummy, i64 %a, i32 %b) { +; CHECK: f3: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgfr %r2, %r4 +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %div = sdiv i64 %a, %bext + %rem = srem i64 %a, %bext + %or = or i64 %rem, %div + ret i64 %or +} + +; Test register division when the dividend is zero rather than sign extended. +; We can't use dsgfr here +define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) { +; CHECK: f4: +; CHECK-NOT: dsgfr +; CHECK: br %r14 + %bext = zext i32 %b to i64 + %div = sdiv i64 %a, %bext + store i64 %div, i64 *%dest + ret void +} + +; ...likewise remainder. +define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) { +; CHECK: f5: +; CHECK-NOT: dsgfr +; CHECK: br %r14 + %bext = zext i32 %b to i64 + %rem = srem i64 %a, %bext + store i64 %rem, i64 *%dest + ret void +} + +; Test memory division with no displacement. +define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) { +; CHECK: f6: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgf %r2, 0(%r4) +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %div = sdiv i64 %a, %bext + store i64 %div, i64 *%dest + ret void +} + +; Test memory remainder with no displacement. +define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) { +; CHECK: f7: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgf %r2, 0(%r4) +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + store i64 %rem, i64 *%dest + ret void +} + +; Test both memory division and memory remainder. +define i64 @f8(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f8: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgf %r2, 0(%r4) +; CHECK-NOT: {{dsgf|dsgfr}} +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %div = sdiv i64 %a, %bext + %rem = srem i64 %a, %bext + %or = or i64 %rem, %div + ret i64 %or +} + +; Check the high end of the DSGF range. +define i64 @f9(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f9: +; CHECK: dsgf %r2, 524284(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f10(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f10: +; CHECK: agfi %r4, 524288 +; CHECK: dsgf %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} + +; Check the high end of the negative aligned DSGF range. +define i64 @f11(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f11: +; CHECK: dsgf %r2, -4(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} + +; Check the low end of the DSGF range. +define i64 @f12(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f12: +; CHECK: dsgf %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f13(i64 %dummy, i64 %a, i32 *%src) { +; CHECK: f13: +; CHECK: agfi %r4, -524292 +; CHECK: dsgf %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} + +; Check that DSGF allows an index. +define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) { +; CHECK: f14: +; CHECK: dsgf %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %rem = srem i64 %a, %bext + ret i64 %rem +} diff --git a/test/CodeGen/SystemZ/int-div-04.ll b/test/CodeGen/SystemZ/int-div-04.ll new file mode 100644 index 000000000000..3f72be9a47da --- /dev/null +++ b/test/CodeGen/SystemZ/int-div-04.ll @@ -0,0 +1,154 @@ +; Testg 64-bit signed division and remainder. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Testg register division. The result is in the second of the two registers. +define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) { +; CHECK: f1: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgr %r2, %r4 +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %div = sdiv i64 %a, %b + store i64 %div, i64 *%dest + ret void +} + +; Testg register remainder. The result is in the first of the two registers. +define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) { +; CHECK: f2: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgr %r2, %r4 +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %rem = srem i64 %a, %b + store i64 %rem, i64 *%dest + ret void +} + +; Testg that division and remainder use a single instruction. +define i64 @f3(i64 %dummy1, i64 %a, i64 %b) { +; CHECK: f3: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsgr %r2, %r4 +; CHECK-NOT: dsgr +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %div = sdiv i64 %a, %b + %rem = srem i64 %a, %b + %or = or i64 %rem, %div + ret i64 %or +} + +; Testg memory division with no displacement. +define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { +; CHECK: f4: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsg %r2, 0(%r4) +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %b = load i64 *%src + %div = sdiv i64 %a, %b + store i64 %div, i64 *%dest + ret void +} + +; Testg memory remainder with no displacement. +define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { +; CHECK: f5: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsg %r2, 0(%r4) +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %b = load i64 *%src + %rem = srem i64 %a, %b + store i64 %rem, i64 *%dest + ret void +} + +; Testg both memory division and memory remainder. +define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK-NOT: {{%r[234]}} +; CHECK: dsg %r2, 0(%r4) +; CHECK-NOT: {{dsg|dsgr}} +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %b = load i64 *%src + %div = sdiv i64 %a, %b + %rem = srem i64 %a, %b + %or = or i64 %rem, %div + ret i64 %or +} + +; Check the high end of the DSG range. +define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: dsg %r2, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f8: +; CHECK: agfi %r4, 524288 +; CHECK: dsg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} + +; Check the high end of the negative aligned DSG range. +define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f9: +; CHECK: dsg %r2, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} + +; Check the low end of the DSG range. +define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f10: +; CHECK: dsg %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f11(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f11: +; CHECK: agfi %r4, -524296 +; CHECK: dsg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} + +; Check that DSG allows an index. +define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: dsg %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %rem = srem i64 %a, %b + ret i64 %rem +} diff --git a/test/CodeGen/SystemZ/int-div-05.ll b/test/CodeGen/SystemZ/int-div-05.ll new file mode 100644 index 000000000000..04f622b44e74 --- /dev/null +++ b/test/CodeGen/SystemZ/int-div-05.ll @@ -0,0 +1,166 @@ +; Testg 64-bit unsigned division and remainder. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Testg register division. The result is in the second of the two registers. +define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) { +; CHECK: f1: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlgr %r2, %r4 +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %div = udiv i64 %a, %b + store i64 %div, i64 *%dest + ret void +} + +; Testg register remainder. The result is in the first of the two registers. +define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) { +; CHECK: f2: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlgr %r2, %r4 +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %rem = urem i64 %a, %b + store i64 %rem, i64 *%dest + ret void +} + +; Testg that division and remainder use a single instruction. +define i64 @f3(i64 %dummy1, i64 %a, i64 %b) { +; CHECK: f3: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlgr %r2, %r4 +; CHECK-NOT: dlgr +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %div = udiv i64 %a, %b + %rem = urem i64 %a, %b + %or = or i64 %rem, %div + ret i64 %or +} + +; Testg memory division with no displacement. +define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { +; CHECK: f4: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlg %r2, 0(%r4) +; CHECK: stg %r3, 0(%r5) +; CHECK: br %r14 + %b = load i64 *%src + %div = udiv i64 %a, %b + store i64 %div, i64 *%dest + ret void +} + +; Testg memory remainder with no displacement. +define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) { +; CHECK: f5: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlg %r2, 0(%r4) +; CHECK: stg %r2, 0(%r5) +; CHECK: br %r14 + %b = load i64 *%src + %rem = urem i64 %a, %b + store i64 %rem, i64 *%dest + ret void +} + +; Testg both memory division and memory remainder. +define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK-NOT: %r3 +; CHECK: {{llill|lghi}} %r2, 0 +; CHECK-NOT: %r3 +; CHECK: dlg %r2, 0(%r4) +; CHECK-NOT: {{dlg|dlgr}} +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %b = load i64 *%src + %div = udiv i64 %a, %b + %rem = urem i64 %a, %b + %or = or i64 %rem, %div + ret i64 %or +} + +; Check the high end of the DLG range. +define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: dlg %r2, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f8: +; CHECK: agfi %r4, 524288 +; CHECK: dlg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} + +; Check the high end of the negative aligned DLG range. +define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f9: +; CHECK: dlg %r2, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} + +; Check the low end of the DLG range. +define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f10: +; CHECK: dlg %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f11(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f11: +; CHECK: agfi %r4, -524296 +; CHECK: dlg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} + +; Check that DLG allows an index. +define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: dlg %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %rem = urem i64 %a, %b + ret i64 %rem +} diff --git a/test/CodeGen/SystemZ/int-move-01.ll b/test/CodeGen/SystemZ/int-move-01.ll new file mode 100644 index 000000000000..ae890ade3275 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-01.ll @@ -0,0 +1,35 @@ +; Test moves between GPRs. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test 8-bit moves, which should get promoted to i32. +define i8 @f1(i8 %a, i8 %b) { +; CHECK: f1: +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + ret i8 %b +} + +; Test 16-bit moves, which again should get promoted to i32. +define i16 @f2(i16 %a, i16 %b) { +; CHECK: f2: +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + ret i16 %b +} + +; Test 32-bit moves. +define i32 @f3(i32 %a, i32 %b) { +; CHECK: f3: +; CHECK: lr %r2, %r3 +; CHECK: br %r14 + ret i32 %b +} + +; Test 64-bit moves. +define i64 @f4(i64 %a, i64 %b) { +; CHECK: f4: +; CHECK: lgr %r2, %r3 +; CHECK: br %r14 + ret i64 %b +} diff --git a/test/CodeGen/SystemZ/int-move-02.ll b/test/CodeGen/SystemZ/int-move-02.ll new file mode 100644 index 000000000000..467e22d89c5a --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-02.ll @@ -0,0 +1,110 @@ +; Test 32-bit GPR loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the L range. +define i32 @f1(i32 *%src) { +; CHECK: f1: +; CHECK: l %r2, 0(%r2) +; CHECK: br %r14 + %val = load i32 *%src + ret i32 %val +} + +; Check the high end of the aligned L range. +define i32 @f2(i32 *%src) { +; CHECK: f2: +; CHECK: l %r2, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the next word up, which should use LY instead of L. +define i32 @f3(i32 *%src) { +; CHECK: f3: +; CHECK: ly %r2, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the high end of the aligned LY range. +define i32 @f4(i32 *%src) { +; CHECK: f4: +; CHECK: ly %r2, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i32 *%src) { +; CHECK: f5: +; CHECK: agfi %r2, 524288 +; CHECK: l %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the high end of the negative aligned LY range. +define i32 @f6(i32 *%src) { +; CHECK: f6: +; CHECK: ly %r2, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the low end of the LY range. +define i32 @f7(i32 *%src) { +; CHECK: f7: +; CHECK: ly %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %val = load i32 *%ptr + ret i32 %val +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, -524292 +; CHECK: l %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %val = load i32 *%ptr + ret i32 %val +} + +; Check that L allows an index. +define i32 @f9(i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: l %r2, 4095({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i32 * + %val = load i32 *%ptr + ret i32 %val +} + +; Check that LY allows an index. +define i32 @f10(i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: ly %r2, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %val = load i32 *%ptr + ret i32 %val +} diff --git a/test/CodeGen/SystemZ/int-move-03.ll b/test/CodeGen/SystemZ/int-move-03.ll new file mode 100644 index 000000000000..97c70a2740c1 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-03.ll @@ -0,0 +1,78 @@ +; Test 64-bit GPR loads. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check LG with no displacement. +define i64 @f1(i64 *%src) { +; CHECK: f1: +; CHECK: lg %r2, 0(%r2) +; CHECK: br %r14 + %val = load i64 *%src + ret i64 %val +} + +; Check the high end of the aligned LG range. +define i64 @f2(i64 *%src) { +; CHECK: f2: +; CHECK: lg %r2, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %val = load i64 *%ptr + ret i64 %val +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 *%src) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: lg %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %val = load i64 *%ptr + ret i64 %val +} + +; Check the high end of the negative aligned LG range. +define i64 @f4(i64 *%src) { +; CHECK: f4: +; CHECK: lg %r2, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %val = load i64 *%ptr + ret i64 %val +} + +; Check the low end of the LG range. +define i64 @f5(i64 *%src) { +; CHECK: f5: +; CHECK: lg %r2, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %val = load i64 *%ptr + ret i64 %val +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 *%src) { +; CHECK: f6: +; CHECK: agfi %r2, -524296 +; CHECK: lg %r2, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %val = load i64 *%ptr + ret i64 %val +} + +; Check that LG allows an index. +define i64 @f7(i64 %src, i64 %index) { +; CHECK: f7: +; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %val = load i64 *%ptr + ret i64 %val +} diff --git a/test/CodeGen/SystemZ/int-move-04.ll b/test/CodeGen/SystemZ/int-move-04.ll new file mode 100644 index 000000000000..9736657b1efa --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-04.ll @@ -0,0 +1,130 @@ +; Test 8-bit GPR stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test an i8 store, which should get converted into an i32 truncation. +define void @f1(i8 *%dst, i8 %val) { +; CHECK: f1: +; CHECK: stc %r3, 0(%r2) +; CHECK: br %r14 + store i8 %val, i8 *%dst + ret void +} + +; Test an i32 truncating store. +define void @f2(i8 *%dst, i32 %val) { +; CHECK: f2: +; CHECK: stc %r3, 0(%r2) +; CHECK: br %r14 + %trunc = trunc i32 %val to i8 + store i8 %trunc, i8 *%dst + ret void +} + +; Test an i64 truncating store. +define void @f3(i8 *%dst, i64 %val) { +; CHECK: f3: +; CHECK: stc %r3, 0(%r2) +; CHECK: br %r14 + %trunc = trunc i64 %val to i8 + store i8 %trunc, i8 *%dst + ret void +} + +; Check the high end of the STC range. +define void @f4(i8 *%dst, i8 %val) { +; CHECK: f4: +; CHECK: stc %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 4095 + store i8 %val, i8 *%ptr + ret void +} + +; Check the next byte up, which should use STCY instead of STC. +define void @f5(i8 *%dst, i8 %val) { +; CHECK: f5: +; CHECK: stcy %r3, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 4096 + store i8 %val, i8 *%ptr + ret void +} + +; Check the high end of the STCY range. +define void @f6(i8 *%dst, i8 %val) { +; CHECK: f6: +; CHECK: stcy %r3, 524287(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 524287 + store i8 %val, i8 *%ptr + ret void +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f7(i8 *%dst, i8 %val) { +; CHECK: f7: +; CHECK: agfi %r2, 524288 +; CHECK: stc %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 524288 + store i8 %val, i8 *%ptr + ret void +} + +; Check the high end of the negative STCY range. +define void @f8(i8 *%dst, i8 %val) { +; CHECK: f8: +; CHECK: stcy %r3, -1(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 -1 + store i8 %val, i8 *%ptr + ret void +} + +; Check the low end of the STCY range. +define void @f9(i8 *%dst, i8 %val) { +; CHECK: f9: +; CHECK: stcy %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 -524288 + store i8 %val, i8 *%ptr + ret void +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f10(i8 *%dst, i8 %val) { +; CHECK: f10: +; CHECK: agfi %r2, -524289 +; CHECK: stc %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8 *%dst, i64 -524289 + store i8 %val, i8 *%ptr + ret void +} + +; Check that STC allows an index. +define void @f11(i64 %dst, i64 %index, i8 %val) { +; CHECK: f11: +; CHECK: stc %r4, 4095(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + store i8 %val, i8 *%ptr + ret void +} + +; Check that STCY allows an index. +define void @f12(i64 %dst, i64 %index, i8 %val) { +; CHECK: f12: +; CHECK: stcy %r4, 4096(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + store i8 %val, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-move-05.ll b/test/CodeGen/SystemZ/int-move-05.ll new file mode 100644 index 000000000000..f61477e71830 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-05.ll @@ -0,0 +1,130 @@ +; Test 16-bit GPR stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test an i16 store, which should get converted into an i32 truncation. +define void @f1(i16 *%dst, i16 %val) { +; CHECK: f1: +; CHECK: sth %r3, 0(%r2) +; CHECK: br %r14 + store i16 %val, i16 *%dst + ret void +} + +; Test an i32 truncating store. +define void @f2(i16 *%dst, i32 %val) { +; CHECK: f2: +; CHECK: sth %r3, 0(%r2) +; CHECK: br %r14 + %trunc = trunc i32 %val to i16 + store i16 %trunc, i16 *%dst + ret void +} + +; Test an i64 truncating store. +define void @f3(i16 *%dst, i64 %val) { +; CHECK: f3: +; CHECK: sth %r3, 0(%r2) +; CHECK: br %r14 + %trunc = trunc i64 %val to i16 + store i16 %trunc, i16 *%dst + ret void +} + +; Check the high end of the STH range. +define void @f4(i16 *%dst, i16 %val) { +; CHECK: f4: +; CHECK: sth %r3, 4094(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 2047 + store i16 %val, i16 *%ptr + ret void +} + +; Check the next halfword up, which should use STHY instead of STH. +define void @f5(i16 *%dst, i16 %val) { +; CHECK: f5: +; CHECK: sthy %r3, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 2048 + store i16 %val, i16 *%ptr + ret void +} + +; Check the high end of the aligned STHY range. +define void @f6(i16 *%dst, i16 %val) { +; CHECK: f6: +; CHECK: sthy %r3, 524286(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 262143 + store i16 %val, i16 *%ptr + ret void +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f7(i16 *%dst, i16 %val) { +; CHECK: f7: +; CHECK: agfi %r2, 524288 +; CHECK: sth %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 262144 + store i16 %val, i16 *%ptr + ret void +} + +; Check the high end of the negative aligned STHY range. +define void @f8(i16 *%dst, i16 %val) { +; CHECK: f8: +; CHECK: sthy %r3, -2(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 -1 + store i16 %val, i16 *%ptr + ret void +} + +; Check the low end of the STHY range. +define void @f9(i16 *%dst, i16 %val) { +; CHECK: f9: +; CHECK: sthy %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 -262144 + store i16 %val, i16 *%ptr + ret void +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f10(i16 *%dst, i16 %val) { +; CHECK: f10: +; CHECK: agfi %r2, -524290 +; CHECK: sth %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i16 *%dst, i64 -262145 + store i16 %val, i16 *%ptr + ret void +} + +; Check that STH allows an index. +define void @f11(i64 %dst, i64 %index, i16 %val) { +; CHECK: f11: +; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + store i16 %val, i16 *%ptr + ret void +} + +; Check that STHY allows an index. +define void @f12(i64 %dst, i64 %index, i16 %val) { +; CHECK: f12: +; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + store i16 %val, i16 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-move-06.ll b/test/CodeGen/SystemZ/int-move-06.ll new file mode 100644 index 000000000000..5b35a32ff543 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-06.ll @@ -0,0 +1,117 @@ +; Test 32-bit GPR stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test an i32 store. +define void @f1(i32 *%dst, i32 %val) { +; CHECK: f1: +; CHECK: st %r3, 0(%r2) +; CHECK: br %r14 + store i32 %val, i32 *%dst + ret void +} + +; Test a truncating i64 store. +define void @f2(i32 *%dst, i64 %val) { + %word = trunc i64 %val to i32 + store i32 %word, i32 *%dst + ret void +} + +; Check the high end of the aligned ST range. +define void @f3(i32 *%dst, i32 %val) { +; CHECK: f3: +; CHECK: st %r3, 4092(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 1023 + store i32 %val, i32 *%ptr + ret void +} + +; Check the next word up, which should use STY instead of ST. +define void @f4(i32 *%dst, i32 %val) { +; CHECK: f4: +; CHECK: sty %r3, 4096(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 1024 + store i32 %val, i32 *%ptr + ret void +} + +; Check the high end of the aligned STY range. +define void @f5(i32 *%dst, i32 %val) { +; CHECK: f5: +; CHECK: sty %r3, 524284(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 131071 + store i32 %val, i32 *%ptr + ret void +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i32 *%dst, i32 %val) { +; CHECK: f6: +; CHECK: agfi %r2, 524288 +; CHECK: st %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 131072 + store i32 %val, i32 *%ptr + ret void +} + +; Check the high end of the negative aligned STY range. +define void @f7(i32 *%dst, i32 %val) { +; CHECK: f7: +; CHECK: sty %r3, -4(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 -1 + store i32 %val, i32 *%ptr + ret void +} + +; Check the low end of the STY range. +define void @f8(i32 *%dst, i32 %val) { +; CHECK: f8: +; CHECK: sty %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 -131072 + store i32 %val, i32 *%ptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i32 *%dst, i32 %val) { +; CHECK: f9: +; CHECK: agfi %r2, -524292 +; CHECK: st %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i32 *%dst, i64 -131073 + store i32 %val, i32 *%ptr + ret void +} + +; Check that ST allows an index. +define void @f10(i64 %dst, i64 %index, i32 %val) { +; CHECK: f10: +; CHECK: st %r4, 4095(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i32 * + store i32 %val, i32 *%ptr + ret void +} + +; Check that STY allows an index. +define void @f11(i64 %dst, i64 %index, i32 %val) { +; CHECK: f11: +; CHECK: sty %r4, 4096(%r3,%r2) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + store i32 %val, i32 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-move-07.ll b/test/CodeGen/SystemZ/int-move-07.ll new file mode 100644 index 000000000000..ab21ab039534 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-07.ll @@ -0,0 +1,78 @@ +; Test 64-bit GPR stores. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check STG with no displacement. +define void @f1(i64 *%dst, i64 %val) { +; CHECK: f1: +; CHECK: stg %r3, 0(%r2) +; CHECK: br %r14 + store i64 %val, i64 *%dst + ret void +} + +; Check the high end of the aligned STG range. +define void @f2(i64 *%dst, i64 %val) { +; CHECK: f2: +; CHECK: stg %r3, 524280(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%dst, i64 65535 + store i64 %val, i64 *%ptr + ret void +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f3(i64 *%dst, i64 %val) { +; CHECK: f3: +; CHECK: agfi %r2, 524288 +; CHECK: stg %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%dst, i64 65536 + store i64 %val, i64 *%ptr + ret void +} + +; Check the high end of the negative aligned STG range. +define void @f4(i64 *%dst, i64 %val) { +; CHECK: f4: +; CHECK: stg %r3, -8(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%dst, i64 -1 + store i64 %val, i64 *%ptr + ret void +} + +; Check the low end of the STG range. +define void @f5(i64 *%dst, i64 %val) { +; CHECK: f5: +; CHECK: stg %r3, -524288(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%dst, i64 -65536 + store i64 %val, i64 *%ptr + ret void +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i64 *%dst, i64 %val) { +; CHECK: f6: +; CHECK: agfi %r2, -524296 +; CHECK: stg %r3, 0(%r2) +; CHECK: br %r14 + %ptr = getelementptr i64 *%dst, i64 -65537 + store i64 %val, i64 *%ptr + ret void +} + +; Check that STG allows an index. +define void @f7(i64 %dst, i64 %index, i64 %val) { +; CHECK: f7: +; CHECK: stg %r4, 524287({{%r3,%r2|%r2,%r3}}) +; CHECK: br %r14 + %add1 = add i64 %dst, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + store i64 %val, i64 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-move-08.ll b/test/CodeGen/SystemZ/int-move-08.ll new file mode 100644 index 000000000000..5640fec3299f --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-08.ll @@ -0,0 +1,49 @@ +; Test 32-bit GPR accesses to a PC-relative location. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@gsrc16 = global i16 1 +@gsrc32 = global i32 1 +@gdst16 = global i16 2 +@gdst32 = global i32 2 + +; Check sign-extending loads from i16. +define i32 @f1() { +; CHECK: f1: +; CHECK: lhrl %r2, gsrc16 +; CHECK: br %r14 + %val = load i16 *@gsrc16 + %ext = sext i16 %val to i32 + ret i32 %ext +} + +; Check zero-extending loads from i16. +define i32 @f2() { +; CHECK: f2: +; CHECK: llhrl %r2, gsrc16 +; CHECK: br %r14 + %val = load i16 *@gsrc16 + %ext = zext i16 %val to i32 + ret i32 %ext +} + +; Check truncating 16-bit stores. +define void @f3(i32 %val) { +; CHECK: f3: +; CHECK: sthrl %r2, gdst16 +; CHECK: br %r14 + %half = trunc i32 %val to i16 + store i16 %half, i16 *@gdst16 + ret void +} + +; Check plain loads and stores. +define void @f4() { +; CHECK: f4: +; CHECK: lrl %r0, gsrc32 +; CHECK: strl %r0, gdst32 +; CHECK: br %r14 + %val = load i32 *@gsrc32 + store i32 %val, i32 *@gdst32 + ret void +} diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll new file mode 100644 index 000000000000..a7a8c82951f5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-move-09.ll @@ -0,0 +1,81 @@ +; Test 64-bit GPR accesses to a PC-relative location. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@gsrc16 = global i16 1 +@gsrc32 = global i32 1 +@gsrc64 = global i64 1 +@gdst16 = global i16 2 +@gdst32 = global i32 2 +@gdst64 = global i64 2 + +; Check sign-extending loads from i16. +define i64 @f1() { +; CHECK: f1: +; CHECK: lghrl %r2, gsrc16 +; CHECK: br %r14 + %val = load i16 *@gsrc16 + %ext = sext i16 %val to i64 + ret i64 %ext +} + +; Check zero-extending loads from i16. +define i64 @f2() { +; CHECK: f2: +; CHECK: llghrl %r2, gsrc16 +; CHECK: br %r14 + %val = load i16 *@gsrc16 + %ext = zext i16 %val to i64 + ret i64 %ext +} + +; Check sign-extending loads from i32. +define i64 @f3() { +; CHECK: f3: +; CHECK: lgfrl %r2, gsrc32 +; CHECK: br %r14 + %val = load i32 *@gsrc32 + %ext = sext i32 %val to i64 + ret i64 %ext +} + +; Check zero-extending loads from i32. +define i64 @f4() { +; CHECK: f4: +; CHECK: llgfrl %r2, gsrc32 +; CHECK: br %r14 + %val = load i32 *@gsrc32 + %ext = zext i32 %val to i64 + ret i64 %ext +} + +; Check truncating 16-bit stores. +define void @f5(i64 %val) { +; CHECK: f5: +; CHECK: sthrl %r2, gdst16 +; CHECK: br %r14 + %half = trunc i64 %val to i16 + store i16 %half, i16 *@gdst16 + ret void +} + +; Check truncating 32-bit stores. +define void @f6(i64 %val) { +; CHECK: f6: +; CHECK: strl %r2, gdst32 +; CHECK: br %r14 + %word = trunc i64 %val to i32 + store i32 %word, i32 *@gdst32 + ret void +} + +; Check plain loads and stores. +define void @f7() { +; CHECK: f7: +; CHECK: lgrl %r0, gsrc64 +; CHECK: stgrl %r0, gdst64 +; CHECK: br %r14 + %val = load i64 *@gsrc64 + store i64 %val, i64 *@gdst64 + ret void +} diff --git a/test/CodeGen/SystemZ/int-mul-01.ll b/test/CodeGen/SystemZ/int-mul-01.ll new file mode 100644 index 000000000000..e1246e2156e3 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-01.ll @@ -0,0 +1,131 @@ +; Test 32-bit multiplication in which the second operand is a sign-extended +; i16 memory value. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the MH range. +define i32 @f1(i32 %lhs, i16 *%src) { +; CHECK: f1: +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %half = load i16 *%src + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned MH range. +define i32 @f2(i32 %lhs, i16 *%src) { +; CHECK: f2: +; CHECK: mh %r2, 4094(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2047 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which should use MHY instead of MH. +define i32 @f3(i32 %lhs, i16 *%src) { +; CHECK: f3: +; CHECK: mhy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2048 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned MHY range. +define i32 @f4(i32 %lhs, i16 *%src) { +; CHECK: f4: +; CHECK: mhy %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i32 %lhs, i16 *%src) { +; CHECK: f5: +; CHECK: agfi %r3, 524288 +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the negative aligned MHY range. +define i32 @f6(i32 %lhs, i16 *%src) { +; CHECK: f6: +; CHECK: mhy %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the low end of the MHY range. +define i32 @f7(i32 %lhs, i16 *%src) { +; CHECK: f7: +; CHECK: mhy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 %lhs, i16 *%src) { +; CHECK: f8: +; CHECK: agfi %r3, -524290 +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check that MH allows an index. +define i32 @f9(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check that MHY allows an index. +define i32 @f10(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/int-mul-02.ll b/test/CodeGen/SystemZ/int-mul-02.ll new file mode 100644 index 000000000000..d39c4dd0961c --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-02.ll @@ -0,0 +1,129 @@ +; Test 32-bit multiplication in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check MSR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: msr %r2, %r3 +; CHECK: br %r14 + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the low end of the MS range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: ms %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the high end of the aligned MS range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: ms %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the next word up, which should use MSY instead of MS. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: msy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the high end of the aligned MSY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: msy %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: ms %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the high end of the negative aligned MSY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: msy %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the low end of the MSY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: msy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: ms %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check that MS allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: ms %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check that MSY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: msy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %mul = mul i32 %a, %b + ret i32 %mul +} diff --git a/test/CodeGen/SystemZ/int-mul-03.ll b/test/CodeGen/SystemZ/int-mul-03.ll new file mode 100644 index 000000000000..ab4ef9edd235 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-03.ll @@ -0,0 +1,102 @@ +; Test multiplications between an i64 and a sign-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check MSGFR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK: msgfr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check MSGF with no displacement. +define i64 @f2(i64 %a, i32 *%src) { +; CHECK: f2: +; CHECK: msgf %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the aligned MSGF range. +define i64 @f3(i64 %a, i32 *%src) { +; CHECK: f3: +; CHECK: msgf %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i32 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: msgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the negative aligned MSGF range. +define i64 @f5(i64 %a, i32 *%src) { +; CHECK: f5: +; CHECK: msgf %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the low end of the MSGF range. +define i64 @f6(i64 %a, i32 *%src) { +; CHECK: f6: +; CHECK: msgf %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524292 +; CHECK: msgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check that MSGF allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: msgf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} diff --git a/test/CodeGen/SystemZ/int-mul-04.ll b/test/CodeGen/SystemZ/int-mul-04.ll new file mode 100644 index 000000000000..94c263978341 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-04.ll @@ -0,0 +1,94 @@ +; Test 64-bit addition in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check MSGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: msgr %r2, %r3 +; CHECK: br %r14 + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check MSG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: msg %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check the high end of the aligned MSG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: msg %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: msg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check the high end of the negative aligned MSG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: msg %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check the low end of the MSG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: msg %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: msg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Check that MSG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: msg %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %mul = mul i64 %a, %b + ret i64 %mul +} diff --git a/test/CodeGen/SystemZ/int-mul-05.ll b/test/CodeGen/SystemZ/int-mul-05.ll new file mode 100644 index 000000000000..5e4031b5d77d --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-05.ll @@ -0,0 +1,159 @@ +; Test 32-bit multiplication in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check multiplication by 2, which should use shifts. +define i32 @f1(i32 %a, i32 *%dest) { +; CHECK: f1: +; CHECK: sll %r2, 1 +; CHECK: br %r14 + %mul = mul i32 %a, 2 + ret i32 %mul +} + +; Check multiplication by 3. +define i32 @f2(i32 %a, i32 *%dest) { +; CHECK: f2: +; CHECK: mhi %r2, 3 +; CHECK: br %r14 + %mul = mul i32 %a, 3 + ret i32 %mul +} + +; Check the high end of the MHI range. +define i32 @f3(i32 %a, i32 *%dest) { +; CHECK: f3: +; CHECK: mhi %r2, 32767 +; CHECK: br %r14 + %mul = mul i32 %a, 32767 + ret i32 %mul +} + +; Check the next value up, which should use shifts. +define i32 @f4(i32 %a, i32 *%dest) { +; CHECK: f4: +; CHECK: sll %r2, 15 +; CHECK: br %r14 + %mul = mul i32 %a, 32768 + ret i32 %mul +} + +; Check the next value up again, which can use MSFI. +define i32 @f5(i32 %a, i32 *%dest) { +; CHECK: f5: +; CHECK: msfi %r2, 32769 +; CHECK: br %r14 + %mul = mul i32 %a, 32769 + ret i32 %mul +} + +; Check the high end of the MSFI range. +define i32 @f6(i32 %a, i32 *%dest) { +; CHECK: f6: +; CHECK: msfi %r2, 2147483647 +; CHECK: br %r14 + %mul = mul i32 %a, 2147483647 + ret i32 %mul +} + +; Check the next value up, which should use shifts. +define i32 @f7(i32 %a, i32 *%dest) { +; CHECK: f7: +; CHECK: sll %r2, 31 +; CHECK: br %r14 + %mul = mul i32 %a, 2147483648 + ret i32 %mul +} + +; Check the next value up again, which is treated as a negative value. +define i32 @f8(i32 %a, i32 *%dest) { +; CHECK: f8: +; CHECK: msfi %r2, -2147483647 +; CHECK: br %r14 + %mul = mul i32 %a, 2147483649 + ret i32 %mul +} + +; Check multiplication by -1, which is a negation. +define i32 @f9(i32 %a, i32 *%dest) { +; CHECK: f9: +; CHECK: lcr %r2, %r2 +; CHECK: br %r14 + %mul = mul i32 %a, -1 + ret i32 %mul +} + +; Check multiplication by -2, which should use shifts. +define i32 @f10(i32 %a, i32 *%dest) { +; CHECK: f10: +; CHECK: sll %r2, 1 +; CHECK: lcr %r2, %r2 +; CHECK: br %r14 + %mul = mul i32 %a, -2 + ret i32 %mul +} + +; Check multiplication by -3. +define i32 @f11(i32 %a, i32 *%dest) { +; CHECK: f11: +; CHECK: mhi %r2, -3 +; CHECK: br %r14 + %mul = mul i32 %a, -3 + ret i32 %mul +} + +; Check the lowest useful MHI value. +define i32 @f12(i32 %a, i32 *%dest) { +; CHECK: f12: +; CHECK: mhi %r2, -32767 +; CHECK: br %r14 + %mul = mul i32 %a, -32767 + ret i32 %mul +} + +; Check the next value down, which should use shifts. +define i32 @f13(i32 %a, i32 *%dest) { +; CHECK: f13: +; CHECK: sll %r2, 15 +; CHECK: lcr %r2, %r2 +; CHECK: br %r14 + %mul = mul i32 %a, -32768 + ret i32 %mul +} + +; Check the next value down again, which can use MSFI. +define i32 @f14(i32 %a, i32 *%dest) { +; CHECK: f14: +; CHECK: msfi %r2, -32769 +; CHECK: br %r14 + %mul = mul i32 %a, -32769 + ret i32 %mul +} + +; Check the lowest useful MSFI value. +define i32 @f15(i32 %a, i32 *%dest) { +; CHECK: f15: +; CHECK: msfi %r2, -2147483647 +; CHECK: br %r14 + %mul = mul i32 %a, -2147483647 + ret i32 %mul +} + +; Check the next value down, which should use shifts. +define i32 @f16(i32 %a, i32 *%dest) { +; CHECK: f16: +; CHECK: sll %r2, 31 +; CHECK-NOT: lcr +; CHECK: br %r14 + %mul = mul i32 %a, -2147483648 + ret i32 %mul +} + +; Check the next value down again, which is treated as a positive value. +define i32 @f17(i32 %a, i32 *%dest) { +; CHECK: f17: +; CHECK: msfi %r2, 2147483647 +; CHECK: br %r14 + %mul = mul i32 %a, -2147483649 + ret i32 %mul +} diff --git a/test/CodeGen/SystemZ/int-mul-06.ll b/test/CodeGen/SystemZ/int-mul-06.ll new file mode 100644 index 000000000000..a3546059c023 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-06.ll @@ -0,0 +1,159 @@ +; Test 64-bit multiplication in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check multiplication by 2, which should use shifts. +define i64 @f1(i64 %a, i64 *%dest) { +; CHECK: f1: +; CHECK: sllg %r2, %r2, 1 +; CHECK: br %r14 + %mul = mul i64 %a, 2 + ret i64 %mul +} + +; Check multiplication by 3. +define i64 @f2(i64 %a, i64 *%dest) { +; CHECK: f2: +; CHECK: mghi %r2, 3 +; CHECK: br %r14 + %mul = mul i64 %a, 3 + ret i64 %mul +} + +; Check the high end of the MGHI range. +define i64 @f3(i64 %a, i64 *%dest) { +; CHECK: f3: +; CHECK: mghi %r2, 32767 +; CHECK: br %r14 + %mul = mul i64 %a, 32767 + ret i64 %mul +} + +; Check the next value up, which should use shifts. +define i64 @f4(i64 %a, i64 *%dest) { +; CHECK: f4: +; CHECK: sllg %r2, %r2, 15 +; CHECK: br %r14 + %mul = mul i64 %a, 32768 + ret i64 %mul +} + +; Check the next value up again, which can use MSGFI. +define i64 @f5(i64 %a, i64 *%dest) { +; CHECK: f5: +; CHECK: msgfi %r2, 32769 +; CHECK: br %r14 + %mul = mul i64 %a, 32769 + ret i64 %mul +} + +; Check the high end of the MSGFI range. +define i64 @f6(i64 %a, i64 *%dest) { +; CHECK: f6: +; CHECK: msgfi %r2, 2147483647 +; CHECK: br %r14 + %mul = mul i64 %a, 2147483647 + ret i64 %mul +} + +; Check the next value up, which should use shifts. +define i64 @f7(i64 %a, i64 *%dest) { +; CHECK: f7: +; CHECK: sllg %r2, %r2, 31 +; CHECK: br %r14 + %mul = mul i64 %a, 2147483648 + ret i64 %mul +} + +; Check the next value up again, which cannot use a constant multiplicatoin. +define i64 @f8(i64 %a, i64 *%dest) { +; CHECK: f8: +; CHECK-NOT: msgfi +; CHECK: br %r14 + %mul = mul i64 %a, 2147483649 + ret i64 %mul +} + +; Check multiplication by -1, which is a negation. +define i64 @f9(i64 %a, i64 *%dest) { +; CHECK: f9: +; CHECK: lcgr {{%r[0-5]}}, %r2 +; CHECK: br %r14 + %mul = mul i64 %a, -1 + ret i64 %mul +} + +; Check multiplication by -2, which should use shifts. +define i64 @f10(i64 %a, i64 *%dest) { +; CHECK: f10: +; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 1 +; CHECK: lcgr %r2, [[SHIFTED]] +; CHECK: br %r14 + %mul = mul i64 %a, -2 + ret i64 %mul +} + +; Check multiplication by -3. +define i64 @f11(i64 %a, i64 *%dest) { +; CHECK: f11: +; CHECK: mghi %r2, -3 +; CHECK: br %r14 + %mul = mul i64 %a, -3 + ret i64 %mul +} + +; Check the lowest useful MGHI value. +define i64 @f12(i64 %a, i64 *%dest) { +; CHECK: f12: +; CHECK: mghi %r2, -32767 +; CHECK: br %r14 + %mul = mul i64 %a, -32767 + ret i64 %mul +} + +; Check the next value down, which should use shifts. +define i64 @f13(i64 %a, i64 *%dest) { +; CHECK: f13: +; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 15 +; CHECK: lcgr %r2, [[SHIFTED]] +; CHECK: br %r14 + %mul = mul i64 %a, -32768 + ret i64 %mul +} + +; Check the next value down again, which can use MSGFI. +define i64 @f14(i64 %a, i64 *%dest) { +; CHECK: f14: +; CHECK: msgfi %r2, -32769 +; CHECK: br %r14 + %mul = mul i64 %a, -32769 + ret i64 %mul +} + +; Check the lowest useful MSGFI value. +define i64 @f15(i64 %a, i64 *%dest) { +; CHECK: f15: +; CHECK: msgfi %r2, -2147483647 +; CHECK: br %r14 + %mul = mul i64 %a, -2147483647 + ret i64 %mul +} + +; Check the next value down, which should use shifts. +define i64 @f16(i64 %a, i64 *%dest) { +; CHECK: f16: +; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 31 +; CHECK: lcgr %r2, [[SHIFTED]] +; CHECK: br %r14 + %mul = mul i64 %a, -2147483648 + ret i64 %mul +} + +; Check the next value down again, which cannot use constant multiplication +define i64 @f17(i64 %a, i64 *%dest) { +; CHECK: f17: +; CHECK-NOT: msgfi +; CHECK: br %r14 + %mul = mul i64 %a, -2147483649 + ret i64 %mul +} diff --git a/test/CodeGen/SystemZ/int-mul-07.ll b/test/CodeGen/SystemZ/int-mul-07.ll new file mode 100644 index 000000000000..2459cc359930 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-07.ll @@ -0,0 +1,64 @@ +; Test high-part i32->i64 multiplications. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; We don't provide *MUL_LOHI or MULH* for the patterns in this file, +; but they should at least still work. + +; Check zero-extended multiplication in which only the high part is used. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: msgr +; CHECK: br %r14 + %ax = zext i32 %a to i64 + %bx = zext i32 %b to i64 + %mulx = mul i64 %ax, %bx + %highx = lshr i64 %mulx, 32 + %high = trunc i64 %highx to i32 + ret i32 %high +} + +; Check sign-extended multiplication in which only the high part is used. +define i32 @f2(i32 %a, i32 %b) { +; CHECK: f2: +; CHECK: msgfr +; CHECK: br %r14 + %ax = sext i32 %a to i64 + %bx = sext i32 %b to i64 + %mulx = mul i64 %ax, %bx + %highx = lshr i64 %mulx, 32 + %high = trunc i64 %highx to i32 + ret i32 %high +} + +; Check zero-extended multiplication in which the result is split into +; high and low halves. +define i32 @f3(i32 %a, i32 %b) { +; CHECK: f3: +; CHECK: msgr +; CHECK: br %r14 + %ax = zext i32 %a to i64 + %bx = zext i32 %b to i64 + %mulx = mul i64 %ax, %bx + %highx = lshr i64 %mulx, 32 + %high = trunc i64 %highx to i32 + %low = trunc i64 %mulx to i32 + %or = or i32 %high, %low + ret i32 %or +} + +; Check sign-extended multiplication in which the result is split into +; high and low halves. +define i32 @f4(i32 %a, i32 %b) { +; CHECK: f4: +; CHECK: msgfr +; CHECK: br %r14 + %ax = sext i32 %a to i64 + %bx = sext i32 %b to i64 + %mulx = mul i64 %ax, %bx + %highx = lshr i64 %mulx, 32 + %high = trunc i64 %highx to i32 + %low = trunc i64 %mulx to i32 + %or = or i32 %high, %low + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/int-mul-08.ll b/test/CodeGen/SystemZ/int-mul-08.ll new file mode 100644 index 000000000000..09ebe7a7b489 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-08.ll @@ -0,0 +1,188 @@ +; Test high-part i64->i128 multiplications. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check zero-extended multiplication in which only the high part is used. +define i64 @f1(i64 %dummy, i64 %a, i64 %b) { +; CHECK: f1: +; CHECK-NOT: {{%r[234]}} +; CHECK: mlgr %r2, %r4 +; CHECK: br %r14 + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check sign-extended multiplication in which only the high part is used. +; This needs a rather convoluted sequence. +define i64 @f2(i64 %dummy, i64 %a, i64 %b) { +; CHECK: f2: +; CHECK: mlgr +; CHECK: agr +; CHECK: agr +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check zero-extended multiplication in which only part of the high half +; is used. +define i64 @f3(i64 %dummy, i64 %a, i64 %b) { +; CHECK: f3: +; CHECK-NOT: {{%r[234]}} +; CHECK: mlgr %r2, %r4 +; CHECK: srlg %r2, %r2, 3 +; CHECK: br %r14 + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 67 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check zero-extended multiplication in which the result is split into +; high and low halves. +define i64 @f4(i64 %dummy, i64 %a, i64 %b) { +; CHECK: f4: +; CHECK-NOT: {{%r[234]}} +; CHECK: mlgr %r2, %r4 +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + %low = trunc i128 %mulx to i64 + %or = or i64 %high, %low + ret i64 %or +} + +; Check division by a constant, which should use multiplication instead. +define i64 @f5(i64 %dummy, i64 %a) { +; CHECK: f5: +; CHECK: mlgr %r2, +; CHECK: srlg %r2, %r2, +; CHECK: br %r14 + %res = udiv i64 %a, 1234 + ret i64 %res +} + +; Check MLG with no displacement. +define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK-NOT: {{%r[234]}} +; CHECK: mlg %r2, 0(%r4) +; CHECK: br %r14 + %b = load i64 *%src + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the aligned MLG range. +define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: mlg %r2, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword up, which requires separate address logic. +; Other sequences besides this one would be OK. +define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f8: +; CHECK: agfi %r4, 524288 +; CHECK: mlg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the negative aligned MLG range. +define i64 @f9(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f9: +; CHECK: mlg %r2, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the low end of the MLG range. +define i64 @f10(i64 %dummy, i64 %a, i64 *%src) { +; CHECK: f10: +; CHECK: mlg %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f11(i64 *%dest, i64 %a, i64 *%src) { +; CHECK: f11: +; CHECK: agfi %r4, -524296 +; CHECK: mlg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check that MLG allows an index. +define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: mlg %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %ax = zext i64 %a to i128 + %bx = zext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} diff --git a/test/CodeGen/SystemZ/int-neg-01.ll b/test/CodeGen/SystemZ/int-neg-01.ll new file mode 100644 index 000000000000..6114f4efbc9a --- /dev/null +++ b/test/CodeGen/SystemZ/int-neg-01.ll @@ -0,0 +1,42 @@ +; Test integer negation. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test i32->i32 negation. +define i32 @f1(i32 %val) { +; CHECK: f1: +; CHECK: lcr %r2, %r2 +; CHECK: br %r14 + %neg = sub i32 0, %val + ret i32 %neg +} + +; Test i32->i64 negation. +define i64 @f2(i32 %val) { +; CHECK: f2: +; CHECK: lcgfr %r2, %r2 +; CHECK: br %r14 + %ext = sext i32 %val to i64 + %neg = sub i64 0, %ext + ret i64 %neg +} + +; Test i32->i64 negation that uses an "in-register" form of sign extension. +define i64 @f3(i64 %val) { +; CHECK: f3: +; CHECK: lcgfr %r2, %r2 +; CHECK: br %r14 + %trunc = trunc i64 %val to i32 + %ext = sext i32 %trunc to i64 + %neg = sub i64 0, %ext + ret i64 %neg +} + +; Test i64 negation. +define i64 @f4(i64 %val) { +; CHECK: f4: +; CHECK: lcgr %r2, %r2 +; CHECK: br %r14 + %neg = sub i64 0, %val + ret i64 %neg +} diff --git a/test/CodeGen/SystemZ/int-sub-01.ll b/test/CodeGen/SystemZ/int-sub-01.ll new file mode 100644 index 000000000000..9a738148f7ef --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-01.ll @@ -0,0 +1,129 @@ +; Test 32-bit subtraction. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check SR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: sr %r2, %r3 +; CHECK: br %r14 + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the low end of the S range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: s %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the high end of the aligned S range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: s %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the next word up, which should use SY instead of S. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: sy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the high end of the aligned SY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: sy %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: s %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the high end of the negative aligned SY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: sy %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the low end of the SY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: sy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: s %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check that S allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: s %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} + +; Check that SY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: sy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %sub = sub i32 %a, %b + ret i32 %sub +} diff --git a/test/CodeGen/SystemZ/int-sub-02.ll b/test/CodeGen/SystemZ/int-sub-02.ll new file mode 100644 index 000000000000..5150a960a554 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-02.ll @@ -0,0 +1,102 @@ +; Test subtractions of a sign-extended i32 from an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check SGFR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK: sgfr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check SGF with no displacement. +define i64 @f2(i64 %a, i32 *%src) { +; CHECK: f2: +; CHECK: sgf %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the aligned SGF range. +define i64 @f3(i64 %a, i32 *%src) { +; CHECK: f3: +; CHECK: sgf %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i32 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: sgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the negative aligned SGF range. +define i64 @f5(i64 %a, i32 *%src) { +; CHECK: f5: +; CHECK: sgf %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the low end of the SGF range. +define i64 @f6(i64 %a, i32 *%src) { +; CHECK: f6: +; CHECK: sgf %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524292 +; CHECK: sgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check that SGF allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: sgf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = sext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} diff --git a/test/CodeGen/SystemZ/int-sub-03.ll b/test/CodeGen/SystemZ/int-sub-03.ll new file mode 100644 index 000000000000..73571b3591f5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-03.ll @@ -0,0 +1,102 @@ +; Test subtractions of a zero-extended i32 from an i64. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check SLGFR. +define i64 @f1(i64 %a, i32 %b) { +; CHECK: f1: +; CHECK: slgfr %r2, %r3 +; CHECK: br %r14 + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check SLGF with no displacement. +define i64 @f2(i64 %a, i32 *%src) { +; CHECK: f2: +; CHECK: slgf %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the aligned SLGF range. +define i64 @f3(i64 %a, i32 *%src) { +; CHECK: f3: +; CHECK: slgf %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i32 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: slgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the negative aligned SLGF range. +define i64 @f5(i64 %a, i32 *%src) { +; CHECK: f5: +; CHECK: slgf %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the low end of the SLGF range. +define i64 @f6(i64 %a, i32 *%src) { +; CHECK: f6: +; CHECK: slgf %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i32 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524292 +; CHECK: slgf %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check that SLGF allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = zext i32 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} diff --git a/test/CodeGen/SystemZ/int-sub-04.ll b/test/CodeGen/SystemZ/int-sub-04.ll new file mode 100644 index 000000000000..545d34216809 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-04.ll @@ -0,0 +1,94 @@ +; Test 64-bit subtraction in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check SGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: sgr %r2, %r3 +; CHECK: br %r14 + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check SG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: sg %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check the high end of the aligned SG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: sg %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: sg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check the high end of the negative aligned SG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: sg %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check the low end of the SG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: sg %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: sg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} + +; Check that SG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %sub = sub i64 %a, %b + ret i64 %sub +} diff --git a/test/CodeGen/SystemZ/int-sub-05.ll b/test/CodeGen/SystemZ/int-sub-05.ll new file mode 100644 index 000000000000..1475b244f678 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-05.ll @@ -0,0 +1,118 @@ +; Test 128-bit addition in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Test register addition. +define void @f1(i128 *%ptr, i64 %high, i64 %low) { +; CHECK: f1: +; CHECK: slgr {{%r[0-5]}}, %r4 +; CHECK: slbgr {{%r[0-5]}}, %r3 +; CHECK: br %r14 + %a = load i128 *%ptr + %highx = zext i64 %high to i128 + %lowx = zext i64 %low to i128 + %bhigh = shl i128 %highx, 64 + %b = or i128 %bhigh, %lowx + %sub = sub i128 %a, %b + store i128 %sub, i128 *%ptr + ret void +} + +; Test memory addition with no offset. +define void @f2(i64 %addr) { +; CHECK: f2: +; CHECK: slg {{%r[0-5]}}, 8(%r2) +; CHECK: slbg {{%r[0-5]}}, 0(%r2) +; CHECK: br %r14 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} + +; Test the highest aligned offset that is in range of both SLG and SLBG. +define void @f3(i64 %base) { +; CHECK: f3: +; CHECK: slg {{%r[0-5]}}, 524280(%r2) +; CHECK: slbg {{%r[0-5]}}, 524272(%r2) +; CHECK: br %r14 + %addr = add i64 %base, 524272 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} + +; Test the next doubleword up, which requires separate address logic for SLG. +define void @f4(i64 %base) { +; CHECK: f4: +; CHECK: lgr [[BASE:%r[1-5]]], %r2 +; CHECK: agfi [[BASE]], 524288 +; CHECK: slg {{%r[0-5]}}, 0([[BASE]]) +; CHECK: slbg {{%r[0-5]}}, 524280(%r2) +; CHECK: br %r14 + %addr = add i64 %base, 524280 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} + +; Test the next doubleword after that, which requires separate logic for +; both instructions. It would be better to create an anchor at 524288 +; that both instructions can use, but that isn't implemented yet. +define void @f5(i64 %base) { +; CHECK: f5: +; CHECK: slg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: br %r14 + %addr = add i64 %base, 524288 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} + +; Test the lowest displacement that is in range of both SLG and SLBG. +define void @f6(i64 %base) { +; CHECK: f6: +; CHECK: slg {{%r[0-5]}}, -524280(%r2) +; CHECK: slbg {{%r[0-5]}}, -524288(%r2) +; CHECK: br %r14 + %addr = add i64 %base, -524288 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} + +; Test the next doubleword down, which is out of range of the SLBG. +define void @f7(i64 %base) { +; CHECK: f7: +; CHECK: slg {{%r[0-5]}}, -524288(%r2) +; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}}) +; CHECK: br %r14 + %addr = add i64 %base, -524296 + %bptr = inttoptr i64 %addr to i128 * + %aptr = getelementptr i128 *%bptr, i64 -8 + %a = load i128 *%aptr + %b = load i128 *%bptr + %sub = sub i128 %a, %b + store i128 %sub, i128 *%aptr + ret void +} diff --git a/test/CodeGen/SystemZ/int-sub-06.ll b/test/CodeGen/SystemZ/int-sub-06.ll new file mode 100644 index 000000000000..0e04d51e2bc7 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-06.ll @@ -0,0 +1,165 @@ +; Test 128-bit addition in which the second operand is a zero-extended i32. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check register additions. The XOR ensures that we don't instead zero-extend +; %b into a register and use memory addition. +define void @f1(i128 *%aptr, i32 %b) { +; CHECK: f1: +; CHECK: slgfr {{%r[0-5]}}, %r3 +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Like f1, but using an "in-register" extension. +define void @f2(i128 *%aptr, i64 %b) { +; CHECK: f2: +; CHECK: slgfr {{%r[0-5]}}, %r3 +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %trunc = trunc i64 %b to i32 + %bext = zext i32 %trunc to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Test register addition in cases where the second operand is zero extended +; from i64 rather than i32, but is later masked to i32 range. +define void @f3(i128 *%aptr, i64 %b) { +; CHECK: f3: +; CHECK: slgfr {{%r[0-5]}}, %r3 +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %bext = zext i64 %b to i128 + %and = and i128 %bext, 4294967295 + %sub = sub i128 %xor, %and + store i128 %sub, i128 *%aptr + ret void +} + +; Test SLGF with no offset. +define void @f4(i128 *%aptr, i32 *%bsrc) { +; CHECK: f4: +; CHECK: slgf {{%r[0-5]}}, 0(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %b = load i32 *%bsrc + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check the high end of the SLGF range. +define void @f5(i128 *%aptr, i32 *%bsrc) { +; CHECK: f5: +; CHECK: slgf {{%r[0-5]}}, 524284(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i64 131071 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check the next word up, which must use separate address logic. +; Other sequences besides this one would be OK. +define void @f6(i128 *%aptr, i32 *%bsrc) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: slgf {{%r[0-5]}}, 0(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i64 131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check the high end of the negative aligned SLGF range. +define void @f7(i128 *%aptr, i32 *%bsrc) { +; CHECK: f7: +; CHECK: slgf {{%r[0-5]}}, -4(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -1 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check the low end of the SLGF range. +define void @f8(i128 *%aptr, i32 *%bsrc) { +; CHECK: f8: +; CHECK: slgf {{%r[0-5]}}, -524288(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -131072 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f9(i128 *%aptr, i32 *%bsrc) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: slgf {{%r[0-5]}}, 0(%r3) +; CHECK: slbgr +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %ptr = getelementptr i32 *%bsrc, i128 -131073 + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} + +; Check that SLGF allows an index. +define void @f10(i128 *%aptr, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %a = load i128 *%aptr + %xor = xor i128 %a, 127 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %bext = zext i32 %b to i128 + %sub = sub i128 %xor, %bext + store i128 %sub, i128 *%aptr + ret void +} diff --git a/test/CodeGen/SystemZ/la-01.ll b/test/CodeGen/SystemZ/la-01.ll new file mode 100644 index 000000000000..b43e3f8662dc --- /dev/null +++ b/test/CodeGen/SystemZ/la-01.ll @@ -0,0 +1,80 @@ +; Test loads of symbolic addresses when generating small-model non-PIC. +; All addresses can be treated as PC +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +@e4 = external global i32 +@d4 = global i32 1 +@e2 = external global i32, align 2 +@d2 = global i32 1, align 2 +@e1 = external global i32, align 1 +@d1 = global i32 1, align 1 + +declare void @ef() +define void @df() { + ret void +} + +; Test a load of a fully-aligned external variable. +define i32 *@f1() { +; CHECK: f1: +; CHECK: larl %r2, e4 +; CHECK-NEXT: br %r14 + ret i32 *@e4 +} + +; Test a load of a fully-aligned local variable. +define i32 *@f2() { +; CHECK: f2: +; CHECK: larl %r2, d4 +; CHECK-NEXT: br %r14 + ret i32 *@d4 +} + +; Test a load of a 2-byte-aligned external variable. +define i32 *@f3() { +; CHECK: f3: +; CHECK: larl %r2, e2 +; CHECK-NEXT: br %r14 + ret i32 *@e2 +} + +; Test a load of a 2-byte-aligned local variable. +define i32 *@f4() { +; CHECK: f4: +; CHECK: larl %r2, d2 +; CHECK-NEXT: br %r14 + ret i32 *@d2 +} + +; Test a load of an unaligned external variable, which must go via the GOT. +define i32 *@f5() { +; CHECK: f5: +; CHECK: lgrl %r2, e1@GOT +; CHECK-NEXT: br %r14 + ret i32 *@e1 +} + +; Test a load of an unaligned local variable, which must go via the GOT. +define i32 *@f6() { +; CHECK: f6: +; CHECK: lgrl %r2, d1@GOT +; CHECK-NEXT: br %r14 + ret i32 *@d1 +} + +; Test a load of an external function. +define void() *@f7() { +; CHECK: f7: +; CHECK: larl %r2, ef +; CHECK-NEXT: br %r14 + ret void() *@ef +} + +; Test a load of a local function. +define void() *@f8() { +; CHECK: f8: +; CHECK: larl %r2, df +; CHECK-NEXT: br %r14 + ret void() *@df +} diff --git a/test/CodeGen/SystemZ/la-02.ll b/test/CodeGen/SystemZ/la-02.ll new file mode 100644 index 000000000000..4c5374a0925b --- /dev/null +++ b/test/CodeGen/SystemZ/la-02.ll @@ -0,0 +1,87 @@ +; Test loads of symbolic addresses when generating medium- and +; large-model non-PIC. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -code-model=medium | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -code-model=large | FileCheck %s + +@ev = external global i32 +@dv = global i32 0 +@pv = protected global i32 0 +@hv = hidden global i32 0 + +declare void @ef() +define void @df() { + ret void +} +define protected void @pf() { + ret void +} +define hidden void @hf() { + ret void +} + +; Test loads of external variables. There is no guarantee that the +; variable will be in range of LARL. +define i32 *@f1() { +; CHECK: f1: +; CHECK: lgrl %r2, ev@GOT +; CHECK: br %r14 + ret i32 *@ev +} + +; ...likewise locally-defined normal-visibility variables. +define i32 *@f2() { +; CHECK: f2: +; CHECK: lgrl %r2, dv@GOT +; CHECK: br %r14 + ret i32 *@dv +} + +; ...likewise protected variables. +define i32 *@f3() { +; CHECK: f3: +; CHECK: lgrl %r2, pv@GOT +; CHECK: br %r14 + ret i32 *@pv +} + +; ...likewise hidden variables. +define i32 *@f4() { +; CHECK: f4: +; CHECK: lgrl %r2, hv@GOT +; CHECK: br %r14 + ret i32 *@hv +} + +; Check loads of external functions. This could use LARL, but we don't have +; code to detect that yet. +define void() *@f5() { +; CHECK: f5: +; CHECK: lgrl %r2, ef@GOT +; CHECK: br %r14 + ret void() *@ef +} + +; ...likewise locally-defined normal-visibility functions. +define void() *@f6() { +; CHECK: f6: +; CHECK: lgrl %r2, df@GOT +; CHECK: br %r14 + ret void() *@df +} + +; ...likewise protected functions. +define void() *@f7() { +; CHECK: f7: +; CHECK: lgrl %r2, pf@GOT +; CHECK: br %r14 + ret void() *@pf +} + +; ...likewise hidden functions. +define void() *@f8() { +; CHECK: f8: +; CHECK: lgrl %r2, hf@GOT +; CHECK: br %r14 + ret void() *@hf +} diff --git a/test/CodeGen/SystemZ/la-03.ll b/test/CodeGen/SystemZ/la-03.ll new file mode 100644 index 000000000000..9449b2bfbec0 --- /dev/null +++ b/test/CodeGen/SystemZ/la-03.ll @@ -0,0 +1,85 @@ +; Test loads of symbolic addresses in PIC code. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck %s + +@ev = external global i32 +@dv = global i32 0 +@pv = protected global i32 0 +@hv = hidden global i32 0 + +declare void @ef() +define void @df() { + ret void +} +define protected void @pf() { + ret void +} +define hidden void @hf() { + ret void +} + +; Test loads of external variables, which must go via the GOT. +define i32 *@f1() { +; CHECK: f1: +; CHECK: lgrl %r2, ev@GOT +; CHECK: br %r14 + ret i32 *@ev +} + +; Check loads of locally-defined normal-visibility variables, which might +; be overridden. The load must go via the GOT. +define i32 *@f2() { +; CHECK: f2: +; CHECK: lgrl %r2, dv@GOT +; CHECK: br %r14 + ret i32 *@dv +} + +; Check loads of protected variables, which in the small code model +; must be in range of LARL. +define i32 *@f3() { +; CHECK: f3: +; CHECK: larl %r2, pv +; CHECK: br %r14 + ret i32 *@pv +} + +; ...likewise hidden variables. +define i32 *@f4() { +; CHECK: f4: +; CHECK: larl %r2, hv +; CHECK: br %r14 + ret i32 *@hv +} + +; Like f1, but for functions. +define void() *@f5() { +; CHECK: f5: +; CHECK: lgrl %r2, ef@GOT +; CHECK: br %r14 + ret void() *@ef +} + +; Like f2, but for functions. +define void() *@f6() { +; CHECK: f6: +; CHECK: lgrl %r2, df@GOT +; CHECK: br %r14 + ret void() *@df +} + +; Like f3, but for functions. +define void() *@f7() { +; CHECK: f7: +; CHECK: larl %r2, pf +; CHECK: br %r14 + ret void() *@pf +} + +; Like f4, but for functions. +define void() *@f8() { +; CHECK: f8: +; CHECK: larl %r2, hf +; CHECK: br %r14 + ret void() *@hf +} diff --git a/test/CodeGen/SystemZ/la-04.ll b/test/CodeGen/SystemZ/la-04.ll new file mode 100644 index 000000000000..4c3636481e7d --- /dev/null +++ b/test/CodeGen/SystemZ/la-04.ll @@ -0,0 +1,18 @@ +; Test blockaddress. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Do some arbitrary work and return the address of the following label. +define i8 *@f1(i8 *%addr) { +; CHECK: f1: +; CHECK: mvi 0(%r2), 1 +; CHECK: [[LABEL:\.L.*]]: +; CHECK: larl %r2, [[LABEL]] +; CHECK: br %r14 +entry: + store i8 1, i8 *%addr + br label %b.lab + +b.lab: + ret i8 *blockaddress(@f1, %b.lab) +} diff --git a/test/CodeGen/SystemZ/lit.local.cfg b/test/CodeGen/SystemZ/lit.local.cfg new file mode 100644 index 000000000000..79528d178f23 --- /dev/null +++ b/test/CodeGen/SystemZ/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'SystemZ' in targets: + config.unsupported = True + diff --git a/test/CodeGen/SystemZ/or-01.ll b/test/CodeGen/SystemZ/or-01.ll new file mode 100644 index 000000000000..20c93129efca --- /dev/null +++ b/test/CodeGen/SystemZ/or-01.ll @@ -0,0 +1,129 @@ +; Test 32-bit ORs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check OR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: or %r2, %r3 +; CHECK: br %r14 + %or = or i32 %a, %b + ret i32 %or +} + +; Check the low end of the O range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: o %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %or = or i32 %a, %b + ret i32 %or +} + +; Check the high end of the aligned O range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: o %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the next word up, which should use OY instead of O. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: oy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the high end of the aligned OY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: oy %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: o %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the high end of the negative aligned OY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: oy %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the low end of the OY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: oy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: o %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check that O allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: o %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} + +; Check that OY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: oy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %or = or i32 %a, %b + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/or-02.ll b/test/CodeGen/SystemZ/or-02.ll new file mode 100644 index 000000000000..377a3e604c60 --- /dev/null +++ b/test/CodeGen/SystemZ/or-02.ll @@ -0,0 +1,66 @@ +; Test 32-bit ORs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful OILL value. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: oill %r2, 1 +; CHECK: br %r14 + %or = or i32 %a, 1 + ret i32 %or +} + +; Check the high end of the OILL range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: oill %r2, 65535 +; CHECK: br %r14 + %or = or i32 %a, 65535 + ret i32 %or +} + +; Check the lowest useful OILH range, which is the next value up. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: oilh %r2, 1 +; CHECK: br %r14 + %or = or i32 %a, 65536 + ret i32 %or +} + +; Check the lowest useful OILF value, which is the next value up again. +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: oilf %r2, 65537 +; CHECK: br %r14 + %or = or i32 %a, 65537 + ret i32 %or +} + +; Check the high end of the OILH range. +define i32 @f5(i32 %a) { +; CHECK: f5: +; CHECK: oilh %r2, 65535 +; CHECK: br %r14 + %or = or i32 %a, -65536 + ret i32 %or +} + +; Check the next value up, which must use OILF instead. +define i32 @f6(i32 %a) { +; CHECK: f6: +; CHECK: oilf %r2, 4294901761 +; CHECK: br %r14 + %or = or i32 %a, -65535 + ret i32 %or +} + +; Check the highest useful OILF value. +define i32 @f7(i32 %a) { +; CHECK: f7: +; CHECK: oilf %r2, 4294967294 +; CHECK: br %r14 + %or = or i32 %a, -2 + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/or-03.ll b/test/CodeGen/SystemZ/or-03.ll new file mode 100644 index 000000000000..16f84f1635a8 --- /dev/null +++ b/test/CodeGen/SystemZ/or-03.ll @@ -0,0 +1,94 @@ +; Test 64-bit ORs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check OGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %or = or i64 %a, %b + ret i64 %or +} + +; Check OG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: og %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %or = or i64 %a, %b + ret i64 %or +} + +; Check the high end of the aligned OG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: og %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: og %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} + +; Check the high end of the negative aligned OG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: og %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} + +; Check the low end of the OG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: og %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: og %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} + +; Check that OG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %or = or i64 %a, %b + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/or-04.ll b/test/CodeGen/SystemZ/or-04.ll new file mode 100644 index 000000000000..a8278423981a --- /dev/null +++ b/test/CodeGen/SystemZ/or-04.ll @@ -0,0 +1,182 @@ +; Test 64-bit ORs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful OILL value. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: oill %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 1 + ret i64 %or +} + +; Check the high end of the OILL range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: oill %r2, 65535 +; CHECK: br %r14 + %or = or i64 %a, 65535 + ret i64 %or +} + +; Check the lowest useful OILH value, which is the next value up. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: oilh %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 65536 + ret i64 %or +} + +; Check the lowest useful OILF value, which is the next value up again. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK: oilf %r2, 4294901759 +; CHECK: br %r14 + %or = or i64 %a, 4294901759 + ret i64 %or +} + +; Check the high end of the OILH range. +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK: oilh %r2, 65535 +; CHECK: br %r14 + %or = or i64 %a, 4294901760 + ret i64 %or +} + +; Check the high end of the OILF range. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK: oilf %r2, 4294967295 +; CHECK: br %r14 + %or = or i64 %a, 4294967295 + ret i64 %or +} + +; Check the lowest useful OIHL value, which is the next value up. +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK: oihl %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 4294967296 + ret i64 %or +} + +; Check the next value up again, which must use two ORs. +define i64 @f8(i64 %a) { +; CHECK: f8: +; CHECK: oihl %r2, 1 +; CHECK: oill %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 4294967297 + ret i64 %or +} + +; Check the high end of the OILL range. +define i64 @f9(i64 %a) { +; CHECK: f9: +; CHECK: oihl %r2, 1 +; CHECK: oill %r2, 65535 +; CHECK: br %r14 + %or = or i64 %a, 4295032831 + ret i64 %or +} + +; Check the next value up, which must use OILH +define i64 @f10(i64 %a) { +; CHECK: f10: +; CHECK: oihl %r2, 1 +; CHECK: oilh %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 4295032832 + ret i64 %or +} + +; Check the next value up again, which must use OILF +define i64 @f11(i64 %a) { +; CHECK: f11: +; CHECK: oihl %r2, 1 +; CHECK: oilf %r2, 65537 +; CHECK: br %r14 + %or = or i64 %a, 4295032833 + ret i64 %or +} + +; Check the high end of the OIHL range. +define i64 @f12(i64 %a) { +; CHECK: f12: +; CHECK: oihl %r2, 65535 +; CHECK: br %r14 + %or = or i64 %a, 281470681743360 + ret i64 %or +} + +; Check a combination of the high end of the OIHL range and the high end +; of the OILF range. +define i64 @f13(i64 %a) { +; CHECK: f13: +; CHECK: oihl %r2, 65535 +; CHECK: oilf %r2, 4294967295 +; CHECK: br %r14 + %or = or i64 %a, 281474976710655 + ret i64 %or +} + +; Check the lowest useful OIHH value. +define i64 @f14(i64 %a) { +; CHECK: f14: +; CHECK: oihh %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 281474976710656 + ret i64 %or +} + +; Check the next value up, which needs two ORs. +define i64 @f15(i64 %a) { +; CHECK: f15: +; CHECK: oihh %r2, 1 +; CHECK: oill %r2, 1 +; CHECK: br %r14 + %or = or i64 %a, 281474976710657 + ret i64 %or +} + +; Check the lowest useful OIHF value. +define i64 @f16(i64 %a) { +; CHECK: f16: +; CHECK: oihf %r2, 65537 +; CHECK: br %r14 + %or = or i64 %a, 281479271677952 + ret i64 %or +} + +; Check the high end of the OIHH range. +define i64 @f17(i64 %a) { +; CHECK: f17: +; CHECK: oihh %r2, 65535 +; CHECK: br %r14 + %or = or i64 %a, 18446462598732840960 + ret i64 %or +} + +; Check the high end of the OIHF range. +define i64 @f18(i64 %a) { +; CHECK: f18: +; CHECK: oihf %r2, 4294967295 +; CHECK: br %r14 + %or = or i64 %a, -4294967296 + ret i64 %or +} + +; Check the highest useful OR value. +define i64 @f19(i64 %a) { +; CHECK: f19: +; CHECK: oihf %r2, 4294967295 +; CHECK: oilf %r2, 4294967294 +; CHECK: br %r14 + %or = or i64 %a, -2 + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/or-05.ll b/test/CodeGen/SystemZ/or-05.ll new file mode 100644 index 000000000000..9b6c10d4b5ce --- /dev/null +++ b/test/CodeGen/SystemZ/or-05.ll @@ -0,0 +1,165 @@ +; Test ORs of a constant into a byte of memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful constant, expressed as a signed integer. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: oi 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %or = or i8 %val, -255 + store i8 %or, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a signed integer. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %or = or i8 %val, -2 + store i8 %or, i8 *%ptr + ret void +} + +; Check the lowest useful constant, expressed as an unsigned integer. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: oi 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %or = or i8 %val, 1 + store i8 %or, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a unsigned integer. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %or = or i8 %val, 254 + store i8 %or, i8 *%ptr + ret void +} + +; Check the high end of the OI range. +define void @f5(i8 *%src) { +; CHECK: f5: +; CHECK: oi 4095(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the next byte up, which should use OIY instead of OI. +define void @f6(i8 *%src) { +; CHECK: f6: +; CHECK: oiy 4096(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the high end of the OIY range. +define void @f7(i8 *%src) { +; CHECK: f7: +; CHECK: oiy 524287(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i8 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, 524288 +; CHECK: oi 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the high end of the negative OIY range. +define void @f9(i8 *%src) { +; CHECK: f9: +; CHECK: oiy -1(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the low end of the OIY range. +define void @f10(i8 *%src) { +; CHECK: f10: +; CHECK: oiy -524288(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f11(i8 *%src) { +; CHECK: f11: +; CHECK: agfi %r2, -524289 +; CHECK: oi 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check that OI does not allow an index +define void @f12(i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: agr %r2, %r3 +; CHECK: oi 4095(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} + +; Check that OIY does not allow an index +define void @f13(i64 %src, i64 %index) { +; CHECK: f13: +; CHECK: agr %r2, %r3 +; CHECK: oiy 4096(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %or = or i8 %val, 127 + store i8 %or, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/or-06.ll b/test/CodeGen/SystemZ/or-06.ll new file mode 100644 index 000000000000..a24a18a191f1 --- /dev/null +++ b/test/CodeGen/SystemZ/or-06.ll @@ -0,0 +1,108 @@ +; Test that we can use OI for byte operations that are expressed as i32 +; or i64 operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Zero extension to 32 bits, negative constant. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %or = or i32 %ext, -2 + %trunc = trunc i32 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, negative constant. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %or = or i64 %ext, -2 + %trunc = trunc i64 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 32 bits, positive constant. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %or = or i32 %ext, 254 + %trunc = trunc i32 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, positive constant. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %or = or i64 %ext, 254 + %trunc = trunc i64 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, negative constant. +define void @f5(i8 *%ptr) { +; CHECK: f5: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %or = or i32 %ext, -2 + %trunc = trunc i32 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, negative constant. +define void @f6(i8 *%ptr) { +; CHECK: f6: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %or = or i64 %ext, -2 + %trunc = trunc i64 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, positive constant. +define void @f7(i8 *%ptr) { +; CHECK: f7: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %or = or i32 %ext, 254 + %trunc = trunc i32 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, positive constant. +define void @f8(i8 *%ptr) { +; CHECK: f8: +; CHECK: oi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %or = or i64 %ext, 254 + %trunc = trunc i64 %or to i8 + store i8 %trunc, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/shift-01.ll b/test/CodeGen/SystemZ/shift-01.ll new file mode 100644 index 000000000000..e5a459aaa828 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-01.ll @@ -0,0 +1,114 @@ +; Test 32-bit shifts left. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SLL range. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: sll %r2, 1 +; CHECK: br %r14 + %shift = shl i32 %a, 1 + ret i32 %shift +} + +; Check the high end of the defined SLL range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: sll %r2, 31 +; CHECK: br %r14 + %shift = shl i32 %a, 31 + ret i32 %shift +} + +; We don't generate shifts by out-of-range values. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK-NOT: sll %r2, 32 +; CHECK: br %r14 + %shift = shl i32 %a, 32 + ret i32 %shift +} + +; Make sure that we don't generate negative shift amounts. +define i32 @f4(i32 %a, i32 %amt) { +; CHECK: f4: +; CHECK-NOT: sll %r2, -1{{.*}} +; CHECK: br %r14 + %sub = sub i32 %amt, 1 + %shift = shl i32 %a, %sub + ret i32 %shift +} + +; Check variable shifts. +define i32 @f5(i32 %a, i32 %amt) { +; CHECK: f5: +; CHECK: sll %r2, 0(%r3) +; CHECK: br %r14 + %shift = shl i32 %a, %amt + ret i32 %shift +} + +; Check shift amounts that have a constant term. +define i32 @f6(i32 %a, i32 %amt) { +; CHECK: f6: +; CHECK: sll %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %shift = shl i32 %a, %add + ret i32 %shift +} + +; ...and again with a truncated 64-bit shift amount. +define i32 @f7(i32 %a, i64 %amt) { +; CHECK: f7: +; CHECK: sll %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %trunc = trunc i64 %add to i32 + %shift = shl i32 %a, %trunc + ret i32 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i32 @f8(i32 %a, i32 %amt) { +; CHECK: f8: +; CHECK: sll %r2, 4095(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4095 + %shift = shl i32 %a, %add + ret i32 %shift +} + +; Check the next value up. Again, we could mask the amount instead. +define i32 @f9(i32 %a, i32 %amt) { +; CHECK: f9: +; CHECK: ahi %r3, 4096 +; CHECK: sll %r2, 0(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4096 + %shift = shl i32 %a, %add + ret i32 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i32 @f10(i32 %a, i32 %b, i32 %c) { +; CHECK: f10: +; CHECK: ar {{%r3, %r4|%r4, %r3}} +; CHECK: sll %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i32 %b, %c + %shift = shl i32 %a, %add + ret i32 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i32 @f11(i32 %a, i32 *%ptr) { +; CHECK: f11: +; CHECK: l %r1, 0(%r3) +; CHECK: sll %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i32 *%ptr + %shift = shl i32 %a, %amt + ret i32 %shift +} diff --git a/test/CodeGen/SystemZ/shift-02.ll b/test/CodeGen/SystemZ/shift-02.ll new file mode 100644 index 000000000000..38093a8ff7a0 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-02.ll @@ -0,0 +1,114 @@ +; Test 32-bit logical shifts right. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SRL range. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: srl %r2, 1 +; CHECK: br %r14 + %shift = lshr i32 %a, 1 + ret i32 %shift +} + +; Check the high end of the defined SRL range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: srl %r2, 31 +; CHECK: br %r14 + %shift = lshr i32 %a, 31 + ret i32 %shift +} + +; We don't generate shifts by out-of-range values. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK-NOT: srl %r2, 32 +; CHECK: br %r14 + %shift = lshr i32 %a, 32 + ret i32 %shift +} + +; Make sure that we don't generate negative shift amounts. +define i32 @f4(i32 %a, i32 %amt) { +; CHECK: f4: +; CHECK-NOT: srl %r2, -1{{.*}} +; CHECK: br %r14 + %sub = sub i32 %amt, 1 + %shift = lshr i32 %a, %sub + ret i32 %shift +} + +; Check variable shifts. +define i32 @f5(i32 %a, i32 %amt) { +; CHECK: f5: +; CHECK: srl %r2, 0(%r3) +; CHECK: br %r14 + %shift = lshr i32 %a, %amt + ret i32 %shift +} + +; Check shift amounts that have a constant term. +define i32 @f6(i32 %a, i32 %amt) { +; CHECK: f6: +; CHECK: srl %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %shift = lshr i32 %a, %add + ret i32 %shift +} + +; ...and again with a truncated 64-bit shift amount. +define i32 @f7(i32 %a, i64 %amt) { +; CHECK: f7: +; CHECK: srl %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %trunc = trunc i64 %add to i32 + %shift = lshr i32 %a, %trunc + ret i32 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i32 @f8(i32 %a, i32 %amt) { +; CHECK: f8: +; CHECK: srl %r2, 4095(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4095 + %shift = lshr i32 %a, %add + ret i32 %shift +} + +; Check the next value up. Again, we could mask the amount instead. +define i32 @f9(i32 %a, i32 %amt) { +; CHECK: f9: +; CHECK: ahi %r3, 4096 +; CHECK: srl %r2, 0(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4096 + %shift = lshr i32 %a, %add + ret i32 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i32 @f10(i32 %a, i32 %b, i32 %c) { +; CHECK: f10: +; CHECK: ar {{%r3, %r4|%r4, %r3}} +; CHECK: srl %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i32 %b, %c + %shift = lshr i32 %a, %add + ret i32 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i32 @f11(i32 %a, i32 *%ptr) { +; CHECK: f11: +; CHECK: l %r1, 0(%r3) +; CHECK: srl %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i32 *%ptr + %shift = lshr i32 %a, %amt + ret i32 %shift +} diff --git a/test/CodeGen/SystemZ/shift-03.ll b/test/CodeGen/SystemZ/shift-03.ll new file mode 100644 index 000000000000..ca510f3c429b --- /dev/null +++ b/test/CodeGen/SystemZ/shift-03.ll @@ -0,0 +1,114 @@ +; Test 32-bit arithmetic shifts right. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SRA range. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: sra %r2, 1 +; CHECK: br %r14 + %shift = ashr i32 %a, 1 + ret i32 %shift +} + +; Check the high end of the defined SRA range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: sra %r2, 31 +; CHECK: br %r14 + %shift = ashr i32 %a, 31 + ret i32 %shift +} + +; We don't generate shifts by out-of-range values. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK-NOT: sra %r2, 32 +; CHECK: br %r14 + %shift = ashr i32 %a, 32 + ret i32 %shift +} + +; Make sure that we don't generate negative shift amounts. +define i32 @f4(i32 %a, i32 %amt) { +; CHECK: f4: +; CHECK-NOT: sra %r2, -1{{.*}} +; CHECK: br %r14 + %sub = sub i32 %amt, 1 + %shift = ashr i32 %a, %sub + ret i32 %shift +} + +; Check variable shifts. +define i32 @f5(i32 %a, i32 %amt) { +; CHECK: f5: +; CHECK: sra %r2, 0(%r3) +; CHECK: br %r14 + %shift = ashr i32 %a, %amt + ret i32 %shift +} + +; Check shift amounts that have a constant term. +define i32 @f6(i32 %a, i32 %amt) { +; CHECK: f6: +; CHECK: sra %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %shift = ashr i32 %a, %add + ret i32 %shift +} + +; ...and again with a truncated 64-bit shift amount. +define i32 @f7(i32 %a, i64 %amt) { +; CHECK: f7: +; CHECK: sra %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %trunc = trunc i64 %add to i32 + %shift = ashr i32 %a, %trunc + ret i32 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i32 @f8(i32 %a, i32 %amt) { +; CHECK: f8: +; CHECK: sra %r2, 4095(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4095 + %shift = ashr i32 %a, %add + ret i32 %shift +} + +; Check the next value up. Again, we could mask the amount instead. +define i32 @f9(i32 %a, i32 %amt) { +; CHECK: f9: +; CHECK: ahi %r3, 4096 +; CHECK: sra %r2, 0(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 4096 + %shift = ashr i32 %a, %add + ret i32 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i32 @f10(i32 %a, i32 %b, i32 %c) { +; CHECK: f10: +; CHECK: ar {{%r3, %r4|%r4, %r3}} +; CHECK: sra %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i32 %b, %c + %shift = ashr i32 %a, %add + ret i32 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i32 @f11(i32 %a, i32 *%ptr) { +; CHECK: f11: +; CHECK: l %r1, 0(%r3) +; CHECK: sra %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i32 *%ptr + %shift = ashr i32 %a, %amt + ret i32 %shift +} diff --git a/test/CodeGen/SystemZ/shift-04.ll b/test/CodeGen/SystemZ/shift-04.ll new file mode 100644 index 000000000000..0146a86ee062 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-04.ll @@ -0,0 +1,189 @@ +; Test 32-bit rotates left. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the RLL range. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: rll %r2, %r2, 1 +; CHECK: br %r14 + %parta = shl i32 %a, 1 + %partb = lshr i32 %a, 31 + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check the high end of the defined RLL range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: rll %r2, %r2, 31 +; CHECK: br %r14 + %parta = shl i32 %a, 31 + %partb = lshr i32 %a, 1 + %or = or i32 %parta, %partb + ret i32 %or +} + +; We don't generate shifts by out-of-range values. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK-NOT: rll +; CHECK: br %r14 + %parta = shl i32 %a, 32 + %partb = lshr i32 %a, 0 + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check variable shifts. +define i32 @f4(i32 %a, i32 %amt) { +; CHECK: f4: +; CHECK: rll %r2, %r2, 0(%r3) +; CHECK: br %r14 + %amtb = sub i32 32, %amt + %parta = shl i32 %a, %amt + %partb = lshr i32 %a, %amtb + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check shift amounts that have a constant term. +define i32 @f5(i32 %a, i32 %amt) { +; CHECK: f5: +; CHECK: rll %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %sub = sub i32 32, %add + %parta = shl i32 %a, %add + %partb = lshr i32 %a, %sub + %or = or i32 %parta, %partb + ret i32 %or +} + +; ...and again with a truncated 64-bit shift amount. +define i32 @f6(i32 %a, i64 %amt) { +; CHECK: f6: +; CHECK: rll %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %addtrunc = trunc i64 %add to i32 + %sub = sub i32 32, %addtrunc + %parta = shl i32 %a, %addtrunc + %partb = lshr i32 %a, %sub + %or = or i32 %parta, %partb + ret i32 %or +} + +; ...and again with a different truncation representation. +define i32 @f7(i32 %a, i64 %amt) { +; CHECK: f7: +; CHECK: rll %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %sub = sub i64 32, %add + %addtrunc = trunc i64 %add to i32 + %subtrunc = trunc i64 %sub to i32 + %parta = shl i32 %a, %addtrunc + %partb = lshr i32 %a, %subtrunc + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i32 @f8(i32 %a, i32 %amt) { +; CHECK: f8: +; CHECK: rll %r2, %r2, 524287(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 524287 + %sub = sub i32 32, %add + %parta = shl i32 %a, %add + %partb = lshr i32 %a, %sub + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check the next value up, which without masking must use a separate +; addition. +define i32 @f9(i32 %a, i32 %amt) { +; CHECK: f9: +; CHECK: afi %r3, 524288 +; CHECK: rll %r2, %r2, 0(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 524288 + %sub = sub i32 32, %add + %parta = shl i32 %a, %add + %partb = lshr i32 %a, %sub + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check cases where 1 is subtracted from the shift amount. +define i32 @f10(i32 %a, i32 %amt) { +; CHECK: f10: +; CHECK: rll %r2, %r2, -1(%r3) +; CHECK: br %r14 + %suba = sub i32 %amt, 1 + %subb = sub i32 32, %suba + %parta = shl i32 %a, %suba + %partb = lshr i32 %a, %subb + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check the lowest value that can be subtracted from the shift amount. +; Again, we could mask the shift amount instead. +define i32 @f11(i32 %a, i32 %amt) { +; CHECK: f11: +; CHECK: rll %r2, %r2, -524288(%r3) +; CHECK: br %r14 + %suba = sub i32 %amt, 524288 + %subb = sub i32 32, %suba + %parta = shl i32 %a, %suba + %partb = lshr i32 %a, %subb + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check the next value down, which without masking must use a separate +; addition. +define i32 @f12(i32 %a, i32 %amt) { +; CHECK: f12: +; CHECK: afi %r3, -524289 +; CHECK: rll %r2, %r2, 0(%r3) +; CHECK: br %r14 + %suba = sub i32 %amt, 524289 + %subb = sub i32 32, %suba + %parta = shl i32 %a, %suba + %partb = lshr i32 %a, %subb + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check that we don't try to generate "indexed" shifts. +define i32 @f13(i32 %a, i32 %b, i32 %c) { +; CHECK: f13: +; CHECK: ar {{%r3, %r4|%r4, %r3}} +; CHECK: rll %r2, %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i32 %b, %c + %sub = sub i32 32, %add + %parta = shl i32 %a, %add + %partb = lshr i32 %a, %sub + %or = or i32 %parta, %partb + ret i32 %or +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i32 @f14(i32 %a, i32 *%ptr) { +; CHECK: f14: +; CHECK: l %r1, 0(%r3) +; CHECK: rll %r2, %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i32 *%ptr + %amtb = sub i32 32, %amt + %parta = shl i32 %a, %amt + %partb = lshr i32 %a, %amtb + %or = or i32 %parta, %partb + ret i32 %or +} diff --git a/test/CodeGen/SystemZ/shift-05.ll b/test/CodeGen/SystemZ/shift-05.ll new file mode 100644 index 000000000000..8c0ca9381bcb --- /dev/null +++ b/test/CodeGen/SystemZ/shift-05.ll @@ -0,0 +1,149 @@ +; Test 32-bit shifts left. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SLLG range. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: sllg %r2, %r2, 1 +; CHECK: br %r14 + %shift = shl i64 %a, 1 + ret i64 %shift +} + +; Check the high end of the defined SLLG range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: sllg %r2, %r2, 63 +; CHECK: br %r14 + %shift = shl i64 %a, 63 + ret i64 %shift +} + +; We don't generate shifts by out-of-range values. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: sllg +; CHECK: br %r14 + %shift = shl i64 %a, 64 + ret i64 %shift +} + +; Check variable shifts. +define i64 @f4(i64 %a, i64 %amt) { +; CHECK: f4: +; CHECK: sllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %shift = shl i64 %a, %amt + ret i64 %shift +} + +; Check shift amounts that have a constant term. +define i64 @f5(i64 %a, i64 %amt) { +; CHECK: f5: +; CHECK: sllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %shift = shl i64 %a, %add + ret i64 %shift +} + +; ...and again with a sign-extended 32-bit shift amount. +define i64 @f6(i64 %a, i32 %amt) { +; CHECK: f6: +; CHECK: sllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = sext i32 %add to i64 + %shift = shl i64 %a, %addext + ret i64 %shift +} + +; ...and now with a zero-extended 32-bit shift amount. +define i64 @f7(i64 %a, i32 %amt) { +; CHECK: f7: +; CHECK: sllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = zext i32 %add to i64 + %shift = shl i64 %a, %addext + ret i64 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i64 @f8(i64 %a, i64 %amt) { +; CHECK: f8: +; CHECK: sllg %r2, %r2, 524287(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524287 + %shift = shl i64 %a, %add + ret i64 %shift +} + +; Check the next value up, which without masking must use a separate +; addition. +define i64 @f9(i64 %a, i64 %amt) { +; CHECK: f9: +; CHECK: a{{g?}}fi %r3, 524288 +; CHECK: sllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524288 + %shift = shl i64 %a, %add + ret i64 %shift +} + +; Check cases where 1 is subtracted from the shift amount. +define i64 @f10(i64 %a, i64 %amt) { +; CHECK: f10: +; CHECK: sllg %r2, %r2, -1(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 1 + %shift = shl i64 %a, %sub + ret i64 %shift +} + +; Check the lowest value that can be subtracted from the shift amount. +; Again, we could mask the shift amount instead. +define i64 @f11(i64 %a, i64 %amt) { +; CHECK: f11: +; CHECK: sllg %r2, %r2, -524288(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524288 + %shift = shl i64 %a, %sub + ret i64 %shift +} + +; Check the next value down, which without masking must use a separate +; addition. +define i64 @f12(i64 %a, i64 %amt) { +; CHECK: f12: +; CHECK: a{{g?}}fi %r3, -524289 +; CHECK: sllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524289 + %shift = shl i64 %a, %sub + ret i64 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i64 @f13(i64 %a, i64 %b, i64 %c) { +; CHECK: f13: +; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}} +; CHECK: sllg %r2, %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i64 %b, %c + %shift = shl i64 %a, %add + ret i64 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i64 @f14(i64 %a, i64 *%ptr) { +; CHECK: f14: +; CHECK: l %r1, 4(%r3) +; CHECK: sllg %r2, %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i64 *%ptr + %shift = shl i64 %a, %amt + ret i64 %shift +} diff --git a/test/CodeGen/SystemZ/shift-06.ll b/test/CodeGen/SystemZ/shift-06.ll new file mode 100644 index 000000000000..5f600b45a884 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-06.ll @@ -0,0 +1,149 @@ +; Test 32-bit logical shifts right. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SRLG range. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: srlg %r2, %r2, 1 +; CHECK: br %r14 + %shift = lshr i64 %a, 1 + ret i64 %shift +} + +; Check the high end of the defined SRLG range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: srlg %r2, %r2, 63 +; CHECK: br %r14 + %shift = lshr i64 %a, 63 + ret i64 %shift +} + +; We don't generate shifts by out-of-range values. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: srlg +; CHECK: br %r14 + %shift = lshr i64 %a, 64 + ret i64 %shift +} + +; Check variable shifts. +define i64 @f4(i64 %a, i64 %amt) { +; CHECK: f4: +; CHECK: srlg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %shift = lshr i64 %a, %amt + ret i64 %shift +} + +; Check shift amounts that have a constant term. +define i64 @f5(i64 %a, i64 %amt) { +; CHECK: f5: +; CHECK: srlg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %shift = lshr i64 %a, %add + ret i64 %shift +} + +; ...and again with a sign-extended 32-bit shift amount. +define i64 @f6(i64 %a, i32 %amt) { +; CHECK: f6: +; CHECK: srlg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = sext i32 %add to i64 + %shift = lshr i64 %a, %addext + ret i64 %shift +} + +; ...and now with a zero-extended 32-bit shift amount. +define i64 @f7(i64 %a, i32 %amt) { +; CHECK: f7: +; CHECK: srlg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = zext i32 %add to i64 + %shift = lshr i64 %a, %addext + ret i64 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i64 @f8(i64 %a, i64 %amt) { +; CHECK: f8: +; CHECK: srlg %r2, %r2, 524287(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524287 + %shift = lshr i64 %a, %add + ret i64 %shift +} + +; Check the next value up, which without masking must use a separate +; addition. +define i64 @f9(i64 %a, i64 %amt) { +; CHECK: f9: +; CHECK: a{{g?}}fi %r3, 524288 +; CHECK: srlg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524288 + %shift = lshr i64 %a, %add + ret i64 %shift +} + +; Check cases where 1 is subtracted from the shift amount. +define i64 @f10(i64 %a, i64 %amt) { +; CHECK: f10: +; CHECK: srlg %r2, %r2, -1(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 1 + %shift = lshr i64 %a, %sub + ret i64 %shift +} + +; Check the lowest value that can be subtracted from the shift amount. +; Again, we could mask the shift amount instead. +define i64 @f11(i64 %a, i64 %amt) { +; CHECK: f11: +; CHECK: srlg %r2, %r2, -524288(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524288 + %shift = lshr i64 %a, %sub + ret i64 %shift +} + +; Check the next value down, which without masking must use a separate +; addition. +define i64 @f12(i64 %a, i64 %amt) { +; CHECK: f12: +; CHECK: a{{g?}}fi %r3, -524289 +; CHECK: srlg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524289 + %shift = lshr i64 %a, %sub + ret i64 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i64 @f13(i64 %a, i64 %b, i64 %c) { +; CHECK: f13: +; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}} +; CHECK: srlg %r2, %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i64 %b, %c + %shift = lshr i64 %a, %add + ret i64 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i64 @f14(i64 %a, i64 *%ptr) { +; CHECK: f14: +; CHECK: l %r1, 4(%r3) +; CHECK: srlg %r2, %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i64 *%ptr + %shift = lshr i64 %a, %amt + ret i64 %shift +} diff --git a/test/CodeGen/SystemZ/shift-07.ll b/test/CodeGen/SystemZ/shift-07.ll new file mode 100644 index 000000000000..ef583e8f3f0d --- /dev/null +++ b/test/CodeGen/SystemZ/shift-07.ll @@ -0,0 +1,149 @@ +; Test 32-bit arithmetic shifts right. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the SRAG range. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: srag %r2, %r2, 1 +; CHECK: br %r14 + %shift = ashr i64 %a, 1 + ret i64 %shift +} + +; Check the high end of the defined SRAG range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: srag %r2, %r2, 63 +; CHECK: br %r14 + %shift = ashr i64 %a, 63 + ret i64 %shift +} + +; We don't generate shifts by out-of-range values. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: srag +; CHECK: br %r14 + %shift = ashr i64 %a, 64 + ret i64 %shift +} + +; Check variable shifts. +define i64 @f4(i64 %a, i64 %amt) { +; CHECK: f4: +; CHECK: srag %r2, %r2, 0(%r3) +; CHECK: br %r14 + %shift = ashr i64 %a, %amt + ret i64 %shift +} + +; Check shift amounts that have a constant term. +define i64 @f5(i64 %a, i64 %amt) { +; CHECK: f5: +; CHECK: srag %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %shift = ashr i64 %a, %add + ret i64 %shift +} + +; ...and again with a sign-extended 32-bit shift amount. +define i64 @f6(i64 %a, i32 %amt) { +; CHECK: f6: +; CHECK: srag %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = sext i32 %add to i64 + %shift = ashr i64 %a, %addext + ret i64 %shift +} + +; ...and now with a zero-extended 32-bit shift amount. +define i64 @f7(i64 %a, i32 %amt) { +; CHECK: f7: +; CHECK: srag %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %addext = zext i32 %add to i64 + %shift = ashr i64 %a, %addext + ret i64 %shift +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i64 @f8(i64 %a, i64 %amt) { +; CHECK: f8: +; CHECK: srag %r2, %r2, 524287(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524287 + %shift = ashr i64 %a, %add + ret i64 %shift +} + +; Check the next value up, which without masking must use a separate +; addition. +define i64 @f9(i64 %a, i64 %amt) { +; CHECK: f9: +; CHECK: a{{g?}}fi %r3, 524288 +; CHECK: srag %r2, %r2, 0(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524288 + %shift = ashr i64 %a, %add + ret i64 %shift +} + +; Check cases where 1 is subtracted from the shift amount. +define i64 @f10(i64 %a, i64 %amt) { +; CHECK: f10: +; CHECK: srag %r2, %r2, -1(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 1 + %shift = ashr i64 %a, %sub + ret i64 %shift +} + +; Check the lowest value that can be subtracted from the shift amount. +; Again, we could mask the shift amount instead. +define i64 @f11(i64 %a, i64 %amt) { +; CHECK: f11: +; CHECK: srag %r2, %r2, -524288(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524288 + %shift = ashr i64 %a, %sub + ret i64 %shift +} + +; Check the next value down, which without masking must use a separate +; addition. +define i64 @f12(i64 %a, i64 %amt) { +; CHECK: f12: +; CHECK: a{{g?}}fi %r3, -524289 +; CHECK: srag %r2, %r2, 0(%r3) +; CHECK: br %r14 + %sub = sub i64 %amt, 524289 + %shift = ashr i64 %a, %sub + ret i64 %shift +} + +; Check that we don't try to generate "indexed" shifts. +define i64 @f13(i64 %a, i64 %b, i64 %c) { +; CHECK: f13: +; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}} +; CHECK: srag %r2, %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i64 %b, %c + %shift = ashr i64 %a, %add + ret i64 %shift +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i64 @f14(i64 %a, i64 *%ptr) { +; CHECK: f14: +; CHECK: l %r1, 4(%r3) +; CHECK: srag %r2, %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i64 *%ptr + %shift = ashr i64 %a, %amt + ret i64 %shift +} diff --git a/test/CodeGen/SystemZ/shift-08.ll b/test/CodeGen/SystemZ/shift-08.ll new file mode 100644 index 000000000000..0688a0671671 --- /dev/null +++ b/test/CodeGen/SystemZ/shift-08.ll @@ -0,0 +1,190 @@ +; Test 32-bit rotates left. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the RLLG range. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: rllg %r2, %r2, 1 +; CHECK: br %r14 + %parta = shl i64 %a, 1 + %partb = lshr i64 %a, 63 + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check the high end of the defined RLLG range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: rllg %r2, %r2, 63 +; CHECK: br %r14 + %parta = shl i64 %a, 63 + %partb = lshr i64 %a, 1 + %or = or i64 %parta, %partb + ret i64 %or +} + +; We don't generate shifts by out-of-range values. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK-NOT: rllg +; CHECK: br %r14 + %parta = shl i64 %a, 64 + %partb = lshr i64 %a, 0 + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check variable shifts. +define i64 @f4(i64 %a, i64 %amt) { +; CHECK: f4: +; CHECK: rllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %amtb = sub i64 64, %amt + %parta = shl i64 %a, %amt + %partb = lshr i64 %a, %amtb + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check shift amounts that have a constant term. +define i64 @f5(i64 %a, i64 %amt) { +; CHECK: f5: +; CHECK: rllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 10 + %sub = sub i64 64, %add + %parta = shl i64 %a, %add + %partb = lshr i64 %a, %sub + %or = or i64 %parta, %partb + ret i64 %or +} + +; ...and again with a sign-extended 32-bit shift amount. +define i64 @f6(i64 %a, i32 %amt) { +; CHECK: f6: +; CHECK: rllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %sub = sub i32 64, %add + %addext = sext i32 %add to i64 + %subext = sext i32 %sub to i64 + %parta = shl i64 %a, %addext + %partb = lshr i64 %a, %subext + %or = or i64 %parta, %partb + ret i64 %or +} + +; ...and now with a zero-extended 32-bit shift amount. +define i64 @f7(i64 %a, i32 %amt) { +; CHECK: f7: +; CHECK: rllg %r2, %r2, 10(%r3) +; CHECK: br %r14 + %add = add i32 %amt, 10 + %sub = sub i32 64, %add + %addext = zext i32 %add to i64 + %subext = zext i32 %sub to i64 + %parta = shl i64 %a, %addext + %partb = lshr i64 %a, %subext + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check shift amounts that have the largest in-range constant term. We could +; mask the amount instead. +define i64 @f8(i64 %a, i64 %amt) { +; CHECK: f8: +; CHECK: rllg %r2, %r2, 524287(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524287 + %sub = sub i64 64, %add + %parta = shl i64 %a, %add + %partb = lshr i64 %a, %sub + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check the next value up, which without masking must use a separate +; addition. +define i64 @f9(i64 %a, i64 %amt) { +; CHECK: f9: +; CHECK: a{{g?}}fi %r3, 524288 +; CHECK: rllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %add = add i64 %amt, 524288 + %sub = sub i64 64, %add + %parta = shl i64 %a, %add + %partb = lshr i64 %a, %sub + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check cases where 1 is subtracted from the shift amount. +define i64 @f10(i64 %a, i64 %amt) { +; CHECK: f10: +; CHECK: rllg %r2, %r2, -1(%r3) +; CHECK: br %r14 + %suba = sub i64 %amt, 1 + %subb = sub i64 64, %suba + %parta = shl i64 %a, %suba + %partb = lshr i64 %a, %subb + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check the lowest value that can be subtracted from the shift amount. +; Again, we could mask the shift amount instead. +define i64 @f11(i64 %a, i64 %amt) { +; CHECK: f11: +; CHECK: rllg %r2, %r2, -524288(%r3) +; CHECK: br %r14 + %suba = sub i64 %amt, 524288 + %subb = sub i64 64, %suba + %parta = shl i64 %a, %suba + %partb = lshr i64 %a, %subb + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check the next value down, which without masking must use a separate +; addition. +define i64 @f12(i64 %a, i64 %amt) { +; CHECK: f12: +; CHECK: a{{g?}}fi %r3, -524289 +; CHECK: rllg %r2, %r2, 0(%r3) +; CHECK: br %r14 + %suba = sub i64 %amt, 524289 + %subb = sub i64 64, %suba + %parta = shl i64 %a, %suba + %partb = lshr i64 %a, %subb + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check that we don't try to generate "indexed" shifts. +define i64 @f13(i64 %a, i64 %b, i64 %c) { +; CHECK: f13: +; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}} +; CHECK: rllg %r2, %r2, 0({{%r[34]}}) +; CHECK: br %r14 + %add = add i64 %b, %c + %sub = sub i64 64, %add + %parta = shl i64 %a, %add + %partb = lshr i64 %a, %sub + %or = or i64 %parta, %partb + ret i64 %or +} + +; Check that the shift amount uses an address register. It cannot be in %r0. +define i64 @f14(i64 %a, i64 *%ptr) { +; CHECK: f14: +; CHECK: l %r1, 4(%r3) +; CHECK: rllg %r2, %r2, 0(%r1) +; CHECK: br %r14 + %amt = load i64 *%ptr + %amtb = sub i64 64, %amt + %parta = shl i64 %a, %amt + %partb = lshr i64 %a, %amtb + %or = or i64 %parta, %partb + ret i64 %or +} diff --git a/test/CodeGen/SystemZ/tls-01.ll b/test/CodeGen/SystemZ/tls-01.ll new file mode 100644 index 000000000000..49037ad51c69 --- /dev/null +++ b/test/CodeGen/SystemZ/tls-01.ll @@ -0,0 +1,22 @@ +; Test initial-exec TLS accesses. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-CP + +@x = thread_local global i32 0 + +; The offset must be loaded from the constant pool. It doesn't really +; matter whether we use LARL/AG or LGRL/AGR for the last part. +define i32 *@foo() { +; CHECK-CP: .LCP{{.*}}: +; CHECK-CP: .quad x@NTPOFF +; +; CHECK-MAIN: foo: +; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0 +; CHECK-MAIN: sllg %r2, [[HIGH]], 32 +; CHECK-MAIN: ear %r2, %a1 +; CHECK-MAIN: larl %r1, .LCP{{.*}} +; CHECK-MAIN: ag %r2, 0(%r1) +; CHECK-MAIN: br %r14 + ret i32 *@x +} diff --git a/test/CodeGen/SystemZ/xor-01.ll b/test/CodeGen/SystemZ/xor-01.ll new file mode 100644 index 000000000000..30bdbe7901f9 --- /dev/null +++ b/test/CodeGen/SystemZ/xor-01.ll @@ -0,0 +1,129 @@ +; Test 32-bit XORs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check XR. +define i32 @f1(i32 %a, i32 %b) { +; CHECK: f1: +; CHECK: xr %r2, %r3 +; CHECK: br %r14 + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the low end of the X range. +define i32 @f2(i32 %a, i32 *%src) { +; CHECK: f2: +; CHECK: x %r2, 0(%r3) +; CHECK: br %r14 + %b = load i32 *%src + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the high end of the aligned X range. +define i32 @f3(i32 %a, i32 *%src) { +; CHECK: f3: +; CHECK: x %r2, 4092(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1023 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the next word up, which should use XY instead of X. +define i32 @f4(i32 %a, i32 *%src) { +; CHECK: f4: +; CHECK: xy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 1024 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the high end of the aligned XY range. +define i32 @f5(i32 %a, i32 *%src) { +; CHECK: f5: +; CHECK: xy %r2, 524284(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131071 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f6(i32 %a, i32 *%src) { +; CHECK: f6: +; CHECK: agfi %r3, 524288 +; CHECK: x %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 131072 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the high end of the negative aligned XY range. +define i32 @f7(i32 %a, i32 *%src) { +; CHECK: f7: +; CHECK: xy %r2, -4(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -1 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the low end of the XY range. +define i32 @f8(i32 %a, i32 *%src) { +; CHECK: f8: +; CHECK: xy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131072 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f9(i32 %a, i32 *%src) { +; CHECK: f9: +; CHECK: agfi %r3, -524292 +; CHECK: x %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i32 *%src, i64 -131073 + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check that X allows an index. +define i32 @f10(i32 %a, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: x %r2, 4092({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4092 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} + +; Check that XY allows an index. +define i32 @f11(i32 %a, i64 %src, i64 %index) { +; CHECK: f11: +; CHECK: xy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i32 * + %b = load i32 *%ptr + %xor = xor i32 %a, %b + ret i32 %xor +} diff --git a/test/CodeGen/SystemZ/xor-02.ll b/test/CodeGen/SystemZ/xor-02.ll new file mode 100644 index 000000000000..c2b52b9b8e20 --- /dev/null +++ b/test/CodeGen/SystemZ/xor-02.ll @@ -0,0 +1,40 @@ +; Test 32-bit XORs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful XILF value. +define i32 @f1(i32 %a) { +; CHECK: f1: +; CHECK: xilf %r2, 1 +; CHECK: br %r14 + %xor = xor i32 %a, 1 + ret i32 %xor +} + +; Check the high end of the signed range. +define i32 @f2(i32 %a) { +; CHECK: f2: +; CHECK: xilf %r2, 2147483647 +; CHECK: br %r14 + %xor = xor i32 %a, 2147483647 + ret i32 %xor +} + +; Check the low end of the signed range, which should be treated +; as a positive value. +define i32 @f3(i32 %a) { +; CHECK: f3: +; CHECK: xilf %r2, 2147483648 +; CHECK: br %r14 + %xor = xor i32 %a, -2147483648 + ret i32 %xor +} + +; Check the high end of the XILF range. +define i32 @f4(i32 %a) { +; CHECK: f4: +; CHECK: xilf %r2, 4294967295 +; CHECK: br %r14 + %xor = xor i32 %a, 4294967295 + ret i32 %xor +} diff --git a/test/CodeGen/SystemZ/xor-03.ll b/test/CodeGen/SystemZ/xor-03.ll new file mode 100644 index 000000000000..a4851b33090d --- /dev/null +++ b/test/CodeGen/SystemZ/xor-03.ll @@ -0,0 +1,94 @@ +; Test 64-bit XORs in which the second operand is variable. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check XGR. +define i64 @f1(i64 %a, i64 %b) { +; CHECK: f1: +; CHECK: xgr %r2, %r3 +; CHECK: br %r14 + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check XG with no displacement. +define i64 @f2(i64 %a, i64 *%src) { +; CHECK: f2: +; CHECK: xg %r2, 0(%r3) +; CHECK: br %r14 + %b = load i64 *%src + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check the high end of the aligned XG range. +define i64 @f3(i64 %a, i64 *%src) { +; CHECK: f3: +; CHECK: xg %r2, 524280(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65535 + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check the next doubleword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f4(i64 %a, i64 *%src) { +; CHECK: f4: +; CHECK: agfi %r3, 524288 +; CHECK: xg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 65536 + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check the high end of the negative aligned XG range. +define i64 @f5(i64 %a, i64 *%src) { +; CHECK: f5: +; CHECK: xg %r2, -8(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -1 + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check the low end of the XG range. +define i64 @f6(i64 %a, i64 *%src) { +; CHECK: f6: +; CHECK: xg %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65536 + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f7(i64 %a, i64 *%src) { +; CHECK: f7: +; CHECK: agfi %r3, -524296 +; CHECK: xg %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i64 *%src, i64 -65537 + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} + +; Check that XG allows an index. +define i64 @f8(i64 %a, i64 %src, i64 %index) { +; CHECK: f8: +; CHECK: xg %r2, 524280({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524280 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 *%ptr + %xor = xor i64 %a, %b + ret i64 %xor +} diff --git a/test/CodeGen/SystemZ/xor-04.ll b/test/CodeGen/SystemZ/xor-04.ll new file mode 100644 index 000000000000..cc141d391a85 --- /dev/null +++ b/test/CodeGen/SystemZ/xor-04.ll @@ -0,0 +1,69 @@ +; Test 64-bit XORs in which the second operand is constant. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful XILF value. +define i64 @f1(i64 %a) { +; CHECK: f1: +; CHECK: xilf %r2, 1 +; CHECK: br %r14 + %xor = xor i64 %a, 1 + ret i64 %xor +} + +; Check the high end of the XILF range. +define i64 @f2(i64 %a) { +; CHECK: f2: +; CHECK: xilf %r2, 4294967295 +; CHECK: br %r14 + %xor = xor i64 %a, 4294967295 + ret i64 %xor +} + +; Check the lowest useful XIHF value, which is one up from the above. +define i64 @f3(i64 %a) { +; CHECK: f3: +; CHECK: xihf %r2, 1 +; CHECK: br %r14 + %xor = xor i64 %a, 4294967296 + ret i64 %xor +} + +; Check the next value up again, which needs a combination of XIHF and XILF. +define i64 @f4(i64 %a) { +; CHECK: f4: +; CHECK: xihf %r2, 1 +; CHECK: xilf %r2, 4294967295 +; CHECK: br %r14 + %xor = xor i64 %a, 8589934591 + ret i64 %xor +} + +; Check the high end of the XIHF range. +define i64 @f5(i64 %a) { +; CHECK: f5: +; CHECK: xihf %r2, 4294967295 +; CHECK: br %r14 + %xor = xor i64 %a, -4294967296 + ret i64 %xor +} + +; Check the next value up, which again must use XIHF and XILF. +define i64 @f6(i64 %a) { +; CHECK: f6: +; CHECK: xihf %r2, 4294967295 +; CHECK: xilf %r2, 1 +; CHECK: br %r14 + %xor = xor i64 %a, -4294967295 + ret i64 %xor +} + +; Check full bitwise negation +define i64 @f7(i64 %a) { +; CHECK: f7: +; CHECK: xihf %r2, 4294967295 +; CHECK: xilf %r2, 4294967295 +; CHECK: br %r14 + %xor = xor i64 %a, -1 + ret i64 %xor +} diff --git a/test/CodeGen/SystemZ/xor-05.ll b/test/CodeGen/SystemZ/xor-05.ll new file mode 100644 index 000000000000..9ef0d20ca52b --- /dev/null +++ b/test/CodeGen/SystemZ/xor-05.ll @@ -0,0 +1,165 @@ +; Test XORs of a constant into a byte of memory. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the lowest useful constant, expressed as a signed integer. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: xi 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %xor = xor i8 %val, -255 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a signed integer. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %xor = xor i8 %val, -2 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the lowest useful constant, expressed as an unsigned integer. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: xi 0(%r2), 1 +; CHECK: br %r14 + %val = load i8 *%ptr + %xor = xor i8 %val, 1 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the highest useful constant, expressed as a unsigned integer. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %xor = xor i8 %val, 254 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the high end of the XI range. +define void @f5(i8 *%src) { +; CHECK: f5: +; CHECK: xi 4095(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4095 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the next byte up, which should use XIY instead of XI. +define void @f6(i8 *%src) { +; CHECK: f6: +; CHECK: xiy 4096(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 4096 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the high end of the XIY range. +define void @f7(i8 *%src) { +; CHECK: f7: +; CHECK: xiy 524287(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524287 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the next byte up, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f8(i8 *%src) { +; CHECK: f8: +; CHECK: agfi %r2, 524288 +; CHECK: xi 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 524288 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the high end of the negative XIY range. +define void @f9(i8 *%src) { +; CHECK: f9: +; CHECK: xiy -1(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -1 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the low end of the XIY range. +define void @f10(i8 *%src) { +; CHECK: f10: +; CHECK: xiy -524288(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524288 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check the next byte down, which needs separate address logic. +; Other sequences besides this one would be OK. +define void @f11(i8 *%src) { +; CHECK: f11: +; CHECK: agfi %r2, -524289 +; CHECK: xi 0(%r2), 127 +; CHECK: br %r14 + %ptr = getelementptr i8 *%src, i64 -524289 + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check that XI does not allow an index +define void @f12(i64 %src, i64 %index) { +; CHECK: f12: +; CHECK: agr %r2, %r3 +; CHECK: xi 4095(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4095 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} + +; Check that XIY does not allow an index +define void @f13(i64 %src, i64 %index) { +; CHECK: f13: +; CHECK: agr %r2, %r3 +; CHECK: xiy 4096(%r2), 127 +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i8 * + %val = load i8 *%ptr + %xor = xor i8 %val, 127 + store i8 %xor, i8 *%ptr + ret void +} diff --git a/test/CodeGen/SystemZ/xor-06.ll b/test/CodeGen/SystemZ/xor-06.ll new file mode 100644 index 000000000000..0ffff47c2b5a --- /dev/null +++ b/test/CodeGen/SystemZ/xor-06.ll @@ -0,0 +1,108 @@ +; Test that we can use XI for byte operations that are expressed as i32 +; or i64 operations. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Zero extension to 32 bits, negative constant. +define void @f1(i8 *%ptr) { +; CHECK: f1: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %xor = xor i32 %ext, -2 + %trunc = trunc i32 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, negative constant. +define void @f2(i8 *%ptr) { +; CHECK: f2: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %xor = xor i64 %ext, -2 + %trunc = trunc i64 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 32 bits, positive constant. +define void @f3(i8 *%ptr) { +; CHECK: f3: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i32 + %xor = xor i32 %ext, 254 + %trunc = trunc i32 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Zero extension to 64 bits, positive constant. +define void @f4(i8 *%ptr) { +; CHECK: f4: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = zext i8 %val to i64 + %xor = xor i64 %ext, 254 + %trunc = trunc i64 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, negative constant. +define void @f5(i8 *%ptr) { +; CHECK: f5: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %xor = xor i32 %ext, -2 + %trunc = trunc i32 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, negative constant. +define void @f6(i8 *%ptr) { +; CHECK: f6: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %xor = xor i64 %ext, -2 + %trunc = trunc i64 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 32 bits, positive constant. +define void @f7(i8 *%ptr) { +; CHECK: f7: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i32 + %xor = xor i32 %ext, 254 + %trunc = trunc i32 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} + +; Sign extension to 64 bits, positive constant. +define void @f8(i8 *%ptr) { +; CHECK: f8: +; CHECK: xi 0(%r2), 254 +; CHECK: br %r14 + %val = load i8 *%ptr + %ext = sext i8 %val to i64 + %xor = xor i64 %ext, 254 + %trunc = trunc i64 %xor to i8 + store i8 %trunc, i8 *%ptr + ret void +} diff --git a/test/CodeGen/Thumb/large-stack.ll b/test/CodeGen/Thumb/large-stack.ll index f8c438c6e0a4..680976e74fba 100644 --- a/test/CodeGen/Thumb/large-stack.ll +++ b/test/CodeGen/Thumb/large-stack.ll @@ -20,8 +20,8 @@ define void @test2() { define i32 @test3() { ; CHECK: test3: -; CHECK: ldr.n r2, LCPI -; CHECK: add sp, r2 +; CHECK: ldr.n r1, LCPI +; CHECK: add sp, r1 ; CHECK: ldr.n r1, LCPI ; CHECK: add r1, sp ; CHECK: subs r4, r7, #4 diff --git a/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll b/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll index 502b138f65c8..e905cb9114c2 100644 --- a/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll +++ b/test/CodeGen/Thumb2/2013-02-19-tail-call-register-hint.ll @@ -18,13 +18,13 @@ define hidden void @func(i8* %Data) nounwind ssp { tail call void @def(%"myclass"* %2) nounwind %3 = getelementptr inbounds i8* %Data, i32 8 %4 = bitcast i8* %3 to i8** - %5 = load i8** %4, align 4, !tbaa !0 + %5 = load i8** %4, align 4 tail call void @ghi(i8* %5) nounwind %6 = bitcast i8* %Data to void (i8*)** - %7 = load void (i8*)** %6, align 4, !tbaa !0 + %7 = load void (i8*)** %6, align 4 %8 = getelementptr inbounds i8* %Data, i32 4 %9 = bitcast i8* %8 to i8** - %10 = load i8** %9, align 4, !tbaa !0 + %10 = load i8** %9, align 4 %11 = icmp eq i8* %Data, null br i1 %11, label %14, label %12 @@ -47,7 +47,3 @@ declare void @abc(%"myclass"*) declare void @ghi(i8*) declare %"myclass"* @jkl(%"myclass"*) nounwind - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll index 2e4cb1fe7eda..cb90bf644d5f 100644 --- a/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll +++ b/test/CodeGen/X86/2003-08-03-CallArgLiveRanges.ll @@ -4,7 +4,9 @@ ; it makes a ton of annoying overlapping live ranges. This code should not ; cause spills! ; -; RUN: llc < %s -march=x86 -stats 2>&1 | not grep spilled +; RUN: llc < %s -march=x86 -stats 2>&1 | FileCheck %s + +; CHECK-NOT: spilled target datalayout = "e-p:32:32" diff --git a/test/CodeGen/X86/2006-07-31-SingleRegClass.ll b/test/CodeGen/X86/2006-07-31-SingleRegClass.ll index c5c74d104863..c4b08a3be283 100644 --- a/test/CodeGen/X86/2006-07-31-SingleRegClass.ll +++ b/test/CodeGen/X86/2006-07-31-SingleRegClass.ll @@ -1,7 +1,8 @@ ; PR850 -; RUN: llc < %s -march=x86 -x86-asm-syntax=att > %t -; RUN: grep "movl 4(%eax),%ebp" %t -; RUN: grep "movl 0(%eax), %ebx" %t +; RUN: llc < %s -march=x86 -x86-asm-syntax=att | FileCheck %s + +; CHECK: {{movl 4[(]%eax[)],%ebp}} +; CHECK: {{movl 0[(]%eax[)], %ebx}} define i32 @foo(i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i) { %tmp9.i.i = call i32 asm sideeffect "push %ebp\0Apush %ebx\0Amovl 4($2),%ebp\0Amovl 0($2), %ebx\0Amovl $1,%eax\0Aint $$0x80\0Apop %ebx\0Apop %ebp", "={ax},i,0,{cx},{dx},{si},{di}"( i32 192, i32 %__s.i.i, i32 %tmp5.i.i, i32 %tmp6.i.i, i32 %tmp7.i.i, i32 %tmp8.i.i ) ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2006-11-27-SelectLegalize.ll b/test/CodeGen/X86/2006-11-27-SelectLegalize.ll index ea2e6db61e1a..ba83a8db8399 100644 --- a/test/CodeGen/X86/2006-11-27-SelectLegalize.ll +++ b/test/CodeGen/X86/2006-11-27-SelectLegalize.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=x86 | grep test.*1 +; RUN: llc < %s -march=x86 | FileCheck %s ; PR1016 +; CHECK: {{test.*1}} + define i32 @test(i32 %A, i32 %B, i32 %C) { %a = trunc i32 %A to i1 ; <i1> [#uses=1] %D = select i1 %a, i32 %B, i32 %C ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll b/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll index 18b06dc0857c..366f5830392d 100644 --- a/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll +++ b/test/CodeGen/X86/2007-03-24-InlineAsmVectorOp.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -mcpu=yonah -march=x86 | \ -; RUN: grep "cmpltsd %xmm0, %xmm0" +; RUN: llc < %s -mcpu=yonah -march=x86 | FileCheck %s + target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" +; CHECK: {{cmpltsd %xmm0, %xmm0}} define void @acoshf() { %tmp19 = tail call <2 x double> asm sideeffect "pcmpeqd $0, $0 \0A\09 cmpltsd $0, $0", "=x,0,~{dirflag},~{fpsr},~{flags}"( <2 x double> zeroinitializer ) ; <<2 x double>> [#uses=0] diff --git a/test/CodeGen/X86/2007-04-24-Huge-Stack.ll b/test/CodeGen/X86/2007-04-24-Huge-Stack.ll index 7528129971ab..648718cc7223 100644 --- a/test/CodeGen/X86/2007-04-24-Huge-Stack.ll +++ b/test/CodeGen/X86/2007-04-24-Huge-Stack.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=x86-64 | not grep 4294967112 +; RUN: llc < %s -march=x86-64 | FileCheck %s ; PR1348 +; CHECK-NOT: 4294967112 + %struct.md5_ctx = type { i32, i32, i32, i32, [2 x i32], i32, [128 x i8], [4294967288 x i8] } define i8* @md5_buffer(i8* %buffer, i64 %len, i8* %resblock) { diff --git a/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll index b27ef836960f..38fc5e18fe28 100644 --- a/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll +++ b/test/CodeGen/X86/2007-05-17-ShuffleISelBug.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep punpckhwd +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s + +; CHECK-NOT: punpckhwd declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) diff --git a/test/CodeGen/X86/2007-06-15-IntToMMX.ll b/test/CodeGen/X86/2007-06-15-IntToMMX.ll index 660d4fe7b19e..5612d9eb282c 100644 --- a/test/CodeGen/X86/2007-06-15-IntToMMX.ll +++ b/test/CodeGen/X86/2007-06-15-IntToMMX.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep paddusw +; RUN: llc < %s -march=x86-64 -mattr=+mmx | FileCheck %s + +; CHECK: paddusw + @R = external global x86_mmx ; <x86_mmx*> [#uses=1] define void @foo(<1 x i64> %A, <1 x i64> %B) { diff --git a/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll index 62624a7e3447..4f7ae327d1fd 100644 --- a/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll +++ b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 | not grep movl +; RUN: llc < %s -march=x86 | FileCheck %s + +; CHECK-NOT: movl define zeroext i8 @t(i8 zeroext %x, i8 zeroext %y) { %tmp2 = add i8 %x, 2 diff --git a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll index d3120f3e0ef7..82052b13e18d 100644 --- a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll +++ b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll @@ -1,4 +1,8 @@ -; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep inc | not grep PTR +; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | FileCheck %s + +; CHECK: inc +; CHECK-NOT: PTR +; CHECK: {{$}} define signext i16 @t(i32* %bitptr, i32* %source, i8** %byteptr, i32 %scale, i32 %round) { entry: diff --git a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll index 56a109acfc79..c4670242b531 100644 --- a/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll +++ b/test/CodeGen/X86/2007-11-04-rip-immediate-constant.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s -relocation-model=static | grep "foo str$" +; RUN: llc < %s -relocation-model=static | FileCheck %s ; PR1761 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-pc-linux" @str = internal constant [12 x i8] c"init/main.c\00" ; <[12 x i8]*> [#uses=1] +; CHECK: {{foo str$}} + define i32 @unknown_bootoption() { entry: tail call void asm sideeffect "foo ${0:c}\0A", "i,~{dirflag},~{fpsr},~{flags}"( i8* getelementptr ([12 x i8]* @str, i32 0, i64 0) ) diff --git a/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll b/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll index 6997d535ff92..e8c957b1ff64 100644 --- a/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll +++ b/test/CodeGen/X86/2008-01-09-LongDoubleSin.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -o - | grep sinl +; RUN: llc < %s -o - | FileCheck %s + +; CHECK: sinl target triple = "i686-pc-linux-gnu" diff --git a/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll index a52b36588a36..b06b249a6326 100644 --- a/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll +++ b/test/CodeGen/X86/2008-02-20-InlineAsmClobber.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s | grep "a:" | not grep ax -; RUN: llc < %s | grep "b:" | not grep ax +; RUN: llc < %s | FileCheck %s ; PR2078 ; The clobber list says that "ax" is clobbered. Make sure that eax isn't ; allocated to the input/output register. @@ -15,6 +14,10 @@ entry: ret void } +; CHECK: a: +; CHECK-NOT: ax +; CHECK: {{$}} + define void @test2(i16* %block, i8* %pixels, i32 %line_size) nounwind { entry: %tmp1 = getelementptr i16* %block, i32 64 ; <i16*> [#uses=1] @@ -22,3 +25,6 @@ entry: ret void } +; CHECK: b: +; CHECK-NOT: ax +; CHECK: {{$}} diff --git a/test/CodeGen/X86/2008-11-06-testb.ll b/test/CodeGen/X86/2008-11-06-testb.ll index f8f317c2dd46..e7caa7a10670 100644 --- a/test/CodeGen/X86/2008-11-06-testb.ll +++ b/test/CodeGen/X86/2008-11-06-testb.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | grep testb +; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s + +; CHECK: testb ; ModuleID = '<stdin>' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" diff --git a/test/CodeGen/X86/2009-02-25-CommuteBug.ll b/test/CodeGen/X86/2009-02-25-CommuteBug.ll index 9ea34e27a17e..5bec179534b9 100644 --- a/test/CodeGen/X86/2009-02-25-CommuteBug.ll +++ b/test/CodeGen/X86/2009-02-25-CommuteBug.ll @@ -1,7 +1,9 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | not grep commuted +; RUN: llc < %s -march=x86 -mattr=+sse2 -stats 2>&1 | FileCheck %s ; rdar://6608609 +; CHECK-NOT: commuted + define <2 x double> @t(<2 x double> %A, <2 x double> %B, <2 x double> %C) nounwind readnone { entry: %tmp.i2 = bitcast <2 x double> %B to <2 x i64> ; <<2 x i64>> [#uses=1] diff --git a/test/CodeGen/X86/2009-03-25-TestBug.ll b/test/CodeGen/X86/2009-03-25-TestBug.ll index f40fddc5a36d..cc1d73da05c5 100644 --- a/test/CodeGen/X86/2009-03-25-TestBug.ll +++ b/test/CodeGen/X86/2009-03-25-TestBug.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=x86 -o %t -; RUN: not grep and %t -; RUN: not grep shr %t +; RUN: llc < %s -march=x86 | FileCheck %s ; rdar://6661955 +; CHECK-NOT: and +; CHECK-NOT: shr + @hello = internal constant [7 x i8] c"hello\0A\00" @world = internal constant [7 x i8] c"world\0A\00" diff --git a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll index 0607eda271af..679a65d93d09 100644 --- a/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll +++ b/test/CodeGen/X86/2009-04-16-SpillerUnfold.ll @@ -1,8 +1,10 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats 2>&1 | grep "Number of modref unfolded" +; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats 2>&1 | FileCheck %s ; XFAIL: * ; 69408 removed the opportunity for this optimization to work +; CHECK: {{Number of modref unfolded}} + %struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 } %struct.anon = type { [16 x i64] } @K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2] diff --git a/test/CodeGen/X86/2009-04-24.ll b/test/CodeGen/X86/2009-04-24.ll index 08bf9e3f9f36..d104c875760a 100644 --- a/test/CodeGen/X86/2009-04-24.ll +++ b/test/CodeGen/X86/2009-04-24.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -optimize-regalloc=0 -relocation-model=pic > %t2 -; RUN: grep "leaq.*TLSGD" %t2 -; RUN: grep "__tls_get_addr" %t2 +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -optimize-regalloc=0 -relocation-model=pic | FileCheck %s ; PR4004 +; CHECK: {{leaq.*TLSGD}} +; CHECK: {{__tls_get_addr}} + @i = thread_local global i32 15 define i32 @f() { diff --git a/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll index 738b5fbb7048..7468acb95f11 100644 --- a/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll +++ b/test/CodeGen/X86/2009-05-08-InlineAsmIOffset.ll @@ -1,8 +1,9 @@ -; RUN: llc < %s -relocation-model=static > %t -; RUN: grep "1: ._pv_cpu_ops+8" %t -; RUN: grep "2: ._G" %t +; RUN: llc < %s -relocation-model=static | FileCheck %s ; PR4152 +; CHECK: {{1: ._pv_cpu_ops[+]8}} +; CHECK: {{2: ._G}} + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin9.6" %struct.pv_cpu_ops = type { i32, [2 x i32] } diff --git a/test/CodeGen/X86/2009-05-23-available_externally.ll b/test/CodeGen/X86/2009-05-23-available_externally.ll index 94773d91ea17..c990108a21c2 100644 --- a/test/CodeGen/X86/2009-05-23-available_externally.ll +++ b/test/CodeGen/X86/2009-05-23-available_externally.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=pic | grep atoi | grep PLT +; RUN: llc < %s -relocation-model=pic | FileCheck %s ; PR4253 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" @@ -9,6 +9,9 @@ entry: ret i32 %call } +; CHECK: foo +; CHECK: {{atoi.+PLT}} + define available_externally fastcc i32 @atoi(i8* %__nptr) nounwind readonly { entry: %call = tail call i64 @strtol(i8* nocapture %__nptr, i8** null, i32 10) nounwind readonly ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll b/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll index 30763225a53d..3061dc2c8275 100644 --- a/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll +++ b/test/CodeGen/X86/2009-06-05-ScalarToVectorByteMMX.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+mmx,+sse2 | not grep movl +; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mattr=+mmx,+sse2 | FileCheck %s + +; CHECK-NOT: movl define <8 x i8> @a(i8 zeroext %x) nounwind { %r = insertelement <8 x i8> undef, i8 %x, i32 0 diff --git a/test/CodeGen/X86/2009-08-08-CastError.ll b/test/CodeGen/X86/2009-08-08-CastError.ll index 2dc812dbc62d..748c5a8cc196 100644 --- a/test/CodeGen/X86/2009-08-08-CastError.ll +++ b/test/CodeGen/X86/2009-08-08-CastError.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=x86_64-pc-mingw64 | grep movabsq +; RUN: llc < %s -mtriple=x86_64-pc-mingw64 | FileCheck %s + +; CHECK: movabsq target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll index 8ab93fcb978f..7650a5c3be88 100644 --- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -203,7 +203,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 1921, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 786478, metadata !2, metadata !"__divsc3", metadata !"__divsc3", metadata !"__divsc3", metadata !2, i32 1922, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, %0 (float, float, float, float)* @__divsc3, null, null, metadata !43, i32 1922} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !45} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !44, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !44, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !45, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !9, metadata !9, metadata !9, metadata !9} !6 = metadata !{i32 786454, metadata !46, metadata !7, metadata !"SCtype", i32 170, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll index 6519ca063a7c..6510ff17f7bb 100644 --- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -25,7 +25,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786484, i32 0, metadata !1, metadata !"ret", metadata !"ret", metadata !"", metadata !1, i32 7, metadata !3, i1 false, i1 true, null} ; [ DW_TAG_variable ] !1 = metadata !{i32 786473, metadata !36} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !36, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !32, metadata !31, metadata !31, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !4 = metadata !{i32 786689, metadata !5, metadata !"x", metadata !1, i32 12, metadata !3, i32 0, null} ; [ DW_TAG_arg_variable ] !5 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 13, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, void (i32)* @foo, null, null, metadata !33, i32 13} ; [ DW_TAG_subprogram ] diff --git a/test/CodeGen/X86/2010-05-28-Crash.ll b/test/CodeGen/X86/2010-05-28-Crash.ll index 4ea3bf077841..ee00dbacbf60 100644 --- a/test/CodeGen/X86/2010-05-28-Crash.ll +++ b/test/CodeGen/X86/2010-05-28-Crash.ll @@ -27,7 +27,7 @@ entry: !0 = metadata !{i32 786689, metadata !1, metadata !"y", metadata !2, i32 2, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 (i32)* @foo, null, null, metadata !15, i32 2} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !17, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !17, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !6} !6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll index b22a391ef358..b5679e665696 100644 --- a/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll +++ b/test/CodeGen/X86/2010-06-14-fast-isel-fs-load.ll @@ -1,4 +1,5 @@ -; RUN: llc -fast-isel -march=x86 < %s | grep %fs: +; RUN: llc -fast-isel -march=x86 < %s | FileCheck %s +; CHECK: %fs: define i32 @test1(i32 addrspace(257)* %arg) nounwind { %tmp = load i32 addrspace(257)* %arg diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll index aaa562a439d5..91711bb758c3 100644 --- a/test/CodeGen/X86/2010-08-04-StackVariable.ll +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -80,7 +80,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", metadata !2, i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 11} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786451, metadata !2, metadata !"SVal", metadata !2, i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] !2 = metadata !{i32 786473, metadata !"small.cc", metadata !"/Users/manav/R8248330", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !46, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 4, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !46, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} !5 = metadata !{i32 786445, metadata !1, metadata !"Data", metadata !2, i32 7, i64 64, i64 64, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] !6 = metadata !{i32 786447, metadata !2, metadata !"", metadata !2, i32 0, i64 64, i64 64, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] diff --git a/test/CodeGen/X86/2010-11-02-DbgParameter.ll b/test/CodeGen/X86/2010-11-02-DbgParameter.ll index 31a6822b34b8..8719f738b7cc 100644 --- a/test/CodeGen/X86/2010-11-02-DbgParameter.ll +++ b/test/CodeGen/X86/2010-11-02-DbgParameter.ll @@ -19,7 +19,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (%struct.bar*)* @foo, null, null, metadata !16, i32 3} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !17} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, null, null, metadata !15, null, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 117922)", i1 true, metadata !"", i32 0, null, null, metadata !15, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll index 2355528a81e8..14fb3e493231 100644 --- a/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll +++ b/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll @@ -73,7 +73,7 @@ declare i32 @puts(i8* nocapture) nounwind !0 = metadata !{i32 786478, metadata !1, metadata !"gcd", metadata !"gcd", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i64 (i64, i64)* @gcd, null, null, metadata !29, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !31} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !31, i32 12, metadata !"clang version 2.9 (trunk 124117)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, null, metadata !2, metadata !"long int", i32 0, i64 64, i64 64, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll index 54d2b403509d..6d91109daafb 100644 --- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll +++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll @@ -96,7 +96,7 @@ while.body.i188: ; preds = %for.end173.i, %if.e while.body85.i: ; preds = %while.body85.i, %while.body.i188 %aFreq.0518.i = phi i32 [ %add93.i, %while.body85.i ], [ 0, %while.body.i188 ] %inc87.i = add nsw i32 0, 1 - %tmp91.i = load i32* undef, align 4, !tbaa !0 + %tmp91.i = load i32* undef, align 4 %add93.i = add nsw i32 %tmp91.i, %aFreq.0518.i %or.cond514.i = and i1 undef, false br i1 %or.cond514.i, label %while.body85.i, label %while.end.i @@ -168,7 +168,3 @@ if.end85: ; preds = %entry } declare void @fprintf(...) nounwind - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll b/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll index 832a8eb8144c..501a8101a3fe 100644 --- a/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll +++ b/test/CodeGen/X86/2012-01-10-UndefExceptionEdge.ll @@ -109,7 +109,7 @@ bb49: ; preds = %bb49, %bb48 %tmp51 = add i32 %tmp50, undef %tmp52 = add i32 %tmp50, undef %tmp53 = getelementptr i32* %tmp13, i32 %tmp52 - %tmp54 = load i32* %tmp53, align 4, !tbaa !0 + %tmp54 = load i32* %tmp53, align 4 %tmp55 = add i32 %tmp50, 1 %tmp56 = icmp eq i32 %tmp55, %tmp8 br i1 %tmp56, label %bb57, label %bb49 @@ -127,7 +127,7 @@ bb61: ; preds = %bb61, %bb59 %tmp62 = phi i32 [ %tmp65, %bb61 ], [ 0, %bb59 ] %tmp63 = add i32 %tmp62, %tmp14 %tmp64 = getelementptr i32* %tmp13, i32 %tmp63 - store i32 0, i32* %tmp64, align 4, !tbaa !0 + store i32 0, i32* %tmp64, align 4 %tmp65 = add i32 %tmp62, 1 %tmp66 = icmp eq i32 %tmp65, %tmp8 br i1 %tmp66, label %bb67, label %bb61 @@ -149,7 +149,3 @@ declare void @Pjii(i32*, i32, i32) optsize declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone declare void @OnOverFlow() noreturn optsize ssp align 2 - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll index 9525653f3fff..9164eb9c6912 100644 --- a/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll +++ b/test/CodeGen/X86/2012-11-30-handlemove-dbg.ll @@ -18,7 +18,7 @@ define signext i16 @subdivp(%struct.node.0.27* nocapture %p, double %dsq, double entry: call void @llvm.dbg.declare(metadata !{%struct.hgstruct.2.29* %hg}, metadata !4) %type = getelementptr inbounds %struct.node.0.27* %p, i64 0, i32 0 - %0 = load i16* %type, align 2, !tbaa !8 + %0 = load i16* %type, align 2 %cmp = icmp eq i16 %0, 1 br i1 %cmp, label %return, label %for.cond.preheader @@ -45,7 +45,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !5 = metadata !{i32 786473, metadata !11} ; [ DW_TAG_file_type ] !6 = metadata !{i32 786454, metadata !11, null, metadata !"hgstruct", i32 492, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] [hgstruct] [line 492, size 0, align 0, offset 0] [from ] !7 = metadata !{i32 786451, metadata !11, null, metadata !"", i32 487, i64 512, i64 64, i32 0, i32 0, null, null, i32 0, i32 0, i32 0} ; [ DW_TAG_structure_type ] [line 487, size 512, align 64, offset 0] [from ] -!8 = metadata !{metadata !"short", metadata !9} -!9 = metadata !{metadata !"omnipotent char", metadata !10} -!10 = metadata !{metadata !"Simple C/C++ TBAA"} !11 = metadata !{metadata !"MultiSource/Benchmarks/Olden/bh/newbh.c", metadata !"MultiSource/Benchmarks/Olden/bh"} diff --git a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll index 03b6bdeafa87..f0c7781fafe9 100644 --- a/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll +++ b/test/CodeGen/X86/2013-03-13-VEX-DestReg.ll @@ -9,7 +9,7 @@ target triple = "x86_64-apple-macosx10.8.0" define void @main() #0 { entry: - %0 = load <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32, !tbaa !0 + %0 = load <8 x float>* bitcast ([8 x float]* @b to <8 x float>*), align 32 %bitcast.i = extractelement <8 x float> %0, i32 0 %vecinit.i.i = insertelement <4 x float> undef, float %bitcast.i, i32 0 %vecinit2.i.i = insertelement <4 x float> %vecinit.i.i, float 0.000000e+00, i32 1 @@ -17,7 +17,7 @@ entry: %vecinit4.i.i = insertelement <4 x float> %vecinit3.i.i, float 0.000000e+00, i32 3 %1 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %vecinit4.i.i) #2 %vecext.i.i = extractelement <4 x float> %1, i32 0 - store float %vecext.i.i, float* getelementptr inbounds ([8 x float]* @e, i64 0, i64 0), align 16, !tbaa !0 + store float %vecext.i.i, float* getelementptr inbounds ([8 x float]* @e, i64 0, i64 0), align 16 unreachable } @@ -26,6 +26,3 @@ declare <4 x float> @llvm.x86.sse.rcp.ss(<4 x float>) #1 attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/2013-05-06-ConactVectorCrash.ll b/test/CodeGen/X86/2013-05-06-ConactVectorCrash.ll new file mode 100644 index 000000000000..920341799d63 --- /dev/null +++ b/test/CodeGen/X86/2013-05-06-ConactVectorCrash.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=x86 + +; Make sure this doesn't crash + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-pc-win32" + +define void @foo() { + %1 = shufflevector <3 x i8> undef, <3 x i8> undef, <2 x i32> <i32 0, i32 1> + %2 = shufflevector <2 x i8> %1, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> + %3 = shufflevector <4 x i8> undef, <4 x i8> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 5> + store <4 x i8> %3, <4 x i8>* undef + ret void +} diff --git a/test/CodeGen/X86/MachineSink-DbgValue.ll b/test/CodeGen/X86/MachineSink-DbgValue.ll index 227ef3466e0a..13a6444a496b 100644 --- a/test/CodeGen/X86/MachineSink-DbgValue.ll +++ b/test/CodeGen/X86/MachineSink-DbgValue.ll @@ -27,7 +27,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, null, null, metadata !18, null, null, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i32*)* @foo, null, null, metadata !19, i32 0} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll index 03d2e472cba6..5fe08ed305f1 100644 --- a/test/CodeGen/X86/add.ll +++ b/test/CodeGen/X86/add.ll @@ -119,8 +119,8 @@ entry: ; X64: test8: ; X64: addq -; X64-NEXT: sbbq -; X64-NEXT: testb +; X64-NEXT: setb +; X64: ret define i32 @test9(i32 %x, i32 %y) nounwind readnone { %cmp = icmp eq i32 %x, 10 diff --git a/test/CodeGen/X86/asm-invalid-register-class-crasher.ll b/test/CodeGen/X86/asm-invalid-register-class-crasher.ll new file mode 100644 index 000000000000..24e2284c8c8b --- /dev/null +++ b/test/CodeGen/X86/asm-invalid-register-class-crasher.ll @@ -0,0 +1,9 @@ +; RUN: not llc < %s -mtriple=i386-apple-darwin 2>&1 %t + +; Previously, this would assert in an assert build, but crash in a release build. +; No FileCheck, just make sure we handle this gracefully. +define i64 @t1(i64* %p, i64 %val) #0 { +entry: + %0 = tail call i64 asm sideeffect "xaddq $0, $1", "=q,*m,0,~{memory},~{cc},~{dirflag},~{fpsr},~{flags}"(i64* %p, i64 %val) + ret i64 %0 +} diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll index 2a34e0298f30..6237b66a5ea6 100644 --- a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload32.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=atom 2>&1 | \ -; RUN: grep "calll" | not grep "(" -; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=core2 2>&1 | \ -; RUN: grep "calll" | grep "*funcp" +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=atom | \ +; RUN: FileCheck --check-prefix=ATOM %s +; RUN: llc < %s -mtriple=i386-linux-gnu -mcpu=core2 | \ +; RUN: FileCheck --check-prefix=CORE2 %s +; ATOM: calll *{{%[a-z]+}} +; CORE2: calll *funcp ; ; original source code built with clang -S -emit-llvm -M32 test32.c: ; @@ -18,10 +20,6 @@ ; } ; } ; -; ModuleID = 'test32.c' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" -target triple = "i386-unknown-linux-gnu" - @sum = external global i32 @a = common global i32 0, align 4 @i = common global i32 0, align 4 @@ -74,4 +72,3 @@ for.end: ; preds = %for.cond ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll index bcfbd6107a56..a196d8175aa9 100644 --- a/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll +++ b/test/CodeGen/X86/atom-call-reg-indirect-foldedreload64.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=atom 2>&1 | \ -; RUN: grep "callq" | not grep "(" -; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core2 2>&1 | \ -; RUN: grep "callq" | grep "*funcp" +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=atom | \ +; RUN: FileCheck --check-prefix=ATOM %s +; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=core2 | \ +; RUN: FileCheck --check-prefix=CORE2 %s +; ATOM: callq *{{%[a-z]+[0-9]*}} +; CORE2: callq *funcp ; ; Original source code built with clang -S -emit-llvm -m64 test64.c: ; int a, b, c, d, e, f, g, h, i, j, k, l, m, n; @@ -19,9 +21,6 @@ ; } ; } ; -; ModuleID = 'test64.c' -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" -target triple = "x86_64-unknown-linux-gnu" @sum = external global i32 @a = common global i32 0, align 4 @@ -88,4 +87,3 @@ for.end: ; preds = %for.cond ret void } -attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/X86/atom-fixup-lea1.ll b/test/CodeGen/X86/atom-fixup-lea1.ll new file mode 100644 index 000000000000..4651bf257fd4 --- /dev/null +++ b/test/CodeGen/X86/atom-fixup-lea1.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s +; CHECK: addl +; CHECK-NEXT:leal +; CHECK-NEXT:decl +; CHECK-NEXT:jne + +; Test for the FixupLEAs pre-emit pass. An LEA should be substituted for the ADD +; that increments the array pointer because it is within 5 instructions of the +; corresponding load. The ADD precedes the load by following the loop back edge. + +; Original C code +;int test(int n, int * array) +;{ +; int sum = 0; +; for(int i = 0; i < n; i++) +; sum += array[i]; +; return sum; +;} + +define i32 @test(i32 %n, i32* nocapture %array) { +entry: + %cmp4 = icmp sgt i32 %n, 0 + br i1 %cmp4, label %for.body, label %for.end + +for.body: + %i.06 = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %array, i32 %i.06 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %sum.05 + %inc = add nsw i32 %i.06, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: + %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ] + ret i32 %sum.0.lcssa +} diff --git a/test/CodeGen/X86/atom-fixup-lea2.ll b/test/CodeGen/X86/atom-fixup-lea2.ll new file mode 100644 index 000000000000..1855ea1d024d --- /dev/null +++ b/test/CodeGen/X86/atom-fixup-lea2.ll @@ -0,0 +1,84 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s +; CHECK:BB#5 +; CHECK-NEXT:leal +; CHECK-NEXT:leal +; CHECK-NEXT:leal +; CHECK-NEXT:movl + + +; Test for fixup lea pre-emit pass. LEA instructions should be substituted for +; ADD instructions which compute the address and index of the load because they +; precede the load within 5 instructions. An LEA should also be substituted for +; an ADD which computes part of the index because it precedes the index LEA +; within 5 instructions, this substitution is referred to as backwards chaining. + +; Original C Code +;struct node_t +;{ +; int k, m, n, p; +; int * array; +;}; + +;extern struct node_t getnode(); + +;int test() +;{ +; int sum = 0; +; struct node_t n = getnode(); +; if(n.array != 0 && n.p > 0 && n.k > 0 && n.n > 0 && n.m > 0) { +; sum = ((int*)((int)n.array + n.p) )[ n.k + n.m + n.n ]; +; } +; return sum; +;} + +%struct.node_t = type { i32, i32, i32, i32, i32* } + +define i32 @test() { +entry: + %n = alloca %struct.node_t, align 4 + call void bitcast (void (%struct.node_t*, ...)* @getnode to void (%struct.node_t*)*)(%struct.node_t* sret %n) + %array = getelementptr inbounds %struct.node_t* %n, i32 0, i32 4 + %0 = load i32** %array, align 4 + %cmp = icmp eq i32* %0, null + br i1 %cmp, label %if.end, label %land.lhs.true + +land.lhs.true: + %p = getelementptr inbounds %struct.node_t* %n, i32 0, i32 3 + %1 = load i32* %p, align 4 + %cmp1 = icmp sgt i32 %1, 0 + br i1 %cmp1, label %land.lhs.true2, label %if.end + +land.lhs.true2: + %k = getelementptr inbounds %struct.node_t* %n, i32 0, i32 0 + %2 = load i32* %k, align 4 + %cmp3 = icmp sgt i32 %2, 0 + br i1 %cmp3, label %land.lhs.true4, label %if.end + +land.lhs.true4: + %n5 = getelementptr inbounds %struct.node_t* %n, i32 0, i32 2 + %3 = load i32* %n5, align 4 + %cmp6 = icmp sgt i32 %3, 0 + br i1 %cmp6, label %land.lhs.true7, label %if.end + +land.lhs.true7: + %m = getelementptr inbounds %struct.node_t* %n, i32 0, i32 1 + %4 = load i32* %m, align 4 + %cmp8 = icmp sgt i32 %4, 0 + br i1 %cmp8, label %if.then, label %if.end + +if.then: + %add = add i32 %3, %2 + %add12 = add i32 %add, %4 + %5 = ptrtoint i32* %0 to i32 + %add15 = add nsw i32 %1, %5 + %6 = inttoptr i32 %add15 to i32* + %arrayidx = getelementptr inbounds i32* %6, i32 %add12 + %7 = load i32* %arrayidx, align 4 + br label %if.end + +if.end: + %sum.0 = phi i32 [ %7, %if.then ], [ 0, %land.lhs.true7 ], [ 0, %land.lhs.true4 ], [ 0, %land.lhs.true2 ], [ 0, %land.lhs.true ], [ 0, %entry ] + ret i32 %sum.0 +} + +declare void @getnode(%struct.node_t* sret, ...) diff --git a/test/CodeGen/X86/atom-fixup-lea3.ll b/test/CodeGen/X86/atom-fixup-lea3.ll new file mode 100644 index 000000000000..311b0b302163 --- /dev/null +++ b/test/CodeGen/X86/atom-fixup-lea3.ll @@ -0,0 +1,51 @@ +; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s +; CHECK: addl ([[reg:%[a-z]+]]) +; CHECK-NEXT: addl $4, [[reg]] + +; Test for the FixupLEAs pre-emit pass. +; An LEA should NOT be substituted for the ADD instruction +; that increments the array pointer if it is greater than 5 instructions +; away from the memory reference that uses it. + +; Original C code: clang -m32 -S -O2 +;int test(int n, int * array, int * m, int * array2) +;{ +; int i, j = 0; +; int sum = 0; +; for (i = 0, j = 0; i < n;) { +; ++i; +; *m += array2[j++]; +; sum += array[i]; +; } +; return sum; +;} + +define i32 @test(i32 %n, i32* nocapture %array, i32* nocapture %m, i32* nocapture %array2) #0 { +entry: + %cmp7 = icmp sgt i32 %n, 0 + br i1 %cmp7, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + %.pre = load i32* %m, align 4 + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph + %0 = phi i32 [ %.pre, %for.body.lr.ph ], [ %add, %for.body ] + %sum.010 = phi i32 [ 0, %for.body.lr.ph ], [ %add3, %for.body ] + %j.09 = phi i32 [ 0, %for.body.lr.ph ], [ %inc1, %for.body ] + %inc1 = add nsw i32 %j.09, 1 + %arrayidx = getelementptr inbounds i32* %array2, i32 %j.09 + %1 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %1 + store i32 %add, i32* %m, align 4 + %arrayidx2 = getelementptr inbounds i32* %array, i32 %inc1 + %2 = load i32* %arrayidx2, align 4 + %add3 = add nsw i32 %2, %sum.010 + %exitcond = icmp eq i32 %inc1, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body, %entry + %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add3, %for.body ] + ret i32 %sum.0.lcssa +} + diff --git a/test/CodeGen/X86/atomic-dagsched.ll b/test/CodeGen/X86/atomic-dagsched.ll index 0e7cf8c09668..05e630be153c 100644 --- a/test/CodeGen/X86/atomic-dagsched.ll +++ b/test/CodeGen/X86/atomic-dagsched.ll @@ -18,8 +18,8 @@ loop.cond: ; preds = %test.exit, %entry br i1 %3, label %return, label %loop loop: ; preds = %loop.cond - %4 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0 - %5 = load i64* %4, align 8, !tbaa !3 + %4 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8 + %5 = load i64* %4, align 8 %vector.size.i = ashr i64 %5, 3 %num.vector.wi.i = shl i64 %vector.size.i, 3 %6 = icmp eq i64 %vector.size.i, 0 @@ -65,8 +65,8 @@ scalarIf.i: ; preds = %vector_kernel_entry br i1 %18, label %test.exit, label %dim_0_pre_head.i dim_0_pre_head.i: ; preds = %scalarIf.i - %19 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8, !tbaa !0 - %20 = load i64* %19, align 8, !tbaa !3 + %19 = load i64* addrspace(256)* inttoptr (i64 264 to i64* addrspace(256)*), align 8 + %20 = load i64* %19, align 8 %21 = trunc i64 %20 to i32 %22 = mul i64 %vector.size.i, 8 br label %scalar_kernel_entry.i @@ -76,10 +76,10 @@ scalar_kernel_entry.i: ; preds = %scalar_kernel_entry %23 = bitcast i8* %asr.iv6 to i32 addrspace(1)* %24 = bitcast i8* %ptrtoarg4 to i32 addrspace(1)* %scevgep16 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12 - %25 = load i32 addrspace(1)* %scevgep16, align 4, !tbaa !4 + %25 = load i32 addrspace(1)* %scevgep16, align 4 %26 = atomicrmw min i32 addrspace(1)* %24, i32 %25 seq_cst %scevgep15 = getelementptr i32 addrspace(1)* %23, i64 %asr.iv12 - store i32 %21, i32 addrspace(1)* %scevgep15, align 4, !tbaa !4 + store i32 %21, i32 addrspace(1)* %scevgep15, align 4 %asr.iv.next13 = add i64 %asr.iv12, 1 %dim_0_cmp.to.max.i = icmp eq i64 %5, %asr.iv.next13 br i1 %dim_0_cmp.to.max.i, label %test.exit, label %scalar_kernel_entry.i @@ -97,12 +97,6 @@ return: ; preds = %loop.cond ret void } -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"long", metadata !1} -!4 = metadata !{metadata !"int", metadata !1} - ; CHECK: test ; CHECK: decq ; CHECK-NOT: cmpxchgl diff --git a/test/CodeGen/X86/avx-basic.ll b/test/CodeGen/X86/avx-basic.ll index 95854c7960e7..64c4627c47c3 100644 --- a/test/CodeGen/X86/avx-basic.ll +++ b/test/CodeGen/X86/avx-basic.ll @@ -121,3 +121,13 @@ define <16 x i16> @build_vec_16x16(i16 %a) nounwind readonly { %res = insertelement <16 x i16> <i16 undef, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, i16 %a, i32 0 ret <16 x i16> %res } + +;;; Check that VMOVPQIto64rr generates the assembly string "vmovd". Previously +;;; an incorrect mnemonic of "movd" was printed for this instruction. +; CHECK: VMOVPQIto64rr +; CHECK: vmovd +define i64 @VMOVPQIto64rr(<2 x i64> %a) { +entry: + %vecext.i = extractelement <2 x i64> %a, i32 0 + ret i64 %vecext.i +} diff --git a/test/CodeGen/X86/avx-brcond.ll b/test/CodeGen/X86/avx-brcond.ll new file mode 100644 index 000000000000..d52ae52e0b98 --- /dev/null +++ b/test/CodeGen/X86/avx-brcond.ll @@ -0,0 +1,150 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +declare i32 @llvm.x86.avx.ptestz.256(<4 x i64> %p1, <4 x i64> %p2) nounwind +declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind + +define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test1: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test3: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test4: +; CHECK: vptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test6: +; CHECK: vptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test7: +; CHECK: vptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test8: +; CHECK: vptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a, <4 x i64> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + + diff --git a/test/CodeGen/X86/block-placement.ll b/test/CodeGen/X86/block-placement.ll index 5534712af832..271fb4250517 100644 --- a/test/CodeGen/X86/block-placement.ll +++ b/test/CodeGen/X86/block-placement.ll @@ -524,7 +524,7 @@ entry: br i1 %cond, label %entry.if.then_crit_edge, label %lor.lhs.false, !prof !1 entry.if.then_crit_edge: - %.pre14 = load i8* undef, align 1, !tbaa !0 + %.pre14 = load i8* undef, align 1 br label %if.then lor.lhs.false: @@ -537,7 +537,7 @@ exit: if.then: %0 = phi i8 [ %.pre14, %entry.if.then_crit_edge ], [ undef, %exit ] %1 = and i8 %0, 1 - store i8 %1, i8* undef, align 4, !tbaa !0 + store i8 %1, i8* undef, align 4 br label %if.end if.end: diff --git a/test/CodeGen/X86/brcond.ll b/test/CodeGen/X86/brcond.ll index 44670c802b41..bc4032b13cc0 100644 --- a/test/CodeGen/X86/brcond.ll +++ b/test/CodeGen/X86/brcond.ll @@ -108,3 +108,150 @@ bb2: ; preds = %entry, %bb1 ret float %.0 } +declare i32 @llvm.x86.sse41.ptestz(<4 x float> %p1, <4 x float> %p2) nounwind +declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind + +define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test5: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test7: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test8: +; CHECK: ptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 0 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test10: +; CHECK: ptest +; CHECK-NEXT: jae +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestc(<4 x float> %a, <4 x float> %a) nounwind + %one = trunc i32 %res to i1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test11: +; CHECK: ptest +; CHECK-NEXT: jne +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp eq i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + +define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind { +entry: +; CHECK: test12: +; CHECK: ptest +; CHECK-NEXT: je +; CHECK: ret + + %res = call i32 @llvm.x86.sse41.ptestz(<4 x float> %a, <4 x float> %a) nounwind + %one = icmp ne i32 %res, 1 + br i1 %one, label %bb1, label %bb2 + +bb1: + %c = fadd <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +bb2: + %d = fdiv <4 x float> %b, < float 1.000000e+002, float 2.000000e+002, float 3.000000e+002, float 4.000000e+002 > + br label %return + +return: + %e = phi <4 x float> [%c, %bb1], [%d, %bb2] + ret <4 x float> %e +} + diff --git a/test/CodeGen/X86/bswap-inline-asm.ll b/test/CodeGen/X86/bswap-inline-asm.ll index 3bb9124633d6..d69bfa6e7eb7 100644 --- a/test/CodeGen/X86/bswap-inline-asm.ll +++ b/test/CodeGen/X86/bswap-inline-asm.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin > %t -; RUN: not grep InlineAsm %t -; RUN: FileCheck %s < %t +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix CHK %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s + +; CHK-NOT: InlineAsm ; CHECK: foo: ; CHECK: bswapq diff --git a/test/CodeGen/X86/bt.ll b/test/CodeGen/X86/bt.ll index 39a784dec37d..e28923bb21d2 100644 --- a/test/CodeGen/X86/bt.ll +++ b/test/CodeGen/X86/bt.ll @@ -522,11 +522,8 @@ UnifiedReturnBlock: ; preds = %entry declare void @foo() -; rdar://12755626 define zeroext i1 @invert(i32 %flags, i32 %flag) nounwind { -; CHECK: invert -; CHECK: btl %eax, %ecx -; CHECK: setae +; CHECK: btl entry: %neg = xor i32 %flags, -1 %shl = shl i32 1, %flag diff --git a/test/CodeGen/X86/call-imm.ll b/test/CodeGen/X86/call-imm.ll index 38cda4d14040..8753594df10a 100644 --- a/test/CodeGen/X86/call-imm.ll +++ b/test/CodeGen/X86/call-imm.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=static | grep "call.*12345678" -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | not grep "call.*12345678" -; RUN: llc < %s -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | grep "call.*12345678" +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=static | FileCheck -check-prefix X86STA %s +; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | FileCheck -check-prefix X86PIC %s +; RUN: llc < %s -mtriple=i386-pc-linux -relocation-model=dynamic-no-pic | FileCheck -check-prefix X86DYN %s ; Call to immediate is not safe on x86-64 unless we *know* that the ; call will be within 32-bits pcrel from the dest immediate. -; RUN: llc < %s -march=x86-64 | grep "call.*\*%rax" +; RUN: llc < %s -march=x86-64 | FileCheck -check-prefix X64 %s ; PR3666 ; PR3773 @@ -16,3 +16,8 @@ entry: %0 = call i32 inttoptr (i32 12345678 to i32 (i32)*)(i32 0) nounwind ; <i32> [#uses=1] ret i32 %0 } + +; X86STA: {{call.*12345678}} +; X86PIC-NOT: {{call.*12345678}} +; X86DYN: {{call.*12345678}} +; X64: {{call.*[*]%rax}} diff --git a/test/CodeGen/X86/coalescer-identity.ll b/test/CodeGen/X86/coalescer-identity.ll index 9c72ee6296bd..1aac09594c43 100644 --- a/test/CodeGen/X86/coalescer-identity.ll +++ b/test/CodeGen/X86/coalescer-identity.ll @@ -12,10 +12,10 @@ target triple = "x86_64-apple-macosx10.8.0" define void @func() nounwind uwtable ssp { for.body.lr.ph: - %0 = load i32* @g2, align 4, !tbaa !0 + %0 = load i32* @g2, align 4 %tobool6 = icmp eq i32 %0, 0 %s.promoted = load i16* @s, align 2 - %.pre = load i32* @g1, align 4, !tbaa !0 + %.pre = load i32* @g1, align 4 br i1 %tobool6, label %for.body.us, label %for.body for.body.us: ; preds = %for.body.lr.ph, %for.inc.us @@ -43,11 +43,11 @@ for.inc.us: ; preds = %cond.end.us, %for.b cond.end.us: ; preds = %if.then7.us, %cond.false.us %4 = phi i32 [ 0, %cond.false.us ], [ %1, %if.then7.us ] %cond.us = phi i32 [ 0, %cond.false.us ], [ %v.010.us, %if.then7.us ] - store i32 %cond.us, i32* @g0, align 4, !tbaa !0 + store i32 %cond.us, i32* @g0, align 4 br label %for.inc.us cond.false.us: ; preds = %if.then7.us - store i32 0, i32* @g1, align 4, !tbaa !0 + store i32 0, i32* @g1, align 4 br label %cond.end.us if.then7.us: ; preds = %for.body.us @@ -76,7 +76,3 @@ for.end: ; preds = %for.inc.us, %for.bo store i16 %dec12.lcssa, i16* @s, align 2 ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/code_placement_align_all.ll b/test/CodeGen/X86/code_placement_align_all.ll new file mode 100644 index 000000000000..1e5e8f780b70 --- /dev/null +++ b/test/CodeGen/X86/code_placement_align_all.ll @@ -0,0 +1,22 @@ +; RUN: llc -mcpu=corei7 -mtriple=x86_64-linux -align-all-blocks=16 < %s | FileCheck %s + +;CHECK: foo +;CHECK: .align 65536, 0x90 +;CHECK: .align 65536, 0x90 +;CHECK: .align 65536, 0x90 +;CHECK: ret +define i32 @foo(i32 %t, i32 %l) nounwind readnone ssp uwtable { + %1 = icmp eq i32 %t, 0 + br i1 %1, label %4, label %2 + +; <label>:2 ; preds = %0 + %3 = add nsw i32 %t, 2 + ret i32 %3 + +; <label>:4 ; preds = %0 + %5 = icmp eq i32 %l, 0 + %. = select i1 %5, i32 0, i32 5 + ret i32 %. +} + + diff --git a/test/CodeGen/X86/codegen-prepare.ll b/test/CodeGen/X86/codegen-prepare.ll new file mode 100644 index 000000000000..e8ee07063531 --- /dev/null +++ b/test/CodeGen/X86/codegen-prepare.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s + +; Check that the CodeGenPrepare Pass +; does not wrongly rewrite the address computed by Instruction %4 +; as [12 + Base:%this]. + +; This test makes sure that: +; - both the store and the first load instructions +; within basic block labeled 'if.then' are not removed. +; - the store instruction stores a value at address [60 + %this] +; - the first load instruction loads a value at address [12 + %this] + +%class.A = type { %struct.B } +%struct.B = type { %class.C, %class.D, %class.C, %class.D } +%class.C = type { float, float, float } +%class.D = type { [3 x %class.C] } + +define linkonce_odr void @foo(%class.A* nocapture %this, i32 %BoolValue) nounwind uwtable { +entry: + %cmp = icmp eq i32 %BoolValue, 0 + %address1 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 3 + %address2 = getelementptr inbounds %class.A* %this, i64 0, i32 0, i32 1 + br i1 %cmp, label %if.else, label %if.then + +if.then: ; preds = %entry + %0 = getelementptr inbounds %class.D* %address2, i64 0, i32 0, i64 0, i32 0 + %1 = load float* %0, align 4 + %2 = getelementptr inbounds float* %0, i64 3 + %3 = load float* %2, align 4 + %4 = getelementptr inbounds %class.D* %address1, i64 0, i32 0, i64 0, i32 0 + store float %1, float* %4, align 4 + br label %if.end + +if.else: ; preds = %entry + br label %if.end + +if.end: ; preds = %if.then, %if.else, %entry + ret void +} + +; CHECK: foo: +; CHECK: movss 12([[THIS:%[a-zA-Z0-9]+]]), [[REGISTER:%[a-zA-Z0-9]+]] +; CHECK-NEXT: movss [[REGISTER]], 60([[THIS]]) + diff --git a/test/CodeGen/X86/commute-intrinsic.ll b/test/CodeGen/X86/commute-intrinsic.ll index d810cb1eff78..7d5ca4766892 100644 --- a/test/CodeGen/X86/commute-intrinsic.ll +++ b/test/CodeGen/X86/commute-intrinsic.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -relocation-model=static | not grep movaps +; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -relocation-model=static | FileCheck %s + +; CHECK-NOT: movaps @a = external global <2 x i64> ; <<2 x i64>*> [#uses=1] diff --git a/test/CodeGen/X86/compact-unwind.ll b/test/CodeGen/X86/compact-unwind.ll new file mode 100644 index 000000000000..8c4fa27da560 --- /dev/null +++ b/test/CodeGen/X86/compact-unwind.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -disable-cfi -disable-fp-elim -mtriple x86_64-apple-darwin11 | FileCheck %s + +%ty = type { i8* } + +@gv = external global i32 + +; This is aligning the stack with a push of a random register. +; CHECK: pushq %rax + +; Even though we can't encode %rax into the compact unwind, We still want to be +; able to generate a compact unwind encoding in this particular case. +; +; CHECK: __LD,__compact_unwind +; CHECK: _foo ## Range Start +; CHECK: 16842753 ## Compact Unwind Encoding: 0x1010001 + +define i8* @foo(i64 %size) { + %addr = alloca i64, align 8 + %tmp20 = load i32* @gv, align 4 + %tmp21 = call i32 @bar() + %tmp25 = load i64* %addr, align 8 + %tmp26 = inttoptr i64 %tmp25 to %ty* + %tmp29 = getelementptr inbounds %ty* %tmp26, i64 0, i32 0 + %tmp34 = load i8** %tmp29, align 8 + %tmp35 = getelementptr inbounds i8* %tmp34, i64 %size + store i8* %tmp35, i8** %tmp29, align 8 + ret i8* null +} + +declare i32 @bar() diff --git a/test/CodeGen/X86/compiler_used.ll b/test/CodeGen/X86/compiler_used.ll index be8de5e09f8a..d38ce91310b1 100644 --- a/test/CodeGen/X86/compiler_used.ll +++ b/test/CodeGen/X86/compiler_used.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep no_dead_strip | count 1 -; We should have a .no_dead_strip directive for Z but not for X/Y. +; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s @X = internal global i8 4 @Y = internal global i32 123 @@ -7,3 +6,7 @@ @llvm.used = appending global [1 x i8*] [ i8* @Z ], section "llvm.metadata" @llvm.compiler_used = appending global [2 x i8*] [ i8* @X, i8* bitcast (i32* @Y to i8*)], section "llvm.metadata" + +; CHECK-NOT: .no_dead_strip +; CHECK: .no_dead_strip _Z +; CHECK-NOT: .no_dead_strip diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 6d2196206e7c..852b642de68d 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -238,7 +238,7 @@ declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { bb: - %tmp = load %t9** undef, align 4, !tbaa !0 + %tmp = load %t9** undef, align 4 %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 br label %bb4 diff --git a/test/CodeGen/X86/dbg-byval-parameter.ll b/test/CodeGen/X86/dbg-byval-parameter.ll index aca06a27a1df..719a526cc892 100644 --- a/test/CodeGen/X86/dbg-byval-parameter.ll +++ b/test/CodeGen/X86/dbg-byval-parameter.ll @@ -30,7 +30,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !0 = metadata !{i32 786689, metadata !1, metadata !"my_r0", metadata !2, i32 11, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 11, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, double (%struct.Rect*)* @foo, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !19, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7} !6 = metadata !{i32 786468, metadata !19, metadata !2, metadata !"double", i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/X86/dbg-const-int.ll b/test/CodeGen/X86/dbg-const-int.ll index aabc2068068d..f72729c5fee1 100644 --- a/test/CodeGen/X86/dbg-const-int.ll +++ b/test/CodeGen/X86/dbg-const-int.ll @@ -14,7 +14,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, null, null, metadata !11, null, null} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 132191)", i1 true, metadata !"", i32 0, null, null, metadata !11, null, null, null} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null, metadata !12, i32 0} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/X86/dbg-const.ll b/test/CodeGen/X86/dbg-const.ll index a9b8f1fdc4f3..5c2e62bc9168 100644 --- a/test/CodeGen/X86/dbg-const.ll +++ b/test/CodeGen/X86/dbg-const.ll @@ -20,7 +20,7 @@ declare i32 @bar() nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar, null, null, metadata !14, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !15} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, null, null, metadata !13, null, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 2.9 (trunk 114183)", i1 true, metadata !"", i32 0, null, null, metadata !13, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} diff --git a/test/CodeGen/X86/dbg-i128-const.ll b/test/CodeGen/X86/dbg-i128-const.ll index 17d645757d99..cc612b2ca53e 100644 --- a/test/CodeGen/X86/dbg-i128-const.ll +++ b/test/CodeGen/X86/dbg-i128-const.ll @@ -19,7 +19,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !2 = metadata !{i32 786443, metadata !4, metadata !3, i32 26, i32 0, i32 0} ; [ DW_TAG_lexical_block ] !3 = metadata !{i32 786478, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i128 (i128, i128)* @__foo, null, null, null, i32 26} ; [ DW_TAG_subprogram ] !4 = metadata !{i32 786473, metadata !13} ; [ DW_TAG_file_type ] -!5 = metadata !{i32 786449, i32 1, metadata !4, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !12, null, metadata !""} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 786449, i32 1, metadata !4, metadata !"clang", i1 true, metadata !"", i32 0, null, null, metadata !12, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !6 = metadata !{i32 786453, metadata !13, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{metadata !8, metadata !8, metadata !8} !8 = metadata !{i32 786454, metadata !14, metadata !4, metadata !"ti_int", i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ] diff --git a/test/CodeGen/X86/dbg-large-unsigned-const.ll b/test/CodeGen/X86/dbg-large-unsigned-const.ll index ff16318efcec..c381cd754cfe 100644 --- a/test/CodeGen/X86/dbg-large-unsigned-const.ll +++ b/test/CodeGen/X86/dbg-large-unsigned-const.ll @@ -7,8 +7,8 @@ define zeroext i1 @_Z3iseRKxS0_(i64* nocapture %LHS, i64* nocapture %RHS) nounwi entry: tail call void @llvm.dbg.value(metadata !{i64* %LHS}, i64 0, metadata !7), !dbg !13 tail call void @llvm.dbg.value(metadata !{i64* %RHS}, i64 0, metadata !11), !dbg !14 - %tmp1 = load i64* %LHS, align 4, !dbg !15, !tbaa !17 - %tmp3 = load i64* %RHS, align 4, !dbg !15, !tbaa !17 + %tmp1 = load i64* %LHS, align 4, !dbg !15 + %tmp3 = load i64* %RHS, align 4, !dbg !15 %cmp = icmp eq i64 %tmp1, %tmp3, !dbg !15 ret i1 %cmp, !dbg !15 } @@ -47,9 +47,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !14 = metadata !{i32 2, i32 49, metadata !1, null} !15 = metadata !{i32 3, i32 3, metadata !16, null} !16 = metadata !{i32 786443, metadata !2, metadata !1, i32 2, i32 54, i32 0} ; [ DW_TAG_lexical_block ] -!17 = metadata !{metadata !"long long", metadata !18} -!18 = metadata !{metadata !"omnipotent char", metadata !19} -!19 = metadata !{metadata !"Simple C/C++ TBAA", null} !20 = metadata !{i32 6, i32 19, metadata !6, null} !21 = metadata !{i32 786689, metadata !1, metadata !"LHS", metadata !2, i32 16777218, metadata !8, i32 0, metadata !22} ; [ DW_TAG_arg_variable ] !22 = metadata !{i32 7, i32 10, metadata !23, null} diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll index baad6c0b60e6..30d03054a104 100644 --- a/test/CodeGen/X86/dbg-merge-loc-entry.ll +++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll @@ -47,7 +47,7 @@ declare %0 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"__udivmodti4", metadata !"__udivmodti4", metadata !"", metadata !1, i32 879, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, null, i32 879} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !28, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !29, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5, metadata !5, metadata !8} !5 = metadata !{i32 786454, metadata !30, metadata !6, metadata !"UTItype", i32 166, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] diff --git a/test/CodeGen/X86/dbg-prolog-end.ll b/test/CodeGen/X86/dbg-prolog-end.ll index 26bac2e08286..d1774cc7bcaf 100644 --- a/test/CodeGen/X86/dbg-prolog-end.ll +++ b/test/CodeGen/X86/dbg-prolog-end.ll @@ -35,7 +35,7 @@ entry: !llvm.dbg.cu = !{!0} !18 = metadata !{metadata !1, metadata !6} -!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 (trunk 131100)", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null, null, i32 1} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/CodeGen/X86/dbg-subrange.ll b/test/CodeGen/X86/dbg-subrange.ll index 6090185dc10e..b08d68a6643d 100644 --- a/test/CodeGen/X86/dbg-subrange.ll +++ b/test/CodeGen/X86/dbg-subrange.ll @@ -14,7 +14,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 144833)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !11, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 720942, metadata !6, metadata !"bar", metadata !"bar", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @bar, null, null, metadata !9} ; [ DW_TAG_subprogram ] diff --git a/test/CodeGen/X86/dbg-value-dag-combine.ll b/test/CodeGen/X86/dbg-value-dag-combine.ll index fcbf64f42378..c63235e7ad65 100644 --- a/test/CodeGen/X86/dbg-value-dag-combine.ll +++ b/test/CodeGen/X86/dbg-value-dag-combine.ll @@ -27,7 +27,7 @@ entry: !0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !19} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !18, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} !5 = metadata !{i32 786447, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] diff --git a/test/CodeGen/X86/dbg-value-isel.ll b/test/CodeGen/X86/dbg-value-isel.ll index 55be3b1f222b..acc360e90cd2 100644 --- a/test/CodeGen/X86/dbg-value-isel.ll +++ b/test/CodeGen/X86/dbg-value-isel.ll @@ -82,7 +82,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !20} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !19, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !20, i32 1, metadata !"clc", i1 false, metadata !"", i32 0, null, null, metadata !19, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !20, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null, metadata !5} !5 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] diff --git a/test/CodeGen/X86/dbg-value-location.ll b/test/CodeGen/X86/dbg-value-location.ll index 2a1916f26c97..a6c3e13621c9 100644 --- a/test/CodeGen/X86/dbg-value-location.ll +++ b/test/CodeGen/X86/dbg-value-location.ll @@ -49,7 +49,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 19510, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i64, i8*, i32)* @foo, null, null, null, i32 19510} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !26} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, null, null, metadata !24, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !27, i32 12, metadata !"clang version 2.9 (trunk 124753)", i1 true, metadata !"", i32 0, null, null, metadata !24, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/CodeGen/X86/dbg-value-range.ll index 6766dbe9edb0..b068bbbe784a 100644 --- a/test/CodeGen/X86/dbg-value-range.ll +++ b/test/CodeGen/X86/dbg-value-range.ll @@ -6,7 +6,7 @@ define i32 @bar(%struct.a* nocapture %b) nounwind ssp { entry: tail call void @llvm.dbg.value(metadata !{%struct.a* %b}, i64 0, metadata !6), !dbg !13 %tmp1 = getelementptr inbounds %struct.a* %b, i64 0, i32 0, !dbg !14 - %tmp2 = load i32* %tmp1, align 4, !dbg !14, !tbaa !15 + %tmp2 = load i32* %tmp1, align 4, !dbg !14 tail call void @llvm.dbg.value(metadata !{i32 %tmp2}, i64 0, metadata !11), !dbg !14 %call = tail call i32 (...)* @foo(i32 %tmp2) nounwind , !dbg !18 %add = add nsw i32 %tmp2, 1, !dbg !19 @@ -21,7 +21,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"bar", metadata !"bar", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.a*)* @bar, null, null, metadata !21, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !22} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, null, null, metadata !20, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !22, i32 12, metadata !"clang version 2.9 (trunk 122997)", i1 true, metadata !"", i32 0, null, null, metadata !20, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -34,9 +34,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !12 = metadata !{i32 786443, metadata !22, metadata !0, i32 5, i32 22, i32 0} ; [ DW_TAG_lexical_block ] !13 = metadata !{i32 5, i32 19, metadata !0, null} !14 = metadata !{i32 6, i32 14, metadata !12, null} -!15 = metadata !{metadata !"int", metadata !16} -!16 = metadata !{metadata !"omnipotent char", metadata !17} -!17 = metadata !{metadata !"Simple C/C++ TBAA", null} !18 = metadata !{i32 7, i32 2, metadata !12, null} !19 = metadata !{i32 8, i32 2, metadata !12, null} !20 = metadata !{metadata !0} diff --git a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll index d591f9408b14..5121ed13228d 100644 --- a/test/CodeGen/X86/fast-cc-merge-stack-adj.ll +++ b/test/CodeGen/X86/fast-cc-merge-stack-adj.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mcpu=generic -march=x86 -x86-asm-syntax=intel | \ -; RUN: grep "add ESP, 8" +; RUN: llc < %s -mcpu=generic -march=x86 -x86-asm-syntax=intel | FileCheck %s +; CHECK: add ESP, 8 target triple = "i686-pc-linux-gnu" diff --git a/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll b/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll index 9233d3f7c1a0..21fae4a82051 100644 --- a/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll +++ b/test/CodeGen/X86/fast-isel-avoid-unnecessary-pic-base.ll @@ -1,4 +1,5 @@ -; RUN: llc -O0 -relocation-model=pic < %s | not grep call +; RUN: llc -O0 -relocation-model=pic < %s | FileCheck %s +; CHECK-NOT: call ; rdar://8396318 ; Don't emit a PIC base register if no addresses are needed. diff --git a/test/CodeGen/X86/fast-isel-constpool.ll b/test/CodeGen/X86/fast-isel-constpool.ll index b3adb802a8c5..bbbaeb233919 100644 --- a/test/CodeGen/X86/fast-isel-constpool.ll +++ b/test/CodeGen/X86/fast-isel-constpool.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -fast-isel | grep "LCPI0_0(%rip)" +; RUN: llc < %s -fast-isel | FileCheck %s +; CHECK: LCPI0_0(%rip) + ; Make sure fast isel uses rip-relative addressing when required. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.0" diff --git a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll new file mode 100644 index 000000000000..45494f139e24 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll @@ -0,0 +1,41 @@ +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s + +define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind { +entry: + %result = sdiv i64 %dividend, %divisor + ret i64 %result +} + +; CHECK: test_sdiv64: +; CHECK: cqto +; CHECK: idivq + +define i64 @test_srem64(i64 %dividend, i64 %divisor) nounwind { +entry: + %result = srem i64 %dividend, %divisor + ret i64 %result +} + +; CHECK: test_srem64: +; CHECK: cqto +; CHECK: idivq + +define i64 @test_udiv64(i64 %dividend, i64 %divisor) nounwind { +entry: + %result = udiv i64 %dividend, %divisor + ret i64 %result +} + +; CHECK: test_udiv64: +; CHECK: xorl +; CHECK: divq + +define i64 @test_urem64(i64 %dividend, i64 %divisor) nounwind { +entry: + %result = urem i64 %dividend, %divisor + ret i64 %result +} + +; CHECK: test_urem64: +; CHECK: xorl +; CHECK: divq diff --git a/test/CodeGen/X86/fast-isel-divrem.ll b/test/CodeGen/X86/fast-isel-divrem.ll new file mode 100644 index 000000000000..7aba7f7b7953 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-divrem.ll @@ -0,0 +1,122 @@ +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s + +define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind { +entry: + %result = sdiv i8 %dividend, %divisor + ret i8 %result +} + +; CHECK: test_sdiv8: +; CHECK: movsbw +; CHECK: idivb + +define i8 @test_srem8(i8 %dividend, i8 %divisor) nounwind { +entry: + %result = srem i8 %dividend, %divisor + ret i8 %result +} + +; CHECK: test_srem8: +; CHECK: movsbw +; CHECK: idivb + +define i8 @test_udiv8(i8 %dividend, i8 %divisor) nounwind { +entry: + %result = udiv i8 %dividend, %divisor + ret i8 %result +} + +; CHECK: test_udiv8: +; CHECK: movzbw +; CHECK: divb + +define i8 @test_urem8(i8 %dividend, i8 %divisor) nounwind { +entry: + %result = urem i8 %dividend, %divisor + ret i8 %result +} + +; CHECK: test_urem8: +; CHECK: movzbw +; CHECK: divb + +define i16 @test_sdiv16(i16 %dividend, i16 %divisor) nounwind { +entry: + %result = sdiv i16 %dividend, %divisor + ret i16 %result +} + +; CHECK: test_sdiv16: +; CHECK: cwtd +; CHECK: idivw + +define i16 @test_srem16(i16 %dividend, i16 %divisor) nounwind { +entry: + %result = srem i16 %dividend, %divisor + ret i16 %result +} + +; CHECK: test_srem16: +; CHECK: cwtd +; CHECK: idivw + +define i16 @test_udiv16(i16 %dividend, i16 %divisor) nounwind { +entry: + %result = udiv i16 %dividend, %divisor + ret i16 %result +} + +; CHECK: test_udiv16: +; CHECK: xorl +; CHECK: divw + +define i16 @test_urem16(i16 %dividend, i16 %divisor) nounwind { +entry: + %result = urem i16 %dividend, %divisor + ret i16 %result +} + +; CHECK: test_urem16: +; CHECK: xorl +; CHECK: divw + +define i32 @test_sdiv32(i32 %dividend, i32 %divisor) nounwind { +entry: + %result = sdiv i32 %dividend, %divisor + ret i32 %result +} + +; CHECK: test_sdiv32: +; CHECK: cltd +; CHECK: idivl + +define i32 @test_srem32(i32 %dividend, i32 %divisor) nounwind { +entry: + %result = srem i32 %dividend, %divisor + ret i32 %result +} + +; CHECK: test_srem32: +; CHECK: cltd +; CHECK: idivl + +define i32 @test_udiv32(i32 %dividend, i32 %divisor) nounwind { +entry: + %result = udiv i32 %dividend, %divisor + ret i32 %result +} + +; CHECK: test_udiv32: +; CHECK: xorl +; CHECK: divl + +define i32 @test_urem32(i32 %dividend, i32 %divisor) nounwind { +entry: + %result = urem i32 %dividend, %divisor + ret i32 %result +} + +; CHECK: test_urem32: +; CHECK: xorl +; CHECK: divl diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll index f42a4a245bc8..67fdad299369 100644 --- a/test/CodeGen/X86/fast-isel-fneg.ll +++ b/test/CodeGen/X86/fast-isel-fneg.ll @@ -1,5 +1,9 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s -; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | grep xor | count 2 +; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | FileCheck --check-prefix=SSE2 %s + +; SSE2: xor +; SSE2: xor +; SSE2-NOT: xor ; CHECK: doo: ; CHECK: xor diff --git a/test/CodeGen/X86/fast-isel-gv.ll b/test/CodeGen/X86/fast-isel-gv.ll index cb2464e746b1..de7509568907 100644 --- a/test/CodeGen/X86/fast-isel-gv.ll +++ b/test/CodeGen/X86/fast-isel-gv.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -fast-isel | grep "_kill@GOTPCREL(%rip)" +; RUN: llc < %s -fast-isel | FileCheck %s +; CHECK: _kill@GOTPCREL(%rip) + target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin10.0" @f = global i8 (...)* @kill ; <i8 (...)**> [#uses=1] diff --git a/test/CodeGen/X86/fast-isel-tailcall.ll b/test/CodeGen/X86/fast-isel-tailcall.ll index c3e527c4e5b4..79ff79d4bca5 100644 --- a/test/CodeGen/X86/fast-isel-tailcall.ll +++ b/test/CodeGen/X86/fast-isel-tailcall.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -fast-isel -tailcallopt -march=x86 | not grep add +; RUN: llc < %s -fast-isel -tailcallopt -march=x86 | FileCheck %s +; CHECK-NOT: add ; PR4154 ; On x86, -tailcallopt changes the ABI so the caller shouldn't readjust diff --git a/test/CodeGen/X86/fast-isel-unaligned-store.ll b/test/CodeGen/X86/fast-isel-unaligned-store.ll new file mode 100644 index 000000000000..7ce7f676add0 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-unaligned-store.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s + +define i32 @test_store_32(i32* nocapture %addr, i32 %value) { +entry: + store i32 %value, i32* %addr, align 1 + ret i32 %value +} + +; CHECK: ret + +define i16 @test_store_16(i16* nocapture %addr, i16 %value) { +entry: + store i16 %value, i16* %addr, align 1 + ret i16 %value +} + +; CHECK: ret diff --git a/test/CodeGen/X86/fastcall-correct-mangling.ll b/test/CodeGen/X86/fastcall-correct-mangling.ll index 33b18bb8cc6e..3569d36541f7 100644 --- a/test/CodeGen/X86/fastcall-correct-mangling.ll +++ b/test/CodeGen/X86/fastcall-correct-mangling.ll @@ -7,3 +7,8 @@ define x86_fastcallcc void @func(i64 %X, i8 %Y, i8 %G, i16 %Z) { ret void } +define x86_fastcallcc i32 @"\01DoNotMangle"(i32 %a) { +; CHECK: DoNotMangle: +entry: + ret i32 %a +} diff --git a/test/CodeGen/X86/fastcc-2.ll b/test/CodeGen/X86/fastcc-2.ll index d044a2ad9e84..e11cdd19723a 100644 --- a/test/CodeGen/X86/fastcc-2.ll +++ b/test/CodeGen/X86/fastcc-2.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep movsd -; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | grep mov | count 1 +; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s +; CHECK: movsd +; CHECK-NOT: mov define i32 @foo() nounwind { entry: diff --git a/test/CodeGen/X86/fastcc-byval.ll b/test/CodeGen/X86/fastcc-byval.ll index f1204d677a55..e6828e42827c 100644 --- a/test/CodeGen/X86/fastcc-byval.ll +++ b/test/CodeGen/X86/fastcc-byval.ll @@ -1,4 +1,8 @@ -; RUN: llc < %s -tailcallopt=false | grep "movl[[:space:]]*8(%esp), %eax" | count 2 +; RUN: llc < %s -tailcallopt=false | FileCheck %s +; CHECK: movl 8(%esp), %eax +; CHECK: movl 8(%esp), %eax +; CHECK-NOT: movl 8(%esp), %eax + ; PR3122 ; rdar://6400815 diff --git a/test/CodeGen/X86/fastcc-sret.ll b/test/CodeGen/X86/fastcc-sret.ll index d45741884c7d..97814dbabdcc 100644 --- a/test/CodeGen/X86/fastcc-sret.ll +++ b/test/CodeGen/X86/fastcc-sret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -tailcallopt=false | grep ret | not grep 4 +; RUN: llc < %s -march=x86 -tailcallopt=false | FileCheck %s %struct.foo = type { [4 x i32] } @@ -9,6 +9,8 @@ entry: store i32 1, i32* %tmp3, align 8 ret void } +; CHECK: bar +; CHECK: ret{{[^4]*$}} @dst = external global i32 @@ -21,3 +23,5 @@ define void @foo() nounwind { store i32 %tmp6, i32* @dst ret void } +; CHECK: foo +; CHECK: ret{{[^4]*$}} diff --git a/test/CodeGen/X86/fastcc3struct.ll b/test/CodeGen/X86/fastcc3struct.ll index 84f8ef6cf360..98dc2f5a1c78 100644 --- a/test/CodeGen/X86/fastcc3struct.ll +++ b/test/CodeGen/X86/fastcc3struct.ll @@ -1,7 +1,8 @@ -; RUN: llc < %s -march=x86 -o %t -; RUN: grep "movl .48, %ecx" %t -; RUN: grep "movl .24, %edx" %t -; RUN: grep "movl .12, %eax" %t +; RUN: llc < %s -march=x86 | FileCheck %s + +; CHECK: movl {{.}}12, %eax +; CHECK: movl {{.}}24, %edx +; CHECK: movl {{.}}48, %ecx %0 = type { i32, i32, i32 } diff --git a/test/CodeGen/X86/fold-imm.ll b/test/CodeGen/X86/fold-imm.ll index f1fcbcfd13b4..16e4786979b9 100644 --- a/test/CodeGen/X86/fold-imm.ll +++ b/test/CodeGen/X86/fold-imm.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep inc -; RUN: llc < %s -march=x86 | grep add | grep 4 +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i32 %X) nounwind { entry: @@ -7,8 +6,16 @@ entry: ret i32 %0 } +; CHECK: test +; CHECK: inc +; CHECK: ret + define i32 @test2(i32 %X) nounwind { entry: %0 = add i32 %X, 4 ret i32 %0 } + +; CHECK: test2 +; CHECK: {{add.*4.*$}} +; CHECK: ret diff --git a/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll new file mode 100644 index 000000000000..3468a457e95f --- /dev/null +++ b/test/CodeGen/X86/fp-elim-and-no-fp-elim.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s + +define void @bar(i32 %argc) #0 { +; CHECK: bar: +; CHECK: pushq %rbp +entry: + %conv = sitofp i32 %argc to double + %mul = fmul double %conv, 3.792700e+01 + %conv1 = fptrunc double %mul to float + %div = fdiv double 9.273700e+02, %conv + %conv3 = fptrunc double %div to float + tail call void @foo(float %conv1, float %conv3) + ret void +} + +define void @qux(i32 %argc) #1 { +; CHECK: qux: +; CHECK-NOT: pushq %rbp +entry: + %conv = sitofp i32 %argc to double + %mul = fmul double %conv, 3.792700e+01 + %conv1 = fptrunc double %mul to float + %div = fdiv double 9.273700e+02, %conv + %conv3 = fptrunc double %div to float + tail call void @foo(float %conv1, float %conv3) + ret void +} + +declare void @foo(float, float) + +attributes #0 = { "no-frame-pointer-elim"="true" } +attributes #1 = { "no-frame-pointer-elim"="false" } diff --git a/test/CodeGen/X86/fp-immediate-shorten.ll b/test/CodeGen/X86/fp-immediate-shorten.ll index 62d81003a62d..dc59c5a44b4e 100644 --- a/test/CodeGen/X86/fp-immediate-shorten.ll +++ b/test/CodeGen/X86/fp-immediate-shorten.ll @@ -1,7 +1,8 @@ ;; Test that this FP immediate is stored in the constant pool as a float. -; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | \ -; RUN: grep ".long.1123418112" +; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | FileCheck %s + +; CHECK: {{.long.1123418112}} define double @D() { ret double 1.230000e+02 diff --git a/test/CodeGen/X86/fp_load_cast_fold.ll b/test/CodeGen/X86/fp_load_cast_fold.ll index a160ac694429..72ea12f9430e 100644 --- a/test/CodeGen/X86/fp_load_cast_fold.ll +++ b/test/CodeGen/X86/fp_load_cast_fold.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep fild | not grep ESP +; RUN: llc < %s -march=x86 | FileCheck %s define double @short(i16* %P) { %V = load i16* %P ; <i16> [#uses=1] @@ -18,3 +18,9 @@ define double @long(i64* %P) { ret double %V2 } +; CHECK: long +; CHECK: fild +; CHECK-NOT: ESP +; CHECK-NOT: esp +; CHECK: {{$}} +; CHECK: ret diff --git a/test/CodeGen/X86/long-setcc.ll b/test/CodeGen/X86/long-setcc.ll index e0165fb01b53..13046d8b3dec 100644 --- a/test/CodeGen/X86/long-setcc.ll +++ b/test/CodeGen/X86/long-setcc.ll @@ -1,18 +1,31 @@ -; RUN: llc < %s -march=x86 | grep cmp | count 1 -; RUN: llc < %s -march=x86 | grep shr | count 1 -; RUN: llc < %s -march=x86 | grep xor | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s define i1 @t1(i64 %x) nounwind { %B = icmp slt i64 %x, 0 ret i1 %B } +; CHECK: t1 +; CHECK: shrl +; CHECK-NOT: shrl +; CHECK: ret + define i1 @t2(i64 %x) nounwind { %tmp = icmp ult i64 %x, 4294967296 ret i1 %tmp } +; CHECK: t2 +; CHECK: cmp +; CHECK-NOT: cmp +; CHECK: ret + define i1 @t3(i32 %x) nounwind { %tmp = icmp ugt i32 %x, -1 ret i1 %tmp } + +; CHECK: t3 +; CHECK: xor +; CHECK-NOT: xor +; CHECK: ret diff --git a/test/CodeGen/X86/lsr-normalization.ll b/test/CodeGen/X86/lsr-normalization.ll index 932141d0448e..bbf8f010efde 100644 --- a/test/CodeGen/X86/lsr-normalization.ll +++ b/test/CodeGen/X86/lsr-normalization.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep div | count 1 +; RUN: llc < %s -march=x86-64 | FileCheck %s ; rdar://8168938 ; This testcase involves SCEV normalization with the exit value from @@ -6,6 +6,9 @@ ; loop. The expression should be properly normalized and simplified, ; and require only a single division. +; CHECK: div +; CHECK-NOT: div + %0 = type { %0*, %0* } @0 = private constant [13 x i8] c"Result: %lu\0A\00" ; <[13 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/lsr-static-addr.ll b/test/CodeGen/X86/lsr-static-addr.ll index 6566f563784d..b2aea90500c4 100644 --- a/test/CodeGen/X86/lsr-static-addr.ll +++ b/test/CodeGen/X86/lsr-static-addr.ll @@ -17,7 +17,7 @@ ; ATOM-NEXT: movsd A(,%rax,8) ; ATOM-NEXT: mulsd ; ATOM-NEXT: movsd -; ATOM-NEXT: incq %rax +; ATOM-NEXT: leaq 1(%rax), %rax @A = external global [0 x double] diff --git a/test/CodeGen/X86/misched-copy.ll b/test/CodeGen/X86/misched-copy.ll new file mode 100644 index 000000000000..0450cfb53908 --- /dev/null +++ b/test/CodeGen/X86/misched-copy.ll @@ -0,0 +1,49 @@ +; REQUIRES: asserts +; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; +; Test scheduling of copy instructions. +; +; Argument copies should be hoisted to the top of the block. +; Return copies should be sunk to the end. +; MUL_HiLo PhysReg use copies should be just above the mul. +; MUL_HiLo PhysReg def copies should be just below the mul. +; +; CHECK: *** Final schedule for BB#1 *** +; CHECK-NEXT: %EAX<def> = COPY +; CHECK: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>; +; CHECK-NEXT: COPY %E{{[AD]}}X; +; CHECK-NEXT: COPY %E{{[AD]}}X; +; CHECK: DIVSSrm +define i64 @mulhoist(i32 %a, i32 %b) #0 { +entry: + br label %body + +body: + %convb = sitofp i32 %b to float + ; Generates an iMUL64r to legalize types. + %aa = zext i32 %a to i64 + %mul = mul i64 %aa, 74383 + ; Do some dependent long latency stuff. + %trunc = trunc i64 %mul to i32 + %convm = sitofp i32 %trunc to float + %divm = fdiv float %convm, 0.75 + ;%addmb = fadd float %divm, %convb + ;%divmb = fdiv float %addmb, 0.125 + ; Do some independent long latency stuff. + %conva = sitofp i32 %a to float + %diva = fdiv float %conva, 0.75 + %addab = fadd float %diva, %convb + %divab = fdiv float %addab, 0.125 + br label %end + +end: + %val = fptosi float %divab to i64 + %add = add i64 %mul, %val + ret i64 %add +} + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!0 = metadata !{metadata !"float", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/misched-matmul.ll b/test/CodeGen/X86/misched-matmul.ll index 0f6e442b1a8d..15e8a0ad6f4b 100644 --- a/test/CodeGen/X86/misched-matmul.ll +++ b/test/CodeGen/X86/misched-matmul.ll @@ -12,86 +12,86 @@ define void @wrap_mul4(double* nocapture %Out, [4 x double]* nocapture %A, [4 x double]* nocapture %B) #0 { entry: %arrayidx1.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 0 - %0 = load double* %arrayidx1.i, align 8, !tbaa !0 + %0 = load double* %arrayidx1.i, align 8 %arrayidx3.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 0 - %1 = load double* %arrayidx3.i, align 8, !tbaa !0 + %1 = load double* %arrayidx3.i, align 8 %mul.i = fmul double %0, %1 %arrayidx5.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 1 - %2 = load double* %arrayidx5.i, align 8, !tbaa !0 + %2 = load double* %arrayidx5.i, align 8 %arrayidx7.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 0 - %3 = load double* %arrayidx7.i, align 8, !tbaa !0 + %3 = load double* %arrayidx7.i, align 8 %mul8.i = fmul double %2, %3 %add.i = fadd double %mul.i, %mul8.i %arrayidx10.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 2 - %4 = load double* %arrayidx10.i, align 8, !tbaa !0 + %4 = load double* %arrayidx10.i, align 8 %arrayidx12.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 0 - %5 = load double* %arrayidx12.i, align 8, !tbaa !0 + %5 = load double* %arrayidx12.i, align 8 %mul13.i = fmul double %4, %5 %add14.i = fadd double %add.i, %mul13.i %arrayidx16.i = getelementptr inbounds [4 x double]* %A, i64 0, i64 3 - %6 = load double* %arrayidx16.i, align 8, !tbaa !0 + %6 = load double* %arrayidx16.i, align 8 %arrayidx18.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 0 - %7 = load double* %arrayidx18.i, align 8, !tbaa !0 + %7 = load double* %arrayidx18.i, align 8 %mul19.i = fmul double %6, %7 %add20.i = fadd double %add14.i, %mul19.i %arrayidx25.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 1 - %8 = load double* %arrayidx25.i, align 8, !tbaa !0 + %8 = load double* %arrayidx25.i, align 8 %mul26.i = fmul double %0, %8 %arrayidx30.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 1 - %9 = load double* %arrayidx30.i, align 8, !tbaa !0 + %9 = load double* %arrayidx30.i, align 8 %mul31.i = fmul double %2, %9 %add32.i = fadd double %mul26.i, %mul31.i %arrayidx36.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 1 - %10 = load double* %arrayidx36.i, align 8, !tbaa !0 + %10 = load double* %arrayidx36.i, align 8 %mul37.i = fmul double %4, %10 %add38.i = fadd double %add32.i, %mul37.i %arrayidx42.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 1 - %11 = load double* %arrayidx42.i, align 8, !tbaa !0 + %11 = load double* %arrayidx42.i, align 8 %mul43.i = fmul double %6, %11 %add44.i = fadd double %add38.i, %mul43.i %arrayidx49.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 2 - %12 = load double* %arrayidx49.i, align 8, !tbaa !0 + %12 = load double* %arrayidx49.i, align 8 %mul50.i = fmul double %0, %12 %arrayidx54.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 2 - %13 = load double* %arrayidx54.i, align 8, !tbaa !0 + %13 = load double* %arrayidx54.i, align 8 %mul55.i = fmul double %2, %13 %add56.i = fadd double %mul50.i, %mul55.i %arrayidx60.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 2 - %14 = load double* %arrayidx60.i, align 8, !tbaa !0 + %14 = load double* %arrayidx60.i, align 8 %mul61.i = fmul double %4, %14 %add62.i = fadd double %add56.i, %mul61.i %arrayidx66.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 2 - %15 = load double* %arrayidx66.i, align 8, !tbaa !0 + %15 = load double* %arrayidx66.i, align 8 %mul67.i = fmul double %6, %15 %add68.i = fadd double %add62.i, %mul67.i %arrayidx73.i = getelementptr inbounds [4 x double]* %B, i64 0, i64 3 - %16 = load double* %arrayidx73.i, align 8, !tbaa !0 + %16 = load double* %arrayidx73.i, align 8 %mul74.i = fmul double %0, %16 %arrayidx78.i = getelementptr inbounds [4 x double]* %B, i64 1, i64 3 - %17 = load double* %arrayidx78.i, align 8, !tbaa !0 + %17 = load double* %arrayidx78.i, align 8 %mul79.i = fmul double %2, %17 %add80.i = fadd double %mul74.i, %mul79.i %arrayidx84.i = getelementptr inbounds [4 x double]* %B, i64 2, i64 3 - %18 = load double* %arrayidx84.i, align 8, !tbaa !0 + %18 = load double* %arrayidx84.i, align 8 %mul85.i = fmul double %4, %18 %add86.i = fadd double %add80.i, %mul85.i %arrayidx90.i = getelementptr inbounds [4 x double]* %B, i64 3, i64 3 - %19 = load double* %arrayidx90.i, align 8, !tbaa !0 + %19 = load double* %arrayidx90.i, align 8 %mul91.i = fmul double %6, %19 %add92.i = fadd double %add86.i, %mul91.i %arrayidx95.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 0 - %20 = load double* %arrayidx95.i, align 8, !tbaa !0 + %20 = load double* %arrayidx95.i, align 8 %mul98.i = fmul double %1, %20 %arrayidx100.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 1 - %21 = load double* %arrayidx100.i, align 8, !tbaa !0 + %21 = load double* %arrayidx100.i, align 8 %mul103.i = fmul double %3, %21 %add104.i = fadd double %mul98.i, %mul103.i %arrayidx106.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 2 - %22 = load double* %arrayidx106.i, align 8, !tbaa !0 + %22 = load double* %arrayidx106.i, align 8 %mul109.i = fmul double %5, %22 %add110.i = fadd double %add104.i, %mul109.i %arrayidx112.i = getelementptr inbounds [4 x double]* %A, i64 1, i64 3 - %23 = load double* %arrayidx112.i, align 8, !tbaa !0 + %23 = load double* %arrayidx112.i, align 8 %mul115.i = fmul double %7, %23 %add116.i = fadd double %add110.i, %mul115.i %mul122.i = fmul double %8, %20 @@ -116,18 +116,18 @@ entry: %mul187.i = fmul double %19, %23 %add188.i = fadd double %add182.i, %mul187.i %arrayidx191.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 0 - %24 = load double* %arrayidx191.i, align 8, !tbaa !0 + %24 = load double* %arrayidx191.i, align 8 %mul194.i = fmul double %1, %24 %arrayidx196.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 1 - %25 = load double* %arrayidx196.i, align 8, !tbaa !0 + %25 = load double* %arrayidx196.i, align 8 %mul199.i = fmul double %3, %25 %add200.i = fadd double %mul194.i, %mul199.i %arrayidx202.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 2 - %26 = load double* %arrayidx202.i, align 8, !tbaa !0 + %26 = load double* %arrayidx202.i, align 8 %mul205.i = fmul double %5, %26 %add206.i = fadd double %add200.i, %mul205.i %arrayidx208.i = getelementptr inbounds [4 x double]* %A, i64 2, i64 3 - %27 = load double* %arrayidx208.i, align 8, !tbaa !0 + %27 = load double* %arrayidx208.i, align 8 %mul211.i = fmul double %7, %27 %add212.i = fadd double %add206.i, %mul211.i %mul218.i = fmul double %8, %24 @@ -152,18 +152,18 @@ entry: %mul283.i = fmul double %19, %27 %add284.i = fadd double %add278.i, %mul283.i %arrayidx287.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 0 - %28 = load double* %arrayidx287.i, align 8, !tbaa !0 + %28 = load double* %arrayidx287.i, align 8 %mul290.i = fmul double %1, %28 %arrayidx292.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 1 - %29 = load double* %arrayidx292.i, align 8, !tbaa !0 + %29 = load double* %arrayidx292.i, align 8 %mul295.i = fmul double %3, %29 %add296.i = fadd double %mul290.i, %mul295.i %arrayidx298.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 2 - %30 = load double* %arrayidx298.i, align 8, !tbaa !0 + %30 = load double* %arrayidx298.i, align 8 %mul301.i = fmul double %5, %30 %add302.i = fadd double %add296.i, %mul301.i %arrayidx304.i = getelementptr inbounds [4 x double]* %A, i64 3, i64 3 - %31 = load double* %arrayidx304.i, align 8, !tbaa !0 + %31 = load double* %arrayidx304.i, align 8 %mul307.i = fmul double %7, %31 %add308.i = fadd double %add302.i, %mul307.i %mul314.i = fmul double %8, %28 @@ -222,7 +222,3 @@ entry: } attributes #0 = { noinline nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } - -!0 = metadata !{metadata !"double", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/misched-matrix.ll b/test/CodeGen/X86/misched-matrix.ll index f5566e5e5de9..4dc95c5e9326 100644 --- a/test/CodeGen/X86/misched-matrix.ll +++ b/test/CodeGen/X86/misched-matrix.ll @@ -94,57 +94,57 @@ entry: for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx8 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 0 - %tmp = load i32* %arrayidx8, align 4, !tbaa !0 + %tmp = load i32* %arrayidx8, align 4 %arrayidx12 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 0 - %tmp1 = load i32* %arrayidx12, align 4, !tbaa !0 + %tmp1 = load i32* %arrayidx12, align 4 %arrayidx8.1 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 1 - %tmp2 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %tmp2 = load i32* %arrayidx8.1, align 4 %arrayidx12.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 0 - %tmp3 = load i32* %arrayidx12.1, align 4, !tbaa !0 + %tmp3 = load i32* %arrayidx12.1, align 4 %arrayidx8.2 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 2 - %tmp4 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %tmp4 = load i32* %arrayidx8.2, align 4 %arrayidx12.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 0 - %tmp5 = load i32* %arrayidx12.2, align 4, !tbaa !0 + %tmp5 = load i32* %arrayidx12.2, align 4 %arrayidx8.3 = getelementptr inbounds [4 x i32]* %m1, i64 %indvars.iv, i64 3 - %tmp6 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %tmp6 = load i32* %arrayidx8.3, align 4 %arrayidx12.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 0 - %tmp8 = load i32* %arrayidx8, align 4, !tbaa !0 + %tmp8 = load i32* %arrayidx8, align 4 %arrayidx12.137 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 1 - %tmp9 = load i32* %arrayidx12.137, align 4, !tbaa !0 - %tmp10 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %tmp9 = load i32* %arrayidx12.137, align 4 + %tmp10 = load i32* %arrayidx8.1, align 4 %arrayidx12.1.1 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 1 - %tmp11 = load i32* %arrayidx12.1.1, align 4, !tbaa !0 - %tmp12 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %tmp11 = load i32* %arrayidx12.1.1, align 4 + %tmp12 = load i32* %arrayidx8.2, align 4 %arrayidx12.2.1 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 1 - %tmp13 = load i32* %arrayidx12.2.1, align 4, !tbaa !0 - %tmp14 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %tmp13 = load i32* %arrayidx12.2.1, align 4 + %tmp14 = load i32* %arrayidx8.3, align 4 %arrayidx12.3.1 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 1 - %tmp15 = load i32* %arrayidx12.3.1, align 4, !tbaa !0 - %tmp16 = load i32* %arrayidx8, align 4, !tbaa !0 + %tmp15 = load i32* %arrayidx12.3.1, align 4 + %tmp16 = load i32* %arrayidx8, align 4 %arrayidx12.239 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 2 - %tmp17 = load i32* %arrayidx12.239, align 4, !tbaa !0 - %tmp18 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %tmp17 = load i32* %arrayidx12.239, align 4 + %tmp18 = load i32* %arrayidx8.1, align 4 %arrayidx12.1.2 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 2 - %tmp19 = load i32* %arrayidx12.1.2, align 4, !tbaa !0 - %tmp20 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %tmp19 = load i32* %arrayidx12.1.2, align 4 + %tmp20 = load i32* %arrayidx8.2, align 4 %arrayidx12.2.2 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 2 - %tmp21 = load i32* %arrayidx12.2.2, align 4, !tbaa !0 - %tmp22 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %tmp21 = load i32* %arrayidx12.2.2, align 4 + %tmp22 = load i32* %arrayidx8.3, align 4 %arrayidx12.3.2 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 2 - %tmp23 = load i32* %arrayidx12.3.2, align 4, !tbaa !0 - %tmp24 = load i32* %arrayidx8, align 4, !tbaa !0 + %tmp23 = load i32* %arrayidx12.3.2, align 4 + %tmp24 = load i32* %arrayidx8, align 4 %arrayidx12.341 = getelementptr inbounds [4 x i32]* %m2, i64 0, i64 3 - %tmp25 = load i32* %arrayidx12.341, align 4, !tbaa !0 - %tmp26 = load i32* %arrayidx8.1, align 4, !tbaa !0 + %tmp25 = load i32* %arrayidx12.341, align 4 + %tmp26 = load i32* %arrayidx8.1, align 4 %arrayidx12.1.3 = getelementptr inbounds [4 x i32]* %m2, i64 1, i64 3 - %tmp27 = load i32* %arrayidx12.1.3, align 4, !tbaa !0 - %tmp28 = load i32* %arrayidx8.2, align 4, !tbaa !0 + %tmp27 = load i32* %arrayidx12.1.3, align 4 + %tmp28 = load i32* %arrayidx8.2, align 4 %arrayidx12.2.3 = getelementptr inbounds [4 x i32]* %m2, i64 2, i64 3 - %tmp29 = load i32* %arrayidx12.2.3, align 4, !tbaa !0 - %tmp30 = load i32* %arrayidx8.3, align 4, !tbaa !0 + %tmp29 = load i32* %arrayidx12.2.3, align 4 + %tmp30 = load i32* %arrayidx8.3, align 4 %arrayidx12.3.3 = getelementptr inbounds [4 x i32]* %m2, i64 3, i64 3 - %tmp31 = load i32* %arrayidx12.3.3, align 4, !tbaa !0 - %tmp7 = load i32* %arrayidx12.3, align 4, !tbaa !0 + %tmp31 = load i32* %arrayidx12.3.3, align 4 + %tmp7 = load i32* %arrayidx12.3, align 4 %mul = mul nsw i32 %tmp1, %tmp %mul.1 = mul nsw i32 %tmp3, %tmp2 %mul.2 = mul nsw i32 %tmp5, %tmp4 @@ -174,13 +174,13 @@ for.body: ; preds = %for.body, %entry %add.2.3 = add nsw i32 %mul.2.3, %add.1.3 %add.3.3 = add nsw i32 %mul.3.3, %add.2.3 %arrayidx16 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 0 - store i32 %add.3, i32* %arrayidx16, align 4, !tbaa !0 + store i32 %add.3, i32* %arrayidx16, align 4 %arrayidx16.1 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 1 - store i32 %add.3.1, i32* %arrayidx16.1, align 4, !tbaa !0 + store i32 %add.3.1, i32* %arrayidx16.1, align 4 %arrayidx16.2 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 2 - store i32 %add.3.2, i32* %arrayidx16.2, align 4, !tbaa !0 + store i32 %add.3.2, i32* %arrayidx16.2, align 4 %arrayidx16.3 = getelementptr inbounds [4 x i32]* %m3, i64 %indvars.iv, i64 3 - store i32 %add.3.3, i32* %arrayidx16.3, align 4, !tbaa !0 + store i32 %add.3.3, i32* %arrayidx16.3, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 4 @@ -189,7 +189,3 @@ for.body: ; preds = %for.body, %entry for.end: ; preds = %for.body ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/mmx-pinsrw.ll b/test/CodeGen/X86/mmx-pinsrw.ll index d9c7c678d1b2..33dd2eb81cfa 100644 --- a/test/CodeGen/X86/mmx-pinsrw.ll +++ b/test/CodeGen/X86/mmx-pinsrw.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | grep pinsr +; RUN: llc < %s -mtriple=x86_64-linux -mcpu=corei7 | FileCheck %s ; PR2562 +; CHECK: pinsr + external global i16 ; <i16*>:0 [#uses=1] external global <4 x i16> ; <<4 x i16>*>:1 [#uses=2] diff --git a/test/CodeGen/X86/mul-legalize.ll b/test/CodeGen/X86/mul-legalize.ll index 069737d4d10d..339de3104335 100644 --- a/test/CodeGen/X86/mul-legalize.ll +++ b/test/CodeGen/X86/mul-legalize.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=x86 | grep 24576 +; RUN: llc < %s -march=x86 | FileCheck %s ; PR2135 +; CHECK: 24576 + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-pc-linux-gnu" @.str = constant [13 x i8] c"c45531m.adb\00\00" diff --git a/test/CodeGen/X86/negative_zero.ll b/test/CodeGen/X86/negative_zero.ll index 29474c21f244..c8c2cd753e08 100644 --- a/test/CodeGen/X86/negative_zero.ll +++ b/test/CodeGen/X86/negative_zero.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | grep fchs +; RUN: llc < %s -march=x86 -mattr=-sse2,-sse3 | FileCheck %s + +; CHECK: fchs define double @T() { diff --git a/test/CodeGen/X86/no-compact-unwind.ll b/test/CodeGen/X86/no-compact-unwind.ll new file mode 100644 index 000000000000..627f7da9f707 --- /dev/null +++ b/test/CodeGen/X86/no-compact-unwind.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple x86_64-apple-macosx10.8.0 -disable-cfi | FileCheck %s + +%"struct.dyld::MappedRanges" = type { [400 x %struct.anon], %"struct.dyld::MappedRanges"* } +%struct.anon = type { %class.ImageLoader*, i64, i64 } +%class.ImageLoader = type { i32 (...)**, i8*, i8*, i32, i64, i64, i32, i32, %"struct.ImageLoader::recursive_lock"*, i16, i16, [4 x i8] } +%"struct.ImageLoader::recursive_lock" = type { i32, i32 } + +@G1 = external hidden global %"struct.dyld::MappedRanges", align 8 + +declare void @OSMemoryBarrier() optsize + +; This compact unwind encoding indicates that we could not generate correct +; compact unwind encodings for this function. This then defaults to using the +; DWARF EH frame. +; +; CHECK: .section __LD,__compact_unwind,regular,debug +; CHECK: .quad _func +; CHECK: .long 67108864 ## Compact Unwind Encoding: 0x4000000 +; CHECK: .quad 0 ## Personality Function +; CHECK: .quad 0 ## LSDA +; +define void @func(%class.ImageLoader* %image) optsize ssp uwtable { +entry: + br label %for.cond1.preheader + +for.cond1.preheader: ; preds = %for.inc10, %entry + %p.019 = phi %"struct.dyld::MappedRanges"* [ @G1, %entry ], [ %1, %for.inc10 ] + br label %for.body3 + +for.body3: ; preds = %for.inc, %for.cond1.preheader + %indvars.iv = phi i64 [ 0, %for.cond1.preheader ], [ %indvars.iv.next, %for.inc ] + %image4 = getelementptr inbounds %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 0, i64 %indvars.iv, i32 0 + %0 = load %class.ImageLoader** %image4, align 8 + %cmp5 = icmp eq %class.ImageLoader* %0, %image + br i1 %cmp5, label %if.then, label %for.inc + +if.then: ; preds = %for.body3 + tail call void @OSMemoryBarrier() optsize + store %class.ImageLoader* null, %class.ImageLoader** %image4, align 8 + br label %for.inc + +for.inc: ; preds = %if.then, %for.body3 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 400 + br i1 %exitcond, label %for.inc10, label %for.body3 + +for.inc10: ; preds = %for.inc + %next = getelementptr inbounds %"struct.dyld::MappedRanges"* %p.019, i64 0, i32 1 + %1 = load %"struct.dyld::MappedRanges"** %next, align 8 + %cmp = icmp eq %"struct.dyld::MappedRanges"* %1, null + br i1 %cmp, label %for.end11, label %for.cond1.preheader + +for.end11: ; preds = %for.inc10 + ret void +} diff --git a/test/CodeGen/X86/nosse-error1.ll b/test/CodeGen/X86/nosse-error1.ll index 16cbb732af0e..cddff3f2753b 100644 --- a/test/CodeGen/X86/nosse-error1.ll +++ b/test/CodeGen/X86/nosse-error1.ll @@ -1,7 +1,10 @@ -; RUN: llvm-as < %s > %t1 -; RUN: not llc -march=x86-64 -mattr=-sse < %t1 2> %t2 -; RUN: grep "SSE register return with SSE disabled" %t2 -; RUN: llc -march=x86-64 < %t1 | grep xmm +; RUN: llc < %s -march=x86-64 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; NOSSE: {{SSE register return with SSE disabled}} + +; CHECK: xmm + target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" @f = external global float ; <float*> [#uses=4] diff --git a/test/CodeGen/X86/nosse-error2.ll b/test/CodeGen/X86/nosse-error2.ll index 45a5eaf3a415..fc9ba010e19d 100644 --- a/test/CodeGen/X86/nosse-error2.ll +++ b/test/CodeGen/X86/nosse-error2.ll @@ -1,7 +1,10 @@ -; RUN: llvm-as < %s > %t1 -; RUN: not llc -march=x86 -mcpu=i686 -mattr=-sse < %t1 2> %t2 -; RUN: grep "SSE register return with SSE disabled" %t2 -; RUN: llc -march=x86 -mcpu=i686 -mattr=+sse < %t1 | grep xmm +; RUN: llc < %s -march=x86 -mcpu=i686 -mattr=-sse 2>&1 | FileCheck --check-prefix NOSSE %s +; RUN: llc < %s -march=x86 -mcpu=i686 -mattr=+sse | FileCheck %s + +; NOSSE: {{SSE register return with SSE disabled}} + +; CHECK: xmm + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i386-unknown-linux-gnu" @f = external global float ; <float*> [#uses=4] diff --git a/test/CodeGen/X86/optimize-max-2.ll b/test/CodeGen/X86/optimize-max-2.ll index 8851c5b1a305..10ab831c1e3d 100644 --- a/test/CodeGen/X86/optimize-max-2.ll +++ b/test/CodeGen/X86/optimize-max-2.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep cmov %t | count 2 -; RUN: grep jne %t | count 1 +; RUN: llc < %s -march=x86-64 | grep cmov | count 2 +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: jne +; CHECK-NOT: jne ; LSR's OptimizeMax function shouldn't try to eliminate this max, because ; it has three operands. diff --git a/test/CodeGen/X86/peep-test-2.ll b/test/CodeGen/X86/peep-test-2.ll index 274517297592..e4bafbb6ffab 100644 --- a/test/CodeGen/X86/peep-test-2.ll +++ b/test/CodeGen/X86/peep-test-2.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 | grep testl +; RUN: llc < %s -march=x86 | FileCheck %s + +; CHECK: testl ; It's tempting to eliminate the testl instruction here and just use the ; EFLAGS value from the incl, however it can't be known whether the add diff --git a/test/CodeGen/X86/phys_subreg_coalesce.ll b/test/CodeGen/X86/phys_subreg_coalesce.ll index 2c855ce8da63..8b2f61e1e2d2 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | not grep movl +; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+sse2 | FileCheck %s + +; CHECK-NOT: movl %struct.dpoint = type { double, double } diff --git a/test/CodeGen/X86/pr12889.ll b/test/CodeGen/X86/pr12889.ll index 331d8f907d58..428e9b760b70 100644 --- a/test/CodeGen/X86/pr12889.ll +++ b/test/CodeGen/X86/pr12889.ll @@ -6,13 +6,10 @@ target triple = "x86_64-unknown-linux-gnu" define void @func() nounwind uwtable { entry: - %0 = load i8* @c0, align 1, !tbaa !0 + %0 = load i8* @c0, align 1 %tobool = icmp ne i8 %0, 0 %conv = zext i1 %tobool to i8 %storemerge = shl nuw nsw i8 %conv, %conv store i8 %storemerge, i8* @c0, align 1 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/pr2656.ll b/test/CodeGen/X86/pr2656.ll index f0e31f7f5fdc..1122d2d57114 100644 --- a/test/CodeGen/X86/pr2656.ll +++ b/test/CodeGen/X86/pr2656.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep "xorps.*sp" | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; PR2656 +; CHECK: {{xorps.*sp}} +; CHECK-NOT: {{xorps.*sp}} + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin9.4.0" %struct.anon = type <{ float, float }> diff --git a/test/CodeGen/X86/private-2.ll b/test/CodeGen/X86/private-2.ll index 8aa744ead8ca..4413cee23b33 100644 --- a/test/CodeGen/X86/private-2.ll +++ b/test/CodeGen/X86/private-2.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | grep L__ZZ20 +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s ; Quote should be outside of private prefix. ; rdar://6855766x +; CHECK: L__ZZ20 + %struct.A = type { i32*, i32 } @"_ZZ20-[Example1 whatever]E4C.91" = private constant %struct.A { i32* null, i32 1 } ; <%struct.A*> [#uses=1] diff --git a/test/CodeGen/X86/rd-mod-wr-eflags.ll b/test/CodeGen/X86/rd-mod-wr-eflags.ll index 8ef9b5dec0d5..0bf601bc1c42 100644 --- a/test/CodeGen/X86/rd-mod-wr-eflags.ll +++ b/test/CodeGen/X86/rd-mod-wr-eflags.ll @@ -8,9 +8,9 @@ entry: ; CHECK: decq (%{{rdi|rcx}}) ; CHECK-NEXT: je %refcnt = getelementptr inbounds %struct.obj* %o, i64 0, i32 0 - %0 = load i64* %refcnt, align 8, !tbaa !0 + %0 = load i64* %refcnt, align 8 %dec = add i64 %0, -1 - store i64 %dec, i64* %refcnt, align 8, !tbaa !0 + store i64 %dec, i64* %refcnt, align 8 %tobool = icmp eq i64 %dec, 0 br i1 %tobool, label %if.end, label %return @@ -33,12 +33,12 @@ define i32 @test() nounwind uwtable ssp { entry: ; CHECK: decq ; CHECK-NOT: decq -%0 = load i64* @c, align 8, !tbaa !0 +%0 = load i64* @c, align 8 %dec.i = add nsw i64 %0, -1 -store i64 %dec.i, i64* @c, align 8, !tbaa !0 +store i64 %dec.i, i64* @c, align 8 %tobool.i = icmp ne i64 %dec.i, 0 %lor.ext.i = zext i1 %tobool.i to i32 -store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3 +store i32 %lor.ext.i, i32* @a, align 4 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind ret i32 0 } @@ -47,12 +47,12 @@ ret i32 0 define i32 @test2() nounwind uwtable ssp { entry: ; CHECK-NOT: decq ({{.*}}) -%0 = load i64* @c, align 8, !tbaa !0 +%0 = load i64* @c, align 8 %dec.i = add nsw i64 %0, -1 -store i64 %dec.i, i64* @c, align 8, !tbaa !0 +store i64 %dec.i, i64* @c, align 8 %tobool.i = icmp ne i64 %0, 0 %lor.ext.i = zext i1 %tobool.i to i32 -store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3 +store i32 %lor.ext.i, i32* @a, align 4 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind ret i32 0 } @@ -61,11 +61,6 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @free(i8* nocapture) nounwind -!0 = metadata !{metadata !"long", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"int", metadata !1} - %struct.obj2 = type { i64, i32, i16, i8 } declare void @other(%struct.obj2* ) nounwind; diff --git a/test/CodeGen/X86/select-with-and-or.ll b/test/CodeGen/X86/select-with-and-or.ll new file mode 100644 index 000000000000..1ccf30bf2083 --- /dev/null +++ b/test/CodeGen/X86/select-with-and-or.ll @@ -0,0 +1,72 @@ +; RUN: opt < %s -O3 | \ +; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +define <4 x i32> @test1(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> zeroinitializer + ret <4 x i32> %r +; CHECK: test1 +; CHECK: cmpnle +; CHECK-NEXT: andps +; CHECK: ret +} + +define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c + ret <4 x i32> %r +; CHECK: test2 +; CHECK: cmpnle +; CHECK-NEXT: orps +; CHECK: ret +} + +define <4 x i32> @test3(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> %c + ret <4 x i32> %r +; CHECK: test3 +; CHECK: cmple +; CHECK-NEXT: andps +; CHECK: ret +} + +define <4 x i32> @test4(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> %c, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %r +; CHECK: test4 +; CHECK: cmple +; CHECK-NEXT: orps +; CHECK: ret +} + +define <4 x i32> @test5(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> zeroinitializer + ret <4 x i32> %r +; CHECK: test5 +; CHECK: cmpnle +; CHECK-NEXT: ret +} + +define <4 x i32> @test6(<4 x float> %a, <4 x float> %b, <4 x i32> %c) { + %f = fcmp ult <4 x float> %a, %b + %r = select <4 x i1> %f, <4 x i32> zeroinitializer, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %r +; CHECK: test6 +; CHECK: cmple +; CHECK-NEXT: ret +} + +define <4 x i32> @test7(<4 x float> %a, <4 x float> %b, <4 x i32>* %p) { + %f = fcmp ult <4 x float> %a, %b + %s = sext <4 x i1> %f to <4 x i32> + %l = load <4 x i32>* %p + %r = and <4 x i32> %l, %s + ret <4 x i32> %r +; CHECK: test7 +; CHECK: cmpnle +; CHECK-NEXT: andps +; CHECK: ret +} diff --git a/test/CodeGen/X86/sincos-opt.ll b/test/CodeGen/X86/sincos-opt.ll index f364d1fc2dc8..333c4663eb0b 100644 --- a/test/CodeGen/X86/sincos-opt.ll +++ b/test/CodeGen/X86/sincos-opt.ll @@ -4,6 +4,7 @@ ; Combine sin / cos into a single call. ; rdar://13087969 +; rdar://13599493 define float @test1(float %x) nounwind { entry: @@ -14,7 +15,8 @@ entry: ; OSX_SINCOS: test1: ; OSX_SINCOS: callq ___sincosf_stret -; OSX_SINCOS: addss %xmm1, %xmm0 +; OSX_SINCOS: pshufd $1, %xmm0, %xmm1 +; OSX_SINCOS: addss %xmm0, %xmm1 ; OSX_NOOPT: test1 ; OSX_NOOPT: callq _cosf diff --git a/test/CodeGen/X86/stdcall.ll b/test/CodeGen/X86/stdcall.ll index a7c2517e7dbe..73826ed0b29d 100644 --- a/test/CodeGen/X86/stdcall.ll +++ b/test/CodeGen/X86/stdcall.ll @@ -1,16 +1,24 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc -mtriple="i386-pc-mingw32" < %s | FileCheck %s ; PR5851 -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i386-pc-mingw32" - %0 = type { void (...)* } -@B = global %0 { void (...)* bitcast (void ()* @MyFunc to void (...)*) }, align 4 -; CHECK: _B: -; CHECK: .long _MyFunc@0 - define internal x86_stdcallcc void @MyFunc() nounwind { entry: +; CHECK: MyFunc@0: +; CHECK: ret ret void } + +; PR14410 +define x86_stdcallcc i32 @"\01DoNotMangle"(i32 %a) { +; CHECK: DoNotMangle: +; CHECK: ret $4 +entry: + ret i32 %a +} + +@B = global %0 { void (...)* bitcast (void ()* @MyFunc to void (...)*) }, align 4 +; CHECK: _B: +; CHECK: .long _MyFunc@0 + diff --git a/test/CodeGen/X86/store-fp-constant.ll b/test/CodeGen/X86/store-fp-constant.ll index 206886bb608f..71df8d3109e6 100644 --- a/test/CodeGen/X86/store-fp-constant.ll +++ b/test/CodeGen/X86/store-fp-constant.ll @@ -1,5 +1,8 @@ -; RUN: llc < %s -march=x86 | not grep rodata -; RUN: llc < %s -march=x86 | not grep literal +; RUN: llc < %s -march=x86 | FileCheck %s + +; CHECK-NOT: rodata +; CHECK-NOT: literal + ; ; Check that no FP constants in this testcase ends up in the ; constant pool. diff --git a/test/CodeGen/X86/subreg-to-reg-1.ll b/test/CodeGen/X86/subreg-to-reg-1.ll index 4f31ab5a9229..2931bab0cdd1 100644 --- a/test/CodeGen/X86/subreg-to-reg-1.ll +++ b/test/CodeGen/X86/subreg-to-reg-1.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=x86-64 | grep "leal .*), %e.*" | count 1 +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: {{leal .*[)], %e.*}} +; CHECK-NOT: {{leal .*[)], %e.*}} ; Don't eliminate or coalesce away the explicit zero-extension! ; This is currently using an leal because of a 3-addressification detail, diff --git a/test/CodeGen/X86/subreg-to-reg-3.ll b/test/CodeGen/X86/subreg-to-reg-3.ll index 931ae758ac5c..80ab1a2e2494 100644 --- a/test/CodeGen/X86/subreg-to-reg-3.ll +++ b/test/CodeGen/X86/subreg-to-reg-3.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86-64 | grep imull +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: imull ; Don't eliminate or coalesce away the explicit zero-extension! diff --git a/test/CodeGen/X86/subtarget-feature-change.ll b/test/CodeGen/X86/subtarget-feature-change.ll index cd677294c669..04d4a7199632 100644 --- a/test/CodeGen/X86/subtarget-feature-change.ll +++ b/test/CodeGen/X86/subtarget-feature-change.ll @@ -14,12 +14,12 @@ entry: for.body: %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4, !tbaa !0 + %1 = load float* %arrayidx2, align 4 %mul = fmul float %0, %1 %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx4, align 4, !tbaa !0 + store float %mul, float* %arrayidx4, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -43,12 +43,12 @@ entry: for.body: %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds float* %c, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4, !tbaa !0 + %1 = load float* %arrayidx2, align 4 %mul = fmul float %0, %1 %arrayidx4 = getelementptr inbounds float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx4, align 4, !tbaa !0 + store float %mul, float* %arrayidx4, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -60,7 +60,3 @@ for.end: attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" } attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" } - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/X86/switch-crit-edge-constant.ll b/test/CodeGen/X86/switch-crit-edge-constant.ll index 1f2ab0dbcbe9..18f987e72213 100644 --- a/test/CodeGen/X86/switch-crit-edge-constant.ll +++ b/test/CodeGen/X86/switch-crit-edge-constant.ll @@ -1,6 +1,8 @@ ; PR925 -; RUN: llc < %s -march=x86 | \ -; RUN: grep mov.*str1 | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s + +; CHECK: {{mov.*str1}} +; CHECK-NOT: {{mov.*str1}} target datalayout = "e-p:32:32" target triple = "i686-apple-darwin8.7.2" diff --git a/test/CodeGen/X86/tailcall-64.ll b/test/CodeGen/X86/tailcall-64.ll index ecc253ba587e..60fe77661797 100644 --- a/test/CodeGen/X86/tailcall-64.ll +++ b/test/CodeGen/X86/tailcall-64.ll @@ -50,9 +50,18 @@ define {i64, i64} @test_pair_trivial() { ; CHECK: test_pair_trivial: ; CHECK: jmp _testp ## TAILCALL +define {i64, i64} @test_pair_notail() { + %A = tail call i64 @testi() + + %b = insertvalue {i64, i64} undef, i64 %A, 0 + %c = insertvalue {i64, i64} %b, i64 %A, 1 + ret { i64, i64} %c +} +; CHECK: test_pair_notail: +; CHECK-NOT: jmp _testi -define {i64, i64} @test_pair_trivial_extract() { +define {i64, i64} @test_pair_extract_trivial() { %A = tail call { i64, i64} @testp() %x = extractvalue { i64, i64} %A, 0 %y = extractvalue { i64, i64} %A, 1 @@ -63,10 +72,24 @@ define {i64, i64} @test_pair_trivial_extract() { ret { i64, i64} %c } -; CHECK: test_pair_trivial_extract: +; CHECK: test_pair_extract_trivial: ; CHECK: jmp _testp ## TAILCALL -define {i8*, i64} @test_pair_conv_extract() { +define {i64, i64} @test_pair_extract_notail() { + %A = tail call { i64, i64} @testp() + %x = extractvalue { i64, i64} %A, 0 + %y = extractvalue { i64, i64} %A, 1 + + %b = insertvalue {i64, i64} undef, i64 %y, 0 + %c = insertvalue {i64, i64} %b, i64 %x, 1 + + ret { i64, i64} %c +} + +; CHECK: test_pair_extract_notail: +; CHECK-NOT: jmp _testp + +define {i8*, i64} @test_pair_extract_conv() { %A = tail call { i64, i64} @testp() %x = extractvalue { i64, i64} %A, 0 %y = extractvalue { i64, i64} %A, 1 @@ -79,10 +102,75 @@ define {i8*, i64} @test_pair_conv_extract() { ret { i8*, i64} %c } -; CHECK: test_pair_conv_extract: +; CHECK: test_pair_extract_conv: +; CHECK: jmp _testp ## TAILCALL + +define {i64, i64} @test_pair_extract_multiple() { + %A = tail call { i64, i64} @testp() + %x = extractvalue { i64, i64} %A, 0 + %y = extractvalue { i64, i64} %A, 1 + + %b = insertvalue {i64, i64} undef, i64 %x, 0 + %c = insertvalue {i64, i64} %b, i64 %y, 1 + + %x1 = extractvalue { i64, i64} %b, 0 + %y1 = extractvalue { i64, i64} %c, 1 + + %d = insertvalue {i64, i64} undef, i64 %x1, 0 + %e = insertvalue {i64, i64} %b, i64 %y1, 1 + + ret { i64, i64} %e +} + +; CHECK: test_pair_extract_multiple: +; CHECK: jmp _testp ## TAILCALL + +define {i64, i64} @test_pair_extract_undef() { + %A = tail call { i64, i64} @testp() + %x = extractvalue { i64, i64} %A, 0 + + %b = insertvalue {i64, i64} undef, i64 %x, 0 + + ret { i64, i64} %b +} + +; CHECK: test_pair_extract_undef: ; CHECK: jmp _testp ## TAILCALL +declare { i64, { i32, i32 } } @testn() + +define {i64, {i32, i32}} @test_nest() { + %A = tail call { i64, { i32, i32 } } @testn() + %x = extractvalue { i64, { i32, i32}} %A, 0 + %y = extractvalue { i64, { i32, i32}} %A, 1 + %y1 = extractvalue { i32, i32} %y, 0 + %y2 = extractvalue { i32, i32} %y, 1 + + %b = insertvalue {i64, {i32, i32}} undef, i64 %x, 0 + %c1 = insertvalue {i32, i32} undef, i32 %y1, 0 + %c2 = insertvalue {i32, i32} %c1, i32 %y2, 1 + %c = insertvalue {i64, {i32, i32}} %b, {i32, i32} %c2, 1 + + ret { i64, { i32, i32}} %c +} + +; CHECK: test_nest: +; CHECK: jmp _testn ## TAILCALL + +%struct.A = type { i32 } +%struct.B = type { %struct.A, i32 } + +declare %struct.B* @testu() + +define %struct.A* @test_upcast() { +entry: + %A = tail call %struct.B* @testu() + %x = getelementptr inbounds %struct.B* %A, i32 0, i32 0 + ret %struct.A* %x +} +; CHECK: test_upcast: +; CHECK: jmp _testu ## TAILCALL ; PR13006 define { i64, i64 } @crash(i8* %this) { diff --git a/test/CodeGen/X86/this-return-64.ll b/test/CodeGen/X86/this-return-64.ll new file mode 100644 index 000000000000..2b26a89e3c87 --- /dev/null +++ b/test/CodeGen/X86/this-return-64.ll @@ -0,0 +1,89 @@ +; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s + +%struct.A = type { i8 } +%struct.B = type { i32 } +%struct.C = type { %struct.B } +%struct.D = type { %struct.B } +%struct.E = type { %struct.B } + +declare %struct.A* @A_ctor(%struct.A* returned) +declare %struct.B* @B_ctor(%struct.B* returned, i32) + +declare %struct.A* @A_ctor_nothisret(%struct.A*) +declare %struct.B* @B_ctor_nothisret(%struct.B*, i32) + +define %struct.C* @C_ctor(%struct.C* %this, i32 %y) { +entry: +; CHECK: C_ctor: +; CHECK: jmp B_ctor # TAILCALL + %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0 + %call = tail call %struct.B* @B_ctor(%struct.B* %0, i32 %y) + ret %struct.C* %this +} + +define %struct.C* @C_ctor_nothisret(%struct.C* %this, i32 %y) { +entry: +; CHECK: C_ctor_nothisret: +; CHECK-NOT: jmp B_ctor_nothisret + %0 = getelementptr inbounds %struct.C* %this, i64 0, i32 0 + %call = tail call %struct.B* @B_ctor_nothisret(%struct.B* %0, i32 %y) + ret %struct.C* %this +} + +define %struct.D* @D_ctor(%struct.D* %this, i32 %y) { +entry: +; CHECK: D_ctor: +; CHECK: movq %rcx, [[SAVETHIS:%r[0-9a-z]+]] +; CHECK: callq A_ctor +; CHECK: movq [[SAVETHIS]], %rcx +; CHECK: jmp B_ctor # TAILCALL + %0 = bitcast %struct.D* %this to %struct.A* + %call = tail call %struct.A* @A_ctor(%struct.A* %0) + %1 = getelementptr inbounds %struct.D* %this, i64 0, i32 0 + %call2 = tail call %struct.B* @B_ctor(%struct.B* %1, i32 %y) +; (this next line would never be generated by Clang, actually) + %2 = bitcast %struct.A* %call to %struct.D* + ret %struct.D* %2 +} + +define %struct.D* @D_ctor_nothisret(%struct.D* %this, i32 %y) { +entry: +; CHECK: D_ctor_nothisret: +; CHECK: movq %rcx, [[SAVETHIS:%r[0-9a-z]+]] +; CHECK: callq A_ctor_nothisret +; CHECK: movq [[SAVETHIS]], %rcx +; CHECK-NOT: jmp B_ctor_nothisret + %0 = bitcast %struct.D* %this to %struct.A* + %call = tail call %struct.A* @A_ctor_nothisret(%struct.A* %0) + %1 = getelementptr inbounds %struct.D* %this, i64 0, i32 0 + %call2 = tail call %struct.B* @B_ctor_nothisret(%struct.B* %1, i32 %y) +; (this next line would never be generated by Clang, actually) + %2 = bitcast %struct.A* %call to %struct.D* + ret %struct.D* %2 +} + +define %struct.E* @E_ctor(%struct.E* %this, i32 %x) { +entry: +; CHECK: E_ctor: +; CHECK: movq %rcx, [[SAVETHIS:%r[0-9a-z]+]] +; CHECK: callq B_ctor +; CHECK: movq [[SAVETHIS]], %rcx +; CHECK: jmp B_ctor # TAILCALL + %b = getelementptr inbounds %struct.E* %this, i64 0, i32 0 + %call = tail call %struct.B* @B_ctor(%struct.B* %b, i32 %x) + %call4 = tail call %struct.B* @B_ctor(%struct.B* %b, i32 %x) + ret %struct.E* %this +} + +define %struct.E* @E_ctor_nothisret(%struct.E* %this, i32 %x) { +entry: +; CHECK: E_ctor_nothisret: +; CHECK: movq %rcx, [[SAVETHIS:%r[0-9a-z]+]] +; CHECK: callq B_ctor_nothisret +; CHECK: movq [[SAVETHIS]], %rcx +; CHECK-NOT: jmp B_ctor_nothisret + %b = getelementptr inbounds %struct.E* %this, i64 0, i32 0 + %call = tail call %struct.B* @B_ctor_nothisret(%struct.B* %b, i32 %x) + %call4 = tail call %struct.B* @B_ctor_nothisret(%struct.B* %b, i32 %x) + ret %struct.E* %this +} diff --git a/test/CodeGen/X86/unwindraise.ll b/test/CodeGen/X86/unwindraise.ll index a438723d9bd4..9bbe98043fd8 100644 --- a/test/CodeGen/X86/unwindraise.ll +++ b/test/CodeGen/X86/unwindraise.ll @@ -50,12 +50,12 @@ while.body: ; preds = %uw_update_context.e ] if.end3: ; preds = %while.body - %4 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality, align 8, !tbaa !0 + %4 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality, align 8 %tobool = icmp eq i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)* %4, null br i1 %tobool, label %if.end13, label %if.then4 if.then4: ; preds = %if.end3 - %5 = load i64* %exception_class, align 8, !tbaa !3 + %5 = load i64* %exception_class, align 8 %call6 = call i32 %4(i32 1, i32 1, i64 %5, %struct._Unwind_Exception* %exc, %struct._Unwind_Context* %cur_context) switch i32 %call6, label %do.end21.loopexit46 [ i32 6, label %while.end @@ -64,7 +64,7 @@ if.then4: ; preds = %if.end3 if.end13: ; preds = %if.then4, %if.end3 call fastcc void @uw_update_context_1(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs) - %6 = load i64* %retaddr_column.i, align 8, !tbaa !3 + %6 = load i64* %retaddr_column.i, align 8 %conv.i = trunc i64 %6 to i32 %cmp.i.i.i = icmp slt i32 %conv.i, 18 br i1 %cmp.i.i.i, label %cond.end.i.i.i, label %cond.true.i.i.i @@ -77,17 +77,17 @@ cond.end.i.i.i: ; preds = %if.end13 %sext.i = shl i64 %6, 32 %idxprom.i.i.i = ashr exact i64 %sext.i, 32 %arrayidx.i.i.i = getelementptr inbounds [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i - %7 = load i8* %arrayidx.i.i.i, align 1, !tbaa !1 + %7 = load i8* %arrayidx.i.i.i, align 1 %arrayidx2.i.i.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i - %8 = load i8** %arrayidx2.i.i.i, align 8, !tbaa !0 - %9 = load i64* %flags.i.i.i.i, align 8, !tbaa !3 + %8 = load i8** %arrayidx2.i.i.i, align 8 + %9 = load i64* %flags.i.i.i.i, align 8 %and.i.i.i.i = and i64 %9, 4611686018427387904 %tobool.i.i.i = icmp eq i64 %and.i.i.i.i, 0 br i1 %tobool.i.i.i, label %if.end.i.i.i, label %land.lhs.true.i.i.i land.lhs.true.i.i.i: ; preds = %cond.end.i.i.i %arrayidx4.i.i.i = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i - %10 = load i8* %arrayidx4.i.i.i, align 1, !tbaa !1 + %10 = load i8* %arrayidx4.i.i.i, align 1 %tobool6.i.i.i = icmp eq i8 %10, 0 br i1 %tobool6.i.i.i, label %if.end.i.i.i, label %if.then.i.i.i @@ -101,7 +101,7 @@ if.end.i.i.i: ; preds = %land.lhs.true.i.i.i if.then10.i.i.i: ; preds = %if.end.i.i.i %12 = bitcast i8* %8 to i64* - %13 = load i64* %12, align 8, !tbaa !3 + %13 = load i64* %12, align 8 br label %uw_update_context.exit cond.true14.i.i.i: ; preds = %if.end.i.i.i @@ -111,16 +111,16 @@ cond.true14.i.i.i: ; preds = %if.end.i.i.i uw_update_context.exit: ; preds = %if.then10.i.i.i, %if.then.i.i.i %retval.0.i.i.i = phi i64 [ %11, %if.then.i.i.i ], [ %13, %if.then10.i.i.i ] %14 = inttoptr i64 %retval.0.i.i.i to i8* - store i8* %14, i8** %ra.i, align 8, !tbaa !0 + store i8* %14, i8** %ra.i, align 8 br label %while.body while.end: ; preds = %if.then4 %private_1 = getelementptr inbounds %struct._Unwind_Exception* %exc, i64 0, i32 2 - store i64 0, i64* %private_1, align 8, !tbaa !3 - %15 = load i8** %ra.i, align 8, !tbaa !0 + store i64 0, i64* %private_1, align 8 + %15 = load i8** %ra.i, align 8 %16 = ptrtoint i8* %15 to i64 %private_2 = getelementptr inbounds %struct._Unwind_Exception* %exc, i64 0, i32 3 - store i64 %16, i64* %private_2, align 8, !tbaa !3 + store i64 %16, i64* %private_2, align 8 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %2, i8* %3, i64 240, i32 8, i1 false) %17 = bitcast %struct._Unwind_FrameState* %fs.i to i8* call void @llvm.lifetime.start(i64 -1, i8* %17) @@ -130,21 +130,21 @@ while.end: ; preds = %if.then4 while.body.i: ; preds = %uw_update_context.exit44, %while.end %call.i = call fastcc i32 @uw_frame_state_for(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs.i) - %18 = load i8** %ra.i, align 8, !tbaa !0 + %18 = load i8** %ra.i, align 8 %19 = ptrtoint i8* %18 to i64 - %20 = load i64* %private_2, align 8, !tbaa !3 + %20 = load i64* %private_2, align 8 %cmp.i = icmp eq i64 %19, %20 %cmp2.i = icmp eq i32 %call.i, 0 br i1 %cmp2.i, label %if.end.i, label %do.end21 if.end.i: ; preds = %while.body.i - %21 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality.i, align 8, !tbaa !0 + %21 = load i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)** %personality.i, align 8 %tobool.i = icmp eq i32 (i32, i32, i64, %struct._Unwind_Exception*, %struct._Unwind_Context*)* %21, null br i1 %tobool.i, label %if.end12.i, label %if.then3.i if.then3.i: ; preds = %if.end.i %or.i = select i1 %cmp.i, i32 6, i32 2 - %22 = load i64* %exception_class, align 8, !tbaa !3 + %22 = load i64* %exception_class, align 8 %call5.i = call i32 %21(i32 1, i32 %or.i, i64 %22, %struct._Unwind_Exception* %exc, %struct._Unwind_Context* %cur_context) switch i32 %call5.i, label %do.end21 [ i32 7, label %do.body19 @@ -160,7 +160,7 @@ cond.true.i: ; preds = %if.end12.i cond.end.i: ; preds = %if.end12.i call fastcc void @uw_update_context_1(%struct._Unwind_Context* %cur_context, %struct._Unwind_FrameState* %fs.i) - %23 = load i64* %retaddr_column.i22, align 8, !tbaa !3 + %23 = load i64* %retaddr_column.i22, align 8 %conv.i23 = trunc i64 %23 to i32 %cmp.i.i.i24 = icmp slt i32 %conv.i23, 18 br i1 %cmp.i.i.i24, label %cond.end.i.i.i33, label %cond.true.i.i.i25 @@ -173,17 +173,17 @@ cond.end.i.i.i33: ; preds = %cond.end.i %sext.i26 = shl i64 %23, 32 %idxprom.i.i.i27 = ashr exact i64 %sext.i26, 32 %arrayidx.i.i.i28 = getelementptr inbounds [18 x i8]* @dwarf_reg_size_table, i64 0, i64 %idxprom.i.i.i27 - %24 = load i8* %arrayidx.i.i.i28, align 1, !tbaa !1 + %24 = load i8* %arrayidx.i.i.i28, align 1 %arrayidx2.i.i.i29 = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 0, i64 %idxprom.i.i.i27 - %25 = load i8** %arrayidx2.i.i.i29, align 8, !tbaa !0 - %26 = load i64* %flags.i.i.i.i, align 8, !tbaa !3 + %25 = load i8** %arrayidx2.i.i.i29, align 8 + %26 = load i64* %flags.i.i.i.i, align 8 %and.i.i.i.i31 = and i64 %26, 4611686018427387904 %tobool.i.i.i32 = icmp eq i64 %and.i.i.i.i31, 0 br i1 %tobool.i.i.i32, label %if.end.i.i.i39, label %land.lhs.true.i.i.i36 land.lhs.true.i.i.i36: ; preds = %cond.end.i.i.i33 %arrayidx4.i.i.i34 = getelementptr inbounds %struct._Unwind_Context* %cur_context, i64 0, i32 8, i64 %idxprom.i.i.i27 - %27 = load i8* %arrayidx4.i.i.i34, align 1, !tbaa !1 + %27 = load i8* %arrayidx4.i.i.i34, align 1 %tobool6.i.i.i35 = icmp eq i8 %27, 0 br i1 %tobool6.i.i.i35, label %if.end.i.i.i39, label %if.then.i.i.i37 @@ -197,7 +197,7 @@ if.end.i.i.i39: ; preds = %land.lhs.true.i.i.i if.then10.i.i.i40: ; preds = %if.end.i.i.i39 %29 = bitcast i8* %25 to i64* - %30 = load i64* %29, align 8, !tbaa !3 + %30 = load i64* %29, align 8 br label %uw_update_context.exit44 cond.true14.i.i.i41: ; preds = %if.end.i.i.i39 @@ -207,13 +207,13 @@ cond.true14.i.i.i41: ; preds = %if.end.i.i.i39 uw_update_context.exit44: ; preds = %if.then10.i.i.i40, %if.then.i.i.i37 %retval.0.i.i.i42 = phi i64 [ %28, %if.then.i.i.i37 ], [ %30, %if.then10.i.i.i40 ] %31 = inttoptr i64 %retval.0.i.i.i42 to i8* - store i8* %31, i8** %ra.i, align 8, !tbaa !0 + store i8* %31, i8** %ra.i, align 8 br label %while.body.i do.body19: ; preds = %if.then3.i call void @llvm.lifetime.end(i64 -1, i8* %17) %call20 = call fastcc i64 @uw_install_context_1(%struct._Unwind_Context* %this_context, %struct._Unwind_Context* %cur_context) - %32 = load i8** %ra.i, align 8, !tbaa !0 + %32 = load i8** %ra.i, align 8 call void @llvm.eh.return.i64(i64 %call20, i8* %32) unreachable @@ -245,8 +245,3 @@ declare fastcc void @uw_update_context_1(%struct._Unwind_Context*, %struct._Unwi declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"long", metadata !1} diff --git a/test/CodeGen/X86/v4f32-immediate.ll b/test/CodeGen/X86/v4f32-immediate.ll index b5ebaa74bd07..68d20a04ecf0 100644 --- a/test/CodeGen/X86/v4f32-immediate.ll +++ b/test/CodeGen/X86/v4f32-immediate.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse | grep movaps +; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s + +; CHECK: movaps define <4 x float> @foo() { ret <4 x float> <float 0x4009C9D0A0000000, float 0x4002666660000000, float 0x3FF3333340000000, float 0x3FB99999A0000000> diff --git a/test/CodeGen/X86/vararg_tailcall.ll b/test/CodeGen/X86/vararg_tailcall.ll index 73d80ebc1d5f..eeda5e15a168 100644 --- a/test/CodeGen/X86/vararg_tailcall.ll +++ b/test/CodeGen/X86/vararg_tailcall.ll @@ -39,7 +39,7 @@ declare void @bar2(i8*, i64) optsize noredzone ; WIN64: callq define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone { entry: - %tmp1 = load i8** @sel, align 8, !tbaa !0 + %tmp1 = load i8** @sel, align 8 %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone ret i8* %call } @@ -52,10 +52,10 @@ declare i8* @x2(i8*, i8*, ...) optsize noredzone ; WIN64: callq define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { entry: - %tmp2 = load i8** @sel3, align 8, !tbaa !0 - %tmp3 = load i8** @sel4, align 8, !tbaa !0 - %tmp4 = load i8** @sel5, align 8, !tbaa !0 - %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %tmp2 = load i8** @sel3, align 8 + %tmp3 = load i8** @sel4, align 8 + %tmp4 = load i8** @sel5, align 8 + %tmp5 = load i8** @sel6, align 8 %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone ret i8* %call } @@ -68,11 +68,11 @@ declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone ; WIN64: callq define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { entry: - %tmp2 = load i8** @sel3, align 8, !tbaa !0 - %tmp3 = load i8** @sel4, align 8, !tbaa !0 - %tmp4 = load i8** @sel5, align 8, !tbaa !0 - %tmp5 = load i8** @sel6, align 8, !tbaa !0 - %tmp6 = load i8** @sel7, align 8, !tbaa !0 + %tmp2 = load i8** @sel3, align 8 + %tmp3 = load i8** @sel4, align 8 + %tmp4 = load i8** @sel5, align 8 + %tmp5 = load i8** @sel6, align 8 + %tmp6 = load i8** @sel7, align 8 %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone ret i8* %call } @@ -85,14 +85,10 @@ declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone ; WIN64: callq define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { entry: - %tmp2 = load i8** @sel3, align 8, !tbaa !0 - %tmp3 = load i8** @sel4, align 8, !tbaa !0 - %tmp4 = load i8** @sel5, align 8, !tbaa !0 - %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %tmp2 = load i8** @sel3, align 8 + %tmp3 = load i8** @sel4, align 8 + %tmp4 = load i8** @sel5, align 8 + %tmp5 = load i8** @sel6, align 8 %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone ret i8* %call } - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/vec_compare.ll b/test/CodeGen/X86/vec_compare.ll index b6d91a3f770e..fd5c234bb160 100644 --- a/test/CodeGen/X86/vec_compare.ll +++ b/test/CodeGen/X86/vec_compare.ll @@ -65,3 +65,159 @@ define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind { %D = sext <2 x i1> %C to <2 x i64> ret <2 x i64> %D } + +define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: [[CONSTSEG:[A-Z0-9_]*]]: +; CHECK: .long 2147483648 +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 0 +; CHECK: test7: +; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pcmpgtd %xmm1 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: ret + %C = icmp sgt <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test8: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm0 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: ret + %C = icmp slt <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test9: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm0 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: pcmpeqd +; CHECK: pxor +; CHECK: ret + %C = icmp sge <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test10: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm1 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: pcmpeqd +; CHECK: pxor +; CHECK: ret + %C = icmp sle <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: [[CONSTSEG:[A-Z0-9_]*]]: +; CHECK: .long 2147483648 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 2147483648 +; CHECK-NEXT: .long 2147483648 +; CHECK: test11: +; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pxor [[CONSTREG]] +; CHECK: pcmpgtd %xmm1 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: ret + %C = icmp ugt <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test12: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm0 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: ret + %C = icmp ult <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test13: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm0 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: pcmpeqd +; CHECK: pxor +; CHECK: ret + %C = icmp uge <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} + +define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK: test14: +; CHECK: pxor +; CHECK: pxor +; CHECK: pcmpgtd %xmm1 +; CHECK: pshufd $-96 +; CHECK: pcmpeqd +; CHECK: pshufd $-11 +; CHECK: pand +; CHECK: pshufd $-11 +; CHECK: por +; CHECK: pcmpeqd +; CHECK: pxor +; CHECK: ret + %C = icmp ule <2 x i64> %A, %B + %D = sext <2 x i1> %C to <2 x i64> + ret <2 x i64> %D +} diff --git a/test/CodeGen/X86/vec_set-9.ll b/test/CodeGen/X86/vec_set-9.ll index b8ec0cf08095..6979f6bb1c26 100644 --- a/test/CodeGen/X86/vec_set-9.ll +++ b/test/CodeGen/X86/vec_set-9.ll @@ -1,5 +1,10 @@ -; RUN: llc < %s -march=x86-64 | grep movd | count 1 -; RUN: llc < %s -march=x86-64 | grep "movlhps.*%xmm0, %xmm0" +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: test3 +; CHECK: movd +; CHECK-NOT: movd +; CHECK: {{movlhps.*%xmm0, %xmm0}} +; CHECK-NEXT: ret define <2 x i64> @test3(i64 %A) nounwind { entry: diff --git a/test/CodeGen/X86/vec_set-B.ll b/test/CodeGen/X86/vec_set-B.ll index f5b3e8baa33a..5578ecaf0007 100644 --- a/test/CodeGen/X86/vec_set-B.ll +++ b/test/CodeGen/X86/vec_set-B.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movaps +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep esp | count 2 +; CHECK-NOT: movaps + ; These should both generate something like this: ;_test3: ; movl $1234567, %eax diff --git a/test/CodeGen/X86/vec_set-D.ll b/test/CodeGen/X86/vec_set-D.ll index 3d6369e1c76a..9c1e1acf0bab 100644 --- a/test/CodeGen/X86/vec_set-D.ll +++ b/test/CodeGen/X86/vec_set-D.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s + +; CHECK: movq define <4 x i32> @t(i32 %x, i32 %y) nounwind { %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %x, i32 0 diff --git a/test/CodeGen/X86/vec_set-I.ll b/test/CodeGen/X86/vec_set-I.ll index 64f36f99e4d2..c5d6ab88a35d 100644 --- a/test/CodeGen/X86/vec_set-I.ll +++ b/test/CodeGen/X86/vec_set-I.ll @@ -1,5 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd -; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xorp +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s + +; CHECK-NOT: xorp +; CHECK: movd +; CHECK-NOT: xorp define void @t1() nounwind { %tmp298.i.i = load <4 x float>* null, align 16 diff --git a/test/CodeGen/X86/vec_shuffle-28.ll b/test/CodeGen/X86/vec_shuffle-28.ll index 343685bf8ad2..ebf557762cb9 100644 --- a/test/CodeGen/X86/vec_shuffle-28.ll +++ b/test/CodeGen/X86/vec_shuffle-28.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=x86 -mcpu=core2 -o %t -; RUN: grep pshufb %t | count 1 +; RUN: llc < %s -march=x86 -mcpu=core2 | FileCheck %s + +; CHECK: pshufb +; CHECK-NOT: pshufb ; FIXME: this test has a superfluous punpcklqdq pre-pshufb currently. ; Don't XFAIL it because it's still better than the previous code. diff --git a/test/CodeGen/X86/vec_zero_cse.ll b/test/CodeGen/X86/vec_zero_cse.ll index 41ea0245ed86..bda3feff2b00 100644 --- a/test/CodeGen/X86/vec_zero_cse.ll +++ b/test/CodeGen/X86/vec_zero_cse.ll @@ -1,7 +1,13 @@ -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep xorps | count 1 -; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | grep pcmpeqd | count 1 +; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | FileCheck %s +; RUN: llc < %s -relocation-model=static -march=x86 -mcpu=yonah | FileCheck -check-prefix CHECK2 %s ; 64-bit stores here do not use MMX. +; CHECK: xorps +; CHECK-NOT: xorps + +; CHECK2: pcmpeqd +; CHECK2-NOT: pcmpeqd + @M1 = external global <1 x i64> @M2 = external global <2 x i32> diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll index 46b0e1890f11..82d20a23f357 100644 --- a/test/CodeGen/X86/vector.ll +++ b/test/CodeGen/X86/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. -; RUN: llc < %s -march=x86 -mcpu=i386 > %t -; RUN: llc < %s -march=x86 -mcpu=yonah >> %t +; RUN: llc < %s -march=x86 -mcpu=i386 +; RUN: llc < %s -march=x86 -mcpu=yonah %d8 = type <8 x double> %f1 = type <1 x float> diff --git a/test/CodeGen/X86/viabs.ll b/test/CodeGen/X86/viabs.ll new file mode 100644 index 000000000000..f748a14836c8 --- /dev/null +++ b/test/CodeGen/X86/viabs.ll @@ -0,0 +1,183 @@ +; RUN: llc < %s -march=x86-64 -mcpu=x86-64 | FileCheck %s -check-prefix=SSE2 +; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s -check-prefix=SSSE3 +; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2 + +define <4 x i32> @test1(<4 x i32> %a) nounwind { +; SSE2: test1: +; SSE2: movdqa +; SSE2: psrad $31 +; SSE2-NEXT: padd +; SSE2-NEXT: pxor +; SSE2-NEXT: ret + +; SSSE3: test1: +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test1: +; AVX2: vpabsd +; AVX2-NEXT: ret + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> + %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg + ret <4 x i32> %abs +} + +define <4 x i32> @test2(<4 x i32> %a) nounwind { +; SSE2: test2: +; SSE2: movdqa +; SSE2: psrad $31 +; SSE2-NEXT: padd +; SSE2-NEXT: pxor +; SSE2-NEXT: ret + +; SSSE3: test2: +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test2: +; AVX2: vpabsd +; AVX2-NEXT: ret + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sge <4 x i32> %a, zeroinitializer + %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg + ret <4 x i32> %abs +} + +define <8 x i16> @test3(<8 x i16> %a) nounwind { +; SSE2: test3: +; SSE2: movdqa +; SSE2: psraw $15 +; SSE2-NEXT: padd +; SSE2-NEXT: pxor +; SSE2-NEXT: ret + +; SSSE3: test3: +; SSSE3: pabsw +; SSSE3-NEXT: ret + +; AVX2: test3: +; AVX2: vpabsw +; AVX2-NEXT: ret + %tmp1neg = sub <8 x i16> zeroinitializer, %a + %b = icmp sgt <8 x i16> %a, zeroinitializer + %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg + ret <8 x i16> %abs +} + +define <16 x i8> @test4(<16 x i8> %a) nounwind { +; SSE2: test4: +; SSE2: pxor +; SSE2: pcmpgtb +; SSE2-NEXT: padd +; SSE2-NEXT: pxor +; SSE2-NEXT: ret + +; SSSE3: test4: +; SSSE3: pabsb +; SSSE3-NEXT: ret + +; AVX2: test4: +; AVX2: vpabsb +; AVX2-NEXT: ret + %tmp1neg = sub <16 x i8> zeroinitializer, %a + %b = icmp slt <16 x i8> %a, zeroinitializer + %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a + ret <16 x i8> %abs +} + +define <4 x i32> @test5(<4 x i32> %a) nounwind { +; SSE2: test5: +; SSE2: movdqa +; SSE2: psrad $31 +; SSE2-NEXT: padd +; SSE2-NEXT: pxor +; SSE2-NEXT: ret + +; SSSE3: test5: +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test5: +; AVX2: vpabsd +; AVX2-NEXT: ret + %tmp1neg = sub <4 x i32> zeroinitializer, %a + %b = icmp sle <4 x i32> %a, zeroinitializer + %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a + ret <4 x i32> %abs +} + +define <8 x i32> @test6(<8 x i32> %a) nounwind { +; SSSE3: test6: +; SSSE3: pabsd +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test6: +; AVX2: vpabsd {{.*}}%ymm +; AVX2-NEXT: ret + %tmp1neg = sub <8 x i32> zeroinitializer, %a + %b = icmp sgt <8 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %abs = select <8 x i1> %b, <8 x i32> %a, <8 x i32> %tmp1neg + ret <8 x i32> %abs +} + +define <8 x i32> @test7(<8 x i32> %a) nounwind { +; SSSE3: test7: +; SSSE3: pabsd +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test7: +; AVX2: vpabsd {{.*}}%ymm +; AVX2-NEXT: ret + %tmp1neg = sub <8 x i32> zeroinitializer, %a + %b = icmp sge <8 x i32> %a, zeroinitializer + %abs = select <8 x i1> %b, <8 x i32> %a, <8 x i32> %tmp1neg + ret <8 x i32> %abs +} + +define <16 x i16> @test8(<16 x i16> %a) nounwind { +; SSSE3: test8: +; SSSE3: pabsw +; SSSE3: pabsw +; SSSE3-NEXT: ret + +; AVX2: test8: +; AVX2: vpabsw {{.*}}%ymm +; AVX2-NEXT: ret + %tmp1neg = sub <16 x i16> zeroinitializer, %a + %b = icmp sgt <16 x i16> %a, zeroinitializer + %abs = select <16 x i1> %b, <16 x i16> %a, <16 x i16> %tmp1neg + ret <16 x i16> %abs +} + +define <32 x i8> @test9(<32 x i8> %a) nounwind { +; SSSE3: test9: +; SSSE3: pabsb +; SSSE3: pabsb +; SSSE3-NEXT: ret + +; AVX2: test9: +; AVX2: vpabsb {{.*}}%ymm +; AVX2-NEXT: ret + %tmp1neg = sub <32 x i8> zeroinitializer, %a + %b = icmp slt <32 x i8> %a, zeroinitializer + %abs = select <32 x i1> %b, <32 x i8> %tmp1neg, <32 x i8> %a + ret <32 x i8> %abs +} + +define <8 x i32> @test10(<8 x i32> %a) nounwind { +; SSSE3: test10: +; SSSE3: pabsd +; SSSE3: pabsd +; SSSE3-NEXT: ret + +; AVX2: test10: +; AVX2: vpabsd {{.*}}%ymm +; AVX2-NEXT: ret + %tmp1neg = sub <8 x i32> zeroinitializer, %a + %b = icmp sle <8 x i32> %a, zeroinitializer + %abs = select <8 x i1> %b, <8 x i32> %tmp1neg, <8 x i32> %a + ret <8 x i32> %abs +} diff --git a/test/CodeGen/X86/win32_sret.ll b/test/CodeGen/X86/win32_sret.ll index 52b987e2be65..2bfe5fb1007b 100644 --- a/test/CodeGen/X86/win32_sret.ll +++ b/test/CodeGen/X86/win32_sret.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; We specify -mcpu explicitly to avoid instruction reordering that happens on +; some setups (e.g., Atom) from affecting the output. +; RUN: llc < %s -mcpu=core2 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 ; RUN: llc < %s -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 +; RUN: llc < %s -mcpu=core2 -O0 -mtriple=i686-pc-win32 | FileCheck %s -check-prefix=WIN32 ; RUN: llc < %s -O0 -mtriple=i686-pc-mingw32 | FileCheck %s -check-prefix=MINGW_X86 ; RUN: llc < %s -O0 -mtriple=i386-pc-linux | FileCheck %s -check-prefix=LINUX @@ -117,11 +119,8 @@ entry: ; WIN32: movl %eax, (%e{{[sc][px]}}) ; The this pointer goes to ECX. -; FIXME: for some reason, the below checks fail on the Ubuntu Atom D2700 bot. -; FIXME-NEXT: leal {{[0-9]+}}(%esp), %ecx -; FIXME-NEXT: calll "?foo@C5@@QAE?AUS5@@XZ" - -; WIN32: calll "?foo@C5@@QAE?AUS5@@XZ" +; WIN32-NEXT: leal {{[0-9]+}}(%esp), %ecx +; WIN32-NEXT: calll "?foo@C5@@QAE?AUS5@@XZ" ; WIN32: ret ret void } diff --git a/test/CodeGen/X86/x86-64-frameaddr.ll b/test/CodeGen/X86/x86-64-frameaddr.ll index 57163d3c6839..7d36a7af6aaa 100644 --- a/test/CodeGen/X86/x86-64-frameaddr.ll +++ b/test/CodeGen/X86/x86-64-frameaddr.ll @@ -1,4 +1,9 @@ -; RUN: llc < %s -march=x86-64 | grep movq | grep rbp +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; CHECK: stack_end_address +; CHECK: {{movq.+rbp.*$}} +; CHECK: {{movq.+rbp.*$}} +; CHECK: ret define i64* @stack_end_address() nounwind { entry: diff --git a/test/CodeGen/X86/x86-64-pic-3.ll b/test/CodeGen/X86/x86-64-pic-3.ll index ba933788a3a5..1b0ddc6fe5ad 100644 --- a/test/CodeGen/X86/x86-64-pic-3.ll +++ b/test/CodeGen/X86/x86-64-pic-3.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic -o %t1 -; RUN: grep "callq f" %t1 -; RUN: not grep "callq f@PLT" %t1 +; RUN: llc < %s -mtriple=x86_64-pc-linux -relocation-model=pic | FileCheck %s + + +; CHECK-NOT: {{callq f@PLT}} +; CHECK: {{callq f}} +; CHECK-NOT: {{callq f@PLT}} define void @g() { entry: diff --git a/test/CodeGen/X86/x86-64-shortint.ll b/test/CodeGen/X86/x86-64-shortint.ll index cbf658888ced..75f89023509d 100644 --- a/test/CodeGen/X86/x86-64-shortint.ll +++ b/test/CodeGen/X86/x86-64-shortint.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s | grep movswl +; RUN: llc < %s | FileCheck %s + +; CHECK: movswl target datalayout = "e-p:64:64" target triple = "x86_64-apple-darwin8" diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll index 4f1dde3c4f0e..168b898f12bd 100644 --- a/test/CodeGen/X86/zext-extract_subreg.ll +++ b/test/CodeGen/X86/zext-extract_subreg.ll @@ -6,7 +6,7 @@ entry: br i1 undef, label %return, label %if.end.i if.end.i: ; preds = %entry - %tmp7.i = load i32* undef, align 4, !tbaa !0 + %tmp7.i = load i32* undef, align 4 br i1 undef, label %return, label %if.end if.end: ; preds = %if.end.i @@ -55,7 +55,3 @@ cond.false280: ; preds = %cond.true225 return: ; preds = %if.end.i, %entry ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/zext-inreg-0.ll b/test/CodeGen/X86/zext-inreg-0.ll index ae6221af9d81..688b88db526a 100644 --- a/test/CodeGen/X86/zext-inreg-0.ll +++ b/test/CodeGen/X86/zext-inreg-0.ll @@ -1,9 +1,12 @@ -; RUN: llc < %s -march=x86 | not grep and -; RUN: llc < %s -march=x86-64 > %t -; RUN: not grep and %t -; RUN: not grep movzbq %t -; RUN: not grep movzwq %t -; RUN: not grep movzlq %t +; RUN: llc < %s -march=x86 | FileCheck -check-prefix=X86 %s +; RUN: llc < %s -march=x86-64 | FileCheck -check-prefix=X64 %s + +; X86-NOT: and + +; X64-NOT: and +; X64-NOT: movzbq +; X64-NOT: movzwq +; X64-NOT: movzlq ; These should use movzbl instead of 'and 255'. ; This related to not having a ZERO_EXTEND_REG opcode. diff --git a/test/CodeGen/XCore/global_negative_offset.ll b/test/CodeGen/XCore/offset_folding.ll index 0328fb0460f3..30edfe695c3f 100644 --- a/test/CodeGen/XCore/global_negative_offset.ll +++ b/test/CodeGen/XCore/offset_folding.ll @@ -1,23 +1,40 @@ ; RUN: llc < %s -march=xcore | FileCheck %s -; Don't fold negative offsets into cp / dp accesses to avoid a relocation -; error if the address + addend is less than the start of the cp / dp. - @a = external constant [0 x i32], section ".cp.rodata" @b = external global [0 x i32] -define i32 *@f() nounwind { +define i32 *@f1() nounwind { +entry: +; CHECK: f1: +; CHECK: ldaw r11, cp[a+4] +; CHECK: mov r0, r11 + %0 = getelementptr [0 x i32]* @a, i32 0, i32 1 + ret i32* %0 +} + +define i32 *@f2() nounwind { +entry: +; CHECK: f2: +; CHECK: ldaw r0, dp[b+4] + %0 = getelementptr [0 x i32]* @b, i32 0, i32 1 + ret i32* %0 +} + +; Don't fold negative offsets into cp / dp accesses to avoid a relocation +; error if the address + addend is less than the start of the cp / dp. + +define i32 *@f3() nounwind { entry: -; CHECK: f: +; CHECK: f3: ; CHECK: ldaw r11, cp[a] ; CHECK: sub r0, r11, 4 %0 = getelementptr [0 x i32]* @a, i32 0, i32 -1 ret i32* %0 } -define i32 *@g() nounwind { +define i32 *@f4() nounwind { entry: -; CHECK: g: +; CHECK: f4: ; CHECK: ldaw [[REG:r[0-9]+]], dp[b] ; CHECK: sub r0, [[REG]], 4 %0 = getelementptr [0 x i32]* @b, i32 0, i32 -1 diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll index 0ee8e1c32667..772a847bd220 100644 --- a/test/CodeGen/XCore/unaligned_load.ll +++ b/test/CodeGen/XCore/unaligned_load.ll @@ -1,20 +1,19 @@ -; RUN: llc < %s -march=xcore > %t1.s -; RUN: grep "bl __misaligned_load" %t1.s | count 1 -; RUN: grep ld16s %t1.s | count 2 -; RUN: grep ldw %t1.s | count 2 -; RUN: grep shl %t1.s | count 2 -; RUN: grep shr %t1.s | count 1 -; RUN: grep zext %t1.s | count 1 -; RUN: grep "or " %t1.s | count 2 +; RUN: llc < %s -march=xcore | FileCheck %s -; Byte aligned load. Expands to call to __misaligned_load. +; Byte aligned load. +; CHECK: align1 +; CHECK: bl __misaligned_load define i32 @align1(i32* %p) nounwind { entry: %0 = load i32* %p, align 1 ; <i32> [#uses=1] ret i32 %0 } -; Half word aligned load. Expands to two 16bit loads. +; Half word aligned load. +; CHECK: align2: +; CHECK: ld16s +; CHECK: ld16s +; CHECK: or define i32 @align2(i32* %p) nounwind { entry: %0 = load i32* %p, align 2 ; <i32> [#uses=1] @@ -23,7 +22,11 @@ entry: @a = global [5 x i8] zeroinitializer, align 4 -; Constant offset from word aligned base. Expands to two 32bit loads. +; Constant offset from word aligned base. +; CHECK: align3: +; CHECK: ldw {{r[0-9]+}}, dp +; CHECK: ldw {{r[0-9]+}}, dp +; CHECK: or define i32 @align3() nounwind { entry: %0 = load i32* bitcast (i8* getelementptr ([5 x i8]* @a, i32 0, i32 1) to i32*), align 1 diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll index 62078e6f6077..94e1852faea7 100644 --- a/test/CodeGen/XCore/unaligned_store.ll +++ b/test/CodeGen/XCore/unaligned_store.ll @@ -1,16 +1,18 @@ -; RUN: llc < %s -march=xcore > %t1.s -; RUN: grep "bl __misaligned_store" %t1.s | count 1 -; RUN: grep st16 %t1.s | count 2 -; RUN: grep shr %t1.s | count 1 +; RUN: llc < %s -march=xcore | FileCheck %s -; Byte aligned store. Expands to call to __misaligned_store. +; Byte aligned store. +; CHECK: align1: +; CHECK: bl __misaligned_store define void @align1(i32* %p, i32 %val) nounwind { entry: store i32 %val, i32* %p, align 1 ret void } -; Half word aligned store. Expands to two 16bit stores. +; Half word aligned store. +; CHECK: align2 +; CHECK: st16 +; CHECK: st16 define void @align2(i32* %p, i32 %val) nounwind { entry: store i32 %val, i32* %p, align 2 diff --git a/test/DebugInfo/2010-03-19-DbgDeclare.ll b/test/DebugInfo/2010-03-19-DbgDeclare.ll index 1f7a889c7d70..9f52d1158a15 100644 --- a/test/DebugInfo/2010-03-19-DbgDeclare.ll +++ b/test/DebugInfo/2010-03-19-DbgDeclare.ll @@ -1,12 +1,17 @@ -; RUN: llvm-as < %s | opt -verify -disable-output +; RUN: llvm-as < %s | opt -verify -S -asm-verbose | FileCheck %s + +; CHECK: lang 0x8001 define void @Foo(i32 %a, i32 %b) { entry: call void @llvm.dbg.declare(metadata !{i32* null}, metadata !1) ret void } - +!llvm.dbg.cu = !{!2} +!2 = metadata !{i32 786449, metadata !4, i32 32769, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !3, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/scratch.cpp] [lang 0x8001] +!3 = metadata !{} !0 = metadata !{i32 662302, i32 26, metadata !1, null} !1 = metadata !{i32 4, metadata !"foo"} +!4 = metadata !{metadata !"scratch.cpp", metadata !"/usr/local/google/home/blaikie/dev/scratch"} declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone diff --git a/test/DebugInfo/2010-03-24-MemberFn.ll b/test/DebugInfo/2010-03-24-MemberFn.ll index 06c2367913da..15197f4461a6 100644 --- a/test/DebugInfo/2010-03-24-MemberFn.ll +++ b/test/DebugInfo/2010-03-24-MemberFn.ll @@ -43,7 +43,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !2 = metadata !{i32 786443, metadata !3, i32 3, i32 0} ; [ DW_TAG_lexical_block ] !3 = metadata !{i32 786478, metadata !4, metadata !4, metadata !"bar", metadata !"bar", metadata !"_Z3barv", i32 3, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @_Z3barv, null, null, null, i32 3} ; [ DW_TAG_subprogram ] !4 = metadata !{i32 786473, metadata !25} ; [ DW_TAG_file_type ] -!5 = metadata !{i32 786449, i32 4, metadata !4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !24, null, metadata !""} ; [ DW_TAG_compile_unit ] +!5 = metadata !{i32 786449, i32 4, metadata !4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !24, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !6 = metadata !{i32 786453, metadata !25, metadata !4, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ] !7 = metadata !{metadata !8} !8 = metadata !{i32 786468, metadata !25, metadata !4, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll index dd98db904509..7f8e418c9bd7 100644 --- a/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll +++ b/test/DebugInfo/2010-04-06-NestedFnDbgInfo.ll @@ -57,7 +57,7 @@ entry: !1 = metadata !{i32 786443, metadata !2, i32 15, i32 12} ; [ DW_TAG_lexical_block ] !2 = metadata !{i32 786478, metadata !3, metadata !"main", metadata !"main", metadata !"main", metadata !3, i32 15, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @main, null, null, null, i32 15} ; [ DW_TAG_subprogram ] !3 = metadata !{i32 786473, metadata !"one.cc", metadata !"/tmp", metadata !4} ; [ DW_TAG_file_type ] -!4 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang 1.5", i1 false, metadata !"", i32 0, null, null, metadata !37, null, metadata !""} ; [ DW_TAG_compile_unit ] +!4 = metadata !{i32 786449, i32 4, metadata !3, metadata !"clang 1.5", i1 false, metadata !"", i32 0, null, null, metadata !37, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !5 = metadata !{i32 786453, metadata !3, metadata !3, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !6, i32 0, null} ; [ DW_TAG_subroutine_type ] !6 = metadata !{metadata !7} !7 = metadata !{i32 786468, metadata !3, metadata !3, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/2010-04-19-FramePtr.ll b/test/DebugInfo/2010-04-19-FramePtr.ll index f9e90cd1b3d1..88eebe6f3b6f 100644 --- a/test/DebugInfo/2010-04-19-FramePtr.ll +++ b/test/DebugInfo/2010-04-19-FramePtr.ll @@ -25,7 +25,7 @@ return: ; preds = %entry !0 = metadata !{i32 2, i32 0, metadata !1, null} !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 2, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i1 false, i32 ()* @foo, null, null, null, i32 2} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !"a.c", metadata !"/tmp", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !9, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6} !6 = metadata !{i32 786468, metadata !2, metadata !"int", metadata !2, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll index e44362d4129e..f5ebb2d80c48 100644 --- a/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll +++ b/test/DebugInfo/2010-06-29-InlinedFnLocalVar.ll @@ -25,7 +25,7 @@ entry: !0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 9, metadata !3, i1 true, i1 true, i32 0, i32 0, null, i1 false, i1 true, null, null, null, metadata !24, i32 9} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !27} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !25, metadata !26, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 1, metadata !1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 true, metadata !"", i32 0, null, null, metadata !25, metadata !26, metadata !26, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !27, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5, metadata !5} !5 = metadata !{i32 786468, metadata !27, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/AArch64/dwarfdump.ll b/test/DebugInfo/AArch64/dwarfdump.ll index 673c789fe62c..bcdd4625b603 100644 --- a/test/DebugInfo/AArch64/dwarfdump.ll +++ b/test/DebugInfo/AArch64/dwarfdump.ll @@ -22,7 +22,7 @@ attributes #0 = { nounwind } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !9, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/llvm/build/tmp.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !9, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/llvm/build/tmp.c] [DW_LANG_C99] !1 = metadata !{i32 0} !2 = metadata !{metadata !3} !3 = metadata !{i32 786478, metadata !4, metadata !"main", metadata !"main", metadata !"", metadata !4, i32 1, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main] diff --git a/test/DebugInfo/AArch64/eh_frame.ll b/test/DebugInfo/AArch64/eh_frame.ll deleted file mode 100644 index 2539c56fa123..000000000000 --- a/test/DebugInfo/AArch64/eh_frame.ll +++ /dev/null @@ -1,51 +0,0 @@ -; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu %s -filetype=obj -o %t -; RUN: llvm-objdump -s %t | FileCheck %s -@var = global i32 0 - -declare void @bar() - -define i64 @check_largest_class(i32 %in) { - %res = load i32* @var - call void @bar() - %ext = zext i32 %res to i64 - ret i64 %ext -} - -; The really key points we're checking here are: -; * Return register is x30. -; * Pointer format is 0x1b (GNU doesn't appear to understand others). - -; The rest is largely incidental, but not expected to change regularly. - -; Output is: - -; CHECK: Contents of section .eh_frame: -; CHECK-NEXT: 0000 10000000 00000000 017a5200 017c1e01 .........zR..|.. -; CHECK-NEXT: 0010 1b0c1f00 18000000 18000000 00000000 ................ - - -; Won't check the rest, it's rather incidental. -; 0020 24000000 00440c1f 10449e02 93040000 $....D...D...... - - -; The first CIE: -; ------------------- -; 10000000: length of first CIE = 0x10 -; 00000000: This is a CIE -; 01: version = 0x1 -; 7a 52 00: augmentation string "zR" -- pointer format is specified -; 01: code alignment factor 1 -; 7c: data alignment factor -4 -; 1e: return address register 30 (== x30). -; 01: 1 byte of augmentation -; 1b: pointer format 1b: DW_EH_PE_pcrel | DW_EH_PE_sdata4 -; 0c 1f 00: initial instructions: "DW_CFA_def_cfa x31 ofs 0" in this case - -; Next the FDE: -; ------------- -; 18000000: FDE length 0x18 -; 18000000: Uses CIE 0x18 backwards (only coincidentally same as above) -; 00000000: PC begin for this FDE is at 00000000 (relocation is applied here) -; 24000000: FDE applies up to PC begin+0x24 -; 00: Augmentation string length 0 for this FDE -; Rest: call frame instructions diff --git a/test/DebugInfo/AArch64/eh_frame.s b/test/DebugInfo/AArch64/eh_frame.s new file mode 100644 index 000000000000..d8d6b6d9325f --- /dev/null +++ b/test/DebugInfo/AArch64/eh_frame.s @@ -0,0 +1,48 @@ +// RUN: llvm-mc -triple aarch64-none-linux-gnu -filetype=obj %s -o %t +// RUN: llvm-objdump -s %t | FileCheck %s + .text + .globl foo + .type foo,@function +foo: + .cfi_startproc + ret + .cfi_endproc + +// The really key points we're checking here are: +// * Return register is x30. +// * Pointer format is 0x1b (GNU doesn't appear to understand others). + +// The rest is largely incidental, but not expected to change regularly. + +// Output is: + +// CHECK: Contents of section .eh_frame: +// CHECK-NEXT: 0000 10000000 00000000 017a5200 017c1e01 .........zR..|.. +// CHECK-NEXT: 0010 1b0c1f00 10000000 18000000 00000000 ................ + + +// Won't check the rest, it's rather incidental. +// 0020 04000000 00000000 ........ + + + +// The first CIE: +// ------------------- +// 10000000: length of first CIE = 0x10 +// 00000000: This is a CIE +// 01: version = 0x1 +// 7a 52 00: augmentation string "zR" -- pointer format is specified +// 01: code alignment factor 1 +// 7c: data alignment factor -4 +// 1e: return address register 30 (== x30). +// 01: 1 byte of augmentation +// 1b: pointer format 1b: DW_EH_PE_pcrel | DW_EH_PE_sdata4 +// 0c 1f 00: initial instructions: "DW_CFA_def_cfa x31 ofs 0" in this case + +// Next the FDE: +// ------------- +// 10000000: FDE length 0x10 +// 18000000: Uses CIE 0x18 backwards (only coincidentally same as above) +// 00000000: PC begin for this FDE is at 00000000 (relocation is applied here) +// 04000000: FDE applies up to PC begin+0x14 +// 00: Augmentation string length 0 for this FDE diff --git a/test/DebugInfo/AArch64/variable-loc.ll b/test/DebugInfo/AArch64/variable-loc.ll index ac3037e04b4b..ba9e13aa2520 100644 --- a/test/DebugInfo/AArch64/variable-loc.ll +++ b/test/DebugInfo/AArch64/variable-loc.ll @@ -69,7 +69,7 @@ declare i32 @printf(i8*, ...) !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !29, i32 12, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !29, i32 12, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !11, metadata !14} !5 = metadata !{i32 786478, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array] diff --git a/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc b/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc new file mode 100644 index 000000000000..260c3c435c11 --- /dev/null +++ b/test/DebugInfo/Inputs/dwarfdump-test-zlib.cc @@ -0,0 +1,24 @@ +class DummyClass { + int a_; + public: + DummyClass(int a) : a_(a) {} + int add(int b) { + return a_ + b; + } +}; + +int f(int a, int b) { + DummyClass c(a); + return c.add(b); +} + +int main() { + return f(2, 3); +} + +// Built with Clang 3.2 and ld.gold linker: +// $ mkdir -p /tmp/dbginfo +// $ cp dwarfdump-test-zlib.cc /tmp/dbginfo +// $ cd /tmp/dbginfo +// $ clang++ -g dwarfdump-test-zlib.cc -Wl,--compress-debug-sections=zlib \ +// -o <output> diff --git a/test/DebugInfo/Inputs/dwarfdump-test-zlib.elf-x86-64 b/test/DebugInfo/Inputs/dwarfdump-test-zlib.elf-x86-64 Binary files differnew file mode 100755 index 000000000000..16b3153939fa --- /dev/null +++ b/test/DebugInfo/Inputs/dwarfdump-test-zlib.elf-x86-64 diff --git a/test/DebugInfo/SystemZ/eh_frame.s b/test/DebugInfo/SystemZ/eh_frame.s new file mode 100644 index 000000000000..4e7afd56e94b --- /dev/null +++ b/test/DebugInfo/SystemZ/eh_frame.s @@ -0,0 +1,54 @@ +# RUN: llvm-mc -triple=s390x-linux-gnu -filetype=obj %s -o %t +# RUN: llvm-objdump -s %t | FileCheck %s + + .text + .globl check_largest_class + .align 4 + .type check_largest_class,@function +check_largest_class: + .cfi_startproc + stmg %r13, %r15, 104(%r15) + .cfi_offset %r13, -56 + .cfi_offset %r14, -48 + .cfi_offset %r15, -40 + aghi %r15, -160 + .cfi_def_cfa_offset 320 + lmg %r13, %r15, 264(%r15) + br %r14 + .size check_largest_class, .-check_largest_class + .cfi_endproc + +# The readelf rendering is: +# +# Contents of the .eh_frame section: +# +# 00000000 0000001c 00000000 CIE +# Version: 1 +# Augmentation: "zR" +# Code alignment factor: 1 +# Data alignment factor: -8 +# Return address column: 14 +# Augmentation data: 1b +# +# DW_CFA_def_cfa: r15 ofs 160 +# DW_CFA_nop +# DW_CFA_nop +# DW_CFA_nop +# +# 00000020 0000001c 00000024 FDE cie=00000000 pc=00000000..00000012 +# DW_CFA_advance_loc: 6 to 00000006 +# DW_CFA_offset: r13 at cfa-56 +# DW_CFA_offset: r14 at cfa-48 +# DW_CFA_offset: r15 at cfa-40 +# DW_CFA_advance_loc: 4 to 0000000a +# DW_CFA_def_cfa_offset: 320 +# DW_CFA_nop +# DW_CFA_nop +# DW_CFA_nop +# DW_CFA_nop +# +# CHECK: Contents of section .eh_frame: +# CHECK-NEXT: 0000 00000014 00000000 017a5200 01780e01 .........zR..x.. +# CHECK-NEXT: 0010 1b0c0fa0 01000000 0000001c 0000001c ................ +# CHECK-NEXT: 0020 00000000 00000012 00468d07 8e068f05 .........F...... +# CHECK-NEXT: 0030 440ec002 00000000 D....... diff --git a/test/DebugInfo/SystemZ/eh_frame_personality.ll b/test/DebugInfo/SystemZ/eh_frame_personality.ll new file mode 100644 index 000000000000..92ba34da456c --- /dev/null +++ b/test/DebugInfo/SystemZ/eh_frame_personality.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-FUNC %s +; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu | FileCheck -check-prefix=CHECK-ET %s +; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -relocation-model=pic | FileCheck -check-prefix=CHECK-REF %s + +declare i32 @__gxx_personality_v0(...) + +declare void @bar() + +define i64 @foo(i64 %lhs, i64 %rhs) { + invoke void @bar() to label %end unwind label %clean +end: + ret i64 0 + +clean: + %tst = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) cleanup + ret i64 42 +} + +; CHECK-FUNC: foo: +; CHECK-FUNC: .cfi_startproc +; CHECK-FUNC: .cfi_personality 0, __gxx_personality_v0 +; CHECK-FUNC: .cfi_lsda 0, .Lexception0 +; CHECK-FUNC: stmg %r14, %r15, 112(%r15) +; CHECK-FUNC: .cfi_offset %r14, -48 +; CHECK-FUNC: .cfi_offset %r15, -40 +; CHECK-FUNC: aghi %r15, -160 +; CHECK-FUNC: .cfi_def_cfa_offset 320 +; ...main function... +; CHECK-FUNC: .cfi_endproc +; +; CHECK-ET: .section .gcc_except_table,"a",@progbits +; CHECK-ET-NEXT: .align 4 +; CHECK-ET-NEXT: GCC_except_table0: +; CHECK-ET-NEXT: .Lexception0: +; +; CHECK-REF: .cfi_personality 155, DW.ref.__gxx_personality_v0 +; CHECK-REF: .cfi_lsda 27, .Lexception0 +; CHECK-REF: .hidden DW.ref.__gxx_personality_v0 +; CHECK-REF: .weak DW.ref.__gxx_personality_v0 +; CHECK-REF: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat +; CHECK-REF-NEXT: .align 8 +; CHECK-REF-NEXT: .type DW.ref.__gxx_personality_v0,@object +; CHECK-REF-NEXT: .size DW.ref.__gxx_personality_v0, 8 +; CHECK-REF-NEXT: DW.ref.__gxx_personality_v0: +; CHECK-REF-NEXT: .quad __gxx_personality_v0 diff --git a/test/DebugInfo/SystemZ/eh_frame_personality.s b/test/DebugInfo/SystemZ/eh_frame_personality.s new file mode 100644 index 000000000000..46b46db1d806 --- /dev/null +++ b/test/DebugInfo/SystemZ/eh_frame_personality.s @@ -0,0 +1,67 @@ +# RUN: llvm-mc -triple=s390x-linux-gnu -filetype=obj %s -o %t +# RUN: llvm-objdump -s %t | FileCheck %s + + .text + .globl foo + .align 4 + .type foo,@function +foo: # @foo + .cfi_startproc + .cfi_personality 155, DW.ref.__gxx_personality_v0 + .cfi_lsda 27, .Lexception0 + stmg %r14, %r15, 112(%r15) + .cfi_offset %r14, -48 + .cfi_offset %r15, -40 + aghi %r15, -160 + .cfi_def_cfa_offset 320 + lmg %r14, %r15, 272(%r15) + br %r14 + .size foo, .-foo + .cfi_endproc + + .section .gcc_except_table,"a",@progbits + .align 4 +.Lexception0: + + .hidden DW.ref.__gxx_personality_v0 + .weak DW.ref.__gxx_personality_v0 + .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat + .align 8 + .type DW.ref.__gxx_personality_v0,@object + .size DW.ref.__gxx_personality_v0, 8 +DW.ref.__gxx_personality_v0: + .quad __gxx_personality_v0 + +# The readelf rendering is: +# +# Contents of the .eh_frame section: +# +# 00000000 0000001c 00000000 CIE +# Version: 1 +# Augmentation: "zPLR" +# Code alignment factor: 1 +# Data alignment factor: -8 +# Return address column: 14 +# Augmentation data: 9b ff ff ff ed 1b 1b +# +# DW_CFA_def_cfa: r15 ofs 160 +# DW_CFA_nop +# DW_CFA_nop +# DW_CFA_nop +# +# 00000020 0000001c 00000024 FDE cie=00000000 pc=00000000..00000012 +# Augmentation data: ff ff ff cf +# +# DW_CFA_advance_loc: 6 to 00000006 +# DW_CFA_offset: r14 at cfa-48 +# DW_CFA_offset: r15 at cfa-40 +# DW_CFA_advance_loc: 4 to 0000000a +# DW_CFA_def_cfa_offset: 320 +# DW_CFA_nop +# DW_CFA_nop +# +# CHECK: Contents of section .eh_frame: +# CHECK-NEXT: 0000 0000001c 00000000 017a504c 52000178 .........zPLR..x +# CHECK-NEXT: 0010 0e079b00 0000001b 1b0c0fa0 01000000 ................ +# CHECK-NEXT: 0020 0000001c 00000024 00000000 00000012 .......$........ +# CHECK-NEXT: 0030 04000000 00468e06 8f05440e c0020000 .....F....D..... diff --git a/test/DebugInfo/SystemZ/lit.local.cfg b/test/DebugInfo/SystemZ/lit.local.cfg new file mode 100644 index 000000000000..a70a6854381b --- /dev/null +++ b/test/DebugInfo/SystemZ/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'SystemZ' in targets: + config.unsupported = True + diff --git a/test/DebugInfo/SystemZ/variable-loc.ll b/test/DebugInfo/SystemZ/variable-loc.ll new file mode 100644 index 000000000000..e6f4ff99dd4f --- /dev/null +++ b/test/DebugInfo/SystemZ/variable-loc.ll @@ -0,0 +1,85 @@ +; RUN: llc -mtriple=s390x-linux-gnu -disable-fp-elim < %s | FileCheck %s +; +; This is a regression test making sure the location of variables is correct in +; debugging information, even if they're addressed via the frame pointer. +; A copy of the AArch64 test, commandeered for SystemZ. +; +; First make sure main_arr is where we expect it: %r11 + 164 +; +; CHECK: main: +; CHECK: aghi %r15, -568 +; CHECK: la [[MAIN_ARR:%r[0-9]+]], 164(%r11) +; CHECK: lgr %r2, [[MAIN_ARR]] +; CHECK: brasl %r14, populate_array@PLT +; +; Now check that the debugging information reflects this: +; CHECK: DW_TAG_variable +; CHECK-NEXT: .long .Linfo_string7 +; +; Rather hard-coded, but 145 => DW_OP_fbreg and the .ascii is the sleb128 +; encoding of 164: +; CHECK: DW_AT_location +; CHECK-NEXT: .byte 145 +; CHECK-NEXT: .ascii "\244\001" +; +; CHECK: .Linfo_string7: +; CHECK-NEXT: main_arr + + +@.str = private unnamed_addr constant [13 x i8] c"Total is %d\0A\00", align 2 + +declare void @populate_array(i32*, i32) nounwind + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare i32 @sum_array(i32*, i32) nounwind + +define i32 @main() nounwind { +entry: + %retval = alloca i32, align 4 + %main_arr = alloca [100 x i32], align 4 + %val = alloca i32, align 4 + store i32 0, i32* %retval + call void @llvm.dbg.declare(metadata !{[100 x i32]* %main_arr}, metadata !17), !dbg !22 + call void @llvm.dbg.declare(metadata !{i32* %val}, metadata !23), !dbg !24 + %arraydecay = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !25 + call void @populate_array(i32* %arraydecay, i32 100), !dbg !25 + %arraydecay1 = getelementptr inbounds [100 x i32]* %main_arr, i32 0, i32 0, !dbg !26 + %call = call i32 @sum_array(i32* %arraydecay1, i32 100), !dbg !26 + store i32 %call, i32* %val, align 4, !dbg !26 + %0 = load i32* %val, align 4, !dbg !27 + %call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), i32 %0), !dbg !27 + ret i32 0, !dbg !28 +} + +declare i32 @printf(i8*, ...) + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, metadata !29, i32 12, metadata !"clang version 3.2 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/timnor01/a64-trunk/build/simple.c] [DW_LANG_C99] +!1 = metadata !{i32 0} +!3 = metadata !{metadata !5, metadata !11, metadata !14} +!5 = metadata !{i32 786478, metadata !6, metadata !"populate_array", metadata !"populate_array", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*, i32)* @populate_array, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [populate_array] +!6 = metadata !{i32 786473, metadata !29} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{null, metadata !9, metadata !10} +!9 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from int] +!10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!11 = metadata !{i32 786478, metadata !6, metadata !"sum_array", metadata !"sum_array", metadata !"", metadata !6, i32 9, metadata !12, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32*, i32)* @sum_array, null, null, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [sum_array] +!12 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !13, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!13 = metadata !{metadata !10, metadata !9, metadata !10} +!14 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 18, metadata !15, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main] +!15 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!16 = metadata !{metadata !10} +!17 = metadata !{i32 786688, metadata !18, metadata !"main_arr", metadata !6, i32 19, metadata !19, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [main_arr] [line 19] +!18 = metadata !{i32 786443, metadata !6, metadata !14, i32 18, i32 16, i32 4} ; [ DW_TAG_lexical_block ] [/home/timnor01/a64-trunk/build/simple.c] +!19 = metadata !{i32 786433, null, null, metadata !"", i32 0, i64 3200, i64 32, i32 0, i32 0, metadata !10, metadata !20, i32 0, i32 0} ; [ DW_TAG_array_type ] [line 0, size 3200, align 32, offset 0] [from int] +!20 = metadata !{i32 786465, i64 0, i64 99} ; [ DW_TAG_subrange_type ] [0, 99] +!22 = metadata !{i32 19, i32 7, metadata !18, null} +!23 = metadata !{i32 786688, metadata !18, metadata !"val", metadata !6, i32 20, metadata !10, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [val] [line 20] +!24 = metadata !{i32 20, i32 7, metadata !18, null} +!25 = metadata !{i32 22, i32 3, metadata !18, null} +!26 = metadata !{i32 23, i32 9, metadata !18, null} +!27 = metadata !{i32 24, i32 3, metadata !18, null} +!28 = metadata !{i32 26, i32 3, metadata !18, null} +!29 = metadata !{metadata !"simple.c", metadata !"/home/timnor01/a64-trunk/build"} diff --git a/test/DebugInfo/SystemZ/variable-loc.s b/test/DebugInfo/SystemZ/variable-loc.s new file mode 100644 index 000000000000..d439a46d8f96 --- /dev/null +++ b/test/DebugInfo/SystemZ/variable-loc.s @@ -0,0 +1,340 @@ +# RUN: llvm-mc < %s -triple=s390x-linux-gnu -filetype=obj | llvm-dwarfdump - | FileCheck %s +# +# We use both R_390_32 and R_390_64 to encode the dwarf information. +# Test that they are used correctly. This uses the assembly output +# for variable-loc.ll +# +# A couple of R_390_32s, both at 0 and elsewhere: +# +# CHECK: DW_AT_producer [DW_FORM_strp] ( .debug_str[0x00000000] = "clang version 3.2 ") +# CHECK: DW_AT_name [DW_FORM_strp] ( .debug_str[0x00000013] = "simple.c") +# +# A couple of R_390_64s similarly: +# +# CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000000000000) +# CHECK: DW_AT_high_pc [DW_FORM_addr] (0x0000000000000050) + + + .file "test/DebugInfo/SystemZ/variable-loc.ll" + .section .debug_info,"",@progbits +.Lsection_info: + .section .debug_abbrev,"",@progbits +.Lsection_abbrev: + .section .debug_aranges,"",@progbits + .section .debug_macinfo,"",@progbits + .section .debug_line,"",@progbits +.Lsection_line: + .section .debug_loc,"",@progbits + .section .debug_pubtypes,"",@progbits + .section .debug_str,"MS",@progbits,1 +.Linfo_string: + .section .debug_ranges,"",@progbits +.Ldebug_range: + .section .debug_loc,"",@progbits +.Lsection_debug_loc: + .text +.Ltext_begin: + .data + .file 1 "simple.c" + .file 2 "<stdin>" + .text + .globl main + .align 4 + .type main,@function +main: # @main + .cfi_startproc +.Lfunc_begin0: + .loc 2 18 0 # :18:0 +# BB#0: # %entry + stmg %r12, %r15, 96(%r15) +.Ltmp2: + .cfi_offset %r12, -64 +.Ltmp3: + .cfi_offset %r13, -56 +.Ltmp4: + .cfi_offset %r14, -48 +.Ltmp5: + .cfi_offset %r15, -40 + aghi %r15, -568 +.Ltmp6: + .cfi_def_cfa_offset 728 + mvhi 564(%r15), 0 + la %r13, 164(%r15) + lhi %r12, 100 + .loc 2 22 3 prologue_end # :22:3 +.Ltmp7: + lgr %r2, %r13 + lr %r3, %r12 + brasl %r14, populate_array@PLT + .loc 2 23 9 # :23:9 + lgr %r2, %r13 + lr %r3, %r12 + brasl %r14, sum_array@PLT + lr %r0, %r2 + st %r0, 160(%r15) + .loc 2 24 3 # :24:3 + larl %r2, .L.str + lr %r3, %r0 + brasl %r14, printf@PLT + lhi %r2, 0 + .loc 2 26 3 # :26:3 + lmg %r12, %r15, 664(%r15) + br %r14 +.Ltmp8: +.Ltmp9: + .size main, .Ltmp9-main +.Lfunc_end0: + .cfi_endproc + + .type .L.str,@object # @.str + .section .rodata.str1.2,"aMS",@progbits,1 + .align 2 +.L.str: + .asciz "Total is %d\n" + .size .L.str, 13 + + .cfi_sections .debug_frame + .text +.Ltext_end: + .data +.Ldata_end: + .text +.Lsection_end1: + .section .debug_info,"",@progbits +.L.debug_info_begin0: + .long 155 # Length of Compilation Unit Info + .short 2 # DWARF version number + .long .L.debug_abbrev_begin # Offset Into Abbrev. Section + .byte 8 # Address Size (in bytes) + .byte 1 # Abbrev [1] 0xb:0x94 DW_TAG_compile_unit + .long .Linfo_string0 # DW_AT_producer + .short 12 # DW_AT_language + .long .Linfo_string1 # DW_AT_name + .quad 0 # DW_AT_low_pc + .long .Lsection_line # DW_AT_stmt_list + .long .Linfo_string2 # DW_AT_comp_dir + .byte 2 # Abbrev [2] 0x26:0x7 DW_TAG_subprogram + .long .Linfo_string3 # DW_AT_name + .byte 2 # DW_AT_decl_file + .byte 4 # DW_AT_decl_line + # DW_AT_prototyped + # DW_AT_external + .byte 3 # Abbrev [3] 0x2d:0xb DW_TAG_subprogram + .long .Linfo_string4 # DW_AT_name + .byte 2 # DW_AT_decl_file + .byte 9 # DW_AT_decl_line + # DW_AT_prototyped + .long 56 # DW_AT_type + # DW_AT_external + .byte 4 # Abbrev [4] 0x38:0x7 DW_TAG_base_type + .long .Linfo_string5 # DW_AT_name + .byte 5 # DW_AT_encoding + .byte 4 # DW_AT_byte_size + .byte 5 # Abbrev [5] 0x3f:0xb DW_TAG_subprogram + .long .Linfo_string6 # DW_AT_name + .byte 2 # DW_AT_decl_file + .byte 18 # DW_AT_decl_line + # DW_AT_prototyped + .long 56 # DW_AT_type + # DW_AT_external + # DW_AT_declaration + .byte 6 # Abbrev [6] 0x4a:0x7 DW_TAG_base_type + .long .Linfo_string5 # DW_AT_name + .byte 4 # DW_AT_byte_size + .byte 5 # DW_AT_encoding + .byte 7 # Abbrev [7] 0x51:0x5 DW_TAG_array_type + .long 56 # DW_AT_type + .byte 8 # Abbrev [8] 0x56:0x48 DW_TAG_subprogram + .long 63 # DW_AT_specification + .quad .Lfunc_begin0 # DW_AT_low_pc + .quad .Lfunc_end0 # DW_AT_high_pc + .byte 1 # DW_AT_frame_base + .byte 95 + # DW_AT_APPLE_omit_frame_ptr + .byte 9 # Abbrev [9] 0x6d:0x30 DW_TAG_lexical_block + .quad .Ltmp7 # DW_AT_low_pc + .quad .Ltmp8 # DW_AT_high_pc + .byte 10 # Abbrev [10] 0x7e:0xf DW_TAG_variable + .long .Linfo_string7 # DW_AT_name + .byte 2 # DW_AT_decl_file + .byte 19 # DW_AT_decl_line + .long 81 # DW_AT_type + .byte 3 # DW_AT_location + .byte 145 + .ascii "\244\001" + .byte 10 # Abbrev [10] 0x8d:0xf DW_TAG_variable + .long .Linfo_string8 # DW_AT_name + .byte 2 # DW_AT_decl_file + .byte 20 # DW_AT_decl_line + .long 56 # DW_AT_type + .byte 3 # DW_AT_location + .byte 145 + .ascii "\240\001" + .byte 0 # End Of Children Mark + .byte 0 # End Of Children Mark + .byte 0 # End Of Children Mark +.L.debug_info_end0: + .section .debug_abbrev,"",@progbits +.L.debug_abbrev_begin: + .byte 1 # Abbreviation Code + .byte 17 # DW_TAG_compile_unit + .byte 1 # DW_CHILDREN_yes + .byte 37 # DW_AT_producer + .byte 14 # DW_FORM_strp + .byte 19 # DW_AT_language + .byte 5 # DW_FORM_data2 + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 17 # DW_AT_low_pc + .byte 1 # DW_FORM_addr + .byte 16 # DW_AT_stmt_list + .byte 6 # DW_FORM_data4 + .byte 27 # DW_AT_comp_dir + .byte 14 # DW_FORM_strp + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 2 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 39 # DW_AT_prototyped + .byte 25 # DW_FORM_flag_present + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 3 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 39 # DW_AT_prototyped + .byte 25 # DW_FORM_flag_present + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 4 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 5 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 39 # DW_AT_prototyped + .byte 25 # DW_FORM_flag_present + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 63 # DW_AT_external + .byte 25 # DW_FORM_flag_present + .byte 60 # DW_AT_declaration + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 6 # Abbreviation Code + .byte 36 # DW_TAG_base_type + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 11 # DW_AT_byte_size + .byte 11 # DW_FORM_data1 + .byte 62 # DW_AT_encoding + .byte 11 # DW_FORM_data1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 7 # Abbreviation Code + .byte 1 # DW_TAG_array_type + .byte 0 # DW_CHILDREN_no + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 8 # Abbreviation Code + .byte 46 # DW_TAG_subprogram + .byte 1 # DW_CHILDREN_yes + .byte 71 # DW_AT_specification + .byte 19 # DW_FORM_ref4 + .byte 17 # DW_AT_low_pc + .byte 1 # DW_FORM_addr + .byte 18 # DW_AT_high_pc + .byte 1 # DW_FORM_addr + .byte 64 # DW_AT_frame_base + .byte 10 # DW_FORM_block1 + .ascii "\347\177" # DW_AT_APPLE_omit_frame_ptr + .byte 25 # DW_FORM_flag_present + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 9 # Abbreviation Code + .byte 11 # DW_TAG_lexical_block + .byte 1 # DW_CHILDREN_yes + .byte 17 # DW_AT_low_pc + .byte 1 # DW_FORM_addr + .byte 18 # DW_AT_high_pc + .byte 1 # DW_FORM_addr + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 10 # Abbreviation Code + .byte 52 # DW_TAG_variable + .byte 0 # DW_CHILDREN_no + .byte 3 # DW_AT_name + .byte 14 # DW_FORM_strp + .byte 58 # DW_AT_decl_file + .byte 11 # DW_FORM_data1 + .byte 59 # DW_AT_decl_line + .byte 11 # DW_FORM_data1 + .byte 73 # DW_AT_type + .byte 19 # DW_FORM_ref4 + .byte 2 # DW_AT_location + .byte 10 # DW_FORM_block1 + .byte 0 # EOM(1) + .byte 0 # EOM(2) + .byte 0 # EOM(3) +.L.debug_abbrev_end: + .section .debug_aranges,"",@progbits + .section .debug_ranges,"",@progbits + .section .debug_macinfo,"",@progbits + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "clang version 3.2 " +.Linfo_string1: + .asciz "simple.c" +.Linfo_string2: + .asciz "/home/timnor01/a64-trunk/build" +.Linfo_string3: + .asciz "populate_array" +.Linfo_string4: + .asciz "sum_array" +.Linfo_string5: + .asciz "int" +.Linfo_string6: + .asciz "main" +.Linfo_string7: + .asciz "main_arr" +.Linfo_string8: + .asciz "val" + + .section ".note.GNU-stack","",@progbits diff --git a/test/DebugInfo/X86/2010-04-13-PubType.ll b/test/DebugInfo/X86/2010-04-13-PubType.ll index 5169647fa41d..5bebeaaaf4ce 100644 --- a/test/DebugInfo/X86/2010-04-13-PubType.ll +++ b/test/DebugInfo/X86/2010-04-13-PubType.ll @@ -33,7 +33,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !0 = metadata !{i32 786689, metadata !1, metadata !"x", metadata !2, i32 7, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 786478, metadata !2, metadata !"foo", metadata !"foo", metadata !"foo", metadata !2, i32 7, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (%struct.X*, %struct.Y*)* @foo, null, null, null, i32 7} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !17, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 1, metadata !2, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, null, null, metadata !17, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] !5 = metadata !{metadata !6, metadata !7, metadata !9} !6 = metadata !{i32 786468, metadata !18, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll b/test/DebugInfo/X86/2010-08-10-DbgConstant.ll index d05dfc6c32be..94eba6af5bac 100644 --- a/test/DebugInfo/X86/2010-08-10-DbgConstant.ll +++ b/test/DebugInfo/X86/2010-08-10-DbgConstant.ll @@ -15,7 +15,7 @@ declare void @bar(i32) !0 = metadata !{i32 786478, metadata !1, metadata !"foo", metadata !"foo", metadata !"foo", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void ()* @foo, null, null, null, i32 3} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !12} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang 2.8", i1 false, metadata !"", i32 0, null, null, metadata !10, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !12, i32 12, metadata !"clang 2.8", i1 false, metadata !"", i32 0, null, null, metadata !10, metadata !11, metadata !11, metadata !""} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 786471, i32 0, metadata !1, metadata !"ro", metadata !"ro", metadata !"ro", metadata !1, i32 1, metadata !6, i1 true, i1 true, i32 201, null} ; [ DW_TAG_constant ] diff --git a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll index ad55db05a70e..7b8d91456a54 100644 --- a/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll +++ b/test/DebugInfo/X86/2011-09-26-GlobalVarContext.ll @@ -18,7 +18,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"clang version 3.0 (trunk)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !20, i32 12, metadata !"clang version 3.0 (trunk)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !12, metadata !12, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 720942, metadata !6, metadata !6, metadata !"f", metadata !"f", metadata !"", i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @f, null, null, metadata !10} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll index e248aa60295e..5464b87fd114 100644 --- a/test/DebugInfo/X86/2011-12-16-BadStructRef.ll +++ b/test/DebugInfo/X86/2011-12-16-BadStructRef.ll @@ -88,7 +88,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 720913, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 146596)", i1 false, metadata !"", i32 0, metadata !1, metadata !3, metadata !27, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 720913, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 146596)", i1 false, metadata !"", i32 0, metadata !1, metadata !3, metadata !27, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !9} !5 = metadata !{i32 720898, metadata !82, null, metadata !"bar", i32 9, i64 128, i64 64, i32 0, i32 0, null, metadata !7, i32 0, null, null} ; [ DW_TAG_class_type ] diff --git a/test/DebugInfo/X86/DW_AT_byte_size.ll b/test/DebugInfo/X86/DW_AT_byte_size.ll index 84e3f630976a..dcacba1912a3 100644 --- a/test/DebugInfo/X86/DW_AT_byte_size.ll +++ b/test/DebugInfo/X86/DW_AT_byte_size.ll @@ -24,7 +24,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 150996)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 150996)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooP1A", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%struct.A*)* @_Z3fooP1A, null, null, metadata !14, i32 3} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/DW_AT_location-reference.ll b/test/DebugInfo/X86/DW_AT_location-reference.ll index 356360b09834..6f1aa41fdde4 100644 --- a/test/DebugInfo/X86/DW_AT_location-reference.ll +++ b/test/DebugInfo/X86/DW_AT_location-reference.ll @@ -49,7 +49,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 define void @f() nounwind { entry: %call = tail call i32 @g(i32 0, i32 0) nounwind, !dbg !8 - store i32 %call, i32* @a, align 4, !dbg !8, !tbaa !9 + store i32 %call, i32* @a, align 4, !dbg !8 tail call void @llvm.dbg.value(metadata !12, i64 0, metadata !5), !dbg !13 br label %while.body @@ -63,7 +63,7 @@ while.body: ; preds = %entry, %while.body while.end: ; preds = %while.body tail call void @llvm.dbg.value(metadata !{i32 %mul}, i64 0, metadata !5), !dbg !14 %call4 = tail call i32 @g(i32 %mul, i32 0) nounwind, !dbg !15 - store i32 %call4, i32* @a, align 4, !dbg !15, !tbaa !9 + store i32 %call4, i32* @a, align 4, !dbg !15 tail call void @llvm.dbg.value(metadata !16, i64 0, metadata !5), !dbg !17 br label %while.body9 @@ -77,7 +77,7 @@ while.body9: ; preds = %while.end, %while.b while.end13: ; preds = %while.body9 tail call void @llvm.dbg.value(metadata !{i32 %mul12}, i64 0, metadata !5), !dbg !18 %call15 = tail call i32 @g(i32 0, i32 %mul12) nounwind, !dbg !19 - store i32 %call15, i32* @a, align 4, !dbg !19, !tbaa !9 + store i32 %call15, i32* @a, align 4, !dbg !19 ret void, !dbg !20 } @@ -89,16 +89,13 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"f", metadata !"f", metadata !"", metadata !1, i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @f, null, null, metadata !22, i32 4} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !23} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk)", i1 true, metadata !"", i32 0, null, null, metadata !21, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, i32 12, metadata !1, metadata !"clang version 3.0 (trunk)", i1 true, metadata !"", i32 0, null, null, metadata !21, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{null} !5 = metadata !{i32 786688, metadata !6, metadata !"x", metadata !1, i32 5, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] !6 = metadata !{i32 786443, metadata !1, metadata !0, i32 4, i32 14, i32 0} ; [ DW_TAG_lexical_block ] !7 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !8 = metadata !{i32 6, i32 3, metadata !6, null} -!9 = metadata !{metadata !"int", metadata !10} -!10 = metadata !{metadata !"omnipotent char", metadata !11} -!11 = metadata !{metadata !"Simple C/C++ TBAA", null} !12 = metadata !{i32 1} !13 = metadata !{i32 7, i32 3, metadata !6, null} !14 = metadata !{i32 8, i32 3, metadata !6, null} diff --git a/test/DebugInfo/X86/DW_AT_object_pointer.ll b/test/DebugInfo/X86/DW_AT_object_pointer.ll index a3ad26cf82bc..789f556cbca0 100644 --- a/test/DebugInfo/X86/DW_AT_object_pointer.ll +++ b/test/DebugInfo/X86/DW_AT_object_pointer.ll @@ -47,7 +47,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !37, i32 4, metadata !"clang version 3.2 (trunk 163586) (llvm/trunk 163570)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/debug-tests/bar.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, metadata !37, i32 4, metadata !"clang version 3.2 (trunk 163586) (llvm/trunk 163570)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/debug-tests/bar.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !10, metadata !20} !5 = metadata !{i32 786478, metadata !6, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", i32 7, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @_Z3fooi, null, null, metadata !1, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [foo] diff --git a/test/DebugInfo/X86/DW_AT_specification.ll b/test/DebugInfo/X86/DW_AT_specification.ll index 07849f352268..93e1ecf38f62 100644 --- a/test/DebugInfo/X86/DW_AT_specification.ll +++ b/test/DebugInfo/X86/DW_AT_specification.ll @@ -16,7 +16,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !27, i32 4, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !27, i32 4, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18, metadata !18, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 720942, metadata !6, null, metadata !"bar", metadata !"bar", metadata !"_ZN3foo3barEv", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void ()* @_ZN3foo3barEv, null, metadata !11, metadata !16, i32 4} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/DW_TAG_friend.ll b/test/DebugInfo/X86/DW_TAG_friend.ll index f60175fb69aa..2e23222588e0 100644 --- a/test/DebugInfo/X86/DW_TAG_friend.ll +++ b/test/DebugInfo/X86/DW_TAG_friend.ll @@ -17,7 +17,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !28, i32 4, metadata !"clang version 3.1 (trunk 153413) (llvm/trunk 153428)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !28, i32 4, metadata !"clang version 3.1 (trunk 153413) (llvm/trunk 153428)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !17} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 10, metadata !7, i32 0, i32 1, %class.A* @a, null} ; [ DW_TAG_variable ] diff --git a/test/DebugInfo/X86/aligned_stack_var.ll b/test/DebugInfo/X86/aligned_stack_var.ll index a8f6cca750c0..b99de3c1ea70 100644 --- a/test/DebugInfo/X86/aligned_stack_var.ll +++ b/test/DebugInfo/X86/aligned_stack_var.ll @@ -26,7 +26,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 155696:155697) (llvm/trunk 155696)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"run", metadata !"run", metadata !"_Z3runv", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/block-capture.ll b/test/DebugInfo/X86/block-capture.ll index fadea775aadf..004673061d8c 100644 --- a/test/DebugInfo/X86/block-capture.ll +++ b/test/DebugInfo/X86/block-capture.ll @@ -62,7 +62,7 @@ declare i32 @__objc_personality_v0(...) !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!35, !36, !37, !38} -!0 = metadata !{i32 786449, metadata !63, i32 16, metadata !"clang version 3.1 (trunk 151227)", i1 false, metadata !"", i32 2, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !63, i32 16, metadata !"clang version 3.1 (trunk 151227)", i1 false, metadata !"", i32 2, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !28, metadata !31, metadata !34} !5 = metadata !{i32 786478, metadata !6, metadata !6, metadata !"foo", metadata !"foo", metadata !"", i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, null, null, null, metadata !26, i32 5} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/concrete_out_of_line.ll b/test/DebugInfo/X86/concrete_out_of_line.ll index 48e1defd4c95..3b9aefc38f56 100644 --- a/test/DebugInfo/X86/concrete_out_of_line.ll +++ b/test/DebugInfo/X86/concrete_out_of_line.ll @@ -34,7 +34,7 @@ declare void @_Z8moz_freePv(i8*) !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !59, i32 4, metadata !"clang version 3.1 ()", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !59, i32 4, metadata !"clang version 3.1 ()", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !47, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !23, metadata !27, metadata !31} !5 = metadata !{i32 720942, metadata !6, null, metadata !"Release", metadata !"Release", metadata !"_ZN17nsAutoRefCnt7ReleaseEv", i32 14, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32* null, null, metadata !12, metadata !20, i32 14} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll index e7a554ff868d..da6423fa76a1 100644 --- a/test/DebugInfo/X86/dbg-value-inlined-parameter.ll +++ b/test/DebugInfo/X86/dbg-value-inlined-parameter.ll @@ -22,10 +22,10 @@ entry: tail call void @llvm.dbg.value(metadata !{%struct.S1* %sp}, i64 0, metadata !9), !dbg !20 tail call void @llvm.dbg.value(metadata !{i32 %nums}, i64 0, metadata !18), !dbg !21 %tmp2 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 1, !dbg !22 - store i32 %nums, i32* %tmp2, align 4, !dbg !22, !tbaa !24 + store i32 %nums, i32* %tmp2, align 4, !dbg !22 %call = tail call float* @bar(i32 %nums) nounwind optsize, !dbg !27 %tmp5 = getelementptr inbounds %struct.S1* %sp, i64 0, i32 0, !dbg !27 - store float* %call, float** %tmp5, align 8, !dbg !27, !tbaa !28 + store float* %call, float** %tmp5, align 8, !dbg !27 %cmp = icmp ne float* %call, null, !dbg !29 %cond = zext i1 %cmp to i32, !dbg !29 ret i32 %cond, !dbg !29 @@ -37,9 +37,9 @@ define void @foobar() nounwind optsize ssp { entry: tail call void @llvm.dbg.value(metadata !30, i64 0, metadata !9) nounwind, !dbg !31 tail call void @llvm.dbg.value(metadata !34, i64 0, metadata !18) nounwind, !dbg !35 - store i32 1, i32* getelementptr inbounds (%struct.S1* @p, i64 0, i32 1), align 8, !dbg !36, !tbaa !24 + store i32 1, i32* getelementptr inbounds (%struct.S1* @p, i64 0, i32 1), align 8, !dbg !36 %call.i = tail call float* @bar(i32 1) nounwind optsize, !dbg !37 - store float* %call.i, float** getelementptr inbounds (%struct.S1* @p, i64 0, i32 0), align 8, !dbg !37, !tbaa !28 + store float* %call.i, float** getelementptr inbounds (%struct.S1* @p, i64 0, i32 0), align 8, !dbg !37 ret void, !dbg !38 } @@ -49,7 +49,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !1, metadata !"foo", metadata !"foo", metadata !"", i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (%struct.S1*, i32)* @foo, null, null, metadata !41, i32 8} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !42} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !42, i32 12, metadata !"clang version 2.9 (trunk 125693)", i1 true, metadata !"", i32 0, null, null, metadata !39, metadata !40, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !42, i32 12, metadata !"clang version 2.9 (trunk 125693)", i1 true, metadata !"", i32 0, null, null, metadata !39, metadata !40, metadata !40, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !42, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -71,11 +71,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !21 = metadata !{i32 7, i32 21, metadata !0, null} !22 = metadata !{i32 9, i32 3, metadata !23, null} !23 = metadata !{i32 786443, metadata !1, metadata !0, i32 8, i32 1, i32 0} ; [ DW_TAG_lexical_block ] -!24 = metadata !{metadata !"int", metadata !25} -!25 = metadata !{metadata !"omnipotent char", metadata !26} -!26 = metadata !{metadata !"Simple C/C++ TBAA", null} !27 = metadata !{i32 10, i32 3, metadata !23, null} -!28 = metadata !{metadata !"any pointer", metadata !25} !29 = metadata !{i32 11, i32 3, metadata !23, null} !30 = metadata !{%struct.S1* @p} !31 = metadata !{i32 7, i32 13, metadata !0, metadata !32} diff --git a/test/DebugInfo/X86/debug-info-block-captured-self.ll b/test/DebugInfo/X86/debug-info-block-captured-self.ll index 77e02c62aada..7e318f6443f8 100644 --- a/test/DebugInfo/X86/debug-info-block-captured-self.ll +++ b/test/DebugInfo/X86/debug-info-block-captured-self.ll @@ -77,7 +77,7 @@ define internal void @"__24-[Main initWithContext:]_block_invoke_2"(i8* %.block_ } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 16, metadata !1, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !4, metadata !23, metadata !15, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m] [DW_LANG_ObjC] +!0 = metadata !{i32 786449, i32 16, metadata !1, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !4, metadata !23, metadata !15, metadata !15, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/debug-info-block-captured-self.m] [DW_LANG_ObjC] !1 = metadata !{i32 786473, metadata !107} ; [ DW_TAG_file_type ] !2 = metadata !{metadata !3} !3 = metadata !{i32 786436, metadata !107, null, metadata !"", i32 20, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [from ] diff --git a/test/DebugInfo/X86/debug-info-blocks.ll b/test/DebugInfo/X86/debug-info-blocks.ll index 36ab61100856..ae9503303812 100644 --- a/test/DebugInfo/X86/debug-info-blocks.ll +++ b/test/DebugInfo/X86/debug-info-blocks.ll @@ -260,7 +260,7 @@ attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!56, !57, !58, !59} -!0 = metadata !{i32 786449, metadata !1, i32 16, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !3, metadata !12, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/<unknown>] [DW_LANG_ObjC] +!0 = metadata !{i32 786449, metadata !1, i32 16, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 2, metadata !2, metadata !3, metadata !12, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [llvm/tools/clang/test/CodeGenObjC/<unknown>] [DW_LANG_ObjC] !1 = metadata !{metadata !"llvm/tools/clang/test/CodeGenObjC/<unknown>", metadata !"llvm/_build.ninja.Debug"} !2 = metadata !{i32 0} !3 = metadata !{metadata !4} diff --git a/test/DebugInfo/X86/debug-info-static-member.ll b/test/DebugInfo/X86/debug-info-static-member.ll index 50a2b3fa5163..33485b680748 100644 --- a/test/DebugInfo/X86/debug-info-static-member.ll +++ b/test/DebugInfo/X86/debug-info-static-member.ll @@ -58,7 +58,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 (trunk 171914)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !10, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/projects/upstream/static-member/test/debug-info-static-member.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 (trunk 171914)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !10, metadata !10, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/projects/upstream/static-member/test/debug-info-static-member.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 18, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 23} ; [ DW_TAG_subprogram ] [line 18] [def] [scope 23] [main] diff --git a/test/DebugInfo/X86/elf-names.ll b/test/DebugInfo/X86/elf-names.ll index 30e8c2e27430..7bc532ebad06 100644 --- a/test/DebugInfo/X86/elf-names.ll +++ b/test/DebugInfo/X86/elf-names.ll @@ -21,13 +21,13 @@ define void @_ZN1DC2Ev(%class.D* nocapture %this) unnamed_addr nounwind uwtable entry: tail call void @llvm.dbg.value(metadata !{%class.D* %this}, i64 0, metadata !29), !dbg !36 %c1 = getelementptr inbounds %class.D* %this, i64 0, i32 0, !dbg !37 - store i32 1, i32* %c1, align 4, !dbg !37, !tbaa !39 + store i32 1, i32* %c1, align 4, !dbg !37 %c2 = getelementptr inbounds %class.D* %this, i64 0, i32 1, !dbg !42 - store i32 2, i32* %c2, align 4, !dbg !42, !tbaa !39 + store i32 2, i32* %c2, align 4, !dbg !42 %c3 = getelementptr inbounds %class.D* %this, i64 0, i32 2, !dbg !43 - store i32 3, i32* %c3, align 4, !dbg !43, !tbaa !39 + store i32 3, i32* %c3, align 4, !dbg !43 %c4 = getelementptr inbounds %class.D* %this, i64 0, i32 3, !dbg !44 - store i32 4, i32* %c4, align 4, !dbg !44, !tbaa !39 + store i32 4, i32* %c4, align 4, !dbg !44 ret void, !dbg !45 } @@ -36,21 +36,21 @@ entry: tail call void @llvm.dbg.value(metadata !{%class.D* %this}, i64 0, metadata !34), !dbg !46 tail call void @llvm.dbg.value(metadata !{%class.D* %d}, i64 0, metadata !35), !dbg !46 %c1 = getelementptr inbounds %class.D* %d, i64 0, i32 0, !dbg !47 - %0 = load i32* %c1, align 4, !dbg !47, !tbaa !39 + %0 = load i32* %c1, align 4, !dbg !47 %c12 = getelementptr inbounds %class.D* %this, i64 0, i32 0, !dbg !47 - store i32 %0, i32* %c12, align 4, !dbg !47, !tbaa !39 + store i32 %0, i32* %c12, align 4, !dbg !47 %c2 = getelementptr inbounds %class.D* %d, i64 0, i32 1, !dbg !49 - %1 = load i32* %c2, align 4, !dbg !49, !tbaa !39 + %1 = load i32* %c2, align 4, !dbg !49 %c23 = getelementptr inbounds %class.D* %this, i64 0, i32 1, !dbg !49 - store i32 %1, i32* %c23, align 4, !dbg !49, !tbaa !39 + store i32 %1, i32* %c23, align 4, !dbg !49 %c3 = getelementptr inbounds %class.D* %d, i64 0, i32 2, !dbg !50 - %2 = load i32* %c3, align 4, !dbg !50, !tbaa !39 + %2 = load i32* %c3, align 4, !dbg !50 %c34 = getelementptr inbounds %class.D* %this, i64 0, i32 2, !dbg !50 - store i32 %2, i32* %c34, align 4, !dbg !50, !tbaa !39 + store i32 %2, i32* %c34, align 4, !dbg !50 %c4 = getelementptr inbounds %class.D* %d, i64 0, i32 3, !dbg !51 - %3 = load i32* %c4, align 4, !dbg !51, !tbaa !39 + %3 = load i32* %c4, align 4, !dbg !51 %c45 = getelementptr inbounds %class.D* %this, i64 0, i32 3, !dbg !51 - store i32 %3, i32* %c45, align 4, !dbg !51, !tbaa !39 + store i32 %3, i32* %c45, align 4, !dbg !51 ret void, !dbg !52 } @@ -58,7 +58,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !53, i32 4, metadata !"clang version 3.2 (trunk 167506) (llvm/trunk 167505)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/foo.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, metadata !53, i32 4, metadata !"clang version 3.2 (trunk 167506) (llvm/trunk 167505)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/foo.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !31} !5 = metadata !{i32 786478, metadata !6, null, metadata !"D", metadata !"D", metadata !"_ZN1DC2Ev", i32 12, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (%class.D*)* @_ZN1DC2Ev, null, metadata !17, metadata !27, i32 12} ; [ DW_TAG_subprogram ] [line 12] [def] [D] @@ -95,9 +95,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !36 = metadata !{i32 12, i32 0, metadata !5, null} !37 = metadata !{i32 13, i32 0, metadata !38, null} !38 = metadata !{i32 786443, metadata !5, i32 12, i32 0, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/foo.cpp] -!39 = metadata !{metadata !"int", metadata !40} -!40 = metadata !{metadata !"omnipotent char", metadata !41} -!41 = metadata !{metadata !"Simple C/C++ TBAA"} !42 = metadata !{i32 14, i32 0, metadata !38, null} !43 = metadata !{i32 15, i32 0, metadata !38, null} !44 = metadata !{i32 16, i32 0, metadata !38, null} diff --git a/test/DebugInfo/X86/empty-and-one-elem-array.ll b/test/DebugInfo/X86/empty-and-one-elem-array.ll index 6e59915fe13e..ce3035e4f98f 100644 --- a/test/DebugInfo/X86/empty-and-one-elem-array.ll +++ b/test/DebugInfo/X86/empty-and-one-elem-array.ll @@ -59,7 +59,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/test.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/test.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !6, metadata !"func", metadata !"func", metadata !"", i32 11, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @func, null, null, metadata !1, i32 11} ; [ DW_TAG_subprogram ] [line 11] [def] [func] diff --git a/test/DebugInfo/X86/empty-array.ll b/test/DebugInfo/X86/empty-array.ll index ace115610ebc..1f462816337a 100644 --- a/test/DebugInfo/X86/empty-array.ll +++ b/test/DebugInfo/X86/empty-array.ll @@ -24,7 +24,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, %class.A* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] diff --git a/test/DebugInfo/X86/ending-run.ll b/test/DebugInfo/X86/ending-run.ll index 6de15f6404cb..b0156b8eac9d 100644 --- a/test/DebugInfo/X86/ending-run.ll +++ b/test/DebugInfo/X86/ending-run.ll @@ -28,7 +28,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !19, i32 12, metadata !"clang version 3.1 (trunk 153921) (llvm/trunk 153916)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !19, i32 12, metadata !"clang version 3.1 (trunk 153921) (llvm/trunk 153916)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !19, metadata !"callee", metadata !"callee", metadata !"", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 (i32)* @callee, null, null, metadata !10, i32 7} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/enum-class.ll b/test/DebugInfo/X86/enum-class.ll index 22728116d9bb..af6129cc28a9 100644 --- a/test/DebugInfo/X86/enum-class.ll +++ b/test/DebugInfo/X86/enum-class.ll @@ -7,7 +7,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !22, i32 4, metadata !"clang version 3.2 (trunk 157269) (llvm/trunk 157264)", i1 false, metadata !"", i32 0, metadata !1, metadata !15, metadata !15, metadata !17, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !22, i32 4, metadata !"clang version 3.2 (trunk 157269) (llvm/trunk 157264)", i1 false, metadata !"", i32 0, metadata !1, metadata !15, metadata !15, metadata !17, metadata !17, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{metadata !3, metadata !8, metadata !12} !3 = metadata !{i32 786436, metadata !4, null, metadata !"A", i32 1, i64 32, i64 32, i32 0, i32 0, metadata !5, metadata !6, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] !4 = metadata !{i32 786473, metadata !22} ; [ DW_TAG_file_type ] diff --git a/test/DebugInfo/X86/enum-fwd-decl.ll b/test/DebugInfo/X86/enum-fwd-decl.ll index 33d807e30548..f4ff8b4fe4d8 100644 --- a/test/DebugInfo/X86/enum-fwd-decl.ll +++ b/test/DebugInfo/X86/enum-fwd-decl.ll @@ -5,7 +5,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i16* @e, null} ; [ DW_TAG_variable ] [e] [line 2] [def] diff --git a/test/DebugInfo/X86/fission-cu.ll b/test/DebugInfo/X86/fission-cu.ll index bfe2d17e20f1..8ad3c2d97a53 100644 --- a/test/DebugInfo/X86/fission-cu.ll +++ b/test/DebugInfo/X86/fission-cu.ll @@ -1,11 +1,12 @@ ; RUN: llc -split-dwarf=Enable -O0 %s -mtriple=x86_64-unknown-linux-gnu -filetype=obj -o %t ; RUN: llvm-dwarfdump -debug-dump=all %t | FileCheck %s +; RUN: llvm-readobj --relocations %t | FileCheck --check-prefix=OBJ %s @a = common global i32 0, align 4 !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.3 (trunk 169021) (llvm/trunk 169020)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !"baz.dwo"} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/baz.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.3 (trunk 169021) (llvm/trunk 169020)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !"baz.dwo"} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/baz.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] @@ -48,9 +49,9 @@ ; CHECK: DW_AT_producer DW_FORM_GNU_str_index ; CHECK: DW_AT_language DW_FORM_data2 ; CHECK: DW_AT_name DW_FORM_GNU_str_index -; CHECK: DW_AT_low_pc DW_FORM_GNU_addr_index -; CHECK: DW_AT_stmt_list DW_FORM_data4 -; CHECK: DW_AT_comp_dir DW_FORM_GNU_str_index +; CHECK-NOT: DW_AT_low_pc +; CHECK-NOT: DW_AT_stmt_list +; CHECK-NOT: DW_AT_comp_dir ; CHECK: DW_AT_GNU_dwo_id DW_FORM_data8 ; CHECK: [2] DW_TAG_base_type DW_CHILDREN_no @@ -72,29 +73,40 @@ ; CHECK: DW_AT_producer [DW_FORM_GNU_str_index] ( indexed (00000000) string = "clang version 3.3 (trunk 169021) (llvm/trunk 169020)") ; CHECK: DW_AT_language [DW_FORM_data2] (0x000c) ; CHECK: DW_AT_name [DW_FORM_GNU_str_index] ( indexed (00000001) string = "baz.c") -; CHECK: DW_AT_low_pc [DW_FORM_GNU_addr_index] ( indexed (00000000) address = 0x0000000000000000) +; CHECK-NOT: DW_AT_low_pc +; CHECK-NOT: DW_AT_stmt_list +; CHECK-NOT: DW_AT_comp_dir ; CHECK: DW_AT_GNU_dwo_id [DW_FORM_data8] (0x0000000000000000) ; CHECK: DW_TAG_base_type -; CHECK: DW_AT_name [DW_FORM_GNU_str_index] ( indexed (00000004) string = "int") +; CHECK: DW_AT_name [DW_FORM_GNU_str_index] ( indexed (00000003) string = "int") ; CHECK: DW_TAG_variable -; CHECK: DW_AT_name [DW_FORM_GNU_str_index] ( indexed (00000003) string = "a") -; CHECK: DW_AT_type [DW_FORM_ref4] (cu + 0x001e => {0x0000001e}) +; CHECK: DW_AT_name [DW_FORM_GNU_str_index] ( indexed (00000002) string = "a") +; CHECK: DW_AT_type [DW_FORM_ref4] (cu + 0x0018 => {0x00000018}) ; CHECK: DW_AT_external [DW_FORM_flag_present] (true) ; CHECK: DW_AT_decl_file [DW_FORM_data1] (0x01) ; CHECK: DW_AT_decl_line [DW_FORM_data1] (0x01) -; CHECK: DW_AT_location [DW_FORM_block1] (<0x02> fb 01 ) +; CHECK: DW_AT_location [DW_FORM_block1] (<0x02> fb 00 ) ; CHECK: .debug_str.dwo contents: ; CHECK: 0x00000000: "clang version 3.3 (trunk 169021) (llvm/trunk 169020)" ; CHECK: 0x00000035: "baz.c" -; CHECK: 0x0000003b: "/usr/local/google/home/echristo/tmp" -; CHECK: 0x0000005f: "a" -; CHECK: 0x00000061: "int" +; CHECK: 0x0000003b: "a" +; CHECK: 0x0000003d: "int" ; CHECK: .debug_str_offsets.dwo contents: ; CHECK: 0x00000000: 00000000 ; CHECK: 0x00000004: 00000035 ; CHECK: 0x00000008: 0000003b -; CHECK: 0x0000000c: 0000005f -; CHECK: 0x00000010: 00000061 +; CHECK: 0x0000000c: 0000003d + +; Object file checks +; For x86-64-linux we should have this set of relocations for the debug info section +; +; OBJ: .debug_info +; OBJ-NEXT: R_X86_64_32 .debug_abbrev +; OBJ-NEXT: R_X86_64_32 .debug_str +; OBJ-NEXT: R_X86_64_32 .debug_addr +; OBJ-NEXT: R_X86_64_32 .debug_line +; OBJ-NEXT: R_X86_64_32 .debug_str +; OBJ-NEXT: } diff --git a/test/DebugInfo/X86/instcombine-instrinsics.ll b/test/DebugInfo/X86/instcombine-instrinsics.ll new file mode 100644 index 000000000000..446682841552 --- /dev/null +++ b/test/DebugInfo/X86/instcombine-instrinsics.ll @@ -0,0 +1,100 @@ +; RUN: opt < %s -O2 -S | FileCheck %s +; Verify that we emit the same intrinsic at most once. +; CHECK: call void @llvm.dbg.value(metadata !{%struct.i14** %i14} +; CHECK-NOT: call void @llvm.dbg.value(metadata !{%struct.i14** %i14} +; CHECK: ret + +;*** IR Dump After Dead Argument Elimination *** +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +%struct.i3 = type { i32 } +%struct.i14 = type { i32 } +%struct.i24 = type opaque + +define %struct.i3* @barz(i64 %i9) nounwind { +entry: + br label %while.cond + +while.cond: ; preds = %while.body, %entry + br label %while.body + +while.body: ; preds = %while.cond + br label %while.cond +} + +declare void @llvm.dbg.declare(metadata, metadata) + +define void @init() nounwind { +entry: + %i14 = alloca %struct.i14*, align 8 + call void @llvm.dbg.declare(metadata !{%struct.i14** %i14}, metadata !25) + store %struct.i14* null, %struct.i14** %i14, align 8 + %call = call i32 @foo(i8* bitcast (void ()* @bar to i8*), %struct.i14** %i14) + %0 = load %struct.i14** %i14, align 8 + %i16 = getelementptr inbounds %struct.i14* %0, i32 0, i32 0 + %1 = load i32* %i16, align 4 + %or = or i32 %1, 4 + store i32 %or, i32* %i16, align 4 + %call4 = call i32 @foo(i8* bitcast (void ()* @baz to i8*), %struct.i14** %i14) + ret void +} + +declare i32 @foo(i8*, %struct.i14**) nounwind + +define internal void @bar() nounwind { +entry: + %i9 = alloca i64, align 8 + store i64 0, i64* %i9, align 8 + %call = call i32 @put(i64 0, i64* %i9, i64 0, %struct.i24* null) + ret void +} + +define internal void @baz() nounwind { +entry: + ret void +} + +declare i32 @put(i64, i64*, i64, %struct.i24*) nounwind readnone + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !48, metadata !""} ; [ DW_TAG_compile_unit ] +!1 = metadata !{metadata !"i1", metadata !""} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4, metadata !21, metadata !33, metadata !47} +!4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"i2", metadata !"i2", metadata !"", i32 31, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, %struct.i3* (i64)* @barz, null, null, metadata !16, i32 32} ; [ DW_TAG_subprogram ] [line 31] [scope 32] +!5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] +!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = metadata !{metadata !8, metadata !13} +!8 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !9} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from i3] +!9 = metadata !{i32 786451, metadata !1, null, metadata !"i3", i32 25, i64 32, i64 32, i32 0, i32 0, null, metadata !10, i32 0, null, null} ; [ DW_TAG_structure_type ] [line 25, size 32, align 32, offset 0] [from ] +!10 = metadata !{metadata !11} +!11 = metadata !{i32 786445, metadata !1, metadata !9, metadata !"i4", i32 26, i64 32, i64 32, i64 0, i32 0, metadata !12} ; [ DW_TAG_member ] [line 26, size 32, align 32, offset 0] [from i5] +!12 = metadata !{i32 786468, null, null, metadata !"i5", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [line 0, size 32, align 32, offset 0, enc DW_ATE_unsigned] +!13 = metadata !{i32 786454, metadata !1, null, metadata !"i6", i32 5, i64 0, i64 0, i64 0, i32 0, metadata !14} ; [ DW_TAG_typedef ] [line 5, size 0, align 0, offset 0] [from i7] +!14 = metadata !{i32 786454, metadata !1, null, metadata !"i7", i32 2, i64 0, i64 0, i64 0, i32 0, metadata !15} ; [ DW_TAG_typedef ] [line 2, size 0, align 0, offset 0] [from i8] +!15 = metadata !{i32 786468, null, null, metadata !"i8", i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned] +!16 = metadata !{} +!21 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"i13", metadata !"i13", metadata !"", i32 42, metadata !22, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @init, null, null, metadata !24, i32 43} ; [ DW_TAG_subprogram ] [line 42] [scope 43] +!22 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !23, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!23 = metadata !{null} +!24 = metadata !{metadata !25} +!25 = metadata !{i32 786688, metadata !21, metadata !"i14", metadata !5, i32 45, metadata !27, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [line 45] +!27 = metadata !{i32 786447, null, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 0, metadata !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from i14] +!28 = metadata !{i32 786451, metadata !1, null, metadata !"i14", i32 16, i64 32, i64 32, i32 0, i32 0, null, metadata !29, i32 0, null, null} ; [ DW_TAG_structure_type ] [line 16, size 32, align 32, offset 0] [from ] +!29 = metadata !{metadata !30} +!30 = metadata !{i32 786445, metadata !1, metadata !28, metadata !"i16", i32 17, i64 32, i64 32, i64 0, i32 0, metadata !31} ; [ DW_TAG_member ] [line 17, size 32, align 32, offset 0] [from i17] +!31 = metadata !{i32 786454, metadata !1, null, metadata !"i17", i32 7, i64 0, i64 0, i64 0, i32 0, metadata !32} ; [ DW_TAG_typedef ] [line 7, size 0, align 0, offset 0] [from int] +!32 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!33 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"i18", metadata !"i18", metadata !"", i32 54, metadata !22, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @bar, null, null, metadata !34, i32 55} ; [ DW_TAG_subprogram ] [line 54] [scope 55] +!34 = metadata !{null} +!47 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"i29", metadata !"i29", metadata !"", i32 53, metadata !22, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @baz, null, null, metadata !2, i32 53} ; [ DW_TAG_subprogram ] [line 53] +!48 = metadata !{metadata !49} +!49 = metadata !{i32 786484, i32 0, metadata !21, metadata !"i30", metadata !"i30", metadata !"", metadata !5, i32 44, metadata !50, i32 1, i32 1, null, null} +!50 = metadata !{i32 786454, metadata !1, null, metadata !"i31", i32 6, i64 0, i64 0, i64 0, i32 0, metadata !32} ; [ DW_TAG_typedef ] [line 6, size 0, align 0, offset 0] [from int] +!52 = metadata !{i64 0} +!55 = metadata !{%struct.i3* null} +!72 = metadata !{%struct.i24* null} diff --git a/test/DebugInfo/X86/line-info.ll b/test/DebugInfo/X86/line-info.ll index 0c0a7ab51d4b..fd813b312162 100644 --- a/test/DebugInfo/X86/line-info.ll +++ b/test/DebugInfo/X86/line-info.ll @@ -37,7 +37,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/list0.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/scratch/list0.c] [DW_LANG_C99] !1 = metadata !{metadata !"list0.c", metadata !"/usr/local/google/home/blaikie/dev/scratch"} !2 = metadata !{i32 0} !3 = metadata !{metadata !4, metadata !10} diff --git a/test/DebugInfo/X86/linkage-name.ll b/test/DebugInfo/X86/linkage-name.ll index 9440f3a994e1..c9bd2cfb5e8e 100644 --- a/test/DebugInfo/X86/linkage-name.ll +++ b/test/DebugInfo/X86/linkage-name.ll @@ -26,7 +26,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 152691) (llvm/trunk 152692)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 152691) (llvm/trunk 152692)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !18, metadata !18, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, null, metadata !"a", metadata !"a", metadata !"_ZN1A1aEi", i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (%class.A*, i32)* @_ZN1A1aEi, null, metadata !13, metadata !16, i32 5} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/low-pc-cu.ll b/test/DebugInfo/X86/low-pc-cu.ll index 4dd5aafe18ea..77f69b961753 100644 --- a/test/DebugInfo/X86/low-pc-cu.ll +++ b/test/DebugInfo/X86/low-pc-cu.ll @@ -14,7 +14,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 153454) (llvm/trunk 153471)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.1 (trunk 153454) (llvm/trunk 153471)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !12} !5 = metadata !{i32 786478, metadata !"_Z1qv", i32 0, metadata !6, metadata !"q", metadata !"q", metadata !6, i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z1qv, null, null, metadata !10} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/misched-dbg-value.ll b/test/DebugInfo/X86/misched-dbg-value.ll index 0980e23b7517..4b78c8812e93 100644 --- a/test/DebugInfo/X86/misched-dbg-value.ll +++ b/test/DebugInfo/X86/misched-dbg-value.ll @@ -43,15 +43,15 @@ entry: tail call void @llvm.dbg.value(metadata !{i32 %add}, i64 0, metadata !27), !dbg !68 %idxprom = sext i32 %add to i64, !dbg !69 %arrayidx = getelementptr inbounds i32* %Array1Par, i64 %idxprom, !dbg !69 - store i32 %IntParI2, i32* %arrayidx, align 4, !dbg !69, !tbaa !70 + store i32 %IntParI2, i32* %arrayidx, align 4, !dbg !69 %add3 = add nsw i32 %IntParI1, 6, !dbg !73 %idxprom4 = sext i32 %add3 to i64, !dbg !73 %arrayidx5 = getelementptr inbounds i32* %Array1Par, i64 %idxprom4, !dbg !73 - store i32 %IntParI2, i32* %arrayidx5, align 4, !dbg !73, !tbaa !70 + store i32 %IntParI2, i32* %arrayidx5, align 4, !dbg !73 %add6 = add nsw i32 %IntParI1, 35, !dbg !74 %idxprom7 = sext i32 %add6 to i64, !dbg !74 %arrayidx8 = getelementptr inbounds i32* %Array1Par, i64 %idxprom7, !dbg !74 - store i32 %add, i32* %arrayidx8, align 4, !dbg !74, !tbaa !70 + store i32 %add, i32* %arrayidx8, align 4, !dbg !74 tail call void @llvm.dbg.value(metadata !{i32 %add}, i64 0, metadata !28), !dbg !75 br label %for.body, !dbg !75 @@ -59,7 +59,7 @@ for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %idxprom, %entry ], [ %indvars.iv.next, %for.body ] %IntIndex.046 = phi i32 [ %add, %entry ], [ %inc, %for.body ] %arrayidx13 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom, i64 %indvars.iv, !dbg !77 - store i32 %add, i32* %arrayidx13, align 4, !dbg !77, !tbaa !70 + store i32 %add, i32* %arrayidx13, align 4, !dbg !77 %inc = add nsw i32 %IntIndex.046, 1, !dbg !75 tail call void @llvm.dbg.value(metadata !{i32 %inc}, i64 0, metadata !28), !dbg !75 %cmp = icmp sgt i32 %inc, %add3, !dbg !75 @@ -70,15 +70,15 @@ for.end: ; preds = %for.body %sub = add nsw i32 %IntParI1, 4, !dbg !78 %idxprom14 = sext i32 %sub to i64, !dbg !78 %arrayidx17 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom, i64 %idxprom14, !dbg !78 - %0 = load i32* %arrayidx17, align 4, !dbg !78, !tbaa !70 + %0 = load i32* %arrayidx17, align 4, !dbg !78 %inc18 = add nsw i32 %0, 1, !dbg !78 - store i32 %inc18, i32* %arrayidx17, align 4, !dbg !78, !tbaa !70 - %1 = load i32* %arrayidx, align 4, !dbg !79, !tbaa !70 + store i32 %inc18, i32* %arrayidx17, align 4, !dbg !78 + %1 = load i32* %arrayidx, align 4, !dbg !79 %add22 = add nsw i32 %IntParI1, 25, !dbg !79 %idxprom23 = sext i32 %add22 to i64, !dbg !79 %arrayidx25 = getelementptr inbounds [51 x i32]* %Array2Par, i64 %idxprom23, i64 %idxprom, !dbg !79 - store i32 %1, i32* %arrayidx25, align 4, !dbg !79, !tbaa !70 - store i32 5, i32* @IntGlob, align 4, !dbg !80, !tbaa !70 + store i32 %1, i32* %arrayidx25, align 4, !dbg !79 + store i32 5, i32* @IntGlob, align 4, !dbg !80 ret void, !dbg !81 } @@ -89,7 +89,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !3, metadata !"clang version 3.3 (trunk 175015)", i1 true, metadata !"", i32 0, metadata !1, metadata !10, metadata !11, metadata !29, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, i32 12, metadata !3, metadata !"clang version 3.3 (trunk 175015)", i1 true, metadata !"", i32 0, metadata !1, metadata !10, metadata !11, metadata !29, metadata !29, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/manmanren/test-Nov/rdar_13183203/test2/dry.c] [DW_LANG_C99] !1 = metadata !{metadata !2} !2 = metadata !{i32 786436, metadata !82, null, metadata !"", i32 128, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] [line 128, size 32, align 32, offset 0] [from ] !3 = metadata !{i32 786473, metadata !82} ; [ DW_TAG_file_type ] @@ -159,9 +159,6 @@ attributes #1 = { nounwind readnone } !67 = metadata !{i32 184, i32 0, metadata !12, null} !68 = metadata !{i32 189, i32 0, metadata !12, null} !69 = metadata !{i32 190, i32 0, metadata !12, null} -!70 = metadata !{metadata !"int", metadata !71} -!71 = metadata !{metadata !"omnipotent char", metadata !72} -!72 = metadata !{metadata !"Simple C/C++ TBAA"} !73 = metadata !{i32 191, i32 0, metadata !12, null} !74 = metadata !{i32 192, i32 0, metadata !12, null} !75 = metadata !{i32 193, i32 0, metadata !76, null} diff --git a/test/DebugInfo/X86/multiple-at-const-val.ll b/test/DebugInfo/X86/multiple-at-const-val.ll index f6ca10bcc4ca..7779d1efe917 100644 --- a/test/DebugInfo/X86/multiple-at-const-val.ll +++ b/test/DebugInfo/X86/multiple-at-const-val.ll @@ -31,7 +31,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !961, metadata !"clang version 3.3 (trunk 174207)", i1 true, metadata !"", i32 0, metadata !1, metadata !955, metadata !956, metadata !1786, metadata !""} ; [ DW_TAG_compile_unit ] [/privite/tmp/student2.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !961, metadata !"clang version 3.3 (trunk 174207)", i1 true, metadata !"", i32 0, metadata !1, metadata !955, metadata !956, metadata !1786, metadata !1786, metadata !""} ; [ DW_TAG_compile_unit ] [/privite/tmp/student2.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{metadata !26} !4 = metadata !{i32 786489, null, metadata !"std", metadata !5, i32 48} ; [ DW_TAG_namespace ] !5 = metadata !{i32 786473, metadata !1801} ; [ DW_TAG_file_type ] diff --git a/test/DebugInfo/X86/nondefault-subrange-array.ll b/test/DebugInfo/X86/nondefault-subrange-array.ll index 33a6f8ba9e50..a5f786c26b26 100644 --- a/test/DebugInfo/X86/nondefault-subrange-array.ll +++ b/test/DebugInfo/X86/nondefault-subrange-array.ll @@ -27,7 +27,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, metadata !20, i32 4, metadata !"clang version 3.3 (trunk 169136)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Volumes/Sandbox/llvm/t.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, %class.A* @a, null} ; [ DW_TAG_variable ] [a] [line 1] [def] diff --git a/test/DebugInfo/X86/objc-fwd-decl.ll b/test/DebugInfo/X86/objc-fwd-decl.ll index 1847d2c10fdf..3070ff88b3b9 100644 --- a/test/DebugInfo/X86/objc-fwd-decl.ll +++ b/test/DebugInfo/X86/objc-fwd-decl.ll @@ -12,7 +12,7 @@ !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!9, !10, !11, !12} -!0 = metadata !{i32 786449, metadata !13, i32 16, metadata !"clang version 3.1 (trunk 152054 trunk 152094)", i1 false, metadata !"", i32 2, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !13, i32 16, metadata !"clang version 3.1 (trunk 152054 trunk 152094)", i1 false, metadata !"", i32 2, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 3, metadata !7, i32 0, i32 1, %0** @a, null} ; [ DW_TAG_variable ] diff --git a/test/DebugInfo/X86/op_deref.ll b/test/DebugInfo/X86/op_deref.ll index 3bb93e7251b8..c3580a790c17 100644 --- a/test/DebugInfo/X86/op_deref.ll +++ b/test/DebugInfo/X86/op_deref.ll @@ -59,7 +59,7 @@ declare void @llvm.stackrestore(i8*) nounwind !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !28, i32 12, metadata !"clang version 3.2 (trunk 156005) (llvm/trunk 156000)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !28, i32 12, metadata !"clang version 3.2 (trunk 156005) (llvm/trunk 156000)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"testVLAwithSize", metadata !"testVLAwithSize", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32)* @testVLAwithSize, null, null, metadata !1, i32 2} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/pointer-type-size.ll b/test/DebugInfo/X86/pointer-type-size.ll index aa560587a602..b06535325368 100644 --- a/test/DebugInfo/X86/pointer-type-size.ll +++ b/test/DebugInfo/X86/pointer-type-size.ll @@ -10,7 +10,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 147882)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 147882)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 720948, i32 0, null, metadata !"crass", metadata !"crass", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, %struct.crass* @crass, null} ; [ DW_TAG_variable ] diff --git a/test/DebugInfo/X86/pr11300.ll b/test/DebugInfo/X86/pr11300.ll index 61df4ad0baa6..54e0c8b6270c 100644 --- a/test/DebugInfo/X86/pr11300.ll +++ b/test/DebugInfo/X86/pr11300.ll @@ -31,7 +31,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !32, i32 4, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !32, i32 4, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !20} !5 = metadata !{i32 720942, metadata !6, metadata !6, metadata !"zed", metadata !"zed", metadata !"_Z3zedP3foo", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%struct.foo*)* @_Z3zedP3foo, null, null, metadata !18, i32 4} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/pr13303.ll b/test/DebugInfo/X86/pr13303.ll index 34956237ae0b..63ddfa7a7455 100644 --- a/test/DebugInfo/X86/pr13303.ll +++ b/test/DebugInfo/X86/pr13303.ll @@ -14,7 +14,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 160143)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/PR13303.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 160143)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/probinson/PR13303.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @main, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [main] diff --git a/test/DebugInfo/X86/prologue-stack.ll b/test/DebugInfo/X86/prologue-stack.ll index 6e4917747c14..00ee7a03f46b 100644 --- a/test/DebugInfo/X86/prologue-stack.ll +++ b/test/DebugInfo/X86/prologue-stack.ll @@ -20,7 +20,7 @@ declare i32 @callme(i32) !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"isel_line_test2", metadata !"isel_line_test2", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @isel_line_test2, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2] diff --git a/test/DebugInfo/X86/rvalue-ref.ll b/test/DebugInfo/X86/rvalue-ref.ll index ae2e3d4578c5..b5aa4f6432d8 100644 --- a/test/DebugInfo/X86/rvalue-ref.ll +++ b/test/DebugInfo/X86/rvalue-ref.ll @@ -22,7 +22,7 @@ declare i32 @printf(i8*, ...) !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 157054) (llvm/trunk 157060)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 157054) (llvm/trunk 157060)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"_Z3fooOi", metadata !6, i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i32*)* @_Z3fooOi, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll index 39a026c35494..620478a879a3 100644 --- a/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll +++ b/test/DebugInfo/X86/stmt-list-multiple-compile-units.ll @@ -1,5 +1,6 @@ ; RUN: llc -O0 %s -mtriple=x86_64-apple-darwin -filetype=obj -o %t ; RUN: llvm-dwarfdump %t | FileCheck %s +; RUN: llc < %s -O0 -mtriple=x86_64-apple-macosx10.7 | FileCheck %s -check-prefix=ASM ; rdar://13067005 ; CHECK: .debug_info contents: @@ -20,6 +21,11 @@ ; CHECK: file_names[ 1] 0 0x00000000 0x00000000 simple2.c ; CHECK-NOT: file_names +; PR15408 +; ASM: L__DWARF__debug_info_begin0: +; ASM: .long 0 ## DW_AT_stmt_list +; ASM: L__DWARF__debug_info_begin1: +; ASM: .long 0 ## DW_AT_stmt_list define i32 @test(i32 %a) nounwind uwtable ssp { entry: %a.addr = alloca i32, align 4 @@ -42,7 +48,7 @@ entry: } !llvm.dbg.cu = !{!0, !10} -!0 = metadata !{i32 786449, metadata !23, i32 12, metadata !"clang version 3.3", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !23, i32 12, metadata !"clang version 3.3", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{metadata !2} !2 = metadata !{i32 0} !3 = metadata !{metadata !5} @@ -51,7 +57,7 @@ entry: !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !8 = metadata !{metadata !9, metadata !9} !9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!10 = metadata !{i32 786449, metadata !24, i32 12, metadata !"clang version 3.3 (trunk 172862)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !11, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!10 = metadata !{i32 786449, metadata !24, i32 12, metadata !"clang version 3.3 (trunk 172862)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !11, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !11 = metadata !{metadata !13} !13 = metadata !{i32 786478, metadata !24, metadata !"fn", metadata !"fn", metadata !"", metadata !14, i32 1, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @fn, null, null, metadata !1, i32 1} ; [ DW_TAG_subprogram ] [line 1] [def] [fn] !14 = metadata !{i32 786473, metadata !24} ; [ DW_TAG_file_type ] diff --git a/test/DebugInfo/X86/stringpool.ll b/test/DebugInfo/X86/stringpool.ll index 8df281d08ea6..d9604de0f62f 100644 --- a/test/DebugInfo/X86/stringpool.ll +++ b/test/DebugInfo/X86/stringpool.ll @@ -5,7 +5,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.1 (trunk 143009)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !8, i32 12, metadata !"clang version 3.1 (trunk 143009)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 720948, i32 0, null, metadata !"yyyy", metadata !"yyyy", metadata !"", metadata !6, i32 1, metadata !7, i32 0, i32 1, i32* @yyyy, null} ; [ DW_TAG_variable ] diff --git a/test/DebugInfo/X86/struct-loc.ll b/test/DebugInfo/X86/struct-loc.ll index bdf104f07e39..76cb1f70634b 100644 --- a/test/DebugInfo/X86/struct-loc.ll +++ b/test/DebugInfo/X86/struct-loc.ll @@ -13,7 +13,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 152837) (llvm/trunk 152845)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.1 (trunk 152837) (llvm/trunk 152845)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"f", metadata !"f", metadata !"", metadata !6, i32 5, metadata !7, i32 0, i32 1, %struct.foo* @f, null} ; [ DW_TAG_variable ] diff --git a/test/DebugInfo/X86/subrange-type.ll b/test/DebugInfo/X86/subrange-type.ll index efc5bf0417f1..da9589338439 100644 --- a/test/DebugInfo/X86/subrange-type.ll +++ b/test/DebugInfo/X86/subrange-type.ll @@ -20,7 +20,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !17, i32 12, metadata !"clang version 3.3 (trunk 171472) (llvm/trunk 171487)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, metadata !17, i32 12, metadata !"clang version 3.3 (trunk 171472) (llvm/trunk 171487)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !6, metadata !"main", metadata !"main", metadata !"", i32 2, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @main, null, null, metadata !1, i32 3} ; [ DW_TAG_subprogram ] [line 2] [def] [scope 3] [main] diff --git a/test/DebugInfo/X86/subreg.ll b/test/DebugInfo/X86/subreg.ll index 027589b3d995..c7f86381204c 100644 --- a/test/DebugInfo/X86/subreg.ll +++ b/test/DebugInfo/X86/subreg.ll @@ -22,7 +22,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !0 = metadata !{i32 786689, metadata !1, metadata !"zzz", metadata !2, i32 16777219, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 786478, metadata !2, metadata !"f", metadata !"f", metadata !"", metadata !2, i32 3, metadata !4, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i16 (i16)* @f, null, null, null, i32 3} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 786473, metadata !"/home/espindola/llvm/test.c", metadata !"/home/espindola/tmpfs/build", metadata !3} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, null, null, metadata !9, null, metadata !""} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 786449, i32 12, metadata !2, metadata !"clang version 3.0 ()", i1 false, metadata !"", i32 0, null, null, metadata !9, null, null, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{i32 786453, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !5, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !5 = metadata !{null} !6 = metadata !{i32 786468, metadata !3, metadata !"short", null, i32 0, i64 16, i64 16, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/X86/union-template.ll b/test/DebugInfo/X86/union-template.ll index 0f5538e8b40e..8d23caec9686 100644 --- a/test/DebugInfo/X86/union-template.ll +++ b/test/DebugInfo/X86/union-template.ll @@ -28,7 +28,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.3 (trunk 178499) (llvm/trunk 178472)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !9, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.cc] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.3 (trunk 178499) (llvm/trunk 178472)", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !9, metadata !9, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/foo.cc] [DW_LANG_C_plus_plus] !1 = metadata !{metadata !"foo.cc", metadata !"/usr/local/google/home/echristo/tmp"} !2 = metadata !{i32 0} !3 = metadata !{metadata !4} diff --git a/test/DebugInfo/X86/vector.ll b/test/DebugInfo/X86/vector.ll index 570adf9e4329..658303a57fd6 100644 --- a/test/DebugInfo/X86/vector.ll +++ b/test/DebugInfo/X86/vector.ll @@ -11,7 +11,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.3 (trunk 171825) (llvm/trunk 171822)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/foo.c] [DW_LANG_C99] +!0 = metadata !{i32 786449, i32 12, metadata !6, metadata !"clang version 3.3 (trunk 171825) (llvm/trunk 171822)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/Users/echristo/foo.c] [DW_LANG_C99] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786484, i32 0, null, metadata !"a", metadata !"a", metadata !"", metadata !6, i32 3, metadata !7, i32 0, i32 1, <4 x i32>* @a, null} ; [ DW_TAG_variable ] [a] [line 3] [def] diff --git a/test/DebugInfo/array.ll b/test/DebugInfo/array.ll index 30771104912f..7dd57d7db21d 100644 --- a/test/DebugInfo/array.ll +++ b/test/DebugInfo/array.ll @@ -16,7 +16,7 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone !0 = metadata !{i32 786478, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null, null, i32 3} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !14} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.0 (trunk 129138)", i1 false, metadata !"", i32 0, null, null, metadata !13, null, null} ; [ DW_TAG_compile_unit ] +!2 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.0 (trunk 129138)", i1 false, metadata !"", i32 0, null, null, metadata !13, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] diff --git a/test/DebugInfo/dwarf-public-names.ll b/test/DebugInfo/dwarf-public-names.ll index 52b2397714e3..5d330486d88c 100644 --- a/test/DebugInfo/dwarf-public-names.ll +++ b/test/DebugInfo/dwarf-public-names.ll @@ -1,6 +1,7 @@ +; REQUIRES: object-emission + ; RUN: llc -generate-dwarf-pubnames -filetype=obj -o %t.o < %s ; RUN: llvm-dwarfdump -debug-dump=pubnames %t.o | FileCheck %s -; XFAIL: hexagon ; ModuleID = 'dwarf-public-names.cpp' ; ; Generated from: @@ -85,7 +86,7 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !4, metadata !"clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !24, metadata !""} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !4, metadata !"clang version 3.3 (http://llvm.org/git/clang.git a09cd8103a6a719cb2628cdf0c91682250a17bd2) (http://llvm.org/git/llvm.git 47d03cec0afca0c01ae42b82916d1d731716cd20)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !2, metadata !24, metadata !24, metadata !""} ; [ DW_TAG_compile_unit ] [/usr2/kparzysz/s.hex/t/dwarf-public-names.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !2 = metadata !{metadata !3, metadata !18, metadata !19, metadata !20} !3 = metadata !{i32 786478, metadata !4, null, metadata !"member_function", metadata !"member_function", metadata !"_ZN1C15member_functionEv", i32 9, metadata !5, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (%struct.C*)* @_ZN1C15member_functionEv, null, metadata !12, metadata !1, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [member_function] diff --git a/test/DebugInfo/dwarfdump-zlib.test b/test/DebugInfo/dwarfdump-zlib.test new file mode 100644 index 000000000000..8ce2cf7690d0 --- /dev/null +++ b/test/DebugInfo/dwarfdump-zlib.test @@ -0,0 +1,12 @@ +REQUIRES: zlib + +RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-zlib.elf-x86-64 \ +RUN: | FileCheck %s -check-prefix FULLDUMP +RUN: llvm-dwarfdump %p/Inputs/dwarfdump-test-zlib.elf-x86-64 \ +RUN: --address=0x400559 --functions | FileCheck %s -check-prefix MAIN + +FULLDUMP: .debug_abbrev contents +FULLDUMP: .debug_info contents + +MAIN: main +MAIN-NEXT: /tmp/dbginfo{{[/\\]}}dwarfdump-test-zlib.cc:16 diff --git a/test/DebugInfo/inline-debug-info-multiret.ll b/test/DebugInfo/inline-debug-info-multiret.ll new file mode 100644 index 000000000000..108f212a255f --- /dev/null +++ b/test/DebugInfo/inline-debug-info-multiret.ll @@ -0,0 +1,154 @@ +; RUN: opt -inline -S < %s | FileCheck %s +; +; A hand-edited version of inline-debug-info.ll to test inlining of a +; function with multiple returns. +; +; Make sure the branch instructions created during inlining has a debug location, +; so the range of the inlined function is correct. +; CHECK: br label %_Z4testi.exit, !dbg ![[MD:[0-9]+]] +; CHECK: br label %_Z4testi.exit, !dbg ![[MD]] +; CHECK: br label %invoke.cont, !dbg ![[MD]] +; The branch instruction has the source location of line 9 and its inlined location +; has the source location of line 14. +; CHECK: ![[INL:[0-9]+]] = metadata !{i32 14, i32 0, metadata {{.*}}, null} +; CHECK: ![[MD]] = metadata !{i32 9, i32 0, metadata {{.*}}, metadata ![[INL]]} + +; ModuleID = 'test.cpp' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin12.0.0" + +@_ZTIi = external constant i8* +@global_var = external global i32 + +; copy of above function with multiple returns +define i32 @_Z4testi(i32 %k) { +entry: + %retval = alloca i32, align 4 + %k.addr = alloca i32, align 4 + %k2 = alloca i32, align 4 + store i32 %k, i32* %k.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %k.addr}, metadata !13), !dbg !14 + call void @llvm.dbg.declare(metadata !{i32* %k2}, metadata !15), !dbg !16 + %0 = load i32* %k.addr, align 4, !dbg !16 + %call = call i32 @_Z8test_exti(i32 %0), !dbg !16 + store i32 %call, i32* %k2, align 4, !dbg !16 + %1 = load i32* %k2, align 4, !dbg !17 + %cmp = icmp sgt i32 %1, 100, !dbg !17 + br i1 %cmp, label %if.then, label %if.end, !dbg !17 + +if.then: ; preds = %entry + %2 = load i32* %k2, align 4, !dbg !18 + store i32 %2, i32* %retval, !dbg !18 + br label %return, !dbg !18 + +if.end: ; preds = %entry + store i32 0, i32* %retval, !dbg !19 + %3 = load i32* %retval, !dbg !20 ; hand-edited + ret i32 %3, !dbg !20 ; hand-edited + +return: ; preds = %if.end, %if.then + %4 = load i32* %retval, !dbg !20 + ret i32 %4, !dbg !20 +} + + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata) #1 + +declare i32 @_Z8test_exti(i32) + +define i32 @_Z5test2v() { +entry: + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %e = alloca i32, align 4 + %0 = load i32* @global_var, align 4, !dbg !21 + %call = invoke i32 @_Z4testi(i32 %0) + to label %invoke.cont unwind label %lpad, !dbg !21 + +invoke.cont: ; preds = %entry + br label %try.cont, !dbg !23 + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*), !dbg !21 + %2 = extractvalue { i8*, i32 } %1, 0, !dbg !21 + store i8* %2, i8** %exn.slot, !dbg !21 + %3 = extractvalue { i8*, i32 } %1, 1, !dbg !21 + store i32 %3, i32* %ehselector.slot, !dbg !21 + br label %catch.dispatch, !dbg !21 + +catch.dispatch: ; preds = %lpad + %sel = load i32* %ehselector.slot, !dbg !23 + %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2, !dbg !23 + %matches = icmp eq i32 %sel, %4, !dbg !23 + br i1 %matches, label %catch, label %eh.resume, !dbg !23 + +catch: ; preds = %catch.dispatch + call void @llvm.dbg.declare(metadata !{i32* %e}, metadata !24), !dbg !25 + %exn = load i8** %exn.slot, !dbg !23 + %5 = call i8* @__cxa_begin_catch(i8* %exn) #2, !dbg !23 + %6 = bitcast i8* %5 to i32*, !dbg !23 + %7 = load i32* %6, align 4, !dbg !23 + store i32 %7, i32* %e, align 4, !dbg !23 + store i32 0, i32* @global_var, align 4, !dbg !26 + call void @__cxa_end_catch() #2, !dbg !28 + br label %try.cont, !dbg !28 + +try.cont: ; preds = %catch, %invoke.cont + store i32 1, i32* @global_var, align 4, !dbg !29 + ret i32 0, !dbg !30 + +eh.resume: ; preds = %catch.dispatch + %exn1 = load i8** %exn.slot, !dbg !23 + %sel2 = load i32* %ehselector.slot, !dbg !23 + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn1, 0, !dbg !23 + %lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel2, 1, !dbg !23 + resume { i8*, i32 } %lpad.val3, !dbg !23 +} + +declare i32 @__gxx_personality_v0(...) + +; Function Attrs: nounwind readnone +declare i32 @llvm.eh.typeid.for(i8*) #1 + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"<unknown>", metadata !""} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4, metadata !10} +!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"test", metadata !"test", metadata !"_Z4testi", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @_Z4testi, null, null, metadata !2, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [test] +!5 = metadata !{metadata !"test.cpp", metadata !""} +!6 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [test.cpp] +!7 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{metadata !9, metadata !9} +!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"test2", metadata !"test2", metadata !"_Z5test2v", i32 11, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z5test2v, null, null, metadata !2, i32 11} ; [ DW_TAG_subprogram ] [line 11] [def] [test2] +!11 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = metadata !{metadata !9} +!13 = metadata !{i32 786689, metadata !4, metadata !"k", metadata !6, i32 16777220, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [k] [line 4] +!14 = metadata !{i32 4, i32 0, metadata !4, null} +!15 = metadata !{i32 786688, metadata !4, metadata !"k2", metadata !6, i32 5, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k2] [line 5] +!16 = metadata !{i32 5, i32 0, metadata !4, null} +!17 = metadata !{i32 6, i32 0, metadata !4, null} +!18 = metadata !{i32 7, i32 0, metadata !4, null} +!19 = metadata !{i32 8, i32 0, metadata !4, null} +!20 = metadata !{i32 9, i32 0, metadata !4, null} +!21 = metadata !{i32 14, i32 0, metadata !22, null} +!22 = metadata !{i32 786443, metadata !5, metadata !10, i32 13, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [test.cpp] +!23 = metadata !{i32 15, i32 0, metadata !22, null} +!24 = metadata !{i32 786688, metadata !10, metadata !"e", metadata !6, i32 16, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [e] [line 16] +!25 = metadata !{i32 16, i32 0, metadata !10, null} +!26 = metadata !{i32 17, i32 0, metadata !27, null} +!27 = metadata !{i32 786443, metadata !5, metadata !10, i32 16, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [test.cpp] +!28 = metadata !{i32 18, i32 0, metadata !27, null} +!29 = metadata !{i32 19, i32 0, metadata !10, null} +!30 = metadata !{i32 20, i32 0, metadata !10, null} diff --git a/test/DebugInfo/inline-debug-info.ll b/test/DebugInfo/inline-debug-info.ll new file mode 100644 index 000000000000..7c3267abcee3 --- /dev/null +++ b/test/DebugInfo/inline-debug-info.ll @@ -0,0 +1,172 @@ +; RUN: opt -inline -S < %s | FileCheck %s + +; Created from source +; +; +; 1 // test.cpp +; 2 extern int global_var; +; 3 extern int test_ext(int k); +; 4 int test (int k) { +; 5 int k2 = test_ext(k); +; 6 if (k2 > 100) +; 7 return k2; +; 8 return 0; +; 9 } +; 10 +; 11 int test2() { +; 12 try +; 13 { +; 14 test(global_var); +; 15 } +; 16 catch (int e) { +; 17 global_var = 0; +; 18 } +; 19 global_var = 1; +; 20 return 0; +; 21 } + +; CHECK: _Z4testi.exit: +; Make sure the branch instruction created during inlining has a debug location, +; so the range of the inlined function is correct. +; CHECK: br label %invoke.cont, !dbg ![[MD:[0-9]+]] +; The branch instruction has the source location of line 9 and its inlined location +; has the source location of line 14. +; CHECK: ![[INL:[0-9]+]] = metadata !{i32 14, i32 0, metadata {{.*}}, null} +; CHECK: ![[MD]] = metadata !{i32 9, i32 0, metadata {{.*}}, metadata ![[INL]]} + +; ModuleID = 'test.cpp' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-darwin12.0.0" + +@_ZTIi = external constant i8* +@global_var = external global i32 + +define i32 @_Z4testi(i32 %k) { +entry: + %retval = alloca i32, align 4 + %k.addr = alloca i32, align 4 + %k2 = alloca i32, align 4 + store i32 %k, i32* %k.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %k.addr}, metadata !13), !dbg !14 + call void @llvm.dbg.declare(metadata !{i32* %k2}, metadata !15), !dbg !16 + %0 = load i32* %k.addr, align 4, !dbg !16 + %call = call i32 @_Z8test_exti(i32 %0), !dbg !16 + store i32 %call, i32* %k2, align 4, !dbg !16 + %1 = load i32* %k2, align 4, !dbg !17 + %cmp = icmp sgt i32 %1, 100, !dbg !17 + br i1 %cmp, label %if.then, label %if.end, !dbg !17 + +if.then: ; preds = %entry + %2 = load i32* %k2, align 4, !dbg !18 + store i32 %2, i32* %retval, !dbg !18 + br label %return, !dbg !18 + +if.end: ; preds = %entry + store i32 0, i32* %retval, !dbg !19 + br label %return, !dbg !19 + +return: ; preds = %if.end, %if.then + %3 = load i32* %retval, !dbg !20 + ret i32 %3, !dbg !20 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata) #1 + +declare i32 @_Z8test_exti(i32) + +define i32 @_Z5test2v() { +entry: + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + %e = alloca i32, align 4 + %0 = load i32* @global_var, align 4, !dbg !21 + %call = invoke i32 @_Z4testi(i32 %0) + to label %invoke.cont unwind label %lpad, !dbg !21 + +invoke.cont: ; preds = %entry + br label %try.cont, !dbg !23 + +lpad: ; preds = %entry + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*), !dbg !21 + %2 = extractvalue { i8*, i32 } %1, 0, !dbg !21 + store i8* %2, i8** %exn.slot, !dbg !21 + %3 = extractvalue { i8*, i32 } %1, 1, !dbg !21 + store i32 %3, i32* %ehselector.slot, !dbg !21 + br label %catch.dispatch, !dbg !21 + +catch.dispatch: ; preds = %lpad + %sel = load i32* %ehselector.slot, !dbg !23 + %4 = call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTIi to i8*)) #2, !dbg !23 + %matches = icmp eq i32 %sel, %4, !dbg !23 + br i1 %matches, label %catch, label %eh.resume, !dbg !23 + +catch: ; preds = %catch.dispatch + call void @llvm.dbg.declare(metadata !{i32* %e}, metadata !24), !dbg !25 + %exn = load i8** %exn.slot, !dbg !23 + %5 = call i8* @__cxa_begin_catch(i8* %exn) #2, !dbg !23 + %6 = bitcast i8* %5 to i32*, !dbg !23 + %7 = load i32* %6, align 4, !dbg !23 + store i32 %7, i32* %e, align 4, !dbg !23 + store i32 0, i32* @global_var, align 4, !dbg !26 + call void @__cxa_end_catch() #2, !dbg !28 + br label %try.cont, !dbg !28 + +try.cont: ; preds = %catch, %invoke.cont + store i32 1, i32* @global_var, align 4, !dbg !29 + ret i32 0, !dbg !30 + +eh.resume: ; preds = %catch.dispatch + %exn1 = load i8** %exn.slot, !dbg !23 + %sel2 = load i32* %ehselector.slot, !dbg !23 + %lpad.val = insertvalue { i8*, i32 } undef, i8* %exn1, 0, !dbg !23 + %lpad.val3 = insertvalue { i8*, i32 } %lpad.val, i32 %sel2, 1, !dbg !23 + resume { i8*, i32 } %lpad.val3, !dbg !23 +} + +declare i32 @__gxx_personality_v0(...) + +; Function Attrs: nounwind readnone +declare i32 @llvm.eh.typeid.for(i8*) #1 + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [<unknown>] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"<unknown>", metadata !""} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4, metadata !10} +!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"test", metadata !"test", metadata !"_Z4testi", i32 4, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i32)* @_Z4testi, null, null, metadata !2, i32 4} ; [ DW_TAG_subprogram ] [line 4] [def] [test] +!5 = metadata !{metadata !"test.cpp", metadata !""} +!6 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [test.cpp] +!7 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{metadata !9, metadata !9} +!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"test2", metadata !"test2", metadata !"_Z5test2v", i32 11, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 ()* @_Z5test2v, null, null, metadata !2, i32 11} ; [ DW_TAG_subprogram ] [line 11] [def] [test2] +!11 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!12 = metadata !{metadata !9} +!13 = metadata !{i32 786689, metadata !4, metadata !"k", metadata !6, i32 16777220, metadata !9, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [k] [line 4] +!14 = metadata !{i32 4, i32 0, metadata !4, null} +!15 = metadata !{i32 786688, metadata !4, metadata !"k2", metadata !6, i32 5, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [k2] [line 5] +!16 = metadata !{i32 5, i32 0, metadata !4, null} +!17 = metadata !{i32 6, i32 0, metadata !4, null} +!18 = metadata !{i32 7, i32 0, metadata !4, null} +!19 = metadata !{i32 8, i32 0, metadata !4, null} +!20 = metadata !{i32 9, i32 0, metadata !4, null} +!21 = metadata !{i32 14, i32 0, metadata !22, null} +!22 = metadata !{i32 786443, metadata !5, metadata !10, i32 13, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [test.cpp] +!23 = metadata !{i32 15, i32 0, metadata !22, null} +!24 = metadata !{i32 786688, metadata !10, metadata !"e", metadata !6, i32 16, metadata !9, i32 0, i32 0} ; [ DW_TAG_auto_variable ] [e] [line 16] +!25 = metadata !{i32 16, i32 0, metadata !10, null} +!26 = metadata !{i32 17, i32 0, metadata !27, null} +!27 = metadata !{i32 786443, metadata !5, metadata !10, i32 16, i32 0, i32 1} ; [ DW_TAG_lexical_block ] [test.cpp] +!28 = metadata !{i32 18, i32 0, metadata !27, null} +!29 = metadata !{i32 19, i32 0, metadata !10, null} +!30 = metadata !{i32 20, i32 0, metadata !10, null} diff --git a/test/DebugInfo/inlined-vars.ll b/test/DebugInfo/inlined-vars.ll index f302294031c0..841daaa7f067 100644 --- a/test/DebugInfo/inlined-vars.ll +++ b/test/DebugInfo/inlined-vars.ll @@ -17,7 +17,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 159419)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 159419)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !10} !5 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 10, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 ()* @main, null, null, metadata !1, i32 10} ; [ DW_TAG_subprogram ] diff --git a/test/DebugInfo/llvm-symbolizer.test b/test/DebugInfo/llvm-symbolizer.test index 842a5e603eb4..163bd8ecb30b 100644 --- a/test/DebugInfo/llvm-symbolizer.test +++ b/test/DebugInfo/llvm-symbolizer.test @@ -1,7 +1,7 @@ RUN: echo "%p/Inputs/dwarfdump-test.elf-x86-64 0x400559" > %t.input RUN: echo "%p/Inputs/dwarfdump-test4.elf-x86-64 0x62c" >> %t.input RUN: echo "%p/Inputs/dwarfdump-inl-test.elf-x86-64 0x710" >> %t.input -RUN: echo '"%p/Inputs/dwarfdump-test3.elf-x86-64 space" 0x633' >> %t.input +RUN: echo "\"%p/Inputs/dwarfdump-test3.elf-x86-64 space\" 0x633" >> %t.input RUN: llvm-symbolizer --functions --inlining --demangle=false < %t.input \ RUN: | FileCheck %s diff --git a/test/DebugInfo/member-pointers.ll b/test/DebugInfo/member-pointers.ll index 4b77189563fe..20f4e68e2aa8 100644 --- a/test/DebugInfo/member-pointers.ll +++ b/test/DebugInfo/member-pointers.ll @@ -1,14 +1,16 @@ +; REQUIRES: object-emission +; XFAIL: hexagon + ; RUN: llc -filetype=obj -O0 < %s > %t ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s ; CHECK: DW_TAG_ptr_to_member_type ; CHECK: [[TYPE:.*]]: DW_TAG_subroutine_type ; CHECK: DW_TAG_formal_parameter ; CHECK-NEXT: DW_AT_type -; CHECK-NEXT: DW_AT_artificial [DW_FORM_flag_present] +; CHECK-NEXT: DW_AT_artificial [DW_FORM_flag ; CHECK: DW_TAG_ptr_to_member_type ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + {{.*}} => {[[TYPE]]}) ; IR generated from clang -g with the following source: -; XFAIL: hexagon ; struct S { ; }; ; @@ -20,7 +22,7 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/blaikie/Development/scratch/simple.cpp] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/blaikie/Development/scratch/simple.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !10} !5 = metadata !{i32 786484, i32 0, null, metadata !"x", metadata !"x", metadata !"", metadata !6, i32 4, metadata !7, i32 0, i32 1, i64* @x, null} ; [ DW_TAG_variable ] [x] [line 4] [def] diff --git a/test/DebugInfo/namespace.ll b/test/DebugInfo/namespace.ll index 8d59b523028a..a7dcf7c6150e 100644 --- a/test/DebugInfo/namespace.ll +++ b/test/DebugInfo/namespace.ll @@ -1,18 +1,45 @@ +; REQUIRES: object-emission + ; RUN: llc -O0 -filetype=obj < %s > %t ; RUN: llvm-dwarfdump %t | FileCheck %s ; CHECK: debug_info contents -; CHECK: DW_TAG_namespace +; CHECK: [[NS1:0x[0-9a-f]*]]:{{ *}}DW_TAG_namespace ; CHECK-NEXT: DW_AT_name{{.*}} = "A" ; CHECK-NEXT: DW_AT_decl_file{{.*}}(0x0[[F1:[0-9]]]) ; CHECK-NEXT: DW_AT_decl_line{{.*}}(0x03) ; CHECK-NOT: NULL -; CHECK: DW_TAG_namespace +; CHECK: [[NS2:0x[0-9a-f]*]]:{{ *}}DW_TAG_namespace ; CHECK-NEXT: DW_AT_name{{.*}} = "B" ; CHECK-NEXT: DW_AT_decl_file{{.*}}(0x0[[F2:[0-9]]]) ; CHECK-NEXT: DW_AT_decl_line{{.*}}(0x01) ; CHECK-NOT: NULL ; CHECK: DW_TAG_variable ; CHECK-NEXT: DW_AT_name{{.*}}= "i" +; CHECK: NULL +; CHECK-NOT: NULL +; CHECK: DW_TAG_imported_module +; This is a bug, it should be in F2 but it inherits the file from its +; enclosing scope +; CHECK-NEXT: DW_AT_decl_file{{.*}}(0x0[[F1]]) +; CHECK-NEXT: DW_AT_decl_line{{.*}}(0x04) +; CHECK-NEXT: DW_AT_import{{.*}}=> {[[NS2]]}) + +; CHECK: DW_TAG_subprogram +; CHECK-NEXT: DW_AT_MIPS_linkage_name +; CHECK-NEXT: DW_AT_name{{.*}}= "func" +; CHECK-NOT: NULL +; CHECK: DW_TAG_imported_module +; CHECK-NEXT: DW_AT_decl_file{{.*}}(0x0[[F2]]) +; CHECK-NEXT: DW_AT_decl_line{{.*}}(0x0e) +; CHECK-NEXT: DW_AT_import{{.*}}=> {[[NS1]]}) +; CHECK-NOT: NULL +; CHECK: DW_TAG_lexical_block +; CHECK-NOT: NULL +; CHECK: DW_TAG_imported_module +; CHECK-NEXT: DW_AT_decl_file{{.*}}(0x0[[F2]]) +; CHECK-NEXT: DW_AT_decl_line{{.*}}(0x0b) +; CHECK-NEXT: DW_AT_import{{.*}}=> {[[NS2]]}) + ; CHECK: file_names[ [[F1]]]{{.*}}debug-info-namespace.cpp ; CHECK: file_names[ [[F2]]]{{.*}}foo.cpp @@ -23,20 +50,81 @@ ; namespace B { ; int i; ; } +; using namespace B; +; } +; +; using namespace A; +; +; int func(bool b) { +; if (b) { +; using namespace A::B; +; return i; +; } +; using namespace A; +; return B::i; ; } @_ZN1A1B1iE = global i32 0, align 4 +; Function Attrs: nounwind uwtable +define i32 @_Z4funcb(i1 zeroext %b) #0 { +entry: + %retval = alloca i32, align 4 + %b.addr = alloca i8, align 1 + %frombool = zext i1 %b to i8 + store i8 %frombool, i8* %b.addr, align 1 + call void @llvm.dbg.declare(metadata !{i8* %b.addr}, metadata !21), !dbg !22 + %0 = load i8* %b.addr, align 1, !dbg !23 + %tobool = trunc i8 %0 to i1, !dbg !23 + br i1 %tobool, label %if.then, label %if.end, !dbg !23 + +if.then: ; preds = %entry + %1 = load i32* @_ZN1A1B1iE, align 4, !dbg !24 + store i32 %1, i32* %retval, !dbg !24 + br label %return, !dbg !24 + +if.end: ; preds = %entry + %2 = load i32* @_ZN1A1B1iE, align 4, !dbg !25 + store i32 %2, i32* %retval, !dbg !25 + br label %return, !dbg !25 + +return: ; preds = %if.end, %if.then + %3 = load i32* %retval, !dbg !26 + ret i32 %3, !dbg !26 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata) #1 + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, metadata !2, i32 4, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !3, metadata !4, metadata !""} ; [ DW_TAG_compile_unit ] [/home/foo/debug-info-namespace.cpp] [DW_LANG_C_plus_plus] -!1 = metadata !{i32 786473, metadata !2} ; [ DW_TAG_file_type ] [/home/foo/debug-info-namespace.cpp] -!2 = metadata !{metadata !"debug-info-namespace.cpp", metadata !"/home/foo"} -!3 = metadata !{i32 0} -!4 = metadata !{metadata !5} -!5 = metadata !{i32 786484, i32 0, metadata !6, metadata !"i", metadata !"i", metadata !"_ZN1A1B1iE", metadata !7, i32 2, metadata !10, i32 0, i32 1, i32* @_ZN1A1B1iE, null} ; [ DW_TAG_variable ] [i] [line 2] [def] -!6 = metadata !{i32 786489, metadata !8, metadata !9, metadata !"B", i32 1} ; [ DW_TAG_namespace ] [B] [line 1] -!7 = metadata !{i32 786473, metadata !8} ; [ DW_TAG_file_type ] [/home/foo/foo.cpp] -!8 = metadata !{metadata !"foo.cpp", metadata !"/home/foo"} -!9 = metadata !{i32 786489, metadata !2, null, metadata !"A", i32 3} ; [ DW_TAG_namespace ] [A] [line 3] -!10 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!0 = metadata !{i32 786449, metadata !1, i32 4, metadata !"clang version 3.3 ", i1 false, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !11, metadata !15, metadata !""} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/blaikie/dev/llvm/src/tools/clang//usr/local/google/home/blaikie/dev/llvm/src/tools/clang/test/CodeGenCXX/debug-info-namespace.cpp] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !"/usr/local/google/home/blaikie/dev/llvm/src/tools/clang/test/CodeGenCXX/debug-info-namespace.cpp", metadata !"/usr/local/google/home/blaikie/dev/llvm/src/tools/clang"} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{i32 786478, metadata !5, metadata !6, metadata !"func", metadata !"func", metadata !"_Z4funcb", i32 9, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, i32 (i1)* @_Z4funcb, null, null, metadata !2, i32 9} ; [ DW_TAG_subprogram ] [line 9] [def] [func] +!5 = metadata !{metadata !"foo.cpp", metadata !"/usr/local/google/home/blaikie/dev/llvm/src/tools/clang"} +!6 = metadata !{i32 786473, metadata !5} ; [ DW_TAG_file_type ] [/usr/local/google/home/blaikie/dev/llvm/build/clang/debug/foo.cpp] +!7 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{metadata !9, metadata !10} +!9 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 786468, null, null, metadata !"bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] [bool] [line 0, size 8, align 8, offset 0, enc DW_ATE_boolean] +!11 = metadata !{metadata !12} +!12 = metadata !{i32 786484, i32 0, metadata !13, metadata !"i", metadata !"i", metadata !"_ZN1A1B1iE", metadata !6, i32 2, metadata !9, i32 0, i32 1, i32* @_ZN1A1B1iE, null} ; [ DW_TAG_variable ] [i] [line 2] [def] +!13 = metadata !{i32 786489, metadata !5, metadata !14, metadata !"B", i32 1} ; [ DW_TAG_namespace ] [B] [line 1] +!14 = metadata !{i32 786489, metadata !1, null, metadata !"A", i32 3} ; [ DW_TAG_namespace ] [A] [line 3] +!15 = metadata !{metadata !16, metadata !17, metadata !18, metadata !20} +!16 = metadata !{i32 786490, metadata !14, metadata !13, i32 4} ; [ DW_TAG_imported_module ] +!17 = metadata !{i32 786490, metadata !0, metadata !14, i32 7} ; [ DW_TAG_imported_module ] +!18 = metadata !{i32 786490, metadata !19, metadata !13, i32 11} ; [ DW_TAG_imported_module ] +!19 = metadata !{i32 786443, metadata !5, metadata !4, i32 10, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/blaikie/dev/llvm/build/clang/debug/foo.cpp] +!20 = metadata !{i32 786490, metadata !4, metadata !14, i32 14} ; [ DW_TAG_imported_module ] +!21 = metadata !{i32 786689, metadata !4, metadata !"b", metadata !6, i32 16777225, metadata !10, i32 0, i32 0} ; [ DW_TAG_arg_variable ] [b] [line 9] +!22 = metadata !{i32 9, i32 0, metadata !4, null} +!23 = metadata !{i32 10, i32 0, metadata !4, null} +!24 = metadata !{i32 12, i32 0, metadata !19, null} +!25 = metadata !{i32 15, i32 0, metadata !4, null} +!26 = metadata !{i32 16, i32 0, metadata !4, null} diff --git a/test/DebugInfo/two-cus-from-same-file.ll b/test/DebugInfo/two-cus-from-same-file.ll index 58671d59f748..22cf4eb0fd37 100644 --- a/test/DebugInfo/two-cus-from-same-file.ll +++ b/test/DebugInfo/two-cus-from-same-file.ll @@ -3,10 +3,11 @@ ; blow llc up and produces something reasonable. ; +; REQUIRES: object-emission + ; RUN: llc %s -o %t -filetype=obj -O0 ; RUN: llvm-dwarfdump -debug-dump=info %t | FileCheck %s -; XFAIL: hexagon ; ModuleID = 'test.bc' @str = private unnamed_addr constant [4 x i8] c"FOO\00" @@ -33,14 +34,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0, !9} -!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !1 = metadata !{i32 0} !3 = metadata !{metadata !5} !5 = metadata !{i32 786478, metadata !6, metadata !"foo", metadata !"foo", metadata !"", metadata !6, i32 5, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @foo, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] !6 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ] !7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !8 = metadata !{null} -!9 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !10, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] +!9 = metadata !{i32 786449, metadata !32, i32 12, metadata !"clang version 3.2 (trunk 156513)", i1 true, metadata !"", i32 0, metadata !1, metadata !1, metadata !10, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] !10 = metadata !{metadata !12} !12 = metadata !{i32 786478, metadata !6, metadata !"main", metadata !"main", metadata !"", metadata !6, i32 11, metadata !13, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !19, i32 11} ; [ DW_TAG_subprogram ] !13 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !14, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] diff --git a/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll index 0ab02747ba1d..349db69e4c63 100644 --- a/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll +++ b/test/ExecutionEngine/2008-06-05-APInt-OverAShr.ll @@ -1,4 +1,5 @@ -; RUN: %lli -force-interpreter=true %s | grep 1 +; RUN: %lli -force-interpreter=true %s | FileCheck %s +; CHECK: 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i686-pc-linux-gnu" diff --git a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll index 0912897c05fa..9897602250a6 100644 --- a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll +++ b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll @@ -1,4 +1,5 @@ -; RUN: %lli_mcjit -force-interpreter=true %s | grep 1 +; RUN: %lli_mcjit -force-interpreter=true %s | FileCheck %s +; CHECK: 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i686-pc-linux-gnu" diff --git a/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll b/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll new file mode 100644 index 000000000000..3f402c593116 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll @@ -0,0 +1,25 @@ +; RUN: %lli_mcjit %s +; +; Verify relocations to global symbols with addend work correctly. +; +; Compiled from this C code: +; +; int test[2] = { -1, 0 }; +; int *p = &test[1]; +; +; int main (void) +; { +; return *p; +; } +; + +@test = global [2 x i32] [i32 -1, i32 0], align 4 +@p = global i32* getelementptr inbounds ([2 x i32]* @test, i64 0, i64 1), align 8 + +define i32 @main() { +entry: + %0 = load i32** @p, align 8 + %1 = load i32* %0, align 4 + ret i32 %1 +} + diff --git a/test/ExecutionEngine/MCJIT/eh.ll b/test/ExecutionEngine/MCJIT/eh.ll new file mode 100644 index 000000000000..c2135736ad48 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/eh.ll @@ -0,0 +1,32 @@ +; RUN: %lli_mcjit %s +; XFAIL: arm, cygwin, win32, mingw +declare i8* @__cxa_allocate_exception(i64) +declare void @__cxa_throw(i8*, i8*, i8*) +declare i32 @__gxx_personality_v0(...) +declare void @__cxa_end_catch() +declare i8* @__cxa_begin_catch(i8*) + +@_ZTIi = external constant i8* + +define void @throwException() { + %exception = tail call i8* @__cxa_allocate_exception(i64 4) + call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null) + unreachable +} + +define i32 @main() { +entry: + invoke void @throwException() + to label %try.cont unwind label %lpad + +lpad: + %p = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + catch i8* bitcast (i8** @_ZTIi to i8*) + %e = extractvalue { i8*, i32 } %p, 0 + call i8* @__cxa_begin_catch(i8* %e) + call void @__cxa_end_catch() + br label %try.cont + +try.cont: + ret i32 0 +} diff --git a/test/ExecutionEngine/MCJIT/fpbitcast.ll b/test/ExecutionEngine/MCJIT/fpbitcast.ll index fb5ab6f24215..ea39617547ab 100644 --- a/test/ExecutionEngine/MCJIT/fpbitcast.ll +++ b/test/ExecutionEngine/MCJIT/fpbitcast.ll @@ -1,5 +1,6 @@ -; RUN: %lli_mcjit -force-interpreter=true %s | grep 40091eb8 -; +; RUN: %lli_mcjit -force-interpreter=true %s | FileCheck %s +; CHECK: 40091eb8 + define i32 @test(double %x) { entry: %x46.i = bitcast double %x to i64 diff --git a/test/ExecutionEngine/MCJIT/lit.local.cfg b/test/ExecutionEngine/MCJIT/lit.local.cfg index fc29f651aa1f..30ed4e87e6c2 100644 --- a/test/ExecutionEngine/MCJIT/lit.local.cfg +++ b/test/ExecutionEngine/MCJIT/lit.local.cfg @@ -8,16 +8,17 @@ def getRoot(config): root = getRoot(config) targets = set(root.targets_to_build.split()) -if ('X86' in targets) | ('ARM' in targets) | ('Mips' in targets) | \ - ('PowerPC' in targets): +if ('X86' in targets) | ('AArch64' in targets) | ('ARM' in targets) | \ + ('Mips' in targets) | ('PowerPC' in targets) | ('SystemZ' in targets): config.unsupported = False else: config.unsupported = True -if root.host_arch not in ['x86', 'x86_64', 'ARM', 'Mips', 'PowerPC']: +if root.host_arch not in ['i386', 'x86', 'x86_64', + 'AArch64', 'ARM', 'Mips', 'PowerPC', 'SystemZ']: config.unsupported = True -if root.host_os in ['Darwin']: +if 'i386-apple-darwin' in root.target_triple: config.unsupported = True if 'powerpc' in root.target_triple and not 'powerpc64' in root.target_triple: diff --git a/test/ExecutionEngine/MCJIT/non-extern-addend.ll b/test/ExecutionEngine/MCJIT/non-extern-addend.ll new file mode 100644 index 000000000000..3a6e63441200 --- /dev/null +++ b/test/ExecutionEngine/MCJIT/non-extern-addend.ll @@ -0,0 +1,12 @@ +; RUN: %lli_mcjit %s > /dev/null + +define i32 @foo(i32 %X, i32 %Y, double %A) { + %cond212 = fcmp ueq double %A, 2.000000e+00 ; <i1> [#uses=1] + %cast110 = zext i1 %cond212 to i32 ; <i32> [#uses=1] + ret i32 %cast110 +} + +define i32 @main() { + %reg212 = call i32 @foo( i32 0, i32 1, double 1.000000e+00 ) ; <i32> [#uses=1] + ret i32 %reg212 +} diff --git a/test/ExecutionEngine/MCJIT/test-global-ctors.ll b/test/ExecutionEngine/MCJIT/test-global-ctors.ll index 4510d9b6a495..947d8f5d423d 100644 --- a/test/ExecutionEngine/MCJIT/test-global-ctors.ll +++ b/test/ExecutionEngine/MCJIT/test-global-ctors.ll @@ -1,4 +1,5 @@ ; RUN: %lli_mcjit %s > /dev/null +; XFAIL: darwin @var = global i32 1, align 4 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @ctor_func }] @llvm.global_dtors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @dtor_func }] diff --git a/test/ExecutionEngine/fpbitcast.ll b/test/ExecutionEngine/fpbitcast.ll index fa84be441010..e6d06f83db49 100644 --- a/test/ExecutionEngine/fpbitcast.ll +++ b/test/ExecutionEngine/fpbitcast.ll @@ -1,5 +1,6 @@ -; RUN: %lli -force-interpreter=true %s | grep 40091eb8 -; +; RUN: %lli -force-interpreter=true %s | FileCheck %s +; CHECK: 40091eb8 + define i32 @test(double %x) { entry: %x46.i = bitcast double %x to i64 diff --git a/test/ExecutionEngine/lit.local.cfg b/test/ExecutionEngine/lit.local.cfg index 1f8ae69b9868..b6945adf015a 100644 --- a/test/ExecutionEngine/lit.local.cfg +++ b/test/ExecutionEngine/lit.local.cfg @@ -7,7 +7,7 @@ def getRoot(config): root = getRoot(config) -if root.host_arch in ['PowerPC', 'AArch64']: +if root.host_arch in ['PowerPC', 'AArch64', 'SystemZ']: config.unsupported = True if 'hexagon' in root.target_triple: diff --git a/test/ExecutionEngine/test-interp-vec-arithm_float.ll b/test/ExecutionEngine/test-interp-vec-arithm_float.ll new file mode 100644 index 000000000000..d7f4ac90a986 --- /dev/null +++ b/test/ExecutionEngine/test-interp-vec-arithm_float.ll @@ -0,0 +1,20 @@ +; RUN: %lli %s > /dev/null + + +define i32 @main() { + + %A_float = fadd <4 x float> <float 0.0, float 11.0, float 22.0, float 33.0>, <float 44.0, float 55.0, float 66.0, float 77.0> + %B_float = fsub <4 x float> %A_float, <float 88.0, float 99.0, float 100.0, float 111.0> + %C_float = fmul <4 x float> %B_float, %B_float + %D_float = fdiv <4 x float> %C_float, %B_float + %E_float = frem <4 x float> %D_float, %A_float + + + %A_double = fadd <3 x double> <double 0.0, double 111.0, double 222.0>, <double 444.0, double 555.0, double 665.0> + %B_double = fsub <3 x double> %A_double, <double 888.0, double 999.0, double 1001.0> + %C_double = fmul <3 x double> %B_double, %B_double + %D_double = fdiv <3 x double> %C_double, %B_double + %E_double = frem <3 x double> %D_double, %A_double + + ret i32 0 +} diff --git a/test/ExecutionEngine/test-interp-vec-arithm_int.ll b/test/ExecutionEngine/test-interp-vec-arithm_int.ll new file mode 100644 index 000000000000..0ee14fe31ba3 --- /dev/null +++ b/test/ExecutionEngine/test-interp-vec-arithm_int.ll @@ -0,0 +1,37 @@ +; RUN: %lli %s > /dev/null + +define i32 @main() { + %A_i8 = add <5 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4>, <i8 12, i8 34, i8 56, i8 78, i8 89> + %B_i8 = sub <5 x i8> %A_i8, <i8 11, i8 22, i8 33, i8 44, i8 55> + %C_i8 = mul <5 x i8> %B_i8, %B_i8 + %D_i8 = sdiv <5 x i8> %C_i8, %C_i8 + %E_i8 = srem <5 x i8> %D_i8, %D_i8 + %F_i8 = udiv <5 x i8> <i8 5, i8 6, i8 7, i8 8, i8 9>, <i8 6, i8 5, i8 4, i8 3, i8 2> + %G_i8 = urem <5 x i8> <i8 6, i8 7, i8 8, i8 9, i8 10>, <i8 5, i8 4, i8 2, i8 2, i8 1> + + %A_i16 = add <4 x i16> <i16 0, i16 1, i16 2, i16 3>, <i16 123, i16 345, i16 567, i16 789> + %B_i16 = sub <4 x i16> %A_i16, <i16 111, i16 222, i16 333, i16 444> + %C_i16 = mul <4 x i16> %B_i16, %B_i16 + %D_i16 = sdiv <4 x i16> %C_i16, %C_i16 + %E_i16 = srem <4 x i16> %D_i16, %D_i16 + %F_i16 = udiv <4 x i16> <i16 5, i16 6, i16 7, i16 8>, <i16 6, i16 5, i16 4, i16 3> + %G_i16 = urem <4 x i16> <i16 6, i16 7, i16 8, i16 9>, <i16 5, i16 4, i16 3, i16 2> + + %A_i32 = add <3 x i32> <i32 0, i32 1, i32 2>, <i32 1234, i32 3456, i32 5678> + %B_i32 = sub <3 x i32> %A_i32, <i32 1111, i32 2222, i32 3333> + %C_i32 = mul <3 x i32> %B_i32, %B_i32 + %D_i32 = sdiv <3 x i32> %C_i32, %C_i32 + %E_i32 = srem <3 x i32> %D_i32, %D_i32 + %F_i32 = udiv <3 x i32> <i32 5, i32 6, i32 7>, <i32 6, i32 5, i32 4> + %G_i32 = urem <3 x i32> <i32 6, i32 7, i32 8>, <i32 5, i32 4, i32 3> + + %A_i64 = add <2 x i64> <i64 0, i64 1>, <i64 12455, i64 34567> + %B_i64 = sub <2 x i64> %A_i64, <i64 11111, i64 22222> + %C_i64 = mul <2 x i64> %B_i64, %B_i64 + %D_i64 = sdiv <2 x i64> %C_i64, %C_i64 + %E_i64 = srem <2 x i64> %D_i64, %D_i64 + %F_i64 = udiv <2 x i64> <i64 5, i64 6>, <i64 6, i64 5> + %G_i64 = urem <2 x i64> <i64 6, i64 7>, <i64 5, i64 3> + + ret i32 0 +} diff --git a/test/ExecutionEngine/test-interp-vec-loadstore.ll b/test/ExecutionEngine/test-interp-vec-loadstore.ll index e9f5b445a864..e5007114c070 100644 --- a/test/ExecutionEngine/test-interp-vec-loadstore.ll +++ b/test/ExecutionEngine/test-interp-vec-loadstore.ll @@ -1,4 +1,5 @@ ; RUN: %lli -force-interpreter=true %s | FileCheck %s +; XFAIL: mips ; CHECK: 1 ; CHECK: 2 ; CHECK: 3 diff --git a/test/ExecutionEngine/test-interp-vec-logical.ll b/test/ExecutionEngine/test-interp-vec-logical.ll new file mode 100644 index 000000000000..f8f1f0d8637e --- /dev/null +++ b/test/ExecutionEngine/test-interp-vec-logical.ll @@ -0,0 +1,22 @@ +; RUN: %lli %s > /dev/null + +define i32 @main() { + %A_i8 = and <5 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4>, <i8 8, i8 8, i8 8, i8 8, i8 8> + %B_i8 = or <5 x i8> %A_i8, <i8 7, i8 7, i8 7, i8 7, i8 7> + %C_i8 = xor <5 x i8> %B_i8, %A_i8 + + %A_i16 = and <4 x i16> <i16 4, i16 4, i16 4, i16 4>, <i16 8, i16 8, i16 8, i16 8> + %B_i16 = or <4 x i16> %A_i16, <i16 7, i16 7, i16 7, i16 7> + %C_i16 = xor <4 x i16> %B_i16, %A_i16 + + %A_i32 = and <3 x i32> <i32 4, i32 4, i32 4>, <i32 8, i32 8, i32 8> + %B_i32 = or <3 x i32> %A_i32, <i32 7, i32 7, i32 7> + %C_i32 = xor <3 x i32> %B_i32, %A_i32 + + %A_i64 = and <2 x i64> <i64 4, i64 4>, <i64 8, i64 8> + %B_i64 = or <2 x i64> %A_i64, <i64 7, i64 7> + %C_i64 = xor <2 x i64> %B_i64, %A_i64 + + ret i32 0 +} + diff --git a/test/ExecutionEngine/test-interp-vec-setcond-fp.ll b/test/ExecutionEngine/test-interp-vec-setcond-fp.ll new file mode 100644 index 000000000000..8b9b7c76d3c5 --- /dev/null +++ b/test/ExecutionEngine/test-interp-vec-setcond-fp.ll @@ -0,0 +1,25 @@ +; RUN: %lli %s > /dev/null + +define i32 @main() { + %double1 = fadd <2 x double> <double 0.0, double 0.0>, <double 0.0, double 0.0> + %double2 = fadd <2 x double> <double 0.0, double 0.0>, <double 0.0, double 0.0> + %float1 = fadd <3 x float> <float 0.0, float 0.0, float 0.0>, <float 0.0, float 0.0, float 0.0> + %float2 = fadd <3 x float> <float 0.0, float 0.0, float 0.0>, <float 0.0, float 0.0, float 0.0> + %test49 = fcmp oeq <3 x float> %float1, %float2 + %test50 = fcmp oge <3 x float> %float1, %float2 + %test51 = fcmp ogt <3 x float> %float1, %float2 + %test52 = fcmp ole <3 x float> %float1, %float2 + %test53 = fcmp olt <3 x float> %float1, %float2 + %test54 = fcmp une <3 x float> %float1, %float2 + + %test55 = fcmp oeq <2 x double> %double1, %double2 + %test56 = fcmp oge <2 x double> %double1, %double2 + %test57 = fcmp ogt <2 x double> %double1, %double2 + %test58 = fcmp ole <2 x double> %double1, %double2 + %test59 = fcmp olt <2 x double> %double1, %double2 + %test60 = fcmp une <2 x double> %double1, %double2 + + ret i32 0 +} + + diff --git a/test/ExecutionEngine/test-interp-vec-setcond-int.ll b/test/ExecutionEngine/test-interp-vec-setcond-int.ll new file mode 100644 index 000000000000..4c8910910595 --- /dev/null +++ b/test/ExecutionEngine/test-interp-vec-setcond-int.ll @@ -0,0 +1,69 @@ +; RUN: %lli %s > /dev/null + +define i32 @main() { + %int1 = add <3 x i32> <i32 0, i32 0, i32 0>, <i32 0, i32 0, i32 0> + %int2 = add <3 x i32> <i32 0, i32 0, i32 0>, <i32 0, i32 0, i32 0> + %long1 = add <2 x i64> <i64 0, i64 0>, <i64 0, i64 0> + %long2 = add <2 x i64> <i64 0, i64 0>, <i64 0, i64 0> + %sbyte1 = add <5 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0>, <i8 0, i8 0, i8 0, i8 0, i8 0> + %sbyte2 = add <5 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0>, <i8 0, i8 0, i8 0, i8 0, i8 0> + %short1 = add <4 x i16> <i16 0, i16 0, i16 0, i16 0>, <i16 0, i16 0, i16 0, i16 0> + %short2 = add <4 x i16> <i16 0, i16 0, i16 0, i16 0>, <i16 0, i16 0, i16 0, i16 0> + %ubyte1 = add <5 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0>, <i8 0, i8 0, i8 0, i8 0, i8 0> + %ubyte2 = add <5 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0>, <i8 0, i8 0, i8 0, i8 0, i8 0> + %uint1 = add <3 x i32> <i32 0, i32 0, i32 0>, <i32 0, i32 0, i32 0> + %uint2 = add <3 x i32> <i32 0, i32 0, i32 0>, <i32 0, i32 0, i32 0> + %ulong1 = add <2 x i64> <i64 0, i64 0>, <i64 0, i64 0> + %ulong2 = add <2 x i64> <i64 0, i64 0>, <i64 0, i64 0> + %ushort1 = add <4 x i16> <i16 0, i16 0, i16 0, i16 0>, <i16 0, i16 0, i16 0, i16 0> + %ushort2 = add <4 x i16> <i16 0, i16 0, i16 0, i16 0>, <i16 0, i16 0, i16 0, i16 0> + %test1 = icmp eq <5 x i8> %ubyte1, %ubyte2 + %test2 = icmp uge <5 x i8> %ubyte1, %ubyte2 + %test3 = icmp ugt <5 x i8> %ubyte1, %ubyte2 + %test4 = icmp ule <5 x i8> %ubyte1, %ubyte2 + %test5 = icmp ult <5 x i8> %ubyte1, %ubyte2 + %test6 = icmp ne <5 x i8> %ubyte1, %ubyte2 + %test7 = icmp eq <4 x i16> %ushort1, %ushort2 + %test8 = icmp uge <4 x i16> %ushort1, %ushort2 + %test9 = icmp ugt <4 x i16> %ushort1, %ushort2 + %test10 = icmp ule <4 x i16> %ushort1, %ushort2 + %test11 = icmp ult <4 x i16> %ushort1, %ushort2 + %test12 = icmp ne <4 x i16> %ushort1, %ushort2 + %test13 = icmp eq <3 x i32> %uint1, %uint2 + %test14 = icmp uge <3 x i32> %uint1, %uint2 + %test15 = icmp ugt <3 x i32> %uint1, %uint2 + %test16 = icmp ule <3 x i32> %uint1, %uint2 + %test17 = icmp ult <3 x i32> %uint1, %uint2 + %test18 = icmp ne <3 x i32> %uint1, %uint2 + %test19 = icmp eq <2 x i64> %ulong1, %ulong2 + %test20 = icmp uge <2 x i64> %ulong1, %ulong2 + %test21 = icmp ugt <2 x i64> %ulong1, %ulong2 + %test22 = icmp ule <2 x i64> %ulong1, %ulong2 + %test23 = icmp ult <2 x i64> %ulong1, %ulong2 + %test24 = icmp ne <2 x i64> %ulong1, %ulong2 + %test25 = icmp eq <5 x i8> %sbyte1, %sbyte2 + %test26 = icmp sge <5 x i8> %sbyte1, %sbyte2 + %test27 = icmp sgt <5 x i8> %sbyte1, %sbyte2 + %test28 = icmp sle <5 x i8> %sbyte1, %sbyte2 + %test29 = icmp slt <5 x i8> %sbyte1, %sbyte2 + %test30 = icmp ne <5 x i8> %sbyte1, %sbyte2 + %test31 = icmp eq <4 x i16> %short1, %short2 + %test32 = icmp sge <4 x i16> %short1, %short2 + %test33 = icmp sgt <4 x i16> %short1, %short2 + %test34 = icmp sle <4 x i16> %short1, %short2 + %test35 = icmp slt <4 x i16> %short1, %short2 + %test36 = icmp ne <4 x i16> %short1, %short2 + %test37 = icmp eq <3 x i32> %int1, %int2 + %test38 = icmp sge <3 x i32> %int1, %int2 + %test39 = icmp sgt <3 x i32> %int1, %int2 + %test40 = icmp sle <3 x i32> %int1, %int2 + %test41 = icmp slt <3 x i32> %int1, %int2 + %test42 = icmp ne <3 x i32> %int1, %int2 + %test43 = icmp eq <2 x i64> %long1, %long2 + %test44 = icmp sge <2 x i64> %long1, %long2 + %test45 = icmp sgt <2 x i64> %long1, %long2 + %test46 = icmp sle <2 x i64> %long1, %long2 + %test47 = icmp slt <2 x i64> %long1, %long2 + %test48 = icmp ne <2 x i64> %long1, %long2 + ret i32 0 +} diff --git a/test/Feature/aliases.ll b/test/Feature/aliases.ll index d44dff4c43c6..139381215ee8 100644 --- a/test/Feature/aliases.ll +++ b/test/Feature/aliases.ll @@ -2,6 +2,8 @@ ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll +@llvm.used = appending global [1 x i8*] [i8* bitcast (i32* @foo1 to i8*)], section "llvm.metadata" + @bar = external global i32 @foo1 = alias i32* @bar @foo2 = alias i32* @bar diff --git a/test/FileCheck/check-not-diaginfo.txt b/test/FileCheck/check-not-diaginfo.txt new file mode 100644 index 000000000000..a4c3ca884010 --- /dev/null +++ b/test/FileCheck/check-not-diaginfo.txt @@ -0,0 +1,7 @@ +; RUN: FileCheck -input-file %s %s 2>&1 | FileCheck -check-prefix DIAG %s + +CHECK-NOT: test + +DIAG: CHECK-NOT: pattern specified here +DIAG-NEXT: CHECK-NOT: test +DIAG-NEXT: {{^ \^}} diff --git a/test/Instrumentation/ThreadSanitizer/tsan_basic.ll b/test/Instrumentation/ThreadSanitizer/tsan_basic.ll index 0ecff40493a2..19dd45bda230 100644 --- a/test/Instrumentation/ThreadSanitizer/tsan_basic.ll +++ b/test/Instrumentation/ThreadSanitizer/tsan_basic.ll @@ -49,7 +49,7 @@ define void @MemSetTest(i8* nocapture %x) { entry: tail call void @llvm.memset.p0i8.i64(i8* %x, i8 77, i64 16, i32 4, i1 false) ret void -; CHECK define void @MemSetTest +; CHECK: define void @MemSetTest ; CHECK: call i8* @memset ; CHECK: ret void } diff --git a/test/Integer/2007-01-19-TruncSext.ll b/test/Integer/2007-01-19-TruncSext.ll index 3fee6bc8b6e3..e6d89ddaf33e 100644 --- a/test/Integer/2007-01-19-TruncSext.ll +++ b/test/Integer/2007-01-19-TruncSext.ll @@ -1,7 +1,8 @@ ; RUN: llvm-as %s -o - | llvm-dis > %t1.ll ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll -; RUN: llvm-as < %s | lli --force-interpreter=true | grep -- -255 +; RUN: llvm-as < %s | lli --force-interpreter=true | FileCheck %s +; CHECK: -255 @ARRAY = global [ 20 x i17 ] zeroinitializer @FORMAT = constant [ 4 x i8 ] c"%d\0A\00" diff --git a/test/Integer/fold-fpcast_bt.ll b/test/Integer/fold-fpcast_bt.ll index 8e5f8386d775..0ce776dbf851 100644 --- a/test/Integer/fold-fpcast_bt.ll +++ b/test/Integer/fold-fpcast_bt.ll @@ -1,4 +1,5 @@ -; RUN: llvm-as < %s | llvm-dis | not grep bitcast +; RUN: llvm-as < %s | llvm-dis | FileCheck %s +; CHECK-NOT: bitcast define i60 @test1() { ret i60 fptoui(float 0x400D9999A0000000 to i60) diff --git a/test/Integer/packed_struct_bt.ll b/test/Integer/packed_struct_bt.ll index 257c1c66ebac..b8301bab545c 100644 --- a/test/Integer/packed_struct_bt.ll +++ b/test/Integer/packed_struct_bt.ll @@ -1,9 +1,9 @@ ; RUN: llvm-as < %s | llvm-dis > %t1.ll ; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll ; RUN: diff %t1.ll %t2.ll -; RUN: not grep cast %t2.ll -; RUN: grep "}>" %t2.ll -; END. +; RUN: FileCheck %s --input-file=%t2.ll +; CHECK-NOT: cast +; CHECK: }> %struct.anon = type <{ i8, i35, i35, i35 }> @foos = external global %struct.anon diff --git a/test/Linker/2003-01-30-LinkerRename.ll b/test/Linker/2003-01-30-LinkerRename.ll index e7431ec15886..cbf754133411 100644 --- a/test/Linker/2003-01-30-LinkerRename.ll +++ b/test/Linker/2003-01-30-LinkerRename.ll @@ -3,7 +3,8 @@ ; RUN: echo "define internal i32 @foo() { ret i32 7 } " | llvm-as > %t.1.bc ; RUN: llvm-as %s -o %t.2.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep "@foo()" | grep -v internal +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: internal{{.*}}@foo{{[0-9]}}() define i32 @foo() { ret i32 0 } diff --git a/test/Linker/2003-01-30-LinkerTypeRename.ll b/test/Linker/2003-01-30-LinkerTypeRename.ll index 94fb5e0826c5..d61eb6d7abb3 100644 --- a/test/Linker/2003-01-30-LinkerTypeRename.ll +++ b/test/Linker/2003-01-30-LinkerTypeRename.ll @@ -3,8 +3,9 @@ ; RUN: echo "%%Ty = type opaque @GV = external global %%Ty*" | llvm-as > %t.1.bc ; RUN: llvm-as < %s > %t.2.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep "%%Ty " | not grep opaque +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: = global %Ty %Ty = type {i32} -@GV = global %Ty* null
\ No newline at end of file +@GV = global %Ty* null diff --git a/test/Linker/2003-04-23-LinkOnceLost.ll b/test/Linker/2003-04-23-LinkOnceLost.ll index 98a943a5344b..e4528906e024 100644 --- a/test/Linker/2003-04-23-LinkOnceLost.ll +++ b/test/Linker/2003-04-23-LinkOnceLost.ll @@ -4,7 +4,8 @@ ; RUN: echo " define linkonce void @foo() { ret void } " | \ ; RUN: llvm-as -o %t.2.bc ; RUN: llvm-as %s -o %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep foo | grep linkonce +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: linkonce{{.*}}foo declare void @foo() diff --git a/test/Linker/2003-05-31-LinkerRename.ll b/test/Linker/2003-05-31-LinkerRename.ll index dff861dc4bb1..2e734beba6d9 100644 --- a/test/Linker/2003-05-31-LinkerRename.ll +++ b/test/Linker/2003-05-31-LinkerRename.ll @@ -6,7 +6,8 @@ ; RUN: echo " define internal i32 @foo() { ret i32 7 } " | llvm-as > %t.1.bc ; RUN: llvm-as < %s > %t.2.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep internal | not grep "@foo(" +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: internal {{.*}} @foo{{[0-9]}}( declare i32 @foo() diff --git a/test/Linker/2003-08-23-GlobalVarLinking.ll b/test/Linker/2003-08-23-GlobalVarLinking.ll index e934836a6135..122bc41f554e 100644 --- a/test/Linker/2003-08-23-GlobalVarLinking.ll +++ b/test/Linker/2003-08-23-GlobalVarLinking.ll @@ -1,7 +1,8 @@ ; RUN: llvm-as < %s > %t.out1.bc ; RUN: echo "%%T1 = type opaque %%T2 = type opaque @S = external global { i32, %%T1* } declare void @F(%%T2*)"\ ; RUN: | llvm-as > %t.out2.bc -; RUN: llvm-link %t.out1.bc %t.out2.bc -S | not grep opaque +; RUN: llvm-link %t.out1.bc %t.out2.bc -S | FileCheck %s +; CHECK-NOT: opaque ; After linking this testcase, there should be no opaque types left. The two ; S's should cause the opaque type to be resolved to 'int'. diff --git a/test/Linker/2003-08-24-InheritPtrSize.ll b/test/Linker/2003-08-24-InheritPtrSize.ll index 51d544b83f90..dbaf9bc111b7 100644 --- a/test/Linker/2003-08-24-InheritPtrSize.ll +++ b/test/Linker/2003-08-24-InheritPtrSize.ll @@ -3,7 +3,8 @@ ; RUN: llvm-as < %s > %t.out1.bc ; RUN: echo "" | llvm-as > %t.out2.bc -; RUN: llvm-link %t.out1.bc %t.out2.bc 2>&1 | not grep warning +; RUN: llvm-link %t.out1.bc %t.out2.bc 2>&1 | FileCheck %s +; CHECK-NOT: warning target datalayout = "e-p:64:64" diff --git a/test/Linker/2004-12-03-DisagreeingType.ll b/test/Linker/2004-12-03-DisagreeingType.ll index 73d7a4055046..63e15299252d 100644 --- a/test/Linker/2004-12-03-DisagreeingType.ll +++ b/test/Linker/2004-12-03-DisagreeingType.ll @@ -1,7 +1,8 @@ ; RUN: echo "@G = weak global {{{{double}}}} zeroinitializer " | \ ; RUN: llvm-as > %t.out2.bc ; RUN: llvm-as < %s > %t.out1.bc -; RUN: llvm-link %t.out1.bc %t.out2.bc -S | not grep "}" +; RUN: llvm-link %t.out1.bc %t.out2.bc -S | FileCheck %s +; CHECK-NOT: } ; When linked, the global above should be eliminated, being merged with the ; global below. diff --git a/test/Linker/2005-02-12-ConstantGlobals-2.ll b/test/Linker/2005-02-12-ConstantGlobals-2.ll index 30bfafeb13b5..7d2e81314651 100644 --- a/test/Linker/2005-02-12-ConstantGlobals-2.ll +++ b/test/Linker/2005-02-12-ConstantGlobals-2.ll @@ -3,6 +3,7 @@ ; RUN: echo "@X = external constant i32" | llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep "global i32 7" +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: global i32 7 @X = global i32 7 diff --git a/test/Linker/2005-02-12-ConstantGlobals.ll b/test/Linker/2005-02-12-ConstantGlobals.ll index 93709cf50bed..db990604d9a8 100644 --- a/test/Linker/2005-02-12-ConstantGlobals.ll +++ b/test/Linker/2005-02-12-ConstantGlobals.ll @@ -3,6 +3,7 @@ ; RUN: echo "@X = global i32 7" | llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep "global i32 7" +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: global i32 7 @X = external constant i32 ; <i32*> [#uses=0] diff --git a/test/Linker/2005-12-06-AppendingZeroLengthArrays.ll b/test/Linker/2005-12-06-AppendingZeroLengthArrays.ll index d7a34c841e63..b99b3a823755 100644 --- a/test/Linker/2005-12-06-AppendingZeroLengthArrays.ll +++ b/test/Linker/2005-12-06-AppendingZeroLengthArrays.ll @@ -1,7 +1,8 @@ ; RUN: echo " @G = appending global [0 x i32] zeroinitializer " | \ ; RUN: llvm-as > %t.out2.bc ; RUN: llvm-as < %s > %t.out1.bc -; RUN: llvm-link %t.out1.bc %t.out2.bc -S | grep "@G =" +; RUN: llvm-link %t.out1.bc %t.out2.bc -S | FileCheck %s +; CHECK: @G = ; When linked, the globals should be merged, and the result should still ; be named '@G'. diff --git a/test/Linker/2006-06-15-GlobalVarAlignment.ll b/test/Linker/2006-06-15-GlobalVarAlignment.ll index eec8f637be0d..c9f9b0e2ab43 100644 --- a/test/Linker/2006-06-15-GlobalVarAlignment.ll +++ b/test/Linker/2006-06-15-GlobalVarAlignment.ll @@ -2,6 +2,7 @@ ; RUN: echo "@X = global i32 7, align 8" | llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep "align 8" +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: align 8 @X = weak global i32 7, align 4 diff --git a/test/Linker/2008-03-07-DroppedSection_a.ll b/test/Linker/2008-03-07-DroppedSection_a.ll index ec9d5c26ed3d..58baad95e498 100644 --- a/test/Linker/2008-03-07-DroppedSection_a.ll +++ b/test/Linker/2008-03-07-DroppedSection_a.ll @@ -1,7 +1,8 @@ ; RUN: llvm-as < %s > %t.bc ; RUN: llvm-as < %p/2008-03-07-DroppedSection_b.ll > %t2.bc ; RUN: llvm-link %t.bc %t2.bc -o %t3.bc -; RUN: llvm-dis < %t3.bc | grep ".data.init_task" +; RUN: llvm-dis < %t3.bc | FileCheck %s +; CHECK: .data.init_task ; ModuleID = 't.bc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" diff --git a/test/Linker/2008-03-07-DroppedSection_b.ll b/test/Linker/2008-03-07-DroppedSection_b.ll index 63b64f6aa1aa..9bcb80d796d1 100644 --- a/test/Linker/2008-03-07-DroppedSection_b.ll +++ b/test/Linker/2008-03-07-DroppedSection_b.ll @@ -1,7 +1,8 @@ ; RUN: llvm-as < %s > %t.bc ; RUN: llvm-as < %p/2008-03-07-DroppedSection_a.ll > %t2.bc ; RUN: llvm-link %t.bc %t2.bc -o %t3.bc -; RUN: llvm-dis < %t3.bc | grep ".data.init_task" +; RUN: llvm-dis < %t3.bc | FileCheck %s +; CHECK: .data.init_task ; ModuleID = 'u.bc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" diff --git a/test/Linker/2008-06-26-AddressSpace.ll b/test/Linker/2008-06-26-AddressSpace.ll index e1d35741e7f1..d4310bc816e2 100644 --- a/test/Linker/2008-06-26-AddressSpace.ll +++ b/test/Linker/2008-06-26-AddressSpace.ll @@ -2,8 +2,9 @@ ; in different modules. ; RUN: llvm-as %s -o %t.foo1.bc ; RUN: echo | llvm-as -o %t.foo2.bc -; RUN: llvm-link %t.foo2.bc %t.foo1.bc -S | grep "addrspace(2)" -; RUN: llvm-link %t.foo1.bc %t.foo2.bc -S | grep "addrspace(2)" +; RUN: llvm-link %t.foo2.bc %t.foo1.bc -S | FileCheck %s +; RUN: llvm-link %t.foo1.bc %t.foo2.bc -S | FileCheck %s +; CHECK: addrspace(2) ; rdar://6038021 @G = addrspace(2) global i32 256 diff --git a/test/Linker/2011-08-18-unique-class-type.ll b/test/Linker/2011-08-18-unique-class-type.ll index cae1245522ef..328e83bd07b9 100644 --- a/test/Linker/2011-08-18-unique-class-type.ll +++ b/test/Linker/2011-08-18-unique-class-type.ll @@ -1,4 +1,6 @@ -; RUN: llvm-link %s %p/2011-08-18-unique-class-type2.ll -S -o - | grep DW_TAG_class_type | count 1 +; RUN: llvm-link %s %p/2011-08-18-unique-class-type2.ll -S -o - | FileCheck %s +; CHECK: DW_TAG_class_type +; CHECK-NOT: DW_TAG_class_type ; Test to check there is only one MDNode for class A after linking. target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/test/Linker/2011-08-18-unique-debug-type.ll b/test/Linker/2011-08-18-unique-debug-type.ll index 696fdb3108b8..cc0df4d0165e 100644 --- a/test/Linker/2011-08-18-unique-debug-type.ll +++ b/test/Linker/2011-08-18-unique-debug-type.ll @@ -1,6 +1,6 @@ - -; RUN: llvm-link %s %p/2011-08-18-unique-debug-type2.ll -S -o - | grep "int" | grep -v "^; ModuleID" | count 1 +; RUN: llvm-link %s %p/2011-08-18-unique-debug-type2.ll -S -o - | FileCheck %s ; Test to check only one MDNode for "int" after linking. +; CHECK: !"int" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-macosx10.7.0" diff --git a/test/Linker/AppendingLinkage.ll b/test/Linker/AppendingLinkage.ll index 014ead91bd10..5beff5a10777 100644 --- a/test/Linker/AppendingLinkage.ll +++ b/test/Linker/AppendingLinkage.ll @@ -3,7 +3,8 @@ ; RUN: echo "@X = appending global [1 x i32] [i32 8] " | \ ; RUN: llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep 7 | grep 4 | grep 8 +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: [i32 7, i32 4, i32 8] @X = appending global [2 x i32] [ i32 7, i32 4 ] ; <[2 x i32]*> [#uses=2] @Y = global i32* getelementptr ([2 x i32]* @X, i64 0, i64 0) ; <i32**> [#uses=0] diff --git a/test/Linker/AppendingLinkage2.ll b/test/Linker/AppendingLinkage2.ll index 7385efb1f9b0..341ca1606b81 100644 --- a/test/Linker/AppendingLinkage2.ll +++ b/test/Linker/AppendingLinkage2.ll @@ -3,6 +3,7 @@ ; RUN: echo "@X = appending global [1 x i32] [i32 8] " | \ ; RUN: llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep 7 | grep 8 +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: [i32 7, i32 8] @X = appending global [1 x i32] [ i32 7 ] ; <[1 x i32]*> [#uses=0] diff --git a/test/Linker/ConstantGlobals1.ll b/test/Linker/ConstantGlobals1.ll index 716eb3d02e92..a2bb6fbfba8a 100644 --- a/test/Linker/ConstantGlobals1.ll +++ b/test/Linker/ConstantGlobals1.ll @@ -3,7 +3,8 @@ ; RUN: echo "@X = constant [1 x i32] [i32 8] " | \ ; RUN: llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep constant +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: constant @X = external global [1 x i32] ; <[1 x i32]*> [#uses=0] diff --git a/test/Linker/ConstantGlobals2.ll b/test/Linker/ConstantGlobals2.ll index ad0f8e25f2c6..471377998713 100644 --- a/test/Linker/ConstantGlobals2.ll +++ b/test/Linker/ConstantGlobals2.ll @@ -3,7 +3,8 @@ ; RUN: echo "@X = external global [1 x i32] " | \ ; RUN: llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep constant +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: constant @X = constant [1 x i32] [ i32 12 ] ; <[1 x i32]*> [#uses=0] diff --git a/test/Linker/ConstantGlobals3.ll b/test/Linker/ConstantGlobals3.ll index 5aa26bc29b09..6b4ed24c31cf 100644 --- a/test/Linker/ConstantGlobals3.ll +++ b/test/Linker/ConstantGlobals3.ll @@ -3,6 +3,7 @@ ; RUN: echo "@X = external constant [1 x i32] " | \ ; RUN: llvm-as > %t.2.bc ; RUN: llvm-as < %s > %t.1.bc -; RUN: llvm-link %t.1.bc %t.2.bc -S | grep constant +; RUN: llvm-link %t.1.bc %t.2.bc -S | FileCheck %s +; CHECK: constant @X = external global [1 x i32] ; <[1 x i32]*> [#uses=0] diff --git a/test/Linker/link-global-to-func.ll b/test/Linker/link-global-to-func.ll index 9d969d768dff..4d83fe59e894 100644 --- a/test/Linker/link-global-to-func.ll +++ b/test/Linker/link-global-to-func.ll @@ -1,7 +1,8 @@ ; RUN: llvm-as %s -o %t1.bc ; RUN: echo "declare void @__eprintf(i8*, i8*, i32, i8*) noreturn define void @foo() { tail call void @__eprintf( i8* undef, i8* undef, i32 4, i8* null ) noreturn nounwind unreachable }" | llvm-as -o %t2.bc -; RUN: llvm-link %t2.bc %t1.bc -S | grep __eprintf -; RUN: llvm-link %t1.bc %t2.bc -S | grep __eprintf +; RUN: llvm-link %t2.bc %t1.bc -S | FileCheck %s +; RUN: llvm-link %t1.bc %t2.bc -S | FileCheck %s +; CHECK: __eprintf ; rdar://6072702 diff --git a/test/Linker/linknamedmdnode.ll b/test/Linker/linknamedmdnode.ll index e6b779f1fc5d..73e7554a9077 100644 --- a/test/Linker/linknamedmdnode.ll +++ b/test/Linker/linknamedmdnode.ll @@ -1,6 +1,7 @@ ; RUN: llvm-as < %s > %t.bc ; RUN: llvm-as < %p/linknamedmdnode2.ll > %t2.bc -; RUN: llvm-link %t.bc %t2.bc -S | grep "!llvm.stuff = !{!0, !1}" +; RUN: llvm-link %t.bc %t2.bc -S | FileCheck %s +; CHECK: !llvm.stuff = !{!0, !1} !0 = metadata !{i32 42} !llvm.stuff = !{!0} diff --git a/test/Linker/redefinition.ll b/test/Linker/redefinition.ll index 23ba6a100f06..64a8c341fedb 100644 --- a/test/Linker/redefinition.ll +++ b/test/Linker/redefinition.ll @@ -3,8 +3,7 @@ ; RUN: llvm-as %s -o %t.foo1.bc ; RUN: llvm-as %s -o %t.foo2.bc ; RUN: echo "define void @foo(i32 %x) { ret void }" | llvm-as -o %t.foo3.bc -; RUN: not llvm-link %t.foo1.bc %t.foo2.bc -o %t.bc 2>&1 | \ -; RUN: grep "symbol multiply defined" -; RUN: not llvm-link %t.foo1.bc %t.foo3.bc -o %t.bc 2>&1 | \ -; RUN: grep "symbol multiply defined" +; RUN: not llvm-link %t.foo1.bc %t.foo2.bc -o %t.bc 2>&1 | FileCheck %s +; RUN: not llvm-link %t.foo1.bc %t.foo3.bc -o %t.bc 2>&1 | FileCheck %s +; CHECK: symbol multiply defined define void @foo() { ret void } diff --git a/test/Linker/weakextern.ll b/test/Linker/weakextern.ll index 3a72a48aae00..b9f2584c7eef 100644 --- a/test/Linker/weakextern.ll +++ b/test/Linker/weakextern.ll @@ -1,9 +1,10 @@ ; RUN: llvm-as < %s > %t.bc ; RUN: llvm-as < %p/testlink1.ll > %t2.bc ; RUN: llvm-link %t.bc %t.bc %t2.bc -o %t1.bc -; RUN: llvm-dis < %t1.bc | grep "kallsyms_names = extern_weak" -; RUN: llvm-dis < %t1.bc | grep "MyVar = external global i32" -; RUN: llvm-dis < %t1.bc | grep "Inte = global i32" +; RUN: llvm-dis < %t1.bc | FileCheck %s +; CHECK: kallsyms_names = extern_weak +; CHECK: Inte = global i32 +; CHECK: MyVar = external global i32 @kallsyms_names = extern_weak global [0 x i8] ; <[0 x i8]*> [#uses=0] @MyVar = extern_weak global i32 ; <i32*> [#uses=0] diff --git a/test/MC/AArch64/elf-globaladdress.ll b/test/MC/AArch64/elf-globaladdress.ll index 190439d8fe48..942920be4de2 100644 --- a/test/MC/AArch64/elf-globaladdress.ll +++ b/test/MC/AArch64/elf-globaladdress.ll @@ -1,10 +1,10 @@ ;; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ -;; RUN: elf-dump | FileCheck -check-prefix=OBJ %s +;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s ; Also take it on a round-trip through llvm-mc to stretch assembly-parsing's legs: ;; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | \ -;; RUN: llvm-mc -arch=aarch64 -filetype=obj -o - | \ -;; RUN: elf-dump | FileCheck -check-prefix=OBJ %s +;; RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj -o - | \ +;; RUN: llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s @var8 = global i8 0 @var16 = global i16 0 @@ -35,77 +35,28 @@ define void @address() { } ; Check we're using EM_AARCH64 -; OBJ: 'e_machine', 0x00 +; OBJ: ElfHeader { +; OBJ: Machine: EM_AARCH64 +; OBJ: } -; OBJ: .rela.text - -; var8 -; R_AARCH64_ADR_PREL_PG_HI21 against var8 -; OBJ: 'r_sym', 0x0000000f -; OBJ-NEXT: 'r_type', 0x00000113 - -; R_AARCH64_LDST8_ABS_LO12_NC against var8 -; OBJ: 'r_sym', 0x0000000f -; OBJ-NEXT: 'r_type', 0x00000116 - - -; var16 -; R_AARCH64_ADR_PREL_PG_HI21 against var16 -; OBJ: 'r_sym', 0x0000000c -; OBJ-NEXT: 'r_type', 0x00000113 - -; R_AARCH64_LDST16_ABS_LO12_NC against var16 -; OBJ: 'r_sym', 0x0000000c -; OBJ-NEXT: 'r_type', 0x0000011c - - -; var32 -; R_AARCH64_ADR_PREL_PG_HI21 against var32 -; OBJ: 'r_sym', 0x0000000d -; OBJ-NEXT: 'r_type', 0x00000113 - -; R_AARCH64_LDST32_ABS_LO12_NC against var32 -; OBJ: 'r_sym', 0x0000000d -; OBJ-NEXT: 'r_type', 0x0000011d - - -; var64 -; R_AARCH64_ADR_PREL_PG_HI21 against var64 -; OBJ: 'r_sym', 0x0000000e -; OBJ-NEXT: 'r_type', 0x00000113 - -; R_AARCH64_LDST64_ABS_LO12_NC against var64 -; OBJ: 'r_sym', 0x0000000e -; OBJ-NEXT: 'r_type', 0x0000011e +; OBJ: Relocations [ +; OBJ: Section (1) .text { +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var8 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC var8 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST16_ABS_LO12_NC var16 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var32 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST32_ABS_LO12_NC var32 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var64 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64 ; This is on the store, so not really important, but it stops the next ; match working. -; R_AARCH64_LDST64_ABS_LO12_NC against var64 -; OBJ: 'r_sym', 0x0000000e -; OBJ-NEXT: 'r_type', 0x0000011e - +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64 ; Pure address-calculation against var64 -; R_AARCH64_ADR_PREL_PG_HI21 against var64 -; OBJ: 'r_sym', 0x0000000e -; OBJ-NEXT: 'r_type', 0x00000113 - -; R_AARCH64_ADD_ABS_LO12_NC against var64 -; OBJ: 'r_sym', 0x0000000e -; OBJ-NEXT: 'r_type', 0x00000115 - - -; Make sure the symbols don't move around, otherwise relocation info -; will be wrong: - -; OBJ: Symbol 12 -; OBJ-NEXT: var16 - -; OBJ: Symbol 13 -; OBJ-NEXT: var32 - -; OBJ: Symbol 14 -; OBJ-NEXT: var64 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var64 +; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC var64 -; OBJ: Symbol 15 -; OBJ-NEXT: var8 +; OBJ: } +; OBJ: ] diff --git a/test/MC/AArch64/elf-objdump.s b/test/MC/AArch64/elf-objdump.s index c5aa5b19899e..51d444a36def 100644 --- a/test/MC/AArch64/elf-objdump.s +++ b/test/MC/AArch64/elf-objdump.s @@ -1,5 +1,5 @@ // 64 bit little endian -// RUN: llvm-mc -filetype=obj -arch=aarch64 -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d +// RUN: llvm-mc -filetype=obj -triple aarch64-none-linux-gnu %s -o - | llvm-objdump -d // We just want to see if llvm-objdump works at all. // CHECK: .text diff --git a/test/MC/AArch64/elf-reloc-addsubimm.s b/test/MC/AArch64/elf-reloc-addsubimm.s index 7fa6e90b5d0d..0321dda332c2 100644 --- a/test/MC/AArch64/elf-reloc-addsubimm.s +++ b/test/MC/AArch64/elf-reloc-addsubimm.s @@ -1,13 +1,10 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s add x2, x3, #:lo12:some_label -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000115 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label
\ No newline at end of file +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-condbr.s b/test/MC/AArch64/elf-reloc-condbr.s index 283d3b95d0db..684e75a33cb7 100644 --- a/test/MC/AArch64/elf-reloc-condbr.s +++ b/test/MC/AArch64/elf-reloc-condbr.s @@ -1,13 +1,10 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s b.eq somewhere -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000118 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: somewhere
\ No newline at end of file +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_CONDBR19 somewhere 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-ldrlit.s b/test/MC/AArch64/elf-reloc-ldrlit.s index ce9ff49db448..de43c4feac98 100644 --- a/test/MC/AArch64/elf-reloc-ldrlit.s +++ b/test/MC/AArch64/elf-reloc-ldrlit.s @@ -1,28 +1,16 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ldr x0, some_label ldr w3, some_label ldrsw x9, some_label prfm pldl3keep, some_label -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000111 - -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000111 - -// OBJ: 'r_offset', 0x0000000000000008 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000111 - -// OBJ: 'r_offset', 0x000000000000000c -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000111 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label
\ No newline at end of file +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_LD_PREL_LO19 some_label 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_LD_PREL_LO19 some_label 0x0 +// OBJ-NEXT: 0x8 R_AARCH64_LD_PREL_LO19 some_label 0x0 +// OBJ-NEXT: 0xC R_AARCH64_LD_PREL_LO19 some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-ldstunsimm.s b/test/MC/AArch64/elf-reloc-ldstunsimm.s index 345fc8247d0e..e1f841bd20f7 100644 --- a/test/MC/AArch64/elf-reloc-ldstunsimm.s +++ b/test/MC/AArch64/elf-reloc-ldstunsimm.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ldrb w0, [sp, #:lo12:some_label] ldrh w0, [sp, #:lo12:some_label] @@ -7,28 +7,12 @@ ldr x0, [sp, #:lo12:some_label] str q0, [sp, #:lo12:some_label] -// OBJ: .rela.text - -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000116 - -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000011c - -// OBJ: 'r_offset', 0x0000000000000008 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000011d - -// OBJ: 'r_offset', 0x000000000000000c -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000011e - -// OBJ: 'r_offset', 0x0000000000000010 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000012b - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_LDST8_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_LDST16_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: 0x8 R_AARCH64_LDST32_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: 0xC R_AARCH64_LDST64_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: 0x10 R_AARCH64_LDST128_ABS_LO12_NC some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-movw.s b/test/MC/AArch64/elf-reloc-movw.s index cb7dc6768e32..8a7e532cdd23 100644 --- a/test/MC/AArch64/elf-reloc-movw.s +++ b/test/MC/AArch64/elf-reloc-movw.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s movz x0, #:abs_g0:some_label movk x0, #:abs_g0_nc:some_label @@ -21,78 +21,22 @@ movz x19, #:abs_g2_s:some_label movn x19, #:abs_g2_s:some_label -// OBJ: .rela.text -// :abs_g0: => R_AARCH64_MOVW_UABS_G0 -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000107 - -// :abs_g0_nc: => R_AARCH64_MOVW_UABS_G0_NC -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000108 - -// :abs_g1: => R_AARCH64_MOVW_UABS_G1 -// OBJ: 'r_offset', 0x0000000000000008 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000109 - -// :abs_g1_nc: => R_AARCH64_MOVW_UABS_G1_NC -// OBJ: 'r_offset', 0x000000000000000c -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010a - -// :abs_g2: => R_AARCH64_MOVW_UABS_G2 -// OBJ: 'r_offset', 0x0000000000000010 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010b - -// :abs_g2_nc: => R_AARCH64_MOVW_UABS_G2_NC -// OBJ: 'r_offset', 0x0000000000000014 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010c - -// :abs_g3: => R_AARCH64_MOVW_UABS_G3 -// OBJ: 'r_offset', 0x0000000000000018 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010d - -// :abs_g3: => R_AARCH64_MOVW_UABS_G3 -// OBJ: 'r_offset', 0x000000000000001c -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010d - -// :abs_g0_s: => R_AARCH64_MOVW_SABS_G0 -// OBJ: 'r_offset', 0x0000000000000020 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010e - -// :abs_g0_s: => R_AARCH64_MOVW_SABS_G0 -// OBJ: 'r_offset', 0x0000000000000024 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010e - -// :abs_g1_s: => R_AARCH64_MOVW_SABS_G1 -// OBJ: 'r_offset', 0x0000000000000028 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010f - -// :abs_g1_s: => R_AARCH64_MOVW_SABS_G1 -// OBJ: 'r_offset', 0x000000000000002c -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000010f - -// :abs_g2_s: => R_AARCH64_MOVW_SABS_G2 -// OBJ: 'r_offset', 0x0000000000000030 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000110 - -// :abs_g2_s: => R_AARCH64_MOVW_SABS_G2 -// OBJ: 'r_offset', 0x0000000000000034 -// OBJ: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000110 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_MOVW_UABS_G0 some_label 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_MOVW_UABS_G0_NC some_label 0x0 +// OBJ-NEXT: 0x8 R_AARCH64_MOVW_UABS_G1 some_label 0x0 +// OBJ-NEXT: 0xC R_AARCH64_MOVW_UABS_G1_NC some_label 0x0 +// OBJ-NEXT: 0x10 R_AARCH64_MOVW_UABS_G2 some_label 0x0 +// OBJ-NEXT: 0x14 R_AARCH64_MOVW_UABS_G2_NC some_label 0x0 +// OBJ-NEXT: 0x18 R_AARCH64_MOVW_UABS_G3 some_label 0x0 +// OBJ-NEXT: 0x1C R_AARCH64_MOVW_UABS_G3 some_label 0x0 +// OBJ-NEXT: 0x20 R_AARCH64_MOVW_SABS_G0 some_label 0x0 +// OBJ-NEXT: 0x24 R_AARCH64_MOVW_SABS_G0 some_label 0x0 +// OBJ-NEXT: 0x28 R_AARCH64_MOVW_SABS_G1 some_label 0x0 +// OBJ-NEXT: 0x2C R_AARCH64_MOVW_SABS_G1 some_label 0x0 +// OBJ-NEXT: 0x30 R_AARCH64_MOVW_SABS_G2 some_label 0x0 +// OBJ-NEXT: 0x34 R_AARCH64_MOVW_SABS_G2 some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-pcreladdressing.s b/test/MC/AArch64/elf-reloc-pcreladdressing.s index 39a8ba9402a8..b5f072712fd7 100644 --- a/test/MC/AArch64/elf-reloc-pcreladdressing.s +++ b/test/MC/AArch64/elf-reloc-pcreladdressing.s @@ -1,29 +1,17 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s adr x2, some_label adrp x5, some_label adrp x5, :got:some_label ldr x0, [x5, #:got_lo12:some_label] -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000112 - -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000113 - -// OBJ: 'r_offset', 0x0000000000000008 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000137 - -// OBJ: 'r_offset', 0x000000000000000c -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000138 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label
\ No newline at end of file +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_ADR_PREL_LO21 some_label 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_ADR_PREL_PG_HI21 some_label 0x0 +// OBJ-NEXT: 0x8 R_AARCH64_ADR_GOT_PAGE some_label 0x0 +// OBJ-NEXT: 0xC R_AARCH64_LD64_GOT_LO12_NC some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-tstb.s b/test/MC/AArch64/elf-reloc-tstb.s index c5e2981a22ef..037e89632e82 100644 --- a/test/MC/AArch64/elf-reloc-tstb.s +++ b/test/MC/AArch64/elf-reloc-tstb.s @@ -1,18 +1,12 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s tbz x6, #45, somewhere tbnz w3, #15, somewhere -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000117 - -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x00000117 - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: somewhere +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_TSTBR14 somewhere 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_TSTBR14 somewhere 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/elf-reloc-uncondbrimm.s b/test/MC/AArch64/elf-reloc-uncondbrimm.s index 0e97bc66695f..bead07c12d2c 100644 --- a/test/MC/AArch64/elf-reloc-uncondbrimm.s +++ b/test/MC/AArch64/elf-reloc-uncondbrimm.s @@ -1,18 +1,12 @@ -// RUN: llvm-mc -arch=aarch64 -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \ +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s b somewhere bl somewhere -// OBJ: .rela.text -// OBJ: 'r_offset', 0x0000000000000000 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000011a - -// OBJ: 'r_offset', 0x0000000000000004 -// OBJ-NEXT: 'r_sym', 0x00000005 -// OBJ-NEXT: 'r_type', 0x0000011b - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: somewhere
\ No newline at end of file +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_AARCH64_JUMP26 somewhere 0x0 +// OBJ-NEXT: 0x4 R_AARCH64_CALL26 somewhere 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/AArch64/tls-relocs.s b/test/MC/AArch64/tls-relocs.s index 690fa8c00962..d0e336ecaf23 100644 --- a/test/MC/AArch64/tls-relocs.s +++ b/test/MC/AArch64/tls-relocs.s @@ -1,9 +1,6 @@ -// RUN: llvm-mc -arch=aarch64 -show-encoding < %s | FileCheck %s -// RUN: llvm-mc -arch=aarch64 -filetype=obj < %s -o %t -// RUN: elf-dump %t | FileCheck --check-prefix=CHECK-ELF %s -// RUN: llvm-objdump -r %t | FileCheck --check-prefix=CHECK-ELF-NAMES %s - -// CHECK-ELF: .rela.text +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -show-encoding < %s | FileCheck %s +// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \ +// RUN: llvm-readobj -r -t | FileCheck --check-prefix=CHECK-ELF %s // TLS local-dynamic forms movz x1, #:dtprel_g2:var @@ -12,34 +9,20 @@ movn x4, #:dtprel_g2:var // CHECK: movz x1, #:dtprel_g2:var // encoding: [0x01'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-NEXT: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A'] +// CHECK: movn x2, #:dtprel_g2:var // encoding: [0x02'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-NEXT: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] +// CHECK: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-NEXT: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] +// CHECK: movn x4, #:dtprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g2:var, kind: fixup_a64_movw_dtprel_g2 -// CHECK-ELF: # Relocation 0 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000000) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM:0x[0-9a-f]+]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020b) -// CHECK-ELF: # Relocation 1 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000004) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020b) -// CHECK-ELF: # Relocation 2 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000008) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020b) -// CHECK-ELF: # Relocation 3 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000000c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020b) +// CHECK-ELF: Relocations [ +// CHECK-ELF-NEXT: Section (1) .text { +// CHECK-ELF-NEXT: 0x0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM:[^ ]+]] +// CHECK-ELF-NEXT: 0x4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] +// CHECK-ELF-NEXT: 0x8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] +// CHECK-ELF-NEXT: 0xC R_AARCH64_TLSLD_MOVW_DTPREL_G2 [[VARSYM]] -// CHECK-ELF-NAMES: 0 R_AARCH64_TLSLD_MOVW_DTPREL_G2 -// CHECK-ELF-NAMES: 4 R_AARCH64_TLSLD_MOVW_DTPREL_G2 -// CHECK-ELF-NAMES: 8 R_AARCH64_TLSLD_MOVW_DTPREL_G2 -// CHECK-ELF-NAMES: 12 R_AARCH64_TLSLD_MOVW_DTPREL_G2 movz x5, #:dtprel_g1:var movn x6, #:dtprel_g1:var @@ -54,46 +37,22 @@ // CHECK-NEXT: movn w8, #:dtprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1:var, kind: fixup_a64_movw_dtprel_g1 -// CHECK-ELF: # Relocation 4 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000010) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020c) -// CHECK-ELF: # Relocation 5 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000014) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020c) -// CHECK-ELF: # Relocation 6 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000018) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020c) -// CHECK-ELF: # Relocation 7 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000001c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020c) +// CHECK-ELF-NEXT: 0x10 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0x14 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0x18 R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0x1C R_AARCH64_TLSLD_MOVW_DTPREL_G1 [[VARSYM]] -// CHECK-ELF-NAMES: 16 R_AARCH64_TLSLD_MOVW_DTPREL_G1 -// CHECK-ELF-NAMES: 20 R_AARCH64_TLSLD_MOVW_DTPREL_G1 -// CHECK-ELF-NAMES: 24 R_AARCH64_TLSLD_MOVW_DTPREL_G1 -// CHECK-ELF-NAMES: 28 R_AARCH64_TLSLD_MOVW_DTPREL_G1 movk x9, #:dtprel_g1_nc:var movk w10, #:dtprel_g1_nc:var // CHECK: movk x9, #:dtprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc -// CHECK-NEXT: movk w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] +// CHECK: movk w10, #:dtprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g1_nc:var, kind: fixup_a64_movw_dtprel_g1_nc -// CHECK-ELF: # Relocation 8 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020d) -// CHECK-ELF: # Relocation 9 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000024) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020d) +// CHECK-ELF-NEXT: 0x20 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x24 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC [[VARSYM]] -// CHECK-ELF-NAMES: 32 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC -// CHECK-ELF-NAMES: 36 R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC movz x11, #:dtprel_g0:var movn x12, #:dtprel_g0:var @@ -101,275 +60,156 @@ movn w14, #:dtprel_g0:var // CHECK: movz x11, #:dtprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-NEXT: movn x12, #:dtprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] +// CHECK: movn x12, #:dtprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-NEXT: movz w13, #:dtprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] +// CHECK: movz w13, #:dtprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0:var, kind: fixup_a64_movw_dtprel_g0 -// CHECK-NEXT: movn w14, #:dtprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] - +// CHECK: movn w14, #:dtprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] -// CHECK-ELF: # Relocation 10 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000028) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020e) -// CHECK-ELF: # Relocation 11 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000002c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020e) -// CHECK-ELF: # Relocation 12 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000030) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020e) -// CHECK-ELF: # Relocation 13 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000034) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020e) - -// CHECK-ELF-NAMES: 40 R_AARCH64_TLSLD_MOVW_DTPREL_G0 -// CHECK-ELF-NAMES: 44 R_AARCH64_TLSLD_MOVW_DTPREL_G0 -// CHECK-ELF-NAMES: 48 R_AARCH64_TLSLD_MOVW_DTPREL_G0 -// CHECK-ELF-NAMES: 52 R_AARCH64_TLSLD_MOVW_DTPREL_G0 +// CHECK-ELF-NEXT: 0x28 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0x2C R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0x30 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0x34 R_AARCH64_TLSLD_MOVW_DTPREL_G0 [[VARSYM]] movk x15, #:dtprel_g0_nc:var movk w16, #:dtprel_g0_nc:var // CHECK: movk x15, #:dtprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc -// CHECK-NEXT: movk w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] +// CHECK: movk w16, #:dtprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_g0_nc:var, kind: fixup_a64_movw_dtprel_g0_nc -// CHECK-ELF: # Relocation 14 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000038) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020f) -// CHECK-ELF: # Relocation 15 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000003c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000020f) +// CHECK-ELF-NEXT: 0x38 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x3C R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC [[VARSYM]] -// CHECK-ELF-NAMES: 56 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC -// CHECK-ELF-NAMES: 60 R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC add x17, x18, #:dtprel_hi12:var, lsl #12 add w19, w20, #:dtprel_hi12:var, lsl #12 // CHECK: add x17, x18, #:dtprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 -// CHECK-NEXT: add w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] +// CHECK: add w19, w20, #:dtprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_a64_add_dtprel_hi12 -// CHECK-ELF: # Relocation 16 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000040) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000210) -// CHECK-ELF: # Relocation 17 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000044) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000210) - -// CHECK-ELF-NAMES: 64 R_AARCH64_TLSLD_ADD_DTPREL_HI12 -// CHECK-ELF-NAMES: 68 R_AARCH64_TLSLD_ADD_DTPREL_HI12 +// CHECK-ELF-NEXT: 0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x44 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]] add x21, x22, #:dtprel_lo12:var add w23, w24, #:dtprel_lo12:var // CHECK: add x21, x22, #:dtprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 -// CHECK-NEXT: add w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] +// CHECK: add w23, w24, #:dtprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_add_dtprel_lo12 -// CHECK-ELF: # Relocation 18 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000048) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000211) -// CHECK-ELF: # Relocation 19 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000004c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000211) +// CHECK-ELF-NEXT: 0x48 R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x4C R_AARCH64_TLSLD_ADD_DTPREL_LO12 [[VARSYM]] -// CHECK-ELF-NAMES: 72 R_AARCH64_TLSLD_ADD_DTPREL_LO12 -// CHECK-ELF-NAMES: 76 R_AARCH64_TLSLD_ADD_DTPREL_LO12 add x25, x26, #:dtprel_lo12_nc:var add w27, w28, #:dtprel_lo12_nc:var // CHECK: add x25, x26, #:dtprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc -// CHECK-NEXT: add w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] +// CHECK: add w27, w28, #:dtprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_add_dtprel_lo12_nc -// CHECK-ELF: # Relocation 20 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000050) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000212) -// CHECK-ELF: # Relocation 21 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000054) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000212) +// CHECK-ELF-NEXT: 0x50 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x54 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 80 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC -// CHECK-ELF-NAMES: 84 R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC ldrb w29, [x30, #:dtprel_lo12:var] ldrsb x29, [x28, #:dtprel_lo12_nc:var] // CHECK: ldrb w29, [x30, #:dtprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst8_dtprel_lo12 -// CHECK-NEXT: ldrsb x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] +// CHECK: ldrsb x29, [x28, #:dtprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst8_dtprel_lo12_nc -// CHECK-ELF: # Relocation 22 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000058) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000213) -// CHECK-ELF: # Relocation 23 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000005c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000214) +// CHECK-ELF-NEXT: 0x58 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x5C R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 88 R_AARCH64_TLSLD_LDST8_DTPREL_LO12 -// CHECK-ELF-NAMES: 92 R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC strh w27, [x26, #:dtprel_lo12:var] ldrsh x25, [x24, #:dtprel_lo12_nc:var] // CHECK: strh w27, [x26, #:dtprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst16_dtprel_lo12 -// CHECK-NEXT: ldrsh x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] +// CHECK: ldrsh x25, [x24, #:dtprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst16_dtprel_lo12_n -// CHECK-ELF: # Relocation 24 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000060) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000215) -// CHECK-ELF: # Relocation 25 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000064) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000216) +// CHECK-ELF-NEXT: 0x60 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x64 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 96 R_AARCH64_TLSLD_LDST16_DTPREL_LO12 -// CHECK-ELF-NAMES: 100 R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC ldr w23, [x22, #:dtprel_lo12:var] ldrsw x21, [x20, #:dtprel_lo12_nc:var] // CHECK: ldr w23, [x22, #:dtprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst32_dtprel_lo12 -// CHECK-NEXT: ldrsw x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] +// CHECK: ldrsw x21, [x20, #:dtprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst32_dtprel_lo12_n -// CHECK-ELF: # Relocation 26 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000068) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000217) -// CHECK-ELF: # Relocation 27 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000006c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000218) +// CHECK-ELF-NEXT: 0x68 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x6C R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 104 R_AARCH64_TLSLD_LDST32_DTPREL_LO12 -// CHECK-ELF-NAMES: 108 R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC ldr x19, [x18, #:dtprel_lo12:var] str x17, [x16, #:dtprel_lo12_nc:var] // CHECK: ldr x19, [x18, #:dtprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_a64_ldst64_dtprel_lo12 -// CHECK-NEXT: str x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] +// CHECK: str x17, [x16, #:dtprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_a64_ldst64_dtprel_lo12_nc -// CHECK-ELF: # Relocation 28 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000070) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000219) -// CHECK-ELF: # Relocation 29 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000074) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021a) +// CHECK-ELF-NEXT: 0x70 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x74 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 112 R_AARCH64_TLSLD_LDST64_DTPREL_LO12 -// CHECK-ELF-NAMES: 116 R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC // TLS initial-exec forms movz x15, #:gottprel_g1:var movz w14, #:gottprel_g1:var // CHECK: movz x15, #:gottprel_g1:var // encoding: [0x0f'A',A,0xa0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 -// CHECK-NEXT: movz w14, #:gottprel_g1:var // encoding: [0x0e'A',A,0xa0'A',0x12'A'] +// CHECK: movz w14, #:gottprel_g1:var // encoding: [0x0e'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g1:var, kind: fixup_a64_movw_gottprel_g1 -// CHECK-ELF: # Relocation 30 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000078) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021b) -// CHECK-ELF: # Relocation 31 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000007c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021b) +// CHECK-ELF-NEXT: 0x78 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0x7C R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 [[VARSYM]] -// CHECK-ELF-NAMES: 120 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 -// CHECK-ELF-NAMES: 124 R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 movk x13, #:gottprel_g0_nc:var movk w12, #:gottprel_g0_nc:var // CHECK: movk x13, #:gottprel_g0_nc:var // encoding: [0x0d'A',A,0x80'A',0xf2'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc -// CHECK-NEXT: movk w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A'] +// CHECK: movk w12, #:gottprel_g0_nc:var // encoding: [0x0c'A',A,0x80'A',0x72'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_g0_nc:var, kind: fixup_a64_movw_gottprel_g0_nc -// CHECK-ELF: # Relocation 32 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000080) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021c) -// CHECK-ELF: # Relocation 33 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000084) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021c) +// CHECK-ELF-NEXT: 0x80 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x84 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC [[VARSYM]] -// CHECK-ELF-NAMES: 128 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC -// CHECK-ELF-NAMES: 132 R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC adrp x11, :gottprel:var ldr x10, [x0, #:gottprel_lo12:var] ldr x9, :gottprel:var // CHECK: adrp x11, :gottprel:var // encoding: [0x0b'A',A,A,0x90'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_adr_gottprel_page -// CHECK-NEXT: ldr x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A'] +// CHECK: ldr x10, [x0, #:gottprel_lo12:var] // encoding: [0x0a'A',A,0x40'A',0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel_lo12:var, kind: fixup_a64_ld64_gottprel_lo12_nc -// CHECK-NEXT: ldr x9, :gottprel:var // encoding: [0x09'A',A,A,0x58'A'] +// CHECK: ldr x9, :gottprel:var // encoding: [0x09'A',A,A,0x58'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :gottprel:var, kind: fixup_a64_ld_gottprel_prel19 -// CHECK-ELF: # Relocation 34 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000088) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021d) -// CHECK-ELF: # Relocation 35 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000008c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021e) -// CHECK-ELF: # Relocation 36 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000090) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000021f) +// CHECK-ELF-NEXT: 0x88 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 [[VARSYM]] +// CHECK-ELF-NEXT: 0x8C R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x90 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 [[VARSYM]] -// CHECK-ELF-NAMES: 136 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE -// CHECK-ELF-NAMES: 140 R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC -// CHECK-ELF-NAMES: 144 R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 // TLS local-exec forms movz x3, #:tprel_g2:var movn x4, #:tprel_g2:var // CHECK: movz x3, #:tprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 -// CHECK-NEXT: movn x4, #:tprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] +// CHECK: movn x4, #:tprel_g2:var // encoding: [0x04'A',A,0xc0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g2:var, kind: fixup_a64_movw_tprel_g2 -// CHECK-ELF: # Relocation 37 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000094) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000220) -// CHECK-ELF: # Relocation 38 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000098) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000220) +// CHECK-ELF-NEXT: 0x94 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] +// CHECK-ELF-NEXT: 0x98 R_AARCH64_TLSLE_MOVW_TPREL_G2 [[VARSYM]] -// CHECK-ELF-NAMES: 148 R_AARCH64_TLSLE_MOVW_TPREL_G2 -// CHECK-ELF-NAMES: 152 R_AARCH64_TLSLE_MOVW_TPREL_G2 movz x5, #:tprel_g1:var movn x6, #:tprel_g1:var @@ -377,53 +217,29 @@ movn w8, #:tprel_g1:var // CHECK: movz x5, #:tprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-NEXT: movn x6, #:tprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] +// CHECK: movn x6, #:tprel_g1:var // encoding: [0x06'A',A,0xa0'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-NEXT: movz w7, #:tprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] +// CHECK: movz w7, #:tprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-NEXT: movn w8, #:tprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] +// CHECK: movn w8, #:tprel_g1:var // encoding: [0x08'A',A,0xa0'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1:var, kind: fixup_a64_movw_tprel_g1 -// CHECK-ELF: # Relocation 39 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000009c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000221) -// CHECK-ELF: # Relocation 40 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000a0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000221) -// CHECK-ELF: # Relocation 41 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000a4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000221) -// CHECK-ELF: # Relocation 42 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000a8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000221) +// CHECK-ELF-NEXT: 0x9C R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0xA0 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0xA4 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] +// CHECK-ELF-NEXT: 0xA8 R_AARCH64_TLSLE_MOVW_TPREL_G1 [[VARSYM]] -// CHECK-ELF-NAMES: 156 R_AARCH64_TLSLE_MOVW_TPREL_G1 -// CHECK-ELF-NAMES: 160 R_AARCH64_TLSLE_MOVW_TPREL_G1 -// CHECK-ELF-NAMES: 164 R_AARCH64_TLSLE_MOVW_TPREL_G1 -// CHECK-ELF-NAMES: 168 R_AARCH64_TLSLE_MOVW_TPREL_G1 movk x9, #:tprel_g1_nc:var movk w10, #:tprel_g1_nc:var // CHECK: movk x9, #:tprel_g1_nc:var // encoding: [0x09'A',A,0xa0'A',0xf2'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc -// CHECK-NEXT: movk w10, #:tprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] +// CHECK: movk w10, #:tprel_g1_nc:var // encoding: [0x0a'A',A,0xa0'A',0x72'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g1_nc:var, kind: fixup_a64_movw_tprel_g1_nc -// CHECK-ELF: # Relocation 43 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000ac) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000222) -// CHECK-ELF: # Relocation 44 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000b0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000222) +// CHECK-ELF-NEXT: 0xAC R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0xB0 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC [[VARSYM]] -// CHECK-ELF-NAMES: 172 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC -// CHECK-ELF-NAMES: 176 R_AARCH64_TLSLE_MOVW_TPREL_G1_NC movz x11, #:tprel_g0:var movn x12, #:tprel_g0:var @@ -431,187 +247,104 @@ movn w14, #:tprel_g0:var // CHECK: movz x11, #:tprel_g0:var // encoding: [0x0b'A',A,0x80'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-NEXT: movn x12, #:tprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] +// CHECK: movn x12, #:tprel_g0:var // encoding: [0x0c'A',A,0x80'A',0x92'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-NEXT: movz w13, #:tprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] +// CHECK: movz w13, #:tprel_g0:var // encoding: [0x0d'A',A,0x80'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-NEXT: movn w14, #:tprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] +// CHECK: movn w14, #:tprel_g0:var // encoding: [0x0e'A',A,0x80'A',0x12'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0:var, kind: fixup_a64_movw_tprel_g0 -// CHECK-ELF: # Relocation 45 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000b4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000223) -// CHECK-ELF: # Relocation 46 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000b8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000223) -// CHECK-ELF: # Relocation 47 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000bc) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000223) -// CHECK-ELF: # Relocation 48 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000c0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000223) +// CHECK-ELF-NEXT: 0xB4 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0xB8 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0xBC R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] +// CHECK-ELF-NEXT: 0xC0 R_AARCH64_TLSLE_MOVW_TPREL_G0 [[VARSYM]] -// CHECK-ELF-NAMES: 180 R_AARCH64_TLSLE_MOVW_TPREL_G0 -// CHECK-ELF-NAMES: 184 R_AARCH64_TLSLE_MOVW_TPREL_G0 -// CHECK-ELF-NAMES: 188 R_AARCH64_TLSLE_MOVW_TPREL_G0 -// CHECK-ELF-NAMES: 192 R_AARCH64_TLSLE_MOVW_TPREL_G0 movk x15, #:tprel_g0_nc:var movk w16, #:tprel_g0_nc:var // CHECK: movk x15, #:tprel_g0_nc:var // encoding: [0x0f'A',A,0x80'A',0xf2'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc -// CHECK-NEXT: movk w16, #:tprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] +// CHECK: movk w16, #:tprel_g0_nc:var // encoding: [0x10'A',A,0x80'A',0x72'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_g0_nc:var, kind: fixup_a64_movw_tprel_g0_nc -// CHECK-ELF: # Relocation 49 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000c4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000224) -// CHECK-ELF: # Relocation 50 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000c8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000224) +// CHECK-ELF-NEXT: 0xC4 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0xC8 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC [[VARSYM]] -// CHECK-ELF-NAMES: 196 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC -// CHECK-ELF-NAMES: 200 R_AARCH64_TLSLE_MOVW_TPREL_G0_NC add x17, x18, #:tprel_hi12:var, lsl #12 add w19, w20, #:tprel_hi12:var, lsl #12 // CHECK: add x17, x18, #:tprel_hi12:var, lsl #12 // encoding: [0x51'A',0x02'A',0x40'A',0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 -// CHECK-NEXT: add w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] +// CHECK: add w19, w20, #:tprel_hi12:var, lsl #12 // encoding: [0x93'A',0x02'A',0x40'A',0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_a64_add_tprel_hi12 -// CHECK-ELF: # Relocation 51 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000cc) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000225) -// CHECK-ELF: # Relocation 52 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000d0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000225) +// CHECK-ELF-NEXT: 0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] +// CHECK-ELF-NEXT: 0xD0 R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]] -// CHECK-ELF-NAMES: 204 R_AARCH64_TLSLE_ADD_TPREL_HI12 -// CHECK-ELF-NAMES: 208 R_AARCH64_TLSLE_ADD_TPREL_HI12 add x21, x22, #:tprel_lo12:var add w23, w24, #:tprel_lo12:var // CHECK: add x21, x22, #:tprel_lo12:var // encoding: [0xd5'A',0x02'A',A,0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 -// CHECK-NEXT: add w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] +// CHECK: add w23, w24, #:tprel_lo12:var // encoding: [0x17'A',0x03'A',A,0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_add_tprel_lo12 -// CHECK-ELF: # Relocation 53 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000d4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000226) -// CHECK-ELF: # Relocation 54 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000d8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000226) +// CHECK-ELF-NEXT: 0xD4 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0xD8 R_AARCH64_TLSLE_ADD_TPREL_LO12 [[VARSYM]] -// CHECK-ELF-NAMES: 212 R_AARCH64_TLSLE_ADD_TPREL_LO12 -// CHECK-ELF-NAMES: 216 R_AARCH64_TLSLE_ADD_TPREL_LO12 add x25, x26, #:tprel_lo12_nc:var add w27, w28, #:tprel_lo12_nc:var // CHECK: add x25, x26, #:tprel_lo12_nc:var // encoding: [0x59'A',0x03'A',A,0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc -// CHECK-NEXT: add w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] +// CHECK: add w27, w28, #:tprel_lo12_nc:var // encoding: [0x9b'A',0x03'A',A,0x11'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_add_tprel_lo12_nc -// CHECK-ELF: # Relocation 55 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000dc) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000227) -// CHECK-ELF: # Relocation 56 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000e0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000227) +// CHECK-ELF-NEXT: 0xDC R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0xE0 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 220 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC -// CHECK-ELF-NAMES: 224 R_AARCH64_TLSLE_ADD_TPREL_LO12_NC - ldrb w29, [x30, #:tprel_lo12:var] ldrsb x29, [x28, #:tprel_lo12_nc:var] // CHECK: ldrb w29, [x30, #:tprel_lo12:var] // encoding: [0xdd'A',0x03'A',0x40'A',0x39'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst8_tprel_lo12 -// CHECK-NEXT: ldrsb x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] +// CHECK: ldrsb x29, [x28, #:tprel_lo12_nc:var] // encoding: [0x9d'A',0x03'A',0x80'A',0x39'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst8_tprel_lo12_nc -// CHECK-ELF: # Relocation 57 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000e4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000228) -// CHECK-ELF: # Relocation 58 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000e8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000229) +// CHECK-ELF-NEXT: 0xE4 R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0xE8 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 228 R_AARCH64_TLSLE_LDST8_TPREL_LO12 -// CHECK-ELF-NAMES: 232 R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC strh w27, [x26, #:tprel_lo12:var] ldrsh x25, [x24, #:tprel_lo12_nc:var] // CHECK: strh w27, [x26, #:tprel_lo12:var] // encoding: [0x5b'A',0x03'A',A,0x79'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst16_tprel_lo12 -// CHECK-NEXT: ldrsh x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] +// CHECK: ldrsh x25, [x24, #:tprel_lo12_nc:var] // encoding: [0x19'A',0x03'A',0x80'A',0x79'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst16_tprel_lo12_n -// CHECK-ELF: # Relocation 59 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000ec) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022a) -// CHECK-ELF: # Relocation 60 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000f0) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022b) +// CHECK-ELF-NEXT: 0xEC R_AARCH64_TLSLE_LDST16_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0xF0 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC [[VARSYM]] -// CHECK-ELF-NAMES: 236 R_AARCH64_TLSLE_LDST16_TPREL_LO12 -// CHECK-ELF-NAMES: 240 R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC ldr w23, [x22, #:tprel_lo12:var] ldrsw x21, [x20, #:tprel_lo12_nc:var] // CHECK: ldr w23, [x22, #:tprel_lo12:var] // encoding: [0xd7'A',0x02'A',0x40'A',0xb9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst32_tprel_lo12 -// CHECK-NEXT: ldrsw x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] +// CHECK: ldrsw x21, [x20, #:tprel_lo12_nc:var] // encoding: [0x95'A',0x02'A',0x80'A',0xb9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst32_tprel_lo12_n -// CHECK-ELF: # Relocation 61 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000f4) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022c) -// CHECK-ELF: # Relocation 62 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000f8) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022d) - -// CHECK-ELF-NAMES: 244 R_AARCH64_TLSLE_LDST32_TPREL_LO12 -// CHECK-ELF-NAMES: 248 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC +// CHECK-ELF-NEXT: 0xF4 R_AARCH64_TLSLE_LDST32_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0xF8 R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC [[VARSYM]] ldr x19, [x18, #:tprel_lo12:var] str x17, [x16, #:tprel_lo12_nc:var] // CHECK: ldr x19, [x18, #:tprel_lo12:var] // encoding: [0x53'A',0x02'A',0x40'A',0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_a64_ldst64_tprel_lo12 -// CHECK-NEXT: str x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] +// CHECK: str x17, [x16, #:tprel_lo12_nc:var] // encoding: [0x11'A',0x02'A',A,0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_a64_ldst64_tprel_lo12_nc -// CHECK-ELF: # Relocation 63 -// CHECK-ELF-NEXT: (('r_offset', 0x00000000000000fc) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022e) -// CHECK-ELF: # Relocation 64 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000100) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x0000022f) - -// CHECK-ELF-NAMES: 252 R_AARCH64_TLSLE_LDST64_TPREL_LO12 -// CHECK-ELF-NAMES: 256 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC +// CHECK-ELF-NEXT: 0xFC R_AARCH64_TLSLE_LDST64_TPREL_LO12 [[VARSYM]] +// CHECK-ELF-NEXT: 0x100 R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC [[VARSYM]] // TLS descriptor forms adrp x8, :tlsdesc:var @@ -622,41 +355,27 @@ // CHECK: adrp x8, :tlsdesc:var // encoding: [0x08'A',A,A,0x90'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_adr_page -// CHECK-NEXT: ldr x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A'] +// CHECK: ldr x7, [x6, #:tlsdesc_lo12:var] // encoding: [0xc7'A',A,0x40'A',0xf9'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_ld64_lo12_nc -// CHECK-NEXT: add x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A'] +// CHECK: add x5, x4, #:tlsdesc_lo12:var // encoding: [0x85'A',A,A,0x91'A'] // CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc_lo12:var, kind: fixup_a64_tlsdesc_add_lo12_nc -// CHECK-NEXT: .tlsdesccall var // encoding: [] +// CHECK: .tlsdesccall var // encoding: [] // CHECK-NEXT: // fixup A - offset: 0, value: :tlsdesc:var, kind: fixup_a64_tlsdesc_call // CHECK: blr x3 // encoding: [0x60,0x00,0x3f,0xd6] -// CHECK-ELF: # Relocation 65 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000104) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000232) -// CHECK-ELF: # Relocation 66 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000108) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000233) -// CHECK-ELF: # Relocation 67 -// CHECK-ELF-NEXT: (('r_offset', 0x000000000000010c) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000234) -// CHECK-ELF: # Relocation 68 -// CHECK-ELF-NEXT: (('r_offset', 0x0000000000000110) -// CHECK-ELF-NEXT: ('r_sym', [[VARSYM]]) -// CHECK-ELF-NEXT: ('r_type', 0x00000239) - -// CHECK-ELF-NAMES: 260 R_AARCH64_TLSDESC_ADR_PAGE -// CHECK-ELF-NAMES: 264 R_AARCH64_TLSDESC_LD64_LO12_NC -// CHECK-ELF-NAMES: 268 R_AARCH64_TLSDESC_ADD_LO12_NC -// CHECK-ELF-NAMES: 272 R_AARCH64_TLSDESC_CALL +// CHECK-ELF-NEXT: 0x104 R_AARCH64_TLSDESC_ADR_PAGE [[VARSYM]] +// CHECK-ELF-NEXT: 0x108 R_AARCH64_TLSDESC_LD64_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x10C R_AARCH64_TLSDESC_ADD_LO12_NC [[VARSYM]] +// CHECK-ELF-NEXT: 0x110 R_AARCH64_TLSDESC_CALL [[VARSYM]] // Make sure symbol 5 has type STT_TLS: -// CHECK-ELF: # Symbol 5 -// CHECK-ELF-NEXT: (('st_name', 0x00000006) # 'var' -// CHECK-ELF-NEXT: ('st_bind', 0x1) -// CHECK-ELF-NEXT: ('st_type', 0x6) +// CHECK-ELF: Symbols [ +// CHECK-ELF: Symbol { +// CHECK-ELF: Name: var (6) +// CHECK-ELF-NEXT: Value: +// CHECK-ELF-NEXT: Size: +// CHECK-ELF-NEXT: Binding: Global +// CHECK-ELF-NEXT: Type: TLS diff --git a/test/MC/ARM/arm-thumb-trustzone.s b/test/MC/ARM/arm-thumb-trustzone.s new file mode 100644 index 000000000000..a080b3efac88 --- /dev/null +++ b/test/MC/ARM/arm-thumb-trustzone.s @@ -0,0 +1,25 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + .syntax unified + .globl _func + +@ Check that the assembler processes SMC instructions when TrustZone support is +@ active and that it rejects them when this feature is not enabled + +_func: +@ CHECK: _func + + +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + ite eq + smceq #0 + +@ NOTZ-NOT: smc #15 +@ NOTZ-NOT: smceq #0 +@ TZ: smc #15 @ encoding: [0xff,0xf7,0x00,0x80] +@ TZ: ite eq @ encoding: [0x0c,0xbf] +@ TZ: smceq #0 @ encoding: [0xf0,0xf7,0x00,0x80] diff --git a/test/MC/ARM/arm-trustzone.s b/test/MC/ARM/arm-trustzone.s new file mode 100644 index 000000000000..69157f60dc0a --- /dev/null +++ b/test/MC/ARM/arm-trustzone.s @@ -0,0 +1,24 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -show-encoding -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + .syntax unified + .globl _func + +@ Check that the assembler processes SMC instructions when TrustZone support is +@ active and that it rejects them when this feature is not enabled + +_func: +@ CHECK: _func + + +@------------------------------------------------------------------------------ +@ SMC +@------------------------------------------------------------------------------ + smc #0xf + smceq #0 + +@ NOTZ-NOT: smc #15 +@ NOTZ-NOT: smceq #0 +@ TZ: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] +@ TZ: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] + diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index 560a0d633cbe..71b5b5da09be 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1791,15 +1791,6 @@ Lforward: @ CHECK: shsub8gt r4, r8, r2 @ encoding: [0xf2,0x4f,0x38,0xc6] @------------------------------------------------------------------------------ -@ SMC -@------------------------------------------------------------------------------ - smc #0xf - smceq #0 - -@ CHECK: smc #15 @ encoding: [0x7f,0x00,0x60,0xe1] -@ CHECK: smceq #0 @ encoding: [0x70,0x00,0x60,0x01] - -@------------------------------------------------------------------------------ @ SMLABB/SMLABT/SMLATB/SMLATT @------------------------------------------------------------------------------ smlabb r3, r1, r9, r0 @@ -2318,7 +2309,7 @@ Lforward: strpl r3, [r10, #0]! @ CHECK: strpl r3, [r10, #-0]! @ encoding: [0x00,0x30,0x2a,0x55] -@ CHECK: strpl r3, [r10]! @ encoding: [0x00,0x30,0xaa,0x55] +@ CHECK: strpl r3, [r10, #0]! @ encoding: [0x00,0x30,0xaa,0x55] @------------------------------------------------------------------------------ @ SUB @@ -2879,7 +2870,6 @@ Lforward: wfilt yield yieldne - hint #5 hint #4 hint #3 hint #2 @@ -2892,7 +2882,6 @@ Lforward: @ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3] @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3] @ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13] -@ CHECK: hint #5 @ encoding: [0x05,0xf0,0x20,0xe3] @ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3] @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3] @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3] diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index 9278a2a94b56..8127feba6d40 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -3486,8 +3486,6 @@ _func: wfelt wfige yieldlt - hint #5 - hint.w #5 hint.w #4 hint #3 hint #2 @@ -3501,8 +3499,6 @@ _func: @ CHECK: wfelt @ encoding: [0x20,0xbf] @ CHECK: wfige @ encoding: [0x30,0xbf] @ CHECK: yieldlt @ encoding: [0x10,0xbf] -@ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80] -@ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80] @ CHECK: sev.w @ encoding: [0xaf,0xf3,0x04,0x80] @ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80] @ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80] diff --git a/test/MC/ARM/cxx-global-constructor.ll b/test/MC/ARM/cxx-global-constructor.ll index e06d2c73ed93..4afd1e19ad44 100644 --- a/test/MC/ARM/cxx-global-constructor.ll +++ b/test/MC/ARM/cxx-global-constructor.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic \ -; RUN: -filetype=obj -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: -filetype=obj -o - | llvm-readobj -r | FileCheck %s @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @f }] @@ -9,4 +9,5 @@ define void @f() { } ; Check for a relocation of type R_ARM_TARGET1. -; CHECK: ('r_type', 0x26) +; CHECK: Relocations [ +; CHECK: 0x{{[0-9,A-F]+}} R_ARM_TARGET1 diff --git a/test/MC/ARM/data-in-code.ll b/test/MC/ARM/data-in-code.ll index c2feec5303c3..e3325b6bf6e6 100644 --- a/test/MC/ARM/data-in-code.ll +++ b/test/MC/ARM/data-in-code.ll @@ -1,8 +1,8 @@ ;; RUN: llc -O0 -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \ -;; RUN: elf-dump | FileCheck -check-prefix=ARM %s +;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s ;; RUN: llc -O0 -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=TMB %s +;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s ;; Ensure that if a jump table is generated that it has Mapping Symbols ;; marking the data-in-code region. @@ -108,68 +108,68 @@ exit: ret void } -;; ARM: # Symbol 2 -;; ARM-NEXT: $a -;; ARM-NEXT: 'st_value', 0x00000000 -;; ARM-NEXT: 'st_size', 0x00000000 -;; ARM-NEXT: 'st_bind', 0x0 -;; ARM-NEXT: 'st_type', 0x0 -;; ARM-NEXT: 'st_other' -;; ARM-NEXT: 'st_shndx', [[MIXED_SECT:0x[0-9a-f]+]] +;; ARM: Symbol { +;; ARM: Name: $a +;; ARM-NEXT: Value: 0x0 +;; ARM-NEXT: Size: 0 +;; ARM-NEXT: Binding: Local +;; ARM-NEXT: Type: None +;; ARM-NEXT: Other: +;; ARM-NEXT: Section: [[MIXED_SECT:[^ ]+]] -;; ARM: # Symbol 3 -;; ARM-NEXT: $a -;; ARM-NEXT: 'st_value', 0x000000ac -;; ARM-NEXT: 'st_size', 0x00000000 -;; ARM-NEXT: 'st_bind', 0x0 -;; ARM-NEXT: 'st_type', 0x0 -;; ARM-NEXT: 'st_other' -;; ARM-NEXT: 'st_shndx', [[MIXED_SECT]] +;; ARM: Symbol { +;; ARM: Name: $a +;; ARM-NEXT: Value: 0xAC +;; ARM-NEXT: Size: 0 +;; ARM-NEXT: Binding: Local +;; ARM-NEXT: Type: None +;; ARM-NEXT: Other: +;; ARM-NEXT: Section: [[MIXED_SECT]] -;; ARM: # Symbol 4 -;; ARM-NEXT: $d -;; ARM-NEXT: 'st_value', 0x00000000 -;; ARM-NEXT: 'st_size', 0x00000000 -;; ARM-NEXT: 'st_bind', 0x0 -;; ARM-NEXT: 'st_type', 0x0 +;; ARM: Symbol { +;; ARM: Name: $d +;; ARM-NEXT: Value: 0 +;; ARM-NEXT: Size: 0 +;; ARM-NEXT: Binding: Local +;; ARM-NEXT: Type: None -;; ARM: # Symbol 5 -;; ARM-NEXT: $d -;; ARM-NEXT: 'st_value', 0x00000030 -;; ARM-NEXT: 'st_size', 0x00000000 -;; ARM-NEXT: 'st_bind', 0x0 -;; ARM-NEXT: 'st_type', 0x0 -;; ARM-NEXT: 'st_other' -;; ARM-NEXT: 'st_shndx', [[MIXED_SECT]] +;; ARM: Symbol { +;; ARM: Name: $d +;; ARM-NEXT: Value: 0x30 +;; ARM-NEXT: Size: 0 +;; ARM-NEXT: Binding: Local +;; ARM-NEXT: Type: None +;; ARM-NEXT: Other: +;; ARM-NEXT: Section: [[MIXED_SECT]] ;; ARM-NOT: ${{[atd]}} -;; TMB: # Symbol 3 -;; TMB-NEXT: $d -;; TMB-NEXT: 'st_value', 0x00000016 -;; TMB-NEXT: 'st_size', 0x00000000 -;; TMB-NEXT: 'st_bind', 0x0 -;; TMB-NEXT: 'st_type', 0x0 -;; TMB-NEXT: 'st_other' -;; TMB-NEXT: 'st_shndx', [[MIXED_SECT:0x[0-9a-f]+]] +;; TMB: Symbol { +;; TMB: Name: $d.2 +;; TMB-NEXT: Value: 0x16 +;; TMB-NEXT: Size: 0 +;; TMB-NEXT: Binding: Local +;; TMB-NEXT: Type: None +;; TMB-NEXT: Other: +;; TMB-NEXT: Section: [[MIXED_SECT:[^ ]+]] -;; TMB: # Symbol 4 -;; TMB-NEXT: $t -;; TMB-NEXT: 'st_value', 0x00000000 -;; TMB-NEXT: 'st_size', 0x00000000 -;; TMB-NEXT: 'st_bind', 0x0 -;; TMB-NEXT: 'st_type', 0x0 -;; TMB-NEXT: 'st_other' -;; TMB-NEXT: 'st_shndx', [[MIXED_SECT]] +;; TMB: Symbol { +;; TMB: Name: $t +;; TMB-NEXT: Value: 0x0 +;; TMB-NEXT: Size: 0 +;; TMB-NEXT: Binding: Local +;; TMB-NEXT: Type: None +;; TMB-NEXT: Other: +;; TMB-NEXT: Section: [[MIXED_SECT]] -;; TMB: # Symbol 5 -;; TMB-NEXT: $t -;; TMB-NEXT: 'st_value', 0x00000036 -;; TMB-NEXT: 'st_size', 0x00000000 -;; TMB-NEXT: 'st_bind', 0x0 -;; TMB-NEXT: 'st_type', 0x0 -;; TMB-NEXT: 'st_other' -;; TMB-NEXT: 'st_shndx', [[MIXED_SECT]] +;; TMB: Symbol { +;; TMB: Name: $t +;; TMB-NEXT: Value: 0x36 +;; TMB-NEXT: Size: 0 +;; TMB-NEXT: Binding: Local +;; TMB-NEXT: Type: None +;; TMB-NEXT: Other: +;; TMB-NEXT: Section: [[MIXED_SECT]] ;; TMB-NOT: ${{[atd]}} diff --git a/test/MC/ARM/elf-eflags-eabi-cg.ll b/test/MC/ARM/elf-eflags-eabi-cg.ll index 2e86a0f36077..0b9de7f2a62a 100644 --- a/test/MC/ARM/elf-eflags-eabi-cg.ll +++ b/test/MC/ARM/elf-eflags-eabi-cg.ll @@ -1,7 +1,7 @@ ; Codegen version to check for ELF header flags. ; ; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic \ -; RUN: -filetype=obj -o - | elf-dump --dump-section-data | \ +; RUN: -filetype=obj -o - | llvm-readobj -h | \ ; RUN: FileCheck %s define void @bar() nounwind { @@ -10,4 +10,5 @@ entry: } ; For now the only e_flag set is EF_ARM_EABI_VER5 -;CHECK: 'e_flags', 0x05000000 +; CHECK: ElfHeader { +; CHECK: Flags [ (0x5000000) diff --git a/test/MC/ARM/elf-eflags-eabi.s b/test/MC/ARM/elf-eflags-eabi.s index ea89eacf74fb..fe0b6c071e62 100644 --- a/test/MC/ARM/elf-eflags-eabi.s +++ b/test/MC/ARM/elf-eflags-eabi.s @@ -1,5 +1,5 @@ @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ -@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +@ RUN: llvm-readobj -h | FileCheck -check-prefix=OBJ %s .syntax unified .text .globl barf @@ -10,4 +10,5 @@ barf: @ @barf b foo @@@ make sure the EF_ARM_EABIMASK comes out OK -@OBJ: 'e_flags', 0x05000000 +@OBJ: ElfHeader { +@OBJ: Flags [ (0x5000000) diff --git a/test/MC/ARM/elf-movt.s b/test/MC/ARM/elf-movt.s index 02bb5a6907de..74b3c9f2f53b 100644 --- a/test/MC/ARM/elf-movt.s +++ b/test/MC/ARM/elf-movt.s @@ -1,6 +1,6 @@ @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ -@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +@ RUN: llvm-readobj -s -sd -sr | FileCheck -check-prefix=OBJ %s .syntax unified .text .globl barf @@ -15,25 +15,24 @@ barf: @ @barf @ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+8)) @@ make sure that the text section fixups are sane too -@ OBJ: '.text' -@ OBJ-NEXT: 'sh_type', 0x00000001 -@ OBJ-NEXT: 'sh_flags', 0x00000006 -@ OBJ-NEXT: 'sh_addr', 0x00000000 -@ OBJ-NEXT: 'sh_offset', 0x00000034 -@ OBJ-NEXT: 'sh_size', 0x00000008 -@ OBJ-NEXT: 'sh_link', 0x00000000 -@ OBJ-NEXT: 'sh_info', 0x00000000 -@ OBJ-NEXT: 'sh_addralign', 0x00000004 -@ OBJ-NEXT: 'sh_entsize', 0x00000000 -@ OBJ-NEXT: '_section_data', 'f00f0fe3 f40f4fe3' - -@ OBJ: Relocation 0 -@ OBJ-NEXT: 'r_offset', 0x00000000 -@ OBJ-NEXT: 'r_sym' -@ OBJ-NEXT: 'r_type', 0x2d - -@ OBJ: Relocation 1 -@ OBJ-NEXT: 'r_offset', 0x00000004 -@ OBJ-NEXT: 'r_sym' -@ OBJ-NEXT: 'r_type', 0x2e - +@ OBJ: Section { +@ OBJ: Name: .text +@ OBJ-NEXT: Type: SHT_PROGBITS +@ OBJ-NEXT: Flags [ (0x6) +@ OBJ-NEXT: SHF_ALLOC +@ OBJ-NEXT: SHF_EXECINSTR +@ OBJ-NEXT: ] +@ OBJ-NEXT: Address: 0x0 +@ OBJ-NEXT: Offset: 0x34 +@ OBJ-NEXT: Size: 8 +@ OBJ-NEXT: Link: 0 +@ OBJ-NEXT: Info: 0 +@ OBJ-NEXT: AddressAlignment: 4 +@ OBJ-NEXT: EntrySize: 0 +@ OBJ-NEXT: Relocations [ +@ OBJ-NEXT: 0x0 R_ARM_MOVW_PREL_NC +@ OBJ-NEXT: 0x4 R_ARM_MOVT_PREL +@ OBJ-NEXT: ] +@ OBJ-NEXT: SectionData ( +@ OBJ-NEXT: 0000: F00F0FE3 F40F4FE3 +@ OBJ-NEXT: ) diff --git a/test/MC/ARM/elf-reloc-01.ll b/test/MC/ARM/elf-reloc-01.ll index 3ebd7c641b6d..9b5dbd9e99dd 100644 --- a/test/MC/ARM/elf-reloc-01.ll +++ b/test/MC/ARM/elf-reloc-01.ll @@ -1,7 +1,7 @@ ;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ ;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ ;; RUN: -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ;; FIXME: This file needs to be in .s form! ;; The args to llc are there to constrain the codegen only. @@ -60,11 +60,8 @@ bb3: ; preds = %bb, %entry declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 1 -;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x000007 -;; OBJ-NEXT: 'r_type', 0x2b - -;; OBJ: Symbol 7 -;; OBJ-NEXT: '_MergedGlobals' -;; OBJ-NEXT: 'st_value', 0x00000010 +; OBJ: Relocations [ +; OBJ: Section (1) .text { +; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC _MergedGlobals +; OBJ: } +; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-02.ll b/test/MC/ARM/elf-reloc-02.ll index 6b6b03c388a4..f0217644cad9 100644 --- a/test/MC/ARM/elf-reloc-02.ll +++ b/test/MC/ARM/elf-reloc-02.ll @@ -1,7 +1,7 @@ ;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ ;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ ;; RUN: -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ;; FIXME: This file needs to be in .s form! ;; The args to llc are there to constrain the codegen only. @@ -41,10 +41,8 @@ declare i32 @write(...) declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 0 -;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x000005 -;; OBJ-NEXT: 'r_type', 0x2b - -;; OBJ: Symbol 5 -;; OBJ-NEXT: '.L.str' +;; OBJ: Relocations [ +;; OBJ: Section (1) .text { +;; OBJ-NEXT: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC .L.str +;; OBJ: } +;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-03.ll b/test/MC/ARM/elf-reloc-03.ll index 87f91c11210b..ac46e697c18a 100644 --- a/test/MC/ARM/elf-reloc-03.ll +++ b/test/MC/ARM/elf-reloc-03.ll @@ -1,7 +1,7 @@ ;; RUN: llc -mtriple=armv7-linux-gnueabi -O3 \ ;; RUN: -mcpu=cortex-a8 -mattr=-neon -mattr=+vfp2 -arm-reserve-r9 \ ;; RUN: -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s +;; RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s ;; FIXME: This file needs to be in .s form! ;; The args to llc are there to constrain the codegen only. @@ -88,10 +88,8 @@ entry: declare void @exit(i32) noreturn nounwind -;; OBJ: Relocation 1 -;; OBJ-NEXT: 'r_offset', -;; OBJ-NEXT: 'r_sym', 0x000010 -;; OBJ-NEXT: 'r_type', 0x2b - -;; OBJ: Symbol 16 -;; OBJ-NEXT: 'vtable' +;; OBJ: Relocations [ +;; OBJ: Section (1) .text { +;; OBJ: 0x{{[0-9,A-F]+}} R_ARM_MOVW_ABS_NC vtable +;; OBJ: } +;; OBJ: ] diff --git a/test/MC/ARM/elf-reloc-condcall.s b/test/MC/ARM/elf-reloc-condcall.s index 3fafb43eb060..612942f2c595 100644 --- a/test/MC/ARM/elf-reloc-condcall.s +++ b/test/MC/ARM/elf-reloc-condcall.s @@ -1,33 +1,18 @@ // RUN: llvm-mc -triple=armv7-linux-gnueabi -filetype=obj %s -o - | \ -// RUN: elf-dump | FileCheck -check-prefix=OBJ %s +// RUN: llvm-readobj -r | FileCheck -check-prefix=OBJ %s bleq some_label bl some_label blx some_label beq some_label b some_label -// OBJ: .rel.text -// OBJ: 'r_offset', 0x00000000 -// OBJ-NEXT: 'r_sym', 0x000005 -// OBJ-NEXT: 'r_type', 0x1d - -// OBJ: 'r_offset', 0x00000004 -// OBJ-NEXT: 'r_sym', 0x000005 -// OBJ-NEXT: 'r_type', 0x1c - -// OBJ: 'r_offset', 0x00000008 -// OBJ-NEXT: 'r_sym', 0x000005 -// OBJ-NEXT: 'r_type', 0x1c - -// OBJ: 'r_offset', 0x0000000c -// OBJ-NEXT: 'r_sym', 0x000005 -// OBJ-NEXT: 'r_type', 0x1d - -// OBJ: 'r_offset', 0x00000010 -// OBJ-NEXT: 'r_sym', 0x000005 -// OBJ-NEXT: 'r_type', 0x1d - -// OBJ: .symtab -// OBJ: Symbol 5 -// OBJ-NEXT: some_label +// OBJ: Relocations [ +// OBJ-NEXT: Section (1) .text { +// OBJ-NEXT: 0x0 R_ARM_JUMP24 some_label 0x0 +// OBJ-NEXT: 0x4 R_ARM_CALL some_label 0x0 +// OBJ-NEXT: 0x8 R_ARM_CALL some_label 0x0 +// OBJ-NEXT: 0xC R_ARM_JUMP24 some_label 0x0 +// OBJ-NEXT: 0x10 R_ARM_JUMP24 some_label 0x0 +// OBJ-NEXT: } +// OBJ-NEXT: ] diff --git a/test/MC/ARM/elf-thumbfunc-reloc.ll b/test/MC/ARM/elf-thumbfunc-reloc.ll index b2f253d2fa95..e7d2c340d44d 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.ll +++ b/test/MC/ARM/elf-thumbfunc-reloc.ll @@ -1,5 +1,5 @@ ; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -relocation-model=pic \ -; RUN: -filetype=obj -o - | elf-dump --dump-section-data | \ +; RUN: -filetype=obj -o - | llvm-readobj -s -sd -r -t | \ ; RUN: FileCheck %s ; FIXME: This file needs to be in .s form! @@ -22,16 +22,20 @@ entry: ; make sure that bl 0 <foo> (fff7feff) is correctly encoded -; CHECK: '_section_data', '704700bf 2de90048 fff7feff bde80088' +; CHECK: Sections [ +; CHECK: SectionData ( +; CHECK: 0000: 704700BF 2DE90048 FFF7FEFF BDE80088 +; CHECK: ) +; CHECK: ] -; Offset Info Type Sym.Value Sym. Name -; 00000008 0000070a R_ARM_THM_CALL 00000001 foo -; CHECK: Relocation 0 -; CHECK-NEXT: 'r_offset', 0x00000008 -; CHECK-NEXT: 'r_sym', 0x000009 -; CHECK-NEXT: 'r_type', 0x0a +; CHECK: Relocations [ +; CHECK-NEXT: Section (1) .text { +; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0 +; CHECK-NEXT: } +; CHECK-NEXT: ] ; make sure foo is thumb function: bit 0 = 1 -; CHECK: Symbol 9 -; CHECK-NEXT: 'foo' -; CHECK-NEXT: 'st_value', 0x00000001 +; CHECK: Symbols [ +; CHECK: Symbol { +; CHECK: Name: foo +; CHECK-NEXT: Value: 0x1 diff --git a/test/MC/ARM/elf-thumbfunc-reloc.s b/test/MC/ARM/elf-thumbfunc-reloc.s index 4a311dd51131..87a26d8df84e 100644 --- a/test/MC/ARM/elf-thumbfunc-reloc.s +++ b/test/MC/ARM/elf-thumbfunc-reloc.s @@ -1,6 +1,6 @@ @@ test st_value bit 0 of thumb function @ RUN: llvm-mc %s -triple=arm-freebsd-eabi -filetype=obj -o - | \ -@ RUN: elf-dump | FileCheck %s +@ RUN: llvm-readobj -r | FileCheck %s .syntax unified @@ -17,7 +17,8 @@ f: pop {r7, pc} @@ make sure an R_ARM_THM_CALL relocation is generated for the call to g -@CHECK: ('_relocations', [ -@CHECK: (('r_offset', 0x00000004) -@CHECK-NEXT: ('r_sym', 0x{{[0-9a-fA-F]+}}) -@CHECK-NEXT: ('r_type', 0x0a) +@CHECK: Relocations [ +@CHECK-NEXT: Section (1) .text { +@CHECK-NEXT: 0x4 R_ARM_THM_CALL g 0x0 +@CHECK-NEXT: } +@CHECK-NEXT: ] diff --git a/test/MC/ARM/elf-thumbfunc.s b/test/MC/ARM/elf-thumbfunc.s index 91b2eee7592b..26f5f0b159af 100644 --- a/test/MC/ARM/elf-thumbfunc.s +++ b/test/MC/ARM/elf-thumbfunc.s @@ -1,6 +1,6 @@ @@ test st_value bit 0 of thumb function @ RUN: llvm-mc %s -triple=thumbv7-linux-gnueabi -filetype=obj -o - | \ -@ RUN: elf-dump | FileCheck %s +@ RUN: llvm-readobj -t | FileCheck %s .syntax unified .text .globl foo @@ -12,9 +12,9 @@ foo: bx lr @@ make sure foo is thumb function: bit 0 = 1 (st_value) -@CHECK: Symbol 5 -@CHECK-NEXT: 'st_name', 0x00000001 -@CHECK-NEXT: 'st_value', 0x00000001 -@CHECK-NEXT: 'st_size', 0x00000000 -@CHECK-NEXT: 'st_bind', 0x1 -@CHECK-NEXT: 'st_type', 0x2 +@CHECK: Symbol { +@CHECK: Name: foo +@CHECK-NEXT: Value: 0x1 +@CHECK-NEXT: Size: 0 +@CHECK-NEXT: Binding: Global +@CHECK-NEXT: Type: Function diff --git a/test/MC/ARM/invalid-hint-arm.s b/test/MC/ARM/invalid-hint-arm.s new file mode 100644 index 000000000000..e0cd97a19028 --- /dev/null +++ b/test/MC/ARM/invalid-hint-arm.s @@ -0,0 +1,7 @@ +@ RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s + +hint #5 +hint #100 + +@ CHECK: error: immediate operand must be in the range [0,4] +@ CHECK: error: immediate operand must be in the range [0,4] diff --git a/test/MC/ARM/invalid-hint-thumb.s b/test/MC/ARM/invalid-hint-thumb.s new file mode 100644 index 000000000000..fd0a761da27b --- /dev/null +++ b/test/MC/ARM/invalid-hint-thumb.s @@ -0,0 +1,9 @@ +@ RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 < %s 2>&1 | FileCheck %s + +hint #5 +hint.w #5 +hint #100 + +@ CHECK: error: immediate operand must be in the range [0,4] +@ CHECK: error: immediate operand must be in the range [0,4] +@ CHECK: error: immediate operand must be in the range [0,4] diff --git a/test/MC/ARM/neon-cmp-encoding.s b/test/MC/ARM/neon-cmp-encoding.s index b3aedb8e52ec..cffbeab644a0 100644 --- a/test/MC/ARM/neon-cmp-encoding.s +++ b/test/MC/ARM/neon-cmp-encoding.s @@ -174,3 +174,24 @@ @ CHECK: vcge.u16 q8, q9, q8 @ encoding: [0xf0,0x03,0x52,0xf3] @ CHECK: vcge.u32 q8, q9, q8 @ encoding: [0xf0,0x03,0x62,0xf3] @ CHECK: vcge.f32 q8, q9, q8 @ encoding: [0xe0,0x0e,0x42,0xf3] + + +@ VACLT is an alias for VACGT w/ the source operands reversed. +@ VACLE is an alias for VACGE w/ the source operands reversed. + vaclt.f32 q9, q11, q12 + vaclt.f32 d9, d11, d12 + vaclt.f32 q11, q12 + vaclt.f32 d11, d12 + vacle.f32 q9, q11, q12 + vacle.f32 d9, d11, d12 + vacle.f32 q11, q12 + vacle.f32 d11, d12 + +@ CHECK: vacgt.f32 q9, q12, q11 @ encoding: [0xf6,0x2e,0x68,0xf3] +@ CHECK: vacgt.f32 d9, d12, d11 @ encoding: [0x1b,0x9e,0x2c,0xf3] +@ CHECK: vacgt.f32 q11, q12, q11 @ encoding: [0xf6,0x6e,0x68,0xf3] +@ CHECK: vacgt.f32 d11, d12, d11 @ encoding: [0x1b,0xbe,0x2c,0xf3] +@ CHECK: vacge.f32 q9, q12, q11 @ encoding: [0xf6,0x2e,0x48,0xf3] +@ CHECK: vacge.f32 d9, d12, d11 @ encoding: [0x1b,0x9e,0x0c,0xf3] +@ CHECK: vacge.f32 q11, q12, q11 @ encoding: [0xf6,0x6e,0x48,0xf3] +@ CHECK: vacge.f32 d11, d12, d11 @ encoding: [0x1b,0xbe,0x0c,0xf3] diff --git a/test/MC/ARM/xscale-attributes.ll b/test/MC/ARM/xscale-attributes.ll index 3ccf02b95e2c..d1e9931e1448 100644 --- a/test/MC/ARM/xscale-attributes.ll +++ b/test/MC/ARM/xscale-attributes.ll @@ -2,7 +2,7 @@ ; RUN: FileCheck -check-prefix=ASM %s ; RUN: llc %s -mtriple=thumbv5-linux-gnueabi -filetype=obj \ -; RUN: -mcpu=xscale -o - | elf-dump --dump-section-data | \ +; RUN: -mcpu=xscale -o - | llvm-readobj -s -sd | \ ; RUN: FileCheck -check-prefix=OBJ %s ; FIXME: The OBJ test should be a .s to .o test and the ASM test should @@ -17,15 +17,22 @@ entry: ; ASM-NEXT: .eabi_attribute 8, 1 ; ASM-NEXT: .eabi_attribute 9, 1 -; OBJ: Section 4 -; OBJ-NEXT: 'sh_name', 0x0000000c -; OBJ-NEXT: 'sh_type', 0x70000003 -; OBJ-NEXT: 'sh_flags', 0x00000000 -; OBJ-NEXT: 'sh_addr', 0x00000000 -; OBJ-NEXT: 'sh_offset', 0x00000038 -; OBJ-NEXT: 'sh_size', 0x00000020 -; OBJ-NEXT: 'sh_link', 0x00000000 -; OBJ-NEXT: 'sh_info', 0x00000000 -; OBJ-NEXT: 'sh_addralign', 0x00000001 -; OBJ-NEXT: 'sh_entsize', 0x00000000 -; OBJ-NEXT: '_section_data', '411f0000 00616561 62690001 15000000 06050801 09011401 15011703 18011901' +; OBJ: Sections [ +; OBJ: Section { +; OBJ: Index: 4 +; OBJ-NEXT: Name: .ARM.attributes (12) +; OBJ-NEXT: Type: SHT_ARM_ATTRIBUTES +; OBJ-NEXT: Flags [ (0x0) +; OBJ-NEXT: ] +; OBJ-NEXT: Address: 0x0 +; OBJ-NEXT: Offset: 0x38 +; OBJ-NEXT: Size: 32 +; OBJ-NEXT: Link: 0 +; OBJ-NEXT: Info: 0 +; OBJ-NEXT: AddressAlignment: 1 +; OBJ-NEXT: EntrySize: 0 +; OBJ-NEXT: SectionData ( +; OBJ-NEXT: 0000: 411F0000 00616561 62690001 15000000 +; OBJ-NEXT: 0010: 06050801 09011401 15011703 18011901 +; OBJ-NEXT: ) +; OBJ-NEXT: } diff --git a/test/MC/AsmParser/exprs.s b/test/MC/AsmParser/exprs.s index df075f85ecf5..a7e10020b67b 100644 --- a/test/MC/AsmParser/exprs.s +++ b/test/MC/AsmParser/exprs.s @@ -45,6 +45,7 @@ k: check_expr 0 || 0, 0 check_expr 1 + 2 < 3 + 4, 1 check_expr 1 << 8 - 1, 128 + check_expr 3 * 9 - 2 * 9 + 1, 10 .set c, 10 check_expr c + 1, 11 diff --git a/test/MC/AsmParser/section.s b/test/MC/AsmParser/section.s index 5abacc701354..0c3828d714a7 100644 --- a/test/MC/AsmParser/section.s +++ b/test/MC/AsmParser/section.s @@ -1,5 +1,5 @@ # RUN: llvm-mc -triple i386-pc-linux-gnu -filetype=obj -o %t %s -# RUN: elf-dump --dump-section-data < %t | FileCheck %s +# RUN: llvm-readobj -s -sd < %t | FileCheck %s .section test1 .byte 1 .section test2 @@ -45,63 +45,85 @@ .previous .byte 1 .previous -# CHECK: (('sh_name', 0x00000044) # 'test1' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK-NEXT: ('sh_flags', 0x00000000) -# CHECK-NEXT: ('sh_addr', 0x00000000) -# CHECK-NEXT: ('sh_offset', 0x00000034) -# CHECK-NEXT: ('sh_size', 0x00000007) -# CHECK-NEXT: ('sh_link', 0x00000000) -# CHECK-NEXT: ('sh_info', 0x00000000) -# CHECK-NEXT: ('sh_addralign', 0x00000001) -# CHECK-NEXT: ('sh_entsize', 0x00000000) -# CHECK-NEXT: ('_section_data', '01010101 010101') -# CHECK-NEXT: ), -# CHECK: (('sh_name', 0x0000003e) # 'test2' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK-NEXT: ('sh_flags', 0x00000000) -# CHECK-NEXT: ('sh_addr', 0x00000000) -# CHECK-NEXT: ('sh_offset', 0x0000003b) -# CHECK-NEXT: ('sh_size', 0x00000006) -# CHECK-NEXT: ('sh_link', 0x00000000) -# CHECK-NEXT: ('sh_info', 0x00000000) -# CHECK-NEXT: ('sh_addralign', 0x00000001) -# CHECK-NEXT: ('sh_entsize', 0x00000000) -# CHECK-NEXT: ('_section_data', '02020202 0202') -# CHECK-NEXT: ), -# CHECK: (('sh_name', 0x00000038) # 'test3' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK-NEXT: ('sh_flags', 0x00000000) -# CHECK-NEXT: ('sh_addr', 0x00000000) -# CHECK-NEXT: ('sh_offset', 0x00000041) -# CHECK-NEXT: ('sh_size', 0x00000005) -# CHECK-NEXT: ('sh_link', 0x00000000) -# CHECK-NEXT: ('sh_info', 0x00000000) -# CHECK-NEXT: ('sh_addralign', 0x00000001) -# CHECK-NEXT: ('sh_entsize', 0x00000000) -# CHECK-NEXT: ('_section_data', '03030303 03') -# CHECK-NEXT: ), -# CHECK: (('sh_name', 0x00000032) # 'test4' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK-NEXT: ('sh_flags', 0x00000000) -# CHECK-NEXT: ('sh_addr', 0x00000000) -# CHECK-NEXT: ('sh_offset', 0x00000046) -# CHECK-NEXT: ('sh_size', 0x00000003) -# CHECK-NEXT: ('sh_link', 0x00000000) -# CHECK-NEXT: ('sh_info', 0x00000000) -# CHECK-NEXT: ('sh_addralign', 0x00000001) -# CHECK-NEXT: ('sh_entsize', 0x00000000) -# CHECK-NEXT: ('_section_data', '040404') -# CHECK-NEXT: ), -# CHECK: (('sh_name', 0x0000002c) # 'test5' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK-NEXT: ('sh_flags', 0x00000000) -# CHECK-NEXT: ('sh_addr', 0x00000000) -# CHECK-NEXT: ('sh_offset', 0x00000049) -# CHECK-NEXT: ('sh_size', 0x00000001) -# CHECK-NEXT: ('sh_link', 0x00000000) -# CHECK-NEXT: ('sh_info', 0x00000000) -# CHECK-NEXT: ('sh_addralign', 0x00000001) -# CHECK-NEXT: ('sh_entsize', 0x00000000) -# CHECK-NEXT: ('_section_data', '05') -# CHECK-NEXT: ), + +# CHECK: Sections [ +# CHECK: Section { +# CHECK: Name: test1 (68) +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x0) +# CHECK-NEXT: ] +# CHECK-NEXT: Address: 0x0 +# CHECK-NEXT: Offset: 0x34 +# CHECK-NEXT: Size: 7 +# CHECK-NEXT: Link: 0 +# CHECK-NEXT: Info: 0 +# CHECK-NEXT: AddressAlignment: 1 +# CHECK-NEXT: EntrySize: 0 +# CHECK-NEXT: SectionData ( +# CHECK-NEXT: 0000: 01010101 010101 +# CHECK-NEXT: ) +# CHECK-NEXT: } +# CHECK: Section { +# CHECK: Name: test2 (62) +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x0) +# CHECK-NEXT: ] +# CHECK-NEXT: Address: 0x0 +# CHECK-NEXT: Offset: 0x3B +# CHECK-NEXT: Size: 6 +# CHECK-NEXT: Link: 0 +# CHECK-NEXT: Info: 0 +# CHECK-NEXT: AddressAlignment: 1 +# CHECK-NEXT: EntrySize: 0 +# CHECK-NEXT: SectionData ( +# CHECK-NEXT: 0000: 02020202 0202 +# CHECK-NEXT: ) +# CHECK-NEXT: } +# CHECK: Section { +# CHECK: Name: test3 (56) +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x0) +# CHECK-NEXT: ] +# CHECK-NEXT: Address: 0x0 +# CHECK-NEXT: Offset: 0x41 +# CHECK-NEXT: Size: 5 +# CHECK-NEXT: Link: 0 +# CHECK-NEXT: Info: 0 +# CHECK-NEXT: AddressAlignment: 1 +# CHECK-NEXT: EntrySize: 0 +# CHECK-NEXT: SectionData ( +# CHECK-NEXT: 0000: 03030303 03 +# CHECK-NEXT: ) +# CHECK-NEXT: } +# CHECK: Section { +# CHECK: Name: test4 (50) +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x0) +# CHECK-NEXT: ] +# CHECK-NEXT: Address: 0x0 +# CHECK-NEXT: Offset: 0x46 +# CHECK-NEXT: Size: 3 +# CHECK-NEXT: Link: 0 +# CHECK-NEXT: Info: 0 +# CHECK-NEXT: AddressAlignment: 1 +# CHECK-NEXT: EntrySize: 0 +# CHECK-NEXT: SectionData ( +# CHECK-NEXT: 0000: 040404 +# CHECK-NEXT: ) +# CHECK-NEXT: } +# CHECK: Section { +# CHECK: Name: test5 (44) +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK-NEXT: Flags [ (0x0) +# CHECK-NEXT: ] +# CHECK-NEXT: Address: 0x0 +# CHECK-NEXT: Offset: 0x49 +# CHECK-NEXT: Size: 1 +# CHECK-NEXT: Link: 0 +# CHECK-NEXT: Info: 0 +# CHECK-NEXT: AddressAlignment: 1 +# CHECK-NEXT: EntrySize: 0 +# CHECK-NEXT: SectionData ( +# CHECK-NEXT: 0000: 05 +# CHECK-NEXT: ) +# CHECK-NEXT: } diff --git a/test/MC/AsmParser/section_names.s b/test/MC/AsmParser/section_names.s index 332cdbe3fed5..3883e15880a5 100644 --- a/test/MC/AsmParser/section_names.s +++ b/test/MC/AsmParser/section_names.s @@ -1,5 +1,5 @@ # RUN: llvm-mc -triple i386-pc-linux-gnu -filetype=obj -o %t %s -# RUN: elf-dump --dump-section-data < %t | FileCheck %s +# RUN: llvm-readobj -s < %t | FileCheck %s .section .nobits .byte 1 .section .nobits2 @@ -30,33 +30,33 @@ .byte 1 .section .notefoo .byte 1 -# CHECK: (('sh_name', 0x00000{{...}}) # '.nobits' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.nobits2' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.nobitsfoo' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.init_array' -# CHECK-NEXT: ('sh_type', 0x0000000e) -# CHECK: (('sh_name', 0x00000{{...}}) # '.init_array2' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.init_arrayfoo' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.fini_array' -# CHECK-NEXT: ('sh_type', 0x0000000f) -# CHECK: (('sh_name', 0x00000{{...}}) # '.fini_array2' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.fini_arrayfoo' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.preinit_array' -# CHECK-NEXT: ('sh_type', 0x00000010) -# CHECK: (('sh_name', 0x00000{{...}}) # '.preinit_array2' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.preinit_arrayfoo' -# CHECK-NEXT: ('sh_type', 0x00000001) -# CHECK: (('sh_name', 0x00000{{...}}) # '.note' -# CHECK-NEXT: ('sh_type', 0x00000007) -# CHECK: (('sh_name', 0x00000{{...}}) # '.note2' -# CHECK-NEXT: ('sh_type', 0x00000007) -#CHECK: (('sh_name', 0x00000{{...}}) # '.notefoo' -# CHECK-NEXT: ('sh_type', 0x00000007) +# CHECK: Name: .nobits +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .nobits2 +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .nobitsfoo +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .init_array +# CHECK-NEXT: Type: SHT_INIT_ARRAY +# CHECK: Name: .init_array2 +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .init_arrayfoo +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .fini_array +# CHECK-NEXT: Type: SHT_FINI_ARRAY +# CHECK: Name: .fini_array2 +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .fini_arrayfoo +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .preinit_array +# CHECK-NEXT: Type: SHT_PREINIT_ARRAY +# CHECK: Name: .preinit_array2 +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .preinit_arrayfoo +# CHECK-NEXT: Type: SHT_PROGBITS +# CHECK: Name: .note +# CHECK-NEXT: Type: SHT_NOTE +# CHECK: Name: .note2 +# CHECK-NEXT: Type: SHT_NOTE +# CHECK: Name: .notefoo +# CHECK-NEXT: Type: SHT_NOTE diff --git a/test/MC/COFF/align-nops.s b/test/MC/COFF/align-nops.s index 2971ec67798e..02b488475e90 100644 --- a/test/MC/COFF/align-nops.s +++ b/test/MC/COFF/align-nops.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s -o - | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s -sd | FileCheck %s // Test that we get optimal nops in text .text @@ -15,36 +15,40 @@ f0: .long 0 .align 8 -//CHECK: Name = .text -//CHECK-NEXT: VirtualSize -//CHECK-NEXT: VirtualAddress -//CHECK-NEXT: SizeOfRawData = 16 -//CHECK-NEXT: PointerToRawData -//CHECK-NEXT: PointerToRelocations -//CHECK-NEXT: PointerToLineNumbers -//CHECK-NEXT: NumberOfRelocations -//CHECK-NEXT: NumberOfLineNumbers -//CHECK-NEXT: Charateristics = 0x60400020 -//CHECK-NEXT: IMAGE_SCN_CNT_CODE +//CHECK: Name: .text +//CHECK-NEXT: VirtualSize +//CHECK-NEXT: VirtualAddress +//CHECK-NEXT: RawDataSize: 16 +//CHECK-NEXT: PointerToRawData +//CHECK-NEXT: PointerToRelocations +//CHECK-NEXT: PointerToLineNumbers +//CHECK-NEXT: RelocationCount +//CHECK-NEXT: LineNumberCount +//CHECK-NEXT: Characteristics [ (0x60400020) //CHECK-NEXT: IMAGE_SCN_ALIGN_8BYTES +//CHECK-NEXT: IMAGE_SCN_CNT_CODE //CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE //CHECK-NEXT: IMAGE_SCN_MEM_READ -//CHECK-NEXT: SectionData = -//CHECK-NEXT: 00 00 00 00 0F 1F 40 00 - 00 00 00 00 0F 1F 40 00 +//CHECK-NEXT: ] +//CHECK-NEXT: SectionData ( +//CHECK-NEXT: 0000: 00000000 0F1F4000 00000000 0F1F4000 +//CHECK-NEXT: ) -//CHECK: Name = .data -//CHECK-NEXT: VirtualSize -//CHECK-NEXT: VirtualAddress -//CHECK-NEXT: SizeOfRawData = 16 -//CHECK-NEXT: PointerToRawData -//CHECK-NEXT: PointerToRelocations -//CHECK-NEXT: PointerToLineNumbers -//CHECK-NEXT: NumberOfRelocations -//CHECK-NEXT: NumberOfLineNumbers -//CHECK-NEXT: Charateristics = 0xC0400040 -//CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA -//CHECK-NEXT: IMAGE_SCN_ALIGN_8BYTES -//CHECK-NEXT: IMAGE_SCN_MEM_READ -//CHECK-NEXT: IMAGE_SCN_MEM_WRITE -//CHECK-NEXT: SectionData = -//CHECK-NEXT: 00 00 00 00 90 90 90 90 - 00 00 00 00 00 00 00 00 +//CHECK: Name: .data +//CHECK-NEXT: VirtualSize: +//CHECK-NEXT: VirtualAddress: +//CHECK-NEXT: RawDataSize: 16 +//CHECK-NEXT: PointerToRawData: +//CHECK-NEXT: PointerToRelocations: +//CHECK-NEXT: PointerToLineNumbers: +//CHECK-NEXT: RelocationCount: +//CHECK-NEXT: LineNumberCount: +//CHECK-NEXT: Characteristics [ (0xC0400040) +//CHECK-NEXT: IMAGE_SCN_ALIGN_8BYTES +//CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +//CHECK-NEXT: IMAGE_SCN_MEM_READ +//CHECK-NEXT: IMAGE_SCN_MEM_WRITE +//CHECK-NEXT: ] +//CHECK-NEXT: SectionData ( +//CHECK-NEXT: 0000: 00000000 90909090 00000000 00000000 +//CHECK-NEXT: ) diff --git a/test/MC/COFF/basic-coff-64.s b/test/MC/COFF/basic-coff-64.s new file mode 100644 index 000000000000..89d17452d0d7 --- /dev/null +++ b/test/MC/COFF/basic-coff-64.s @@ -0,0 +1,137 @@ +// This test checks that the COFF object emitter works for the most basic +// programs. + +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -h -s -sr -sd -t | FileCheck %s + +.def _main; + .scl 2; + .type 32; + .endef + .text + .globl _main + .align 16, 0x90 +_main: # @main +# BB#0: # %entry + subl $4, %esp + movl $.L_.str, (%esp) + call _printf + xorl %eax, %eax + addl $4, %esp + ret + + .data +.L_.str: # @.str + .asciz "Hello World" + +// CHECK: ImageFileHeader { +// CHECK: Machine: IMAGE_FILE_MACHINE_AMD64 +// CHECK: SectionCount: 2 +// CHECK: TimeDateStamp: {{[0-9]+}} +// CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} +// CHECK: SymbolCount: 6 +// CHECK: OptionalHeaderSize: 0 +// CHECK: Characteristics [ (0x0) +// CHECK: ] +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Number: [[TextNum:[0-9]+]] +// CHECK: Name: .text +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: [[TextSize:[0-9]+]] +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 2 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0x60500020) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: ] +// CHECK: Relocations [ +// CHECK: 0x{{[0-9A-F]+}} IMAGE_REL_AMD64_ADDR32 .data +// CHECK: 0x{{[0-9A-F]+}} IMAGE_REL_AMD64_REL32 _printf +// CHECK: ] +// CHECK: } +// CHECK: Section { +// CHECK: Number: [[DataNum:[0-9]+]] +// CHECK: Name: .data +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: [[DataSize:[0-9]+]] +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x0 +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0xC0300040) +// CHECK: IMAGE_SCN_ALIGN_4BYTES +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: ] +// CHECK: Relocations [ +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 48656C6C 6F20576F 726C6400 |Hello World.| +// CHECK: ) +// CHECK: } +// CHECK: ] +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Name: .text +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: [[TextSize]] +// CHECK: RelocationCount: 2 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: [[TextNum]] +// CHECK: Selection: 0x0 +// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: .data +// CHECK: Value: 0 +// CHECK: Section: .data +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: [[DataSize]] +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: [[DataNum]] +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) +// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _main +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Function +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _printf +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: ] diff --git a/test/MC/COFF/basic-coff.s b/test/MC/COFF/basic-coff.s index 23156b82d2e5..9b299707a130 100644 --- a/test/MC/COFF/basic-coff.s +++ b/test/MC/COFF/basic-coff.s @@ -1,8 +1,7 @@ // This test checks that the COFF object emitter works for the most basic // programs. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s -// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -h -s -sr -sd -t | FileCheck %s .def _main; .scl 2; @@ -15,119 +14,124 @@ _main: # @main # BB#0: # %entry subl $4, %esp movl $L_.str, (%esp) - calll _printf + call _printf xorl %eax, %eax addl $4, %esp ret .data L_.str: # @.str - .asciz "Hello World" + .asciz "Hello World" -// CHECK: { -// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C) -// CHECK: NumberOfSections = 2 -// CHECK: TimeDateStamp = {{[0-9]+}} -// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}} -// CHECK: NumberOfSymbols = 6 -// CHECK: SizeOfOptionalHeader = 0 -// CHECK: Characteristics = 0x0 -// CHECK: Sections = [ -// CHECK: 1 = { -// CHECK: Name = .text -// CHECK: VirtualSize = 0 -// CHECK: VirtualAddress = 0 -// CHECK: SizeOfRawData = {{[0-9]+}} -// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} -// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}} -// CHECK: PointerToLineNumbers = 0x0 -// CHECK: NumberOfRelocations = 2 -// CHECK: NumberOfLineNumbers = 0 -// CHECK: Charateristics = 0x60500020 -// CHECK: IMAGE_SCN_CNT_CODE -// CHECK: IMAGE_SCN_ALIGN_16BYTES -// CHECK: IMAGE_SCN_MEM_EXECUTE -// CHECK: IMAGE_SCN_MEM_READ -// CHECK: SectionData = -// CHECK: Relocations = [ -// CHECK: 0 = { -// CHECK: VirtualAddress = 0x{{[0-9A-F]+}} -// CHECK: SymbolTableIndex = 2 -// CHECK: Type = IMAGE_REL_I386_DIR32 (6) -// CHECK: SymbolName = .data -// CHECK: } -// CHECK: 1 = { -// CHECK: VirtualAddress = 0x{{[0-9A-F]+}} -// CHECK: SymbolTableIndex = 5 -// CHECK: Type = IMAGE_REL_I386_REL32 (20) -// CHECK: SymbolName = _printf -// CHECK: } -// CHECK: ] -// CHECK: } -// CHECK: 2 = { -// CHECK: Name = .data -// CHECK: VirtualSize = 0 -// CHECK: VirtualAddress = 0 -// CHECK: SizeOfRawData = {{[0-9]+}} -// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} -// CHECK: PointerToRelocations = 0x0 -// CHECK: PointerToLineNumbers = 0x0 -// CHECK: NumberOfRelocations = 0 -// CHECK: NumberOfLineNumbers = 0 -// CHECK: Charateristics = 0xC0300040 -// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA -// CHECK: IMAGE_SCN_ALIGN_4BYTES -// CHECK: IMAGE_SCN_MEM_READ -// CHECK: IMAGE_SCN_MEM_WRITE -// CHECK: SectionData = -// CHECK: 48 65 6C 6C 6F 20 57 6F - 72 6C 64 00 |Hello World.| -// CHECK: Relocations = None -// CHECK: } +// CHECK: ImageFileHeader { +// CHECK: Machine: IMAGE_FILE_MACHINE_I386 +// CHECK: SectionCount: 2 +// CHECK: TimeDateStamp: {{[0-9]+}} +// CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} +// CHECK: SymbolCount: 6 +// CHECK: OptionalHeaderSize: 0 +// CHECK: Characteristics [ (0x0) // CHECK: ] -// CHECK: Symbols = [ -// CHECK: 0 = { -// CHECK: Name = .text -// CHECK: Value = 0 -// CHECK: SectionNumber = 1 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) -// CHECK: NumberOfAuxSymbols = 1 -// CHECK: AuxillaryData = -// CHECK: 15 00 00 00 02 00 00 00 - 00 00 00 00 01 00 00 00 |................| -// CHECK: 00 00 |..| -// CHECK: } -// CHECK: 2 = { -// CHECK: Name = .data -// CHECK: Value = 0 -// CHECK: SectionNumber = 2 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) -// CHECK: NumberOfAuxSymbols = 1 -// CHECK: AuxillaryData = -// CHECK: 0C 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |................| -// CHECK: 00 00 |..| -// CHECK: } -// CHECK: 4 = { -// CHECK: Name = _main -// CHECK: Value = 0 -// CHECK: SectionNumber = 1 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) -// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK: NumberOfAuxSymbols = 0 -// CHECK: AuxillaryData = +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Number: [[TextNum:[0-9]+]] +// CHECK: Name: .text +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 2 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0x60500020) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: ] +// CHECK: Relocations [ +// CHECK: 0x{{[0-9A-F]+}} IMAGE_REL_I386_DIR32 .data +// CHECK: 0x{{[0-9A-F]+}} IMAGE_REL_I386_REL32 _printf +// CHECK: ] +// CHECK: } +// CHECK: Section { +// CHECK: Number: [[DataNum:[0-9]+]] +// CHECK: Name: .data +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x0 +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0xC0300040) +// CHECK: IMAGE_SCN_ALIGN_4BYTES +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: ] +// CHECK: Relocations [ +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 48656C6C 6F20576F 726C6400 |Hello World.| +// CHECK: ) +// CHECK: } +// CHECK: ] +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Name: .text +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 21 +// CHECK: RelocationCount: 2 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 1 +// CHECK: Selection: 0x0 // CHECK: } -// CHECK: 5 = { -// CHECK: Name = _printf -// CHECK: Value = 0 -// CHECK: SectionNumber = 0 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK: NumberOfAuxSymbols = 0 -// CHECK: AuxillaryData = +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: .data +// CHECK: Value: 0 +// CHECK: Section: .data +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 12 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 2 +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) // CHECK: } -// CHECK: ] -// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _main +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Function +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _printf +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: ] diff --git a/test/MC/COFF/bss.s b/test/MC/COFF/bss.s index 3bed13d4aac9..86294c18683e 100644 --- a/test/MC/COFF/bss.s +++ b/test/MC/COFF/bss.s @@ -1,7 +1,7 @@ // The purpose of this test is to verify that bss sections are emited correctly. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -s | FileCheck %s .bss .globl _g0 @@ -9,7 +9,7 @@ _g0: .long 0 -// CHECK: Name = .bss -// CHECK-NEXT: VirtualSize = 0 -// CHECK-NEXT: VirtualAddress = 0 -// CHECK-NEXT: SizeOfRawData = 4 +// CHECK: Name: .bss +// CHECK-NEXT: VirtualSize: 0 +// CHECK-NEXT: VirtualAddress: 0 +// CHECK-NEXT: RawDataSize: 4 diff --git a/test/MC/COFF/diff.s b/test/MC/COFF/diff.s index aa683f26a7b1..820272a40bf4 100644 --- a/test/MC/COFF/diff.s +++ b/test/MC/COFF/diff.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-mingw32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-mingw32 %s | llvm-readobj -s -sr -sd | FileCheck %s .def _foobar; .scl 2; @@ -21,26 +21,12 @@ _rust_crate: .long _foobar-_rust_crate .long _foobar-_rust_crate -// CHECK: Name = .data -// CHECK: SectionData = -// CHECK-NEXT: 00 00 00 00 00 00 00 00 - 1C 00 00 00 20 00 00 00 |............ ...| -// CHECK: Relocations = [ -// CHECK-NEXT: 0 = { -// CHECK-NEXT: VirtualAddress = 0x4 -// CHECK-NEXT: SymbolTableIndex = -// CHECK-NEXT: Type = IMAGE_REL_I386_DIR32 (6) -// CHECK-NEXT: SymbolName = _foobar -// CHECK-NEXT: } -// CHECK-NEXT: 1 = { -// CHECK-NEXT: VirtualAddress = 0x8 -// CHECK-NEXT: SymbolTableIndex = 0 -// CHECK-NEXT: Type = IMAGE_REL_I386_REL32 (20) -// CHECK-NEXT: SymbolName = .text -// CHECK-NEXT: } -// CHECK-NEXT: 2 = { -// CHECK-NEXT: VirtualAddress = 0xC -// CHECK-NEXT: SymbolTableIndex = 0 -// CHECK-NEXT: Type = IMAGE_REL_I386_REL32 (20) -// CHECK-NEXT: SymbolName = .text -// CHECK-NEXT: } -// CHECK-NEXT: ] +// CHECK: Name: .data +// CHECK: Relocations [ +// CHECK-NEXT: 0x4 IMAGE_REL_I386_DIR32 _foobar +// CHECK-NEXT: 0x8 IMAGE_REL_I386_REL32 .text +// CHECK-NEXT: 0xC IMAGE_REL_I386_REL32 .text +// CHECK-NEXT: ] +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 00000000 00000000 1C000000 20000000 +// CHECK-NEXT: ) diff --git a/test/MC/COFF/linker-options.ll b/test/MC/COFF/linker-options.ll new file mode 100755 index 000000000000..de119417447e --- /dev/null +++ b/test/MC/COFF/linker-options.ll @@ -0,0 +1,21 @@ +; RUN: llc -O0 -mtriple=i386-pc-win32 -filetype=asm -o - %s | FileCheck %s + +!0 = metadata !{ i32 6, metadata !"Linker Options", + metadata !{ + metadata !{ metadata !"/DEFAULTLIB:msvcrt.lib" }, + metadata !{ metadata !"/DEFAULTLIB:msvcrt.lib", + metadata !"/DEFAULTLIB:secur32.lib" }, + metadata !{ metadata !"/with spaces" } } } + +!llvm.module.flags = !{ !0 } + +define dllexport void @foo() { + ret void +} + +; CHECK: .section .drectve,"r" +; CHECK: .ascii " /DEFAULTLIB:msvcrt.lib" +; CHECK: .ascii " /DEFAULTLIB:msvcrt.lib" +; CHECK: .ascii " /DEFAULTLIB:secur32.lib" +; CHECK: .ascii " \"/with spaces\"" +; CHECK: .ascii " /EXPORT:_foo" diff --git a/test/MC/COFF/module-asm.ll b/test/MC/COFF/module-asm.ll index 9c6d00d2f503..bf14dc695b58 100644 --- a/test/MC/COFF/module-asm.ll +++ b/test/MC/COFF/module-asm.ll @@ -1,26 +1,28 @@ ; The purpose of this test is to verify that various module level assembly ; constructs work. -; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | coff-dump.py | FileCheck %s -; RUN: llc -filetype=obj -mtriple x86_64-pc-win32 %s -o - | coff-dump.py | FileCheck %s +; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | llvm-readobj -s -sd | FileCheck %s +; RUN: llc -filetype=obj -mtriple x86_64-pc-win32 %s -o - | llvm-readobj -s -sd | FileCheck %s module asm ".text" module asm "_foo:" module asm " ret" -; CHECK: Name = .text -; CHECK-NEXT: VirtualSize = 0 -; CHECK-NEXT: VirtualAddress = 0 -; CHECK-NEXT: SizeOfRawData = {{[0-9]+}} -; CHECK-NEXT: PointerToRawData = 0x{{[0-9A-F]+}} -; CHECK-NEXT: PointerToRelocations = 0x{{[0-9A-F]+}} -; CHECK-NEXT: PointerToLineNumbers = 0x0 -; CHECK-NEXT: NumberOfRelocations = 0 -; CHECK-NEXT: NumberOfLineNumbers = 0 -; CHECK-NEXT: Charateristics = 0x60300020 -; CHECK-NEXT: IMAGE_SCN_CNT_CODE +; CHECK: Name: .text +; CHECK-NEXT: VirtualSize: 0 +; CHECK-NEXT: VirtualAddress: 0 +; CHECK-NEXT: RawDataSize: {{[0-9]+}} +; CHECK-NEXT: PointerToRawData: 0x{{[0-9A-F]+}} +; CHECK-NEXT: PointerToRelocations: 0x{{[0-9A-F]+}} +; CHECK-NEXT: PointerToLineNumbers: 0x0 +; CHECK-NEXT: RelocationCount: 0 +; CHECK-NEXT: LineNumberCount: 0 +; CHECK-NEXT: Characteristics [ (0x60300020) ; CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +; CHECK-NEXT: IMAGE_SCN_CNT_CODE ; CHECK-NEXT: IMAGE_SCN_MEM_EXECUTE ; CHECK-NEXT: IMAGE_SCN_MEM_READ -; CHECK-NEXT: SectionData = -; CHECK-NEXT: C3 +; CHECK-NEXT: ] +; CHECK-NEXT: SectionData ( +; CHECK-NEXT: 0000: C3 +; CHECK-NEXT: ) diff --git a/test/MC/COFF/relocation-imgrel.s b/test/MC/COFF/relocation-imgrel.s new file mode 100644 index 000000000000..ccd19ee318b6 --- /dev/null +++ b/test/MC/COFF/relocation-imgrel.s @@ -0,0 +1,29 @@ +// COFF Image-relative relocations +// +// Test that we produce image-relative relocations (IMAGE_REL_I386_DIR32NB +// and IMAGE_REL_AMD64_ADDR32NB) when accessing foo@imgrel. + +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -r | FileCheck --check-prefix=W32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -r | FileCheck --check-prefix=W64 %s + +.data +foo: + .long 1 + +.text + mov foo@IMGREL(%ebx, %ecx, 4), %eax + mov foo@imgrel(%ebx, %ecx, 4), %eax + +// W32: Relocations [ +// W32-NEXT: Section (1) .text { +// W32-NEXT: 0x3 IMAGE_REL_I386_DIR32NB foo +// W32-NEXT: 0xA IMAGE_REL_I386_DIR32NB foo +// W32-NEXT: } +// W32-NEXT: ] + +// W64: Relocations [ +// W64-NEXT: Section (1) .text { +// W64-NEXT: 0x4 IMAGE_REL_AMD64_ADDR32NB foo +// W64-NEXT: 0xC IMAGE_REL_AMD64_ADDR32NB foo +// W64-NEXT: } +// W64-NEXT: ] diff --git a/test/MC/COFF/secrel-variant.s b/test/MC/COFF/secrel-variant.s new file mode 100644 index 000000000000..1061bd404eaa --- /dev/null +++ b/test/MC/COFF/secrel-variant.s @@ -0,0 +1,19 @@ +// COFF section-relative relocations + +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -r | FileCheck %s + +.data +values: + .long 1 + .long 0 + +.text + movq values@SECREL32(%rax), %rcx + movq values@SECREL32+8(%rax), %rax + +// CHECK: Relocations [ +// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: 0x3 IMAGE_REL_AMD64_SECREL values +// CHECK-NEXT: 0xA IMAGE_REL_AMD64_SECREL values +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/COFF/secrel32.s b/test/MC/COFF/secrel32.s index ce148db9000c..deadfe09e0e4 100644 --- a/test/MC/COFF/secrel32.s +++ b/test/MC/COFF/secrel32.s @@ -1,14 +1,10 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s -sr | FileCheck %s // check that we produce the correct relocation for .secrel32 Lfoo: .secrel32 Lfoo -// CHECK: Relocations = [ -// CHECK-NEXT: 0 = { -// CHECK-NEXT: VirtualAddress = 0x0 -// CHECK-NEXT: SymbolTableIndex = 0 -// CHECK-NEXT: Type = IMAGE_REL_I386_SECREL (11) -// CHECK-NEXT: SymbolName = .text -// CHECK-NEXT: } +// CHECK: Relocations [ +// CHECK-NEXT: 0x0 IMAGE_REL_I386_SECREL .text +// CHECK-NEXT: ] diff --git a/test/MC/COFF/seh-section.s b/test/MC/COFF/seh-section.s index 802cba5e6b31..7f05cc372e07 100644 --- a/test/MC/COFF/seh-section.s +++ b/test/MC/COFF/seh-section.s @@ -1,24 +1,26 @@ // This test ensures that, if the section containing a function has a suffix // (e.g. .text$foo), its unwind info section also has a suffix (.xdata$foo). -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -s -sd | FileCheck %s // XFAIL: * -// CHECK: Name = .xdata$foo +// CHECK: Name: .xdata$foo // CHECK-NEXT: VirtualSize // CHECK-NEXT: VirtualAddress -// CHECK-NEXT: SizeOfRawData = 8 +// CHECK-NEXT: RawDataSize: 8 // CHECK-NEXT: PointerToRawData // CHECK-NEXT: PointerToRelocations // CHECK-NEXT: PointerToLineNumbers -// CHECK-NEXT: NumberOfRelocations = 0 -// CHECK-NEXT: NumberOfLineNumbers = 0 -// CHECK-NEXT: Charateristics -// CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK-NEXT: RelocationCount: 0 +// CHECK-NEXT: LineNumberCount: 0 +// CHECK-NEXT: Characteristics [ // CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES +// CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA // CHECK-NEXT: IMAGE_SCN_MEM_READ // CHECK-NEXT: IMAGE_SCN_MEM_WRITE -// CHECK-NEXT: SectionData -// CHECK-NEXT: 01 05 02 00 05 50 04 02 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 01050200 05500402 +// CHECK-NEXT: ) .section .text$foo,"x" .globl foo diff --git a/test/MC/COFF/seh.s b/test/MC/COFF/seh.s index 3f728056005b..bef425efb437 100644 --- a/test/MC/COFF/seh.s +++ b/test/MC/COFF/seh.s @@ -1,24 +1,105 @@ // This test checks that the SEH directives emit the correct unwind data. -// RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | coff-dump.py | FileCheck %s -// CHECK: Name = .xdata -// CHECK-NEXT: VirtualSize -// CHECK-NEXT: VirtualAddress -// CHECK-NEXT: SizeOfRawData = 52 -// CHECK-NEXT: PointerToRawData -// CHECK-NEXT: PointerToRelocations -// CHECK-NEXT: PointerToLineNumbers -// CHECK-NEXT: NumberOfRelocations = 4 -// CHECK-NEXT: NumberOfLineNumbers = 0 -// CHECK-NEXT: Charateristics -// CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA -// CHECK-NEXT: IMAGE_SCN_ALIGN_4BYTES -// CHECK-NEXT: IMAGE_SCN_MEM_READ -// CHECK-NEXT: SectionData -// CHECK-NEXT: 09 12 08 03 00 03 0F 30 - 0E 88 00 00 09 64 02 00 -// CHECK-NEXT: 04 22 00 1A 00 00 00 00 - 00 00 00 00 21 00 00 00 -// CHECK-NEXT: 00 00 00 00 1B 00 00 00 - 00 00 00 00 01 00 00 00 -// CHECK-NEXT: 00 00 00 00 +// TODO: Expected fail because SET_FPREG has a wrong offset. +// XFAIL: * +// RUN: llvm-mc -triple x86_64-pc-win32 -filetype=obj %s | llvm-readobj -s -u | FileCheck %s + +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Name: .text +// CHECK: RelocationCount: 0 +// CHECK: Characteristics [ +// CHECK-NEXT: ALIGN_4BYTES +// CHECK-NEXT: CNT_CODE +// CHECK-NEXT: MEM_EXECUTE +// CHECK-NEXT: MEM_READ +// CHECK-NEXT: ] +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .xdata +// CHECK: RawDataSize: 52 +// CHECK: RelocationCount: 4 +// CHECK: Characteristics [ +// CHECK-NEXT: ALIGN_4BYTES +// CHECK-NEXT: CNT_INITIALIZED_DATA +// CHECK-NEXT: MEM_READ +// CHECK-NEXT: ] +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .pdata +// CHECK: RelocationCount: 9 +// CHECK: Characteristics [ +// CHECK-NEXT: ALIGN_4BYTES +// CHECK-NEXT: CNT_INITIALIZED_DATA +// CHECK-NEXT: MEM_READ +// CHECK-NEXT: ] +// CHECK-NEXT: } +// CHECK-NEXT: ] + +// CHECK: UnwindInformation [ +// CHECK-NEXT: RuntimeFunction { +// CHECK-NEXT: StartAddress: [[CodeSect1:[^ ]+]] [[BeginDisp1:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: EndAddress: [[CodeSect1]] [[EndDisp1:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: UnwindInfoAddress: +// CHECK-NEXT: UnwindInfo { +// CHECK-NEXT: Version: 1 +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ExceptionHandler +// CHECK-NEXT: ] +// CHECK-NEXT: PrologSize: 18 +// CHECK-NEXT: FrameRegister: RBX +// CHECK-NEXT: FrameOffset: 0x0 +// CHECK-NEXT: UnwindCodeCount: 8 +// CHECK-NEXT: UnwindCodes [ +// CHECK-NEXT: 0x12: SET_FPREG reg=RBX, offset=0x0 +// CHECK-NEXT: 0x0F: PUSH_NONVOL reg=RBX +// CHECK-NEXT: 0x0E: SAVE_XMM128 reg=XMM8, offset=0x0 +// CHECK-NEXT: 0x09: SAVE_NONVOL reg=RSI, offset=0x10 +// CHECK-NEXT: 0x04: ALLOC_SMALL size=24 +// CHECK-NEXT: 0x00: PUSH_MACHFRAME errcode=yes +// CHECK-NEXT: ] +// CHECK-NEXT: Handler: __C_specific_handler +// CHECK-NEXT: } +// CHECK-NEXT: } +// CHECK-NEXT: RuntimeFunction { +// CHECK-NEXT: StartAddress: [[CodeSect2:[^ ]+]] [[BeginDisp2:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: EndAddress: [[CodeSect2]] [[BeginDisp2:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: UnwindInfoAddress: +// CHECK-NEXT: UnwindInfo { +// CHECK-NEXT: Version: 1 +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ChainInfo +// CHECK-NEXT: ] +// CHECK-NEXT: PrologSize: 0 +// CHECK-NEXT: FrameRegister: - +// CHECK-NEXT: FrameOffset: - +// CHECK-NEXT: UnwindCodeCount: 0 +// CHECK-NEXT: UnwindCodes [ +// CHECK-NEXT: ] +// CHECK-NEXT: Chained { +// CHECK-NEXT: StartAddress: [[CodeSect1]] [[BeginDisp1]] +// CHECK-NEXT: EndAddress: [[CodeSect1]] [[EndDisp1]] +// CHECK-NEXT: UnwindInfoAddress: +// CHECK-NEXT: } +// CHECK-NEXT: } +// CHECK-NEXT: } +// CHECK-NEXT: RuntimeFunction { +// CHECK-NEXT: StartAddress: [[CodeSect3:[^ ]+]] [[BeginDisp3:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: EndAddress: [[CodeSect3]] [[BeginDisp3:(\+0x[A-F0-9]+)?]] +// CHECK-NEXT: UnwindInfoAddress: +// CHECK-NEXT: UnwindInfo { +// CHECK-NEXT: Version: 1 +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: PrologSize: 0 +// CHECK-NEXT: FrameRegister: - +// CHECK-NEXT: FrameOffset: - +// CHECK-NEXT: UnwindCodeCount: 0 +// CHECK-NEXT: UnwindCodes [ +// CHECK-NEXT: ] +// CHECK-NEXT: } +// CHECK-NEXT: } +// CHECK-NEXT: ] .text .globl func diff --git a/test/MC/COFF/simple-fixups.s b/test/MC/COFF/simple-fixups.s index 4c9b4d44528f..2a74f21f12d0 100644 --- a/test/MC/COFF/simple-fixups.s +++ b/test/MC/COFF/simple-fixups.s @@ -1,8 +1,8 @@ // The purpose of this test is to verify that we do not produce unneeded // relocations when symbols are in the same section and we know their offset. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s -// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -s | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -s | FileCheck %s .def _foo; .scl 2; @@ -41,10 +41,9 @@ _baz: # @baz # BB#0: # %e subl $4, %esp Ltmp0: - calll _baz + call _baz addl $4, %esp ret -// CHECK: Sections = [ -// CHECK-NOT: NumberOfRelocations = {{[^0]}} -// CHECK: Symbols = [ +// CHECK: Sections [ +// CHECK-NOT: RelocationCount: {{[^0]}} diff --git a/test/MC/COFF/symbol-alias.s b/test/MC/COFF/symbol-alias.s index 4b1772ce711b..ccada3793ca3 100644 --- a/test/MC/COFF/symbol-alias.s +++ b/test/MC/COFF/symbol-alias.s @@ -1,9 +1,9 @@ // The purpose of this test is to verify that symbol aliases -// (@foo = alias <type> @bar) generate the correct entries in the symbol table. +// (@foo: alias <type> @bar) generate the correct entries in the symbol table. // They should be identical except for the name. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -t | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -t | FileCheck %s .def _foo; .scl 2; @@ -31,43 +31,43 @@ _bar_alias_alias = _bar_alias .globl _bar_alias _bar_alias = _bar -// CHECK: Name = {{_?}}foo -// CHECK-NEXT: Value = [[FOO_VALUE:.*$]] -// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER:.*$]] -// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE:.*$]] -// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE:.*$]] -// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS:.*$]] -// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS:.*$]] +// CHECK: Name: {{_?}}foo +// CHECK-NEXT: Value: [[FOO_VALUE:.*$]] +// CHECK-NEXT: Section: [[FOO_SECTION_NUMBER:.*$]] +// CHECK-NEXT: BaseType: [[FOO_SIMPLE_TYPE:.*$]] +// CHECK-NEXT: ComplexType: [[FOO_COMPLEX_TYPE:.*$]] +// CHECK-NEXT: StorageClass: [[FOO_STORAGE_CLASS:.*$]] +// CHECK-NEXT: AuxSymbolCount: [[FOO_NUMBER_OF_AUX_SYMBOLS:.*$]] -// CHECK: Name = {{_?}}bar -// CHECK-NEXT: Value = [[BAR_VALUE:.*$]] -// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER:.*$]] -// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE:.*$]] -// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE:.*$]] -// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS:.*$]] -// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS:.*$]] +// CHECK: Name: {{_?}}bar +// CHECK-NEXT: Value: [[BAR_VALUE:.*$]] +// CHECK-NEXT: Section: [[BAR_SECTION_NUMBER:.*$]] +// CHECK-NEXT: BaseType: [[BAR_SIMPLE_TYPE:.*$]] +// CHECK-NEXT: ComplexType: [[BAR_COMPLEX_TYPE:.*$]] +// CHECK-NEXT: StorageClass: [[BAR_STORAGE_CLASS:.*$]] +// CHECK-NEXT: AuxSymbolCount: [[BAR_NUMBER_OF_AUX_SYMBOLS:.*$]] -// CHECK: Name = {{_?}}foo_alias -// CHECK-NEXT: Value = [[FOO_VALUE]] -// CHECK-NEXT: SectionNumber = [[FOO_SECTION_NUMBER]] -// CHECK-NEXT: SimpleType = [[FOO_SIMPLE_TYPE]] -// CHECK-NEXT: ComplexType = [[FOO_COMPLEX_TYPE]] -// CHECK-NEXT: StorageClass = [[FOO_STORAGE_CLASS]] -// CHECK-NEXT: NumberOfAuxSymbols = [[FOO_NUMBER_OF_AUX_SYMBOLS]] +// CHECK: Name: {{_?}}foo_alias +// CHECK-NEXT: Value: [[FOO_VALUE]] +// CHECK-NEXT: Section: [[FOO_SECTION_NUMBER]] +// CHECK-NEXT: BaseType: [[FOO_SIMPLE_TYPE]] +// CHECK-NEXT: ComplexType: [[FOO_COMPLEX_TYPE]] +// CHECK-NEXT: StorageClass: [[FOO_STORAGE_CLASS]] +// CHECK-NEXT: AuxSymbolCount: [[FOO_NUMBER_OF_AUX_SYMBOLS]] -// CHECK: Name = {{_?}}bar_alias_alias -// CHECK-NEXT: Value = [[BAR_VALUE]] -// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER]] -// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE]] -// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE]] -// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS]] -// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS]] +// CHECK: Name: {{_?}}bar_alias_alias +// CHECK-NEXT: Value: [[BAR_VALUE]] +// CHECK-NEXT: Section: [[BAR_SECTION_NUMBER]] +// CHECK-NEXT: BaseType: [[BAR_SIMPLE_TYPE]] +// CHECK-NEXT: ComplexType: [[BAR_COMPLEX_TYPE]] +// CHECK-NEXT: StorageClass: [[BAR_STORAGE_CLASS]] +// CHECK-NEXT: AuxSymbolCount: [[BAR_NUMBER_OF_AUX_SYMBOLS]] -// CHECK: Name = {{_?}}bar_alias -// CHECK-NEXT: Value = [[BAR_VALUE]] -// CHECK-NEXT: SectionNumber = [[BAR_SECTION_NUMBER]] -// CHECK-NEXT: SimpleType = [[BAR_SIMPLE_TYPE]] -// CHECK-NEXT: ComplexType = [[BAR_COMPLEX_TYPE]] -// CHECK-NEXT: StorageClass = [[BAR_STORAGE_CLASS]] -// CHECK-NEXT: NumberOfAuxSymbols = [[BAR_NUMBER_OF_AUX_SYMBOLS]] +// CHECK: Name: {{_?}}bar_alias +// CHECK-NEXT: Value: [[BAR_VALUE]] +// CHECK-NEXT: Section: [[BAR_SECTION_NUMBER]] +// CHECK-NEXT: BaseType: [[BAR_SIMPLE_TYPE]] +// CHECK-NEXT: ComplexType: [[BAR_COMPLEX_TYPE]] +// CHECK-NEXT: StorageClass: [[BAR_STORAGE_CLASS]] +// CHECK-NEXT: AuxSymbolCount: [[BAR_NUMBER_OF_AUX_SYMBOLS]] diff --git a/test/MC/COFF/symbol-fragment-offset-64.s b/test/MC/COFF/symbol-fragment-offset-64.s new file mode 100644 index 000000000000..b8244709aa75 --- /dev/null +++ b/test/MC/COFF/symbol-fragment-offset-64.s @@ -0,0 +1,168 @@ +// The purpose of this test is to see if the COFF object writer is emitting the +// proper relocations for multiple pieces of data in a single data fragment. + +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -h -s -sr -sd -t | FileCheck %s + +.def _main; + .scl 2; + .type 32; + .endef + .text + .globl _main + .align 16, 0x90 +_main: # @main +# BB#0: # %entry + subl $4, %esp + movl $.L_.str0, (%esp) + callq _printf + movl $.L_.str1, (%esp) + callq _puts + movl $.L_.str2, (%esp) + callq _puts + xorl %eax, %eax + addl $4, %esp + ret + + .data +.L_.str0: # @.str0 + .asciz "Hello " + +.L_.str1: # @.str1 + .asciz "World!" + + .align 16 # @.str2 +.L_.str2: + .asciz "I'm The Last Line." + +// CHECK: { +// CHECK: Machine: IMAGE_FILE_MACHINE_AMD64 +// CHECK: SectionCount: 2 +// CHECK: TimeDateStamp: {{[0-9]+}} +// CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} +// CHECK: SymbolCount: 7 +// CHECK: OptionalHeaderSize: 0 +// CHECK: Characteristics [ (0x0) +// CHECK: ] +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Number: 1 +// CHECK: Name: .text +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 6 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0x60500020) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: ] +// CHECK: Relocations [ +// CHECK: 0x7 IMAGE_REL_AMD64_ADDR32 .data +// CHECK: 0xC IMAGE_REL_AMD64_REL32 _printf +// CHECK: 0x14 IMAGE_REL_AMD64_ADDR32 .data +// CHECK: 0x19 IMAGE_REL_AMD64_REL32 _puts +// CHECK: 0x21 IMAGE_REL_AMD64_ADDR32 .data +// CHECK: 0x26 IMAGE_REL_AMD64_REL32 _puts +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 83EC0467 C7042400 000000E8 00000000 +// CHECK: 0010: 67C70424 07000000 E8000000 0067C704 +// CHECK: 0020: 24100000 00E80000 000031C0 83C404C3 +// CHECK: ) +// CHECK: } +// CHECK: Section { +// CHECK: Number: 2 +// CHECK: Name: .data +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x0 +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0xC0500040) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: Relocations [ +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 48656C6C 6F200057 6F726C64 21000000 |Hello .World!...| +// CHECK: 0010: 49276D20 54686520 4C617374 204C696E |I'm The Last Lin| +// CHECK: 0020: 652E00 |e..| +// CHECK: ) +// CHECK: } +// CHECK: ] +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Name: .text +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 48 +// CHECK: RelocationCount: 6 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 1 +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) +// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: .data +// CHECK: Value: 0 +// CHECK: Section: .data +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 35 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 2 +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) +// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _main +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Function +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _printf +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _puts +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: ] diff --git a/test/MC/COFF/symbol-fragment-offset.s b/test/MC/COFF/symbol-fragment-offset.s index 1df8baacaf22..71b1703972ab 100644 --- a/test/MC/COFF/symbol-fragment-offset.s +++ b/test/MC/COFF/symbol-fragment-offset.s @@ -1,8 +1,7 @@ // The purpose of this test is to see if the COFF object writer is emitting the // proper relocations for multiple pieces of data in a single data fragment. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | coff-dump.py | FileCheck %s -// I WOULD RUN, BUT THIS FAILS: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -h -s -sr -sd -t | FileCheck %s .def _main; .scl 2; @@ -36,152 +35,134 @@ L_.str2: .asciz "I'm The Last Line." // CHECK: { -// CHECK: MachineType = IMAGE_FILE_MACHINE_I386 (0x14C) -// CHECK: NumberOfSections = 2 -// CHECK: TimeDateStamp = {{[0-9]+}} -// CHECK: PointerToSymbolTable = 0x{{[0-9A-F]+}} -// CHECK: NumberOfSymbols = 7 -// CHECK: SizeOfOptionalHeader = 0 -// CHECK: Characteristics = 0x0 -// CHECK: Sections = [ -// CHECK: 1 = { -// CHECK: Name = .text -// CHECK: VirtualSize = 0 -// CHECK: VirtualAddress = 0 -// CHECK: SizeOfRawData = {{[0-9]+}} -// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} -// CHECK: PointerToRelocations = 0x{{[0-9A-F]+}} -// CHECK: PointerToLineNumbers = 0x0 -// CHECK: NumberOfRelocations = 6 -// CHECK: NumberOfLineNumbers = 0 -// CHECK: Charateristics = 0x60500020 -// CHECK: IMAGE_SCN_CNT_CODE -// CHECK: IMAGE_SCN_ALIGN_16BYTES -// CHECK: IMAGE_SCN_MEM_EXECUTE -// CHECK: IMAGE_SCN_MEM_READ -// CHECK: SectionData = -// CHECK: 83 EC 04 C7 04 24 00 00 - 00 00 E8 00 00 00 00 C7 |.....$..........| -// CHECK: 04 24 07 00 00 00 E8 00 - 00 00 00 C7 04 24 10 00 |.$...........$..| -// CHECK: 00 00 E8 00 00 00 00 31 - C0 83 C4 04 C3 |.......1.....| -// CHECK: Relocations = [ -// CHECK: 0 = { -// CHECK: VirtualAddress = 0x6 -// CHECK: SymbolTableIndex = 2 -// CHECK: Type = IMAGE_REL_I386_DIR32 (6) -// CHECK: SymbolName = .data -// CHECK: } -// CHECK: 1 = { -// CHECK: VirtualAddress = 0xB -// CHECK: SymbolTableIndex = 5 -// CHECK: Type = IMAGE_REL_I386_REL32 (20) -// CHECK: SymbolName = _printf -// CHECK: } -// CHECK: 2 = { -// CHECK: VirtualAddress = 0x12 -// CHECK: SymbolTableIndex = 2 -// CHECK: Type = IMAGE_REL_I386_DIR32 (6) -// CHECK: SymbolName = .data -// CHECK: } -// CHECK: 3 = { -// CHECK: VirtualAddress = 0x17 -// CHECK: SymbolTableIndex = 6 -// CHECK: Type = IMAGE_REL_I386_REL32 (20) -// CHECK: SymbolName = _puts -// CHECK: } -// CHECK: 4 = { -// CHECK: VirtualAddress = 0x1E -// CHECK: SymbolTableIndex = 2 -// CHECK: Type = IMAGE_REL_I386_DIR32 (6) -// CHECK: SymbolName = .data -// CHECK: } -// CHECK: 5 = { -// CHECK: VirtualAddress = 0x23 -// CHECK: SymbolTableIndex = 6 -// CHECK: Type = IMAGE_REL_I386_REL32 (20) -// CHECK: SymbolName = _puts -// CHECK: } -// CHECK: ] -// CHECK: } -// CHECK: 2 = { -// CHECK: Name = .data -// CHECK: VirtualSize = 0 -// CHECK: VirtualAddress = 0 -// CHECK: SizeOfRawData = {{[0-9]+}} -// CHECK: PointerToRawData = 0x{{[0-9A-F]+}} -// CHECK: PointerToRelocations = 0x0 -// CHECK: PointerToLineNumbers = 0x0 -// CHECK: NumberOfRelocations = 0 -// CHECK: NumberOfLineNumbers = 0 -// CHECK: Charateristics = 0xC0500040 -// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA -// CHECK: IMAGE_SCN_ALIGN_16BYTES -// CHECK: IMAGE_SCN_MEM_READ -// CHECK: IMAGE_SCN_MEM_WRITE -// CHECK: SectionData = -// CHECK: 48 65 6C 6C 6F 20 00 57 - 6F 72 6C 64 21 00 00 00 |Hello .World!...| -// CHECK: 49 27 6D 20 54 68 65 20 - 4C 61 73 74 20 4C 69 6E |I'm The Last Lin| -// CHECK: 65 2E 00 |e..| -// CHECK: Relocations = None -// CHECK: } +// CHECK: Machine: IMAGE_FILE_MACHINE_I386 (0x14C) +// CHECK: SectionCount: 2 +// CHECK: TimeDateStamp: {{[0-9]+}} +// CHECK: PointerToSymbolTable: 0x{{[0-9A-F]+}} +// CHECK: SymbolCount: 7 +// CHECK: OptionalHeaderSize: 0 +// CHECK: Characteristics [ (0x0) // CHECK: ] -// CHECK: Symbols = [ -// CHECK: 0 = { -// CHECK: Name = .text -// CHECK: Value = 0 -// CHECK: SectionNumber = 1 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) -// CHECK: NumberOfAuxSymbols = 1 -// CHECK: AuxillaryData = -// CHECK: 2D 00 00 00 06 00 00 00 - 00 00 00 00 01 00 00 00 |-...............| -// CHECK: 00 00 |..| - -// CHECK: } -// CHECK: 2 = { -// CHECK: Name = .data -// CHECK: Value = 0 -// CHECK: SectionNumber = 2 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_STATIC (3) -// CHECK: NumberOfAuxSymbols = 1 -// CHECK: AuxillaryData = -// CHECK: 23 00 00 00 00 00 00 00 - 00 00 00 00 02 00 00 00 |#...............| -// CHECK: 00 00 |..| - -// CHECK: } -// CHECK: 4 = { -// CHECK: Name = _main -// CHECK: Value = 0 -// CHECK: SectionNumber = 1 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_FUNCTION (2) -// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK: NumberOfAuxSymbols = 0 -// CHECK: AuxillaryData = - -// CHECK: 5 = { -// CHECK: Name = _printf -// CHECK: Value = 0 -// CHECK: SectionNumber = 0 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK: NumberOfAuxSymbols = 0 -// CHECK: AuxillaryData = - +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Number: 1 +// CHECK: Name: .text +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x{{[0-9A-F]+}} +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 6 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0x60500020) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_CODE +// CHECK: IMAGE_SCN_MEM_EXECUTE +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: ] +// CHECK: Relocations [ +// CHECK: 0x6 IMAGE_REL_I386_DIR32 .data +// CHECK: 0xB IMAGE_REL_I386_REL32 _printf +// CHECK: 0x12 IMAGE_REL_I386_DIR32 .data +// CHECK: 0x17 IMAGE_REL_I386_REL32 _puts +// CHECK: 0x1E IMAGE_REL_I386_DIR32 .data +// CHECK: 0x23 IMAGE_REL_I386_REL32 _puts +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 83EC04C7 04240000 0000E800 000000C7 |.....$..........| +// CHECK: 0010: 04240700 0000E800 000000C7 04241000 |.$...........$..| +// CHECK: 0020: 0000E800 00000031 C083C404 C3 |.......1.....| +// CHECK: ) +// CHECK: } +// CHECK: Section { +// CHECK: Number: 2 +// CHECK: Name: .data +// CHECK: VirtualSize: 0 +// CHECK: VirtualAddress: 0 +// CHECK: RawDataSize: {{[0-9]+}} +// CHECK: PointerToRawData: 0x{{[0-9A-F]+}} +// CHECK: PointerToRelocations: 0x0 +// CHECK: PointerToLineNumbers: 0x0 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Characteristics [ (0xC0500040) +// CHECK: IMAGE_SCN_ALIGN_16BYTES +// CHECK: IMAGE_SCN_CNT_INITIALIZED_DATA +// CHECK: IMAGE_SCN_MEM_READ +// CHECK: IMAGE_SCN_MEM_WRITE +// CHECK: Relocations [ +// CHECK: ] +// CHECK: SectionData ( +// CHECK: 0000: 48656C6C 6F200057 6F726C64 21000000 |Hello .World!...| +// CHECK: 0010: 49276D20 54686520 4C617374 204C696E |I'm The Last Lin| +// CHECK: 0020: 652E00 |e..| +// CHECK: ) +// CHECK: } +// CHECK: ] +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Name: .text +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 45 +// CHECK: RelocationCount: 6 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 1 +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) // CHECK: } -// CHECK: 6 = { -// CHECK: Name = _puts -// CHECK: Value = 0 -// CHECK: SectionNumber = 0 -// CHECK: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK: NumberOfAuxSymbols = 0 -// CHECK: AuxillaryData = - +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: .data +// CHECK: Value: 0 +// CHECK: Section: .data +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: Static +// CHECK: AuxSymbolCount: 1 +// CHECK: AuxSectionDef { +// CHECK: Length: 35 +// CHECK: RelocationCount: 0 +// CHECK: LineNumberCount: 0 +// CHECK: Checksum: 0x0 +// CHECK: Number: 2 +// CHECK: Selection: 0x0 +// CHECK: Unused: (00 00 00) // CHECK: } -// CHECK: ] -// CHECK: } +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _main +// CHECK: Value: 0 +// CHECK: Section: .text +// CHECK: BaseType: Null +// CHECK: ComplexType: Function +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _printf +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: Symbol { +// CHECK: Name: _puts +// CHECK: Value: 0 +// CHECK: Section: (0) +// CHECK: BaseType: Null +// CHECK: ComplexType: Null +// CHECK: StorageClass: External +// CHECK: AuxSymbolCount: 0 +// CHECK: } +// CHECK: ] diff --git a/test/MC/COFF/weak-symbol-section-specification.ll b/test/MC/COFF/weak-symbol-section-specification.ll index 5049372959fb..4772c929f29e 100644 --- a/test/MC/COFF/weak-symbol-section-specification.ll +++ b/test/MC/COFF/weak-symbol-section-specification.ll @@ -1,23 +1,25 @@ ; The purpose of this test is to verify that weak linkage type is not ignored by backend, ; if section was specialized. -; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | coff-dump.py | FileCheck %s +; RUN: llc -filetype=obj -mtriple i686-pc-win32 %s -o - | llvm-readobj -s -sd | FileCheck %s @a = weak unnamed_addr constant { i32, i32, i32 } { i32 0, i32 0, i32 0}, section ".data" -; CHECK: Name = .data$a -; CHECK-NEXT: VirtualSize = 0 -; CHECK-NEXT: VirtualAddress = 0 -; CHECK-NEXT: SizeOfRawData = {{[0-9]+}} -; CHECK-NEXT: PointerToRawData = 0x{{[0-9A-F]+}} -; CHECK-NEXT: PointerToRelocations = 0x0 -; CHECK-NEXT: PointerToLineNumbers = 0x0 -; CHECK-NEXT: NumberOfRelocations = 0 -; CHECK-NEXT: NumberOfLineNumbers = 0 -; CHECK-NEXT: Charateristics = 0x40401040 +; CHECK: Name: .data$a +; CHECK-NEXT: VirtualSize: 0 +; CHECK-NEXT: VirtualAddress: 0 +; CHECK-NEXT: RawDataSize: {{[0-9]+}} +; CHECK-NEXT: PointerToRawData: 0x{{[0-9A-F]+}} +; CHECK-NEXT: PointerToRelocations: 0x0 +; CHECK-NEXT: PointerToLineNumbers: 0x0 +; CHECK-NEXT: RelocationCount: 0 +; CHECK-NEXT: LineNumberCount: 0 +; CHECK-NEXT: Characteristics [ (0x40401040) +; CHECK-NEXT: IMAGE_SCN_ALIGN_8BYTES ; CHECK-NEXT: IMAGE_SCN_CNT_INITIALIZED_DATA ; CHECK-NEXT: IMAGE_SCN_LNK_COMDAT -; CHECK-NEXT: IMAGE_SCN_ALIGN_8BYTES ; CHECK-NEXT: IMAGE_SCN_MEM_READ -; CHECK-NEXT: SectionData = -; CHECK-NEXT: 00 00 00 00 00 00 00 00 - 00 00 00 00 +; CHECK-NEXT: ] +; CHECK-NEXT: SectionData ( +; CHECK-NEXT: 0000: 00000000 00000000 00000000 +; CHECK-NEXT: ) diff --git a/test/MC/COFF/weak.s b/test/MC/COFF/weak.s index 0f99313c9c03..b9df0f1df2fd 100644 --- a/test/MC/COFF/weak.s +++ b/test/MC/COFF/weak.s @@ -1,7 +1,8 @@ // This tests that default-null weak symbols (a GNU extension) are created // properly via the .weak directive. -// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 < %s | coff-dump.py | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-win32 %s | llvm-readobj -t | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-win32 %s | llvm-readobj -t | FileCheck %s .def _main; .scl 2; @@ -17,7 +18,7 @@ _main: # @main testl %eax, %eax je LBB0_2 # BB#1: # %if.then - calll _test_weak + call _test_weak movl $1, %eax addl $4, %esp ret @@ -28,24 +29,47 @@ LBB0_2: # %return .weak _test_weak -// CHECK: Symbols = [ + .weak _test_weak_alias + _test_weak_alias=_main -// CHECK: Name = _test_weak -// CHECK-NEXT: Value = 0 -// CHECK-NEXT: SectionNumber = 0 -// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_WEAK_EXTERNAL (105) -// CHECK-NEXT: NumberOfAuxSymbols = 1 -// CHECK-NEXT: AuxillaryData = -// CHECK-NEXT: 05 00 00 00 02 00 00 00 - 00 00 00 00 00 00 00 00 |................| -// CHECK-NEXT: 00 00 |..| +// CHECK: Symbols [ -// CHECK: Name = .weak._test_weak.default -// CHECK-NEXT: Value = 0 -// CHECK-NEXT: SectionNumber = 65535 -// CHECK-NEXT: SimpleType = IMAGE_SYM_TYPE_NULL (0) -// CHECK-NEXT: ComplexType = IMAGE_SYM_DTYPE_NULL (0) -// CHECK-NEXT: StorageClass = IMAGE_SYM_CLASS_EXTERNAL (2) -// CHECK-NEXT: NumberOfAuxSymbols = 0 -// CHECK-NEXT: AuxillaryData = +// CHECK: Symbol { +// CHECK: Name: _test_weak +// CHECK-NEXT: Value: 0 +// CHECK-NEXT: Section: (0) +// CHECK-NEXT: BaseType: Null +// CHECK-NEXT: ComplexType: Null +// CHECK-NEXT: StorageClass: WeakExternal +// CHECK-NEXT: AuxSymbolCount: 1 +// CHECK-NEXT: AuxWeakExternal { +// CHECK-NEXT: Linked: .weak._test_weak.default +// CHECK-NEXT: Search: Library +// CHECK-NEXT: Unused: (00 00 00 00 00 00 00 00 00 00) +// CHECK-NEXT: } +// CHECK-NEXT: } + +// CHECK: Symbol { +// CHECK: Name: .weak._test_weak.default +// CHECK-NEXT: Value: 0 +// CHECK-NEXT: Section: (-1) +// CHECK-NEXT: BaseType: Null +// CHECK-NEXT: ComplexType: Null +// CHECK-NEXT: StorageClass: External +// CHECK-NEXT: AuxSymbolCount: 0 +// CHECK-NEXT: } + +// CHECK: Symbol { +// CHECK: Name: _test_weak_alias +// CHECK-NEXT: Value: 0 +// CHECK-NEXT: Section: (0) +// CHECK-NEXT: BaseType: Null +// CHECK-NEXT: ComplexType: Null +// CHECK-NEXT: StorageClass: WeakExternal +// CHECK-NEXT: AuxSymbolCount: 1 +// CHECK-NEXT: AuxWeakExternal { +// CHECK-NEXT: Linked: _main +// CHECK-NEXT: Search: Library +// CHECK-NEXT: Unused: (00 00 00 00 00 00 00 00 00 00) +// CHECK-NEXT: } +// CHECK-NEXT: } diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0c9aaab38c7e..98daaa7649aa 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -51,24 +51,48 @@ # CHECKx: ldclvc p5, cr15, [r8], #-0 #0x00 0xf5 0x78 0x7c +# CHECK: ldc p13, c9, [r2, #0]! +0x00 0x9d 0xb2 0xed + +# CHECK: ldcl p1, c9, [r3, #0]! +0x00 0x91 0xf3 0xed + # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 # CHECK: ldr r5, [r7, -r10, lsl #2] 0x0a 0x51 0x17 0xe7 +# CHECK: ldr r4, [r5, #0]! +0x00 0x40 0xb5 0xe5 + +# CHECK: ldrb lr, [r10, #0]! +0x00 0xe0 0xfa 0xe5 + +# CHECK: ldrd r4, r5, [r0, #0]! +0xd0 0x40 0xe0 0xe1 + # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 # CHECK: ldrh r0, [r2] 0xb0 0x00 0xd2 0xe1 +# CHECK: ldrh lr, [sp, #0]! +0xb0 0xe0 0xfd 0xe1 + # CHECK: ldrht r0, [r2], #15 0xbf 0x00 0xf2 0xe0 +# CHECK: ldrsb r1, [lr, #0]! +0xd0 0x10 0xfe 0xe1 + # CHECK: ldrsbtvs lr, [r2], -r9 0xd9 0xe0 0x32 0x60 +# CHECK: ldrsh r9, [r1, #0] +0xf0 0x90 0xf1 0xe1 + # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 @@ -245,9 +269,27 @@ # CHECK: stc p2, c4, [r9], {157} 0x9d 0x42 0x89 0xec +# CHECK: stc p15, c0, [r3, #0]! +0x00 0x0f 0xa3 0xed + # CHECK: stc2 p2, c4, [r9], {157} 0x9d 0x42 0x89 0xfc +# CHECK: stcl p13, c12, [r9, #0]! +0x00 0xcd 0xe9 0xed + +# CHECK: str pc, [r11, #0]! +0x00 0xf0 0xab 0xe5 + +# CHECK: strb r9, [r10, #0]! +0x00 0x90 0xea 0xe5 + +# CHECK: strd r12, sp, [r6, #0]! +0xf0 0xc0 0xe6 0xe1 + +# CHECK: strh r7, [r9, #0]! +0xb0 0x70 0xe9 0xe1 + # CHECK: bne #-24 0xfa 0xff 0xff 0x1a diff --git a/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt new file mode 100644 index 000000000000..d6b7cf1a0bb5 --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-thumb-trustzone.txt @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0xff 0xf7 0x00 0x80 +0x0c 0xbf +0xf0 0xf7 0x00 0x80 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: ite eq +# TZ: smceq #0 diff --git a/test/MC/Disassembler/ARM/arm-trustzone.txt b/test/MC/Disassembler/ARM/arm-trustzone.txt new file mode 100644 index 000000000000..92d5d6b29072 --- /dev/null +++ b/test/MC/Disassembler/ARM/arm-trustzone.txt @@ -0,0 +1,16 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=-trustzone < %s | FileCheck %s -check-prefix=NOTZ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble -mattr=trustzone < %s | FileCheck %s -check-prefix=TZ + + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ + +0x7f 0x00 0x60 0xe1 +0x70 0x00 0x60 0x01 + +# NOTZ-NOT: smc #15 +# NOTZ-NOT: smceq #0 +# TZ: smc #15 +# TZ: smceq #0 + diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 1100ce64a947..9f63e1e914ff 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -707,8 +707,10 @@ # CHECK: mov r3, #7 # CHECK: mov r4, #4080 # CHECK: mov r5, #16711680 +# CHECK: mov sp, #35 # CHECK: movw r6, #65535 # CHECK: movw r9, #65535 +# CHECK: movw sp, #1193 # CHECK: movs r3, #7 # CHECK: moveq r4, #4080 # CHECK: movseq r5, #16711680 @@ -716,8 +718,10 @@ 0x07 0x30 0xa0 0xe3 0xff 0x4e 0xa0 0xe3 0xff 0x58 0xa0 0xe3 +0x23 0xd0 0xa0 0xe3 0xff 0x6f 0x0f 0xe3 0xff 0x9f 0x0f 0xe3 +0xa9 0xd4 0x00 0xe3 0x07 0x30 0xb0 0xe3 0xff 0x4e 0xa0 0x03 0xff 0x58 0xb0 0x03 @@ -740,10 +744,12 @@ #------------------------------------------------------------------------------ # CHECK: movt r3, #7 # CHECK: movt r6, #65535 +# CHECK: movt sp, #3397 # CHECK: movteq r4, #4080 0x07 0x30 0x40 0xe3 0xff 0x6f 0x4f 0xe3 +0x45 0xdd 0x40 0xe3 0xf0 0x4f 0x40 0x03 @@ -1442,15 +1448,6 @@ 0xf2 0x4f 0x38 0xc6 #------------------------------------------------------------------------------ -# SMC -#------------------------------------------------------------------------------ -# CHECK: smc #15 -# CHECK: smceq #0 - -0x7f 0x00 0x60 0xe1 -0x70 0x00 0x60 0x01 - -#------------------------------------------------------------------------------ # SMLABB/SMLABT/SMLATB/SMLATT #------------------------------------------------------------------------------ # CHECK: smlabb r3, r1, r9, r0 @@ -1826,12 +1823,13 @@ # CHECK: strexh r4, r2, [r5 # CHECK: strex r2, r1, [r7 # CHECK: strexd r6, r2, r3, [r8 +# CHECK: strexd sp, r0, r1, [r0] 0x93 0x1f 0xc4 0xe1 0x92 0x4f 0xe5 0xe1 0x91 0x2f 0x87 0xe1 0x92 0x6f 0xa8 0xe1 - +0x90 0xdf 0xa0 0xe1 #------------------------------------------------------------------------------ # SUB diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index 0cff28ad2b2b..ecab5a5758e2 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 2>&1 | grep "invalid instruction encoding" -# XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. 0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-hint-arm.txt b/test/MC/Disassembler/ARM/invalid-hint-arm.txt new file mode 100644 index 000000000000..7da96d8f15ce --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-hint-arm.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -mcpu=cortex-a8 -disassemble < %s 2>&1 | FileCheck %s + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +0x05 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding +0x41 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding +0xfe 0xf0 0x20 0xe3 +# CHECK: invalid instruction encoding + diff --git a/test/MC/Disassembler/ARM/invalid-hint-thumb.txt b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt new file mode 100644 index 000000000000..1e4133668b84 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-hint-thumb.txt @@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple=thumbv7 -disassemble -show-encoding < %s 2>&1 | FileCheck %s + +#------------------------------------------------------------------------------ +# Undefined encoding space for hint instructions +#------------------------------------------------------------------------------ + +0xaf 0xf3 0x05 0x80 +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/Mips/mips-dsp.txt b/test/MC/Disassembler/Mips/mips-dsp.txt new file mode 100644 index 000000000000..d10e62cd23cd --- /dev/null +++ b/test/MC/Disassembler/Mips/mips-dsp.txt @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple=mipsel-unknown-linux -mattr=+dsp -disassemble < %s | FileCheck %s + +# CHECK: mfhi $21, $ac3 +0x10 0xa8 0x60 0x00 + +# CHECK: mflo $21, $ac3 +0x12 0xa8 0x60 0x00 + +# CHECK: mthi $21, $ac3 +0x11 0x18 0xa0 0x02 + +# CHECK: mtlo $21, $ac3 +0x13 0x18 0xa0 0x02 diff --git a/test/MC/Disassembler/Mips/mips32.txt b/test/MC/Disassembler/Mips/mips32.txt index 70224860bc71..ef8bf71bd3a6 100644 --- a/test/MC/Disassembler/Mips/mips32.txt +++ b/test/MC/Disassembler/Mips/mips32.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x46 0x20 0x73 0x05 diff --git a/test/MC/Disassembler/Mips/mips32_le.txt b/test/MC/Disassembler/Mips/mips32_le.txt index 48fa8e2c7fac..a0885a4bfe85 100644 --- a/test/MC/Disassembler/Mips/mips32_le.txt +++ b/test/MC/Disassembler/Mips/mips32_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x05 0x73 0x20 0x46 diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 3b70db3bc29d..991eaa6cc97f 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x46 0x20 0x73 0x05 diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index ecfde7a39c4f..10c293821c9d 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: abs.d $f12, $f14 0x05 0x73 0x20 0x46 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index 38b137766125..b88747370b67 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0x67 0x4b 0x7c 0xcd diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index a7ef0e473bbe..ddc3c2b60be4 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0xcd 0x7c 0x4b 0x67 diff --git a/test/MC/Disassembler/Mips/mips64r2.txt b/test/MC/Disassembler/Mips/mips64r2.txt index 0b421fc551e2..cee6f3c21f72 100644 --- a/test/MC/Disassembler/Mips/mips64r2.txt +++ b/test/MC/Disassembler/Mips/mips64r2.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64-unknown-linux -mattr +mips64r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0x67 0x4b 0x7c 0xcd diff --git a/test/MC/Disassembler/Mips/mips64r2_le.txt b/test/MC/Disassembler/Mips/mips64r2_le.txt index c1d326f6d674..82e4d6ae1ce0 100644 --- a/test/MC/Disassembler/Mips/mips64r2_le.txt +++ b/test/MC/Disassembler/Mips/mips64r2_le.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=mips64el-unknown-linux -mattr +mips64r2 | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: daddiu $11, $26, 31949 0xcd 0x7c 0x4b 0x67 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 27694cd01446..57e602f1500e 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -110,3 +110,12 @@ # CHECK: vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8 0xc4 0x02 0x39 0x90 0x14 0x4f + +# CHECK: xsave64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x20 + +# CHECK: xrstor64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x28 + +# CHECK: xsaveopt64 OPAQUE PTR [RAX] +0x48 0x0f 0xae 0x30 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index 5de1d5978433..c285af72b358 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -112,3 +112,18 @@ # CHECK: xabort $13 0xc6 0xf8 0x0d + +# CHECK: xsaveq (%rax) +0x48 0x0f 0xae 0x20 + +# CHECK: xrstorq (%rax) +0x48 0x0f 0xae 0x28 + +# CHECK: xsaveoptq (%rax) +0x48 0x0f 0xae 0x30 + +# CHECK: clac +0x0f 0x01 0xca + +# CHECK: stac +0x0f 0x01 0xcb diff --git a/test/MC/Disassembler/XCore/xcore.txt b/test/MC/Disassembler/XCore/xcore.txt index 99e54e9857c5..116433051a5a 100644 --- a/test/MC/Disassembler/XCore/xcore.txt +++ b/test/MC/Disassembler/XCore/xcore.txt @@ -1,5 +1,4 @@ # RUN: llvm-mc --disassemble %s -triple=xcore-xmos-elf | FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions # 0r instructions @@ -649,12 +648,24 @@ # CHECK: ldap r11, 53112 0x33 0xf0 0x78 0xdb +# CHECK: ldap r11, -22 +0x16 0xdc + +# CHECK: ldap r11, -9999 +0x09 0xf0 0x0f 0xdf + # CHECK: bl 8 0x08 0xd0 # CHECK: bl 38631 0x25 0xf0 0xe7 0xd2 +# CHECK: bl -222 +0xde 0xd4 + +# CHECK: bl -55132 +0x35 0xf0 0x5c 0xd7 + # CHECK: bla cp[500] 0xf4 0xe1 diff --git a/test/MC/ELF/abs.s b/test/MC/ELF/abs.s index 48dbe3dffcc5..1836f4005973 100644 --- a/test/MC/ELF/abs.s +++ b/test/MC/ELF/abs.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that zed will be an ABS symbol @@ -6,11 +6,12 @@ .Lbar: zed = .Lfoo - .Lbar -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000001) # 'zed' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff1) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK: Symbol { +// CHECK: Name: zed +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF1) +// CHECK-NEXT: } diff --git a/test/MC/ELF/alias-reloc.s b/test/MC/ELF/alias-reloc.s index f0db81592e78..c25c25932f09 100644 --- a/test/MC/ELF/alias-reloc.s +++ b/test/MC/ELF/alias-reloc.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s // Test that this produces a R_X86_64_PLT32 with bar. @@ -17,36 +17,30 @@ foo2: .set bar2,foo2 .quad bar2 -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000001) -// CHECK-NEXT: ('r_sym', 0x00000001) -// CHECK-NEXT: ('r_type', 0x00000004) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) -// CHECK-NEXT: ), +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[0-9]+}}) zed { +// CHECK-NEXT: 0x1 R_X86_64_PLT32 bar 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x5 R_X86_64_64 bar2 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: ] -// CHECK: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000005) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK-NEXT: Name: bar +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000005) # 'bar' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), - -// CHECK: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x0000000e) # 'bar2' -// CHECK-NEXT: ('st_bind', 0x2) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ('st_value', 0x0000000000000005) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: bar2 +// CHECK-NEXT: Value: 0x5 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: zed +// CHECK-NEXT: } diff --git a/test/MC/ELF/alias.s b/test/MC/ELF/alias.s index f38262801353..0575f41fc851 100644 --- a/test/MC/ELF/alias.s +++ b/test/MC/ELF/alias.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s foo: bar = foo @@ -16,70 +16,78 @@ foo4: bar4 = foo4 .long foo2 -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000005) # 'bar' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x0000001d) # 'bar4' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x2) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 3 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x0000000e) # 'foo3' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000018) # 'foo4' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x2) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x00000013) # 'bar3' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK: # Symbol 10 -// CHECK-NEXT: (('st_name', 0x00000009) # 'bar2' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) + +// CHECK: Symbols [ +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar4 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Function +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo3 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo4 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Function +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .text (0) +// CHECK: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .data (0) +// CHECK: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .bss (0) +// CHECK: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar3 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar2 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/align-bss.s b/test/MC/ELF/align-bss.s index a59232b812a4..776eef38467c 100644 --- a/test/MC/ELF/align-bss.s +++ b/test/MC/ELF/align-bss.s @@ -1,17 +1,22 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the bss section is correctly aligned .local foo .comm foo,2048,16 -// CHECK: ('sh_name', 0x00000007) # '.bss' -// CHECK-NEXT: ('sh_type', 0x00000008) -// CHECK-NEXT: ('sh_flags', 0x0000000000000003) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000800) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000010) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK: Section { +// CHECK: Name: .bss +// CHECK-NEXT: Type: SHT_NOBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_WRITE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 2048 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 16 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } diff --git a/test/MC/ELF/align-nops.s b/test/MC/ELF/align-nops.s index 3bf96e956a93..5e3386823f26 100644 --- a/test/MC/ELF/align-nops.s +++ b/test/MC/ELF/align-nops.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s // Test that we get optimal nops in text .text @@ -15,26 +15,40 @@ f0: .long 0 .align 8 -// CHECK: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000010) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '00000000 0f1f4000 00000000 0f1f4000') +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 16 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00000000 0F1F4000 00000000 0F1F4000 +// CHECK-NEXT: ) +// CHECK-NEXT: } -// CHECK: (('sh_name', 0x00000026) # '.data' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000003) -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000010) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '00000000 90909090 00000000 00000000') +// CHECK: Section { +// CHECK: Name: .data +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_WRITE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 16 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00000000 90909090 00000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/align-size.s b/test/MC/ELF/align-size.s index f6282910db07..84a6e9981488 100644 --- a/test/MC/ELF/align-size.s +++ b/test/MC/ELF/align-size.s @@ -1,13 +1,18 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the alignment does contribute to the size of the section. .zero 4 .align 8 -// CHECK: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000008) +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 8 +// CHECK: } diff --git a/test/MC/ELF/align-text.s b/test/MC/ELF/align-text.s index 2fd3cba50231..b00af4a34b08 100644 --- a/test/MC/ELF/align-text.s +++ b/test/MC/ELF/align-text.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the .text directive doesn't cause alignment. @@ -6,14 +6,18 @@ .text .zero 1 -// CHECK: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000002) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 2 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } diff --git a/test/MC/ELF/align.s b/test/MC/ELF/align.s index 3142ffb55351..46be3df62f2d 100644 --- a/test/MC/ELF/align.s +++ b/test/MC/ELF/align.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the alignment of rodata doesn't force a alignment of the // previous section (.bss) @@ -7,26 +7,33 @@ .section .rodata,"a",@progbits .align 8 -// CHECK: # Section 3 -// CHECK-NEXT: (('sh_name', 0x00000007) # '.bss' -// CHECK-NEXT: ('sh_type', 0x00000008) -// CHECK-NEXT: ('sh_flags', 0x0000000000000003) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000044) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000026) # '.rodata' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK: Section { +// CHECK: Name: .bss +// CHECK-NEXT: Type: SHT_NOBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_WRITE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x44 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 4 +// CHECK-NEXT: Name: .rodata +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } diff --git a/test/MC/ELF/basic-elf-32.s b/test/MC/ELF/basic-elf-32.s index 2c6a9841956c..3ddb53981a9f 100644 --- a/test/MC/ELF/basic-elf-32.s +++ b/test/MC/ELF/basic-elf-32.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -h -s -r -t | FileCheck %s .text .globl main @@ -30,49 +30,53 @@ main: # @main .section .note.GNU-stack,"",@progbits -// CHECK: ('e_indent[EI_CLASS]', 0x01) -// CHECK: ('e_indent[EI_DATA]', 0x01) -// CHECK: ('e_indent[EI_VERSION]', 0x01) -// CHECK: ('_sections', [ -// CHECK: # Section 0 -// CHECK: (('sh_name', 0x00000000) # '' +// CHECK: ElfHeader { +// CHECK: Class: 32-bit +// CHECK: DataEncoding: LittleEndian +// CHECK: FileVersion: 1 +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Index: 0 +// CHECK: Name: (0) -// CHECK: # '.text' +// CHECK: Name: .text -// CHECK: # '.rel.text' +// CHECK: Name: .rel.text -// CHECK: ('_relocations', [ -// CHECK: # Relocation 0 -// CHECK: (('r_offset', 0x00000006) -// CHECK: ('r_type', 0x01) -// CHECK: ), -// CHECK: # Relocation 1 -// CHECK: (('r_offset', 0x0000000b) -// CHECK: ('r_type', 0x02) -// CHECK: ), -// CHECK: # Relocation 2 -// CHECK: (('r_offset', 0x00000012) -// CHECK: ('r_type', 0x01) -// CHECK: ), -// CHECK: # Relocation 3 -// CHECK: (('r_offset', 0x00000017) -// CHECK: ('r_type', 0x02) -// CHECK: ), -// CHECK: ]) +// CHECK: Relocations [ +// CHECK: Section (1) .text { +// CHECK: 0x6 R_386_32 .rodata.str1.1 +// CHECK: 0xB R_386_PC32 puts +// CHECK: 0x12 R_386_32 .rodata.str1.1 +// CHECK: 0x17 R_386_PC32 puts +// CHECK: } +// CHECK: ] -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section +// CHECK: } -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section +// CHECK: } -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section +// CHECK: } -// CHECK: # 'main' -// CHECK: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x2) +// CHECK: Symbol { +// CHECK: Name: main +// CHECK: Binding: Global +// CHECK: Type: Function +// CHECK: } -// CHECK: # 'puts' -// CHECK: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) +// CHECK: Symbol { +// CHECK: Name: puts +// CHECK: Binding: Global +// CHECK: Type: None +// CHECK: } diff --git a/test/MC/ELF/basic-elf-64.s b/test/MC/ELF/basic-elf-64.s index 38ffaa724acc..f98623ad1e3c 100644 --- a/test/MC/ELF/basic-elf-64.s +++ b/test/MC/ELF/basic-elf-64.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -h -s -r -t | FileCheck %s .text .globl main @@ -30,53 +30,51 @@ main: # @main .section .note.GNU-stack,"",@progbits -// CHECK: ('e_indent[EI_CLASS]', 0x02) -// CHECK: ('e_indent[EI_DATA]', 0x01) -// CHECK: ('e_indent[EI_VERSION]', 0x01) -// CHECK: ('_sections', [ -// CHECK: # Section 0 -// CHECK: (('sh_name', 0x00000000) # '' +// CHECK: ElfHeader { +// CHECK: Class: 64-bit +// CHECK: DataEncoding: LittleEndian +// CHECK: FileVersion: 1 +// CHECK: } +// CHECK: Sections [ +// CHECK: Section { +// CHECK: Index: 0 +// CHECK: Name: (0) -// CHECK: # '.text' +// CHECK: Name: .text -// CHECK: # '.rela.text' +// CHECK: Name: .rela.text -// CHECK: ('_relocations', [ -// CHECK: # Relocation 0 -// CHECK: (('r_offset', 0x0000000000000005) -// CHECK: ('r_type', 0x0000000a) -// CHECK: ('r_addend', 0x0000000000000000) -// CHECK: ), -// CHECK: # Relocation 1 -// CHECK: (('r_offset', 0x000000000000000a) -// CHECK: ('r_type', 0x00000002) -// CHECK: ('r_addend', 0xfffffffffffffffc) -// CHECK: ), -// CHECK: # Relocation 2 -// CHECK: (('r_offset', 0x000000000000000f) -// CHECK: ('r_type', 0x0000000a) -// CHECK: ('r_addend', 0x0000000000000006) -// CHECK: ), -// CHECK: # Relocation 3 -// CHECK: (('r_offset', 0x0000000000000014) -// CHECK: ('r_type', 0x00000002) -// CHECK: ('r_addend', 0xfffffffffffffffc) -// CHECK: ), -// CHECK: ]) +// CHECK: Relocations [ +// CHECK: Section (1) .text { +// CHECK: 0x5 R_X86_64_32 .rodata.str1.1 0x0 +// CHECK: 0xA R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC +// CHECK: 0xF R_X86_64_32 .rodata.str1.1 0x6 +// CHECK: 0x14 R_X86_64_PC32 puts 0xFFFFFFFFFFFFFFFC +// CHECK: } +// CHECK: ] -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section +// CHECK: } -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) +// CHECK: Symbol { +// CHECK: Binding: Local +// CHECK: Type: Section +// CHECK: } -// CHECK: # 'main' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x2) +// CHECK: Symbol { +// CHECK: Name: main +// CHECK: Binding: Global +// CHECK: Type: Function +// CHECK: } -// CHECK: # 'puts' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) +// CHECK: Symbol { +// CHECK: Name: puts +// CHECK: Binding: Global +// CHECK: Type: None +// CHECK: } diff --git a/test/MC/ELF/call-abs.s b/test/MC/ELF/call-abs.s index 795a65993c0d..81265a1b075d 100644 --- a/test/MC/ELF/call-abs.s +++ b/test/MC/ELF/call-abs.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s .text .globl f @@ -15,10 +15,8 @@ f: # @f .section .note.GNU-stack,"",@progbits -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x00000004) -// CHECK-NEXT: ('r_sym', 0x000000) -// CHECK-NEXT: ('r_type', 0x02) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Relocations [ +// CHECK: Section ({{[^ ]+}}) {{[^ ]+}} { +// CHECK-NEXT: 0x4 R_386_PC32 - +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/cfi-adjust-cfa-offset.s b/test/MC/ELF/cfi-adjust-cfa-offset.s index f0d9c5fe23ee..137b8b6f8490 100644 --- a/test/MC/ELF/cfi-adjust-cfa-offset.s +++ b/test/MC/ELF/cfi-adjust-cfa-offset.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -11,36 +11,43 @@ f: ret .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000038) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 1c000000 1c000000 00000000 0a000000 00440e10 410e1444 0e080000 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x00000000000003a0) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 56 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 1C000000 1C000000 +// CHECK-NEXT: 0020: 00000000 0A000000 00440E10 410E1444 +// CHECK-NEXT: 0030: 0E080000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x3A0 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-advance-loc2.s b/test/MC/ELF/cfi-advance-loc2.s index b3c08e0a0ec0..1cad32507cde 100644 --- a/test/MC/ELF/cfi-advance-loc2.s +++ b/test/MC/ELF/cfi-advance-loc2.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s // test that this produces a correctly encoded cfi_advance_loc2 @@ -10,36 +10,41 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000148) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 01010000 00030001 0e080000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x148 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 01010000 00030001 0E080000 +// CHECK-NEXT: ) +// CHECK-NEXT: } - -// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000490) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x490 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa-offset.s b/test/MC/ELF/cfi-def-cfa-offset.s index 0ed2be057edd..f1a54a810e0a 100644 --- a/test/MC/ELF/cfi-def-cfa-offset.s +++ b/test/MC/ELF/cfi-def-cfa-offset.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -10,37 +10,43 @@ f: ret .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 0a000000 00440e10 450e0800') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 0A000000 00440E10 450E0800 +// CHECK-NEXT: ) +// CHECK-NEXT: } -// CHECK: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000398) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x398 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa-register.s b/test/MC/ELF/cfi-def-cfa-register.s index e87b4f67d4b6..b1e74ea098c2 100644 --- a/test/MC/ELF/cfi-def-cfa-register.s +++ b/test/MC/ELF/cfi-def-cfa-register.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,35 +7,41 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410d06 00000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00410D06 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } -// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-def-cfa.s b/test/MC/ELF/cfi-def-cfa.s index e25bf5c8e3c4..abde0de4fad0 100644 --- a/test/MC/ELF/cfi-def-cfa.s +++ b/test/MC/ELF/cfi-def-cfa.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,41 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410c07 08000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00410C07 08000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } - -// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-escape.s b/test/MC/ELF/cfi-escape.s index 3a5af00901cf..a910faba64cc 100644 --- a/test/MC/ELF/cfi-escape.s +++ b/test/MC/ELF/cfi-escape.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,42 @@ f: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00411507 7f000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00411507 7F000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-offset.s b/test/MC/ELF/cfi-offset.s index 9acb76c24d5b..f7f95fbc5f2d 100644 --- a/test/MC/ELF/cfi-offset.s +++ b/test/MC/ELF/cfi-offset.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,41 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00418602 00000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00418602 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } - -// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-register.s b/test/MC/ELF/cfi-register.s index 37723097030f..f7a07e45d8b5 100644 --- a/test/MC/ELF/cfi-register.s +++ b/test/MC/ELF/cfi-register.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,42 @@ f: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410906 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00410906 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-rel-offset.s b/test/MC/ELF/cfi-rel-offset.s index 82bbd8d6cef5..35a73efb0f4a 100644 --- a/test/MC/ELF/cfi-rel-offset.s +++ b/test/MC/ELF/cfi-rel-offset.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -14,36 +14,43 @@ f: .cfi_rel_offset 6,0 .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000040) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 24000000 1c000000 00000000 05000000 00410e08 410d0641 11067f41 0e104186 02000000 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x00000000000003a0) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 64 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 24000000 1C000000 +// CHECK-NEXT: 0020: 00000000 05000000 00410E08 410D0641 +// CHECK-NEXT: 0030: 11067F41 0E104186 02000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x3A0 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-rel-offset2.s b/test/MC/ELF/cfi-rel-offset2.s index 7726adbe38f1..5817d1f4af7f 100644 --- a/test/MC/ELF/cfi-rel-offset2.s +++ b/test/MC/ELF/cfi-rel-offset2.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -6,36 +6,42 @@ f: .cfi_rel_offset 6,16 .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 01000000 00411106 7f000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 01000000 00411106 7F000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-remember.s b/test/MC/ELF/cfi-remember.s index 1717662c1090..932a1828eb29 100644 --- a/test/MC/ELF/cfi-remember.s +++ b/test/MC/ELF/cfi-remember.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -9,37 +9,42 @@ f: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 03000000 00410a41 0b000000') -// CHECK-NEXT: ), - -// CHECK: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 03000000 00410A41 0B000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-restore.s b/test/MC/ELF/cfi-restore.s index 0fc3129c713c..6c25d5b47195 100644 --- a/test/MC/ELF/cfi-restore.s +++ b/test/MC/ELF/cfi-restore.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,42 @@ f: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 0041c600 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 0041C600 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-same-value.s b/test/MC/ELF/cfi-same-value.s index 4c80a0a06660..075c6b9b8435 100644 --- a/test/MC/ELF/cfi-same-value.s +++ b/test/MC/ELF/cfi-same-value.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -7,36 +7,42 @@ f: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410806 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00410806 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-sections.s b/test/MC/ELF/cfi-sections.s index b256bbf4cd44..15a79e5c055e 100644 --- a/test/MC/ELF/cfi-sections.s +++ b/test/MC/ELF/cfi-sections.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 %s .cfi_sections .debug_frame @@ -13,26 +13,43 @@ f2: nop .cfi_endproc -// ELF_64: (('sh_name', 0x00000011) # '.debug_frame' -// ELF_64-NEXT: ('sh_type', 0x00000001) -// ELF_64-NEXT: ('sh_flags', 0x0000000000000000) -// ELF_64-NEXT: ('sh_addr', 0x0000000000000000) -// ELF_64-NEXT: ('sh_offset', 0x0000000000000048) -// ELF_64-NEXT: ('sh_size', 0x0000000000000048) -// ELF_64-NEXT: ('sh_link', 0x00000000) -// ELF_64-NEXT: ('sh_info', 0x00000000) -// ELF_64-NEXT: ('sh_addralign', 0x0000000000000008) -// ELF_64-NEXT: ('sh_entsize', 0x0000000000000000) -// ELF_64-NEXT: ('_section_data', '14000000 ffffffff 01000178 100c0708 90010000 00000000 14000000 00000000 00000000 00000000 01000000 00000000 14000000 00000000 00000000 00000000 01000000 00000000') +// ELF_64: Section { +// ELF_64: Name: .debug_frame +// ELF_64-NEXT: Type: SHT_PROGBITS +// ELF_64-NEXT: Flags [ +// ELF_64-NEXT: ] +// ELF_64-NEXT: Address: 0x0 +// ELF_64-NEXT: Offset: 0x48 +// ELF_64-NEXT: Size: 72 +// ELF_64-NEXT: Link: 0 +// ELF_64-NEXT: Info: 0 +// ELF_64-NEXT: AddressAlignment: 8 +// ELF_64-NEXT: EntrySize: 0 +// ELF_64-NEXT: SectionData ( +// ELF_64-NEXT: 0000: 14000000 FFFFFFFF 01000178 100C0708 +// ELF_64-NEXT: 0010: 90010000 00000000 14000000 00000000 +// ELF_64-NEXT: 0020: 00000000 00000000 01000000 00000000 +// ELF_64-NEXT: 0030: 14000000 00000000 00000000 00000000 +// ELF_64-NEXT: 0040: 01000000 00000000 +// ELF_64-NEXT: ) +// ELF_64-NEXT: } -// ELF_32: (('sh_name', 0x00000010) # '.debug_frame' -// ELF_32-NEXT: ('sh_type', 0x00000001) -// ELF_32-NEXT: ('sh_flags', 0x00000000) -// ELF_32-NEXT: ('sh_addr', 0x00000000) -// ELF_32-NEXT: ('sh_offset', 0x00000038) -// ELF_32-NEXT: ('sh_size', 0x00000034) -// ELF_32-NEXT: ('sh_link', 0x00000000) -// ELF_32-NEXT: ('sh_info', 0x00000000) -// ELF_32-NEXT: ('sh_addralign', 0x00000004) -// ELF_32-NEXT: ('sh_entsize', 0x00000000) -// ELF_32-NEXT: ('_section_data', '10000000 ffffffff 0100017c 080c0404 88010000 0c000000 00000000 00000000 01000000 0c000000 00000000 01000000 01000000') +// ELF_32: Section { +// ELF_32: Name: .debug_frame +// ELF_32-NEXT: Type: SHT_PROGBITS +// ELF_32-NEXT: Flags [ +// ELF_32-NEXT: ] +// ELF_32-NEXT: Address: 0x0 +// ELF_32-NEXT: Offset: 0x38 +// ELF_32-NEXT: Size: 52 +// ELF_32-NEXT: Link: 0 +// ELF_32-NEXT: Info: 0 +// ELF_32-NEXT: AddressAlignment: 4 +// ELF_32-NEXT: EntrySize: 0 +// ELF_32-NEXT: SectionData ( +// ELF_32-NEXT: 0000: 10000000 FFFFFFFF 0100017C 080C0404 +// ELF_32-NEXT: 0010: 88010000 0C000000 00000000 00000000 +// ELF_32-NEXT: 0020: 01000000 0C000000 00000000 01000000 +// ELF_32-NEXT: 0030: 01000000 +// ELF_32-NEXT: ) +// ELF_32-NEXT: } diff --git a/test/MC/ELF/cfi-signal-frame.s b/test/MC/ELF/cfi-signal-frame.s index cf6d16073abe..023311962189 100644 --- a/test/MC/ELF/cfi-signal-frame.s +++ b/test/MC/ELF/cfi-signal-frame.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s f: .cfi_startproc @@ -9,15 +9,25 @@ g: .cfi_startproc .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000058) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5253 00017810 011b0c07 08900100 10000000 1c000000 00000000 00000000 00000000 14000000 00000000 017a5200 01781001 1b0c0708 90010000 10000000 1c000000 00000000 00000000 00000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 88 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5253 00017810 +// CHECK-NEXT: 0010: 011B0C07 08900100 10000000 1C000000 +// CHECK-NEXT: 0020: 00000000 00000000 00000000 14000000 +// CHECK-NEXT: 0030: 00000000 017A5200 01781001 1B0C0708 +// CHECK-NEXT: 0040: 90010000 10000000 1C000000 00000000 +// CHECK-NEXT: 0050: 00000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/cfi-undefined.s b/test/MC/ELF/cfi-undefined.s index 28049faec285..c83b47c142b4 100644 --- a/test/MC/ELF/cfi-undefined.s +++ b/test/MC/ELF/cfi-undefined.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f: .cfi_startproc @@ -6,36 +6,43 @@ f: .cfi_undefined %rbp nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 14000000 1c000000 00000000 02000000 00410706 00000000') -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000390) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), + +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 02000000 00410706 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x390 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/cfi-zero-addr-delta.s b/test/MC/ELF/cfi-zero-addr-delta.s index 9e818e694846..4ac0e34f10c3 100644 --- a/test/MC/ELF/cfi-zero-addr-delta.s +++ b/test/MC/ELF/cfi-zero-addr-delta.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s // Test that we don't produce a DW_CFA_advance_loc 0 @@ -14,35 +14,41 @@ f: nop .cfi_endproc -// CHECK: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000048) -// CHECK-NEXT: ('sh_size', 0x0000000000000038) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a5200 01781001 1b0c0708 90010000 1c000000 1c000000 00000000 04000000 00410e10 410a0e08 410b0000 00000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x48 +// CHECK-NEXT: Size: 56 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A5200 01781001 +// CHECK-NEXT: 0010: 1B0C0708 90010000 1C000000 1C000000 +// CHECK-NEXT: 0020: 00000000 04000000 00410E10 410A0E08 +// CHECK-NEXT: 0030: 410B0000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } -// CHECK: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000398) -// CHECK-NEXT: ('sh_size', 0x0000000000000018) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x398 +// CHECK-NEXT: Size: 24 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] diff --git a/test/MC/ELF/cfi.s b/test/MC/ELF/cfi.s index 9320894226fa..98f4fa9c62e6 100644 --- a/test/MC/ELF/cfi.s +++ b/test/MC/ELF/cfi.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -sd | FileCheck %s f1: .cfi_startproc @@ -212,463 +212,220 @@ f36: nop .cfi_endproc -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000068) -// CHECK-NEXT: ('sh_size', 0x00000000000006c8) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '14000000 00000000 017a4c52 00017810 02031b0c 07089001 14000000 1c000000 00000000 01000000 04000000 00000000 20000000 00000000 017a504c 52000178 100b0000 00000000 00000003 1b0c0708 90010000 14000000 28000000 00000000 01000000 04000000 00000000 14000000 70000000 00000000 01000000 04000000 00000000 20000000 00000000 017a504c 52000178 100b0000 00000000 00000002 1b0c0708 90010000 10000000 28000000 00000000 01000000 02000000 18000000 00000000 017a5052 00017810 04020000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06030000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a040000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 040a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 060b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a0c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a080000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a100000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04120000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06130000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a140000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 041a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 061b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a1c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a180000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a800000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04820000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06830000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a840000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 048a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 068b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a8c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a880000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a900000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 04920000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 06930000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a940000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 049a0000 1b0c0708 90010000 10000000 20000000 00000000 01000000 00000000 18000000 00000000 017a5052 00017810 069b0000 00001b0c 07089001 10000000 20000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a9c0000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000 1c000000 00000000 017a5052 00017810 0a980000 00000000 00001b0c 07089001 10000000 24000000 00000000 01000000 00000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .eh_frame +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x68 +// CHECK-NEXT: Size: 1736 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x20 R_X86_64_PC32 .text 0x0 +// CHECK-NEXT: 0x29 R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x43 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x5C R_X86_64_PC32 .text 0x1 +// CHECK-NEXT: 0x65 R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x74 R_X86_64_PC32 .text 0x2 +// CHECK-NEXT: 0x7D R_X86_64_32 bar 0x0 +// CHECK-NEXT: 0x97 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0xB0 R_X86_64_PC32 .text 0x3 +// CHECK-NEXT: 0xB9 R_X86_64_16 bar 0x0 +// CHECK-NEXT: 0xCE R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0xE0 R_X86_64_PC32 .text 0x4 +// CHECK-NEXT: 0xFE R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x110 R_X86_64_PC32 .text 0x5 +// CHECK-NEXT: 0x12E R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x144 R_X86_64_PC32 .text 0x6 +// CHECK-NEXT: 0x162 R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x174 R_X86_64_PC32 .text 0x7 +// CHECK-NEXT: 0x192 R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x1A4 R_X86_64_PC32 .text 0x8 +// CHECK-NEXT: 0x1C2 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x1D8 R_X86_64_PC32 .text 0x9 +// CHECK-NEXT: 0x1F6 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x20C R_X86_64_PC32 .text 0xA +// CHECK-NEXT: 0x22A R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x240 R_X86_64_PC32 .text 0xB +// CHECK-NEXT: 0x25E R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x270 R_X86_64_PC32 .text 0xC +// CHECK-NEXT: 0x28E R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x2A0 R_X86_64_PC32 .text 0xD +// CHECK-NEXT: 0x2BE R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x2D4 R_X86_64_PC32 .text 0xE +// CHECK-NEXT: 0x2F2 R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x304 R_X86_64_PC32 .text 0xF +// CHECK-NEXT: 0x322 R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x334 R_X86_64_PC32 .text 0x10 +// CHECK-NEXT: 0x352 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x368 R_X86_64_PC32 .text 0x11 +// CHECK-NEXT: 0x386 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x39C R_X86_64_PC32 .text 0x12 +// CHECK-NEXT: 0x3BA R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x3D0 R_X86_64_PC32 .text 0x13 +// CHECK-NEXT: 0x3EE R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x400 R_X86_64_PC32 .text 0x14 +// CHECK-NEXT: 0x41E R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x430 R_X86_64_PC32 .text 0x15 +// CHECK-NEXT: 0x44E R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x464 R_X86_64_PC32 .text 0x16 +// CHECK-NEXT: 0x482 R_X86_64_16 foo 0x0 +// CHECK-NEXT: 0x494 R_X86_64_PC32 .text 0x17 +// CHECK-NEXT: 0x4B2 R_X86_64_32 foo 0x0 +// CHECK-NEXT: 0x4C4 R_X86_64_PC32 .text 0x18 +// CHECK-NEXT: 0x4E2 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x4F8 R_X86_64_PC32 .text 0x19 +// CHECK-NEXT: 0x516 R_X86_64_64 foo 0x0 +// CHECK-NEXT: 0x52C R_X86_64_PC32 .text 0x1A +// CHECK-NEXT: 0x54A R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x560 R_X86_64_PC32 .text 0x1B +// CHECK-NEXT: 0x57E R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x590 R_X86_64_PC32 .text 0x1C +// CHECK-NEXT: 0x5AE R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x5C0 R_X86_64_PC32 .text 0x1D +// CHECK-NEXT: 0x5DE R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x5F4 R_X86_64_PC32 .text 0x1E +// CHECK-NEXT: 0x612 R_X86_64_PC16 foo 0x0 +// CHECK-NEXT: 0x624 R_X86_64_PC32 .text 0x1F +// CHECK-NEXT: 0x642 R_X86_64_PC32 foo 0x0 +// CHECK-NEXT: 0x654 R_X86_64_PC32 .text 0x20 +// CHECK-NEXT: 0x672 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x688 R_X86_64_PC32 .text 0x21 +// CHECK-NEXT: 0x6A6 R_X86_64_PC64 foo 0x0 +// CHECK-NEXT: 0x6BC R_X86_64_PC32 .text 0x22 +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 14000000 00000000 017A4C52 00017810 +// CHECK-NEXT: 0010: 02031B0C 07089001 14000000 1C000000 +// CHECK-NEXT: 0020: 00000000 01000000 04000000 00000000 +// CHECK-NEXT: 0030: 20000000 00000000 017A504C 52000178 +// CHECK-NEXT: 0040: 100B0000 00000000 00000003 1B0C0708 +// CHECK-NEXT: 0050: 90010000 14000000 28000000 00000000 +// CHECK-NEXT: 0060: 01000000 04000000 00000000 14000000 +// CHECK-NEXT: 0070: 70000000 00000000 01000000 04000000 +// CHECK-NEXT: 0080: 00000000 20000000 00000000 017A504C +// CHECK-NEXT: 0090: 52000178 100B0000 00000000 00000002 +// CHECK-NEXT: 00A0: 1B0C0708 90010000 10000000 28000000 +// CHECK-NEXT: 00B0: 00000000 01000000 02000000 18000000 +// CHECK-NEXT: 00C0: 00000000 017A5052 00017810 04020000 +// CHECK-NEXT: 00D0: 1B0C0708 90010000 10000000 20000000 +// CHECK-NEXT: 00E0: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 00F0: 00000000 017A5052 00017810 06030000 +// CHECK-NEXT: 0100: 00001B0C 07089001 10000000 20000000 +// CHECK-NEXT: 0110: 00000000 01000000 00000000 1C000000 +// CHECK-NEXT: 0120: 00000000 017A5052 00017810 0A040000 +// CHECK-NEXT: 0130: 00000000 00001B0C 07089001 10000000 +// CHECK-NEXT: 0140: 24000000 00000000 01000000 00000000 +// CHECK-NEXT: 0150: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0160: 040A0000 1B0C0708 90010000 10000000 +// CHECK-NEXT: 0170: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 0180: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0190: 060B0000 00001B0C 07089001 10000000 +// CHECK-NEXT: 01A0: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 01B0: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 01C0: 0A0C0000 00000000 00001B0C 07089001 +// CHECK-NEXT: 01D0: 10000000 24000000 00000000 01000000 +// CHECK-NEXT: 01E0: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 01F0: 00017810 0A080000 00000000 00001B0C +// CHECK-NEXT: 0200: 07089001 10000000 24000000 00000000 +// CHECK-NEXT: 0210: 01000000 00000000 1C000000 00000000 +// CHECK-NEXT: 0220: 017A5052 00017810 0A100000 00000000 +// CHECK-NEXT: 0230: 00001B0C 07089001 10000000 24000000 +// CHECK-NEXT: 0240: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 0250: 00000000 017A5052 00017810 04120000 +// CHECK-NEXT: 0260: 1B0C0708 90010000 10000000 20000000 +// CHECK-NEXT: 0270: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 0280: 00000000 017A5052 00017810 06130000 +// CHECK-NEXT: 0290: 00001B0C 07089001 10000000 20000000 +// CHECK-NEXT: 02A0: 00000000 01000000 00000000 1C000000 +// CHECK-NEXT: 02B0: 00000000 017A5052 00017810 0A140000 +// CHECK-NEXT: 02C0: 00000000 00001B0C 07089001 10000000 +// CHECK-NEXT: 02D0: 24000000 00000000 01000000 00000000 +// CHECK-NEXT: 02E0: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 02F0: 041A0000 1B0C0708 90010000 10000000 +// CHECK-NEXT: 0300: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 0310: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0320: 061B0000 00001B0C 07089001 10000000 +// CHECK-NEXT: 0330: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 0340: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0350: 0A1C0000 00000000 00001B0C 07089001 +// CHECK-NEXT: 0360: 10000000 24000000 00000000 01000000 +// CHECK-NEXT: 0370: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 0380: 00017810 0A180000 00000000 00001B0C +// CHECK-NEXT: 0390: 07089001 10000000 24000000 00000000 +// CHECK-NEXT: 03A0: 01000000 00000000 1C000000 00000000 +// CHECK-NEXT: 03B0: 017A5052 00017810 0A800000 00000000 +// CHECK-NEXT: 03C0: 00001B0C 07089001 10000000 24000000 +// CHECK-NEXT: 03D0: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 03E0: 00000000 017A5052 00017810 04820000 +// CHECK-NEXT: 03F0: 1B0C0708 90010000 10000000 20000000 +// CHECK-NEXT: 0400: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 0410: 00000000 017A5052 00017810 06830000 +// CHECK-NEXT: 0420: 00001B0C 07089001 10000000 20000000 +// CHECK-NEXT: 0430: 00000000 01000000 00000000 1C000000 +// CHECK-NEXT: 0440: 00000000 017A5052 00017810 0A840000 +// CHECK-NEXT: 0450: 00000000 00001B0C 07089001 10000000 +// CHECK-NEXT: 0460: 24000000 00000000 01000000 00000000 +// CHECK-NEXT: 0470: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0480: 048A0000 1B0C0708 90010000 10000000 +// CHECK-NEXT: 0490: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 04A0: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 04B0: 068B0000 00001B0C 07089001 10000000 +// CHECK-NEXT: 04C0: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 04D0: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 04E0: 0A8C0000 00000000 00001B0C 07089001 +// CHECK-NEXT: 04F0: 10000000 24000000 00000000 01000000 +// CHECK-NEXT: 0500: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 0510: 00017810 0A880000 00000000 00001B0C +// CHECK-NEXT: 0520: 07089001 10000000 24000000 00000000 +// CHECK-NEXT: 0530: 01000000 00000000 1C000000 00000000 +// CHECK-NEXT: 0540: 017A5052 00017810 0A900000 00000000 +// CHECK-NEXT: 0550: 00001B0C 07089001 10000000 24000000 +// CHECK-NEXT: 0560: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 0570: 00000000 017A5052 00017810 04920000 +// CHECK-NEXT: 0580: 1B0C0708 90010000 10000000 20000000 +// CHECK-NEXT: 0590: 00000000 01000000 00000000 18000000 +// CHECK-NEXT: 05A0: 00000000 017A5052 00017810 06930000 +// CHECK-NEXT: 05B0: 00001B0C 07089001 10000000 20000000 +// CHECK-NEXT: 05C0: 00000000 01000000 00000000 1C000000 +// CHECK-NEXT: 05D0: 00000000 017A5052 00017810 0A940000 +// CHECK-NEXT: 05E0: 00000000 00001B0C 07089001 10000000 +// CHECK-NEXT: 05F0: 24000000 00000000 01000000 00000000 +// CHECK-NEXT: 0600: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0610: 049A0000 1B0C0708 90010000 10000000 +// CHECK-NEXT: 0620: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 0630: 18000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0640: 069B0000 00001B0C 07089001 10000000 +// CHECK-NEXT: 0650: 20000000 00000000 01000000 00000000 +// CHECK-NEXT: 0660: 1C000000 00000000 017A5052 00017810 +// CHECK-NEXT: 0670: 0A9C0000 00000000 00001B0C 07089001 +// CHECK-NEXT: 0680: 10000000 24000000 00000000 01000000 +// CHECK-NEXT: 0690: 00000000 1C000000 00000000 017A5052 +// CHECK-NEXT: 06A0: 00017810 0A980000 00000000 00001B0C +// CHECK-NEXT: 06B0: 07089001 10000000 24000000 00000000 +// CHECK-NEXT: 06C0: 01000000 00000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } -// CHECK: # Section 5 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.rela.eh_frame' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000e30) -// CHECK-NEXT: ('sh_size', 0x00000000000006c0) -// CHECK-NEXT: ('sh_link', 0x00000007) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000020) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000029) -// CHECK-NEXT: ('r_sym', 0x00000028) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 2 -// CHECK-NEXT: (('r_offset', 0x0000000000000043) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 3 -// CHECK-NEXT: (('r_offset', 0x000000000000005c) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000001) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 4 -// CHECK-NEXT: (('r_offset', 0x0000000000000065) -// CHECK-NEXT: ('r_sym', 0x00000028) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 5 -// CHECK-NEXT: (('r_offset', 0x0000000000000074) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000002) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 6 -// CHECK-NEXT: (('r_offset', 0x000000000000007d) -// CHECK-NEXT: ('r_sym', 0x00000028) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 7 -// CHECK-NEXT: (('r_offset', 0x0000000000000097) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 8 -// CHECK-NEXT: (('r_offset', 0x00000000000000b0) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000003) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 9 -// CHECK-NEXT: (('r_offset', 0x00000000000000b9) -// CHECK-NEXT: ('r_sym', 0x00000028) -// CHECK-NEXT: ('r_type', 0x0000000c) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 10 -// CHECK-NEXT: (('r_offset', 0x00000000000000ce) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000c) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 11 -// CHECK-NEXT: (('r_offset', 0x00000000000000e0) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000004) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 12 -// CHECK-NEXT: (('r_offset', 0x00000000000000fe) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 13 -// CHECK-NEXT: (('r_offset', 0x0000000000000110) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000005) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 14 -// CHECK-NEXT: (('r_offset', 0x000000000000012e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 15 -// CHECK-NEXT: (('r_offset', 0x0000000000000144) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000006) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 16 -// CHECK-NEXT: (('r_offset', 0x0000000000000162) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000c) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 17 -// CHECK-NEXT: (('r_offset', 0x0000000000000174) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000007) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 18 -// CHECK-NEXT: (('r_offset', 0x0000000000000192) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 19 -// CHECK-NEXT: (('r_offset', 0x00000000000001a4) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000008) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 20 -// CHECK-NEXT: (('r_offset', 0x00000000000001c2) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 21 -// CHECK-NEXT: (('r_offset', 0x00000000000001d8) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000009) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 22 -// CHECK-NEXT: (('r_offset', 0x00000000000001f6) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 23 -// CHECK-NEXT: (('r_offset', 0x000000000000020c) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000a) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 24 -// CHECK-NEXT: (('r_offset', 0x000000000000022a) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 25 -// CHECK-NEXT: (('r_offset', 0x0000000000000240) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000b) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 26 -// CHECK-NEXT: (('r_offset', 0x000000000000025e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000d) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 27 -// CHECK-NEXT: (('r_offset', 0x0000000000000270) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000c) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 28 -// CHECK-NEXT: (('r_offset', 0x000000000000028e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 29 -// CHECK-NEXT: (('r_offset', 0x00000000000002a0) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000d) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 30 -// CHECK-NEXT: (('r_offset', 0x00000000000002be) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 31 -// CHECK-NEXT: (('r_offset', 0x00000000000002d4) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000e) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 32 -// CHECK-NEXT: (('r_offset', 0x00000000000002f2) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000d) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 33 -// CHECK-NEXT: (('r_offset', 0x0000000000000304) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000000f) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 34 -// CHECK-NEXT: (('r_offset', 0x0000000000000322) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 35 -// CHECK-NEXT: (('r_offset', 0x0000000000000334) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000010) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 36 -// CHECK-NEXT: (('r_offset', 0x0000000000000352) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 37 -// CHECK-NEXT: (('r_offset', 0x0000000000000368) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000011) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 38 -// CHECK-NEXT: (('r_offset', 0x0000000000000386) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 39 -// CHECK-NEXT: (('r_offset', 0x000000000000039c) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000012) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 40 -// CHECK-NEXT: (('r_offset', 0x00000000000003ba) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 41 -// CHECK-NEXT: (('r_offset', 0x00000000000003d0) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000013) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 42 -// CHECK-NEXT: (('r_offset', 0x00000000000003ee) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000c) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 43 -// CHECK-NEXT: (('r_offset', 0x0000000000000400) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000014) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 44 -// CHECK-NEXT: (('r_offset', 0x000000000000041e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 45 -// CHECK-NEXT: (('r_offset', 0x0000000000000430) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000015) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 46 -// CHECK-NEXT: (('r_offset', 0x000000000000044e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 47 -// CHECK-NEXT: (('r_offset', 0x0000000000000464) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000016) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 48 -// CHECK-NEXT: (('r_offset', 0x0000000000000482) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000c) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 49 -// CHECK-NEXT: (('r_offset', 0x0000000000000494) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000017) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 50 -// CHECK-NEXT: (('r_offset', 0x00000000000004b2) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 51 -// CHECK-NEXT: (('r_offset', 0x00000000000004c4) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000018) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 52 -// CHECK-NEXT: (('r_offset', 0x00000000000004e2) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 53 -// CHECK-NEXT: (('r_offset', 0x00000000000004f8) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000019) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 54 -// CHECK-NEXT: (('r_offset', 0x0000000000000516) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000001) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 55 -// CHECK-NEXT: (('r_offset', 0x000000000000052c) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001a) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 56 -// CHECK-NEXT: (('r_offset', 0x000000000000054a) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 57 -// CHECK-NEXT: (('r_offset', 0x0000000000000560) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001b) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 58 -// CHECK-NEXT: (('r_offset', 0x000000000000057e) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000d) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 59 -// CHECK-NEXT: (('r_offset', 0x0000000000000590) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001c) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 60 -// CHECK-NEXT: (('r_offset', 0x00000000000005ae) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 61 -// CHECK-NEXT: (('r_offset', 0x00000000000005c0) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001d) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 62 -// CHECK-NEXT: (('r_offset', 0x00000000000005de) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 63 -// CHECK-NEXT: (('r_offset', 0x00000000000005f4) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001e) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 64 -// CHECK-NEXT: (('r_offset', 0x0000000000000612) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x0000000d) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 65 -// CHECK-NEXT: (('r_offset', 0x0000000000000624) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000001f) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 66 -// CHECK-NEXT: (('r_offset', 0x0000000000000642) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 67 -// CHECK-NEXT: (('r_offset', 0x0000000000000654) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000020) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 68 -// CHECK-NEXT: (('r_offset', 0x0000000000000672) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 69 -// CHECK-NEXT: (('r_offset', 0x0000000000000688) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000021) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 70 -// CHECK-NEXT: (('r_offset', 0x00000000000006a6) -// CHECK-NEXT: ('r_sym', 0x00000029) -// CHECK-NEXT: ('r_type', 0x00000018) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 71 -// CHECK-NEXT: (('r_offset', 0x00000000000006bc) -// CHECK-NEXT: ('r_sym', 0x00000024) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000022) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 5 +// CHECK-NEXT: Name: .rela.eh_frame +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0xE30 +// CHECK-NEXT: Size: 1728 +// CHECK-NEXT: Link: 7 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK: } diff --git a/test/MC/ELF/comdat.s b/test/MC/ELF/comdat.s index d7acea6778d4..f9469dfae273 100644 --- a/test/MC/ELF/comdat.s +++ b/test/MC/ELF/comdat.s @@ -1,75 +1,81 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s // Test that we produce the group sections and that they are a the beginning // of the file. -// CHECK: # Section 1 -// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' -// CHECK-NEXT: ('sh_type', 0x00000011) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x000000000000000c) -// CHECK-NEXT: ('sh_link', 0x0000000d) -// CHECK-NEXT: ('sh_info', 0x00000001) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000004) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 2 -// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' -// CHECK-NEXT: ('sh_type', 0x00000011) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x000000000000004c) -// CHECK-NEXT: ('sh_size', 0x0000000000000008) -// CHECK-NEXT: ('sh_link', 0x0000000d) -// CHECK-NEXT: ('sh_info', 0x00000002) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000004) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 3 -// CHECK-NEXT: (('sh_name', 0x0000001b) # '.group' -// CHECK-NEXT: ('sh_type', 0x00000011) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000054) -// CHECK-NEXT: ('sh_size', 0x0000000000000008) -// CHECK-NEXT: ('sh_link', 0x0000000d) -// CHECK-NEXT: ('sh_info', 0x0000000d) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000004) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: .group +// CHECK-NEXT: Type: SHT_GROUP +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 12 +// CHECK-NEXT: Link: 13 +// CHECK-NEXT: Info: 1 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 4 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 2 +// CHECK-NEXT: Name: .group +// CHECK-NEXT: Type: SHT_GROUP +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x4C +// CHECK-NEXT: Size: 8 +// CHECK-NEXT: Link: 13 +// CHECK-NEXT: Info: 2 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 4 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 3 +// CHECK-NEXT: Name: .group +// CHECK-NEXT: Type: SHT_GROUP +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x54 +// CHECK-NEXT: Size: 8 +// CHECK-NEXT: Link: 13 +// CHECK-NEXT: Info: 13 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 4 +// CHECK-NEXT: } // Test that g1 and g2 are local, but g3 is an undefined global. -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000001) # 'g1' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0007) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000004) # 'g2' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0002) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: g1 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .foo (0x7) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: g2 (4) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .group (0x2) +// CHECK-NEXT: } -// CHECK: # Symbol 13 -// CHECK-NEXT: (('st_name', 0x00000007) # 'g3' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: g3 (7) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } .section .foo,"axG",@progbits,g1,comdat diff --git a/test/MC/ELF/common.s b/test/MC/ELF/common.s index 046306e3d37d..4fc2154d850c 100644 --- a/test/MC/ELF/common.s +++ b/test/MC/ELF/common.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s .text @@ -8,13 +8,15 @@ .local common1 .comm common1,1,1 -// CHECK: ('st_name', 0x00000001) # 'common1' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000001) +// CHECK: Symbol { +// CHECK: Name: common1 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 1 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: +// CHECK-NEXT: } // Same as common1, but with directives in a different order. @@ -22,38 +24,44 @@ .type common2,@object .comm common2,1,1 -// CHECK: ('st_name', 0x00000009) # 'common2' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', -// CHECK-NEXT: ('st_value', 0x0000000000000001) -// CHECK-NEXT: ('st_size', 0x0000000000000001) +// CHECK: Symbol { +// CHECK: Name: common2 (9) +// CHECK-NEXT: Value: 0x1 +// CHECK-NEXT: Size: 1 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: +// CHECK-NEXT: } + .local common6 .comm common6,8,16 -// CHECK: # Symbol 3 -// CHECK-NEXT: (('st_name', 0x00000011) # 'common6' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ('st_value', 0x0000000000000010) -// CHECK-NEXT: ('st_size', 0x0000000000000008) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: common6 (17) +// CHECK-NEXT: Value: 0x10 +// CHECK-NEXT: Size: 8 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: } + // Test that without an explicit .local we produce a global. .type common3,@object .comm common3,4,4 -// CHECK: ('st_name', 0x00000019) # 'common3' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff2) -// CHECK-NEXT: ('st_value', 0x0000000000000004) -// CHECK-NEXT: ('st_size', 0x0000000000000004) +// CHECK: Symbol { +// CHECK: Name: common3 (25) +// CHECK-NEXT: Value: 0x4 +// CHECK-NEXT: Size: 4 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF2) +// CHECK-NEXT: } // Test that without an explicit .local we produce a global, even if the first @@ -67,22 +75,25 @@ foo: .type common4,@object .comm common4,40,16 -// CHECK: ('st_name', 0x00000025) # 'common4' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff2) -// CHECK-NEXT: ('st_value', 0x0000000000000010) -// CHECK-NEXT: ('st_size', 0x0000000000000028) +// CHECK: Symbol { +// CHECK: Name: common4 (37) +// CHECK-NEXT: Value: 0x10 +// CHECK-NEXT: Size: 40 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF2) +// CHECK-NEXT: } + .comm common5,4,4 -// CHECK: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x0000002d) # 'common5' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff2) -// CHECK-NEXT: ('st_value', 0x0000000000000004) -// CHECK-NEXT: ('st_size', 0x0000000000000004) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: common5 (45) +// CHECK-NEXT: Value: 0x4 +// CHECK-NEXT: Size: 4 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF2) +// CHECK-NEXT: } diff --git a/test/MC/ELF/common2.s b/test/MC/ELF/common2.s index b13577d4a004..526ebc2a95ff 100644 --- a/test/MC/ELF/common2.s +++ b/test/MC/ELF/common2.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the common symbols are placed at the end of .bss. In this example // it causes .bss to have size 9 instead of 8. @@ -9,13 +9,16 @@ .zero 1 .align 8 -// CHECK: (('sh_name', 0x00000007) # '.bss' -// CHECK-NEXT: ('sh_type', -// CHECK-NEXT: ('sh_flags' -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000009) -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', -// CHECK-NEXT: ('sh_entsize', +// CHECK: Section { +// CHECK: Name: .bss (7) +// CHECK-NEXT: Type: +// CHECK-NEXT: Flags [ +// CHECK: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 9 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: +// CHECK-NEXT: EntrySize: +// CHECK-NEXT: } diff --git a/test/MC/ELF/debug-line.s b/test/MC/ELF/debug-line.s index fed816afccef..75e050e9da1c 100644 --- a/test/MC/ELF/debug-line.s +++ b/test/MC/ELF/debug-line.s @@ -1,18 +1,26 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s // Test that .debug_line is populated. -// CHECK: (('sh_name', 0x00000011) # '.debug_line' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000044) -// CHECK-NEXT: ('sh_size', 0x0000000000000037) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '33000000 02001c00 00000101 fb0e0d00 01010101 00000001 00000100 666f6f2e 63000000 00000009 02000000 00000000 00150204 000101') +// CHECK: Section { +// CHECK: Name: .debug_line +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x44 +// CHECK-NEXT: Size: 55 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 33000000 02001C00 00000101 FB0E0D00 +// CHECK-NEXT: 0010: 01010101 00000001 00000100 666F6F2E +// CHECK-NEXT: 0020: 63000000 00000009 02000000 00000000 +// CHECK-NEXT: 0030: 00150204 000101 +// CHECK-NEXT: ) +// CHECK-NEXT: } .section .debug_line,"",@progbits .text diff --git a/test/MC/ELF/debug-loc.s b/test/MC/ELF/debug-loc.s index 3eb3797f443f..b24fa169deb2 100644 --- a/test/MC/ELF/debug-loc.s +++ b/test/MC/ELF/debug-loc.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that we don't regress on the size of the line info section. We used // to handle negative line diffs incorrectly which manifested as very @@ -7,18 +7,20 @@ // FIXME: This size is the same as gnu as, but we can probably do a bit better. // FIXME2: We need a debug_line dumper so that we can test the actual contents. -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x00000011) # '.debug_line' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000044) -// CHECK-NEXT: ('sh_size', 0x000000000000003d) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .debug_line +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x44 +// CHECK-NEXT: Size: 61 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } .section .debug_line,"",@progbits .text diff --git a/test/MC/ELF/diff.s b/test/MC/ELF/diff.s index 4214fc7c0368..543651066969 100644 --- a/test/MC/ELF/diff.s +++ b/test/MC/ELF/diff.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s .global zed foo: @@ -8,8 +8,4 @@ bar: zed: mov zed+(bar-foo), %eax -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000005) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', 0x0000000000000001) +// CHECK: 0x5 R_X86_64_32S zed 0x1 diff --git a/test/MC/ELF/empty-dwarf-lines.s b/test/MC/ELF/empty-dwarf-lines.s index 7baedbcfb826..241580bb3b83 100644 --- a/test/MC/ELF/empty-dwarf-lines.s +++ b/test/MC/ELF/empty-dwarf-lines.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that the dwarf debug_line section contains no line directives. @@ -7,15 +7,17 @@ c: .asciz "hi\n" -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.debug_line' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000044) -// CHECK-NEXT: ('sh_size', 0x0000000000000027) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .debug_line +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x44 +// CHECK-NEXT: Size: 39 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } diff --git a/test/MC/ELF/empty.s b/test/MC/ELF/empty.s index b38a621054b4..c421fe844882 100644 --- a/test/MC/ELF/empty.s +++ b/test/MC/ELF/empty.s @@ -1,70 +1,89 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that like gnu as we create text, data and bss by default. Also test // that shstrtab, symtab and strtab are listed in that order. -// CHECK: ('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) - -// CHECK: ('sh_name', 0x00000026) # '.data' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000003) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) - -// CHECK: ('sh_name', 0x00000007) # '.bss' -// CHECK-NEXT: ('sh_type', 0x00000008) -// CHECK-NEXT: ('sh_flags', 0x0000000000000003) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) - -// CHECK: ('sh_name', 0x0000000c) # '.shstrtab' -// CHECK-NEXT: ('sh_type', 0x00000003) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x000000000000002c) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) - -// CHECK: ('sh_name', 0x0000001e) # '.symtab' -// CHECK-NEXT: ('sh_type', 0x00000002) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000060) -// CHECK-NEXT: ('sh_link', 0x00000006) -// CHECK-NEXT: ('sh_info', 0x00000004) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) - -// CHECK: ('sh_name', 0x00000016) # '.strtab' -// CHECK-NEXT: ('sh_type', 0x00000003) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000001) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .data +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_WRITE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .bss +// CHECK-NEXT: Type: SHT_NOBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_WRITE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .shstrtab +// CHECK-NEXT: Type: SHT_STRTAB +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 44 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .symtab +// CHECK-NEXT: Type: SHT_SYMTAB +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 96 +// CHECK-NEXT: Link: 6 +// CHECK-NEXT: Info: 4 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Name: .strtab +// CHECK-NEXT: Type: SHT_STRTAB +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 1 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } diff --git a/test/MC/ELF/entsize.ll b/test/MC/ELF/entsize.ll index dce6dbaa2a07..2bf9fa9fb594 100644 --- a/test/MC/ELF/entsize.ll +++ b/test/MC/ELF/entsize.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=obj -mtriple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck -check-prefix=64 %s +; RUN: llc -filetype=obj -mtriple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck -check-prefix=64 %s ; Test that constant mergeable strings have sh_entsize set. @@ -20,25 +20,35 @@ declare void @foo(i64* nocapture) nounwind ;;;;; -; 64: (('sh_name', 0x0000004e) # '.rodata.str1.1' -; 64-NEXT: ('sh_type', 0x00000001) -; 64-NEXT: ('sh_flags', 0x0000000000000032) -; 64-NEXT: ('sh_addr', -; 64-NEXT: ('sh_offset', -; 64-NEXT: ('sh_size', 0x000000000000000d) -; 64-NEXT: ('sh_link', -; 64-NEXT: ('sh_info', -; 64-NEXT: ('sh_addralign', 0x0000000000000001) -; 64-NEXT: ('sh_entsize', 0x0000000000000001) - -; 64: (('sh_name', 0x00000041) # '.rodata.cst8' -; 64-NEXT: ('sh_type', 0x00000001) -; 64-NEXT: ('sh_flags', 0x0000000000000012) -; 64-NEXT: ('sh_addr', -; 64-NEXT: ('sh_offset', -; 64-NEXT: ('sh_size', 0x0000000000000010) -; 64-NEXT: ('sh_link', -; 64-NEXT: ('sh_info', -; 64-NEXT: ('sh_addralign', 0x0000000000000008) -; 64-NEXT: ('sh_entsize', 0x0000000000000008) +; 64: Section { +; 64: Name: .rodata.str1.1 +; 64-NEXT: Type: SHT_PROGBITS +; 64-NEXT: Flags [ +; 64-NEXT: SHF_ALLOC +; 64-NEXT: SHF_MERGE +; 64-NEXT: SHF_STRINGS +; 64-NEXT: ] +; 64-NEXT: Address: +; 64-NEXT: Offset: +; 64-NEXT: Size: 13 +; 64-NEXT: Link: +; 64-NEXT: Info: +; 64-NEXT: AddressAlignment: 1 +; 64-NEXT: EntrySize: 1 +; 64-NEXT: } +; 64: Section { +; 64: Name: .rodata.cst8 +; 64-NEXT: Type: SHT_PROGBITS +; 64-NEXT: Flags [ +; 64-NEXT: SHF_ALLOC +; 64-NEXT: SHF_MERGE +; 64-NEXT: ] +; 64-NEXT: Address: +; 64-NEXT: Offset: +; 64-NEXT: Size: 16 +; 64-NEXT: Link: +; 64-NEXT: Info: +; 64-NEXT: AddressAlignment: 8 +; 64-NEXT: EntrySize: 8 +; 64-NEXT: } diff --git a/test/MC/ELF/entsize.s b/test/MC/ELF/entsize.s index 4645686b6d4e..8e084e24b255 100644 --- a/test/MC/ELF/entsize.s +++ b/test/MC/ELF/entsize.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that mergeable constants have sh_entsize set. @@ -32,38 +32,53 @@ .quad 42 .quad 42 -// CHECK: # Section 4 -// CHECK-NEXT: ('sh_name', 0x00000048) # '.rodata.str1.1' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000032) -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x000000000000000d) -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000001) - -// CHECK: # Section 5 -// CHECK-NEXT: ('sh_name', 0x00000039) # '.rodata.str2.1' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000032) -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000010) -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000002) - -// CHECK: # Section 6 -// CHECK-NEXT: ('sh_name', 0x0000002c) # '.rodata.cst8 -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000012) -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', 0x0000000000000010) -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000008) +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .rodata.str1.1 +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_MERGE +// CHECK-NEXT: SHF_STRINGS +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 13 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 1 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Index: 5 +// CHECK-NEXT: Name: .rodata.str2.1 +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_MERGE +// CHECK-NEXT: SHF_STRINGS +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 16 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 2 +// CHECK-NEXT: } +// CHECK: Section { +// CHECK: Index: 6 +// CHECK-NEXT: Name: .rodata.cst8 +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_MERGE +// CHECK-NEXT: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 16 +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 8 +// CHECK-NEXT: } diff --git a/test/MC/ELF/file.s b/test/MC/ELF/file.s index 434fb6e2b3c6..7e287f7e3fa9 100644 --- a/test/MC/ELF/file.s +++ b/test/MC/ELF/file.s @@ -1,23 +1,25 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that the STT_FILE symbol precedes the other local symbols. .file "foo" foa: -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x4) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff1) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000005) # 'foa' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) + +// CHECK: Symbol { +// CHECK: Name: foo (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: File +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foa (5) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } diff --git a/test/MC/ELF/gen-dwarf.s b/test/MC/ELF/gen-dwarf.s index 85e02428fe3f..907bf424f470 100644 --- a/test/MC/ELF/gen-dwarf.s +++ b/test/MC/ELF/gen-dwarf.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=obj -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -g -triple i686-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -r | FileCheck %s // Test that on ELF: @@ -14,97 +14,13 @@ foo: ret .size foo, .-foo -// Section 4 is .debug_line -// CHECK: # Section 4 -// CHECK-NEXT: # '.debug_line' - - - -// The two relocations, one to symbol 6 and one to 4 -// CHECK: # '.rel.debug_info' -// CHECK-NEXT: ('sh_type', -// CHECK-NEXT: ('sh_flags' -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', -// CHECK-NEXT: ('sh_entsize', -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x00000006) -// CHECK-NEXT: ('r_sym', 0x000006) -// CHECK-NEXT: ('r_type', 0x01) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000c) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x01) -// CHECK-NEXT: ), - - -// Section 8 is .debug_abbrev -// CHECK: # Section 8 -// CHECK-NEXT: (('sh_name', 0x00000001) # '.debug_abbrev' - -// Section 9 is .debug_aranges -// CHECK: # Section 9 -// CHECK-NEXT: (('sh_name', 0x0000001e) # '.debug_aranges' - -// Two relocations in .debug_aranges, one to text and one to debug_info. -// CHECK: # '.rel.debug_aranges' -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x00000006) -// CHECK-NEXT: ('r_sym', 0x000005) -// CHECK-NEXT: ('r_type', 0x01) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x00000010) -// CHECK-NEXT: ('r_sym', 0x000001) -// CHECK-NEXT: ('r_type', 0x01) -// CHECK-NEXT: ), - -// Symbol 1 is section 1 (.text) -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ), - -// Symbol 4 is section 4 (.debug_line) -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ), - -// Symbol 5 is section 6 (.debug_info) -// CHECK: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0006) -// CHECK-NEXT: ), - -// Symbol 6 is section 8 (.debug_abbrev) -// CHECK: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0008) -// CHECK-NEXT: ), +// CHECK: Relocations [ +// CHECK: Section ({{[^ ]+}}) .debug_info { +// CHECK-NEXT: 0x6 R_386_32 .debug_abbrev 0x0 +// CHECK-NEXT: 0xC R_386_32 .debug_line 0x0 +// CHECK: } +// CHECK-NEXT: Section ({{[^ ]+}}) .debug_aranges { +// CHECK-NEXT: 0x6 R_386_32 .debug_info 0x0 +// CHECK-NEXT: 0x10 R_386_32 .text 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/global-offset.s b/test/MC/ELF/global-offset.s index 81ae5d785df9..c6886734ca40 100644 --- a/test/MC/ELF/global-offset.s +++ b/test/MC/ELF/global-offset.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s // We test that _GLOBAL_OFFSET_TABLE_ will account for the two bytes at the // start of the addl/leal. @@ -10,14 +10,20 @@ foo: addl _GLOBAL_OFFSET_TABLE_-foo,%ebx -// CHECK: ('sh_name', 0x00000005) # '.text' -// CHECK-NEXT: ('sh_type', -// CHECK-NEXT: ('sh_flags', -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset', -// CHECK-NEXT: ('sh_size', -// CHECK-NEXT: ('sh_link', -// CHECK-NEXT: ('sh_info', -// CHECK-NEXT: ('sh_addralign', -// CHECK-NEXT: ('sh_entsize', -// CHECK-NEXT: ('_section_data', '81c30200 00008d9b 02000000 031d0200 0000') +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: +// CHECK-NEXT: Flags [ +// CHECK: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: +// CHECK-NEXT: Link: +// CHECK-NEXT: Info: +// CHECK-NEXT: AddressAlignment: +// CHECK-NEXT: EntrySize: +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 81C30200 00008D9B 02000000 031D0200 +// CHECK-NEXT: 0010: 0000 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/got.s b/test/MC/ELF/got.s index a84987281818..60dea6d3b172 100644 --- a/test/MC/ELF/got.s +++ b/test/MC/ELF/got.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s // Test that this produces a R_X86_64_GOT32 and that we have an undefined // reference to _GLOBAL_OFFSET_TABLE_. @@ -6,20 +6,15 @@ movl foo@GOT, %eax movl foo@GOTPCREL(%rip), %eax -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x00000003) -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x00000009) -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Relocations [ +// CHECK: Section ({{[^ ]+}}) .text { +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_GOT32 foo 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_GOTPCREL foo 0x{{[^ ]+}} +// CHECK-NEXT: } +// CHECK-NEXT: ] -// CHECK: (('st_name', 0x00000005) # '_GLOBAL_OFFSET_TABLE_' -// CHECK-NEXT: ('st_bind', 0x1) +// CHECK: Symbol { +// CHECK: Name: _GLOBAL_OFFSET_TABLE_ +// CHECK-NEXT: Value: +// CHECK-NEXT: Size: +// CHECK-NEXT: Binding: Global diff --git a/test/MC/ELF/ident.s b/test/MC/ELF/ident.s index 56af19a30752..259220522e3c 100644 --- a/test/MC/ELF/ident.s +++ b/test/MC/ELF/ident.s @@ -1,16 +1,23 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s -// CHECK: (('sh_name', 0x00000007) # '.comment' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000030) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x000000000000000d) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000001) -// CHECK-NEXT: ('_section_data', '00666f6f 00626172 007a6564 00') +// CHECK: Section { +// CHECK: Name: .comment +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_MERGE +// CHECK-NEXT: SHF_STRINGS +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 13 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 1 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00666F6F 00626172 007A6564 00 +// CHECK-NEXT: ) +// CHECK-NEXT: } .ident "foo" .ident "bar" diff --git a/test/MC/ELF/lcomm.s b/test/MC/ELF/lcomm.s index ae8d0baa3323..430b79b54b0a 100644 --- a/test/MC/ELF/lcomm.s +++ b/test/MC/ELF/lcomm.s @@ -1,21 +1,23 @@ -// RUN: llvm-mc -triple i386-pc-linux-gnu %s -filetype=obj -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -triple i386-pc-linux-gnu %s -filetype=obj -o - | llvm-readobj -t | FileCheck %s .lcomm A, 5 .lcomm B, 32 << 20 -// CHECK: (('st_name', 0x00000001) # 'A' -// CHECK: ('st_value', 0x00000000) -// CHECK: ('st_size', 0x00000005) -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x1) -// CHECK: ('st_other', 0x00) -// CHECK: ('st_shndx', 0x0003) -// CHECK: ), -// CHECK: (('st_name', 0x00000003) # 'B' -// CHECK: ('st_value', 0x00000005) -// CHECK: ('st_size', 0x02000000) -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x1) -// CHECK: ('st_other', 0x00) -// CHECK: ('st_shndx', 0x0003) -// CHECK: ), +// CHECK: Symbol { +// CHECK: Name: A (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 5 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x3) +// CHECK-NEXT: } +// CHECK: Symbol { +// CHECK: Name: B (3) +// CHECK-NEXT: Value: 0x5 +// CHECK-NEXT: Size: 33554432 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x3) +// CHECK-NEXT: } diff --git a/test/MC/ELF/leb128.s b/test/MC/ELF/leb128.s index f6daac8ace5c..84c5b54fa1a5 100644 --- a/test/MC/ELF/leb128.s +++ b/test/MC/ELF/leb128.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s .sleb128 .Lfoo - .Lbar .Lfoo: @@ -6,14 +6,29 @@ .fill 126, 1, 0x90 .Lbar: -// CHECK: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000081) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '817f7f90 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90909090 90') +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 129 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 817F7F90 90909090 90909090 90909090 +// CHECK-NEXT: 0010: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0020: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0030: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0040: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0050: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0060: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0070: 90909090 90909090 90909090 90909090 +// CHECK-NEXT: 0080: 90 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/local-reloc.s b/test/MC/ELF/local-reloc.s index b32a9cc16973..4241ba5af410 100644 --- a/test/MC/ELF/local-reloc.s +++ b/test/MC/ELF/local-reloc.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -r -t | FileCheck %s // Test that relocations with local symbols are represented as relocations // with the section. They should be equivalent, but gas behaves like this. @@ -6,26 +6,8 @@ movl foo, %r14d foo: -// Section number 1 is .text -// CHECK: # Section 1 -// CHECK-next: (('sh_name', 0x00000001) # '.text' - -// Relocation refers to symbol number 2 -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), -// CHECK-NEXT: ]) - -// Symbol number 2 is section number 1 -// CHECK: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECKT: Relocations [ +// CHECK: Section (1) .text { +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S .text 0x{{[^ ]+}} +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/merge.s b/test/MC/ELF/merge.s index 11a80ad0350d..d34635a6710a 100644 --- a/test/MC/ELF/merge.s +++ b/test/MC/ELF/merge.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s // Test that PIC relocations with local symbols in a mergeable section are done // with a reference to the symbol. Not sure if this is a linker limitation, @@ -22,76 +22,13 @@ zed: .section bar,"ax",@progbits foo: -// Relocation 0 refers to symbol 1 -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000001) -// CHECK-NEXT: ('r_type', 0x00000002 -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), - -// Relocation 1 refers to symbol 6 -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), - -// Relocation 2 refers to symbol 1 -// CHECK-NEXT: # Relocation 2 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000001) -// CHECK-NEXT: ('r_type', 0x0000000a -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), - -// Relocation 3 refers to symbol 2 -// CHECK-NEXT: # Relocation 3 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000004 -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), - -// Relocation 4 refers to symbol 2 -// CHECK-NEXT: # Relocation 4 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x00000009 -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), - -// Relocation 5 refers to symbol 8 -// CHECK-NEXT: # Relocation 5 -// CHECK-NEXT: (('r_offset', 0x0000000000000023) -// CHECK-NEXT: ('r_sym', 0x00000008) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) - -// Section 5 is "sec1" -// CHECK: # Section 5 -// CHECK-NEXT: (('sh_name', 0x00000035) # '.sec1' - -// Symbol number 1 is .Lfoo -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000001) # '.Lfoo' - -// Symbol number 2 is foo -// CHECK: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000007) # 'foo' - -// Symbol number 6 is section 5 -// CHECK: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0005) - -// Symbol number 8 is zed -// CHECK: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x0000000b) # 'zed' +// CHECK: Relocations [ +// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PC32 .Lfoo 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .sec1 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32 .Lfoo 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PLT32 foo 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_GOTPCREL foo 0x{{[^ ]+}} +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_32S zed 0x{{[^ ]+}} +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/n_bytes.s b/test/MC/ELF/n_bytes.s index de6632232c06..e658de09a2fa 100644 --- a/test/MC/ELF/n_bytes.s +++ b/test/MC/ELF/n_bytes.s @@ -1,20 +1,30 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s .2byte 42, 1, 2, 3 .4byte 42, 1, 2, 3 .8byte 42, 1, 2, 3 .int 42, 1, 2, 3 -// CHECK: # Section 1 -// CHECK-NEXT: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000048) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', '2a000100 02000300 2a000000 01000000 02000000 03000000 2a000000 00000000 01000000 00000000 02000000 00000000 03000000 00000000 2a000000 01000000 02000000 03000000') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 72 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 2A000100 02000300 2A000000 01000000 +// CHECK-NEXT: 0010: 02000000 03000000 2A000000 00000000 +// CHECK-NEXT: 0020: 01000000 00000000 02000000 00000000 +// CHECK-NEXT: 0030: 03000000 00000000 2A000000 01000000 +// CHECK-NEXT: 0040: 02000000 03000000 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/noexec.s b/test/MC/ELF/noexec.s index d8b7b3233864..33cb8ae3452b 100644 --- a/test/MC/ELF/noexec.s +++ b/test/MC/ELF/noexec.s @@ -1,24 +1,26 @@ -// RUN: llvm-mc -mc-no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -mc-no-exec-stack -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x0000000c) # '.note.GNU-stack' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 4 +// CHECK-NEXT: Name: .note.GNU-stack +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: .note.GNU-stack (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .note.GNU-stack (0x4) +// CHECK-NEXT: } diff --git a/test/MC/ELF/norelocation.s b/test/MC/ELF/norelocation.s index c6394791ad80..137038292802 100644 --- a/test/MC/ELF/norelocation.s +++ b/test/MC/ELF/norelocation.s @@ -1,18 +1,26 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd -sr | FileCheck %s call bar bar: -// CHECK: ('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000005) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', 'e8000000 00') -// CHECK-NOT: .rela.text +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ (0x6) +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 5 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: E8000000 00 +// CHECK-NEXT: ) +// CHECK-NEXT: } // CHECK: shstrtab diff --git a/test/MC/ELF/org.s b/test/MC/ELF/org.s index 3afc364b2102..d878fa1aab45 100644 --- a/test/MC/ELF/org.s +++ b/test/MC/ELF/org.s @@ -1,13 +1,15 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s .zero 4 foo: .zero 4 .org foo+16 -// CHECK: (('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', -// CHECK-NEXT: ('sh_flags', -// CHECK-NEXT: ('sh_addr', -// CHECK-NEXT: ('sh_offset' -// CHECK-NEXT: ('sh_size', 0x0000000000000014) +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: +// CHECK-NEXT: Flags [ +// CHECK: ] +// CHECK-NEXT: Address: +// CHECK-NEXT: Offset: +// CHECK-NEXT: Size: 20 diff --git a/test/MC/ELF/pic-diff.s b/test/MC/ELF/pic-diff.s index 2c68f6cc718a..cffa0dd368eb 100644 --- a/test/MC/ELF/pic-diff.s +++ b/test/MC/ELF/pic-diff.s @@ -1,23 +1,20 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x000000000000000c) -// CHECK-NEXT: ('r_sym', 0x00000005) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000008) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[^ ]+}}) {{[^ ]+}} { +// CHECK-NEXT: 0xC R_X86_64_PC32 baz 0x8 +// CHECK-NEXT: } +// CHECK-NEXT: ] -// CHECK: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000005) # 'baz' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: baz (5) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } .zero 4 .data diff --git a/test/MC/ELF/plt.s b/test/MC/ELF/plt.s index 7d78e23443e7..604a4bf3a38e 100644 --- a/test/MC/ELF/plt.s +++ b/test/MC/ELF/plt.s @@ -1,14 +1,11 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s // Test that this produces a R_X86_64_PLT32. jmp foo@PLT -// CHECK: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x00000004) -// CHECK-NEXT: ('r_addend', -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[^ ]+}}) {{[^ ]+}} { +// CHECK-NEXT: 0x{{[^ ]+}} R_X86_64_PLT32 {{[^ ]+}} 0x{{[^ ]+}} +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/pr9292.s b/test/MC/ELF/pr9292.s index 05f377faa71c..a6e78dc992a8 100644 --- a/test/MC/ELF/pr9292.s +++ b/test/MC/ELF/pr9292.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that both foo and bar are undefined. @@ -7,20 +7,21 @@ mov %eax,bar -// CHECK: (('st_name', 0x00000005) # 'bar' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: bar (5) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } diff --git a/test/MC/ELF/relax-arith.s b/test/MC/ELF/relax-arith.s index 3236b41e532c..b8145564db08 100644 --- a/test/MC/ELF/relax-arith.s +++ b/test/MC/ELF/relax-arith.s @@ -1,11 +1,16 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s // Test that we correctly relax these instructions into versions that use // 16 or 32 bit immediate values. bar: -// CHECK: 'imul' -// CHECK: ('_section_data', '6669db00 0066691c 25000000 00000069 db000000 00691c25 00000000 00000000 4869db00 00000048 691c2500 00000000 000000') +// CHECK: Name: imul +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6669DB00 0066691C 25000000 00000069 +// CHECK-NEXT: 0010: DB000000 00691C25 00000000 00000000 +// CHECK-NEXT: 0020: 4869DB00 00000048 691C2500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section imul imul $foo, %bx, %bx imul $foo, bar, %bx @@ -14,8 +19,14 @@ bar: imul $foo, %rbx, %rbx imul $foo, bar, %rbx -// CHECK: and' -// CHECK:('_section_data', '6681e300 00668124 25000000 00000081 e3000000 00812425 00000000 00000000 4881e300 00000048 81242500 00000000 000000') + +// CHECK: Name: and +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6681E300 00668124 25000000 00000081 +// CHECK-NEXT: 0010: E3000000 00812425 00000000 00000000 +// CHECK-NEXT: 0020: 4881E300 00000048 81242500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section and and $foo, %bx andw $foo, bar @@ -24,8 +35,13 @@ bar: and $foo, %rbx andq $foo, bar -// CHECK: 'or' -// CHECK: ('_section_data', '6681cb00 0066810c 25000000 00000081 cb000000 00810c25 00000000 00000000 4881cb00 00000048 810c2500 00000000 000000') +// CHECK: Name: or +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6681CB00 0066810C 25000000 00000081 +// CHECK-NEXT: 0010: CB000000 00810C25 00000000 00000000 +// CHECK-NEXT: 0020: 4881CB00 00000048 810C2500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section or or $foo, %bx orw $foo, bar @@ -34,8 +50,13 @@ bar: or $foo, %rbx orq $foo, bar -// CHECK: 'xor' -// CHECK: ('_section_data', '6681f300 00668134 25000000 00000081 f3000000 00813425 00000000 00000000 4881f300 00000048 81342500 00000000 000000') +// CHECK: Name: xor +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6681F300 00668134 25000000 00000081 +// CHECK-NEXT: 0010: F3000000 00813425 00000000 00000000 +// CHECK-NEXT: 0020: 4881F300 00000048 81342500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section xor xor $foo, %bx xorw $foo, bar @@ -44,8 +65,13 @@ bar: xor $foo, %rbx xorq $foo, bar -// CHECK: 'add' -// CHECK: ('_section_data', '6681c300 00668104 25000000 00000081 c3000000 00810425 00000000 00000000 4881c300 00000048 81042500 00000000 000000') +// CHECK: Name: add +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6681C300 00668104 25000000 00000081 +// CHECK-NEXT: 0010: C3000000 00810425 00000000 00000000 +// CHECK-NEXT: 0020: 4881C300 00000048 81042500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section add add $foo, %bx addw $foo, bar @@ -54,8 +80,13 @@ bar: add $foo, %rbx addq $foo, bar -// CHECK: 'sub' -// CHECK: ('_section_data', '6681eb00 0066812c 25000000 00000081 eb000000 00812c25 00000000 00000000 4881eb00 00000048 812c2500 00000000 000000') +// CHECK: Name: sub +// CHECK: SectionData ( +// CHECK-NEXT: 000: 6681EB00 0066812C 25000000 00000081 +// CHECK-NEXT: 010: EB000000 00812C25 00000000 00000000 +// CHECK-NEXT: 020: 4881EB00 00000048 812C2500 00000000 +// CHECK-NEXT: 030: 000000 +// CHECK-NEXT: ) .section sub sub $foo, %bx subw $foo, bar @@ -64,8 +95,13 @@ bar: sub $foo, %rbx subq $foo, bar -// CHECK: 'cmp' -// CHECK: ('_section_data', '6681fb00 0066813c 25000000 00000081 fb000000 00813c25 00000000 00000000 4881fb00 00000048 813c2500 00000000 000000') +// CHECK: Name: cmp +// CHECK: SectionData ( +// CHECK-NEXT: 0000: 6681FB00 0066813C 25000000 00000081 +// CHECK-NEXT: 0010: FB000000 00813C25 00000000 00000000 +// CHECK-NEXT: 0020: 4881FB00 00000048 813C2500 00000000 +// CHECK-NEXT: 0030: 000000 +// CHECK-NEXT: ) .section cmp cmp $foo, %bx cmpw $foo, bar diff --git a/test/MC/ELF/relax.s b/test/MC/ELF/relax.s index 0b5d24f0f7ff..49ee8e2eefe0 100644 --- a/test/MC/ELF/relax.s +++ b/test/MC/ELF/relax.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd -t | FileCheck %s // Test that we do not relax these. @@ -11,17 +11,23 @@ foo: jmp foo jmp zed -// CHECK: ('sh_name', 0x00000001) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000006) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ('_section_data', 'ebfeebfc ebfa') - -// CHECK: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000005) # 'foo' +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 6 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: EBFEEBFC EBFA +// CHECK-NEXT: ) +// CHECK-NEXT: } +// CHECK: Symbol { +// CHECK: Name: foo (5) diff --git a/test/MC/ELF/relocation-386.s b/test/MC/ELF/relocation-386.s index 85da2eb8c949..24d0172e724e 100644 --- a/test/MC/ELF/relocation-386.s +++ b/test/MC/ELF/relocation-386.s @@ -1,205 +1,86 @@ -// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s // Test that we produce the correct relocation types and that the relocations // correctly point to the section or the symbol. -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x00000002) -// CHECK-NEXT: ('r_sym', 0x000001) -// CHECK-NEXT: ('r_type', 0x09) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x04) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 2 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x0a) -// CHECK-NEXT: ), - +// CHECK: Relocations [ +// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: 0x2 R_386_GOTOFF .Lfoo 0x0 +// CHECK-NEXT: 0x{{[^ ]+}} R_386_PLT32 bar2 0x0 +// CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 // Relocation 3 (bar3@GOTOFF) is done with symbol 7 (bss) -// CHECK-NEXT: # Relocation 3 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', 0x000007 -// CHECK-NEXT: ('r_type', -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x{{[^ ]+}} R_386_GOTOFF .bss 0x0 // Relocation 4 (bar2@GOT) is of type R_386_GOT32 -// CHECK-NEXT: # Relocation 4 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x03 -// CHECK-NEXT: ), +// CHECK-NEXT: 0x{{[^ ]+}} R_386_GOT32 bar2j 0x0 // Relocation 5 (foo@TLSGD) is of type R_386_TLS_GD -// CHECK-NEXT: # Relocation 5 -// CHECK-NEXT: (('r_offset', 0x00000020) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x12) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x20 R_386_TLS_GD foo 0x0 // Relocation 6 ($foo@TPOFF) is of type R_386_TLS_LE_32 -// CHECK-NEXT: # Relocation 6 -// CHECK-NEXT: (('r_offset', 0x00000025) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x22) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x25 R_386_TLS_LE_32 foo 0x0 // Relocation 7 (foo@INDNTPOFF) is of type R_386_TLS_IE -// CHECK-NEXT: # Relocation 7 -// CHECK-NEXT: (('r_offset', 0x0000002b) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x0f) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x2B R_386_TLS_IE foo 0x0 // Relocation 8 (foo@NTPOFF) is of type R_386_TLS_LE -// CHECK-NEXT: # Relocation 8 -// CHECK-NEXT: (('r_offset', 0x00000031) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x11) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x31 R_386_TLS_LE foo 0x0 // Relocation 9 (foo@GOTNTPOFF) is of type R_386_TLS_GOTIE -// CHECK-NEXT: # Relocation 9 -// CHECK-NEXT: (('r_offset', 0x00000037) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x10) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x37 R_386_TLS_GOTIE foo 0x0 // Relocation 10 (foo@TLSLDM) is of type R_386_TLS_LDM -// CHECK-NEXT: # Relocation 10 -// CHECK-NEXT: (('r_offset', 0x0000003d) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x13) -// CHECK-NEXT: ), - +// CHECK-NEXT: 0x3D R_386_TLS_LDM foo 0x0 // Relocation 11 (foo@DTPOFF) is of type R_386_TLS_LDO_32 -// CHECK-NEXT: # Relocation 11 -// CHECK-NEXT: (('r_offset', 0x00000043) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x20) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x43 R_386_TLS_LDO_32 foo 0x0 // Relocation 12 (calll 4096) is of type R_386_PC32 -// CHECK-NEXT: # Relocation 12 -// CHECK-NEXT: (('r_offset', 0x00000048) -// CHECK-NEXT: ('r_sym', 0x000000) -// CHECK-NEXT: ('r_type', 0x02) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x48 R_386_PC32 - 0x0 // Relocation 13 (zed@GOT) is of type R_386_GOT32 and uses the symbol -// CHECK-NEXT: # Relocation 13 -// CHECK-NEXT: (('r_offset', 0x0000004e) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x03) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x4E R_386_GOT32 zed 0x0 // Relocation 14 (zed@GOTOFF) is of type R_386_GOTOFF and uses the symbol -// CHECK-NEXT: # Relocation 14 -// CHECK-NEXT: (('r_offset', 0x00000054) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x09) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x54 R_386_GOTOFF zed 0x0 // Relocation 15 (zed@INDNTPOFF) is of type R_386_TLS_IE and uses the symbol -// CHECK-NEXT: # Relocation 15 -// CHECK-NEXT: (('r_offset', 0x0000005a) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x0f) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x5A R_386_TLS_IE zed 0x0 // Relocation 16 (zed@NTPOFF) is of type R_386_TLS_LE and uses the symbol -// CHECK-NEXT: # Relocation 16 -// CHECK-NEXT: (('r_offset', 0x00000060) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x11) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x60 R_386_TLS_LE zed 0x0 // Relocation 17 (zed@GOTNTPOFF) is of type R_386_TLS_GOTIE and uses the symbol -// CHECK-NEXT: # Relocation 17 -// CHECK-NEXT: (('r_offset', 0x00000066) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x10) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x66 R_386_TLS_GOTIE zed 0x0 // Relocation 18 (zed@PLT) is of type R_386_PLT32 and uses the symbol -// CHECK-NEXT: # Relocation 18 -// CHECK-NEXT: (('r_offset', 0x0000006b) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x04) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x6B R_386_PLT32 zed 0x0 // Relocation 19 (zed@TLSGD) is of type R_386_TLS_GD and uses the symbol -// CHECK-NEXT: # Relocation 19 -// CHECK-NEXT: (('r_offset', 0x00000071) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x12) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x71 R_386_TLS_GD zed 0x0 // Relocation 20 (zed@TLSLDM) is of type R_386_TLS_LDM and uses the symbol -// CHECK-NEXT: # Relocation 20 -// CHECK-NEXT: (('r_offset', 0x00000077) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x13) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x77 R_386_TLS_LDM zed 0x0 // Relocation 21 (zed@TPOFF) is of type R_386_TLS_LE_32 and uses the symbol -// CHECK-NEXT:# Relocation 21 -// CHECK-NEXT: (('r_offset', 0x0000007d) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x22) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x7D R_386_TLS_LE_32 zed 0x0 // Relocation 22 (zed@DTPOFF) is of type R_386_TLS_LDO_32 and uses the symbol -// CHECK-NEXT: Relocation 22 -// CHECK-NEXT: (('r_offset', 0x00000083) -// CHECK-NEXT: ('r_sym', 0x000004) -// CHECK-NEXT: ('r_type', 0x20) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x83 R_386_TLS_LDO_32 zed 0x0 // Relocation 23 ($bar) is of type R_386_32 and uses the section -// CHECK-NEXT: Relocation 23 -// CHECK-NEXT: (('r_offset', -// CHECK-NEXT: ('r_sym', -// CHECK-NEXT: ('r_type', 0x01) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x{{[^ ]+}} R_386_32 .text 0x0 // Relocation 24 (foo@GOTTPOFF(%edx)) is of type R_386_TLS_IE_32 and uses the // symbol -// CHECK-NEXT: Relocation 24 -// CHECK-NEXT: (('r_offset', 0x0000008e) -// CHECK-NEXT: ('r_sym', 0x00000d) -// CHECK-NEXT: ('r_type', 0x21) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x8E R_386_TLS_IE_32 foo 0x0 // Relocation 25 (_GLOBAL_OFFSET_TABLE_-bar2) is of type R_386_GOTPC. -// CHECK-NEXT: Relocation 25 -// CHECK-NEXT: (('r_offset', 0x00000094) -// CHECK-NEXT: ('r_sym', 0x00000b) -// CHECK-NEXT: ('r_type', 0x0a) -// CHECK-NEXT: ), +// CHECK-NEXT: 0x94 R_386_GOTPC _GLOBAL_OFFSET_TABLE_ 0x0 // Relocation 26 (und_symbol-bar2) is of type R_386_PC32 -// CHECK-NEXT: Relocation 26 -// CHECK-NEXT: (('r_offset', 0x0000009a) -// CHECK-NEXT: ('r_sym', 0x00000e) -// CHECK-NEXT: ('r_type', 0x02) -// CHECK-NEXT: ), - -// Section 4 is bss -// CHECK: # Section 4 -// CHECK-NEXT: (('sh_name', 0x0000000b) # '.bss' - -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000005) # '.Lfoo' +// CHECK-NEXT: 0x9A R_386_PC32 und_symbol 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: ] // Symbol 4 is zed -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000035) # 'zed' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0005) - +// CHECK: Symbol { +// CHECK: Name: zed (53) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: zedsec (0x5) +// CHECK-NEXT: } // Symbol 7 is section 4 -// CHECK: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) - +// CHECK: Symbol { +// CHECK: Name: .bss (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: } .text bar: diff --git a/test/MC/ELF/relocation-pc.s b/test/MC/ELF/relocation-pc.s index b6279c3e55dd..551f5ff378ef 100644 --- a/test/MC/ELF/relocation-pc.s +++ b/test/MC/ELF/relocation-pc.s @@ -1,33 +1,32 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr | FileCheck %s // Test that we produce the correct relocation. loope 0 # R_X86_64_PC8 jmp -256 # R_X86_64_PC32 -// CHECK: # Section 2 -// CHECK-NEXT: (('sh_name', 0x00000001) # '.rela.text' -// CHECK-NEXT: ('sh_type', 0x00000004) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x00000000000002e8) -// CHECK-NEXT: ('sh_size', 0x0000000000000030) -// CHECK-NEXT: ('sh_link', 0x00000006) -// CHECK-NEXT: ('sh_info', 0x00000001) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000008) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000018) -// CHECK-NEXT: ('_relocations', [ -// CHECK-NEXT: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000001) -// CHECK-NEXT: ('r_sym', 0x00000000) -// CHECK-NEXT: ('r_type', 0x0000000f) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000003) -// CHECK-NEXT: ('r_sym', 0x00000000) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: .text +// CHECK: Relocations [ +// CHECK-NEXT: 0x1 R_X86_64_PC8 - 0x0 +// CHECK-NEXT: 0x3 R_X86_64_PC32 - 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: } + +// CHECK: Section { +// CHECK: Index: 2 +// CHECK-NEXT: Name: .rela.text +// CHECK-NEXT: Type: SHT_RELA +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x2E8 +// CHECK-NEXT: Size: 48 +// CHECK-NEXT: Link: 6 +// CHECK-NEXT: Info: 1 +// CHECK-NEXT: AddressAlignment: 8 +// CHECK-NEXT: EntrySize: 24 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: ] +// CHECK-NEXT: } diff --git a/test/MC/ELF/relocation.s b/test/MC/ELF/relocation.s index 5db213bc0497..19bcc18d8f88 100644 --- a/test/MC/ELF/relocation.s +++ b/test/MC/ELF/relocation.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -t | FileCheck %s // Test that we produce the correct relocation. @@ -20,102 +20,33 @@ bar: addq $bar,%rax # R_X86_64_32S -// CHECK: # Section 1 -// CHECK: (('sh_name', 0x00000006) # '.text' +// CHECK: Section { +// CHECK: Name: .text +// CHECK: Relocations [ +// CHECK-NEXT: 0x1 R_X86_64_32 .text +// CHECK-NEXT: 0x8 R_X86_64_32S .text +// CHECK-NEXT: 0x13 R_X86_64_32S .text +// CHECK-NEXT: 0x1A R_X86_64_32S .text +// CHECK-NEXT: 0x22 R_X86_64_32S .text +// CHECK-NEXT: 0x26 R_X86_64_32 .text +// CHECK-NEXT: 0x2D R_X86_64_GOTTPOFF foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x34 R_X86_64_TLSGD foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x3B R_X86_64_TPOFF32 foo 0x0 +// CHECK-NEXT: 0x42 R_X86_64_TLSLD foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x49 R_X86_64_DTPOFF32 foo 0x0 +// CHECK-NEXT: 0x4E R_X86_64_32S .text 0x0 +// CHECK-NEXT: 0x55 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x5C R_X86_64_PC32 foo 0x5C +// CHECK-NEXT: 0x63 R_X86_64_32S .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: } -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000001) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000008) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 2 -// CHECK-NEXT: (('r_offset', 0x0000000000000013) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 3 -// CHECK-NEXT: (('r_offset', 0x000000000000001a) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 4 -// CHECK-NEXT: (('r_offset', 0x0000000000000022) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 5 -// CHECK-NEXT: (('r_offset', 0x0000000000000026) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', - -// CHECK: # Relocation 6 -// CHECK-NEXT: (('r_offset', 0x000000000000002d) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000016) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) - -// CHECK: # Relocation 7 -// CHECK-NEXT: (('r_offset', 0x0000000000000034) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000013) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) - -// CHECK: # Relocation 8 -// CHECK-NEXT: (('r_offset', 0x000000000000003b) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000017) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) - -// CHECK: # Relocation 9 -// CHECK-NEXT: (('r_offset', 0x0000000000000042) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000014) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) - -// CHECK: # Relocation 10 -// CHECK-NEXT: (('r_offset', 0x0000000000000049) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000015) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) - -// CHECK: # Relocation 11 -// CHECK-NEXT: (('r_offset', 0x000000000000004e) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) - -// CHECK: # Relocation 12 -// CHECK-NEXT: (('r_offset', 0x0000000000000055) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) - -// CHECK: # Relocation 13 -// CHECK-NEXT: (('r_offset', 0x000000000000005c) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0x000000000000005c) - -// CHECK: # Relocation 14 -// CHECK-NEXT: (('r_offset', 0x0000000000000063) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) - -// CHECK: # Symbol 2 -// CHECK: (('st_name', 0x00000000) # '' -// CHECK: ('st_bind', 0x0) -// CHECK: ('st_type', 0x3) -// CHECK: ('st_other', 0x00) -// CHECK: ('st_shndx', 0x0001) +// CHECK: Symbol { +// CHECK: Name: .text (0) +// CHECK-NEXT: Value: +// CHECK-NEXT: Size: +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } diff --git a/test/MC/ELF/rename.s b/test/MC/ELF/rename.s index 241aa05ecbde..c50910b41ec0 100644 --- a/test/MC/ELF/rename.s +++ b/test/MC/ELF/rename.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sr -t | FileCheck %s // When doing a rename, all the checks for where the relocation should go // should be performed with the original symbol. Only if we decide to relocate @@ -16,31 +16,33 @@ defined3: .global defined1 // Section 1 is .text -// CHECK: # Section 1 -// CHECK-NEXT: (('sh_name', 0x00000006) # '.text' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000040) -// CHECK-NEXT: ('sh_size', 0x0000000000000004) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000004) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) - -// The relocation uses symbol 2 -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000000) -// CHECK-NEXT: ('r_sym', 0x00000002) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) +// CHECK: Section { +// CHECK: Index: 1 +// CHECK-NEXT: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 4 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: Relocations [ +// CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 +// CHECK-NEXT: ] +// CHECK-NEXT: } // Symbol 2 is section 1 -// CHECK: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) +// CHECK: Symbol { +// CHECK: Name: .text (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } diff --git a/test/MC/ELF/section.s b/test/MC/ELF/section.s index c71e1a72c471..a6794034c94d 100644 --- a/test/MC/ELF/section.s +++ b/test/MC/ELF/section.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s | FileCheck %s // Test that these names are accepted. @@ -7,10 +7,10 @@ .section .note.GNU-,"",@progbits .section -.note.GNU,"",@progbits -// CHECK: ('sh_name', 0x00000038) # '.note.GNU-stack' -// CHECK: ('sh_name', 0x0000008f) # '.note.GNU-stack2' -// CHECK: ('sh_name', 0x000000a0) # '.note.GNU-' -// CHECK: ('sh_name', 0x00000084) # '-.note.GNU' +// CHECK: Name: .note.GNU-stack (56) +// CHECK: Name: .note.GNU-stack2 (143) +// CHECK: Name: .note.GNU- (160) +// CHECK: Name: -.note.GNU (132) // Test that the defaults are used @@ -19,66 +19,81 @@ .section .rodata .section zed, "" -// CHECK: (('sh_name', 0x00000012) # '.init' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 11 -// CHECK-NEXT: (('sh_name', 0x00000048) # '.fini' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000006) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 12 -// CHECK-NEXT: (('sh_name', 0x00000076) # '.rodata' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Section 13 -// CHECK-NEXT: (('sh_name', 0x00000058) # 'zed' -// CHECK-NEXT: ('sh_type', 0x00000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .init +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 11 +// CHECK-NEXT: Name: .fini +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 12 +// CHECK-NEXT: Name: .rodata +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } +// CHECK-NEXT: Section { +// CHECK-NEXT: Index: 13 +// CHECK-NEXT: Name: zed +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } .section .note.test,"",@note -// CHECK: (('sh_name', 0x00000007) # '.note.test' -// CHECK-NEXT: ('sh_type', 0x00000007) -// CHECK-NEXT: ('sh_flags', 0x0000000000000000) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .note.test +// CHECK-NEXT: Type: SHT_NOTE +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } // Test that we can parse these foo: @@ -90,21 +105,26 @@ bar: .section .eh_frame,"a",@unwind -// CHECK: (('sh_name', 0x0000004e) # '.eh_frame' -// CHECK-NEXT: ('sh_type', 0x70000001) -// CHECK-NEXT: ('sh_flags', 0x0000000000000002) -// CHECK-NEXT: ('sh_addr', 0x0000000000000000) -// CHECK-NEXT: ('sh_offset', 0x0000000000000050) -// CHECK-NEXT: ('sh_size', 0x0000000000000000) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x0000000000000001) -// CHECK-NEXT: ('sh_entsize', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .eh_frame +// CHECK-NEXT: Type: SHT_X86_64_UNWIND +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x50 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: } // Test that we handle the strings like gas .section bar-"foo" .section "foo" -// CHECK: ('sh_name', 0x000000ab) # 'bar-"foo"' -// CHECK: ('sh_name', 0x00000034) # 'foo' +// CHECK: Section { +// CHECK: Name: bar-"foo" (171) +// CHECK: Section { +// CHECK: Name: foo (52) diff --git a/test/MC/ELF/set.s b/test/MC/ELF/set.s index 2258b1923678..f6965a583a9f 100644 --- a/test/MC/ELF/set.s +++ b/test/MC/ELF/set.s @@ -1,17 +1,18 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that we emit the correct value. .set kernbase,0xffffffff80000000 -// CHECK: (('st_name', 0x00000001) # 'kernbase' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0xfff1) -// CHECK-NEXT: ('st_value', 0xffffffff80000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: kernbase (1) +// CHECK-NEXT: Value: 0xFFFFFFFF80000000 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0xFFF1) +// CHECK-NEXT: } // Test that we accept .set of a symbol after it has been used in a statement. @@ -24,11 +25,12 @@ .set foo2,bar2 // Test that there is an undefined reference to bar -// CHECK: (('st_name', 0x0000000a) # 'bar' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: bar (10) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } diff --git a/test/MC/ELF/sleb.s b/test/MC/ELF/sleb.s index 00e5b4bf2821..5cba5829a12b 100644 --- a/test/MC/ELF/sleb.s +++ b/test/MC/ELF/sleb.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 %s // RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s // RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s @@ -19,10 +19,14 @@ foo: .sleb128 8193 -// ELF_32: ('sh_name', 0x00000001) # '.text' -// ELF_32: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') -// ELF_64: ('sh_name', 0x00000001) # '.text' -// ELF_64: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') +// ELF_32: Name: .text +// ELF_32: SectionData ( +// ELF_32: 0000: 00017F3F 40C000BF 7FFF3F80 4081C000 +// ELF_32: ) +// ELF_64: Name: .text +// ELF_64: SectionData ( +// ELF_64: 0000: 00017F3F 40C000BF 7FFF3F80 4081C000 +// ELF_64: ) // MACHO_32: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // MACHO_32: ('_section_data', '00017f3f 40c000bf 7fff3f80 4081c000') // MACHO_64: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') diff --git a/test/MC/ELF/subsection.s b/test/MC/ELF/subsection.s new file mode 100644 index 000000000000..d437cacf6347 --- /dev/null +++ b/test/MC/ELF/subsection.s @@ -0,0 +1,37 @@ +// RUN: llvm-mc -filetype=obj %s -o - -triple x86_64-pc-linux | llvm-objdump -s - | FileCheck %s + +// CHECK: Contents of section .text: +// CHECK-NEXT: 0000 03042502 00000003 04250100 0000ebf7 +.text 1 +add 1, %eax +jmp label +.subsection +add 2, %eax +label: + +// CHECK-NOT: Contents of section .rela.text: + +// CHECK: Contents of section .data: +// CHECK-NEXT: 0000 01030402 74657374 +.data +l0: +.byte 1 +.subsection 1+1 +l1: +.byte 2 +l2: +.subsection l2-l1 +.byte l1-l0 +.subsection 3 +.ascii "test" +.previous +.byte 4 + +// CHECK: Contents of section test: +// CHECK-NEXT: 0000 010302 +.section test +.byte 1 +.pushsection test, 1 +.byte 2 +.popsection +.byte 3 diff --git a/test/MC/ELF/symref.s b/test/MC/ELF/symref.s index 2dfa058ab086..9a71a81930ee 100644 --- a/test/MC/ELF/symref.s +++ b/test/MC/ELF/symref.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s defined1: defined2: @@ -21,145 +21,122 @@ defined3: .symver global1, g1@@zed global1: +// CHECK: Relocations [ +// CHECK-NEXT: Section (1) .text { +// CHECK-NEXT: 0x0 R_X86_64_32 .text 0x0 +// CHECK-NEXT: 0x4 R_X86_64_32 bar2@zed 0x0 +// CHECK-NEXT: 0x8 R_X86_64_32 .text 0x0 +// CHECK-NEXT: 0xC R_X86_64_32 .text 0x0 +// CHECK-NEXT: 0x10 R_X86_64_32 bar6@zed 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: ] -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000000) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000004) -// CHECK-NEXT: ('r_sym', 0x0000000b) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 2 -// CHECK-NEXT: (('r_offset', 0x0000000000000008) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 3 -// CHECK-NEXT: (('r_offset', 0x000000000000000c) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 4 -// CHECK-NEXT: (('r_offset', 0x0000000000000010) -// CHECK-NEXT: ('r_sym', 0x0000000c) -// CHECK-NEXT: ('r_type', 0x0000000a) -// CHECK-NEXT: ('r_addend', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT:]) - -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000013) # 'bar1@zed' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000025) # 'bar3@@zed' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 3 -// CHECK-NEXT: (('st_name', 0x0000002f) # 'bar5@@zed' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000001) # 'defined1' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x0000000a) # 'defined2' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0003) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x0000004a) # 'g1@@zed' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000014) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 10 -// CHECK-NEXT: (('st_name', 0x00000042) # 'global1' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000014) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 11 -// CHECK-NEXT: (('st_name', 0x0000001c) # 'bar2@zed' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 12 -// CHECK-NEXT: (('st_name', 0x00000039) # 'bar6@zed' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT:]) +// CHECK: Symbol { +// CHECK: Name: bar1@zed (19) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar3@@zed (37) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar5@@zed (47) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: defined1 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: defined2 (10) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .text (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .data (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data (0x3) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .bss (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: g1@@zed (74) +// CHECK-NEXT: Value: 0x14 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: global1 (66) +// CHECK-NEXT: Value: 0x14 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar2@zed (28) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar6@zed (57) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/tls-i386.s b/test/MC/ELF/tls-i386.s index 922d4c6e6c2c..267046ef5bfb 100644 --- a/test/MC/ELF/tls-i386.s +++ b/test/MC/ELF/tls-i386.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that all symbols are of type STT_TLS. @@ -17,129 +17,129 @@ .long fooD@DTPOFF .long fooE@INDNTPOFF -// CHECK: (('st_name', 0x00000001) # 'foo1' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000006) # 'foo2' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x0000000b) # 'foo3' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x00000010) # 'foo4' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x00000015) # 'foo5' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 10 -// CHECK-NEXT: (('st_name', 0x0000001a) # 'foo6' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 11 -// CHECK-NEXT: (('st_name', 0x0000001f) # 'foo7' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 12 -// CHECK-NEXT: (('st_name', 0x00000024) # 'foo8' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 13 -// CHECK-NEXT: (('st_name', 0x00000029) # 'foo9' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 14 -// CHECK-NEXT: (('st_name', 0x0000002e) # 'fooA' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 15 -// CHECK-NEXT: (('st_name', 0x00000033) # 'fooB' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 16 -// CHECK-NEXT: (('st_name', 0x00000038) # 'fooC' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 17 -// CHECK-NEXT: (('st_name', 0x0000003d) # 'fooD' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 18 -// CHECK-NEXT: (('st_name', 0x00000042) # 'fooE' -// CHECK-NEXT: ('st_value', 0x00000000) -// CHECK-NEXT: ('st_size', 0x00000000) -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ), - +// CHECK: Symbol { +// CHECK: Name: foo1 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo2 (6) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo3 (11) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo4 (16) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo5 (21) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo6 (26) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo7 (31) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo8 (36) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo9 (41) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: fooA (46) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: fooB (51) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: fooC (56) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: fooD (61) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: fooE (66) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } diff --git a/test/MC/ELF/tls.s b/test/MC/ELF/tls.s index fe2bb4e73307..c71e3962bb49 100644 --- a/test/MC/ELF/tls.s +++ b/test/MC/ELF/tls.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that all symbols are of type STT_TLS. @@ -12,66 +12,67 @@ foobar: .long 43 -// CHECK: (('st_name', 0x0000001f) # 'foobar' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0005) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: foobar (31) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .zed (0x5) +// CHECK-NEXT: } -// CHECK: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo1' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x00000006) # 'foo2' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x0000000b) # 'foo3' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 10 -// CHECK-NEXT: (('st_name', 0x00000010) # 'foo4' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 11 -// CHECK-NEXT: (('st_name', 0x00000015) # 'foo5' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 12 -// CHECK-NEXT: (('st_name', 0x0000001a) # 'foo6' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x6) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbol { +// CHECK: Name: foo1 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo2 (6) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo3 (11) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo4 (16) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo5 (21) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo6 (26) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } diff --git a/test/MC/ELF/type.s b/test/MC/ELF/type.s index ec53e4ffa524..a5b98129c94a 100644 --- a/test/MC/ELF/type.s +++ b/test/MC/ELF/type.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that both % and @ are accepted. .global foo @@ -12,35 +12,76 @@ bar: // Test that gnu_unique_object is accepted. .type zed,@gnu_unique_object +obj: + .global obj + .type obj,@object + .type obj,@notype + +func: + .global func + .type func,@function + .type func,@object + ifunc: .global ifunc .type ifunc,@gnu_indirect_function -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000005) # 'bar' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x2) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000009) # 'ifunc' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0xa) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +tls: + .global tls + .type tls,@tls_object + .type tls,@gnu_indirect_function +// CHECK: Symbol { +// CHECK: Name: bar +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Function +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: func +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Function +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: ifunc +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: GNU_IFunc +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: obj +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: tls +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: TLS +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } diff --git a/test/MC/ELF/uleb.s b/test/MC/ELF/uleb.s index 1e4734bcafc6..d755cc23e392 100644 --- a/test/MC/ELF/uleb.s +++ b/test/MC/ELF/uleb.s @@ -1,5 +1,5 @@ -// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_32 %s -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=ELF_64 %s +// RUN: llvm-mc -filetype=obj -triple i686-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_32 %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck -check-prefix=ELF_64 %s // RUN: llvm-mc -filetype=obj -triple i386-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_32 %s // RUN: llvm-mc -filetype=obj -triple x86_64-apple-darwin9 %s -o - | macho-dump --dump-section-data | FileCheck -check-prefix=MACHO_64 %s @@ -12,10 +12,14 @@ foo: .uleb128 16383 .uleb128 16384 -// ELF_32: ('sh_name', 0x00000001) # '.text' -// ELF_32: ('_section_data', '00017f80 01ff7f80 8001') -// ELF_64: ('sh_name', 0x00000001) # '.text' -// ELF_64: ('_section_data', '00017f80 01ff7f80 8001') +// ELF_32: Name: .text +// ELF_32: SectionData ( +// ELF_32: 0000: 00017F80 01FF7F80 8001 +// ELF_32: ) +// ELF_64: Name: .text +// ELF_64: SectionData ( +// ELF_64: 0000: 00017F80 01FF7F80 8001 +// ELF_64: ) // MACHO_32: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') // MACHO_32: ('_section_data', '00017f80 01ff7f80 8001') // MACHO_64: ('section_name', '__text\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00') diff --git a/test/MC/ELF/undef.s b/test/MC/ELF/undef.s index e377c6331747..0d89fb129361 100644 --- a/test/MC/ELF/undef.s +++ b/test/MC/ELF/undef.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test which symbols should be in the symbol table @@ -19,28 +19,21 @@ .text movsd .Lsym8(%rip), %xmm1 -// CHECK: ('_symbols', [ -// CHECK-NEXT: # Symbol 0 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x0000000d) # '.Lsym8' -// CHECK: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 3 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000001) # '.Lsym1' -// CHECK: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000008) # 'sym6' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x1) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Symbols [ + +// CHECK: Symbol { +// CHECK: Name: .Lsym8 + +// CHECK: Symbol { +// CHECK: Name: .Lsym1 + +// CHECK: Symbol { +// CHECK: Name: sym6 +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: Object +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/undef2.s b/test/MC/ELF/undef2.s index 6f971c55bf6c..6aa66c05c4bb 100644 --- a/test/MC/ELF/undef2.s +++ b/test/MC/ELF/undef2.s @@ -1,10 +1,18 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -t | FileCheck %s // Test that this produces an undefined reference to .Lfoo je .Lfoo -// CHECK: ('_symbols', [ -// CHECK: (('st_name', 0x00000001) # '.Lfoo' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK: (('sh_name', 0x0000001b) # '.strtab' +// CHECK: Section { +// CHECK: Name: .strtab + +// CHECK: Symbol { +// CHECK: Name: .Lfoo +// CHECK-NEXT: Value: +// CHECK-NEXT: Size: +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: +// CHECK-NEXT: Other: +// CHECK-NEXT: Section: +// CHECK-NEXT: } diff --git a/test/MC/ELF/version.s b/test/MC/ELF/version.s index 31e952afeb40..0bc9c8b7a782 100644 --- a/test/MC/ELF/version.s +++ b/test/MC/ELF/version.s @@ -1,17 +1,23 @@ -// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple i386-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s .version "1234" .version "123" -// CHECK: (('sh_name', 0x0000000c) # '.note' -// CHECK-NEXT: ('sh_type', 0x00000007) -// CHECK-NEXT: ('sh_flags', 0x00000000) -// CHECK-NEXT: ('sh_addr', 0x00000000) -// CHECK-NEXT: ('sh_offset', 0x00000034) -// CHECK-NEXT: ('sh_size', 0x00000024) -// CHECK-NEXT: ('sh_link', 0x00000000) -// CHECK-NEXT: ('sh_info', 0x00000000) -// CHECK-NEXT: ('sh_addralign', 0x00000004) -// CHECK-NEXT: ('sh_entsize', 0x00000000) -// CHECK-NEXT: ('_section_data', '05000000 00000000 01000000 31323334 00000000 04000000 00000000 01000000 31323300') -// CHECK-NEXT: ), +// CHECK: Section { +// CHECK: Name: .note +// CHECK-NEXT: Type: SHT_NOTE +// CHECK-NEXT: Flags [ +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x34 +// CHECK-NEXT: Size: 36 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 05000000 00000000 01000000 31323334 +// CHECK-NEXT: 0010: 00000000 04000000 00000000 01000000 +// CHECK-NEXT: 0020: 31323300 +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/ELF/weak-relocation.s b/test/MC/ELF/weak-relocation.s index 88e841e65bf5..0f5bba2383d7 100644 --- a/test/MC/ELF/weak-relocation.s +++ b/test/MC/ELF/weak-relocation.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r | FileCheck %s // Test that weak symbols always produce relocations @@ -7,9 +7,8 @@ foo: bar: call foo -//CHECK: # Relocation 0 -//CHECK-NEXT: (('r_offset', 0x0000000000000001) -//CHECK-NEXT: ('r_sym', 0x00000005) -//CHECK-NEXT: ('r_type', 0x00000002) -//CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) -//CHECK-NEXT: ), +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[0-9]+}}) .text { +// CHECK-NEXT: 0x1 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/weak.s b/test/MC/ELF/weak.s index 07a83913631a..2ed3eb7b2bd4 100644 --- a/test/MC/ELF/weak.s +++ b/test/MC/ELF/weak.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // Test that this produces a weak undefined symbol. @@ -9,22 +9,22 @@ .weak bar bar: -//CHECK: # Symbol 4 -//CHECK-NEXT: (('st_name', 0x00000005) # 'bar' -//CHECK-NEXT: ('st_bind', 0x2) -//CHECK-NEXT: ('st_type', 0x0) -//CHECK-NEXT: ('st_other', 0x00) -//CHECK-NEXT: ('st_shndx', 0x0001) -//CHECK-NEXT: ('st_value', 0x0000000000000004) -//CHECK-NEXT: ('st_size', 0x0000000000000000) -//CHECK-NEXT: ), -//CHECK-NEXT: # Symbol 5 -//CHECK: (('st_name', 0x00000001) # 'foo' -//CHECK-NEXT: ('st_bind', 0x2) -//CHECK-NEXT: ('st_type', 0x0) -//CHECK-NEXT: ('st_other', 0x00) -//CHECK-NEXT: ('st_shndx', 0x0000) -//CHECK-NEXT: ('st_value', 0x0000000000000000) -//CHECK-NEXT: ('st_size', 0x0000000000000000) -//CHECK-NEXT: ), -//CHECK-NEXT: ]) +// CHECK: Symbol { +// CHECK: Name: bar +// CHECK-NEXT: Value: 0x4 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text +// CHECK-NEXT: } +// CHECK: Symbol { +// CHECK: Name: foo +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/weakref-plt.s b/test/MC/ELF/weakref-plt.s index 2e500935b6db..d6486dcd5283 100644 --- a/test/MC/ELF/weakref-plt.s +++ b/test/MC/ELF/weakref-plt.s @@ -1,8 +1,14 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s .weakref bar,foo call bar@PLT -// CHECK: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x2) +// CHECK: Symbol { +// CHECK: Name: foo +// CHECK-NEXT: Value: +// CHECK-NEXT: Size: +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: +// CHECK-NEXT: Other: +// CHECK-NEXT: Section: +// CHECK-NEXT: } diff --git a/test/MC/ELF/weakref-reloc.s b/test/MC/ELF/weakref-reloc.s index 4bbf2645a8cd..48bda8748fde 100644 --- a/test/MC/ELF/weakref-reloc.s +++ b/test/MC/ELF/weakref-reloc.s @@ -1,49 +1,44 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -r -t | FileCheck %s // Test that the relocations point to the correct symbols. We used to get the // symbol index wrong for weakrefs when creating _GLOBAL_OFFSET_TABLE_. - .weakref bar,foo + .weakref bar,foo call zed@PLT - call bar + call bar -// CHECK: # Relocation 0 -// CHECK-NEXT: (('r_offset', 0x0000000000000001) -// CHECK-NEXT: ('r_sym', 0x00000006) -// CHECK-NEXT: ('r_type', 0x00000004) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) -// CHECK-NEXT: ), -// CHECK-NEXT: # Relocation 1 -// CHECK-NEXT: (('r_offset', 0x0000000000000006) -// CHECK-NEXT: ('r_sym', 0x00000005) -// CHECK-NEXT: ('r_type', 0x00000002) -// CHECK-NEXT: ('r_addend', 0xfffffffffffffffc) -// CHECK-NEXT: ), +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[0-9]+}}) {{[^ ]+}} { +// CHECK-NEXT: 0x1 R_X86_64_PLT32 zed 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: 0x6 R_X86_64_PC32 foo 0xFFFFFFFFFFFFFFFC +// CHECK-NEXT: } +// CHECK-NEXT: ] -// CHECK: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000009) # '_GLOBAL_OFFSET_TABLE_' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000001) # 'foo' -// CHECK-NEXT: ('st_bind', 0x2) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000005) # 'zed' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), +// CHECK: Symbols [ +// CHECK: Symbol { +// CHECK: Name: _GLOBAL_OFFSET_TABLE_ (9) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: foo (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: zed (5) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } diff --git a/test/MC/ELF/weakref.s b/test/MC/ELF/weakref.s index e12d2c74eb8a..87173641b56f 100644 --- a/test/MC/ELF/weakref.s +++ b/test/MC/ELF/weakref.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -t | FileCheck %s // This is a long test that checks that the aliases created by weakref are // never in the symbol table and that the only case it causes a symbol to @@ -69,166 +69,158 @@ bar15: .long bar15 .long foo15 -// CHECK: # Symbol 0 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 1 -// CHECK-NEXT: (('st_name', 0x00000015) # 'bar6' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000018) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 2 -// CHECK-NEXT: (('st_name', 0x0000001a) # 'bar7' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000018) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 3 -// CHECK-NEXT: (('st_name', 0x0000001f) # 'bar8' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x000000000000001c) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 4 -// CHECK-NEXT: (('st_name', 0x00000024) # 'bar9' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000020) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 5 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 6 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0003) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 7 -// CHECK-NEXT: (('st_name', 0x00000000) # '' -// CHECK-NEXT: ('st_bind', 0x0) -// CHECK-NEXT: ('st_type', 0x3) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0004) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 8 -// CHECK-NEXT: (('st_name', 0x00000029) # 'bar10' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000028) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 9 -// CHECK-NEXT: (('st_name', 0x0000002f) # 'bar11' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000030) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 10 -// CHECK-NEXT: (('st_name', 0x00000035) # 'bar12' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000030) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 11 -// CHECK-NEXT: (('st_name', 0x0000003b) # 'bar13' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000034) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 12 -// CHECK-NEXT: (('st_name', 0x00000041) # 'bar14' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000038) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 13 -// CHECK-NEXT: (('st_name', 0x00000047) # 'bar15' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0001) -// CHECK-NEXT: ('st_value', 0x0000000000000040) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 14 -// CHECK-NEXT: (('st_name', 0x00000001) # 'bar2' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 15 -// CHECK-NEXT: (('st_name', 0x00000006) # 'bar3' -// CHECK-NEXT: ('st_bind', 0x2) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 16 -// CHECK-NEXT: (('st_name', 0x0000000b) # 'bar4' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: # Symbol 17 -// CHECK-NEXT: (('st_name', 0x00000010) # 'bar5' -// CHECK-NEXT: ('st_bind', 0x1) -// CHECK-NEXT: ('st_type', 0x0) -// CHECK-NEXT: ('st_other', 0x00) -// CHECK-NEXT: ('st_shndx', 0x0000) -// CHECK-NEXT: ('st_value', 0x0000000000000000) -// CHECK-NEXT: ('st_size', 0x0000000000000000) -// CHECK-NEXT: ), -// CHECK-NEXT: ]) +// CHECK: Symbols [ +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar6 (21) +// CHECK-NEXT: Value: 0x18 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar7 (26) +// CHECK-NEXT: Value: 0x18 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar8 (31) +// CHECK-NEXT: Value: 0x1C +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar9 (36) +// CHECK-NEXT: Value: 0x20 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .text (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .data (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .data (0x3) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: .bss (0) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Local +// CHECK-NEXT: Type: Section +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .bss (0x4) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar10 (41) +// CHECK-NEXT: Value: 0x28 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar11 (47) +// CHECK-NEXT: Value: 0x30 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar12 (53) +// CHECK-NEXT: Value: 0x30 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar13 (59) +// CHECK-NEXT: Value: 0x34 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar14 (65) +// CHECK-NEXT: Value: 0x38 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar15 (71) +// CHECK-NEXT: Value: 0x40 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: .text (0x1) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar2 (1) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar3 (6) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Weak +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar4 (11) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: Symbol { +// CHECK-NEXT: Name: bar5 (16) +// CHECK-NEXT: Value: 0x0 +// CHECK-NEXT: Size: 0 +// CHECK-NEXT: Binding: Global +// CHECK-NEXT: Type: None +// CHECK-NEXT: Other: 0 +// CHECK-NEXT: Section: (0x0) +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/x86_64-reloc-sizetest.s b/test/MC/ELF/x86_64-reloc-sizetest.s index acca2f5076a5..bd67ee0f9de8 100644 --- a/test/MC/ELF/x86_64-reloc-sizetest.s +++ b/test/MC/ELF/x86_64-reloc-sizetest.s @@ -1,4 +1,4 @@ -// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | elf-dump | FileCheck %s +// RUN: llvm-mc -triple x86_64-linux-gnu -filetype=obj %s | llvm-readobj -r | FileCheck %s // Tests that relocation value fits in the provided size // Original bug http://llvm.org/bugs/show_bug.cgi?id=10568 @@ -6,8 +6,8 @@ L: movq $(L + 2147483648),%rax -// CHECK: Relocation 0 -// CHECK-NEXT: ('r_offset', 0x0000000000000003) -// CHECK-NEXT: ('r_sym' -// CHECK-NEXT: ('r_type', 0x0000000b) -// CHECK-NEXT: ('r_addend', 0x0000000080000000 +// CHECK: Relocations [ +// CHECK-NEXT: Section ({{[0-9]+}}) .text { +// CHECK-NEXT: 0x3 R_X86_64_32S {{[^ ]+}} 0x80000000 +// CHECK-NEXT: } +// CHECK-NEXT: ] diff --git a/test/MC/ELF/zero.s b/test/MC/ELF/zero.s index 46ffe17cfbf7..be92eb839e1c 100644 --- a/test/MC/ELF/zero.s +++ b/test/MC/ELF/zero.s @@ -1,16 +1,23 @@ -// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | elf-dump --dump-section-data | FileCheck %s +// RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-readobj -s -sd | FileCheck %s .zero 4 .zero 1,42 -// CHECK: ('sh_name', 0x00000001) # '.text' -// CHECK: ('sh_type', 0x00000001) -// CHECK: ('sh_flags', 0x0000000000000006) -// CHECK: ('sh_addr', 0x0000000000000000) -// CHECK: ('sh_offset', 0x0000000000000040) -// CHECK: ('sh_size', 0x0000000000000005) -// CHECK: ('sh_link', 0x00000000) -// CHECK: ('sh_info', 0x00000000) -// CHECK: ('sh_addralign', 0x0000000000000004) -// CHECK: ('sh_entsize', 0x0000000000000000) -// CHECK: ('_section_data', '00000000 2a') +// CHECK: Section { +// CHECK: Name: .text +// CHECK-NEXT: Type: SHT_PROGBITS +// CHECK-NEXT: Flags [ +// CHECK-NEXT: SHF_ALLOC +// CHECK-NEXT: SHF_EXECINSTR +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x40 +// CHECK-NEXT: Size: 5 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 4 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 00000000 2A +// CHECK-NEXT: ) +// CHECK-NEXT: } diff --git a/test/MC/Mips/elf-N64.ll b/test/MC/Mips/elf-N64.ll index ae6de78d6552..a1ea34a80a71 100644 --- a/test/MC/Mips/elf-N64.ll +++ b/test/MC/Mips/elf-N64.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 -disable-mips-delay-filler %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 -disable-mips-delay-filler %s -o - | llvm-readobj -r | FileCheck %s ; Check for N64 relocation production. ; @@ -12,25 +12,12 @@ define i32 @main() nounwind { entry: ; Check that the appropriate relocations were created. -; R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 -; CHECK: ('r_type3', 0x05) -; CHECK-NEXT: ('r_type2', 0x18) -; CHECK-NEXT: ('r_type', 0x07) - -; R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 -; CHECK: ('r_type3', 0x06) -; CHECK-NEXT: ('r_type2', 0x18) -; CHECK-NEXT: ('r_type', 0x07) - -; R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE -; CHECK: ('r_type3', 0x00) -; CHECK-NEXT: ('r_type2', 0x00) -; CHECK-NEXT: ('r_type', 0x14) - -; R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE -; CHECK: ('r_type3', 0x00) -; CHECK-NEXT: ('r_type2', 0x00) -; CHECK-NEXT: ('r_type', 0x15) +; CHECK: Relocations [ +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_PAGE/R_MIPS_NONE/R_MIPS_NONE +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_OFST/R_MIPS_NONE/R_MIPS_NONE +; CHECK: ] %puts = tail call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @str, i64 0, i64 0)) ret i32 0 diff --git a/test/MC/Mips/elf-bigendian.ll b/test/MC/Mips/elf-bigendian.ll index 7111debd11b1..a92fe339f88b 100644 --- a/test/MC/Mips/elf-bigendian.ll +++ b/test/MC/Mips/elf-bigendian.ll @@ -1,24 +1,37 @@ -; DISABLE: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; DISABLE: llc -filetype=obj -mtriple mips-unknown-linux %s -o - | llvm-readobj -h -s -sd | FileCheck %s ; RUN: false ; XFAIL: * ; Check that this is big endian. -; CHECK: ('e_indent[EI_DATA]', 0x02) +; CHECK: ElfHeader { +; CHECK: Ident { +; CHECK: DataEncoding: BigEndian +; CHECK: } +; CHECK: } ; Make sure that a section table (text) entry is correct. -; CHECK: (('sh_name', 0x{{[0]*}}5) # '.text' -; CHECK-NEXT: ('sh_type', 0x{{[0]*}}1) -; CHECK-NEXT: ('sh_flags', 0x{{[0]*}}6) -; CHECK-NEXT: ('sh_addr', 0x{{[0-9,a-f]+}}) -; CHECK-NEXT: ('sh_offset', 0x{{[0-9,a-f]+}}) -; CHECK-NEXT: ('sh_size', 0x{{[0-9,a-f]+}}) -; CHECK-NEXT: ('sh_link', 0x{{[0]+}}) -; CHECK-NEXT: ('sh_info', 0x{{[0]+}}) -; CHECK-NEXT: ('sh_addralign', 0x{{[0]*}}4) -; CHECK-NEXT: ('sh_entsize', 0x{{[0]+}}) +; CHECK: Sections [ +; CHECK: Section { +; CHECK: Index: +; CHECK: Name: .text +; CHECK-NEXT: Type: SHT_PROGBITS +; CHECK-NEXT: Flags [ (0x6) +; CHECK-NEXT: SHF_ALLOC +; CHECK-NEXT: SHF_EXECINSTR +; CHECK-NEXT: ] +; CHECK-NEXT: Address: 0x{{[0-9,A-F]+}} +; CHECK-NEXT: Offset: 0x{{[0-9,A-F]+}} +; CHECK-NEXT: Size: {{[0-9]+}} +; CHECK-NEXT: Link: 0 +; CHECK-NEXT: Info: 0 +; CHECK-NEXT: AddressAlignment: 4 +; CHECK-NEXT: EntrySize: 0 ; See that at least first 3 instructions are correct: GP prologue -; CHECK-NEXT: ('_section_data', '3c1c0000 279c0000 0399e021 {{[0-9,a-f, ]*}}') +; CHECK-NEXT: SectionData ( +; CHECK-NEXT: 0000: 3C1C0000 279C0000 0399E021 {{[0-9,A-F, ]*}} +; CHECK: ) +; CHECK: } ; ModuleID = '../br1.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32" diff --git a/test/MC/Mips/elf-gprel-32-64.ll b/test/MC/Mips/elf-gprel-32-64.ll index b94682214df7..47003fa1e752 100644 --- a/test/MC/Mips/elf-gprel-32-64.ll +++ b/test/MC/Mips/elf-gprel-32-64.ll @@ -1,5 +1,5 @@ ; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 %s -o - \ -; RUN: | elf-dump --dump-section-data \ +; RUN: | llvm-readobj -r \ ; RUN: | FileCheck %s define i32 @test(i32 %c) nounwind { @@ -30,8 +30,11 @@ return: ; Check that the appropriate relocations were created. ; R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE -; CHECK: (('sh_name', 0x{{[a-z0-9]+}}) # '.rela.rodata' -; CHECK: ('r_type3', 0x00) -; CHECK-NEXT: ('r_type2', 0x12) -; CHECK-NEXT: ('r_type', 0x0c) - +; CHECK: Relocations [ +; CHECK: Section ({{[a-z0-9]+}}) .rodata { +; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE +; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE +; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE +; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_MIPS_GPREL32/R_MIPS_64/R_MIPS_NONE +; CHECK-NEXT: } +; CHECK-NEXT: ] diff --git a/test/MC/Mips/elf-reginfo.ll b/test/MC/Mips/elf-reginfo.ll index 1d7a18866c50..a255af931d83 100644 --- a/test/MC/Mips/elf-reginfo.ll +++ b/test/MC/Mips/elf-reginfo.ll @@ -1,7 +1,7 @@ ; RUN: llc -filetype=obj -march=mips64el -mcpu=mips64 %s -o - \ - ; RUN: | elf-dump --dump-section-data | FileCheck --check-prefix=CHECK_64 %s + ; RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_64 %s ; RUN: llc -filetype=obj -march=mipsel -mcpu=mips32 %s -o - \ - ; RUN: | elf-dump --dump-section-data | FileCheck --check-prefix=CHECK_32 %s + ; RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_32 %s ; Check for register information sections. ; @@ -13,14 +13,18 @@ entry: ; Check that the appropriate relocations were created. ; check for .MIPS.options -; CHECK_64: (('sh_name', 0x{{[0-9|a-f]+}}) # '.MIPS.options' -; CHECK_64-NEXT: ('sh_type', 0x7000000d) -; CHECK_64-NEXT: ('sh_flags', 0x0000000008000002) +; CHECK_64: Sections [ +; CHECK_64: Section { +; CHECK_64: Name: .MIPS.options +; CHECK_64-NEXT: Type: SHT_MIPS_OPTIONS +; CHECK_64-NEXT: Flags [ (0x8000002) ; check for .reginfo -; CHECK_32: (('sh_name', 0x{{[0-9|a-f]+}}) # '.reginfo' -; CHECK_32-NEXT: ('sh_type', 0x70000006) -; CHECK_32-NEXT: ('sh_flags', 0x00000002) +; CHECK_32: Sections [ +; CHECK_32: Section { +; CHECK_32: Name: .reginfo +; CHECK_32-NEXT: Type: SHT_MIPS_REGINFO +; CHECK_32-NEXT: Flags [ (0x2) %puts = tail call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @str, i64 0, i64 0)) @@ -28,4 +32,3 @@ entry: } declare i32 @puts(i8* nocapture) nounwind - diff --git a/test/MC/Mips/elf-relsym.ll b/test/MC/Mips/elf-relsym.ll index 0f74437ec5d4..6da926273ab7 100644 --- a/test/MC/Mips/elf-relsym.ll +++ b/test/MC/Mips/elf-relsym.ll @@ -1,11 +1,21 @@ -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | llvm-readobj -t | FileCheck %s ; Check that the appropriate symbols were created. -; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$.str' -; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$.str1' -; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$CPI0_0' -; CHECK: (('st_name', 0x{{[0-9|a-f]+}}) # '$CPI0_1' +; CHECK: Symbols [ +; CHECK: Symbol { +; CHECK: Name: $.str +; CHECK: } +; CHECK: Symbol { +; CHECK: Name: $.str1 +; CHECK: } +; CHECK: Symbol { +; CHECK: Name: $CPI0_0 +; CHECK: } +; CHECK: Symbol { +; CHECK: Name: $CPI0_1 +; CHECK: } +; CHECK: ] @.str = private unnamed_addr constant [6 x i8] c"abcde\00", align 1 @gc1 = external global i8* diff --git a/test/MC/Mips/elf-tls.ll b/test/MC/Mips/elf-tls.ll index b4183b835779..9f604e00a0a8 100644 --- a/test/MC/Mips/elf-tls.ll +++ b/test/MC/Mips/elf-tls.ll @@ -1,10 +1,14 @@ -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | llvm-readobj -r | FileCheck %s ; Check that the appropriate relocations were created. -; CHECK: ('r_type', 0x2b) -; CHECK: ('r_type', 0x2c) -; CHECK: ('r_type', 0x2d) +; CHECK: Relocations [ +; CHECK: Section (1) .text { +; CHECK: R_MIPS_TLS_LDM +; CHECK: R_MIPS_TLS_DTPREL_HI16 +; CHECK: R_MIPS_TLS_DTPREL_LO16 +; CHECK: } +; CHECK: ] @t1 = thread_local global i32 0, align 4 diff --git a/test/MC/Mips/elf_basic.s b/test/MC/Mips/elf_basic.s index ffc3b112e502..6c1e7690126d 100644 --- a/test/MC/Mips/elf_basic.s +++ b/test/MC/Mips/elf_basic.s @@ -1,35 +1,41 @@ // 32 bit big endian -// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32 %s +// RUN: llvm-mc -filetype=obj -triple mips-unknown-linux %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32 %s // 32 bit little endian -// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE32 %s +// RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-LE32 %s // 64 bit big endian -// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64 %s +// RUN: llvm-mc -filetype=obj -arch=mips64 -triple mips64-unknown-linux %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE64 %s // 64 bit little endian -// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE64 %s +// RUN: llvm-mc -filetype=obj -arch=mips64el -triple mips64el-unknown-linux %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-LE64 %s // Check that we produce 32 bit with each endian. -// This is 32 bit. -// CHECK-BE32: ('e_indent[EI_CLASS]', 0x01) -// This is big endian. -// CHECK-BE32: ('e_indent[EI_DATA]', 0x02) +// CHECK-BE32: ElfHeader { +// CHECK-BE32: Ident { +// CHECK-BE32: Class: 32-bit +// CHECK-BE32: DataEncoding: BigEndian +// CHECK-BE32: } +// CHECK-BE32: } -// This is 32 bit. -// CHECK-LE32: ('e_indent[EI_CLASS]', 0x01) -// This is little endian. -// CHECK-LE32: ('e_indent[EI_DATA]', 0x01) +// CHECK-LE32: ElfHeader { +// CHECK-LE32: Ident { +// CHECK-LE32: Class: 32-bit +// CHECK-LE32: DataEncoding: LittleEndian +// CHECK-LE32: } +// CHECK-LE32: } // Check that we produce 64 bit with each endian. -// This is 64 bit. -// CHECK-BE64: ('e_indent[EI_CLASS]', 0x02) -// This is big endian. -// CHECK-BE64: ('e_indent[EI_DATA]', 0x02) +// CHECK-BE64: ElfHeader { +// CHECK-BE64: Ident { +// CHECK-BE64: Class: 64-bit +// CHECK-BE64: DataEncoding: BigEndian +// CHECK-BE64: } +// CHECK-BE64: } -// This is 64 bit. -// CHECK-LE64: ('e_indent[EI_CLASS]', 0x02) -// This is little endian. -// CHECK-LE64: ('e_indent[EI_DATA]', 0x01) - -// Check that we are setting EI_OSABI to ELFOSABI_LINUX. -// CHECK-LE64: ('e_indent[EI_OSABI]', 0x03) +// CHECK-LE64: ElfHeader { +// CHECK-LE64: Ident { +// CHECK-LE64: Class: 64-bit +// CHECK-LE64: DataEncoding: LittleEndian +// CHECK-LE64: OS/ABI: GNU/Linux +// CHECK-LE64: } +// CHECK-LE64: } diff --git a/test/MC/Mips/elf_eflags.ll b/test/MC/Mips/elf_eflags.ll index 315cb812bf77..6d16a42aca2f 100644 --- a/test/MC/Mips/elf_eflags.ll +++ b/test/MC/Mips/elf_eflags.ll @@ -13,52 +13,52 @@ ; EF_MIPS_ARCH_32R2 (0x70000000) ; EF_MIPS_ARCH_64R2 (0x80000000) -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32 %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32_PIC %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -relocation-model=static %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32R2 %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32R2_PIC %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips -relocation-model=static %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32R2-MICROMIPS %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE32R2-MICROMIPS_PIC %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32 %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32_PIC %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32R2 %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32R2_PIC %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32R2-MICROMIPS %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE32R2-MICROMIPS_PIC %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64 %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64 %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64_PIC %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64r2 -relocation-model=static %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64R2 %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64r2 %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-BE64R2_PIC %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE64 %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64 %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE64_PIC %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64r2 -relocation-model=static %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE64R2 %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips64r2 %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-BE64R2_PIC %s -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | elf-dump --dump-section-data | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | llvm-readobj -h | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s ; 32(R1) bit with NO_REORDER and static -; CHECK-BE32: ('e_flags', 0x50001001) +; CHECK-BE32: Flags [ (0x50001001) ; ; 32(R1) bit with NO_REORDER and PIC -; CHECK-BE32_PIC: ('e_flags', 0x50001003) +; CHECK-BE32_PIC: Flags [ (0x50001003) ; ; 32R2 bit with NO_REORDER and static -; CHECK-BE32R2: ('e_flags', 0x70001001) +; CHECK-BE32R2: Flags [ (0x70001001) ; ; 32R2 bit with NO_REORDER and PIC -; CHECK-BE32R2_PIC: ('e_flags', 0x70001003) +; CHECK-BE32R2_PIC: Flags [ (0x70001003) ; ; 32R2 bit MICROMIPS with NO_REORDER and static -; CHECK-BE32R2-MICROMIPS: ('e_flags', 0x72001001) +; CHECK-BE32R2-MICROMIPS: Flags [ (0x72001001) ; ; 32R2 bit MICROMIPS with NO_REORDER and PIC -;CHECK-BE32R2-MICROMIPS_PIC: ('e_flags', 0x72001003) +;CHECK-BE32R2-MICROMIPS_PIC: Flags [ (0x72001003) ; ; 64(R1) bit with NO_REORDER and static -; CHECK-BE64: ('e_flags', 0x60000001) +; CHECK-BE64: Flags [ (0x60000001) ; ; 64(R1) bit with NO_REORDER and PIC -; CHECK-BE64_PIC: ('e_flags', 0x60000003) +; CHECK-BE64_PIC: Flags [ (0x60000003) ; ; 64R2 bit with NO_REORDER and static -; CHECK-BE64R2: ('e_flags', 0x80000001) +; CHECK-BE64R2: Flags [ (0x80000001) ; ; 64R2 bit with NO_REORDER and PIC -; CHECK-BE64R2_PIC: ('e_flags', 0x80000003) +; CHECK-BE64R2_PIC: Flags [ (0x80000003) ; ; 32R2 bit MIPS16 with PIC -; CHECK-LE32R2-MIPS16: ('e_flags', 0x74001002) +; CHECK-LE32R2-MIPS16: Flags [ (0x74001002) define i32 @main() nounwind { entry: diff --git a/test/MC/Mips/elf_st_other.ll b/test/MC/Mips/elf_st_other.ll index f188ce7ba387..bc56c0033e58 100644 --- a/test/MC/Mips/elf_st_other.ll +++ b/test/MC/Mips/elf_st_other.ll @@ -1,13 +1,12 @@ ; This tests value of ELF st_other field for function symbol table entries. ; For microMIPS value should be equal to STO_MIPS_MICROMIPS. -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | llvm-readobj -t | FileCheck %s define i32 @main() nounwind { entry: ret i32 0 } -; CHECK: 'main' -; CHECK: ('st_other', 0x80) - +; CHECK: Name: main +; CHECK: Other: 128 diff --git a/test/MC/Mips/expr1.s b/test/MC/Mips/expr1.s new file mode 100644 index 000000000000..67664c1a2ae4 --- /dev/null +++ b/test/MC/Mips/expr1.s @@ -0,0 +1,26 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s +# Check that the assembler can handle the expressions as operands. +# CHECK: .text +# CHECK: .globl foo +# CHECK: foo: +# CHECK: lw $4, %lo(foo)($4) # encoding: [A,A,0x84,0x8c] +# CHECK: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: lw $4, 56($4) # encoding: [0x38,0x00,0x84,0x8c] +# CHECK: lw $4, %lo(foo+8)($4) # encoding: [0x08'A',A,0x84,0x8c] +# CHECK: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: lw $4, %lo(foo+8)($4) # encoding: [0x08'A',A,0x84,0x8c] +# CHECK: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: lw $4, %lo(foo+8)($4) # encoding: [0x08'A',A,0x84,0x8c] +# CHECK: # fixup A - offset: 0, value: foo@ABS_LO, kind: fixup_Mips_LO16 +# CHECK: .space 64 + + .globl foo + .ent foo +foo: + lw $4,%lo(foo)($4) + lw $4,((10 + 4) * 4)($4) + lw $4,%lo (2 * 4) + foo($4) + lw $4,%lo((2 * 4) + foo)($4) + lw $4,(((%lo ((2 * 4) + foo))))($4) + .space 64 + .end foo diff --git a/test/MC/Mips/higher_highest.ll b/test/MC/Mips/higher_highest.ll index 0c665220335b..6c3d71f6a4b1 100644 --- a/test/MC/Mips/higher_highest.ll +++ b/test/MC/Mips/higher_highest.ll @@ -1,14 +1,16 @@ -; DISABLE: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | elf-dump --dump-section-data | FileCheck %s +; DISABLE: llc -march=mips64el -mcpu=mips64 -mattr=n64 -force-mips-long-branch -filetype=obj < %s -o - | llvm-readobj -r | FileCheck %s ; RUN: false ; XFAIL: * ; Disabled because currently we don't have a way to generate these relocations. ; ; Check that the R_MIPS_HIGHER and R_MIPS_HIGHEST relocations were created. -; CHECK: ('r_type', 0x1d) -; CHECK: ('r_type', 0x1d) -; CHECK: ('r_type', 0x1c) -; CHECK: ('r_type', 0x1c) +; CHECK: Relocations [ +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_HIGHEST +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_HIGHEST +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_HIGHER +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_HIGHER +; CHECK: ] @g0 = external global i32 diff --git a/test/MC/Mips/micromips-alu-instructions.s b/test/MC/Mips/micromips-alu-instructions.s new file mode 100644 index 000000000000..c541e1ace554 --- /dev/null +++ b/test/MC/Mips/micromips-alu-instructions.s @@ -0,0 +1,64 @@ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips | FileCheck %s +# Check that the assembler can handle the documented syntax +# for arithmetic and logical instructions. +#------------------------------------------------------------------------------ +# Arithmetic and Logical Instructions +#------------------------------------------------------------------------------ +# CHECK: add $9, $6, $7 # encoding: [0x10,0x49,0xe6,0x00] +# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0x26,0x11] +# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0x26,0x31] +# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0x26,0x11] +# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0x26,0x31] +# CHECK: addu $9, $6, $7 # encoding: [0x50,0x49,0xe6,0x00] +# CHECK: sub $9, $6, $7 # encoding: [0x90,0x49,0xe6,0x00] +# CHECK: subu $4, $3, $5 # encoding: [0xd0,0x21,0xa3,0x00] +# CHECK: neg $6, $7 # encoding: [0x90,0x31,0xe0,0x00] +# CHECK: negu $6, $7 # encoding: [0xd0,0x31,0xe0,0x00] +# CHECK: move $7, $8 # encoding: [0x50,0x39,0x08,0x00] +# CHECK: slt $3, $3, $5 # encoding: [0x50,0x1b,0xa3,0x00] +# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x90] +# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x90] +# CHECK: sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0xb0] +# CHECK: sltu $3, $3, $5 # encoding: [0x90,0x1b,0xa3,0x00] +# CHECK: and $9, $6, $7 # encoding: [0x50,0x4a,0xe6,0x00] +# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0x26,0xd1] +# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0x26,0xd1] +# CHECK: or $3, $4, $5 # encoding: [0x90,0x1a,0xa4,0x00] +# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0x26,0x51] +# CHECK: xor $3, $3, $5 # encoding: [0x10,0x1b,0xa3,0x00] +# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0x26,0x71] +# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0x26,0x71] +# CHECK: nor $9, $6, $7 # encoding: [0xd0,0x4a,0xe6,0x00] +# CHECK: not $7, $8 # encoding: [0xd0,0x3a,0x08,0x00] +# CHECK: mul $9, $6, $7 # encoding: [0x10,0x4a,0xe6,0x00] +# CHECK: mult $9, $7 # encoding: [0x3c,0x8b,0xe9,0x00] +# CHECK: multu $9, $7 # encoding: [0x3c,0x9b,0xe9,0x00] + add $9, $6, $7 + add $9, $6, 17767 + addu $9, $6, -15001 + addi $9, $6, 17767 + addiu $9, $6,-15001 + addu $9, $6, $7 + sub $9, $6, $7 + subu $4, $3, $5 + neg $6, $7 + negu $6, $7 + move $7, $8 + slt $3, $3, $5 + slt $3, $3, 103 + slti $3, $3, 103 + sltiu $3, $3, 103 + sltu $3, $3, $5 + and $9, $6, $7 + and $9, $6, 17767 + andi $9, $6, 17767 + or $3, $4, $5 + ori $9, $6, 17767 + xor $3, $3, $5 + xor $9, $6, 17767 + xori $9, $6, 17767 + nor $9, $6, $7 + nor $7, $8, $zero + mul $9, $6, $7 + mult $9, $7 + multu $9, $7 diff --git a/test/MC/Mips/micromips-loadstore-instructions.s b/test/MC/Mips/micromips-loadstore-instructions.s new file mode 100644 index 000000000000..623e2acdcbf6 --- /dev/null +++ b/test/MC/Mips/micromips-loadstore-instructions.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mattr=micromips | FileCheck %s +# Check that the assembler can handle the documented syntax +# for load and store instructions. +#------------------------------------------------------------------------------ +# Load and Store Instructions +#------------------------------------------------------------------------------ +# CHECK: lb $5, 8($4) # encoding: [0x08,0x00,0xa4,0x1c] +# CHECK: lbu $6, 8($4) # encoding: [0x08,0x00,0xc4,0x14] +# CHECK: lh $2, 8($4) # encoding: [0x08,0x00,0x44,0x3c] +# CHECK: lhu $4, 8($2) # encoding: [0x08,0x00,0x82,0x34] +# CHECK: lw $6, 4($5) # encoding: [0x04,0x00,0xc5,0xfc] +# CHECK: sb $5, 8($4) # encoding: [0x08,0x00,0xa4,0x18] +# CHECK: sh $2, 8($4) # encoding: [0x08,0x00,0x44,0x38] +# CHECK: sw $5, 4($6) # encoding: [0x04,0x00,0xa6,0xf8] + lb $5, 8($4) + lbu $6, 8($4) + lh $2, 8($4) + lhu $4, 8($2) + lw $6, 4($5) + sb $5, 8($4) + sh $2, 8($4) + sw $5, 4($6) diff --git a/test/MC/Mips/micromips-shift-instructions.s b/test/MC/Mips/micromips-shift-instructions.s new file mode 100644 index 000000000000..3b5060f5280e --- /dev/null +++ b/test/MC/Mips/micromips-shift-instructions.s @@ -0,0 +1,22 @@ +# RUN: llvm-mc %s -triple=mipsel -show-encoding -mcpu=mips32r2 -mattr=micromips | FileCheck %s +# Check that the assembler can handle the documented syntax +# for shift instructions. +#------------------------------------------------------------------------------ +# Shift Instructions +#------------------------------------------------------------------------------ +# CHECK: sll $4, $3, 7 # encoding: [0x00,0x38,0x83,0x00] +# CHECK: sllv $2, $3, $5 # encoding: [0x10,0x10,0x65,0x00] +# CHECK: sra $4, $3, 7 # encoding: [0x80,0x38,0x83,0x00] +# CHECK: srav $2, $3, $5 # encoding: [0x90,0x10,0x65,0x00] +# CHECK: srl $4, $3, 7 # encoding: [0x40,0x38,0x83,0x00] +# CHECK: srlv $2, $3, $5 # encoding: [0x50,0x10,0x65,0x00] +# CHECK: rotr $9, $6, 7 # encoding: [0xc0,0x38,0x26,0x01] +# CHECK: rotrv $9, $6, $7 # encoding: [0xd0,0x48,0xc7,0x00] + sll $4, $3, 7 + sllv $2, $3, $5 + sra $4, $3, 7 + srav $2, $3, $5 + srl $4, $3, 7 + srlv $2, $3, $5 + rotr $9, $6, 7 + rotrv $9, $6, $7 diff --git a/test/MC/Mips/mips-alu-instructions.s b/test/MC/Mips/mips-alu-instructions.s index 7384d19e440f..586e88bc4814 100644 --- a/test/MC/Mips/mips-alu-instructions.s +++ b/test/MC/Mips/mips-alu-instructions.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for arithmetic and logical instructions. -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # Logical instructions #------------------------------------------------------------------------------ diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s index 3385fe19309f..1622965a4139 100644 --- a/test/MC/Mips/mips-expansions.s +++ b/test/MC/Mips/mips-expansions.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for macro instructions -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # Load immediate instructions #------------------------------------------------------------------------------ diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index a126c6f7188c..e515872f260a 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for FPU instructions. -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # FP aritmetic instructions #------------------------------------------------------------------------------ @@ -157,6 +156,8 @@ # CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] # CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] # CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] +# CHECK: movf $2, $1, $fcc0 # encoding: [0x01,0x10,0x20,0x00] +# CHECK: movt $2, $1, $fcc0 # encoding: [0x01,0x10,0x21,0x00] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -176,3 +177,5 @@ mtc0 $9, $8, 3 mfc2 $5, $7, 4 mtc2 $9, $4, 5 + movf $2, $1, $fcc0 + movt $2, $1, $fcc0 diff --git a/test/MC/Mips/mips-jump-instructions.s b/test/MC/Mips/mips-jump-instructions.s index 1dcb287738ce..597f6872d60f 100644 --- a/test/MC/Mips/mips-jump-instructions.s +++ b/test/MC/Mips/mips-jump-instructions.s @@ -1,31 +1,54 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \ -# RUN: FileCheck %s +# RUN: FileCheck -check-prefix=CHECK32 %s +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | \ +# RUN: FileCheck -check-prefix=CHECK64 %s + # Check that the assembler can handle the documented syntax # for jumps and branches. -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # Branch instructions #------------------------------------------------------------------------------ -# CHECK: b 1332 # encoding: [0x4d,0x01,0x00,0x10] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: b 1332 # encoding: [0x4d,0x01,0x00,0x10] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] + +# CHECK64: b 1332 # encoding: [0x4d,0x01,0x00,0x10] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: bal 1332 # encoding: [0x4d,0x01,0x11,0x04] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] .set noreorder @@ -54,24 +77,43 @@ end_of_code: #------------------------------------------------------------------------------ # Jump instructions #------------------------------------------------------------------------------ -# CHECK: j 1328 # encoding: [0x4c,0x01,0x00,0x08] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jr $7 # encoding: [0x08,0x00,0xe0,0x00] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03] -# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: j 1328 # encoding: [0x4c,0x01,0x00,0x08] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK32: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03] +# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00] + +# CHECK64: j 1328 # encoding: [0x4c,0x01,0x00,0x08] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK64: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03] +# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00] j 1328 diff --git a/test/MC/Mips/mips-memory-instructions.s b/test/MC/Mips/mips-memory-instructions.s index b5f1267ef386..c8b055906ebb 100644 --- a/test/MC/Mips/mips-memory-instructions.s +++ b/test/MC/Mips/mips-memory-instructions.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for loads and stores. -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # Memory store instructions #------------------------------------------------------------------------------ diff --git a/test/MC/Mips/mips-relocations.s b/test/MC/Mips/mips-relocations.s index ff71c7559cd0..6f095d1ecdff 100644 --- a/test/MC/Mips/mips-relocations.s +++ b/test/MC/Mips/mips-relocations.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for relocations. -# CHECK: .section __TEXT,__text,regular,pure_instructions # CHECK: lui $2, %hi(_gp_disp) # encoding: [A,A,0x02,0x3c] # CHECK: # fixup A - offset: 0, value: _gp_disp@ABS_HI, kind: fixup_Mips_HI16 # CHECK: addiu $2, $2, %lo(_gp_disp) # encoding: [A,A,0x42,0x24] diff --git a/test/MC/Mips/mips64-alu-instructions.s b/test/MC/Mips/mips64-alu-instructions.s index 1b4ebdfbbd49..db6c972b3b49 100644 --- a/test/MC/Mips/mips64-alu-instructions.s +++ b/test/MC/Mips/mips64-alu-instructions.s @@ -1,7 +1,6 @@ # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s # Check that the assembler can handle the documented syntax # for arithmetic and logical instructions. -# CHECK: .section __TEXT,__text,regular,pure_instructions #------------------------------------------------------------------------------ # Logical instructions #------------------------------------------------------------------------------ @@ -13,6 +12,7 @@ # CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d] # CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00] # CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00] +# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34] # CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34] # CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00] # CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00] @@ -40,6 +40,7 @@ ins $19, $9, 6,7 nor $9, $6, $7 or $3, $3, $5 + or $4, $5, 17767 ori $9, $6, 17767 rotr $9, $6, 7 rotrv $9, $6, $7 diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index df7e64563371..45247cd162b5 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -1,11 +1,20 @@ # RUN: llvm-mc -show-encoding -triple mips-unknown-unknown %s | FileCheck %s # +# CHECK: .text +# CHECK: $BB0_2: $BB0_2: .ent directives_test .frame $sp,0,$ra .mask 0x00000000,0 .fmask 0x00000000,0 +# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d] +# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] +# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] + .set noreorder + b 1332 + j 1328 + jal 1328 .set nomacro .set noat $JTI0_0: @@ -15,7 +24,16 @@ $JTI0_0: # CHECK-NEXT: .4byte 2013265916 .set at=$12 .set macro +# CHECK: b 1332 # encoding: [0x10,0x00,0x01,0x4d] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK: jal 1328 # encoding: [0x0c,0x00,0x01,0x4c] +# CHECK: nop # encoding: [0x00,0x00,0x00,0x00] .set reorder + b 1332 + j 1328 + jal 1328 .set at=$a0 .set STORE_MASK,$t7 .set FPU_MASK,$f7 diff --git a/test/MC/Mips/nabi-regs.s b/test/MC/Mips/nabi-regs.s index 9371208a2a9e..050fb8134880 100644 --- a/test/MC/Mips/nabi-regs.s +++ b/test/MC/Mips/nabi-regs.s @@ -8,7 +8,6 @@ # RUN: -mcpu=mips64r2 -arch=mips64 | \ # RUN: FileCheck %s -# CHECK: .section __TEXT,__text,regular,pure_instructions .text foo: diff --git a/test/MC/Mips/r-mips-got-disp.ll b/test/MC/Mips/r-mips-got-disp.ll index 73396ac5139d..7e78a46649d8 100644 --- a/test/MC/Mips/r-mips-got-disp.ll +++ b/test/MC/Mips/r-mips-got-disp.ll @@ -1,8 +1,9 @@ -; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 < %s -o - | llvm-readobj -r | FileCheck %s ; Check that the R_MIPS_GOT_DISP relocations were created. -; CHECK: ('r_type', 0x13) +; CHECK: Relocations [ +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_DISP @shl = global i64 1, align 8 @.str = private unnamed_addr constant [8 x i8] c"0x%llx\0A\00", align 1 diff --git a/test/MC/Mips/set-at-directive.s b/test/MC/Mips/set-at-directive.s index 98a3a35b5428..828175a223a7 100644 --- a/test/MC/Mips/set-at-directive.s +++ b/test/MC/Mips/set-at-directive.s @@ -3,7 +3,6 @@ # Check that the assembler can handle the documented syntax # for ".set at" and set the correct value. -# CHECK: .section __TEXT,__text,regular,pure_instructions .text foo: # CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] diff --git a/test/MC/Mips/sym-offset.ll b/test/MC/Mips/sym-offset.ll index 5162c913ad06..c7450f74ae41 100644 --- a/test/MC/Mips/sym-offset.ll +++ b/test/MC/Mips/sym-offset.ll @@ -1,4 +1,4 @@ -; DISABLED: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | elf-dump --dump-section-data | FileCheck %s +; DISABLED: llc -filetype=obj -mtriple mipsel-unknown-linux %s -o - | llvm-readobj -s -sd | FileCheck %s ; RUN: false ; XFAIL: * @@ -13,7 +13,9 @@ entry: ; 8841000e lwl at,14(v0) ; 9841000b lwr at,11(v0) -; CHECK: ('_section_data', '00001c3c 00009c27 21e09903 0000828f 0e004188 0b004198 +; CHECK: SectionData ( +; CHECK: 0000: 00001C3C 00009C27 21E09903 0000828F +; CHECK-NEXT: 0010: 0E004188 0B004198 %call = tail call i32 @memcmp(i8* getelementptr inbounds ([11 x i8]* @string1, i32 0, i32 0), i8* getelementptr inbounds ([10 x i8]* @string2, i32 0, i32 0), i32 4) nounwind readonly %cmp = icmp eq i32 %call, 0 diff --git a/test/MC/Mips/xgot.ll b/test/MC/Mips/xgot.ll index bfe9b9ad6604..e2a500ffdeea 100644 --- a/test/MC/Mips/xgot.ll +++ b/test/MC/Mips/xgot.ll @@ -1,4 +1,4 @@ -; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mxgot %s -o - | elf-dump --dump-section-data | FileCheck %s +; RUN: llc -filetype=obj -mtriple mipsel-unknown-linux -mxgot %s -o - | llvm-readobj -r | FileCheck %s @.str = private unnamed_addr constant [16 x i8] c"ext_1=%d, i=%d\0A\00", align 1 @ext_1 = external global i32 @@ -9,29 +9,16 @@ entry: ; Check that the appropriate relocations were created. ; For the xgot case we want to see R_MIPS_[GOT|CALL]_[HI|LO]16. -; R_MIPS_HI16 -; CHECK: ('r_type', 0x05) - -; R_MIPS_LO16 -; CHECK: ('r_type', 0x06) - -; R_MIPS_GOT_HI16 -; CHECK: ('r_type', 0x16) - -; R_MIPS_GOT_LO16 -; CHECK: ('r_type', 0x17) - -; R_MIPS_GOT -; CHECK: ('r_type', 0x09) - -; R_MIPS_LO16 -; CHECK: ('r_type', 0x06) - -; R_MIPS_CALL_HI16 -; CHECK: ('r_type', 0x1e) - -; R_MIPS_CALL_LO16 -; CHECK: ('r_type', 0x1f) +; CHECK: Relocations [ +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_HI16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_HI16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT_LO16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_GOT +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_LO16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_HI16 +; CHECK: 0x{{[0-9,A-F]+}} R_MIPS_CALL_LO16 +; CHECK: ] %0 = load i32* @ext_1, align 4 %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([16 x i8]* @.str, i32 0, i32 0), i32 %0) nounwind diff --git a/test/MC/PowerPC/ppc64-encoding-bookII.s b/test/MC/PowerPC/ppc64-encoding-bookII.s new file mode 100644 index 000000000000..e74c971323fb --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding-bookII.s @@ -0,0 +1,58 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# Cache management instruction + +# FIXME: icbi 2, 3 +# FIXME: icbt 1, 2, 3 + +# FIXME: dcbt 2, 3, 10 +# FIXME: dcbtst 2, 3, 10 +# CHECK: dcbz 2, 3 # encoding: [0x7c,0x02,0x1f,0xec] + dcbz 2, 3 +# CHECK: dcbst 2, 3 # encoding: [0x7c,0x02,0x18,0x6c] + dcbst 2, 3 +# FIXME: dcbf 2, 3, 1 + +# Synchronization instructions + +# FIXME: isync + +# FIXME: lbarx 2, 3, 4, 1 +# FIXME: lharx 2, 3, 4, 1 +# FIXME: lwarx 2, 3, 4, 1 +# FIXME: ldarx 2, 3, 4, 1 + +# FIXME: stbcx. 2, 3, 4 +# FIXME: sthcx. 2, 3, 4 +# CHECK: stwcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2d] + stwcx. 2, 3, 4 +# CHECK: stdcx. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xad] + stdcx. 2, 3, 4 + +# FIXME: sync 2 +# FIXME: eieio +# FIXME: wait 2 + +# Extended mnemonics + +# CHECK: dcbf 2, 3 # encoding: [0x7c,0x02,0x18,0xac] + dcbf 2, 3 +# FIXME: dcbfl 2, 3 + +# FIXME: lbarx 2, 3, 4 +# FIXME: lharx 2, 3, 4 +# CHECK: lwarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x28] + lwarx 2, 3, 4 +# CHECK: ldarx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xa8] + ldarx 2, 3, 4 + +# CHECK: sync # encoding: [0x7c,0x00,0x04,0xac] + sync +# FIXME: lwsync +# FIXME: ptesync + +# FIXME: wait +# FIXME: waitrsv +# FIXME: waitimpl + diff --git a/test/MC/PowerPC/ppc64-encoding-ext.s b/test/MC/PowerPC/ppc64-encoding-ext.s new file mode 100644 index 000000000000..4395b1980aba --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding-ext.s @@ -0,0 +1,331 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# FIXME: Condition register bit symbols + +# Branch mnemonics + +# CHECK: blr # encoding: [0x4e,0x80,0x00,0x20] + blr +# CHECK: bctr # encoding: [0x4e,0x80,0x04,0x20] + bctr +# FIXME: blrl +# CHECK: bctrl # encoding: [0x4e,0x80,0x04,0x21] + bctrl + +# FIXME: bt 2, target +# FIXME: bta 2, target +# FIXME: btlr 2 +# FIXME: btctr 2 +# FIXME: btl 2, target +# FIXME: btla 2, target +# FIXME: btlrl 2 +# FIXME: btctrl 2 + +# FIXME: bf 2, target +# FIXME: bfa 2, target +# FIXME: bflr 2 +# FIXME: bfctr 2 +# FIXME: bfl 2, target +# FIXME: bfla 2, target +# FIXME: bflrl 2 +# FIXME: bfctrl 2 + +# CHECK: bdnz target # encoding: [0x42,0x00,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdnz target +# FIXME: bdnza target +# CHECK: bdnzlr # encoding: [0x4e,0x00,0x00,0x20] + bdnzlr +# FIXME: bdnzl target +# FIXME: bdnzla target +# FIXME: bdnzlrl + +# FIXME: bdnzt 2, target +# FIXME: bdnzta 2, target +# FIXME: bdnztlr 2 +# FIXME: bdnztl 2, target +# FIXME: bdnztla 2, target +# FIXME: bdnztlrl 2 +# FIXME: bdnzf 2, target +# FIXME: bdnzfa 2, target +# FIXME: bdnzflr 2 +# FIXME: bdnzfl 2, target +# FIXME: bdnzfla 2, target +# FIXME: bdnzflrl 2 + +# CHECK: bdz target # encoding: [0x42,0x40,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bdz target +# FIXME: bdza target +# CHECK: bdzlr # encoding: [0x4e,0x40,0x00,0x20] + bdzlr +# FIXME: bdzl target +# FIXME: bdzla target + +# FIXME: bdzlrl +# FIXME: bdzt 2, target +# FIXME: bdzta 2, target +# FIXME: bdztlr 2 +# FIXME: bdztl 2, target +# FIXME: bdztla 2, target +# FIXME: bdztlrl 2 +# FIXME: bdzf 2, target +# FIXME: bdzfa 2, target +# FIXME: bdzflr 2 +# FIXME: bdzfl 2, target +# FIXME: bdzfla 2, target +# FIXME: bdzflrl 2 + +# CHECK: blt 2, target # encoding: [0x41,0x88,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + blt 2, target +# FIXME: blta 2, target +# CHECK: bltlr 2 # encoding: [0x4d,0x88,0x00,0x20] + bltlr 2 +# CHECK: bltctr 2 # encoding: [0x4d,0x88,0x04,0x20] + bltctr 2 +# FIXME: bltl 2, target +# FIXME: bltla 2, target +# FIXME: bltlrl 2 +# CHECK: bltctrl 2 # encoding: [0x4d,0x88,0x04,0x21] + bltctrl 2 + +# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + ble 2, target +# FIXME: blea 2, target +# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] + blelr 2 +# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] + blectr 2 +# FIXME: blel 2, target +# FIXME: blela 2, target +# FIXME: blelrl 2 +# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] + blectrl 2 + +# CHECK: beq 2, target # encoding: [0x41,0x8a,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + beq 2, target +# FIXME: beqa 2, target +# CHECK: beqlr 2 # encoding: [0x4d,0x8a,0x00,0x20] + beqlr 2 +# CHECK: beqctr 2 # encoding: [0x4d,0x8a,0x04,0x20] + beqctr 2 +# FIXME: beql 2, target +# FIXME: beqla 2, target +# FIXME: beqlrl 2 +# CHECK: beqctrl 2 # encoding: [0x4d,0x8a,0x04,0x21] + beqctrl 2 + +# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bge 2, target +# FIXME: bgea 2, target +# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] + bgelr 2 +# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] + bgectr 2 +# FIXME: bgel 2, target +# FIXME: bgela 2, target +# FIXME: bgelrl 2 +# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] + bgectrl 2 + +# CHECK: bgt 2, target # encoding: [0x41,0x89,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bgt 2, target +# FIXME: bgta 2, target +# CHECK: bgtlr 2 # encoding: [0x4d,0x89,0x00,0x20] + bgtlr 2 +# CHECK: bgtctr 2 # encoding: [0x4d,0x89,0x04,0x20] + bgtctr 2 +# FIXME: bgtl 2, target +# FIXME: bgtla 2, target +# FIXME: bgtlrl 2 +# CHECK: bgtctrl 2 # encoding: [0x4d,0x89,0x04,0x21] + bgtctrl 2 + +# CHECK: bge 2, target # encoding: [0x40,0x88,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnl 2, target +# FIXME: bnla 2, target +# CHECK: bgelr 2 # encoding: [0x4c,0x88,0x00,0x20] + bnllr 2 +# CHECK: bgectr 2 # encoding: [0x4c,0x88,0x04,0x20] + bnlctr 2 +# FIXME: bnll 2, target +# FIXME: bnlla 2, target +# FIXME: bnllrl 2 +# CHECK: bgectrl 2 # encoding: [0x4c,0x88,0x04,0x21] + bnlctrl 2 + +# CHECK: bne 2, target # encoding: [0x40,0x8a,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bne 2, target +# FIXME: bnea 2, target +# CHECK: bnelr 2 # encoding: [0x4c,0x8a,0x00,0x20] + bnelr 2 +# CHECK: bnectr 2 # encoding: [0x4c,0x8a,0x04,0x20] + bnectr 2 +# FIXME: bnel 2, target +# FIXME: bnela 2, target +# FIXME: bnelrl 2 +# CHECK: bnectrl 2 # encoding: [0x4c,0x8a,0x04,0x21] + bnectrl 2 + +# CHECK: ble 2, target # encoding: [0x40,0x89,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bng 2, target +# FIXME: bnga 2, target +# CHECK: blelr 2 # encoding: [0x4c,0x89,0x00,0x20] + bnglr 2 +# CHECK: blectr 2 # encoding: [0x4c,0x89,0x04,0x20] + bngctr 2 +# FIXME: bngl 2, target +# FIXME: bngla 2, target +# FIXME: bnglrl 2 +# CHECK: blectrl 2 # encoding: [0x4c,0x89,0x04,0x21] + bngctrl 2 + +# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bso 2, target +# FIXME: bsoa 2, target +# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] + bsolr 2 +# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] + bsoctr 2 +# FIXME: bsol 2, target +# FIXME: bsola 2, target +# FIXME: bsolrl 2 +# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] + bsoctrl 2 + +# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bns 2, target +# FIXME: bnsa 2, target +# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] + bnslr 2 +# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] + bnsctr 2 +# FIXME: bnsl 2, target +# FIXME: bnsla 2, target +# FIXME: bnslrl 2 +# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] + bnsctrl 2 + +# CHECK: bun 2, target # encoding: [0x41,0x8b,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bun 2, target +# FIXME: buna 2, target +# CHECK: bunlr 2 # encoding: [0x4d,0x8b,0x00,0x20] + bunlr 2 +# CHECK: bunctr 2 # encoding: [0x4d,0x8b,0x04,0x20] + bunctr 2 +# FIXME: bunl 2, target +# FIXME: bunla 2, target +# FIXME: bunlrl 2 +# CHECK: bunctrl 2 # encoding: [0x4d,0x8b,0x04,0x21] + bunctrl 2 + +# CHECK: bnu 2, target # encoding: [0x40,0x8b,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_brcond14 + bnu 2, target +# FIXME: bnua 2, target +# CHECK: bnulr 2 # encoding: [0x4c,0x8b,0x00,0x20] + bnulr 2 +# CHECK: bnuctr 2 # encoding: [0x4c,0x8b,0x04,0x20] + bnuctr 2 +# FIXME: bnul 2, target +# FIXME: bnula 2, target +# FIXME: bnulrl 2 +# CHECK: bnuctrl 2 # encoding: [0x4c,0x8b,0x04,0x21] + bnuctrl 2 + +# FIXME: Condition register logical mnemonics + +# FIXME: Subtract mnemonics + +# Compare mnemonics + +# CHECK: cmpdi 2, 3, 128 # encoding: [0x2d,0x23,0x00,0x80] + cmpdi 2, 3, 128 +# CHECK: cmpd 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x00] + cmpd 2, 3, 4 +# CHECK: cmpldi 2, 3, 128 # encoding: [0x29,0x23,0x00,0x80] + cmpldi 2, 3, 128 +# CHECK: cmpld 2, 3, 4 # encoding: [0x7d,0x23,0x20,0x40] + cmpld 2, 3, 4 + +# CHECK: cmpwi 2, 3, 128 # encoding: [0x2d,0x03,0x00,0x80] + cmpwi 2, 3, 128 +# CHECK: cmpw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x00] + cmpw 2, 3, 4 +# CHECK: cmplwi 2, 3, 128 # encoding: [0x29,0x03,0x00,0x80] + cmplwi 2, 3, 128 +# CHECK: cmplw 2, 3, 4 # encoding: [0x7d,0x03,0x20,0x40] + cmplw 2, 3, 4 + +# FIXME: Trap mnemonics + +# Rotate and shift mnemonics + +# FIXME: extldi 2, 3, 4, 5 +# FIXME: extrdi 2, 3, 4, 5 +# FIXME: insrdi 2, 3, 4, 5 +# FIXME: rotldi 2, 3, 4 +# FIXME: rotrdi 2, 3, 4 +# FIXME: rotld 2, 3, 4 +# CHECK: sldi 2, 3, 4 # encoding: [0x78,0x62,0x26,0xe4] + sldi 2, 3, 4 +# CHECK: rldicl 2, 3, 60, 4 # encoding: [0x78,0x62,0xe1,0x02] + srdi 2, 3, 4 +# FIXME: clrldi 2, 3, 4 +# FIXME: clrrdi 2, 3, 4 +# FIXME: clrlsldi 2, 3, 4, 5 + +# FIXME: extlwi 2, 3, 4, 5 +# FIXME: extrwi 2, 3, 4, 5 +# FIXME: inslwi 2, 3, 4, 5 +# FIXME: insrwi 2, 3, 4, 5 +# FIXME: rotlwi 2, 3, 4 +# FIXME: rotrwi 2, 3, 4 +# FIXME: rotlw 2, 3, 4 +# CHECK: slwi 2, 3, 4 # encoding: [0x54,0x62,0x20,0x36] + slwi 2, 3, 4 +# CHECK: srwi 2, 3, 4 # encoding: [0x54,0x62,0xe1,0x3e] + srwi 2, 3, 4 +# FIXME: clrlwi 2, 3, 4 +# FIXME: clrrwi 2, 3, 4 +# FIXME: clrlslwi 2, 3, 4, 5 + +# Move to/from special purpose register mnemonics + +# FIXME: mtxer 2 +# FIXME: mfxer 2 +# CHECK: mtlr 2 # encoding: [0x7c,0x48,0x03,0xa6] + mtlr 2 +# CHECK: mflr 2 # encoding: [0x7c,0x48,0x02,0xa6] + mflr 2 +# CHECK: mtctr 2 # encoding: [0x7c,0x49,0x03,0xa6] + mtctr 2 +# CHECK: mfctr 2 # encoding: [0x7c,0x49,0x02,0xa6] + mfctr 2 + +# Miscellaneous mnemonics + +# CHECK: nop # encoding: [0x60,0x00,0x00,0x00] + nop +# FIXME: xnop +# CHECK: li 2, 128 # encoding: [0x38,0x40,0x00,0x80] + li 2, 128 +# CHECK: lis 2, 128 # encoding: [0x3c,0x40,0x00,0x80] + lis 2, 128 +# FIXME: la 2, 128(4) +# CHECK: mr 2, 3 # encoding: [0x7c,0x62,0x1b,0x78] + mr 2, 3 +# FIXME: not 2, 3 + diff --git a/test/MC/PowerPC/ppc64-encoding-fp.s b/test/MC/PowerPC/ppc64-encoding-fp.s new file mode 100644 index 000000000000..ae0e2866a261 --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding-fp.s @@ -0,0 +1,263 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# Floating-point facility + +# Floating-point load instructions + +# CHECK: lfs 2, 128(4) # encoding: [0xc0,0x44,0x00,0x80] + lfs 2, 128(4) +# CHECK: lfsx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2e] + lfsx 2, 3, 4 +# CHECK: lfsu 2, 128(4) # encoding: [0xc4,0x44,0x00,0x80] + lfsu 2, 128(4) +# CHECK: lfsux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x6e] + lfsux 2, 3, 4 +# CHECK: lfd 2, 128(4) # encoding: [0xc8,0x44,0x00,0x80] + lfd 2, 128(4) +# CHECK: lfdx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xae] + lfdx 2, 3, 4 +# CHECK: lfdu 2, 128(4) # encoding: [0xcc,0x44,0x00,0x80] + lfdu 2, 128(4) +# CHECK: lfdux 2, 3, 4 # encoding: [0x7c,0x43,0x24,0xee] + lfdux 2, 3, 4 +# CHECK: lfiwax 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xae] + lfiwax 2, 3, 4 +# CHECK: lfiwzx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0xee] + lfiwzx 2, 3, 4 + +# Floating-point store instructions + +# CHECK: stfs 2, 128(4) # encoding: [0xd0,0x44,0x00,0x80] + stfs 2, 128(4) +# CHECK: stfsx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2e] + stfsx 2, 3, 4 +# CHECK: stfsu 2, 128(4) # encoding: [0xd4,0x44,0x00,0x80] + stfsu 2, 128(4) +# CHECK: stfsux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x6e] + stfsux 2, 3, 4 +# CHECK: stfd 2, 128(4) # encoding: [0xd8,0x44,0x00,0x80] + stfd 2, 128(4) +# CHECK: stfdx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xae] + stfdx 2, 3, 4 +# CHECK: stfdu 2, 128(4) # encoding: [0xdc,0x44,0x00,0x80] + stfdu 2, 128(4) +# CHECK: stfdux 2, 3, 4 # encoding: [0x7c,0x43,0x25,0xee] + stfdux 2, 3, 4 +# CHECK: stfiwx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0xae] + stfiwx 2, 3, 4 + +# Floating-point move instructions + +# CHECK: fmr 2, 3 # encoding: [0xfc,0x40,0x18,0x90] + fmr 2, 3 +# CHECK: fmr. 2, 3 # encoding: [0xfc,0x40,0x18,0x91] + fmr. 2, 3 +# CHECK: fneg 2, 3 # encoding: [0xfc,0x40,0x18,0x50] + fneg 2, 3 +# CHECK: fneg. 2, 3 # encoding: [0xfc,0x40,0x18,0x51] + fneg. 2, 3 +# CHECK: fabs 2, 3 # encoding: [0xfc,0x40,0x1a,0x10] + fabs 2, 3 +# CHECK: fabs. 2, 3 # encoding: [0xfc,0x40,0x1a,0x11] + fabs. 2, 3 +# CHECK: fnabs 2, 3 # encoding: [0xfc,0x40,0x19,0x10] + fnabs 2, 3 +# CHECK: fnabs. 2, 3 # encoding: [0xfc,0x40,0x19,0x11] + fnabs. 2, 3 +# FIXME: fcpsgn 2, 3 +# FIXME: fcpsgn. 2, 3 + +# Floating-point arithmetic instructions + +# CHECK: fadd 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2a] + fadd 2, 3, 4 +# CHECK: fadd. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x2b] + fadd. 2, 3, 4 +# CHECK: fadds 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2a] + fadds 2, 3, 4 +# CHECK: fadds. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x2b] + fadds. 2, 3, 4 +# CHECK: fsub 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x28] + fsub 2, 3, 4 +# CHECK: fsub. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x29] + fsub. 2, 3, 4 +# CHECK: fsubs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x28] + fsubs 2, 3, 4 +# CHECK: fsubs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x29] + fsubs. 2, 3, 4 + +# CHECK: fmul 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x32] + fmul 2, 3, 4 +# CHECK: fmul. 2, 3, 4 # encoding: [0xfc,0x43,0x01,0x33] + fmul. 2, 3, 4 +# CHECK: fmuls 2, 3, 4 # encoding: [0xec,0x43,0x01,0x32] + fmuls 2, 3, 4 +# CHECK: fmuls. 2, 3, 4 # encoding: [0xec,0x43,0x01,0x33] + fmuls. 2, 3, 4 +# CHECK: fdiv 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x24] + fdiv 2, 3, 4 +# CHECK: fdiv. 2, 3, 4 # encoding: [0xfc,0x43,0x20,0x25] + fdiv. 2, 3, 4 +# CHECK: fdivs 2, 3, 4 # encoding: [0xec,0x43,0x20,0x24] + fdivs 2, 3, 4 +# CHECK: fdivs. 2, 3, 4 # encoding: [0xec,0x43,0x20,0x25] + fdivs. 2, 3, 4 +# CHECK: fsqrt 2, 3 # encoding: [0xfc,0x40,0x18,0x2c] + fsqrt 2, 3 +# CHECK: fsqrt. 2, 3 # encoding: [0xfc,0x40,0x18,0x2d] + fsqrt. 2, 3 +# CHECK: fsqrts 2, 3 # encoding: [0xec,0x40,0x18,0x2c] + fsqrts 2, 3 +# CHECK: fsqrts. 2, 3 # encoding: [0xec,0x40,0x18,0x2d] + fsqrts. 2, 3 + +# CHECK: fre 2, 3 # encoding: [0xfc,0x40,0x18,0x30] + fre 2, 3 +# CHECK: fre. 2, 3 # encoding: [0xfc,0x40,0x18,0x31] + fre. 2, 3 +# CHECK: fres 2, 3 # encoding: [0xec,0x40,0x18,0x30] + fres 2, 3 +# CHECK: fres. 2, 3 # encoding: [0xec,0x40,0x18,0x31] + fres. 2, 3 +# CHECK: frsqrte 2, 3 # encoding: [0xfc,0x40,0x18,0x34] + frsqrte 2, 3 +# CHECK: frsqrte. 2, 3 # encoding: [0xfc,0x40,0x18,0x35] + frsqrte. 2, 3 +# CHECK: frsqrtes 2, 3 # encoding: [0xec,0x40,0x18,0x34] + frsqrtes 2, 3 +# CHECK: frsqrtes. 2, 3 # encoding: [0xec,0x40,0x18,0x35] + frsqrtes. 2, 3 +# FIXME: ftdiv 2, 3, 4 +# FIXME: ftsqrt 2, 3, 4 + +# CHECK: fmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3a] + fmadd 2, 3, 4, 5 +# CHECK: fmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3b] + fmadd. 2, 3, 4, 5 +# CHECK: fmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3a] + fmadds 2, 3, 4, 5 +# CHECK: fmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3b] + fmadds. 2, 3, 4, 5 +# CHECK: fmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x38] + fmsub 2, 3, 4, 5 +# CHECK: fmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x39] + fmsub. 2, 3, 4, 5 +# CHECK: fmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x38] + fmsubs 2, 3, 4, 5 +# CHECK: fmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x39] + fmsubs. 2, 3, 4, 5 +# CHECK: fnmadd 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3e] + fnmadd 2, 3, 4, 5 +# CHECK: fnmadd. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3f] + fnmadd. 2, 3, 4, 5 +# CHECK: fnmadds 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3e] + fnmadds 2, 3, 4, 5 +# CHECK: fnmadds. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3f] + fnmadds. 2, 3, 4, 5 +# CHECK: fnmsub 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3c] + fnmsub 2, 3, 4, 5 +# CHECK: fnmsub. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x3d] + fnmsub. 2, 3, 4, 5 +# CHECK: fnmsubs 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3c] + fnmsubs 2, 3, 4, 5 +# CHECK: fnmsubs. 2, 3, 4, 5 # encoding: [0xec,0x43,0x29,0x3d] + fnmsubs. 2, 3, 4, 5 + +# Floating-point rounding and conversion instructions + +# CHECK: frsp 2, 3 # encoding: [0xfc,0x40,0x18,0x18] + frsp 2, 3 +# CHECK: frsp. 2, 3 # encoding: [0xfc,0x40,0x18,0x19] + frsp. 2, 3 + +# FIXME: fctid 2, 3 +# FIXME: fctid. 2, 3 +# CHECK: fctidz 2, 3 # encoding: [0xfc,0x40,0x1e,0x5e] + fctidz 2, 3 +# CHECK: fctidz. 2, 3 # encoding: [0xfc,0x40,0x1e,0x5f] + fctidz. 2, 3 +# FIXME: fctidu 2, 3 +# FIXME: fctidu. 2, 3 +# CHECK: fctiduz 2, 3 # encoding: [0xfc,0x40,0x1f,0x5e] + fctiduz 2, 3 +# CHECK: fctiduz. 2, 3 # encoding: [0xfc,0x40,0x1f,0x5f] + fctiduz. 2, 3 +# FIXME: fctiw 2, 3 +# FIXME: fctiw. 2, 3 +# CHECK: fctiwz 2, 3 # encoding: [0xfc,0x40,0x18,0x1e] + fctiwz 2, 3 +# CHECK: fctiwz. 2, 3 # encoding: [0xfc,0x40,0x18,0x1f] + fctiwz. 2, 3 +# FIXME: fctiwu 2, 3 +# FIXME: fctiwu. 2, 3 +# CHECK: fctiwuz 2, 3 # encoding: [0xfc,0x40,0x19,0x1e] + fctiwuz 2, 3 +# CHECK: fctiwuz. 2, 3 # encoding: [0xfc,0x40,0x19,0x1f] + fctiwuz. 2, 3 +# CHECK: fcfid 2, 3 # encoding: [0xfc,0x40,0x1e,0x9c] + fcfid 2, 3 +# CHECK: fcfid. 2, 3 # encoding: [0xfc,0x40,0x1e,0x9d] + fcfid. 2, 3 +# CHECK: fcfidu 2, 3 # encoding: [0xfc,0x40,0x1f,0x9c] + fcfidu 2, 3 +# CHECK: fcfidu. 2, 3 # encoding: [0xfc,0x40,0x1f,0x9d] + fcfidu. 2, 3 +# CHECK: fcfids 2, 3 # encoding: [0xec,0x40,0x1e,0x9c] + fcfids 2, 3 +# CHECK: fcfids. 2, 3 # encoding: [0xec,0x40,0x1e,0x9d] + fcfids. 2, 3 +# CHECK: fcfidus 2, 3 # encoding: [0xec,0x40,0x1f,0x9c] + fcfidus 2, 3 +# CHECK: fcfidus. 2, 3 # encoding: [0xec,0x40,0x1f,0x9d] + fcfidus. 2, 3 +# CHECK: frin 2, 3 # encoding: [0xfc,0x40,0x1b,0x10] + frin 2, 3 +# CHECK: frin. 2, 3 # encoding: [0xfc,0x40,0x1b,0x11] + frin. 2, 3 +# CHECK: frip 2, 3 # encoding: [0xfc,0x40,0x1b,0x90] + frip 2, 3 +# CHECK: frip. 2, 3 # encoding: [0xfc,0x40,0x1b,0x91] + frip. 2, 3 +# CHECK: friz 2, 3 # encoding: [0xfc,0x40,0x1b,0x50] + friz 2, 3 +# CHECK: friz. 2, 3 # encoding: [0xfc,0x40,0x1b,0x51] + friz. 2, 3 +# CHECK: frim 2, 3 # encoding: [0xfc,0x40,0x1b,0xd0] + frim 2, 3 +# CHECK: frim. 2, 3 # encoding: [0xfc,0x40,0x1b,0xd1] + frim. 2, 3 + +# Floating-point compare instructions + +# CHECK: fcmpu 2, 3, 4 # encoding: [0xfd,0x03,0x20,0x00] + fcmpu 2, 3, 4 +# FIXME: fcmpo 2, 3, 4 + +# Floating-point select instruction + +# CHECK: fsel 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2e] + fsel 2, 3, 4, 5 +# CHECK: fsel. 2, 3, 4, 5 # encoding: [0xfc,0x43,0x29,0x2f] + fsel. 2, 3, 4, 5 + +# Floating-point status and control register instructions + +# CHECK: mffs 2 # encoding: [0xfc,0x40,0x04,0x8e] + mffs 2 +# FIXME: mffs. 2 + +# FIXME: mcrfs 2, 3 + +# FIXME: mtfsfi 2, 3, 1 +# FIXME: mtfsfi. 2, 3, 1 +# FIXME: mtfsf 2, 3, 1, 1 +# FIXME: mtfsf. 2, 3, 1, 1 + +# CHECK: mtfsb0 31 # encoding: [0xff,0xe0,0x00,0x8c] + mtfsb0 31 +# FIXME: mtfsb0. 31 +# CHECK: mtfsb1 31 # encoding: [0xff,0xe0,0x00,0x4c] + mtfsb1 31 +# FIXME: mtfsb1. 31 + diff --git a/test/MC/PowerPC/ppc64-encoding-vmx.s b/test/MC/PowerPC/ppc64-encoding-vmx.s new file mode 100644 index 000000000000..0154076390bc --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding-vmx.s @@ -0,0 +1,384 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# Vector facility + +# Vector storage access instructions + +# CHECK: lvebx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0e] + lvebx 2, 3, 4 +# CHECK: lvehx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4e] + lvehx 2, 3, 4 +# CHECK: lvewx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x8e] + lvewx 2, 3, 4 +# CHECK: lvx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xce] + lvx 2, 3, 4 +# CHECK: lvxl 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xce] + lvxl 2, 3, 4 +# CHECK: stvebx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x0e] + stvebx 2, 3, 4 +# CHECK: stvehx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x4e] + stvehx 2, 3, 4 +# CHECK: stvewx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x8e] + stvewx 2, 3, 4 +# CHECK: stvx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xce] + stvx 2, 3, 4 +# CHECK: stvxl 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xce] + stvxl 2, 3, 4 +# CHECK: lvsl 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0c] + lvsl 2, 3, 4 +# CHECK: lvsr 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4c] + lvsr 2, 3, 4 + +# Vector permute and formatting instructions + +# CHECK: vpkpx 2, 3, 4 # encoding: [0x10,0x43,0x23,0x0e] + vpkpx 2, 3, 4 +# CHECK: vpkshss 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8e] + vpkshss 2, 3, 4 +# CHECK: vpkshus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0e] + vpkshus 2, 3, 4 +# CHECK: vpkswss 2, 3, 4 # encoding: [0x10,0x43,0x21,0xce] + vpkswss 2, 3, 4 +# CHECK: vpkswus 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4e] + vpkswus 2, 3, 4 +# CHECK: vpkuhum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0e] + vpkuhum 2, 3, 4 +# CHECK: vpkuhus 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8e] + vpkuhus 2, 3, 4 +# CHECK: vpkuwum 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4e] + vpkuwum 2, 3, 4 +# CHECK: vpkuwus 2, 3, 4 # encoding: [0x10,0x43,0x20,0xce] + vpkuwus 2, 3, 4 + +# CHECK: vupkhpx 2, 3 # encoding: [0x10,0x40,0x1b,0x4e] + vupkhpx 2, 3 +# CHECK: vupkhsb 2, 3 # encoding: [0x10,0x40,0x1a,0x0e] + vupkhsb 2, 3 +# CHECK: vupkhsh 2, 3 # encoding: [0x10,0x40,0x1a,0x4e] + vupkhsh 2, 3 +# CHECK: vupklpx 2, 3 # encoding: [0x10,0x40,0x1b,0xce] + vupklpx 2, 3 +# CHECK: vupklsb 2, 3 # encoding: [0x10,0x40,0x1a,0x8e] + vupklsb 2, 3 +# CHECK: vupklsh 2, 3 # encoding: [0x10,0x40,0x1a,0xce] + vupklsh 2, 3 + +# CHECK: vmrghb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0c] + vmrghb 2, 3, 4 +# CHECK: vmrghh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4c] + vmrghh 2, 3, 4 +# CHECK: vmrghw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x8c] + vmrghw 2, 3, 4 +# CHECK: vmrglb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x0c] + vmrglb 2, 3, 4 +# CHECK: vmrglh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x4c] + vmrglh 2, 3, 4 +# CHECK: vmrglw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x8c] + vmrglw 2, 3, 4 + +# CHECK: vspltb 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x0c] + vspltb 2, 3, 1 +# CHECK: vsplth 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x4c] + vsplth 2, 3, 1 +# CHECK: vspltw 2, 3, 1 # encoding: [0x10,0x41,0x1a,0x8c] + vspltw 2, 3, 1 +# CHECK: vspltisb 2, 3 # encoding: [0x10,0x43,0x03,0x0c] + vspltisb 2, 3 +# CHECK: vspltish 2, 3 # encoding: [0x10,0x43,0x03,0x4c] + vspltish 2, 3 +# CHECK: vspltisw 2, 3 # encoding: [0x10,0x43,0x03,0x8c] + vspltisw 2, 3 + +# CHECK: vperm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6b] + vperm 2, 3, 4, 5 +# CHECK: vsel 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6a] + vsel 2, 3, 4, 5 + +# CHECK: vsl 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc4] + vsl 2, 3, 4 +# CHECK: vsldoi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x6c] + vsldoi 2, 3, 4, 5 +# CHECK: vslo 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0c] + vslo 2, 3, 4 +# CHECK: vsr 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc4] + vsr 2, 3, 4 +# CHECK: vsro 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4c] + vsro 2, 3, 4 + +# Vector integer arithmetic instructions + +# CHECK: vaddcuw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x80] + vaddcuw 2, 3, 4 +# CHECK: vaddsbs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x00] + vaddsbs 2, 3, 4 +# CHECK: vaddshs 2, 3, 4 # encoding: [0x10,0x43,0x23,0x40] + vaddshs 2, 3, 4 +# CHECK: vaddsws 2, 3, 4 # encoding: [0x10,0x43,0x23,0x80] + vaddsws 2, 3, 4 +# CHECK: vaddubm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x00] + vaddubm 2, 3, 4 +# CHECK: vadduhm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x40] + vadduhm 2, 3, 4 +# CHECK: vadduwm 2, 3, 4 # encoding: [0x10,0x43,0x20,0x80] + vadduwm 2, 3, 4 +# CHECK: vaddubs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x00] + vaddubs 2, 3, 4 +# CHECK: vadduhs 2, 3, 4 # encoding: [0x10,0x43,0x22,0x40] + vadduhs 2, 3, 4 +# CHECK: vadduws 2, 3, 4 # encoding: [0x10,0x43,0x22,0x80] + vadduws 2, 3, 4 + +# CHECK: vsubcuw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x80] + vsubcuw 2, 3, 4 +# CHECK: vsubsbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x00] + vsubsbs 2, 3, 4 +# CHECK: vsubshs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x40] + vsubshs 2, 3, 4 +# CHECK: vsubsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x80] + vsubsws 2, 3, 4 +# CHECK: vsububm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x00] + vsububm 2, 3, 4 +# CHECK: vsubuhm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x40] + vsubuhm 2, 3, 4 +# CHECK: vsubuwm 2, 3, 4 # encoding: [0x10,0x43,0x24,0x80] + vsubuwm 2, 3, 4 +# CHECK: vsububs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x00] + vsububs 2, 3, 4 +# CHECK: vsubuhs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x40] + vsubuhs 2, 3, 4 +# CHECK: vsubuws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x80] + vsubuws 2, 3, 4 + +# CHECK: vmulesb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x08] + vmulesb 2, 3, 4 +# CHECK: vmulesh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x48] + vmulesh 2, 3, 4 +# CHECK: vmuleub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x08] + vmuleub 2, 3, 4 +# CHECK: vmuleuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x48] + vmuleuh 2, 3, 4 +# CHECK: vmulosb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x08] + vmulosb 2, 3, 4 +# CHECK: vmulosh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x48] + vmulosh 2, 3, 4 +# CHECK: vmuloub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x08] + vmuloub 2, 3, 4 +# CHECK: vmulouh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x48] + vmulouh 2, 3, 4 + +# CHECK: vmhaddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x60] + vmhaddshs 2, 3, 4, 5 +# CHECK: vmhraddshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x61] + vmhraddshs 2, 3, 4, 5 +# CHECK: vmladduhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x62] + vmladduhm 2, 3, 4, 5 +# CHECK: vmsumubm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x64] + vmsumubm 2, 3, 4, 5 +# CHECK: vmsummbm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x65] + vmsummbm 2, 3, 4, 5 +# CHECK: vmsumshm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x68] + vmsumshm 2, 3, 4, 5 +# CHECK: vmsumshs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x69] + vmsumshs 2, 3, 4, 5 +# CHECK: vmsumuhm 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x66] + vmsumuhm 2, 3, 4, 5 +# CHECK: vmsumuhs 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x67] + vmsumuhs 2, 3, 4, 5 + +# CHECK: vsumsws 2, 3, 4 # encoding: [0x10,0x43,0x27,0x88] + vsumsws 2, 3, 4 +# CHECK: vsum2sws 2, 3, 4 # encoding: [0x10,0x43,0x26,0x88] + vsum2sws 2, 3, 4 +# CHECK: vsum4sbs 2, 3, 4 # encoding: [0x10,0x43,0x27,0x08] + vsum4sbs 2, 3, 4 +# CHECK: vsum4shs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x48] + vsum4shs 2, 3, 4 +# CHECK: vsum4ubs 2, 3, 4 # encoding: [0x10,0x43,0x26,0x08] + vsum4ubs 2, 3, 4 + +# CHECK: vavgsb 2, 3, 4 # encoding: [0x10,0x43,0x25,0x02] + vavgsb 2, 3, 4 +# CHECK: vavgsh 2, 3, 4 # encoding: [0x10,0x43,0x25,0x42] + vavgsh 2, 3, 4 +# CHECK: vavgsw 2, 3, 4 # encoding: [0x10,0x43,0x25,0x82] + vavgsw 2, 3, 4 +# CHECK: vavgub 2, 3, 4 # encoding: [0x10,0x43,0x24,0x02] + vavgub 2, 3, 4 +# CHECK: vavguh 2, 3, 4 # encoding: [0x10,0x43,0x24,0x42] + vavguh 2, 3, 4 +# CHECK: vavguw 2, 3, 4 # encoding: [0x10,0x43,0x24,0x82] + vavguw 2, 3, 4 + +# CHECK: vmaxsb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x02] + vmaxsb 2, 3, 4 +# CHECK: vmaxsh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x42] + vmaxsh 2, 3, 4 +# CHECK: vmaxsw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x82] + vmaxsw 2, 3, 4 +# CHECK: vmaxub 2, 3, 4 # encoding: [0x10,0x43,0x20,0x02] + vmaxub 2, 3, 4 +# CHECK: vmaxuh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x42] + vmaxuh 2, 3, 4 +# CHECK: vmaxuw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x82] + vmaxuw 2, 3, 4 + +# CHECK: vminsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x02] + vminsb 2, 3, 4 +# CHECK: vminsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x42] + vminsh 2, 3, 4 +# CHECK: vminsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x82] + vminsw 2, 3, 4 +# CHECK: vminub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x02] + vminub 2, 3, 4 +# CHECK: vminuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x42] + vminuh 2, 3, 4 +# CHECK: vminuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x82] + vminuw 2, 3, 4 + +# Vector integer compare instructions + +# CHECK: vcmpequb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x06] + vcmpequb 2, 3, 4 +# CHECK: vcmpequb. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x06] + vcmpequb. 2, 3, 4 +# CHECK: vcmpequh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x46] + vcmpequh 2, 3, 4 +# CHECK: vcmpequh. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x46] + vcmpequh. 2, 3, 4 +# CHECK: vcmpequw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x86] + vcmpequw 2, 3, 4 +# CHECK: vcmpequw. 2, 3, 4 # encoding: [0x10,0x43,0x24,0x86] + vcmpequw. 2, 3, 4 +# CHECK: vcmpgtsb 2, 3, 4 # encoding: [0x10,0x43,0x23,0x06] + vcmpgtsb 2, 3, 4 +# CHECK: vcmpgtsb. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x06] + vcmpgtsb. 2, 3, 4 +# CHECK: vcmpgtsh 2, 3, 4 # encoding: [0x10,0x43,0x23,0x46] + vcmpgtsh 2, 3, 4 +# CHECK: vcmpgtsh. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x46] + vcmpgtsh. 2, 3, 4 +# CHECK: vcmpgtsw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x86] + vcmpgtsw 2, 3, 4 +# CHECK: vcmpgtsw. 2, 3, 4 # encoding: [0x10,0x43,0x27,0x86] + vcmpgtsw. 2, 3, 4 +# CHECK: vcmpgtub 2, 3, 4 # encoding: [0x10,0x43,0x22,0x06] + vcmpgtub 2, 3, 4 +# CHECK: vcmpgtub. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x06] + vcmpgtub. 2, 3, 4 +# CHECK: vcmpgtuh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x46] + vcmpgtuh 2, 3, 4 +# CHECK: vcmpgtuh. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x46] + vcmpgtuh. 2, 3, 4 +# CHECK: vcmpgtuw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x86] + vcmpgtuw 2, 3, 4 +# CHECK: vcmpgtuw. 2, 3, 4 # encoding: [0x10,0x43,0x26,0x86] + vcmpgtuw. 2, 3, 4 + +# Vector integer logical instructions + +# CHECK: vand 2, 3, 4 # encoding: [0x10,0x43,0x24,0x04] + vand 2, 3, 4 +# CHECK: vandc 2, 3, 4 # encoding: [0x10,0x43,0x24,0x44] + vandc 2, 3, 4 +# CHECK: vnor 2, 3, 4 # encoding: [0x10,0x43,0x25,0x04] + vnor 2, 3, 4 +# CHECK: vor 2, 3, 4 # encoding: [0x10,0x43,0x24,0x84] + vor 2, 3, 4 +# CHECK: vxor 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc4] + vxor 2, 3, 4 + +# Vector integer rotate and shift instructions + +# CHECK: vrlb 2, 3, 4 # encoding: [0x10,0x43,0x20,0x04] + vrlb 2, 3, 4 +# CHECK: vrlh 2, 3, 4 # encoding: [0x10,0x43,0x20,0x44] + vrlh 2, 3, 4 +# CHECK: vrlw 2, 3, 4 # encoding: [0x10,0x43,0x20,0x84] + vrlw 2, 3, 4 + +# CHECK: vslb 2, 3, 4 # encoding: [0x10,0x43,0x21,0x04] + vslb 2, 3, 4 +# CHECK: vslh 2, 3, 4 # encoding: [0x10,0x43,0x21,0x44] + vslh 2, 3, 4 +# CHECK: vslw 2, 3, 4 # encoding: [0x10,0x43,0x21,0x84] + vslw 2, 3, 4 +# CHECK: vsrb 2, 3, 4 # encoding: [0x10,0x43,0x22,0x04] + vsrb 2, 3, 4 +# CHECK: vsrh 2, 3, 4 # encoding: [0x10,0x43,0x22,0x44] + vsrh 2, 3, 4 +# CHECK: vsrw 2, 3, 4 # encoding: [0x10,0x43,0x22,0x84] + vsrw 2, 3, 4 +# CHECK: vsrab 2, 3, 4 # encoding: [0x10,0x43,0x23,0x04] + vsrab 2, 3, 4 +# CHECK: vsrah 2, 3, 4 # encoding: [0x10,0x43,0x23,0x44] + vsrah 2, 3, 4 +# CHECK: vsraw 2, 3, 4 # encoding: [0x10,0x43,0x23,0x84] + vsraw 2, 3, 4 + +# Vector floating-point instructions + +# CHECK: vaddfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x0a] + vaddfp 2, 3, 4 +# CHECK: vsubfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0x4a] + vsubfp 2, 3, 4 +# CHECK: vmaddfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2e] + vmaddfp 2, 3, 4, 5 +# CHECK: vnmsubfp 2, 3, 4, 5 # encoding: [0x10,0x43,0x29,0x2f] + vnmsubfp 2, 3, 4, 5 + +# CHECK: vmaxfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x0a] + vmaxfp 2, 3, 4 +# CHECK: vminfp 2, 3, 4 # encoding: [0x10,0x43,0x24,0x4a] + vminfp 2, 3, 4 + +# CHECK: vctsxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0xca] + vctsxs 2, 3, 4 +# CHECK: vctuxs 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x8a] + vctuxs 2, 3, 4 +# CHECK: vcfsx 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x4a] + vcfsx 2, 3, 4 +# CHECK: vcfux 2, 3, 4 # encoding: [0x10,0x44,0x1b,0x0a] + vcfux 2, 3, 4 +# CHECK: vrfim 2, 3 # encoding: [0x10,0x40,0x1a,0xca] + vrfim 2, 3 +# CHECK: vrfin 2, 3 # encoding: [0x10,0x40,0x1a,0x0a] + vrfin 2, 3 +# CHECK: vrfip 2, 3 # encoding: [0x10,0x40,0x1a,0x8a] + vrfip 2, 3 +# CHECK: vrfiz 2, 3 # encoding: [0x10,0x40,0x1a,0x4a] + vrfiz 2, 3 + +# CHECK: vcmpbfp 2, 3, 4 # encoding: [0x10,0x43,0x23,0xc6] + vcmpbfp 2, 3, 4 +# CHECK: vcmpbfp. 2, 3, 4 # encoding: [0x10,0x43,0x27,0xc6] + vcmpbfp. 2, 3, 4 +# CHECK: vcmpeqfp 2, 3, 4 # encoding: [0x10,0x43,0x20,0xc6] + vcmpeqfp 2, 3, 4 +# CHECK: vcmpeqfp. 2, 3, 4 # encoding: [0x10,0x43,0x24,0xc6] + vcmpeqfp. 2, 3, 4 +# CHECK: vcmpgefp 2, 3, 4 # encoding: [0x10,0x43,0x21,0xc6] + vcmpgefp 2, 3, 4 +# CHECK: vcmpgefp. 2, 3, 4 # encoding: [0x10,0x43,0x25,0xc6] + vcmpgefp. 2, 3, 4 +# CHECK: vcmpgtfp 2, 3, 4 # encoding: [0x10,0x43,0x22,0xc6] + vcmpgtfp 2, 3, 4 +# CHECK: vcmpgtfp. 2, 3, 4 # encoding: [0x10,0x43,0x26,0xc6] + vcmpgtfp. 2, 3, 4 + +# CHECK: vexptefp 2, 3 # encoding: [0x10,0x40,0x19,0x8a] + vexptefp 2, 3 +# CHECK: vlogefp 2, 3 # encoding: [0x10,0x40,0x19,0xca] + vlogefp 2, 3 +# CHECK: vrefp 2, 3 # encoding: [0x10,0x40,0x19,0x0a] + vrefp 2, 3 +# CHECK: vrsqrtefp 2, 3 # encoding: [0x10,0x40,0x19,0x4a] + vrsqrtefp 2, 3 + +# Vector status and control register instructions + +# CHECK: mtvscr 2 # encoding: [0x10,0x00,0x16,0x44] + mtvscr 2 +# CHECK: mfvscr 2 # encoding: [0x10,0x40,0x06,0x04] + mfvscr 2 + diff --git a/test/MC/PowerPC/ppc64-encoding.s b/test/MC/PowerPC/ppc64-encoding.s new file mode 100644 index 000000000000..dda796063849 --- /dev/null +++ b/test/MC/PowerPC/ppc64-encoding.s @@ -0,0 +1,480 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# Branch facility + +# Branch instructions + +# CHECK: b target # encoding: [0b010010AA,A,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 + b target +# FIXME: ba target +# CHECK: bl target # encoding: [0b010010AA,A,A,0bAAAAAA01] +# CHECK-NEXT: # fixup A - offset: 0, value: target, kind: fixup_ppc_br24 + bl target +# FIXME: bla target + +# FIXME: bc 4, 10, target +# FIXME: bca 4, 10, target +# FIXME: bcl 4, 10, target +# FIXME: bcla 4, 10, target + +# FIXME: bclr 4, 10, 3 +# FIXME: bclrl 4, 10, 3 +# FIXME: bcctr 4, 10, 3 +# FIXME: bcctrl 4, 10, 3 + +# Condition register instructions + +# FIXME: crand 2, 3, 4 +# FIXME: crnand 2, 3, 4 +# CHECK: cror 2, 3, 4 # encoding: [0x4c,0x43,0x23,0x82] + cror 2, 3, 4 +# FIXME: crxor 2, 3, 4 +# FIXME: crnor 2, 3, 4 +# CHECK: creqv 2, 3, 4 # encoding: [0x4c,0x43,0x22,0x42] + creqv 2, 3, 4 +# FIXME: crandc 2, 3, 4 +# FIXME: crorc 2, 3, 4 +# CHECK: mcrf 2, 3 # encoding: [0x4d,0x0c,0x00,0x00] + mcrf 2, 3 + +# System call instruction + +# FIXME: sc 1 + +# Fixed-point facility + +# Fixed-point load instructions + +# CHECK: lbz 2, 128(4) # encoding: [0x88,0x44,0x00,0x80] + lbz 2, 128(4) +# CHECK: lbzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xae] + lbzx 2, 3, 4 +# CHECK: lbzu 2, 128(4) # encoding: [0x8c,0x44,0x00,0x80] + lbzu 2, 128(4) +# CHECK: lbzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xee] + lbzux 2, 3, 4 +# CHECK: lhz 2, 128(4) # encoding: [0xa0,0x44,0x00,0x80] + lhz 2, 128(4) +# CHECK: lhzx 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x2e] + lhzx 2, 3, 4 +# CHECK: lhzu 2, 128(4) # encoding: [0xa4,0x44,0x00,0x80] + lhzu 2, 128(4) +# CHECK: lhzux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x6e] + lhzux 2, 3, 4 +# CHECK: lha 2, 128(4) # encoding: [0xa8,0x44,0x00,0x80] + lha 2, 128(4) +# CHECK: lhax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xae] + lhax 2, 3, 4 +# CHECK: lhau 2, 128(4) # encoding: [0xac,0x44,0x00,0x80] + lhau 2, 128(4) +# CHECK: lhaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xee] + lhaux 2, 3, 4 +# CHECK: lwz 2, 128(4) # encoding: [0x80,0x44,0x00,0x80] + lwz 2, 128(4) +# CHECK: lwzx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2e] + lwzx 2, 3, 4 +# CHECK: lwzu 2, 128(4) # encoding: [0x84,0x44,0x00,0x80] + lwzu 2, 128(4) +# CHECK: lwzux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6e] + lwzux 2, 3, 4 +# CHECK: lwa 2, 128(4) # encoding: [0xe8,0x44,0x00,0x82] + lwa 2, 128(4) +# CHECK: lwax 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xaa] + lwax 2, 3, 4 +# CHECK: lwaux 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xea] + lwaux 2, 3, 4 +# CHECK: ld 2, 128(4) # encoding: [0xe8,0x44,0x00,0x80] + ld 2, 128(4) +# CHECK: ldx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x2a] + ldx 2, 3, 4 +# CHECK: ldu 2, 128(4) # encoding: [0xe8,0x44,0x00,0x81] + ldu 2, 128(4) +# CHECK: ldux 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x6a] + ldux 2, 3, 4 + +# Fixed-point store instructions + +# CHECK: stb 2, 128(4) # encoding: [0x98,0x44,0x00,0x80] + stb 2, 128(4) +# CHECK: stbx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xae] + stbx 2, 3, 4 +# CHECK: stbu 2, 128(4) # encoding: [0x9c,0x44,0x00,0x80] + stbu 2, 128(4) +# CHECK: stbux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xee] + stbux 2, 3, 4 +# CHECK: sth 2, 128(4) # encoding: [0xb0,0x44,0x00,0x80] + sth 2, 128(4) +# CHECK: sthx 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x2e] + sthx 2, 3, 4 +# CHECK: sthu 2, 128(4) # encoding: [0xb4,0x44,0x00,0x80] + sthu 2, 128(4) +# CHECK: sthux 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x6e] + sthux 2, 3, 4 +# CHECK: stw 2, 128(4) # encoding: [0x90,0x44,0x00,0x80] + stw 2, 128(4) +# CHECK: stwx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2e] + stwx 2, 3, 4 +# CHECK: stwu 2, 128(4) # encoding: [0x94,0x44,0x00,0x80] + stwu 2, 128(4) +# CHECK: stwux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6e] + stwux 2, 3, 4 +# CHECK: std 2, 128(4) # encoding: [0xf8,0x44,0x00,0x80] + std 2, 128(4) +# CHECK: stdx 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x2a] + stdx 2, 3, 4 +# CHECK: stdu 2, 128(4) # encoding: [0xf8,0x44,0x00,0x81] + stdu 2, 128(4) +# CHECK: stdux 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x6a] + stdux 2, 3, 4 + +# Fixed-point load and store with byte reversal instructions + +# CHECK: lhbrx 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x2c] + lhbrx 2, 3, 4 +# CHECK: sthbrx 2, 3, 4 # encoding: [0x7c,0x43,0x27,0x2c] + sthbrx 2, 3, 4 +# CHECK: lwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x2c] + lwbrx 2, 3, 4 +# CHECK: stwbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x2c] + stwbrx 2, 3, 4 +# CHECK: ldbrx 2, 3, 4 # encoding: [0x7c,0x43,0x24,0x28] + ldbrx 2, 3, 4 +# CHECK: stdbrx 2, 3, 4 # encoding: [0x7c,0x43,0x25,0x28] + stdbrx 2, 3, 4 + +# FIXME: Fixed-point load and store multiple instructions + +# FIXME: Fixed-point move assist instructions + +# Fixed-point arithmetic instructions + +# CHECK: addi 2, 3, 128 # encoding: [0x38,0x43,0x00,0x80] + addi 2, 3, 128 +# CHECK: addis 2, 3, 128 # encoding: [0x3c,0x43,0x00,0x80] + addis 2, 3, 128 +# CHECK: add 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x14] + add 2, 3, 4 +# CHECK: add. 2, 3, 4 # encoding: [0x7c,0x43,0x22,0x15] + add. 2, 3, 4 +# FIXME: addo 2, 3, 4 +# FIXME: addo. 2, 3, 4 +# CHECK: subf 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x50] + subf 2, 3, 4 +# CHECK: subf. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x51] + subf. 2, 3, 4 +# FIXME: subfo 2, 3, 4 +# FIXME: subfo. 2, 3, 4 +# CHECK: addic 2, 3, 128 # encoding: [0x30,0x43,0x00,0x80] + addic 2, 3, 128 +# CHECK: addic. 2, 3, 128 # encoding: [0x34,0x43,0x00,0x80] + addic. 2, 3, 128 +# CHECK: subfic 2, 3, 4 # encoding: [0x20,0x43,0x00,0x04] + subfic 2, 3, 4 + +# CHECK: addc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x14] + addc 2, 3, 4 +# CHECK: addc. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x15] + addc. 2, 3, 4 +# FIXME: addco 2, 3, 4 +# FIXME: addco. 2, 3, 4 +# CHECK: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] + subfc 2, 3, 4 +# CHECK: subfc 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x10] + subfc 2, 3, 4 +# FIXME: subfco 2, 3, 4 +# FIXME: subfco. 2, 3, 4 + +# CHECK: adde 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x14] + adde 2, 3, 4 +# CHECK: adde. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x15] + adde. 2, 3, 4 +# FIXME: addeo 2, 3, 4 +# FIXME: addeo. 2, 3, 4 +# CHECK: subfe 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x10] + subfe 2, 3, 4 +# CHECK: subfe. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0x11] + subfe. 2, 3, 4 +# FIXME: subfeo 2, 3, 4 +# FIXME: subfeo. 2, 3, 4 + +# CHECK: addme 2, 3 # encoding: [0x7c,0x43,0x01,0xd4] + addme 2, 3 +# CHECK: addme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd5] + addme. 2, 3 +# FIXME: addmeo 2, 3 +# FIXME: addmeo. 2, 3 +# CHECK: subfme 2, 3 # encoding: [0x7c,0x43,0x01,0xd0] + subfme 2, 3 +# CHECK: subfme. 2, 3 # encoding: [0x7c,0x43,0x01,0xd1] + subfme. 2, 3 +# FIXME: subfmeo 2, 3 +# FIXME: subfmeo. 2, 3 + +# CHECK: addze 2, 3 # encoding: [0x7c,0x43,0x01,0x94] + addze 2, 3 +# CHECK: addze. 2, 3 # encoding: [0x7c,0x43,0x01,0x95] + addze. 2, 3 +# FIXME: addzeo 2, 3 +# FIXME: addzeo. 2, 3 +# CHECK: subfze 2, 3 # encoding: [0x7c,0x43,0x01,0x90] + subfze 2, 3 +# CHECK: subfze. 2, 3 # encoding: [0x7c,0x43,0x01,0x91] + subfze. 2, 3 +# FIXME: subfzeo 2, 3 +# FIXME: subfzeo. 2, 3 + +# CHECK: neg 2, 3 # encoding: [0x7c,0x43,0x00,0xd0] + neg 2, 3 +# CHECK: neg. 2, 3 # encoding: [0x7c,0x43,0x00,0xd1] + neg. 2, 3 +# FIXME: nego 2, 3 +# FIXME: nego. 2, 3 + +# CHECK: mulli 2, 3, 128 # encoding: [0x1c,0x43,0x00,0x80] + mulli 2, 3, 128 +# CHECK: mulhw 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x96] + mulhw 2, 3, 4 +# CHECK: mulhw. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x97] + mulhw. 2, 3, 4 +# CHECK: mullw 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd6] + mullw 2, 3, 4 +# CHECK: mullw. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd7] + mullw. 2, 3, 4 +# FIXME: mullwo 2, 3, 4 +# FIXME: mullwo. 2, 3, 4 +# CHECK: mulhwu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x16] + mulhwu 2, 3, 4 +# CHECK: mulhwu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x17] + mulhwu. 2, 3, 4 + +# CHECK: divw 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd6] + divw 2, 3, 4 +# CHECK: divw. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd7] + divw. 2, 3, 4 +# FIXME: divwo 2, 3, 4 +# FIXME: divwo. 2, 3, 4 +# CHECK: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96] + divwu 2, 3, 4 +# CHECK: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97] + divwu. 2, 3, 4 +# FIXME: divwuo 2, 3, 4 +# FIXME: divwuo. 2, 3, 4 +# FIXME: divwe 2, 3, 4 +# FIXME: divwe. 2, 3, 4 +# FIXME: divweo 2, 3, 4 +# FIXME: divweo. 2, 3, 4 +# FIXME: divweu 2, 3, 4 +# FIXME: divweu. 2, 3, 4 +# FIXME: divweuo 2, 3, 4 +# FIXME: divweuo. 2, 3, 4 + +# CHECK: mulld 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd2] + mulld 2, 3, 4 +# CHECK: mulld. 2, 3, 4 # encoding: [0x7c,0x43,0x21,0xd3] + mulld. 2, 3, 4 +# FIXME: mulldo 2, 3, 4 +# FIXME: mulldo. 2, 3, 4 +# CHECK: mulhd 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x92] + mulhd 2, 3, 4 +# CHECK: mulhd. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x93] + mulhd. 2, 3, 4 +# CHECK: mulhdu 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x12] + mulhdu 2, 3, 4 +# CHECK: mulhdu. 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x13] + mulhdu. 2, 3, 4 + +# CHECK: divd 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd2] + divd 2, 3, 4 +# CHECK: divd. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0xd3] + divd. 2, 3, 4 +# FIXME: divdo 2, 3, 4 +# FIXME: divdo. 2, 3, 4 +# CHECK: divdu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x92] + divdu 2, 3, 4 +# CHECK: divdu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x93] + divdu. 2, 3, 4 +# FIXME: divduo 2, 3, 4 +# FIXME: divduo. 2, 3, 4 +# FIXME: divde 2, 3, 4 +# FIXME: divde. 2, 3, 4 +# FIXME: divdeo 2, 3, 4 +# FIXME: divdeo. 2, 3, 4 +# FIXME: divdeu 2, 3, 4 +# FIXME: divdeu. 2, 3, 4 +# FIXME: divdeuo 2, 3, 4 +# FIXME: divdeuo. 2, 3, 4 + +# FIXME: Fixed-point compare instructions + +# FIXME: Fixed-point trap instructions + +# Fixed-point select + +# CHECK: isel 2, 3, 4, 5 # encoding: [0x7c,0x43,0x21,0x5e] + isel 2, 3, 4, 5 + +# Fixed-point logical instructions + +# CHECK: andi. 2, 3, 128 # encoding: [0x70,0x62,0x00,0x80] + andi. 2, 3, 128 +# CHECK: andis. 2, 3, 128 # encoding: [0x74,0x62,0x00,0x80] + andis. 2, 3, 128 +# CHECK: ori 2, 3, 128 # encoding: [0x60,0x62,0x00,0x80] + ori 2, 3, 128 +# CHECK: oris 2, 3, 128 # encoding: [0x64,0x62,0x00,0x80] + oris 2, 3, 128 +# CHECK: xori 2, 3, 128 # encoding: [0x68,0x62,0x00,0x80] + xori 2, 3, 128 +# CHECK: xoris 2, 3, 128 # encoding: [0x6c,0x62,0x00,0x80] + xoris 2, 3, 128 +# CHECK: and 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x38] + and 2, 3, 4 +# CHECK: and. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x39] + and. 2, 3, 4 +# CHECK: xor 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x78] + xor 2, 3, 4 +# CHECK: xor. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x79] + xor. 2, 3, 4 +# CHECK: nand 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb8] + nand 2, 3, 4 +# CHECK: nand. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0xb9] + nand. 2, 3, 4 +# CHECK: or 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x78] + or 2, 3, 4 +# CHECK: or. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x79] + or. 2, 3, 4 +# CHECK: nor 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf8] + nor 2, 3, 4 +# CHECK: nor. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0xf9] + nor. 2, 3, 4 +# CHECK: eqv 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x38] + eqv 2, 3, 4 +# CHECK: eqv. 2, 3, 4 # encoding: [0x7c,0x62,0x22,0x39] + eqv. 2, 3, 4 +# CHECK: andc 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x78] + andc 2, 3, 4 +# CHECK: andc. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x79] + andc. 2, 3, 4 +# CHECK: orc 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x38] + orc 2, 3, 4 +# CHECK: orc. 2, 3, 4 # encoding: [0x7c,0x62,0x23,0x39] + orc. 2, 3, 4 + +# CHECK: extsb 2, 3 # encoding: [0x7c,0x62,0x07,0x74] + extsb 2, 3 +# CHECK: extsb. 2, 3 # encoding: [0x7c,0x62,0x07,0x75] + extsb. 2, 3 +# CHECK: extsh 2, 3 # encoding: [0x7c,0x62,0x07,0x34] + extsh 2, 3 +# CHECK: extsh. 2, 3 # encoding: [0x7c,0x62,0x07,0x35] + extsh. 2, 3 + +# CHECK: cntlzw 2, 3 # encoding: [0x7c,0x62,0x00,0x34] + cntlzw 2, 3 +# CHECK: cntlzw. 2, 3 # encoding: [0x7c,0x62,0x00,0x35] + cntlzw. 2, 3 +# FIXME: cmpb 2, 3, 4 +# FIXME: popcntb 2, 3 +# CHECK: popcntw 2, 3 # encoding: [0x7c,0x62,0x02,0xf4] + popcntw 2, 3 +# FIXME: prtyd 2, 3 +# FIXME: prtyw 2, 3 + +# CHECK: extsw 2, 3 # encoding: [0x7c,0x62,0x07,0xb4] + extsw 2, 3 +# CHECK: extsw. 2, 3 # encoding: [0x7c,0x62,0x07,0xb5] + extsw. 2, 3 + +# CHECK: cntlzd 2, 3 # encoding: [0x7c,0x62,0x00,0x74] + cntlzd 2, 3 +# CHECK: cntlzd. 2, 3 # encoding: [0x7c,0x62,0x00,0x75] + cntlzd. 2, 3 +# CHECK: popcntd 2, 3 # encoding: [0x7c,0x62,0x03,0xf4] + popcntd 2, 3 +# FIXME: bpermd 2, 3, 4 + +# Fixed-point rotate and shift instructions + +# CHECK: rlwinm 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4c] + rlwinm 2, 3, 4, 5, 6 +# CHECK: rlwinm. 2, 3, 4, 5, 6 # encoding: [0x54,0x62,0x21,0x4d] + rlwinm. 2, 3, 4, 5, 6 +# CHECK: rlwnm 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4c] + rlwnm 2, 3, 4, 5, 6 +# CHECK: rlwnm. 2, 3, 4, 5, 6 # encoding: [0x5c,0x62,0x21,0x4d] + rlwnm. 2, 3, 4, 5, 6 +# CHECK: rlwimi 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4c] + rlwimi 2, 3, 4, 5, 6 +# CHECK: rlwimi. 2, 3, 4, 5, 6 # encoding: [0x50,0x62,0x21,0x4d] + rlwimi. 2, 3, 4, 5, 6 +# CHECK: rldicl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x40] + rldicl 2, 3, 4, 5 +# CHECK: rldicl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x41] + rldicl. 2, 3, 4, 5 +# CHECK: rldicr 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x44] + rldicr 2, 3, 4, 5 +# CHECK: rldicr. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x45] + rldicr. 2, 3, 4, 5 +# FIXME: rldic 2, 3, 4, 5 +# FIXME: rldic. 2, 3, 4, 5 +# CHECK: rldcl 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x50] + rldcl 2, 3, 4, 5 +# CHECK: rldcl. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x51] + rldcl. 2, 3, 4, 5 +# FIXME: rldcr 2, 3, 4, 5 +# FIXME: rldcr. 2, 3, 4, 5 +# CHECK: rldimi 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4c] + rldimi 2, 3, 4, 5 +# CHECK: rldimi. 2, 3, 4, 5 # encoding: [0x78,0x62,0x21,0x4d] + rldimi. 2, 3, 4, 5 + +# CHECK: slw 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x30] + slw 2, 3, 4 +# CHECK: slw. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x31] + slw. 2, 3, 4 +# CHECK: srw 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x30] + srw 2, 3, 4 +# CHECK: srw. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x31] + srw. 2, 3, 4 +# CHECK: srawi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x70] + srawi 2, 3, 4 +# CHECK: srawi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x71] + srawi. 2, 3, 4 +# CHECK: sraw 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x30] + sraw 2, 3, 4 +# CHECK: sraw. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x31] + sraw. 2, 3, 4 +# CHECK: sld 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x36] + sld 2, 3, 4 +# CHECK: sld. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x37] + sld. 2, 3, 4 +# CHECK: srd 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x36] + srd 2, 3, 4 +# CHECK: srd. 2, 3, 4 # encoding: [0x7c,0x62,0x24,0x37] + srd. 2, 3, 4 +# CHECK: sradi 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x74] + sradi 2, 3, 4 +# CHECK: sradi. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x75] + sradi. 2, 3, 4 +# CHECK: srad 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x34] + srad 2, 3, 4 +# CHECK: srad. 2, 3, 4 # encoding: [0x7c,0x62,0x26,0x35] + srad. 2, 3, 4 + +# FIXME: BCD assist instructions + +# Move to/from system register instructions + +# FIXME: mtspr 256, 2 +# FIXME: mfspr 2, 256 +# CHECK: mtcrf 16, 2 # encoding: [0x7c,0x41,0x01,0x20] + mtcrf 16, 2 +# CHECK: mfcr 2 # encoding: [0x7c,0x40,0x00,0x26] + mfcr 2 +# FIXME: mtocrf 16, 2 +# CHECK: mfocrf 16, 8 # encoding: [0x7e,0x10,0x80,0x26] + mfocrf 16, 8 +# FIXME: mcrxr 2 + diff --git a/test/MC/PowerPC/ppc64-errors.s b/test/MC/PowerPC/ppc64-errors.s new file mode 100644 index 000000000000..1da575304609 --- /dev/null +++ b/test/MC/PowerPC/ppc64-errors.s @@ -0,0 +1,80 @@ + +# RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t +# RUN: FileCheck < %t %s + +# Register operands + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: add 32, 32, 32 + add 32, 32, 32 + +# CHECK: error: invalid register name +# CHECK-NEXT: add %r32, %r32, %r32 + add %r32, %r32, %r32 + +# Signed 16-bit immediate operands + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: addi 1, 0, -32769 + addi 1, 0, -32769 + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: addi 1, 0, 32768 + addi 1, 0, 32768 + +# Unsigned 16-bit immediate operands + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ori 1, 2, -1 + ori 1, 2, -1 + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ori 1, 2, 65536 + ori 1, 2, 65536 + +# D-Form memory operands + +# CHECK: error: invalid register number +# CHECK-NEXT: lwz 1, 0(32) + lwz 1, 0(32) + +# CHECK: error: invalid register name +# CHECK-NEXT: lwz 1, 0(%r32) + lwz 1, 0(%r32) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: lwz 1, -32769(2) + lwz 1, -32769(2) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: lwz 1, 32768(2) + lwz 1, 32768(2) + +# CHECK: error: invalid register number +# CHECK-NEXT: ld 1, 0(32) + ld 1, 0(32) + +# CHECK: error: invalid register name +# CHECK-NEXT: ld 1, 0(%r32) + ld 1, 0(%r32) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ld 1, 1(2) + ld 1, 1(2) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ld 1, 2(2) + ld 1, 2(2) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ld 1, 3(2) + ld 1, 3(2) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ld 1, -32772(2) + ld 1, -32772(2) + +# CHECK: error: invalid operand for instruction +# CHECK-NEXT: ld 1, 32768(2) + ld 1, 32768(2) + diff --git a/test/MC/PowerPC/ppc64-fixups.s b/test/MC/PowerPC/ppc64-fixups.s new file mode 100644 index 000000000000..1dcbca8f8189 --- /dev/null +++ b/test/MC/PowerPC/ppc64-fixups.s @@ -0,0 +1,95 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# FIXME: .TOC.@tocbase + +# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 + li 3, target@l + +# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16 + addis 3, 3, target@ha + +# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@ha, kind: fixup_ppc_ha16 + lis 3, target@ha + +# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 + addi 4, 3, target@l + +# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16 + lwz 1, target@l(3) + +# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target@l, kind: fixup_ppc_lo16_ds + ld 1, target@l(3) + +# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target@toc, kind: fixup_ppc_lo16_ds + ld 1, target@toc(2) + +# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@toc@ha + +# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16 + addi 4, 3, target@toc@l + +# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16 + lwz 1, target@toc@l(3) + +# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target@toc@l, kind: fixup_ppc_lo16_ds + ld 1, target@toc@l(3) + +# FIXME: @tls + + +# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@tprel@ha + +# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@tprel@l, kind: fixup_ppc_lo16 + addi 3, 3, target@tprel@l + +# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@dtprel@ha + +# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@dtprel@l, kind: fixup_ppc_lo16 + addi 3, 3, target@dtprel@l + + +# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@got@tprel@ha + +# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tprel@l, kind: fixup_ppc_lo16_ds + ld 1, target@got@tprel@l(3) + + +# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@got@tlsgd@ha + +# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsgd@l, kind: fixup_ppc_lo16 + addi 3, 3, target@got@tlsgd@l + + +# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@ha, kind: fixup_ppc_ha16 + addis 3, 2, target@got@tlsld@ha + +# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A] +# CHECK-NEXT: # fixup A - offset: 0, value: target@got@tlsld@l, kind: fixup_ppc_lo16 + addi 3, 3, target@got@tlsld@l + diff --git a/test/MC/PowerPC/ppc64-initial-cfa.ll b/test/MC/PowerPC/ppc64-initial-cfa.ll index 16236c9c650d..23a77384ecd0 100644 --- a/test/MC/PowerPC/ppc64-initial-cfa.ll +++ b/test/MC/PowerPC/ppc64-initial-cfa.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=static %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s -check-prefix=STATIC +; RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=STATIC ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj -relocation-model=pic %s -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck %s -check-prefix=PIC +; RUN: llvm-readobj -s -sr -sd | FileCheck %s -check-prefix=PIC ; FIXME: this file should be in .s form, change when asm parser is available. @@ -10,69 +10,75 @@ entry: ret void } -; STATIC: ('sh_name', 0x{{.*}}) # '.eh_frame' -; STATIC-NEXT: ('sh_type', 0x00000001) -; STATIC-NEXT: ('sh_flags', 0x0000000000000002) -; STATIC-NEXT: ('sh_addr', 0x{{.*}}) -; STATIC-NEXT: ('sh_offset', 0x{{.*}}) -; STATIC-NEXT: ('sh_size', 0x0000000000000028) -; STATIC-NEXT: ('sh_link', 0x00000000) -; STATIC-NEXT: ('sh_info', 0x00000000) -; STATIC-NEXT: ('sh_addralign', 0x0000000000000008) -; STATIC-NEXT: ('sh_entsize', 0x0000000000000000) -; STATIC-NEXT: ('_section_data', '00000010 00000000 017a5200 01784101 1b0c0100 00000010 00000018 00000000 00000010 00000000') +; STATIC: Section { +; STATIC: Name: .eh_frame +; STATIC-NEXT: Type: SHT_PROGBITS +; STATIC-NEXT: Flags [ (0x2) +; STATIC-NEXT: SHF_ALLOC +; STATIC-NEXT: ] +; STATIC-NEXT: Address: +; STATIC-NEXT: Offset: +; STATIC-NEXT: Size: 40 +; STATIC-NEXT: Link: 0 +; STATIC-NEXT: Info: 0 +; STATIC-NEXT: AddressAlignment: 8 +; STATIC-NEXT: EntrySize: +; STATIC-NEXT: Relocations [ +; STATIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 +; STATIC-NEXT: ] +; STATIC-NEXT: SectionData ( +; STATIC-NEXT: 0000: 00000010 00000000 017A5200 01784101 +; STATIC-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 +; STATIC-NEXT: 0020: 00000010 00000000 +; STATIC-NEXT: ) +; STATIC-NEXT: } -; STATIC: ('sh_name', 0x{{.*}}) # '.rela.eh_frame' -; STATIC-NEXT: ('sh_type', 0x00000004) -; STATIC-NEXT: ('sh_flags', 0x0000000000000000) -; STATIC-NEXT: ('sh_addr', 0x{{.*}}) -; STATIC-NEXT: ('sh_offset', 0x{{.*}}) -; STATIC-NEXT: ('sh_size', 0x0000000000000018) -; STATIC-NEXT: ('sh_link', 0x{{.*}}) -; STATIC-NEXT: ('sh_info', 0x{{.*}}) -; STATIC-NEXT: ('sh_addralign', 0x0000000000000008) -; STATIC-NEXT: ('sh_entsize', 0x0000000000000018) -; STATIC-NEXT: ('_relocations', [ +; STATIC: Section { +; STATIC: Name: .rela.eh_frame +; STATIC-NEXT: Type: SHT_RELA +; STATIC-NEXT: Flags [ (0x0) +; STATIC-NEXT: ] +; STATIC-NEXT: Address: +; STATIC-NEXT: Offset: +; STATIC-NEXT: Size: 24 +; STATIC-NEXT: Link: +; STATIC-NEXT: Info: +; STATIC-NEXT: AddressAlignment: 8 +; STATIC-NEXT: EntrySize: 24 -; Static build should create R_PPC64_REL32 relocations -; STATIC-NEXT: # Relocation 0 -; STATIC-NEXT: (('r_offset', 0x000000000000001c) -; STATIC-NEXT: ('r_sym', 0x{{.*}}) -; STATIC-NEXT: ('r_type', 0x0000001a) -; STATIC-NEXT: ('r_addend', 0x0000000000000000) -; STATIC-NEXT: ), -; STATIC-NEXT: ]) +; PIC: Section { +; PIC: Name: .eh_frame +; PIC-NEXT: Type: SHT_PROGBITS +; PIC-NEXT: Flags [ (0x2) +; PIC-NEXT: SHF_ALLOC +; PIC-NEXT: ] +; PIC-NEXT: Address: +; PIC-NEXT: Offset: +; PIC-NEXT: Size: 40 +; PIC-NEXT: Link: 0 +; PIC-NEXT: Info: 0 +; PIC-NEXT: AddressAlignment: 8 +; PIC-NEXT: EntrySize: 0 +; PIC-NEXT: Relocations [ +; PIC-NEXT: 0x1C R_PPC64_REL32 .text 0x0 +; PIC-NEXT: ] +; PIC-NEXT: SectionData ( +; PIC-NEXT: 0000: 00000010 00000000 017A5200 01784101 +; PIC-NEXT: 0010: 1B0C0100 00000010 00000018 00000000 +; PIC-NEXT: 0020: 00000010 00000000 +; PIC-NEXT: ) +; PIC-NEXT: } -; PIC: ('sh_name', 0x{{.*}}) # '.eh_frame' -; PIC-NEXT: ('sh_type', 0x00000001) -; PIC-NEXT: ('sh_flags', 0x0000000000000002) -; PIC-NEXT: ('sh_addr', 0x{{.*}}) -; PIC-NEXT: ('sh_offset', 0x{{.*}}) -; PIC-NEXT: ('sh_size', 0x0000000000000028) -; PIC-NEXT: ('sh_link', 0x00000000) -; PIC-NEXT: ('sh_info', 0x00000000) -; PIC-NEXT: ('sh_addralign', 0x0000000000000008) -; PIC-NEXT: ('sh_entsize', 0x0000000000000000) -; PIC-NEXT: ('_section_data', '00000010 00000000 017a5200 01784101 1b0c0100 00000010 00000018 00000000 00000010 00000000') - -; PIC: ('sh_name', 0x{{.*}}) # '.rela.eh_frame' -; PIC-NEXT: ('sh_type', 0x00000004) -; PIC-NEXT: ('sh_flags', 0x0000000000000000) -; PIC-NEXT: ('sh_addr', 0x{{.*}}) -; PIC-NEXT: ('sh_offset', 0x{{.*}}) -; PIC-NEXT: ('sh_size', 0x0000000000000018) -; PIC-NEXT: ('sh_link', 0x{{.*}}) -; PIC-NEXT: ('sh_info', 0x{{.*}}) -; PIC-NEXT: ('sh_addralign', 0x0000000000000008) -; PIC-NEXT: ('sh_entsize', 0x0000000000000018) -; PIC-NEXT: ('_relocations', [ - -; PIC build should create R_PPC64_REL32 relocations -; PIC-NEXT: # Relocation 0 -; PIC-NEXT: (('r_offset', 0x000000000000001c) -; PIC-NEXT: ('r_sym', 0x{{.*}}) -; PIC-NEXT: ('r_type', 0x0000001a) -; PIC-NEXT: ('r_addend', 0x0000000000000000) -; PIC-NEXT: ), -; PIC-NEXT: ]) +; PIC: Section { +; PIC: Name: .rela.eh_frame +; PIC-NEXT: Type: SHT_RELA +; PIC-NEXT: Flags [ (0x0) +; PIC-NEXT: ] +; PIC-NEXT: Address: +; PIC-NEXT: Offset: +; PIC-NEXT: Size: 24 +; PIC-NEXT: Link: +; PIC-NEXT: Info: +; PIC-NEXT: AddressAlignment: 8 +; PIC-NEXT: EntrySize: 24 diff --git a/test/MC/PowerPC/ppc64-operands.s b/test/MC/PowerPC/ppc64-operands.s new file mode 100644 index 000000000000..de5fcb0e8d2e --- /dev/null +++ b/test/MC/PowerPC/ppc64-operands.s @@ -0,0 +1,87 @@ + +# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s + +# Register operands + +# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] + add 1, 2, 3 + +# CHECK: add 1, 2, 3 # encoding: [0x7c,0x22,0x1a,0x14] + add %r1, %r2, %r3 + +# CHECK: add 0, 0, 0 # encoding: [0x7c,0x00,0x02,0x14] + add 0, 0, 0 + +# CHECK: add 31, 31, 31 # encoding: [0x7f,0xff,0xfa,0x14] + add 31, 31, 31 + +# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] + addi 1, 0, 0 + +# CHECK: addi 1, 0, 0 # encoding: [0x38,0x20,0x00,0x00] + addi 1, %r0, 0 + +# Signed 16-bit immediate operands + +# CHECK: addi 1, 2, 0 # encoding: [0x38,0x22,0x00,0x00] + addi 1, 2, 0 + +# CHECK: addi 1, 0, -32768 # encoding: [0x38,0x20,0x80,0x00] + addi 1, 0, -32768 + +# CHECK: addi 1, 0, 32767 # encoding: [0x38,0x20,0x7f,0xff] + addi 1, 0, 32767 + +# Unsigned 16-bit immediate operands + +# CHECK: ori 1, 2, 0 # encoding: [0x60,0x41,0x00,0x00] + ori 1, 2, 0 + +# CHECK: ori 1, 2, 65535 # encoding: [0x60,0x41,0xff,0xff] + ori 1, 2, 65535 + +# D-Form memory operands + +# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] + lwz 1, 0(0) + +# CHECK: lwz 1, 0(0) # encoding: [0x80,0x20,0x00,0x00] + lwz 1, 0(%r0) + +# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] + lwz 1, 0(31) + +# CHECK: lwz 1, 0(31) # encoding: [0x80,0x3f,0x00,0x00] + lwz 1, 0(%r31) + +# CHECK: lwz 1, -32768(2) # encoding: [0x80,0x22,0x80,0x00] + lwz 1, -32768(2) + +# CHECK: lwz 1, 32767(2) # encoding: [0x80,0x22,0x7f,0xff] + lwz 1, 32767(2) + + +# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] + ld 1, 0(0) + +# CHECK: ld 1, 0(0) # encoding: [0xe8,0x20,0x00,0x00] + ld 1, 0(%r0) + +# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] + ld 1, 0(31) + +# CHECK: ld 1, 0(31) # encoding: [0xe8,0x3f,0x00,0x00] + ld 1, 0(%r31) + +# CHECK: ld 1, -32768(2) # encoding: [0xe8,0x22,0x80,0x00] + ld 1, -32768(2) + +# CHECK: ld 1, 32764(2) # encoding: [0xe8,0x22,0x7f,0xfc] + ld 1, 32764(2) + +# CHECK: ld 1, 4(2) # encoding: [0xe8,0x22,0x00,0x04] + ld 1, 4(2) + +# CHECK: ld 1, -4(2) # encoding: [0xe8,0x22,0xff,0xfc] + ld 1, -4(2) + diff --git a/test/MC/PowerPC/ppc64-relocs-01.ll b/test/MC/PowerPC/ppc64-relocs-01.ll index 4919e91400ba..ac8d303dd4cf 100644 --- a/test/MC/PowerPC/ppc64-relocs-01.ll +++ b/test/MC/PowerPC/ppc64-relocs-01.ll @@ -1,6 +1,6 @@ ;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -O3 -code-model=small \ ;; RUN: -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck %s +;; RUN: llvm-readobj -r | FileCheck %s ;; FIXME: this file need to be in .s form, change when asm parse is done. @@ -22,45 +22,28 @@ entry: ret double %add } +;; CHECK: Relocations [ + ;; The relocations in .rela.text are the 'number64' load using a ;; R_PPC64_TOC16_DS against the .toc and the 'sin' external function ;; address using a R_PPC64_REL24 -;; CHECK: '.rela.text' -;; CHECK: Relocation 0 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000006 -;; CHECK-NEXT: 'r_type', 0x0000003f -;; CHECK: Relocation 1 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x0000000a -;; CHECK-NEXT: 'r_type', 0x0000000a +;; CHECK: Section ({{[0-9]+}}) .text { +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC16_DS .toc +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_REL24 sin +;; CHECK-NEXT: } ;; The .opd entry for the 'access_int64' function creates 2 relocations: ;; 1. A R_PPC64_ADDR64 against the .text segment plus addend (the function ; address itself); ;; 2. And a R_PPC64_TOC against no symbol (the linker will replace for the ;; module's TOC base). -;; CHECK: '.rela.opd' -;; CHECK: Relocation 0 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000002 -;; CHECK-NEXT: 'r_type', 0x00000026 -;; CHECK: Relocation 1 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000000 -;; CHECK-NEXT: 'r_type', 0x00000033 +;; CHECK: Section ({{[0-9]+}}) .opd { +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 .text 0x0 +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TOC - 0x0 ;; Finally the TOC creates the relocation for the 'number64'. -;; CHECK: '.rela.toc' -;; CHECK: Relocation 0 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000008 -;; CHECK-NEXT: 'r_type', 0x00000026 +;; CHECK: Section ({{[0-9]+}}) .toc { +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_ADDR64 number64 0x0 +;; CHECK-NEXT: } -;; Check if the relocation references are for correct symbols. -;; CHECK: Symbol 7 -;; CHECK-NEXT: 'access_int64' -;; CHECK: Symbol 8 -;; CHECK-NEXT: 'number64' -;; CHECK: Symbol 10 -;; CHECK-NEXT: 'sin' +;; CHECK-NEXT: ] diff --git a/test/MC/PowerPC/ppc64-tls-relocs-01.ll b/test/MC/PowerPC/ppc64-tls-relocs-01.ll index 5e3731107522..4e901e816a68 100644 --- a/test/MC/PowerPC/ppc64-tls-relocs-01.ll +++ b/test/MC/PowerPC/ppc64-tls-relocs-01.ll @@ -1,5 +1,5 @@ ;; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -filetype=obj %s -o - | \ -;; RUN: elf-dump --dump-section-data | FileCheck %s +;; RUN: llvm-readobj -r | FileCheck %s ;; FIXME: this file should be in .s form, change when asm parser is available. @@ -12,17 +12,8 @@ entry: ;; Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs ;; against the thread-local symbol 't'. -;; CHECK: '.rela.text' -;; CHECK: Relocation 0 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000008 -;; CHECK-NEXT: 'r_type', 0x00000048 -;; CHECK: Relocation 1 -;; CHECK-NEXT: 'r_offset', -;; CHECK-NEXT: 'r_sym', 0x00000008 -;; CHECK-NEXT: 'r_type', 0x00000046 - -;; Check that we got the correct symbol. -;; CHECK: Symbol 8 -;; CHECK-NEXT: 't' - +;; CHECK: Relocations [ +;; CHECK: Section ({{[0-9]+}}) .text { +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t +;; CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t +;; CHECK-NEXT: } diff --git a/test/MC/SystemZ/insn-a-01.s b/test/MC/SystemZ/insn-a-01.s new file mode 100644 index 000000000000..7bb94b31ebe8 --- /dev/null +++ b/test/MC/SystemZ/insn-a-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: a %r0, 0 # encoding: [0x5a,0x00,0x00,0x00] +#CHECK: a %r0, 4095 # encoding: [0x5a,0x00,0x0f,0xff] +#CHECK: a %r0, 0(%r1) # encoding: [0x5a,0x00,0x10,0x00] +#CHECK: a %r0, 0(%r15) # encoding: [0x5a,0x00,0xf0,0x00] +#CHECK: a %r0, 4095(%r1,%r15) # encoding: [0x5a,0x01,0xff,0xff] +#CHECK: a %r0, 4095(%r15,%r1) # encoding: [0x5a,0x0f,0x1f,0xff] +#CHECK: a %r15, 0 # encoding: [0x5a,0xf0,0x00,0x00] + + a %r0, 0 + a %r0, 4095 + a %r0, 0(%r1) + a %r0, 0(%r15) + a %r0, 4095(%r1,%r15) + a %r0, 4095(%r15,%r1) + a %r15, 0 diff --git a/test/MC/SystemZ/insn-a-02.s b/test/MC/SystemZ/insn-a-02.s new file mode 100644 index 000000000000..9cc967e0cefb --- /dev/null +++ b/test/MC/SystemZ/insn-a-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: a %r0, -1 +#CHECK: error: invalid operand +#CHECK: a %r0, 4096 + + a %r0, -1 + a %r0, 4096 diff --git a/test/MC/SystemZ/insn-adb-01.s b/test/MC/SystemZ/insn-adb-01.s new file mode 100644 index 000000000000..b54be60c6b53 --- /dev/null +++ b/test/MC/SystemZ/insn-adb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: adb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1a] +#CHECK: adb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1a] +#CHECK: adb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1a] +#CHECK: adb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1a] +#CHECK: adb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1a] +#CHECK: adb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1a] +#CHECK: adb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1a] + + adb %f0, 0 + adb %f0, 4095 + adb %f0, 0(%r1) + adb %f0, 0(%r15) + adb %f0, 4095(%r1,%r15) + adb %f0, 4095(%r15,%r1) + adb %f15, 0 diff --git a/test/MC/SystemZ/insn-adb-02.s b/test/MC/SystemZ/insn-adb-02.s new file mode 100644 index 000000000000..ff97a51affa8 --- /dev/null +++ b/test/MC/SystemZ/insn-adb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: adb %f0, -1 +#CHECK: error: invalid operand +#CHECK: adb %f0, 4096 + + adb %f0, -1 + adb %f0, 4096 diff --git a/test/MC/SystemZ/insn-adbr-01.s b/test/MC/SystemZ/insn-adbr-01.s new file mode 100644 index 000000000000..05724d2a6a89 --- /dev/null +++ b/test/MC/SystemZ/insn-adbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: adbr %f0, %f0 # encoding: [0xb3,0x1a,0x00,0x00] +#CHECK: adbr %f0, %f15 # encoding: [0xb3,0x1a,0x00,0x0f] +#CHECK: adbr %f7, %f8 # encoding: [0xb3,0x1a,0x00,0x78] +#CHECK: adbr %f15, %f0 # encoding: [0xb3,0x1a,0x00,0xf0] + + adbr %f0, %f0 + adbr %f0, %f15 + adbr %f7, %f8 + adbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-aeb-01.s b/test/MC/SystemZ/insn-aeb-01.s new file mode 100644 index 000000000000..b4268e5c72b6 --- /dev/null +++ b/test/MC/SystemZ/insn-aeb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: aeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0a] +#CHECK: aeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0a] +#CHECK: aeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0a] +#CHECK: aeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0a] +#CHECK: aeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0a] +#CHECK: aeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0a] +#CHECK: aeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0a] + + aeb %f0, 0 + aeb %f0, 4095 + aeb %f0, 0(%r1) + aeb %f0, 0(%r15) + aeb %f0, 4095(%r1,%r15) + aeb %f0, 4095(%r15,%r1) + aeb %f15, 0 diff --git a/test/MC/SystemZ/insn-aeb-02.s b/test/MC/SystemZ/insn-aeb-02.s new file mode 100644 index 000000000000..4fade8ecebce --- /dev/null +++ b/test/MC/SystemZ/insn-aeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: aeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: aeb %f0, 4096 + + aeb %f0, -1 + aeb %f0, 4096 diff --git a/test/MC/SystemZ/insn-aebr-01.s b/test/MC/SystemZ/insn-aebr-01.s new file mode 100644 index 000000000000..2147627e3896 --- /dev/null +++ b/test/MC/SystemZ/insn-aebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: aebr %f0, %f0 # encoding: [0xb3,0x0a,0x00,0x00] +#CHECK: aebr %f0, %f15 # encoding: [0xb3,0x0a,0x00,0x0f] +#CHECK: aebr %f7, %f8 # encoding: [0xb3,0x0a,0x00,0x78] +#CHECK: aebr %f15, %f0 # encoding: [0xb3,0x0a,0x00,0xf0] + + aebr %f0, %f0 + aebr %f0, %f15 + aebr %f7, %f8 + aebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-afi-01.s b/test/MC/SystemZ/insn-afi-01.s new file mode 100644 index 000000000000..f9a911810ca9 --- /dev/null +++ b/test/MC/SystemZ/insn-afi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: afi %r0, -2147483648 # encoding: [0xc2,0x09,0x80,0x00,0x00,0x00] +#CHECK: afi %r0, -1 # encoding: [0xc2,0x09,0xff,0xff,0xff,0xff] +#CHECK: afi %r0, 0 # encoding: [0xc2,0x09,0x00,0x00,0x00,0x00] +#CHECK: afi %r0, 1 # encoding: [0xc2,0x09,0x00,0x00,0x00,0x01] +#CHECK: afi %r0, 2147483647 # encoding: [0xc2,0x09,0x7f,0xff,0xff,0xff] +#CHECK: afi %r15, 0 # encoding: [0xc2,0xf9,0x00,0x00,0x00,0x00] + + afi %r0, -1 << 31 + afi %r0, -1 + afi %r0, 0 + afi %r0, 1 + afi %r0, (1 << 31) - 1 + afi %r15, 0 diff --git a/test/MC/SystemZ/insn-afi-02.s b/test/MC/SystemZ/insn-afi-02.s new file mode 100644 index 000000000000..f848e196a9a7 --- /dev/null +++ b/test/MC/SystemZ/insn-afi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: afi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: afi %r0, (1 << 31) + + afi %r0, (-1 << 31) - 1 + afi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-ag-01.s b/test/MC/SystemZ/insn-ag-01.s new file mode 100644 index 000000000000..63029d75e452 --- /dev/null +++ b/test/MC/SystemZ/insn-ag-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ag %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x08] +#CHECK: ag %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x08] +#CHECK: ag %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x08] +#CHECK: ag %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x08] +#CHECK: ag %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x08] +#CHECK: ag %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x08] +#CHECK: ag %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x08] +#CHECK: ag %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x08] +#CHECK: ag %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x08] +#CHECK: ag %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x08] + + ag %r0, -524288 + ag %r0, -1 + ag %r0, 0 + ag %r0, 1 + ag %r0, 524287 + ag %r0, 0(%r1) + ag %r0, 0(%r15) + ag %r0, 524287(%r1,%r15) + ag %r0, 524287(%r15,%r1) + ag %r15, 0 diff --git a/test/MC/SystemZ/insn-ag-02.s b/test/MC/SystemZ/insn-ag-02.s new file mode 100644 index 000000000000..59694cd7d5a7 --- /dev/null +++ b/test/MC/SystemZ/insn-ag-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ag %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ag %r0, 524288 + + ag %r0, -524289 + ag %r0, 524288 diff --git a/test/MC/SystemZ/insn-agf-01.s b/test/MC/SystemZ/insn-agf-01.s new file mode 100644 index 000000000000..40a985834200 --- /dev/null +++ b/test/MC/SystemZ/insn-agf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: agf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x18] +#CHECK: agf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x18] +#CHECK: agf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x18] +#CHECK: agf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x18] +#CHECK: agf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x18] +#CHECK: agf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x18] +#CHECK: agf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x18] +#CHECK: agf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x18] +#CHECK: agf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x18] +#CHECK: agf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x18] + + agf %r0, -524288 + agf %r0, -1 + agf %r0, 0 + agf %r0, 1 + agf %r0, 524287 + agf %r0, 0(%r1) + agf %r0, 0(%r15) + agf %r0, 524287(%r1,%r15) + agf %r0, 524287(%r15,%r1) + agf %r15, 0 diff --git a/test/MC/SystemZ/insn-agf-02.s b/test/MC/SystemZ/insn-agf-02.s new file mode 100644 index 000000000000..dee31dc1d547 --- /dev/null +++ b/test/MC/SystemZ/insn-agf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: agf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: agf %r0, 524288 + + agf %r0, -524289 + agf %r0, 524288 diff --git a/test/MC/SystemZ/insn-agfi-01.s b/test/MC/SystemZ/insn-agfi-01.s new file mode 100644 index 000000000000..a64721ddd1d8 --- /dev/null +++ b/test/MC/SystemZ/insn-agfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: agfi %r0, -2147483648 # encoding: [0xc2,0x08,0x80,0x00,0x00,0x00] +#CHECK: agfi %r0, -1 # encoding: [0xc2,0x08,0xff,0xff,0xff,0xff] +#CHECK: agfi %r0, 0 # encoding: [0xc2,0x08,0x00,0x00,0x00,0x00] +#CHECK: agfi %r0, 1 # encoding: [0xc2,0x08,0x00,0x00,0x00,0x01] +#CHECK: agfi %r0, 2147483647 # encoding: [0xc2,0x08,0x7f,0xff,0xff,0xff] +#CHECK: agfi %r15, 0 # encoding: [0xc2,0xf8,0x00,0x00,0x00,0x00] + + agfi %r0, -1 << 31 + agfi %r0, -1 + agfi %r0, 0 + agfi %r0, 1 + agfi %r0, (1 << 31) - 1 + agfi %r15, 0 diff --git a/test/MC/SystemZ/insn-agfi-02.s b/test/MC/SystemZ/insn-agfi-02.s new file mode 100644 index 000000000000..1db3eaae0b6f --- /dev/null +++ b/test/MC/SystemZ/insn-agfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: agfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: agfi %r0, (1 << 31) + + agfi %r0, (-1 << 31) - 1 + agfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-agfr-01.s b/test/MC/SystemZ/insn-agfr-01.s new file mode 100644 index 000000000000..cd17db95f91e --- /dev/null +++ b/test/MC/SystemZ/insn-agfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: agfr %r0, %r0 # encoding: [0xb9,0x18,0x00,0x00] +#CHECK: agfr %r0, %r15 # encoding: [0xb9,0x18,0x00,0x0f] +#CHECK: agfr %r15, %r0 # encoding: [0xb9,0x18,0x00,0xf0] +#CHECK: agfr %r7, %r8 # encoding: [0xb9,0x18,0x00,0x78] + + agfr %r0,%r0 + agfr %r0,%r15 + agfr %r15,%r0 + agfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-aghi-01.s b/test/MC/SystemZ/insn-aghi-01.s new file mode 100644 index 000000000000..cd77c355d241 --- /dev/null +++ b/test/MC/SystemZ/insn-aghi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: aghi %r0, -32768 # encoding: [0xa7,0x0b,0x80,0x00] +#CHECK: aghi %r0, -1 # encoding: [0xa7,0x0b,0xff,0xff] +#CHECK: aghi %r0, 0 # encoding: [0xa7,0x0b,0x00,0x00] +#CHECK: aghi %r0, 1 # encoding: [0xa7,0x0b,0x00,0x01] +#CHECK: aghi %r0, 32767 # encoding: [0xa7,0x0b,0x7f,0xff] +#CHECK: aghi %r15, 0 # encoding: [0xa7,0xfb,0x00,0x00] + + aghi %r0, -32768 + aghi %r0, -1 + aghi %r0, 0 + aghi %r0, 1 + aghi %r0, 32767 + aghi %r15, 0 diff --git a/test/MC/SystemZ/insn-aghi-02.s b/test/MC/SystemZ/insn-aghi-02.s new file mode 100644 index 000000000000..e2657c6869e4 --- /dev/null +++ b/test/MC/SystemZ/insn-aghi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: aghi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: aghi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: aghi %r0, foo + + aghi %r0, -32769 + aghi %r0, 32768 + aghi %r0, foo diff --git a/test/MC/SystemZ/insn-agr-01.s b/test/MC/SystemZ/insn-agr-01.s new file mode 100644 index 000000000000..a84ff3d22620 --- /dev/null +++ b/test/MC/SystemZ/insn-agr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: agr %r0, %r0 # encoding: [0xb9,0x08,0x00,0x00] +#CHECK: agr %r0, %r15 # encoding: [0xb9,0x08,0x00,0x0f] +#CHECK: agr %r15, %r0 # encoding: [0xb9,0x08,0x00,0xf0] +#CHECK: agr %r7, %r8 # encoding: [0xb9,0x08,0x00,0x78] + + agr %r0,%r0 + agr %r0,%r15 + agr %r15,%r0 + agr %r7,%r8 diff --git a/test/MC/SystemZ/insn-agsi-01.s b/test/MC/SystemZ/insn-agsi-01.s new file mode 100644 index 000000000000..9b2fe4b80e81 --- /dev/null +++ b/test/MC/SystemZ/insn-agsi-01.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: agsi -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x7a] +#CHECK: agsi -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x7a] +#CHECK: agsi 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x7a] +#CHECK: agsi 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x7a] +#CHECK: agsi 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x7a] +#CHECK: agsi 0, -128 # encoding: [0xeb,0x80,0x00,0x00,0x00,0x7a] +#CHECK: agsi 0, -1 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x7a] +#CHECK: agsi 0, 1 # encoding: [0xeb,0x01,0x00,0x00,0x00,0x7a] +#CHECK: agsi 0, 127 # encoding: [0xeb,0x7f,0x00,0x00,0x00,0x7a] +#CHECK: agsi 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x7a] +#CHECK: agsi 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x7a] +#CHECK: agsi 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x7a] +#CHECK: agsi 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x7a] + + agsi -524288, 0 + agsi -1, 0 + agsi 0, 0 + agsi 1, 0 + agsi 524287, 0 + agsi 0, -128 + agsi 0, -1 + agsi 0, 1 + agsi 0, 127 + agsi 0(%r1), 42 + agsi 0(%r15), 42 + agsi 524287(%r1), 42 + agsi 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-agsi-02.s b/test/MC/SystemZ/insn-agsi-02.s new file mode 100644 index 000000000000..a4b3d9a8883b --- /dev/null +++ b/test/MC/SystemZ/insn-agsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: agsi -524289, 0 +#CHECK: error: invalid operand +#CHECK: agsi 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: agsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: agsi 0, -129 +#CHECK: error: invalid operand +#CHECK: agsi 0, 128 + + agsi -524289, 0 + agsi 524288, 0 + agsi 0(%r1,%r2), 0 + agsi 0, -129 + agsi 0, 128 diff --git a/test/MC/SystemZ/insn-ah-01.s b/test/MC/SystemZ/insn-ah-01.s new file mode 100644 index 000000000000..35012f0678ed --- /dev/null +++ b/test/MC/SystemZ/insn-ah-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ah %r0, 0 # encoding: [0x4a,0x00,0x00,0x00] +#CHECK: ah %r0, 4095 # encoding: [0x4a,0x00,0x0f,0xff] +#CHECK: ah %r0, 0(%r1) # encoding: [0x4a,0x00,0x10,0x00] +#CHECK: ah %r0, 0(%r15) # encoding: [0x4a,0x00,0xf0,0x00] +#CHECK: ah %r0, 4095(%r1,%r15) # encoding: [0x4a,0x01,0xff,0xff] +#CHECK: ah %r0, 4095(%r15,%r1) # encoding: [0x4a,0x0f,0x1f,0xff] +#CHECK: ah %r15, 0 # encoding: [0x4a,0xf0,0x00,0x00] + + ah %r0, 0 + ah %r0, 4095 + ah %r0, 0(%r1) + ah %r0, 0(%r15) + ah %r0, 4095(%r1,%r15) + ah %r0, 4095(%r15,%r1) + ah %r15, 0 diff --git a/test/MC/SystemZ/insn-ah-02.s b/test/MC/SystemZ/insn-ah-02.s new file mode 100644 index 000000000000..1a20cd715f77 --- /dev/null +++ b/test/MC/SystemZ/insn-ah-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ah %r0, -1 +#CHECK: error: invalid operand +#CHECK: ah %r0, 4096 + + ah %r0, -1 + ah %r0, 4096 diff --git a/test/MC/SystemZ/insn-ahi-01.s b/test/MC/SystemZ/insn-ahi-01.s new file mode 100644 index 000000000000..e0a5fb389e6c --- /dev/null +++ b/test/MC/SystemZ/insn-ahi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ahi %r0, -32768 # encoding: [0xa7,0x0a,0x80,0x00] +#CHECK: ahi %r0, -1 # encoding: [0xa7,0x0a,0xff,0xff] +#CHECK: ahi %r0, 0 # encoding: [0xa7,0x0a,0x00,0x00] +#CHECK: ahi %r0, 1 # encoding: [0xa7,0x0a,0x00,0x01] +#CHECK: ahi %r0, 32767 # encoding: [0xa7,0x0a,0x7f,0xff] +#CHECK: ahi %r15, 0 # encoding: [0xa7,0xfa,0x00,0x00] + + ahi %r0, -32768 + ahi %r0, -1 + ahi %r0, 0 + ahi %r0, 1 + ahi %r0, 32767 + ahi %r15, 0 diff --git a/test/MC/SystemZ/insn-ahi-02.s b/test/MC/SystemZ/insn-ahi-02.s new file mode 100644 index 000000000000..d41e2da2a21b --- /dev/null +++ b/test/MC/SystemZ/insn-ahi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ahi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: ahi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: ahi %r0, foo + + ahi %r0, -32769 + ahi %r0, 32768 + ahi %r0, foo diff --git a/test/MC/SystemZ/insn-ahy-01.s b/test/MC/SystemZ/insn-ahy-01.s new file mode 100644 index 000000000000..ff25dc503c6b --- /dev/null +++ b/test/MC/SystemZ/insn-ahy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ahy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7a] +#CHECK: ahy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7a] +#CHECK: ahy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7a] +#CHECK: ahy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7a] +#CHECK: ahy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7a] +#CHECK: ahy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7a] +#CHECK: ahy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7a] +#CHECK: ahy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x7a] +#CHECK: ahy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x7a] +#CHECK: ahy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x7a] + + ahy %r0, -524288 + ahy %r0, -1 + ahy %r0, 0 + ahy %r0, 1 + ahy %r0, 524287 + ahy %r0, 0(%r1) + ahy %r0, 0(%r15) + ahy %r0, 524287(%r1,%r15) + ahy %r0, 524287(%r15,%r1) + ahy %r15, 0 diff --git a/test/MC/SystemZ/insn-ahy-02.s b/test/MC/SystemZ/insn-ahy-02.s new file mode 100644 index 000000000000..e725e146df56 --- /dev/null +++ b/test/MC/SystemZ/insn-ahy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ahy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ahy %r0, 524288 + + ahy %r0, -524289 + ahy %r0, 524288 diff --git a/test/MC/SystemZ/insn-al-01.s b/test/MC/SystemZ/insn-al-01.s new file mode 100644 index 000000000000..1efc33f0e980 --- /dev/null +++ b/test/MC/SystemZ/insn-al-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: al %r0, 0 # encoding: [0x5e,0x00,0x00,0x00] +#CHECK: al %r0, 4095 # encoding: [0x5e,0x00,0x0f,0xff] +#CHECK: al %r0, 0(%r1) # encoding: [0x5e,0x00,0x10,0x00] +#CHECK: al %r0, 0(%r15) # encoding: [0x5e,0x00,0xf0,0x00] +#CHECK: al %r0, 4095(%r1,%r15) # encoding: [0x5e,0x01,0xff,0xff] +#CHECK: al %r0, 4095(%r15,%r1) # encoding: [0x5e,0x0f,0x1f,0xff] +#CHECK: al %r15, 0 # encoding: [0x5e,0xf0,0x00,0x00] + + al %r0, 0 + al %r0, 4095 + al %r0, 0(%r1) + al %r0, 0(%r15) + al %r0, 4095(%r1,%r15) + al %r0, 4095(%r15,%r1) + al %r15, 0 diff --git a/test/MC/SystemZ/insn-al-02.s b/test/MC/SystemZ/insn-al-02.s new file mode 100644 index 000000000000..39b1b06a1ba2 --- /dev/null +++ b/test/MC/SystemZ/insn-al-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: al %r0, -1 +#CHECK: error: invalid operand +#CHECK: al %r0, 4096 + + al %r0, -1 + al %r0, 4096 diff --git a/test/MC/SystemZ/insn-alc-01.s b/test/MC/SystemZ/insn-alc-01.s new file mode 100644 index 000000000000..5f8be6a7d5af --- /dev/null +++ b/test/MC/SystemZ/insn-alc-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x98] +#CHECK: alc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x98] +#CHECK: alc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x98] +#CHECK: alc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x98] +#CHECK: alc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x98] +#CHECK: alc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x98] +#CHECK: alc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x98] +#CHECK: alc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x98] +#CHECK: alc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x98] +#CHECK: alc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x98] + + alc %r0, -524288 + alc %r0, -1 + alc %r0, 0 + alc %r0, 1 + alc %r0, 524287 + alc %r0, 0(%r1) + alc %r0, 0(%r15) + alc %r0, 524287(%r1,%r15) + alc %r0, 524287(%r15,%r1) + alc %r15, 0 diff --git a/test/MC/SystemZ/insn-alc-02.s b/test/MC/SystemZ/insn-alc-02.s new file mode 100644 index 000000000000..9c082f2dfb7a --- /dev/null +++ b/test/MC/SystemZ/insn-alc-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: alc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: alc %r0, 524288 + + alc %r0, -524289 + alc %r0, 524288 diff --git a/test/MC/SystemZ/insn-alcg-01.s b/test/MC/SystemZ/insn-alcg-01.s new file mode 100644 index 000000000000..c05207ec9e98 --- /dev/null +++ b/test/MC/SystemZ/insn-alcg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alcg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x88] +#CHECK: alcg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x88] +#CHECK: alcg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x88] +#CHECK: alcg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x88] +#CHECK: alcg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x88] +#CHECK: alcg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x88] +#CHECK: alcg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x88] +#CHECK: alcg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x88] +#CHECK: alcg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x88] +#CHECK: alcg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x88] + + alcg %r0, -524288 + alcg %r0, -1 + alcg %r0, 0 + alcg %r0, 1 + alcg %r0, 524287 + alcg %r0, 0(%r1) + alcg %r0, 0(%r15) + alcg %r0, 524287(%r1,%r15) + alcg %r0, 524287(%r15,%r1) + alcg %r15, 0 diff --git a/test/MC/SystemZ/insn-alcg-02.s b/test/MC/SystemZ/insn-alcg-02.s new file mode 100644 index 000000000000..3dab6ddc5dd8 --- /dev/null +++ b/test/MC/SystemZ/insn-alcg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: alcg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: alcg %r0, 524288 + + alcg %r0, -524289 + alcg %r0, 524288 diff --git a/test/MC/SystemZ/insn-alcgr-01.s b/test/MC/SystemZ/insn-alcgr-01.s new file mode 100644 index 000000000000..c9f3ce293418 --- /dev/null +++ b/test/MC/SystemZ/insn-alcgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alcgr %r0, %r0 # encoding: [0xb9,0x88,0x00,0x00] +#CHECK: alcgr %r0, %r15 # encoding: [0xb9,0x88,0x00,0x0f] +#CHECK: alcgr %r15, %r0 # encoding: [0xb9,0x88,0x00,0xf0] +#CHECK: alcgr %r7, %r8 # encoding: [0xb9,0x88,0x00,0x78] + + alcgr %r0,%r0 + alcgr %r0,%r15 + alcgr %r15,%r0 + alcgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-alcr-01.s b/test/MC/SystemZ/insn-alcr-01.s new file mode 100644 index 000000000000..7369224a1bea --- /dev/null +++ b/test/MC/SystemZ/insn-alcr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alcr %r0, %r0 # encoding: [0xb9,0x98,0x00,0x00] +#CHECK: alcr %r0, %r15 # encoding: [0xb9,0x98,0x00,0x0f] +#CHECK: alcr %r15, %r0 # encoding: [0xb9,0x98,0x00,0xf0] +#CHECK: alcr %r7, %r8 # encoding: [0xb9,0x98,0x00,0x78] + + alcr %r0,%r0 + alcr %r0,%r15 + alcr %r15,%r0 + alcr %r7,%r8 diff --git a/test/MC/SystemZ/insn-alfi-01.s b/test/MC/SystemZ/insn-alfi-01.s new file mode 100644 index 000000000000..332a74fdc7aa --- /dev/null +++ b/test/MC/SystemZ/insn-alfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alfi %r0, 0 # encoding: [0xc2,0x0b,0x00,0x00,0x00,0x00] +#CHECK: alfi %r0, 4294967295 # encoding: [0xc2,0x0b,0xff,0xff,0xff,0xff] +#CHECK: alfi %r15, 0 # encoding: [0xc2,0xfb,0x00,0x00,0x00,0x00] + + alfi %r0, 0 + alfi %r0, (1 << 32) - 1 + alfi %r15, 0 diff --git a/test/MC/SystemZ/insn-alfi-02.s b/test/MC/SystemZ/insn-alfi-02.s new file mode 100644 index 000000000000..a5d38942257b --- /dev/null +++ b/test/MC/SystemZ/insn-alfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: alfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: alfi %r0, (1 << 32) + + alfi %r0, -1 + alfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-alg-01.s b/test/MC/SystemZ/insn-alg-01.s new file mode 100644 index 000000000000..6df084c02b2f --- /dev/null +++ b/test/MC/SystemZ/insn-alg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0a] +#CHECK: alg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0a] +#CHECK: alg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0a] +#CHECK: alg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0a] +#CHECK: alg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0a] +#CHECK: alg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0a] +#CHECK: alg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0a] +#CHECK: alg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0a] +#CHECK: alg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0a] +#CHECK: alg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0a] + + alg %r0, -524288 + alg %r0, -1 + alg %r0, 0 + alg %r0, 1 + alg %r0, 524287 + alg %r0, 0(%r1) + alg %r0, 0(%r15) + alg %r0, 524287(%r1,%r15) + alg %r0, 524287(%r15,%r1) + alg %r15, 0 diff --git a/test/MC/SystemZ/insn-alg-02.s b/test/MC/SystemZ/insn-alg-02.s new file mode 100644 index 000000000000..407d73d2bd57 --- /dev/null +++ b/test/MC/SystemZ/insn-alg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: alg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: alg %r0, 524288 + + alg %r0, -524289 + alg %r0, 524288 diff --git a/test/MC/SystemZ/insn-algf-01.s b/test/MC/SystemZ/insn-algf-01.s new file mode 100644 index 000000000000..751b59059f10 --- /dev/null +++ b/test/MC/SystemZ/insn-algf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: algf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1a] +#CHECK: algf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1a] +#CHECK: algf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1a] +#CHECK: algf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1a] +#CHECK: algf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1a] +#CHECK: algf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1a] +#CHECK: algf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1a] +#CHECK: algf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x1a] +#CHECK: algf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x1a] +#CHECK: algf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x1a] + + algf %r0, -524288 + algf %r0, -1 + algf %r0, 0 + algf %r0, 1 + algf %r0, 524287 + algf %r0, 0(%r1) + algf %r0, 0(%r15) + algf %r0, 524287(%r1,%r15) + algf %r0, 524287(%r15,%r1) + algf %r15, 0 diff --git a/test/MC/SystemZ/insn-algf-02.s b/test/MC/SystemZ/insn-algf-02.s new file mode 100644 index 000000000000..64ef1c975b7b --- /dev/null +++ b/test/MC/SystemZ/insn-algf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: algf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: algf %r0, 524288 + + algf %r0, -524289 + algf %r0, 524288 diff --git a/test/MC/SystemZ/insn-algfi-01.s b/test/MC/SystemZ/insn-algfi-01.s new file mode 100644 index 000000000000..b6ccb336b3b8 --- /dev/null +++ b/test/MC/SystemZ/insn-algfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: algfi %r0, 0 # encoding: [0xc2,0x0a,0x00,0x00,0x00,0x00] +#CHECK: algfi %r0, 4294967295 # encoding: [0xc2,0x0a,0xff,0xff,0xff,0xff] +#CHECK: algfi %r15, 0 # encoding: [0xc2,0xfa,0x00,0x00,0x00,0x00] + + algfi %r0, 0 + algfi %r0, (1 << 32) - 1 + algfi %r15, 0 diff --git a/test/MC/SystemZ/insn-algfi-02.s b/test/MC/SystemZ/insn-algfi-02.s new file mode 100644 index 000000000000..a5ed4b04e55b --- /dev/null +++ b/test/MC/SystemZ/insn-algfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: algfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: algfi %r0, (1 << 32) + + algfi %r0, -1 + algfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-algfr-01.s b/test/MC/SystemZ/insn-algfr-01.s new file mode 100644 index 000000000000..3ccb692ab947 --- /dev/null +++ b/test/MC/SystemZ/insn-algfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: algfr %r0, %r0 # encoding: [0xb9,0x1a,0x00,0x00] +#CHECK: algfr %r0, %r15 # encoding: [0xb9,0x1a,0x00,0x0f] +#CHECK: algfr %r15, %r0 # encoding: [0xb9,0x1a,0x00,0xf0] +#CHECK: algfr %r7, %r8 # encoding: [0xb9,0x1a,0x00,0x78] + + algfr %r0,%r0 + algfr %r0,%r15 + algfr %r15,%r0 + algfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-algr-01.s b/test/MC/SystemZ/insn-algr-01.s new file mode 100644 index 000000000000..c3758ee74df4 --- /dev/null +++ b/test/MC/SystemZ/insn-algr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: algr %r0, %r0 # encoding: [0xb9,0x0a,0x00,0x00] +#CHECK: algr %r0, %r15 # encoding: [0xb9,0x0a,0x00,0x0f] +#CHECK: algr %r15, %r0 # encoding: [0xb9,0x0a,0x00,0xf0] +#CHECK: algr %r7, %r8 # encoding: [0xb9,0x0a,0x00,0x78] + + algr %r0,%r0 + algr %r0,%r15 + algr %r15,%r0 + algr %r7,%r8 diff --git a/test/MC/SystemZ/insn-alr-01.s b/test/MC/SystemZ/insn-alr-01.s new file mode 100644 index 000000000000..e85173ef151c --- /dev/null +++ b/test/MC/SystemZ/insn-alr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: alr %r0, %r0 # encoding: [0x1e,0x00] +#CHECK: alr %r0, %r15 # encoding: [0x1e,0x0f] +#CHECK: alr %r15, %r0 # encoding: [0x1e,0xf0] +#CHECK: alr %r7, %r8 # encoding: [0x1e,0x78] + + alr %r0,%r0 + alr %r0,%r15 + alr %r15,%r0 + alr %r7,%r8 diff --git a/test/MC/SystemZ/insn-aly-01.s b/test/MC/SystemZ/insn-aly-01.s new file mode 100644 index 000000000000..94afb07578f4 --- /dev/null +++ b/test/MC/SystemZ/insn-aly-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: aly %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5e] +#CHECK: aly %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5e] +#CHECK: aly %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5e] +#CHECK: aly %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x5e] +#CHECK: aly %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x5e] +#CHECK: aly %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x5e] +#CHECK: aly %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x5e] +#CHECK: aly %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x5e] +#CHECK: aly %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x5e] +#CHECK: aly %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x5e] + + aly %r0, -524288 + aly %r0, -1 + aly %r0, 0 + aly %r0, 1 + aly %r0, 524287 + aly %r0, 0(%r1) + aly %r0, 0(%r15) + aly %r0, 524287(%r1,%r15) + aly %r0, 524287(%r15,%r1) + aly %r15, 0 diff --git a/test/MC/SystemZ/insn-aly-02.s b/test/MC/SystemZ/insn-aly-02.s new file mode 100644 index 000000000000..01c6f3dcdd19 --- /dev/null +++ b/test/MC/SystemZ/insn-aly-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: aly %r0, -524289 +#CHECK: error: invalid operand +#CHECK: aly %r0, 524288 + + aly %r0, -524289 + aly %r0, 524288 diff --git a/test/MC/SystemZ/insn-ar-01.s b/test/MC/SystemZ/insn-ar-01.s new file mode 100644 index 000000000000..7cd627a17021 --- /dev/null +++ b/test/MC/SystemZ/insn-ar-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ar %r0, %r0 # encoding: [0x1a,0x00] +#CHECK: ar %r0, %r15 # encoding: [0x1a,0x0f] +#CHECK: ar %r15, %r0 # encoding: [0x1a,0xf0] +#CHECK: ar %r7, %r8 # encoding: [0x1a,0x78] + + ar %r0,%r0 + ar %r0,%r15 + ar %r15,%r0 + ar %r7,%r8 diff --git a/test/MC/SystemZ/insn-asi-01.s b/test/MC/SystemZ/insn-asi-01.s new file mode 100644 index 000000000000..7a1d241e2356 --- /dev/null +++ b/test/MC/SystemZ/insn-asi-01.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: asi -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x6a] +#CHECK: asi -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x6a] +#CHECK: asi 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x6a] +#CHECK: asi 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x6a] +#CHECK: asi 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x6a] +#CHECK: asi 0, -128 # encoding: [0xeb,0x80,0x00,0x00,0x00,0x6a] +#CHECK: asi 0, -1 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x6a] +#CHECK: asi 0, 1 # encoding: [0xeb,0x01,0x00,0x00,0x00,0x6a] +#CHECK: asi 0, 127 # encoding: [0xeb,0x7f,0x00,0x00,0x00,0x6a] +#CHECK: asi 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x6a] +#CHECK: asi 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x6a] +#CHECK: asi 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x6a] +#CHECK: asi 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x6a] + + asi -524288, 0 + asi -1, 0 + asi 0, 0 + asi 1, 0 + asi 524287, 0 + asi 0, -128 + asi 0, -1 + asi 0, 1 + asi 0, 127 + asi 0(%r1), 42 + asi 0(%r15), 42 + asi 524287(%r1), 42 + asi 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-asi-02.s b/test/MC/SystemZ/insn-asi-02.s new file mode 100644 index 000000000000..3c09f9050382 --- /dev/null +++ b/test/MC/SystemZ/insn-asi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: asi -524289, 0 +#CHECK: error: invalid operand +#CHECK: asi 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: asi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: asi 0, -129 +#CHECK: error: invalid operand +#CHECK: asi 0, 128 + + asi -524289, 0 + asi 524288, 0 + asi 0(%r1,%r2), 0 + asi 0, -129 + asi 0, 128 diff --git a/test/MC/SystemZ/insn-axbr-01.s b/test/MC/SystemZ/insn-axbr-01.s new file mode 100644 index 000000000000..cb592efba6a5 --- /dev/null +++ b/test/MC/SystemZ/insn-axbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: axbr %f0, %f0 # encoding: [0xb3,0x4a,0x00,0x00] +#CHECK: axbr %f0, %f13 # encoding: [0xb3,0x4a,0x00,0x0d] +#CHECK: axbr %f8, %f8 # encoding: [0xb3,0x4a,0x00,0x88] +#CHECK: axbr %f13, %f0 # encoding: [0xb3,0x4a,0x00,0xd0] + + axbr %f0, %f0 + axbr %f0, %f13 + axbr %f8, %f8 + axbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-axbr-02.s b/test/MC/SystemZ/insn-axbr-02.s new file mode 100644 index 000000000000..307664d51e53 --- /dev/null +++ b/test/MC/SystemZ/insn-axbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: axbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: axbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: axbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: axbr %f14, %f0 + + axbr %f0, %f2 + axbr %f0, %f14 + axbr %f2, %f0 + axbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-ay-01.s b/test/MC/SystemZ/insn-ay-01.s new file mode 100644 index 000000000000..3b65c9a7c0e8 --- /dev/null +++ b/test/MC/SystemZ/insn-ay-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ay %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5a] +#CHECK: ay %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5a] +#CHECK: ay %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5a] +#CHECK: ay %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x5a] +#CHECK: ay %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x5a] +#CHECK: ay %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x5a] +#CHECK: ay %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x5a] +#CHECK: ay %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x5a] +#CHECK: ay %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x5a] +#CHECK: ay %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x5a] + + ay %r0, -524288 + ay %r0, -1 + ay %r0, 0 + ay %r0, 1 + ay %r0, 524287 + ay %r0, 0(%r1) + ay %r0, 0(%r15) + ay %r0, 524287(%r1,%r15) + ay %r0, 524287(%r15,%r1) + ay %r15, 0 diff --git a/test/MC/SystemZ/insn-ay-02.s b/test/MC/SystemZ/insn-ay-02.s new file mode 100644 index 000000000000..09704dfb9f4a --- /dev/null +++ b/test/MC/SystemZ/insn-ay-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ay %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ay %r0, 524288 + + ay %r0, -524289 + ay %r0, 524288 diff --git a/test/MC/SystemZ/insn-basr-01.s b/test/MC/SystemZ/insn-basr-01.s new file mode 100644 index 000000000000..a66cee8f6352 --- /dev/null +++ b/test/MC/SystemZ/insn-basr-01.s @@ -0,0 +1,12 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: basr %r0, %r1 # encoding: [0x0d,0x01] +#CHECK: basr %r0, %r15 # encoding: [0x0d,0x0f] +#CHECK: basr %r14, %r9 # encoding: [0x0d,0xe9] +#CHECK: basr %r15, %r1 # encoding: [0x0d,0xf1] + + basr %r0,%r1 + basr %r0,%r15 + basr %r14,%r9 + basr %r15,%r1 + diff --git a/test/MC/SystemZ/insn-br-01.s b/test/MC/SystemZ/insn-br-01.s new file mode 100644 index 000000000000..8e2f2aac78a5 --- /dev/null +++ b/test/MC/SystemZ/insn-br-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: br %r1 # encoding: [0x07,0xf1] +#CHECK: br %r14 # encoding: [0x07,0xfe] +#CHECK: br %r15 # encoding: [0x07,0xff] + + br %r1 + br %r14 + br %r15 diff --git a/test/MC/SystemZ/insn-bras-01.s b/test/MC/SystemZ/insn-bras-01.s new file mode 100644 index 000000000000..89f7f77477dd --- /dev/null +++ b/test/MC/SystemZ/insn-bras-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: bras %r0, foo # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: bras %r14, foo # encoding: [0xa7,0xe5,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: bras %r15, foo # encoding: [0xa7,0xf5,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + bras %r0,foo + bras %r14,foo + bras %r15,foo + +#CHECK: bras %r0, bar+100 # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: bras %r14, bar+100 # encoding: [0xa7,0xe5,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: bras %r15, bar+100 # encoding: [0xa7,0xf5,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + bras %r0,bar+100 + bras %r14,bar+100 + bras %r15,bar+100 + +#CHECK: bras %r0, bar@PLT # encoding: [0xa7,0x05,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: bras %r14, bar@PLT # encoding: [0xa7,0xe5,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: bras %r15, bar@PLT # encoding: [0xa7,0xf5,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + bras %r0,bar@PLT + bras %r14,bar@PLT + bras %r15,bar@PLT diff --git a/test/MC/SystemZ/insn-brasl-01.s b/test/MC/SystemZ/insn-brasl-01.s new file mode 100644 index 000000000000..86d0ced9b33d --- /dev/null +++ b/test/MC/SystemZ/insn-brasl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: brasl %r0, foo # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: brasl %r14, foo # encoding: [0xc0,0xe5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: brasl %r15, foo # encoding: [0xc0,0xf5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brasl %r0,foo + brasl %r14,foo + brasl %r15,foo + +#CHECK: brasl %r0, bar+100 # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: brasl %r14, bar+100 # encoding: [0xc0,0xe5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: brasl %r15, bar+100 # encoding: [0xc0,0xf5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + brasl %r0,bar+100 + brasl %r14,bar+100 + brasl %r15,bar+100 + +#CHECK: brasl %r0, bar@PLT # encoding: [0xc0,0x05,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL +#CHECK: brasl %r14, bar@PLT # encoding: [0xc0,0xe5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL +#CHECK: brasl %r15, bar@PLT # encoding: [0xc0,0xf5,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + brasl %r0,bar@PLT + brasl %r14,bar@PLT + brasl %r15,bar@PLT diff --git a/test/MC/SystemZ/insn-brc-01.s b/test/MC/SystemZ/insn-brc-01.s new file mode 100644 index 000000000000..a92ea45ecfcc --- /dev/null +++ b/test/MC/SystemZ/insn-brc-01.s @@ -0,0 +1,238 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: brc 0, foo # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 0, foo + +#CHECK: brc 1, foo # encoding: [0xa7,0x14,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jo foo # encoding: [0xa7,0x14,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 1, foo + jo foo + +#CHECK: brc 2, foo # encoding: [0xa7,0x24,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jh foo # encoding: [0xa7,0x24,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 2, foo + jh foo + +#CHECK: brc 3, foo # encoding: [0xa7,0x34,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jnle foo # encoding: [0xa7,0x34,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 3, foo + jnle foo + +#CHECK: brc 4, foo # encoding: [0xa7,0x44,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jl foo # encoding: [0xa7,0x44,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 4, foo + jl foo + +#CHECK: brc 5, foo # encoding: [0xa7,0x54,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jnhe foo # encoding: [0xa7,0x54,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 5, foo + jnhe foo + +#CHECK: brc 6, foo # encoding: [0xa7,0x64,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jlh foo # encoding: [0xa7,0x64,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 6, foo + jlh foo + +#CHECK: brc 7, foo # encoding: [0xa7,0x74,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jne foo # encoding: [0xa7,0x74,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 7, foo + jne foo + +#CHECK: brc 8, foo # encoding: [0xa7,0x84,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: je foo # encoding: [0xa7,0x84,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 8, foo + je foo + +#CHECK: brc 9, foo # encoding: [0xa7,0x94,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jnlh foo # encoding: [0xa7,0x94,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 9, foo + jnlh foo + +#CHECK: brc 10, foo # encoding: [0xa7,0xa4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jhe foo # encoding: [0xa7,0xa4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 10, foo + jhe foo + +#CHECK: brc 11, foo # encoding: [0xa7,0xb4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jnl foo # encoding: [0xa7,0xb4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 11, foo + jnl foo + +#CHECK: brc 12, foo # encoding: [0xa7,0xc4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jle foo # encoding: [0xa7,0xc4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 12, foo + jle foo + +#CHECK: brc 13, foo # encoding: [0xa7,0xd4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jnh foo # encoding: [0xa7,0xd4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 13, foo + jnh foo + +#CHECK: brc 14, foo # encoding: [0xa7,0xe4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: jno foo # encoding: [0xa7,0xe4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 14, foo + jno foo + +#CHECK: brc 15, foo # encoding: [0xa7,0xf4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: j foo # encoding: [0xa7,0xf4,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brc 15, foo + j foo + +#CHECK: brc 0, bar+100 # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + brc 0, bar+100 + +#CHECK: jo bar+100 # encoding: [0xa7,0x14,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jo bar+100 + +#CHECK: jh bar+100 # encoding: [0xa7,0x24,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jh bar+100 + +#CHECK: jnle bar+100 # encoding: [0xa7,0x34,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jnle bar+100 + +#CHECK: jl bar+100 # encoding: [0xa7,0x44,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jl bar+100 + +#CHECK: jnhe bar+100 # encoding: [0xa7,0x54,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jnhe bar+100 + +#CHECK: jlh bar+100 # encoding: [0xa7,0x64,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jlh bar+100 + +#CHECK: jne bar+100 # encoding: [0xa7,0x74,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jne bar+100 + +#CHECK: je bar+100 # encoding: [0xa7,0x84,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + je bar+100 + +#CHECK: jnlh bar+100 # encoding: [0xa7,0x94,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jnlh bar+100 + +#CHECK: jhe bar+100 # encoding: [0xa7,0xa4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jhe bar+100 + +#CHECK: jnl bar+100 # encoding: [0xa7,0xb4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jnl bar+100 + +#CHECK: jle bar+100 # encoding: [0xa7,0xc4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jle bar+100 + +#CHECK: jnh bar+100 # encoding: [0xa7,0xd4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jnh bar+100 + +#CHECK: jno bar+100 # encoding: [0xa7,0xe4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + jno bar+100 + +#CHECK: j bar+100 # encoding: [0xa7,0xf4,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + j bar+100 + +#CHECK: brc 0, bar@PLT # encoding: [0xa7,0x04,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + brc 0, bar@PLT + +#CHECK: jo bar@PLT # encoding: [0xa7,0x14,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jo bar@PLT + +#CHECK: jh bar@PLT # encoding: [0xa7,0x24,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jh bar@PLT + +#CHECK: jnle bar@PLT # encoding: [0xa7,0x34,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jnle bar@PLT + +#CHECK: jl bar@PLT # encoding: [0xa7,0x44,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jl bar@PLT + +#CHECK: jnhe bar@PLT # encoding: [0xa7,0x54,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jnhe bar@PLT + +#CHECK: jlh bar@PLT # encoding: [0xa7,0x64,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jlh bar@PLT + +#CHECK: jne bar@PLT # encoding: [0xa7,0x74,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jne bar@PLT + +#CHECK: je bar@PLT # encoding: [0xa7,0x84,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + je bar@PLT + +#CHECK: jnlh bar@PLT # encoding: [0xa7,0x94,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jnlh bar@PLT + +#CHECK: jhe bar@PLT # encoding: [0xa7,0xa4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jhe bar@PLT + +#CHECK: jnl bar@PLT # encoding: [0xa7,0xb4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jnl bar@PLT + +#CHECK: jle bar@PLT # encoding: [0xa7,0xc4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jle bar@PLT + +#CHECK: jnh bar@PLT # encoding: [0xa7,0xd4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jnh bar@PLT + +#CHECK: jno bar@PLT # encoding: [0xa7,0xe4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + jno bar@PLT + +#CHECK: j bar@PLT # encoding: [0xa7,0xf4,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + j bar@PLT diff --git a/test/MC/SystemZ/insn-brc-02.s b/test/MC/SystemZ/insn-brc-02.s new file mode 100644 index 000000000000..941cc459f38a --- /dev/null +++ b/test/MC/SystemZ/insn-brc-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: brc foo, bar +#CHECK: error: invalid operand +#CHECK: brc -1, bar +#CHECK: error: invalid operand +#CHECK: brc 16, bar + + brc foo, bar + brc -1, bar + brc 16, bar diff --git a/test/MC/SystemZ/insn-brcl-01.s b/test/MC/SystemZ/insn-brcl-01.s new file mode 100644 index 000000000000..f7138bf5be39 --- /dev/null +++ b/test/MC/SystemZ/insn-brcl-01.s @@ -0,0 +1,238 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: brcl 0, foo # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 0, foo + +#CHECK: brcl 1, foo # encoding: [0xc0,0x14,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgo foo # encoding: [0xc0,0x14,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 1, foo + jgo foo + +#CHECK: brcl 2, foo # encoding: [0xc0,0x24,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgh foo # encoding: [0xc0,0x24,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 2, foo + jgh foo + +#CHECK: brcl 3, foo # encoding: [0xc0,0x34,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgnle foo # encoding: [0xc0,0x34,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 3, foo + jgnle foo + +#CHECK: brcl 4, foo # encoding: [0xc0,0x44,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgl foo # encoding: [0xc0,0x44,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 4, foo + jgl foo + +#CHECK: brcl 5, foo # encoding: [0xc0,0x54,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgnhe foo # encoding: [0xc0,0x54,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 5, foo + jgnhe foo + +#CHECK: brcl 6, foo # encoding: [0xc0,0x64,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jglh foo # encoding: [0xc0,0x64,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 6, foo + jglh foo + +#CHECK: brcl 7, foo # encoding: [0xc0,0x74,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgne foo # encoding: [0xc0,0x74,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 7, foo + jgne foo + +#CHECK: brcl 8, foo # encoding: [0xc0,0x84,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jge foo # encoding: [0xc0,0x84,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 8, foo + jge foo + +#CHECK: brcl 9, foo # encoding: [0xc0,0x94,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgnlh foo # encoding: [0xc0,0x94,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 9, foo + jgnlh foo + +#CHECK: brcl 10, foo # encoding: [0xc0,0xa4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jghe foo # encoding: [0xc0,0xa4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 10, foo + jghe foo + +#CHECK: brcl 11, foo # encoding: [0xc0,0xb4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgnl foo # encoding: [0xc0,0xb4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 11, foo + jgnl foo + +#CHECK: brcl 12, foo # encoding: [0xc0,0xc4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgle foo # encoding: [0xc0,0xc4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 12, foo + jgle foo + +#CHECK: brcl 13, foo # encoding: [0xc0,0xd4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgnh foo # encoding: [0xc0,0xd4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 13, foo + jgnh foo + +#CHECK: brcl 14, foo # encoding: [0xc0,0xe4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jgno foo # encoding: [0xc0,0xe4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 14, foo + jgno foo + +#CHECK: brcl 15, foo # encoding: [0xc0,0xf4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: jg foo # encoding: [0xc0,0xf4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + brcl 15, foo + jg foo + +#CHECK: brcl 0, bar+100 # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + brcl 0, bar+100 + +#CHECK: jgo bar+100 # encoding: [0xc0,0x14,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgo bar+100 + +#CHECK: jgh bar+100 # encoding: [0xc0,0x24,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgh bar+100 + +#CHECK: jgnle bar+100 # encoding: [0xc0,0x34,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgnle bar+100 + +#CHECK: jgl bar+100 # encoding: [0xc0,0x44,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgl bar+100 + +#CHECK: jgnhe bar+100 # encoding: [0xc0,0x54,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgnhe bar+100 + +#CHECK: jglh bar+100 # encoding: [0xc0,0x64,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jglh bar+100 + +#CHECK: jgne bar+100 # encoding: [0xc0,0x74,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgne bar+100 + +#CHECK: jge bar+100 # encoding: [0xc0,0x84,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jge bar+100 + +#CHECK: jgnlh bar+100 # encoding: [0xc0,0x94,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgnlh bar+100 + +#CHECK: jghe bar+100 # encoding: [0xc0,0xa4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jghe bar+100 + +#CHECK: jgnl bar+100 # encoding: [0xc0,0xb4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgnl bar+100 + +#CHECK: jgle bar+100 # encoding: [0xc0,0xc4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgle bar+100 + +#CHECK: jgnh bar+100 # encoding: [0xc0,0xd4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgnh bar+100 + +#CHECK: jgno bar+100 # encoding: [0xc0,0xe4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jgno bar+100 + +#CHECK: jg bar+100 # encoding: [0xc0,0xf4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + jg bar+100 + +#CHECK: brcl 0, bar@PLT # encoding: [0xc0,0x04,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + brcl 0, bar@PLT + +#CHECK: jgo bar@PLT # encoding: [0xc0,0x14,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgo bar@PLT + +#CHECK: jgh bar@PLT # encoding: [0xc0,0x24,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgh bar@PLT + +#CHECK: jgnle bar@PLT # encoding: [0xc0,0x34,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgnle bar@PLT + +#CHECK: jgl bar@PLT # encoding: [0xc0,0x44,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgl bar@PLT + +#CHECK: jgnhe bar@PLT # encoding: [0xc0,0x54,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgnhe bar@PLT + +#CHECK: jglh bar@PLT # encoding: [0xc0,0x64,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jglh bar@PLT + +#CHECK: jgne bar@PLT # encoding: [0xc0,0x74,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgne bar@PLT + +#CHECK: jge bar@PLT # encoding: [0xc0,0x84,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jge bar@PLT + +#CHECK: jgnlh bar@PLT # encoding: [0xc0,0x94,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgnlh bar@PLT + +#CHECK: jghe bar@PLT # encoding: [0xc0,0xa4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jghe bar@PLT + +#CHECK: jgnl bar@PLT # encoding: [0xc0,0xb4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgnl bar@PLT + +#CHECK: jgle bar@PLT # encoding: [0xc0,0xc4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgle bar@PLT + +#CHECK: jgnh bar@PLT # encoding: [0xc0,0xd4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgnh bar@PLT + +#CHECK: jgno bar@PLT # encoding: [0xc0,0xe4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jgno bar@PLT + +#CHECK: jg bar@PLT # encoding: [0xc0,0xf4,A,A,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC32DBL + jg bar@PLT diff --git a/test/MC/SystemZ/insn-brcl-02.s b/test/MC/SystemZ/insn-brcl-02.s new file mode 100644 index 000000000000..ded5f7e4a6e1 --- /dev/null +++ b/test/MC/SystemZ/insn-brcl-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: brcl foo, bar +#CHECK: error: invalid operand +#CHECK: brcl -1, bar +#CHECK: error: invalid operand +#CHECK: brcl 16, bar + + brcl foo, bar + brcl -1, bar + brcl 16, bar diff --git a/test/MC/SystemZ/insn-c-01.s b/test/MC/SystemZ/insn-c-01.s new file mode 100644 index 000000000000..e8a8ada30d89 --- /dev/null +++ b/test/MC/SystemZ/insn-c-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: c %r0, 0 # encoding: [0x59,0x00,0x00,0x00] +#CHECK: c %r0, 4095 # encoding: [0x59,0x00,0x0f,0xff] +#CHECK: c %r0, 0(%r1) # encoding: [0x59,0x00,0x10,0x00] +#CHECK: c %r0, 0(%r15) # encoding: [0x59,0x00,0xf0,0x00] +#CHECK: c %r0, 4095(%r1,%r15) # encoding: [0x59,0x01,0xff,0xff] +#CHECK: c %r0, 4095(%r15,%r1) # encoding: [0x59,0x0f,0x1f,0xff] +#CHECK: c %r15, 0 # encoding: [0x59,0xf0,0x00,0x00] + + c %r0, 0 + c %r0, 4095 + c %r0, 0(%r1) + c %r0, 0(%r15) + c %r0, 4095(%r1,%r15) + c %r0, 4095(%r15,%r1) + c %r15, 0 diff --git a/test/MC/SystemZ/insn-c-02.s b/test/MC/SystemZ/insn-c-02.s new file mode 100644 index 000000000000..81fe25181968 --- /dev/null +++ b/test/MC/SystemZ/insn-c-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: c %r0, -1 +#CHECK: error: invalid operand +#CHECK: c %r0, 4096 + + c %r0, -1 + c %r0, 4096 diff --git a/test/MC/SystemZ/insn-cdb-01.s b/test/MC/SystemZ/insn-cdb-01.s new file mode 100644 index 000000000000..7f6bb59956cb --- /dev/null +++ b/test/MC/SystemZ/insn-cdb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x19] +#CHECK: cdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x19] +#CHECK: cdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x19] +#CHECK: cdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x19] +#CHECK: cdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x19] +#CHECK: cdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x19] +#CHECK: cdb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x19] + + cdb %f0, 0 + cdb %f0, 4095 + cdb %f0, 0(%r1) + cdb %f0, 0(%r15) + cdb %f0, 4095(%r1,%r15) + cdb %f0, 4095(%r15,%r1) + cdb %f15, 0 diff --git a/test/MC/SystemZ/insn-cdb-02.s b/test/MC/SystemZ/insn-cdb-02.s new file mode 100644 index 000000000000..5f02b84c1496 --- /dev/null +++ b/test/MC/SystemZ/insn-cdb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: cdb %f0, 4096 + + cdb %f0, -1 + cdb %f0, 4096 diff --git a/test/MC/SystemZ/insn-cdbr-01.s b/test/MC/SystemZ/insn-cdbr-01.s new file mode 100644 index 000000000000..d2acfc01a256 --- /dev/null +++ b/test/MC/SystemZ/insn-cdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cdbr %f0, %f0 # encoding: [0xb3,0x19,0x00,0x00] +#CHECK: cdbr %f0, %f15 # encoding: [0xb3,0x19,0x00,0x0f] +#CHECK: cdbr %f7, %f8 # encoding: [0xb3,0x19,0x00,0x78] +#CHECK: cdbr %f15, %f0 # encoding: [0xb3,0x19,0x00,0xf0] + + cdbr %f0, %f0 + cdbr %f0, %f15 + cdbr %f7, %f8 + cdbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-cdfbr-01.s b/test/MC/SystemZ/insn-cdfbr-01.s new file mode 100644 index 000000000000..94c9b0779c76 --- /dev/null +++ b/test/MC/SystemZ/insn-cdfbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cdfbr %f0, %r0 # encoding: [0xb3,0x95,0x00,0x00] +#CHECK: cdfbr %f0, %r15 # encoding: [0xb3,0x95,0x00,0x0f] +#CHECK: cdfbr %f15, %r0 # encoding: [0xb3,0x95,0x00,0xf0] +#CHECK: cdfbr %f7, %r8 # encoding: [0xb3,0x95,0x00,0x78] +#CHECK: cdfbr %f15, %r15 # encoding: [0xb3,0x95,0x00,0xff] + + cdfbr %f0, %r0 + cdfbr %f0, %r15 + cdfbr %f15, %r0 + cdfbr %f7, %r8 + cdfbr %f15, %r15 diff --git a/test/MC/SystemZ/insn-cdfbr-02.s b/test/MC/SystemZ/insn-cdfbr-02.s new file mode 100644 index 000000000000..14caa1e3c0d8 --- /dev/null +++ b/test/MC/SystemZ/insn-cdfbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cdfbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cdfbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cdfbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cdfbr %a0, %r0 + + cdfbr %r0, %r0 + cdfbr %f0, %f0 + cdfbr %f0, %a0 + cdfbr %a0, %r0 diff --git a/test/MC/SystemZ/insn-cdgbr-01.s b/test/MC/SystemZ/insn-cdgbr-01.s new file mode 100644 index 000000000000..6a994af744e9 --- /dev/null +++ b/test/MC/SystemZ/insn-cdgbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cdgbr %f0, %r0 # encoding: [0xb3,0xa5,0x00,0x00] +#CHECK: cdgbr %f0, %r15 # encoding: [0xb3,0xa5,0x00,0x0f] +#CHECK: cdgbr %f15, %r0 # encoding: [0xb3,0xa5,0x00,0xf0] +#CHECK: cdgbr %f7, %r8 # encoding: [0xb3,0xa5,0x00,0x78] +#CHECK: cdgbr %f15, %r15 # encoding: [0xb3,0xa5,0x00,0xff] + + cdgbr %f0, %r0 + cdgbr %f0, %r15 + cdgbr %f15, %r0 + cdgbr %f7, %r8 + cdgbr %f15, %r15 diff --git a/test/MC/SystemZ/insn-cdgbr-02.s b/test/MC/SystemZ/insn-cdgbr-02.s new file mode 100644 index 000000000000..8fa9d4fa5c28 --- /dev/null +++ b/test/MC/SystemZ/insn-cdgbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cdgbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cdgbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cdgbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cdgbr %a0, %r0 + + cdgbr %r0, %r0 + cdgbr %f0, %f0 + cdgbr %f0, %a0 + cdgbr %a0, %r0 diff --git a/test/MC/SystemZ/insn-ceb-01.s b/test/MC/SystemZ/insn-ceb-01.s new file mode 100644 index 000000000000..d576e9d572df --- /dev/null +++ b/test/MC/SystemZ/insn-ceb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ceb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x09] +#CHECK: ceb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x09] +#CHECK: ceb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x09] +#CHECK: ceb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x09] +#CHECK: ceb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x09] +#CHECK: ceb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x09] +#CHECK: ceb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x09] + + ceb %f0, 0 + ceb %f0, 4095 + ceb %f0, 0(%r1) + ceb %f0, 0(%r15) + ceb %f0, 4095(%r1,%r15) + ceb %f0, 4095(%r15,%r1) + ceb %f15, 0 diff --git a/test/MC/SystemZ/insn-ceb-02.s b/test/MC/SystemZ/insn-ceb-02.s new file mode 100644 index 000000000000..90829dbe12f5 --- /dev/null +++ b/test/MC/SystemZ/insn-ceb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ceb %f0, -1 +#CHECK: error: invalid operand +#CHECK: ceb %f0, 4096 + + ceb %f0, -1 + ceb %f0, 4096 diff --git a/test/MC/SystemZ/insn-cebr-01.s b/test/MC/SystemZ/insn-cebr-01.s new file mode 100644 index 000000000000..b820e3901a67 --- /dev/null +++ b/test/MC/SystemZ/insn-cebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cebr %f0, %f0 # encoding: [0xb3,0x09,0x00,0x00] +#CHECK: cebr %f0, %f15 # encoding: [0xb3,0x09,0x00,0x0f] +#CHECK: cebr %f7, %f8 # encoding: [0xb3,0x09,0x00,0x78] +#CHECK: cebr %f15, %f0 # encoding: [0xb3,0x09,0x00,0xf0] + + cebr %f0, %f0 + cebr %f0, %f15 + cebr %f7, %f8 + cebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-cefbr-01.s b/test/MC/SystemZ/insn-cefbr-01.s new file mode 100644 index 000000000000..f1068f506c58 --- /dev/null +++ b/test/MC/SystemZ/insn-cefbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cefbr %f0, %r0 # encoding: [0xb3,0x94,0x00,0x00] +#CHECK: cefbr %f0, %r15 # encoding: [0xb3,0x94,0x00,0x0f] +#CHECK: cefbr %f15, %r0 # encoding: [0xb3,0x94,0x00,0xf0] +#CHECK: cefbr %f7, %r8 # encoding: [0xb3,0x94,0x00,0x78] +#CHECK: cefbr %f15, %r15 # encoding: [0xb3,0x94,0x00,0xff] + + cefbr %f0, %r0 + cefbr %f0, %r15 + cefbr %f15, %r0 + cefbr %f7, %r8 + cefbr %f15, %r15 diff --git a/test/MC/SystemZ/insn-cefbr-02.s b/test/MC/SystemZ/insn-cefbr-02.s new file mode 100644 index 000000000000..b894fb9f3257 --- /dev/null +++ b/test/MC/SystemZ/insn-cefbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cefbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cefbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cefbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cefbr %a0, %r0 + + cefbr %r0, %r0 + cefbr %f0, %f0 + cefbr %f0, %a0 + cefbr %a0, %r0 diff --git a/test/MC/SystemZ/insn-cegbr-01.s b/test/MC/SystemZ/insn-cegbr-01.s new file mode 100644 index 000000000000..5b2e6caf12c1 --- /dev/null +++ b/test/MC/SystemZ/insn-cegbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cegbr %f0, %r0 # encoding: [0xb3,0xa4,0x00,0x00] +#CHECK: cegbr %f0, %r15 # encoding: [0xb3,0xa4,0x00,0x0f] +#CHECK: cegbr %f15, %r0 # encoding: [0xb3,0xa4,0x00,0xf0] +#CHECK: cegbr %f7, %r8 # encoding: [0xb3,0xa4,0x00,0x78] +#CHECK: cegbr %f15, %r15 # encoding: [0xb3,0xa4,0x00,0xff] + + cegbr %f0, %r0 + cegbr %f0, %r15 + cegbr %f15, %r0 + cegbr %f7, %r8 + cegbr %f15, %r15 diff --git a/test/MC/SystemZ/insn-cegbr-02.s b/test/MC/SystemZ/insn-cegbr-02.s new file mode 100644 index 000000000000..bf0c31ad13f9 --- /dev/null +++ b/test/MC/SystemZ/insn-cegbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cegbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cegbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cegbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cegbr %a0, %r0 + + cegbr %r0, %r0 + cegbr %f0, %f0 + cegbr %f0, %a0 + cegbr %a0, %r0 diff --git a/test/MC/SystemZ/insn-cfdbr-01.s b/test/MC/SystemZ/insn-cfdbr-01.s new file mode 100644 index 000000000000..be4f87fb29e4 --- /dev/null +++ b/test/MC/SystemZ/insn-cfdbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cfdbr %r0, 0, %f0 # encoding: [0xb3,0x99,0x00,0x00] +#CHECK: cfdbr %r0, 0, %f15 # encoding: [0xb3,0x99,0x00,0x0f] +#CHECK: cfdbr %r0, 15, %f0 # encoding: [0xb3,0x99,0xf0,0x00] +#CHECK: cfdbr %r4, 5, %f6 # encoding: [0xb3,0x99,0x50,0x46] +#CHECK: cfdbr %r15, 0, %f0 # encoding: [0xb3,0x99,0x00,0xf0] + + cfdbr %r0, 0, %f0 + cfdbr %r0, 0, %f15 + cfdbr %r0, 15, %f0 + cfdbr %r4, 5, %f6 + cfdbr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cfdbr-02.s b/test/MC/SystemZ/insn-cfdbr-02.s new file mode 100644 index 000000000000..00175955f255 --- /dev/null +++ b/test/MC/SystemZ/insn-cfdbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cfdbr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cfdbr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cfdbr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cfdbr %r0, 16, %f0 + + cfdbr %r0, 0, %r0 + cfdbr %f0, 0, %f0 + cfdbr %r0, -1, %f0 + cfdbr %r0, 16, %f0 diff --git a/test/MC/SystemZ/insn-cfebr-01.s b/test/MC/SystemZ/insn-cfebr-01.s new file mode 100644 index 000000000000..6f7ab2c0e038 --- /dev/null +++ b/test/MC/SystemZ/insn-cfebr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cfebr %r0, 0, %f0 # encoding: [0xb3,0x98,0x00,0x00] +#CHECK: cfebr %r0, 0, %f15 # encoding: [0xb3,0x98,0x00,0x0f] +#CHECK: cfebr %r0, 15, %f0 # encoding: [0xb3,0x98,0xf0,0x00] +#CHECK: cfebr %r4, 5, %f6 # encoding: [0xb3,0x98,0x50,0x46] +#CHECK: cfebr %r15, 0, %f0 # encoding: [0xb3,0x98,0x00,0xf0] + + cfebr %r0, 0, %f0 + cfebr %r0, 0, %f15 + cfebr %r0, 15, %f0 + cfebr %r4, 5, %f6 + cfebr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cfebr-02.s b/test/MC/SystemZ/insn-cfebr-02.s new file mode 100644 index 000000000000..c3c5adaed2ca --- /dev/null +++ b/test/MC/SystemZ/insn-cfebr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cfebr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cfebr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cfebr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cfebr %r0, 16, %f0 + + cfebr %r0, 0, %r0 + cfebr %f0, 0, %f0 + cfebr %r0, -1, %f0 + cfebr %r0, 16, %f0 diff --git a/test/MC/SystemZ/insn-cfi-01.s b/test/MC/SystemZ/insn-cfi-01.s new file mode 100644 index 000000000000..52e34c02e896 --- /dev/null +++ b/test/MC/SystemZ/insn-cfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cfi %r0, -2147483648 # encoding: [0xc2,0x0d,0x80,0x00,0x00,0x00] +#CHECK: cfi %r0, -1 # encoding: [0xc2,0x0d,0xff,0xff,0xff,0xff] +#CHECK: cfi %r0, 0 # encoding: [0xc2,0x0d,0x00,0x00,0x00,0x00] +#CHECK: cfi %r0, 1 # encoding: [0xc2,0x0d,0x00,0x00,0x00,0x01] +#CHECK: cfi %r0, 2147483647 # encoding: [0xc2,0x0d,0x7f,0xff,0xff,0xff] +#CHECK: cfi %r15, 0 # encoding: [0xc2,0xfd,0x00,0x00,0x00,0x00] + + cfi %r0, -1 << 31 + cfi %r0, -1 + cfi %r0, 0 + cfi %r0, 1 + cfi %r0, (1 << 31) - 1 + cfi %r15, 0 diff --git a/test/MC/SystemZ/insn-cfi-02.s b/test/MC/SystemZ/insn-cfi-02.s new file mode 100644 index 000000000000..cf7c72621b74 --- /dev/null +++ b/test/MC/SystemZ/insn-cfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: cfi %r0, (1 << 31) + + cfi %r0, (-1 << 31) - 1 + cfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-cfxbr-01.s b/test/MC/SystemZ/insn-cfxbr-01.s new file mode 100644 index 000000000000..c509106b5430 --- /dev/null +++ b/test/MC/SystemZ/insn-cfxbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cfxbr %r0, 0, %f0 # encoding: [0xb3,0x9a,0x00,0x00] +#CHECK: cfxbr %r0, 0, %f13 # encoding: [0xb3,0x9a,0x00,0x0d] +#CHECK: cfxbr %r0, 15, %f0 # encoding: [0xb3,0x9a,0xf0,0x00] +#CHECK: cfxbr %r4, 5, %f8 # encoding: [0xb3,0x9a,0x50,0x48] +#CHECK: cfxbr %r15, 0, %f0 # encoding: [0xb3,0x9a,0x00,0xf0] + + cfxbr %r0, 0, %f0 + cfxbr %r0, 0, %f13 + cfxbr %r0, 15, %f0 + cfxbr %r4, 5, %f8 + cfxbr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cfxbr-02.s b/test/MC/SystemZ/insn-cfxbr-02.s new file mode 100644 index 000000000000..3802c514332b --- /dev/null +++ b/test/MC/SystemZ/insn-cfxbr-02.s @@ -0,0 +1,23 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cfxbr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cfxbr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cfxbr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cfxbr %r0, 16, %f0 +#CHECK: error: invalid register +#CHECK: cfxbr %r0, 0, %f2 +#CHECK: error: invalid register +#CHECK: cfxbr %r0, 0, %f14 + + cfxbr %r0, 0, %r0 + cfxbr %f0, 0, %f0 + cfxbr %r0, -1, %f0 + cfxbr %r0, 16, %f0 + cfxbr %r0, 0, %f2 + cfxbr %r0, 0, %f14 + diff --git a/test/MC/SystemZ/insn-cg-01.s b/test/MC/SystemZ/insn-cg-01.s new file mode 100644 index 000000000000..1eb185f0ec60 --- /dev/null +++ b/test/MC/SystemZ/insn-cg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x20] +#CHECK: cg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x20] +#CHECK: cg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x20] +#CHECK: cg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x20] +#CHECK: cg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x20] +#CHECK: cg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x20] +#CHECK: cg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x20] +#CHECK: cg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x20] +#CHECK: cg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x20] +#CHECK: cg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x20] + + cg %r0, -524288 + cg %r0, -1 + cg %r0, 0 + cg %r0, 1 + cg %r0, 524287 + cg %r0, 0(%r1) + cg %r0, 0(%r15) + cg %r0, 524287(%r1,%r15) + cg %r0, 524287(%r15,%r1) + cg %r15, 0 diff --git a/test/MC/SystemZ/insn-cg-02.s b/test/MC/SystemZ/insn-cg-02.s new file mode 100644 index 000000000000..e093ccd75112 --- /dev/null +++ b/test/MC/SystemZ/insn-cg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: cg %r0, 524288 + + cg %r0, -524289 + cg %r0, 524288 diff --git a/test/MC/SystemZ/insn-cgdbr-01.s b/test/MC/SystemZ/insn-cgdbr-01.s new file mode 100644 index 000000000000..718f50a9ea9a --- /dev/null +++ b/test/MC/SystemZ/insn-cgdbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgdbr %r0, 0, %f0 # encoding: [0xb3,0xa9,0x00,0x00] +#CHECK: cgdbr %r0, 0, %f15 # encoding: [0xb3,0xa9,0x00,0x0f] +#CHECK: cgdbr %r0, 15, %f0 # encoding: [0xb3,0xa9,0xf0,0x00] +#CHECK: cgdbr %r4, 5, %f6 # encoding: [0xb3,0xa9,0x50,0x46] +#CHECK: cgdbr %r15, 0, %f0 # encoding: [0xb3,0xa9,0x00,0xf0] + + cgdbr %r0, 0, %f0 + cgdbr %r0, 0, %f15 + cgdbr %r0, 15, %f0 + cgdbr %r4, 5, %f6 + cgdbr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cgdbr-02.s b/test/MC/SystemZ/insn-cgdbr-02.s new file mode 100644 index 000000000000..3a3e01fde0f4 --- /dev/null +++ b/test/MC/SystemZ/insn-cgdbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cgdbr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cgdbr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cgdbr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgdbr %r0, 16, %f0 + + cgdbr %r0, 0, %r0 + cgdbr %f0, 0, %f0 + cgdbr %r0, -1, %f0 + cgdbr %r0, 16, %f0 diff --git a/test/MC/SystemZ/insn-cgebr-01.s b/test/MC/SystemZ/insn-cgebr-01.s new file mode 100644 index 000000000000..dc6a7dbfafdb --- /dev/null +++ b/test/MC/SystemZ/insn-cgebr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgebr %r0, 0, %f0 # encoding: [0xb3,0xa8,0x00,0x00] +#CHECK: cgebr %r0, 0, %f15 # encoding: [0xb3,0xa8,0x00,0x0f] +#CHECK: cgebr %r0, 15, %f0 # encoding: [0xb3,0xa8,0xf0,0x00] +#CHECK: cgebr %r4, 5, %f6 # encoding: [0xb3,0xa8,0x50,0x46] +#CHECK: cgebr %r15, 0, %f0 # encoding: [0xb3,0xa8,0x00,0xf0] + + cgebr %r0, 0, %f0 + cgebr %r0, 0, %f15 + cgebr %r0, 15, %f0 + cgebr %r4, 5, %f6 + cgebr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cgebr-02.s b/test/MC/SystemZ/insn-cgebr-02.s new file mode 100644 index 000000000000..9b817a417281 --- /dev/null +++ b/test/MC/SystemZ/insn-cgebr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cgebr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cgebr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cgebr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgebr %r0, 16, %f0 + + cgebr %r0, 0, %r0 + cgebr %f0, 0, %f0 + cgebr %r0, -1, %f0 + cgebr %r0, 16, %f0 diff --git a/test/MC/SystemZ/insn-cgf-01.s b/test/MC/SystemZ/insn-cgf-01.s new file mode 100644 index 000000000000..03c439f1f5dc --- /dev/null +++ b/test/MC/SystemZ/insn-cgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x30] +#CHECK: cgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x30] +#CHECK: cgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x30] +#CHECK: cgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x30] +#CHECK: cgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x30] +#CHECK: cgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x30] +#CHECK: cgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x30] +#CHECK: cgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x30] +#CHECK: cgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x30] +#CHECK: cgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x30] + + cgf %r0, -524288 + cgf %r0, -1 + cgf %r0, 0 + cgf %r0, 1 + cgf %r0, 524287 + cgf %r0, 0(%r1) + cgf %r0, 0(%r15) + cgf %r0, 524287(%r1,%r15) + cgf %r0, 524287(%r15,%r1) + cgf %r15, 0 diff --git a/test/MC/SystemZ/insn-cgf-02.s b/test/MC/SystemZ/insn-cgf-02.s new file mode 100644 index 000000000000..7171c6e38816 --- /dev/null +++ b/test/MC/SystemZ/insn-cgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: cgf %r0, 524288 + + cgf %r0, -524289 + cgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-cgfi-01.s b/test/MC/SystemZ/insn-cgfi-01.s new file mode 100644 index 000000000000..d6f72d5d6712 --- /dev/null +++ b/test/MC/SystemZ/insn-cgfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgfi %r0, -2147483648 # encoding: [0xc2,0x0c,0x80,0x00,0x00,0x00] +#CHECK: cgfi %r0, -1 # encoding: [0xc2,0x0c,0xff,0xff,0xff,0xff] +#CHECK: cgfi %r0, 0 # encoding: [0xc2,0x0c,0x00,0x00,0x00,0x00] +#CHECK: cgfi %r0, 1 # encoding: [0xc2,0x0c,0x00,0x00,0x00,0x01] +#CHECK: cgfi %r0, 2147483647 # encoding: [0xc2,0x0c,0x7f,0xff,0xff,0xff] +#CHECK: cgfi %r15, 0 # encoding: [0xc2,0xfc,0x00,0x00,0x00,0x00] + + cgfi %r0, -1 << 31 + cgfi %r0, -1 + cgfi %r0, 0 + cgfi %r0, 1 + cgfi %r0, (1 << 31) - 1 + cgfi %r15, 0 diff --git a/test/MC/SystemZ/insn-cgfi-02.s b/test/MC/SystemZ/insn-cgfi-02.s new file mode 100644 index 000000000000..6f72a24e6902 --- /dev/null +++ b/test/MC/SystemZ/insn-cgfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cgfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: cgfi %r0, (1 << 31) + + cgfi %r0, (-1 << 31) - 1 + cgfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-cgfr-01.s b/test/MC/SystemZ/insn-cgfr-01.s new file mode 100644 index 000000000000..6bd1792ea020 --- /dev/null +++ b/test/MC/SystemZ/insn-cgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgfr %r0, %r0 # encoding: [0xb9,0x30,0x00,0x00] +#CHECK: cgfr %r0, %r15 # encoding: [0xb9,0x30,0x00,0x0f] +#CHECK: cgfr %r15, %r0 # encoding: [0xb9,0x30,0x00,0xf0] +#CHECK: cgfr %r7, %r8 # encoding: [0xb9,0x30,0x00,0x78] + + cgfr %r0,%r0 + cgfr %r0,%r15 + cgfr %r15,%r0 + cgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-cgfrl-01.s b/test/MC/SystemZ/insn-cgfrl-01.s new file mode 100644 index 000000000000..2792fb4a93b7 --- /dev/null +++ b/test/MC/SystemZ/insn-cgfrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgfrl %r0, 2864434397 # encoding: [0xc6,0x0c,0x55,0x5d,0xe6,0x6e] +#CHECK: cgfrl %r15, 2864434397 # encoding: [0xc6,0xfc,0x55,0x5d,0xe6,0x6e] + + cgfrl %r0,0xaabbccdd + cgfrl %r15,0xaabbccdd + +#CHECK: cgfrl %r0, foo # encoding: [0xc6,0x0c,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: cgfrl %r15, foo # encoding: [0xc6,0xfc,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + cgfrl %r0,foo + cgfrl %r15,foo + +#CHECK: cgfrl %r3, bar+100 # encoding: [0xc6,0x3c,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: cgfrl %r4, bar+100 # encoding: [0xc6,0x4c,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + cgfrl %r3,bar+100 + cgfrl %r4,bar+100 + +#CHECK: cgfrl %r7, frob@PLT # encoding: [0xc6,0x7c,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: cgfrl %r8, frob@PLT # encoding: [0xc6,0x8c,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + cgfrl %r7,frob@PLT + cgfrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cgh-01.s b/test/MC/SystemZ/insn-cgh-01.s new file mode 100644 index 000000000000..31c86abdda76 --- /dev/null +++ b/test/MC/SystemZ/insn-cgh-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x34] +#CHECK: cgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x34] +#CHECK: cgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x34] +#CHECK: cgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x34] +#CHECK: cgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x34] +#CHECK: cgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x34] +#CHECK: cgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x34] +#CHECK: cgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x34] +#CHECK: cgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x34] +#CHECK: cgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x34] + + cgh %r0, -524288 + cgh %r0, -1 + cgh %r0, 0 + cgh %r0, 1 + cgh %r0, 524287 + cgh %r0, 0(%r1) + cgh %r0, 0(%r15) + cgh %r0, 524287(%r1,%r15) + cgh %r0, 524287(%r15,%r1) + cgh %r15, 0 diff --git a/test/MC/SystemZ/insn-cgh-02.s b/test/MC/SystemZ/insn-cgh-02.s new file mode 100644 index 000000000000..60e665f2dd85 --- /dev/null +++ b/test/MC/SystemZ/insn-cgh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: cgh %r0, 524288 + + cgh %r0, -524289 + cgh %r0, 524288 diff --git a/test/MC/SystemZ/insn-cghi-01.s b/test/MC/SystemZ/insn-cghi-01.s new file mode 100644 index 000000000000..575ad89023a2 --- /dev/null +++ b/test/MC/SystemZ/insn-cghi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cghi %r0, -32768 # encoding: [0xa7,0x0f,0x80,0x00] +#CHECK: cghi %r0, -1 # encoding: [0xa7,0x0f,0xff,0xff] +#CHECK: cghi %r0, 0 # encoding: [0xa7,0x0f,0x00,0x00] +#CHECK: cghi %r0, 1 # encoding: [0xa7,0x0f,0x00,0x01] +#CHECK: cghi %r0, 32767 # encoding: [0xa7,0x0f,0x7f,0xff] +#CHECK: cghi %r15, 0 # encoding: [0xa7,0xff,0x00,0x00] + + cghi %r0, -32768 + cghi %r0, -1 + cghi %r0, 0 + cghi %r0, 1 + cghi %r0, 32767 + cghi %r15, 0 diff --git a/test/MC/SystemZ/insn-cghi-02.s b/test/MC/SystemZ/insn-cghi-02.s new file mode 100644 index 000000000000..bd4a52a6b720 --- /dev/null +++ b/test/MC/SystemZ/insn-cghi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cghi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: cghi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: cghi %r0, foo + + cghi %r0, -32769 + cghi %r0, 32768 + cghi %r0, foo diff --git a/test/MC/SystemZ/insn-cghrl-01.s b/test/MC/SystemZ/insn-cghrl-01.s new file mode 100644 index 000000000000..c48c5ec3efdf --- /dev/null +++ b/test/MC/SystemZ/insn-cghrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cghrl %r0, 2864434397 # encoding: [0xc6,0x04,0x55,0x5d,0xe6,0x6e] +#CHECK: cghrl %r15, 2864434397 # encoding: [0xc6,0xf4,0x55,0x5d,0xe6,0x6e] + + cghrl %r0,0xaabbccdd + cghrl %r15,0xaabbccdd + +#CHECK: cghrl %r0, foo # encoding: [0xc6,0x04,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: cghrl %r15, foo # encoding: [0xc6,0xf4,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + cghrl %r0,foo + cghrl %r15,foo + +#CHECK: cghrl %r3, bar+100 # encoding: [0xc6,0x34,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: cghrl %r4, bar+100 # encoding: [0xc6,0x44,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + cghrl %r3,bar+100 + cghrl %r4,bar+100 + +#CHECK: cghrl %r7, frob@PLT # encoding: [0xc6,0x74,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: cghrl %r8, frob@PLT # encoding: [0xc6,0x84,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + cghrl %r7,frob@PLT + cghrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cghsi-01.s b/test/MC/SystemZ/insn-cghsi-01.s new file mode 100644 index 000000000000..7d67e20b5b70 --- /dev/null +++ b/test/MC/SystemZ/insn-cghsi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cghsi 0, 0 # encoding: [0xe5,0x58,0x00,0x00,0x00,0x00] +#CHECK: cghsi 4095, 0 # encoding: [0xe5,0x58,0x0f,0xff,0x00,0x00] +#CHECK: cghsi 0, -32768 # encoding: [0xe5,0x58,0x00,0x00,0x80,0x00] +#CHECK: cghsi 0, -1 # encoding: [0xe5,0x58,0x00,0x00,0xff,0xff] +#CHECK: cghsi 0, 0 # encoding: [0xe5,0x58,0x00,0x00,0x00,0x00] +#CHECK: cghsi 0, 1 # encoding: [0xe5,0x58,0x00,0x00,0x00,0x01] +#CHECK: cghsi 0, 32767 # encoding: [0xe5,0x58,0x00,0x00,0x7f,0xff] +#CHECK: cghsi 0(%r1), 42 # encoding: [0xe5,0x58,0x10,0x00,0x00,0x2a] +#CHECK: cghsi 0(%r15), 42 # encoding: [0xe5,0x58,0xf0,0x00,0x00,0x2a] +#CHECK: cghsi 4095(%r1), 42 # encoding: [0xe5,0x58,0x1f,0xff,0x00,0x2a] +#CHECK: cghsi 4095(%r15), 42 # encoding: [0xe5,0x58,0xff,0xff,0x00,0x2a] + + cghsi 0, 0 + cghsi 4095, 0 + cghsi 0, -32768 + cghsi 0, -1 + cghsi 0, 0 + cghsi 0, 1 + cghsi 0, 32767 + cghsi 0(%r1), 42 + cghsi 0(%r15), 42 + cghsi 4095(%r1), 42 + cghsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-cghsi-02.s b/test/MC/SystemZ/insn-cghsi-02.s new file mode 100644 index 000000000000..773ee5cd9e9d --- /dev/null +++ b/test/MC/SystemZ/insn-cghsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cghsi -1, 0 +#CHECK: error: invalid operand +#CHECK: cghsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cghsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: cghsi 0, -32769 +#CHECK: error: invalid operand +#CHECK: cghsi 0, 32768 + + cghsi -1, 0 + cghsi 4096, 0 + cghsi 0(%r1,%r2), 0 + cghsi 0, -32769 + cghsi 0, 32768 diff --git a/test/MC/SystemZ/insn-cgr-01.s b/test/MC/SystemZ/insn-cgr-01.s new file mode 100644 index 000000000000..334a0f63f82b --- /dev/null +++ b/test/MC/SystemZ/insn-cgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgr %r0, %r0 # encoding: [0xb9,0x20,0x00,0x00] +#CHECK: cgr %r0, %r15 # encoding: [0xb9,0x20,0x00,0x0f] +#CHECK: cgr %r15, %r0 # encoding: [0xb9,0x20,0x00,0xf0] +#CHECK: cgr %r7, %r8 # encoding: [0xb9,0x20,0x00,0x78] + + cgr %r0,%r0 + cgr %r0,%r15 + cgr %r15,%r0 + cgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-cgrl-01.s b/test/MC/SystemZ/insn-cgrl-01.s new file mode 100644 index 000000000000..af878cbf450a --- /dev/null +++ b/test/MC/SystemZ/insn-cgrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgrl %r0, 2864434397 # encoding: [0xc6,0x08,0x55,0x5d,0xe6,0x6e] +#CHECK: cgrl %r15, 2864434397 # encoding: [0xc6,0xf8,0x55,0x5d,0xe6,0x6e] + + cgrl %r0,0xaabbccdd + cgrl %r15,0xaabbccdd + +#CHECK: cgrl %r0, foo # encoding: [0xc6,0x08,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: cgrl %r15, foo # encoding: [0xc6,0xf8,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + cgrl %r0,foo + cgrl %r15,foo + +#CHECK: cgrl %r3, bar+100 # encoding: [0xc6,0x38,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: cgrl %r4, bar+100 # encoding: [0xc6,0x48,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + cgrl %r3,bar+100 + cgrl %r4,bar+100 + +#CHECK: cgrl %r7, frob@PLT # encoding: [0xc6,0x78,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: cgrl %r8, frob@PLT # encoding: [0xc6,0x88,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + cgrl %r7,frob@PLT + cgrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cgxbr-01.s b/test/MC/SystemZ/insn-cgxbr-01.s new file mode 100644 index 000000000000..0250b52955af --- /dev/null +++ b/test/MC/SystemZ/insn-cgxbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cgxbr %r0, 0, %f0 # encoding: [0xb3,0xaa,0x00,0x00] +#CHECK: cgxbr %r0, 0, %f13 # encoding: [0xb3,0xaa,0x00,0x0d] +#CHECK: cgxbr %r0, 15, %f0 # encoding: [0xb3,0xaa,0xf0,0x00] +#CHECK: cgxbr %r4, 5, %f8 # encoding: [0xb3,0xaa,0x50,0x48] +#CHECK: cgxbr %r15, 0, %f0 # encoding: [0xb3,0xaa,0x00,0xf0] + + cgxbr %r0, 0, %f0 + cgxbr %r0, 0, %f13 + cgxbr %r0, 15, %f0 + cgxbr %r4, 5, %f8 + cgxbr %r15, 0, %f0 diff --git a/test/MC/SystemZ/insn-cgxbr-02.s b/test/MC/SystemZ/insn-cgxbr-02.s new file mode 100644 index 000000000000..9caab9fc401d --- /dev/null +++ b/test/MC/SystemZ/insn-cgxbr-02.s @@ -0,0 +1,23 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cgxbr %r0, 0, %r0 +#CHECK: error: invalid register +#CHECK: cgxbr %f0, 0, %f0 +#CHECK: error: invalid operand +#CHECK: cgxbr %r0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: cgxbr %r0, 16, %f0 +#CHECK: error: invalid register +#CHECK: cgxbr %r0, 0, %f2 +#CHECK: error: invalid register +#CHECK: cgxbr %r0, 0, %f14 + + cgxbr %r0, 0, %r0 + cgxbr %f0, 0, %f0 + cgxbr %r0, -1, %f0 + cgxbr %r0, 16, %f0 + cgxbr %r0, 0, %f2 + cgxbr %r0, 0, %f14 + diff --git a/test/MC/SystemZ/insn-ch-01.s b/test/MC/SystemZ/insn-ch-01.s new file mode 100644 index 000000000000..dfb0b7fcca05 --- /dev/null +++ b/test/MC/SystemZ/insn-ch-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ch %r0, 0 # encoding: [0x49,0x00,0x00,0x00] +#CHECK: ch %r0, 4095 # encoding: [0x49,0x00,0x0f,0xff] +#CHECK: ch %r0, 0(%r1) # encoding: [0x49,0x00,0x10,0x00] +#CHECK: ch %r0, 0(%r15) # encoding: [0x49,0x00,0xf0,0x00] +#CHECK: ch %r0, 4095(%r1,%r15) # encoding: [0x49,0x01,0xff,0xff] +#CHECK: ch %r0, 4095(%r15,%r1) # encoding: [0x49,0x0f,0x1f,0xff] +#CHECK: ch %r15, 0 # encoding: [0x49,0xf0,0x00,0x00] + + ch %r0, 0 + ch %r0, 4095 + ch %r0, 0(%r1) + ch %r0, 0(%r15) + ch %r0, 4095(%r1,%r15) + ch %r0, 4095(%r15,%r1) + ch %r15, 0 diff --git a/test/MC/SystemZ/insn-ch-02.s b/test/MC/SystemZ/insn-ch-02.s new file mode 100644 index 000000000000..2034c2b8d4e9 --- /dev/null +++ b/test/MC/SystemZ/insn-ch-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ch %r0, -1 +#CHECK: error: invalid operand +#CHECK: ch %r0, 4096 + + ch %r0, -1 + ch %r0, 4096 diff --git a/test/MC/SystemZ/insn-chhsi-01.s b/test/MC/SystemZ/insn-chhsi-01.s new file mode 100644 index 000000000000..0fd50bc5e100 --- /dev/null +++ b/test/MC/SystemZ/insn-chhsi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: chhsi 0, 0 # encoding: [0xe5,0x54,0x00,0x00,0x00,0x00] +#CHECK: chhsi 4095, 0 # encoding: [0xe5,0x54,0x0f,0xff,0x00,0x00] +#CHECK: chhsi 0, -32768 # encoding: [0xe5,0x54,0x00,0x00,0x80,0x00] +#CHECK: chhsi 0, -1 # encoding: [0xe5,0x54,0x00,0x00,0xff,0xff] +#CHECK: chhsi 0, 0 # encoding: [0xe5,0x54,0x00,0x00,0x00,0x00] +#CHECK: chhsi 0, 1 # encoding: [0xe5,0x54,0x00,0x00,0x00,0x01] +#CHECK: chhsi 0, 32767 # encoding: [0xe5,0x54,0x00,0x00,0x7f,0xff] +#CHECK: chhsi 0(%r1), 42 # encoding: [0xe5,0x54,0x10,0x00,0x00,0x2a] +#CHECK: chhsi 0(%r15), 42 # encoding: [0xe5,0x54,0xf0,0x00,0x00,0x2a] +#CHECK: chhsi 4095(%r1), 42 # encoding: [0xe5,0x54,0x1f,0xff,0x00,0x2a] +#CHECK: chhsi 4095(%r15), 42 # encoding: [0xe5,0x54,0xff,0xff,0x00,0x2a] + + chhsi 0, 0 + chhsi 4095, 0 + chhsi 0, -32768 + chhsi 0, -1 + chhsi 0, 0 + chhsi 0, 1 + chhsi 0, 32767 + chhsi 0(%r1), 42 + chhsi 0(%r15), 42 + chhsi 4095(%r1), 42 + chhsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-chhsi-02.s b/test/MC/SystemZ/insn-chhsi-02.s new file mode 100644 index 000000000000..24e8c0cfbd3a --- /dev/null +++ b/test/MC/SystemZ/insn-chhsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: chhsi -1, 0 +#CHECK: error: invalid operand +#CHECK: chhsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: chhsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: chhsi 0, -32769 +#CHECK: error: invalid operand +#CHECK: chhsi 0, 32768 + + chhsi -1, 0 + chhsi 4096, 0 + chhsi 0(%r1,%r2), 0 + chhsi 0, -32769 + chhsi 0, 32768 diff --git a/test/MC/SystemZ/insn-chi-01.s b/test/MC/SystemZ/insn-chi-01.s new file mode 100644 index 000000000000..fb44cfc21708 --- /dev/null +++ b/test/MC/SystemZ/insn-chi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: chi %r0, -32768 # encoding: [0xa7,0x0e,0x80,0x00] +#CHECK: chi %r0, -1 # encoding: [0xa7,0x0e,0xff,0xff] +#CHECK: chi %r0, 0 # encoding: [0xa7,0x0e,0x00,0x00] +#CHECK: chi %r0, 1 # encoding: [0xa7,0x0e,0x00,0x01] +#CHECK: chi %r0, 32767 # encoding: [0xa7,0x0e,0x7f,0xff] +#CHECK: chi %r15, 0 # encoding: [0xa7,0xfe,0x00,0x00] + + chi %r0, -32768 + chi %r0, -1 + chi %r0, 0 + chi %r0, 1 + chi %r0, 32767 + chi %r15, 0 diff --git a/test/MC/SystemZ/insn-chi-02.s b/test/MC/SystemZ/insn-chi-02.s new file mode 100644 index 000000000000..bb9ffdc7e6b0 --- /dev/null +++ b/test/MC/SystemZ/insn-chi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: chi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: chi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: chi %r0, foo + + chi %r0, -32769 + chi %r0, 32768 + chi %r0, foo diff --git a/test/MC/SystemZ/insn-chrl-01.s b/test/MC/SystemZ/insn-chrl-01.s new file mode 100644 index 000000000000..c133a326d2b0 --- /dev/null +++ b/test/MC/SystemZ/insn-chrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: chrl %r0, 2864434397 # encoding: [0xc6,0x05,0x55,0x5d,0xe6,0x6e] +#CHECK: chrl %r15, 2864434397 # encoding: [0xc6,0xf5,0x55,0x5d,0xe6,0x6e] + + chrl %r0,0xaabbccdd + chrl %r15,0xaabbccdd + +#CHECK: chrl %r0, foo # encoding: [0xc6,0x05,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: chrl %r15, foo # encoding: [0xc6,0xf5,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + chrl %r0,foo + chrl %r15,foo + +#CHECK: chrl %r3, bar+100 # encoding: [0xc6,0x35,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: chrl %r4, bar+100 # encoding: [0xc6,0x45,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + chrl %r3,bar+100 + chrl %r4,bar+100 + +#CHECK: chrl %r7, frob@PLT # encoding: [0xc6,0x75,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: chrl %r8, frob@PLT # encoding: [0xc6,0x85,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + chrl %r7,frob@PLT + chrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-chsi-01.s b/test/MC/SystemZ/insn-chsi-01.s new file mode 100644 index 000000000000..6d92202185ab --- /dev/null +++ b/test/MC/SystemZ/insn-chsi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: chsi 0, 0 # encoding: [0xe5,0x5c,0x00,0x00,0x00,0x00] +#CHECK: chsi 4095, 0 # encoding: [0xe5,0x5c,0x0f,0xff,0x00,0x00] +#CHECK: chsi 0, -32768 # encoding: [0xe5,0x5c,0x00,0x00,0x80,0x00] +#CHECK: chsi 0, -1 # encoding: [0xe5,0x5c,0x00,0x00,0xff,0xff] +#CHECK: chsi 0, 0 # encoding: [0xe5,0x5c,0x00,0x00,0x00,0x00] +#CHECK: chsi 0, 1 # encoding: [0xe5,0x5c,0x00,0x00,0x00,0x01] +#CHECK: chsi 0, 32767 # encoding: [0xe5,0x5c,0x00,0x00,0x7f,0xff] +#CHECK: chsi 0(%r1), 42 # encoding: [0xe5,0x5c,0x10,0x00,0x00,0x2a] +#CHECK: chsi 0(%r15), 42 # encoding: [0xe5,0x5c,0xf0,0x00,0x00,0x2a] +#CHECK: chsi 4095(%r1), 42 # encoding: [0xe5,0x5c,0x1f,0xff,0x00,0x2a] +#CHECK: chsi 4095(%r15), 42 # encoding: [0xe5,0x5c,0xff,0xff,0x00,0x2a] + + chsi 0, 0 + chsi 4095, 0 + chsi 0, -32768 + chsi 0, -1 + chsi 0, 0 + chsi 0, 1 + chsi 0, 32767 + chsi 0(%r1), 42 + chsi 0(%r15), 42 + chsi 4095(%r1), 42 + chsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-chsi-02.s b/test/MC/SystemZ/insn-chsi-02.s new file mode 100644 index 000000000000..16ace53d6710 --- /dev/null +++ b/test/MC/SystemZ/insn-chsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: chsi -1, 0 +#CHECK: error: invalid operand +#CHECK: chsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: chsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: chsi 0, -32769 +#CHECK: error: invalid operand +#CHECK: chsi 0, 32768 + + chsi -1, 0 + chsi 4096, 0 + chsi 0(%r1,%r2), 0 + chsi 0, -32769 + chsi 0, 32768 diff --git a/test/MC/SystemZ/insn-chy-01.s b/test/MC/SystemZ/insn-chy-01.s new file mode 100644 index 000000000000..9ecc0551cf2b --- /dev/null +++ b/test/MC/SystemZ/insn-chy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: chy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x79] +#CHECK: chy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x79] +#CHECK: chy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x79] +#CHECK: chy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x79] +#CHECK: chy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x79] +#CHECK: chy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x79] +#CHECK: chy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x79] +#CHECK: chy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x79] +#CHECK: chy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x79] +#CHECK: chy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x79] + + chy %r0, -524288 + chy %r0, -1 + chy %r0, 0 + chy %r0, 1 + chy %r0, 524287 + chy %r0, 0(%r1) + chy %r0, 0(%r15) + chy %r0, 524287(%r1,%r15) + chy %r0, 524287(%r15,%r1) + chy %r15, 0 diff --git a/test/MC/SystemZ/insn-chy-02.s b/test/MC/SystemZ/insn-chy-02.s new file mode 100644 index 000000000000..8ab849f0908c --- /dev/null +++ b/test/MC/SystemZ/insn-chy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: chy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: chy %r0, 524288 + + chy %r0, -524289 + chy %r0, 524288 diff --git a/test/MC/SystemZ/insn-cl-01.s b/test/MC/SystemZ/insn-cl-01.s new file mode 100644 index 000000000000..7face8f85431 --- /dev/null +++ b/test/MC/SystemZ/insn-cl-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cl %r0, 0 # encoding: [0x55,0x00,0x00,0x00] +#CHECK: cl %r0, 4095 # encoding: [0x55,0x00,0x0f,0xff] +#CHECK: cl %r0, 0(%r1) # encoding: [0x55,0x00,0x10,0x00] +#CHECK: cl %r0, 0(%r15) # encoding: [0x55,0x00,0xf0,0x00] +#CHECK: cl %r0, 4095(%r1,%r15) # encoding: [0x55,0x01,0xff,0xff] +#CHECK: cl %r0, 4095(%r15,%r1) # encoding: [0x55,0x0f,0x1f,0xff] +#CHECK: cl %r15, 0 # encoding: [0x55,0xf0,0x00,0x00] + + cl %r0, 0 + cl %r0, 4095 + cl %r0, 0(%r1) + cl %r0, 0(%r15) + cl %r0, 4095(%r1,%r15) + cl %r0, 4095(%r15,%r1) + cl %r15, 0 diff --git a/test/MC/SystemZ/insn-cl-02.s b/test/MC/SystemZ/insn-cl-02.s new file mode 100644 index 000000000000..ec3e1df996fa --- /dev/null +++ b/test/MC/SystemZ/insn-cl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cl %r0, -1 +#CHECK: error: invalid operand +#CHECK: cl %r0, 4096 + + cl %r0, -1 + cl %r0, 4096 diff --git a/test/MC/SystemZ/insn-clfhsi-01.s b/test/MC/SystemZ/insn-clfhsi-01.s new file mode 100644 index 000000000000..910515d96b7c --- /dev/null +++ b/test/MC/SystemZ/insn-clfhsi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clfhsi 0, 0 # encoding: [0xe5,0x5d,0x00,0x00,0x00,0x00] +#CHECK: clfhsi 4095, 0 # encoding: [0xe5,0x5d,0x0f,0xff,0x00,0x00] +#CHECK: clfhsi 0, 65535 # encoding: [0xe5,0x5d,0x00,0x00,0xff,0xff] +#CHECK: clfhsi 0(%r1), 42 # encoding: [0xe5,0x5d,0x10,0x00,0x00,0x2a] +#CHECK: clfhsi 0(%r15), 42 # encoding: [0xe5,0x5d,0xf0,0x00,0x00,0x2a] +#CHECK: clfhsi 4095(%r1), 42 # encoding: [0xe5,0x5d,0x1f,0xff,0x00,0x2a] +#CHECK: clfhsi 4095(%r15), 42 # encoding: [0xe5,0x5d,0xff,0xff,0x00,0x2a] + + clfhsi 0, 0 + clfhsi 4095, 0 + clfhsi 0, 65535 + clfhsi 0(%r1), 42 + clfhsi 0(%r15), 42 + clfhsi 4095(%r1), 42 + clfhsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-clfhsi-02.s b/test/MC/SystemZ/insn-clfhsi-02.s new file mode 100644 index 000000000000..4a6f4049c584 --- /dev/null +++ b/test/MC/SystemZ/insn-clfhsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clfhsi -1, 0 +#CHECK: error: invalid operand +#CHECK: clfhsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: clfhsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: clfhsi 0, -1 +#CHECK: error: invalid operand +#CHECK: clfhsi 0, 65536 + + clfhsi -1, 0 + clfhsi 4096, 0 + clfhsi 0(%r1,%r2), 0 + clfhsi 0, -1 + clfhsi 0, 65536 diff --git a/test/MC/SystemZ/insn-clfi-01.s b/test/MC/SystemZ/insn-clfi-01.s new file mode 100644 index 000000000000..4156c7f6e8ea --- /dev/null +++ b/test/MC/SystemZ/insn-clfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clfi %r0, 0 # encoding: [0xc2,0x0f,0x00,0x00,0x00,0x00] +#CHECK: clfi %r0, 4294967295 # encoding: [0xc2,0x0f,0xff,0xff,0xff,0xff] +#CHECK: clfi %r15, 0 # encoding: [0xc2,0xff,0x00,0x00,0x00,0x00] + + clfi %r0, 0 + clfi %r0, (1 << 32) - 1 + clfi %r15, 0 diff --git a/test/MC/SystemZ/insn-clfi-02.s b/test/MC/SystemZ/insn-clfi-02.s new file mode 100644 index 000000000000..9d3f80630ef9 --- /dev/null +++ b/test/MC/SystemZ/insn-clfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: clfi %r0, (1 << 32) + + clfi %r0, -1 + clfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-clg-01.s b/test/MC/SystemZ/insn-clg-01.s new file mode 100644 index 000000000000..596bae1c813b --- /dev/null +++ b/test/MC/SystemZ/insn-clg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x21] +#CHECK: clg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x21] +#CHECK: clg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x21] +#CHECK: clg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x21] +#CHECK: clg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x21] +#CHECK: clg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x21] +#CHECK: clg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x21] +#CHECK: clg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x21] +#CHECK: clg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x21] +#CHECK: clg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x21] + + clg %r0, -524288 + clg %r0, -1 + clg %r0, 0 + clg %r0, 1 + clg %r0, 524287 + clg %r0, 0(%r1) + clg %r0, 0(%r15) + clg %r0, 524287(%r1,%r15) + clg %r0, 524287(%r15,%r1) + clg %r15, 0 diff --git a/test/MC/SystemZ/insn-clg-02.s b/test/MC/SystemZ/insn-clg-02.s new file mode 100644 index 000000000000..a17aab52049f --- /dev/null +++ b/test/MC/SystemZ/insn-clg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: clg %r0, 524288 + + clg %r0, -524289 + clg %r0, 524288 diff --git a/test/MC/SystemZ/insn-clgf-01.s b/test/MC/SystemZ/insn-clgf-01.s new file mode 100644 index 000000000000..003ba838028e --- /dev/null +++ b/test/MC/SystemZ/insn-clgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x31] +#CHECK: clgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x31] +#CHECK: clgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x31] +#CHECK: clgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x31] +#CHECK: clgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x31] +#CHECK: clgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x31] +#CHECK: clgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x31] +#CHECK: clgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x31] +#CHECK: clgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x31] +#CHECK: clgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x31] + + clgf %r0, -524288 + clgf %r0, -1 + clgf %r0, 0 + clgf %r0, 1 + clgf %r0, 524287 + clgf %r0, 0(%r1) + clgf %r0, 0(%r15) + clgf %r0, 524287(%r1,%r15) + clgf %r0, 524287(%r15,%r1) + clgf %r15, 0 diff --git a/test/MC/SystemZ/insn-clgf-02.s b/test/MC/SystemZ/insn-clgf-02.s new file mode 100644 index 000000000000..9de49ae79b6a --- /dev/null +++ b/test/MC/SystemZ/insn-clgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: clgf %r0, 524288 + + clgf %r0, -524289 + clgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-clgfi-01.s b/test/MC/SystemZ/insn-clgfi-01.s new file mode 100644 index 000000000000..dbf4a0e8f0a7 --- /dev/null +++ b/test/MC/SystemZ/insn-clgfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgfi %r0, 0 # encoding: [0xc2,0x0e,0x00,0x00,0x00,0x00] +#CHECK: clgfi %r0, 4294967295 # encoding: [0xc2,0x0e,0xff,0xff,0xff,0xff] +#CHECK: clgfi %r15, 0 # encoding: [0xc2,0xfe,0x00,0x00,0x00,0x00] + + clgfi %r0, 0 + clgfi %r0, (1 << 32) - 1 + clgfi %r15, 0 diff --git a/test/MC/SystemZ/insn-clgfi-02.s b/test/MC/SystemZ/insn-clgfi-02.s new file mode 100644 index 000000000000..3f2db33d8366 --- /dev/null +++ b/test/MC/SystemZ/insn-clgfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clgfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: clgfi %r0, (1 << 32) + + clgfi %r0, -1 + clgfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-clgfr-01.s b/test/MC/SystemZ/insn-clgfr-01.s new file mode 100644 index 000000000000..37f1e24452de --- /dev/null +++ b/test/MC/SystemZ/insn-clgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgfr %r0, %r0 # encoding: [0xb9,0x31,0x00,0x00] +#CHECK: clgfr %r0, %r15 # encoding: [0xb9,0x31,0x00,0x0f] +#CHECK: clgfr %r15, %r0 # encoding: [0xb9,0x31,0x00,0xf0] +#CHECK: clgfr %r7, %r8 # encoding: [0xb9,0x31,0x00,0x78] + + clgfr %r0,%r0 + clgfr %r0,%r15 + clgfr %r15,%r0 + clgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-clgfrl-01.s b/test/MC/SystemZ/insn-clgfrl-01.s new file mode 100644 index 000000000000..6fc6d5eb3bad --- /dev/null +++ b/test/MC/SystemZ/insn-clgfrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgfrl %r0, 2864434397 # encoding: [0xc6,0x0e,0x55,0x5d,0xe6,0x6e] +#CHECK: clgfrl %r15, 2864434397 # encoding: [0xc6,0xfe,0x55,0x5d,0xe6,0x6e] + + clgfrl %r0,0xaabbccdd + clgfrl %r15,0xaabbccdd + +#CHECK: clgfrl %r0, foo # encoding: [0xc6,0x0e,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: clgfrl %r15, foo # encoding: [0xc6,0xfe,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + clgfrl %r0,foo + clgfrl %r15,foo + +#CHECK: clgfrl %r3, bar+100 # encoding: [0xc6,0x3e,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: clgfrl %r4, bar+100 # encoding: [0xc6,0x4e,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + clgfrl %r3,bar+100 + clgfrl %r4,bar+100 + +#CHECK: clgfrl %r7, frob@PLT # encoding: [0xc6,0x7e,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: clgfrl %r8, frob@PLT # encoding: [0xc6,0x8e,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + clgfrl %r7,frob@PLT + clgfrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-clghrl-01.s b/test/MC/SystemZ/insn-clghrl-01.s new file mode 100644 index 000000000000..41c2580abde5 --- /dev/null +++ b/test/MC/SystemZ/insn-clghrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clghrl %r0, 2864434397 # encoding: [0xc6,0x06,0x55,0x5d,0xe6,0x6e] +#CHECK: clghrl %r15, 2864434397 # encoding: [0xc6,0xf6,0x55,0x5d,0xe6,0x6e] + + clghrl %r0,0xaabbccdd + clghrl %r15,0xaabbccdd + +#CHECK: clghrl %r0, foo # encoding: [0xc6,0x06,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: clghrl %r15, foo # encoding: [0xc6,0xf6,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + clghrl %r0,foo + clghrl %r15,foo + +#CHECK: clghrl %r3, bar+100 # encoding: [0xc6,0x36,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: clghrl %r4, bar+100 # encoding: [0xc6,0x46,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + clghrl %r3,bar+100 + clghrl %r4,bar+100 + +#CHECK: clghrl %r7, frob@PLT # encoding: [0xc6,0x76,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: clghrl %r8, frob@PLT # encoding: [0xc6,0x86,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + clghrl %r7,frob@PLT + clghrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-clghsi-01.s b/test/MC/SystemZ/insn-clghsi-01.s new file mode 100644 index 000000000000..05e0c585c0a9 --- /dev/null +++ b/test/MC/SystemZ/insn-clghsi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clghsi 0, 0 # encoding: [0xe5,0x59,0x00,0x00,0x00,0x00] +#CHECK: clghsi 4095, 0 # encoding: [0xe5,0x59,0x0f,0xff,0x00,0x00] +#CHECK: clghsi 0, 65535 # encoding: [0xe5,0x59,0x00,0x00,0xff,0xff] +#CHECK: clghsi 0(%r1), 42 # encoding: [0xe5,0x59,0x10,0x00,0x00,0x2a] +#CHECK: clghsi 0(%r15), 42 # encoding: [0xe5,0x59,0xf0,0x00,0x00,0x2a] +#CHECK: clghsi 4095(%r1), 42 # encoding: [0xe5,0x59,0x1f,0xff,0x00,0x2a] +#CHECK: clghsi 4095(%r15), 42 # encoding: [0xe5,0x59,0xff,0xff,0x00,0x2a] + + clghsi 0, 0 + clghsi 4095, 0 + clghsi 0, 65535 + clghsi 0(%r1), 42 + clghsi 0(%r15), 42 + clghsi 4095(%r1), 42 + clghsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-clghsi-02.s b/test/MC/SystemZ/insn-clghsi-02.s new file mode 100644 index 000000000000..f0361280705d --- /dev/null +++ b/test/MC/SystemZ/insn-clghsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clghsi -1, 0 +#CHECK: error: invalid operand +#CHECK: clghsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: clghsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: clghsi 0, -1 +#CHECK: error: invalid operand +#CHECK: clghsi 0, 65536 + + clghsi -1, 0 + clghsi 4096, 0 + clghsi 0(%r1,%r2), 0 + clghsi 0, -1 + clghsi 0, 65536 diff --git a/test/MC/SystemZ/insn-clgr-01.s b/test/MC/SystemZ/insn-clgr-01.s new file mode 100644 index 000000000000..7e9d2ad43988 --- /dev/null +++ b/test/MC/SystemZ/insn-clgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgr %r0, %r0 # encoding: [0xb9,0x21,0x00,0x00] +#CHECK: clgr %r0, %r15 # encoding: [0xb9,0x21,0x00,0x0f] +#CHECK: clgr %r15, %r0 # encoding: [0xb9,0x21,0x00,0xf0] +#CHECK: clgr %r7, %r8 # encoding: [0xb9,0x21,0x00,0x78] + + clgr %r0,%r0 + clgr %r0,%r15 + clgr %r15,%r0 + clgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-clgrl-01.s b/test/MC/SystemZ/insn-clgrl-01.s new file mode 100644 index 000000000000..439bcd94ff89 --- /dev/null +++ b/test/MC/SystemZ/insn-clgrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clgrl %r0, 2864434397 # encoding: [0xc6,0x0a,0x55,0x5d,0xe6,0x6e] +#CHECK: clgrl %r15, 2864434397 # encoding: [0xc6,0xfa,0x55,0x5d,0xe6,0x6e] + + clgrl %r0,0xaabbccdd + clgrl %r15,0xaabbccdd + +#CHECK: clgrl %r0, foo # encoding: [0xc6,0x0a,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: clgrl %r15, foo # encoding: [0xc6,0xfa,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + clgrl %r0,foo + clgrl %r15,foo + +#CHECK: clgrl %r3, bar+100 # encoding: [0xc6,0x3a,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: clgrl %r4, bar+100 # encoding: [0xc6,0x4a,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + clgrl %r3,bar+100 + clgrl %r4,bar+100 + +#CHECK: clgrl %r7, frob@PLT # encoding: [0xc6,0x7a,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: clgrl %r8, frob@PLT # encoding: [0xc6,0x8a,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + clgrl %r7,frob@PLT + clgrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-clhhsi-01.s b/test/MC/SystemZ/insn-clhhsi-01.s new file mode 100644 index 000000000000..ae72ffa018ad --- /dev/null +++ b/test/MC/SystemZ/insn-clhhsi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clhhsi 0, 0 # encoding: [0xe5,0x55,0x00,0x00,0x00,0x00] +#CHECK: clhhsi 4095, 0 # encoding: [0xe5,0x55,0x0f,0xff,0x00,0x00] +#CHECK: clhhsi 0, 65535 # encoding: [0xe5,0x55,0x00,0x00,0xff,0xff] +#CHECK: clhhsi 0(%r1), 42 # encoding: [0xe5,0x55,0x10,0x00,0x00,0x2a] +#CHECK: clhhsi 0(%r15), 42 # encoding: [0xe5,0x55,0xf0,0x00,0x00,0x2a] +#CHECK: clhhsi 4095(%r1), 42 # encoding: [0xe5,0x55,0x1f,0xff,0x00,0x2a] +#CHECK: clhhsi 4095(%r15), 42 # encoding: [0xe5,0x55,0xff,0xff,0x00,0x2a] + + clhhsi 0, 0 + clhhsi 4095, 0 + clhhsi 0, 65535 + clhhsi 0(%r1), 42 + clhhsi 0(%r15), 42 + clhhsi 4095(%r1), 42 + clhhsi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-clhhsi-02.s b/test/MC/SystemZ/insn-clhhsi-02.s new file mode 100644 index 000000000000..bbdf7cd0da6c --- /dev/null +++ b/test/MC/SystemZ/insn-clhhsi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: clhhsi -1, 0 +#CHECK: error: invalid operand +#CHECK: clhhsi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: clhhsi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: clhhsi 0, -1 +#CHECK: error: invalid operand +#CHECK: clhhsi 0, 65536 + + clhhsi -1, 0 + clhhsi 4096, 0 + clhhsi 0(%r1,%r2), 0 + clhhsi 0, -1 + clhhsi 0, 65536 diff --git a/test/MC/SystemZ/insn-clhrl-01.s b/test/MC/SystemZ/insn-clhrl-01.s new file mode 100644 index 000000000000..b424de8f6678 --- /dev/null +++ b/test/MC/SystemZ/insn-clhrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clhrl %r0, 2864434397 # encoding: [0xc6,0x07,0x55,0x5d,0xe6,0x6e] +#CHECK: clhrl %r15, 2864434397 # encoding: [0xc6,0xf7,0x55,0x5d,0xe6,0x6e] + + clhrl %r0,0xaabbccdd + clhrl %r15,0xaabbccdd + +#CHECK: clhrl %r0, foo # encoding: [0xc6,0x07,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: clhrl %r15, foo # encoding: [0xc6,0xf7,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + clhrl %r0,foo + clhrl %r15,foo + +#CHECK: clhrl %r3, bar+100 # encoding: [0xc6,0x37,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: clhrl %r4, bar+100 # encoding: [0xc6,0x47,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + clhrl %r3,bar+100 + clhrl %r4,bar+100 + +#CHECK: clhrl %r7, frob@PLT # encoding: [0xc6,0x77,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: clhrl %r8, frob@PLT # encoding: [0xc6,0x87,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + clhrl %r7,frob@PLT + clhrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cli-01.s b/test/MC/SystemZ/insn-cli-01.s new file mode 100644 index 000000000000..23bccfab4b79 --- /dev/null +++ b/test/MC/SystemZ/insn-cli-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cli 0, 0 # encoding: [0x95,0x00,0x00,0x00] +#CHECK: cli 4095, 0 # encoding: [0x95,0x00,0x0f,0xff] +#CHECK: cli 0, 255 # encoding: [0x95,0xff,0x00,0x00] +#CHECK: cli 0(%r1), 42 # encoding: [0x95,0x2a,0x10,0x00] +#CHECK: cli 0(%r15), 42 # encoding: [0x95,0x2a,0xf0,0x00] +#CHECK: cli 4095(%r1), 42 # encoding: [0x95,0x2a,0x1f,0xff] +#CHECK: cli 4095(%r15), 42 # encoding: [0x95,0x2a,0xff,0xff] + + cli 0, 0 + cli 4095, 0 + cli 0, 255 + cli 0(%r1), 42 + cli 0(%r15), 42 + cli 4095(%r1), 42 + cli 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-cli-02.s b/test/MC/SystemZ/insn-cli-02.s new file mode 100644 index 000000000000..7fe6fdabfd32 --- /dev/null +++ b/test/MC/SystemZ/insn-cli-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cli -1, 0 +#CHECK: error: invalid operand +#CHECK: cli 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cli 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: cli 0, -1 +#CHECK: error: invalid operand +#CHECK: cli 0, 256 + + cli -1, 0 + cli 4096, 0 + cli 0(%r1,%r2), 0 + cli 0, -1 + cli 0, 256 diff --git a/test/MC/SystemZ/insn-cliy-01.s b/test/MC/SystemZ/insn-cliy-01.s new file mode 100644 index 000000000000..1a26f605d8b1 --- /dev/null +++ b/test/MC/SystemZ/insn-cliy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cliy -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x55] +#CHECK: cliy -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x55] +#CHECK: cliy 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x55] +#CHECK: cliy 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x55] +#CHECK: cliy 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x55] +#CHECK: cliy 0, 255 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x55] +#CHECK: cliy 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x55] +#CHECK: cliy 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x55] +#CHECK: cliy 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x55] +#CHECK: cliy 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x55] + + cliy -524288, 0 + cliy -1, 0 + cliy 0, 0 + cliy 1, 0 + cliy 524287, 0 + cliy 0, 255 + cliy 0(%r1), 42 + cliy 0(%r15), 42 + cliy 524287(%r1), 42 + cliy 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-cliy-02.s b/test/MC/SystemZ/insn-cliy-02.s new file mode 100644 index 000000000000..3e8056315d78 --- /dev/null +++ b/test/MC/SystemZ/insn-cliy-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cliy -524289, 0 +#CHECK: error: invalid operand +#CHECK: cliy 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: cliy 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: cliy 0, -1 +#CHECK: error: invalid operand +#CHECK: cliy 0, 256 + + cliy -524289, 0 + cliy 524288, 0 + cliy 0(%r1,%r2), 0 + cliy 0, -1 + cliy 0, 256 diff --git a/test/MC/SystemZ/insn-clr-01.s b/test/MC/SystemZ/insn-clr-01.s new file mode 100644 index 000000000000..d187d4e3e823 --- /dev/null +++ b/test/MC/SystemZ/insn-clr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clr %r0, %r0 # encoding: [0x15,0x00] +#CHECK: clr %r0, %r15 # encoding: [0x15,0x0f] +#CHECK: clr %r15, %r0 # encoding: [0x15,0xf0] +#CHECK: clr %r7, %r8 # encoding: [0x15,0x78] + + clr %r0,%r0 + clr %r0,%r15 + clr %r15,%r0 + clr %r7,%r8 diff --git a/test/MC/SystemZ/insn-clrl-01.s b/test/MC/SystemZ/insn-clrl-01.s new file mode 100644 index 000000000000..4c6e649b439d --- /dev/null +++ b/test/MC/SystemZ/insn-clrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: clrl %r0, 2864434397 # encoding: [0xc6,0x0f,0x55,0x5d,0xe6,0x6e] +#CHECK: clrl %r15, 2864434397 # encoding: [0xc6,0xff,0x55,0x5d,0xe6,0x6e] + + clrl %r0,0xaabbccdd + clrl %r15,0xaabbccdd + +#CHECK: clrl %r0, foo # encoding: [0xc6,0x0f,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: clrl %r15, foo # encoding: [0xc6,0xff,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + clrl %r0,foo + clrl %r15,foo + +#CHECK: clrl %r3, bar+100 # encoding: [0xc6,0x3f,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: clrl %r4, bar+100 # encoding: [0xc6,0x4f,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + clrl %r3,bar+100 + clrl %r4,bar+100 + +#CHECK: clrl %r7, frob@PLT # encoding: [0xc6,0x7f,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: clrl %r8, frob@PLT # encoding: [0xc6,0x8f,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + clrl %r7,frob@PLT + clrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cly-01.s b/test/MC/SystemZ/insn-cly-01.s new file mode 100644 index 000000000000..8fb4af683e60 --- /dev/null +++ b/test/MC/SystemZ/insn-cly-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cly %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x55] +#CHECK: cly %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x55] +#CHECK: cly %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x55] +#CHECK: cly %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x55] +#CHECK: cly %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x55] +#CHECK: cly %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x55] +#CHECK: cly %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x55] +#CHECK: cly %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x55] +#CHECK: cly %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x55] +#CHECK: cly %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x55] + + cly %r0, -524288 + cly %r0, -1 + cly %r0, 0 + cly %r0, 1 + cly %r0, 524287 + cly %r0, 0(%r1) + cly %r0, 0(%r15) + cly %r0, 524287(%r1,%r15) + cly %r0, 524287(%r15,%r1) + cly %r15, 0 diff --git a/test/MC/SystemZ/insn-cly-02.s b/test/MC/SystemZ/insn-cly-02.s new file mode 100644 index 000000000000..23f37a96cc4a --- /dev/null +++ b/test/MC/SystemZ/insn-cly-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cly %r0, -524289 +#CHECK: error: invalid operand +#CHECK: cly %r0, 524288 + + cly %r0, -524289 + cly %r0, 524288 diff --git a/test/MC/SystemZ/insn-cpsdr-01.s b/test/MC/SystemZ/insn-cpsdr-01.s new file mode 100644 index 000000000000..23d773dfc9c7 --- /dev/null +++ b/test/MC/SystemZ/insn-cpsdr-01.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cpsdr %f0, %f0, %f0 # encoding: [0xb3,0x72,0x00,0x00] +#CHECK: cpsdr %f0, %f0, %f15 # encoding: [0xb3,0x72,0x00,0x0f] +#CHECK: cpsdr %f0, %f15, %f0 # encoding: [0xb3,0x72,0xf0,0x00] +#CHECK: cpsdr %f15, %f0, %f0 # encoding: [0xb3,0x72,0x00,0xf0] +#CHECK: cpsdr %f1, %f2, %f3 # encoding: [0xb3,0x72,0x20,0x13] +#CHECK: cpsdr %f15, %f15, %f15 # encoding: [0xb3,0x72,0xf0,0xff] + + cpsdr %f0, %f0, %f0 + cpsdr %f0, %f0, %f15 + cpsdr %f0, %f15, %f0 + cpsdr %f15, %f0, %f0 + cpsdr %f1, %f2, %f3 + cpsdr %f15, %f15, %f15 + diff --git a/test/MC/SystemZ/insn-cr-01.s b/test/MC/SystemZ/insn-cr-01.s new file mode 100644 index 000000000000..d77e08513fc3 --- /dev/null +++ b/test/MC/SystemZ/insn-cr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cr %r0, %r0 # encoding: [0x19,0x00] +#CHECK: cr %r0, %r15 # encoding: [0x19,0x0f] +#CHECK: cr %r15, %r0 # encoding: [0x19,0xf0] +#CHECK: cr %r7, %r8 # encoding: [0x19,0x78] + + cr %r0,%r0 + cr %r0,%r15 + cr %r15,%r0 + cr %r7,%r8 diff --git a/test/MC/SystemZ/insn-crl-01.s b/test/MC/SystemZ/insn-crl-01.s new file mode 100644 index 000000000000..2451b4c9f829 --- /dev/null +++ b/test/MC/SystemZ/insn-crl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: crl %r0, 2864434397 # encoding: [0xc6,0x0d,0x55,0x5d,0xe6,0x6e] +#CHECK: crl %r15, 2864434397 # encoding: [0xc6,0xfd,0x55,0x5d,0xe6,0x6e] + + crl %r0,0xaabbccdd + crl %r15,0xaabbccdd + +#CHECK: crl %r0, foo # encoding: [0xc6,0x0d,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: crl %r15, foo # encoding: [0xc6,0xfd,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + crl %r0,foo + crl %r15,foo + +#CHECK: crl %r3, bar+100 # encoding: [0xc6,0x3d,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: crl %r4, bar+100 # encoding: [0xc6,0x4d,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + crl %r3,bar+100 + crl %r4,bar+100 + +#CHECK: crl %r7, frob@PLT # encoding: [0xc6,0x7d,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: crl %r8, frob@PLT # encoding: [0xc6,0x8d,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + crl %r7,frob@PLT + crl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-cs-01.s b/test/MC/SystemZ/insn-cs-01.s new file mode 100644 index 000000000000..3fc6c34b7404 --- /dev/null +++ b/test/MC/SystemZ/insn-cs-01.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cs %r0, %r0, 0 # encoding: [0xba,0x00,0x00,0x00] +#CHECK: cs %r0, %r0, 4095 # encoding: [0xba,0x00,0x0f,0xff] +#CHECK: cs %r0, %r0, 0(%r1) # encoding: [0xba,0x00,0x10,0x00] +#CHECK: cs %r0, %r0, 0(%r15) # encoding: [0xba,0x00,0xf0,0x00] +#CHECK: cs %r0, %r0, 4095(%r1) # encoding: [0xba,0x00,0x1f,0xff] +#CHECK: cs %r0, %r0, 4095(%r15) # encoding: [0xba,0x00,0xff,0xff] +#CHECK: cs %r0, %r15, 0 # encoding: [0xba,0x0f,0x00,0x00] +#CHECK: cs %r15, %r0, 0 # encoding: [0xba,0xf0,0x00,0x00] + + cs %r0, %r0, 0 + cs %r0, %r0, 4095 + cs %r0, %r0, 0(%r1) + cs %r0, %r0, 0(%r15) + cs %r0, %r0, 4095(%r1) + cs %r0, %r0, 4095(%r15) + cs %r0, %r15, 0 + cs %r15, %r0, 0 diff --git a/test/MC/SystemZ/insn-cs-02.s b/test/MC/SystemZ/insn-cs-02.s new file mode 100644 index 000000000000..c22795998dd2 --- /dev/null +++ b/test/MC/SystemZ/insn-cs-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cs %r0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: cs %r0, %r0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: cs %r0, %r0, 0(%r1,%r2) + + cs %r0, %r0, -1 + cs %r0, %r0, 4096 + cs %r0, %r0, 0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-csg-01.s b/test/MC/SystemZ/insn-csg-01.s new file mode 100644 index 000000000000..b0fcfa6450a3 --- /dev/null +++ b/test/MC/SystemZ/insn-csg-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: csg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x30] +#CHECK: csg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x30] +#CHECK: csg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x30] +#CHECK: csg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x30] +#CHECK: csg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x30] +#CHECK: csg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x30] +#CHECK: csg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x30] +#CHECK: csg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x30] +#CHECK: csg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x30] +#CHECK: csg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x30] +#CHECK: csg %r15, %r0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0x30] + + csg %r0, %r0, -524288 + csg %r0, %r0, -1 + csg %r0, %r0, 0 + csg %r0, %r0, 1 + csg %r0, %r0, 524287 + csg %r0, %r0, 0(%r1) + csg %r0, %r0, 0(%r15) + csg %r0, %r0, 524287(%r1) + csg %r0, %r0, 524287(%r15) + csg %r0, %r15, 0 + csg %r15, %r0, 0 diff --git a/test/MC/SystemZ/insn-csg-02.s b/test/MC/SystemZ/insn-csg-02.s new file mode 100644 index 000000000000..816b155930bb --- /dev/null +++ b/test/MC/SystemZ/insn-csg-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: csg %r0, %r0, -524289 +#CHECK: error: invalid operand +#CHECK: csg %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: csg %r0, %r0, 0(%r1,%r2) + + csg %r0, %r0, -524289 + csg %r0, %r0, 524288 + csg %r0, %r0, 0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-csy-01.s b/test/MC/SystemZ/insn-csy-01.s new file mode 100644 index 000000000000..d19b2df703c3 --- /dev/null +++ b/test/MC/SystemZ/insn-csy-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: csy %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x14] +#CHECK: csy %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x14] +#CHECK: csy %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x14] +#CHECK: csy %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x14] +#CHECK: csy %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x14] +#CHECK: csy %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x14] +#CHECK: csy %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x14] +#CHECK: csy %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x14] +#CHECK: csy %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x14] +#CHECK: csy %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x14] +#CHECK: csy %r15, %r0, 0 # encoding: [0xeb,0xf0,0x00,0x00,0x00,0x14] + + csy %r0, %r0, -524288 + csy %r0, %r0, -1 + csy %r0, %r0, 0 + csy %r0, %r0, 1 + csy %r0, %r0, 524287 + csy %r0, %r0, 0(%r1) + csy %r0, %r0, 0(%r15) + csy %r0, %r0, 524287(%r1) + csy %r0, %r0, 524287(%r15) + csy %r0, %r15, 0 + csy %r15, %r0, 0 diff --git a/test/MC/SystemZ/insn-csy-02.s b/test/MC/SystemZ/insn-csy-02.s new file mode 100644 index 000000000000..3ff795909b43 --- /dev/null +++ b/test/MC/SystemZ/insn-csy-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: csy %r0, %r0, -524289 +#CHECK: error: invalid operand +#CHECK: csy %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: csy %r0, %r0, 0(%r1,%r2) + + csy %r0, %r0, -524289 + csy %r0, %r0, 524288 + csy %r0, %r0, 0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-cxbr-01.s b/test/MC/SystemZ/insn-cxbr-01.s new file mode 100644 index 000000000000..79527f0c5033 --- /dev/null +++ b/test/MC/SystemZ/insn-cxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cxbr %f0, %f0 # encoding: [0xb3,0x49,0x00,0x00] +#CHECK: cxbr %f0, %f13 # encoding: [0xb3,0x49,0x00,0x0d] +#CHECK: cxbr %f8, %f8 # encoding: [0xb3,0x49,0x00,0x88] +#CHECK: cxbr %f13, %f0 # encoding: [0xb3,0x49,0x00,0xd0] + + cxbr %f0, %f0 + cxbr %f0, %f13 + cxbr %f8, %f8 + cxbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-cxbr-02.s b/test/MC/SystemZ/insn-cxbr-02.s new file mode 100644 index 000000000000..7aaca91c5f22 --- /dev/null +++ b/test/MC/SystemZ/insn-cxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: cxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: cxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: cxbr %f14, %f0 + + cxbr %f0, %f2 + cxbr %f0, %f14 + cxbr %f2, %f0 + cxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-cxfbr-01.s b/test/MC/SystemZ/insn-cxfbr-01.s new file mode 100644 index 000000000000..14bafd12071d --- /dev/null +++ b/test/MC/SystemZ/insn-cxfbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cxfbr %f0, %r0 # encoding: [0xb3,0x96,0x00,0x00] +#CHECK: cxfbr %f0, %r15 # encoding: [0xb3,0x96,0x00,0x0f] +#CHECK: cxfbr %f13, %r0 # encoding: [0xb3,0x96,0x00,0xd0] +#CHECK: cxfbr %f8, %r7 # encoding: [0xb3,0x96,0x00,0x87] +#CHECK: cxfbr %f13, %r15 # encoding: [0xb3,0x96,0x00,0xdf] + + cxfbr %f0, %r0 + cxfbr %f0, %r15 + cxfbr %f13, %r0 + cxfbr %f8, %r7 + cxfbr %f13, %r15 diff --git a/test/MC/SystemZ/insn-cxfbr-02.s b/test/MC/SystemZ/insn-cxfbr-02.s new file mode 100644 index 000000000000..5343378569c1 --- /dev/null +++ b/test/MC/SystemZ/insn-cxfbr-02.s @@ -0,0 +1,22 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cxfbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cxfbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cxfbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cxfbr %a0, %r0 +#CHECK: error: invalid register +#CHECK: cxfbr %f2, %r0 +#CHECK: error: invalid register +#CHECK: cxfbr %f14, %r0 + + cxfbr %r0, %r0 + cxfbr %f0, %f0 + cxfbr %f0, %a0 + cxfbr %a0, %r0 + cxfbr %f2, %r0 + cxfbr %f14, %r0 diff --git a/test/MC/SystemZ/insn-cxgbr-01.s b/test/MC/SystemZ/insn-cxgbr-01.s new file mode 100644 index 000000000000..90914b44e9a2 --- /dev/null +++ b/test/MC/SystemZ/insn-cxgbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cxgbr %f0, %r0 # encoding: [0xb3,0xa6,0x00,0x00] +#CHECK: cxgbr %f0, %r15 # encoding: [0xb3,0xa6,0x00,0x0f] +#CHECK: cxgbr %f13, %r0 # encoding: [0xb3,0xa6,0x00,0xd0] +#CHECK: cxgbr %f8, %r7 # encoding: [0xb3,0xa6,0x00,0x87] +#CHECK: cxgbr %f13, %r15 # encoding: [0xb3,0xa6,0x00,0xdf] + + cxgbr %f0, %r0 + cxgbr %f0, %r15 + cxgbr %f13, %r0 + cxgbr %f8, %r7 + cxgbr %f13, %r15 diff --git a/test/MC/SystemZ/insn-cxgbr-02.s b/test/MC/SystemZ/insn-cxgbr-02.s new file mode 100644 index 000000000000..d10664dba7c2 --- /dev/null +++ b/test/MC/SystemZ/insn-cxgbr-02.s @@ -0,0 +1,22 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: cxgbr %r0, %r0 +#CHECK: error: invalid register +#CHECK: cxgbr %f0, %f0 +#CHECK: error: invalid register +#CHECK: cxgbr %f0, %a0 +#CHECK: error: invalid register +#CHECK: cxgbr %a0, %r0 +#CHECK: error: invalid register +#CHECK: cxgbr %f2, %r0 +#CHECK: error: invalid register +#CHECK: cxgbr %f14, %r0 + + cxgbr %r0, %r0 + cxgbr %f0, %f0 + cxgbr %f0, %a0 + cxgbr %a0, %r0 + cxgbr %f2, %r0 + cxgbr %f14, %r0 diff --git a/test/MC/SystemZ/insn-cy-01.s b/test/MC/SystemZ/insn-cy-01.s new file mode 100644 index 000000000000..5f21b963ff90 --- /dev/null +++ b/test/MC/SystemZ/insn-cy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: cy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x59] +#CHECK: cy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x59] +#CHECK: cy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x59] +#CHECK: cy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x59] +#CHECK: cy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x59] +#CHECK: cy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x59] +#CHECK: cy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x59] +#CHECK: cy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x59] +#CHECK: cy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x59] +#CHECK: cy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x59] + + cy %r0, -524288 + cy %r0, -1 + cy %r0, 0 + cy %r0, 1 + cy %r0, 524287 + cy %r0, 0(%r1) + cy %r0, 0(%r15) + cy %r0, 524287(%r1,%r15) + cy %r0, 524287(%r15,%r1) + cy %r15, 0 diff --git a/test/MC/SystemZ/insn-cy-02.s b/test/MC/SystemZ/insn-cy-02.s new file mode 100644 index 000000000000..1c996cdced35 --- /dev/null +++ b/test/MC/SystemZ/insn-cy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: cy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: cy %r0, 524288 + + cy %r0, -524289 + cy %r0, 524288 diff --git a/test/MC/SystemZ/insn-ddb-01.s b/test/MC/SystemZ/insn-ddb-01.s new file mode 100644 index 000000000000..417af11c08ae --- /dev/null +++ b/test/MC/SystemZ/insn-ddb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ddb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1d] +#CHECK: ddb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1d] +#CHECK: ddb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1d] +#CHECK: ddb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1d] +#CHECK: ddb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1d] +#CHECK: ddb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1d] +#CHECK: ddb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1d] + + ddb %f0, 0 + ddb %f0, 4095 + ddb %f0, 0(%r1) + ddb %f0, 0(%r15) + ddb %f0, 4095(%r1,%r15) + ddb %f0, 4095(%r15,%r1) + ddb %f15, 0 diff --git a/test/MC/SystemZ/insn-ddb-02.s b/test/MC/SystemZ/insn-ddb-02.s new file mode 100644 index 000000000000..c6357d10e429 --- /dev/null +++ b/test/MC/SystemZ/insn-ddb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ddb %f0, -1 +#CHECK: error: invalid operand +#CHECK: ddb %f0, 4096 + + ddb %f0, -1 + ddb %f0, 4096 diff --git a/test/MC/SystemZ/insn-ddbr-01.s b/test/MC/SystemZ/insn-ddbr-01.s new file mode 100644 index 000000000000..7ee1fee5b375 --- /dev/null +++ b/test/MC/SystemZ/insn-ddbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ddbr %f0, %f0 # encoding: [0xb3,0x1d,0x00,0x00] +#CHECK: ddbr %f0, %f15 # encoding: [0xb3,0x1d,0x00,0x0f] +#CHECK: ddbr %f7, %f8 # encoding: [0xb3,0x1d,0x00,0x78] +#CHECK: ddbr %f15, %f0 # encoding: [0xb3,0x1d,0x00,0xf0] + + ddbr %f0, %f0 + ddbr %f0, %f15 + ddbr %f7, %f8 + ddbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-deb-01.s b/test/MC/SystemZ/insn-deb-01.s new file mode 100644 index 000000000000..93cfb024648c --- /dev/null +++ b/test/MC/SystemZ/insn-deb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: deb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0d] +#CHECK: deb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0d] +#CHECK: deb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0d] +#CHECK: deb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0d] +#CHECK: deb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0d] +#CHECK: deb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0d] +#CHECK: deb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0d] + + deb %f0, 0 + deb %f0, 4095 + deb %f0, 0(%r1) + deb %f0, 0(%r15) + deb %f0, 4095(%r1,%r15) + deb %f0, 4095(%r15,%r1) + deb %f15, 0 diff --git a/test/MC/SystemZ/insn-deb-02.s b/test/MC/SystemZ/insn-deb-02.s new file mode 100644 index 000000000000..e4edd4ef86d1 --- /dev/null +++ b/test/MC/SystemZ/insn-deb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: deb %f0, -1 +#CHECK: error: invalid operand +#CHECK: deb %f0, 4096 + + deb %f0, -1 + deb %f0, 4096 diff --git a/test/MC/SystemZ/insn-debr-01.s b/test/MC/SystemZ/insn-debr-01.s new file mode 100644 index 000000000000..02ee16c9cf44 --- /dev/null +++ b/test/MC/SystemZ/insn-debr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: debr %f0, %f0 # encoding: [0xb3,0x0d,0x00,0x00] +#CHECK: debr %f0, %f15 # encoding: [0xb3,0x0d,0x00,0x0f] +#CHECK: debr %f7, %f8 # encoding: [0xb3,0x0d,0x00,0x78] +#CHECK: debr %f15, %f0 # encoding: [0xb3,0x0d,0x00,0xf0] + + debr %f0, %f0 + debr %f0, %f15 + debr %f7, %f8 + debr %f15, %f0 diff --git a/test/MC/SystemZ/insn-dl-01.s b/test/MC/SystemZ/insn-dl-01.s new file mode 100644 index 000000000000..50b24e7a00da --- /dev/null +++ b/test/MC/SystemZ/insn-dl-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dl %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x97] +#CHECK: dl %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x97] +#CHECK: dl %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x97] +#CHECK: dl %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x97] +#CHECK: dl %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x97] +#CHECK: dl %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x97] +#CHECK: dl %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x97] +#CHECK: dl %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x97] +#CHECK: dl %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x97] +#CHECK: dl %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x97] + + dl %r0, -524288 + dl %r0, -1 + dl %r0, 0 + dl %r0, 1 + dl %r0, 524287 + dl %r0, 0(%r1) + dl %r0, 0(%r15) + dl %r0, 524287(%r1,%r15) + dl %r0, 524287(%r15,%r1) + dl %r14, 0 diff --git a/test/MC/SystemZ/insn-dl-02.s b/test/MC/SystemZ/insn-dl-02.s new file mode 100644 index 000000000000..8f9f37320b86 --- /dev/null +++ b/test/MC/SystemZ/insn-dl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: dl %r0, -524289 +#CHECK: error: invalid operand +#CHECK: dl %r0, 524288 +#CHECK: error: invalid register +#CHECK: dl %r1, 0 +#CHECK: error: invalid register +#CHECK: dl %r15, 0 + + dl %r0, -524289 + dl %r0, 524288 + dl %r1, 0 + dl %r15, 0 diff --git a/test/MC/SystemZ/insn-dlg-01.s b/test/MC/SystemZ/insn-dlg-01.s new file mode 100644 index 000000000000..8a304f828ec8 --- /dev/null +++ b/test/MC/SystemZ/insn-dlg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dlg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x87] +#CHECK: dlg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x87] +#CHECK: dlg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x87] +#CHECK: dlg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x87] +#CHECK: dlg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x87] +#CHECK: dlg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x87] +#CHECK: dlg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x87] +#CHECK: dlg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x87] +#CHECK: dlg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x87] +#CHECK: dlg %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x87] + + dlg %r0, -524288 + dlg %r0, -1 + dlg %r0, 0 + dlg %r0, 1 + dlg %r0, 524287 + dlg %r0, 0(%r1) + dlg %r0, 0(%r15) + dlg %r0, 524287(%r1,%r15) + dlg %r0, 524287(%r15,%r1) + dlg %r14, 0 diff --git a/test/MC/SystemZ/insn-dlg-02.s b/test/MC/SystemZ/insn-dlg-02.s new file mode 100644 index 000000000000..cbed8981732f --- /dev/null +++ b/test/MC/SystemZ/insn-dlg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: dlg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: dlg %r0, 524288 +#CHECK: error: invalid register +#CHECK: dlg %r1, 0 +#CHECK: error: invalid register +#CHECK: dlg %r15, 0 + + dlg %r0, -524289 + dlg %r0, 524288 + dlg %r1, 0 + dlg %r15, 0 diff --git a/test/MC/SystemZ/insn-dlgr-01.s b/test/MC/SystemZ/insn-dlgr-01.s new file mode 100644 index 000000000000..b2a4de5f91f3 --- /dev/null +++ b/test/MC/SystemZ/insn-dlgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dlgr %r0, %r0 # encoding: [0xb9,0x87,0x00,0x00] +#CHECK: dlgr %r0, %r15 # encoding: [0xb9,0x87,0x00,0x0f] +#CHECK: dlgr %r14, %r0 # encoding: [0xb9,0x87,0x00,0xe0] +#CHECK: dlgr %r6, %r9 # encoding: [0xb9,0x87,0x00,0x69] + + dlgr %r0,%r0 + dlgr %r0,%r15 + dlgr %r14,%r0 + dlgr %r6,%r9 diff --git a/test/MC/SystemZ/insn-dlgr-02.s b/test/MC/SystemZ/insn-dlgr-02.s new file mode 100644 index 000000000000..c407b4fb0bf8 --- /dev/null +++ b/test/MC/SystemZ/insn-dlgr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dlgr %r1, %r0 +#CHECK: error: invalid register +#CHECK: dlgr %r15, %r0 + + dlgr %r1, %r0 + dlgr %r15, %r0 diff --git a/test/MC/SystemZ/insn-dlr-01.s b/test/MC/SystemZ/insn-dlr-01.s new file mode 100644 index 000000000000..7e8be79e46aa --- /dev/null +++ b/test/MC/SystemZ/insn-dlr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00] +#CHECK: dlr %r0, %r15 # encoding: [0xb9,0x97,0x00,0x0f] +#CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0] +#CHECK: dlr %r6, %r9 # encoding: [0xb9,0x97,0x00,0x69] + + dlr %r0,%r0 + dlr %r0,%r15 + dlr %r14,%r0 + dlr %r6,%r9 diff --git a/test/MC/SystemZ/insn-dlr-02.s b/test/MC/SystemZ/insn-dlr-02.s new file mode 100644 index 000000000000..eb31e18fd876 --- /dev/null +++ b/test/MC/SystemZ/insn-dlr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dlr %r1, %r0 +#CHECK: error: invalid register +#CHECK: dlr %r15, %r0 + + dlr %r1, %r0 + dlr %r15, %r0 diff --git a/test/MC/SystemZ/insn-dsg-01.s b/test/MC/SystemZ/insn-dsg-01.s new file mode 100644 index 000000000000..5cd0b40a9fb1 --- /dev/null +++ b/test/MC/SystemZ/insn-dsg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dsg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0d] +#CHECK: dsg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0d] +#CHECK: dsg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0d] +#CHECK: dsg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0d] +#CHECK: dsg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0d] +#CHECK: dsg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0d] +#CHECK: dsg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0d] +#CHECK: dsg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0d] +#CHECK: dsg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0d] +#CHECK: dsg %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x0d] + + dsg %r0, -524288 + dsg %r0, -1 + dsg %r0, 0 + dsg %r0, 1 + dsg %r0, 524287 + dsg %r0, 0(%r1) + dsg %r0, 0(%r15) + dsg %r0, 524287(%r1,%r15) + dsg %r0, 524287(%r15,%r1) + dsg %r14, 0 diff --git a/test/MC/SystemZ/insn-dsg-02.s b/test/MC/SystemZ/insn-dsg-02.s new file mode 100644 index 000000000000..16979418c48b --- /dev/null +++ b/test/MC/SystemZ/insn-dsg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: dsg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: dsg %r0, 524288 +#CHECK: error: invalid register +#CHECK: dsg %r1, 0 +#CHECK: error: invalid register +#CHECK: dsg %r15, 0 + + dsg %r0, -524289 + dsg %r0, 524288 + dsg %r1, 0 + dsg %r15, 0 diff --git a/test/MC/SystemZ/insn-dsgf-01.s b/test/MC/SystemZ/insn-dsgf-01.s new file mode 100644 index 000000000000..2cde0c79d9d4 --- /dev/null +++ b/test/MC/SystemZ/insn-dsgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dsgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1d] +#CHECK: dsgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1d] +#CHECK: dsgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1d] +#CHECK: dsgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1d] +#CHECK: dsgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1d] +#CHECK: dsgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1d] +#CHECK: dsgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1d] +#CHECK: dsgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x1d] +#CHECK: dsgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x1d] +#CHECK: dsgf %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x1d] + + dsgf %r0, -524288 + dsgf %r0, -1 + dsgf %r0, 0 + dsgf %r0, 1 + dsgf %r0, 524287 + dsgf %r0, 0(%r1) + dsgf %r0, 0(%r15) + dsgf %r0, 524287(%r1,%r15) + dsgf %r0, 524287(%r15,%r1) + dsgf %r14, 0 diff --git a/test/MC/SystemZ/insn-dsgf-02.s b/test/MC/SystemZ/insn-dsgf-02.s new file mode 100644 index 000000000000..253d9ad70be5 --- /dev/null +++ b/test/MC/SystemZ/insn-dsgf-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: dsgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: dsgf %r0, 524288 +#CHECK: error: invalid register +#CHECK: dsgf %r1, 0 +#CHECK: error: invalid register +#CHECK: dsgf %r15, 0 + + dsgf %r0, -524289 + dsgf %r0, 524288 + dsgf %r1, 0 + dsgf %r15, 0 diff --git a/test/MC/SystemZ/insn-dsgfr-01.s b/test/MC/SystemZ/insn-dsgfr-01.s new file mode 100644 index 000000000000..9b61550ffcbf --- /dev/null +++ b/test/MC/SystemZ/insn-dsgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dsgfr %r0, %r0 # encoding: [0xb9,0x1d,0x00,0x00] +#CHECK: dsgfr %r0, %r15 # encoding: [0xb9,0x1d,0x00,0x0f] +#CHECK: dsgfr %r14, %r0 # encoding: [0xb9,0x1d,0x00,0xe0] +#CHECK: dsgfr %r6, %r9 # encoding: [0xb9,0x1d,0x00,0x69] + + dsgfr %r0,%r0 + dsgfr %r0,%r15 + dsgfr %r14,%r0 + dsgfr %r6,%r9 diff --git a/test/MC/SystemZ/insn-dsgfr-02.s b/test/MC/SystemZ/insn-dsgfr-02.s new file mode 100644 index 000000000000..2eb8b2394723 --- /dev/null +++ b/test/MC/SystemZ/insn-dsgfr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dsgfr %r1, %r0 +#CHECK: error: invalid register +#CHECK: dsgfr %r15, %r0 + + dsgfr %r1, %r0 + dsgfr %r15, %r0 diff --git a/test/MC/SystemZ/insn-dsgr-01.s b/test/MC/SystemZ/insn-dsgr-01.s new file mode 100644 index 000000000000..02b4099cfaa7 --- /dev/null +++ b/test/MC/SystemZ/insn-dsgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dsgr %r0, %r0 # encoding: [0xb9,0x0d,0x00,0x00] +#CHECK: dsgr %r0, %r15 # encoding: [0xb9,0x0d,0x00,0x0f] +#CHECK: dsgr %r14, %r0 # encoding: [0xb9,0x0d,0x00,0xe0] +#CHECK: dsgr %r6, %r9 # encoding: [0xb9,0x0d,0x00,0x69] + + dsgr %r0,%r0 + dsgr %r0,%r15 + dsgr %r14,%r0 + dsgr %r6,%r9 diff --git a/test/MC/SystemZ/insn-dsgr-02.s b/test/MC/SystemZ/insn-dsgr-02.s new file mode 100644 index 000000000000..019429580696 --- /dev/null +++ b/test/MC/SystemZ/insn-dsgr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dsgr %r1, %r0 +#CHECK: error: invalid register +#CHECK: dsgr %r15, %r0 + + dsgr %r1, %r0 + dsgr %r15, %r0 diff --git a/test/MC/SystemZ/insn-dxbr-01.s b/test/MC/SystemZ/insn-dxbr-01.s new file mode 100644 index 000000000000..6a452080ced9 --- /dev/null +++ b/test/MC/SystemZ/insn-dxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dxbr %f0, %f0 # encoding: [0xb3,0x4d,0x00,0x00] +#CHECK: dxbr %f0, %f13 # encoding: [0xb3,0x4d,0x00,0x0d] +#CHECK: dxbr %f8, %f8 # encoding: [0xb3,0x4d,0x00,0x88] +#CHECK: dxbr %f13, %f0 # encoding: [0xb3,0x4d,0x00,0xd0] + + dxbr %f0, %f0 + dxbr %f0, %f13 + dxbr %f8, %f8 + dxbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-dxbr-02.s b/test/MC/SystemZ/insn-dxbr-02.s new file mode 100644 index 000000000000..cac64191b8be --- /dev/null +++ b/test/MC/SystemZ/insn-dxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: dxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: dxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: dxbr %f14, %f0 + + dxbr %f0, %f2 + dxbr %f0, %f14 + dxbr %f2, %f0 + dxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-ear-01.s b/test/MC/SystemZ/insn-ear-01.s new file mode 100644 index 000000000000..f614f86999ba --- /dev/null +++ b/test/MC/SystemZ/insn-ear-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ear %r0, %a0 # encoding: [0xb2,0x4f,0x00,0x00] +#CHECK: ear %r0, %a15 # encoding: [0xb2,0x4f,0x00,0x0f] +#CHECK: ear %r15, %a0 # encoding: [0xb2,0x4f,0x00,0xf0] +#CHECK: ear %r7, %a8 # encoding: [0xb2,0x4f,0x00,0x78] +#CHECK: ear %r15, %a15 # encoding: [0xb2,0x4f,0x00,0xff] + + ear %r0, %a0 + ear %r0, %a15 + ear %r15, %a0 + ear %r7, %a8 + ear %r15, %a15 diff --git a/test/MC/SystemZ/insn-ear-02.s b/test/MC/SystemZ/insn-ear-02.s new file mode 100644 index 000000000000..7fb35eaa5353 --- /dev/null +++ b/test/MC/SystemZ/insn-ear-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ear %r0, 0 +#CHECK: error: invalid register +#CHECK: ear %r0, %r0 +#CHECK: error: invalid register +#CHECK: ear %a0, %r0 + + ear %r0, 0 + ear %r0, %r0 + ear %a0, %r0 diff --git a/test/MC/SystemZ/insn-fidbr-01.s b/test/MC/SystemZ/insn-fidbr-01.s new file mode 100644 index 000000000000..e52c91c21142 --- /dev/null +++ b/test/MC/SystemZ/insn-fidbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: fidbr %f0, 0, %f0 # encoding: [0xb3,0x5f,0x00,0x00] +#CHECK: fidbr %f0, 0, %f15 # encoding: [0xb3,0x5f,0x00,0x0f] +#CHECK: fidbr %f0, 15, %f0 # encoding: [0xb3,0x5f,0xf0,0x00] +#CHECK: fidbr %f4, 5, %f6 # encoding: [0xb3,0x5f,0x50,0x46] +#CHECK: fidbr %f15, 0, %f0 # encoding: [0xb3,0x5f,0x00,0xf0] + + fidbr %f0, 0, %f0 + fidbr %f0, 0, %f15 + fidbr %f0, 15, %f0 + fidbr %f4, 5, %f6 + fidbr %f15, 0, %f0 diff --git a/test/MC/SystemZ/insn-fidbr-02.s b/test/MC/SystemZ/insn-fidbr-02.s new file mode 100644 index 000000000000..5a35f46589bc --- /dev/null +++ b/test/MC/SystemZ/insn-fidbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: fidbr %r0, 0, %f0 +#CHECK: error: invalid register +#CHECK: fidbr %f0, 0, %r0 +#CHECK: error: invalid operand +#CHECK: fidbr %f0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: fidbr %f0, 16, %f0 + + fidbr %r0, 0, %f0 + fidbr %f0, 0, %r0 + fidbr %f0, -1, %f0 + fidbr %f0, 16, %f0 diff --git a/test/MC/SystemZ/insn-fiebr-01.s b/test/MC/SystemZ/insn-fiebr-01.s new file mode 100644 index 000000000000..0b4e633a1edc --- /dev/null +++ b/test/MC/SystemZ/insn-fiebr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: fiebr %f0, 0, %f0 # encoding: [0xb3,0x57,0x00,0x00] +#CHECK: fiebr %f0, 0, %f15 # encoding: [0xb3,0x57,0x00,0x0f] +#CHECK: fiebr %f0, 15, %f0 # encoding: [0xb3,0x57,0xf0,0x00] +#CHECK: fiebr %f4, 5, %f6 # encoding: [0xb3,0x57,0x50,0x46] +#CHECK: fiebr %f15, 0, %f0 # encoding: [0xb3,0x57,0x00,0xf0] + + fiebr %f0, 0, %f0 + fiebr %f0, 0, %f15 + fiebr %f0, 15, %f0 + fiebr %f4, 5, %f6 + fiebr %f15, 0, %f0 diff --git a/test/MC/SystemZ/insn-fiebr-02.s b/test/MC/SystemZ/insn-fiebr-02.s new file mode 100644 index 000000000000..2ecdd4d1bc00 --- /dev/null +++ b/test/MC/SystemZ/insn-fiebr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: fiebr %r0, 0, %f0 +#CHECK: error: invalid register +#CHECK: fiebr %f0, 0, %r0 +#CHECK: error: invalid operand +#CHECK: fiebr %f0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: fiebr %f0, 16, %f0 + + fiebr %r0, 0, %f0 + fiebr %f0, 0, %r0 + fiebr %f0, -1, %f0 + fiebr %f0, 16, %f0 diff --git a/test/MC/SystemZ/insn-fixbr-01.s b/test/MC/SystemZ/insn-fixbr-01.s new file mode 100644 index 000000000000..02676ed76d32 --- /dev/null +++ b/test/MC/SystemZ/insn-fixbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: fixbr %f0, 0, %f0 # encoding: [0xb3,0x47,0x00,0x00] +#CHECK: fixbr %f0, 0, %f13 # encoding: [0xb3,0x47,0x00,0x0d] +#CHECK: fixbr %f0, 15, %f0 # encoding: [0xb3,0x47,0xf0,0x00] +#CHECK: fixbr %f4, 5, %f8 # encoding: [0xb3,0x47,0x50,0x48] +#CHECK: fixbr %f13, 0, %f0 # encoding: [0xb3,0x47,0x00,0xd0] + + fixbr %f0, 0, %f0 + fixbr %f0, 0, %f13 + fixbr %f0, 15, %f0 + fixbr %f4, 5, %f8 + fixbr %f13, 0, %f0 diff --git a/test/MC/SystemZ/insn-fixbr-02.s b/test/MC/SystemZ/insn-fixbr-02.s new file mode 100644 index 000000000000..3f6873429208 --- /dev/null +++ b/test/MC/SystemZ/insn-fixbr-02.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: fixbr %r0, 0, %f0 +#CHECK: error: invalid register +#CHECK: fixbr %f0, 0, %r0 +#CHECK: error: invalid operand +#CHECK: fixbr %f0, -1, %f0 +#CHECK: error: invalid operand +#CHECK: fixbr %f0, 16, %f0 +#CHECK: error: invalid register +#CHECK: fixbr %f0, 0, %f2 +#CHECK: error: invalid register +#CHECK: fixbr %f0, 0, %f14 +#CHECK: error: invalid register +#CHECK: fixbr %f2, 0, %f0 +#CHECK: error: invalid register +#CHECK: fixbr %f14, 0, %f0 + + fixbr %r0, 0, %f0 + fixbr %f0, 0, %r0 + fixbr %f0, -1, %f0 + fixbr %f0, 16, %f0 + fixbr %f0, 0, %f2 + fixbr %f0, 0, %f14 + fixbr %f2, 0, %f0 + fixbr %f14, 0, %f0 diff --git a/test/MC/SystemZ/insn-flogr-01.s b/test/MC/SystemZ/insn-flogr-01.s new file mode 100644 index 000000000000..f6031ce3b678 --- /dev/null +++ b/test/MC/SystemZ/insn-flogr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: flogr %r0, %r0 # encoding: [0xb9,0x83,0x00,0x00] +#CHECK: flogr %r0, %r15 # encoding: [0xb9,0x83,0x00,0x0f] +#CHECK: flogr %r10, %r9 # encoding: [0xb9,0x83,0x00,0xa9] +#CHECK: flogr %r14, %r0 # encoding: [0xb9,0x83,0x00,0xe0] + + flogr %r0, %r0 + flogr %r0, %r15 + flogr %r10, %r9 + flogr %r14, %r0 diff --git a/test/MC/SystemZ/insn-flogr-02.s b/test/MC/SystemZ/insn-flogr-02.s new file mode 100644 index 000000000000..e0d117c3be73 --- /dev/null +++ b/test/MC/SystemZ/insn-flogr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: flogr %r1, %r0 +#CHECK: error: invalid register +#CHECK: flogr %r15, %r0 + + flogr %r1, %r0 + flogr %r15, %r0 diff --git a/test/MC/SystemZ/insn-ic-01.s b/test/MC/SystemZ/insn-ic-01.s new file mode 100644 index 000000000000..76772f9d1a08 --- /dev/null +++ b/test/MC/SystemZ/insn-ic-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ic %r0, 0 # encoding: [0x43,0x00,0x00,0x00] +#CHECK: ic %r0, 4095 # encoding: [0x43,0x00,0x0f,0xff] +#CHECK: ic %r0, 0(%r1) # encoding: [0x43,0x00,0x10,0x00] +#CHECK: ic %r0, 0(%r15) # encoding: [0x43,0x00,0xf0,0x00] +#CHECK: ic %r0, 4095(%r1,%r15) # encoding: [0x43,0x01,0xff,0xff] +#CHECK: ic %r0, 4095(%r15,%r1) # encoding: [0x43,0x0f,0x1f,0xff] +#CHECK: ic %r15, 0 # encoding: [0x43,0xf0,0x00,0x00] + + ic %r0, 0 + ic %r0, 4095 + ic %r0, 0(%r1) + ic %r0, 0(%r15) + ic %r0, 4095(%r1,%r15) + ic %r0, 4095(%r15,%r1) + ic %r15, 0 diff --git a/test/MC/SystemZ/insn-ic-02.s b/test/MC/SystemZ/insn-ic-02.s new file mode 100644 index 000000000000..e70ef1c58dbe --- /dev/null +++ b/test/MC/SystemZ/insn-ic-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ic %r0, -1 +#CHECK: error: invalid operand +#CHECK: ic %r0, 4096 + + ic %r0, -1 + ic %r0, 4096 diff --git a/test/MC/SystemZ/insn-icy-01.s b/test/MC/SystemZ/insn-icy-01.s new file mode 100644 index 000000000000..079ae2142f1c --- /dev/null +++ b/test/MC/SystemZ/insn-icy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: icy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x73] +#CHECK: icy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x73] +#CHECK: icy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x73] +#CHECK: icy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x73] +#CHECK: icy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x73] +#CHECK: icy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x73] +#CHECK: icy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x73] +#CHECK: icy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x73] +#CHECK: icy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x73] +#CHECK: icy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x73] + + icy %r0, -524288 + icy %r0, -1 + icy %r0, 0 + icy %r0, 1 + icy %r0, 524287 + icy %r0, 0(%r1) + icy %r0, 0(%r15) + icy %r0, 524287(%r1,%r15) + icy %r0, 524287(%r15,%r1) + icy %r15, 0 diff --git a/test/MC/SystemZ/insn-icy-02.s b/test/MC/SystemZ/insn-icy-02.s new file mode 100644 index 000000000000..321c86f9dfff --- /dev/null +++ b/test/MC/SystemZ/insn-icy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: icy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: icy %r0, 524288 + + icy %r0, -524289 + icy %r0, 524288 diff --git a/test/MC/SystemZ/insn-iihf-01.s b/test/MC/SystemZ/insn-iihf-01.s new file mode 100644 index 000000000000..bf8d48fbc634 --- /dev/null +++ b/test/MC/SystemZ/insn-iihf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iihf %r0, 0 # encoding: [0xc0,0x08,0x00,0x00,0x00,0x00] +#CHECK: iihf %r0, 4294967295 # encoding: [0xc0,0x08,0xff,0xff,0xff,0xff] +#CHECK: iihf %r15, 0 # encoding: [0xc0,0xf8,0x00,0x00,0x00,0x00] + + iihf %r0, 0 + iihf %r0, 0xffffffff + iihf %r15, 0 diff --git a/test/MC/SystemZ/insn-iihf-02.s b/test/MC/SystemZ/insn-iihf-02.s new file mode 100644 index 000000000000..1c7a69addf60 --- /dev/null +++ b/test/MC/SystemZ/insn-iihf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iihf %r0, -1 +#CHECK: error: invalid operand +#CHECK: iihf %r0, 1 << 32 + + iihf %r0, -1 + iihf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-iihh-01.s b/test/MC/SystemZ/insn-iihh-01.s new file mode 100644 index 000000000000..a2ba9a33a456 --- /dev/null +++ b/test/MC/SystemZ/insn-iihh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iihh %r0, 0 # encoding: [0xa5,0x00,0x00,0x00] +#CHECK: iihh %r0, 32768 # encoding: [0xa5,0x00,0x80,0x00] +#CHECK: iihh %r0, 65535 # encoding: [0xa5,0x00,0xff,0xff] +#CHECK: iihh %r15, 0 # encoding: [0xa5,0xf0,0x00,0x00] + + iihh %r0, 0 + iihh %r0, 0x8000 + iihh %r0, 0xffff + iihh %r15, 0 diff --git a/test/MC/SystemZ/insn-iihh-02.s b/test/MC/SystemZ/insn-iihh-02.s new file mode 100644 index 000000000000..2d8f8541dd07 --- /dev/null +++ b/test/MC/SystemZ/insn-iihh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iihh %r0, -1 +#CHECK: error: invalid operand +#CHECK: iihh %r0, 0x10000 + + iihh %r0, -1 + iihh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-iihl-01.s b/test/MC/SystemZ/insn-iihl-01.s new file mode 100644 index 000000000000..ff591e8b8696 --- /dev/null +++ b/test/MC/SystemZ/insn-iihl-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iihl %r0, 0 # encoding: [0xa5,0x01,0x00,0x00] +#CHECK: iihl %r0, 32768 # encoding: [0xa5,0x01,0x80,0x00] +#CHECK: iihl %r0, 65535 # encoding: [0xa5,0x01,0xff,0xff] +#CHECK: iihl %r15, 0 # encoding: [0xa5,0xf1,0x00,0x00] + + iihl %r0, 0 + iihl %r0, 0x8000 + iihl %r0, 0xffff + iihl %r15, 0 diff --git a/test/MC/SystemZ/insn-iihl-02.s b/test/MC/SystemZ/insn-iihl-02.s new file mode 100644 index 000000000000..262955e38d39 --- /dev/null +++ b/test/MC/SystemZ/insn-iihl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iihl %r0, -1 +#CHECK: error: invalid operand +#CHECK: iihl %r0, 0x10000 + + iihl %r0, -1 + iihl %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-iilf-01.s b/test/MC/SystemZ/insn-iilf-01.s new file mode 100644 index 000000000000..228e1476764c --- /dev/null +++ b/test/MC/SystemZ/insn-iilf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iilf %r0, 0 # encoding: [0xc0,0x09,0x00,0x00,0x00,0x00] +#CHECK: iilf %r0, 4294967295 # encoding: [0xc0,0x09,0xff,0xff,0xff,0xff] +#CHECK: iilf %r15, 0 # encoding: [0xc0,0xf9,0x00,0x00,0x00,0x00] + + iilf %r0, 0 + iilf %r0, 0xffffffff + iilf %r15, 0 diff --git a/test/MC/SystemZ/insn-iilf-02.s b/test/MC/SystemZ/insn-iilf-02.s new file mode 100644 index 000000000000..c7571e8f6d17 --- /dev/null +++ b/test/MC/SystemZ/insn-iilf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iilf %r0, -1 +#CHECK: error: invalid operand +#CHECK: iilf %r0, 1 << 32 + + iilf %r0, -1 + iilf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-iilh-01.s b/test/MC/SystemZ/insn-iilh-01.s new file mode 100644 index 000000000000..045ccfe80b66 --- /dev/null +++ b/test/MC/SystemZ/insn-iilh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iilh %r0, 0 # encoding: [0xa5,0x02,0x00,0x00] +#CHECK: iilh %r0, 32768 # encoding: [0xa5,0x02,0x80,0x00] +#CHECK: iilh %r0, 65535 # encoding: [0xa5,0x02,0xff,0xff] +#CHECK: iilh %r15, 0 # encoding: [0xa5,0xf2,0x00,0x00] + + iilh %r0, 0 + iilh %r0, 0x8000 + iilh %r0, 0xffff + iilh %r15, 0 diff --git a/test/MC/SystemZ/insn-iilh-02.s b/test/MC/SystemZ/insn-iilh-02.s new file mode 100644 index 000000000000..af5bdacaff8b --- /dev/null +++ b/test/MC/SystemZ/insn-iilh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iilh %r0, -1 +#CHECK: error: invalid operand +#CHECK: iilh %r0, 0x10000 + + iilh %r0, -1 + iilh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-iill-01.s b/test/MC/SystemZ/insn-iill-01.s new file mode 100644 index 000000000000..bf50eeb0f678 --- /dev/null +++ b/test/MC/SystemZ/insn-iill-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: iill %r0, 0 # encoding: [0xa5,0x03,0x00,0x00] +#CHECK: iill %r0, 32768 # encoding: [0xa5,0x03,0x80,0x00] +#CHECK: iill %r0, 65535 # encoding: [0xa5,0x03,0xff,0xff] +#CHECK: iill %r15, 0 # encoding: [0xa5,0xf3,0x00,0x00] + + iill %r0, 0 + iill %r0, 0x8000 + iill %r0, 0xffff + iill %r15, 0 diff --git a/test/MC/SystemZ/insn-iill-02.s b/test/MC/SystemZ/insn-iill-02.s new file mode 100644 index 000000000000..fe31e44ee66b --- /dev/null +++ b/test/MC/SystemZ/insn-iill-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: iill %r0, -1 +#CHECK: error: invalid operand +#CHECK: iill %r0, 0x10000 + + iill %r0, -1 + iill %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-l-01.s b/test/MC/SystemZ/insn-l-01.s new file mode 100644 index 000000000000..a589116ebf41 --- /dev/null +++ b/test/MC/SystemZ/insn-l-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: l %r0, 0 # encoding: [0x58,0x00,0x00,0x00] +#CHECK: l %r0, 4095 # encoding: [0x58,0x00,0x0f,0xff] +#CHECK: l %r0, 0(%r1) # encoding: [0x58,0x00,0x10,0x00] +#CHECK: l %r0, 0(%r15) # encoding: [0x58,0x00,0xf0,0x00] +#CHECK: l %r0, 4095(%r1,%r15) # encoding: [0x58,0x01,0xff,0xff] +#CHECK: l %r0, 4095(%r15,%r1) # encoding: [0x58,0x0f,0x1f,0xff] +#CHECK: l %r15, 0 # encoding: [0x58,0xf0,0x00,0x00] + + l %r0, 0 + l %r0, 4095 + l %r0, 0(%r1) + l %r0, 0(%r15) + l %r0, 4095(%r1,%r15) + l %r0, 4095(%r15,%r1) + l %r15, 0 diff --git a/test/MC/SystemZ/insn-l-02.s b/test/MC/SystemZ/insn-l-02.s new file mode 100644 index 000000000000..fad96ff6ce2f --- /dev/null +++ b/test/MC/SystemZ/insn-l-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: l %r0, -1 +#CHECK: error: invalid operand +#CHECK: l %r0, 4096 + + l %r0, -1 + l %r0, 4096 diff --git a/test/MC/SystemZ/insn-la-01.s b/test/MC/SystemZ/insn-la-01.s new file mode 100644 index 000000000000..d4776ab58570 --- /dev/null +++ b/test/MC/SystemZ/insn-la-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: la %r0, 0 # encoding: [0x41,0x00,0x00,0x00] +#CHECK: la %r0, 4095 # encoding: [0x41,0x00,0x0f,0xff] +#CHECK: la %r0, 0(%r1) # encoding: [0x41,0x00,0x10,0x00] +#CHECK: la %r0, 0(%r15) # encoding: [0x41,0x00,0xf0,0x00] +#CHECK: la %r0, 4095(%r1,%r15) # encoding: [0x41,0x01,0xff,0xff] +#CHECK: la %r0, 4095(%r15,%r1) # encoding: [0x41,0x0f,0x1f,0xff] +#CHECK: la %r15, 0 # encoding: [0x41,0xf0,0x00,0x00] + + la %r0, 0 + la %r0, 4095 + la %r0, 0(%r1) + la %r0, 0(%r15) + la %r0, 4095(%r1,%r15) + la %r0, 4095(%r15,%r1) + la %r15, 0 diff --git a/test/MC/SystemZ/insn-la-02.s b/test/MC/SystemZ/insn-la-02.s new file mode 100644 index 000000000000..35c1ab04b5ea --- /dev/null +++ b/test/MC/SystemZ/insn-la-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: la %r0, -1 +#CHECK: error: invalid operand +#CHECK: la %r0, 4096 + + la %r0, -1 + la %r0, 4096 diff --git a/test/MC/SystemZ/insn-larl-01.s b/test/MC/SystemZ/insn-larl-01.s new file mode 100644 index 000000000000..3d0f98f562a2 --- /dev/null +++ b/test/MC/SystemZ/insn-larl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: larl %r0, 2864434397 # encoding: [0xc0,0x00,0x55,0x5d,0xe6,0x6e] +#CHECK: larl %r15, 2864434397 # encoding: [0xc0,0xf0,0x55,0x5d,0xe6,0x6e] + + larl %r0,0xaabbccdd + larl %r15,0xaabbccdd + +#CHECK: larl %r0, foo # encoding: [0xc0,0x00,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: larl %r15, foo # encoding: [0xc0,0xf0,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + larl %r0,foo + larl %r15,foo + +#CHECK: larl %r3, bar+100 # encoding: [0xc0,0x30,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: larl %r4, bar+100 # encoding: [0xc0,0x40,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + larl %r3,bar+100 + larl %r4,bar+100 + +#CHECK: larl %r7, frob@PLT # encoding: [0xc0,0x70,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: larl %r8, frob@PLT # encoding: [0xc0,0x80,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + larl %r7,frob@PLT + larl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lay-01.s b/test/MC/SystemZ/insn-lay-01.s new file mode 100644 index 000000000000..daa88288ab56 --- /dev/null +++ b/test/MC/SystemZ/insn-lay-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lay %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x71] +#CHECK: lay %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x71] +#CHECK: lay %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x71] +#CHECK: lay %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x71] +#CHECK: lay %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x71] +#CHECK: lay %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x71] +#CHECK: lay %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x71] +#CHECK: lay %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x71] +#CHECK: lay %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x71] +#CHECK: lay %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x71] + + lay %r0, -524288 + lay %r0, -1 + lay %r0, 0 + lay %r0, 1 + lay %r0, 524287 + lay %r0, 0(%r1) + lay %r0, 0(%r15) + lay %r0, 524287(%r1,%r15) + lay %r0, 524287(%r15,%r1) + lay %r15, 0 diff --git a/test/MC/SystemZ/insn-lay-02.s b/test/MC/SystemZ/insn-lay-02.s new file mode 100644 index 000000000000..2729eead22a6 --- /dev/null +++ b/test/MC/SystemZ/insn-lay-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lay %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lay %r0, 524288 + + lay %r0, -524289 + lay %r0, 524288 diff --git a/test/MC/SystemZ/insn-lb-01.s b/test/MC/SystemZ/insn-lb-01.s new file mode 100644 index 000000000000..e9ee0fab2266 --- /dev/null +++ b/test/MC/SystemZ/insn-lb-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lb %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x76] +#CHECK: lb %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x76] +#CHECK: lb %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x76] +#CHECK: lb %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x76] +#CHECK: lb %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x76] +#CHECK: lb %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x76] +#CHECK: lb %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x76] +#CHECK: lb %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x76] +#CHECK: lb %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x76] +#CHECK: lb %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x76] + + lb %r0, -524288 + lb %r0, -1 + lb %r0, 0 + lb %r0, 1 + lb %r0, 524287 + lb %r0, 0(%r1) + lb %r0, 0(%r15) + lb %r0, 524287(%r1,%r15) + lb %r0, 524287(%r15,%r1) + lb %r15, 0 diff --git a/test/MC/SystemZ/insn-lb-02.s b/test/MC/SystemZ/insn-lb-02.s new file mode 100644 index 000000000000..e65edaf09dac --- /dev/null +++ b/test/MC/SystemZ/insn-lb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lb %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lb %r0, 524288 + + lb %r0, -524289 + lb %r0, 524288 diff --git a/test/MC/SystemZ/insn-lbr-01.s b/test/MC/SystemZ/insn-lbr-01.s new file mode 100644 index 000000000000..cb4ead043080 --- /dev/null +++ b/test/MC/SystemZ/insn-lbr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lbr %r0, %r15 # encoding: [0xb9,0x26,0x00,0x0f] +#CHECK: lbr %r7, %r8 # encoding: [0xb9,0x26,0x00,0x78] +#CHECK: lbr %r15, %r0 # encoding: [0xb9,0x26,0x00,0xf0] + + lbr %r0, %r15 + lbr %r7, %r8 + lbr %r15, %r0 diff --git a/test/MC/SystemZ/insn-lcdbr-01.s b/test/MC/SystemZ/insn-lcdbr-01.s new file mode 100644 index 000000000000..347cab514116 --- /dev/null +++ b/test/MC/SystemZ/insn-lcdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcdbr %f0, %f9 # encoding: [0xb3,0x13,0x00,0x09] +#CHECK: lcdbr %f0, %f15 # encoding: [0xb3,0x13,0x00,0x0f] +#CHECK: lcdbr %f15, %f0 # encoding: [0xb3,0x13,0x00,0xf0] +#CHECK: lcdbr %f15, %f9 # encoding: [0xb3,0x13,0x00,0xf9] + + lcdbr %f0,%f9 + lcdbr %f0,%f15 + lcdbr %f15,%f0 + lcdbr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lcebr-01.s b/test/MC/SystemZ/insn-lcebr-01.s new file mode 100644 index 000000000000..e31822f00460 --- /dev/null +++ b/test/MC/SystemZ/insn-lcebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcebr %f0, %f9 # encoding: [0xb3,0x03,0x00,0x09] +#CHECK: lcebr %f0, %f15 # encoding: [0xb3,0x03,0x00,0x0f] +#CHECK: lcebr %f15, %f0 # encoding: [0xb3,0x03,0x00,0xf0] +#CHECK: lcebr %f15, %f9 # encoding: [0xb3,0x03,0x00,0xf9] + + lcebr %f0,%f9 + lcebr %f0,%f15 + lcebr %f15,%f0 + lcebr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lcgfr-01.s b/test/MC/SystemZ/insn-lcgfr-01.s new file mode 100644 index 000000000000..bca430b8015d --- /dev/null +++ b/test/MC/SystemZ/insn-lcgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcgfr %r0, %r0 # encoding: [0xb9,0x13,0x00,0x00] +#CHECK: lcgfr %r0, %r15 # encoding: [0xb9,0x13,0x00,0x0f] +#CHECK: lcgfr %r15, %r0 # encoding: [0xb9,0x13,0x00,0xf0] +#CHECK: lcgfr %r7, %r8 # encoding: [0xb9,0x13,0x00,0x78] + + lcgfr %r0,%r0 + lcgfr %r0,%r15 + lcgfr %r15,%r0 + lcgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-lcgr-01.s b/test/MC/SystemZ/insn-lcgr-01.s new file mode 100644 index 000000000000..dc4e94f03eed --- /dev/null +++ b/test/MC/SystemZ/insn-lcgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcgr %r0, %r0 # encoding: [0xb9,0x03,0x00,0x00] +#CHECK: lcgr %r0, %r15 # encoding: [0xb9,0x03,0x00,0x0f] +#CHECK: lcgr %r15, %r0 # encoding: [0xb9,0x03,0x00,0xf0] +#CHECK: lcgr %r7, %r8 # encoding: [0xb9,0x03,0x00,0x78] + + lcgr %r0,%r0 + lcgr %r0,%r15 + lcgr %r15,%r0 + lcgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-lcr-01.s b/test/MC/SystemZ/insn-lcr-01.s new file mode 100644 index 000000000000..52471cbbdc54 --- /dev/null +++ b/test/MC/SystemZ/insn-lcr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcr %r0, %r0 # encoding: [0x13,0x00] +#CHECK: lcr %r0, %r15 # encoding: [0x13,0x0f] +#CHECK: lcr %r15, %r0 # encoding: [0x13,0xf0] +#CHECK: lcr %r7, %r8 # encoding: [0x13,0x78] + + lcr %r0,%r0 + lcr %r0,%r15 + lcr %r15,%r0 + lcr %r7,%r8 diff --git a/test/MC/SystemZ/insn-lcxbr-01.s b/test/MC/SystemZ/insn-lcxbr-01.s new file mode 100644 index 000000000000..48c0b8a77213 --- /dev/null +++ b/test/MC/SystemZ/insn-lcxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lcxbr %f0, %f8 # encoding: [0xb3,0x43,0x00,0x08] +#CHECK: lcxbr %f0, %f13 # encoding: [0xb3,0x43,0x00,0x0d] +#CHECK: lcxbr %f13, %f0 # encoding: [0xb3,0x43,0x00,0xd0] +#CHECK: lcxbr %f13, %f9 # encoding: [0xb3,0x43,0x00,0xd9] + + lcxbr %f0,%f8 + lcxbr %f0,%f13 + lcxbr %f13,%f0 + lcxbr %f13,%f9 diff --git a/test/MC/SystemZ/insn-lcxbr-02.s b/test/MC/SystemZ/insn-lcxbr-02.s new file mode 100644 index 000000000000..ab3d6bfe9cd8 --- /dev/null +++ b/test/MC/SystemZ/insn-lcxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lcxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: lcxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: lcxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: lcxbr %f14, %f0 + + lcxbr %f0, %f2 + lcxbr %f0, %f14 + lcxbr %f2, %f0 + lcxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-ld-01.s b/test/MC/SystemZ/insn-ld-01.s new file mode 100644 index 000000000000..653eab5e0a57 --- /dev/null +++ b/test/MC/SystemZ/insn-ld-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ld %f0, 0 # encoding: [0x68,0x00,0x00,0x00] +#CHECK: ld %f0, 4095 # encoding: [0x68,0x00,0x0f,0xff] +#CHECK: ld %f0, 0(%r1) # encoding: [0x68,0x00,0x10,0x00] +#CHECK: ld %f0, 0(%r15) # encoding: [0x68,0x00,0xf0,0x00] +#CHECK: ld %f0, 4095(%r1,%r15) # encoding: [0x68,0x01,0xff,0xff] +#CHECK: ld %f0, 4095(%r15,%r1) # encoding: [0x68,0x0f,0x1f,0xff] +#CHECK: ld %f15, 0 # encoding: [0x68,0xf0,0x00,0x00] + + ld %f0, 0 + ld %f0, 4095 + ld %f0, 0(%r1) + ld %f0, 0(%r15) + ld %f0, 4095(%r1,%r15) + ld %f0, 4095(%r15,%r1) + ld %f15, 0 diff --git a/test/MC/SystemZ/insn-ld-02.s b/test/MC/SystemZ/insn-ld-02.s new file mode 100644 index 000000000000..5d786b555705 --- /dev/null +++ b/test/MC/SystemZ/insn-ld-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ld %f0, -1 +#CHECK: error: invalid operand +#CHECK: ld %f0, 4096 + + ld %f0, -1 + ld %f0, 4096 diff --git a/test/MC/SystemZ/insn-ldeb-01.s b/test/MC/SystemZ/insn-ldeb-01.s new file mode 100644 index 000000000000..a06344d27d97 --- /dev/null +++ b/test/MC/SystemZ/insn-ldeb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x04] +#CHECK: ldeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x04] +#CHECK: ldeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x04] +#CHECK: ldeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x04] +#CHECK: ldeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x04] +#CHECK: ldeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x04] +#CHECK: ldeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x04] + + ldeb %f0, 0 + ldeb %f0, 4095 + ldeb %f0, 0(%r1) + ldeb %f0, 0(%r15) + ldeb %f0, 4095(%r1,%r15) + ldeb %f0, 4095(%r15,%r1) + ldeb %f15, 0 diff --git a/test/MC/SystemZ/insn-ldeb-02.s b/test/MC/SystemZ/insn-ldeb-02.s new file mode 100644 index 000000000000..6df5e7b46d05 --- /dev/null +++ b/test/MC/SystemZ/insn-ldeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ldeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: ldeb %f0, 4096 + + ldeb %f0, -1 + ldeb %f0, 4096 diff --git a/test/MC/SystemZ/insn-ldebr-01.s b/test/MC/SystemZ/insn-ldebr-01.s new file mode 100644 index 000000000000..2df932c6686a --- /dev/null +++ b/test/MC/SystemZ/insn-ldebr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldebr %f0, %f15 # encoding: [0xb3,0x04,0x00,0x0f] +#CHECK: ldebr %f7, %f8 # encoding: [0xb3,0x04,0x00,0x78] +#CHECK: ldebr %f15, %f0 # encoding: [0xb3,0x04,0x00,0xf0] + + ldebr %f0, %f15 + ldebr %f7, %f8 + ldebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-ldgr-01.s b/test/MC/SystemZ/insn-ldgr-01.s new file mode 100644 index 000000000000..61a4529bee7c --- /dev/null +++ b/test/MC/SystemZ/insn-ldgr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldgr %f0, %r0 # encoding: [0xb3,0xc1,0x00,0x00] +#CHECK: ldgr %f0, %r15 # encoding: [0xb3,0xc1,0x00,0x0f] +#CHECK: ldgr %f15, %r0 # encoding: [0xb3,0xc1,0x00,0xf0] +#CHECK: ldgr %f7, %r9 # encoding: [0xb3,0xc1,0x00,0x79] +#CHECK: ldgr %f15, %r15 # encoding: [0xb3,0xc1,0x00,0xff] + + ldgr %f0,%r0 + ldgr %f0,%r15 + ldgr %f15,%r0 + ldgr %f7,%r9 + ldgr %f15,%r15 diff --git a/test/MC/SystemZ/insn-ldgr-02.s b/test/MC/SystemZ/insn-ldgr-02.s new file mode 100644 index 000000000000..900174ab1f14 --- /dev/null +++ b/test/MC/SystemZ/insn-ldgr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: ldgr %f0, %f0 +#CHECK: error: invalid register +#CHECK: ldgr %r0, %r0 +#CHECK: error: invalid register +#CHECK: ldgr %f0, %a0 +#CHECK: error: invalid register +#CHECK: ldgr %a0, %r0 + + ldgr %f0, %f0 + ldgr %r0, %r0 + ldgr %f0, %a0 + ldgr %a0, %r0 diff --git a/test/MC/SystemZ/insn-ldr-01.s b/test/MC/SystemZ/insn-ldr-01.s new file mode 100644 index 000000000000..895ed3439fce --- /dev/null +++ b/test/MC/SystemZ/insn-ldr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldr %f0, %f9 # encoding: [0x28,0x09] +#CHECK: ldr %f0, %f15 # encoding: [0x28,0x0f] +#CHECK: ldr %f15, %f0 # encoding: [0x28,0xf0] +#CHECK: ldr %f15, %f9 # encoding: [0x28,0xf9] + + ldr %f0,%f9 + ldr %f0,%f15 + ldr %f15,%f0 + ldr %f15,%f9 diff --git a/test/MC/SystemZ/insn-ldxbr-01.s b/test/MC/SystemZ/insn-ldxbr-01.s new file mode 100644 index 000000000000..49e1d2adfb15 --- /dev/null +++ b/test/MC/SystemZ/insn-ldxbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldxbr %f0, %f0 # encoding: [0xb3,0x45,0x00,0x00] +#CHECK: ldxbr %f0, %f13 # encoding: [0xb3,0x45,0x00,0x0d] +#CHECK: ldxbr %f8, %f12 # encoding: [0xb3,0x45,0x00,0x8c] +#CHECK: ldxbr %f13, %f0 # encoding: [0xb3,0x45,0x00,0xd0] +#CHECK: ldxbr %f13, %f13 # encoding: [0xb3,0x45,0x00,0xdd] + + ldxbr %f0, %f0 + ldxbr %f0, %f13 + ldxbr %f8, %f12 + ldxbr %f13, %f0 + ldxbr %f13, %f13 diff --git a/test/MC/SystemZ/insn-ldxbr-02.s b/test/MC/SystemZ/insn-ldxbr-02.s new file mode 100644 index 000000000000..89914dff9d47 --- /dev/null +++ b/test/MC/SystemZ/insn-ldxbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: ldxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: ldxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: ldxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: ldxbr %f14, %f0 + + ldxbr %f0, %f2 + ldxbr %f0, %f14 + ldxbr %f2, %f0 + ldxbr %f14, %f0 diff --git a/test/MC/SystemZ/insn-ldy-01.s b/test/MC/SystemZ/insn-ldy-01.s new file mode 100644 index 000000000000..5c2d145af124 --- /dev/null +++ b/test/MC/SystemZ/insn-ldy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldy %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x65] +#CHECK: ldy %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x65] +#CHECK: ldy %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x65] +#CHECK: ldy %f0, 1 # encoding: [0xed,0x00,0x00,0x01,0x00,0x65] +#CHECK: ldy %f0, 524287 # encoding: [0xed,0x00,0x0f,0xff,0x7f,0x65] +#CHECK: ldy %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x65] +#CHECK: ldy %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x65] +#CHECK: ldy %f0, 524287(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x7f,0x65] +#CHECK: ldy %f0, 524287(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x7f,0x65] +#CHECK: ldy %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x65] + + ldy %f0, -524288 + ldy %f0, -1 + ldy %f0, 0 + ldy %f0, 1 + ldy %f0, 524287 + ldy %f0, 0(%r1) + ldy %f0, 0(%r15) + ldy %f0, 524287(%r1,%r15) + ldy %f0, 524287(%r15,%r1) + ldy %f15, 0 diff --git a/test/MC/SystemZ/insn-ldy-02.s b/test/MC/SystemZ/insn-ldy-02.s new file mode 100644 index 000000000000..b16e0149ee76 --- /dev/null +++ b/test/MC/SystemZ/insn-ldy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ldy %f0, -524289 +#CHECK: error: invalid operand +#CHECK: ldy %f0, 524288 + + ldy %f0, -524289 + ldy %f0, 524288 diff --git a/test/MC/SystemZ/insn-le-01.s b/test/MC/SystemZ/insn-le-01.s new file mode 100644 index 000000000000..15bbce26a519 --- /dev/null +++ b/test/MC/SystemZ/insn-le-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: le %f0, 0 # encoding: [0x78,0x00,0x00,0x00] +#CHECK: le %f0, 4095 # encoding: [0x78,0x00,0x0f,0xff] +#CHECK: le %f0, 0(%r1) # encoding: [0x78,0x00,0x10,0x00] +#CHECK: le %f0, 0(%r15) # encoding: [0x78,0x00,0xf0,0x00] +#CHECK: le %f0, 4095(%r1,%r15) # encoding: [0x78,0x01,0xff,0xff] +#CHECK: le %f0, 4095(%r15,%r1) # encoding: [0x78,0x0f,0x1f,0xff] +#CHECK: le %f15, 0 # encoding: [0x78,0xf0,0x00,0x00] + + le %f0, 0 + le %f0, 4095 + le %f0, 0(%r1) + le %f0, 0(%r15) + le %f0, 4095(%r1,%r15) + le %f0, 4095(%r15,%r1) + le %f15, 0 diff --git a/test/MC/SystemZ/insn-le-02.s b/test/MC/SystemZ/insn-le-02.s new file mode 100644 index 000000000000..f784ea1c9012 --- /dev/null +++ b/test/MC/SystemZ/insn-le-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: le %f0, -1 +#CHECK: error: invalid operand +#CHECK: le %f0, 4096 + + le %f0, -1 + le %f0, 4096 diff --git a/test/MC/SystemZ/insn-ledbr-01.s b/test/MC/SystemZ/insn-ledbr-01.s new file mode 100644 index 000000000000..6582d6344f7e --- /dev/null +++ b/test/MC/SystemZ/insn-ledbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ledbr %f0, %f0 # encoding: [0xb3,0x44,0x00,0x00] +#CHECK: ledbr %f0, %f15 # encoding: [0xb3,0x44,0x00,0x0f] +#CHECK: ledbr %f7, %f8 # encoding: [0xb3,0x44,0x00,0x78] +#CHECK: ledbr %f15, %f0 # encoding: [0xb3,0x44,0x00,0xf0] +#CHECK: ledbr %f15, %f15 # encoding: [0xb3,0x44,0x00,0xff] + + ledbr %f0, %f0 + ledbr %f0, %f15 + ledbr %f7, %f8 + ledbr %f15, %f0 + ledbr %f15, %f15 diff --git a/test/MC/SystemZ/insn-ler-01.s b/test/MC/SystemZ/insn-ler-01.s new file mode 100644 index 000000000000..775e5232186d --- /dev/null +++ b/test/MC/SystemZ/insn-ler-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ler %f0, %f9 # encoding: [0x38,0x09] +#CHECK: ler %f0, %f15 # encoding: [0x38,0x0f] +#CHECK: ler %f15, %f0 # encoding: [0x38,0xf0] +#CHECK: ler %f15, %f9 # encoding: [0x38,0xf9] + + ler %f0,%f9 + ler %f0,%f15 + ler %f15,%f0 + ler %f15,%f9 diff --git a/test/MC/SystemZ/insn-lexbr-01.s b/test/MC/SystemZ/insn-lexbr-01.s new file mode 100644 index 000000000000..ce32103c66cb --- /dev/null +++ b/test/MC/SystemZ/insn-lexbr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lexbr %f0, %f0 # encoding: [0xb3,0x46,0x00,0x00] +#CHECK: lexbr %f0, %f13 # encoding: [0xb3,0x46,0x00,0x0d] +#CHECK: lexbr %f8, %f12 # encoding: [0xb3,0x46,0x00,0x8c] +#CHECK: lexbr %f13, %f0 # encoding: [0xb3,0x46,0x00,0xd0] +#CHECK: lexbr %f13, %f13 # encoding: [0xb3,0x46,0x00,0xdd] + + lexbr %f0, %f0 + lexbr %f0, %f13 + lexbr %f8, %f12 + lexbr %f13, %f0 + lexbr %f13, %f13 diff --git a/test/MC/SystemZ/insn-lexbr-02.s b/test/MC/SystemZ/insn-lexbr-02.s new file mode 100644 index 000000000000..8c9bb9ed600e --- /dev/null +++ b/test/MC/SystemZ/insn-lexbr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lexbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: lexbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: lexbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: lexbr %f14, %f0 + + lexbr %f0, %f2 + lexbr %f0, %f14 + lexbr %f2, %f0 + lexbr %f14, %f0 diff --git a/test/MC/SystemZ/insn-ley-01.s b/test/MC/SystemZ/insn-ley-01.s new file mode 100644 index 000000000000..b854dc148c77 --- /dev/null +++ b/test/MC/SystemZ/insn-ley-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ley %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x64] +#CHECK: ley %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x64] +#CHECK: ley %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x64] +#CHECK: ley %f0, 1 # encoding: [0xed,0x00,0x00,0x01,0x00,0x64] +#CHECK: ley %f0, 524287 # encoding: [0xed,0x00,0x0f,0xff,0x7f,0x64] +#CHECK: ley %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x64] +#CHECK: ley %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x64] +#CHECK: ley %f0, 524287(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x7f,0x64] +#CHECK: ley %f0, 524287(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x7f,0x64] +#CHECK: ley %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x64] + + ley %f0, -524288 + ley %f0, -1 + ley %f0, 0 + ley %f0, 1 + ley %f0, 524287 + ley %f0, 0(%r1) + ley %f0, 0(%r15) + ley %f0, 524287(%r1,%r15) + ley %f0, 524287(%r15,%r1) + ley %f15, 0 diff --git a/test/MC/SystemZ/insn-ley-02.s b/test/MC/SystemZ/insn-ley-02.s new file mode 100644 index 000000000000..98bbd94dc176 --- /dev/null +++ b/test/MC/SystemZ/insn-ley-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ley %f0, -524289 +#CHECK: error: invalid operand +#CHECK: ley %f0, 524288 + + ley %f0, -524289 + ley %f0, 524288 diff --git a/test/MC/SystemZ/insn-lg-01.s b/test/MC/SystemZ/insn-lg-01.s new file mode 100644 index 000000000000..10a95cc8958a --- /dev/null +++ b/test/MC/SystemZ/insn-lg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x04] +#CHECK: lg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x04] +#CHECK: lg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x04] +#CHECK: lg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x04] +#CHECK: lg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x04] +#CHECK: lg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x04] +#CHECK: lg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x04] +#CHECK: lg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x04] +#CHECK: lg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x04] +#CHECK: lg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x04] + + lg %r0, -524288 + lg %r0, -1 + lg %r0, 0 + lg %r0, 1 + lg %r0, 524287 + lg %r0, 0(%r1) + lg %r0, 0(%r15) + lg %r0, 524287(%r1,%r15) + lg %r0, 524287(%r15,%r1) + lg %r15, 0 diff --git a/test/MC/SystemZ/insn-lg-02.s b/test/MC/SystemZ/insn-lg-02.s new file mode 100644 index 000000000000..85b29fff5533 --- /dev/null +++ b/test/MC/SystemZ/insn-lg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lg %r0, 524288 + + lg %r0, -524289 + lg %r0, 524288 diff --git a/test/MC/SystemZ/insn-lgb-01.s b/test/MC/SystemZ/insn-lgb-01.s new file mode 100644 index 000000000000..82b92f167272 --- /dev/null +++ b/test/MC/SystemZ/insn-lgb-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgb %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x77] +#CHECK: lgb %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x77] +#CHECK: lgb %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x77] +#CHECK: lgb %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x77] +#CHECK: lgb %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x77] +#CHECK: lgb %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x77] +#CHECK: lgb %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x77] +#CHECK: lgb %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x77] +#CHECK: lgb %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x77] +#CHECK: lgb %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x77] + + lgb %r0, -524288 + lgb %r0, -1 + lgb %r0, 0 + lgb %r0, 1 + lgb %r0, 524287 + lgb %r0, 0(%r1) + lgb %r0, 0(%r15) + lgb %r0, 524287(%r1,%r15) + lgb %r0, 524287(%r15,%r1) + lgb %r15, 0 + diff --git a/test/MC/SystemZ/insn-lgb-02.s b/test/MC/SystemZ/insn-lgb-02.s new file mode 100644 index 000000000000..7acc1762b51b --- /dev/null +++ b/test/MC/SystemZ/insn-lgb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lgb %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgb %r0, 524288 + + lgb %r0, -524289 + lgb %r0, 524288 diff --git a/test/MC/SystemZ/insn-lgbr-01.s b/test/MC/SystemZ/insn-lgbr-01.s new file mode 100644 index 000000000000..ec2e6220091d --- /dev/null +++ b/test/MC/SystemZ/insn-lgbr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgbr %r0, %r15 # encoding: [0xb9,0x06,0x00,0x0f] +#CHECK: lgbr %r7, %r8 # encoding: [0xb9,0x06,0x00,0x78] +#CHECK: lgbr %r15, %r0 # encoding: [0xb9,0x06,0x00,0xf0] + + lgbr %r0, %r15 + lgbr %r7, %r8 + lgbr %r15, %r0 diff --git a/test/MC/SystemZ/insn-lgdr-01.s b/test/MC/SystemZ/insn-lgdr-01.s new file mode 100644 index 000000000000..56d1e035b425 --- /dev/null +++ b/test/MC/SystemZ/insn-lgdr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgdr %r0, %f0 # encoding: [0xb3,0xcd,0x00,0x00] +#CHECK: lgdr %r0, %f15 # encoding: [0xb3,0xcd,0x00,0x0f] +#CHECK: lgdr %r15, %f0 # encoding: [0xb3,0xcd,0x00,0xf0] +#CHECK: lgdr %r8, %f8 # encoding: [0xb3,0xcd,0x00,0x88] +#CHECK: lgdr %r15, %f15 # encoding: [0xb3,0xcd,0x00,0xff] + + lgdr %r0,%f0 + lgdr %r0,%f15 + lgdr %r15,%f0 + lgdr %r8,%f8 + lgdr %r15,%f15 diff --git a/test/MC/SystemZ/insn-lgdr-02.s b/test/MC/SystemZ/insn-lgdr-02.s new file mode 100644 index 000000000000..3bf014d90ec1 --- /dev/null +++ b/test/MC/SystemZ/insn-lgdr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lgdr %f0, %f0 +#CHECK: error: invalid register +#CHECK: lgdr %r0, %r0 +#CHECK: error: invalid register +#CHECK: lgdr %r0, %a0 +#CHECK: error: invalid register +#CHECK: lgdr %a0, %f0 + + lgdr %f0, %f0 + lgdr %r0, %r0 + lgdr %r0, %a0 + lgdr %a0, %f0 diff --git a/test/MC/SystemZ/insn-lgf-01.s b/test/MC/SystemZ/insn-lgf-01.s new file mode 100644 index 000000000000..9ed917228a8a --- /dev/null +++ b/test/MC/SystemZ/insn-lgf-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x14] +#CHECK: lgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x14] +#CHECK: lgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x14] +#CHECK: lgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x14] +#CHECK: lgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x14] +#CHECK: lgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x14] +#CHECK: lgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x14] +#CHECK: lgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x14] +#CHECK: lgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x14] +#CHECK: lgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x14] + + lgf %r0, -524288 + lgf %r0, -1 + lgf %r0, 0 + lgf %r0, 1 + lgf %r0, 524287 + lgf %r0, 0(%r1) + lgf %r0, 0(%r15) + lgf %r0, 524287(%r1,%r15) + lgf %r0, 524287(%r15,%r1) + lgf %r15, 0 + diff --git a/test/MC/SystemZ/insn-lgf-02.s b/test/MC/SystemZ/insn-lgf-02.s new file mode 100644 index 000000000000..32095a840936 --- /dev/null +++ b/test/MC/SystemZ/insn-lgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgf %r0, 524288 + + lgf %r0, -524289 + lgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-lgfi-01.s b/test/MC/SystemZ/insn-lgfi-01.s new file mode 100644 index 000000000000..a5ca7a59b5d2 --- /dev/null +++ b/test/MC/SystemZ/insn-lgfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgfi %r0, -2147483648 # encoding: [0xc0,0x01,0x80,0x00,0x00,0x00] +#CHECK: lgfi %r0, -1 # encoding: [0xc0,0x01,0xff,0xff,0xff,0xff] +#CHECK: lgfi %r0, 0 # encoding: [0xc0,0x01,0x00,0x00,0x00,0x00] +#CHECK: lgfi %r0, 1 # encoding: [0xc0,0x01,0x00,0x00,0x00,0x01] +#CHECK: lgfi %r0, 2147483647 # encoding: [0xc0,0x01,0x7f,0xff,0xff,0xff] +#CHECK: lgfi %r15, 0 # encoding: [0xc0,0xf1,0x00,0x00,0x00,0x00] + + lgfi %r0, -1 << 31 + lgfi %r0, -1 + lgfi %r0, 0 + lgfi %r0, 1 + lgfi %r0, (1 << 31) - 1 + lgfi %r15, 0 diff --git a/test/MC/SystemZ/insn-lgfi-02.s b/test/MC/SystemZ/insn-lgfi-02.s new file mode 100644 index 000000000000..a45cfeb46d05 --- /dev/null +++ b/test/MC/SystemZ/insn-lgfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lgfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: lgfi %r0, (1 << 31) + + lgfi %r0, (-1 << 31) - 1 + lgfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-lgfr-01.s b/test/MC/SystemZ/insn-lgfr-01.s new file mode 100644 index 000000000000..bc375a67b000 --- /dev/null +++ b/test/MC/SystemZ/insn-lgfr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgfr %r0, %r15 # encoding: [0xb9,0x14,0x00,0x0f] +#CHECK: lgfr %r7, %r8 # encoding: [0xb9,0x14,0x00,0x78] +#CHECK: lgfr %r15, %r0 # encoding: [0xb9,0x14,0x00,0xf0] + + lgfr %r0, %r15 + lgfr %r7, %r8 + lgfr %r15, %r0 diff --git a/test/MC/SystemZ/insn-lgfrl-01.s b/test/MC/SystemZ/insn-lgfrl-01.s new file mode 100644 index 000000000000..85c9ea764c8d --- /dev/null +++ b/test/MC/SystemZ/insn-lgfrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgfrl %r0, 2864434397 # encoding: [0xc4,0x0c,0x55,0x5d,0xe6,0x6e] +#CHECK: lgfrl %r15, 2864434397 # encoding: [0xc4,0xfc,0x55,0x5d,0xe6,0x6e] + + lgfrl %r0,0xaabbccdd + lgfrl %r15,0xaabbccdd + +#CHECK: lgfrl %r0, foo # encoding: [0xc4,0x0c,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: lgfrl %r15, foo # encoding: [0xc4,0xfc,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + lgfrl %r0,foo + lgfrl %r15,foo + +#CHECK: lgfrl %r3, bar+100 # encoding: [0xc4,0x3c,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: lgfrl %r4, bar+100 # encoding: [0xc4,0x4c,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + lgfrl %r3,bar+100 + lgfrl %r4,bar+100 + +#CHECK: lgfrl %r7, frob@PLT # encoding: [0xc4,0x7c,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: lgfrl %r8, frob@PLT # encoding: [0xc4,0x8c,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + lgfrl %r7,frob@PLT + lgfrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lgh-01.s b/test/MC/SystemZ/insn-lgh-01.s new file mode 100644 index 000000000000..9dae6212b2c2 --- /dev/null +++ b/test/MC/SystemZ/insn-lgh-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x15] +#CHECK: lgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x15] +#CHECK: lgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x15] +#CHECK: lgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x15] +#CHECK: lgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x15] +#CHECK: lgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x15] +#CHECK: lgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x15] +#CHECK: lgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x15] +#CHECK: lgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x15] +#CHECK: lgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x15] + + lgh %r0, -524288 + lgh %r0, -1 + lgh %r0, 0 + lgh %r0, 1 + lgh %r0, 524287 + lgh %r0, 0(%r1) + lgh %r0, 0(%r15) + lgh %r0, 524287(%r1,%r15) + lgh %r0, 524287(%r15,%r1) + lgh %r15, 0 + diff --git a/test/MC/SystemZ/insn-lgh-02.s b/test/MC/SystemZ/insn-lgh-02.s new file mode 100644 index 000000000000..62b7341d8276 --- /dev/null +++ b/test/MC/SystemZ/insn-lgh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgh %r0, 524288 + + lgh %r0, -524289 + lgh %r0, 524288 diff --git a/test/MC/SystemZ/insn-lghi-01.s b/test/MC/SystemZ/insn-lghi-01.s new file mode 100644 index 000000000000..d9d12ae1bb39 --- /dev/null +++ b/test/MC/SystemZ/insn-lghi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lghi %r0, -32768 # encoding: [0xa7,0x09,0x80,0x00] +#CHECK: lghi %r0, -1 # encoding: [0xa7,0x09,0xff,0xff] +#CHECK: lghi %r0, 0 # encoding: [0xa7,0x09,0x00,0x00] +#CHECK: lghi %r0, 1 # encoding: [0xa7,0x09,0x00,0x01] +#CHECK: lghi %r0, 32767 # encoding: [0xa7,0x09,0x7f,0xff] +#CHECK: lghi %r15, 0 # encoding: [0xa7,0xf9,0x00,0x00] + + lghi %r0, -32768 + lghi %r0, -1 + lghi %r0, 0 + lghi %r0, 1 + lghi %r0, 32767 + lghi %r15, 0 diff --git a/test/MC/SystemZ/insn-lghi-02.s b/test/MC/SystemZ/insn-lghi-02.s new file mode 100644 index 000000000000..b1af7a0c54ad --- /dev/null +++ b/test/MC/SystemZ/insn-lghi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lghi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: lghi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: lghi %r0, foo + + lghi %r0, -32769 + lghi %r0, 32768 + lghi %r0, foo diff --git a/test/MC/SystemZ/insn-lghr-01.s b/test/MC/SystemZ/insn-lghr-01.s new file mode 100644 index 000000000000..a1dc842339b4 --- /dev/null +++ b/test/MC/SystemZ/insn-lghr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lghr %r0, %r15 # encoding: [0xb9,0x07,0x00,0x0f] +#CHECK: lghr %r7, %r8 # encoding: [0xb9,0x07,0x00,0x78] +#CHECK: lghr %r15, %r0 # encoding: [0xb9,0x07,0x00,0xf0] + + lghr %r0, %r15 + lghr %r7, %r8 + lghr %r15, %r0 diff --git a/test/MC/SystemZ/insn-lghrl-01.s b/test/MC/SystemZ/insn-lghrl-01.s new file mode 100644 index 000000000000..34992e6ff26a --- /dev/null +++ b/test/MC/SystemZ/insn-lghrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lghrl %r0, 2864434397 # encoding: [0xc4,0x04,0x55,0x5d,0xe6,0x6e] +#CHECK: lghrl %r15, 2864434397 # encoding: [0xc4,0xf4,0x55,0x5d,0xe6,0x6e] + + lghrl %r0,0xaabbccdd + lghrl %r15,0xaabbccdd + +#CHECK: lghrl %r0, foo # encoding: [0xc4,0x04,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: lghrl %r15, foo # encoding: [0xc4,0xf4,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + lghrl %r0,foo + lghrl %r15,foo + +#CHECK: lghrl %r3, bar+100 # encoding: [0xc4,0x34,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: lghrl %r4, bar+100 # encoding: [0xc4,0x44,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + lghrl %r3,bar+100 + lghrl %r4,bar+100 + +#CHECK: lghrl %r7, frob@PLT # encoding: [0xc4,0x74,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: lghrl %r8, frob@PLT # encoding: [0xc4,0x84,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + lghrl %r7,frob@PLT + lghrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lgr-01.s b/test/MC/SystemZ/insn-lgr-01.s new file mode 100644 index 000000000000..e50295682bd4 --- /dev/null +++ b/test/MC/SystemZ/insn-lgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgr %r0, %r9 # encoding: [0xb9,0x04,0x00,0x09] +#CHECK: lgr %r0, %r15 # encoding: [0xb9,0x04,0x00,0x0f] +#CHECK: lgr %r15, %r0 # encoding: [0xb9,0x04,0x00,0xf0] +#CHECK: lgr %r15, %r9 # encoding: [0xb9,0x04,0x00,0xf9] + + lgr %r0,%r9 + lgr %r0,%r15 + lgr %r15,%r0 + lgr %r15,%r9 diff --git a/test/MC/SystemZ/insn-lgrl-01.s b/test/MC/SystemZ/insn-lgrl-01.s new file mode 100644 index 000000000000..7a18908f9ab7 --- /dev/null +++ b/test/MC/SystemZ/insn-lgrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgrl %r0, 2864434397 # encoding: [0xc4,0x08,0x55,0x5d,0xe6,0x6e] +#CHECK: lgrl %r15, 2864434397 # encoding: [0xc4,0xf8,0x55,0x5d,0xe6,0x6e] + + lgrl %r0,0xaabbccdd + lgrl %r15,0xaabbccdd + +#CHECK: lgrl %r0, foo # encoding: [0xc4,0x08,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: lgrl %r15, foo # encoding: [0xc4,0xf8,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + lgrl %r0,foo + lgrl %r15,foo + +#CHECK: lgrl %r3, bar+100 # encoding: [0xc4,0x38,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: lgrl %r4, bar+100 # encoding: [0xc4,0x48,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + lgrl %r3,bar+100 + lgrl %r4,bar+100 + +#CHECK: lgrl %r7, frob@PLT # encoding: [0xc4,0x78,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: lgrl %r8, frob@PLT # encoding: [0xc4,0x88,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + lgrl %r7,frob@PLT + lgrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lh-01.s b/test/MC/SystemZ/insn-lh-01.s new file mode 100644 index 000000000000..07be01275693 --- /dev/null +++ b/test/MC/SystemZ/insn-lh-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lh %r0, 0 # encoding: [0x48,0x00,0x00,0x00] +#CHECK: lh %r0, 4095 # encoding: [0x48,0x00,0x0f,0xff] +#CHECK: lh %r0, 0(%r1) # encoding: [0x48,0x00,0x10,0x00] +#CHECK: lh %r0, 0(%r15) # encoding: [0x48,0x00,0xf0,0x00] +#CHECK: lh %r0, 4095(%r1,%r15) # encoding: [0x48,0x01,0xff,0xff] +#CHECK: lh %r0, 4095(%r15,%r1) # encoding: [0x48,0x0f,0x1f,0xff] +#CHECK: lh %r15, 0 # encoding: [0x48,0xf0,0x00,0x00] + + lh %r0, 0 + lh %r0, 4095 + lh %r0, 0(%r1) + lh %r0, 0(%r15) + lh %r0, 4095(%r1,%r15) + lh %r0, 4095(%r15,%r1) + lh %r15, 0 diff --git a/test/MC/SystemZ/insn-lh-02.s b/test/MC/SystemZ/insn-lh-02.s new file mode 100644 index 000000000000..80566d8d37ef --- /dev/null +++ b/test/MC/SystemZ/insn-lh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lh %r0, -1 +#CHECK: error: invalid operand +#CHECK: lh %r0, 4096 + + lh %r0, -1 + lh %r0, 4096 diff --git a/test/MC/SystemZ/insn-lhi-01.s b/test/MC/SystemZ/insn-lhi-01.s new file mode 100644 index 000000000000..43b7df08f016 --- /dev/null +++ b/test/MC/SystemZ/insn-lhi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lhi %r0, -32768 # encoding: [0xa7,0x08,0x80,0x00] +#CHECK: lhi %r0, -1 # encoding: [0xa7,0x08,0xff,0xff] +#CHECK: lhi %r0, 0 # encoding: [0xa7,0x08,0x00,0x00] +#CHECK: lhi %r0, 1 # encoding: [0xa7,0x08,0x00,0x01] +#CHECK: lhi %r0, 32767 # encoding: [0xa7,0x08,0x7f,0xff] +#CHECK: lhi %r15, 0 # encoding: [0xa7,0xf8,0x00,0x00] + + lhi %r0, -32768 + lhi %r0, -1 + lhi %r0, 0 + lhi %r0, 1 + lhi %r0, 32767 + lhi %r15, 0 diff --git a/test/MC/SystemZ/insn-lhi-02.s b/test/MC/SystemZ/insn-lhi-02.s new file mode 100644 index 000000000000..8e38464b828f --- /dev/null +++ b/test/MC/SystemZ/insn-lhi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lhi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: lhi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: lhi %r0, foo + + lhi %r0, -32769 + lhi %r0, 32768 + lhi %r0, foo diff --git a/test/MC/SystemZ/insn-lhr-01.s b/test/MC/SystemZ/insn-lhr-01.s new file mode 100644 index 000000000000..a31cbc65f44d --- /dev/null +++ b/test/MC/SystemZ/insn-lhr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lhr %r0, %r15 # encoding: [0xb9,0x27,0x00,0x0f] +#CHECK: lhr %r7, %r8 # encoding: [0xb9,0x27,0x00,0x78] +#CHECK: lhr %r15, %r0 # encoding: [0xb9,0x27,0x00,0xf0] + + lhr %r0, %r15 + lhr %r7, %r8 + lhr %r15, %r0 diff --git a/test/MC/SystemZ/insn-lhrl-01.s b/test/MC/SystemZ/insn-lhrl-01.s new file mode 100644 index 000000000000..87925fe09870 --- /dev/null +++ b/test/MC/SystemZ/insn-lhrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lhrl %r0, 2864434397 # encoding: [0xc4,0x05,0x55,0x5d,0xe6,0x6e] +#CHECK: lhrl %r15, 2864434397 # encoding: [0xc4,0xf5,0x55,0x5d,0xe6,0x6e] + + lhrl %r0,0xaabbccdd + lhrl %r15,0xaabbccdd + +#CHECK: lhrl %r0, foo # encoding: [0xc4,0x05,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: lhrl %r15, foo # encoding: [0xc4,0xf5,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + lhrl %r0,foo + lhrl %r15,foo + +#CHECK: lhrl %r3, bar+100 # encoding: [0xc4,0x35,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: lhrl %r4, bar+100 # encoding: [0xc4,0x45,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + lhrl %r3,bar+100 + lhrl %r4,bar+100 + +#CHECK: lhrl %r7, frob@PLT # encoding: [0xc4,0x75,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: lhrl %r8, frob@PLT # encoding: [0xc4,0x85,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + lhrl %r7,frob@PLT + lhrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lhy-01.s b/test/MC/SystemZ/insn-lhy-01.s new file mode 100644 index 000000000000..db811a41a4a5 --- /dev/null +++ b/test/MC/SystemZ/insn-lhy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lhy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x78] +#CHECK: lhy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x78] +#CHECK: lhy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x78] +#CHECK: lhy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x78] +#CHECK: lhy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x78] +#CHECK: lhy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x78] +#CHECK: lhy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x78] +#CHECK: lhy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x78] +#CHECK: lhy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x78] +#CHECK: lhy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x78] + + lhy %r0, -524288 + lhy %r0, -1 + lhy %r0, 0 + lhy %r0, 1 + lhy %r0, 524287 + lhy %r0, 0(%r1) + lhy %r0, 0(%r15) + lhy %r0, 524287(%r1,%r15) + lhy %r0, 524287(%r15,%r1) + lhy %r15, 0 diff --git a/test/MC/SystemZ/insn-lhy-02.s b/test/MC/SystemZ/insn-lhy-02.s new file mode 100644 index 000000000000..6f1caa59faf5 --- /dev/null +++ b/test/MC/SystemZ/insn-lhy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lhy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lhy %r0, 524288 + + lhy %r0, -524289 + lhy %r0, 524288 diff --git a/test/MC/SystemZ/insn-llc-01.s b/test/MC/SystemZ/insn-llc-01.s new file mode 100644 index 000000000000..74a819b2ee30 --- /dev/null +++ b/test/MC/SystemZ/insn-llc-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x94] +#CHECK: llc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x94] +#CHECK: llc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x94] +#CHECK: llc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x94] +#CHECK: llc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x94] +#CHECK: llc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x94] +#CHECK: llc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x94] +#CHECK: llc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x94] +#CHECK: llc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x94] +#CHECK: llc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x94] + + llc %r0, -524288 + llc %r0, -1 + llc %r0, 0 + llc %r0, 1 + llc %r0, 524287 + llc %r0, 0(%r1) + llc %r0, 0(%r15) + llc %r0, 524287(%r1,%r15) + llc %r0, 524287(%r15,%r1) + llc %r15, 0 diff --git a/test/MC/SystemZ/insn-llc-02.s b/test/MC/SystemZ/insn-llc-02.s new file mode 100644 index 000000000000..4a65f6c55e78 --- /dev/null +++ b/test/MC/SystemZ/insn-llc-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llc %r0, 524288 + + llc %r0, -524289 + llc %r0, 524288 diff --git a/test/MC/SystemZ/insn-llcr-01.s b/test/MC/SystemZ/insn-llcr-01.s new file mode 100644 index 000000000000..72a695ceffa7 --- /dev/null +++ b/test/MC/SystemZ/insn-llcr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llcr %r0, %r15 # encoding: [0xb9,0x94,0x00,0x0f] +#CHECK: llcr %r7, %r8 # encoding: [0xb9,0x94,0x00,0x78] +#CHECK: llcr %r15, %r0 # encoding: [0xb9,0x94,0x00,0xf0] + + llcr %r0, %r15 + llcr %r7, %r8 + llcr %r15, %r0 diff --git a/test/MC/SystemZ/insn-llgc-01.s b/test/MC/SystemZ/insn-llgc-01.s new file mode 100644 index 000000000000..297c6d62db4f --- /dev/null +++ b/test/MC/SystemZ/insn-llgc-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x90] +#CHECK: llgc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x90] +#CHECK: llgc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x90] +#CHECK: llgc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x90] +#CHECK: llgc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x90] +#CHECK: llgc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x90] +#CHECK: llgc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x90] +#CHECK: llgc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x90] +#CHECK: llgc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x90] +#CHECK: llgc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x90] + + llgc %r0, -524288 + llgc %r0, -1 + llgc %r0, 0 + llgc %r0, 1 + llgc %r0, 524287 + llgc %r0, 0(%r1) + llgc %r0, 0(%r15) + llgc %r0, 524287(%r1,%r15) + llgc %r0, 524287(%r15,%r1) + llgc %r15, 0 + diff --git a/test/MC/SystemZ/insn-llgc-02.s b/test/MC/SystemZ/insn-llgc-02.s new file mode 100644 index 000000000000..76fca0f2512f --- /dev/null +++ b/test/MC/SystemZ/insn-llgc-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llgc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llgc %r0, 524288 + + llgc %r0, -524289 + llgc %r0, 524288 diff --git a/test/MC/SystemZ/insn-llgcr-01.s b/test/MC/SystemZ/insn-llgcr-01.s new file mode 100644 index 000000000000..5d653bfff909 --- /dev/null +++ b/test/MC/SystemZ/insn-llgcr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgcr %r0, %r15 # encoding: [0xb9,0x84,0x00,0x0f] +#CHECK: llgcr %r7, %r8 # encoding: [0xb9,0x84,0x00,0x78] +#CHECK: llgcr %r15, %r0 # encoding: [0xb9,0x84,0x00,0xf0] + + llgcr %r0, %r15 + llgcr %r7, %r8 + llgcr %r15, %r0 diff --git a/test/MC/SystemZ/insn-llgf-01.s b/test/MC/SystemZ/insn-llgf-01.s new file mode 100644 index 000000000000..0394140dab82 --- /dev/null +++ b/test/MC/SystemZ/insn-llgf-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x16] +#CHECK: llgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x16] +#CHECK: llgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x16] +#CHECK: llgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x16] +#CHECK: llgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x16] +#CHECK: llgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x16] +#CHECK: llgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x16] +#CHECK: llgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x16] +#CHECK: llgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x16] +#CHECK: llgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x16] + + llgf %r0, -524288 + llgf %r0, -1 + llgf %r0, 0 + llgf %r0, 1 + llgf %r0, 524287 + llgf %r0, 0(%r1) + llgf %r0, 0(%r15) + llgf %r0, 524287(%r1,%r15) + llgf %r0, 524287(%r15,%r1) + llgf %r15, 0 + diff --git a/test/MC/SystemZ/insn-llgf-02.s b/test/MC/SystemZ/insn-llgf-02.s new file mode 100644 index 000000000000..0b2fab033aad --- /dev/null +++ b/test/MC/SystemZ/insn-llgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llgf %r0, 524288 + + llgf %r0, -524289 + llgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-llgfr-01.s b/test/MC/SystemZ/insn-llgfr-01.s new file mode 100644 index 000000000000..74f1074d150f --- /dev/null +++ b/test/MC/SystemZ/insn-llgfr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgfr %r0, %r15 # encoding: [0xb9,0x16,0x00,0x0f] +#CHECK: llgfr %r7, %r8 # encoding: [0xb9,0x16,0x00,0x78] +#CHECK: llgfr %r15, %r0 # encoding: [0xb9,0x16,0x00,0xf0] + + llgfr %r0, %r15 + llgfr %r7, %r8 + llgfr %r15, %r0 diff --git a/test/MC/SystemZ/insn-llgfrl-01.s b/test/MC/SystemZ/insn-llgfrl-01.s new file mode 100644 index 000000000000..85fc9f4b3c3f --- /dev/null +++ b/test/MC/SystemZ/insn-llgfrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgfrl %r0, 2864434397 # encoding: [0xc4,0x0e,0x55,0x5d,0xe6,0x6e] +#CHECK: llgfrl %r15, 2864434397 # encoding: [0xc4,0xfe,0x55,0x5d,0xe6,0x6e] + + llgfrl %r0,0xaabbccdd + llgfrl %r15,0xaabbccdd + +#CHECK: llgfrl %r0, foo # encoding: [0xc4,0x0e,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: llgfrl %r15, foo # encoding: [0xc4,0xfe,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + llgfrl %r0,foo + llgfrl %r15,foo + +#CHECK: llgfrl %r3, bar+100 # encoding: [0xc4,0x3e,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: llgfrl %r4, bar+100 # encoding: [0xc4,0x4e,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + llgfrl %r3,bar+100 + llgfrl %r4,bar+100 + +#CHECK: llgfrl %r7, frob@PLT # encoding: [0xc4,0x7e,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: llgfrl %r8, frob@PLT # encoding: [0xc4,0x8e,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + llgfrl %r7,frob@PLT + llgfrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-llgh-01.s b/test/MC/SystemZ/insn-llgh-01.s new file mode 100644 index 000000000000..acbab004382c --- /dev/null +++ b/test/MC/SystemZ/insn-llgh-01.s @@ -0,0 +1,24 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x91] +#CHECK: llgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x91] +#CHECK: llgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x91] +#CHECK: llgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x91] +#CHECK: llgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x91] +#CHECK: llgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x91] +#CHECK: llgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x91] +#CHECK: llgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x91] +#CHECK: llgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x91] +#CHECK: llgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x91] + + llgh %r0, -524288 + llgh %r0, -1 + llgh %r0, 0 + llgh %r0, 1 + llgh %r0, 524287 + llgh %r0, 0(%r1) + llgh %r0, 0(%r15) + llgh %r0, 524287(%r1,%r15) + llgh %r0, 524287(%r15,%r1) + llgh %r15, 0 + diff --git a/test/MC/SystemZ/insn-llgh-02.s b/test/MC/SystemZ/insn-llgh-02.s new file mode 100644 index 000000000000..95b6b12c91e6 --- /dev/null +++ b/test/MC/SystemZ/insn-llgh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llgh %r0, 524288 + + llgh %r0, -524289 + llgh %r0, 524288 diff --git a/test/MC/SystemZ/insn-llghr-01.s b/test/MC/SystemZ/insn-llghr-01.s new file mode 100644 index 000000000000..3e2f6de2ae8f --- /dev/null +++ b/test/MC/SystemZ/insn-llghr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llghr %r0, %r15 # encoding: [0xb9,0x85,0x00,0x0f] +#CHECK: llghr %r7, %r8 # encoding: [0xb9,0x85,0x00,0x78] +#CHECK: llghr %r15, %r0 # encoding: [0xb9,0x85,0x00,0xf0] + + llghr %r0, %r15 + llghr %r7, %r8 + llghr %r15, %r0 diff --git a/test/MC/SystemZ/insn-llghrl-01.s b/test/MC/SystemZ/insn-llghrl-01.s new file mode 100644 index 000000000000..af3fa8b9d787 --- /dev/null +++ b/test/MC/SystemZ/insn-llghrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llghrl %r0, 2864434397 # encoding: [0xc4,0x06,0x55,0x5d,0xe6,0x6e] +#CHECK: llghrl %r15, 2864434397 # encoding: [0xc4,0xf6,0x55,0x5d,0xe6,0x6e] + + llghrl %r0,0xaabbccdd + llghrl %r15,0xaabbccdd + +#CHECK: llghrl %r0, foo # encoding: [0xc4,0x06,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: llghrl %r15, foo # encoding: [0xc4,0xf6,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + llghrl %r0,foo + llghrl %r15,foo + +#CHECK: llghrl %r3, bar+100 # encoding: [0xc4,0x36,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: llghrl %r4, bar+100 # encoding: [0xc4,0x46,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + llghrl %r3,bar+100 + llghrl %r4,bar+100 + +#CHECK: llghrl %r7, frob@PLT # encoding: [0xc4,0x76,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: llghrl %r8, frob@PLT # encoding: [0xc4,0x86,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + llghrl %r7,frob@PLT + llghrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-llh-01.s b/test/MC/SystemZ/insn-llh-01.s new file mode 100644 index 000000000000..7e15f3f6d601 --- /dev/null +++ b/test/MC/SystemZ/insn-llh-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x95] +#CHECK: llh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x95] +#CHECK: llh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x95] +#CHECK: llh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x95] +#CHECK: llh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x95] +#CHECK: llh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x95] +#CHECK: llh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x95] +#CHECK: llh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x95] +#CHECK: llh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x95] +#CHECK: llh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x95] + + llh %r0, -524288 + llh %r0, -1 + llh %r0, 0 + llh %r0, 1 + llh %r0, 524287 + llh %r0, 0(%r1) + llh %r0, 0(%r15) + llh %r0, 524287(%r1,%r15) + llh %r0, 524287(%r15,%r1) + llh %r15, 0 diff --git a/test/MC/SystemZ/insn-llh-02.s b/test/MC/SystemZ/insn-llh-02.s new file mode 100644 index 000000000000..92c49bb59c29 --- /dev/null +++ b/test/MC/SystemZ/insn-llh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llh %r0, 524288 + + llh %r0, -524289 + llh %r0, 524288 diff --git a/test/MC/SystemZ/insn-llhr-01.s b/test/MC/SystemZ/insn-llhr-01.s new file mode 100644 index 000000000000..bb1d3b5d32fb --- /dev/null +++ b/test/MC/SystemZ/insn-llhr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llhr %r0, %r15 # encoding: [0xb9,0x95,0x00,0x0f] +#CHECK: llhr %r7, %r8 # encoding: [0xb9,0x95,0x00,0x78] +#CHECK: llhr %r15, %r0 # encoding: [0xb9,0x95,0x00,0xf0] + + llhr %r0, %r15 + llhr %r7, %r8 + llhr %r15, %r0 diff --git a/test/MC/SystemZ/insn-llhrl-01.s b/test/MC/SystemZ/insn-llhrl-01.s new file mode 100644 index 000000000000..30ed4f90565c --- /dev/null +++ b/test/MC/SystemZ/insn-llhrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llhrl %r0, 2864434397 # encoding: [0xc4,0x02,0x55,0x5d,0xe6,0x6e] +#CHECK: llhrl %r15, 2864434397 # encoding: [0xc4,0xf2,0x55,0x5d,0xe6,0x6e] + + llhrl %r0,0xaabbccdd + llhrl %r15,0xaabbccdd + +#CHECK: llhrl %r0, foo # encoding: [0xc4,0x02,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: llhrl %r15, foo # encoding: [0xc4,0xf2,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + llhrl %r0,foo + llhrl %r15,foo + +#CHECK: llhrl %r3, bar+100 # encoding: [0xc4,0x32,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: llhrl %r4, bar+100 # encoding: [0xc4,0x42,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + llhrl %r3,bar+100 + llhrl %r4,bar+100 + +#CHECK: llhrl %r7, frob@PLT # encoding: [0xc4,0x72,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: llhrl %r8, frob@PLT # encoding: [0xc4,0x82,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + llhrl %r7,frob@PLT + llhrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-llihf-01.s b/test/MC/SystemZ/insn-llihf-01.s new file mode 100644 index 000000000000..6ddd29ffa370 --- /dev/null +++ b/test/MC/SystemZ/insn-llihf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llihf %r0, 0 # encoding: [0xc0,0x0e,0x00,0x00,0x00,0x00] +#CHECK: llihf %r0, 4294967295 # encoding: [0xc0,0x0e,0xff,0xff,0xff,0xff] +#CHECK: llihf %r15, 0 # encoding: [0xc0,0xfe,0x00,0x00,0x00,0x00] + + llihf %r0, 0 + llihf %r0, 0xffffffff + llihf %r15, 0 diff --git a/test/MC/SystemZ/insn-llihf-02.s b/test/MC/SystemZ/insn-llihf-02.s new file mode 100644 index 000000000000..e1b4537b02c8 --- /dev/null +++ b/test/MC/SystemZ/insn-llihf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llihf %r0, -1 +#CHECK: error: invalid operand +#CHECK: llihf %r0, 1 << 32 + + llihf %r0, -1 + llihf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-llihh-01.s b/test/MC/SystemZ/insn-llihh-01.s new file mode 100644 index 000000000000..06060765c740 --- /dev/null +++ b/test/MC/SystemZ/insn-llihh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llihh %r0, 0 # encoding: [0xa5,0x0c,0x00,0x00] +#CHECK: llihh %r0, 32768 # encoding: [0xa5,0x0c,0x80,0x00] +#CHECK: llihh %r0, 65535 # encoding: [0xa5,0x0c,0xff,0xff] +#CHECK: llihh %r15, 0 # encoding: [0xa5,0xfc,0x00,0x00] + + llihh %r0, 0 + llihh %r0, 0x8000 + llihh %r0, 0xffff + llihh %r15, 0 diff --git a/test/MC/SystemZ/insn-llihh-02.s b/test/MC/SystemZ/insn-llihh-02.s new file mode 100644 index 000000000000..1309f1440f59 --- /dev/null +++ b/test/MC/SystemZ/insn-llihh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llihh %r0, -1 +#CHECK: error: invalid operand +#CHECK: llihh %r0, 0x10000 + + llihh %r0, -1 + llihh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-llihl-01.s b/test/MC/SystemZ/insn-llihl-01.s new file mode 100644 index 000000000000..6353353321c3 --- /dev/null +++ b/test/MC/SystemZ/insn-llihl-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llihl %r0, 0 # encoding: [0xa5,0x0d,0x00,0x00] +#CHECK: llihl %r0, 32768 # encoding: [0xa5,0x0d,0x80,0x00] +#CHECK: llihl %r0, 65535 # encoding: [0xa5,0x0d,0xff,0xff] +#CHECK: llihl %r15, 0 # encoding: [0xa5,0xfd,0x00,0x00] + + llihl %r0, 0 + llihl %r0, 0x8000 + llihl %r0, 0xffff + llihl %r15, 0 diff --git a/test/MC/SystemZ/insn-llihl-02.s b/test/MC/SystemZ/insn-llihl-02.s new file mode 100644 index 000000000000..6891c4219624 --- /dev/null +++ b/test/MC/SystemZ/insn-llihl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llihl %r0, -1 +#CHECK: error: invalid operand +#CHECK: llihl %r0, 0x10000 + + llihl %r0, -1 + llihl %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-llilf-01.s b/test/MC/SystemZ/insn-llilf-01.s new file mode 100644 index 000000000000..8166583a2c01 --- /dev/null +++ b/test/MC/SystemZ/insn-llilf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llilf %r0, 0 # encoding: [0xc0,0x0f,0x00,0x00,0x00,0x00] +#CHECK: llilf %r0, 4294967295 # encoding: [0xc0,0x0f,0xff,0xff,0xff,0xff] +#CHECK: llilf %r15, 0 # encoding: [0xc0,0xff,0x00,0x00,0x00,0x00] + + llilf %r0, 0 + llilf %r0, 0xffffffff + llilf %r15, 0 diff --git a/test/MC/SystemZ/insn-llilf-02.s b/test/MC/SystemZ/insn-llilf-02.s new file mode 100644 index 000000000000..dc10cc34ee00 --- /dev/null +++ b/test/MC/SystemZ/insn-llilf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llilf %r0, -1 +#CHECK: error: invalid operand +#CHECK: llilf %r0, 1 << 32 + + llilf %r0, -1 + llilf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-llilh-01.s b/test/MC/SystemZ/insn-llilh-01.s new file mode 100644 index 000000000000..2ec5a7952f08 --- /dev/null +++ b/test/MC/SystemZ/insn-llilh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llilh %r0, 0 # encoding: [0xa5,0x0e,0x00,0x00] +#CHECK: llilh %r0, 32768 # encoding: [0xa5,0x0e,0x80,0x00] +#CHECK: llilh %r0, 65535 # encoding: [0xa5,0x0e,0xff,0xff] +#CHECK: llilh %r15, 0 # encoding: [0xa5,0xfe,0x00,0x00] + + llilh %r0, 0 + llilh %r0, 0x8000 + llilh %r0, 0xffff + llilh %r15, 0 diff --git a/test/MC/SystemZ/insn-llilh-02.s b/test/MC/SystemZ/insn-llilh-02.s new file mode 100644 index 000000000000..bdfa1e77435a --- /dev/null +++ b/test/MC/SystemZ/insn-llilh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llilh %r0, -1 +#CHECK: error: invalid operand +#CHECK: llilh %r0, 0x10000 + + llilh %r0, -1 + llilh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-llill-01.s b/test/MC/SystemZ/insn-llill-01.s new file mode 100644 index 000000000000..b95841da4d01 --- /dev/null +++ b/test/MC/SystemZ/insn-llill-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: llill %r0, 0 # encoding: [0xa5,0x0f,0x00,0x00] +#CHECK: llill %r0, 32768 # encoding: [0xa5,0x0f,0x80,0x00] +#CHECK: llill %r0, 65535 # encoding: [0xa5,0x0f,0xff,0xff] +#CHECK: llill %r15, 0 # encoding: [0xa5,0xff,0x00,0x00] + + llill %r0, 0 + llill %r0, 0x8000 + llill %r0, 0xffff + llill %r15, 0 diff --git a/test/MC/SystemZ/insn-llill-02.s b/test/MC/SystemZ/insn-llill-02.s new file mode 100644 index 000000000000..2503b533317f --- /dev/null +++ b/test/MC/SystemZ/insn-llill-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: llill %r0, -1 +#CHECK: error: invalid operand +#CHECK: llill %r0, 0x10000 + + llill %r0, -1 + llill %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-lmg-01.s b/test/MC/SystemZ/insn-lmg-01.s new file mode 100644 index 000000000000..24a2768192c9 --- /dev/null +++ b/test/MC/SystemZ/insn-lmg-01.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04] +#CHECK: lmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x04] +#CHECK: lmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x04] +#CHECK: lmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x04] +#CHECK: lmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x04] +#CHECK: lmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x04] +#CHECK: lmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x04] +#CHECK: lmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x04] +#CHECK: lmg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x04] +#CHECK: lmg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x04] +#CHECK: lmg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x04] +#CHECK: lmg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x04] +#CHECK: lmg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x04] + + lmg %r0,%r0,0 + lmg %r0,%r15,0 + lmg %r14,%r15,0 + lmg %r15,%r15,0 + lmg %r0,%r0,-524288 + lmg %r0,%r0,-1 + lmg %r0,%r0,0 + lmg %r0,%r0,1 + lmg %r0,%r0,524287 + lmg %r0,%r0,0(%r1) + lmg %r0,%r0,0(%r15) + lmg %r0,%r0,524287(%r1) + lmg %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-lmg-02.s b/test/MC/SystemZ/insn-lmg-02.s new file mode 100644 index 000000000000..9a67c08ee649 --- /dev/null +++ b/test/MC/SystemZ/insn-lmg-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lmg %r0, %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lmg %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: lmg %r0, %r0, 0(%r1,%r2) + + lmg %r0, %r0, -524289 + lmg %r0, %r0, 524288 + lmg %r0, %r0, 0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-lndbr-01.s b/test/MC/SystemZ/insn-lndbr-01.s new file mode 100644 index 000000000000..22786238ab59 --- /dev/null +++ b/test/MC/SystemZ/insn-lndbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lndbr %f0, %f9 # encoding: [0xb3,0x11,0x00,0x09] +#CHECK: lndbr %f0, %f15 # encoding: [0xb3,0x11,0x00,0x0f] +#CHECK: lndbr %f15, %f0 # encoding: [0xb3,0x11,0x00,0xf0] +#CHECK: lndbr %f15, %f9 # encoding: [0xb3,0x11,0x00,0xf9] + + lndbr %f0,%f9 + lndbr %f0,%f15 + lndbr %f15,%f0 + lndbr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lnebr-01.s b/test/MC/SystemZ/insn-lnebr-01.s new file mode 100644 index 000000000000..cf32734ad21f --- /dev/null +++ b/test/MC/SystemZ/insn-lnebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lnebr %f0, %f9 # encoding: [0xb3,0x01,0x00,0x09] +#CHECK: lnebr %f0, %f15 # encoding: [0xb3,0x01,0x00,0x0f] +#CHECK: lnebr %f15, %f0 # encoding: [0xb3,0x01,0x00,0xf0] +#CHECK: lnebr %f15, %f9 # encoding: [0xb3,0x01,0x00,0xf9] + + lnebr %f0,%f9 + lnebr %f0,%f15 + lnebr %f15,%f0 + lnebr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lnxbr-01.s b/test/MC/SystemZ/insn-lnxbr-01.s new file mode 100644 index 000000000000..bf3794859ed1 --- /dev/null +++ b/test/MC/SystemZ/insn-lnxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lnxbr %f0, %f8 # encoding: [0xb3,0x41,0x00,0x08] +#CHECK: lnxbr %f0, %f13 # encoding: [0xb3,0x41,0x00,0x0d] +#CHECK: lnxbr %f13, %f0 # encoding: [0xb3,0x41,0x00,0xd0] +#CHECK: lnxbr %f13, %f9 # encoding: [0xb3,0x41,0x00,0xd9] + + lnxbr %f0,%f8 + lnxbr %f0,%f13 + lnxbr %f13,%f0 + lnxbr %f13,%f9 diff --git a/test/MC/SystemZ/insn-lnxbr-02.s b/test/MC/SystemZ/insn-lnxbr-02.s new file mode 100644 index 000000000000..9a69f48a0638 --- /dev/null +++ b/test/MC/SystemZ/insn-lnxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lnxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: lnxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: lnxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: lnxbr %f14, %f0 + + lnxbr %f0, %f2 + lnxbr %f0, %f14 + lnxbr %f2, %f0 + lnxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-lpdbr-01.s b/test/MC/SystemZ/insn-lpdbr-01.s new file mode 100644 index 000000000000..869b0c9117e3 --- /dev/null +++ b/test/MC/SystemZ/insn-lpdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lpdbr %f0, %f9 # encoding: [0xb3,0x10,0x00,0x09] +#CHECK: lpdbr %f0, %f15 # encoding: [0xb3,0x10,0x00,0x0f] +#CHECK: lpdbr %f15, %f0 # encoding: [0xb3,0x10,0x00,0xf0] +#CHECK: lpdbr %f15, %f9 # encoding: [0xb3,0x10,0x00,0xf9] + + lpdbr %f0,%f9 + lpdbr %f0,%f15 + lpdbr %f15,%f0 + lpdbr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lpebr-01.s b/test/MC/SystemZ/insn-lpebr-01.s new file mode 100644 index 000000000000..917f26e9aee5 --- /dev/null +++ b/test/MC/SystemZ/insn-lpebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lpebr %f0, %f9 # encoding: [0xb3,0x00,0x00,0x09] +#CHECK: lpebr %f0, %f15 # encoding: [0xb3,0x00,0x00,0x0f] +#CHECK: lpebr %f15, %f0 # encoding: [0xb3,0x00,0x00,0xf0] +#CHECK: lpebr %f15, %f9 # encoding: [0xb3,0x00,0x00,0xf9] + + lpebr %f0,%f9 + lpebr %f0,%f15 + lpebr %f15,%f0 + lpebr %f15,%f9 diff --git a/test/MC/SystemZ/insn-lpxbr-01.s b/test/MC/SystemZ/insn-lpxbr-01.s new file mode 100644 index 000000000000..56a628ab96c2 --- /dev/null +++ b/test/MC/SystemZ/insn-lpxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lpxbr %f0, %f8 # encoding: [0xb3,0x40,0x00,0x08] +#CHECK: lpxbr %f0, %f13 # encoding: [0xb3,0x40,0x00,0x0d] +#CHECK: lpxbr %f13, %f0 # encoding: [0xb3,0x40,0x00,0xd0] +#CHECK: lpxbr %f13, %f9 # encoding: [0xb3,0x40,0x00,0xd9] + + lpxbr %f0,%f8 + lpxbr %f0,%f13 + lpxbr %f13,%f0 + lpxbr %f13,%f9 diff --git a/test/MC/SystemZ/insn-lpxbr-02.s b/test/MC/SystemZ/insn-lpxbr-02.s new file mode 100644 index 000000000000..6fa3697111ea --- /dev/null +++ b/test/MC/SystemZ/insn-lpxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lpxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: lpxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: lpxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: lpxbr %f14, %f0 + + lpxbr %f0, %f2 + lpxbr %f0, %f14 + lpxbr %f2, %f0 + lpxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-lr-01.s b/test/MC/SystemZ/insn-lr-01.s new file mode 100644 index 000000000000..8ce4a00678d6 --- /dev/null +++ b/test/MC/SystemZ/insn-lr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lr %r0, %r9 # encoding: [0x18,0x09] +#CHECK: lr %r0, %r15 # encoding: [0x18,0x0f] +#CHECK: lr %r15, %r0 # encoding: [0x18,0xf0] +#CHECK: lr %r15, %r9 # encoding: [0x18,0xf9] + + lr %r0,%r9 + lr %r0,%r15 + lr %r15,%r0 + lr %r15,%r9 diff --git a/test/MC/SystemZ/insn-lrl-01.s b/test/MC/SystemZ/insn-lrl-01.s new file mode 100644 index 000000000000..32d0eeb2b848 --- /dev/null +++ b/test/MC/SystemZ/insn-lrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lrl %r0, 2864434397 # encoding: [0xc4,0x0d,0x55,0x5d,0xe6,0x6e] +#CHECK: lrl %r15, 2864434397 # encoding: [0xc4,0xfd,0x55,0x5d,0xe6,0x6e] + + lrl %r0,0xaabbccdd + lrl %r15,0xaabbccdd + +#CHECK: lrl %r0, foo # encoding: [0xc4,0x0d,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: lrl %r15, foo # encoding: [0xc4,0xfd,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + lrl %r0,foo + lrl %r15,foo + +#CHECK: lrl %r3, bar+100 # encoding: [0xc4,0x3d,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: lrl %r4, bar+100 # encoding: [0xc4,0x4d,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + lrl %r3,bar+100 + lrl %r4,bar+100 + +#CHECK: lrl %r7, frob@PLT # encoding: [0xc4,0x7d,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: lrl %r8, frob@PLT # encoding: [0xc4,0x8d,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + lrl %r7,frob@PLT + lrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-lrv-01.s b/test/MC/SystemZ/insn-lrv-01.s new file mode 100644 index 000000000000..75b973a22d0e --- /dev/null +++ b/test/MC/SystemZ/insn-lrv-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lrv %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1e] +#CHECK: lrv %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1e] +#CHECK: lrv %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1e] +#CHECK: lrv %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1e] +#CHECK: lrv %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1e] +#CHECK: lrv %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1e] +#CHECK: lrv %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1e] +#CHECK: lrv %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x1e] +#CHECK: lrv %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x1e] +#CHECK: lrv %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x1e] + + lrv %r0,-524288 + lrv %r0,-1 + lrv %r0,0 + lrv %r0,1 + lrv %r0,524287 + lrv %r0,0(%r1) + lrv %r0,0(%r15) + lrv %r0,524287(%r1,%r15) + lrv %r0,524287(%r15,%r1) + lrv %r15,0 diff --git a/test/MC/SystemZ/insn-lrv-02.s b/test/MC/SystemZ/insn-lrv-02.s new file mode 100644 index 000000000000..f2dcfa777a26 --- /dev/null +++ b/test/MC/SystemZ/insn-lrv-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lrv %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lrv %r0, 524288 + + lrv %r0, -524289 + lrv %r0, 524288 diff --git a/test/MC/SystemZ/insn-lrvg-01.s b/test/MC/SystemZ/insn-lrvg-01.s new file mode 100644 index 000000000000..d2d8b2db43d4 --- /dev/null +++ b/test/MC/SystemZ/insn-lrvg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lrvg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0f] +#CHECK: lrvg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0f] +#CHECK: lrvg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0f] +#CHECK: lrvg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0f] +#CHECK: lrvg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0f] +#CHECK: lrvg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0f] +#CHECK: lrvg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0f] +#CHECK: lrvg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0f] +#CHECK: lrvg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0f] +#CHECK: lrvg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0f] + + lrvg %r0,-524288 + lrvg %r0,-1 + lrvg %r0,0 + lrvg %r0,1 + lrvg %r0,524287 + lrvg %r0,0(%r1) + lrvg %r0,0(%r15) + lrvg %r0,524287(%r1,%r15) + lrvg %r0,524287(%r15,%r1) + lrvg %r15,0 diff --git a/test/MC/SystemZ/insn-lrvg-02.s b/test/MC/SystemZ/insn-lrvg-02.s new file mode 100644 index 000000000000..690fa1350092 --- /dev/null +++ b/test/MC/SystemZ/insn-lrvg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: lrvg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lrvg %r0, 524288 + + lrvg %r0, -524289 + lrvg %r0, 524288 diff --git a/test/MC/SystemZ/insn-lrvgr-01.s b/test/MC/SystemZ/insn-lrvgr-01.s new file mode 100644 index 000000000000..1b6e8841ee2c --- /dev/null +++ b/test/MC/SystemZ/insn-lrvgr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lrvgr %r0, %r0 # encoding: [0xb9,0x0f,0x00,0x00] +#CHECK: lrvgr %r0, %r15 # encoding: [0xb9,0x0f,0x00,0x0f] +#CHECK: lrvgr %r15, %r0 # encoding: [0xb9,0x0f,0x00,0xf0] +#CHECK: lrvgr %r7, %r8 # encoding: [0xb9,0x0f,0x00,0x78] +#CHECK: lrvgr %r15, %r15 # encoding: [0xb9,0x0f,0x00,0xff] + + lrvgr %r0,%r0 + lrvgr %r0,%r15 + lrvgr %r15,%r0 + lrvgr %r7,%r8 + lrvgr %r15,%r15 diff --git a/test/MC/SystemZ/insn-lrvr-01.s b/test/MC/SystemZ/insn-lrvr-01.s new file mode 100644 index 000000000000..c0d5d895b8bc --- /dev/null +++ b/test/MC/SystemZ/insn-lrvr-01.s @@ -0,0 +1,13 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lrvr %r0, %r0 # encoding: [0xb9,0x1f,0x00,0x00] +#CHECK: lrvr %r0, %r15 # encoding: [0xb9,0x1f,0x00,0x0f] +#CHECK: lrvr %r15, %r0 # encoding: [0xb9,0x1f,0x00,0xf0] +#CHECK: lrvr %r7, %r8 # encoding: [0xb9,0x1f,0x00,0x78] +#CHECK: lrvr %r15, %r15 # encoding: [0xb9,0x1f,0x00,0xff] + + lrvr %r0,%r0 + lrvr %r0,%r15 + lrvr %r15,%r0 + lrvr %r7,%r8 + lrvr %r15,%r15 diff --git a/test/MC/SystemZ/insn-lxr-01.s b/test/MC/SystemZ/insn-lxr-01.s new file mode 100644 index 000000000000..a04cdf747285 --- /dev/null +++ b/test/MC/SystemZ/insn-lxr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lxr %f0, %f8 # encoding: [0xb3,0x65,0x00,0x08] +#CHECK: lxr %f0, %f13 # encoding: [0xb3,0x65,0x00,0x0d] +#CHECK: lxr %f13, %f0 # encoding: [0xb3,0x65,0x00,0xd0] +#CHECK: lxr %f13, %f9 # encoding: [0xb3,0x65,0x00,0xd9] + + lxr %f0,%f8 + lxr %f0,%f13 + lxr %f13,%f0 + lxr %f13,%f9 diff --git a/test/MC/SystemZ/insn-lxr-02.s b/test/MC/SystemZ/insn-lxr-02.s new file mode 100644 index 000000000000..b18ad756b125 --- /dev/null +++ b/test/MC/SystemZ/insn-lxr-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lxr %f2, %f0 +#CHECK: error: invalid register +#CHECK: lxr %f15, %f0 +#CHECK: error: invalid register +#CHECK: lxr %f0, %f2 +#CHECK: error: invalid register +#CHECK: lxr %f0, %f15 + + lxr %f2, %f0 + lxr %f15, %f0 + lxr %f0, %f2 + lxr %f0, %f15 diff --git a/test/MC/SystemZ/insn-ly-01.s b/test/MC/SystemZ/insn-ly-01.s new file mode 100644 index 000000000000..25bc3e8a34c4 --- /dev/null +++ b/test/MC/SystemZ/insn-ly-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ly %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x58] +#CHECK: ly %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x58] +#CHECK: ly %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x58] +#CHECK: ly %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x58] +#CHECK: ly %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x58] +#CHECK: ly %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x58] +#CHECK: ly %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x58] +#CHECK: ly %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x58] +#CHECK: ly %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x58] +#CHECK: ly %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x58] + + ly %r0, -524288 + ly %r0, -1 + ly %r0, 0 + ly %r0, 1 + ly %r0, 524287 + ly %r0, 0(%r1) + ly %r0, 0(%r15) + ly %r0, 524287(%r1,%r15) + ly %r0, 524287(%r15,%r1) + ly %r15, 0 diff --git a/test/MC/SystemZ/insn-ly-02.s b/test/MC/SystemZ/insn-ly-02.s new file mode 100644 index 000000000000..b2d424e1152e --- /dev/null +++ b/test/MC/SystemZ/insn-ly-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ly %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ly %r0, 524288 + + ly %r0, -524289 + ly %r0, 524288 diff --git a/test/MC/SystemZ/insn-lzdr-01.s b/test/MC/SystemZ/insn-lzdr-01.s new file mode 100644 index 000000000000..c95082f47b75 --- /dev/null +++ b/test/MC/SystemZ/insn-lzdr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lzdr %f0 # encoding: [0xb3,0x75,0x00,0x00] +#CHECK: lzdr %f7 # encoding: [0xb3,0x75,0x00,0x70] +#CHECK: lzdr %f15 # encoding: [0xb3,0x75,0x00,0xf0] + + lzdr %f0 + lzdr %f7 + lzdr %f15 diff --git a/test/MC/SystemZ/insn-lzer-01.s b/test/MC/SystemZ/insn-lzer-01.s new file mode 100644 index 000000000000..0944047a5ba6 --- /dev/null +++ b/test/MC/SystemZ/insn-lzer-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lzer %f0 # encoding: [0xb3,0x74,0x00,0x00] +#CHECK: lzer %f7 # encoding: [0xb3,0x74,0x00,0x70] +#CHECK: lzer %f15 # encoding: [0xb3,0x74,0x00,0xf0] + + lzer %f0 + lzer %f7 + lzer %f15 diff --git a/test/MC/SystemZ/insn-lzxr-01.s b/test/MC/SystemZ/insn-lzxr-01.s new file mode 100644 index 000000000000..bd5a5c2ea13c --- /dev/null +++ b/test/MC/SystemZ/insn-lzxr-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lzxr %f0 # encoding: [0xb3,0x76,0x00,0x00] +#CHECK: lzxr %f8 # encoding: [0xb3,0x76,0x00,0x80] +#CHECK: lzxr %f13 # encoding: [0xb3,0x76,0x00,0xd0] + + lzxr %f0 + lzxr %f8 + lzxr %f13 diff --git a/test/MC/SystemZ/insn-lzxr-02.s b/test/MC/SystemZ/insn-lzxr-02.s new file mode 100644 index 000000000000..4ce2ad04bc6e --- /dev/null +++ b/test/MC/SystemZ/insn-lzxr-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lzxr %f2 +#CHECK: error: invalid register +#CHECK: lzxr %f14 +#CHECK: error: invalid register +#CHECK: lzxr %f15 + + lzxr %f2 + lzxr %f14 + lzxr %f15 diff --git a/test/MC/SystemZ/insn-madb-01.s b/test/MC/SystemZ/insn-madb-01.s new file mode 100644 index 000000000000..6eec4beb37a2 --- /dev/null +++ b/test/MC/SystemZ/insn-madb-01.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: madb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1e] +#CHECK: madb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1e] +#CHECK: madb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1e] +#CHECK: madb %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1e] +#CHECK: madb %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1e] +#CHECK: madb %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1e] +#CHECK: madb %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1e] +#CHECK: madb %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x1e] +#CHECK: madb %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x1e] + + madb %f0, %f0, 0 + madb %f0, %f0, 4095 + madb %f0, %f0, 0(%r1) + madb %f0, %f0, 0(%r15) + madb %f0, %f0, 4095(%r1,%r15) + madb %f0, %f0, 4095(%r15,%r1) + madb %f0, %f15, 0 + madb %f15, %f0, 0 + madb %f15, %f15, 0 diff --git a/test/MC/SystemZ/insn-madb-02.s b/test/MC/SystemZ/insn-madb-02.s new file mode 100644 index 000000000000..f7fdee978e13 --- /dev/null +++ b/test/MC/SystemZ/insn-madb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: madb %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: madb %f0, %f0, 4096 + + madb %f0, %f0, -1 + madb %f0, %f0, 4096 diff --git a/test/MC/SystemZ/insn-madbr-01.s b/test/MC/SystemZ/insn-madbr-01.s new file mode 100644 index 000000000000..42142be99e5a --- /dev/null +++ b/test/MC/SystemZ/insn-madbr-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: madbr %f0, %f0, %f0 # encoding: [0xb3,0x1e,0x00,0x00] +#CHECK: madbr %f0, %f0, %f15 # encoding: [0xb3,0x1e,0x00,0x0f] +#CHECK: madbr %f0, %f15, %f0 # encoding: [0xb3,0x1e,0x00,0xf0] +#CHECK: madbr %f15, %f0, %f0 # encoding: [0xb3,0x1e,0xf0,0x00] +#CHECK: madbr %f7, %f8, %f9 # encoding: [0xb3,0x1e,0x70,0x89] +#CHECK: madbr %f15, %f15, %f15 # encoding: [0xb3,0x1e,0xf0,0xff] + + madbr %f0, %f0, %f0 + madbr %f0, %f0, %f15 + madbr %f0, %f15, %f0 + madbr %f15, %f0, %f0 + madbr %f7, %f8, %f9 + madbr %f15, %f15, %f15 diff --git a/test/MC/SystemZ/insn-maeb-01.s b/test/MC/SystemZ/insn-maeb-01.s new file mode 100644 index 000000000000..7a998fd79ff9 --- /dev/null +++ b/test/MC/SystemZ/insn-maeb-01.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: maeb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0e] +#CHECK: maeb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0e] +#CHECK: maeb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0e] +#CHECK: maeb %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0e] +#CHECK: maeb %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0e] +#CHECK: maeb %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0e] +#CHECK: maeb %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0e] +#CHECK: maeb %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x0e] +#CHECK: maeb %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x0e] + + maeb %f0, %f0, 0 + maeb %f0, %f0, 4095 + maeb %f0, %f0, 0(%r1) + maeb %f0, %f0, 0(%r15) + maeb %f0, %f0, 4095(%r1,%r15) + maeb %f0, %f0, 4095(%r15,%r1) + maeb %f0, %f15, 0 + maeb %f15, %f0, 0 + maeb %f15, %f15, 0 diff --git a/test/MC/SystemZ/insn-maeb-02.s b/test/MC/SystemZ/insn-maeb-02.s new file mode 100644 index 000000000000..e12407acc2d0 --- /dev/null +++ b/test/MC/SystemZ/insn-maeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: maeb %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: maeb %f0, %f0, 4096 + + maeb %f0, %f0, -1 + maeb %f0, %f0, 4096 diff --git a/test/MC/SystemZ/insn-maebr-01.s b/test/MC/SystemZ/insn-maebr-01.s new file mode 100644 index 000000000000..be92aaf87483 --- /dev/null +++ b/test/MC/SystemZ/insn-maebr-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: maebr %f0, %f0, %f0 # encoding: [0xb3,0x0e,0x00,0x00] +#CHECK: maebr %f0, %f0, %f15 # encoding: [0xb3,0x0e,0x00,0x0f] +#CHECK: maebr %f0, %f15, %f0 # encoding: [0xb3,0x0e,0x00,0xf0] +#CHECK: maebr %f15, %f0, %f0 # encoding: [0xb3,0x0e,0xf0,0x00] +#CHECK: maebr %f7, %f8, %f9 # encoding: [0xb3,0x0e,0x70,0x89] +#CHECK: maebr %f15, %f15, %f15 # encoding: [0xb3,0x0e,0xf0,0xff] + + maebr %f0, %f0, %f0 + maebr %f0, %f0, %f15 + maebr %f0, %f15, %f0 + maebr %f15, %f0, %f0 + maebr %f7, %f8, %f9 + maebr %f15, %f15, %f15 diff --git a/test/MC/SystemZ/insn-mdb-01.s b/test/MC/SystemZ/insn-mdb-01.s new file mode 100644 index 000000000000..58be9779fc56 --- /dev/null +++ b/test/MC/SystemZ/insn-mdb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1c] +#CHECK: mdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1c] +#CHECK: mdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1c] +#CHECK: mdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1c] +#CHECK: mdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1c] +#CHECK: mdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1c] +#CHECK: mdb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1c] + + mdb %f0, 0 + mdb %f0, 4095 + mdb %f0, 0(%r1) + mdb %f0, 0(%r15) + mdb %f0, 4095(%r1,%r15) + mdb %f0, 4095(%r15,%r1) + mdb %f15, 0 diff --git a/test/MC/SystemZ/insn-mdb-02.s b/test/MC/SystemZ/insn-mdb-02.s new file mode 100644 index 000000000000..f1bdab015f1c --- /dev/null +++ b/test/MC/SystemZ/insn-mdb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: mdb %f0, 4096 + + mdb %f0, -1 + mdb %f0, 4096 diff --git a/test/MC/SystemZ/insn-mdbr-01.s b/test/MC/SystemZ/insn-mdbr-01.s new file mode 100644 index 000000000000..4ff16b9c0b36 --- /dev/null +++ b/test/MC/SystemZ/insn-mdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mdbr %f0, %f0 # encoding: [0xb3,0x1c,0x00,0x00] +#CHECK: mdbr %f0, %f15 # encoding: [0xb3,0x1c,0x00,0x0f] +#CHECK: mdbr %f7, %f8 # encoding: [0xb3,0x1c,0x00,0x78] +#CHECK: mdbr %f15, %f0 # encoding: [0xb3,0x1c,0x00,0xf0] + + mdbr %f0, %f0 + mdbr %f0, %f15 + mdbr %f7, %f8 + mdbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-mdeb-01.s b/test/MC/SystemZ/insn-mdeb-01.s new file mode 100644 index 000000000000..5d85c079db1f --- /dev/null +++ b/test/MC/SystemZ/insn-mdeb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mdeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0c] +#CHECK: mdeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0c] +#CHECK: mdeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0c] +#CHECK: mdeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0c] +#CHECK: mdeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0c] +#CHECK: mdeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0c] +#CHECK: mdeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0c] + + mdeb %f0, 0 + mdeb %f0, 4095 + mdeb %f0, 0(%r1) + mdeb %f0, 0(%r15) + mdeb %f0, 4095(%r1,%r15) + mdeb %f0, 4095(%r15,%r1) + mdeb %f15, 0 diff --git a/test/MC/SystemZ/insn-mdeb-02.s b/test/MC/SystemZ/insn-mdeb-02.s new file mode 100644 index 000000000000..87ec6767d4e1 --- /dev/null +++ b/test/MC/SystemZ/insn-mdeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mdeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: mdeb %f0, 4096 + + mdeb %f0, -1 + mdeb %f0, 4096 diff --git a/test/MC/SystemZ/insn-mdebr-01.s b/test/MC/SystemZ/insn-mdebr-01.s new file mode 100644 index 000000000000..17c495581d34 --- /dev/null +++ b/test/MC/SystemZ/insn-mdebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mdebr %f0, %f0 # encoding: [0xb3,0x0c,0x00,0x00] +#CHECK: mdebr %f0, %f15 # encoding: [0xb3,0x0c,0x00,0x0f] +#CHECK: mdebr %f7, %f8 # encoding: [0xb3,0x0c,0x00,0x78] +#CHECK: mdebr %f15, %f0 # encoding: [0xb3,0x0c,0x00,0xf0] + + mdebr %f0, %f0 + mdebr %f0, %f15 + mdebr %f7, %f8 + mdebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-meeb-01.s b/test/MC/SystemZ/insn-meeb-01.s new file mode 100644 index 000000000000..bb14d0435577 --- /dev/null +++ b/test/MC/SystemZ/insn-meeb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: meeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x17] +#CHECK: meeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x17] +#CHECK: meeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x17] +#CHECK: meeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x17] +#CHECK: meeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x17] +#CHECK: meeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x17] +#CHECK: meeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x17] + + meeb %f0, 0 + meeb %f0, 4095 + meeb %f0, 0(%r1) + meeb %f0, 0(%r15) + meeb %f0, 4095(%r1,%r15) + meeb %f0, 4095(%r15,%r1) + meeb %f15, 0 diff --git a/test/MC/SystemZ/insn-meeb-02.s b/test/MC/SystemZ/insn-meeb-02.s new file mode 100644 index 000000000000..ba5e3b28e3c8 --- /dev/null +++ b/test/MC/SystemZ/insn-meeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: meeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: meeb %f0, 4096 + + meeb %f0, -1 + meeb %f0, 4096 diff --git a/test/MC/SystemZ/insn-meebr-01.s b/test/MC/SystemZ/insn-meebr-01.s new file mode 100644 index 000000000000..99cd8a38e000 --- /dev/null +++ b/test/MC/SystemZ/insn-meebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: meebr %f0, %f0 # encoding: [0xb3,0x17,0x00,0x00] +#CHECK: meebr %f0, %f15 # encoding: [0xb3,0x17,0x00,0x0f] +#CHECK: meebr %f7, %f8 # encoding: [0xb3,0x17,0x00,0x78] +#CHECK: meebr %f15, %f0 # encoding: [0xb3,0x17,0x00,0xf0] + + meebr %f0, %f0 + meebr %f0, %f15 + meebr %f7, %f8 + meebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-mghi-01.s b/test/MC/SystemZ/insn-mghi-01.s new file mode 100644 index 000000000000..d07278f20a14 --- /dev/null +++ b/test/MC/SystemZ/insn-mghi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mghi %r0, -32768 # encoding: [0xa7,0x0d,0x80,0x00] +#CHECK: mghi %r0, -1 # encoding: [0xa7,0x0d,0xff,0xff] +#CHECK: mghi %r0, 0 # encoding: [0xa7,0x0d,0x00,0x00] +#CHECK: mghi %r0, 1 # encoding: [0xa7,0x0d,0x00,0x01] +#CHECK: mghi %r0, 32767 # encoding: [0xa7,0x0d,0x7f,0xff] +#CHECK: mghi %r15, 0 # encoding: [0xa7,0xfd,0x00,0x00] + + mghi %r0, -32768 + mghi %r0, -1 + mghi %r0, 0 + mghi %r0, 1 + mghi %r0, 32767 + mghi %r15, 0 diff --git a/test/MC/SystemZ/insn-mghi-02.s b/test/MC/SystemZ/insn-mghi-02.s new file mode 100644 index 000000000000..860fa3b78754 --- /dev/null +++ b/test/MC/SystemZ/insn-mghi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mghi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: mghi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: mghi %r0, foo + + mghi %r0, -32769 + mghi %r0, 32768 + mghi %r0, foo diff --git a/test/MC/SystemZ/insn-mh-01.s b/test/MC/SystemZ/insn-mh-01.s new file mode 100644 index 000000000000..59d5515438a0 --- /dev/null +++ b/test/MC/SystemZ/insn-mh-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mh %r0, 0 # encoding: [0x4c,0x00,0x00,0x00] +#CHECK: mh %r0, 4095 # encoding: [0x4c,0x00,0x0f,0xff] +#CHECK: mh %r0, 0(%r1) # encoding: [0x4c,0x00,0x10,0x00] +#CHECK: mh %r0, 0(%r15) # encoding: [0x4c,0x00,0xf0,0x00] +#CHECK: mh %r0, 4095(%r1,%r15) # encoding: [0x4c,0x01,0xff,0xff] +#CHECK: mh %r0, 4095(%r15,%r1) # encoding: [0x4c,0x0f,0x1f,0xff] +#CHECK: mh %r15, 0 # encoding: [0x4c,0xf0,0x00,0x00] + + mh %r0, 0 + mh %r0, 4095 + mh %r0, 0(%r1) + mh %r0, 0(%r15) + mh %r0, 4095(%r1,%r15) + mh %r0, 4095(%r15,%r1) + mh %r15, 0 diff --git a/test/MC/SystemZ/insn-mh-02.s b/test/MC/SystemZ/insn-mh-02.s new file mode 100644 index 000000000000..4ea35fca5916 --- /dev/null +++ b/test/MC/SystemZ/insn-mh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mh %r0, -1 +#CHECK: error: invalid operand +#CHECK: mh %r0, 4096 + + mh %r0, -1 + mh %r0, 4096 diff --git a/test/MC/SystemZ/insn-mhi-01.s b/test/MC/SystemZ/insn-mhi-01.s new file mode 100644 index 000000000000..adf42ae7346c --- /dev/null +++ b/test/MC/SystemZ/insn-mhi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mhi %r0, -32768 # encoding: [0xa7,0x0c,0x80,0x00] +#CHECK: mhi %r0, -1 # encoding: [0xa7,0x0c,0xff,0xff] +#CHECK: mhi %r0, 0 # encoding: [0xa7,0x0c,0x00,0x00] +#CHECK: mhi %r0, 1 # encoding: [0xa7,0x0c,0x00,0x01] +#CHECK: mhi %r0, 32767 # encoding: [0xa7,0x0c,0x7f,0xff] +#CHECK: mhi %r15, 0 # encoding: [0xa7,0xfc,0x00,0x00] + + mhi %r0, -32768 + mhi %r0, -1 + mhi %r0, 0 + mhi %r0, 1 + mhi %r0, 32767 + mhi %r15, 0 diff --git a/test/MC/SystemZ/insn-mhi-02.s b/test/MC/SystemZ/insn-mhi-02.s new file mode 100644 index 000000000000..74e83576e91b --- /dev/null +++ b/test/MC/SystemZ/insn-mhi-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mhi %r0, -32769 +#CHECK: error: invalid operand +#CHECK: mhi %r0, 32768 +#CHECK: error: invalid operand +#CHECK: mhi %r0, foo + + mhi %r0, -32769 + mhi %r0, 32768 + mhi %r0, foo diff --git a/test/MC/SystemZ/insn-mhy-01.s b/test/MC/SystemZ/insn-mhy-01.s new file mode 100644 index 000000000000..89c394bd81ed --- /dev/null +++ b/test/MC/SystemZ/insn-mhy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mhy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x7c] +#CHECK: mhy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x7c] +#CHECK: mhy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x7c] +#CHECK: mhy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x7c] +#CHECK: mhy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x7c] +#CHECK: mhy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x7c] +#CHECK: mhy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x7c] +#CHECK: mhy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x7c] +#CHECK: mhy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x7c] +#CHECK: mhy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x7c] + + mhy %r0, -524288 + mhy %r0, -1 + mhy %r0, 0 + mhy %r0, 1 + mhy %r0, 524287 + mhy %r0, 0(%r1) + mhy %r0, 0(%r15) + mhy %r0, 524287(%r1,%r15) + mhy %r0, 524287(%r15,%r1) + mhy %r15, 0 diff --git a/test/MC/SystemZ/insn-mhy-02.s b/test/MC/SystemZ/insn-mhy-02.s new file mode 100644 index 000000000000..bce62f096c18 --- /dev/null +++ b/test/MC/SystemZ/insn-mhy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mhy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mhy %r0, 524288 + + mhy %r0, -524289 + mhy %r0, 524288 diff --git a/test/MC/SystemZ/insn-mlg-01.s b/test/MC/SystemZ/insn-mlg-01.s new file mode 100644 index 000000000000..e9bd6510fc68 --- /dev/null +++ b/test/MC/SystemZ/insn-mlg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mlg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x86] +#CHECK: mlg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x86] +#CHECK: mlg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x86] +#CHECK: mlg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x86] +#CHECK: mlg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x86] +#CHECK: mlg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x86] +#CHECK: mlg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x86] +#CHECK: mlg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x86] +#CHECK: mlg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x86] +#CHECK: mlg %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x86] + + mlg %r0, -524288 + mlg %r0, -1 + mlg %r0, 0 + mlg %r0, 1 + mlg %r0, 524287 + mlg %r0, 0(%r1) + mlg %r0, 0(%r15) + mlg %r0, 524287(%r1,%r15) + mlg %r0, 524287(%r15,%r1) + mlg %r14, 0 diff --git a/test/MC/SystemZ/insn-mlg-02.s b/test/MC/SystemZ/insn-mlg-02.s new file mode 100644 index 000000000000..7174bc50c2f1 --- /dev/null +++ b/test/MC/SystemZ/insn-mlg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mlg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mlg %r0, 524288 +#CHECK: error: invalid register +#CHECK: mlg %r1, 0 +#CHECK: error: invalid register +#CHECK: mlg %r15, 0 + + mlg %r0, -524289 + mlg %r0, 524288 + mlg %r1, 0 + mlg %r15, 0 diff --git a/test/MC/SystemZ/insn-mlgr-01.s b/test/MC/SystemZ/insn-mlgr-01.s new file mode 100644 index 000000000000..215bde099151 --- /dev/null +++ b/test/MC/SystemZ/insn-mlgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mlgr %r0, %r0 # encoding: [0xb9,0x86,0x00,0x00] +#CHECK: mlgr %r0, %r15 # encoding: [0xb9,0x86,0x00,0x0f] +#CHECK: mlgr %r14, %r0 # encoding: [0xb9,0x86,0x00,0xe0] +#CHECK: mlgr %r6, %r9 # encoding: [0xb9,0x86,0x00,0x69] + + mlgr %r0,%r0 + mlgr %r0,%r15 + mlgr %r14,%r0 + mlgr %r6,%r9 diff --git a/test/MC/SystemZ/insn-mlgr-02.s b/test/MC/SystemZ/insn-mlgr-02.s new file mode 100644 index 000000000000..30f4259031bb --- /dev/null +++ b/test/MC/SystemZ/insn-mlgr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: mlgr %r1, %r0 +#CHECK: error: invalid register +#CHECK: mlgr %r15, %r0 + + mlgr %r1, %r0 + mlgr %r15, %r0 diff --git a/test/MC/SystemZ/insn-ms-01.s b/test/MC/SystemZ/insn-ms-01.s new file mode 100644 index 000000000000..e104e09a1bf4 --- /dev/null +++ b/test/MC/SystemZ/insn-ms-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ms %r0, 0 # encoding: [0x71,0x00,0x00,0x00] +#CHECK: ms %r0, 4095 # encoding: [0x71,0x00,0x0f,0xff] +#CHECK: ms %r0, 0(%r1) # encoding: [0x71,0x00,0x10,0x00] +#CHECK: ms %r0, 0(%r15) # encoding: [0x71,0x00,0xf0,0x00] +#CHECK: ms %r0, 4095(%r1,%r15) # encoding: [0x71,0x01,0xff,0xff] +#CHECK: ms %r0, 4095(%r15,%r1) # encoding: [0x71,0x0f,0x1f,0xff] +#CHECK: ms %r15, 0 # encoding: [0x71,0xf0,0x00,0x00] + + ms %r0, 0 + ms %r0, 4095 + ms %r0, 0(%r1) + ms %r0, 0(%r15) + ms %r0, 4095(%r1,%r15) + ms %r0, 4095(%r15,%r1) + ms %r15, 0 diff --git a/test/MC/SystemZ/insn-ms-02.s b/test/MC/SystemZ/insn-ms-02.s new file mode 100644 index 000000000000..9cc7ecda3402 --- /dev/null +++ b/test/MC/SystemZ/insn-ms-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ms %r0, -1 +#CHECK: error: invalid operand +#CHECK: ms %r0, 4096 + + ms %r0, -1 + ms %r0, 4096 diff --git a/test/MC/SystemZ/insn-msdb-01.s b/test/MC/SystemZ/insn-msdb-01.s new file mode 100644 index 000000000000..50ef45bfc42f --- /dev/null +++ b/test/MC/SystemZ/insn-msdb-01.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msdb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1f] +#CHECK: msdb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1f] +#CHECK: msdb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1f] +#CHECK: msdb %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1f] +#CHECK: msdb %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1f] +#CHECK: msdb %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1f] +#CHECK: msdb %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1f] +#CHECK: msdb %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x1f] +#CHECK: msdb %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x1f] + + msdb %f0, %f0, 0 + msdb %f0, %f0, 4095 + msdb %f0, %f0, 0(%r1) + msdb %f0, %f0, 0(%r15) + msdb %f0, %f0, 4095(%r1,%r15) + msdb %f0, %f0, 4095(%r15,%r1) + msdb %f0, %f15, 0 + msdb %f15, %f0, 0 + msdb %f15, %f15, 0 diff --git a/test/MC/SystemZ/insn-msdb-02.s b/test/MC/SystemZ/insn-msdb-02.s new file mode 100644 index 000000000000..552fc72223dd --- /dev/null +++ b/test/MC/SystemZ/insn-msdb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msdb %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: msdb %f0, %f0, 4096 + + msdb %f0, %f0, -1 + msdb %f0, %f0, 4096 diff --git a/test/MC/SystemZ/insn-msdbr-01.s b/test/MC/SystemZ/insn-msdbr-01.s new file mode 100644 index 000000000000..0c816578a2a9 --- /dev/null +++ b/test/MC/SystemZ/insn-msdbr-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msdbr %f0, %f0, %f0 # encoding: [0xb3,0x1f,0x00,0x00] +#CHECK: msdbr %f0, %f0, %f15 # encoding: [0xb3,0x1f,0x00,0x0f] +#CHECK: msdbr %f0, %f15, %f0 # encoding: [0xb3,0x1f,0x00,0xf0] +#CHECK: msdbr %f15, %f0, %f0 # encoding: [0xb3,0x1f,0xf0,0x00] +#CHECK: msdbr %f7, %f8, %f9 # encoding: [0xb3,0x1f,0x70,0x89] +#CHECK: msdbr %f15, %f15, %f15 # encoding: [0xb3,0x1f,0xf0,0xff] + + msdbr %f0, %f0, %f0 + msdbr %f0, %f0, %f15 + msdbr %f0, %f15, %f0 + msdbr %f15, %f0, %f0 + msdbr %f7, %f8, %f9 + msdbr %f15, %f15, %f15 diff --git a/test/MC/SystemZ/insn-mseb-01.s b/test/MC/SystemZ/insn-mseb-01.s new file mode 100644 index 000000000000..4464cfb803ca --- /dev/null +++ b/test/MC/SystemZ/insn-mseb-01.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mseb %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0f] +#CHECK: mseb %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0f] +#CHECK: mseb %f0, %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0f] +#CHECK: mseb %f0, %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0f] +#CHECK: mseb %f0, %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0f] +#CHECK: mseb %f0, %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0f] +#CHECK: mseb %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0f] +#CHECK: mseb %f15, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xf0,0x0f] +#CHECK: mseb %f15, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xf0,0x0f] + + mseb %f0, %f0, 0 + mseb %f0, %f0, 4095 + mseb %f0, %f0, 0(%r1) + mseb %f0, %f0, 0(%r15) + mseb %f0, %f0, 4095(%r1,%r15) + mseb %f0, %f0, 4095(%r15,%r1) + mseb %f0, %f15, 0 + mseb %f15, %f0, 0 + mseb %f15, %f15, 0 diff --git a/test/MC/SystemZ/insn-mseb-02.s b/test/MC/SystemZ/insn-mseb-02.s new file mode 100644 index 000000000000..03aaa0fb8a6b --- /dev/null +++ b/test/MC/SystemZ/insn-mseb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mseb %f0, %f0, -1 +#CHECK: error: invalid operand +#CHECK: mseb %f0, %f0, 4096 + + mseb %f0, %f0, -1 + mseb %f0, %f0, 4096 diff --git a/test/MC/SystemZ/insn-msebr-01.s b/test/MC/SystemZ/insn-msebr-01.s new file mode 100644 index 000000000000..f936cb632529 --- /dev/null +++ b/test/MC/SystemZ/insn-msebr-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msebr %f0, %f0, %f0 # encoding: [0xb3,0x0f,0x00,0x00] +#CHECK: msebr %f0, %f0, %f15 # encoding: [0xb3,0x0f,0x00,0x0f] +#CHECK: msebr %f0, %f15, %f0 # encoding: [0xb3,0x0f,0x00,0xf0] +#CHECK: msebr %f15, %f0, %f0 # encoding: [0xb3,0x0f,0xf0,0x00] +#CHECK: msebr %f7, %f8, %f9 # encoding: [0xb3,0x0f,0x70,0x89] +#CHECK: msebr %f15, %f15, %f15 # encoding: [0xb3,0x0f,0xf0,0xff] + + msebr %f0, %f0, %f0 + msebr %f0, %f0, %f15 + msebr %f0, %f15, %f0 + msebr %f15, %f0, %f0 + msebr %f7, %f8, %f9 + msebr %f15, %f15, %f15 diff --git a/test/MC/SystemZ/insn-msfi-01.s b/test/MC/SystemZ/insn-msfi-01.s new file mode 100644 index 000000000000..629260e42060 --- /dev/null +++ b/test/MC/SystemZ/insn-msfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msfi %r0, -2147483648 # encoding: [0xc2,0x01,0x80,0x00,0x00,0x00] +#CHECK: msfi %r0, -1 # encoding: [0xc2,0x01,0xff,0xff,0xff,0xff] +#CHECK: msfi %r0, 0 # encoding: [0xc2,0x01,0x00,0x00,0x00,0x00] +#CHECK: msfi %r0, 1 # encoding: [0xc2,0x01,0x00,0x00,0x00,0x01] +#CHECK: msfi %r0, 2147483647 # encoding: [0xc2,0x01,0x7f,0xff,0xff,0xff] +#CHECK: msfi %r15, 0 # encoding: [0xc2,0xf1,0x00,0x00,0x00,0x00] + + msfi %r0, -1 << 31 + msfi %r0, -1 + msfi %r0, 0 + msfi %r0, 1 + msfi %r0, (1 << 31) - 1 + msfi %r15, 0 diff --git a/test/MC/SystemZ/insn-msfi-02.s b/test/MC/SystemZ/insn-msfi-02.s new file mode 100644 index 000000000000..2700ce78b8e3 --- /dev/null +++ b/test/MC/SystemZ/insn-msfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: msfi %r0, (1 << 31) + + msfi %r0, (-1 << 31) - 1 + msfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-msg-01.s b/test/MC/SystemZ/insn-msg-01.s new file mode 100644 index 000000000000..298811c1e965 --- /dev/null +++ b/test/MC/SystemZ/insn-msg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0c] +#CHECK: msg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0c] +#CHECK: msg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0c] +#CHECK: msg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0c] +#CHECK: msg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0c] +#CHECK: msg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0c] +#CHECK: msg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0c] +#CHECK: msg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0c] +#CHECK: msg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0c] +#CHECK: msg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0c] + + msg %r0, -524288 + msg %r0, -1 + msg %r0, 0 + msg %r0, 1 + msg %r0, 524287 + msg %r0, 0(%r1) + msg %r0, 0(%r15) + msg %r0, 524287(%r1,%r15) + msg %r0, 524287(%r15,%r1) + msg %r15, 0 diff --git a/test/MC/SystemZ/insn-msg-02.s b/test/MC/SystemZ/insn-msg-02.s new file mode 100644 index 000000000000..3326f40e56aa --- /dev/null +++ b/test/MC/SystemZ/insn-msg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msg %r0, 524288 + + msg %r0, -524289 + msg %r0, 524288 diff --git a/test/MC/SystemZ/insn-msgf-01.s b/test/MC/SystemZ/insn-msgf-01.s new file mode 100644 index 000000000000..9812bcc9cb47 --- /dev/null +++ b/test/MC/SystemZ/insn-msgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1c] +#CHECK: msgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1c] +#CHECK: msgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1c] +#CHECK: msgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1c] +#CHECK: msgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1c] +#CHECK: msgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1c] +#CHECK: msgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1c] +#CHECK: msgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x1c] +#CHECK: msgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x1c] +#CHECK: msgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x1c] + + msgf %r0, -524288 + msgf %r0, -1 + msgf %r0, 0 + msgf %r0, 1 + msgf %r0, 524287 + msgf %r0, 0(%r1) + msgf %r0, 0(%r15) + msgf %r0, 524287(%r1,%r15) + msgf %r0, 524287(%r15,%r1) + msgf %r15, 0 diff --git a/test/MC/SystemZ/insn-msgf-02.s b/test/MC/SystemZ/insn-msgf-02.s new file mode 100644 index 000000000000..03983b305f07 --- /dev/null +++ b/test/MC/SystemZ/insn-msgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msgf %r0, 524288 + + msgf %r0, -524289 + msgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-msgfi-01.s b/test/MC/SystemZ/insn-msgfi-01.s new file mode 100644 index 000000000000..802ad143a503 --- /dev/null +++ b/test/MC/SystemZ/insn-msgfi-01.s @@ -0,0 +1,15 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msgfi %r0, -2147483648 # encoding: [0xc2,0x00,0x80,0x00,0x00,0x00] +#CHECK: msgfi %r0, -1 # encoding: [0xc2,0x00,0xff,0xff,0xff,0xff] +#CHECK: msgfi %r0, 0 # encoding: [0xc2,0x00,0x00,0x00,0x00,0x00] +#CHECK: msgfi %r0, 1 # encoding: [0xc2,0x00,0x00,0x00,0x00,0x01] +#CHECK: msgfi %r0, 2147483647 # encoding: [0xc2,0x00,0x7f,0xff,0xff,0xff] +#CHECK: msgfi %r15, 0 # encoding: [0xc2,0xf0,0x00,0x00,0x00,0x00] + + msgfi %r0, -1 << 31 + msgfi %r0, -1 + msgfi %r0, 0 + msgfi %r0, 1 + msgfi %r0, (1 << 31) - 1 + msgfi %r15, 0 diff --git a/test/MC/SystemZ/insn-msgfi-02.s b/test/MC/SystemZ/insn-msgfi-02.s new file mode 100644 index 000000000000..82e1f8f9b44c --- /dev/null +++ b/test/MC/SystemZ/insn-msgfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msgfi %r0, (-1 << 31) - 1 +#CHECK: error: invalid operand +#CHECK: msgfi %r0, (1 << 31) + + msgfi %r0, (-1 << 31) - 1 + msgfi %r0, (1 << 31) diff --git a/test/MC/SystemZ/insn-msgfr-01.s b/test/MC/SystemZ/insn-msgfr-01.s new file mode 100644 index 000000000000..e25f6302ac62 --- /dev/null +++ b/test/MC/SystemZ/insn-msgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msgfr %r0, %r0 # encoding: [0xb9,0x1c,0x00,0x00] +#CHECK: msgfr %r0, %r15 # encoding: [0xb9,0x1c,0x00,0x0f] +#CHECK: msgfr %r15, %r0 # encoding: [0xb9,0x1c,0x00,0xf0] +#CHECK: msgfr %r7, %r8 # encoding: [0xb9,0x1c,0x00,0x78] + + msgfr %r0,%r0 + msgfr %r0,%r15 + msgfr %r15,%r0 + msgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-msgr-01.s b/test/MC/SystemZ/insn-msgr-01.s new file mode 100644 index 000000000000..0b9cd360c8fe --- /dev/null +++ b/test/MC/SystemZ/insn-msgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msgr %r0, %r0 # encoding: [0xb9,0x0c,0x00,0x00] +#CHECK: msgr %r0, %r15 # encoding: [0xb9,0x0c,0x00,0x0f] +#CHECK: msgr %r15, %r0 # encoding: [0xb9,0x0c,0x00,0xf0] +#CHECK: msgr %r7, %r8 # encoding: [0xb9,0x0c,0x00,0x78] + + msgr %r0,%r0 + msgr %r0,%r15 + msgr %r15,%r0 + msgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-msr-01.s b/test/MC/SystemZ/insn-msr-01.s new file mode 100644 index 000000000000..6f7d917a16ce --- /dev/null +++ b/test/MC/SystemZ/insn-msr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msr %r0, %r0 # encoding: [0xb2,0x52,0x00,0x00] +#CHECK: msr %r0, %r15 # encoding: [0xb2,0x52,0x00,0x0f] +#CHECK: msr %r15, %r0 # encoding: [0xb2,0x52,0x00,0xf0] +#CHECK: msr %r7, %r8 # encoding: [0xb2,0x52,0x00,0x78] + + msr %r0,%r0 + msr %r0,%r15 + msr %r15,%r0 + msr %r7,%r8 diff --git a/test/MC/SystemZ/insn-msy-01.s b/test/MC/SystemZ/insn-msy-01.s new file mode 100644 index 000000000000..aed9318a8a56 --- /dev/null +++ b/test/MC/SystemZ/insn-msy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: msy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x51] +#CHECK: msy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x51] +#CHECK: msy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x51] +#CHECK: msy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x51] +#CHECK: msy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x51] +#CHECK: msy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x51] +#CHECK: msy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x51] +#CHECK: msy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x51] +#CHECK: msy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x51] +#CHECK: msy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x51] + + msy %r0, -524288 + msy %r0, -1 + msy %r0, 0 + msy %r0, 1 + msy %r0, 524287 + msy %r0, 0(%r1) + msy %r0, 0(%r15) + msy %r0, 524287(%r1,%r15) + msy %r0, 524287(%r15,%r1) + msy %r15, 0 diff --git a/test/MC/SystemZ/insn-msy-02.s b/test/MC/SystemZ/insn-msy-02.s new file mode 100644 index 000000000000..6f10069ae704 --- /dev/null +++ b/test/MC/SystemZ/insn-msy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: msy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msy %r0, 524288 + + msy %r0, -524289 + msy %r0, 524288 diff --git a/test/MC/SystemZ/insn-mvghi-01.s b/test/MC/SystemZ/insn-mvghi-01.s new file mode 100644 index 000000000000..191aa49cd854 --- /dev/null +++ b/test/MC/SystemZ/insn-mvghi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00] +#CHECK: mvghi 4095, 0 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00] +#CHECK: mvghi 0, -32768 # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00] +#CHECK: mvghi 0, -1 # encoding: [0xe5,0x48,0x00,0x00,0xff,0xff] +#CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00] +#CHECK: mvghi 0, 1 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x01] +#CHECK: mvghi 0, 32767 # encoding: [0xe5,0x48,0x00,0x00,0x7f,0xff] +#CHECK: mvghi 0(%r1), 42 # encoding: [0xe5,0x48,0x10,0x00,0x00,0x2a] +#CHECK: mvghi 0(%r15), 42 # encoding: [0xe5,0x48,0xf0,0x00,0x00,0x2a] +#CHECK: mvghi 4095(%r1), 42 # encoding: [0xe5,0x48,0x1f,0xff,0x00,0x2a] +#CHECK: mvghi 4095(%r15), 42 # encoding: [0xe5,0x48,0xff,0xff,0x00,0x2a] + + mvghi 0, 0 + mvghi 4095, 0 + mvghi 0, -32768 + mvghi 0, -1 + mvghi 0, 0 + mvghi 0, 1 + mvghi 0, 32767 + mvghi 0(%r1), 42 + mvghi 0(%r15), 42 + mvghi 4095(%r1), 42 + mvghi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-mvghi-02.s b/test/MC/SystemZ/insn-mvghi-02.s new file mode 100644 index 000000000000..38b38a517a0b --- /dev/null +++ b/test/MC/SystemZ/insn-mvghi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mvghi -1, 0 +#CHECK: error: invalid operand +#CHECK: mvghi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvghi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: mvghi 0, -32769 +#CHECK: error: invalid operand +#CHECK: mvghi 0, 32768 + + mvghi -1, 0 + mvghi 4096, 0 + mvghi 0(%r1,%r2), 0 + mvghi 0, -32769 + mvghi 0, 32768 diff --git a/test/MC/SystemZ/insn-mvhhi-01.s b/test/MC/SystemZ/insn-mvhhi-01.s new file mode 100644 index 000000000000..63574a487f93 --- /dev/null +++ b/test/MC/SystemZ/insn-mvhhi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mvhhi 0, 0 # encoding: [0xe5,0x44,0x00,0x00,0x00,0x00] +#CHECK: mvhhi 4095, 0 # encoding: [0xe5,0x44,0x0f,0xff,0x00,0x00] +#CHECK: mvhhi 0, -32768 # encoding: [0xe5,0x44,0x00,0x00,0x80,0x00] +#CHECK: mvhhi 0, -1 # encoding: [0xe5,0x44,0x00,0x00,0xff,0xff] +#CHECK: mvhhi 0, 0 # encoding: [0xe5,0x44,0x00,0x00,0x00,0x00] +#CHECK: mvhhi 0, 1 # encoding: [0xe5,0x44,0x00,0x00,0x00,0x01] +#CHECK: mvhhi 0, 32767 # encoding: [0xe5,0x44,0x00,0x00,0x7f,0xff] +#CHECK: mvhhi 0(%r1), 42 # encoding: [0xe5,0x44,0x10,0x00,0x00,0x2a] +#CHECK: mvhhi 0(%r15), 42 # encoding: [0xe5,0x44,0xf0,0x00,0x00,0x2a] +#CHECK: mvhhi 4095(%r1), 42 # encoding: [0xe5,0x44,0x1f,0xff,0x00,0x2a] +#CHECK: mvhhi 4095(%r15), 42 # encoding: [0xe5,0x44,0xff,0xff,0x00,0x2a] + + mvhhi 0, 0 + mvhhi 4095, 0 + mvhhi 0, -32768 + mvhhi 0, -1 + mvhhi 0, 0 + mvhhi 0, 1 + mvhhi 0, 32767 + mvhhi 0(%r1), 42 + mvhhi 0(%r15), 42 + mvhhi 4095(%r1), 42 + mvhhi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-mvhhi-02.s b/test/MC/SystemZ/insn-mvhhi-02.s new file mode 100644 index 000000000000..58abb025ebd6 --- /dev/null +++ b/test/MC/SystemZ/insn-mvhhi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mvhhi -1, 0 +#CHECK: error: invalid operand +#CHECK: mvhhi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvhhi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: mvhhi 0, -32769 +#CHECK: error: invalid operand +#CHECK: mvhhi 0, 32768 + + mvhhi -1, 0 + mvhhi 4096, 0 + mvhhi 0(%r1,%r2), 0 + mvhhi 0, -32769 + mvhhi 0, 32768 diff --git a/test/MC/SystemZ/insn-mvhi-01.s b/test/MC/SystemZ/insn-mvhi-01.s new file mode 100644 index 000000000000..5bf9fd312167 --- /dev/null +++ b/test/MC/SystemZ/insn-mvhi-01.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mvhi 0, 0 # encoding: [0xe5,0x4c,0x00,0x00,0x00,0x00] +#CHECK: mvhi 4095, 0 # encoding: [0xe5,0x4c,0x0f,0xff,0x00,0x00] +#CHECK: mvhi 0, -32768 # encoding: [0xe5,0x4c,0x00,0x00,0x80,0x00] +#CHECK: mvhi 0, -1 # encoding: [0xe5,0x4c,0x00,0x00,0xff,0xff] +#CHECK: mvhi 0, 0 # encoding: [0xe5,0x4c,0x00,0x00,0x00,0x00] +#CHECK: mvhi 0, 1 # encoding: [0xe5,0x4c,0x00,0x00,0x00,0x01] +#CHECK: mvhi 0, 32767 # encoding: [0xe5,0x4c,0x00,0x00,0x7f,0xff] +#CHECK: mvhi 0(%r1), 42 # encoding: [0xe5,0x4c,0x10,0x00,0x00,0x2a] +#CHECK: mvhi 0(%r15), 42 # encoding: [0xe5,0x4c,0xf0,0x00,0x00,0x2a] +#CHECK: mvhi 4095(%r1), 42 # encoding: [0xe5,0x4c,0x1f,0xff,0x00,0x2a] +#CHECK: mvhi 4095(%r15), 42 # encoding: [0xe5,0x4c,0xff,0xff,0x00,0x2a] + + mvhi 0, 0 + mvhi 4095, 0 + mvhi 0, -32768 + mvhi 0, -1 + mvhi 0, 0 + mvhi 0, 1 + mvhi 0, 32767 + mvhi 0(%r1), 42 + mvhi 0(%r15), 42 + mvhi 4095(%r1), 42 + mvhi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-mvhi-02.s b/test/MC/SystemZ/insn-mvhi-02.s new file mode 100644 index 000000000000..517301c51356 --- /dev/null +++ b/test/MC/SystemZ/insn-mvhi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mvhi -1, 0 +#CHECK: error: invalid operand +#CHECK: mvhi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvhi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: mvhi 0, -32769 +#CHECK: error: invalid operand +#CHECK: mvhi 0, 32768 + + mvhi -1, 0 + mvhi 4096, 0 + mvhi 0(%r1,%r2), 0 + mvhi 0, -32769 + mvhi 0, 32768 diff --git a/test/MC/SystemZ/insn-mvi-01.s b/test/MC/SystemZ/insn-mvi-01.s new file mode 100644 index 000000000000..83e30900ac3a --- /dev/null +++ b/test/MC/SystemZ/insn-mvi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mvi 0, 0 # encoding: [0x92,0x00,0x00,0x00] +#CHECK: mvi 4095, 0 # encoding: [0x92,0x00,0x0f,0xff] +#CHECK: mvi 0, 255 # encoding: [0x92,0xff,0x00,0x00] +#CHECK: mvi 0(%r1), 42 # encoding: [0x92,0x2a,0x10,0x00] +#CHECK: mvi 0(%r15), 42 # encoding: [0x92,0x2a,0xf0,0x00] +#CHECK: mvi 4095(%r1), 42 # encoding: [0x92,0x2a,0x1f,0xff] +#CHECK: mvi 4095(%r15), 42 # encoding: [0x92,0x2a,0xff,0xff] + + mvi 0, 0 + mvi 4095, 0 + mvi 0, 255 + mvi 0(%r1), 42 + mvi 0(%r15), 42 + mvi 4095(%r1), 42 + mvi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-mvi-02.s b/test/MC/SystemZ/insn-mvi-02.s new file mode 100644 index 000000000000..ddd5909d459c --- /dev/null +++ b/test/MC/SystemZ/insn-mvi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mvi -1, 0 +#CHECK: error: invalid operand +#CHECK: mvi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: mvi 0, -1 +#CHECK: error: invalid operand +#CHECK: mvi 0, 256 + + mvi -1, 0 + mvi 4096, 0 + mvi 0(%r1,%r2), 0 + mvi 0, -1 + mvi 0, 256 diff --git a/test/MC/SystemZ/insn-mviy-01.s b/test/MC/SystemZ/insn-mviy-01.s new file mode 100644 index 000000000000..8bd6979b81ee --- /dev/null +++ b/test/MC/SystemZ/insn-mviy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mviy -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x52] +#CHECK: mviy -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x52] +#CHECK: mviy 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x52] +#CHECK: mviy 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x52] +#CHECK: mviy 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x52] +#CHECK: mviy 0, 255 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x52] +#CHECK: mviy 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x52] +#CHECK: mviy 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x52] +#CHECK: mviy 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x52] +#CHECK: mviy 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x52] + + mviy -524288, 0 + mviy -1, 0 + mviy 0, 0 + mviy 1, 0 + mviy 524287, 0 + mviy 0, 255 + mviy 0(%r1), 42 + mviy 0(%r15), 42 + mviy 524287(%r1), 42 + mviy 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-mviy-02.s b/test/MC/SystemZ/insn-mviy-02.s new file mode 100644 index 000000000000..ab78dab5c971 --- /dev/null +++ b/test/MC/SystemZ/insn-mviy-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: mviy -524289, 0 +#CHECK: error: invalid operand +#CHECK: mviy 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: mviy 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: mviy 0, -1 +#CHECK: error: invalid operand +#CHECK: mviy 0, 256 + + mviy -524289, 0 + mviy 524288, 0 + mviy 0(%r1,%r2), 0 + mviy 0, -1 + mviy 0, 256 diff --git a/test/MC/SystemZ/insn-mxbr-01.s b/test/MC/SystemZ/insn-mxbr-01.s new file mode 100644 index 000000000000..60c8ebadfba3 --- /dev/null +++ b/test/MC/SystemZ/insn-mxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mxbr %f0, %f0 # encoding: [0xb3,0x4c,0x00,0x00] +#CHECK: mxbr %f0, %f13 # encoding: [0xb3,0x4c,0x00,0x0d] +#CHECK: mxbr %f8, %f5 # encoding: [0xb3,0x4c,0x00,0x85] +#CHECK: mxbr %f13, %f13 # encoding: [0xb3,0x4c,0x00,0xdd] + + mxbr %f0, %f0 + mxbr %f0, %f13 + mxbr %f8, %f5 + mxbr %f13, %f13 diff --git a/test/MC/SystemZ/insn-mxbr-02.s b/test/MC/SystemZ/insn-mxbr-02.s new file mode 100644 index 000000000000..92820234139a --- /dev/null +++ b/test/MC/SystemZ/insn-mxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: mxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: mxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: mxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: mxbr %f14, %f0 + + mxbr %f0, %f2 + mxbr %f0, %f14 + mxbr %f2, %f0 + mxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-mxdb-01.s b/test/MC/SystemZ/insn-mxdb-01.s new file mode 100644 index 000000000000..46a723e8426f --- /dev/null +++ b/test/MC/SystemZ/insn-mxdb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mxdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x07] +#CHECK: mxdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x07] +#CHECK: mxdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x07] +#CHECK: mxdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x07] +#CHECK: mxdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x07] +#CHECK: mxdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x07] +#CHECK: mxdb %f13, 0 # encoding: [0xed,0xd0,0x00,0x00,0x00,0x07] + + mxdb %f0, 0 + mxdb %f0, 4095 + mxdb %f0, 0(%r1) + mxdb %f0, 0(%r15) + mxdb %f0, 4095(%r1,%r15) + mxdb %f0, 4095(%r15,%r1) + mxdb %f13, 0 diff --git a/test/MC/SystemZ/insn-mxdb-02.s b/test/MC/SystemZ/insn-mxdb-02.s new file mode 100644 index 000000000000..44c821cad039 --- /dev/null +++ b/test/MC/SystemZ/insn-mxdb-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: mxdb %f2, 0 +#CHECK: error: invalid register +#CHECK: mxdb %f15, 0 +#CHECK: error: invalid operand +#CHECK: mxdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: mxdb %f0, 4096 + + mxdb %f2, 0 + mxdb %f15, 0 + mxdb %f0, -1 + mxdb %f0, 4096 diff --git a/test/MC/SystemZ/insn-mxdbr-01.s b/test/MC/SystemZ/insn-mxdbr-01.s new file mode 100644 index 000000000000..dfb898fbdaf6 --- /dev/null +++ b/test/MC/SystemZ/insn-mxdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: mxdbr %f0, %f0 # encoding: [0xb3,0x07,0x00,0x00] +#CHECK: mxdbr %f0, %f15 # encoding: [0xb3,0x07,0x00,0x0f] +#CHECK: mxdbr %f8, %f8 # encoding: [0xb3,0x07,0x00,0x88] +#CHECK: mxdbr %f13, %f0 # encoding: [0xb3,0x07,0x00,0xd0] + + mxdbr %f0, %f0 + mxdbr %f0, %f15 + mxdbr %f8, %f8 + mxdbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-mxdbr-02.s b/test/MC/SystemZ/insn-mxdbr-02.s new file mode 100644 index 000000000000..90260481f2a7 --- /dev/null +++ b/test/MC/SystemZ/insn-mxdbr-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: mxdbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: mxdbr %f15, %f0 + + mxdbr %f2, %f0 + mxdbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-n-01.s b/test/MC/SystemZ/insn-n-01.s new file mode 100644 index 000000000000..75fa141e2c86 --- /dev/null +++ b/test/MC/SystemZ/insn-n-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: n %r0, 0 # encoding: [0x54,0x00,0x00,0x00] +#CHECK: n %r0, 4095 # encoding: [0x54,0x00,0x0f,0xff] +#CHECK: n %r0, 0(%r1) # encoding: [0x54,0x00,0x10,0x00] +#CHECK: n %r0, 0(%r15) # encoding: [0x54,0x00,0xf0,0x00] +#CHECK: n %r0, 4095(%r1,%r15) # encoding: [0x54,0x01,0xff,0xff] +#CHECK: n %r0, 4095(%r15,%r1) # encoding: [0x54,0x0f,0x1f,0xff] +#CHECK: n %r15, 0 # encoding: [0x54,0xf0,0x00,0x00] + + n %r0, 0 + n %r0, 4095 + n %r0, 0(%r1) + n %r0, 0(%r15) + n %r0, 4095(%r1,%r15) + n %r0, 4095(%r15,%r1) + n %r15, 0 diff --git a/test/MC/SystemZ/insn-n-02.s b/test/MC/SystemZ/insn-n-02.s new file mode 100644 index 000000000000..7c14b1fe1c0e --- /dev/null +++ b/test/MC/SystemZ/insn-n-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: n %r0, -1 +#CHECK: error: invalid operand +#CHECK: n %r0, 4096 + + n %r0, -1 + n %r0, 4096 diff --git a/test/MC/SystemZ/insn-ng-01.s b/test/MC/SystemZ/insn-ng-01.s new file mode 100644 index 000000000000..bf71a2183f45 --- /dev/null +++ b/test/MC/SystemZ/insn-ng-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ng %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x80] +#CHECK: ng %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x80] +#CHECK: ng %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x80] +#CHECK: ng %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x80] +#CHECK: ng %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x80] +#CHECK: ng %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x80] +#CHECK: ng %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x80] +#CHECK: ng %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x80] +#CHECK: ng %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x80] +#CHECK: ng %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x80] + + ng %r0, -524288 + ng %r0, -1 + ng %r0, 0 + ng %r0, 1 + ng %r0, 524287 + ng %r0, 0(%r1) + ng %r0, 0(%r15) + ng %r0, 524287(%r1,%r15) + ng %r0, 524287(%r15,%r1) + ng %r15, 0 diff --git a/test/MC/SystemZ/insn-ng-02.s b/test/MC/SystemZ/insn-ng-02.s new file mode 100644 index 000000000000..a6f326052683 --- /dev/null +++ b/test/MC/SystemZ/insn-ng-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ng %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ng %r0, 524288 + + ng %r0, -524289 + ng %r0, 524288 diff --git a/test/MC/SystemZ/insn-ngr-01.s b/test/MC/SystemZ/insn-ngr-01.s new file mode 100644 index 000000000000..714b9fa71292 --- /dev/null +++ b/test/MC/SystemZ/insn-ngr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ngr %r0, %r0 # encoding: [0xb9,0x80,0x00,0x00] +#CHECK: ngr %r0, %r15 # encoding: [0xb9,0x80,0x00,0x0f] +#CHECK: ngr %r15, %r0 # encoding: [0xb9,0x80,0x00,0xf0] +#CHECK: ngr %r7, %r8 # encoding: [0xb9,0x80,0x00,0x78] + + ngr %r0,%r0 + ngr %r0,%r15 + ngr %r15,%r0 + ngr %r7,%r8 diff --git a/test/MC/SystemZ/insn-ni-01.s b/test/MC/SystemZ/insn-ni-01.s new file mode 100644 index 000000000000..d075674feaa3 --- /dev/null +++ b/test/MC/SystemZ/insn-ni-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ni 0, 0 # encoding: [0x94,0x00,0x00,0x00] +#CHECK: ni 4095, 0 # encoding: [0x94,0x00,0x0f,0xff] +#CHECK: ni 0, 255 # encoding: [0x94,0xff,0x00,0x00] +#CHECK: ni 0(%r1), 42 # encoding: [0x94,0x2a,0x10,0x00] +#CHECK: ni 0(%r15), 42 # encoding: [0x94,0x2a,0xf0,0x00] +#CHECK: ni 4095(%r1), 42 # encoding: [0x94,0x2a,0x1f,0xff] +#CHECK: ni 4095(%r15), 42 # encoding: [0x94,0x2a,0xff,0xff] + + ni 0, 0 + ni 4095, 0 + ni 0, 255 + ni 0(%r1), 42 + ni 0(%r15), 42 + ni 4095(%r1), 42 + ni 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-ni-02.s b/test/MC/SystemZ/insn-ni-02.s new file mode 100644 index 000000000000..1b9a6a748de2 --- /dev/null +++ b/test/MC/SystemZ/insn-ni-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ni -1, 0 +#CHECK: error: invalid operand +#CHECK: ni 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: ni 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: ni 0, -1 +#CHECK: error: invalid operand +#CHECK: ni 0, 256 + + ni -1, 0 + ni 4096, 0 + ni 0(%r1,%r2), 0 + ni 0, -1 + ni 0, 256 diff --git a/test/MC/SystemZ/insn-nihf-01.s b/test/MC/SystemZ/insn-nihf-01.s new file mode 100644 index 000000000000..dceb8d1297c2 --- /dev/null +++ b/test/MC/SystemZ/insn-nihf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nihf %r0, 0 # encoding: [0xc0,0x0a,0x00,0x00,0x00,0x00] +#CHECK: nihf %r0, 4294967295 # encoding: [0xc0,0x0a,0xff,0xff,0xff,0xff] +#CHECK: nihf %r15, 0 # encoding: [0xc0,0xfa,0x00,0x00,0x00,0x00] + + nihf %r0, 0 + nihf %r0, 0xffffffff + nihf %r15, 0 diff --git a/test/MC/SystemZ/insn-nihf-02.s b/test/MC/SystemZ/insn-nihf-02.s new file mode 100644 index 000000000000..5f7f10a6b3f0 --- /dev/null +++ b/test/MC/SystemZ/insn-nihf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nihf %r0, -1 +#CHECK: error: invalid operand +#CHECK: nihf %r0, 1 << 32 + + nihf %r0, -1 + nihf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-nihh-01.s b/test/MC/SystemZ/insn-nihh-01.s new file mode 100644 index 000000000000..a87540d04c08 --- /dev/null +++ b/test/MC/SystemZ/insn-nihh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nihh %r0, 0 # encoding: [0xa5,0x04,0x00,0x00] +#CHECK: nihh %r0, 32768 # encoding: [0xa5,0x04,0x80,0x00] +#CHECK: nihh %r0, 65535 # encoding: [0xa5,0x04,0xff,0xff] +#CHECK: nihh %r15, 0 # encoding: [0xa5,0xf4,0x00,0x00] + + nihh %r0, 0 + nihh %r0, 0x8000 + nihh %r0, 0xffff + nihh %r15, 0 diff --git a/test/MC/SystemZ/insn-nihh-02.s b/test/MC/SystemZ/insn-nihh-02.s new file mode 100644 index 000000000000..3df88e40a281 --- /dev/null +++ b/test/MC/SystemZ/insn-nihh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nihh %r0, -1 +#CHECK: error: invalid operand +#CHECK: nihh %r0, 0x10000 + + nihh %r0, -1 + nihh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-nihl-01.s b/test/MC/SystemZ/insn-nihl-01.s new file mode 100644 index 000000000000..6eab58c7e7bf --- /dev/null +++ b/test/MC/SystemZ/insn-nihl-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nihl %r0, 0 # encoding: [0xa5,0x05,0x00,0x00] +#CHECK: nihl %r0, 32768 # encoding: [0xa5,0x05,0x80,0x00] +#CHECK: nihl %r0, 65535 # encoding: [0xa5,0x05,0xff,0xff] +#CHECK: nihl %r15, 0 # encoding: [0xa5,0xf5,0x00,0x00] + + nihl %r0, 0 + nihl %r0, 0x8000 + nihl %r0, 0xffff + nihl %r15, 0 diff --git a/test/MC/SystemZ/insn-nihl-02.s b/test/MC/SystemZ/insn-nihl-02.s new file mode 100644 index 000000000000..6e2d52f5a91a --- /dev/null +++ b/test/MC/SystemZ/insn-nihl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nihl %r0, -1 +#CHECK: error: invalid operand +#CHECK: nihl %r0, 0x10000 + + nihl %r0, -1 + nihl %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-nilf-01.s b/test/MC/SystemZ/insn-nilf-01.s new file mode 100644 index 000000000000..0b3a13e752cf --- /dev/null +++ b/test/MC/SystemZ/insn-nilf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nilf %r0, 0 # encoding: [0xc0,0x0b,0x00,0x00,0x00,0x00] +#CHECK: nilf %r0, 4294967295 # encoding: [0xc0,0x0b,0xff,0xff,0xff,0xff] +#CHECK: nilf %r15, 0 # encoding: [0xc0,0xfb,0x00,0x00,0x00,0x00] + + nilf %r0, 0 + nilf %r0, 0xffffffff + nilf %r15, 0 diff --git a/test/MC/SystemZ/insn-nilf-02.s b/test/MC/SystemZ/insn-nilf-02.s new file mode 100644 index 000000000000..87b65e46fe96 --- /dev/null +++ b/test/MC/SystemZ/insn-nilf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nilf %r0, -1 +#CHECK: error: invalid operand +#CHECK: nilf %r0, 1 << 32 + + nilf %r0, -1 + nilf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-nilh-01.s b/test/MC/SystemZ/insn-nilh-01.s new file mode 100644 index 000000000000..4bc9353dd284 --- /dev/null +++ b/test/MC/SystemZ/insn-nilh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nilh %r0, 0 # encoding: [0xa5,0x06,0x00,0x00] +#CHECK: nilh %r0, 32768 # encoding: [0xa5,0x06,0x80,0x00] +#CHECK: nilh %r0, 65535 # encoding: [0xa5,0x06,0xff,0xff] +#CHECK: nilh %r15, 0 # encoding: [0xa5,0xf6,0x00,0x00] + + nilh %r0, 0 + nilh %r0, 0x8000 + nilh %r0, 0xffff + nilh %r15, 0 diff --git a/test/MC/SystemZ/insn-nilh-02.s b/test/MC/SystemZ/insn-nilh-02.s new file mode 100644 index 000000000000..ae5a852a6c69 --- /dev/null +++ b/test/MC/SystemZ/insn-nilh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nilh %r0, -1 +#CHECK: error: invalid operand +#CHECK: nilh %r0, 0x10000 + + nilh %r0, -1 + nilh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-nill-01.s b/test/MC/SystemZ/insn-nill-01.s new file mode 100644 index 000000000000..5f4f87785bf3 --- /dev/null +++ b/test/MC/SystemZ/insn-nill-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nill %r0, 0 # encoding: [0xa5,0x07,0x00,0x00] +#CHECK: nill %r0, 32768 # encoding: [0xa5,0x07,0x80,0x00] +#CHECK: nill %r0, 65535 # encoding: [0xa5,0x07,0xff,0xff] +#CHECK: nill %r15, 0 # encoding: [0xa5,0xf7,0x00,0x00] + + nill %r0, 0 + nill %r0, 0x8000 + nill %r0, 0xffff + nill %r15, 0 diff --git a/test/MC/SystemZ/insn-nill-02.s b/test/MC/SystemZ/insn-nill-02.s new file mode 100644 index 000000000000..27fbc4a50658 --- /dev/null +++ b/test/MC/SystemZ/insn-nill-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: nill %r0, -1 +#CHECK: error: invalid operand +#CHECK: nill %r0, 0x10000 + + nill %r0, -1 + nill %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-niy-01.s b/test/MC/SystemZ/insn-niy-01.s new file mode 100644 index 000000000000..4c007e917295 --- /dev/null +++ b/test/MC/SystemZ/insn-niy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: niy -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x54] +#CHECK: niy -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x54] +#CHECK: niy 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x54] +#CHECK: niy 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x54] +#CHECK: niy 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x54] +#CHECK: niy 0, 255 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x54] +#CHECK: niy 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x54] +#CHECK: niy 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x54] +#CHECK: niy 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x54] +#CHECK: niy 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x54] + + niy -524288, 0 + niy -1, 0 + niy 0, 0 + niy 1, 0 + niy 524287, 0 + niy 0, 255 + niy 0(%r1), 42 + niy 0(%r15), 42 + niy 524287(%r1), 42 + niy 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-niy-02.s b/test/MC/SystemZ/insn-niy-02.s new file mode 100644 index 000000000000..ca398e6fca86 --- /dev/null +++ b/test/MC/SystemZ/insn-niy-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: niy -524289, 0 +#CHECK: error: invalid operand +#CHECK: niy 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: niy 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: niy 0, -1 +#CHECK: error: invalid operand +#CHECK: niy 0, 256 + + niy -524289, 0 + niy 524288, 0 + niy 0(%r1,%r2), 0 + niy 0, -1 + niy 0, 256 diff --git a/test/MC/SystemZ/insn-nr-01.s b/test/MC/SystemZ/insn-nr-01.s new file mode 100644 index 000000000000..c10216d68f41 --- /dev/null +++ b/test/MC/SystemZ/insn-nr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: nr %r0, %r0 # encoding: [0x14,0x00] +#CHECK: nr %r0, %r15 # encoding: [0x14,0x0f] +#CHECK: nr %r15, %r0 # encoding: [0x14,0xf0] +#CHECK: nr %r7, %r8 # encoding: [0x14,0x78] + + nr %r0,%r0 + nr %r0,%r15 + nr %r15,%r0 + nr %r7,%r8 diff --git a/test/MC/SystemZ/insn-ny-01.s b/test/MC/SystemZ/insn-ny-01.s new file mode 100644 index 000000000000..a12bb67e2b03 --- /dev/null +++ b/test/MC/SystemZ/insn-ny-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ny %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x54] +#CHECK: ny %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x54] +#CHECK: ny %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x54] +#CHECK: ny %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x54] +#CHECK: ny %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x54] +#CHECK: ny %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x54] +#CHECK: ny %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x54] +#CHECK: ny %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x54] +#CHECK: ny %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x54] +#CHECK: ny %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x54] + + ny %r0, -524288 + ny %r0, -1 + ny %r0, 0 + ny %r0, 1 + ny %r0, 524287 + ny %r0, 0(%r1) + ny %r0, 0(%r15) + ny %r0, 524287(%r1,%r15) + ny %r0, 524287(%r15,%r1) + ny %r15, 0 diff --git a/test/MC/SystemZ/insn-ny-02.s b/test/MC/SystemZ/insn-ny-02.s new file mode 100644 index 000000000000..5f53ebd3e114 --- /dev/null +++ b/test/MC/SystemZ/insn-ny-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ny %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ny %r0, 524288 + + ny %r0, -524289 + ny %r0, 524288 diff --git a/test/MC/SystemZ/insn-o-01.s b/test/MC/SystemZ/insn-o-01.s new file mode 100644 index 000000000000..0c74e9ccc6dc --- /dev/null +++ b/test/MC/SystemZ/insn-o-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: o %r0, 0 # encoding: [0x56,0x00,0x00,0x00] +#CHECK: o %r0, 4095 # encoding: [0x56,0x00,0x0f,0xff] +#CHECK: o %r0, 0(%r1) # encoding: [0x56,0x00,0x10,0x00] +#CHECK: o %r0, 0(%r15) # encoding: [0x56,0x00,0xf0,0x00] +#CHECK: o %r0, 4095(%r1,%r15) # encoding: [0x56,0x01,0xff,0xff] +#CHECK: o %r0, 4095(%r15,%r1) # encoding: [0x56,0x0f,0x1f,0xff] +#CHECK: o %r15, 0 # encoding: [0x56,0xf0,0x00,0x00] + + o %r0, 0 + o %r0, 4095 + o %r0, 0(%r1) + o %r0, 0(%r15) + o %r0, 4095(%r1,%r15) + o %r0, 4095(%r15,%r1) + o %r15, 0 diff --git a/test/MC/SystemZ/insn-o-02.s b/test/MC/SystemZ/insn-o-02.s new file mode 100644 index 000000000000..34b741803b42 --- /dev/null +++ b/test/MC/SystemZ/insn-o-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: o %r0, -1 +#CHECK: error: invalid operand +#CHECK: o %r0, 4096 + + o %r0, -1 + o %r0, 4096 diff --git a/test/MC/SystemZ/insn-og-01.s b/test/MC/SystemZ/insn-og-01.s new file mode 100644 index 000000000000..3c9811b008a6 --- /dev/null +++ b/test/MC/SystemZ/insn-og-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: og %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x81] +#CHECK: og %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x81] +#CHECK: og %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x81] +#CHECK: og %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x81] +#CHECK: og %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x81] +#CHECK: og %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x81] +#CHECK: og %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x81] +#CHECK: og %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x81] +#CHECK: og %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x81] +#CHECK: og %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x81] + + og %r0, -524288 + og %r0, -1 + og %r0, 0 + og %r0, 1 + og %r0, 524287 + og %r0, 0(%r1) + og %r0, 0(%r15) + og %r0, 524287(%r1,%r15) + og %r0, 524287(%r15,%r1) + og %r15, 0 diff --git a/test/MC/SystemZ/insn-og-02.s b/test/MC/SystemZ/insn-og-02.s new file mode 100644 index 000000000000..7f4e45328be7 --- /dev/null +++ b/test/MC/SystemZ/insn-og-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: og %r0, -524289 +#CHECK: error: invalid operand +#CHECK: og %r0, 524288 + + og %r0, -524289 + og %r0, 524288 diff --git a/test/MC/SystemZ/insn-ogr-01.s b/test/MC/SystemZ/insn-ogr-01.s new file mode 100644 index 000000000000..25ba913ac557 --- /dev/null +++ b/test/MC/SystemZ/insn-ogr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ogr %r0, %r0 # encoding: [0xb9,0x81,0x00,0x00] +#CHECK: ogr %r0, %r15 # encoding: [0xb9,0x81,0x00,0x0f] +#CHECK: ogr %r15, %r0 # encoding: [0xb9,0x81,0x00,0xf0] +#CHECK: ogr %r7, %r8 # encoding: [0xb9,0x81,0x00,0x78] + + ogr %r0,%r0 + ogr %r0,%r15 + ogr %r15,%r0 + ogr %r7,%r8 diff --git a/test/MC/SystemZ/insn-oi-01.s b/test/MC/SystemZ/insn-oi-01.s new file mode 100644 index 000000000000..5d52fd2500bd --- /dev/null +++ b/test/MC/SystemZ/insn-oi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oi 0, 0 # encoding: [0x96,0x00,0x00,0x00] +#CHECK: oi 4095, 0 # encoding: [0x96,0x00,0x0f,0xff] +#CHECK: oi 0, 255 # encoding: [0x96,0xff,0x00,0x00] +#CHECK: oi 0(%r1), 42 # encoding: [0x96,0x2a,0x10,0x00] +#CHECK: oi 0(%r15), 42 # encoding: [0x96,0x2a,0xf0,0x00] +#CHECK: oi 4095(%r1), 42 # encoding: [0x96,0x2a,0x1f,0xff] +#CHECK: oi 4095(%r15), 42 # encoding: [0x96,0x2a,0xff,0xff] + + oi 0, 0 + oi 4095, 0 + oi 0, 255 + oi 0(%r1), 42 + oi 0(%r15), 42 + oi 4095(%r1), 42 + oi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-oi-02.s b/test/MC/SystemZ/insn-oi-02.s new file mode 100644 index 000000000000..330a290aa365 --- /dev/null +++ b/test/MC/SystemZ/insn-oi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oi -1, 0 +#CHECK: error: invalid operand +#CHECK: oi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: oi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: oi 0, -1 +#CHECK: error: invalid operand +#CHECK: oi 0, 256 + + oi -1, 0 + oi 4096, 0 + oi 0(%r1,%r2), 0 + oi 0, -1 + oi 0, 256 diff --git a/test/MC/SystemZ/insn-oihf-01.s b/test/MC/SystemZ/insn-oihf-01.s new file mode 100644 index 000000000000..627820d31dcb --- /dev/null +++ b/test/MC/SystemZ/insn-oihf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oihf %r0, 0 # encoding: [0xc0,0x0c,0x00,0x00,0x00,0x00] +#CHECK: oihf %r0, 4294967295 # encoding: [0xc0,0x0c,0xff,0xff,0xff,0xff] +#CHECK: oihf %r15, 0 # encoding: [0xc0,0xfc,0x00,0x00,0x00,0x00] + + oihf %r0, 0 + oihf %r0, 0xffffffff + oihf %r15, 0 diff --git a/test/MC/SystemZ/insn-oihf-02.s b/test/MC/SystemZ/insn-oihf-02.s new file mode 100644 index 000000000000..a944cb013cd4 --- /dev/null +++ b/test/MC/SystemZ/insn-oihf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oihf %r0, -1 +#CHECK: error: invalid operand +#CHECK: oihf %r0, 1 << 32 + + oihf %r0, -1 + oihf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-oihh-01.s b/test/MC/SystemZ/insn-oihh-01.s new file mode 100644 index 000000000000..f62f61f03f88 --- /dev/null +++ b/test/MC/SystemZ/insn-oihh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oihh %r0, 0 # encoding: [0xa5,0x08,0x00,0x00] +#CHECK: oihh %r0, 32768 # encoding: [0xa5,0x08,0x80,0x00] +#CHECK: oihh %r0, 65535 # encoding: [0xa5,0x08,0xff,0xff] +#CHECK: oihh %r15, 0 # encoding: [0xa5,0xf8,0x00,0x00] + + oihh %r0, 0 + oihh %r0, 0x8000 + oihh %r0, 0xffff + oihh %r15, 0 diff --git a/test/MC/SystemZ/insn-oihh-02.s b/test/MC/SystemZ/insn-oihh-02.s new file mode 100644 index 000000000000..6bf7e237e039 --- /dev/null +++ b/test/MC/SystemZ/insn-oihh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oihh %r0, -1 +#CHECK: error: invalid operand +#CHECK: oihh %r0, 0x10000 + + oihh %r0, -1 + oihh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-oihl-01.s b/test/MC/SystemZ/insn-oihl-01.s new file mode 100644 index 000000000000..437b15c39c17 --- /dev/null +++ b/test/MC/SystemZ/insn-oihl-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oihl %r0, 0 # encoding: [0xa5,0x09,0x00,0x00] +#CHECK: oihl %r0, 32768 # encoding: [0xa5,0x09,0x80,0x00] +#CHECK: oihl %r0, 65535 # encoding: [0xa5,0x09,0xff,0xff] +#CHECK: oihl %r15, 0 # encoding: [0xa5,0xf9,0x00,0x00] + + oihl %r0, 0 + oihl %r0, 0x8000 + oihl %r0, 0xffff + oihl %r15, 0 diff --git a/test/MC/SystemZ/insn-oihl-02.s b/test/MC/SystemZ/insn-oihl-02.s new file mode 100644 index 000000000000..f4f7a59b774c --- /dev/null +++ b/test/MC/SystemZ/insn-oihl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oihl %r0, -1 +#CHECK: error: invalid operand +#CHECK: oihl %r0, 0x10000 + + oihl %r0, -1 + oihl %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-oilf-01.s b/test/MC/SystemZ/insn-oilf-01.s new file mode 100644 index 000000000000..6f0c0717bd0e --- /dev/null +++ b/test/MC/SystemZ/insn-oilf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oilf %r0, 0 # encoding: [0xc0,0x0d,0x00,0x00,0x00,0x00] +#CHECK: oilf %r0, 4294967295 # encoding: [0xc0,0x0d,0xff,0xff,0xff,0xff] +#CHECK: oilf %r15, 0 # encoding: [0xc0,0xfd,0x00,0x00,0x00,0x00] + + oilf %r0, 0 + oilf %r0, 0xffffffff + oilf %r15, 0 diff --git a/test/MC/SystemZ/insn-oilf-02.s b/test/MC/SystemZ/insn-oilf-02.s new file mode 100644 index 000000000000..5501724d54c1 --- /dev/null +++ b/test/MC/SystemZ/insn-oilf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oilf %r0, -1 +#CHECK: error: invalid operand +#CHECK: oilf %r0, 1 << 32 + + oilf %r0, -1 + oilf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-oilh-01.s b/test/MC/SystemZ/insn-oilh-01.s new file mode 100644 index 000000000000..0140500e340f --- /dev/null +++ b/test/MC/SystemZ/insn-oilh-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oilh %r0, 0 # encoding: [0xa5,0x0a,0x00,0x00] +#CHECK: oilh %r0, 32768 # encoding: [0xa5,0x0a,0x80,0x00] +#CHECK: oilh %r0, 65535 # encoding: [0xa5,0x0a,0xff,0xff] +#CHECK: oilh %r15, 0 # encoding: [0xa5,0xfa,0x00,0x00] + + oilh %r0, 0 + oilh %r0, 0x8000 + oilh %r0, 0xffff + oilh %r15, 0 diff --git a/test/MC/SystemZ/insn-oilh-02.s b/test/MC/SystemZ/insn-oilh-02.s new file mode 100644 index 000000000000..d2f180d6abd3 --- /dev/null +++ b/test/MC/SystemZ/insn-oilh-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oilh %r0, -1 +#CHECK: error: invalid operand +#CHECK: oilh %r0, 0x10000 + + oilh %r0, -1 + oilh %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-oill-01.s b/test/MC/SystemZ/insn-oill-01.s new file mode 100644 index 000000000000..ef95d2d90f52 --- /dev/null +++ b/test/MC/SystemZ/insn-oill-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oill %r0, 0 # encoding: [0xa5,0x0b,0x00,0x00] +#CHECK: oill %r0, 32768 # encoding: [0xa5,0x0b,0x80,0x00] +#CHECK: oill %r0, 65535 # encoding: [0xa5,0x0b,0xff,0xff] +#CHECK: oill %r15, 0 # encoding: [0xa5,0xfb,0x00,0x00] + + oill %r0, 0 + oill %r0, 0x8000 + oill %r0, 0xffff + oill %r15, 0 diff --git a/test/MC/SystemZ/insn-oill-02.s b/test/MC/SystemZ/insn-oill-02.s new file mode 100644 index 000000000000..01321db30937 --- /dev/null +++ b/test/MC/SystemZ/insn-oill-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oill %r0, -1 +#CHECK: error: invalid operand +#CHECK: oill %r0, 0x10000 + + oill %r0, -1 + oill %r0, 0x10000 diff --git a/test/MC/SystemZ/insn-oiy-01.s b/test/MC/SystemZ/insn-oiy-01.s new file mode 100644 index 000000000000..ba060cad1efa --- /dev/null +++ b/test/MC/SystemZ/insn-oiy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oiy -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x56] +#CHECK: oiy -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x56] +#CHECK: oiy 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x56] +#CHECK: oiy 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x56] +#CHECK: oiy 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x56] +#CHECK: oiy 0, 255 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x56] +#CHECK: oiy 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x56] +#CHECK: oiy 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x56] +#CHECK: oiy 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x56] +#CHECK: oiy 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x56] + + oiy -524288, 0 + oiy -1, 0 + oiy 0, 0 + oiy 1, 0 + oiy 524287, 0 + oiy 0, 255 + oiy 0(%r1), 42 + oiy 0(%r15), 42 + oiy 524287(%r1), 42 + oiy 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-oiy-02.s b/test/MC/SystemZ/insn-oiy-02.s new file mode 100644 index 000000000000..c1c556931da1 --- /dev/null +++ b/test/MC/SystemZ/insn-oiy-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oiy -524289, 0 +#CHECK: error: invalid operand +#CHECK: oiy 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: oiy 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: oiy 0, -1 +#CHECK: error: invalid operand +#CHECK: oiy 0, 256 + + oiy -524289, 0 + oiy 524288, 0 + oiy 0(%r1,%r2), 0 + oiy 0, -1 + oiy 0, 256 diff --git a/test/MC/SystemZ/insn-or-01.s b/test/MC/SystemZ/insn-or-01.s new file mode 100644 index 000000000000..8ac366d32ac0 --- /dev/null +++ b/test/MC/SystemZ/insn-or-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: or %r0, %r0 # encoding: [0x16,0x00] +#CHECK: or %r0, %r15 # encoding: [0x16,0x0f] +#CHECK: or %r15, %r0 # encoding: [0x16,0xf0] +#CHECK: or %r7, %r8 # encoding: [0x16,0x78] + + or %r0,%r0 + or %r0,%r15 + or %r15,%r0 + or %r7,%r8 diff --git a/test/MC/SystemZ/insn-oy-01.s b/test/MC/SystemZ/insn-oy-01.s new file mode 100644 index 000000000000..58013d0cabbd --- /dev/null +++ b/test/MC/SystemZ/insn-oy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: oy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x56] +#CHECK: oy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x56] +#CHECK: oy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x56] +#CHECK: oy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x56] +#CHECK: oy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x56] +#CHECK: oy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x56] +#CHECK: oy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x56] +#CHECK: oy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x56] +#CHECK: oy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x56] +#CHECK: oy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x56] + + oy %r0, -524288 + oy %r0, -1 + oy %r0, 0 + oy %r0, 1 + oy %r0, 524287 + oy %r0, 0(%r1) + oy %r0, 0(%r15) + oy %r0, 524287(%r1,%r15) + oy %r0, 524287(%r15,%r1) + oy %r15, 0 diff --git a/test/MC/SystemZ/insn-oy-02.s b/test/MC/SystemZ/insn-oy-02.s new file mode 100644 index 000000000000..a9ae5b23954a --- /dev/null +++ b/test/MC/SystemZ/insn-oy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: oy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: oy %r0, 524288 + + oy %r0, -524289 + oy %r0, 524288 diff --git a/test/MC/SystemZ/insn-risbg-01.s b/test/MC/SystemZ/insn-risbg-01.s new file mode 100644 index 000000000000..b50fbe7f96bd --- /dev/null +++ b/test/MC/SystemZ/insn-risbg-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] +#CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] +#CHECK: risbg %r0, %r0, 0, 63, 0 # encoding: [0xec,0x00,0x00,0x3f,0x00,0x55] +#CHECK: risbg %r0, %r0, 63, 0, 0 # encoding: [0xec,0x00,0x3f,0x00,0x00,0x55] +#CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55] +#CHECK: risbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55] +#CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55] + + risbg %r0,%r0,0,0,0 + risbg %r0,%r0,0,0,63 + risbg %r0,%r0,0,63,0 + risbg %r0,%r0,63,0,0 + risbg %r0,%r15,0,0,0 + risbg %r15,%r0,0,0,0 + risbg %r4,%r5,6,7,8 diff --git a/test/MC/SystemZ/insn-risbg-02.s b/test/MC/SystemZ/insn-risbg-02.s new file mode 100644 index 000000000000..781cb563c847 --- /dev/null +++ b/test/MC/SystemZ/insn-risbg-02.s @@ -0,0 +1,22 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,0,0,-1 +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,0,0,64 +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,0,-1,0 +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,0,64,0 +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,-1,0,0 +#CHECK: error: invalid operand +#CHECK: risbg %r0,%r0,64,0,0 + + risbg %r0,%r0,0,0,-1 + risbg %r0,%r0,0,0,64 + risbg %r0,%r0,0,-1,0 + risbg %r0,%r0,0,64,0 + risbg %r0,%r0,-1,0,0 + risbg %r0,%r0,64,0,0 diff --git a/test/MC/SystemZ/insn-rll-01.s b/test/MC/SystemZ/insn-rll-01.s new file mode 100644 index 000000000000..06e3774786c9 --- /dev/null +++ b/test/MC/SystemZ/insn-rll-01.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: rll %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1d] +#CHECK: rll %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1d] +#CHECK: rll %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x1d] +#CHECK: rll %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x1d] +#CHECK: rll %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x1d] +#CHECK: rll %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x1d] +#CHECK: rll %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x1d] +#CHECK: rll %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x1d] +#CHECK: rll %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x1d] +#CHECK: rll %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x1d] +#CHECK: rll %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x1d] +#CHECK: rll %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x1d] + + rll %r0,%r0,0 + rll %r15,%r1,0 + rll %r1,%r15,0 + rll %r15,%r15,0 + rll %r0,%r0,-524288 + rll %r0,%r0,-1 + rll %r0,%r0,1 + rll %r0,%r0,524287 + rll %r0,%r0,0(%r1) + rll %r0,%r0,0(%r15) + rll %r0,%r0,524287(%r1) + rll %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-rll-02.s b/test/MC/SystemZ/insn-rll-02.s new file mode 100644 index 000000000000..baf160700fcb --- /dev/null +++ b/test/MC/SystemZ/insn-rll-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: rll %r0,%r0,-524289 +#CHECK: error: invalid operand +#CHECK: rll %r0,%r0,524288 +#CHECK: error: %r0 used in an address +#CHECK: rll %r0,%r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: rll %r0,%r0,0(%r1,%r2) + + rll %r0,%r0,-524289 + rll %r0,%r0,524288 + rll %r0,%r0,0(%r0) + rll %r0,%r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-rllg-01.s b/test/MC/SystemZ/insn-rllg-01.s new file mode 100644 index 000000000000..c36dc6daf20b --- /dev/null +++ b/test/MC/SystemZ/insn-rllg-01.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: rllg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x1c] +#CHECK: rllg %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x1c] +#CHECK: rllg %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x1c] +#CHECK: rllg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x1c] +#CHECK: rllg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x1c] +#CHECK: rllg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x1c] +#CHECK: rllg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x1c] +#CHECK: rllg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x1c] +#CHECK: rllg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x1c] +#CHECK: rllg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x1c] +#CHECK: rllg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x1c] +#CHECK: rllg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x1c] + + rllg %r0,%r0,0 + rllg %r15,%r1,0 + rllg %r1,%r15,0 + rllg %r15,%r15,0 + rllg %r0,%r0,-524288 + rllg %r0,%r0,-1 + rllg %r0,%r0,1 + rllg %r0,%r0,524287 + rllg %r0,%r0,0(%r1) + rllg %r0,%r0,0(%r15) + rllg %r0,%r0,524287(%r1) + rllg %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-rllg-02.s b/test/MC/SystemZ/insn-rllg-02.s new file mode 100644 index 000000000000..7f82845aa646 --- /dev/null +++ b/test/MC/SystemZ/insn-rllg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: rllg %r0,%r0,-524289 +#CHECK: error: invalid operand +#CHECK: rllg %r0,%r0,524288 +#CHECK: error: %r0 used in an address +#CHECK: rllg %r0,%r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: rllg %r0,%r0,0(%r1,%r2) + + rllg %r0,%r0,-524289 + rllg %r0,%r0,524288 + rllg %r0,%r0,0(%r0) + rllg %r0,%r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-s-01.s b/test/MC/SystemZ/insn-s-01.s new file mode 100644 index 000000000000..2effedbc6c88 --- /dev/null +++ b/test/MC/SystemZ/insn-s-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: s %r0, 0 # encoding: [0x5b,0x00,0x00,0x00] +#CHECK: s %r0, 4095 # encoding: [0x5b,0x00,0x0f,0xff] +#CHECK: s %r0, 0(%r1) # encoding: [0x5b,0x00,0x10,0x00] +#CHECK: s %r0, 0(%r15) # encoding: [0x5b,0x00,0xf0,0x00] +#CHECK: s %r0, 4095(%r1,%r15) # encoding: [0x5b,0x01,0xff,0xff] +#CHECK: s %r0, 4095(%r15,%r1) # encoding: [0x5b,0x0f,0x1f,0xff] +#CHECK: s %r15, 0 # encoding: [0x5b,0xf0,0x00,0x00] + + s %r0, 0 + s %r0, 4095 + s %r0, 0(%r1) + s %r0, 0(%r15) + s %r0, 4095(%r1,%r15) + s %r0, 4095(%r15,%r1) + s %r15, 0 diff --git a/test/MC/SystemZ/insn-s-02.s b/test/MC/SystemZ/insn-s-02.s new file mode 100644 index 000000000000..f0b4a137ec74 --- /dev/null +++ b/test/MC/SystemZ/insn-s-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: s %r0, -1 +#CHECK: error: invalid operand +#CHECK: s %r0, 4096 + + s %r0, -1 + s %r0, 4096 diff --git a/test/MC/SystemZ/insn-sdb-01.s b/test/MC/SystemZ/insn-sdb-01.s new file mode 100644 index 000000000000..9267796ece45 --- /dev/null +++ b/test/MC/SystemZ/insn-sdb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1b] +#CHECK: sdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1b] +#CHECK: sdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1b] +#CHECK: sdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x1b] +#CHECK: sdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x1b] +#CHECK: sdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x1b] +#CHECK: sdb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x1b] + + sdb %f0, 0 + sdb %f0, 4095 + sdb %f0, 0(%r1) + sdb %f0, 0(%r15) + sdb %f0, 4095(%r1,%r15) + sdb %f0, 4095(%r15,%r1) + sdb %f15, 0 diff --git a/test/MC/SystemZ/insn-sdb-02.s b/test/MC/SystemZ/insn-sdb-02.s new file mode 100644 index 000000000000..c77284fb9a8c --- /dev/null +++ b/test/MC/SystemZ/insn-sdb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: sdb %f0, 4096 + + sdb %f0, -1 + sdb %f0, 4096 diff --git a/test/MC/SystemZ/insn-sdbr-01.s b/test/MC/SystemZ/insn-sdbr-01.s new file mode 100644 index 000000000000..b07f5f2cd8fd --- /dev/null +++ b/test/MC/SystemZ/insn-sdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sdbr %f0, %f0 # encoding: [0xb3,0x1b,0x00,0x00] +#CHECK: sdbr %f0, %f15 # encoding: [0xb3,0x1b,0x00,0x0f] +#CHECK: sdbr %f7, %f8 # encoding: [0xb3,0x1b,0x00,0x78] +#CHECK: sdbr %f15, %f0 # encoding: [0xb3,0x1b,0x00,0xf0] + + sdbr %f0, %f0 + sdbr %f0, %f15 + sdbr %f7, %f8 + sdbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-seb-01.s b/test/MC/SystemZ/insn-seb-01.s new file mode 100644 index 000000000000..4bf5cfa06271 --- /dev/null +++ b/test/MC/SystemZ/insn-seb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: seb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x0b] +#CHECK: seb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x0b] +#CHECK: seb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x0b] +#CHECK: seb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x0b] +#CHECK: seb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x0b] +#CHECK: seb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x0b] +#CHECK: seb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x0b] + + seb %f0, 0 + seb %f0, 4095 + seb %f0, 0(%r1) + seb %f0, 0(%r15) + seb %f0, 4095(%r1,%r15) + seb %f0, 4095(%r15,%r1) + seb %f15, 0 diff --git a/test/MC/SystemZ/insn-seb-02.s b/test/MC/SystemZ/insn-seb-02.s new file mode 100644 index 000000000000..e185a20fdc20 --- /dev/null +++ b/test/MC/SystemZ/insn-seb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: seb %f0, -1 +#CHECK: error: invalid operand +#CHECK: seb %f0, 4096 + + seb %f0, -1 + seb %f0, 4096 diff --git a/test/MC/SystemZ/insn-sebr-01.s b/test/MC/SystemZ/insn-sebr-01.s new file mode 100644 index 000000000000..467b57cabe01 --- /dev/null +++ b/test/MC/SystemZ/insn-sebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sebr %f0, %f0 # encoding: [0xb3,0x0b,0x00,0x00] +#CHECK: sebr %f0, %f15 # encoding: [0xb3,0x0b,0x00,0x0f] +#CHECK: sebr %f7, %f8 # encoding: [0xb3,0x0b,0x00,0x78] +#CHECK: sebr %f15, %f0 # encoding: [0xb3,0x0b,0x00,0xf0] + + sebr %f0, %f0 + sebr %f0, %f15 + sebr %f7, %f8 + sebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-sg-01.s b/test/MC/SystemZ/insn-sg-01.s new file mode 100644 index 000000000000..153df1ae2d67 --- /dev/null +++ b/test/MC/SystemZ/insn-sg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x09] +#CHECK: sg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x09] +#CHECK: sg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x09] +#CHECK: sg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x09] +#CHECK: sg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x09] +#CHECK: sg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x09] +#CHECK: sg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x09] +#CHECK: sg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x09] +#CHECK: sg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x09] +#CHECK: sg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x09] + + sg %r0, -524288 + sg %r0, -1 + sg %r0, 0 + sg %r0, 1 + sg %r0, 524287 + sg %r0, 0(%r1) + sg %r0, 0(%r15) + sg %r0, 524287(%r1,%r15) + sg %r0, 524287(%r15,%r1) + sg %r15, 0 diff --git a/test/MC/SystemZ/insn-sg-02.s b/test/MC/SystemZ/insn-sg-02.s new file mode 100644 index 000000000000..f183e58f7b74 --- /dev/null +++ b/test/MC/SystemZ/insn-sg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sg %r0, 524288 + + sg %r0, -524289 + sg %r0, 524288 diff --git a/test/MC/SystemZ/insn-sgf-01.s b/test/MC/SystemZ/insn-sgf-01.s new file mode 100644 index 000000000000..844c09998d38 --- /dev/null +++ b/test/MC/SystemZ/insn-sgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x19] +#CHECK: sgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x19] +#CHECK: sgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x19] +#CHECK: sgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x19] +#CHECK: sgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x19] +#CHECK: sgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x19] +#CHECK: sgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x19] +#CHECK: sgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x19] +#CHECK: sgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x19] +#CHECK: sgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x19] + + sgf %r0, -524288 + sgf %r0, -1 + sgf %r0, 0 + sgf %r0, 1 + sgf %r0, 524287 + sgf %r0, 0(%r1) + sgf %r0, 0(%r15) + sgf %r0, 524287(%r1,%r15) + sgf %r0, 524287(%r15,%r1) + sgf %r15, 0 diff --git a/test/MC/SystemZ/insn-sgf-02.s b/test/MC/SystemZ/insn-sgf-02.s new file mode 100644 index 000000000000..7eba3abe2c3f --- /dev/null +++ b/test/MC/SystemZ/insn-sgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sgf %r0, 524288 + + sgf %r0, -524289 + sgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-sgfr-01.s b/test/MC/SystemZ/insn-sgfr-01.s new file mode 100644 index 000000000000..49a1412f8814 --- /dev/null +++ b/test/MC/SystemZ/insn-sgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sgfr %r0, %r0 # encoding: [0xb9,0x19,0x00,0x00] +#CHECK: sgfr %r0, %r15 # encoding: [0xb9,0x19,0x00,0x0f] +#CHECK: sgfr %r15, %r0 # encoding: [0xb9,0x19,0x00,0xf0] +#CHECK: sgfr %r7, %r8 # encoding: [0xb9,0x19,0x00,0x78] + + sgfr %r0,%r0 + sgfr %r0,%r15 + sgfr %r15,%r0 + sgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-sgr-01.s b/test/MC/SystemZ/insn-sgr-01.s new file mode 100644 index 000000000000..86c59a145254 --- /dev/null +++ b/test/MC/SystemZ/insn-sgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sgr %r0, %r0 # encoding: [0xb9,0x09,0x00,0x00] +#CHECK: sgr %r0, %r15 # encoding: [0xb9,0x09,0x00,0x0f] +#CHECK: sgr %r15, %r0 # encoding: [0xb9,0x09,0x00,0xf0] +#CHECK: sgr %r7, %r8 # encoding: [0xb9,0x09,0x00,0x78] + + sgr %r0,%r0 + sgr %r0,%r15 + sgr %r15,%r0 + sgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-sl-01.s b/test/MC/SystemZ/insn-sl-01.s new file mode 100644 index 000000000000..c2186da486cf --- /dev/null +++ b/test/MC/SystemZ/insn-sl-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sl %r0, 0 # encoding: [0x5f,0x00,0x00,0x00] +#CHECK: sl %r0, 4095 # encoding: [0x5f,0x00,0x0f,0xff] +#CHECK: sl %r0, 0(%r1) # encoding: [0x5f,0x00,0x10,0x00] +#CHECK: sl %r0, 0(%r15) # encoding: [0x5f,0x00,0xf0,0x00] +#CHECK: sl %r0, 4095(%r1,%r15) # encoding: [0x5f,0x01,0xff,0xff] +#CHECK: sl %r0, 4095(%r15,%r1) # encoding: [0x5f,0x0f,0x1f,0xff] +#CHECK: sl %r15, 0 # encoding: [0x5f,0xf0,0x00,0x00] + + sl %r0, 0 + sl %r0, 4095 + sl %r0, 0(%r1) + sl %r0, 0(%r15) + sl %r0, 4095(%r1,%r15) + sl %r0, 4095(%r15,%r1) + sl %r15, 0 diff --git a/test/MC/SystemZ/insn-sl-02.s b/test/MC/SystemZ/insn-sl-02.s new file mode 100644 index 000000000000..8abd99d23514 --- /dev/null +++ b/test/MC/SystemZ/insn-sl-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sl %r0, -1 +#CHECK: error: invalid operand +#CHECK: sl %r0, 4096 + + sl %r0, -1 + sl %r0, 4096 diff --git a/test/MC/SystemZ/insn-slb-01.s b/test/MC/SystemZ/insn-slb-01.s new file mode 100644 index 000000000000..4bc79f6746a9 --- /dev/null +++ b/test/MC/SystemZ/insn-slb-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slb %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x99] +#CHECK: slb %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x99] +#CHECK: slb %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x99] +#CHECK: slb %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x99] +#CHECK: slb %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x99] +#CHECK: slb %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x99] +#CHECK: slb %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x99] +#CHECK: slb %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x99] +#CHECK: slb %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x99] +#CHECK: slb %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x99] + + slb %r0, -524288 + slb %r0, -1 + slb %r0, 0 + slb %r0, 1 + slb %r0, 524287 + slb %r0, 0(%r1) + slb %r0, 0(%r15) + slb %r0, 524287(%r1,%r15) + slb %r0, 524287(%r15,%r1) + slb %r15, 0 diff --git a/test/MC/SystemZ/insn-slb-02.s b/test/MC/SystemZ/insn-slb-02.s new file mode 100644 index 000000000000..ac87128ffc4d --- /dev/null +++ b/test/MC/SystemZ/insn-slb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slb %r0, -524289 +#CHECK: error: invalid operand +#CHECK: slb %r0, 524288 + + slb %r0, -524289 + slb %r0, 524288 diff --git a/test/MC/SystemZ/insn-slbg-01.s b/test/MC/SystemZ/insn-slbg-01.s new file mode 100644 index 000000000000..8878aeda5edc --- /dev/null +++ b/test/MC/SystemZ/insn-slbg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slbg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x89] +#CHECK: slbg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x89] +#CHECK: slbg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x89] +#CHECK: slbg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x89] +#CHECK: slbg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x89] +#CHECK: slbg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x89] +#CHECK: slbg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x89] +#CHECK: slbg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x89] +#CHECK: slbg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x89] +#CHECK: slbg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x89] + + slbg %r0, -524288 + slbg %r0, -1 + slbg %r0, 0 + slbg %r0, 1 + slbg %r0, 524287 + slbg %r0, 0(%r1) + slbg %r0, 0(%r15) + slbg %r0, 524287(%r1,%r15) + slbg %r0, 524287(%r15,%r1) + slbg %r15, 0 diff --git a/test/MC/SystemZ/insn-slbg-02.s b/test/MC/SystemZ/insn-slbg-02.s new file mode 100644 index 000000000000..ce09c8a9de51 --- /dev/null +++ b/test/MC/SystemZ/insn-slbg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slbg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: slbg %r0, 524288 + + slbg %r0, -524289 + slbg %r0, 524288 diff --git a/test/MC/SystemZ/insn-slbgr-01.s b/test/MC/SystemZ/insn-slbgr-01.s new file mode 100644 index 000000000000..bcc2b535ba7b --- /dev/null +++ b/test/MC/SystemZ/insn-slbgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slbgr %r0, %r0 # encoding: [0xb9,0x89,0x00,0x00] +#CHECK: slbgr %r0, %r15 # encoding: [0xb9,0x89,0x00,0x0f] +#CHECK: slbgr %r15, %r0 # encoding: [0xb9,0x89,0x00,0xf0] +#CHECK: slbgr %r7, %r8 # encoding: [0xb9,0x89,0x00,0x78] + + slbgr %r0,%r0 + slbgr %r0,%r15 + slbgr %r15,%r0 + slbgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-slbr-01.s b/test/MC/SystemZ/insn-slbr-01.s new file mode 100644 index 000000000000..9c10dbd02106 --- /dev/null +++ b/test/MC/SystemZ/insn-slbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slbr %r0, %r0 # encoding: [0xb9,0x99,0x00,0x00] +#CHECK: slbr %r0, %r15 # encoding: [0xb9,0x99,0x00,0x0f] +#CHECK: slbr %r15, %r0 # encoding: [0xb9,0x99,0x00,0xf0] +#CHECK: slbr %r7, %r8 # encoding: [0xb9,0x99,0x00,0x78] + + slbr %r0,%r0 + slbr %r0,%r15 + slbr %r15,%r0 + slbr %r7,%r8 diff --git a/test/MC/SystemZ/insn-slfi-01.s b/test/MC/SystemZ/insn-slfi-01.s new file mode 100644 index 000000000000..4c8e5b4a84d7 --- /dev/null +++ b/test/MC/SystemZ/insn-slfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slfi %r0, 0 # encoding: [0xc2,0x05,0x00,0x00,0x00,0x00] +#CHECK: slfi %r0, 4294967295 # encoding: [0xc2,0x05,0xff,0xff,0xff,0xff] +#CHECK: slfi %r15, 0 # encoding: [0xc2,0xf5,0x00,0x00,0x00,0x00] + + slfi %r0, 0 + slfi %r0, (1 << 32) - 1 + slfi %r15, 0 diff --git a/test/MC/SystemZ/insn-slfi-02.s b/test/MC/SystemZ/insn-slfi-02.s new file mode 100644 index 000000000000..12e14f6164b0 --- /dev/null +++ b/test/MC/SystemZ/insn-slfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: slfi %r0, (1 << 32) + + slfi %r0, -1 + slfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-slg-01.s b/test/MC/SystemZ/insn-slg-01.s new file mode 100644 index 000000000000..0b4f99e2e139 --- /dev/null +++ b/test/MC/SystemZ/insn-slg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x0b] +#CHECK: slg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x0b] +#CHECK: slg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x0b] +#CHECK: slg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x0b] +#CHECK: slg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x0b] +#CHECK: slg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x0b] +#CHECK: slg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x0b] +#CHECK: slg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x0b] +#CHECK: slg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x0b] +#CHECK: slg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x0b] + + slg %r0, -524288 + slg %r0, -1 + slg %r0, 0 + slg %r0, 1 + slg %r0, 524287 + slg %r0, 0(%r1) + slg %r0, 0(%r15) + slg %r0, 524287(%r1,%r15) + slg %r0, 524287(%r15,%r1) + slg %r15, 0 diff --git a/test/MC/SystemZ/insn-slg-02.s b/test/MC/SystemZ/insn-slg-02.s new file mode 100644 index 000000000000..1ad04c6111d0 --- /dev/null +++ b/test/MC/SystemZ/insn-slg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: slg %r0, 524288 + + slg %r0, -524289 + slg %r0, 524288 diff --git a/test/MC/SystemZ/insn-slgf-01.s b/test/MC/SystemZ/insn-slgf-01.s new file mode 100644 index 000000000000..bca480ecd77a --- /dev/null +++ b/test/MC/SystemZ/insn-slgf-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x1b] +#CHECK: slgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x1b] +#CHECK: slgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x1b] +#CHECK: slgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x1b] +#CHECK: slgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x1b] +#CHECK: slgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x1b] +#CHECK: slgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x1b] +#CHECK: slgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x1b] +#CHECK: slgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x1b] +#CHECK: slgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x1b] + + slgf %r0, -524288 + slgf %r0, -1 + slgf %r0, 0 + slgf %r0, 1 + slgf %r0, 524287 + slgf %r0, 0(%r1) + slgf %r0, 0(%r15) + slgf %r0, 524287(%r1,%r15) + slgf %r0, 524287(%r15,%r1) + slgf %r15, 0 diff --git a/test/MC/SystemZ/insn-slgf-02.s b/test/MC/SystemZ/insn-slgf-02.s new file mode 100644 index 000000000000..71a9aa7812e5 --- /dev/null +++ b/test/MC/SystemZ/insn-slgf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: slgf %r0, 524288 + + slgf %r0, -524289 + slgf %r0, 524288 diff --git a/test/MC/SystemZ/insn-slgfi-01.s b/test/MC/SystemZ/insn-slgfi-01.s new file mode 100644 index 000000000000..c9fef187f5ad --- /dev/null +++ b/test/MC/SystemZ/insn-slgfi-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slgfi %r0, 0 # encoding: [0xc2,0x04,0x00,0x00,0x00,0x00] +#CHECK: slgfi %r0, 4294967295 # encoding: [0xc2,0x04,0xff,0xff,0xff,0xff] +#CHECK: slgfi %r15, 0 # encoding: [0xc2,0xf4,0x00,0x00,0x00,0x00] + + slgfi %r0, 0 + slgfi %r0, (1 << 32) - 1 + slgfi %r15, 0 diff --git a/test/MC/SystemZ/insn-slgfi-02.s b/test/MC/SystemZ/insn-slgfi-02.s new file mode 100644 index 000000000000..696408d377e3 --- /dev/null +++ b/test/MC/SystemZ/insn-slgfi-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: slgfi %r0, -1 +#CHECK: error: invalid operand +#CHECK: slgfi %r0, (1 << 32) + + slgfi %r0, -1 + slgfi %r0, (1 << 32) diff --git a/test/MC/SystemZ/insn-slgfr-01.s b/test/MC/SystemZ/insn-slgfr-01.s new file mode 100644 index 000000000000..94c10edcd3b6 --- /dev/null +++ b/test/MC/SystemZ/insn-slgfr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slgfr %r0, %r0 # encoding: [0xb9,0x1b,0x00,0x00] +#CHECK: slgfr %r0, %r15 # encoding: [0xb9,0x1b,0x00,0x0f] +#CHECK: slgfr %r15, %r0 # encoding: [0xb9,0x1b,0x00,0xf0] +#CHECK: slgfr %r7, %r8 # encoding: [0xb9,0x1b,0x00,0x78] + + slgfr %r0,%r0 + slgfr %r0,%r15 + slgfr %r15,%r0 + slgfr %r7,%r8 diff --git a/test/MC/SystemZ/insn-slgr-01.s b/test/MC/SystemZ/insn-slgr-01.s new file mode 100644 index 000000000000..4d226be83e6e --- /dev/null +++ b/test/MC/SystemZ/insn-slgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slgr %r0, %r0 # encoding: [0xb9,0x0b,0x00,0x00] +#CHECK: slgr %r0, %r15 # encoding: [0xb9,0x0b,0x00,0x0f] +#CHECK: slgr %r15, %r0 # encoding: [0xb9,0x0b,0x00,0xf0] +#CHECK: slgr %r7, %r8 # encoding: [0xb9,0x0b,0x00,0x78] + + slgr %r0,%r0 + slgr %r0,%r15 + slgr %r15,%r0 + slgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-sll-01.s b/test/MC/SystemZ/insn-sll-01.s new file mode 100644 index 000000000000..5bc112856d70 --- /dev/null +++ b/test/MC/SystemZ/insn-sll-01.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sll %r0, 0 # encoding: [0x89,0x00,0x00,0x00] +#CHECK: sll %r7, 0 # encoding: [0x89,0x70,0x00,0x00] +#CHECK: sll %r15, 0 # encoding: [0x89,0xf0,0x00,0x00] +#CHECK: sll %r0, 4095 # encoding: [0x89,0x00,0x0f,0xff] +#CHECK: sll %r0, 0(%r1) # encoding: [0x89,0x00,0x10,0x00] +#CHECK: sll %r0, 0(%r15) # encoding: [0x89,0x00,0xf0,0x00] +#CHECK: sll %r0, 4095(%r1) # encoding: [0x89,0x00,0x1f,0xff] +#CHECK: sll %r0, 4095(%r15) # encoding: [0x89,0x00,0xff,0xff] + + sll %r0,0 + sll %r7,0 + sll %r15,0 + sll %r0,4095 + sll %r0,0(%r1) + sll %r0,0(%r15) + sll %r0,4095(%r1) + sll %r0,4095(%r15) diff --git a/test/MC/SystemZ/insn-sll-02.s b/test/MC/SystemZ/insn-sll-02.s new file mode 100644 index 000000000000..1b951be02c27 --- /dev/null +++ b/test/MC/SystemZ/insn-sll-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sll %r0,-1 +#CHECK: error: invalid operand +#CHECK: sll %r0,4096 +#CHECK: error: %r0 used in an address +#CHECK: sll %r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: sll %r0,0(%r1,%r2) + + sll %r0,-1 + sll %r0,4096 + sll %r0,0(%r0) + sll %r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-sllg-01.s b/test/MC/SystemZ/insn-sllg-01.s new file mode 100644 index 000000000000..1b0f0094676f --- /dev/null +++ b/test/MC/SystemZ/insn-sllg-01.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sllg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x0d] +#CHECK: sllg %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x0d] +#CHECK: sllg %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x0d] +#CHECK: sllg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x0d] +#CHECK: sllg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x0d] +#CHECK: sllg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x0d] +#CHECK: sllg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x0d] +#CHECK: sllg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x0d] +#CHECK: sllg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x0d] +#CHECK: sllg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x0d] +#CHECK: sllg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x0d] +#CHECK: sllg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x0d] + + sllg %r0,%r0,0 + sllg %r15,%r1,0 + sllg %r1,%r15,0 + sllg %r15,%r15,0 + sllg %r0,%r0,-524288 + sllg %r0,%r0,-1 + sllg %r0,%r0,1 + sllg %r0,%r0,524287 + sllg %r0,%r0,0(%r1) + sllg %r0,%r0,0(%r15) + sllg %r0,%r0,524287(%r1) + sllg %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-sllg-02.s b/test/MC/SystemZ/insn-sllg-02.s new file mode 100644 index 000000000000..68c3d1da29f4 --- /dev/null +++ b/test/MC/SystemZ/insn-sllg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sllg %r0,%r0,-524289 +#CHECK: error: invalid operand +#CHECK: sllg %r0,%r0,524288 +#CHECK: error: %r0 used in an address +#CHECK: sllg %r0,%r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: sllg %r0,%r0,0(%r1,%r2) + + sllg %r0,%r0,-524289 + sllg %r0,%r0,524288 + sllg %r0,%r0,0(%r0) + sllg %r0,%r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-slr-01.s b/test/MC/SystemZ/insn-slr-01.s new file mode 100644 index 000000000000..c142407cff64 --- /dev/null +++ b/test/MC/SystemZ/insn-slr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: slr %r0, %r0 # encoding: [0x1f,0x00] +#CHECK: slr %r0, %r15 # encoding: [0x1f,0x0f] +#CHECK: slr %r15, %r0 # encoding: [0x1f,0xf0] +#CHECK: slr %r7, %r8 # encoding: [0x1f,0x78] + + slr %r0,%r0 + slr %r0,%r15 + slr %r15,%r0 + slr %r7,%r8 diff --git a/test/MC/SystemZ/insn-sly-01.s b/test/MC/SystemZ/insn-sly-01.s new file mode 100644 index 000000000000..59d2907a4d8c --- /dev/null +++ b/test/MC/SystemZ/insn-sly-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sly %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5f] +#CHECK: sly %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5f] +#CHECK: sly %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5f] +#CHECK: sly %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x5f] +#CHECK: sly %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x5f] +#CHECK: sly %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x5f] +#CHECK: sly %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x5f] +#CHECK: sly %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x5f] +#CHECK: sly %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x5f] +#CHECK: sly %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x5f] + + sly %r0, -524288 + sly %r0, -1 + sly %r0, 0 + sly %r0, 1 + sly %r0, 524287 + sly %r0, 0(%r1) + sly %r0, 0(%r15) + sly %r0, 524287(%r1,%r15) + sly %r0, 524287(%r15,%r1) + sly %r15, 0 diff --git a/test/MC/SystemZ/insn-sly-02.s b/test/MC/SystemZ/insn-sly-02.s new file mode 100644 index 000000000000..9abd53e1ab1e --- /dev/null +++ b/test/MC/SystemZ/insn-sly-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sly %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sly %r0, 524288 + + sly %r0, -524289 + sly %r0, 524288 diff --git a/test/MC/SystemZ/insn-sqdb-01.s b/test/MC/SystemZ/insn-sqdb-01.s new file mode 100644 index 000000000000..b79aae144429 --- /dev/null +++ b/test/MC/SystemZ/insn-sqdb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sqdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x15] +#CHECK: sqdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x15] +#CHECK: sqdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x15] +#CHECK: sqdb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x15] +#CHECK: sqdb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x15] +#CHECK: sqdb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x15] +#CHECK: sqdb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x15] + + sqdb %f0, 0 + sqdb %f0, 4095 + sqdb %f0, 0(%r1) + sqdb %f0, 0(%r15) + sqdb %f0, 4095(%r1,%r15) + sqdb %f0, 4095(%r15,%r1) + sqdb %f15, 0 diff --git a/test/MC/SystemZ/insn-sqdb-02.s b/test/MC/SystemZ/insn-sqdb-02.s new file mode 100644 index 000000000000..68df26777045 --- /dev/null +++ b/test/MC/SystemZ/insn-sqdb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sqdb %f0, -1 +#CHECK: error: invalid operand +#CHECK: sqdb %f0, 4096 + + sqdb %f0, -1 + sqdb %f0, 4096 diff --git a/test/MC/SystemZ/insn-sqdbr-01.s b/test/MC/SystemZ/insn-sqdbr-01.s new file mode 100644 index 000000000000..d66415fa0523 --- /dev/null +++ b/test/MC/SystemZ/insn-sqdbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sqdbr %f0, %f0 # encoding: [0xb3,0x15,0x00,0x00] +#CHECK: sqdbr %f0, %f15 # encoding: [0xb3,0x15,0x00,0x0f] +#CHECK: sqdbr %f7, %f8 # encoding: [0xb3,0x15,0x00,0x78] +#CHECK: sqdbr %f15, %f0 # encoding: [0xb3,0x15,0x00,0xf0] + + sqdbr %f0, %f0 + sqdbr %f0, %f15 + sqdbr %f7, %f8 + sqdbr %f15, %f0 diff --git a/test/MC/SystemZ/insn-sqeb-01.s b/test/MC/SystemZ/insn-sqeb-01.s new file mode 100644 index 000000000000..60f6e9063572 --- /dev/null +++ b/test/MC/SystemZ/insn-sqeb-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sqeb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x14] +#CHECK: sqeb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x14] +#CHECK: sqeb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x14] +#CHECK: sqeb %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x14] +#CHECK: sqeb %f0, 4095(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x00,0x14] +#CHECK: sqeb %f0, 4095(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x00,0x14] +#CHECK: sqeb %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x14] + + sqeb %f0, 0 + sqeb %f0, 4095 + sqeb %f0, 0(%r1) + sqeb %f0, 0(%r15) + sqeb %f0, 4095(%r1,%r15) + sqeb %f0, 4095(%r15,%r1) + sqeb %f15, 0 diff --git a/test/MC/SystemZ/insn-sqeb-02.s b/test/MC/SystemZ/insn-sqeb-02.s new file mode 100644 index 000000000000..efb09fcfbc75 --- /dev/null +++ b/test/MC/SystemZ/insn-sqeb-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sqeb %f0, -1 +#CHECK: error: invalid operand +#CHECK: sqeb %f0, 4096 + + sqeb %f0, -1 + sqeb %f0, 4096 diff --git a/test/MC/SystemZ/insn-sqebr-01.s b/test/MC/SystemZ/insn-sqebr-01.s new file mode 100644 index 000000000000..2d13dbeb2654 --- /dev/null +++ b/test/MC/SystemZ/insn-sqebr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sqebr %f0, %f0 # encoding: [0xb3,0x14,0x00,0x00] +#CHECK: sqebr %f0, %f15 # encoding: [0xb3,0x14,0x00,0x0f] +#CHECK: sqebr %f7, %f8 # encoding: [0xb3,0x14,0x00,0x78] +#CHECK: sqebr %f15, %f0 # encoding: [0xb3,0x14,0x00,0xf0] + + sqebr %f0, %f0 + sqebr %f0, %f15 + sqebr %f7, %f8 + sqebr %f15, %f0 diff --git a/test/MC/SystemZ/insn-sqxbr-01.s b/test/MC/SystemZ/insn-sqxbr-01.s new file mode 100644 index 000000000000..78ba908d5af0 --- /dev/null +++ b/test/MC/SystemZ/insn-sqxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sqxbr %f0, %f0 # encoding: [0xb3,0x16,0x00,0x00] +#CHECK: sqxbr %f0, %f13 # encoding: [0xb3,0x16,0x00,0x0d] +#CHECK: sqxbr %f8, %f8 # encoding: [0xb3,0x16,0x00,0x88] +#CHECK: sqxbr %f13, %f0 # encoding: [0xb3,0x16,0x00,0xd0] + + sqxbr %f0, %f0 + sqxbr %f0, %f13 + sqxbr %f8, %f8 + sqxbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-sqxbr-02.s b/test/MC/SystemZ/insn-sqxbr-02.s new file mode 100644 index 000000000000..e51e552fb70d --- /dev/null +++ b/test/MC/SystemZ/insn-sqxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: sqxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: sqxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: sqxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: sqxbr %f14, %f0 + + sqxbr %f0, %f2 + sqxbr %f0, %f14 + sqxbr %f2, %f0 + sqxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-sr-01.s b/test/MC/SystemZ/insn-sr-01.s new file mode 100644 index 000000000000..856bef5eac99 --- /dev/null +++ b/test/MC/SystemZ/insn-sr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sr %r0, %r0 # encoding: [0x1b,0x00] +#CHECK: sr %r0, %r15 # encoding: [0x1b,0x0f] +#CHECK: sr %r15, %r0 # encoding: [0x1b,0xf0] +#CHECK: sr %r7, %r8 # encoding: [0x1b,0x78] + + sr %r0,%r0 + sr %r0,%r15 + sr %r15,%r0 + sr %r7,%r8 diff --git a/test/MC/SystemZ/insn-sra-01.s b/test/MC/SystemZ/insn-sra-01.s new file mode 100644 index 000000000000..fcdaf5de1625 --- /dev/null +++ b/test/MC/SystemZ/insn-sra-01.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sra %r0, 0 # encoding: [0x8a,0x00,0x00,0x00] +#CHECK: sra %r7, 0 # encoding: [0x8a,0x70,0x00,0x00] +#CHECK: sra %r15, 0 # encoding: [0x8a,0xf0,0x00,0x00] +#CHECK: sra %r0, 4095 # encoding: [0x8a,0x00,0x0f,0xff] +#CHECK: sra %r0, 0(%r1) # encoding: [0x8a,0x00,0x10,0x00] +#CHECK: sra %r0, 0(%r15) # encoding: [0x8a,0x00,0xf0,0x00] +#CHECK: sra %r0, 4095(%r1) # encoding: [0x8a,0x00,0x1f,0xff] +#CHECK: sra %r0, 4095(%r15) # encoding: [0x8a,0x00,0xff,0xff] + + sra %r0,0 + sra %r7,0 + sra %r15,0 + sra %r0,4095 + sra %r0,0(%r1) + sra %r0,0(%r15) + sra %r0,4095(%r1) + sra %r0,4095(%r15) diff --git a/test/MC/SystemZ/insn-sra-02.s b/test/MC/SystemZ/insn-sra-02.s new file mode 100644 index 000000000000..7a84f1774331 --- /dev/null +++ b/test/MC/SystemZ/insn-sra-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sra %r0,-1 +#CHECK: error: invalid operand +#CHECK: sra %r0,4096 +#CHECK: error: %r0 used in an address +#CHECK: sra %r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: sra %r0,0(%r1,%r2) + + sra %r0,-1 + sra %r0,4096 + sra %r0,0(%r0) + sra %r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-srag-01.s b/test/MC/SystemZ/insn-srag-01.s new file mode 100644 index 000000000000..9271db237d99 --- /dev/null +++ b/test/MC/SystemZ/insn-srag-01.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: srag %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x0a] +#CHECK: srag %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x0a] +#CHECK: srag %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x0a] +#CHECK: srag %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x0a] +#CHECK: srag %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x0a] +#CHECK: srag %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x0a] +#CHECK: srag %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x0a] +#CHECK: srag %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x0a] +#CHECK: srag %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x0a] +#CHECK: srag %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x0a] +#CHECK: srag %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x0a] +#CHECK: srag %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x0a] + + srag %r0,%r0,0 + srag %r15,%r1,0 + srag %r1,%r15,0 + srag %r15,%r15,0 + srag %r0,%r0,-524288 + srag %r0,%r0,-1 + srag %r0,%r0,1 + srag %r0,%r0,524287 + srag %r0,%r0,0(%r1) + srag %r0,%r0,0(%r15) + srag %r0,%r0,524287(%r1) + srag %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-srag-02.s b/test/MC/SystemZ/insn-srag-02.s new file mode 100644 index 000000000000..7413cbaf9fc3 --- /dev/null +++ b/test/MC/SystemZ/insn-srag-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: srag %r0,%r0,-524289 +#CHECK: error: invalid operand +#CHECK: srag %r0,%r0,524288 +#CHECK: error: %r0 used in an address +#CHECK: srag %r0,%r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: srag %r0,%r0,0(%r1,%r2) + + srag %r0,%r0,-524289 + srag %r0,%r0,524288 + srag %r0,%r0,0(%r0) + srag %r0,%r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-srl-01.s b/test/MC/SystemZ/insn-srl-01.s new file mode 100644 index 000000000000..a3a5df8a2bce --- /dev/null +++ b/test/MC/SystemZ/insn-srl-01.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: srl %r0, 0 # encoding: [0x88,0x00,0x00,0x00] +#CHECK: srl %r7, 0 # encoding: [0x88,0x70,0x00,0x00] +#CHECK: srl %r15, 0 # encoding: [0x88,0xf0,0x00,0x00] +#CHECK: srl %r0, 4095 # encoding: [0x88,0x00,0x0f,0xff] +#CHECK: srl %r0, 0(%r1) # encoding: [0x88,0x00,0x10,0x00] +#CHECK: srl %r0, 0(%r15) # encoding: [0x88,0x00,0xf0,0x00] +#CHECK: srl %r0, 4095(%r1) # encoding: [0x88,0x00,0x1f,0xff] +#CHECK: srl %r0, 4095(%r15) # encoding: [0x88,0x00,0xff,0xff] + + srl %r0,0 + srl %r7,0 + srl %r15,0 + srl %r0,4095 + srl %r0,0(%r1) + srl %r0,0(%r15) + srl %r0,4095(%r1) + srl %r0,4095(%r15) diff --git a/test/MC/SystemZ/insn-srl-02.s b/test/MC/SystemZ/insn-srl-02.s new file mode 100644 index 000000000000..212d16bd8d56 --- /dev/null +++ b/test/MC/SystemZ/insn-srl-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: srl %r0,-1 +#CHECK: error: invalid operand +#CHECK: srl %r0,4096 +#CHECK: error: %r0 used in an address +#CHECK: srl %r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: srl %r0,0(%r1,%r2) + + srl %r0,-1 + srl %r0,4096 + srl %r0,0(%r0) + srl %r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-srlg-01.s b/test/MC/SystemZ/insn-srlg-01.s new file mode 100644 index 000000000000..0087fefd9285 --- /dev/null +++ b/test/MC/SystemZ/insn-srlg-01.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: srlg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x0c] +#CHECK: srlg %r15, %r1, 0 # encoding: [0xeb,0xf1,0x00,0x00,0x00,0x0c] +#CHECK: srlg %r1, %r15, 0 # encoding: [0xeb,0x1f,0x00,0x00,0x00,0x0c] +#CHECK: srlg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x0c] +#CHECK: srlg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x0c] +#CHECK: srlg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x0c] +#CHECK: srlg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x0c] +#CHECK: srlg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x0c] +#CHECK: srlg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x0c] +#CHECK: srlg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x0c] +#CHECK: srlg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x0c] +#CHECK: srlg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x0c] + + srlg %r0,%r0,0 + srlg %r15,%r1,0 + srlg %r1,%r15,0 + srlg %r15,%r15,0 + srlg %r0,%r0,-524288 + srlg %r0,%r0,-1 + srlg %r0,%r0,1 + srlg %r0,%r0,524287 + srlg %r0,%r0,0(%r1) + srlg %r0,%r0,0(%r15) + srlg %r0,%r0,524287(%r1) + srlg %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-srlg-02.s b/test/MC/SystemZ/insn-srlg-02.s new file mode 100644 index 000000000000..1e24d0e407f3 --- /dev/null +++ b/test/MC/SystemZ/insn-srlg-02.s @@ -0,0 +1,16 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: srlg %r0,%r0,-524289 +#CHECK: error: invalid operand +#CHECK: srlg %r0,%r0,524288 +#CHECK: error: %r0 used in an address +#CHECK: srlg %r0,%r0,0(%r0) +#CHECK: error: invalid use of indexed addressing +#CHECK: srlg %r0,%r0,0(%r1,%r2) + + srlg %r0,%r0,-524289 + srlg %r0,%r0,524288 + srlg %r0,%r0,0(%r0) + srlg %r0,%r0,0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-st-01.s b/test/MC/SystemZ/insn-st-01.s new file mode 100644 index 000000000000..0b5fdb682c68 --- /dev/null +++ b/test/MC/SystemZ/insn-st-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: st %r0, 0 # encoding: [0x50,0x00,0x00,0x00] +#CHECK: st %r0, 4095 # encoding: [0x50,0x00,0x0f,0xff] +#CHECK: st %r0, 0(%r1) # encoding: [0x50,0x00,0x10,0x00] +#CHECK: st %r0, 0(%r15) # encoding: [0x50,0x00,0xf0,0x00] +#CHECK: st %r0, 4095(%r1,%r15) # encoding: [0x50,0x01,0xff,0xff] +#CHECK: st %r0, 4095(%r15,%r1) # encoding: [0x50,0x0f,0x1f,0xff] +#CHECK: st %r15, 0 # encoding: [0x50,0xf0,0x00,0x00] + + st %r0, 0 + st %r0, 4095 + st %r0, 0(%r1) + st %r0, 0(%r15) + st %r0, 4095(%r1,%r15) + st %r0, 4095(%r15,%r1) + st %r15, 0 diff --git a/test/MC/SystemZ/insn-st-02.s b/test/MC/SystemZ/insn-st-02.s new file mode 100644 index 000000000000..63e547a92bc4 --- /dev/null +++ b/test/MC/SystemZ/insn-st-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: st %r0, -1 +#CHECK: error: invalid operand +#CHECK: st %r0, 4096 + + st %r0, -1 + st %r0, 4096 diff --git a/test/MC/SystemZ/insn-stc-01.s b/test/MC/SystemZ/insn-stc-01.s new file mode 100644 index 000000000000..563f8914b643 --- /dev/null +++ b/test/MC/SystemZ/insn-stc-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stc %r0, 0 # encoding: [0x42,0x00,0x00,0x00] +#CHECK: stc %r0, 4095 # encoding: [0x42,0x00,0x0f,0xff] +#CHECK: stc %r0, 0(%r1) # encoding: [0x42,0x00,0x10,0x00] +#CHECK: stc %r0, 0(%r15) # encoding: [0x42,0x00,0xf0,0x00] +#CHECK: stc %r0, 4095(%r1,%r15) # encoding: [0x42,0x01,0xff,0xff] +#CHECK: stc %r0, 4095(%r15,%r1) # encoding: [0x42,0x0f,0x1f,0xff] +#CHECK: stc %r15, 0 # encoding: [0x42,0xf0,0x00,0x00] + + stc %r0, 0 + stc %r0, 4095 + stc %r0, 0(%r1) + stc %r0, 0(%r15) + stc %r0, 4095(%r1,%r15) + stc %r0, 4095(%r15,%r1) + stc %r15, 0 diff --git a/test/MC/SystemZ/insn-stc-02.s b/test/MC/SystemZ/insn-stc-02.s new file mode 100644 index 000000000000..aa7dcb29df6f --- /dev/null +++ b/test/MC/SystemZ/insn-stc-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stc %r0, -1 +#CHECK: error: invalid operand +#CHECK: stc %r0, 4096 + + stc %r0, -1 + stc %r0, 4096 diff --git a/test/MC/SystemZ/insn-stcy-01.s b/test/MC/SystemZ/insn-stcy-01.s new file mode 100644 index 000000000000..acc7ac5996e2 --- /dev/null +++ b/test/MC/SystemZ/insn-stcy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stcy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x72] +#CHECK: stcy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x72] +#CHECK: stcy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x72] +#CHECK: stcy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x72] +#CHECK: stcy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x72] +#CHECK: stcy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x72] +#CHECK: stcy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x72] +#CHECK: stcy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x72] +#CHECK: stcy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x72] +#CHECK: stcy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x72] + + stcy %r0, -524288 + stcy %r0, -1 + stcy %r0, 0 + stcy %r0, 1 + stcy %r0, 524287 + stcy %r0, 0(%r1) + stcy %r0, 0(%r15) + stcy %r0, 524287(%r1,%r15) + stcy %r0, 524287(%r15,%r1) + stcy %r15, 0 diff --git a/test/MC/SystemZ/insn-stcy-02.s b/test/MC/SystemZ/insn-stcy-02.s new file mode 100644 index 000000000000..cbd7f7abdec9 --- /dev/null +++ b/test/MC/SystemZ/insn-stcy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stcy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: stcy %r0, 524288 + + stcy %r0, -524289 + stcy %r0, 524288 diff --git a/test/MC/SystemZ/insn-std-01.s b/test/MC/SystemZ/insn-std-01.s new file mode 100644 index 000000000000..6867df8bb167 --- /dev/null +++ b/test/MC/SystemZ/insn-std-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: std %f0, 0 # encoding: [0x60,0x00,0x00,0x00] +#CHECK: std %f0, 4095 # encoding: [0x60,0x00,0x0f,0xff] +#CHECK: std %f0, 0(%r1) # encoding: [0x60,0x00,0x10,0x00] +#CHECK: std %f0, 0(%r15) # encoding: [0x60,0x00,0xf0,0x00] +#CHECK: std %f0, 4095(%r1,%r15) # encoding: [0x60,0x01,0xff,0xff] +#CHECK: std %f0, 4095(%r15,%r1) # encoding: [0x60,0x0f,0x1f,0xff] +#CHECK: std %f15, 0 # encoding: [0x60,0xf0,0x00,0x00] + + std %f0, 0 + std %f0, 4095 + std %f0, 0(%r1) + std %f0, 0(%r15) + std %f0, 4095(%r1,%r15) + std %f0, 4095(%r15,%r1) + std %f15, 0 diff --git a/test/MC/SystemZ/insn-std-02.s b/test/MC/SystemZ/insn-std-02.s new file mode 100644 index 000000000000..62bb9eb7fac4 --- /dev/null +++ b/test/MC/SystemZ/insn-std-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: std %f0, -1 +#CHECK: error: invalid operand +#CHECK: std %f0, 4096 + + std %f0, -1 + std %f0, 4096 diff --git a/test/MC/SystemZ/insn-stdy-01.s b/test/MC/SystemZ/insn-stdy-01.s new file mode 100644 index 000000000000..1ae9a7d3d01b --- /dev/null +++ b/test/MC/SystemZ/insn-stdy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stdy %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x67] +#CHECK: stdy %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x67] +#CHECK: stdy %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x67] +#CHECK: stdy %f0, 1 # encoding: [0xed,0x00,0x00,0x01,0x00,0x67] +#CHECK: stdy %f0, 524287 # encoding: [0xed,0x00,0x0f,0xff,0x7f,0x67] +#CHECK: stdy %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x67] +#CHECK: stdy %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x67] +#CHECK: stdy %f0, 524287(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x7f,0x67] +#CHECK: stdy %f0, 524287(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x7f,0x67] +#CHECK: stdy %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x67] + + stdy %f0, -524288 + stdy %f0, -1 + stdy %f0, 0 + stdy %f0, 1 + stdy %f0, 524287 + stdy %f0, 0(%r1) + stdy %f0, 0(%r15) + stdy %f0, 524287(%r1,%r15) + stdy %f0, 524287(%r15,%r1) + stdy %f15, 0 diff --git a/test/MC/SystemZ/insn-stdy-02.s b/test/MC/SystemZ/insn-stdy-02.s new file mode 100644 index 000000000000..f9a09a59f1c8 --- /dev/null +++ b/test/MC/SystemZ/insn-stdy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stdy %f0, -524289 +#CHECK: error: invalid operand +#CHECK: stdy %f0, 524288 + + stdy %f0, -524289 + stdy %f0, 524288 diff --git a/test/MC/SystemZ/insn-ste-01.s b/test/MC/SystemZ/insn-ste-01.s new file mode 100644 index 000000000000..8e245df98579 --- /dev/null +++ b/test/MC/SystemZ/insn-ste-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ste %f0, 0 # encoding: [0x70,0x00,0x00,0x00] +#CHECK: ste %f0, 4095 # encoding: [0x70,0x00,0x0f,0xff] +#CHECK: ste %f0, 0(%r1) # encoding: [0x70,0x00,0x10,0x00] +#CHECK: ste %f0, 0(%r15) # encoding: [0x70,0x00,0xf0,0x00] +#CHECK: ste %f0, 4095(%r1,%r15) # encoding: [0x70,0x01,0xff,0xff] +#CHECK: ste %f0, 4095(%r15,%r1) # encoding: [0x70,0x0f,0x1f,0xff] +#CHECK: ste %f15, 0 # encoding: [0x70,0xf0,0x00,0x00] + + ste %f0, 0 + ste %f0, 4095 + ste %f0, 0(%r1) + ste %f0, 0(%r15) + ste %f0, 4095(%r1,%r15) + ste %f0, 4095(%r15,%r1) + ste %f15, 0 diff --git a/test/MC/SystemZ/insn-ste-02.s b/test/MC/SystemZ/insn-ste-02.s new file mode 100644 index 000000000000..acc50eada847 --- /dev/null +++ b/test/MC/SystemZ/insn-ste-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: ste %f0, -1 +#CHECK: error: invalid operand +#CHECK: ste %f0, 4096 + + ste %f0, -1 + ste %f0, 4096 diff --git a/test/MC/SystemZ/insn-stey-01.s b/test/MC/SystemZ/insn-stey-01.s new file mode 100644 index 000000000000..1f8259365086 --- /dev/null +++ b/test/MC/SystemZ/insn-stey-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stey %f0, -524288 # encoding: [0xed,0x00,0x00,0x00,0x80,0x66] +#CHECK: stey %f0, -1 # encoding: [0xed,0x00,0x0f,0xff,0xff,0x66] +#CHECK: stey %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x66] +#CHECK: stey %f0, 1 # encoding: [0xed,0x00,0x00,0x01,0x00,0x66] +#CHECK: stey %f0, 524287 # encoding: [0xed,0x00,0x0f,0xff,0x7f,0x66] +#CHECK: stey %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x66] +#CHECK: stey %f0, 0(%r15) # encoding: [0xed,0x00,0xf0,0x00,0x00,0x66] +#CHECK: stey %f0, 524287(%r1,%r15) # encoding: [0xed,0x01,0xff,0xff,0x7f,0x66] +#CHECK: stey %f0, 524287(%r15,%r1) # encoding: [0xed,0x0f,0x1f,0xff,0x7f,0x66] +#CHECK: stey %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x66] + + stey %f0, -524288 + stey %f0, -1 + stey %f0, 0 + stey %f0, 1 + stey %f0, 524287 + stey %f0, 0(%r1) + stey %f0, 0(%r15) + stey %f0, 524287(%r1,%r15) + stey %f0, 524287(%r15,%r1) + stey %f15, 0 diff --git a/test/MC/SystemZ/insn-stey-02.s b/test/MC/SystemZ/insn-stey-02.s new file mode 100644 index 000000000000..203b016e314a --- /dev/null +++ b/test/MC/SystemZ/insn-stey-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stey %f0, -524289 +#CHECK: error: invalid operand +#CHECK: stey %f0, 524288 + + stey %f0, -524289 + stey %f0, 524288 diff --git a/test/MC/SystemZ/insn-stg-01.s b/test/MC/SystemZ/insn-stg-01.s new file mode 100644 index 000000000000..e8508d9f4e53 --- /dev/null +++ b/test/MC/SystemZ/insn-stg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x24] +#CHECK: stg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x24] +#CHECK: stg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x24] +#CHECK: stg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x24] +#CHECK: stg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x24] +#CHECK: stg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x24] +#CHECK: stg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x24] +#CHECK: stg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x24] +#CHECK: stg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x24] +#CHECK: stg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x24] + + stg %r0, -524288 + stg %r0, -1 + stg %r0, 0 + stg %r0, 1 + stg %r0, 524287 + stg %r0, 0(%r1) + stg %r0, 0(%r15) + stg %r0, 524287(%r1,%r15) + stg %r0, 524287(%r15,%r1) + stg %r15, 0 diff --git a/test/MC/SystemZ/insn-stg-02.s b/test/MC/SystemZ/insn-stg-02.s new file mode 100644 index 000000000000..1214ad1998c5 --- /dev/null +++ b/test/MC/SystemZ/insn-stg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: stg %r0, 524288 + + stg %r0, -524289 + stg %r0, 524288 diff --git a/test/MC/SystemZ/insn-stgrl-01.s b/test/MC/SystemZ/insn-stgrl-01.s new file mode 100644 index 000000000000..729b01dc115b --- /dev/null +++ b/test/MC/SystemZ/insn-stgrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stgrl %r0, 2864434397 # encoding: [0xc4,0x0b,0x55,0x5d,0xe6,0x6e] +#CHECK: stgrl %r15, 2864434397 # encoding: [0xc4,0xfb,0x55,0x5d,0xe6,0x6e] + + stgrl %r0,0xaabbccdd + stgrl %r15,0xaabbccdd + +#CHECK: stgrl %r0, foo # encoding: [0xc4,0x0b,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: stgrl %r15, foo # encoding: [0xc4,0xfb,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + stgrl %r0,foo + stgrl %r15,foo + +#CHECK: stgrl %r3, bar+100 # encoding: [0xc4,0x3b,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: stgrl %r4, bar+100 # encoding: [0xc4,0x4b,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + stgrl %r3,bar+100 + stgrl %r4,bar+100 + +#CHECK: stgrl %r7, frob@PLT # encoding: [0xc4,0x7b,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: stgrl %r8, frob@PLT # encoding: [0xc4,0x8b,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + stgrl %r7,frob@PLT + stgrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-sth-01.s b/test/MC/SystemZ/insn-sth-01.s new file mode 100644 index 000000000000..0dabe345b59e --- /dev/null +++ b/test/MC/SystemZ/insn-sth-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sth %r0, 0 # encoding: [0x40,0x00,0x00,0x00] +#CHECK: sth %r0, 4095 # encoding: [0x40,0x00,0x0f,0xff] +#CHECK: sth %r0, 0(%r1) # encoding: [0x40,0x00,0x10,0x00] +#CHECK: sth %r0, 0(%r15) # encoding: [0x40,0x00,0xf0,0x00] +#CHECK: sth %r0, 4095(%r1,%r15) # encoding: [0x40,0x01,0xff,0xff] +#CHECK: sth %r0, 4095(%r15,%r1) # encoding: [0x40,0x0f,0x1f,0xff] +#CHECK: sth %r15, 0 # encoding: [0x40,0xf0,0x00,0x00] + + sth %r0, 0 + sth %r0, 4095 + sth %r0, 0(%r1) + sth %r0, 0(%r15) + sth %r0, 4095(%r1,%r15) + sth %r0, 4095(%r15,%r1) + sth %r15, 0 diff --git a/test/MC/SystemZ/insn-sth-02.s b/test/MC/SystemZ/insn-sth-02.s new file mode 100644 index 000000000000..e73c28917b0a --- /dev/null +++ b/test/MC/SystemZ/insn-sth-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sth %r0, -1 +#CHECK: error: invalid operand +#CHECK: sth %r0, 4096 + + sth %r0, -1 + sth %r0, 4096 diff --git a/test/MC/SystemZ/insn-sthrl-01.s b/test/MC/SystemZ/insn-sthrl-01.s new file mode 100644 index 000000000000..0bcdbd4bc8f9 --- /dev/null +++ b/test/MC/SystemZ/insn-sthrl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sthrl %r0, 2864434397 # encoding: [0xc4,0x07,0x55,0x5d,0xe6,0x6e] +#CHECK: sthrl %r15, 2864434397 # encoding: [0xc4,0xf7,0x55,0x5d,0xe6,0x6e] + + sthrl %r0,0xaabbccdd + sthrl %r15,0xaabbccdd + +#CHECK: sthrl %r0, foo # encoding: [0xc4,0x07,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: sthrl %r15, foo # encoding: [0xc4,0xf7,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + sthrl %r0,foo + sthrl %r15,foo + +#CHECK: sthrl %r3, bar+100 # encoding: [0xc4,0x37,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: sthrl %r4, bar+100 # encoding: [0xc4,0x47,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + sthrl %r3,bar+100 + sthrl %r4,bar+100 + +#CHECK: sthrl %r7, frob@PLT # encoding: [0xc4,0x77,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: sthrl %r8, frob@PLT # encoding: [0xc4,0x87,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + sthrl %r7,frob@PLT + sthrl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-sthy-01.s b/test/MC/SystemZ/insn-sthy-01.s new file mode 100644 index 000000000000..259c5e1c82f5 --- /dev/null +++ b/test/MC/SystemZ/insn-sthy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sthy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x70] +#CHECK: sthy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x70] +#CHECK: sthy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x70] +#CHECK: sthy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x70] +#CHECK: sthy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x70] +#CHECK: sthy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x70] +#CHECK: sthy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x70] +#CHECK: sthy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x70] +#CHECK: sthy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x70] +#CHECK: sthy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x70] + + sthy %r0, -524288 + sthy %r0, -1 + sthy %r0, 0 + sthy %r0, 1 + sthy %r0, 524287 + sthy %r0, 0(%r1) + sthy %r0, 0(%r15) + sthy %r0, 524287(%r1,%r15) + sthy %r0, 524287(%r15,%r1) + sthy %r15, 0 diff --git a/test/MC/SystemZ/insn-sthy-02.s b/test/MC/SystemZ/insn-sthy-02.s new file mode 100644 index 000000000000..0ad547b4b813 --- /dev/null +++ b/test/MC/SystemZ/insn-sthy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sthy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sthy %r0, 524288 + + sthy %r0, -524289 + sthy %r0, 524288 diff --git a/test/MC/SystemZ/insn-stmg-01.s b/test/MC/SystemZ/insn-stmg-01.s new file mode 100644 index 000000000000..d1890144227c --- /dev/null +++ b/test/MC/SystemZ/insn-stmg-01.s @@ -0,0 +1,29 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24] +#CHECK: stmg %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x24] +#CHECK: stmg %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x24] +#CHECK: stmg %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x24] +#CHECK: stmg %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x24] +#CHECK: stmg %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x24] +#CHECK: stmg %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x24] +#CHECK: stmg %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x24] +#CHECK: stmg %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x24] +#CHECK: stmg %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x24] +#CHECK: stmg %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x24] +#CHECK: stmg %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x24] +#CHECK: stmg %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x24] + + stmg %r0,%r0,0 + stmg %r0,%r15,0 + stmg %r14,%r15,0 + stmg %r15,%r15,0 + stmg %r0,%r0,-524288 + stmg %r0,%r0,-1 + stmg %r0,%r0,0 + stmg %r0,%r0,1 + stmg %r0,%r0,524287 + stmg %r0,%r0,0(%r1) + stmg %r0,%r0,0(%r15) + stmg %r0,%r0,524287(%r1) + stmg %r0,%r0,524287(%r15) diff --git a/test/MC/SystemZ/insn-stmg-02.s b/test/MC/SystemZ/insn-stmg-02.s new file mode 100644 index 000000000000..342c38aec99f --- /dev/null +++ b/test/MC/SystemZ/insn-stmg-02.s @@ -0,0 +1,13 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: stmg %r0, %r0, -524289 +#CHECK: error: invalid operand +#CHECK: stmg %r0, %r0, 524288 +#CHECK: error: invalid use of indexed addressing +#CHECK: stmg %r0, %r0, 0(%r1,%r2) + + stmg %r0, %r0, -524289 + stmg %r0, %r0, 524288 + stmg %r0, %r0, 0(%r1,%r2) diff --git a/test/MC/SystemZ/insn-strl-01.s b/test/MC/SystemZ/insn-strl-01.s new file mode 100644 index 000000000000..84bd41f4c0c1 --- /dev/null +++ b/test/MC/SystemZ/insn-strl-01.s @@ -0,0 +1,31 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: strl %r0, 2864434397 # encoding: [0xc4,0x0f,0x55,0x5d,0xe6,0x6e] +#CHECK: strl %r15, 2864434397 # encoding: [0xc4,0xff,0x55,0x5d,0xe6,0x6e] + + strl %r0,0xaabbccdd + strl %r15,0xaabbccdd + +#CHECK: strl %r0, foo # encoding: [0xc4,0x0f,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL +#CHECK: strl %r15, foo # encoding: [0xc4,0xff,A,A,A,A] +# fixup A - offset: 2, value: foo+2, kind: FK_390_PC32DBL + + strl %r0,foo + strl %r15,foo + +#CHECK: strl %r3, bar+100 # encoding: [0xc4,0x3f,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL +#CHECK: strl %r4, bar+100 # encoding: [0xc4,0x4f,A,A,A,A] +# fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC32DBL + + strl %r3,bar+100 + strl %r4,bar+100 + +#CHECK: strl %r7, frob@PLT # encoding: [0xc4,0x7f,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL +#CHECK: strl %r8, frob@PLT # encoding: [0xc4,0x8f,A,A,A,A] +# fixup A - offset: 2, value: frob@PLT+2, kind: FK_390_PC32DBL + + strl %r7,frob@PLT + strl %r8,frob@PLT diff --git a/test/MC/SystemZ/insn-strv-01.s b/test/MC/SystemZ/insn-strv-01.s new file mode 100644 index 000000000000..6a818a8b9eaf --- /dev/null +++ b/test/MC/SystemZ/insn-strv-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: strv %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x3e] +#CHECK: strv %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x3e] +#CHECK: strv %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x3e] +#CHECK: strv %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x3e] +#CHECK: strv %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x3e] +#CHECK: strv %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x3e] +#CHECK: strv %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x3e] +#CHECK: strv %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x3e] +#CHECK: strv %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x3e] +#CHECK: strv %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x3e] + + strv %r0,-524288 + strv %r0,-1 + strv %r0,0 + strv %r0,1 + strv %r0,524287 + strv %r0,0(%r1) + strv %r0,0(%r15) + strv %r0,524287(%r1,%r15) + strv %r0,524287(%r15,%r1) + strv %r15,0 diff --git a/test/MC/SystemZ/insn-strv-02.s b/test/MC/SystemZ/insn-strv-02.s new file mode 100644 index 000000000000..24460edfed35 --- /dev/null +++ b/test/MC/SystemZ/insn-strv-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: strv %r0, -524289 +#CHECK: error: invalid operand +#CHECK: strv %r0, 524288 + + strv %r0, -524289 + strv %r0, 524288 diff --git a/test/MC/SystemZ/insn-strvg-01.s b/test/MC/SystemZ/insn-strvg-01.s new file mode 100644 index 000000000000..6a4d49d3bcc5 --- /dev/null +++ b/test/MC/SystemZ/insn-strvg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: strvg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x2f] +#CHECK: strvg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x2f] +#CHECK: strvg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x2f] +#CHECK: strvg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x2f] +#CHECK: strvg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x2f] +#CHECK: strvg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x2f] +#CHECK: strvg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x2f] +#CHECK: strvg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x2f] +#CHECK: strvg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x2f] +#CHECK: strvg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x2f] + + strvg %r0,-524288 + strvg %r0,-1 + strvg %r0,0 + strvg %r0,1 + strvg %r0,524287 + strvg %r0,0(%r1) + strvg %r0,0(%r15) + strvg %r0,524287(%r1,%r15) + strvg %r0,524287(%r15,%r1) + strvg %r15,0 diff --git a/test/MC/SystemZ/insn-strvg-02.s b/test/MC/SystemZ/insn-strvg-02.s new file mode 100644 index 000000000000..ebb0d5bffba3 --- /dev/null +++ b/test/MC/SystemZ/insn-strvg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: strvg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: strvg %r0, 524288 + + strvg %r0, -524289 + strvg %r0, 524288 diff --git a/test/MC/SystemZ/insn-sty-01.s b/test/MC/SystemZ/insn-sty-01.s new file mode 100644 index 000000000000..1ca2d5c55027 --- /dev/null +++ b/test/MC/SystemZ/insn-sty-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sty %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x50] +#CHECK: sty %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x50] +#CHECK: sty %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x50] +#CHECK: sty %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x50] +#CHECK: sty %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x50] +#CHECK: sty %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x50] +#CHECK: sty %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x50] +#CHECK: sty %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x50] +#CHECK: sty %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x50] +#CHECK: sty %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x50] + + sty %r0, -524288 + sty %r0, -1 + sty %r0, 0 + sty %r0, 1 + sty %r0, 524287 + sty %r0, 0(%r1) + sty %r0, 0(%r15) + sty %r0, 524287(%r1,%r15) + sty %r0, 524287(%r15,%r1) + sty %r15, 0 diff --git a/test/MC/SystemZ/insn-sty-02.s b/test/MC/SystemZ/insn-sty-02.s new file mode 100644 index 000000000000..fea7c089ab94 --- /dev/null +++ b/test/MC/SystemZ/insn-sty-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sty %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sty %r0, 524288 + + sty %r0, -524289 + sty %r0, 524288 diff --git a/test/MC/SystemZ/insn-sxbr-01.s b/test/MC/SystemZ/insn-sxbr-01.s new file mode 100644 index 000000000000..e7f4ed25bf46 --- /dev/null +++ b/test/MC/SystemZ/insn-sxbr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sxbr %f0, %f0 # encoding: [0xb3,0x4b,0x00,0x00] +#CHECK: sxbr %f0, %f13 # encoding: [0xb3,0x4b,0x00,0x0d] +#CHECK: sxbr %f8, %f8 # encoding: [0xb3,0x4b,0x00,0x88] +#CHECK: sxbr %f13, %f0 # encoding: [0xb3,0x4b,0x00,0xd0] + + sxbr %f0, %f0 + sxbr %f0, %f13 + sxbr %f8, %f8 + sxbr %f13, %f0 diff --git a/test/MC/SystemZ/insn-sxbr-02.s b/test/MC/SystemZ/insn-sxbr-02.s new file mode 100644 index 000000000000..397238bd3926 --- /dev/null +++ b/test/MC/SystemZ/insn-sxbr-02.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: sxbr %f0, %f2 +#CHECK: error: invalid register +#CHECK: sxbr %f0, %f14 +#CHECK: error: invalid register +#CHECK: sxbr %f2, %f0 +#CHECK: error: invalid register +#CHECK: sxbr %f14, %f0 + + sxbr %f0, %f2 + sxbr %f0, %f14 + sxbr %f2, %f0 + sxbr %f14, %f0 + diff --git a/test/MC/SystemZ/insn-sy-01.s b/test/MC/SystemZ/insn-sy-01.s new file mode 100644 index 000000000000..bc56bd790ecc --- /dev/null +++ b/test/MC/SystemZ/insn-sy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: sy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x5b] +#CHECK: sy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x5b] +#CHECK: sy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x5b] +#CHECK: sy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x5b] +#CHECK: sy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x5b] +#CHECK: sy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x5b] +#CHECK: sy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x5b] +#CHECK: sy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x5b] +#CHECK: sy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x5b] +#CHECK: sy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x5b] + + sy %r0, -524288 + sy %r0, -1 + sy %r0, 0 + sy %r0, 1 + sy %r0, 524287 + sy %r0, 0(%r1) + sy %r0, 0(%r15) + sy %r0, 524287(%r1,%r15) + sy %r0, 524287(%r15,%r1) + sy %r15, 0 diff --git a/test/MC/SystemZ/insn-sy-02.s b/test/MC/SystemZ/insn-sy-02.s new file mode 100644 index 000000000000..7d64ca922d12 --- /dev/null +++ b/test/MC/SystemZ/insn-sy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: sy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sy %r0, 524288 + + sy %r0, -524289 + sy %r0, 524288 diff --git a/test/MC/SystemZ/insn-x-01.s b/test/MC/SystemZ/insn-x-01.s new file mode 100644 index 000000000000..a2e3a2605a28 --- /dev/null +++ b/test/MC/SystemZ/insn-x-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: x %r0, 0 # encoding: [0x57,0x00,0x00,0x00] +#CHECK: x %r0, 4095 # encoding: [0x57,0x00,0x0f,0xff] +#CHECK: x %r0, 0(%r1) # encoding: [0x57,0x00,0x10,0x00] +#CHECK: x %r0, 0(%r15) # encoding: [0x57,0x00,0xf0,0x00] +#CHECK: x %r0, 4095(%r1,%r15) # encoding: [0x57,0x01,0xff,0xff] +#CHECK: x %r0, 4095(%r15,%r1) # encoding: [0x57,0x0f,0x1f,0xff] +#CHECK: x %r15, 0 # encoding: [0x57,0xf0,0x00,0x00] + + x %r0, 0 + x %r0, 4095 + x %r0, 0(%r1) + x %r0, 0(%r15) + x %r0, 4095(%r1,%r15) + x %r0, 4095(%r15,%r1) + x %r15, 0 diff --git a/test/MC/SystemZ/insn-x-02.s b/test/MC/SystemZ/insn-x-02.s new file mode 100644 index 000000000000..371974046416 --- /dev/null +++ b/test/MC/SystemZ/insn-x-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: x %r0, -1 +#CHECK: error: invalid operand +#CHECK: x %r0, 4096 + + x %r0, -1 + x %r0, 4096 diff --git a/test/MC/SystemZ/insn-xg-01.s b/test/MC/SystemZ/insn-xg-01.s new file mode 100644 index 000000000000..6cf5e7e4b48c --- /dev/null +++ b/test/MC/SystemZ/insn-xg-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x82] +#CHECK: xg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x82] +#CHECK: xg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x82] +#CHECK: xg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x82] +#CHECK: xg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x82] +#CHECK: xg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x82] +#CHECK: xg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x82] +#CHECK: xg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x82] +#CHECK: xg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x82] +#CHECK: xg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x82] + + xg %r0, -524288 + xg %r0, -1 + xg %r0, 0 + xg %r0, 1 + xg %r0, 524287 + xg %r0, 0(%r1) + xg %r0, 0(%r15) + xg %r0, 524287(%r1,%r15) + xg %r0, 524287(%r15,%r1) + xg %r15, 0 diff --git a/test/MC/SystemZ/insn-xg-02.s b/test/MC/SystemZ/insn-xg-02.s new file mode 100644 index 000000000000..0505b9facfe6 --- /dev/null +++ b/test/MC/SystemZ/insn-xg-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: xg %r0, 524288 + + xg %r0, -524289 + xg %r0, 524288 diff --git a/test/MC/SystemZ/insn-xgr-01.s b/test/MC/SystemZ/insn-xgr-01.s new file mode 100644 index 000000000000..1a5a6d6e1c6a --- /dev/null +++ b/test/MC/SystemZ/insn-xgr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xgr %r0, %r0 # encoding: [0xb9,0x82,0x00,0x00] +#CHECK: xgr %r0, %r15 # encoding: [0xb9,0x82,0x00,0x0f] +#CHECK: xgr %r15, %r0 # encoding: [0xb9,0x82,0x00,0xf0] +#CHECK: xgr %r7, %r8 # encoding: [0xb9,0x82,0x00,0x78] + + xgr %r0,%r0 + xgr %r0,%r15 + xgr %r15,%r0 + xgr %r7,%r8 diff --git a/test/MC/SystemZ/insn-xi-01.s b/test/MC/SystemZ/insn-xi-01.s new file mode 100644 index 000000000000..2a7670c732ca --- /dev/null +++ b/test/MC/SystemZ/insn-xi-01.s @@ -0,0 +1,17 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xi 0, 0 # encoding: [0x97,0x00,0x00,0x00] +#CHECK: xi 4095, 0 # encoding: [0x97,0x00,0x0f,0xff] +#CHECK: xi 0, 255 # encoding: [0x97,0xff,0x00,0x00] +#CHECK: xi 0(%r1), 42 # encoding: [0x97,0x2a,0x10,0x00] +#CHECK: xi 0(%r15), 42 # encoding: [0x97,0x2a,0xf0,0x00] +#CHECK: xi 4095(%r1), 42 # encoding: [0x97,0x2a,0x1f,0xff] +#CHECK: xi 4095(%r15), 42 # encoding: [0x97,0x2a,0xff,0xff] + + xi 0, 0 + xi 4095, 0 + xi 0, 255 + xi 0(%r1), 42 + xi 0(%r15), 42 + xi 4095(%r1), 42 + xi 4095(%r15), 42 diff --git a/test/MC/SystemZ/insn-xi-02.s b/test/MC/SystemZ/insn-xi-02.s new file mode 100644 index 000000000000..a1ce668a6931 --- /dev/null +++ b/test/MC/SystemZ/insn-xi-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xi -1, 0 +#CHECK: error: invalid operand +#CHECK: xi 4096, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: xi 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: xi 0, -1 +#CHECK: error: invalid operand +#CHECK: xi 0, 256 + + xi -1, 0 + xi 4096, 0 + xi 0(%r1,%r2), 0 + xi 0, -1 + xi 0, 256 diff --git a/test/MC/SystemZ/insn-xihf-01.s b/test/MC/SystemZ/insn-xihf-01.s new file mode 100644 index 000000000000..ad2ec1946a09 --- /dev/null +++ b/test/MC/SystemZ/insn-xihf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xihf %r0, 0 # encoding: [0xc0,0x06,0x00,0x00,0x00,0x00] +#CHECK: xihf %r0, 4294967295 # encoding: [0xc0,0x06,0xff,0xff,0xff,0xff] +#CHECK: xihf %r15, 0 # encoding: [0xc0,0xf6,0x00,0x00,0x00,0x00] + + xihf %r0, 0 + xihf %r0, 0xffffffff + xihf %r15, 0 diff --git a/test/MC/SystemZ/insn-xihf-02.s b/test/MC/SystemZ/insn-xihf-02.s new file mode 100644 index 000000000000..945993b82246 --- /dev/null +++ b/test/MC/SystemZ/insn-xihf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xihf %r0, -1 +#CHECK: error: invalid operand +#CHECK: xihf %r0, 1 << 32 + + xihf %r0, -1 + xihf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-xilf-01.s b/test/MC/SystemZ/insn-xilf-01.s new file mode 100644 index 000000000000..475e57332103 --- /dev/null +++ b/test/MC/SystemZ/insn-xilf-01.s @@ -0,0 +1,9 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xilf %r0, 0 # encoding: [0xc0,0x07,0x00,0x00,0x00,0x00] +#CHECK: xilf %r0, 4294967295 # encoding: [0xc0,0x07,0xff,0xff,0xff,0xff] +#CHECK: xilf %r15, 0 # encoding: [0xc0,0xf7,0x00,0x00,0x00,0x00] + + xilf %r0, 0 + xilf %r0, 0xffffffff + xilf %r15, 0 diff --git a/test/MC/SystemZ/insn-xilf-02.s b/test/MC/SystemZ/insn-xilf-02.s new file mode 100644 index 000000000000..df02b7cc9477 --- /dev/null +++ b/test/MC/SystemZ/insn-xilf-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xilf %r0, -1 +#CHECK: error: invalid operand +#CHECK: xilf %r0, 1 << 32 + + xilf %r0, -1 + xilf %r0, 1 << 32 diff --git a/test/MC/SystemZ/insn-xiy-01.s b/test/MC/SystemZ/insn-xiy-01.s new file mode 100644 index 000000000000..c329ce057260 --- /dev/null +++ b/test/MC/SystemZ/insn-xiy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xiy -524288, 0 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x57] +#CHECK: xiy -1, 0 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x57] +#CHECK: xiy 0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x57] +#CHECK: xiy 1, 0 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x57] +#CHECK: xiy 524287, 0 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x57] +#CHECK: xiy 0, 255 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x57] +#CHECK: xiy 0(%r1), 42 # encoding: [0xeb,0x2a,0x10,0x00,0x00,0x57] +#CHECK: xiy 0(%r15), 42 # encoding: [0xeb,0x2a,0xf0,0x00,0x00,0x57] +#CHECK: xiy 524287(%r1), 42 # encoding: [0xeb,0x2a,0x1f,0xff,0x7f,0x57] +#CHECK: xiy 524287(%r15), 42 # encoding: [0xeb,0x2a,0xff,0xff,0x7f,0x57] + + xiy -524288, 0 + xiy -1, 0 + xiy 0, 0 + xiy 1, 0 + xiy 524287, 0 + xiy 0, 255 + xiy 0(%r1), 42 + xiy 0(%r15), 42 + xiy 524287(%r1), 42 + xiy 524287(%r15), 42 diff --git a/test/MC/SystemZ/insn-xiy-02.s b/test/MC/SystemZ/insn-xiy-02.s new file mode 100644 index 000000000000..519c26c9659c --- /dev/null +++ b/test/MC/SystemZ/insn-xiy-02.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xiy -524289, 0 +#CHECK: error: invalid operand +#CHECK: xiy 524288, 0 +#CHECK: error: invalid use of indexed addressing +#CHECK: xiy 0(%r1,%r2), 0 +#CHECK: error: invalid operand +#CHECK: xiy 0, -1 +#CHECK: error: invalid operand +#CHECK: xiy 0, 256 + + xiy -524289, 0 + xiy 524288, 0 + xiy 0(%r1,%r2), 0 + xiy 0, -1 + xiy 0, 256 diff --git a/test/MC/SystemZ/insn-xr-01.s b/test/MC/SystemZ/insn-xr-01.s new file mode 100644 index 000000000000..471e6a63d6fa --- /dev/null +++ b/test/MC/SystemZ/insn-xr-01.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xr %r0, %r0 # encoding: [0x17,0x00] +#CHECK: xr %r0, %r15 # encoding: [0x17,0x0f] +#CHECK: xr %r15, %r0 # encoding: [0x17,0xf0] +#CHECK: xr %r7, %r8 # encoding: [0x17,0x78] + + xr %r0,%r0 + xr %r0,%r15 + xr %r15,%r0 + xr %r7,%r8 diff --git a/test/MC/SystemZ/insn-xy-01.s b/test/MC/SystemZ/insn-xy-01.s new file mode 100644 index 000000000000..132db04bf560 --- /dev/null +++ b/test/MC/SystemZ/insn-xy-01.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: xy %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x57] +#CHECK: xy %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x57] +#CHECK: xy %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x57] +#CHECK: xy %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x57] +#CHECK: xy %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x57] +#CHECK: xy %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x57] +#CHECK: xy %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x57] +#CHECK: xy %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x57] +#CHECK: xy %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x57] +#CHECK: xy %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x57] + + xy %r0, -524288 + xy %r0, -1 + xy %r0, 0 + xy %r0, 1 + xy %r0, 524287 + xy %r0, 0(%r1) + xy %r0, 0(%r15) + xy %r0, 524287(%r1,%r15) + xy %r0, 524287(%r15,%r1) + xy %r15, 0 diff --git a/test/MC/SystemZ/insn-xy-02.s b/test/MC/SystemZ/insn-xy-02.s new file mode 100644 index 000000000000..6ba3bad48c9b --- /dev/null +++ b/test/MC/SystemZ/insn-xy-02.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: xy %r0, -524289 +#CHECK: error: invalid operand +#CHECK: xy %r0, 524288 + + xy %r0, -524289 + xy %r0, 524288 diff --git a/test/MC/SystemZ/lit.local.cfg b/test/MC/SystemZ/lit.local.cfg new file mode 100644 index 000000000000..abb697406d6f --- /dev/null +++ b/test/MC/SystemZ/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp', '.s'] + +targets = set(config.root.targets_to_build.split()) +if not 'SystemZ' in targets: + config.unsupported = True + diff --git a/test/MC/SystemZ/regs-01.s b/test/MC/SystemZ/regs-01.s new file mode 100644 index 000000000000..df11fee691bc --- /dev/null +++ b/test/MC/SystemZ/regs-01.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lr %r0, %r1 # encoding: [0x18,0x01] +#CHECK: lr %r2, %r3 # encoding: [0x18,0x23] +#CHECK: lr %r4, %r5 # encoding: [0x18,0x45] +#CHECK: lr %r6, %r7 # encoding: [0x18,0x67] +#CHECK: lr %r8, %r9 # encoding: [0x18,0x89] +#CHECK: lr %r10, %r11 # encoding: [0x18,0xab] +#CHECK: lr %r12, %r13 # encoding: [0x18,0xcd] +#CHECK: lr %r14, %r15 # encoding: [0x18,0xef] + + lr %r0,%r1 + lr %r2,%r3 + lr %r4,%r5 + lr %r6,%r7 + lr %r8,%r9 + lr %r10,%r11 + lr %r12,%r13 + lr %r14,%r15 diff --git a/test/MC/SystemZ/regs-02.s b/test/MC/SystemZ/regs-02.s new file mode 100644 index 000000000000..baaa0f9f9781 --- /dev/null +++ b/test/MC/SystemZ/regs-02.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lgr %r0, %r1 # encoding: [0xb9,0x04,0x00,0x01] +#CHECK: lgr %r2, %r3 # encoding: [0xb9,0x04,0x00,0x23] +#CHECK: lgr %r4, %r5 # encoding: [0xb9,0x04,0x00,0x45] +#CHECK: lgr %r6, %r7 # encoding: [0xb9,0x04,0x00,0x67] +#CHECK: lgr %r8, %r9 # encoding: [0xb9,0x04,0x00,0x89] +#CHECK: lgr %r10, %r11 # encoding: [0xb9,0x04,0x00,0xab] +#CHECK: lgr %r12, %r13 # encoding: [0xb9,0x04,0x00,0xcd] +#CHECK: lgr %r14, %r15 # encoding: [0xb9,0x04,0x00,0xef] + + lgr %r0,%r1 + lgr %r2,%r3 + lgr %r4,%r5 + lgr %r6,%r7 + lgr %r8,%r9 + lgr %r10,%r11 + lgr %r12,%r13 + lgr %r14,%r15 diff --git a/test/MC/SystemZ/regs-03.s b/test/MC/SystemZ/regs-03.s new file mode 100644 index 000000000000..6ced4157b453 --- /dev/null +++ b/test/MC/SystemZ/regs-03.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: dlr %r0, %r0 # encoding: [0xb9,0x97,0x00,0x00] +#CHECK: dlr %r2, %r0 # encoding: [0xb9,0x97,0x00,0x20] +#CHECK: dlr %r4, %r0 # encoding: [0xb9,0x97,0x00,0x40] +#CHECK: dlr %r6, %r0 # encoding: [0xb9,0x97,0x00,0x60] +#CHECK: dlr %r8, %r0 # encoding: [0xb9,0x97,0x00,0x80] +#CHECK: dlr %r10, %r0 # encoding: [0xb9,0x97,0x00,0xa0] +#CHECK: dlr %r12, %r0 # encoding: [0xb9,0x97,0x00,0xc0] +#CHECK: dlr %r14, %r0 # encoding: [0xb9,0x97,0x00,0xe0] + + dlr %r0,%r0 + dlr %r2,%r0 + dlr %r4,%r0 + dlr %r6,%r0 + dlr %r8,%r0 + dlr %r10,%r0 + dlr %r12,%r0 + dlr %r14,%r0 diff --git a/test/MC/SystemZ/regs-04.s b/test/MC/SystemZ/regs-04.s new file mode 100644 index 000000000000..a2da67186f2b --- /dev/null +++ b/test/MC/SystemZ/regs-04.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ler %f0, %f1 # encoding: [0x38,0x01] +#CHECK: ler %f2, %f3 # encoding: [0x38,0x23] +#CHECK: ler %f4, %f5 # encoding: [0x38,0x45] +#CHECK: ler %f6, %f7 # encoding: [0x38,0x67] +#CHECK: ler %f8, %f9 # encoding: [0x38,0x89] +#CHECK: ler %f10, %f11 # encoding: [0x38,0xab] +#CHECK: ler %f12, %f13 # encoding: [0x38,0xcd] +#CHECK: ler %f14, %f15 # encoding: [0x38,0xef] + + ler %f0,%f1 + ler %f2,%f3 + ler %f4,%f5 + ler %f6,%f7 + ler %f8,%f9 + ler %f10,%f11 + ler %f12,%f13 + ler %f14,%f15 diff --git a/test/MC/SystemZ/regs-05.s b/test/MC/SystemZ/regs-05.s new file mode 100644 index 000000000000..b5f50b51a3ba --- /dev/null +++ b/test/MC/SystemZ/regs-05.s @@ -0,0 +1,19 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: ldr %f0, %f1 # encoding: [0x28,0x01] +#CHECK: ldr %f2, %f3 # encoding: [0x28,0x23] +#CHECK: ldr %f4, %f5 # encoding: [0x28,0x45] +#CHECK: ldr %f6, %f7 # encoding: [0x28,0x67] +#CHECK: ldr %f8, %f9 # encoding: [0x28,0x89] +#CHECK: ldr %f10, %f11 # encoding: [0x28,0xab] +#CHECK: ldr %f12, %f13 # encoding: [0x28,0xcd] +#CHECK: ldr %f14, %f15 # encoding: [0x28,0xef] + + ldr %f0,%f1 + ldr %f2,%f3 + ldr %f4,%f5 + ldr %f6,%f7 + ldr %f8,%f9 + ldr %f10,%f11 + ldr %f12,%f13 + ldr %f14,%f15 diff --git a/test/MC/SystemZ/regs-06.s b/test/MC/SystemZ/regs-06.s new file mode 100644 index 000000000000..43bf38c9c4b6 --- /dev/null +++ b/test/MC/SystemZ/regs-06.s @@ -0,0 +1,11 @@ +# RUN: llvm-mc -triple s390x-linux-gnu -show-encoding %s | FileCheck %s + +#CHECK: lxr %f0, %f1 # encoding: [0xb3,0x65,0x00,0x01] +#CHECK: lxr %f4, %f5 # encoding: [0xb3,0x65,0x00,0x45] +#CHECK: lxr %f8, %f9 # encoding: [0xb3,0x65,0x00,0x89] +#CHECK: lxr %f12, %f13 # encoding: [0xb3,0x65,0x00,0xcd] + + lxr %f0,%f1 + lxr %f4,%f5 + lxr %f8,%f9 + lxr %f12,%f13 diff --git a/test/MC/SystemZ/regs-07.s b/test/MC/SystemZ/regs-07.s new file mode 100644 index 000000000000..d3585a6e2ccb --- /dev/null +++ b/test/MC/SystemZ/regs-07.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lr %r16,%r1 +#CHECK: error: invalid register +#CHECK: lr %f0,%r1 +#CHECK: error: invalid register +#CHECK: lr %a0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lr %arid,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lr %0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lr 0,%r1 +#CHECK: error: unknown token in expression +#CHECK: lr (%r0),%r1 +#CHECK: error: unknown token in expression +#CHECK: lr %,%r1 + + lr %r16,%r1 + lr %f0,%r1 + lr %a0,%r1 + lr %arid,%r1 + lr %0,%r1 + lr 0,%r1 + lr (%r0),%r1 + lr %,%r1 diff --git a/test/MC/SystemZ/regs-08.s b/test/MC/SystemZ/regs-08.s new file mode 100644 index 000000000000..f11c45737a43 --- /dev/null +++ b/test/MC/SystemZ/regs-08.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lgr %r16,%r1 +#CHECK: error: invalid register +#CHECK: lgr %f0,%r1 +#CHECK: error: invalid register +#CHECK: lgr %a0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lgr %arid,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lgr %0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: lgr 0,%r1 +#CHECK: error: unknown token in expression +#CHECK: lgr (%r0),%r1 +#CHECK: error: unknown token in expression +#CHECK: lgr %,%r1 + + lgr %r16,%r1 + lgr %f0,%r1 + lgr %a0,%r1 + lgr %arid,%r1 + lgr %0,%r1 + lgr 0,%r1 + lgr (%r0),%r1 + lgr %,%r1 diff --git a/test/MC/SystemZ/regs-09.s b/test/MC/SystemZ/regs-09.s new file mode 100644 index 000000000000..60f4d3914030 --- /dev/null +++ b/test/MC/SystemZ/regs-09.s @@ -0,0 +1,31 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: dlr %r1,%r8 +#CHECK: error: invalid register +#CHECK: dlr %r16,%r1 +#CHECK: error: invalid register +#CHECK: dlr %f0,%r1 +#CHECK: error: invalid register +#CHECK: dlr %a0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: dlr %arid,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: dlr %0,%r1 +#CHECK: error: invalid operand for instruction +#CHECK: dlr 0,%r1 +#CHECK: error: unknown token in expression +#CHECK: dlr (%r0),%r1 +#CHECK: error: unknown token in expression +#CHECK: dlr %,%r1 + + dlr %r1,%r8 + dlr %r16,%r1 + dlr %f0,%r1 + dlr %a0,%r1 + dlr %arid,%r1 + dlr %0,%r1 + dlr 0,%r1 + dlr (%r0),%r1 + dlr %,%r1 diff --git a/test/MC/SystemZ/regs-10.s b/test/MC/SystemZ/regs-10.s new file mode 100644 index 000000000000..865aa82532ff --- /dev/null +++ b/test/MC/SystemZ/regs-10.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: ler %f1,%f16 +#CHECK: error: invalid register +#CHECK: ler %f1,%r0 +#CHECK: error: invalid register +#CHECK: ler %f1,%a0 +#CHECK: error: invalid operand for instruction +#CHECK: ler %f1,%fly +#CHECK: error: invalid operand for instruction +#CHECK: ler %f1,%0 +#CHECK: error: invalid operand for instruction +#CHECK: ler %f1,0 +#CHECK: error: unknown token in expression +#CHECK: ler %f1,(%f0) +#CHECK: error: unknown token in expression +#CHECK: ler %f1,% + + ler %f1,%f16 + ler %f1,%r0 + ler %f1,%a0 + ler %f1,%fly + ler %f1,%0 + ler %f1,0 + ler %f1,(%f0) + ler %f1,% diff --git a/test/MC/SystemZ/regs-11.s b/test/MC/SystemZ/regs-11.s new file mode 100644 index 000000000000..5d0f04f04343 --- /dev/null +++ b/test/MC/SystemZ/regs-11.s @@ -0,0 +1,28 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: ldr %f1,%f16 +#CHECK: error: invalid register +#CHECK: ldr %f1,%r0 +#CHECK: error: invalid register +#CHECK: ldr %f1,%a0 +#CHECK: error: invalid operand for instruction +#CHECK: ldr %f1,%fly +#CHECK: error: invalid operand for instruction +#CHECK: ldr %f1,%0 +#CHECK: error: invalid operand for instruction +#CHECK: ldr %f1,0 +#CHECK: error: unknown token in expression +#CHECK: ldr %f1,(%f0) +#CHECK: error: unknown token in expression +#CHECK: ldr %f1,% + + ldr %f1,%f16 + ldr %f1,%r0 + ldr %f1,%a0 + ldr %f1,%fly + ldr %f1,%0 + ldr %f1,0 + ldr %f1,(%f0) + ldr %f1,% diff --git a/test/MC/SystemZ/regs-12.s b/test/MC/SystemZ/regs-12.s new file mode 100644 index 000000000000..f6cf0e75844d --- /dev/null +++ b/test/MC/SystemZ/regs-12.s @@ -0,0 +1,31 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: lxr %f1,%f2 +#CHECK: error: invalid register +#CHECK: lxr %f1,%f16 +#CHECK: error: invalid register +#CHECK: lxr %f1,%r0 +#CHECK: error: invalid register +#CHECK: lxr %f1,%a0 +#CHECK: error: invalid operand for instruction +#CHECK: lxr %f1,%fly +#CHECK: error: invalid operand for instruction +#CHECK: lxr %f1,%0 +#CHECK: error: invalid operand for instruction +#CHECK: lxr %f1,0 +#CHECK: error: unknown token in expression +#CHECK: lxr %f1,(%f0) +#CHECK: error: unknown token in expression +#CHECK: lxr %f1,% + + lxr %f1,%f2 + lxr %f1,%f16 + lxr %f1,%r0 + lxr %f1,%a0 + lxr %f1,%fly + lxr %f1,%0 + lxr %f1,0 + lxr %f1,(%f0) + lxr %f1,% diff --git a/test/MC/SystemZ/regs-13.s b/test/MC/SystemZ/regs-13.s new file mode 100644 index 000000000000..88b0c05b86fb --- /dev/null +++ b/test/MC/SystemZ/regs-13.s @@ -0,0 +1,69 @@ +# RUN: llvm-mc -triple s390x-linux-gnu < %s | FileCheck %s + +#CHECK: .cfi_offset %r0, 0 +#CHECK: .cfi_offset %r1, 8 +#CHECK: .cfi_offset %r2, 16 +#CHECK: .cfi_offset %r3, 24 +#CHECK: .cfi_offset %r4, 32 +#CHECK: .cfi_offset %r5, 40 +#CHECK: .cfi_offset %r6, 48 +#CHECK: .cfi_offset %r7, 56 +#CHECK: .cfi_offset %r8, 64 +#CHECK: .cfi_offset %r9, 72 +#CHECK: .cfi_offset %r10, 80 +#CHECK: .cfi_offset %r11, 88 +#CHECK: .cfi_offset %r12, 96 +#CHECK: .cfi_offset %r13, 104 +#CHECK: .cfi_offset %r14, 112 +#CHECK: .cfi_offset %r15, 120 +#CHECK: .cfi_offset %f0, 128 +#CHECK: .cfi_offset %f1, 136 +#CHECK: .cfi_offset %f2, 144 +#CHECK: .cfi_offset %f3, 152 +#CHECK: .cfi_offset %f4, 160 +#CHECK: .cfi_offset %f5, 168 +#CHECK: .cfi_offset %f6, 176 +#CHECK: .cfi_offset %f7, 184 +#CHECK: .cfi_offset %f8, 192 +#CHECK: .cfi_offset %f9, 200 +#CHECK: .cfi_offset %f10, 208 +#CHECK: .cfi_offset %f11, 216 +#CHECK: .cfi_offset %f12, 224 +#CHECK: .cfi_offset %f13, 232 +#CHECK: .cfi_offset %f14, 240 +#CHECK: .cfi_offset %f15, 248 + + .cfi_startproc + .cfi_offset %r0,0 + .cfi_offset %r1,8 + .cfi_offset %r2,16 + .cfi_offset %r3,24 + .cfi_offset %r4,32 + .cfi_offset %r5,40 + .cfi_offset %r6,48 + .cfi_offset %r7,56 + .cfi_offset %r8,64 + .cfi_offset %r9,72 + .cfi_offset %r10,80 + .cfi_offset %r11,88 + .cfi_offset %r12,96 + .cfi_offset %r13,104 + .cfi_offset %r14,112 + .cfi_offset %r15,120 + .cfi_offset %f0,128 + .cfi_offset %f1,136 + .cfi_offset %f2,144 + .cfi_offset %f3,152 + .cfi_offset %f4,160 + .cfi_offset %f5,168 + .cfi_offset %f6,176 + .cfi_offset %f7,184 + .cfi_offset %f8,192 + .cfi_offset %f9,200 + .cfi_offset %f10,208 + .cfi_offset %f11,216 + .cfi_offset %f12,224 + .cfi_offset %f13,232 + .cfi_offset %f14,240 + .cfi_offset %f15,248 + .cfi_endproc diff --git a/test/MC/SystemZ/regs-14.s b/test/MC/SystemZ/regs-14.s new file mode 100644 index 000000000000..e22307d49ce1 --- /dev/null +++ b/test/MC/SystemZ/regs-14.s @@ -0,0 +1,18 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid register +#CHECK: .cfi_offset %a0,0 +#CHECK: error: register expected +#CHECK: .cfi_offset %foo,0 +#CHECK: error: register expected +#CHECK: .cfi_offset %,0 +#CHECK: error: register expected +#CHECK: .cfi_offset r0,0 + + .cfi_startproc + .cfi_offset %a0,0 + .cfi_offset %foo,0 + .cfi_offset %,0 + .cfi_offset r0,0 + .cfi_endproc diff --git a/test/MC/SystemZ/regs-15.s b/test/MC/SystemZ/regs-15.s new file mode 100644 index 000000000000..baec6a639bbf --- /dev/null +++ b/test/MC/SystemZ/regs-15.s @@ -0,0 +1,19 @@ +# RUN: not llvm-mc -triple s390x-linux-gnu < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: %r0 used in an address +#CHECK: sll %r2,8(%r0) +#CHECK: error: %r0 used in an address +#CHECK: br %r0 +#CHECK: error: %r0 used in an address +#CHECK: l %r1,8(%r0) +#CHECK: error: %r0 used in an address +#CHECK: l %r1,8(%r0,%r15) +#CHECK: error: %r0 used in an address +#CHECK: l %r1,8(%r15,%r0) + + sll %r2,8(%r0) + br %r0 + l %r1,8(%r0) + l %r1,8(%r0,%r15) + l %r1,8(%r15,%r0) diff --git a/test/MC/X86/intel-syntax.s b/test/MC/X86/intel-syntax.s index 8bfa58a4bed8..b2f337dac9d7 100644 --- a/test/MC/X86/intel-syntax.s +++ b/test/MC/X86/intel-syntax.s @@ -247,4 +247,79 @@ _main: mov [16][eax][ebx*4], ecx // CHECK: movl %ecx, -16(%eax,%ebx,4) mov [eax][ebx*4 - 16], ecx - ret + +// CHECK: prefetchnta 12800(%esi) + prefetchnta [esi + (200*64)] +// CHECK: prefetchnta 32(%esi) + prefetchnta [esi + (64/2)] +// CHECK: prefetchnta 128(%esi) + prefetchnta [esi + (64/2*4)] +// CHECK: prefetchnta 8(%esi) + prefetchnta [esi + (64/(2*4))] +// CHECK: prefetchnta 48(%esi) + prefetchnta [esi + (64/(2*4)+40)] + +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax][ebx*4 - 2*8], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax][4*ebx - 2*8], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax + 4*ebx - 2*8], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [12 + eax + (4*ebx) - 2*14], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax][ebx*4 - 2*2*2*2], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax][ebx*4 - (2*8)], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax][ebx*4 - 2 * 8 + 4 - 4], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax + ebx*4 - 2 * 8 + 4 - 4], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax + ebx*4 - 2 * ((8 + 4) - 4)], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [-2 * ((8 + 4) - 4) + eax + ebx*4], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [((-2) * ((8 + 4) - 4)) + eax + ebx*4], ecx +// CHECK: movl %ecx, -16(%eax,%ebx,4) + mov [eax + ((-2) * ((8 + 4) - 4)) + ebx*4], ecx +// CHECK: movl %ecx, 96(%eax,%ebx,4) + mov [eax + ((-2) * ((8 + 4) * -4)) + ebx*4], ecx +// CHECK: movl %ecx, -8(%eax,%ebx,4) + mov [eax][-8][ebx*4], ecx +// CHECK: movl %ecx, -2(%eax,%ebx,4) + mov [eax][16/-8][ebx*4], ecx +// CHECK: movl %ecx, -2(%eax,%ebx,4) + mov [eax][(16)/-8][ebx*4], ecx + +// CHECK: setb %al + setc al +// CHECK: sete %al + setz al +// CHECK: setbe %al + setna al +// CHECK: setae %al + setnb al +// CHECK: setae %al + setnc al +// CHECK: setle %al + setng al +// CHECK: setge %al + setnl al +// CHECK: setne %al + setnz al +// CHECK: setp %al + setpe al +// CHECK: setnp %al + setpo al +// CHECK: setb %al + setnae al +// CHECK: seta %al + setnbe al +// CHECK: setl %al + setnge al +// CHECK: setg %al + setnle al +// CHECK: jne _foo + jnz _foo + ret diff --git a/test/MC/X86/x86-64.s b/test/MC/X86/x86-64.s index c5f1d15f8ff0..521a0776d8af 100644 --- a/test/MC/X86/x86-64.s +++ b/test/MC/X86/x86-64.s @@ -1228,3 +1228,11 @@ sysexitl // CHECK: sysexitq // CHECK: encoding: [0x48,0x0f,0x35] sysexitq + +// CHECK: clac +// CHECK: encoding: [0x0f,0x01,0xca] +clac + +// CHECK: stac +// CHECK: encoding: [0x0f,0x01,0xcb] +stac diff --git a/test/Makefile b/test/Makefile index b47695100a9e..88573c552386 100644 --- a/test/Makefile +++ b/test/Makefile @@ -100,13 +100,6 @@ check-local-all:: lit.site.cfg Unit/lit.site.cfg extra-site-cfgs clean:: $(RM) -rf `find $(LLVM_OBJ_ROOT)/test -name Output -type d -print` -# dsymutil is used on the Darwin to manipulate DWARF debugging information. -ifeq ($(TARGET_OS),Darwin) -DSYMUTIL=dsymutil -else -DSYMUTIL=true -endif - ifneq ($(OCAMLOPT),) CC_FOR_OCAMLOPT := $(shell $(OCAMLOPT) -config | grep native_c_compiler | sed -e 's/native_c_compiler: //') CXX_FOR_OCAMLOPT := $(subst gcc,g++,$(CC_FOR_OCAMLOPT)) @@ -132,7 +125,7 @@ endif lit.site.cfg: FORCE @echo "Making LLVM 'lit.site.cfg' file..." - @$(ECHOPATH) s=@LLVM_HOSTTRIPLE@=$(HOST_TRIPLE)=g > lit.tmp + @$(ECHOPATH) s=@LLVM_HOST_TRIPLE@=$(HOST_TRIPLE)=g > lit.tmp @$(ECHOPATH) s=@TARGET_TRIPLE@=$(TARGET_TRIPLE)=g >> lit.tmp @$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g >> lit.tmp @$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> lit.tmp @@ -148,6 +141,7 @@ lit.site.cfg: FORCE @$(ECHOPATH) s=@LLVM_BINDINGS@=$(BINDINGS_TO_BUILD)=g >> lit.tmp @$(ECHOPATH) s=@HOST_OS@=$(HOST_OS)=g >> lit.tmp @$(ECHOPATH) s=@HOST_ARCH@=$(HOST_ARCH)=g >> lit.tmp + @$(ECHOPATH) s=@HAVE_LIBZ@=$(HAVE_LIBZ)=g >> lit.tmp @sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@ @-rm -f lit.tmp diff --git a/test/Makefile.tests b/test/Makefile.tests index aeb5871e7cdf..c60c90c075d2 100644 --- a/test/Makefile.tests +++ b/test/Makefile.tests @@ -38,7 +38,7 @@ LCCFLAGS += -O2 -Wall LCXXFLAGS += -O2 -Wall LLCFLAGS = TESTRUNR = @echo Running test: $<; \ - PATH="$(LLVMTOOLCURRENT):$(LLVM_SRC_ROOT)/test/Scripts:$(PATH)" \ + PATH="$(LLVMTOOLCURRENT):$(PATH)" \ $(LLVM_SRC_ROOT)/test/TestRunner.sh LLCLIBS := $(LLCLIBS) -lm diff --git a/test/Object/ARM/lit.local.cfg b/test/Object/ARM/lit.local.cfg new file mode 100644 index 000000000000..5fc35d80541d --- /dev/null +++ b/test/Object/ARM/lit.local.cfg @@ -0,0 +1,3 @@ +targets = set(config.root.targets_to_build.split()) +if not 'ARM' in targets: + config.unsupported = True diff --git a/test/Object/ARM/objdump-thumb.test b/test/Object/ARM/objdump-thumb.test new file mode 100644 index 000000000000..9c92a27782d4 --- /dev/null +++ b/test/Object/ARM/objdump-thumb.test @@ -0,0 +1,4 @@ +RUN: llvm-objdump -d -macho -triple=thumbv7-apple-ios \ +RUN: %p/../Inputs/macho-text.thumb | FileCheck %s + +CHECK: 0: 00 bf nop diff --git a/test/Object/Inputs/COFF/i386.yaml b/test/Object/Inputs/COFF/i386.yaml index aec7a5813cf9..f7631821c192 100644 --- a/test/Object/Inputs/COFF/i386.yaml +++ b/test/Object/Inputs/COFF/i386.yaml @@ -5,7 +5,8 @@ header: !Header sections: - !Section Name: .text - Characteristics: [IMAGE_SCN_CNT_CODE, IMAGE_SCN_ALIGN_16BYTES, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ, ] # 0x60500020 + Alignment: 16 + Characteristics: [IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ, ] # 0x60500020 SectionData: !hex "83EC0CC744240800000000C7042400000000E800000000E8000000008B44240883C40CC3" # |....D$.......$...............D$.....| Relocations: @@ -26,7 +27,8 @@ sections: - !Section Name: .data - Characteristics: [IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_ALIGN_1BYTES, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE, ] # 0xc0100040 + Alignment: 1 + Characteristics: [IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE, ] # 0xc0100040 SectionData: !hex "48656C6C6F20576F726C642100" # |Hello World!.| symbols: @@ -38,7 +40,7 @@ symbols: ComplexType: IMAGE_SYM_DTYPE_NULL # (0) StorageClass: IMAGE_SYM_CLASS_STATIC # (3) NumberOfAuxSymbols: 1 - AuxillaryData: !hex "240000000300000000000000010000000000" # |$.................| + AuxiliaryData: !hex "240000000300000000000000010000000000" # |$.................| - !Symbol Name: .data @@ -48,7 +50,7 @@ symbols: ComplexType: IMAGE_SYM_DTYPE_NULL # (0) StorageClass: IMAGE_SYM_CLASS_STATIC # (3) NumberOfAuxSymbols: 1 - AuxillaryData: !hex "0D0000000000000000000000020000000000" # |..................| + AuxiliaryData: !hex "0D0000000000000000000000020000000000" # |..................| - !Symbol Name: _main diff --git a/test/Object/Inputs/COFF/x86-64.yaml b/test/Object/Inputs/COFF/x86-64.yaml index 0b1265f6f5c2..5134071cda41 100644 --- a/test/Object/Inputs/COFF/x86-64.yaml +++ b/test/Object/Inputs/COFF/x86-64.yaml @@ -4,7 +4,8 @@ header: !Header sections: - !Section Name: .text - Characteristics: [IMAGE_SCN_CNT_CODE, IMAGE_SCN_ALIGN_16BYTES, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ, ] # 0x60500020 + Alignment: 16 + Characteristics: [IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ, ] # 0x60500020 SectionData: !hex "4883EC28C744242400000000488D0D00000000E800000000E8000000008B4424244883C428C3" # |H..(.D$$....H.................D$$H..(.| Relocations: @@ -25,7 +26,8 @@ sections: - !Section Name: .data - Characteristics: [IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_ALIGN_1BYTES, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE, ] # 0xc0100040 + Alignment: 1 + Characteristics: [IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE, ] # 0xc0100040 SectionData: !hex "48656C6C6F20576F726C642100" # |Hello World!.| symbols: @@ -37,7 +39,7 @@ symbols: ComplexType: IMAGE_SYM_DTYPE_NULL # (0) StorageClass: IMAGE_SYM_CLASS_STATIC # (3) NumberOfAuxSymbols: 1 - AuxillaryData: !hex "260000000300000000000000010000000000" # |&.................| + AuxiliaryData: !hex "260000000300000000000000010000000000" # |&.................| - !Symbol Name: .data @@ -47,7 +49,7 @@ symbols: ComplexType: IMAGE_SYM_DTYPE_NULL # (0) StorageClass: IMAGE_SYM_CLASS_STATIC # (3) NumberOfAuxSymbols: 1 - AuxillaryData: !hex "0D0000000000000000000000020000000000" # |..................| + AuxiliaryData: !hex "0D0000000000000000000000020000000000" # |..................| - !Symbol Name: main diff --git a/test/Object/Inputs/hello-world.elf-x86-64 b/test/Object/Inputs/hello-world.elf-x86-64 Binary files differnew file mode 100755 index 000000000000..16092b894721 --- /dev/null +++ b/test/Object/Inputs/hello-world.elf-x86-64 diff --git a/test/Object/Inputs/macho-text.thumb b/test/Object/Inputs/macho-text.thumb Binary files differnew file mode 100644 index 000000000000..b29428a78781 --- /dev/null +++ b/test/Object/Inputs/macho-text.thumb diff --git a/test/Object/lit.local.cfg b/test/Object/lit.local.cfg index df9b335dd131..b2439b2d1b79 100644 --- a/test/Object/lit.local.cfg +++ b/test/Object/lit.local.cfg @@ -1 +1 @@ -config.suffixes = ['.test'] +config.suffixes = ['.test', '.ll'] diff --git a/test/Object/nm-trivial-object.test b/test/Object/nm-trivial-object.test index 8fd1c0482de9..5c3cc315e543 100644 --- a/test/Object/nm-trivial-object.test +++ b/test/Object/nm-trivial-object.test @@ -1,7 +1,7 @@ RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-nm \ RUN: | FileCheck %s -check-prefix COFF RUN: yaml2obj %p/Inputs/COFF/x86-64.yaml | llvm-nm \ -RUN | FileCheck %s -check-prefix COFF +RUN: | FileCheck %s -check-prefix COFF RUN: llvm-nm %p/Inputs/trivial-object-test.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF RUN: llvm-nm %p/Inputs/trivial-object-test.elf-x86-64 \ diff --git a/test/Object/objdump-section-content.test b/test/Object/objdump-section-content.test index f9c4f43f0be0..e0199b329d18 100644 --- a/test/Object/objdump-section-content.test +++ b/test/Object/objdump-section-content.test @@ -1,6 +1,8 @@ RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-objdump -s - | FileCheck %s -check-prefix COFF-i386 RUN: llvm-objdump -s %p/Inputs/trivial-object-test.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF-i386 +RUN: llvm-objdump -s %p/Inputs/shared-object-test.elf-i386 \ +RUN: | FileCheck %s -check-prefix BSS COFF-i386: file format COFF-i386: Contents of section .text: @@ -17,3 +19,6 @@ ELF-i386: 0010 0000e8fc ffffffe8 fcffffff 8b442408 .............D$. ELF-i386: 0020 83c40cc3 .... ELF-i386: Contents of section .rodata.str1.1: ELF-i386: 0024 48656c6c 6f20576f 726c6421 00 Hello World!. + +BSS: Contents of section .bss: +BSS-NEXT: <skipping contents of bss section at [12c8, 12cc)> diff --git a/test/Object/relocation-executable.test b/test/Object/relocation-executable.test new file mode 100644 index 000000000000..98f5b4ee2fd6 --- /dev/null +++ b/test/Object/relocation-executable.test @@ -0,0 +1,18 @@ +RUN: llvm-readobj -r -expand-relocs %p/Inputs/hello-world.elf-x86-64 \ +RUN: | FileCheck %s + +// CHECK: Relocations [ +// CHECK: Section (11) .plt { +// CHECK-NEXT: Relocation { +// CHECK-NEXT: Offset: 0x4018F8 +// CHECK-NEXT: Type: R_X86_64_JUMP_SLOT (7) +// CHECK-NEXT: Symbol: __libc_start_main +// CHECK-NEXT: Info: 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: Relocation { +// CHECK-NEXT: Offset: 0x401900 +// CHECK-NEXT: Type: R_X86_64_JUMP_SLOT (7) +// CHECK-NEXT: Symbol: puts +// CHECK-NEXT: Info: 0x0 +// CHECK-NEXT: } +// CHECK-NEXT: } diff --git a/test/Object/yaml2obj-readobj.test b/test/Object/yaml2obj-readobj.test index 545ccc48aa4c..3031f5ed31bc 100644 --- a/test/Object/yaml2obj-readobj.test +++ b/test/Object/yaml2obj-readobj.test @@ -1,5 +1,25 @@ -RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-readobj -file-headers - | FileCheck %s --check-prefix COFF-I386 +RUN: yaml2obj %p/Inputs/COFF/i386.yaml | llvm-readobj -file-headers -relocations -expand-relocs - | FileCheck %s --check-prefix COFF-I386 // COFF-I386: Characteristics [ (0x200) // COFF-I386-NEXT: IMAGE_FILE_DEBUG_STRIPPED (0x200) // COFF-I386-NEXT: ] + +// COFF-I386: Relocations [ +// COFF-I386-NEXT: Section (1) .text { +// COFF-I386-NEXT: Relocation { +// COFF-I386-NEXT: Offset: 0xE +// COFF-I386-NEXT: Type: IMAGE_REL_I386_DIR32 (6) +// COFF-I386-NEXT: Symbol: L_.str +// COFF-I386-NEXT: } +// COFF-I386-NEXT: Relocation { +// COFF-I386-NEXT: Offset: 0x13 +// COFF-I386-NEXT: Type: IMAGE_REL_I386_REL32 (20) +// COFF-I386-NEXT: Symbol: _puts +// COFF-I386-NEXT: } +// COFF-I386-NEXT: Relocation { +// COFF-I386-NEXT: Offset: 0x18 +// COFF-I386-NEXT: Type: IMAGE_REL_I386_REL32 (20) +// COFF-I386-NEXT: Symbol: _SomeOtherFunction +// COFF-I386-NEXT: } +// COFF-I386-NEXT: } +// COFF-I386-NEXT: ] diff --git a/test/Other/attribute-comment.ll b/test/Other/attribute-comment.ll new file mode 100644 index 000000000000..7354e7f765fd --- /dev/null +++ b/test/Other/attribute-comment.ll @@ -0,0 +1,9 @@ +; RUN: opt -S < %s | FileCheck %s -strict-whitespace + +; CHECK: {{^}}; Function Attrs: nounwind readnone ssp uwtable{{$}} +; CHECK-NEXT: define void @test1() #0 +define void @test1() #0 { + ret void +} + +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" uwtable "no-frame-pointer-elim"="true" readnone "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/Scripts/README.txt b/test/Scripts/README.txt deleted file mode 100644 index b0b11050375f..000000000000 --- a/test/Scripts/README.txt +++ /dev/null @@ -1,2 +0,0 @@ -This directory contains scripts which are used by the TestRunner style -tests, which allows them to be simpler and more direct. diff --git a/test/Scripts/coff-dump.py b/test/Scripts/coff-dump.py deleted file mode 100755 index 36ec53932c63..000000000000 --- a/test/Scripts/coff-dump.py +++ /dev/null @@ -1,590 +0,0 @@ -#!/usr/bin/env python -#===-- coff-dump.py - COFF object file dump utility-------------------------===# -# -# The LLVM Compiler Infrastructure -# -# This file is distributed under the University of Illinois Open Source -# License. See LICENSE.TXT for details. -# -#===------------------------------------------------------------------------===# - -# -# COFF File Definition -# - -def string_table_entry (offset): - return ('ptr', '+ + PointerToSymbolTable * NumberOfSymbols 18 %s' % offset, ('scalar', 'cstr', '%s')) - -def secname(value): - if value[0] == '/': - return string_table_entry(value[1:].rstrip('\0')) - else: - return '%s' - -def symname(value): - parts = struct.unpack("<2L", value) - if parts[0] == 0: - return string_table_entry(parts[1]) - else: - return '%s' - -file = ('struct', [ - ('MachineType', ('enum', '<H', '0x%X', { - 0x0: 'IMAGE_FILE_MACHINE_UNKNOWN', - 0x1d3: 'IMAGE_FILE_MACHINE_AM33', - 0x8664: 'IMAGE_FILE_MACHINE_AMD64', - 0x1c0: 'IMAGE_FILE_MACHINE_ARM', - 0xebc: 'IMAGE_FILE_MACHINE_EBC', - 0x14c: 'IMAGE_FILE_MACHINE_I386', - 0x200: 'IMAGE_FILE_MACHINE_IA64', - 0x904: 'IMAGE_FILE_MACHINE_M32R', - 0x266: 'IMAGE_FILE_MACHINE_MIPS16', - 0x366: 'IMAGE_FILE_MACHINE_MIPSFPU', - 0x466: 'IMAGE_FILE_MACHINE_MIPSFPU16', - 0x1f0: 'IMAGE_FILE_MACHINE_POWERPC', - 0x1f1: 'IMAGE_FILE_MACHINE_POWERPCFP', - 0x166: 'IMAGE_FILE_MACHINE_R4000', - 0x1a2: 'IMAGE_FILE_MACHINE_SH3', - 0x1a3: 'IMAGE_FILE_MACHINE_SH3DSP', - 0x1a6: 'IMAGE_FILE_MACHINE_SH4', - 0x1a8: 'IMAGE_FILE_MACHINE_SH5', - 0x1c2: 'IMAGE_FILE_MACHINE_THUMB', - 0x169: 'IMAGE_FILE_MACHINE_WCEMIPSV2', - })), - ('NumberOfSections', ('scalar', '<H', '%d')), - ('TimeDateStamp', ('scalar', '<L', '%d')), - ('PointerToSymbolTable', ('scalar', '<L', '0x%0X')), - ('NumberOfSymbols', ('scalar', '<L', '%d')), - ('SizeOfOptionalHeader', ('scalar', '<H', '%d')), - ('Characteristics', ('flags', '<H', '0x%x', [ - (0x0001, 'IMAGE_FILE_RELOCS_STRIPPED', ), - (0x0002, 'IMAGE_FILE_EXECUTABLE_IMAGE', ), - (0x0004, 'IMAGE_FILE_LINE_NUMS_STRIPPED', ), - (0x0008, 'IMAGE_FILE_LOCAL_SYMS_STRIPPED', ), - (0x0010, 'IMAGE_FILE_AGGRESSIVE_WS_TRIM', ), - (0x0020, 'IMAGE_FILE_LARGE_ADDRESS_AWARE', ), - (0x0080, 'IMAGE_FILE_BYTES_REVERSED_LO', ), - (0x0100, 'IMAGE_FILE_32BIT_MACHINE', ), - (0x0200, 'IMAGE_FILE_DEBUG_STRIPPED', ), - (0x0400, 'IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP', ), - (0x0800, 'IMAGE_FILE_NET_RUN_FROM_SWAP', ), - (0x1000, 'IMAGE_FILE_SYSTEM', ), - (0x2000, 'IMAGE_FILE_DLL', ), - (0x4000, 'IMAGE_FILE_UP_SYSTEM_ONLY', ), - (0x8000, 'IMAGE_FILE_BYTES_REVERSED_HI', ), - ])), - ('Sections', ('array', '1', 'NumberOfSections', ('struct', [ - ('Name', ('scalar', '<8s', secname)), - ('VirtualSize', ('scalar', '<L', '%d' )), - ('VirtualAddress', ('scalar', '<L', '%d' )), - ('SizeOfRawData', ('scalar', '<L', '%d' )), - ('PointerToRawData', ('scalar', '<L', '0x%X' )), - ('PointerToRelocations', ('scalar', '<L', '0x%X' )), - ('PointerToLineNumbers', ('scalar', '<L', '0x%X' )), - ('NumberOfRelocations', ('scalar', '<H', '%d' )), - ('NumberOfLineNumbers', ('scalar', '<H', '%d' )), - ('Charateristics', ('flags', '<L', '0x%X', [ - (0x00000008, 'IMAGE_SCN_TYPE_NO_PAD'), - (0x00000020, 'IMAGE_SCN_CNT_CODE'), - (0x00000040, 'IMAGE_SCN_CNT_INITIALIZED_DATA'), - (0x00000080, 'IMAGE_SCN_CNT_UNINITIALIZED_DATA'), - (0x00000100, 'IMAGE_SCN_LNK_OTHER'), - (0x00000200, 'IMAGE_SCN_LNK_INFO'), - (0x00000800, 'IMAGE_SCN_LNK_REMOVE'), - (0x00001000, 'IMAGE_SCN_LNK_COMDAT'), - (0x00008000, 'IMAGE_SCN_GPREL'), - (0x00020000, 'IMAGE_SCN_MEM_PURGEABLE'), - (0x00020000, 'IMAGE_SCN_MEM_16BIT'), - (0x00040000, 'IMAGE_SCN_MEM_LOCKED'), - (0x00080000, 'IMAGE_SCN_MEM_PRELOAD'), - (0x00F00000, 'IMAGE_SCN_ALIGN', { - 0x00100000: 'IMAGE_SCN_ALIGN_1BYTES', - 0x00200000: 'IMAGE_SCN_ALIGN_2BYTES', - 0x00300000: 'IMAGE_SCN_ALIGN_4BYTES', - 0x00400000: 'IMAGE_SCN_ALIGN_8BYTES', - 0x00500000: 'IMAGE_SCN_ALIGN_16BYTES', - 0x00600000: 'IMAGE_SCN_ALIGN_32BYTES', - 0x00700000: 'IMAGE_SCN_ALIGN_64BYTES', - 0x00800000: 'IMAGE_SCN_ALIGN_128BYTES', - 0x00900000: 'IMAGE_SCN_ALIGN_256BYTES', - 0x00A00000: 'IMAGE_SCN_ALIGN_512BYTES', - 0x00B00000: 'IMAGE_SCN_ALIGN_1024BYTES', - 0x00C00000: 'IMAGE_SCN_ALIGN_2048BYTES', - 0x00D00000: 'IMAGE_SCN_ALIGN_4096BYTES', - 0x00E00000: 'IMAGE_SCN_ALIGN_8192BYTES', - }), - (0x01000000, 'IMAGE_SCN_LNK_NRELOC_OVFL'), - (0x02000000, 'IMAGE_SCN_MEM_DISCARDABLE'), - (0x04000000, 'IMAGE_SCN_MEM_NOT_CACHED'), - (0x08000000, 'IMAGE_SCN_MEM_NOT_PAGED'), - (0x10000000, 'IMAGE_SCN_MEM_SHARED'), - (0x20000000, 'IMAGE_SCN_MEM_EXECUTE'), - (0x40000000, 'IMAGE_SCN_MEM_READ'), - (0x80000000, 'IMAGE_SCN_MEM_WRITE'), - ])), - ('SectionData', ('ptr', 'PointerToRawData', ('blob', 'SizeOfRawData'))), - ('Relocations', ('ptr', 'PointerToRelocations', ('array', '0', 'NumberOfRelocations', ('struct', [ - ('VirtualAddress', ('scalar', '<L', '0x%X')), - ('SymbolTableIndex', ('scalar', '<L', '%d' )), - ('Type', ('enum', '<H', '%d', ('MachineType', { - 0x14c: { - 0x0000: 'IMAGE_REL_I386_ABSOLUTE', - 0x0001: 'IMAGE_REL_I386_DIR16', - 0x0002: 'IMAGE_REL_I386_REL16', - 0x0006: 'IMAGE_REL_I386_DIR32', - 0x0007: 'IMAGE_REL_I386_DIR32NB', - 0x0009: 'IMAGE_REL_I386_SEG12', - 0x000A: 'IMAGE_REL_I386_SECTION', - 0x000B: 'IMAGE_REL_I386_SECREL', - 0x000C: 'IMAGE_REL_I386_TOKEN', - 0x000D: 'IMAGE_REL_I386_SECREL7', - 0x0014: 'IMAGE_REL_I386_REL32', - }, - 0x8664: { - 0x0000: 'IMAGE_REL_AMD64_ABSOLUTE', - 0x0001: 'IMAGE_REL_AMD64_ADDR64', - 0x0002: 'IMAGE_REL_AMD64_ADDR32', - 0x0003: 'IMAGE_REL_AMD64_ADDR32NB', - 0x0004: 'IMAGE_REL_AMD64_REL32', - 0x0005: 'IMAGE_REL_AMD64_REL32_1', - 0x0006: 'IMAGE_REL_AMD64_REL32_2', - 0x0007: 'IMAGE_REL_AMD64_REL32_3', - 0x0008: 'IMAGE_REL_AMD64_REL32_4', - 0x0009: 'IMAGE_REL_AMD64_REL32_5', - 0x000A: 'IMAGE_REL_AMD64_SECTION', - 0x000B: 'IMAGE_REL_AMD64_SECREL', - 0x000C: 'IMAGE_REL_AMD64_SECREL7', - 0x000D: 'IMAGE_REL_AMD64_TOKEN', - 0x000E: 'IMAGE_REL_AMD64_SREL32', - 0x000F: 'IMAGE_REL_AMD64_PAIR', - 0x0010: 'IMAGE_REL_AMD64_SSPAN32', - }, - }))), - ('SymbolName', ('ptr', '+ PointerToSymbolTable * SymbolTableIndex 18', ('scalar', '<8s', symname))) - ])))), - ]))), - ('Symbols', ('ptr', 'PointerToSymbolTable', ('byte-array', '18', '* NumberOfSymbols 18', ('struct', [ - ('Name', ('scalar', '<8s', symname)), - ('Value', ('scalar', '<L', '%d' )), - ('SectionNumber', ('scalar', '<H', '%d' )), - ('_Type', ('scalar', '<H', None )), - ('SimpleType', ('enum', '& _Type 15', '%d', { - 0: 'IMAGE_SYM_TYPE_NULL', - 1: 'IMAGE_SYM_TYPE_VOID', - 2: 'IMAGE_SYM_TYPE_CHAR', - 3: 'IMAGE_SYM_TYPE_SHORT', - 4: 'IMAGE_SYM_TYPE_INT', - 5: 'IMAGE_SYM_TYPE_LONG', - 6: 'IMAGE_SYM_TYPE_FLOAT', - 7: 'IMAGE_SYM_TYPE_DOUBLE', - 8: 'IMAGE_SYM_TYPE_STRUCT', - 9: 'IMAGE_SYM_TYPE_UNION', - 10: 'IMAGE_SYM_TYPE_ENUM', - 11: 'IMAGE_SYM_TYPE_MOE', - 12: 'IMAGE_SYM_TYPE_BYTE', - 13: 'IMAGE_SYM_TYPE_WORD', - 14: 'IMAGE_SYM_TYPE_UINT', - 15: 'IMAGE_SYM_TYPE_DWORD', - })), # (Type & 0xF0) >> 4 - ('ComplexType', ('enum', '>> & _Type 240 4', '%d', { - 0: 'IMAGE_SYM_DTYPE_NULL', - 1: 'IMAGE_SYM_DTYPE_POINTER', - 2: 'IMAGE_SYM_DTYPE_FUNCTION', - 3: 'IMAGE_SYM_DTYPE_ARRAY', - })), - ('StorageClass', ('enum', '<B', '%d', { - -1: 'IMAGE_SYM_CLASS_END_OF_FUNCTION', - 0: 'IMAGE_SYM_CLASS_NULL', - 1: 'IMAGE_SYM_CLASS_AUTOMATIC', - 2: 'IMAGE_SYM_CLASS_EXTERNAL', - 3: 'IMAGE_SYM_CLASS_STATIC', - 4: 'IMAGE_SYM_CLASS_REGISTER', - 5: 'IMAGE_SYM_CLASS_EXTERNAL_DEF', - 6: 'IMAGE_SYM_CLASS_LABEL', - 7: 'IMAGE_SYM_CLASS_UNDEFINED_LABEL', - 8: 'IMAGE_SYM_CLASS_MEMBER_OF_STRUCT', - 9: 'IMAGE_SYM_CLASS_ARGUMENT', - 10: 'IMAGE_SYM_CLASS_STRUCT_TAG', - 11: 'IMAGE_SYM_CLASS_MEMBER_OF_UNION', - 12: 'IMAGE_SYM_CLASS_UNION_TAG', - 13: 'IMAGE_SYM_CLASS_TYPE_DEFINITION', - 14: 'IMAGE_SYM_CLASS_UNDEFINED_STATIC', - 15: 'IMAGE_SYM_CLASS_ENUM_TAG', - 16: 'IMAGE_SYM_CLASS_MEMBER_OF_ENUM', - 17: 'IMAGE_SYM_CLASS_REGISTER_PARAM', - 18: 'IMAGE_SYM_CLASS_BIT_FIELD', - 100: 'IMAGE_SYM_CLASS_BLOCK', - 101: 'IMAGE_SYM_CLASS_FUNCTION', - 102: 'IMAGE_SYM_CLASS_END_OF_STRUCT', - 103: 'IMAGE_SYM_CLASS_FILE', - 104: 'IMAGE_SYM_CLASS_SECTION', - 105: 'IMAGE_SYM_CLASS_WEAK_EXTERNAL', - 107: 'IMAGE_SYM_CLASS_CLR_TOKEN', - })), - ('NumberOfAuxSymbols', ('scalar', '<B', '%d' )), - ('AuxillaryData', ('blob', '* NumberOfAuxSymbols 18')), - ])))), -]) - -# -# Definition Interpreter -# - -import sys, types, struct, re - -Input = None -Stack = [] -Fields = {} - -Indent = 0 -NewLine = True - -def indent(): - global Indent - Indent += 1 - -def dedent(): - global Indent - Indent -= 1 - -def write(input): - global NewLine - output = "" - - for char in input: - - if NewLine: - output += Indent * ' ' - NewLine = False - - output += char - - if char == '\n': - NewLine = True - - sys.stdout.write(output) - -def read(format): - return struct.unpack(format, Input.read(struct.calcsize(format))) - -def read_cstr(): - output = "" - while True: - char = Input.read(1) - if len(char) == 0: - raise RuntimeError ("EOF while reading cstr") - if char == '\0': - break - output += char - return output - -def push_pos(seek_to = None): - Stack [0:0] = [Input.tell()] - if seek_to: - Input.seek(seek_to) - -def pop_pos(): - assert(len(Stack) > 0) - Input.seek(Stack[0]) - del Stack[0] - -def print_binary_data(size): - value = "" - while size > 0: - if size >= 16: - data = Input.read(16) - size -= 16 - else: - data = Input.read(size) - size = 0 - value += data - bytes = "" - text = "" - for index in xrange(16): - if index < len(data): - if index == 8: - bytes += "- " - ch = ord(data[index]) - bytes += "%02X " % ch - if ch >= 0x20 and ch <= 0x7F: - text += data[index] - else: - text += "." - else: - if index == 8: - bytes += " " - bytes += " " - - write("%s|%s|\n" % (bytes, text)) - return value - -idlit = re.compile("[a-zA-Z_][a-zA-Z0-9_-]*") -numlit = re.compile("[0-9]+") - -def read_value(expr): - - input = iter(expr.split()) - - def eval(): - - token = input.next() - - if expr == 'cstr': - return read_cstr() - if expr == 'true': - return True - if expr == 'false': - return False - - if token == '+': - return eval() + eval() - if token == '-': - return eval() - eval() - if token == '*': - return eval() * eval() - if token == '/': - return eval() / eval() - if token == '&': - return eval() & eval() - if token == '|': - return eval() | eval() - if token == '>>': - return eval() >> eval() - if token == '<<': - return eval() << eval() - - if len(token) > 1 and token[0] in ('=', '@', '<', '!', '>'): - val = read(expr) - assert(len(val) == 1) - return val[0] - - if idlit.match(token): - return Fields[token] - if numlit.match(token): - return int(token) - - raise RuntimeError("unexpected token %s" % repr(token)) - - value = eval() - - try: - input.next() - except StopIteration: - return value - raise RuntimeError("unexpected input at end of expression") - -def write_value(format,value): - format_type = type(format) - if format_type is types.StringType: - write(format % value) - elif format_type is types.FunctionType: - write_value(format(value), value) - elif format_type is types.TupleType: - Fields['this'] = value - handle_element(format) - elif format_type is types.NoneType: - pass - else: - raise RuntimeError("unexpected type: %s" % repr(format_type)) - -def handle_scalar(entry): - iformat = entry[1] - oformat = entry[2] - - value = read_value(iformat) - - write_value(oformat, value) - - return value - -def handle_enum(entry): - iformat = entry[1] - oformat = entry[2] - definitions = entry[3] - - value = read_value(iformat) - - if type(definitions) is types.TupleType: - selector = read_value(definitions[0]) - definitions = definitions[1][selector] - - if value in definitions: - description = definitions[value] - else: - description = "unknown" - - write("%s (" % description) - write_value(oformat, value) - write(")") - - return value - -def handle_flags(entry): - iformat = entry[1] - oformat = entry[2] - definitions = entry[3] - - value = read_value(iformat) - - write_value(oformat, value) - - indent() - for entry in definitions: - mask = entry[0] - name = entry[1] - if len (entry) == 3: - map = entry[2] - selection = value & mask - if selection in map: - write("\n%s" % map[selection]) - else: - write("\n%s <%d>" % (name, selection)) - elif len(entry) == 2: - if value & mask != 0: - write("\n%s" % name) - dedent() - - return value - -def handle_struct(entry): - global Fields - members = entry[1] - - newFields = {} - - write("{\n"); - indent() - - for member in members: - name = member[0] - type = member[1] - - if name[0] != "_": - write("%s = " % name.ljust(24)) - - value = handle_element(type) - - if name[0] != "_": - write("\n") - - Fields[name] = value - newFields[name] = value - - dedent() - write("}") - - return newFields - -def handle_array(entry): - start_index = entry[1] - length = entry[2] - element = entry[3] - - newItems = [] - - write("[\n") - indent() - - start_index = read_value(start_index) - value = read_value(length) - - for index in xrange(value): - write("%d = " % (index + start_index)) - value = handle_element(element) - write("\n") - newItems.append(value) - - dedent() - write("]") - - return newItems - -def handle_byte_array(entry): - ent_size = entry[1] - length = entry[2] - element = entry[3] - - newItems = [] - - write("[\n") - indent() - - item_size = read_value(ent_size) - value = read_value(length) - end_of_array = Input.tell() + value - - prev_loc = Input.tell() - index = 0 - while Input.tell() < end_of_array: - write("%d = " % index) - value = handle_element(element) - write("\n") - newItems.append(value) - index += (Input.tell() - prev_loc) / item_size - prev_loc = Input.tell() - - dedent() - write("]") - - return newItems - -def handle_ptr(entry): - offset = entry[1] - element = entry[2] - - value = None - offset = read_value(offset) - - if offset != 0: - - push_pos(offset) - - value = handle_element(element) - - pop_pos() - - else: - write("None") - - return value - -def handle_blob(entry): - length = entry[1] - - write("\n") - indent() - - value = print_binary_data(read_value(length)) - - dedent() - - return value - -def handle_element(entry): - handlers = { - 'struct': handle_struct, - 'scalar': handle_scalar, - 'enum': handle_enum, - 'flags': handle_flags, - 'ptr': handle_ptr, - 'blob': handle_blob, - 'array': handle_array, - 'byte-array': handle_byte_array, - } - - if not entry[0] in handlers: - raise RuntimeError ("unexpected type '%s'" % str (entry[0])) - - return handlers[entry[0]](entry) - -if len(sys.argv) <= 1 or sys.argv[1] == '-': - import StringIO - Input = StringIO.StringIO(sys.stdin.read()) -else: - Input = open (sys.argv[1], "rb") - -try: - handle_element(file) -finally: - Input.close() - Input = None diff --git a/test/Scripts/coff-dump.py.bat b/test/Scripts/coff-dump.py.bat deleted file mode 100644 index 56428e1a605c..000000000000 --- a/test/Scripts/coff-dump.py.bat +++ /dev/null @@ -1,7 +0,0 @@ -@echo off - -@rem We need to set -u to treat stdin as binary. Python 3 has support for doing -@rem this in code, but I haven't found a way to do this in 2.6 yet. - -%PYTHON_EXECUTABLE% -u %LLVM_SRC_ROOT%\test\Scripts\coff-dump.py %1 %2 %3 %4 %5 %6 %7 %8 %9 - diff --git a/test/Scripts/common_dump.py b/test/Scripts/common_dump.py deleted file mode 100644 index fd58993c0584..000000000000 --- a/test/Scripts/common_dump.py +++ /dev/null @@ -1,48 +0,0 @@ -def dataToHex(d): - """ Convert the raw data in 'd' to an hex string with a space every 4 bytes. - """ - bytes = [] - for i,c in enumerate(d): - byte = ord(c) - hex_byte = hex(byte)[2:] - if byte <= 0xf: - hex_byte = '0' + hex_byte - if i % 4 == 3: - hex_byte += ' ' - bytes.append(hex_byte) - return ''.join(bytes).strip() - -def dataToHexUnified(d): - """ Convert the raw data in 'd' to an hex string with a space every 4 bytes. - Each 4byte number is prefixed with 0x for easy sed/rx - Fixme: convert all MC tests to use this routine instead of the above - """ - bytes = [] - for i,c in enumerate(d): - byte = ord(c) - hex_byte = hex(byte)[2:] - if byte <= 0xf: - hex_byte = '0' + hex_byte - if i % 4 == 0: - hex_byte = '0x' + hex_byte - if i % 4 == 3: - hex_byte += ' ' - bytes.append(hex_byte) - return ''.join(bytes).strip() - - -def HexDump(valPair): - """ - 1. do not print 'L' - 2. Handle negatives and large numbers by mod (2^numBits) - 3. print fixed length, prepend with zeros. - Length is exactly 2+(numBits/4) - 4. Do print 0x Why? - so that they can be easily distinguished using sed/rx - """ - val, numBits = valPair - assert 0 <= val < (1 << numBits) - - val = val & (( 1 << numBits) - 1) - newFmt = "0x%0" + "%d" % (numBits / 4) + "x" - return newFmt % val diff --git a/test/Scripts/elf-dump b/test/Scripts/elf-dump deleted file mode 100755 index 61342d8f98e5..000000000000 --- a/test/Scripts/elf-dump +++ /dev/null @@ -1,285 +0,0 @@ -#!/usr/bin/env python - -import struct -import sys -import StringIO - -import common_dump - -class Reader: - def __init__(self, path): - if path == "-": - # Snarf all the data so we can seek. - self.file = StringIO.StringIO(sys.stdin.read()) - else: - self.file = open(path, "rb") - self.isLSB = None - self.is64Bit = None - self.isN64 = False - - def seek(self, pos): - self.file.seek(pos) - - def read(self, N): - data = self.file.read(N) - if len(data) != N: - raise ValueError, "Out of data!" - return data - - def read8(self): - return (ord(self.read(1)), 8) - - def read16(self): - return (struct.unpack('><'[self.isLSB] + 'H', self.read(2))[0], 16) - - def read32(self): - return (struct.unpack('><'[self.isLSB] + 'I', self.read(4))[0], 32) - - def read64(self): - return (struct.unpack('><'[self.isLSB] + 'Q', self.read(8))[0], 64) - - def readWord(self): - if self.is64Bit: - return self.read64() - else: - return self.read32() - -class StringTable: - def __init__(self, strings): - self.string_table = strings - - def __getitem__(self, index): - end = self.string_table.index('\x00', index) - return self.string_table[index:end] - -class ProgramHeader: - def __init__(self, f): - self.p_type = f.read32() - if f.is64Bit: - self.p_flags = f.read32() - self.p_offset = f.readWord() - self.p_vaddr = f.readWord() - self.p_paddr = f.readWord() - self.p_filesz = f.readWord() - self.p_memsz = f.readWord() - if not f.is64Bit: - self.p_flags = f.read32() - self.p_align = f.readWord() - - def dump(self): - print " (('p_type', %s)" % common_dump.HexDump(self.p_type) - print " ('p_flags', %s)" % common_dump.HexDump(self.p_flags) - print " ('p_offset', %s)" % common_dump.HexDump(self.p_offset) - print " ('p_vaddr', %s)" % common_dump.HexDump(self.p_vaddr) - print " ('p_paddr', %s)" % common_dump.HexDump(self.p_paddr) - print " ('p_filesz', %s)" % common_dump.HexDump(self.p_filesz) - print " ('p_memsz', %s)" % common_dump.HexDump(self.p_memsz) - print " ('p_align', %s)" % common_dump.HexDump(self.p_align) - print " )," - -class Section: - def __init__(self, f): - self.sh_name = f.read32() - self.sh_type = f.read32() - self.sh_flags = f.readWord() - self.sh_addr = f.readWord() - self.sh_offset = f.readWord() - self.sh_size = f.readWord() - self.sh_link = f.read32() - self.sh_info = f.read32() - self.sh_addralign = f.readWord() - self.sh_entsize = f.readWord() - - def dump(self, shstrtab, f, strtab, dumpdata): - print " (('sh_name', %s)" % common_dump.HexDump(self.sh_name), "# %r" % shstrtab[self.sh_name[0]] - print " ('sh_type', %s)" % common_dump.HexDump(self.sh_type) - print " ('sh_flags', %s)" % common_dump.HexDump(self.sh_flags) - print " ('sh_addr', %s)" % common_dump.HexDump(self.sh_addr) - print " ('sh_offset', %s)" % common_dump.HexDump(self.sh_offset) - print " ('sh_size', %s)" % common_dump.HexDump(self.sh_size) - print " ('sh_link', %s)" % common_dump.HexDump(self.sh_link) - print " ('sh_info', %s)" % common_dump.HexDump(self.sh_info) - print " ('sh_addralign', %s)" % common_dump.HexDump(self.sh_addralign) - print " ('sh_entsize', %s)" % common_dump.HexDump(self.sh_entsize) - if self.sh_type[0] == 2: # SHT_SYMTAB - print " ('_symbols', [" - dumpSymtab(f, self, strtab) - print " ])" - elif self.sh_type[0] == 4 or self.sh_type[0] == 9: # SHT_RELA / SHT_REL - print " ('_relocations', [" - dumpRel(f, self, self.sh_type[0] == 4) - print " ])" - elif dumpdata: - f.seek(self.sh_offset[0]) - if self.sh_type != 8: # != SHT_NOBITS - data = f.read(self.sh_size[0]) - print " ('_section_data', '%s')" % common_dump.dataToHex(data) - else: - print " ('_section_data', '')" - print " )," - -def dumpSymtab(f, section, strtab): - entries = section.sh_size[0] // section.sh_entsize[0] - - for index in range(entries): - f.seek(section.sh_offset[0] + index * section.sh_entsize[0]) - print " # Symbol %s" % index - name = f.read32() - print " (('st_name', %s)" % common_dump.HexDump(name), "# %r" % strtab[name[0]] - if not f.is64Bit: - print " ('st_value', %s)" % common_dump.HexDump(f.read32()) - print " ('st_size', %s)" % common_dump.HexDump(f.read32()) - st_info = f.read8()[0] - st_bind = (st_info >> 4, 4) - st_type = (st_info & 0xf, 4) - print " ('st_bind', %s)" % common_dump.HexDump(st_bind) - print " ('st_type', %s)" % common_dump.HexDump(st_type) - print " ('st_other', %s)" % common_dump.HexDump(f.read8()) - print " ('st_shndx', %s)" % common_dump.HexDump(f.read16()) - if f.is64Bit: - print " ('st_value', %s)" % common_dump.HexDump(f.read64()) - print " ('st_size', %s)" % common_dump.HexDump(f.read64()) - print " )," - -def dumpRel(f, section, dumprela = False): - entries = section.sh_size[0] // section.sh_entsize[0] - - for index in range(entries): - f.seek(section.sh_offset[0] + index * section.sh_entsize[0]) - print " # Relocation %s" % index - print " (('r_offset', %s)" % common_dump.HexDump(f.readWord()) - - if f.isN64: - r_sym = f.read32() - r_ssym = f.read8() - r_type3 = f.read8() - r_type2 = f.read8() - r_type = f.read8() - print " ('r_sym', %s)" % common_dump.HexDump(r_sym) - print " ('r_ssym', %s)" % common_dump.HexDump(r_ssym) - print " ('r_type3', %s)" % common_dump.HexDump(r_type3) - print " ('r_type2', %s)" % common_dump.HexDump(r_type2) - print " ('r_type', %s)" % common_dump.HexDump(r_type) - else: - r_info = f.readWord()[0] - if f.is64Bit: - r_sym = (r_info >> 32, 32) - r_type = (r_info & 0xffffffff, 32) - else: - r_sym = (r_info >> 8, 24) - r_type = (r_info & 0xff, 8) - print " ('r_sym', %s)" % common_dump.HexDump(r_sym) - print " ('r_type', %s)" % common_dump.HexDump(r_type) - if dumprela: - print " ('r_addend', %s)" % common_dump.HexDump(f.readWord()) - print " )," - -def dumpELF(path, opts): - f = Reader(path) - - magic = f.read(4) - assert magic == '\x7FELF' - - fileclass = f.read8() - if fileclass[0] == 1: # ELFCLASS32 - f.is64Bit = False - elif fileclass[0] == 2: # ELFCLASS64 - f.is64Bit = True - else: - raise ValueError, "Unknown file class %s" % common_dump.HexDump(fileclass) - print "('e_indent[EI_CLASS]', %s)" % common_dump.HexDump(fileclass) - - byteordering = f.read8() - if byteordering[0] == 1: # ELFDATA2LSB - f.isLSB = True - elif byteordering[0] == 2: # ELFDATA2MSB - f.isLSB = False - else: - raise ValueError, "Unknown byte ordering %s" % common_dump.HexDump(byteordering) - print "('e_indent[EI_DATA]', %s)" % common_dump.HexDump(byteordering) - - print "('e_indent[EI_VERSION]', %s)" % common_dump.HexDump(f.read8()) - print "('e_indent[EI_OSABI]', %s)" % common_dump.HexDump(f.read8()) - print "('e_indent[EI_ABIVERSION]', %s)" % common_dump.HexDump(f.read8()) - - f.seek(16) # Seek to end of e_ident. - - print "('e_type', %s)" % common_dump.HexDump(f.read16()) - - # Does any other architecture use N64? - e_machine = f.read16() - if e_machine[0] == 0x0008 and f.is64Bit: # EM_MIPS && 64 bit - f.isN64 = True - - print "('e_machine', %s)" % common_dump.HexDump(e_machine) - print "('e_version', %s)" % common_dump.HexDump(f.read32()) - print "('e_entry', %s)" % common_dump.HexDump(f.readWord()) - e_phoff = f.readWord() - print "('e_phoff', %s)" % common_dump.HexDump(e_phoff) - e_shoff = f.readWord() - print "('e_shoff', %s)" % common_dump.HexDump(e_shoff) - print "('e_flags', %s)" % common_dump.HexDump(f.read32()) - print "('e_ehsize', %s)" % common_dump.HexDump(f.read16()) - e_phentsize = f.read16() - print "('e_phentsize', %s)" % common_dump.HexDump(e_phentsize) - e_phnum = f.read16() - print "('e_phnum', %s)" % common_dump.HexDump(e_phnum) - e_shentsize = f.read16() - print "('e_shentsize', %s)" % common_dump.HexDump(e_shentsize) - e_shnum = f.read16() - print "('e_shnum', %s)" % common_dump.HexDump(e_shnum) - e_shstrndx = f.read16() - print "('e_shstrndx', %s)" % common_dump.HexDump(e_shstrndx) - - - # Read all section headers - sections = [] - for index in range(e_shnum[0]): - f.seek(e_shoff[0] + index * e_shentsize[0]) - s = Section(f) - sections.append(s) - - # Read .shstrtab so we can resolve section names - f.seek(sections[e_shstrndx[0]].sh_offset[0]) - shstrtab = StringTable(f.read(sections[e_shstrndx[0]].sh_size[0])) - - # Get the symbol string table - strtab = None - for section in sections: - if shstrtab[section.sh_name[0]] == ".strtab": - f.seek(section.sh_offset[0]) - strtab = StringTable(f.read(section.sh_size[0])) - break - - print "('_sections', [" - for index in range(e_shnum[0]): - print " # Section %s" % index - sections[index].dump(shstrtab, f, strtab, opts.dumpSectionData) - print "])" - - # Read all program headers - headers = [] - for index in range(e_phnum[0]): - f.seek(e_phoff[0] + index * e_phentsize[0]) - h = ProgramHeader(f) - headers.append(h) - - print "('_ProgramHeaders', [" - for index in range(e_phnum[0]): - print " # Program Header %s" % index - headers[index].dump() - print "])" - -if __name__ == "__main__": - from optparse import OptionParser, OptionGroup - parser = OptionParser("usage: %prog [options] {files}") - parser.add_option("", "--dump-section-data", dest="dumpSectionData", - help="Dump the contents of sections", - action="store_true", default=False) - (opts, args) = parser.parse_args() - - if not args: - args.append('-') - - for arg in args: - dumpELF(arg, opts) diff --git a/test/Scripts/elf-dump.bat b/test/Scripts/elf-dump.bat deleted file mode 100644 index 9c708083b302..000000000000 --- a/test/Scripts/elf-dump.bat +++ /dev/null @@ -1,7 +0,0 @@ -@echo off - -@rem We need to set -u to treat stdin as binary. Python 3 has support for doing -@rem this in code, but I haven't found a way to do this in 2.6 yet. - -%PYTHON_EXECUTABLE% -u %LLVM_SRC_ROOT%\test\Scripts\elf-dump %1 %2 %3 %4 %5 %6 %7 %8 %9 - diff --git a/test/Scripts/ignore b/test/Scripts/ignore deleted file mode 100755 index 865ae4df1bd4..000000000000 --- a/test/Scripts/ignore +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh -# -# Program: ignore -# -# Synopsis: Ignore the result code of the command and always return 0 -# -# Syntax: ignore command <arguments> - -"$@" || exit 0 && exit 0 -exit 0 diff --git a/test/Scripts/macho-dumpx b/test/Scripts/macho-dumpx deleted file mode 100755 index 71e06d837b90..000000000000 --- a/test/Scripts/macho-dumpx +++ /dev/null @@ -1,294 +0,0 @@ -#!/usr/bin/env python - -import struct -import sys -import StringIO - -import common_dump - -class Reader: - def __init__(self, path): - if path == '-': - # Snarf all the data so we can seek. - self.file = StringIO.StringIO(sys.stdin.read()) - else: - self.file = open(path,'rb') - self.isLSB = None - self.is64Bit = None - - self.string_table = None - - def tell(self): - return self.file.tell() - - def seek(self, pos): - self.file.seek(pos) - - def read(self, N): - data = self.file.read(N) - if len(data) != N: - raise ValueError,"Out of data!" - return data - - def read8(self): - return ord(self.read(1)) - - def read16(self): - return struct.unpack('><'[self.isLSB] + 'H', self.read(2))[0] - - def read32(self): - # Force to 32-bit, if possible; otherwise these might be long ints on a - # big-endian platform. FIXME: Why??? - Value = struct.unpack('><'[self.isLSB] + 'I', self.read(4))[0] - return int(Value) - - def read64(self): - Value = struct.unpack('><'[self.isLSB] + 'Q', self.read(8))[0] - if Value == int(Value): - Value = int(Value) - return Value - - def registerStringTable(self, strings): - if self.string_table is not None: - raise ValueError,"%s: warning: multiple string tables" % sys.argv[0] - - self.string_table = strings - - def getString(self, index): - if self.string_table is None: - raise ValueError,"%s: warning: no string table registered" % sys.argv[0] - - end = self.string_table.index('\x00', index) - return self.string_table[index:end] - -def dumpmacho(path, opts): - f = Reader(path) - - magic = f.read(4) - if magic == '\xFE\xED\xFA\xCE': - f.isLSB, f.is64Bit = False, False - elif magic == '\xCE\xFA\xED\xFE': - f.isLSB, f.is64Bit = True, False - elif magic == '\xFE\xED\xFA\xCF': - f.isLSB, f.is64Bit = False, True - elif magic == '\xCF\xFA\xED\xFE': - f.isLSB, f.is64Bit = True, True - else: - raise ValueError,"Not a Mach-O object file: %r (bad magic)" % path - - print "('cputype', %r)" % f.read32() - print "('cpusubtype', %r)" % f.read32() - filetype = f.read32() - print "('filetype', %r)" % filetype - - numLoadCommands = f.read32() - print "('num_load_commands', %r)" % numLoadCommands - - loadCommandsSize = f.read32() - print "('load_commands_size', %r)" % loadCommandsSize - - print "('flag', %r)" % f.read32() - - if f.is64Bit: - print "('reserved', %r)" % f.read32() - - start = f.tell() - - print "('load_commands', [" - for i in range(numLoadCommands): - dumpLoadCommand(f, i, opts) - print "])" - - if f.tell() - start != loadCommandsSize: - raise ValueError,"%s: warning: invalid load commands size: %r" % ( - sys.argv[0], loadCommandsSize) - -def dumpLoadCommand(f, i, opts): - start = f.tell() - - print " # Load Command %r" % i - cmd = f.read32() - print " (('command', %r)" % cmd - cmdSize = f.read32() - print " ('size', %r)" % cmdSize - - if cmd == 1: - dumpSegmentLoadCommand(f, opts, False) - elif cmd == 2: - dumpSymtabCommand(f, opts) - elif cmd == 11: - dumpDysymtabCommand(f, opts) - elif cmd == 25: - dumpSegmentLoadCommand(f, opts, True) - elif cmd == 27: - import uuid - print " ('uuid', %s)" % uuid.UUID(bytes=f.read(16)) - else: - print >>sys.stderr,"%s: warning: unknown load command: %r" % ( - sys.argv[0], cmd) - f.read(cmdSize - 8) - print " )," - - if f.tell() - start != cmdSize: - raise ValueError,"%s: warning: invalid load command size: %r" % ( - sys.argv[0], cmdSize) - -def dumpSegmentLoadCommand(f, opts, is64Bit): - print " ('segment_name', %r)" % f.read(16) - if is64Bit: - print " ('vm_addr', %r)" % f.read64() - print " ('vm_size', %r)" % f.read64() - print " ('file_offset', %r)" % f.read64() - print " ('file_size', %r)" % f.read64() - else: - print " ('vm_addr', %r)" % f.read32() - print " ('vm_size', %r)" % f.read32() - print " ('file_offset', %r)" % f.read32() - print " ('file_size', %r)" % f.read32() - print " ('maxprot', %r)" % f.read32() - print " ('initprot', %r)" % f.read32() - numSections = f.read32() - print " ('num_sections', %r)" % numSections - print " ('flags', %r)" % f.read32() - - print " ('sections', [" - for i in range(numSections): - dumpSection(f, i, opts, is64Bit) - print " ])" - -def dumpSymtabCommand(f, opts): - symoff = f.read32() - print " ('symoff', %r)" % symoff - nsyms = f.read32() - print " ('nsyms', %r)" % nsyms - stroff = f.read32() - print " ('stroff', %r)" % stroff - strsize = f.read32() - print " ('strsize', %r)" % strsize - - prev_pos = f.tell() - - f.seek(stroff) - string_data = f.read(strsize) - print " ('_string_data', %r)" % string_data - - f.registerStringTable(string_data) - - f.seek(symoff) - print " ('_symbols', [" - for i in range(nsyms): - dumpNlist32(f, i, opts) - print " ])" - - f.seek(prev_pos) - -def dumpNlist32(f, i, opts): - print " # Symbol %r" % i - n_strx = f.read32() - print " (('n_strx', %r)" % n_strx - n_type = f.read8() - print " ('n_type', %#x)" % n_type - n_sect = f.read8() - print " ('n_sect', %r)" % n_sect - n_desc = f.read16() - print " ('n_desc', %r)" % n_desc - if f.is64Bit: - n_value = f.read64() - print " ('n_value', %r)" % n_value - else: - n_value = f.read32() - print " ('n_value', %r)" % n_value - print " ('_string', %r)" % f.getString(n_strx) - print " )," - -def dumpDysymtabCommand(f, opts): - print " ('ilocalsym', %r)" % f.read32() - print " ('nlocalsym', %r)" % f.read32() - print " ('iextdefsym', %r)" % f.read32() - print " ('nextdefsym', %r)" % f.read32() - print " ('iundefsym', %r)" % f.read32() - print " ('nundefsym', %r)" % f.read32() - print " ('tocoff', %r)" % f.read32() - print " ('ntoc', %r)" % f.read32() - print " ('modtaboff', %r)" % f.read32() - print " ('nmodtab', %r)" % f.read32() - print " ('extrefsymoff', %r)" % f.read32() - print " ('nextrefsyms', %r)" % f.read32() - indirectsymoff = f.read32() - print " ('indirectsymoff', %r)" % indirectsymoff - nindirectsyms = f.read32() - print " ('nindirectsyms', %r)" % nindirectsyms - print " ('extreloff', %r)" % f.read32() - print " ('nextrel', %r)" % f.read32() - print " ('locreloff', %r)" % f.read32() - print " ('nlocrel', %r)" % f.read32() - - prev_pos = f.tell() - - f.seek(indirectsymoff) - print " ('_indirect_symbols', [" - for i in range(nindirectsyms): - print " # Indirect Symbol %r" % i - print " (('symbol_index', %#x),)," % f.read32() - print " ])" - - f.seek(prev_pos) - -def dumpSection(f, i, opts, is64Bit): - print " # Section %r" % i - print " (('section_name', %r)" % f.read(16) - print " ('segment_name', %r)" % f.read(16) - if is64Bit: - print " ('address', %r)" % f.read64() - size = f.read64() - print " ('size', %r)" % size - else: - print " ('address', %r)" % f.read32() - size = f.read32() - print " ('size', %r)" % size - offset = f.read32() - print " ('offset', %r)" % offset - print " ('alignment', %r)" % f.read32() - reloc_offset = f.read32() - print " ('reloc_offset', %r)" % reloc_offset - num_reloc = f.read32() - print " ('num_reloc', %r)" % num_reloc - print " ('flags', %#x)" % f.read32() - print " ('reserved1', %r)" % f.read32() - print " ('reserved2', %r)" % f.read32() - if is64Bit: - print " ('reserved3', %r)" % f.read32() - print " )," - - prev_pos = f.tell() - - f.seek(reloc_offset) - print " ('_relocations', [" - for i in range(num_reloc): - print " # Relocation %r" % i - print " (('word-0', %#x)," % f.read32() - print " ('word-1', %#x))," % f.read32() - print " ])" - - if opts.dumpSectionData: - f.seek(offset) - print " ('_section_data', '%s')" % common_dump.dataToHex(f.read(size)) - - f.seek(prev_pos) - -def main(): - from optparse import OptionParser, OptionGroup - parser = OptionParser("usage: %prog [options] {files}") - parser.add_option("", "--dump-section-data", dest="dumpSectionData", - help="Dump the contents of sections", - action="store_true", default=False) - (opts, args) = parser.parse_args() - - if not args: - args.append('-') - - for arg in args: - dumpmacho(arg, opts) - -if __name__ == '__main__': - main() diff --git a/test/Scripts/macho-dumpx.bat b/test/Scripts/macho-dumpx.bat deleted file mode 100644 index 81484f67d702..000000000000 --- a/test/Scripts/macho-dumpx.bat +++ /dev/null @@ -1,7 +0,0 @@ -@echo off - -@rem We need to set -u to treat stdin as binary. Python 3 has support for doing -@rem this in code, but I haven't found a way to do this in 2.6 yet. - -%PYTHON_EXECUTABLE% -u %LLVM_SRC_ROOT%\test\Scripts\macho-dump %1 %2 %3 %4 %5 %6 %7 %8 %9 - diff --git a/test/Transforms/BBVectorize/X86/loop1.ll b/test/Transforms/BBVectorize/X86/loop1.ll index 493f23b09853..bbf565d1cc7f 100644 --- a/test/Transforms/BBVectorize/X86/loop1.ll +++ b/test/Transforms/BBVectorize/X86/loop1.ll @@ -34,7 +34,15 @@ for.body: ; preds = %for.body, %entry %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 10 br i1 %exitcond, label %for.end, label %for.body -; CHECK-NOT: <2 x double> +; CHECK: insertelement +; CHECK-NEXT: insertelement +; CHECK-NEXT: fadd <2 x double> +; CHECK-NEXT: insertelement +; CHECK-NEXT: insertelement +; CHECK-NEXT: fadd <2 x double> +; CHECK-NEXT: insertelement +; CHECK-NEXT: fmul <2 x double> + ; CHECK-UNRL: %mul = fmul <2 x double> %2, %2 ; CHECK-UNRL: %mul3 = fmul <2 x double> %2, %3 ; CHECK-UNRL: %add = fadd <2 x double> %mul, %mul3 diff --git a/test/Transforms/BBVectorize/X86/simple.ll b/test/Transforms/BBVectorize/X86/simple.ll index 0113e38bb1c9..8abfa5f8bd29 100644 --- a/test/Transforms/BBVectorize/X86/simple.ll +++ b/test/Transforms/BBVectorize/X86/simple.ll @@ -12,7 +12,11 @@ define double @test1(double %A1, double %A2, double %B1, double %B2) { %R = fmul double %Z1, %Z2 ret double %R ; CHECK: @test1 -; CHECK-NOT: fmul <2 x double> +; CHECK: fsub <2 x double> +; CHECK: fmul <2 x double> +; CHECK: fadd <2 x double> +; CHECK: extract +; CHECK: extract ; CHECK: ret double %R } @@ -63,7 +67,12 @@ define double @test2(double %A1, double %A2, double %B1, double %B2) { %R = fmul double %Z1, %Z2 ret double %R ; CHECK: @test2 -; CHECK-NOT: fmul <2 x double> +; CHECK: insertelement +; CHECK: insertelement +; CHECK: insertelement +; CHECK: insertelement +; CHECK: fsub <2 x double> +; CHECK: fmul <2 x double> ; CHECK: ret double %R } @@ -80,7 +89,15 @@ define double @test4(double %A1, double %A2, double %B1, double %B2) { %R = fmul double %Z1, %Z2 ret double %R ; CHECK: @test4 -; CHECK-NOT: fmul <2 x double> +; CHECK: insertelement +; CHECK: insertelement +; CHECK: insertelement +; CHECK: insertelement +; CHECK: fsub <2 x double> +; CHECK: fmul <2 x double> +; CHECK: insertelement +; CHECK: insertelement +; CHECK: fadd <2 x double> ; CHECK: ret double %R } diff --git a/test/Transforms/ConstantMerge/merge-both.ll b/test/Transforms/ConstantMerge/merge-both.ll index b00345557c83..316267648f1f 100644 --- a/test/Transforms/ConstantMerge/merge-both.ll +++ b/test/Transforms/ConstantMerge/merge-both.ll @@ -26,6 +26,9 @@ declare void @helper([16 x i8]*) ; CHECK-NEXT: @var6 = private constant [16 x i8] c"foo1bar2foo3bar\00", align 16 ; CHECK-NEXT: @var8 = private constant [16 x i8] c"foo1bar2foo3bar\00" +@var4a = alias %struct.foobar* @var4 +@llvm.used = appending global [1 x %struct.foobar*] [%struct.foobar* @var4a], section "llvm.metadata" + define i32 @main() { entry: call void @zed(%struct.foobar* @var1, %struct.foobar* @var2) diff --git a/test/Transforms/DeadArgElim/dbginfo.ll b/test/Transforms/DeadArgElim/dbginfo.ll index 24448b7009ed..d53c19c8ef58 100644 --- a/test/Transforms/DeadArgElim/dbginfo.ll +++ b/test/Transforms/DeadArgElim/dbginfo.ll @@ -36,7 +36,7 @@ entry: !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165305)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !6, metadata !"clang version 3.2 (trunk 165305)", i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus] !1 = metadata !{i32 0} !3 = metadata !{metadata !5, metadata !8, metadata !9} !5 = metadata !{i32 786478, metadata !6, metadata !"run", metadata !"run", metadata !"", metadata !6, i32 8, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [run] diff --git a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll index c5cc101a5f7b..d114e513ed2b 100644 --- a/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll +++ b/test/Transforms/DeadStoreElimination/2011-09-06-EndOfFunction.ll @@ -11,17 +11,13 @@ _ZNSt8auto_ptrIiED1Ev.exit: %temp.lvalue = alloca %"class.std::auto_ptr", align 8 call void @_Z3barv(%"class.std::auto_ptr"* sret %temp.lvalue) %_M_ptr.i.i = getelementptr inbounds %"class.std::auto_ptr"* %temp.lvalue, i64 0, i32 0 - %tmp.i.i = load i32** %_M_ptr.i.i, align 8, !tbaa !0 + %tmp.i.i = load i32** %_M_ptr.i.i, align 8 ; CHECK-NOT: store i32* null - store i32* null, i32** %_M_ptr.i.i, align 8, !tbaa !0 + store i32* null, i32** %_M_ptr.i.i, align 8 %_M_ptr.i.i4 = getelementptr inbounds %"class.std::auto_ptr"* %agg.result, i64 0, i32 0 - store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8, !tbaa !0 + store i32* %tmp.i.i, i32** %_M_ptr.i.i4, align 8 ; CHECK: ret void ret void } declare void @_Z3barv(%"class.std::auto_ptr"* sret) - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/GCOVProfiling/linkagename.ll b/test/Transforms/GCOVProfiling/linkagename.ll index d1bce728e08c..7ce4d861f0e0 100644 --- a/test/Transforms/GCOVProfiling/linkagename.ll +++ b/test/Transforms/GCOVProfiling/linkagename.ll @@ -14,7 +14,7 @@ entry: !llvm.dbg.cu = !{!0} !llvm.gcov = !{!9} -!0 = metadata !{i32 786449, i32 4, metadata !1, metadata !"clang version 3.3 (trunk 177323)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/nlewycky/hello.cc] [DW_LANG_C_plus_plus] +!0 = metadata !{i32 786449, i32 4, metadata !1, metadata !"clang version 3.3 (trunk 177323)", i1 false, metadata !"", i32 0, metadata !3, metadata !3, metadata !4, metadata !3, metadata !3, metadata !""} ; [ DW_TAG_compile_unit ] [/home/nlewycky/hello.cc] [DW_LANG_C_plus_plus] !1 = metadata !{i32 786473, metadata !2} ; [ DW_TAG_file_type ] [/home/nlewycky/hello.cc] !2 = metadata !{metadata !"hello.cc", metadata !"/home/nlewycky"} !3 = metadata !{i32 0} diff --git a/test/Transforms/GVN/unreachable_block_infinite_loop.ll b/test/Transforms/GVN/unreachable_block_infinite_loop.ll new file mode 100644 index 000000000000..fe335ced5c37 --- /dev/null +++ b/test/Transforms/GVN/unreachable_block_infinite_loop.ll @@ -0,0 +1,14 @@ +; RUN: opt -memdep -gvn -disable-output + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0" + +define i32 @test2() nounwind ssp { +entry: + ret i32 0 + +unreachable_block: + %a = add i32 %a, 1 + ret i32 %a +} + diff --git a/test/Transforms/GlobalDCE/complex-constantexpr.ll b/test/Transforms/GlobalDCE/complex-constantexpr.ll new file mode 100644 index 000000000000..4bf1aeee709b --- /dev/null +++ b/test/Transforms/GlobalDCE/complex-constantexpr.ll @@ -0,0 +1,97 @@ +; RUN: opt -O2 -disable-output < %s +; PR15714 + +%struct.ham = type { i32 } + +@global5 = common global i32 0, align 4 +@global6 = common global i32 0, align 4 +@global7 = common global i32 0, align 4 +@global = common global i32 0, align 4 +@global8 = common global %struct.ham zeroinitializer, align 4 +@global9 = common global i32 0, align 4 +@global10 = common global i32 0, align 4 +@global11 = common global i32 0, align 4 + +define void @zot12() { +bb: + store i32 0, i32* @global5, align 4 + store i32 0, i32* @global6, align 4 + br label %bb2 + +bb1: ; preds = %bb11 + %tmp = load i32* @global5, align 4 + br label %bb2 + +bb2: ; preds = %bb1, %bb + %tmp3 = phi i32 [ %tmp, %bb1 ], [ 0, %bb ] + %tmp4 = xor i32 %tmp3, zext (i1 icmp ne (i64 ptrtoint (i32* @global5 to i64), i64 1) to i32) + store i32 %tmp4, i32* @global5, align 4 + %tmp5 = icmp eq i32 %tmp3, zext (i1 icmp ne (i64 ptrtoint (i32* @global5 to i64), i64 1) to i32) + br i1 %tmp5, label %bb8, label %bb6 + +bb6: ; preds = %bb2 + %tmp7 = tail call i32 @quux13() + br label %bb8 + +bb8: ; preds = %bb6, %bb2 + %tmp9 = load i32* @global7, align 4 + %tmp10 = icmp eq i32 %tmp9, 0 + br i1 %tmp10, label %bb11, label %bb15 + +bb11: ; preds = %bb8 + %tmp12 = load i32* @global6, align 4 + %tmp13 = add nsw i32 %tmp12, 1 + store i32 %tmp13, i32* @global6, align 4 + %tmp14 = icmp slt i32 %tmp13, 42 + br i1 %tmp14, label %bb1, label %bb15 + +bb15: ; preds = %bb11, %bb8 + ret void +} + +define i32 @quux13() { +bb: + store i32 1, i32* @global5, align 4 + ret i32 1 +} + +define void @wombat() { +bb: + tail call void @zot12() + ret void +} + +define void @wombat14() { +bb: + tail call void @blam() + ret void +} + +define void @blam() { +bb: + store i32 ptrtoint (i32* @global to i32), i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4 + store i32 0, i32* @global9, align 4 + %tmp = load i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4 + br label %bb1 + +bb1: ; preds = %bb1, %bb + %tmp2 = phi i32 [ 0, %bb ], [ %tmp11, %bb1 ] + %tmp3 = phi i32 [ %tmp, %bb ], [ %tmp10, %bb1 ] + %tmp4 = icmp sgt i32 %tmp3, 0 + %tmp5 = zext i1 %tmp4 to i32 + %tmp6 = urem i32 %tmp5, 5 + %tmp7 = mul i32 %tmp3, -80 + %tmp8 = or i32 %tmp7, %tmp6 + %tmp9 = icmp eq i32 %tmp8, 0 + %tmp10 = zext i1 %tmp9 to i32 + %tmp11 = add nsw i32 %tmp2, 1 + %tmp12 = icmp eq i32 %tmp11, 20 + br i1 %tmp12, label %bb13, label %bb1 + +bb13: ; preds = %bb1 + store i32 %tmp10, i32* getelementptr inbounds (%struct.ham* @global8, i64 0, i32 0), align 4 + store i32 0, i32* @global10, align 4 + store i32 %tmp6, i32* @global11, align 4 + store i32 20, i32* @global9, align 4 + ret void +} diff --git a/test/Transforms/GlobalDCE/indirectbr.ll b/test/Transforms/GlobalDCE/indirectbr.ll new file mode 100644 index 000000000000..90f1ae44b1ac --- /dev/null +++ b/test/Transforms/GlobalDCE/indirectbr.ll @@ -0,0 +1,18 @@ +; RUN: opt -S -globaldce < %s | FileCheck %s + +@L = internal unnamed_addr constant [3 x i8*] [i8* blockaddress(@test1, %L1), i8* blockaddress(@test1, %L2), i8* null], align 16 + +; CHECK: @L = internal unnamed_addr constant + +define void @test1(i32 %idx) { +entry: + br label %L1 + +L1: + %arrayidx = getelementptr inbounds [3 x i8*]* @L, i32 0, i32 %idx + %l = load i8** %arrayidx + indirectbr i8* %l, [label %L1, label %L2] + +L2: + ret void +} diff --git a/test/Transforms/GlobalOpt/alias-used.ll b/test/Transforms/GlobalOpt/alias-used.ll new file mode 100644 index 000000000000..f91579bf0507 --- /dev/null +++ b/test/Transforms/GlobalOpt/alias-used.ll @@ -0,0 +1,42 @@ +; RUN: opt < %s -globalopt -S | FileCheck %s + +@c = global i8 42 + +@llvm.used = appending global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca], section "llvm.metadata" +; CHECK: @llvm.used = appending global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca], section "llvm.metadata" + +@llvm.compiler_used = appending global [2 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @fa3 to i8*)], section "llvm.metadata" + +@sameAsUsed = global [3 x i8*] [i8* bitcast (void ()* @fa to i8*), i8* bitcast (void ()* @f to i8*), i8* @ca] +; CHECK: @sameAsUsed = global [3 x i8*] [i8* bitcast (void ()* @f to i8*), i8* bitcast (void ()* @f to i8*), i8* @c] + +@other = global i32* bitcast (void ()* @fa to i32*) +; CHECK: @other = global i32* bitcast (void ()* @f to i32*) + +@fa = alias internal void ()* @f +; CHECK: @fa = alias internal void ()* @f + +@fa2 = alias internal void ()* @f +; CHECK-NOT: @fa2 + +@fa3 = alias internal void ()* @f +; CHECK: @fa3 + +@ca = alias internal i8* @c +; CHECK: @ca = alias internal i8* @c + +define void @f() { + ret void +} + +define i8* @g() { + ret i8* bitcast (void ()* @fa to i8*); +} + +define i8* @g2() { + ret i8* bitcast (void ()* @fa2 to i8*); +} + +define i8* @h() { + ret i8* @ca +} diff --git a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll index 2ec0a32ffcbf..ba83fe9ec0ad 100644 --- a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll +++ b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll @@ -20,10 +20,10 @@ entry: define void @fn4() nounwind uwtable ssp { entry: - %0 = load i32* @d, align 4, !tbaa !0 + %0 = load i32* @d, align 4 %cmp = icmp eq i32 %0, 0 %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @c, align 4, !tbaa !0 + store i32 %conv, i32* @c, align 4 tail call void @fn3(i32 %conv) nounwind ret void } @@ -31,15 +31,15 @@ entry: define void @fn3(i32 %p1) nounwind uwtable ssp { entry: %and = and i32 %p1, 8 - store i32 %and, i32* @e, align 4, !tbaa !0 + store i32 %and, i32* @e, align 4 %sub = add nsw i32 %and, -1 - store i32 %sub, i32* @f, align 4, !tbaa !0 - %0 = load i32* @a, align 4, !tbaa !0 + store i32 %sub, i32* @f, align 4 + %0 = load i32* @a, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %1 = load i32* @b, align 4, !tbaa !0 + %1 = load i32* @b, align 4 %.lobit = lshr i32 %1, 31 %2 = trunc i32 %.lobit to i8 %.not = xor i8 %2, 1 @@ -55,7 +55,3 @@ if.end: ; preds = %if.else, %if.then store i32 %storemerge, i32* @b, align 4 ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/InstCombine/add4.ll b/test/Transforms/InstCombine/add4.ll new file mode 100644 index 000000000000..0fc0a6c1ac26 --- /dev/null +++ b/test/Transforms/InstCombine/add4.ll @@ -0,0 +1,58 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +;; Target triple for gep raising case below. +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + +define float @test1(float %A, float %B, i1 %C) { +EntryBlock: + ;; A*(1 - uitofp i1 C) -> select C, 0, A + %cf = uitofp i1 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + ret float %p1 +; CHECK: @test1 +; CHECK: select i1 %C, float -0.000000e+00, float %A +} + +define float @test2(float %A, float %B, i1 %C) { +EntryBlock: + ;; B*(uitofp i1 C) -> select C, B, 0 + %cf = uitofp i1 %C to float + %p2 = fmul fast float %B, %cf + ret float %p2 +; CHECK: @test2 +; CHECK: select i1 %C, float %B, float -0.000000e+00 +} + +define float @test3(float %A, float %B, i1 %C) { +EntryBlock: + ;; A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B + %cf = uitofp i1 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + %p2 = fmul fast float %B, %cf + %s1 = fadd fast float %p1, %p2 + ret float %s1 +; CHECK: @test3 +; CHECK: select i1 %C, float %B, float %A +} + +; PR15952 +define float @test4(float %A, float %B, i32 %C) { + %cf = uitofp i32 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + ret float %p1 +; CHECK: @test4 +; CHECK: uitofp +} + +define float @test5(float %A, float %B, i32 %C) { + %cf = uitofp i32 %C to float + %p2 = fmul fast float %B, %cf + ret float %p2 +; CHECK: @test5 +; CHECK: uitofp +} + diff --git a/test/Transforms/InstCombine/and-fcmp.ll b/test/Transforms/InstCombine/and-fcmp.ll index 40c44c09a8c0..a398307f869e 100644 --- a/test/Transforms/InstCombine/and-fcmp.ll +++ b/test/Transforms/InstCombine/and-fcmp.ll @@ -77,3 +77,24 @@ define zeroext i8 @t7(float %x, float %y) nounwind { ; CHECK: fcmp uno ; CHECK-NOT: fcmp ult } + +; PR15737 +define i1 @t8(float %a, double %b) { + %cmp = fcmp ord float %a, 0.000000e+00 + %cmp1 = fcmp ord double %b, 0.000000e+00 + %and = and i1 %cmp, %cmp1 + ret i1 %and +; CHECK: t8 +; CHECK: fcmp ord +; CHECK: fcmp ord +} + +define <2 x i1> @t9(<2 x float> %a, <2 x double> %b) { + %cmp = fcmp ord <2 x float> %a, zeroinitializer + %cmp1 = fcmp ord <2 x double> %b, zeroinitializer + %and = and <2 x i1> %cmp, %cmp1 + ret <2 x i1> %and +; CHECK: t9 +; CHECK: fcmp ord +; CHECK: fcmp ord +} diff --git a/test/Transforms/InstCombine/apint-shift-simplify.ll b/test/Transforms/InstCombine/apint-shift-simplify.ll index 818ae6659b26..14e895ad4bf6 100644 --- a/test/Transforms/InstCombine/apint-shift-simplify.ll +++ b/test/Transforms/InstCombine/apint-shift-simplify.ll @@ -1,11 +1,14 @@ -; RUN: opt < %s -instcombine -S | \ -; RUN: egrep "shl|lshr|ashr" | count 3 +; RUN: opt < %s -instcombine -S | FileCheck %s define i41 @test0(i41 %A, i41 %B, i41 %C) { %X = shl i41 %A, %C %Y = shl i41 %B, %C %Z = and i41 %X, %Y ret i41 %Z +; CHECK: @test0 +; CHECK-NEXT: and i41 %A, %B +; CHECK-NEXT: shl i41 +; CHECK-NEXT: ret } define i57 @test1(i57 %A, i57 %B, i57 %C) { @@ -13,6 +16,10 @@ define i57 @test1(i57 %A, i57 %B, i57 %C) { %Y = lshr i57 %B, %C %Z = or i57 %X, %Y ret i57 %Z +; CHECK: @test1 +; CHECK-NEXT: or i57 %A, %B +; CHECK-NEXT: lshr i57 +; CHECK-NEXT: ret } define i49 @test2(i49 %A, i49 %B, i49 %C) { @@ -20,4 +27,8 @@ define i49 @test2(i49 %A, i49 %B, i49 %C) { %Y = ashr i49 %B, %C %Z = xor i49 %X, %Y ret i49 %Z +; CHECK: @test2 +; CHECK-NEXT: xor i49 %A, %B +; CHECK-NEXT: ashr i49 +; CHECK-NEXT: ret } diff --git a/test/Transforms/InstCombine/debuginfo.ll b/test/Transforms/InstCombine/debuginfo.ll index cdbcd865117c..a9e3de3b3f7b 100644 --- a/test/Transforms/InstCombine/debuginfo.ll +++ b/test/Transforms/InstCombine/debuginfo.ll @@ -11,18 +11,18 @@ entry: %__dest.addr = alloca i8*, align 8 %__val.addr = alloca i32, align 4 %__len.addr = alloca i64, align 8 - store i8* %__dest, i8** %__dest.addr, align 8, !tbaa !1 + store i8* %__dest, i8** %__dest.addr, align 8 ; CHECK-NOT: call void @llvm.dbg.declare ; CHECK: call void @llvm.dbg.value call void @llvm.dbg.declare(metadata !{i8** %__dest.addr}, metadata !0), !dbg !16 - store i32 %__val, i32* %__val.addr, align 4, !tbaa !17 + store i32 %__val, i32* %__val.addr, align 4 call void @llvm.dbg.declare(metadata !{i32* %__val.addr}, metadata !7), !dbg !18 - store i64 %__len, i64* %__len.addr, align 8, !tbaa !19 + store i64 %__len, i64* %__len.addr, align 8 call void @llvm.dbg.declare(metadata !{i64* %__len.addr}, metadata !9), !dbg !20 - %tmp = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 - %tmp1 = load i32* %__val.addr, align 4, !dbg !21, !tbaa !17 - %tmp2 = load i64* %__len.addr, align 8, !dbg !21, !tbaa !19 - %tmp3 = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 + %tmp = load i8** %__dest.addr, align 8, !dbg !21 + %tmp1 = load i32* %__val.addr, align 4, !dbg !21 + %tmp2 = load i64* %__len.addr, align 8, !dbg !21 + %tmp3 = load i8** %__dest.addr, align 8, !dbg !21 %0 = call i64 @llvm.objectsize.i64(i8* %tmp3, i1 false), !dbg !21 %call = call i8* @foo(i8* %tmp, i32 %tmp1, i64 %tmp2, i64 %0), !dbg !21 ret i8* %call, !dbg !21 @@ -43,13 +43,8 @@ entry: !10 = metadata !{i32 589846, metadata !3, metadata !"size_t", metadata !2, i32 80, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_typedef ] !11 = metadata !{i32 589846, metadata !3, metadata !"__darwin_size_t", metadata !2, i32 90, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ] !12 = metadata !{i32 786468, metadata !3, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!13 = metadata !{metadata !"any pointer", metadata !14} -!14 = metadata !{metadata !"omnipotent char", metadata !15} -!15 = metadata !{metadata !"Simple C/C++ TBAA", null} !16 = metadata !{i32 78, i32 28, metadata !1, null} -!17 = metadata !{metadata !"int", metadata !14} !18 = metadata !{i32 78, i32 40, metadata !1, null} -!19 = metadata !{metadata !"long", metadata !14} !20 = metadata !{i32 78, i32 54, metadata !1, null} !21 = metadata !{i32 80, i32 3, metadata !22, null} !22 = metadata !{i32 786443, metadata !23, i32 80, i32 3, metadata !2, i32 7} ; [ DW_TAG_lexical_block ] diff --git a/test/Transforms/InstCombine/fprintf-1.ll b/test/Transforms/InstCombine/fprintf-1.ll index 39d86b4588cc..e1dc191bd700 100644 --- a/test/Transforms/InstCombine/fprintf-1.ll +++ b/test/Transforms/InstCombine/fprintf-1.ll @@ -78,3 +78,12 @@ define void @test_no_simplify2(%FILE* %fp, double %d) { ret void ; CHECK-NEXT: ret void } + +define i32 @test_no_simplify3(%FILE* %fp) { +; CHECK: @test_no_simplify3 + %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0 + %1 = call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt) +; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0)) + ret i32 %1 +; CHECK-NEXT: ret i32 %1 +} diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 446c0e01dcaa..c912a576c3d2 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -886,3 +886,93 @@ define i1 @icmp_mul0_ne0(i32 %x) { %cmp = icmp ne i32 %mul, 0 ret i1 %cmp } + +; CHECK: @icmp_sub1_sge +; CHECK-NEXT: icmp sgt i32 %x, %y +define i1 @icmp_sub1_sge(i32 %x, i32 %y) { + %sub = add nsw i32 %x, -1 + %cmp = icmp sge i32 %sub, %y + ret i1 %cmp +} + +; CHECK: @icmp_add1_sgt +; CHECK-NEXT: icmp sge i32 %x, %y +define i1 @icmp_add1_sgt(i32 %x, i32 %y) { + %add = add nsw i32 %x, 1 + %cmp = icmp sgt i32 %add, %y + ret i1 %cmp +} + +; CHECK: @icmp_sub1_slt +; CHECK-NEXT: icmp sle i32 %x, %y +define i1 @icmp_sub1_slt(i32 %x, i32 %y) { + %sub = add nsw i32 %x, -1 + %cmp = icmp slt i32 %sub, %y + ret i1 %cmp +} + +; CHECK: @icmp_add1_sle +; CHECK-NEXT: icmp slt i32 %x, %y +define i1 @icmp_add1_sle(i32 %x, i32 %y) { + %add = add nsw i32 %x, 1 + %cmp = icmp sle i32 %add, %y + ret i1 %cmp +} + +; CHECK: @icmp_add20_sge_add57 +; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add nsw i32 %y, 37 +; CHECK-NEXT: icmp sle i32 [[ADD]], %x +define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) { + %1 = add nsw i32 %x, 20 + %2 = add nsw i32 %y, 57 + %cmp = icmp sge i32 %1, %2 + ret i1 %cmp +} + +; CHECK: @icmp_sub57_sge_sub20 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add nsw i32 %x, -37 +; CHECK-NEXT: icmp sge i32 [[SUB]], %y +define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) { + %1 = add nsw i32 %x, -57 + %2 = add nsw i32 %y, -20 + %cmp = icmp sge i32 %1, %2 + ret i1 %cmp +} + +; CHECK: @icmp_and_shl_neg_ne_0 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { + %neg = xor i32 %A, -1 + %shl = shl i32 1, %B + %and = and i32 %shl, %neg + %cmp = icmp ne i32 %and, 0 + ret i1 %cmp +} + +; CHECK: @icmp_and_shl_neg_eq_0 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { + %neg = xor i32 %A, -1 + %shl = shl i32 1, %B + %and = and i32 %shl, %neg + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +; CHECK: @icmp_add_and_shr_ne_0 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, 240 +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 224 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_add_and_shr_ne_0(i32 %X) { + %shr = lshr i32 %X, 4 + %and = and i32 %shr, 15 + %add = add i32 %and, -14 + %tobool = icmp ne i32 %add, 0 + ret i1 %tobool +} diff --git a/test/Transforms/InstCombine/load-cmp.ll b/test/Transforms/InstCombine/load-cmp.ll index d88188e4109c..869215cb58d4 100644 --- a/test/Transforms/InstCombine/load-cmp.ll +++ b/test/Transforms/InstCombine/load-cmp.ll @@ -100,8 +100,8 @@ define i1 @test8(i32 %X) { %S = icmp eq i16 %R, 0 ret i1 %S ; CHECK: @test8 -; CHECK-NEXT: add i32 %X, -8 -; CHECK-NEXT: icmp ult i32 {{.*}}, 2 +; CHECK-NEXT: and i32 %X, -2 +; CHECK-NEXT: icmp eq i32 {{.*}}, 8 ; CHECK-NEXT: ret i1 } diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll index 0ead9d123749..122c6501a3f5 100644 --- a/test/Transforms/InstCombine/objsize.ll +++ b/test/Transforms/InstCombine/objsize.ll @@ -257,114 +257,6 @@ return: ret i32 7 } -declare noalias i8* @valloc(i32) nounwind - -; CHECK: @test14 -; CHECK: ret i32 6 -define i32 @test14(i32 %a) nounwind { - switch i32 %a, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %call = tail call noalias i8* @malloc(i32 6) nounwind - br label %sw.epilog - -sw.bb1: - %call2 = tail call noalias i8* @calloc(i32 3, i32 2) nounwind - br label %sw.epilog - -sw.default: - %call3 = tail call noalias i8* @valloc(i32 6) nounwind - br label %sw.epilog - -sw.epilog: - %b.0 = phi i8* [ %call3, %sw.default ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ] - %1 = tail call i32 @llvm.objectsize.i32(i8* %b.0, i1 false) - ret i32 %1 -} - -; CHECK: @test15 -; CHECK: llvm.objectsize -define i32 @test15(i32 %a) nounwind { - switch i32 %a, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %call = tail call noalias i8* @malloc(i32 3) nounwind - br label %sw.epilog - -sw.bb1: - %call2 = tail call noalias i8* @calloc(i32 2, i32 1) nounwind - br label %sw.epilog - -sw.default: - %call3 = tail call noalias i8* @valloc(i32 3) nounwind - br label %sw.epilog - -sw.epilog: - %b.0 = phi i8* [ %call3, %sw.default ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ] - %1 = tail call i32 @llvm.objectsize.i32(i8* %b.0, i1 false) - ret i32 %1 -} - -; CHECK: @test16 -; CHECK: llvm.objectsize -define i32 @test16(i8* %a, i32 %n) nounwind { - %b = alloca [5 x i8], align 1 - %c = alloca [5 x i8], align 1 - switch i32 %n, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %bp = bitcast [5 x i8]* %b to i8* - br label %sw.epilog - -sw.bb1: - %cp = bitcast [5 x i8]* %c to i8* - br label %sw.epilog - -sw.default: - br label %sw.epilog - -sw.epilog: - %phi = phi i8* [ %a, %sw.default ], [ %cp, %sw.bb1 ], [ %bp, %sw.bb ] - %sz = call i32 @llvm.objectsize.i32(i8* %phi, i1 false) - ret i32 %sz -} - -; CHECK: @test17 -; CHECK: ret i32 5 -define i32 @test17(i32 %n) nounwind { - %b = alloca [5 x i8], align 1 - %c = alloca [5 x i8], align 1 - %bp = bitcast [5 x i8]* %b to i8* - switch i32 %n, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - br label %sw.epilog - -sw.bb1: - %cp = bitcast [5 x i8]* %c to i8* - br label %sw.epilog - -sw.default: - br label %sw.epilog - -sw.epilog: - %phi = phi i8* [ %bp, %sw.default ], [ %cp, %sw.bb1 ], [ %bp, %sw.bb ] - %sz = call i32 @llvm.objectsize.i32(i8* %phi, i1 false) - ret i32 %sz -} - @globalalias = alias internal [60 x i8]* @a ; CHECK: @test18 diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll index bde2a54048ad..7226bd93996f 100644 --- a/test/Transforms/InstCombine/or.ll +++ b/test/Transforms/InstCombine/or.ll @@ -178,12 +178,12 @@ define i1 @test18(i32 %A) { define i1 @test19(i32 %A) { %B = icmp eq i32 %A, 50 %C = icmp eq i32 %A, 51 - ;; (A-50) < 2 + ;; (A&-2) == 50 %D = or i1 %B, %C ret i1 %D ; CHECK: @test19 -; CHECK: add i32 -; CHECK: icmp ult +; CHECK: and i32 +; CHECK: icmp eq ; CHECK: ret i1 } diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index cc3aacdce3c8..c72a6f7c49c6 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -863,3 +863,125 @@ while.body: ; CHECK: @test64 ; CHECK-NOT: select } + +; CHECK: @select_icmp_eq_and_1_0_or_2 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) { + %and = and i32 %x, 1 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_and_32_0_or_8 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) { + %and = and i32 %x, 32 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 8 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_4096_or_4096 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_and_4096_0_or_4096 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_0_and_1_or_1 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i64 %x, 1 +; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = trunc i64 [[AND]] to i32 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_0_and_1_or_1(i64 %x, i32 %y) { + %and = and i64 %x, 1 + %cmp = icmp eq i64 %and, 0 + %or = or i32 %y, 1 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_4096_or_32 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 32 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_32_or_4096 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 32 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_1073741824_or_8 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 27 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8 +; CHECK-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i32 [[AND]] to i8 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i8 [[TRUNC]], 8 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i8 [[XOR]], %y +; CHECK-NEXT: ret i8 [[OR]] +define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) { + %and = and i32 %x, 1073741824 + %cmp = icmp ne i32 0, %and + %or = or i8 %y, 8 + %select = select i1 %cmp, i8 %y, i8 %or + ret i8 %select +} + +; CHECK: @select_icmp_ne_0_and_8_or_1073741824 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i8 %x, 8 +; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i8 [[AND]] to i32 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl nuw nsw i32 [[ZEXT]], 27 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[SHL]], 1073741824 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) { + %and = and i8 %x, 8 + %cmp = icmp ne i8 0, %and + %or = or i32 %y, 1073741824 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} diff --git a/test/Transforms/InstCombine/sub-xor.ll b/test/Transforms/InstCombine/sub-xor.ll index 279e4aca9de4..1d14852bc803 100644 --- a/test/Transforms/InstCombine/sub-xor.ll +++ b/test/Transforms/InstCombine/sub-xor.ll @@ -35,3 +35,13 @@ define i32 @test3(i32 %x) nounwind { ; CHECK-NEXT: sub i32 73, %and ; CHECK-NEXT: ret } + +define i32 @test4(i32 %x) nounwind { + %sub = xor i32 %x, 2147483648 + %add = add i32 %sub, 42 + ret i32 %add + +; CHECK: @test4 +; CHECK-NEXT: add i32 %x, -2147483606 +; CHECK-NEXT: ret +} diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll index 2d90750a2f1e..0019a57627cb 100644 --- a/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -196,7 +196,7 @@ define <4 x float> @test_select(float %f, float %g) { ; CHECK-NOT: insertelement ; CHECK: %a3 = insertelement <4 x float> %a0, float 3.000000e+00, i32 3 ; CHECK-NOT: insertelement -; CHECK: shufflevector <4 x float> %a3, <4 x float> <float undef, float 4.000000e+00, float 5.000000e+00, float undef>, <4 x i32> <i32 0, i32 5, i32 6, i32 3> +; CHECK: %ret = select <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %a3, <4 x float> <float undef, float 4.000000e+00, float 5.000000e+00, float undef> %a0 = insertelement <4 x float> undef, float %f, i32 0 %a1 = insertelement <4 x float> %a0, float 1.000000e+00, i32 1 %a2 = insertelement <4 x float> %a1, float 2.000000e+00, i32 2 diff --git a/test/Transforms/InstCombine/vec_extract_2elts.ll b/test/Transforms/InstCombine/vec_extract_2elts.ll new file mode 100644 index 000000000000..5972340d60a9 --- /dev/null +++ b/test/Transforms/InstCombine/vec_extract_2elts.ll @@ -0,0 +1,12 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @test(<4 x i32> %v, i64 *%r1, i64 *%r2) { +;CHECK: %1 = extractelement <4 x i32> %v, i32 0 +;CHECK: %2 = zext i32 %1 to i64 + %1 = zext <4 x i32> %v to <4 x i64> + %2 = extractelement <4 x i64> %1, i32 0 + store i64 %2, i64 *%r1 + store i64 %2, i64 *%r2 + ret void +} + diff --git a/test/Transforms/InstCombine/vec_extract_var_elt.ll b/test/Transforms/InstCombine/vec_extract_var_elt.ll new file mode 100644 index 000000000000..3c982873e288 --- /dev/null +++ b/test/Transforms/InstCombine/vec_extract_var_elt.ll @@ -0,0 +1,18 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @test (float %b, <8 x float> * %p) { +; CHECK: extractelement +; CHECK: fptosi + %1 = load <8 x float> * %p + %2 = bitcast <8 x float> %1 to <8 x i32> + %3 = bitcast <8 x i32> %2 to <8 x float> + %a = fptosi <8 x float> %3 to <8 x i32> + %4 = fptosi float %b to i32 + %5 = add i32 %4, -2 + %6 = extractelement <8 x i32> %a, i32 %5 + %7 = insertelement <8 x i32> undef, i32 %6, i32 7 + %8 = sitofp <8 x i32> %7 to <8 x float> + store <8 x float> %8, <8 x float>* %p + ret void +} + diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll new file mode 100644 index 000000000000..2f10fc2c1ed2 --- /dev/null +++ b/test/Transforms/InstCombine/vec_phi_extract.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @f(i64 %val, i32 %limit, i32 *%ptr) { +;CHECK: %0 = trunc i64 +;CHECK: %1 = phi i32 +entry: + %tempvector = insertelement <16 x i64> undef, i64 %val, i32 0 + %vector = shufflevector <16 x i64> %tempvector, <16 x i64> undef, <16 x i32> zeroinitializer + %0 = add <16 x i64> %vector, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15> + %1 = trunc <16 x i64> %0 to <16 x i32> + br label %loop + +loop: + %2 = phi <16 x i32> [ %1, %entry ], [ %inc, %loop ] + %elt = extractelement <16 x i32> %2, i32 0 + %end = icmp ult i32 %elt, %limit + %3 = add i32 10, %elt + %4 = sext i32 %elt to i64 + %5 = getelementptr i32* %ptr, i64 %4 + store i32 %3, i32* %5 + %inc = add <16 x i32> %2, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> + br i1 %end, label %loop, label %ret + +ret: + ret void +} + diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 14f532195d7c..8f78c2e6bd50 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -153,46 +153,3 @@ define <8 x i8> @test12a(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind { ret <8 x i8> %tmp3 } -; We should form a shuffle out of a select with constant condition. -define <4 x i16> @test13a(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13a -; CHECK-NEXT: shufflevector <4 x i16> %lhs, <4 x i16> %rhs, <4 x i32> <i32 0, i32 5, i32 2, i32 7> -; CHECK-NEXT: ret - %A = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13b(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13b -; CHECK-NEXT: ret <4 x i16> %lhs - %A = select <4 x i1> <i1 true, i1 undef, i1 true, i1 true>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13c(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13c -; CHECK-NEXT: shufflevector <4 x i16> %lhs, <4 x i16> %rhs, <4 x i32> <i32 0, i32 undef, i32 2, i32 7> -; CHECK-NEXT: ret - %A = select <4 x i1> <i1 true, i1 undef, i1 true, i1 false>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13d(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13d -; CHECK: select -; CHECK-NEXT: ret - %A = select <4 x i1> <i1 true, i1 icmp ugt (<4 x i16>(<4 x i16>, <4 x i16>)* @test13a, <4 x i16>(<4 x i16>, <4 x i16>)* @test13b), i1 true, i1 false>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13e(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13e -; CHECK-NEXT: ret <4 x i16> %rhs - %A = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} diff --git a/test/Transforms/InstSimplify/2013-04-19-ConstantFoldingCrash.ll b/test/Transforms/InstSimplify/2013-04-19-ConstantFoldingCrash.ll new file mode 100644 index 000000000000..164751784a65 --- /dev/null +++ b/test/Transforms/InstSimplify/2013-04-19-ConstantFoldingCrash.ll @@ -0,0 +1,9 @@ +; RUN: opt < %s -instsimplify + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; PR15791 +define <2 x i64> @test1() { + %a = and <2 x i64> undef, bitcast (<4 x i32> <i32 undef, i32 undef, i32 undef, i32 2147483647> to <2 x i64>) + ret <2 x i64> %a +} diff --git a/test/Transforms/InstSimplify/floating-point-arithmetic.ll b/test/Transforms/InstSimplify/floating-point-arithmetic.ll index f9c364cade36..91ce26324b81 100644 --- a/test/Transforms/InstSimplify/floating-point-arithmetic.ll +++ b/test/Transforms/InstSimplify/floating-point-arithmetic.ll @@ -14,7 +14,7 @@ define float @fsub_0_0_x(float %a) { ; CHECK: @fsub_x_0 define float @fsub_x_0(float %a) { %ret = fsub float %a, 0.0 -; CHECK ret float %a +; CHECK: ret float %a ret float %ret } @@ -22,7 +22,7 @@ define float @fsub_x_0(float %a) { ; CHECK: @fadd_x_n0 define float @fadd_x_n0(float %a) { %ret = fadd float %a, -0.0 -; CHECK ret float %a +; CHECK: ret float %a ret float %ret } diff --git a/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll index e80bae578a93..86a1321c3543 100644 --- a/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll +++ b/test/Transforms/JumpThreading/2011-04-14-InfLoop.ll @@ -15,7 +15,7 @@ for.cond1177: br i1 %cmp1179, label %for.cond1177, label %land.rhs1320 land.rhs1320: - %tmp1324 = load volatile i64* getelementptr inbounds (%0* @g_338, i64 0, i32 2), align 1, !tbaa !0 + %tmp1324 = load volatile i64* getelementptr inbounds (%0* @g_338, i64 0, i32 2), align 1 br label %if.end.i if.end.i: @@ -25,7 +25,3 @@ if.end.i: return: ret void } - -!0 = metadata !{metadata !"long long", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/LoopRotate/simplifylatch.ll b/test/Transforms/LoopRotate/simplifylatch.ll index f4227245f74b..037bb2042f95 100644 --- a/test/Transforms/LoopRotate/simplifylatch.ll +++ b/test/Transforms/LoopRotate/simplifylatch.ll @@ -1,4 +1,4 @@ -; RUN: opt -S < %s -loop-rotate -verify-dom-info -verify-loop-info | FileCheck %s +; RUN: opt -S < %s -loop-rotate -licm -verify-dom-info -verify-loop-info | FileCheck %s ; PR2624 unroll multiple exits @mode_table = global [4 x i32] zeroinitializer ; <[4 x i32]*> [#uses=1] @@ -37,3 +37,40 @@ bb5: ; preds = %bb2 declare i32 @fegetround() declare void @raise_exception() noreturn + +;CHECK: for.body.lr.ph: +;CHECK-NEXT: %arrayidx1 = getelementptr inbounds i8* %CurPtr, i64 0 +;CHECK-NEXT: %0 = load i8* %arrayidx1, align 1 +;CHECK-NEXT: %conv2 = sext i8 %0 to i32 +;CHECK-NEXT: br label %for.body + +define i32 @foo(i8* %CurPtr, i32 %a) #0 { +entry: + br label %for.cond + +for.cond: ; preds = %for.inc, %entry + %i.0 = phi i32 [ 1, %entry ], [ %inc, %for.inc ] + %cmp = icmp ne i32 %i.0, %a + br i1 %cmp, label %for.body, label %return + +for.body: ; preds = %for.cond + %idxprom = zext i32 %i.0 to i64 + %arrayidx = getelementptr inbounds i8* %CurPtr, i64 %idxprom + %0 = load i8* %arrayidx, align 1 + %conv = sext i8 %0 to i32 + %arrayidx1 = getelementptr inbounds i8* %CurPtr, i64 0 + %1 = load i8* %arrayidx1, align 1 + %conv2 = sext i8 %1 to i32 + %cmp3 = icmp ne i32 %conv, %conv2 + br i1 %cmp3, label %return, label %for.inc + +for.inc: ; preds = %for.body + %inc = add i32 %i.0, 1 + br label %for.cond + +return: ; preds = %for.cond, %for.body + %retval.0 = phi i32 [ 0, %for.body ], [ 1, %for.cond ] + ret i32 %retval.0 +} + +attributes #0 = { nounwind uwtable } diff --git a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll index a1222083abc9..8bac639ae559 100644 --- a/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll +++ b/test/Transforms/LoopStrengthReduce/2012-07-13-ExpandUDiv.ll @@ -18,11 +18,11 @@ define i32 @main() nounwind uwtable ssp { entry: %l_2 = alloca [1 x i32], align 4 %arrayidx = getelementptr inbounds [1 x i32]* %l_2, i64 0, i64 0 - store i32 0, i32* %arrayidx, align 4, !tbaa !0 - %tmp = load i32* @g_3, align 4, !tbaa !0 + store i32 0, i32* %arrayidx, align 4 + %tmp = load i32* @g_3, align 4 %idxprom = sext i32 %tmp to i64 %arrayidx1 = getelementptr inbounds [1 x i32]* %l_2, i64 0, i64 %idxprom - %tmp1 = load i32* %arrayidx1, align 4, !tbaa !0 + %tmp1 = load i32* %arrayidx1, align 4 %conv.i.i = and i32 %tmp1, 65535 %tobool.i.i.i = icmp ne i32 %tmp, 0 br label %codeRepl @@ -48,7 +48,7 @@ for.cond.i.i.us: ; preds = %for.inc.i.i.us, %co for.inc.i.i.us: ; preds = %for.body.i.i.us %add.i.i.us = add nsw i32 %tmp2, 1 - store i32 %add.i.i.us, i32* @g_752, align 4, !tbaa !0 + store i32 %add.i.i.us, i32* @g_752, align 4 br label %for.cond.i.i.us for.body.i.i.us: ; preds = %codeRepl5.us @@ -78,13 +78,9 @@ for.body.i.i: ; preds = %codeRepl5 for.inc.i.i: ; preds = %for.body.i.i %add.i.i = add nsw i32 %tmp3, 1 - store i32 %add.i.i, i32* @g_752, align 4, !tbaa !0 + store i32 %add.i.i, i32* @g_752, align 4 br label %for.cond.i.i func_4.exit: ; No predecessors! ret i32 0 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll index b5124ea6f30d..5d728b528ea5 100644 --- a/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll +++ b/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll @@ -50,7 +50,7 @@ declare %s* @getstruct() nounwind ; CHECK: ldr{{.*}}lsl #2 define i32 @main() nounwind ssp { entry: - %v0 = load i32* @ncol, align 4, !tbaa !0 + %v0 = load i32* @ncol, align 4 %v1 = tail call i32* @getptr() nounwind %cmp10.i = icmp eq i32 %v0, 0 br label %while.cond.outer @@ -64,12 +64,12 @@ while.cond: br label %while.body while.body: - %v3 = load i32* @ncol, align 4, !tbaa !0 + %v3 = load i32* @ncol, align 4 br label %end_of_chain end_of_chain: %state.i = getelementptr inbounds %s* %call18, i32 0, i32 0 - %v4 = load i32** %state.i, align 4, !tbaa !3 + %v4 = load i32** %state.i, align 4 br label %while.cond.i.i while.cond.i.i: @@ -80,9 +80,9 @@ while.cond.i.i: land.rhs.i.i: %arrayidx.i.i = getelementptr inbounds i32* %v4, i32 %dec.i.i - %v5 = load i32* %arrayidx.i.i, align 4, !tbaa !0 + %v5 = load i32* %arrayidx.i.i, align 4 %arrayidx1.i.i = getelementptr inbounds i32* %v1, i32 %dec.i.i - %v6 = load i32* %arrayidx1.i.i, align 4, !tbaa !0 + %v6 = load i32* %arrayidx1.i.i, align 4 %cmp.i.i = icmp eq i32 %v5, %v6 br i1 %cmp.i.i, label %while.cond.i.i, label %equal_data.exit.i @@ -95,8 +95,3 @@ where.exit: while.end.i: ret i32 %v3 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"any pointer", metadata !1} diff --git a/test/Transforms/LoopUnroll/scevunroll.ll b/test/Transforms/LoopUnroll/scevunroll.ll index 99b3a7d86197..308a0363165c 100644 --- a/test/Transforms/LoopUnroll/scevunroll.ll +++ b/test/Transforms/LoopUnroll/scevunroll.ll @@ -66,13 +66,16 @@ exit2: ; SCEV properly unrolls multi-exit loops. ; +; SCEV cannot currently unroll this loop. +; It should ideally detect a trip count of 5. +; rdar:14038809 [SCEV]: Optimize trip count computation for multi-exit loops. ; CHECK: @multiExit -; CHECK: getelementptr i32* %base, i32 10 -; CHECK-NEXT: load i32* -; CHECK: br i1 false, label %l2.10, label %exit1 -; CHECK: l2.10: -; CHECK-NOT: br -; CHECK: ret i32 +; CHECKFIXME: getelementptr i32* %base, i32 10 +; CHECKFIXME-NEXT: load i32* +; CHECKFIXME: br i1 false, label %l2.10, label %exit1 +; CHECKFIXME: l2.10: +; CHECKFIXME-NOT: br +; CHECKFIXME: ret i32 define i32 @multiExit(i32* %base) nounwind { entry: br label %l1 @@ -170,3 +173,38 @@ for.body87: br label %for.body87 } +; PR16130: clang produces incorrect code with loop/expression at -O2 +; rdar:14036816 loop-unroll makes assumptions about undefined behavior +; +; The loop latch is assumed to exit after the first iteration because +; of the induction variable's NSW flag. However, the loop latch's +; equality test is skipped and the loop exits after the second +; iteration via the early exit. So loop unrolling cannot assume that +; the loop latch's exit count of zero is an upper bound on the number +; of iterations. +; +; CHECK: @nsw_latch +; CHECK: for.body: +; CHECK: %b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ] +; CHECK: return: +; CHECK: %b.03.lcssa = phi i32 [ %b.03, %for.body ], [ %b.03, %for.cond ] +define void @nsw_latch(i32* %a) nounwind { +entry: + br label %for.body + +for.body: ; preds = %for.cond, %entry + %b.03 = phi i32 [ 0, %entry ], [ %add, %for.cond ] + %tobool = icmp eq i32 %b.03, 0 + %add = add nsw i32 %b.03, 8 + br i1 %tobool, label %for.cond, label %return + +for.cond: ; preds = %for.body + %cmp = icmp eq i32 %add, 13 + br i1 %cmp, label %return, label %for.body + +return: ; preds = %for.body, %for.cond + %b.03.lcssa = phi i32 [ %b.03, %for.body ], [ %b.03, %for.cond ] + %retval.0 = phi i32 [ 1, %for.body ], [ 0, %for.cond ] + store i32 %b.03.lcssa, i32* %a, align 4 + ret void +} diff --git a/test/Transforms/LoopUnroll/unloop.ll b/test/Transforms/LoopUnroll/unloop.ll index 5a9cacda443c..9a938cc28774 100644 --- a/test/Transforms/LoopUnroll/unloop.ll +++ b/test/Transforms/LoopUnroll/unloop.ll @@ -21,8 +21,8 @@ outer: inner: %iv = phi i32 [ 0, %outer ], [ %inc, %tail ] %inc = add i32 %iv, 1 - %wbucond = call zeroext i1 @check() - br i1 %wbucond, label %outer.backedge, label %tail + call zeroext i1 @check() + br i1 true, label %outer.backedge, label %tail tail: br i1 false, label %inner, label %exit @@ -126,25 +126,27 @@ return: ; Ensure that only the middle loop is removed and rely on verify-loopinfo to ; check soundness. ; -; CHECK: @unloopDeepNested +; This test must be disabled until trip count computation can be optimized... +; rdar:14038809 [SCEV]: Optimize trip count computation for multi-exit loops. +; CHECKFIXME: @unloopDeepNested ; Inner-inner loop control. -; CHECK: while.cond.us.i: -; CHECK: br i1 %cmp.us.i, label %next_data.exit, label %while.body.us.i -; CHECK: if.then.us.i: -; CHECK: br label %while.cond.us.i +; CHECKFIXME: while.cond.us.i: +; CHECKFIXME: br i1 %cmp.us.i, label %next_data.exit, label %while.body.us.i +; CHECKFIXME: if.then.us.i: +; CHECKFIXME: br label %while.cond.us.i ; Inner loop tail. -; CHECK: if.else.i: -; CHECK: br label %while.cond.outer.i +; CHECKFIXME: if.else.i: +; CHECKFIXME: br label %while.cond.outer.i ; Middle loop control (removed). -; CHECK: valid_data.exit: -; CHECK-NOT: br -; CHECK: %cmp = call zeroext i1 @check() +; CHECKFIXME: valid_data.exit: +; CHECKFIXME-NOT: br +; CHECKFIXME: %cmp = call zeroext i1 @check() ; Outer loop control. -; CHECK: copy_data.exit: -; CHECK: br i1 %cmp38, label %if.then39, label %while.cond.outer +; CHECKFIXME: copy_data.exit: +; CHECKFIXME: br i1 %cmp38, label %if.then39, label %while.cond.outer ; Outer-outer loop tail. -; CHECK: while.cond.outer.outer.backedge: -; CHECK: br label %while.cond.outer.outer +; CHECKFIXME: while.cond.outer.outer.backedge: +; CHECKFIXME: br label %while.cond.outer.outer define void @unloopDeepNested() nounwind { for.cond8.preheader.i: %cmp113.i = call zeroext i1 @check() diff --git a/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll b/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll index 0e3103dc6db7..e8feef383b05 100644 --- a/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll +++ b/test/Transforms/LoopUnswitch/2011-09-26-EHCrash.ll @@ -24,7 +24,7 @@ if.then: ; preds = %for.body %idxprom = sext i32 %inc1 to i64 %array_ = getelementptr inbounds %class.MyContainer.1.3.19.29* %this, i32 0, i32 0 %arrayidx = getelementptr inbounds [6 x %class.MyMemVarClass.0.2.18.28*]* %array_, i32 0, i64 %idxprom - %tmp4 = load %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8, !tbaa !0 + %tmp4 = load %class.MyMemVarClass.0.2.18.28** %arrayidx, align 8 %isnull = icmp eq %class.MyMemVarClass.0.2.18.28* %tmp4, null br i1 %isnull, label %for.inc, label %delete.notnull @@ -61,7 +61,3 @@ declare void @_ZN13MyMemVarClassD1Ev(%class.MyMemVarClass.0.2.18.28*) declare i32 @__gxx_personality_v0(...) declare void @_ZdlPv(i8*) nounwind - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll index 261876df2aa0..a6c0d83484b3 100644 --- a/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll +++ b/test/Transforms/LoopUnswitch/2012-04-30-LoopUnswitch-LPad-Crash.ll @@ -45,10 +45,10 @@ for.end: ; preds = %invoke.cont6 define void @_ZN1DptEv(%class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this) uwtable ssp align 2 { entry: %this.addr = alloca %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379*, align 8 - store %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr, align 8, !tbaa !0 + store %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this, %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr, align 8 %this1 = load %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379** %this.addr %px = getelementptr inbounds %class.D.22.42.66.102.138.158.178.198.238.242.246.250.262.294.302.338.346.379* %this1, i32 0, i32 0 - %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8, !tbaa !0 + %0 = load %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376** %px, align 8 %tobool = icmp ne %class.C.23.43.67.103.139.159.179.199.239.243.247.251.263.295.303.339.347.376* %0, null br i1 %tobool, label %cond.end, label %cond.false @@ -95,7 +95,3 @@ entry: } declare void @_Z10__assert13v() noreturn - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll index 2dd7fe34a70b..bab6300f2e7f 100644 --- a/test/Transforms/LoopVectorize/12-12-11-if-conv.ll +++ b/test/Transforms/LoopVectorize/12-12-11-if-conv.ll @@ -15,7 +15,7 @@ entry: for.body: ; preds = %entry, %if.end %indvars.iv = phi i64 [ %indvars.iv.next, %if.end ], [ 0, %entry ] %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv - %0 = load i32* %arrayidx, align 4, !tbaa !0 + %0 = load i32* %arrayidx, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.end, label %if.then @@ -29,7 +29,7 @@ if.then: ; preds = %for.body if.end: ; preds = %for.body, %if.then %z.0 = phi i32 [ %add1, %if.then ], [ 9, %for.body ] - store i32 %z.0, i32* %arrayidx, align 4, !tbaa !0 + store i32 %z.0, i32* %arrayidx, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %x @@ -38,7 +38,3 @@ if.end: ; preds = %for.body, %if.then for.end: ; preds = %if.end, %entry ret i32 undef } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll b/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll index 405582c40899..ae9f998fee26 100644 --- a/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll +++ b/test/Transforms/LoopVectorize/2012-10-22-isconsec.ll @@ -24,7 +24,7 @@ entry: %3 = shl nsw i64 %indvars.iv, 2 %4 = getelementptr inbounds i8* %1, i64 %3 %5 = bitcast i8* %4 to float* - store float %value, float* %5, align 4, !tbaa !0 + store float %value, float* %5, align 4 %indvars.iv.next = add i64 %indvars.iv, %2 %6 = trunc i64 %indvars.iv.next to i32 %7 = icmp slt i32 %6, %_n @@ -43,7 +43,7 @@ entry: %0 = shl nsw i64 %indvars.iv, 2 %1 = getelementptr inbounds i8* bitcast (float* getelementptr inbounds ([32000 x float]* @b, i64 0, i64 16000) to i8*), i64 %0 %2 = bitcast i8* %1 to float* - store float -1.000000e+00, float* %2, align 4, !tbaa !0 + store float -1.000000e+00, float* %2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 16000 @@ -52,6 +52,3 @@ entry: "5": ; preds = %"3" ret i32 0 } - -!0 = metadata !{metadata !"alias set 7: float", metadata !1} -!1 = metadata !{metadata !1} diff --git a/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll b/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll index 6c924409af37..f4c07b4b24d9 100644 --- a/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll +++ b/test/Transforms/LoopVectorize/X86/constant-vector-operand.ll @@ -1,5 +1,7 @@ ; RUN: opt -mtriple=x86_64-apple-darwin -mcpu=core2 -loop-vectorize -dce -instcombine -S < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + @B = common global [1024 x i32] zeroinitializer, align 16 @A = common global [1024 x i32] zeroinitializer, align 16 diff --git a/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll new file mode 100644 index 000000000000..47a5e7aee4c1 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll @@ -0,0 +1,56 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +;CHECK: @foo +;CHECK-NOT: <4 x i32> +;CHECK: ret void + +; Function Attrs: nounwind uwtable +define void @foo(i32* nocapture %a, i32* nocapture %b, i32 %k, i32 %m) #0 { +entry: + %cmp27 = icmp sgt i32 %m, 0 + br i1 %cmp27, label %for.body3.lr.ph.us, label %for.end15 + +for.end.us: ; preds = %for.body3.us + %arrayidx9.us = getelementptr inbounds i32* %b, i64 %indvars.iv33 + %0 = load i32* %arrayidx9.us, align 4, !llvm.mem.parallel_loop_access !3 + %add10.us = add nsw i32 %0, 3 + store i32 %add10.us, i32* %arrayidx9.us, align 4, !llvm.mem.parallel_loop_access !3 + %indvars.iv.next34 = add i64 %indvars.iv33, 1 + %lftr.wideiv35 = trunc i64 %indvars.iv.next34 to i32 + %exitcond36 = icmp eq i32 %lftr.wideiv35, %m + br i1 %exitcond36, label %for.end15, label %for.body3.lr.ph.us, !llvm.loop.parallel !5 + +for.body3.us: ; preds = %for.body3.us, %for.body3.lr.ph.us + %indvars.iv29 = phi i64 [ 0, %for.body3.lr.ph.us ], [ %indvars.iv.next30, %for.body3.us ] + %1 = trunc i64 %indvars.iv29 to i32 + %add4.us = add i32 %add.us, %1 + %idxprom.us = sext i32 %add4.us to i64 + %arrayidx.us = getelementptr inbounds i32* %a, i64 %idxprom.us + %2 = load i32* %arrayidx.us, align 4, !llvm.mem.parallel_loop_access !3 + %add5.us = add nsw i32 %2, 1 + store i32 %add5.us, i32* %arrayidx7.us, align 4, !llvm.mem.parallel_loop_access !3 + %indvars.iv.next30 = add i64 %indvars.iv29, 1 + %lftr.wideiv31 = trunc i64 %indvars.iv.next30 to i32 + %exitcond32 = icmp eq i32 %lftr.wideiv31, %m + br i1 %exitcond32, label %for.end.us, label %for.body3.us, !llvm.loop.parallel !4 + +for.body3.lr.ph.us: ; preds = %for.end.us, %entry + %indvars.iv33 = phi i64 [ %indvars.iv.next34, %for.end.us ], [ 0, %entry ] + %3 = trunc i64 %indvars.iv33 to i32 + %add.us = add i32 %3, %k + %arrayidx7.us = getelementptr inbounds i32* %a, i64 %indvars.iv33 + br label %for.body3.us + +for.end15: ; preds = %for.end.us, %entry + ret void +} + +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!3 = metadata !{metadata !4, metadata !5} +!4 = metadata !{metadata !4} +!5 = metadata !{metadata !5} + diff --git a/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll b/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll index 186fba87d653..8716cff77789 100644 --- a/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll +++ b/test/Transforms/LoopVectorize/X86/min-trip-count-switch.ll @@ -11,9 +11,9 @@ entry: for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds float* %a, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %add = fadd float %0, 1.000000e+00 - store float %add, float* %arrayidx, align 4, !tbaa !0 + store float %add, float* %arrayidx, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 8 @@ -22,7 +22,3 @@ for.body: ; preds = %for.body, %entry for.end: ; preds = %for.body ret void } - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll b/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll index 452d0df133db..f904a8e0b117 100644 --- a/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll +++ b/test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll @@ -19,19 +19,19 @@ entry: for.body: ; preds = %for.body.for.body_crit_edge, %entry %indvars.iv.reload = load i64* %indvars.iv.reg2mem %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv.reload - %0 = load i32* %arrayidx, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv.reload - %1 = load i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 %idxprom3 = sext i32 %1 to i64 %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3 - store i32 %0, i32* %arrayidx4, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !3 %indvars.iv.next = add i64 %indvars.iv.reload, 1 ; A new store without the parallel metadata here: store i64 %indvars.iv.next, i64* %indvars.iv.next.reg2mem %indvars.iv.next.reload1 = load i64* %indvars.iv.next.reg2mem %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next.reload1 - %2 = load i32* %arrayidx6, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 - store i32 %2, i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3 + store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 %indvars.iv.next.reload = load i64* %indvars.iv.next.reg2mem %lftr.wideiv = trunc i64 %indvars.iv.next.reload to i32 %exitcond = icmp eq i32 %lftr.wideiv, 512 @@ -46,7 +46,4 @@ for.end: ; preds = %for.body ret void } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} !3 = metadata !{metadata !3} diff --git a/test/Transforms/LoopVectorize/X86/parallel-loops.ll b/test/Transforms/LoopVectorize/X86/parallel-loops.ll index f648722734a1..3f1a071e69fa 100644 --- a/test/Transforms/LoopVectorize/X86/parallel-loops.ll +++ b/test/Transforms/LoopVectorize/X86/parallel-loops.ll @@ -21,16 +21,16 @@ entry: for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv - %0 = load i32* %arrayidx, align 4, !tbaa !0 + %0 = load i32* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv - %1 = load i32* %arrayidx2, align 4, !tbaa !0 + %1 = load i32* %arrayidx2, align 4 %idxprom3 = sext i32 %1 to i64 %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3 - store i32 %0, i32* %arrayidx4, align 4, !tbaa !0 + store i32 %0, i32* %arrayidx4, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next - %2 = load i32* %arrayidx6, align 4, !tbaa !0 - store i32 %2, i32* %arrayidx2, align 4, !tbaa !0 + %2 = load i32* %arrayidx6, align 4 + store i32 %2, i32* %arrayidx2, align 4 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 512 br i1 %exitcond, label %for.end, label %for.body @@ -51,18 +51,18 @@ entry: for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv - %0 = load i32* %arrayidx, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !3 %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv - %1 = load i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 %idxprom3 = sext i32 %1 to i64 %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3 ; This store might have originated from inlining a function with a parallel ; loop. Refers to a list with the "original loop reference" (!4) also included. - store i32 %0, i32* %arrayidx4, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !5 + store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !5 %indvars.iv.next = add i64 %indvars.iv, 1 %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next - %2 = load i32* %arrayidx6, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 - store i32 %2, i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !3 + %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !3 + store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !3 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 512 br i1 %exitcond, label %for.end, label %for.body, !llvm.loop.parallel !3 @@ -84,18 +84,18 @@ entry: for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32* %b, i64 %indvars.iv - %0 = load i32* %arrayidx, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !6 + %0 = load i32* %arrayidx, align 4, !llvm.mem.parallel_loop_access !6 %arrayidx2 = getelementptr inbounds i32* %a, i64 %indvars.iv - %1 = load i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !6 + %1 = load i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !6 %idxprom3 = sext i32 %1 to i64 %arrayidx4 = getelementptr inbounds i32* %a, i64 %idxprom3 ; This refers to the loop marked with !7 which we are not in at the moment. ; It should prevent detecting as a parallel loop. - store i32 %0, i32* %arrayidx4, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !7 + store i32 %0, i32* %arrayidx4, align 4, !llvm.mem.parallel_loop_access !7 %indvars.iv.next = add i64 %indvars.iv, 1 %arrayidx6 = getelementptr inbounds i32* %b, i64 %indvars.iv.next - %2 = load i32* %arrayidx6, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !6 - store i32 %2, i32* %arrayidx2, align 4, !tbaa !0, !llvm.mem.parallel_loop_access !6 + %2 = load i32* %arrayidx6, align 4, !llvm.mem.parallel_loop_access !6 + store i32 %2, i32* %arrayidx2, align 4, !llvm.mem.parallel_loop_access !6 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, 512 br i1 %exitcond, label %for.end, label %for.body, !llvm.loop.parallel !6 @@ -104,9 +104,6 @@ for.end: ; preds = %for.body ret void } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} !3 = metadata !{metadata !3} !4 = metadata !{metadata !4} !5 = metadata !{metadata !3, metadata !4} diff --git a/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll new file mode 100644 index 000000000000..b66119f4ef59 --- /dev/null +++ b/test/Transforms/LoopVectorize/X86/x86_fp80-vector-store.ll @@ -0,0 +1,29 @@ +; RUN: opt -O3 -loop-vectorize -force-vector-unroll=1 -force-vector-width=2 -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.0" + +@x = common global [1024 x x86_fp80] zeroinitializer, align 16 + +;CHECK: @example +;CHECK-NOT: bitcast x86_fp80* {{%[^ ]+}} to <{{[2-9][0-9]*}} x x86_fp80>* +;CHECK: store +;CHECK: ret void + +define void @example() nounwind ssp uwtable { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %conv = sitofp i32 1 to x86_fp80 + %arrayidx = getelementptr inbounds [1024 x x86_fp80]* @x, i64 0, i64 %indvars.iv + store x86_fp80 %conv, x86_fp80* %arrayidx, align 16 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/Transforms/LoopVectorize/bsd_regex.ll b/test/Transforms/LoopVectorize/bsd_regex.ll new file mode 100644 index 000000000000..a14b92d229b4 --- /dev/null +++ b/test/Transforms/LoopVectorize/bsd_regex.ll @@ -0,0 +1,38 @@ +; RUN: opt -S -loop-vectorize -dce -instcombine -force-vector-width=2 -force-vector-unroll=2 < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +;PR 15830. + +;CHECK: foo +; When scalarizing stores we need to preserve the original order. +; Make sure that we are extracting in the correct order (0101, and not 0011). +;CHECK: extractelement <2 x i64> {{.*}}, i32 0 +;CHECK: extractelement <2 x i64> {{.*}}, i32 1 +;CHECK: extractelement <2 x i64> {{.*}}, i32 0 +;CHECK: extractelement <2 x i64> {{.*}}, i32 1 +;CHECK: store +;CHECK: store +;CHECK: store +;CHECK: store +;CHECK: ret + +define i32 @foo(i32* nocapture %A) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %0 = shl nsw i64 %indvars.iv, 2 + %arrayidx = getelementptr inbounds i32* %A, i64 %0 + store i32 4, i32* %arrayidx, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 10000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 undef +} + + diff --git a/test/Transforms/LoopVectorize/bzip_reverse_loops.ll b/test/Transforms/LoopVectorize/bzip_reverse_loops.ll index 431e422c2fbe..2648bbea8035 100644 --- a/test/Transforms/LoopVectorize/bzip_reverse_loops.ll +++ b/test/Transforms/LoopVectorize/bzip_reverse_loops.ll @@ -17,7 +17,7 @@ do.body: ; preds = %cond.end, %entry %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %cond.end ] %p.addr.0 = phi i16* [ %p, %entry ], [ %incdec.ptr, %cond.end ] %incdec.ptr = getelementptr inbounds i16* %p.addr.0, i64 -1 - %0 = load i16* %incdec.ptr, align 2, !tbaa !0 + %0 = load i16* %incdec.ptr, align 2 %conv = zext i16 %0 to i32 %cmp = icmp ult i32 %conv, %size br i1 %cmp, label %cond.end, label %cond.true @@ -29,7 +29,7 @@ cond.true: ; preds = %do.body cond.end: ; preds = %do.body, %cond.true %cond = phi i16 [ %phitmp, %cond.true ], [ 0, %do.body ] - store i16 %cond, i16* %incdec.ptr, align 2, !tbaa !0 + store i16 %cond, i16* %incdec.ptr, align 2 %dec = add i32 %n.addr.0, -1 %tobool = icmp eq i32 %dec, 0 br i1 %tobool, label %do.end, label %do.body @@ -52,11 +52,11 @@ do.body: ; preds = %do.body, %entry %n.addr.0 = phi i32 [ %n, %entry ], [ %dec, %do.body ] %p.0 = phi i32* [ %a, %entry ], [ %incdec.ptr, %do.body ] %incdec.ptr = getelementptr inbounds i32* %p.0, i64 -1 - %0 = load i32* %incdec.ptr, align 4, !tbaa !3 + %0 = load i32* %incdec.ptr, align 4 %cmp = icmp slt i32 %0, %wsize %sub = sub nsw i32 %0, %wsize %cond = select i1 %cmp, i32 0, i32 %sub - store i32 %cond, i32* %incdec.ptr, align 4, !tbaa !3 + store i32 %cond, i32* %incdec.ptr, align 4 %dec = add nsw i32 %n.addr.0, -1 %tobool = icmp eq i32 %dec, 0 br i1 %tobool, label %do.end, label %do.body @@ -64,8 +64,3 @@ do.body: ; preds = %do.body, %entry do.end: ; preds = %do.body ret void } - -!0 = metadata !{metadata !"short", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"int", metadata !1} diff --git a/test/Transforms/LoopVectorize/calloc.ll b/test/Transforms/LoopVectorize/calloc.ll index 08c84eff5dbf..7e7991616459 100644 --- a/test/Transforms/LoopVectorize/calloc.ll +++ b/test/Transforms/LoopVectorize/calloc.ll @@ -23,7 +23,7 @@ for.body: ; preds = %for.body, %for.body %i.030 = phi i64 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] %shr = lshr i64 %i.030, 1 %arrayidx = getelementptr inbounds i8* %bytes, i64 %shr - %1 = load i8* %arrayidx, align 1, !tbaa !0 + %1 = load i8* %arrayidx, align 1 %conv = zext i8 %1 to i32 %and = shl i64 %i.030, 2 %neg = and i64 %and, 4 @@ -38,7 +38,7 @@ for.body: ; preds = %for.body, %for.body %add17 = add nsw i32 %cond, %shr11 %conv18 = trunc i32 %add17 to i8 %arrayidx19 = getelementptr inbounds i8* %call, i64 %i.030 - store i8 %conv18, i8* %arrayidx19, align 1, !tbaa !0 + store i8 %conv18, i8* %arrayidx19, align 1 %inc = add i64 %i.030, 1 %exitcond = icmp eq i64 %inc, %0 br i1 %exitcond, label %for.end, label %for.body @@ -48,6 +48,3 @@ for.end: ; preds = %for.body, %entry } declare noalias i8* @calloc(i64, i64) nounwind - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/dbg.value.ll b/test/Transforms/LoopVectorize/dbg.value.ll index a2ea9511bb22..127d479b3a06 100644 --- a/test/Transforms/LoopVectorize/dbg.value.ll +++ b/test/Transforms/LoopVectorize/dbg.value.ll @@ -18,12 +18,12 @@ for.body: ;CHECK: load <4 x i32> %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds [1024 x i32]* @B, i64 0, i64 %indvars.iv, !dbg !19 - %0 = load i32* %arrayidx, align 4, !dbg !19, !tbaa !21 + %0 = load i32* %arrayidx, align 4, !dbg !19 %arrayidx2 = getelementptr inbounds [1024 x i32]* @C, i64 0, i64 %indvars.iv, !dbg !19 - %1 = load i32* %arrayidx2, align 4, !dbg !19, !tbaa !21 + %1 = load i32* %arrayidx2, align 4, !dbg !19 %add = add nsw i32 %1, %0, !dbg !19 %arrayidx4 = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv, !dbg !19 - store i32 %add, i32* %arrayidx4, align 4, !dbg !19, !tbaa !21 + store i32 %add, i32* %arrayidx4, align 4, !dbg !19 %indvars.iv.next = add i64 %indvars.iv, 1, !dbg !18 tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !9), !dbg !18 %lftr.wideiv = trunc i64 %indvars.iv.next to i32, !dbg !18 @@ -64,7 +64,4 @@ attributes #1 = { nounwind readnone } !18 = metadata !{i32 6, i32 0, metadata !10, null} !19 = metadata !{i32 7, i32 0, metadata !20, null} !20 = metadata !{i32 786443, metadata !10, i32 6, i32 0, metadata !4, i32 1} -!21 = metadata !{metadata !"int", metadata !22} -!22 = metadata !{metadata !"omnipotent char", metadata !23} -!23 = metadata !{metadata !"Simple C/C++ TBAA"} !24 = metadata !{i32 9, i32 0, metadata !3, null} diff --git a/test/Transforms/LoopVectorize/float-reduction.ll b/test/Transforms/LoopVectorize/float-reduction.ll index 565684cccb9a..54ca172e8696 100644 --- a/test/Transforms/LoopVectorize/float-reduction.ll +++ b/test/Transforms/LoopVectorize/float-reduction.ll @@ -13,7 +13,7 @@ for.body: ; preds = %for.body, %entry %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] %sum.04 = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ] %arrayidx = getelementptr inbounds float* %A, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %add = fadd fast float %sum.04, %0 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 @@ -23,7 +23,3 @@ for.body: ; preds = %for.body, %entry for.end: ; preds = %for.body ret float %add } - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/i8-induction.ll b/test/Transforms/LoopVectorize/i8-induction.ll index 7759b7085a1b..2a0e82645494 100644 --- a/test/Transforms/LoopVectorize/i8-induction.ll +++ b/test/Transforms/LoopVectorize/i8-induction.ll @@ -8,8 +8,8 @@ target triple = "x86_64-apple-macosx10.8.0" define void @f() nounwind uwtable ssp { scalar.ph: - store i8 0, i8* inttoptr (i64 1 to i8*), align 1, !tbaa !0 - %0 = load i8* @a, align 1, !tbaa !0 + store i8 0, i8* inttoptr (i64 1 to i8*), align 1 + %0 = load i8* @a, align 1 br label %for.body for.body: @@ -26,10 +26,6 @@ for.body: br i1 %phitmp14, label %for.body, label %for.end for.end: ; preds = %for.body - store i8 %mul, i8* @b, align 1, !tbaa !0 + store i8 %mul, i8* @b, align 1 ret void } - -!0 = metadata !{metadata !"omnipotent char", metadata !1} -!1 = metadata !{metadata !"Simple C/C++ TBAA"} - diff --git a/test/Transforms/LoopVectorize/if-conversion-nest.ll b/test/Transforms/LoopVectorize/if-conversion-nest.ll new file mode 100644 index 000000000000..f44862a2ebb9 --- /dev/null +++ b/test/Transforms/LoopVectorize/if-conversion-nest.ll @@ -0,0 +1,48 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -enable-if-conversion -dce -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +;CHECK: @foo +;CHECK: icmp sgt +;CHECK: icmp sgt +;CHECK: icmp slt +;CHECK: select <4 x i1> +;CHECK: %[[P1:.*]] = select <4 x i1> +;CHECK: xor <4 x i1> +;CHECK: and <4 x i1> +;CHECK: select <4 x i1> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %[[P1]] +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32* nocapture %B, i32 %n) { +entry: + %cmp26 = icmp sgt i32 %n, 0 + br i1 %cmp26, label %for.body, label %for.end + +for.body: + %indvars.iv = phi i64 [ %indvars.iv.next, %if.end14 ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds i32* %B, i64 %indvars.iv + %1 = load i32* %arrayidx2, align 4 + %cmp3 = icmp sgt i32 %0, %1 + br i1 %cmp3, label %if.then, label %if.end14 + +if.then: + %cmp6 = icmp sgt i32 %0, 19 + br i1 %cmp6, label %if.end14, label %if.else + +if.else: + %cmp10 = icmp slt i32 %1, 4 + %. = select i1 %cmp10, i32 4, i32 5 + br label %if.end14 + +if.end14: + %x.0 = phi i32 [ 9, %for.body ], [ 3, %if.then ], [ %., %if.else ] ; <------------- A PHI with 3 entries that we can still vectorize. + store i32 %x.0, i32* %arrayidx, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 undef +} diff --git a/test/Transforms/LoopVectorize/intrinsic.ll b/test/Transforms/LoopVectorize/intrinsic.ll index e79d78de67c5..defbb5bd94ba 100644 --- a/test/Transforms/LoopVectorize/intrinsic.ll +++ b/test/Transforms/LoopVectorize/intrinsic.ll @@ -14,10 +14,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.sqrt.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -40,10 +40,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.sqrt.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -66,10 +66,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.sin.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -92,10 +92,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.sin.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -118,10 +118,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.cos.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -144,10 +144,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.cos.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -170,10 +170,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.exp.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -196,10 +196,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.exp.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -222,10 +222,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.exp2.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -248,10 +248,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.exp2.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -274,10 +274,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.log.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -300,10 +300,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.log.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -326,10 +326,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.log10.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -352,10 +352,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.log10.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -378,10 +378,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.log2.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -404,10 +404,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.log2.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -430,10 +430,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.fabs.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -453,10 +453,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.fabs(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -479,10 +479,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.floor.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -505,10 +505,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.floor.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -531,10 +531,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.ceil.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -557,10 +557,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.ceil.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -583,10 +583,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.trunc.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -609,10 +609,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.trunc.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -635,10 +635,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.rint.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -661,10 +661,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.rint.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -687,10 +687,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %call = tail call float @llvm.nearbyint.f32(float %0) nounwind readnone %arrayidx2 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx2, align 4, !tbaa !0 + store float %call, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -713,10 +713,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %call = tail call double @llvm.nearbyint.f64(double %0) nounwind readnone %arrayidx2 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx2, align 8, !tbaa !3 + store double %call, double* %arrayidx2, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -739,14 +739,14 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds float* %w, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4, !tbaa !0 + %1 = load float* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds float* %z, i64 %indvars.iv - %2 = load float* %arrayidx4, align 4, !tbaa !0 + %2 = load float* %arrayidx4, align 4 %3 = tail call float @llvm.fma.f32(float %0, float %2, float %1) %arrayidx6 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %3, float* %arrayidx6, align 4, !tbaa !0 + store float %3, float* %arrayidx6, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -769,14 +769,14 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %arrayidx2 = getelementptr inbounds double* %w, i64 %indvars.iv - %1 = load double* %arrayidx2, align 8, !tbaa !3 + %1 = load double* %arrayidx2, align 8 %arrayidx4 = getelementptr inbounds double* %z, i64 %indvars.iv - %2 = load double* %arrayidx4, align 8, !tbaa !3 + %2 = load double* %arrayidx4, align 8 %3 = tail call double @llvm.fma.f64(double %0, double %2, double %1) %arrayidx6 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %3, double* %arrayidx6, align 8, !tbaa !3 + store double %3, double* %arrayidx6, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -799,14 +799,14 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds float* %w, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4, !tbaa !0 + %1 = load float* %arrayidx2, align 4 %arrayidx4 = getelementptr inbounds float* %z, i64 %indvars.iv - %2 = load float* %arrayidx4, align 4, !tbaa !0 + %2 = load float* %arrayidx4, align 4 %3 = tail call float @llvm.fmuladd.f32(float %0, float %2, float %1) %arrayidx6 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %3, float* %arrayidx6, align 4, !tbaa !0 + store float %3, float* %arrayidx6, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -829,14 +829,14 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %arrayidx2 = getelementptr inbounds double* %w, i64 %indvars.iv - %1 = load double* %arrayidx2, align 8, !tbaa !3 + %1 = load double* %arrayidx2, align 8 %arrayidx4 = getelementptr inbounds double* %z, i64 %indvars.iv - %2 = load double* %arrayidx4, align 8, !tbaa !3 + %2 = load double* %arrayidx4, align 8 %3 = tail call double @llvm.fmuladd.f64(double %0, double %2, double %1) %arrayidx6 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %3, double* %arrayidx6, align 8, !tbaa !3 + store double %3, double* %arrayidx6, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -859,12 +859,12 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %y, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %arrayidx2 = getelementptr inbounds float* %z, i64 %indvars.iv - %1 = load float* %arrayidx2, align 4, !tbaa !0 + %1 = load float* %arrayidx2, align 4 %call = tail call float @llvm.pow.f32(float %0, float %1) nounwind readnone %arrayidx4 = getelementptr inbounds float* %x, i64 %indvars.iv - store float %call, float* %arrayidx4, align 4, !tbaa !0 + store float %call, float* %arrayidx4, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -887,12 +887,12 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds double* %y, i64 %indvars.iv - %0 = load double* %arrayidx, align 8, !tbaa !3 + %0 = load double* %arrayidx, align 8 %arrayidx2 = getelementptr inbounds double* %z, i64 %indvars.iv - %1 = load double* %arrayidx2, align 8, !tbaa !3 + %1 = load double* %arrayidx2, align 8 %call = tail call double @llvm.pow.f64(double %0, double %1) nounwind readnone %arrayidx4 = getelementptr inbounds double* %x, i64 %indvars.iv - store double %call, double* %arrayidx4, align 8, !tbaa !3 + store double %call, double* %arrayidx4, align 8 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -927,9 +927,3 @@ for.end: ; preds = %for.body declare float @fabsf(float) nounwind readnone declare double @llvm.pow.f64(double, double) nounwind readnone - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"double", metadata !1} -!4 = metadata !{metadata !"int", metadata !1} diff --git a/test/Transforms/LoopVectorize/lcssa-crash.ll b/test/Transforms/LoopVectorize/lcssa-crash.ll index 06b3b08aa0e3..de6be548490c 100644 --- a/test/Transforms/LoopVectorize/lcssa-crash.ll +++ b/test/Transforms/LoopVectorize/lcssa-crash.ll @@ -27,3 +27,14 @@ for.end.i.i.i: unreachable } +; PR16139 +define void @test2(i8* %x) { +entry: + indirectbr i8* %x, [ label %L0, label %L1 ] + +L0: + br label %L0 + +L1: + ret void +} diff --git a/test/Transforms/LoopVectorize/minmax_reduction.ll b/test/Transforms/LoopVectorize/minmax_reduction.ll new file mode 100644 index 000000000000..502fd8b9383b --- /dev/null +++ b/test/Transforms/LoopVectorize/minmax_reduction.ll @@ -0,0 +1,885 @@ +; RUN: opt -S -loop-vectorize -dce -instcombine -force-vector-width=2 -force-vector-unroll=1 < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +@A = common global [1024 x i32] zeroinitializer, align 16 +@fA = common global [1024 x float] zeroinitializer, align 16 +@dA = common global [1024 x double] zeroinitializer, align 16 + +; Signed tests. + +; Turn this into a max reduction. Make sure we use a splat to initialize the +; vector for the reduction. +; CHECK: @max_red +; CHECK: %[[VAR:.*]] = insertelement <2 x i32> undef, i32 %max, i32 0 +; CHECK: {{.*}} = shufflevector <2 x i32> %[[VAR]], <2 x i32> undef, <2 x i32> zeroinitializer +; CHECK: icmp sgt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp sgt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @max_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp sgt i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a max reduction. The select has its inputs reversed therefore +; this is a max reduction. +; CHECK: @max_red_inverse_select +; CHECK: icmp slt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp sgt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @max_red_inverse_select(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp slt i32 %max.red.08, %0 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a min reduction. +; CHECK: @min_red +; CHECK: icmp slt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp slt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @min_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp slt i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a min reduction. The select has its inputs reversed therefore +; this is a min reduction. +; CHECK: @min_red_inverse_select +; CHECK: icmp sgt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp slt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @min_red_inverse_select(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp sgt i32 %max.red.08, %0 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Unsigned tests. + +; Turn this into a max reduction. +; CHECK: @umax_red +; CHECK: icmp ugt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ugt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @umax_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp ugt i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a max reduction. The select has its inputs reversed therefore +; this is a max reduction. +; CHECK: @umax_red_inverse_select +; CHECK: icmp ult <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ugt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @umax_red_inverse_select(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp ult i32 %max.red.08, %0 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a min reduction. +; CHECK: @umin_red +; CHECK: icmp ult <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ult <2 x i32> +; CHECK: select <2 x i1> + +define i32 @umin_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp ult i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Turn this into a min reduction. The select has its inputs reversed therefore +; this is a min reduction. +; CHECK: @umin_red_inverse_select +; CHECK: icmp ugt <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ult <2 x i32> +; CHECK: select <2 x i1> + +define i32 @umin_red_inverse_select(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp ugt i32 %max.red.08, %0 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; SGE -> SLT +; Turn this into a min reduction (select inputs are reversed). +; CHECK: @sge_min_red +; CHECK: icmp sge <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp slt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @sge_min_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp sge i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; SLE -> SGT +; Turn this into a max reduction (select inputs are reversed). +; CHECK: @sle_min_red +; CHECK: icmp sle <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp sgt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @sle_min_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp sle i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; UGE -> ULT +; Turn this into a min reduction (select inputs are reversed). +; CHECK: @uge_min_red +; CHECK: icmp uge <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ult <2 x i32> +; CHECK: select <2 x i1> + +define i32 @uge_min_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp uge i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; ULE -> UGT +; Turn this into a max reduction (select inputs are reversed). +; CHECK: @ule_min_red +; CHECK: icmp ule <2 x i32> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: icmp ugt <2 x i32> +; CHECK: select <2 x i1> + +define i32 @ule_min_red(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %cmp3 = icmp ule i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %max.red.08, i32 %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; No reduction. +; CHECK: @no_red_1 +; CHECK-NOT: icmp <2 x i32> +define i32 @no_red_1(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %arrayidx1 = getelementptr inbounds [1024 x i32]* @A, i64 1, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %1 = load i32* %arrayidx1, align 4 + %cmp3 = icmp sgt i32 %0, %1 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; CHECK: @no_red_2 +; CHECK-NOT: icmp <2 x i32> +define i32 @no_red_2(i32 %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi i32 [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x i32]* @A, i64 0, i64 %indvars.iv + %arrayidx1 = getelementptr inbounds [1024 x i32]* @A, i64 1, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %1 = load i32* %arrayidx1, align 4 + %cmp3 = icmp sgt i32 %0, %max.red.08 + %max.red.0 = select i1 %cmp3, i32 %0, i32 %1 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %max.red.0 +} + +; Float tests. + +; Maximum. + +; Turn this into a max reduction in the presence of a no-nans-fp-math attribute. +; CHECK: @max_red_float +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @max_red_float(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ogt float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %0, float %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @max_red_float_ge +; CHECK: fcmp oge <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @max_red_float_ge(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp oge float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %0, float %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @inverted_max_red_float +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_max_red_float(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp olt float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %max.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @inverted_max_red_float_le +; CHECK: fcmp ole <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_max_red_float_le(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ole float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %max.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @unordered_max_red +; CHECK: fcmp ugt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @unordered_max_red_float(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ugt float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %0, float %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @unordered_max_red_float_ge +; CHECK: fcmp uge <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @unordered_max_red_float_ge(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp uge float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %0, float %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @inverted_unordered_max_red +; CHECK: fcmp ult <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_unordered_max_red_float(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ult float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %max.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; CHECK: @inverted_unordered_max_red_float_le +; CHECK: fcmp ule <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_unordered_max_red_float_le(float %max) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ule float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %max.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + +; Minimum. + +; Turn this into a min reduction in the presence of a no-nans-fp-math attribute. +; CHECK: @min_red_float +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @min_red_float(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp olt float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %0, float %min.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @min_red_float_le +; CHECK: fcmp ole <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @min_red_float_le(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ole float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %0, float %min.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @inverted_min_red_float +; CHECK: fcmp ogt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_min_red_float(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ogt float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %min.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @inverted_min_red_float_ge +; CHECK: fcmp oge <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_min_red_float_ge(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp oge float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %min.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @unordered_min_red +; CHECK: fcmp ult <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @unordered_min_red_float(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ult float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %0, float %min.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @unordered_min_red_float_le +; CHECK: fcmp ule <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @unordered_min_red_float_le(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ule float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %0, float %min.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @inverted_unordered_min_red +; CHECK: fcmp ugt <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_unordered_min_red_float(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ugt float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %min.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; CHECK: @inverted_unordered_min_red_float_ge +; CHECK: fcmp uge <2 x float> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x float> +; CHECK: select <2 x i1> + +define float @inverted_unordered_min_red_float_ge(float %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi float [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp uge float %0, %min.red.08 + %min.red.0 = select i1 %cmp3, float %min.red.08, float %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %min.red.0 +} + +; Make sure we handle doubles, too. +; CHECK: @min_red_double +; CHECK: fcmp olt <2 x double> +; CHECK: select <2 x i1> +; CHECK: middle.block +; CHECK: fcmp olt <2 x double> +; CHECK: select <2 x i1> + +define double @min_red_double(double %min) #0 { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %min.red.08 = phi double [ %min, %entry ], [ %min.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x double]* @dA, i64 0, i64 %indvars.iv + %0 = load double* %arrayidx, align 4 + %cmp3 = fcmp olt double %0, %min.red.08 + %min.red.0 = select i1 %cmp3, double %0, double %min.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret double %min.red.0 +} + + +; Don't this into a max reduction. The no-nans-fp-math attribute is missing +; CHECK: @max_red_float_nans +; CHECK-NOT: <2 x float> + +define float @max_red_float_nans(float %max) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %max.red.08 = phi float [ %max, %entry ], [ %max.red.0, %for.body ] + %arrayidx = getelementptr inbounds [1024 x float]* @fA, i64 0, i64 %indvars.iv + %0 = load float* %arrayidx, align 4 + %cmp3 = fcmp ogt float %0, %max.red.08 + %max.red.0 = select i1 %cmp3, float %0, float %max.red.08 + %indvars.iv.next = add i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret float %max.red.0 +} + + +attributes #0 = { "no-nans-fp-math"="true" } diff --git a/test/Transforms/LoopVectorize/no_idiv_reduction.ll b/test/Transforms/LoopVectorize/no_idiv_reduction.ll new file mode 100644 index 000000000000..cdfb3fd66f05 --- /dev/null +++ b/test/Transforms/LoopVectorize/no_idiv_reduction.ll @@ -0,0 +1,24 @@ +; RUN: opt -loop-vectorize -force-vector-width=2 -force-vector-unroll=1 -S < %s | FileCheck %s +@a = common global [128 x i32] zeroinitializer, align 16 + +;; Must not vectorize division reduction. Division is lossy. +define i32 @g() { +entry: + br label %for.body + +for.body: + ; CHECK: @g + ; CHECK-NOT: sdiv <2 x i32> + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %r.05 = phi i32 [ 80, %entry ], [ %div, %for.body ] + %arrayidx = getelementptr inbounds [128 x i32]* @a, i64 0, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %div = sdiv i32 %r.05, %0 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 1024 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret i32 %div +} diff --git a/test/Transforms/LoopVectorize/no_outside_user.ll b/test/Transforms/LoopVectorize/no_outside_user.ll new file mode 100644 index 000000000000..6f0357c5e546 --- /dev/null +++ b/test/Transforms/LoopVectorize/no_outside_user.ll @@ -0,0 +1,41 @@ +; RUN: opt -S -loop-vectorize -force-vector-unroll=1 -force-vector-width=2 < %s | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" + +@f = common global i32 0, align 4 +@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 +@c = common global i32 0, align 4 +@a = common global i32 0, align 4 +@b = common global i32 0, align 4 +@e = common global i32 0, align 4 + +; We used to vectorize this loop. But it has a value that is used outside of the +; and is not a recognized reduction variable "tmp17". + +; CHECK-NOT: <2 x i32> + +define i32 @main() { +bb: + %b.promoted = load i32* @b, align 4 + br label %.lr.ph.i + +.lr.ph.i: + %tmp8 = phi i32 [ %tmp18, %bb16 ], [ %b.promoted, %bb ] + %tmp2 = icmp sgt i32 %tmp8, 10 + br i1 %tmp2, label %bb16, label %bb10 + +bb10: + br label %bb16 + +bb16: + %tmp17 = phi i32 [ 0, %bb10 ], [ 1, %.lr.ph.i ] + %tmp18 = add nsw i32 %tmp8, 1 + %tmp19 = icmp slt i32 %tmp18, 4 + br i1 %tmp19, label %.lr.ph.i, label %f1.exit.loopexit + +f1.exit.loopexit: + %.lcssa = phi i32 [ %tmp17, %bb16 ] + ret i32 %.lcssa +} + + diff --git a/test/Transforms/LoopVectorize/phi-hang.ll b/test/Transforms/LoopVectorize/phi-hang.ll index b80d45995dc3..bbce239afa71 100644 --- a/test/Transforms/LoopVectorize/phi-hang.ll +++ b/test/Transforms/LoopVectorize/phi-hang.ll @@ -27,3 +27,21 @@ bb5: ; preds = %bb4, %bb1 bb11: ; preds = %bb5 ret void } + +; PR15748 +define void @test2() { +bb: + br label %bb1 + +bb1: ; preds = %bb1, %bb + %tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb1 ] + %tmp2 = phi i32 [ 0, %bb ], [ 1, %bb1 ] + %tmp3 = phi i32 [ 0, %bb ], [ %tmp4, %bb1 ] + %tmp4 = or i32 %tmp2, %tmp3 + %tmp5 = add nsw i32 %tmp, 1 + %tmp6 = icmp eq i32 %tmp5, 0 + br i1 %tmp6, label %bb7, label %bb1 + +bb7: ; preds = %bb1 + ret void +} diff --git a/test/Transforms/LoopVectorize/reverse_induction.ll b/test/Transforms/LoopVectorize/reverse_induction.ll new file mode 100644 index 000000000000..f43f02bc3132 --- /dev/null +++ b/test/Transforms/LoopVectorize/reverse_induction.ll @@ -0,0 +1,79 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=2 -force-vector-width=4 -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; Make sure consecutive vector generates correct negative indices. +; PR15882 + +; CHECK: reverse_induction_i64 +; CHECK: add <4 x i64> %[[SPLAT:.*]], <i64 0, i64 -1, i64 -2, i64 -3> +; CHECK: add <4 x i64> %[[SPLAT]], <i64 -4, i64 -5, i64 -6, i64 -7> + +define i32 @reverse_induction_i64(i64 %startval, i32 * %ptr) { +entry: + br label %for.body + +for.body: + %add.i7 = phi i64 [ %startval, %entry ], [ %add.i, %for.body ] + %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ] + %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ] + %add.i = add i64 %add.i7, -1 + %kind_.i = getelementptr inbounds i32* %ptr, i64 %add.i + %tmp.i1 = load i32* %kind_.i, align 4 + %inc.redux = add i32 %tmp.i1, %redux5 + %inc4 = add i32 %i.06, 1 + %exitcond = icmp ne i32 %inc4, 1024 + br i1 %exitcond, label %for.body, label %loopend + +loopend: + ret i32 %inc.redux +} + +; CHECK: reverse_induction_i128 +; CHECK: add <4 x i128> %[[SPLAT:.*]], <i128 0, i128 -1, i128 -2, i128 -3> +; CHECK: add <4 x i128> %[[SPLAT]], <i128 -4, i128 -5, i128 -6, i128 -7> +define i32 @reverse_induction_i128(i128 %startval, i32 * %ptr) { +entry: + br label %for.body + +for.body: + %add.i7 = phi i128 [ %startval, %entry ], [ %add.i, %for.body ] + %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ] + %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ] + %add.i = add i128 %add.i7, -1 + %kind_.i = getelementptr inbounds i32* %ptr, i128 %add.i + %tmp.i1 = load i32* %kind_.i, align 4 + %inc.redux = add i32 %tmp.i1, %redux5 + %inc4 = add i32 %i.06, 1 + %exitcond = icmp ne i32 %inc4, 1024 + br i1 %exitcond, label %for.body, label %loopend + +loopend: + ret i32 %inc.redux +} + +; CHECK: reverse_induction_i16 +; CHECK: add <4 x i16> %[[SPLAT:.*]], <i16 0, i16 -1, i16 -2, i16 -3> +; CHECK: add <4 x i16> %[[SPLAT]], <i16 -4, i16 -5, i16 -6, i16 -7> + +define i32 @reverse_induction_i16(i16 %startval, i32 * %ptr) { +entry: + br label %for.body + +for.body: + %add.i7 = phi i16 [ %startval, %entry ], [ %add.i, %for.body ] + %i.06 = phi i32 [ 0, %entry ], [ %inc4, %for.body ] + %redux5 = phi i32 [ 0, %entry ], [ %inc.redux, %for.body ] + %add.i = add i16 %add.i7, -1 + %kind_.i = getelementptr inbounds i32* %ptr, i16 %add.i + %tmp.i1 = load i32* %kind_.i, align 4 + %inc.redux = add i32 %tmp.i1, %redux5 + %inc4 = add i32 %i.06, 1 + %exitcond = icmp ne i32 %inc4, 1024 + br i1 %exitcond, label %for.body, label %loopend + +loopend: + ret i32 %inc.redux +} + + diff --git a/test/Transforms/LoopVectorize/runtime-check-readonly.ll b/test/Transforms/LoopVectorize/runtime-check-readonly.ll new file mode 100644 index 000000000000..4145d134fd70 --- /dev/null +++ b/test/Transforms/LoopVectorize/runtime-check-readonly.ll @@ -0,0 +1,36 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK: add_ints +;CHECK: br +;CHECK: getelementptr +;CHECK-NEXT: getelementptr +;CHECK-NEXT: icmp uge +;CHECK-NEXT: icmp uge +;CHECK-NEXT: icmp uge +;CHECK-NEXT: icmp uge +;CHECK-NEXT: and +;CHECK: ret +define void @add_ints(i32* nocapture %A, i32* nocapture %B, i32* nocapture %C) { +entry: + br label %for.body + +for.body: + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %B, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %arrayidx2 = getelementptr inbounds i32* %C, i64 %indvars.iv + %1 = load i32* %arrayidx2, align 4 + %add = add nsw i32 %1, %0 + %arrayidx4 = getelementptr inbounds i32* %A, i64 %indvars.iv + store i32 %add, i32* %arrayidx4, align 4 + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 200 + br i1 %exitcond, label %for.end, label %for.body + +for.end: + ret void +} diff --git a/test/Transforms/LoopVectorize/runtime-check.ll b/test/Transforms/LoopVectorize/runtime-check.ll index 86098a6e7db2..014c4fc48f87 100644 --- a/test/Transforms/LoopVectorize/runtime-check.ll +++ b/test/Transforms/LoopVectorize/runtime-check.ll @@ -22,10 +22,10 @@ entry: for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %arrayidx = getelementptr inbounds float* %b, i64 %indvars.iv - %0 = load float* %arrayidx, align 4, !tbaa !0 + %0 = load float* %arrayidx, align 4 %mul = fmul float %0, 3.000000e+00 %arrayidx2 = getelementptr inbounds float* %a, i64 %indvars.iv - store float %mul, float* %arrayidx2, align 4, !tbaa !0 + store float %mul, float* %arrayidx2, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 %exitcond = icmp eq i32 %lftr.wideiv, %n @@ -34,7 +34,3 @@ for.body: ; preds = %entry, %for.body for.end: ; preds = %for.body, %entry ret i32 undef } - -!0 = metadata !{metadata !"float", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/runtime-limit.ll b/test/Transforms/LoopVectorize/runtime-limit.ll new file mode 100644 index 000000000000..d7839746f0e1 --- /dev/null +++ b/test/Transforms/LoopVectorize/runtime-limit.ll @@ -0,0 +1,84 @@ +; RUN: opt < %s -loop-vectorize -force-vector-unroll=1 -force-vector-width=4 -dce -instcombine -S | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; We are vectorizing with 6 runtime checks. +;CHECK: func1x6 +;CHECK: <4 x i32> +;CHECK: ret +define i32 @func1x6(i32* nocapture %out, i32* nocapture %A, i32* nocapture %B, i32* nocapture %C, i32* nocapture %D, i32* nocapture %E, i32* nocapture %F) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.016 = phi i64 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i32* %A, i64 %i.016 + %0 = load i32* %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32* %B, i64 %i.016 + %1 = load i32* %arrayidx1, align 4 + %add = add nsw i32 %1, %0 + %arrayidx2 = getelementptr inbounds i32* %C, i64 %i.016 + %2 = load i32* %arrayidx2, align 4 + %add3 = add nsw i32 %add, %2 + %arrayidx4 = getelementptr inbounds i32* %E, i64 %i.016 + %3 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %add3, %3 + %arrayidx6 = getelementptr inbounds i32* %F, i64 %i.016 + %4 = load i32* %arrayidx6, align 4 + %add7 = add nsw i32 %add5, %4 + %arrayidx8 = getelementptr inbounds i32* %out, i64 %i.016 + store i32 %add7, i32* %arrayidx8, align 4 + %inc = add i64 %i.016, 1 + %exitcond = icmp eq i64 %inc, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 undef +} + +; We are not vectorizing with 12 runtime checks. +;CHECK: func2x6 +;CHECK-NOT: <4 x i32> +;CHECK: ret +define i32 @func2x6(i32* nocapture %out, i32* nocapture %out2, i32* nocapture %A, i32* nocapture %B, i32* nocapture %C, i32* nocapture %D, i32* nocapture %E, i32* nocapture %F) { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %i.037 = phi i64 [ 0, %entry ], [ %inc, %for.body ] + %arrayidx = getelementptr inbounds i32* %A, i64 %i.037 + %0 = load i32* %arrayidx, align 4 + %arrayidx1 = getelementptr inbounds i32* %B, i64 %i.037 + %1 = load i32* %arrayidx1, align 4 + %add = add nsw i32 %1, %0 + %arrayidx2 = getelementptr inbounds i32* %C, i64 %i.037 + %2 = load i32* %arrayidx2, align 4 + %add3 = add nsw i32 %add, %2 + %arrayidx4 = getelementptr inbounds i32* %E, i64 %i.037 + %3 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %add3, %3 + %arrayidx6 = getelementptr inbounds i32* %F, i64 %i.037 + %4 = load i32* %arrayidx6, align 4 + %add7 = add nsw i32 %add5, %4 + %arrayidx8 = getelementptr inbounds i32* %out, i64 %i.037 + store i32 %add7, i32* %arrayidx8, align 4 + %5 = load i32* %arrayidx, align 4 + %6 = load i32* %arrayidx1, align 4 + %add11 = add nsw i32 %6, %5 + %7 = load i32* %arrayidx2, align 4 + %add13 = add nsw i32 %add11, %7 + %8 = load i32* %arrayidx4, align 4 + %add15 = add nsw i32 %add13, %8 + %9 = load i32* %arrayidx6, align 4 + %add17 = add nsw i32 %add15, %9 + %arrayidx18 = getelementptr inbounds i32* %out2, i64 %i.037 + store i32 %add17, i32* %arrayidx18, align 4 + %inc = add i64 %i.037, 1 + %exitcond = icmp eq i64 %inc, 256 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret i32 undef +} + diff --git a/test/Transforms/LoopVectorize/start-non-zero.ll b/test/Transforms/LoopVectorize/start-non-zero.ll index 998001c3187b..e8a089a98120 100644 --- a/test/Transforms/LoopVectorize/start-non-zero.ll +++ b/test/Transforms/LoopVectorize/start-non-zero.ll @@ -18,9 +18,9 @@ for.body.lr.ph: ; preds = %entry for.body: ; preds = %for.body.lr.ph, %for.body %indvars.iv = phi i64 [ %0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body ] %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv - %1 = load i32* %arrayidx, align 4, !tbaa !0 + %1 = load i32* %arrayidx, align 4 %mul = mul nuw i32 %1, 333 - store i32 %mul, i32* %arrayidx, align 4, !tbaa !0 + store i32 %mul, i32* %arrayidx, align 4 %indvars.iv.next = add i64 %indvars.iv, 1 %2 = trunc i64 %indvars.iv.next to i32 %cmp = icmp slt i32 %2, %end @@ -29,7 +29,3 @@ for.body: ; preds = %for.body.lr.ph, %fo for.end: ; preds = %for.body, %entry ret i32 4 } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/struct_access.ll b/test/Transforms/LoopVectorize/struct_access.ll index de65d0d14870..573480d77cdd 100644 --- a/test/Transforms/LoopVectorize/struct_access.ll +++ b/test/Transforms/LoopVectorize/struct_access.ll @@ -33,7 +33,7 @@ for.body: ; preds = %entry, %for.body %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] %sum.05 = phi i32 [ %add, %for.body ], [ 0, %entry ] %x = getelementptr inbounds %struct.coordinate* %A, i64 %indvars.iv, i32 0 - %0 = load i32* %x, align 4, !tbaa !0 + %0 = load i32* %x, align 4 %add = add nsw i32 %0, %sum.05 %indvars.iv.next = add i64 %indvars.iv, 1 %lftr.wideiv = trunc i64 %indvars.iv.next to i32 @@ -44,7 +44,3 @@ for.end: ; preds = %for.body, %entry %sum.0.lcssa = phi i32 [ 0, %entry ], [ %add, %for.body ] ret i32 %sum.0.lcssa } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/LoopVectorize/value-ptr-bug.ll b/test/Transforms/LoopVectorize/value-ptr-bug.ll new file mode 100644 index 000000000000..f376656f0754 --- /dev/null +++ b/test/Transforms/LoopVectorize/value-ptr-bug.ll @@ -0,0 +1,50 @@ +; RUN: opt -S -loop-vectorize -force-vector-width=4 -force-vector-unroll=1 -dce -instcombine < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" + +; PR16073 + +; Because we were caching value pointers accross a function call that could RAUW +; we would generate an undefined value store below: +; SCEVExpander::expandCodeFor would change a value (the start value of an +; induction) that we cached in the induction variable list. + +; CHECK: test_vh +; CHECK-NOT: store <4 x i8> undef + +define void @test_vh(i32* %ptr265, i32* %ptr266, i32 %sub267) { +entry: + br label %loop + +loop: + %inc = phi i32 [ %sub267, %entry ], [ %add, %loop] + %ext.inc = sext i32 %inc to i64 + %add.ptr265 = getelementptr inbounds i32* %ptr265, i64 %ext.inc + %add.ptr266 = getelementptr inbounds i32* %ptr266, i64 %ext.inc + %add = add i32 %inc, 9 + %cmp = icmp slt i32 %add, 140 + br i1 %cmp, label %block1, label %loop + +block1: + %sub267.lcssa = phi i32 [ %add, %loop ] + %add.ptr266.lcssa = phi i32* [ %add.ptr266, %loop ] + %add.ptr265.lcssa = phi i32* [ %add.ptr265, %loop ] + %tmp29 = bitcast i32* %add.ptr265.lcssa to i8* + %tmp30 = bitcast i32* %add.ptr266.lcssa to i8* + br label %do.body272 + +do.body272: + %row_width.5 = phi i32 [ %sub267.lcssa, %block1 ], [ %dec, %do.body272 ] + %sp.4 = phi i8* [ %tmp30, %block1 ], [ %incdec.ptr273, %do.body272 ] + %dp.addr.4 = phi i8* [ %tmp29, %block1 ], [ %incdec.ptr274, %do.body272 ] + %incdec.ptr273 = getelementptr inbounds i8* %sp.4, i64 1 + %tmp31 = load i8* %sp.4, align 1 + %incdec.ptr274 = getelementptr inbounds i8* %dp.addr.4, i64 1 + store i8 %tmp31, i8* %dp.addr.4, align 1 + %dec = add i32 %row_width.5, -1 + %cmp276 = icmp eq i32 %dec, 0 + br i1 %cmp276, label %loop.exit, label %do.body272 + +loop.exit: + ret void +} diff --git a/test/Transforms/LoopVectorize/vectorize-once.ll b/test/Transforms/LoopVectorize/vectorize-once.ll index ac1694802a32..f289ded25de1 100644 --- a/test/Transforms/LoopVectorize/vectorize-once.ll +++ b/test/Transforms/LoopVectorize/vectorize-once.ll @@ -29,7 +29,7 @@ entry: for.body.i: ; preds = %entry, %for.body.i %__init.addr.05.i = phi i32 [ %add.i, %for.body.i ], [ 0, %entry ] %__first.addr.04.i = phi i32* [ %incdec.ptr.i, %for.body.i ], [ %A, %entry ] - %0 = load i32* %__first.addr.04.i, align 4, !tbaa !0 + %0 = load i32* %__first.addr.04.i, align 4 %add.i = add nsw i32 %0, %__init.addr.05.i %incdec.ptr.i = getelementptr inbounds i32* %__first.addr.04.i, i64 1 %cmp.i = icmp eq i32* %incdec.ptr.i, %add.ptr @@ -55,7 +55,7 @@ entry: for.body.i: ; preds = %entry, %for.body.i %__init.addr.05.i = phi i32 [ %add.i, %for.body.i ], [ 0, %entry ] %__first.addr.04.i = phi i32* [ %incdec.ptr.i, %for.body.i ], [ %A, %entry ] - %0 = load i32* %__first.addr.04.i, align 4, !tbaa !0 + %0 = load i32* %__first.addr.04.i, align 4 %add.i = add nsw i32 %0, %__init.addr.05.i %incdec.ptr.i = getelementptr inbounds i32* %__first.addr.04.i, i64 1 %cmp.i = icmp eq i32* %incdec.ptr.i, %add.ptr @@ -68,8 +68,5 @@ _ZSt10accumulateIPiiET0_T_S2_S1_.exit: ; preds = %for.body.i, %entry attributes #0 = { nounwind readonly ssp uwtable "fp-contract-model"="standard" "no-frame-pointer-elim" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="pic" "ssp-buffers-size"="8" } -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} !3 = metadata !{} diff --git a/test/Transforms/MergeFunc/crash.ll b/test/Transforms/MergeFunc/crash.ll new file mode 100644 index 000000000000..0897ba289337 --- /dev/null +++ b/test/Transforms/MergeFunc/crash.ll @@ -0,0 +1,46 @@ +; RUN: opt -mergefunc -disable-output < %s +; PR15185 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" +target triple = "i386-pc-linux-gnu" + +%.qux.2496 = type { i32, %.qux.2497 } +%.qux.2497 = type { i8, i32 } +%.qux.2585 = type { i32, i32, i8* } + +@g2 = external unnamed_addr constant [9 x i8], align 1 +@g3 = internal hidden unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] + +define internal hidden i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { + br label %1 + +; <label>:1 + br label %2 + +; <label>:2 + ret i32 undef +} + +define internal hidden i32 @func10(%.qux.2496* nocapture %this) align 2 { + %1 = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1 + %2 = load i32* %1, align 4 + ret i32 %2 +} + +define internal hidden i8* @func29(i32* nocapture %this) align 2 { + ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0) +} + +define internal hidden i32* @func33(%.qux.2585* nocapture %this) align 2 { + ret i32* undef +} + +define internal hidden i32* @func34(%.qux.2585* nocapture %this) align 2 { + %1 = getelementptr inbounds %.qux.2585* %this, i32 0 + ret i32* undef +} + +define internal hidden i8* @func35(%.qux.2585* nocapture %this) align 2 { + %1 = getelementptr inbounds %.qux.2585* %this, i32 0, i32 2 + %2 = load i8** %1, align 4 + ret i8* %2 +} diff --git a/test/Transforms/MergeFunc/inttoptr.ll b/test/Transforms/MergeFunc/inttoptr.ll new file mode 100644 index 000000000000..93250fa8ed1a --- /dev/null +++ b/test/Transforms/MergeFunc/inttoptr.ll @@ -0,0 +1,55 @@ +; RUN: opt -mergefunc -S < %s | FileCheck %s +; PR15185 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" +target triple = "i386-pc-linux-gnu" + +%.qux.2496 = type { i32, %.qux.2497 } +%.qux.2497 = type { i8, i32 } +%.qux.2585 = type { i32, i32, i8* } + +@g2 = external unnamed_addr constant [9 x i8], align 1 +@g3 = internal hidden unnamed_addr constant [1 x i8*] [i8* bitcast (i8* (%.qux.2585*)* @func35 to i8*)] + +define internal hidden i32 @func1(i32* %ptr, { i32, i32 }* nocapture %method) align 2 { +bb: + br label %bb1 + +bb1: ; preds = %bb + br label %bb2 + +bb2: ; preds = %bb1 + ret i32 undef +} + +define internal hidden i32 @func10(%.qux.2496* nocapture %this) align 2 { +bb: + %tmp = getelementptr inbounds %.qux.2496* %this, i32 0, i32 1, i32 1 + %tmp1 = load i32* %tmp, align 4 + ret i32 %tmp1 +} + +define internal hidden i8* @func29(i32* nocapture %this) align 2 { +bb: + ret i8* getelementptr inbounds ([9 x i8]* @g2, i32 0, i32 0) +} + +define internal hidden i32* @func33(%.qux.2585* nocapture %this) align 2 { +bb: + ret i32* undef +} + +define internal hidden i32* @func34(%.qux.2585* nocapture %this) align 2 { +bb: + %tmp = getelementptr inbounds %.qux.2585* %this, i32 0 + ret i32* undef +} + +define internal hidden i8* @func35(%.qux.2585* nocapture %this) align 2 { +bb: +; CHECK: %[[V2:.+]] = bitcast %.qux.2585* %{{.*}} to %.qux.2496* +; CHECK: %[[V3:.+]] = tail call i32 @func10(%.qux.2496* %[[V2]]) +; CHECK: %{{.*}} = inttoptr i32 %[[V3]] to i8* + %tmp = getelementptr inbounds %.qux.2585* %this, i32 0, i32 2 + %tmp1 = load i8** %tmp, align 4 + ret i8* %tmp1 +} diff --git a/test/Transforms/MergeFunc/vector.ll b/test/Transforms/MergeFunc/vector.ll index dba5fa349aba..56f74e65c60d 100644 --- a/test/Transforms/MergeFunc/vector.ll +++ b/test/Transforms/MergeFunc/vector.ll @@ -22,7 +22,7 @@ target triple = "x86_64-unknown-linux-gnu" define linkonce_odr void @_ZNSt6vectorIlSaIlEED1Ev(%"class.std::vector"* nocapture %this) unnamed_addr align 2 { entry: %tmp2.i.i = bitcast %"class.std::vector"* %this to i64** - %tmp3.i.i = load i64** %tmp2.i.i, align 8, !tbaa !0 + %tmp3.i.i = load i64** %tmp2.i.i, align 8 %tobool.i.i.i = icmp eq i64* %tmp3.i.i, null br i1 %tobool.i.i.i, label %_ZNSt6vectorIlSaIlEED2Ev.exit, label %if.then.i.i.i @@ -40,7 +40,7 @@ declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) define linkonce_odr void @_ZNSt6vectorIPvSaIS0_EED1Ev(%"class.std::vector"* nocapture %this) unnamed_addr align 2 { entry: %tmp2.i.i = bitcast %"class.std::vector"* %this to i8*** - %tmp3.i.i = load i8*** %tmp2.i.i, align 8, !tbaa !0 + %tmp3.i.i = load i8*** %tmp2.i.i, align 8 %tobool.i.i.i = icmp eq i8** %tmp3.i.i, null br i1 %tobool.i.i.i, label %_ZNSt6vectorIPvSaIS0_EED2Ev.exit, label %if.then.i.i.i @@ -70,8 +70,3 @@ declare void @_ZNSt6vectorIlSaIlEE13_M_insert_auxEN9__gnu_cxx17__normal_iterator declare void @_GLOBAL__I_a() declare %1 @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"long", metadata !1} diff --git a/test/Transforms/ObjCARC/apelim.ll b/test/Transforms/ObjCARC/apelim.ll index 4541b3f2fdf3..14412c6fc9c7 100644 --- a/test/Transforms/ObjCARC/apelim.ll +++ b/test/Transforms/ObjCARC/apelim.ll @@ -26,7 +26,7 @@ entry: ret void } -; CHECK: define internal void @_GLOBAL__I_x() +; CHECK: define internal void @_GLOBAL__I_x() { ; CHECK-NOT: @objc ; CHECK: } define internal void @_GLOBAL__I_x() { @@ -37,7 +37,7 @@ entry: ret void } -; CHECK: define internal void @_GLOBAL__I_y() +; CHECK: define internal void @_GLOBAL__I_y() { ; CHECK: %0 = call i8* @objc_autoreleasePoolPush() [[NUW:#[0-9]+]] ; CHECK: call void @objc_autoreleasePoolPop(i8* %0) [[NUW]] ; CHECK: } diff --git a/test/Transforms/ObjCARC/arc-annotations.ll b/test/Transforms/ObjCARC/arc-annotations.ll index 4c56b4a3def9..c0dea4b1b6a0 100644 --- a/test/Transforms/ObjCARC/arc-annotations.ll +++ b/test/Transforms/ObjCARC/arc-annotations.ll @@ -30,25 +30,25 @@ declare i8* @returner() ; CHECK: define void @test0( ; CHECK: entry: ; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: %0 = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup !0, !llvm.arc.annotation.topdown !1 +; CHECK: %0 = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup ![[ANN0:[0-9]+]], !llvm.arc.annotation.topdown ![[ANN1:[0-9]+]] ; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Use) ; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) ; CHECK: t: ; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) ; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: store float 2.000000e+00, float* %b, !llvm.arc.annotation.bottomup !2 +; CHECK: store float 2.000000e+00, float* %b, !llvm.arc.annotation.bottomup ![[ANN2:[0-9]+]] ; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) ; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) ; CHECK: f: ; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) ; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: store i32 7, i32* %x, !llvm.arc.annotation.bottomup !2 +; CHECK: store i32 7, i32* %x, !llvm.arc.annotation.bottomup ![[ANN2]] ; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) ; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) ; CHECK: return: ; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) ; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Release) -; CHECK: call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup !3, !llvm.arc.annotation.topdown !4 +; CHECK: call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup ![[ANN3:[0-9]+]], !llvm.arc.annotation.topdown ![[ANN4:[0-9]+]] ; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) ; CHECK: } define void @test0(i32* %x, i1 %p) nounwind { @@ -73,235 +73,11 @@ return: ret void } -; Like test0 but the release isn't always executed when the retain is, -; so the optimization is not safe. - -; TODO: Make the objc_release's argument be %0. - -; CHECK: define void @test1( -; CHECK: entry: -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: %0 = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup !5, !llvm.arc.annotation.topdown !6 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: t: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: store float 2.000000e+00, float* %b, !llvm.arc.annotation.bottomup !7 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: f: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: call void @callee(), !llvm.arc.annotation.topdown !8 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_CanRelease) -; CHECK: return: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Release) -; CHECK: call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup !9 -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: alt_return: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: } -define void @test1(i32* %x, i1 %p, i1 %q) nounwind { -entry: - %a = bitcast i32* %x to i8* - %0 = call i8* @objc_retain(i8* %a) nounwind - br i1 %p, label %t, label %f - -t: - store i8 3, i8* %a - %b = bitcast i32* %x to float* - store float 2.0, float* %b - br label %return - -f: - store i32 7, i32* %x - call void @callee() - br i1 %q, label %return, label %alt_return - -return: - %c = bitcast i32* %x to i8* - call void @objc_release(i8* %c) nounwind - ret void - -alt_return: - ret void -} - -; Don't do partial elimination into two different CFG diamonds. - -; CHECK: define void @test1b( -; CHECK: entry: -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: %0 = tail call i8* @objc_retain(i8* %x) #0, !llvm.arc.annotation.bottomup !10, !llvm.arc.annotation.topdown !11 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: if.then: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_CanRelease) -; CHECK: tail call void @callee(), !llvm.arc.annotation.bottomup !12, !llvm.arc.annotation.topdown !13 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Use) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_CanRelease) -; CHECK: if.end: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_CanRelease) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Use) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_CanRelease) -; CHECK: if.then3: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_CanRelease) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: tail call void @use_pointer(i8* %x), !llvm.arc.annotation.bottomup !14, !llvm.arc.annotation.topdown !15 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_MovableRelease) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Use) -; CHECK: if.end5: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_MovableRelease) -; CHECK: tail call void @objc_release(i8* %x) #0, !clang.imprecise_release !16, !llvm.arc.annotation.bottomup !17 -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: } -define void @test1b(i8* %x, i1 %p, i1 %q) { -entry: - tail call i8* @objc_retain(i8* %x) nounwind - br i1 %p, label %if.then, label %if.end - -if.then: ; preds = %entry - tail call void @callee() - br label %if.end - -if.end: ; preds = %if.then, %entry - br i1 %q, label %if.then3, label %if.end5 - -if.then3: ; preds = %if.end - tail call void @use_pointer(i8* %x) - br label %if.end5 - -if.end5: ; preds = %if.then3, %if.end - tail call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 - ret void -} - -; Like test0 but the pointer is passed to an intervening call, -; so the optimization is not safe. - -; CHECK: define void @test2( -; CHECK: entry: -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: %e = tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup !18, !llvm.arc.annotation.topdown !19 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_CanRelease) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: t: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Use) -; CHECK: store float 2.000000e+00, float* %b, !llvm.arc.annotation.bottomup !20 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: f: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_CanRelease) -; CHECK: call void @use_pointer(i8* %e), !llvm.arc.annotation.bottomup !21, !llvm.arc.annotation.topdown !22 -; CHECK: store float 3.000000e+00, float* %d, !llvm.arc.annotation.bottomup !20, !llvm.arc.annotation.topdown !23 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Use) -; CHECK: return: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Use) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Release) -; CHECK: call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup !24, !llvm.arc.annotation.topdown !25 -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: } -define void @test2(i32* %x, i1 %p) nounwind { -entry: - %a = bitcast i32* %x to i8* - %e = call i8* @objc_retain(i8* %a) nounwind - br i1 %p, label %t, label %f - -t: - store i8 3, i8* %a - %b = bitcast i32* %x to float* - store float 2.0, float* %b - br label %return - -f: - store i32 7, i32* %x - call void @use_pointer(i8* %e) - %d = bitcast i32* %x to float* - store float 3.0, float* %d - br label %return - -return: - %c = bitcast i32* %x to i8* - call void @objc_release(i8* %c) nounwind - ret void -} - -; Like test0 but the release is in a loop, -; so the optimization is not safe. - -; TODO: For now, assume this can't happen. - -; CHECK: define void @test3( -; CHECK: entry: -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_None) -; CHECK: tail call i8* @objc_retain(i8* %a) #0, !llvm.arc.annotation.bottomup !26, !llvm.arc.annotation.topdown !27 -; CHECK: call void @llvm.arc.annotation.bottomup.bbend(i8** @x, i8** @S_Release) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_Retain) -; CHECK: loop: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_Retain) -; CHECK: call void @llvm.arc.annotation.bottomup.bbstart(i8** @x, i8** @S_Release) -; CHECK: call void @objc_release(i8* %c) #0, !llvm.arc.annotation.bottomup !28, !llvm.arc.annotation.topdown !29 -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: return: -; CHECK: call void @llvm.arc.annotation.topdown.bbstart(i8** @x, i8** @S_None) -; CHECK: call void @llvm.arc.annotation.topdown.bbend(i8** @x, i8** @S_None) -; CHECK: } -define void @test3(i32* %x, i1* %q) nounwind { -entry: - %a = bitcast i32* %x to i8* - %0 = call i8* @objc_retain(i8* %a) nounwind - br label %loop - -loop: - %c = bitcast i32* %x to i8* - call void @objc_release(i8* %c) nounwind - %j = load volatile i1* %q - br i1 %j, label %loop, label %return - -return: - ret void -} - !0 = metadata !{} -; CHECK: !0 = metadata !{metadata !"(test0,%x)", metadata !"S_Use", metadata !"S_None"} -; CHECK: !1 = metadata !{metadata !"(test0,%x)", metadata !"S_None", metadata !"S_Retain"} -; CHECK: !2 = metadata !{metadata !"(test0,%x)", metadata !"S_Release", metadata !"S_Use"} -; CHECK: !3 = metadata !{metadata !"(test0,%x)", metadata !"S_None", metadata !"S_Release"} -; CHECK: !4 = metadata !{metadata !"(test0,%x)", metadata !"S_Retain", metadata !"S_None"} -; CHECK: !5 = metadata !{metadata !"(test1,%x)", metadata !"S_None", metadata !"S_None"} -; CHECK: !6 = metadata !{metadata !"(test1,%x)", metadata !"S_None", metadata !"S_Retain"} -; CHECK: !7 = metadata !{metadata !"(test1,%x)", metadata !"S_Release", metadata !"S_Use"} -; CHECK: !8 = metadata !{metadata !"(test1,%x)", metadata !"S_Retain", metadata !"S_CanRelease"} -; CHECK: !9 = metadata !{metadata !"(test1,%x)", metadata !"S_None", metadata !"S_Release"} -; CHECK: !10 = metadata !{metadata !"(test1b,%x)", metadata !"S_None", metadata !"S_None"} -; CHECK: !11 = metadata !{metadata !"(test1b,%x)", metadata !"S_None", metadata !"S_Retain"} -; CHECK: !12 = metadata !{metadata !"(test1b,%x)", metadata !"S_Use", metadata !"S_CanRelease"} -; CHECK: !13 = metadata !{metadata !"(test1b,%x)", metadata !"S_Retain", metadata !"S_CanRelease"} -; CHECK: !14 = metadata !{metadata !"(test1b,%x)", metadata !"S_MovableRelease", metadata !"S_Use"} -; CHECK: !15 = metadata !{metadata !"(test1b,%x)", metadata !"S_CanRelease", metadata !"S_Use"} -; CHECK: !16 = metadata !{} -; CHECK: !17 = metadata !{metadata !"(test1b,%x)", metadata !"S_None", metadata !"S_MovableRelease"} -; CHECK: !18 = metadata !{metadata !"(test2,%x)", metadata !"S_CanRelease", metadata !"S_None"} -; CHECK: !19 = metadata !{metadata !"(test2,%x)", metadata !"S_None", metadata !"S_Retain"} -; CHECK: !20 = metadata !{metadata !"(test2,%x)", metadata !"S_Release", metadata !"S_Use"} -; CHECK: !21 = metadata !{metadata !"(test2,%x)", metadata !"S_Use", metadata !"S_CanRelease"} -; CHECK: !22 = metadata !{metadata !"(test2,%x)", metadata !"S_Retain", metadata !"S_CanRelease"} -; CHECK: !23 = metadata !{metadata !"(test2,%x)", metadata !"S_CanRelease", metadata !"S_Use"} -; CHECK: !24 = metadata !{metadata !"(test2,%x)", metadata !"S_None", metadata !"S_Release"} -; CHECK: !25 = metadata !{metadata !"(test2,%x)", metadata !"S_Use", metadata !"S_None"} -; CHECK: !26 = metadata !{metadata !"(test3,%x)", metadata !"S_Release", metadata !"S_None"} -; CHECK: !27 = metadata !{metadata !"(test3,%x)", metadata !"S_None", metadata !"S_Retain"} -; CHECK: !28 = metadata !{metadata !"(test3,%x)", metadata !"S_None", metadata !"S_Release"} -; CHECK: !29 = metadata !{metadata !"(test3,%x)", metadata !"S_Retain", metadata !"S_None"} +; CHECK: ![[ANN0]] = metadata !{metadata !"(test0,%x)", metadata !"S_Use", metadata !"S_None"} +; CHECK: ![[ANN1]] = metadata !{metadata !"(test0,%x)", metadata !"S_None", metadata !"S_Retain"} +; CHECK: ![[ANN2]] = metadata !{metadata !"(test0,%x)", metadata !"S_Release", metadata !"S_Use"} +; CHECK: ![[ANN3]] = metadata !{metadata !"(test0,%x)", metadata !"S_None", metadata !"S_Release"} +; CHECK: ![[ANN4]] = metadata !{metadata !"(test0,%x)", metadata !"S_Retain", metadata !"S_None"} diff --git a/test/Transforms/ObjCARC/basic.ll b/test/Transforms/ObjCARC/basic.ll index 828a8a701127..ca1279206591 100644 --- a/test/Transforms/ObjCARC/basic.ll +++ b/test/Transforms/ObjCARC/basic.ll @@ -20,6 +20,7 @@ declare void @callee() declare void @callee_fnptr(void ()*) declare void @invokee() declare i8* @returner() +declare void @bar(i32 ()*) declare void @llvm.dbg.value(metadata, i64, metadata) @@ -28,10 +29,11 @@ declare i8* @objc_msgSend(i8*, i8*, ...) ; Simple retain+release pair deletion, with some intervening control ; flow and harmless instructions. -; CHECK: define void @test0( -; CHECK-NOT: @objc_ +; CHECK: define void @test0_precise(i32* %x, i1 %p) [[NUW:#[0-9]+]] { +; CHECK: @objc_retain +; CHECK: @objc_release ; CHECK: } -define void @test0(i32* %x, i1 %p) nounwind { +define void @test0_precise(i32* %x, i1 %p) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -53,16 +55,41 @@ return: ret void } +; CHECK: define void @test0_imprecise(i32* %x, i1 %p) [[NUW]] { +; CHECK-NOT: @objc_ +; CHECK: } +define void @test0_imprecise(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %return + +f: + store i32 7, i32* %x + br label %return + +return: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void +} + ; Like test0 but the release isn't always executed when the retain is, ; so the optimization is not safe. ; TODO: Make the objc_release's argument be %0. -; CHECK: define void @test1( +; CHECK: define void @test1_precise(i32* %x, i1 %p, i1 %q) [[NUW]] { ; CHECK: @objc_retain(i8* %a) ; CHECK: @objc_release ; CHECK: } -define void @test1(i32* %x, i1 %p, i1 %q) nounwind { +define void @test1_precise(i32* %x, i1 %p, i1 %q) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -88,9 +115,69 @@ alt_return: ret void } +; CHECK: define void @test1_imprecise(i32* %x, i1 %p, i1 %q) [[NUW]] { +; CHECK: @objc_retain(i8* %a) +; CHECK: @objc_release +; CHECK: } +define void @test1_imprecise(i32* %x, i1 %p, i1 %q) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %return + +f: + store i32 7, i32* %x + call void @callee() + br i1 %q, label %return, label %alt_return + +return: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void + +alt_return: + ret void +} + + ; Don't do partial elimination into two different CFG diamonds. -; CHECK: define void @test1b( +; CHECK: define void @test1b_precise(i8* %x, i1 %p, i1 %q) { +; CHECK: entry: +; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW]] +; CHECK-NOT: @objc_ +; CHECK: if.end5: +; CHECK: tail call void @objc_release(i8* %x) [[NUW]] +; CHECK-NOT: @objc_ +; CHECK: } +define void @test1b_precise(i8* %x, i1 %p, i1 %q) { +entry: + tail call i8* @objc_retain(i8* %x) nounwind + br i1 %p, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void @callee() + br label %if.end + +if.end: ; preds = %if.then, %entry + br i1 %q, label %if.then3, label %if.end5 + +if.then3: ; preds = %if.end + tail call void @use_pointer(i8* %x) + br label %if.end5 + +if.end5: ; preds = %if.then3, %if.end + tail call void @objc_release(i8* %x) nounwind + ret void +} + +; CHECK: define void @test1b_imprecise( ; CHECK: entry: ; CHECK: tail call i8* @objc_retain(i8* %x) [[NUW:#[0-9]+]] ; CHECK-NOT: @objc_ @@ -98,7 +185,7 @@ alt_return: ; CHECK: tail call void @objc_release(i8* %x) [[NUW]], !clang.imprecise_release !0 ; CHECK-NOT: @objc_ ; CHECK: } -define void @test1b(i8* %x, i1 %p, i1 %q) { +define void @test1b_imprecise(i8* %x, i1 %p, i1 %q) { entry: tail call i8* @objc_retain(i8* %x) nounwind br i1 %p, label %if.then, label %if.end @@ -119,14 +206,15 @@ if.end5: ; preds = %if.then3, %if.end ret void } + ; Like test0 but the pointer is passed to an intervening call, ; so the optimization is not safe. -; CHECK: define void @test2( +; CHECK: define void @test2_precise( ; CHECK: @objc_retain(i8* %a) ; CHECK: @objc_release ; CHECK: } -define void @test2(i32* %x, i1 %p) nounwind { +define void @test2_precise(i32* %x, i1 %p) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -151,16 +239,45 @@ return: ret void } +; CHECK: define void @test2_imprecise( +; CHECK: @objc_retain(i8* %a) +; CHECK: @objc_release +; CHECK: } +define void @test2_imprecise(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %return + +f: + store i32 7, i32* %x + call void @use_pointer(i8* %0) + %d = bitcast i32* %x to float* + store float 3.0, float* %d + br label %return + +return: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void +} + ; Like test0 but the release is in a loop, ; so the optimization is not safe. ; TODO: For now, assume this can't happen. -; CHECK: define void @test3( +; CHECK: define void @test3_precise( ; TODO: @objc_retain(i8* %a) ; TODO: @objc_release ; CHECK: } -define void @test3(i32* %x, i1* %q) nounwind { +define void @test3_precise(i32* %x, i1* %q) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -176,16 +293,37 @@ return: ret void } +; CHECK: define void @test3_imprecise( +; TODO: @objc_retain(i8* %a) +; TODO: @objc_release +; CHECK: } +define void @test3_imprecise(i32* %x, i1* %q) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br label %loop + +loop: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + %j = load volatile i1* %q + br i1 %j, label %loop, label %return + +return: + ret void +} + + ; TODO: For now, assume this can't happen. ; Like test0 but the retain is in a loop, ; so the optimization is not safe. -; CHECK: define void @test4( +; CHECK: define void @test4_precise( ; TODO: @objc_retain(i8* %a) ; TODO: @objc_release ; CHECK: } -define void @test4(i32* %x, i1* %q) nounwind { +define void @test4_precise(i32* %x, i1* %q) nounwind { entry: br label %loop @@ -201,14 +339,35 @@ return: ret void } +; CHECK: define void @test4_imprecise( +; TODO: @objc_retain(i8* %a) +; TODO: @objc_release +; CHECK: } +define void @test4_imprecise(i32* %x, i1* %q) nounwind { +entry: + br label %loop + +loop: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + %j = load volatile i1* %q + br i1 %j, label %loop, label %return + +return: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void +} + + ; Like test0 but the pointer is conditionally passed to an intervening call, ; so the optimization is not safe. -; CHECK: define void @test5( +; CHECK: define void @test5a( ; CHECK: @objc_retain(i8* ; CHECK: @objc_release ; CHECK: } -define void @test5(i32* %x, i1 %q, i8* %y) nounwind { +define void @test5a(i32* %x, i1 %q, i8* %y) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -220,13 +379,98 @@ entry: ret void } +; CHECK: define void @test5b( +; CHECK: @objc_retain(i8* +; CHECK: @objc_release +; CHECK: } +define void @test5b(i32* %x, i1 %q, i8* %y) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + %s = select i1 %q, i8* %y, i8* %0 + call void @use_pointer(i8* %s) + store i32 7, i32* %x + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void +} + + ; retain+release pair deletion, where the release happens on two different ; flow paths. -; CHECK: define void @test6( +; CHECK: define void @test6a( +; CHECK: entry: +; CHECK: tail call i8* @objc_retain( +; CHECK: t: +; CHECK: call void @objc_release( +; CHECK: f: +; CHECK: call void @objc_release( +; CHECK: return: +; CHECK: } +define void @test6a(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + %ct = bitcast i32* %x to i8* + call void @objc_release(i8* %ct) nounwind + br label %return + +f: + store i32 7, i32* %x + call void @callee() + %cf = bitcast i32* %x to i8* + call void @objc_release(i8* %cf) nounwind + br label %return + +return: + ret void +} + +; CHECK: define void @test6b( ; CHECK-NOT: @objc_ ; CHECK: } -define void @test6(i32* %x, i1 %p) nounwind { +define void @test6b(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + %ct = bitcast i32* %x to i8* + call void @objc_release(i8* %ct) nounwind, !clang.imprecise_release !0 + br label %return + +f: + store i32 7, i32* %x + call void @callee() + %cf = bitcast i32* %x to i8* + call void @objc_release(i8* %cf) nounwind, !clang.imprecise_release !0 + br label %return + +return: + ret void +} + +; CHECK: define void @test6c( +; CHECK: entry: +; CHECK: tail call i8* @objc_retain( +; CHECK: t: +; CHECK: call void @objc_release( +; CHECK: f: +; CHECK: call void @objc_release( +; CHECK: return: +; CHECK: } +define void @test6c(i32* %x, i1 %p) nounwind { entry: %a = bitcast i32* %x to i8* %0 = call i8* @objc_retain(i8* %a) nounwind @@ -244,6 +488,40 @@ f: store i32 7, i32* %x call void @callee() %cf = bitcast i32* %x to i8* + call void @objc_release(i8* %cf) nounwind, !clang.imprecise_release !0 + br label %return + +return: + ret void +} + +; CHECK: define void @test6d( +; CHECK: entry: +; CHECK: tail call i8* @objc_retain( +; CHECK: t: +; CHECK: call void @objc_release( +; CHECK: f: +; CHECK: call void @objc_release( +; CHECK: return: +; CHECK: } +define void @test6d(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + %0 = call i8* @objc_retain(i8* %a) nounwind + br i1 %p, label %t, label %f + +t: + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + %ct = bitcast i32* %x to i8* + call void @objc_release(i8* %ct) nounwind, !clang.imprecise_release !0 + br label %return + +f: + store i32 7, i32* %x + call void @callee() + %cf = bitcast i32* %x to i8* call void @objc_release(i8* %cf) nounwind br label %return @@ -251,11 +529,19 @@ return: ret void } + ; retain+release pair deletion, where the retain happens on two different ; flow paths. -; CHECK: define void @test7( -; CHECK-NOT: @objc_ +; CHECK: define void @test7( +; CHECK: entry: +; CHECK-NOT: objc_ +; CHECK: t: +; CHECK: call i8* @objc_retain +; CHECK: f: +; CHECK: call i8* @objc_retain +; CHECK: return: +; CHECK: call void @objc_release ; CHECK: } define void @test7(i32* %x, i1 %p) nounwind { entry: @@ -281,17 +567,44 @@ return: ret void } +; CHECK: define void @test7b( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test7b(i32* %x, i1 %p) nounwind { +entry: + %a = bitcast i32* %x to i8* + br i1 %p, label %t, label %f + +t: + %0 = call i8* @objc_retain(i8* %a) nounwind + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %return + +f: + %1 = call i8* @objc_retain(i8* %a) nounwind + store i32 7, i32* %x + call void @callee() + br label %return + +return: + %c = bitcast i32* %x to i8* + call void @objc_release(i8* %c) nounwind, !clang.imprecise_release !0 + ret void +} + ; Like test7, but there's a retain/retainBlock mismatch. Don't delete! -; CHECK: define void @test7b +; CHECK: define void @test7c ; CHECK: t: -; CHECK: call i8* @objc_retainBlock +; CHECK: call i8* @objc_retainBlock ; CHECK: f: -; CHECK: call i8* @objc_retain +; CHECK: call i8* @objc_retain ; CHECK: return: -; CHECK: call void @objc_release +; CHECK: call void @objc_release ; CHECK: } -define void @test7b(i32* %x, i1 %p) nounwind { +define void @test7c(i32* %x, i1 %p) nounwind { entry: %a = bitcast i32* %x to i8* br i1 %p, label %t, label %f @@ -318,10 +631,106 @@ return: ; retain+release pair deletion, where the retain and release both happen on ; different flow paths. Wild! -; CHECK: define void @test8( +; CHECK: define void @test8a( +; CHECK: entry: +; CHECK: t: +; CHECK: @objc_retain +; CHECK: f: +; CHECK: @objc_retain +; CHECK: mid: +; CHECK: u: +; CHECK: @objc_release +; CHECK: g: +; CHECK: @objc_release +; CHECK: return: +; CHECK: } +define void @test8a(i32* %x, i1 %p, i1 %q) nounwind { +entry: + %a = bitcast i32* %x to i8* + br i1 %p, label %t, label %f + +t: + %0 = call i8* @objc_retain(i8* %a) nounwind + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %mid + +f: + %1 = call i8* @objc_retain(i8* %a) nounwind + store i32 7, i32* %x + br label %mid + +mid: + br i1 %q, label %u, label %g + +u: + call void @callee() + %cu = bitcast i32* %x to i8* + call void @objc_release(i8* %cu) nounwind + br label %return + +g: + %cg = bitcast i32* %x to i8* + call void @objc_release(i8* %cg) nounwind + br label %return + +return: + ret void +} + +; CHECK: define void @test8b( ; CHECK-NOT: @objc_ ; CHECK: } -define void @test8(i32* %x, i1 %p, i1 %q) nounwind { +define void @test8b(i32* %x, i1 %p, i1 %q) nounwind { +entry: + %a = bitcast i32* %x to i8* + br i1 %p, label %t, label %f + +t: + %0 = call i8* @objc_retain(i8* %a) nounwind + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %mid + +f: + %1 = call i8* @objc_retain(i8* %a) nounwind + store i32 7, i32* %x + br label %mid + +mid: + br i1 %q, label %u, label %g + +u: + call void @callee() + %cu = bitcast i32* %x to i8* + call void @objc_release(i8* %cu) nounwind, !clang.imprecise_release !0 + br label %return + +g: + %cg = bitcast i32* %x to i8* + call void @objc_release(i8* %cg) nounwind, !clang.imprecise_release !0 + br label %return + +return: + ret void +} + +; CHECK: define void @test8c( +; CHECK: entry: +; CHECK: t: +; CHECK: @objc_retain +; CHECK: f: +; CHECK: @objc_retain +; CHECK: mid: +; CHECK: u: +; CHECK: @objc_release +; CHECK: g: +; CHECK: @objc_release +; CHECK: return: +; CHECK: } +define void @test8c(i32* %x, i1 %p, i1 %q) nounwind { entry: %a = bitcast i32* %x to i8* br i1 %p, label %t, label %f @@ -349,6 +758,54 @@ u: g: %cg = bitcast i32* %x to i8* + call void @objc_release(i8* %cg) nounwind, !clang.imprecise_release !0 + br label %return + +return: + ret void +} + +; CHECK: define void @test8d( +; CHECK: entry: +; CHECK: t: +; CHECK: @objc_retain +; CHECK: f: +; CHECK: @objc_retain +; CHECK: mid: +; CHECK: u: +; CHECK: @objc_release +; CHECK: g: +; CHECK: @objc_release +; CHECK: return: +; CHECK: } +define void @test8d(i32* %x, i1 %p, i1 %q) nounwind { +entry: + %a = bitcast i32* %x to i8* + br i1 %p, label %t, label %f + +t: + %0 = call i8* @objc_retain(i8* %a) nounwind + store i8 3, i8* %a + %b = bitcast i32* %x to float* + store float 2.0, float* %b + br label %mid + +f: + %1 = call i8* @objc_retain(i8* %a) nounwind + store i32 7, i32* %x + br label %mid + +mid: + br i1 %q, label %u, label %g + +u: + call void @callee() + %cu = bitcast i32* %x to i8* + call void @objc_release(i8* %cu) nounwind, !clang.imprecise_release !0 + br label %return + +g: + %cg = bitcast i32* %x to i8* call void @objc_release(i8* %cg) nounwind br label %return @@ -486,6 +943,7 @@ entry: ; CHECK-NEXT: @use_pointer ; CHECK-NEXT: @use_pointer ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test13b(i8* %x, i64 %n) { entry: call i8* @objc_retain(i8* %x) nounwind @@ -527,6 +985,7 @@ entry: ; CHECK-NEXT: @use_pointer ; CHECK-NEXT: @use_pointer ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test13d(i8* %x, i64 %n) { entry: call i8* @objc_retain(i8* %x) nounwind @@ -583,7 +1042,9 @@ entry: ; CHECK: define void @test15b ; CHECK-NEXT: entry: +; CHECK-NEXT: @objc_retain ; CHECK-NEXT: @objc_autorelease +; CHECK-NEXT: @objc_release ; CHECK-NEXT: ret void ; CHECK-NEXT: } define void @test15b(i8* %x, i64 %n) { @@ -594,13 +1055,60 @@ entry: ret void } +; CHECK: define void @test15c +; CHECK-NEXT: entry: +; CHECK-NEXT: @objc_autorelease +; CHECK-NEXT: ret void +; CHECK-NEXT: } +define void @test15c(i8* %x, i64 %n) { +entry: + call i8* @objc_retain(i8* %x) nounwind + call i8* @objc_autorelease(i8* %x) nounwind + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + ret void +} + ; Retain+release pairs in diamonds, all dominated by a retain. -; CHECK: define void @test16( +; CHECK: define void @test16a( +; CHECK: @objc_retain(i8* %x) +; CHECK-NOT: @objc +; CHECK: } +define void @test16a(i1 %a, i1 %b, i8* %x) { +entry: + call i8* @objc_retain(i8* %x) nounwind + br i1 %a, label %red, label %orange + +red: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +orange: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +yellow: + call void @use_pointer(i8* %x) + call void @use_pointer(i8* %x) + br i1 %b, label %green, label %blue + +green: + call void @objc_release(i8* %x) nounwind + br label %purple + +blue: + call void @objc_release(i8* %x) nounwind + br label %purple + +purple: + ret void +} + +; CHECK: define void @test16b( ; CHECK: @objc_retain(i8* %x) ; CHECK-NOT: @objc ; CHECK: } -define void @test16(i1 %a, i1 %b, i8* %x) { +define void @test16b(i1 %a, i1 %b, i8* %x) { entry: call i8* @objc_retain(i8* %x) nounwind br i1 %a, label %red, label %orange @@ -619,17 +1127,86 @@ yellow: br i1 %b, label %green, label %blue green: + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + br label %purple + +blue: call void @objc_release(i8* %x) nounwind br label %purple +purple: + ret void +} + +; CHECK: define void @test16c( +; CHECK: @objc_retain(i8* %x) +; CHECK-NOT: @objc +; CHECK: } +define void @test16c(i1 %a, i1 %b, i8* %x) { +entry: + call i8* @objc_retain(i8* %x) nounwind + br i1 %a, label %red, label %orange + +red: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +orange: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +yellow: + call void @use_pointer(i8* %x) + call void @use_pointer(i8* %x) + br i1 %b, label %green, label %blue + +green: + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + br label %purple + blue: + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + br label %purple + +purple: + ret void +} + +; CHECK: define void @test16d( +; CHECK: @objc_retain(i8* %x) +; CHECK-NOT: @objc +; CHECK: } +define void @test16d(i1 %a, i1 %b, i8* %x) { +entry: + call i8* @objc_retain(i8* %x) nounwind + br i1 %a, label %red, label %orange + +red: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +orange: + call i8* @objc_retain(i8* %x) nounwind + br label %yellow + +yellow: + call void @use_pointer(i8* %x) + call void @use_pointer(i8* %x) + br i1 %b, label %green, label %blue + +green: call void @objc_release(i8* %x) nounwind br label %purple +blue: + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + br label %purple + purple: ret void } + ; Retain+release pairs in diamonds, all post-dominated by a release. ; CHECK: define void @test17( @@ -720,6 +1297,7 @@ entry: ; CHECK: define void @test20( ; CHECK: %tmp1 = tail call i8* @objc_retain(i8* %tmp) [[NUW]] ; CHECK-NEXT: invoke +; CHECK: } define void @test20(double* %self) { if.then12: %tmp = bitcast double* %self to i8* @@ -747,6 +1325,7 @@ if.end: ; preds = %invoke.cont23 ; CHECK: define i8* @test21( ; CHECK: call i8* @returner() ; CHECK-NEXT: ret i8* %call +; CHECK-NEXT: } define i8* @test21() { entry: %call = call i8* @returner() @@ -799,7 +1378,7 @@ entry: ; Don't optimize objc_retainBlock, but do strength reduce it. -; CHECK: define void @test23b +; CHECK: define void @test23b(i8* %p) { ; CHECK: @objc_retain ; CHECK: @objc_release ; CHECK: } @@ -1163,12 +1742,16 @@ done: ret void } -; Delete retain,release if there's just a possible dec. +; Delete retain,release if there's just a possible dec and we have imprecise +; releases. -; CHECK: define void @test34( -; CHECK-NOT: @objc_ +; CHECK: define void @test34a( +; CHECK: call i8* @objc_retain +; CHECK: true: +; CHECK: done: +; CHECK: call void @objc_release ; CHECK: } -define void @test34(i8* %p, i1 %x, i8* %y) { +define void @test34a(i8* %p, i1 %x, i8* %y) { entry: %f0 = call i8* @objc_retain(i8* %p) br i1 %x, label %true, label %done @@ -1184,12 +1767,38 @@ done: ret void } -; Delete retain,release if there's just a use. - -; CHECK: define void @test35( +; CHECK: define void @test34b( ; CHECK-NOT: @objc_ ; CHECK: } -define void @test35(i8* %p, i1 %x, i8* %y) { +define void @test34b(i8* %p, i1 %x, i8* %y) { +entry: + %f0 = call i8* @objc_retain(i8* %p) + br i1 %x, label %true, label %done + +true: + call void @callee() + br label %done + +done: + %g = bitcast i8* %p to i8* + %h = getelementptr i8* %g, i64 0 + call void @objc_release(i8* %g), !clang.imprecise_release !0 + ret void +} + + +; Delete retain,release if there's just a use and we do not have a precise +; release. + +; Precise. +; CHECK: define void @test35a( +; CHECK: entry: +; CHECK: call i8* @objc_retain +; CHECK: true: +; CHECK: done: +; CHECK: call void @objc_release +; CHECK: } +define void @test35a(i8* %p, i1 %x, i8* %y) { entry: %f0 = call i8* @objc_retain(i8* %p) br i1 %x, label %true, label %done @@ -1205,16 +1814,36 @@ done: ret void } -; Delete a retain,release if there's no actual use. - -; CHECK: define void @test36( +; Imprecise. +; CHECK: define void @test35b( ; CHECK-NOT: @objc_ +; CHECK: } +define void @test35b(i8* %p, i1 %x, i8* %y) { +entry: + %f0 = call i8* @objc_retain(i8* %p) + br i1 %x, label %true, label %done + +true: + %v = icmp eq i8* %p, %y + br label %done + +done: + %g = bitcast i8* %p to i8* + %h = getelementptr i8* %g, i64 0 + call void @objc_release(i8* %g), !clang.imprecise_release !0 + ret void +} + +; Delete a retain,release if there's no actual use and we have precise release. + +; CHECK: define void @test36a( +; CHECK: @objc_retain ; CHECK: call void @callee() ; CHECK-NOT: @objc_ ; CHECK: call void @callee() -; CHECK-NOT: @objc_ +; CHECK: @objc_release ; CHECK: } -define void @test36(i8* %p) { +define void @test36a(i8* %p) { entry: call i8* @objc_retain(i8* %p) call void @callee() @@ -1225,10 +1854,10 @@ entry: ; Like test36, but with metadata. -; CHECK: define void @test37( +; CHECK: define void @test36b( ; CHECK-NOT: @objc_ ; CHECK: } -define void @test37(i8* %p) { +define void @test36b(i8* %p) { entry: call i8* @objc_retain(i8* %p) call void @callee() @@ -1439,6 +2068,7 @@ define void @test44(i8** %pp) { ; CHECK: call void @objc_release(i8* %q) ; CHECK: call void @use_pointer(i8* %p) ; CHECK: call void @objc_release(i8* %p) +; CHECK: } define void @test45(i8** %pp, i8** %qq) { %p = load i8** %pp %q = load i8** %qq @@ -1455,6 +2085,7 @@ define void @test45(i8** %pp, i8** %qq) { ; CHECK: tail call i8* @objc_retain(i8* %p) [[NUW]] ; CHECK: true: ; CHECK: call i8* @objc_autorelease(i8* %p) [[NUW]] +; CHECK: } define void @test46(i8* %p, i1 %a) { entry: call i8* @objc_retain(i8* %p) @@ -1474,6 +2105,7 @@ false: ; CHECK: define i8* @test47( ; CHECK-NOT: call ; CHECK: ret i8* %p +; CHECK: } define i8* @test47(i8* %p) nounwind { %x = call i8* @objc_retainedObject(i8* %p) ret i8* %x @@ -1484,6 +2116,7 @@ define i8* @test47(i8* %p) nounwind { ; CHECK: define i8* @test48( ; CHECK-NOT: call ; CHECK: ret i8* %p +; CHECK: } define i8* @test48(i8* %p) nounwind { %x = call i8* @objc_unretainedObject(i8* %p) ret i8* %x @@ -1494,32 +2127,51 @@ define i8* @test48(i8* %p) nounwind { ; CHECK: define i8* @test49( ; CHECK-NOT: call ; CHECK: ret i8* %p +; CHECK: } define i8* @test49(i8* %p) nounwind { %x = call i8* @objc_unretainedPointer(i8* %p) ret i8* %x } -; Do delete retain+release with intervening stores of the -; address value. +; Do delete retain+release with intervening stores of the address value if we +; have imprecise release attached to objc_release. -; CHECK: define void @test50( +; CHECK: define void @test50a( +; CHECK-NEXT: call i8* @objc_retain +; CHECK-NEXT: call void @callee +; CHECK-NEXT: store +; CHECK-NEXT: call void @objc_release +; CHECK-NEXT: ret void +; CHECK-NEXT: } +define void @test50a(i8* %p, i8** %pp) { + call i8* @objc_retain(i8* %p) + call void @callee() + store i8* %p, i8** %pp + call void @objc_release(i8* %p) + ret void +} + +; CHECK: define void @test50b( ; CHECK-NOT: @objc_ ; CHECK: } -define void @test50(i8* %p, i8** %pp) { +define void @test50b(i8* %p, i8** %pp) { call i8* @objc_retain(i8* %p) call void @callee() store i8* %p, i8** %pp - call void @objc_release(i8* %p) + call void @objc_release(i8* %p), !clang.imprecise_release !0 ret void } + ; Don't delete retain+release with intervening stores through the ; address value. -; CHECK: define void @test51( +; CHECK: define void @test51a( ; CHECK: call i8* @objc_retain(i8* %p) ; CHECK: call void @objc_release(i8* %p) -define void @test51(i8* %p) { +; CHECK: ret void +; CHECK: } +define void @test51a(i8* %p) { call i8* @objc_retain(i8* %p) call void @callee() store i8 0, i8* %p @@ -1527,15 +2179,30 @@ define void @test51(i8* %p) { ret void } +; CHECK: define void @test51b( +; CHECK: call i8* @objc_retain(i8* %p) +; CHECK: call void @objc_release(i8* %p) +; CHECK: ret void +; CHECK: } +define void @test51b(i8* %p) { + call i8* @objc_retain(i8* %p) + call void @callee() + store i8 0, i8* %p + call void @objc_release(i8* %p), !clang.imprecise_release !0 + ret void +} + ; Don't delete retain+release with intervening use of a pointer of ; unknown provenance. -; CHECK: define void @test52( +; CHECK: define void @test52a( ; CHECK: call i8* @objc_retain ; CHECK: call void @callee() ; CHECK: call void @use_pointer(i8* %z) ; CHECK: call void @objc_release -define void @test52(i8** %zz, i8** %pp) { +; CHECK: ret void +; CHECK: } +define void @test52a(i8** %zz, i8** %pp) { %p = load i8** %pp %1 = call i8* @objc_retain(i8* %p) call void @callee() @@ -1545,6 +2212,23 @@ define void @test52(i8** %zz, i8** %pp) { ret void } +; CHECK: define void @test52b( +; CHECK: call i8* @objc_retain +; CHECK: call void @callee() +; CHECK: call void @use_pointer(i8* %z) +; CHECK: call void @objc_release +; CHECK: ret void +; CHECK: } +define void @test52b(i8** %zz, i8** %pp) { + %p = load i8** %pp + %1 = call i8* @objc_retain(i8* %p) + call void @callee() + %z = load i8** %zz + call void @use_pointer(i8* %z) + call void @objc_release(i8* %p), !clang.imprecise_release !0 + ret void +} + ; Like test52, but the pointer has function type, so it's assumed to ; be not reference counted. ; Oops. That's wrong. Clang sometimes uses function types gratuitously. @@ -1569,6 +2253,7 @@ define void @test53(void ()** %zz, i8** %pp) { ; CHECK: call i8* @returner() ; CHECK-NEXT: call void @objc_release(i8* %t) [[NUW]], !clang.imprecise_release !0 ; CHECK-NEXT: ret void +; CHECK: } define void @test54() { %t = call i8* @returner() call i8* @objc_autorelease(i8* %t) @@ -1697,19 +2382,78 @@ entry: @constptr = external constant i8* @something = external global i8* -; CHECK: define void @test60( -; CHECK-NOT: @objc_ +; We have a precise lifetime retain/release here. We can not remove them since +; @something is not constant. + +; CHECK: define void @test60a( +; CHECK: call i8* @objc_retain +; CHECK: call void @objc_release +; CHECK: } +define void @test60a() { + %t = load i8** @constptr + %s = load i8** @something + call i8* @objc_retain(i8* %s) + call void @callee() + call void @use_pointer(i8* %t) + call void @objc_release(i8* %s) + ret void +} + +; CHECK: define void @test60b( +; CHECK: call i8* @objc_retain +; CHECK-NOT: call i8* @objc_retain +; CHECK-NOT: call i8* @objc_rrelease ; CHECK: } -define void @test60() { +define void @test60b() { %t = load i8** @constptr %s = load i8** @something call i8* @objc_retain(i8* %s) + call i8* @objc_retain(i8* %s) call void @callee() call void @use_pointer(i8* %t) call void @objc_release(i8* %s) ret void } +; CHECK: define void @test60c( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test60c() { + %t = load i8** @constptr + %s = load i8** @something + call i8* @objc_retain(i8* %s) + call void @callee() + call void @use_pointer(i8* %t) + call void @objc_release(i8* %s), !clang.imprecise_release !0 + ret void +} + +; CHECK: define void @test60d( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test60d() { + %t = load i8** @constptr + %s = load i8** @something + call i8* @objc_retain(i8* %t) + call void @callee() + call void @use_pointer(i8* %s) + call void @objc_release(i8* %t) + ret void +} + +; CHECK: define void @test60e( +; CHECK-NOT: @objc_ +; CHECK: } +define void @test60e() { + %t = load i8** @constptr + %s = load i8** @something + call i8* @objc_retain(i8* %t) + call void @callee() + call void @use_pointer(i8* %s) + call void @objc_release(i8* %t), !clang.imprecise_release !0 + ret void +} + ; Constant pointers to objects don't need to be considered related to other ; pointers. @@ -1876,11 +2620,13 @@ return: ; preds = %if.then, %entry ; An objc_retain can serve as a may-use for a different pointer. ; rdar://11931823 -; CHECK: define void @test66( -; CHECK: %tmp7 = tail call i8* @objc_retain(i8* %cond) [[NUW]] +; CHECK: define void @test66a( +; CHECK: tail call i8* @objc_retain(i8* %cond) [[NUW]] +; CHECK: tail call void @objc_release(i8* %call) [[NUW]] +; CHECK: tail call i8* @objc_retain(i8* %tmp8) [[NUW]] ; CHECK: tail call void @objc_release(i8* %cond) [[NUW]] ; CHECK: } -define void @test66(i8* %tmp5, i8* %bar, i1 %tobool, i1 %tobool1, i8* %call) { +define void @test66a(i8* %tmp5, i8* %bar, i1 %tobool, i1 %tobool1, i8* %call) { entry: br i1 %tobool, label %cond.true, label %cond.end @@ -1897,7 +2643,74 @@ cond.end: ; preds = %cond.true, %entry ret void } -declare void @bar(i32 ()*) +; CHECK: define void @test66b( +; CHECK: tail call i8* @objc_retain(i8* %cond) [[NUW]] +; CHECK: tail call void @objc_release(i8* %call) [[NUW]] +; CHECK: tail call i8* @objc_retain(i8* %tmp8) [[NUW]] +; CHECK: tail call void @objc_release(i8* %cond) [[NUW]] +; CHECK: } +define void @test66b(i8* %tmp5, i8* %bar, i1 %tobool, i1 %tobool1, i8* %call) { +entry: + br i1 %tobool, label %cond.true, label %cond.end + +cond.true: + br label %cond.end + +cond.end: ; preds = %cond.true, %entry + %cond = phi i8* [ %tmp5, %cond.true ], [ %call, %entry ] + %tmp7 = tail call i8* @objc_retain(i8* %cond) nounwind + tail call void @objc_release(i8* %call) nounwind, !clang.imprecise_release !0 + %tmp8 = select i1 %tobool1, i8* %cond, i8* %bar + %tmp9 = tail call i8* @objc_retain(i8* %tmp8) nounwind + tail call void @objc_release(i8* %cond) nounwind + ret void +} + +; CHECK: define void @test66c( +; CHECK: tail call i8* @objc_retain(i8* %cond) [[NUW]] +; CHECK: tail call void @objc_release(i8* %call) [[NUW]] +; CHECK: tail call i8* @objc_retain(i8* %tmp8) [[NUW]] +; CHECK: tail call void @objc_release(i8* %cond) [[NUW]] +; CHECK: } +define void @test66c(i8* %tmp5, i8* %bar, i1 %tobool, i1 %tobool1, i8* %call) { +entry: + br i1 %tobool, label %cond.true, label %cond.end + +cond.true: + br label %cond.end + +cond.end: ; preds = %cond.true, %entry + %cond = phi i8* [ %tmp5, %cond.true ], [ %call, %entry ] + %tmp7 = tail call i8* @objc_retain(i8* %cond) nounwind + tail call void @objc_release(i8* %call) nounwind + %tmp8 = select i1 %tobool1, i8* %cond, i8* %bar + %tmp9 = tail call i8* @objc_retain(i8* %tmp8) nounwind, !clang.imprecise_release !0 + tail call void @objc_release(i8* %cond) nounwind + ret void +} + +; CHECK: define void @test66d( +; CHECK: tail call i8* @objc_retain(i8* %cond) [[NUW]] +; CHECK: tail call void @objc_release(i8* %call) [[NUW]] +; CHECK: tail call i8* @objc_retain(i8* %tmp8) [[NUW]] +; CHECK: tail call void @objc_release(i8* %cond) [[NUW]] +; CHECK: } +define void @test66d(i8* %tmp5, i8* %bar, i1 %tobool, i1 %tobool1, i8* %call) { +entry: + br i1 %tobool, label %cond.true, label %cond.end + +cond.true: + br label %cond.end + +cond.end: ; preds = %cond.true, %entry + %cond = phi i8* [ %tmp5, %cond.true ], [ %call, %entry ] + %tmp7 = tail call i8* @objc_retain(i8* %cond) nounwind + tail call void @objc_release(i8* %call) nounwind, !clang.imprecise_release !0 + %tmp8 = select i1 %tobool1, i8* %cond, i8* %bar + %tmp9 = tail call i8* @objc_retain(i8* %tmp8) nounwind + tail call void @objc_release(i8* %cond) nounwind, !clang.imprecise_release !0 + ret void +} ; A few real-world testcases. @@ -1907,7 +2720,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare i32 @puts(i8* nocapture) nounwind @str = internal constant [16 x i8] c"-[ Top0 _getX ]\00" -; CHECK: @"\01-[A z]" +; CHECK: define { <2 x float>, <2 x float> } @"\01-[A z]"({}* %self, i8* nocapture %_cmd) [[NUW]] { ; CHECK-NOT: @objc_ ; CHECK: } @@ -1953,7 +2766,7 @@ invoke.cont: ret {<2 x float>, <2 x float>} %tmp35 } -; CHECK: @"\01-[Top0 _getX]" +; CHECK: @"\01-[Top0 _getX]"({}* %self, i8* nocapture %_cmd) [[NUW]] { ; CHECK-NOT: @objc_ ; CHECK: } @@ -1972,12 +2785,13 @@ invoke.cont: ; A simple loop. Eliminate the retain and release inside of it! -; CHECK: define void @loop +; CHECK: define void @loop(i8* %x, i64 %n) { ; CHECK: for.body: ; CHECK-NOT: @objc_ ; CHECK: @objc_msgSend ; CHECK-NOT: @objc_ ; CHECK: for.end: +; CHECK: } define void @loop(i8* %x, i64 %n) { entry: %0 = tail call i8* @objc_retain(i8* %x) nounwind @@ -2001,7 +2815,7 @@ for.end: ; preds = %for.body, %entry ; ObjCARCOpt can delete the retain,release on self. -; CHECK: define void @TextEditTest +; CHECK: define void @TextEditTest(%2* %self, %3* %pboard) { ; CHECK-NOT: call i8* @objc_retain(i8* %tmp7) ; CHECK: } diff --git a/test/Transforms/ObjCARC/cfg-hazards.ll b/test/Transforms/ObjCARC/cfg-hazards.ll index 899298b5967e..0156d5bfb464 100644 --- a/test/Transforms/ObjCARC/cfg-hazards.ll +++ b/test/Transforms/ObjCARC/cfg-hazards.ll @@ -8,6 +8,7 @@ declare void @use_pointer(i8*) declare i8* @objc_retain(i8*) declare void @objc_release(i8*) declare void @callee() +declare void @block_callee(void ()*) ; CHECK: define void @test0( ; CHECK: call i8* @objc_retain( @@ -394,6 +395,41 @@ exit: ret void } +; Do not improperly pair retains in a for loop with releases outside of a for +; loop when the proper pairing is disguised by a separate provenance represented +; by an alloca. +; rdar://12969722 + +; CHECK: define void @test13(i8* %a) [[NUW]] { +; CHECK: entry: +; CHECK: tail call i8* @objc_retain(i8* %a) [[NUW]] +; CHECK: loop: +; CHECK: tail call i8* @objc_retain(i8* %a) [[NUW]] +; CHECK: call void @block_callee +; CHECK: call void @objc_release(i8* %reloaded_a) [[NUW]] +; CHECK: exit: +; CHECK: call void @objc_release(i8* %a) [[NUW]] +; CHECK: } +define void @test13(i8* %a) nounwind { +entry: + %block = alloca i8* + %a1 = tail call i8* @objc_retain(i8* %a) nounwind + br label %loop + +loop: + %a2 = tail call i8* @objc_retain(i8* %a) nounwind + store i8* %a, i8** %block, align 8 + %casted_block = bitcast i8** %block to void ()* + call void @block_callee(void ()* %casted_block) + %reloaded_a = load i8** %block, align 8 + call void @objc_release(i8* %reloaded_a) nounwind, !clang.imprecise_release !0 + br i1 undef, label %loop, label %exit + +exit: + call void @objc_release(i8* %a) nounwind, !clang.imprecise_release !0 + ret void +} + ; CHECK: attributes [[NUW]] = { nounwind } !0 = metadata !{} diff --git a/test/Transforms/ObjCARC/contract-marker.ll b/test/Transforms/ObjCARC/contract-marker.ll index 01fd1e71436e..55a1b28e1c46 100644 --- a/test/Transforms/ObjCARC/contract-marker.ll +++ b/test/Transforms/ObjCARC/contract-marker.ll @@ -1,9 +1,11 @@ ; RUN: opt -S -objc-arc-contract < %s | FileCheck %s +; CHECK: define void @foo() { ; CHECK: %call = tail call i32* @qux() ; CHECK-NEXT: %tcall = bitcast i32* %call to i8* ; CHECK-NEXT: call void asm sideeffect "mov\09r7, r7\09\09@ marker for objc_retainAutoreleaseReturnValue", ""() ; CHECK-NEXT: %0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %tcall) [[NUW:#[0-9]+]] +; CHECK: } define void @foo() { entry: diff --git a/test/Transforms/ObjCARC/contract-storestrong.ll b/test/Transforms/ObjCARC/contract-storestrong.ll index 6999237300e7..023604e105b0 100644 --- a/test/Transforms/ObjCARC/contract-storestrong.ll +++ b/test/Transforms/ObjCARC/contract-storestrong.ll @@ -12,6 +12,7 @@ declare void @use_pointer(i8*) ; CHECK: entry: ; CHECK-NEXT: tail call void @objc_storeStrong(i8** @x, i8* %p) [[NUW:#[0-9]+]] ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test0(i8* %p) { entry: %0 = tail call i8* @objc_retain(i8* %p) nounwind @@ -107,6 +108,7 @@ entry: ; CHECK: define i1 @test5(i8* %newValue, i8* %foo) { ; CHECK: %t = icmp eq i8* %x1, %foo ; CHECK: tail call void @objc_storeStrong(i8** @x, i8* %newValue) [[NUW]] +; CHECK: } define i1 @test5(i8* %newValue, i8* %foo) { entry: %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind @@ -122,6 +124,7 @@ entry: ; CHECK: define i1 @test6(i8* %newValue, i8* %foo) { ; CHECK: %t = icmp eq i8* %x1, %foo ; CHECK: tail call void @objc_storeStrong(i8** @x, i8* %newValue) [[NUW]] +; CHECK: } define i1 @test6(i8* %newValue, i8* %foo) { entry: %x0 = tail call i8* @objc_retain(i8* %newValue) nounwind diff --git a/test/Transforms/ObjCARC/contract-testcases.ll b/test/Transforms/ObjCARC/contract-testcases.ll index 85b03be275ec..fc023f898198 100644 --- a/test/Transforms/ObjCARC/contract-testcases.ll +++ b/test/Transforms/ObjCARC/contract-testcases.ll @@ -50,6 +50,7 @@ bb6: ; preds = %bb5, %bb4, %bb4, %b ; CHECK: br i1 undef, label %bb7, label %bb7 ; CHECK: bb7: ; CHECK: %tmp8 = phi %0* [ %0, %bb ], [ %0, %bb ] +; CHECK: } define void @test1() { bb: %tmp = tail call %0* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to %0* ()*)() @@ -70,6 +71,7 @@ bb7: ; preds = %bb6, %bb6, %bb5 ; CHECK: invoke.cont: ; preds = %entry ; CHECK-NEXT: call void asm sideeffect "mov\09r7, r7\09\09@ marker for objc_retainAutoreleaseReturnValue", ""() ; CHECK-NEXT: %tmp = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %call) [[NUW:#[0-9]+]] +; CHECK: } define void @_Z6doTestP8NSString() { entry: %call = invoke i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* ()*)() diff --git a/test/Transforms/ObjCARC/contract.ll b/test/Transforms/ObjCARC/contract.ll index 0b60683d9995..3544f885528b 100644 --- a/test/Transforms/ObjCARC/contract.ll +++ b/test/Transforms/ObjCARC/contract.ll @@ -10,6 +10,7 @@ declare i8* @objc_retainAutoreleasedReturnValue(i8*) declare void @use_pointer(i8*) declare i8* @returner() +declare void @callee() ; CHECK: define void @test0 ; CHECK: call void @use_pointer(i8* %0) @@ -137,6 +138,7 @@ define i8* @test6() { ; CHECK: call void @use_pointer(i8* %1) ; CHECK: tail call i8* @objc_autoreleaseReturnValue(i8* %1) ; CHECK: ret i8* %2 +; CHECK-NEXT: } define i8* @test7(i8* %p) { %1 = tail call i8* @objc_retain(i8* %p) call void @use_pointer(i8* %p) @@ -171,6 +173,60 @@ define void @test9(i8* %a, i8* %b) { ret void } + +; Turn objc_retain into objc_retainAutoreleasedReturnValue if its operand +; is a return value. + +; CHECK: define void @test10() +; CHECK: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %p) +define void @test10() { + %p = call i8* @returner() + tail call i8* @objc_retain(i8* %p) nounwind + ret void +} + +; Convert objc_retain to objc_retainAutoreleasedReturnValue if its +; argument is a return value. + +; CHECK: define void @test11( +; CHECK-NEXT: %y = call i8* @returner() +; CHECK-NEXT: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) [[NUW]] +; CHECK-NEXT: ret void +define void @test11() { + %y = call i8* @returner() + tail call i8* @objc_retain(i8* %y) nounwind + ret void +} + +; Don't convert objc_retain to objc_retainAutoreleasedReturnValue if its +; argument is not a return value. + +; CHECK: define void @test12( +; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]] +; CHECK-NEXT: ret void +; CHECK-NEXT: } +define void @test12(i8* %y) { + tail call i8* @objc_retain(i8* %y) nounwind + ret void +} + +; Don't Convert objc_retain to objc_retainAutoreleasedReturnValue if it +; isn't next to the call providing its return value. + +; CHECK: define void @test13( +; CHECK-NEXT: %y = call i8* @returner() +; CHECK-NEXT: call void @callee() +; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]] +; CHECK-NEXT: ret void +; CHECK-NEXT: } +define void @test13() { + %y = call i8* @returner() + call void @callee() + tail call i8* @objc_retain(i8* %y) nounwind + ret void +} + + declare void @clang.arc.use(...) nounwind ; CHECK: attributes [[NUW]] = { nounwind } diff --git a/test/Transforms/ObjCARC/expand.ll b/test/Transforms/ObjCARC/expand.ll index 5388673f2b9d..fe47ee52e907 100644 --- a/test/Transforms/ObjCARC/expand.ll +++ b/test/Transforms/ObjCARC/expand.ll @@ -4,25 +4,91 @@ target datalayout = "e-p:64:64:64" declare i8* @objc_retain(i8*) declare i8* @objc_autorelease(i8*) +declare i8* @objc_retainAutoreleasedReturnValue(i8*) +declare i8* @objc_autoreleaseReturnValue(i8*) +declare i8* @objc_retainAutorelease(i8*) +declare i8* @objc_retainAutoreleaseReturnValue(i8*) +declare i8* @objc_retainBlock(i8*) declare void @use_pointer(i8*) -; CHECK: define void @test0 +; CHECK: define void @test_retain(i8* %x) [[NUW:#[0-9]+]] { +; CHECK: call i8* @objc_retain(i8* %x) ; CHECK: call void @use_pointer(i8* %x) ; CHECK: } -define void @test0(i8* %x) nounwind { +define void @test_retain(i8* %x) nounwind { entry: %0 = call i8* @objc_retain(i8* %x) nounwind call void @use_pointer(i8* %0) ret void } -; CHECK: define void @test1 +; CHECK: define void @test_retainAutoreleasedReturnValue(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_retainAutoreleasedReturnValue(i8* %x) ; CHECK: call void @use_pointer(i8* %x) ; CHECK: } -define void @test1(i8* %x) nounwind { +define void @test_retainAutoreleasedReturnValue(i8* %x) nounwind { +entry: + %0 = call i8* @objc_retainAutoreleasedReturnValue(i8* %x) nounwind + call void @use_pointer(i8* %0) + ret void +} + +; CHECK: define void @test_retainAutorelease(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_retainAutorelease(i8* %x) +; CHECK: call void @use_pointer(i8* %x) +; CHECK: } +define void @test_retainAutorelease(i8* %x) nounwind { +entry: + %0 = call i8* @objc_retainAutorelease(i8* %x) nounwind + call void @use_pointer(i8* %0) + ret void +} + +; CHECK: define void @test_retainAutoreleaseReturnValue(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_retainAutoreleaseReturnValue(i8* %x) +; CHECK: call void @use_pointer(i8* %x) +; CHECK: } +define void @test_retainAutoreleaseReturnValue(i8* %x) nounwind { +entry: + %0 = call i8* @objc_retainAutoreleaseReturnValue(i8* %x) nounwind + call void @use_pointer(i8* %0) + ret void +} + +; CHECK: define void @test_autorelease(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_autorelease(i8* %x) +; CHECK: call void @use_pointer(i8* %x) +; CHECK: } +define void @test_autorelease(i8* %x) nounwind { entry: %0 = call i8* @objc_autorelease(i8* %x) nounwind - call void @use_pointer(i8* %x) + call void @use_pointer(i8* %0) + ret void +} + +; CHECK: define void @test_autoreleaseReturnValue(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_autoreleaseReturnValue(i8* %x) +; CHECK: call void @use_pointer(i8* %x) +; CHECK: } +define void @test_autoreleaseReturnValue(i8* %x) nounwind { +entry: + %0 = call i8* @objc_autoreleaseReturnValue(i8* %x) nounwind + call void @use_pointer(i8* %0) + ret void +} + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; RetainBlock is not strictly forwarding. Do not touch it. ; +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; CHECK: define void @test_retainBlock(i8* %x) [[NUW]] { +; CHECK: call i8* @objc_retainBlock(i8* %x) +; CHECK: call void @use_pointer(i8* %0) +; CHECK: } +define void @test_retainBlock(i8* %x) nounwind { +entry: + %0 = call i8* @objc_retainBlock(i8* %x) nounwind + call void @use_pointer(i8* %0) ret void } diff --git a/test/Transforms/ObjCARC/gvn.ll b/test/Transforms/ObjCARC/gvn.ll index 3648866de01a..a828b5485f4c 100644 --- a/test/Transforms/ObjCARC/gvn.ll +++ b/test/Transforms/ObjCARC/gvn.ll @@ -7,11 +7,12 @@ declare i8* @objc_retain(i8*) ; GVN should be able to eliminate this redundant load, with ARC-specific ; alias analysis. -; CHECK: @foo +; CHECK: define i8* @foo(i32 %n) ; CHECK-NEXT: entry: ; CHECK-NEXT: %s = load i8** @x ; CHECK-NOT: load ; CHECK: ret i8* %s +; CHECK-NEXT: } define i8* @foo(i32 %n) nounwind { entry: %s = load i8** @x diff --git a/test/Transforms/ObjCARC/clang-arc-used-intrinsic-removed-if-isolated.ll b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll index 4215b5c36465..4215b5c36465 100644 --- a/test/Transforms/ObjCARC/clang-arc-used-intrinsic-removed-if-isolated.ll +++ b/test/Transforms/ObjCARC/intrinsic-use-isolated.ll diff --git a/test/Transforms/ObjCARC/intrinsic-use.ll b/test/Transforms/ObjCARC/intrinsic-use.ll index 9c7b81a95d23..60370c1f4405 100644 --- a/test/Transforms/ObjCARC/intrinsic-use.ll +++ b/test/Transforms/ObjCARC/intrinsic-use.ll @@ -34,8 +34,11 @@ declare void @test0_helper(i8*, i8**) ; CHECK-NEXT: @objc_release(i8* [[VAL1]]) ; CHECK-NEXT: @objc_autorelease(i8* %x) ; CHECK-NEXT: store i8* %x, i8** %out +; CHECK-NEXT: @objc_retain(i8* %x) ; CHECK-NEXT: @objc_release(i8* [[VAL2]]) +; CHECK-NEXT: @objc_release(i8* %x) ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test0(i8** %out, i8* %x, i8* %y) { entry: %temp0 = alloca i8*, align 8 @@ -61,3 +64,53 @@ entry: call void @objc_release(i8* %x) nounwind ret void } + +; CHECK: define void @test0a( +; CHECK: @objc_retain(i8* %x) +; CHECK-NEXT: store i8* %y, i8** %temp0 +; CHECK-NEXT: @objc_retain(i8* %y) +; CHECK-NEXT: call void @test0_helper +; CHECK-NEXT: [[VAL1:%.*]] = load i8** %temp0 +; CHECK-NEXT: call void (...)* @clang.arc.use(i8* %y) +; CHECK-NEXT: @objc_retain(i8* [[VAL1]]) +; CHECK-NEXT: @objc_release(i8* %y) +; CHECK-NEXT: store i8* [[VAL1]], i8** %temp1 +; CHECK-NEXT: call void @test0_helper +; CHECK-NEXT: [[VAL2:%.*]] = load i8** %temp1 +; CHECK-NEXT: call void (...)* @clang.arc.use(i8* [[VAL1]]) +; CHECK-NEXT: @objc_retain(i8* [[VAL2]]) +; CHECK-NEXT: @objc_release(i8* [[VAL1]]) +; CHECK-NEXT: @objc_autorelease(i8* %x) +; CHECK-NEXT: @objc_release(i8* [[VAL2]]) +; CHECK-NEXT: store i8* %x, i8** %out +; CHECK-NEXT: ret void +; CHECK-NEXT: } +define void @test0a(i8** %out, i8* %x, i8* %y) { +entry: + %temp0 = alloca i8*, align 8 + %temp1 = alloca i8*, align 8 + %0 = call i8* @objc_retain(i8* %x) nounwind + %1 = call i8* @objc_retain(i8* %y) nounwind + store i8* %y, i8** %temp0 + call void @test0_helper(i8* %x, i8** %temp0) + %val1 = load i8** %temp0 + %2 = call i8* @objc_retain(i8* %val1) nounwind + call void (...)* @clang.arc.use(i8* %y) nounwind + call void @objc_release(i8* %y) nounwind, !clang.imprecise_release !0 + store i8* %val1, i8** %temp1 + call void @test0_helper(i8* %x, i8** %temp1) + %val2 = load i8** %temp1 + %3 = call i8* @objc_retain(i8* %val2) nounwind + call void (...)* @clang.arc.use(i8* %val1) nounwind + call void @objc_release(i8* %val1) nounwind, !clang.imprecise_release !0 + %4 = call i8* @objc_retain(i8* %x) nounwind + %5 = call i8* @objc_autorelease(i8* %x) nounwind + store i8* %x, i8** %out + call void @objc_release(i8* %val2) nounwind, !clang.imprecise_release !0 + call void @objc_release(i8* %x) nounwind, !clang.imprecise_release !0 + ret void +} + + +!0 = metadata !{} + diff --git a/test/Transforms/ObjCARC/invoke.ll b/test/Transforms/ObjCARC/invoke.ll index f528b4ac35bc..9510f2e7ddec 100644 --- a/test/Transforms/ObjCARC/invoke.ll +++ b/test/Transforms/ObjCARC/invoke.ll @@ -17,6 +17,7 @@ declare i8* @returner() ; CHECK: lpad: ; CHECK: call void @objc_release(i8* %zipFile) [[NUW]], !clang.imprecise_release !0 ; CHECK: ret void +; CHECK-NEXT: } define void @test0(i8* %zipFile) { entry: call i8* @objc_retain(i8* %zipFile) nounwind @@ -48,6 +49,7 @@ lpad: ; preds = %entry ; CHECK: br label %done ; CHECK: done: ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test1(i8* %zipFile) { entry: call i8* @objc_retain(i8* %zipFile) nounwind @@ -110,6 +112,7 @@ finally.rethrow: ; preds = %invoke.cont, %entry ; CHECK: if.end: ; CHECK-NEXT: call void @objc_release(i8* %p) [[NUW]] ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test3(i8* %p, i1 %b) { entry: %0 = call i8* @objc_retain(i8* %p) @@ -145,6 +148,7 @@ if.end: ; CHECK: if.end: ; CHECK-NEXT: call void @objc_release(i8* %p) [[NUW]] ; CHECK-NEXT: ret void +; CHECK-NEXT: } define void @test4(i8* %p, i1 %b) { entry: %0 = call i8* @objc_retain(i8* %p) diff --git a/test/Transforms/ObjCARC/move-and-merge-autorelease.ll b/test/Transforms/ObjCARC/move-and-merge-autorelease.ll index 8462c70a48e7..e5d2f07e45a2 100644 --- a/test/Transforms/ObjCARC/move-and-merge-autorelease.ll +++ b/test/Transforms/ObjCARC/move-and-merge-autorelease.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -objc-arc < %s | FileCheck %s +; RUN: opt -S -objc-arc -objc-arc-contract < %s | FileCheck %s ; The optimizer should be able to move the autorelease past two phi nodes ; and fold it with the release in bb65. diff --git a/test/Transforms/ObjCARC/retain-block-escape-analysis.ll b/test/Transforms/ObjCARC/retain-block-escape-analysis.ll index 2c1ddce32836..8df05ad22666 100644 --- a/test/Transforms/ObjCARC/retain-block-escape-analysis.ll +++ b/test/Transforms/ObjCARC/retain-block-escape-analysis.ll @@ -23,6 +23,23 @@ define void @bitcasttest(i8* %storage, void (...)* %block) { ; CHECK: define void @bitcasttest entry: %t1 = bitcast void (...)* %block to i8* +; CHECK: tail call i8* @objc_retain + %t2 = tail call i8* @objc_retain(i8* %t1) +; CHECK: tail call i8* @objc_retainBlock + %t3 = tail call i8* @objc_retainBlock(i8* %t1), !clang.arc.copy_on_escape !0 + %t4 = bitcast i8* %storage to void (...)** + %t5 = bitcast i8* %t3 to void (...)* + store void (...)* %t5, void (...)** %t4, align 8 +; CHECK: call void @objc_release + call void @objc_release(i8* %t1) + ret void +; CHECK: } +} + +define void @bitcasttest_a(i8* %storage, void (...)* %block) { +; CHECK: define void @bitcasttest_a +entry: + %t1 = bitcast void (...)* %block to i8* ; CHECK-NOT: tail call i8* @objc_retain %t2 = tail call i8* @objc_retain(i8* %t1) ; CHECK: tail call i8* @objc_retainBlock @@ -31,14 +48,34 @@ entry: %t5 = bitcast i8* %t3 to void (...)* store void (...)* %t5, void (...)** %t4, align 8 ; CHECK-NOT: call void @objc_release - call void @objc_release(i8* %t1) + call void @objc_release(i8* %t1), !clang.imprecise_release !0 ret void +; CHECK: } } define void @geptest(void (...)** %storage_array, void (...)* %block) { ; CHECK: define void @geptest entry: %t1 = bitcast void (...)* %block to i8* +; CHECK: tail call i8* @objc_retain + %t2 = tail call i8* @objc_retain(i8* %t1) +; CHECK: tail call i8* @objc_retainBlock + %t3 = tail call i8* @objc_retainBlock(i8* %t1), !clang.arc.copy_on_escape !0 + %t4 = bitcast i8* %t3 to void (...)* + + %storage = getelementptr inbounds void (...)** %storage_array, i64 0 + + store void (...)* %t4, void (...)** %storage, align 8 +; CHECK: call void @objc_release + call void @objc_release(i8* %t1) + ret void +; CHECK: } +} + +define void @geptest_a(void (...)** %storage_array, void (...)* %block) { +; CHECK: define void @geptest_a +entry: + %t1 = bitcast void (...)* %block to i8* ; CHECK-NOT: tail call i8* @objc_retain %t2 = tail call i8* @objc_retain(i8* %t1) ; CHECK: tail call i8* @objc_retainBlock @@ -49,8 +86,9 @@ entry: store void (...)* %t4, void (...)** %storage, align 8 ; CHECK-NOT: call void @objc_release - call void @objc_release(i8* %t1) + call void @objc_release(i8* %t1), !clang.imprecise_release !0 ret void +; CHECK: } } define void @selecttest(void (...)** %store1, void (...)** %store2, @@ -58,6 +96,24 @@ define void @selecttest(void (...)** %store1, void (...)** %store2, ; CHECK: define void @selecttest entry: %t1 = bitcast void (...)* %block to i8* +; CHECK: tail call i8* @objc_retain + %t2 = tail call i8* @objc_retain(i8* %t1) +; CHECK: tail call i8* @objc_retainBlock + %t3 = tail call i8* @objc_retainBlock(i8* %t1), !clang.arc.copy_on_escape !0 + %t4 = bitcast i8* %t3 to void (...)* + %store = select i1 undef, void (...)** %store1, void (...)** %store2 + store void (...)* %t4, void (...)** %store, align 8 +; CHECK: call void @objc_release + call void @objc_release(i8* %t1) + ret void +; CHECK: } +} + +define void @selecttest_a(void (...)** %store1, void (...)** %store2, + void (...)* %block) { +; CHECK: define void @selecttest_a +entry: + %t1 = bitcast void (...)* %block to i8* ; CHECK-NOT: tail call i8* @objc_retain %t2 = tail call i8* @objc_retain(i8* %t1) ; CHECK: tail call i8* @objc_retainBlock @@ -66,8 +122,9 @@ entry: %store = select i1 undef, void (...)** %store1, void (...)** %store2 store void (...)* %t4, void (...)** %store, align 8 ; CHECK-NOT: call void @objc_release - call void @objc_release(i8* %t1) + call void @objc_release(i8* %t1), !clang.imprecise_release !0 ret void +; CHECK: } } define void @phinodetest(void (...)** %storage1, @@ -76,6 +133,36 @@ define void @phinodetest(void (...)** %storage1, ; CHECK: define void @phinodetest entry: %t1 = bitcast void (...)* %block to i8* +; CHECK: tail call i8* @objc_retain + %t2 = tail call i8* @objc_retain(i8* %t1) +; CHECK: tail call i8* @objc_retainBlock + %t3 = tail call i8* @objc_retainBlock(i8* %t1), !clang.arc.copy_on_escape !0 + %t4 = bitcast i8* %t3 to void (...)* + br i1 undef, label %store1_set, label %store2_set +; CHECK: store1_set: + +store1_set: + br label %end + +store2_set: + br label %end + +end: +; CHECK: end: + %storage = phi void (...)** [ %storage1, %store1_set ], [ %storage2, %store2_set] + store void (...)* %t4, void (...)** %storage, align 8 +; CHECK: call void @objc_release + call void @objc_release(i8* %t1) + ret void +; CHECK: } +} + +define void @phinodetest_a(void (...)** %storage1, + void (...)** %storage2, + void (...)* %block) { +; CHECK: define void @phinodetest_a +entry: + %t1 = bitcast void (...)* %block to i8* ; CHECK-NOT: tail call i8* @objc_retain %t2 = tail call i8* @objc_retain(i8* %t1) ; CHECK: tail call i8* @objc_retainBlock @@ -93,10 +180,11 @@ end: %storage = phi void (...)** [ %storage1, %store1_set ], [ %storage2, %store2_set] store void (...)* %t4, void (...)** %storage, align 8 ; CHECK-NOT: call void @objc_release - call void @objc_release(i8* %t1) + call void @objc_release(i8* %t1), !clang.imprecise_release !0 ret void } + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; This test makes sure that we do not hang clang when visiting a use ; ; cycle caused by phi nodes during objc-arc analysis. *NOTE* This ; diff --git a/test/Transforms/ObjCARC/rv.ll b/test/Transforms/ObjCARC/rv.ll index 589c60f9f3aa..e857c9f41bb4 100644 --- a/test/Transforms/ObjCARC/rv.ll +++ b/test/Transforms/ObjCARC/rv.ll @@ -136,17 +136,6 @@ define i8* @test7b() { ret i8* %p } -; Turn objc_retain into objc_retainAutoreleasedReturnValue if its operand -; is a return value. - -; CHECK: define void @test8() -; CHECK: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %p) -define void @test8() { - %p = call i8* @returner() - call i8* @objc_retain(i8* %p) - ret void -} - ; Don't apply the RV optimization to autorelease if there's no retain. ; CHECK: define i8* @test9(i8* %p) @@ -235,45 +224,6 @@ define void @test15() { ret void } -; Convert objc_retain to objc_retainAutoreleasedReturnValue if its -; argument is a return value. - -; CHECK: define void @test16( -; CHECK-NEXT: %y = call i8* @returner() -; CHECK-NEXT: tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) [[NUW]] -; CHECK-NEXT: ret void -define void @test16() { - %y = call i8* @returner() - call i8* @objc_retain(i8* %y) - ret void -} - -; Don't convert objc_retain to objc_retainAutoreleasedReturnValue if its -; argument is not a return value. - -; CHECK: define void @test17( -; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]] -; CHECK-NEXT: ret void -define void @test17(i8* %y) { - call i8* @objc_retain(i8* %y) - ret void -} - -; Don't Convert objc_retain to objc_retainAutoreleasedReturnValue if it -; isn't next to the call providing its return value. - -; CHECK: define void @test18( -; CHECK-NEXT: %y = call i8* @returner() -; CHECK-NEXT: call void @callee() -; CHECK-NEXT: tail call i8* @objc_retain(i8* %y) [[NUW]] -; CHECK-NEXT: ret void -define void @test18() { - %y = call i8* @returner() - call void @callee() - call i8* @objc_retain(i8* %y) - ret void -} - ; Delete autoreleaseRV+retainRV pairs. ; CHECK: define i8* @test19(i8* %p) { diff --git a/test/Transforms/ObjCARC/tail-call-invariant-enforcement.ll b/test/Transforms/ObjCARC/tail-call-invariant-enforcement.ll index 26cd67727e6a..1ec61c848101 100644 --- a/test/Transforms/ObjCARC/tail-call-invariant-enforcement.ll +++ b/test/Transforms/ObjCARC/tail-call-invariant-enforcement.ll @@ -1,74 +1,89 @@ ; RUN: opt -objc-arc -S < %s | FileCheck %s -declare i8* @objc_release(i8* %x) +declare void @objc_release(i8* %x) declare i8* @objc_retain(i8* %x) declare i8* @objc_autorelease(i8* %x) declare i8* @objc_autoreleaseReturnValue(i8* %x) declare i8* @objc_retainAutoreleasedReturnValue(i8* %x) +declare i8* @tmp(i8*) ; Never tail call objc_autorelease. -define i8* @test0(i8* %x) { + +; CHECK: define i8* @test0(i8* %x) [[NUW:#[0-9]+]] { +; CHECK: %tmp0 = call i8* @objc_autorelease(i8* %x) [[NUW]] +; CHECK: %tmp1 = call i8* @objc_autorelease(i8* %x) [[NUW]] +; CHECK: } +define i8* @test0(i8* %x) nounwind { entry: - ; CHECK: %tmp0 = call i8* @objc_autorelease(i8* %x) %tmp0 = call i8* @objc_autorelease(i8* %x) - ; CHECK: %tmp1 = call i8* @objc_autorelease(i8* %x) %tmp1 = tail call i8* @objc_autorelease(i8* %x) ret i8* %x } ; Always tail call autoreleaseReturnValue. -define i8* @test1(i8* %x) { + +; CHECK: define i8* @test1(i8* %x) [[NUW]] { +; CHECK: %tmp0 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) [[NUW]] +; CHECK: %tmp1 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) [[NUW]] +; CHECK: } +define i8* @test1(i8* %x) nounwind { entry: - ; CHECK: %tmp0 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) %tmp0 = call i8* @objc_autoreleaseReturnValue(i8* %x) - ; CHECK: %tmp1 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) %tmp1 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) ret i8* %x } ; Always tail call objc_retain. -define i8* @test2(i8* %x) { + +; CHECK: define i8* @test2(i8* %x) [[NUW]] { +; CHECK: %tmp0 = tail call i8* @objc_retain(i8* %x) [[NUW]] +; CHECK: %tmp1 = tail call i8* @objc_retain(i8* %x) [[NUW]] +; CHECK: } +define i8* @test2(i8* %x) nounwind { entry: - ; CHECK: %tmp0 = tail call i8* @objc_retain(i8* %x) %tmp0 = call i8* @objc_retain(i8* %x) - ; CHECK: %tmp1 = tail call i8* @objc_retain(i8* %x) %tmp1 = tail call i8* @objc_retain(i8* %x) ret i8* %x } -define i8* @tmp(i8* %x) { - ret i8* %x -} - ; Always tail call objc_retainAutoreleasedReturnValue. -define i8* @test3(i8* %x) { +; CHECK: define i8* @test3(i8* %x) [[NUW]] { +; CHECK: %tmp0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) [[NUW]] +; CHECK: %tmp1 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %z) [[NUW]] +; CHECK: } +define i8* @test3(i8* %x) nounwind { entry: %y = call i8* @tmp(i8* %x) - ; CHECK: %tmp0 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %y) %tmp0 = call i8* @objc_retainAutoreleasedReturnValue(i8* %y) %z = call i8* @tmp(i8* %x) - ; CHECK: %tmp1 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %z) %tmp1 = tail call i8* @objc_retainAutoreleasedReturnValue(i8* %z) ret i8* %x } ; By itself, we should never change whether or not objc_release is tail called. -define i8* @test4(i8* %x) { + +; CHECK: define void @test4(i8* %x) [[NUW]] { +; CHECK: call void @objc_release(i8* %x) [[NUW]] +; CHECK: tail call void @objc_release(i8* %x) [[NUW]] +; CHECK: } +define void @test4(i8* %x) nounwind { entry: - ; CHECK: %tmp0 = call i8* @objc_release(i8* %x) - %tmp0 = call i8* @objc_release(i8* %x) - ; CHECK: %tmp1 = tail call i8* @objc_release(i8* %x) - %tmp1 = tail call i8* @objc_release(i8* %x) - ret i8* %x + call void @objc_release(i8* %x) + tail call void @objc_release(i8* %x) + ret void } ; If we convert a tail called @objc_autoreleaseReturnValue to an ; @objc_autorelease, ensure that the tail call is removed. -define i8* @test5(i8* %x) { +; CHECK: define i8* @test5(i8* %x) [[NUW]] { +; CHECK: %tmp0 = call i8* @objc_autorelease(i8* %x) [[NUW]] +; CHECK: } +define i8* @test5(i8* %x) nounwind { entry: - ; CHECK: %tmp0 = call i8* @objc_autorelease(i8* %x) %tmp0 = tail call i8* @objc_autoreleaseReturnValue(i8* %x) ret i8* %tmp0 } +; CHECK: attributes [[NUW]] = { nounwind } + diff --git a/test/Transforms/Reassociate/pr12245.ll b/test/Transforms/Reassociate/pr12245.ll index 84098bdb006b..e9b5355cceb1 100644 --- a/test/Transforms/Reassociate/pr12245.ll +++ b/test/Transforms/Reassociate/pr12245.ll @@ -6,36 +6,36 @@ define i32 @fn2() nounwind uwtable ssp { entry: - %0 = load i32* @a, align 4, !tbaa !0 + %0 = load i32* @a, align 4 %dec = add nsw i32 %0, -1 - store i32 %dec, i32* @a, align 4, !tbaa !0 - %1 = load i32* @d, align 4, !tbaa !0 + store i32 %dec, i32* @a, align 4 + %1 = load i32* @d, align 4 %sub = sub nsw i32 %dec, %1 - store i32 %sub, i32* @d, align 4, !tbaa !0 - %2 = load i32* @a, align 4, !tbaa !0 + store i32 %sub, i32* @d, align 4 + %2 = load i32* @a, align 4 %dec1 = add nsw i32 %2, -1 - store i32 %dec1, i32* @a, align 4, !tbaa !0 - %3 = load i32* @d, align 4, !tbaa !0 + store i32 %dec1, i32* @a, align 4 + %3 = load i32* @d, align 4 %sub2 = sub nsw i32 %dec1, %3 - store i32 %sub2, i32* @d, align 4, !tbaa !0 - %4 = load i32* @a, align 4, !tbaa !0 + store i32 %sub2, i32* @d, align 4 + %4 = load i32* @a, align 4 %dec3 = add nsw i32 %4, -1 - store i32 %dec3, i32* @a, align 4, !tbaa !0 - %5 = load i32* @d, align 4, !tbaa !0 + store i32 %dec3, i32* @a, align 4 + %5 = load i32* @d, align 4 %sub4 = sub nsw i32 %dec3, %5 - store i32 %sub4, i32* @d, align 4, !tbaa !0 - %6 = load i32* @a, align 4, !tbaa !0 + store i32 %sub4, i32* @d, align 4 + %6 = load i32* @a, align 4 %dec5 = add nsw i32 %6, -1 - store i32 %dec5, i32* @a, align 4, !tbaa !0 - %7 = load i32* @d, align 4, !tbaa !0 + store i32 %dec5, i32* @a, align 4 + %7 = load i32* @d, align 4 %sub6 = sub nsw i32 %dec5, %7 - store i32 %sub6, i32* @d, align 4, !tbaa !0 - %8 = load i32* @a, align 4, !tbaa !0 + store i32 %sub6, i32* @d, align 4 + %8 = load i32* @a, align 4 %dec7 = add nsw i32 %8, -1 - store i32 %dec7, i32* @a, align 4, !tbaa !0 - %9 = load i32* @d, align 4, !tbaa !0 + store i32 %dec7, i32* @a, align 4 + %9 = load i32* @d, align 4 %sub8 = sub nsw i32 %dec7, %9 - store i32 %sub8, i32* @d, align 4, !tbaa !0 + store i32 %sub8, i32* @d, align 4 ret i32 0 } @@ -44,7 +44,3 @@ entry: %call = call i32 @fn2() ret i32 %call } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/Reassociate/xor_reassoc.ll b/test/Transforms/Reassociate/xor_reassoc.ll index d371a9b5b68f..b9353c7f81fe 100644 --- a/test/Transforms/Reassociate/xor_reassoc.ll +++ b/test/Transforms/Reassociate/xor_reassoc.ll @@ -164,3 +164,30 @@ define void @xor_bug1() { %3 = and i64 undef, %2 ret void } + +; The bug was that when the compiler optimize "(x | c1)" ^ "(x & c2)", it may +; swap the two xor-subexpressions if they are not in canoninical order; however, +; when optimizer swaps two sub-expressions, if forgot to swap the cached value +; of c1 and c2 accordingly, hence cause the problem. +; +define i32 @xor_bug2(i32, i32, i32, i32) { + %5 = mul i32 %0, 123 + %6 = add i32 %2, 24 + %7 = add i32 %1, 8 + %8 = and i32 %1, 3456789 + %9 = or i32 %8, 4567890 + %10 = and i32 %1, 543210987 + %11 = or i32 %1, 891034567 + %12 = and i32 %2, 255 + %13 = xor i32 %9, %10 + %14 = xor i32 %11, %13 + %15 = xor i32 %5, %14 + %16 = and i32 %3, 255 + %17 = xor i32 %16, 42 + %18 = add i32 %6, %7 + %19 = add i32 %18, %12 + %20 = add i32 %19, %15 + ret i32 %20 +;CHECK: @xor_bug2 +;CHECK: xor i32 %5, 891034567 +} diff --git a/test/Transforms/SLPVectorizer/X86/barriercall.ll b/test/Transforms/SLPVectorizer/X86/barriercall.ll new file mode 100644 index 000000000000..04eb8f919bc7 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/barriercall.ll @@ -0,0 +1,32 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK: @foo +;CHECK: store <4 x i32> +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32 %n) { +entry: + %call = tail call i32 (...)* @bar() #2 + %mul = mul nsw i32 %n, 5 + %add = add nsw i32 %mul, 9 + store i32 %add, i32* %A, align 4 + %mul1 = mul nsw i32 %n, 9 + %add2 = add nsw i32 %mul1, 9 + %arrayidx3 = getelementptr inbounds i32* %A, i64 1 + store i32 %add2, i32* %arrayidx3, align 4 + %mul4 = shl i32 %n, 3 + %add5 = add nsw i32 %mul4, 9 + %arrayidx6 = getelementptr inbounds i32* %A, i64 2 + store i32 %add5, i32* %arrayidx6, align 4 + %mul7 = mul nsw i32 %n, 10 + %add8 = add nsw i32 %mul7, 9 + %arrayidx9 = getelementptr inbounds i32* %A, i64 3 + store i32 %add8, i32* %arrayidx9, align 4 + ret i32 undef +} + + ; We can still vectorize the stores below. + +declare i32 @bar(...) diff --git a/test/Transforms/SLPVectorizer/X86/cast.ll b/test/Transforms/SLPVectorizer/X86/cast.ll new file mode 100644 index 000000000000..344dbbca2c57 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/cast.ll @@ -0,0 +1,38 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.9.0" + +; int foo(int * restrict A, char * restrict B) { +; A[0] = B[0]; +; A[1] = B[1]; +; A[2] = B[2]; +; A[3] = B[3]; +; } +;CHECK: @foo +;CHECK: load <4 x i8> +;CHECK: sext +;CHECK: store <4 x i32> +define i32 @foo(i32* noalias nocapture %A, i8* noalias nocapture %B) { +entry: + %0 = load i8* %B, align 1 + %conv = sext i8 %0 to i32 + store i32 %conv, i32* %A, align 4 + %arrayidx2 = getelementptr inbounds i8* %B, i64 1 + %1 = load i8* %arrayidx2, align 1 + %conv3 = sext i8 %1 to i32 + %arrayidx4 = getelementptr inbounds i32* %A, i64 1 + store i32 %conv3, i32* %arrayidx4, align 4 + %arrayidx5 = getelementptr inbounds i8* %B, i64 2 + %2 = load i8* %arrayidx5, align 1 + %conv6 = sext i8 %2 to i32 + %arrayidx7 = getelementptr inbounds i32* %A, i64 2 + store i32 %conv6, i32* %arrayidx7, align 4 + %arrayidx8 = getelementptr inbounds i8* %B, i64 3 + %3 = load i8* %arrayidx8, align 1 + %conv9 = sext i8 %3 to i32 + %arrayidx10 = getelementptr inbounds i32* %A, i64 3 + store i32 %conv9, i32* %arrayidx10, align 4 + ret i32 undef +} + diff --git a/test/Transforms/SLPVectorizer/X86/compare-reduce.ll b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll new file mode 100644 index 000000000000..05f8e616bb8e --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/compare-reduce.ll @@ -0,0 +1,53 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.0" + +@.str = private unnamed_addr constant [6 x i8] c"bingo\00", align 1 + +;CHECK: @reduce_compare +;CHECK: load <2 x double> +;CHECK: fmul <2 x double> +;CHECK: fmul <2 x double> +;CHECK: fadd <2 x double> +;CHECK: extractelement +;CHECK: extractelement +;CHECK: ret +define void @reduce_compare(double* nocapture %A, i32 %n) { +entry: + %conv = sitofp i32 %n to double + br label %for.body + +for.body: ; preds = %for.inc, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.inc ] + %0 = shl nsw i64 %indvars.iv, 1 + %arrayidx = getelementptr inbounds double* %A, i64 %0 + %1 = load double* %arrayidx, align 8 + %mul1 = fmul double %conv, %1 + %mul2 = fmul double %mul1, 7.000000e+00 + %add = fadd double %mul2, 5.000000e+00 + %2 = or i64 %0, 1 + %arrayidx6 = getelementptr inbounds double* %A, i64 %2 + %3 = load double* %arrayidx6, align 8 + %mul8 = fmul double %conv, %3 + %mul9 = fmul double %mul8, 4.000000e+00 + %add10 = fadd double %mul9, 9.000000e+00 + %cmp11 = fcmp ogt double %add, %add10 + br i1 %cmp11, label %if.then, label %for.inc + +if.then: ; preds = %for.body + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([6 x i8]* @.str, i64 0, i64 0)) + br label %for.inc + +for.inc: ; preds = %for.body, %if.then + %indvars.iv.next = add i64 %indvars.iv, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, 100 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.inc + ret void +} + +declare i32 @printf(i8* nocapture, ...) + diff --git a/test/Transforms/SLPVectorizer/X86/diamond.ll b/test/Transforms/SLPVectorizer/X86/diamond.ll new file mode 100644 index 000000000000..8e85cb6c9b8f --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/diamond.ll @@ -0,0 +1,78 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; int foo(int * restrict B, int * restrict A, int n, int m) { +; B[0] = n * A[0] + m * A[0]; +; B[1] = n * A[1] + m * A[1]; +; B[2] = n * A[2] + m * A[2]; +; B[3] = n * A[3] + m * A[3]; +; return 0; +; } + +; CHECK: @foo +; CHECK: load <4 x i32> +; CHECK: mul <4 x i32> +; CHECK: store <4 x i32> +; CHECK: ret +define i32 @foo(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) #0 { +entry: + %0 = load i32* %A, align 4 + %mul238 = add i32 %m, %n + %add = mul i32 %0, %mul238 + store i32 %add, i32* %B, align 4 + %arrayidx4 = getelementptr inbounds i32* %A, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add8 = mul i32 %1, %mul238 + %arrayidx9 = getelementptr inbounds i32* %B, i64 1 + store i32 %add8, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %A, i64 2 + %2 = load i32* %arrayidx10, align 4 + %add14 = mul i32 %2, %mul238 + %arrayidx15 = getelementptr inbounds i32* %B, i64 2 + store i32 %add14, i32* %arrayidx15, align 4 + %arrayidx16 = getelementptr inbounds i32* %A, i64 3 + %3 = load i32* %arrayidx16, align 4 + %add20 = mul i32 %3, %mul238 + %arrayidx21 = getelementptr inbounds i32* %B, i64 3 + store i32 %add20, i32* %arrayidx21, align 4 + ret i32 0 +} + + +; int foo_fail(int * restrict B, int * restrict A, int n, int m) { +; B[0] = n * A[0] + m * A[0]; +; B[1] = n * A[1] + m * A[1]; +; B[2] = n * A[2] + m * A[2]; +; B[3] = n * A[3] + m * A[3]; +; return A[0]; +; } + +; CHECK: @foo_fail +; CHECK-NOT: load <4 x i32> +; CHECK: ret +define i32 @foo_fail(i32* noalias nocapture %B, i32* noalias nocapture %A, i32 %n, i32 %m) { +entry: + %0 = load i32* %A, align 4 + %mul238 = add i32 %m, %n + %add = mul i32 %0, %mul238 + store i32 %add, i32* %B, align 4 + %arrayidx4 = getelementptr inbounds i32* %A, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add8 = mul i32 %1, %mul238 + %arrayidx9 = getelementptr inbounds i32* %B, i64 1 + store i32 %add8, i32* %arrayidx9, align 4 + %arrayidx10 = getelementptr inbounds i32* %A, i64 2 + %2 = load i32* %arrayidx10, align 4 + %add14 = mul i32 %2, %mul238 + %arrayidx15 = getelementptr inbounds i32* %B, i64 2 + store i32 %add14, i32* %arrayidx15, align 4 + %arrayidx16 = getelementptr inbounds i32* %A, i64 3 + %3 = load i32* %arrayidx16, align 4 + %add20 = mul i32 %3, %mul238 + %arrayidx21 = getelementptr inbounds i32* %B, i64 3 + store i32 %add20, i32* %arrayidx21, align 4 + ret i32 %0 ;<--------- This value has multiple users and can't be vectorized. +} + diff --git a/test/Transforms/SLPVectorizer/X86/flag.ll b/test/Transforms/SLPVectorizer/X86/flag.ll new file mode 100644 index 000000000000..3ca540706744 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/flag.ll @@ -0,0 +1,51 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -slp-threshold=1000 -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Check that the command line flag works. +;CHECK:rollable +;CHECK-NOT:load <4 x i32> +;CHECK: ret + +define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i64 %n) { + %1 = icmp eq i64 %n, 0 + br i1 %1, label %._crit_edge, label %.lr.ph + +.lr.ph: ; preds = %0, %.lr.ph + %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ] + %2 = shl i64 %i.019, 2 + %3 = getelementptr inbounds i32* %in, i64 %2 + %4 = load i32* %3, align 4 + %5 = or i64 %2, 1 + %6 = getelementptr inbounds i32* %in, i64 %5 + %7 = load i32* %6, align 4 + %8 = or i64 %2, 2 + %9 = getelementptr inbounds i32* %in, i64 %8 + %10 = load i32* %9, align 4 + %11 = or i64 %2, 3 + %12 = getelementptr inbounds i32* %in, i64 %11 + %13 = load i32* %12, align 4 + %14 = mul i32 %4, 7 + %15 = add i32 %14, 7 + %16 = mul i32 %7, 7 + %17 = add i32 %16, 14 + %18 = mul i32 %10, 7 + %19 = add i32 %18, 21 + %20 = mul i32 %13, 7 + %21 = add i32 %20, 28 + %22 = getelementptr inbounds i32* %out, i64 %2 + store i32 %15, i32* %22, align 4 + %23 = getelementptr inbounds i32* %out, i64 %5 + store i32 %17, i32* %23, align 4 + %24 = getelementptr inbounds i32* %out, i64 %8 + store i32 %19, i32* %24, align 4 + %25 = getelementptr inbounds i32* %out, i64 %11 + store i32 %21, i32* %25, align 4 + %26 = add i64 %i.019, 1 + %exitcond = icmp eq i64 %26, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + ret i32 undef +} diff --git a/test/Transforms/SLPVectorizer/X86/hoist.ll b/test/Transforms/SLPVectorizer/X86/hoist.ll new file mode 100644 index 000000000000..5074ceaaabd7 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/hoist.ll @@ -0,0 +1,59 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" +target triple = "i386-apple-macosx10.9.0" + +;int foo(int *A, int n, int k) { +; for (int i=0; i < 10000; i+=4) { +; A[i] += n; +; A[i+1] += k; +; A[i+2] += n; +; A[i+3] += k; +; } +;} + +; preheader: +;CHECK: entry +;CHECK-NEXT: insertelement +;CHECK-NEXT: insertelement +;CHECK-NEXT: insertelement +;CHECK-NEXT: insertelement +; loop body: +;CHECK: phi +;CHECK: load <4 x i32> +;CHECK: add <4 x i32> +;CHECK: store <4 x i32> +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32 %n, i32 %k) { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.body + %i.024 = phi i32 [ 0, %entry ], [ %add10, %for.body ] + %arrayidx = getelementptr inbounds i32* %A, i32 %i.024 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %n + store i32 %add, i32* %arrayidx, align 4 + %add121 = or i32 %i.024, 1 + %arrayidx2 = getelementptr inbounds i32* %A, i32 %add121 + %1 = load i32* %arrayidx2, align 4 + %add3 = add nsw i32 %1, %k + store i32 %add3, i32* %arrayidx2, align 4 + %add422 = or i32 %i.024, 2 + %arrayidx5 = getelementptr inbounds i32* %A, i32 %add422 + %2 = load i32* %arrayidx5, align 4 + %add6 = add nsw i32 %2, %n + store i32 %add6, i32* %arrayidx5, align 4 + %add723 = or i32 %i.024, 3 + %arrayidx8 = getelementptr inbounds i32* %A, i32 %add723 + %3 = load i32* %arrayidx8, align 4 + %add9 = add nsw i32 %3, %k + store i32 %add9, i32* %arrayidx8, align 4 + %add10 = add nsw i32 %i.024, 4 + %cmp = icmp slt i32 %add10, 10000 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body + ret i32 undef +} + diff --git a/test/Transforms/SLPVectorizer/X86/lit.local.cfg b/test/Transforms/SLPVectorizer/X86/lit.local.cfg new file mode 100644 index 000000000000..a8ad0f1a28b2 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'X86' in targets: + config.unsupported = True + diff --git a/test/Transforms/SLPVectorizer/X86/loopinvariant.ll b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll new file mode 100644 index 000000000000..4a37fce2ff24 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/loopinvariant.ll @@ -0,0 +1,69 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK: @foo +;CHECK: load <4 x i32> +;CHECK: add <4 x i32> +;CHECK: store <4 x i32> +;CHECK: load <4 x i32> +;CHECK: add <4 x i32> +;CHECK: store <4 x i32> +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32 %n) #0 { +entry: + %cmp62 = icmp sgt i32 %n, 0 + br i1 %cmp62, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ] + %arrayidx = getelementptr inbounds i32* %A, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %add1 = add nsw i32 %0, %n + store i32 %add1, i32* %arrayidx, align 4 + %1 = or i64 %indvars.iv, 1 + %arrayidx4 = getelementptr inbounds i32* %A, i64 %1 + %2 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %2, %n + store i32 %add5, i32* %arrayidx4, align 4 + %3 = or i64 %indvars.iv, 2 + %arrayidx8 = getelementptr inbounds i32* %A, i64 %3 + %4 = load i32* %arrayidx8, align 4 + %add9 = add nsw i32 %4, %n + store i32 %add9, i32* %arrayidx8, align 4 + %5 = or i64 %indvars.iv, 3 + %arrayidx12 = getelementptr inbounds i32* %A, i64 %5 + %6 = load i32* %arrayidx12, align 4 + %add13 = add nsw i32 %6, %n + store i32 %add13, i32* %arrayidx12, align 4 + %7 = or i64 %indvars.iv, 4 + %arrayidx16 = getelementptr inbounds i32* %A, i64 %7 + %8 = load i32* %arrayidx16, align 4 + %add17 = add nsw i32 %8, %n + store i32 %add17, i32* %arrayidx16, align 4 + %9 = or i64 %indvars.iv, 5 + %arrayidx20 = getelementptr inbounds i32* %A, i64 %9 + %10 = load i32* %arrayidx20, align 4 + %add21 = add nsw i32 %10, %n + store i32 %add21, i32* %arrayidx20, align 4 + %11 = or i64 %indvars.iv, 6 + %arrayidx24 = getelementptr inbounds i32* %A, i64 %11 + %12 = load i32* %arrayidx24, align 4 + %add25 = add nsw i32 %12, %n + store i32 %add25, i32* %arrayidx24, align 4 + %13 = or i64 %indvars.iv, 7 + %arrayidx28 = getelementptr inbounds i32* %A, i64 %13 + %14 = load i32* %arrayidx28, align 4 + %add29 = add nsw i32 %14, %n + store i32 %add29, i32* %arrayidx28, align 4 + %indvars.iv.next = add i64 %indvars.iv, 8 + %15 = trunc i64 %indvars.iv.next to i32 + %cmp = icmp slt i32 %15, %n + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body, %entry + ret i32 undef +} + +attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/Transforms/SLPVectorizer/X86/multi_user.ll b/test/Transforms/SLPVectorizer/X86/multi_user.ll new file mode 100644 index 000000000000..aaa6063fdeda --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/multi_user.ll @@ -0,0 +1,47 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.7.0" + +;int foo (int *A, int n) { +; A[0] += n * 5 + 7; +; A[1] += n * 5 + 8; +; A[2] += n * 5 + 9; +; A[3] += n * 5 + 10; +; A[4] += n * 5 + 11; +;} + +;CHECK: @foo +;CHECK: insertelement <4 x i32> +;CHECK: load <4 x i32> +;CHECK: add <4 x i32> +;CHECK: store <4 x i32> +;CHECK: ret +define i32 @foo(i32* nocapture %A, i32 %n) { + %1 = mul nsw i32 %n, 5 + %2 = add nsw i32 %1, 7 + %3 = load i32* %A, align 4 + %4 = add nsw i32 %2, %3 + store i32 %4, i32* %A, align 4 + %5 = add nsw i32 %1, 8 + %6 = getelementptr inbounds i32* %A, i64 1 + %7 = load i32* %6, align 4 + %8 = add nsw i32 %5, %7 + store i32 %8, i32* %6, align 4 + %9 = add nsw i32 %1, 9 + %10 = getelementptr inbounds i32* %A, i64 2 + %11 = load i32* %10, align 4 + %12 = add nsw i32 %9, %11 + store i32 %12, i32* %10, align 4 + %13 = add nsw i32 %1, 10 + %14 = getelementptr inbounds i32* %A, i64 3 + %15 = load i32* %14, align 4 + %16 = add nsw i32 %13, %15 + store i32 %16, i32* %14, align 4 + %17 = add nsw i32 %1, 11 + %18 = getelementptr inbounds i32* %A, i64 4 + %19 = load i32* %18, align 4 + %20 = add nsw i32 %17, %19 + store i32 %20, i32* %18, align 4 + ret i32 undef +} diff --git a/test/Transforms/SLPVectorizer/X86/reduction.ll b/test/Transforms/SLPVectorizer/X86/reduction.ll new file mode 100644 index 000000000000..70b7c3a0b998 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/reduction.ll @@ -0,0 +1,47 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" +target triple = "i386-apple-macosx10.8.0" + +; int foo(double *A, int n, int m) { +; double sum = 0, v1 = 2, v0 = 3; +; for (int i=0; i < n; ++i) +; sum += 7*A[i*2] + 7*A[i*2+1]; +; return sum; +; } + +;CHECK: reduce +;CHECK: load <2 x double> +;CHECK: fmul <2 x double> +;CHECK: ret +define i32 @reduce(double* nocapture %A, i32 %n, i32 %m) { +entry: + %cmp13 = icmp sgt i32 %n, 0 + br i1 %cmp13, label %for.body, label %for.end + +for.body: ; preds = %entry, %for.body + %i.015 = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %sum.014 = phi double [ %add6, %for.body ], [ 0.000000e+00, %entry ] + %mul = shl nsw i32 %i.015, 1 + %arrayidx = getelementptr inbounds double* %A, i32 %mul + %0 = load double* %arrayidx, align 4 + %mul1 = fmul double %0, 7.000000e+00 + %add12 = or i32 %mul, 1 + %arrayidx3 = getelementptr inbounds double* %A, i32 %add12 + %1 = load double* %arrayidx3, align 4 + %mul4 = fmul double %1, 7.000000e+00 + %add5 = fadd double %mul1, %mul4 + %add6 = fadd double %sum.014, %add5 + %inc = add nsw i32 %i.015, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.cond.for.end_crit_edge, label %for.body + +for.cond.for.end_crit_edge: ; preds = %for.body + %phitmp = fptosi double %add6 to i32 + br label %for.end + +for.end: ; preds = %for.cond.for.end_crit_edge, %entry + %sum.0.lcssa = phi i32 [ %phitmp, %for.cond.for.end_crit_edge ], [ 0, %entry ] + ret i32 %sum.0.lcssa +} + diff --git a/test/Transforms/SLPVectorizer/X86/reduction2.ll b/test/Transforms/SLPVectorizer/X86/reduction2.ll new file mode 100644 index 000000000000..7aa7d7e243d0 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/reduction2.ll @@ -0,0 +1,32 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=i386-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32-S128" +target triple = "i386-apple-macosx10.8.0" + +;CHECK: @foo +;CHECK: load <2 x double> +;CHECK: ret +define double @foo(double* nocapture %D) { + br label %1 + +; <label>:1 ; preds = %1, %0 + %i.02 = phi i32 [ 0, %0 ], [ %10, %1 ] + %sum.01 = phi double [ 0.000000e+00, %0 ], [ %9, %1 ] + %2 = shl nsw i32 %i.02, 1 + %3 = getelementptr inbounds double* %D, i32 %2 + %4 = load double* %3, align 4 + %A4 = fmul double %4, %4 + %5 = or i32 %2, 1 + %6 = getelementptr inbounds double* %D, i32 %5 + %7 = load double* %6, align 4 + %A7 = fmul double %7, %7 + %8 = fadd double %A4, %A7 + %9 = fadd double %sum.01, %8 + %10 = add nsw i32 %i.02, 1 + %exitcond = icmp eq i32 %10, 100 + br i1 %exitcond, label %11, label %1 + +; <label>:11 ; preds = %1 + ret double %9 +} + diff --git a/test/Transforms/SLPVectorizer/X86/saxpy.ll b/test/Transforms/SLPVectorizer/X86/saxpy.ll new file mode 100644 index 000000000000..b520913a398d --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/saxpy.ll @@ -0,0 +1,45 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; SLP vectorization example from http://cs.stanford.edu/people/eschkufz/research/asplos291-schkufza.pdf +;CHECK: SAXPY +;CHECK: mul <4 x i32> +;CHECK: ret + +define void @SAXPY(i32* noalias nocapture %x, i32* noalias nocapture %y, i32 %a, i64 %i) { + %1 = getelementptr inbounds i32* %x, i64 %i + %2 = load i32* %1, align 4 + %3 = mul nsw i32 %2, %a + %4 = getelementptr inbounds i32* %y, i64 %i + %5 = load i32* %4, align 4 + %6 = add nsw i32 %3, %5 + store i32 %6, i32* %1, align 4 + %7 = add i64 %i, 1 + %8 = getelementptr inbounds i32* %x, i64 %7 + %9 = load i32* %8, align 4 + %10 = mul nsw i32 %9, %a + %11 = getelementptr inbounds i32* %y, i64 %7 + %12 = load i32* %11, align 4 + %13 = add nsw i32 %10, %12 + store i32 %13, i32* %8, align 4 + %14 = add i64 %i, 2 + %15 = getelementptr inbounds i32* %x, i64 %14 + %16 = load i32* %15, align 4 + %17 = mul nsw i32 %16, %a + %18 = getelementptr inbounds i32* %y, i64 %14 + %19 = load i32* %18, align 4 + %20 = add nsw i32 %17, %19 + store i32 %20, i32* %15, align 4 + %21 = add i64 %i, 3 + %22 = getelementptr inbounds i32* %x, i64 %21 + %23 = load i32* %22, align 4 + %24 = mul nsw i32 %23, %a + %25 = getelementptr inbounds i32* %y, i64 %21 + %26 = load i32* %25, align 4 + %27 = add nsw i32 %24, %26 + store i32 %27, i32* %22, align 4 + ret void +} + diff --git a/test/Transforms/SLPVectorizer/X86/simple-loop.ll b/test/Transforms/SLPVectorizer/X86/simple-loop.ll new file mode 100644 index 000000000000..0111b946d496 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/simple-loop.ll @@ -0,0 +1,100 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +;CHECK:rollable +define i32 @rollable(i32* noalias nocapture %in, i32* noalias nocapture %out, i64 %n) { + %1 = icmp eq i64 %n, 0 + br i1 %1, label %._crit_edge, label %.lr.ph + +.lr.ph: ; preds = %0, %.lr.ph + %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ] + %2 = shl i64 %i.019, 2 + %3 = getelementptr inbounds i32* %in, i64 %2 +;CHECK:load <4 x i32> + %4 = load i32* %3, align 4 + %5 = or i64 %2, 1 + %6 = getelementptr inbounds i32* %in, i64 %5 + %7 = load i32* %6, align 4 + %8 = or i64 %2, 2 + %9 = getelementptr inbounds i32* %in, i64 %8 + %10 = load i32* %9, align 4 + %11 = or i64 %2, 3 + %12 = getelementptr inbounds i32* %in, i64 %11 + %13 = load i32* %12, align 4 +;CHECK:mul <4 x i32> + %14 = mul i32 %4, 7 +;CHECK:add <4 x i32> + %15 = add i32 %14, 7 + %16 = mul i32 %7, 7 + %17 = add i32 %16, 14 + %18 = mul i32 %10, 7 + %19 = add i32 %18, 21 + %20 = mul i32 %13, 7 + %21 = add i32 %20, 28 + %22 = getelementptr inbounds i32* %out, i64 %2 +;CHECK:store <4 x i32> + store i32 %15, i32* %22, align 4 + %23 = getelementptr inbounds i32* %out, i64 %5 + store i32 %17, i32* %23, align 4 + %24 = getelementptr inbounds i32* %out, i64 %8 + store i32 %19, i32* %24, align 4 + %25 = getelementptr inbounds i32* %out, i64 %11 + store i32 %21, i32* %25, align 4 + %26 = add i64 %i.019, 1 + %exitcond = icmp eq i64 %26, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 +;CHECK: ret + ret i32 undef +} + +;CHECK:unrollable +;CHECK-NOT: <4 x i32> +;CHECK: ret +define i32 @unrollable(i32* %in, i32* %out, i64 %n) nounwind ssp uwtable { + %1 = icmp eq i64 %n, 0 + br i1 %1, label %._crit_edge, label %.lr.ph + +.lr.ph: ; preds = %0, %.lr.ph + %i.019 = phi i64 [ %26, %.lr.ph ], [ 0, %0 ] + %2 = shl i64 %i.019, 2 + %3 = getelementptr inbounds i32* %in, i64 %2 + %4 = load i32* %3, align 4 + %5 = or i64 %2, 1 + %6 = getelementptr inbounds i32* %in, i64 %5 + %7 = load i32* %6, align 4 + %8 = or i64 %2, 2 + %9 = getelementptr inbounds i32* %in, i64 %8 + %10 = load i32* %9, align 4 + %11 = or i64 %2, 3 + %12 = getelementptr inbounds i32* %in, i64 %11 + %13 = load i32* %12, align 4 + %14 = mul i32 %4, 7 + %15 = add i32 %14, 7 + %16 = mul i32 %7, 7 + %17 = add i32 %16, 14 + %18 = mul i32 %10, 7 + %19 = add i32 %18, 21 + %20 = mul i32 %13, 7 + %21 = add i32 %20, 28 + %22 = getelementptr inbounds i32* %out, i64 %2 + store i32 %15, i32* %22, align 4 + %23 = getelementptr inbounds i32* %out, i64 %5 + store i32 %17, i32* %23, align 4 + %barrier = call i32 @goo(i32 0) ; <---------------- memory barrier. + %24 = getelementptr inbounds i32* %out, i64 %8 + store i32 %19, i32* %24, align 4 + %25 = getelementptr inbounds i32* %out, i64 %11 + store i32 %21, i32* %25, align 4 + %26 = add i64 %i.019, 1 + %exitcond = icmp eq i64 %26, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + ret i32 undef +} + +declare i32 @goo(i32) diff --git a/test/Transforms/SLPVectorizer/X86/simplebb.ll b/test/Transforms/SLPVectorizer/X86/simplebb.ll new file mode 100644 index 000000000000..cd0b99e64677 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/simplebb.ll @@ -0,0 +1,25 @@ +; RUN: opt < %s -basicaa -slp-vectorizer -dce -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Simple 3-pair chain with loads and stores +; CHECK: test1 +; CHECK: store <2 x double> +; CHECK: ret +define void @test1(double* %a, double* %b, double* %c) { +entry: + %i0 = load double* %a, align 8 + %i1 = load double* %b, align 8 + %mul = fmul double %i0, %i1 + %arrayidx3 = getelementptr inbounds double* %a, i64 1 + %i3 = load double* %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds double* %b, i64 1 + %i4 = load double* %arrayidx4, align 8 + %mul5 = fmul double %i3, %i4 + store double %mul, double* %c, align 8 + %arrayidx5 = getelementptr inbounds double* %c, i64 1 + store double %mul5, double* %arrayidx5, align 8 + ret void +} + diff --git a/test/Transforms/SLPVectorizer/X86/vector.ll b/test/Transforms/SLPVectorizer/X86/vector.ll new file mode 100644 index 000000000000..02a18979c659 --- /dev/null +++ b/test/Transforms/SLPVectorizer/X86/vector.ll @@ -0,0 +1,14 @@ +; RUN: opt < %s -slp-vectorizer -S -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +; Make sure that we are not crashing or changing the code. +;CHECK: test +;CHECK: icmp +;CHECK: ret +define void @test(<4 x i32> %in, <4 x i32> %in2) { + %k = icmp eq <4 x i32> %in, %in2 + ret void +} + diff --git a/test/Transforms/SLPVectorizer/lit.local.cfg b/test/Transforms/SLPVectorizer/lit.local.cfg new file mode 100644 index 000000000000..19eebc0ac7ac --- /dev/null +++ b/test/Transforms/SLPVectorizer/lit.local.cfg @@ -0,0 +1 @@ +config.suffixes = ['.ll', '.c', '.cpp'] diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll index 30dd21774343..834032246f9a 100644 --- a/test/Transforms/SROA/basictest.ll +++ b/test/Transforms/SROA/basictest.ll @@ -1243,3 +1243,77 @@ entry: %v = load i32* %a ret i32 %v } + +define void @PR15674(i8* %data, i8* %src, i32 %size) { +; Arrange (via control flow) to have unmerged stores of a particular width to +; an alloca where we incrementally store from the end of the array toward the +; beginning of the array. Ensure that the final integer store, despite being +; convertable to the integer type that we end up promoting this alloca toward, +; doesn't get widened to a full alloca store. +; CHECK: @PR15674 + +entry: + %tmp = alloca [4 x i8], align 1 +; CHECK: alloca i32 + + switch i32 %size, label %end [ + i32 4, label %bb4 + i32 3, label %bb3 + i32 2, label %bb2 + i32 1, label %bb1 + ] + +bb4: + %src.gep3 = getelementptr inbounds i8* %src, i32 3 + %src.3 = load i8* %src.gep3 + %tmp.gep3 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 3 + store i8 %src.3, i8* %tmp.gep3 +; CHECK: store i8 + + br label %bb3 + +bb3: + %src.gep2 = getelementptr inbounds i8* %src, i32 2 + %src.2 = load i8* %src.gep2 + %tmp.gep2 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 2 + store i8 %src.2, i8* %tmp.gep2 +; CHECK: store i8 + + br label %bb2 + +bb2: + %src.gep1 = getelementptr inbounds i8* %src, i32 1 + %src.1 = load i8* %src.gep1 + %tmp.gep1 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 1 + store i8 %src.1, i8* %tmp.gep1 +; CHECK: store i8 + + br label %bb1 + +bb1: + %src.gep0 = getelementptr inbounds i8* %src, i32 0 + %src.0 = load i8* %src.gep0 + %tmp.gep0 = getelementptr inbounds [4 x i8]* %tmp, i32 0, i32 0 + store i8 %src.0, i8* %tmp.gep0 +; CHECK: store i8 + + br label %end + +end: + %tmp.raw = bitcast [4 x i8]* %tmp to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %data, i8* %tmp.raw, i32 %size, i32 1, i1 false) + ret void +; CHECK: ret void +} + +define void @PR15805(i1 %a, i1 %b) { +; CHECK: @PR15805 +; CHECK: select i1 undef, i64* %c, i64* %c +; CHECK: ret void + + %c = alloca i64, align 8 + %p.0.c = select i1 undef, i64* %c, i64* %c + %cond.in = select i1 undef, i64* %p.0.c, i64* %c + %cond = load i64* %cond.in, align 8 + ret void +} diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll index 02f6d040cc95..3336515770a3 100644 --- a/test/Transforms/SROA/vector-promotion.ll +++ b/test/Transforms/SROA/vector-promotion.ll @@ -224,26 +224,26 @@ entry: %a.cast0 = bitcast i32* %a.gep0 to <2 x i32>* store <2 x i32> <i32 0, i32 0>, <2 x i32>* %a.cast0 ; CHECK-NOT: store -; CHECK: %[[insert1:.*]] = shufflevector <4 x i32> <i32 0, i32 0, i32 undef, i32 undef>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, {{.*}}> +; CHECK: select <4 x i1> <i1 true, i1 true, i1 false, i1 false> %a.gep1 = getelementptr <4 x i32>* %a, i32 0, i32 1 %a.cast1 = bitcast i32* %a.gep1 to <2 x i32>* store <2 x i32> <i32 1, i32 1>, <2 x i32>* %a.cast1 -; CHECK-NEXT: %[[insert2:.*]] = shufflevector <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>, <4 x i32> %[[insert1]], <4 x i32> <i32 4, i32 1, i32 2, {{.*}}> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false> %a.gep2 = getelementptr <4 x i32>* %a, i32 0, i32 2 %a.cast2 = bitcast i32* %a.gep2 to <2 x i32>* store <2 x i32> <i32 2, i32 2>, <2 x i32>* %a.cast2 -; CHECK-NEXT: %[[insert3:.*]] = shufflevector <4 x i32> <i32 undef, i32 undef, i32 2, i32 2>, <4 x i32> %[[insert2]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true> %a.gep3 = getelementptr <4 x i32>* %a, i32 0, i32 3 store i32 3, i32* %a.gep3 -; CHECK-NEXT: %[[insert4:.*]] = insertelement <4 x i32> %[[insert3]], i32 3, i32 3 +; CHECK-NEXT: insertelement <4 x i32> %ret = load <4 x i32>* %a ret <4 x i32> %ret -; CHECK-NEXT: ret <4 x i32> %[[insert4]] +; CHECK-NEXT: ret <4 x i32> } define <4 x i32> @test_subvec_load() { @@ -291,27 +291,27 @@ entry: %a.cast0 = bitcast float* %a.gep0 to i8* call void @llvm.memset.p0i8.i32(i8* %a.cast0, i8 0, i32 8, i32 0, i1 false) ; CHECK-NOT: store -; CHECK: %[[insert1:.*]] = shufflevector <4 x float> <float 0.000000e+00, float 0.000000e+00, float undef, float undef>, <4 x float> undef, <4 x i32> <i32 0, i32 1, {{.*}}> +; CHECK: select <4 x i1> <i1 true, i1 true, i1 false, i1 false> %a.gep1 = getelementptr <4 x float>* %a, i32 0, i32 1 %a.cast1 = bitcast float* %a.gep1 to i8* call void @llvm.memset.p0i8.i32(i8* %a.cast1, i8 1, i32 8, i32 0, i1 false) -; CHECK-NEXT: %[[insert2:.*]] = shufflevector <4 x float> <float undef, float 0x3820202020000000, float 0x3820202020000000, float undef>, <4 x float> %[[insert1]], <4 x i32> <i32 4, i32 1, i32 2, {{.*}}> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false> %a.gep2 = getelementptr <4 x float>* %a, i32 0, i32 2 %a.cast2 = bitcast float* %a.gep2 to i8* call void @llvm.memset.p0i8.i32(i8* %a.cast2, i8 3, i32 8, i32 0, i1 false) -; CHECK-NEXT: %[[insert3:.*]] = shufflevector <4 x float> <float undef, float undef, float 0x3860606060000000, float 0x3860606060000000>, <4 x float> %[[insert2]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true> %a.gep3 = getelementptr <4 x float>* %a, i32 0, i32 3 %a.cast3 = bitcast float* %a.gep3 to i8* call void @llvm.memset.p0i8.i32(i8* %a.cast3, i8 7, i32 4, i32 0, i1 false) -; CHECK-NEXT: %[[insert4:.*]] = insertelement <4 x float> %[[insert3]], float 0x38E0E0E0E0000000, i32 3 +; CHECK-NEXT: insertelement <4 x float> %ret = load <4 x float>* %a ret <4 x float> %ret -; CHECK-NEXT: ret <4 x float> %[[insert4]] +; CHECK-NEXT: ret <4 x float> } define <4 x float> @test_subvec_memcpy(i8* %x, i8* %y, i8* %z, i8* %f, i8* %out) { @@ -326,7 +326,7 @@ entry: ; CHECK: %[[xptr:.*]] = bitcast i8* %x to <2 x float>* ; CHECK-NEXT: %[[x:.*]] = load <2 x float>* %[[xptr]] ; CHECK-NEXT: %[[expand_x:.*]] = shufflevector <2 x float> %[[x]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> -; CHECK-NEXT: %[[insert_x:.*]] = shufflevector <4 x float> %[[expand_x]], <4 x float> undef, <4 x i32> <i32 0, i32 1, {{.*}}> +; CHECK-NEXT: select <4 x i1> <i1 true, i1 true, i1 false, i1 false> %a.gep1 = getelementptr <4 x float>* %a, i32 0, i32 1 %a.cast1 = bitcast float* %a.gep1 to i8* @@ -334,7 +334,7 @@ entry: ; CHECK-NEXT: %[[yptr:.*]] = bitcast i8* %y to <2 x float>* ; CHECK-NEXT: %[[y:.*]] = load <2 x float>* %[[yptr]] ; CHECK-NEXT: %[[expand_y:.*]] = shufflevector <2 x float> %[[y]], <2 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef> -; CHECK-NEXT: %[[insert_y:.*]] = shufflevector <4 x float> %[[expand_y]], <4 x float> %[[insert_x]], <4 x i32> <i32 4, i32 1, i32 2, {{.*}}> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 true, i1 true, i1 false> %a.gep2 = getelementptr <4 x float>* %a, i32 0, i32 2 %a.cast2 = bitcast float* %a.gep2 to i8* @@ -342,14 +342,14 @@ entry: ; CHECK-NEXT: %[[zptr:.*]] = bitcast i8* %z to <2 x float>* ; CHECK-NEXT: %[[z:.*]] = load <2 x float>* %[[zptr]] ; CHECK-NEXT: %[[expand_z:.*]] = shufflevector <2 x float> %[[z]], <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1> -; CHECK-NEXT: %[[insert_z:.*]] = shufflevector <4 x float> %[[expand_z]], <4 x float> %[[insert_y]], <4 x i32> <i32 4, i32 5, i32 2, i32 3> +; CHECK-NEXT: select <4 x i1> <i1 false, i1 false, i1 true, i1 true> %a.gep3 = getelementptr <4 x float>* %a, i32 0, i32 3 %a.cast3 = bitcast float* %a.gep3 to i8* call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a.cast3, i8* %f, i32 4, i32 0, i1 false) ; CHECK-NEXT: %[[fptr:.*]] = bitcast i8* %f to float* ; CHECK-NEXT: %[[f:.*]] = load float* %[[fptr]] -; CHECK-NEXT: %[[insert_f:.*]] = insertelement <4 x float> %[[insert_z]], float %[[f]], i32 3 +; CHECK-NEXT: %[[insert_f:.*]] = insertelement <4 x float> call void @llvm.memcpy.p0i8.p0i8.i32(i8* %out, i8* %a.cast2, i32 8, i32 0, i1 false) ; CHECK-NEXT: %[[outptr:.*]] = bitcast i8* %out to <2 x float>* diff --git a/test/Transforms/ScalarRepl/dynamic-vector-gep.ll b/test/Transforms/ScalarRepl/dynamic-vector-gep.ll deleted file mode 100644 index 565cd7616422..000000000000 --- a/test/Transforms/ScalarRepl/dynamic-vector-gep.ll +++ /dev/null @@ -1,167 +0,0 @@ -; RUN: opt < %s -scalarrepl -S | FileCheck %s - -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "x86_64-apple-darwin10.0.0" - -; CHECK: @test1 -; CHECK: %[[alloc:[\.a-z0-9]*]] = alloca <4 x float> -; CHECK: store <4 x float> zeroinitializer, <4 x float>* %[[alloc]] -; CHECK: memset -; CHECK: extractelement <4 x float> zeroinitializer, i32 %idx2 - -; Split the array but don't replace the memset with an insert -; element as its not a constant offset. -; The load, however, can be replaced with an extract element. -define float @test1(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca [4 x <4 x float>] - store [4 x <4 x float>] zeroinitializer, [4 x <4 x float>]* %0 - %ptr1 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0, i32 %idx1 - %cast = bitcast float* %ptr1 to i8* - call void @llvm.memset.p0i8.i32(i8* %cast, i8 0, i32 4, i32 4, i1 false) - %ptr2 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 1, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: @test2 -; CHECK: %[[ins:[\.a-z0-9]*]] = insertelement <4 x float> zeroinitializer, float 1.000000e+00, i32 %idx1 -; CHECK: extractelement <4 x float> %[[ins]], i32 %idx2 - -; Do SROA on the array when it has dynamic vector reads and writes. -define float @test2(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca [4 x <4 x float>] - store [4 x <4 x float>] zeroinitializer, [4 x <4 x float>]* %0 - %ptr1 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr2 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: test3 -; CHECK: %0 = alloca [4 x <4 x float>] -; CHECK-NOT: alloca - -; Don't do SROA on a dynamically indexed vector when it spans -; more than one array element of the alloca array it is within. -define float @test3(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca [4 x <4 x float>] - store [4 x <4 x float>] zeroinitializer, [4 x <4 x float>]* %0 - %bigvec = bitcast [4 x <4 x float>]* %0 to <16 x float>* - %ptr1 = getelementptr <16 x float>* %bigvec, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr2 = getelementptr <16 x float>* %bigvec, i32 0, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: test4 -; CHECK: insertelement <16 x float> zeroinitializer, float 1.000000e+00, i32 %idx1 -; CHECK: extractelement <16 x float> %0, i32 %idx2 - -; Don't do SROA on a dynamically indexed vector when it spans -; more than one array element of the alloca array it is within. -; However, unlike test3, the store is on the vector type -; so SROA will convert the large alloca into the large vector -; type and do all accesses with insert/extract element -define float @test4(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca [4 x <4 x float>] - %bigvec = bitcast [4 x <4 x float>]* %0 to <16 x float>* - store <16 x float> zeroinitializer, <16 x float>* %bigvec - %ptr1 = getelementptr <16 x float>* %bigvec, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr2 = getelementptr <16 x float>* %bigvec, i32 0, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: @test5 -; CHECK: %0 = alloca [4 x <4 x float>] -; CHECK-NOT: alloca - -; Don't do SROA as the is a second dynamically indexed array -; which may span multiple elements of the alloca. -define float @test5(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca [4 x <4 x float>] - store [4 x <4 x float>] zeroinitializer, [4 x <4 x float>]* %0 - %ptr1 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0, i32 %idx1 - %ptr2 = bitcast float* %ptr1 to [1 x <2 x float>]* - %ptr3 = getelementptr [1 x <2 x float>]* %ptr2, i32 0, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr4 = getelementptr [4 x <4 x float>]* %0, i32 0, i32 0, i32 %idx2 - %ret = load float* %ptr4 - ret float %ret -} - -; CHECK: test6 -; CHECK: insertelement <4 x float> zeroinitializer, float 1.000000e+00, i32 %idx1 -; CHECK: extractelement <4 x float> zeroinitializer, i32 %idx2 - -%vector.pair = type { %vector.anon, %vector.anon } -%vector.anon = type { %vector } -%vector = type { <4 x float> } - -; Dynamic GEPs on vectors were crashing when the vector was inside a struct -; as the new GEP for the new alloca might not include all the indices from -; the original GEP, just the indices it needs to get to the correct offset of -; some type, not necessarily the dynamic vector. -; This test makes sure we don't have this crash. -define float @test6(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca %vector.pair - store %vector.pair zeroinitializer, %vector.pair* %0 - %ptr1 = getelementptr %vector.pair* %0, i32 0, i32 0, i32 0, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr2 = getelementptr %vector.pair* %0, i32 0, i32 1, i32 0, i32 0, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: test7 -; CHECK: insertelement <4 x float> zeroinitializer, float 1.000000e+00, i32 %idx1 -; CHECK: extractelement <4 x float> zeroinitializer, i32 %idx2 - -%array.pair = type { [2 x %array.anon], %array.anon } -%array.anon = type { [2 x %vector] } - -; This is the same as test6 and tests the same crash, but on arrays. -define float @test7(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca %array.pair - store %array.pair zeroinitializer, %array.pair* %0 - %ptr1 = getelementptr %array.pair* %0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 %idx1 - store float 1.0, float* %ptr1 - %ptr2 = getelementptr %array.pair* %0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 %idx2 - %ret = load float* %ptr2 - ret float %ret -} - -; CHECK: test8 -; CHECK: %[[offset1:[\.a-z0-9]*]] = add i32 %idx1, 1 -; CHECK: %[[ins:[\.a-z0-9]*]] = insertelement <4 x float> zeroinitializer, float 1.000000e+00, i32 %[[offset1]] -; CHECK: %[[offset2:[\.a-z0-9]*]] = add i32 %idx2, 2 -; CHECK: extractelement <4 x float> %[[ins]], i32 %[[offset2]] - -; Do SROA on the vector when it has dynamic vector reads and writes -; from a non-zero offset. -define float @test8(i32 %idx1, i32 %idx2) { -entry: - %0 = alloca <4 x float> - store <4 x float> zeroinitializer, <4 x float>* %0 - %ptr1 = getelementptr <4 x float>* %0, i32 0, i32 1 - %ptr2 = bitcast float* %ptr1 to <3 x float>* - %ptr3 = getelementptr <3 x float>* %ptr2, i32 0, i32 %idx1 - store float 1.0, float* %ptr3 - %ptr4 = getelementptr <4 x float>* %0, i32 0, i32 2 - %ptr5 = bitcast float* %ptr4 to <2 x float>* - %ptr6 = getelementptr <2 x float>* %ptr5, i32 0, i32 %idx2 - %ret = load float* %ptr6 - ret float %ret -} - -declare void @llvm.memset.p0i8.i32(i8*, i8, i32, i32, i1) diff --git a/test/Transforms/SimplifyCFG/2003-08-17-BranchFold.ll b/test/Transforms/SimplifyCFG/2003-08-17-BranchFold.ll index fc89b165f85b..f6b068fd79c3 100644 --- a/test/Transforms/SimplifyCFG/2003-08-17-BranchFold.ll +++ b/test/Transforms/SimplifyCFG/2003-08-17-BranchFold.ll @@ -1,11 +1,11 @@ ; This test checks to make sure that 'br X, Dest, Dest' is folded into ; 'br Dest' -; RUN: opt < %s -simplifycfg -S | \ -; RUN: not grep "br i1 %c2" +; RUN: opt < %s -simplifycfg -S | FileCheck %s declare void @noop() +; CHECK-NOT: br i1 %c2 define i32 @test(i1 %c1, i1 %c2) { call void @noop( ) br i1 %c1, label %A, label %Y diff --git a/test/Transforms/SimplifyCFG/2003-08-17-BranchFoldOrdering.ll b/test/Transforms/SimplifyCFG/2003-08-17-BranchFoldOrdering.ll index c1b032fb8b39..78049080a64e 100644 --- a/test/Transforms/SimplifyCFG/2003-08-17-BranchFoldOrdering.ll +++ b/test/Transforms/SimplifyCFG/2003-08-17-BranchFoldOrdering.ll @@ -3,8 +3,9 @@ ; due to the fact that the SimplifyCFG function does not use ; the ConstantFoldTerminator function. -; RUN: opt < %s -simplifycfg -S | \ -; RUN: not grep "br i1 %c2" +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; CHECK-NOT: br i1 %c2 declare void @noop() diff --git a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll index af59ba04f441..fbfb100274f6 100644 --- a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll +++ b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch-dbg.ll @@ -1,7 +1,6 @@ -; RUN: opt < %s -simplifycfg -S | \ -; RUN: not grep switch - +; RUN: opt < %s -simplifycfg -S | FileCheck %s +; CHECK-NOT: switch %llvm.dbg.anchor.type = type { i32, i32 } %llvm.dbg.compile_unit.type = type { i32, { }*, i32, i8*, i8*, i8*, i1, i1, i8* } diff --git a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll index 93f851c6f9ea..806659635e4b 100644 --- a/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll +++ b/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll @@ -1,5 +1,6 @@ -; RUN: opt < %s -simplifycfg -S | \ -; RUN: not grep switch +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; CHECK-NOT: switch ; Test normal folding define i32 @test1() { diff --git a/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll b/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll index 760aa139bf7b..907261bd438a 100644 --- a/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll +++ b/test/Transforms/SimplifyCFG/2005-12-03-IncorrectPHIFold.ll @@ -1,9 +1,7 @@ ; Make sure this doesn't turn into an infinite loop -; RUN: opt < %s -simplifycfg -constprop -simplifycfg |\ -; RUN: llvm-dis | grep bb86 -; END. - +; RUN: opt < %s -simplifycfg -constprop -simplifycfg | llvm-dis | FileCheck %s + %struct.anon = type { i32, i32, i32, i32, [1024 x i8] } @_zero_ = external global %struct.anon* ; <%struct.anon**> [#uses=2] @_one_ = external global %struct.anon* ; <%struct.anon**> [#uses=4] @@ -112,6 +110,7 @@ cond_true83: ; preds = %bb80 %tmp71 = call i32 @_do_compare( %struct.anon* null, %struct.anon* null, i32 0, i32 1 ) ; <i32> [#uses=1] %tmp76 = icmp eq i32 %tmp71, 0 ; <i1> [#uses=1] br i1 %tmp76, label %bb80.outer, label %bb80 +; CHECK: bb86 bb86: ; preds = %bb80 call void @free_num( %struct.anon** %num ) %tmp88 = load %struct.anon** %guess ; <%struct.anon*> [#uses=1] diff --git a/test/Transforms/SimplifyCFG/2006-10-19-UncondDiv.ll b/test/Transforms/SimplifyCFG/2006-10-19-UncondDiv.ll index 009d1c8cc4da..8f21b9bab9b6 100644 --- a/test/Transforms/SimplifyCFG/2006-10-19-UncondDiv.ll +++ b/test/Transforms/SimplifyCFG/2006-10-19-UncondDiv.ll @@ -1,6 +1,7 @@ ; PR957 -; RUN: opt < %s -simplifycfg -S | \ -; RUN: not grep select +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; CHECK-NOT: select @G = extern_weak global i32 diff --git a/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll b/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll index a20c46e1ad1f..a90e07276253 100644 --- a/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll +++ b/test/Transforms/SimplifyCFG/2007-11-22-InvokeNoUnwind.ll @@ -1,4 +1,6 @@ -; RUN: opt < %s -simplifycfg -S | not grep invoke +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; CHECK-NOT: invoke declare i32 @func(i8*) nounwind diff --git a/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll b/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll index 14baeea4b0b9..cf29b7159793 100644 --- a/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll +++ b/test/Transforms/SimplifyCFG/2008-01-02-hoist-fp-add.ll @@ -1,5 +1,5 @@ ; The phi should not be eliminated in this case, because the fp op could trap. -; RUN: opt < %s -simplifycfg -S | grep "= phi double" +; RUN: opt < %s -simplifycfg -S | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i686-apple-darwin8" @@ -19,6 +19,7 @@ cond_true: ; preds = %entry br label %cond_next cond_next: ; preds = %cond_true, %entry +; CHECK: = phi double %F.0 = phi double [ %tmp, %entry ], [ %tmp7, %cond_true ] ; <double> [#uses=1] store double %F.0, double* @G, align 8 ret void diff --git a/test/Transforms/SimplifyCFG/speculate-store.ll b/test/Transforms/SimplifyCFG/speculate-store.ll new file mode 100644 index 000000000000..8d7fe79dcd4e --- /dev/null +++ b/test/Transforms/SimplifyCFG/speculate-store.ll @@ -0,0 +1,108 @@ +; RUN: opt -simplifycfg -S < %s | FileCheck %s + +define void @ifconvertstore(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) { +entry: + %arrayidx = getelementptr inbounds i32* %B, i64 0 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %C + %arrayidx2 = getelementptr inbounds i32* %A, i64 0 + +; First store to the location. + store i32 %add, i32* %arrayidx2, align 4 + %arrayidx4 = getelementptr inbounds i32* %B, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %1, %D + %cmp6 = icmp sgt i32 %add5, %C + br i1 %cmp6, label %if.then, label %ret.end + +; Make sure we speculate stores like the following one. It is cheap compared to +; a mispredicated branch. +; CHECK: @ifconvertstore +; CHECK: %add5.add = select i1 %cmp6, i32 %add5, i32 %add +; CHECK: store i32 %add5.add, i32* %arrayidx2, align 4 +if.then: + store i32 %add5, i32* %arrayidx2, align 4 + br label %ret.end + +ret.end: + ret void +} + +define void @noifconvertstore1(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) { +entry: + %arrayidx = getelementptr inbounds i32* %B, i64 0 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %C + %arrayidx2 = getelementptr inbounds i32* %A, i64 0 + +; Store to a different location. + store i32 %add, i32* %arrayidx, align 4 + %arrayidx4 = getelementptr inbounds i32* %B, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %1, %D + %cmp6 = icmp sgt i32 %add5, %C + br i1 %cmp6, label %if.then, label %ret.end + +; CHECK: @noifconvertstore1 +; CHECK-NOT: select +if.then: + store i32 %add5, i32* %arrayidx2, align 4 + br label %ret.end + +ret.end: + ret void +} + +declare void @unknown_fun() + +define void @noifconvertstore2(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) { +entry: + %arrayidx = getelementptr inbounds i32* %B, i64 0 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %C + %arrayidx2 = getelementptr inbounds i32* %A, i64 0 + +; First store to the location. + store i32 %add, i32* %arrayidx2, align 4 + call void @unknown_fun() + %arrayidx4 = getelementptr inbounds i32* %B, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %1, %D + %cmp6 = icmp sgt i32 %add5, %C + br i1 %cmp6, label %if.then, label %ret.end + +; CHECK: @noifconvertstore2 +; CHECK-NOT: select +if.then: + store i32 %add5, i32* %arrayidx2, align 4 + br label %ret.end + +ret.end: + ret void +} + +define void @noifconvertstore_volatile(i32 %m, i32* %A, i32* %B, i32 %C, i32 %D) { +entry: + %arrayidx = getelementptr inbounds i32* %B, i64 0 + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, %C + %arrayidx2 = getelementptr inbounds i32* %A, i64 0 + +; First store to the location. + store i32 %add, i32* %arrayidx2, align 4 + %arrayidx4 = getelementptr inbounds i32* %B, i64 1 + %1 = load i32* %arrayidx4, align 4 + %add5 = add nsw i32 %1, %D + %cmp6 = icmp sgt i32 %add5, %C + br i1 %cmp6, label %if.then, label %ret.end + +; Make sure we don't speculate volatile stores. +; CHECK: @noifconvertstore_volatile +; CHECK-NOT: select +if.then: + store volatile i32 %add5, i32* %arrayidx2, align 4 + br label %ret.end + +ret.end: + ret void +} diff --git a/test/Transforms/SimplifyCFG/switch-to-icmp.ll b/test/Transforms/SimplifyCFG/switch-to-icmp.ll index 414f8475bc23..e9a6db45cb00 100644 --- a/test/Transforms/SimplifyCFG/switch-to-icmp.ll +++ b/test/Transforms/SimplifyCFG/switch-to-icmp.ll @@ -37,3 +37,21 @@ lor.end: ; CHECK: @test2 ; CHECK: %switch = icmp ult i32 %x, 2 } + +define i32 @test3(i1 %flag) { +entry: + switch i1 %flag, label %bad [ + i1 true, label %good + i1 false, label %good + ] + +good: + ret i32 0 + +bad: + ret i32 1 + +; CHECK: @test3 +; CHECK: entry: +; CHECK-NEXT: ret i32 0 +} diff --git a/test/Verifier/2002-04-13-RetTypes.ll b/test/Verifier/2002-04-13-RetTypes.ll index af468395be38..9385ebe5ff1a 100644 --- a/test/Verifier/2002-04-13-RetTypes.ll +++ b/test/Verifier/2002-04-13-RetTypes.ll @@ -1,7 +1,8 @@ -; RUN: not llvm-as < %s 2>&1 | grep "value doesn't match function result type 'i32'" +; RUN: not llvm-as < %s 2>&1 | FileCheck %s ; Verify the operand type of the ret instructions in a function match the -; delcared return type of the function they live in. +; declared return type of the function they live in. +; CHECK: value doesn't match function result type 'i32' ; define i32 @testfunc() { diff --git a/test/Verifier/2002-11-05-GetelementptrPointers.ll b/test/Verifier/2002-11-05-GetelementptrPointers.ll index 108ae5f76579..66b233ec63ae 100644 --- a/test/Verifier/2002-11-05-GetelementptrPointers.ll +++ b/test/Verifier/2002-11-05-GetelementptrPointers.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as < %s 2>&1 | grep "invalid getelementptr indices" +; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; CHECK: invalid getelementptr indices ; This testcase is invalid because we are indexing into a pointer that is ; contained WITHIN a structure. diff --git a/test/Verifier/2006-07-11-StoreStruct.ll b/test/Verifier/2006-07-11-StoreStruct.ll index 65b229d1ca9d..70aea8779bf1 100644 --- a/test/Verifier/2006-07-11-StoreStruct.ll +++ b/test/Verifier/2006-07-11-StoreStruct.ll @@ -1,4 +1,6 @@ -; RUN: llvm-as < %s 2>&1 | not grep "Instruction operands must be first-class" +; RUN: llvm-as < %s 2>&1 | FileCheck %s + +; CHECK-NOT: Instruction operands must be first-class ; This previously was for PR826, but structs are now first-class so ; the following is now valid. diff --git a/test/Verifier/2006-10-15-AddrLabel.ll b/test/Verifier/2006-10-15-AddrLabel.ll index c8fedb5f195d..decbf5ba42bb 100644 --- a/test/Verifier/2006-10-15-AddrLabel.ll +++ b/test/Verifier/2006-10-15-AddrLabel.ll @@ -1,5 +1,6 @@ ; RUN: not llvm-as < %s > /dev/null 2> %t -; RUN: grep "basic block pointers are invalid" %t +; RUN: FileCheck %s --input-file=%t +; CHECK: basic block pointers are invalid define i32 @main() { %foo = call i8* %llvm.stacksave() diff --git a/test/Verifier/2006-12-12-IntrinsicDefine.ll b/test/Verifier/2006-12-12-IntrinsicDefine.ll index 6e7468c1d9eb..8cc3d24b5c80 100644 --- a/test/Verifier/2006-12-12-IntrinsicDefine.ll +++ b/test/Verifier/2006-12-12-IntrinsicDefine.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as < %s 2>&1 | grep "llvm intrinsics cannot be defined" +; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; CHECK: llvm intrinsics cannot be defined ; PR1047 define void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) { diff --git a/test/Verifier/2008-03-01-AllocaSized.ll b/test/Verifier/2008-03-01-AllocaSized.ll index 51258bef76e5..fc12a96e4f9f 100644 --- a/test/Verifier/2008-03-01-AllocaSized.ll +++ b/test/Verifier/2008-03-01-AllocaSized.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Cannot allocate unsized type" +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: Cannot allocate unsized type ; PR2113 define void @test() { diff --git a/test/Verifier/2008-08-22-MemCpyAlignment.ll b/test/Verifier/2008-08-22-MemCpyAlignment.ll index c6d5afd51c95..3f7cb5234305 100644 --- a/test/Verifier/2008-08-22-MemCpyAlignment.ll +++ b/test/Verifier/2008-08-22-MemCpyAlignment.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "alignment argument of memory intrinsics must be a constant int" +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: alignment argument of memory intrinsics must be a constant int ; PR2318 define void @x(i8* %a, i8* %src, i64 %len, i32 %align) nounwind { diff --git a/test/Verifier/2008-11-15-RetVoid.ll b/test/Verifier/2008-11-15-RetVoid.ll index 42503fabbec9..62f6da113139 100644 --- a/test/Verifier/2008-11-15-RetVoid.ll +++ b/test/Verifier/2008-11-15-RetVoid.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as < %s 2>&1 | grep "value doesn't match function result type 'void'" +; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; CHECK: value doesn't match function result type 'void' define void @foo() { ret i32 0 diff --git a/test/Verifier/2010-08-07-PointerIntrinsic.ll b/test/Verifier/2010-08-07-PointerIntrinsic.ll index 3136c61514ba..a668d04213fa 100644 --- a/test/Verifier/2010-08-07-PointerIntrinsic.ll +++ b/test/Verifier/2010-08-07-PointerIntrinsic.ll @@ -1,5 +1,6 @@ ; RUN: not llvm-as < %s 2> %t -; RUN: grep "Broken module" %t +; RUN: FileCheck %s --input-file=%t +; CHECK: Broken module ; PR7316 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32" diff --git a/test/Verifier/AmbiguousPhi.ll b/test/Verifier/AmbiguousPhi.ll index f31bc107accf..cb05a7282629 100644 --- a/test/Verifier/AmbiguousPhi.ll +++ b/test/Verifier/AmbiguousPhi.ll @@ -1,6 +1,5 @@ -; RUN: not llvm-as < %s 2>&1 | grep "multiple entries for the same basic block" - - +; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; CHECK: multiple entries for the same basic block define i32 @test(i32 %i, i32 %j, i1 %c) { br i1 %c, label %A, label %A diff --git a/test/Verifier/PhiGrouping.ll b/test/Verifier/PhiGrouping.ll index 7b42fd28e3d8..291f0848cb2b 100644 --- a/test/Verifier/PhiGrouping.ll +++ b/test/Verifier/PhiGrouping.ll @@ -1,6 +1,5 @@ -; RUN: not llvm-as < %s 2>&1 | grep "PHI nodes not grouped at top" - - +; RUN: not llvm-as < %s 2>&1 | FileCheck %s +; CHECK: PHI nodes not grouped at top define i32 @test(i32 %i, i32 %j, i1 %c) { br i1 %c, label %A, label %B diff --git a/test/Verifier/SelfReferential.ll b/test/Verifier/SelfReferential.ll index c24c0ebba3d1..7f0166a158d5 100644 --- a/test/Verifier/SelfReferential.ll +++ b/test/Verifier/SelfReferential.ll @@ -1,4 +1,5 @@ -; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Only PHI nodes may reference their own value" +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: Only PHI nodes may reference their own value ; Test that self referential instructions are not allowed diff --git a/test/Verifier/aliasing-chain.ll b/test/Verifier/aliasing-chain.ll index a52e796b2b86..ae0b77fdc395 100644 --- a/test/Verifier/aliasing-chain.ll +++ b/test/Verifier/aliasing-chain.ll @@ -1,5 +1,5 @@ -; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Aliasing chain should end with function or global variable" - +; RUN: not llvm-as %s -o /dev/null 2>&1 | FileCheck %s +; CHECK: Aliasing chain should end with function or global variable ; Test that alising chain does not create a cycle @b1 = alias i32* @c1 diff --git a/test/Verifier/llvm.compiler_used-invalid-type.ll b/test/Verifier/llvm.compiler_used-invalid-type.ll new file mode 100644 index 000000000000..0913027fb479 --- /dev/null +++ b/test/Verifier/llvm.compiler_used-invalid-type.ll @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s + +@llvm.compiler_used = appending global [1 x i32] [i32 0], section "llvm.metadata" + +; CHECK: wrong type for intrinsic global variable +; CHECK-NEXT: [1 x i32]* @llvm.compiler_used diff --git a/test/Verifier/llvm.used-invalid-init.ll b/test/Verifier/llvm.used-invalid-init.ll new file mode 100644 index 000000000000..b0887c994e77 --- /dev/null +++ b/test/Verifier/llvm.used-invalid-init.ll @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s + +@llvm.used = appending global [1 x i8*] zeroinitializer, section "llvm.metadata" + +; CHECK: wrong initalizer for intrinsic global variable +; CHECK-NEXT: [1 x i8*] zeroinitializer diff --git a/test/Verifier/llvm.used-invalid-init2.ll b/test/Verifier/llvm.used-invalid-init2.ll new file mode 100644 index 000000000000..ee8a970bf107 --- /dev/null +++ b/test/Verifier/llvm.used-invalid-init2.ll @@ -0,0 +1,7 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s + +@a = global i8 42 +@llvm.used = appending global [2 x i8*] [i8* @a, i8* null], section "llvm.metadata" + +; CHECK: invalid llvm.used member +; CHECK-NEXT: i8* null diff --git a/test/Verifier/llvm.used-invalid-type.ll b/test/Verifier/llvm.used-invalid-type.ll new file mode 100644 index 000000000000..2de5c86fce3f --- /dev/null +++ b/test/Verifier/llvm.used-invalid-type.ll @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s + +@llvm.used = appending global [1 x i32] [i32 0], section "llvm.metadata" + +; CHECK: wrong type for intrinsic global variable +; CHECK-NEXT: [1 x i32]* @llvm.used diff --git a/test/Verifier/llvm.used-invalid-type2.ll b/test/Verifier/llvm.used-invalid-type2.ll new file mode 100644 index 000000000000..bff3f2d153a7 --- /dev/null +++ b/test/Verifier/llvm.used-invalid-type2.ll @@ -0,0 +1,5 @@ +; RUN: not llvm-as < %s -o /dev/null 2>&1 | FileCheck %s +@llvm.used = appending global i32 0, section "llvm.metadata" + +; CHECK: Only global arrays can have appending linkage! +; CHEKC-NEXT: i32* @llvm.used diff --git a/test/Verifier/llvm.used-ptr-type.ll b/test/Verifier/llvm.used-ptr-type.ll new file mode 100644 index 000000000000..adfb1691d34d --- /dev/null +++ b/test/Verifier/llvm.used-ptr-type.ll @@ -0,0 +1,4 @@ +; RUN: llvm-as < %s -o /dev/null + +@a = global i32 42 +@llvm.used = appending global [1 x i32*] [i32* @a], section "llvm.metadata" diff --git a/test/lit.cfg b/test/lit.cfg index 0ecd8feb26a2..8272e97c3856 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -22,9 +22,18 @@ if sys.platform in ['win32']: config.environment['PATH'])) config.environment['PATH'] = path +# Choose between lit's internal shell pipeline runner and a real shell. If +# LIT_USE_INTERNAL_SHELL is in the environment, we use that as an override. +use_lit_shell = os.environ.get("LIT_USE_INTERNAL_SHELL") +if use_lit_shell: + # 0 is external, "" is default, and everything else is internal. + execute_external = (use_lit_shell == "0") +else: + # Otherwise we default to internal on Windows and external elsewhere, as + # bash on Windows is usually very slow. + execute_external = (not sys.platform in ['win32']) + # testFormat: The test format to use to interpret tests. -execute_external = (not sys.platform in ['win32'] - or lit.getBashPath() not in [None, ""]) config.test_format = lit.formats.ShTest(execute_external) # To ignore test output on stderr so it doesn't trigger failures uncomment this: @@ -47,17 +56,8 @@ llvm_obj_root = getattr(config, 'llvm_obj_root', None) if llvm_obj_root is not None: config.test_exec_root = os.path.join(llvm_obj_root, 'test') -# Tweak the PATH to include the scripts dir, the tools dir, and the llvm-gcc bin -# dir (if available). +# Tweak the PATH to include the tools dir. if llvm_obj_root is not None: - llvm_src_root = getattr(config, 'llvm_src_root', None) - if not llvm_src_root: - lit.fatal('No LLVM source root set!') - path = os.path.pathsep.join((os.path.join(llvm_src_root, 'test', - 'Scripts'), - config.environment['PATH'])) - config.environment['PATH'] = path - llvm_tools_dir = getattr(config, 'llvm_tools_dir', None) if not llvm_tools_dir: lit.fatal('No LLVM tools dir set!') @@ -160,7 +160,9 @@ config.substitutions.append( ('%lli_mcjit', lli_mcjit) ) # but simply want use the currently considered most reliable jit for platform # FIXME: ppc32 is not ready for mcjit. if 'arm' in config.target_triple \ - or 'powerpc64' in config.target_triple: + or 'aarch64' in config.target_triple \ + or 'powerpc64' in config.target_triple \ + or 's390x' in config.target_triple: defaultIsMCJIT = 'true' else: defaultIsMCJIT = 'false' @@ -240,7 +242,7 @@ for pattern in [r"\bbugpoint\b(?!-)", r"(?<!/|-)\bclang\b(?!-)", ### Features # Shell execution -if sys.platform not in ['win32'] or lit.getBashPath() != '': +if execute_external: config.available_features.add('shell') # Loadable module @@ -264,6 +266,13 @@ if (config.llvm_use_sanitizer == "Memory" or config.llvm_use_sanitizer == "MemoryWithOrigins"): config.available_features.add("msan") +# Direct object generation +if not 'hexagon' in config.target_triple: + config.available_features.add("object-emission") + +if config.have_zlib == "1": + config.available_features.add("zlib") + # llc knows whether he is compiled with -DNDEBUG. import subprocess try: diff --git a/test/lit.site.cfg.in b/test/lit.site.cfg.in index 8024b24fcde7..1ae99eb02496 100644 --- a/test/lit.site.cfg.in +++ b/test/lit.site.cfg.in @@ -1,6 +1,6 @@ ## Autogenerated by LLVM/Clang configuration. # Do not edit! -config.host_triple = "@LLVM_HOSTTRIPLE@" +config.host_triple = "@LLVM_HOST_TRIPLE@" config.target_triple = "@TARGET_TRIPLE@" config.llvm_src_root = "@LLVM_SOURCE_DIR@" config.llvm_obj_root = "@LLVM_BINARY_DIR@" @@ -19,6 +19,7 @@ config.host_os = "@HOST_OS@" config.host_arch = "@HOST_ARCH@" config.llvm_use_intel_jitevents = "@LLVM_USE_INTEL_JITEVENTS@" config.llvm_use_sanitizer = "@LLVM_USE_SANITIZER@" +config.have_zlib = "@HAVE_LIBZ@" # Support substitution of the tools_dir with user parameters. This is # used when we can't determine the tool dir at configuration time. diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.coff-i386 b/test/tools/llvm-readobj/Inputs/relocs.obj.coff-i386 Binary files differnew file mode 100644 index 000000000000..15e43ef54fef --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.coff-i386 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.coff-x86_64 b/test/tools/llvm-readobj/Inputs/relocs.obj.coff-x86_64 Binary files differnew file mode 100644 index 000000000000..cd63173b0e3a --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.coff-x86_64 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64 b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64 Binary files differnew file mode 100644 index 000000000000..d39e60c8eec3 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-aarch64 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-arm b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-arm Binary files differnew file mode 100644 index 000000000000..908507d20ab9 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-arm diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-i386 b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-i386 Binary files differnew file mode 100644 index 000000000000..7860df6de763 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-i386 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips Binary files differnew file mode 100644 index 000000000000..e387942b450b --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips64el b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips64el Binary files differnew file mode 100644 index 000000000000..a9779645c312 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-mips64el diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-ppc64 b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-ppc64 Binary files differnew file mode 100644 index 000000000000..c46e4c04285b --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-ppc64 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.elf-x86_64 b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-x86_64 Binary files differnew file mode 100644 index 000000000000..3ca9d8c6939f --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.elf-x86_64 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.macho-arm b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-arm Binary files differnew file mode 100644 index 000000000000..992ae17ffb15 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-arm diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.macho-i386 b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-i386 Binary files differnew file mode 100644 index 000000000000..5305fe8663a2 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-i386 diff --git a/test/tools/llvm-readobj/Inputs/relocs.obj.macho-x86_64 b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-x86_64 Binary files differnew file mode 100644 index 000000000000..42b80dd9d2f0 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.obj.macho-x86_64 diff --git a/test/tools/llvm-readobj/Inputs/relocs.py b/test/tools/llvm-readobj/Inputs/relocs.py new file mode 100644 index 000000000000..232d080d7d78 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/relocs.py @@ -0,0 +1,1086 @@ +#!/usr/bin/env python + +# Generates ELF, COFF and MachO object files for different architectures +# containing all relocations: +# +# ELF: i386, x86_64, ppc64, aarch64, arm, mips, mips64el +# COFF: i386, x86_64 +# MachO: i386, x86_64, arm +# (see end of file for triples) +# +# To simplify generation, object files are generated with just the proper +# number of relocations through repeated instructions. Afterwards, the +# relocations in the object file are patched to their proper value. + +import operator +import shutil +import StringIO +import struct +import subprocess +import sys + +class EnumType(type): + def __init__(self, name, bases = (), attributes = {}): + super(EnumType, self).__init__(name, bases, attributes) + + type.__setattr__(self, '_map', {}) + type.__setattr__(self, '_nameMap', {}) + + for symbol in attributes: + if symbol.startswith('__') or symbol.endswith('__'): + continue + + value = attributes[symbol] + + # MyEnum.symbol == value + type.__setattr__(self, symbol, value) + self._nameMap[symbol] = value + + # The first symbol with the given value is authoritative. + if not (value in self._map): + # MyEnum[value] == symbol + self._map[value] = symbol + + # Not supported (Enums are immutable). + def __setattr__(self, name, value): + raise NotSupportedException, self.__setattr__ + + # Not supported (Enums are immutable). + def __delattr__(self, name): + raise NotSupportedException, self.__delattr__ + + # Gets the enum symbol for the specified value. + def __getitem__(self, value): + symbol = self._map.get(value) + if symbol is None: + raise KeyError, value + return symbol + + # Gets the enum symbol for the specified value or none. + def lookup(self, value): + symbol = self._map.get(value) + return symbol + + # Not supported (Enums are immutable). + def __setitem__(self, value, symbol): + raise NotSupportedException, self.__setitem__ + + # Not supported (Enums are immutable). + def __delitem__(self, value): + raise NotSupportedException, self.__delitem__ + + def entries(self): + # sort by (value, name) + def makeKey(item): + return (item[1], item[0]) + e = [] + for pair in sorted(self._nameMap.iteritems(), key=makeKey): + e.append(pair) + return e + + def __iter__(self): + for e in self.entries(): + yield e + +Enum = EnumType('Enum', (), {}) + +class BinaryReader: + def __init__(self, path): + self.file = open(path, "r+b", 0) + self.isLSB = None + self.is64Bit = None + self.isN64 = False + + def tell(self): + return self.file.tell() + + def seek(self, pos): + self.file.seek(pos) + + def read(self, N): + data = self.file.read(N) + if len(data) != N: + raise ValueError, "Out of data!" + return data + + def int8(self): + return ord(self.read(1)) + + def uint8(self): + return ord(self.read(1)) + + def int16(self): + return struct.unpack('><'[self.isLSB] + 'h', self.read(2))[0] + + def uint16(self): + return struct.unpack('><'[self.isLSB] + 'H', self.read(2))[0] + + def int32(self): + return struct.unpack('><'[self.isLSB] + 'i', self.read(4))[0] + + def uint32(self): + return struct.unpack('><'[self.isLSB] + 'I', self.read(4))[0] + + def int64(self): + return struct.unpack('><'[self.isLSB] + 'q', self.read(8))[0] + + def uint64(self): + return struct.unpack('><'[self.isLSB] + 'Q', self.read(8))[0] + + def writeUInt8(self, value): + self.file.write(struct.pack('><'[self.isLSB] + 'B', value)) + + def writeUInt16(self, value): + self.file.write(struct.pack('><'[self.isLSB] + 'H', value)) + + def writeUInt32(self, value): + self.file.write(struct.pack('><'[self.isLSB] + 'I', value)) + + def writeUInt64(self, value): + self.file.write(struct.pack('><'[self.isLSB] + 'Q', value)) + + def word(self): + if self.is64Bit: + return self.uint64() + else: + return self.uint32() + + def writeWord(self, value): + if self.is64Bit: + self.writeUInt64(value) + else: + self.writeUInt32(value) + +class StringTable: + def __init__(self, strings): + self.string_table = strings + + def __getitem__(self, index): + end = self.string_table.index('\x00', index) + return self.string_table[index:end] + +class ElfSection: + def __init__(self, f): + self.sh_name = f.uint32() + self.sh_type = f.uint32() + self.sh_flags = f.word() + self.sh_addr = f.word() + self.sh_offset = f.word() + self.sh_size = f.word() + self.sh_link = f.uint32() + self.sh_info = f.uint32() + self.sh_addralign = f.word() + self.sh_entsize = f.word() + + def patch(self, f, relocs): + if self.sh_type == 4 or self.sh_type == 9: # SHT_RELA / SHT_REL + self.patchRelocs(f, relocs) + + def patchRelocs(self, f, relocs): + entries = self.sh_size // self.sh_entsize + + for index in range(entries): + f.seek(self.sh_offset + index * self.sh_entsize) + r_offset = f.word() + + if index < len(relocs): + ri = index + else: + ri = 0 + + if f.isN64: + r_sym = f.uint32() + r_ssym = f.uint8() + f.seek(f.tell()) + f.writeUInt8(relocs[ri][1]) + f.writeUInt8(relocs[ri][1]) + f.writeUInt8(relocs[ri][1]) + else: + pos = f.tell() + r_info = f.word() + + r_type = relocs[ri][1] + if f.is64Bit: + r_info = (r_info & 0xFFFFFFFF00000000) | (r_type & 0xFFFFFFFF) + else: + r_info = (r_info & 0xFF00) | (r_type & 0xFF) + + print(" %s" % relocs[ri][0]) + f.seek(pos) + f.writeWord(r_info) + + +class CoffSection: + def __init__(self, f): + self.raw_name = f.read(8) + self.virtual_size = f.uint32() + self.virtual_address = f.uint32() + self.raw_data_size = f.uint32() + self.pointer_to_raw_data = f.uint32() + self.pointer_to_relocations = f.uint32() + self.pointer_to_line_numbers = f.uint32() + self.relocation_count = f.uint16() + self.line_number_count = f.uint16() + self.characteristics = f.uint32() + + +def compileAsm(filename, triple, src): + cmd = ["llvm-mc", "-triple=" + triple, "-filetype=obj", "-o", filename] + print(" Running: " + " ".join(cmd)) + p = subprocess.Popen(cmd, stdin=subprocess.PIPE) + p.communicate(input=src) + p.wait() + +def compileIR(filename, triple, src): + cmd = ["llc", "-mtriple=" + triple, "-filetype=obj", "-o", filename] + print(" Running: " + " ".join(cmd)) + p = subprocess.Popen(cmd, stdin=subprocess.PIPE) + p.communicate(input=src) + p.wait() + + +def craftElf(filename, triple, relocs, dummyReloc): + print("Crafting " + filename + " for " + triple) + if type(dummyReloc) is tuple: + preSrc, dummyReloc, relocsPerDummy = dummyReloc + src = preSrc + "\n" + for i in range((len(relocs) + relocsPerDummy - 1) / relocsPerDummy): + src += dummyReloc.format(i) + "\n" + compileIR(filename, triple, src) + else: + src = (dummyReloc + "\n") * len(relocs) + compileAsm(filename, triple, src) + + print(" Patching relocations...") + patchElf(filename, relocs) + +def patchElf(path, relocs): + f = BinaryReader(path) + + magic = f.read(4) + assert magic == '\x7FELF' + + fileclass = f.uint8() + if fileclass == 1: + f.is64Bit = False + elif fileclass == 2: + f.is64Bit = True + else: + raise ValueError, "Unknown file class %x" % fileclass + + byteordering = f.uint8() + if byteordering == 1: + f.isLSB = True + elif byteordering == 2: + f.isLSB = False + else: + raise ValueError, "Unknown byte ordering %x" % byteordering + + f.seek(18) + e_machine = f.uint16() + if e_machine == 0x0008 and f.is64Bit: # EM_MIPS && 64 bit + f.isN64 = True + + e_version = f.uint32() + e_entry = f.word() + e_phoff = f.word() + e_shoff = f.word() + e_flags = f.uint32() + e_ehsize = f.uint16() + e_phentsize = f.uint16() + e_phnum = f.uint16() + e_shentsize = f.uint16() + e_shnum = f.uint16() + e_shstrndx = f.uint16() + + sections = [] + for index in range(e_shnum): + f.seek(e_shoff + index * e_shentsize) + s = ElfSection(f) + sections.append(s) + + f.seek(sections[e_shstrndx].sh_offset) + shstrtab = StringTable(f.read(sections[e_shstrndx].sh_size)) + + strtab = None + for section in sections: + if shstrtab[section.sh_name] == ".strtab": + f.seek(section.sh_offset) + strtab = StringTable(f.read(section.sh_size)) + break + + for index in range(e_shnum): + sections[index].patch(f, relocs) + + +def craftCoff(filename, triple, relocs, dummyReloc): + print("Crafting " + filename + " for " + triple) + src = (dummyReloc + "\n") * len(relocs) + compileAsm(filename, triple, src) + + print(" Patching relocations...") + patchCoff(filename, relocs) + +def patchCoff(path, relocs): + f = BinaryReader(path) + f.isLSB = True + + machine_type = f.uint16() + section_count = f.uint16() + f.seek(20) + sections = [CoffSection(f) for idx in range(section_count)] + + section = sections[0] + f.seek(section.pointer_to_relocations) + for i in range(section.relocation_count): + virtual_addr = f.uint32() + symtab_idx = f.uint32() + print(" %s" % relocs[i][0]) + f.writeUInt16(relocs[i][1]) + + +def craftMacho(filename, triple, relocs, dummyReloc): + print("Crafting " + filename + " for " + triple) + + if type(dummyReloc) is tuple: + srcType, preSrc, dummyReloc, relocsPerDummy = dummyReloc + src = preSrc + "\n" + for i in range((len(relocs) + relocsPerDummy - 1) / relocsPerDummy): + src += dummyReloc.format(i) + "\n" + if srcType == "asm": + compileAsm(filename, triple, src) + elif srcType == "ir": + compileIR(filename, triple, src) + else: + src = (dummyReloc + "\n") * len(relocs) + compileAsm(filename, triple, src) + + print(" Patching relocations...") + patchMacho(filename, relocs) + +def patchMacho(filename, relocs): + f = BinaryReader(filename) + + magic = f.read(4) + if magic == '\xFE\xED\xFA\xCE': + f.isLSB, f.is64Bit = False, False + elif magic == '\xCE\xFA\xED\xFE': + f.isLSB, f.is64Bit = True, False + elif magic == '\xFE\xED\xFA\xCF': + f.isLSB, f.is64Bit = False, True + elif magic == '\xCF\xFA\xED\xFE': + f.isLSB, f.is64Bit = True, True + else: + raise ValueError,"Not a Mach-O object file: %r (bad magic)" % path + + cputype = f.uint32() + cpusubtype = f.uint32() + filetype = f.uint32() + numLoadCommands = f.uint32() + loadCommandsSize = f.uint32() + flag = f.uint32() + if f.is64Bit: + reserved = f.uint32() + + start = f.tell() + + for i in range(numLoadCommands): + patchMachoLoadCommand(f, relocs) + + if f.tell() - start != loadCommandsSize: + raise ValueError,"%s: warning: invalid load commands size: %r" % ( + sys.argv[0], loadCommandsSize) + +def patchMachoLoadCommand(f, relocs): + start = f.tell() + cmd = f.uint32() + cmdSize = f.uint32() + + if cmd == 1: + patchMachoSegmentLoadCommand(f, relocs) + elif cmd == 25: + patchMachoSegmentLoadCommand(f, relocs) + else: + f.read(cmdSize - 8) + + if f.tell() - start != cmdSize: + raise ValueError,"%s: warning: invalid load command size: %r" % ( + sys.argv[0], cmdSize) + +def patchMachoSegmentLoadCommand(f, relocs): + segment_name = f.read(16) + vm_addr = f.word() + vm_size = f.word() + file_offset = f.word() + file_size = f.word() + maxprot = f.uint32() + initprot = f.uint32() + numSections = f.uint32() + flags = f.uint32() + for i in range(numSections): + patchMachoSection(f, relocs) + +def patchMachoSection(f, relocs): + section_name = f.read(16) + segment_name = f.read(16) + address = f.word() + size = f.word() + offset = f.uint32() + alignment = f.uint32() + relocOffset = f.uint32() + numReloc = f.uint32() + flags = f.uint32() + reserved1 = f.uint32() + reserved2 = f.uint32() + if f.is64Bit: + reserved3 = f.uint32() + + prev_pos = f.tell() + + f.seek(relocOffset) + for i in range(numReloc): + ri = i < len(relocs) and i or 0 + print(" %s" % relocs[ri][0]) + word1 = f.uint32() + pos = f.tell() + value = f.uint32() + f.seek(pos) + value = (value & 0x0FFFFFFF) | ((relocs[ri][1] & 0xF) << 28) + f.writeUInt32(value) + f.seek(prev_pos) + + +class Relocs_Elf_X86_64(Enum): + R_X86_64_NONE = 0 + R_X86_64_64 = 1 + R_X86_64_PC32 = 2 + R_X86_64_GOT32 = 3 + R_X86_64_PLT32 = 4 + R_X86_64_COPY = 5 + R_X86_64_GLOB_DAT = 6 + R_X86_64_JUMP_SLOT = 7 + R_X86_64_RELATIVE = 8 + R_X86_64_GOTPCREL = 9 + R_X86_64_32 = 10 + R_X86_64_32S = 11 + R_X86_64_16 = 12 + R_X86_64_PC16 = 13 + R_X86_64_8 = 14 + R_X86_64_PC8 = 15 + R_X86_64_DTPMOD64 = 16 + R_X86_64_DTPOFF64 = 17 + R_X86_64_TPOFF64 = 18 + R_X86_64_TLSGD = 19 + R_X86_64_TLSLD = 20 + R_X86_64_DTPOFF32 = 21 + R_X86_64_GOTTPOFF = 22 + R_X86_64_TPOFF32 = 23 + R_X86_64_PC64 = 24 + R_X86_64_GOTOFF64 = 25 + R_X86_64_GOTPC32 = 26 + R_X86_64_GOT64 = 27 + R_X86_64_GOTPCREL64 = 28 + R_X86_64_GOTPC64 = 29 + R_X86_64_GOTPLT64 = 30 + R_X86_64_PLTOFF64 = 31 + R_X86_64_SIZE32 = 32 + R_X86_64_SIZE64 = 33 + R_X86_64_GOTPC32_TLSDESC = 34 + R_X86_64_TLSDESC_CALL = 35 + R_X86_64_TLSDESC = 36 + R_X86_64_IRELATIVE = 37 + +class Relocs_Elf_i386(Enum): + R_386_NONE = 0 + R_386_32 = 1 + R_386_PC32 = 2 + R_386_GOT32 = 3 + R_386_PLT32 = 4 + R_386_COPY = 5 + R_386_GLOB_DAT = 6 + R_386_JUMP_SLOT = 7 + R_386_RELATIVE = 8 + R_386_GOTOFF = 9 + R_386_GOTPC = 10 + R_386_32PLT = 11 + R_386_TLS_TPOFF = 14 + R_386_TLS_IE = 15 + R_386_TLS_GOTIE = 16 + R_386_TLS_LE = 17 + R_386_TLS_GD = 18 + R_386_TLS_LDM = 19 + R_386_16 = 20 + R_386_PC16 = 21 + R_386_8 = 22 + R_386_PC8 = 23 + R_386_TLS_GD_32 = 24 + R_386_TLS_GD_PUSH = 25 + R_386_TLS_GD_CALL = 26 + R_386_TLS_GD_POP = 27 + R_386_TLS_LDM_32 = 28 + R_386_TLS_LDM_PUSH = 29 + R_386_TLS_LDM_CALL = 30 + R_386_TLS_LDM_POP = 31 + R_386_TLS_LDO_32 = 32 + R_386_TLS_IE_32 = 33 + R_386_TLS_LE_32 = 34 + R_386_TLS_DTPMOD32 = 35 + R_386_TLS_DTPOFF32 = 36 + R_386_TLS_TPOFF32 = 37 + R_386_TLS_GOTDESC = 39 + R_386_TLS_DESC_CALL = 40 + R_386_TLS_DESC = 41 + R_386_IRELATIVE = 42 + R_386_NUM = 43 + +class Relocs_Elf_MBlaze(Enum): + R_MICROBLAZE_NONE = 0 + R_MICROBLAZE_32 = 1 + R_MICROBLAZE_32_PCREL = 2 + R_MICROBLAZE_64_PCREL = 3 + R_MICROBLAZE_32_PCREL_LO = 4 + R_MICROBLAZE_64 = 5 + R_MICROBLAZE_32_LO = 6 + R_MICROBLAZE_SRO32 = 7 + R_MICROBLAZE_SRW32 = 8 + R_MICROBLAZE_64_NONE = 9 + R_MICROBLAZE_32_SYM_OP_SYM = 10 + R_MICROBLAZE_GNU_VTINHERIT = 11 + R_MICROBLAZE_GNU_VTENTRY = 12 + R_MICROBLAZE_GOTPC_64 = 13 + R_MICROBLAZE_GOT_64 = 14 + R_MICROBLAZE_PLT_64 = 15 + R_MICROBLAZE_REL = 16 + R_MICROBLAZE_JUMP_SLOT = 17 + R_MICROBLAZE_GLOB_DAT = 18 + R_MICROBLAZE_GOTOFF_64 = 19 + R_MICROBLAZE_GOTOFF_32 = 20 + R_MICROBLAZE_COPY = 21 + +class Relocs_Elf_PPC32(Enum): + R_PPC_NONE = 0 + R_PPC_ADDR32 = 1 + R_PPC_ADDR24 = 2 + R_PPC_ADDR16 = 3 + R_PPC_ADDR16_LO = 4 + R_PPC_ADDR16_HI = 5 + R_PPC_ADDR16_HA = 6 + R_PPC_ADDR14 = 7 + R_PPC_ADDR14_BRTAKEN = 8 + R_PPC_ADDR14_BRNTAKEN = 9 + R_PPC_REL24 = 10 + R_PPC_REL14 = 11 + R_PPC_REL14_BRTAKEN = 12 + R_PPC_REL14_BRNTAKEN = 13 + R_PPC_REL32 = 26 + R_PPC_TPREL16_LO = 70 + R_PPC_TPREL16_HA = 72 + +class Relocs_Elf_PPC64(Enum): + R_PPC64_NONE = 0 + R_PPC64_ADDR32 = 1 + R_PPC64_ADDR16_LO = 4 + R_PPC64_ADDR16_HI = 5 + R_PPC64_ADDR14 = 7 + R_PPC64_REL24 = 10 + R_PPC64_REL32 = 26 + R_PPC64_ADDR64 = 38 + R_PPC64_ADDR16_HIGHER = 39 + R_PPC64_ADDR16_HIGHEST = 41 + R_PPC64_REL64 = 44 + R_PPC64_TOC16 = 47 + R_PPC64_TOC16_LO = 48 + R_PPC64_TOC16_HA = 50 + R_PPC64_TOC = 51 + R_PPC64_ADDR16_DS = 56 + R_PPC64_ADDR16_LO_DS = 57 + R_PPC64_TOC16_DS = 63 + R_PPC64_TOC16_LO_DS = 64 + R_PPC64_TLS = 67 + R_PPC64_TPREL16_LO = 70 + R_PPC64_TPREL16_HA = 72 + R_PPC64_DTPREL16_LO = 75 + R_PPC64_DTPREL16_HA = 77 + R_PPC64_GOT_TLSGD16_LO = 80 + R_PPC64_GOT_TLSGD16_HA = 82 + R_PPC64_GOT_TLSLD16_LO = 84 + R_PPC64_GOT_TLSLD16_HA = 86 + R_PPC64_GOT_TPREL16_LO_DS = 88 + R_PPC64_GOT_TPREL16_HA = 90 + R_PPC64_TLSGD = 107 + R_PPC64_TLSLD = 108 + +class Relocs_Elf_AArch64(Enum): + R_AARCH64_NONE = 0x100 + R_AARCH64_ABS64 = 0x101 + R_AARCH64_ABS32 = 0x102 + R_AARCH64_ABS16 = 0x103 + R_AARCH64_PREL64 = 0x104 + R_AARCH64_PREL32 = 0x105 + R_AARCH64_PREL16 = 0x106 + R_AARCH64_MOVW_UABS_G0 = 0x107 + R_AARCH64_MOVW_UABS_G0_NC = 0x108 + R_AARCH64_MOVW_UABS_G1 = 0x109 + R_AARCH64_MOVW_UABS_G1_NC = 0x10a + R_AARCH64_MOVW_UABS_G2 = 0x10b + R_AARCH64_MOVW_UABS_G2_NC = 0x10c + R_AARCH64_MOVW_UABS_G3 = 0x10d + R_AARCH64_MOVW_SABS_G0 = 0x10e + R_AARCH64_MOVW_SABS_G1 = 0x10f + R_AARCH64_MOVW_SABS_G2 = 0x110 + R_AARCH64_LD_PREL_LO19 = 0x111 + R_AARCH64_ADR_PREL_LO21 = 0x112 + R_AARCH64_ADR_PREL_PG_HI21 = 0x113 + R_AARCH64_ADD_ABS_LO12_NC = 0x115 + R_AARCH64_LDST8_ABS_LO12_NC = 0x116 + R_AARCH64_TSTBR14 = 0x117 + R_AARCH64_CONDBR19 = 0x118 + R_AARCH64_JUMP26 = 0x11a + R_AARCH64_CALL26 = 0x11b + R_AARCH64_LDST16_ABS_LO12_NC = 0x11c + R_AARCH64_LDST32_ABS_LO12_NC = 0x11d + R_AARCH64_LDST64_ABS_LO12_NC = 0x11e + R_AARCH64_LDST128_ABS_LO12_NC = 0x12b + R_AARCH64_ADR_GOT_PAGE = 0x137 + R_AARCH64_LD64_GOT_LO12_NC = 0x138 + R_AARCH64_TLSLD_MOVW_DTPREL_G2 = 0x20b + R_AARCH64_TLSLD_MOVW_DTPREL_G1 = 0x20c + R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC = 0x20d + R_AARCH64_TLSLD_MOVW_DTPREL_G0 = 0x20e + R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC = 0x20f + R_AARCH64_TLSLD_ADD_DTPREL_HI12 = 0x210 + R_AARCH64_TLSLD_ADD_DTPREL_LO12 = 0x211 + R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC = 0x212 + R_AARCH64_TLSLD_LDST8_DTPREL_LO12 = 0x213 + R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC = 0x214 + R_AARCH64_TLSLD_LDST16_DTPREL_LO12 = 0x215 + R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC = 0x216 + R_AARCH64_TLSLD_LDST32_DTPREL_LO12 = 0x217 + R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC = 0x218 + R_AARCH64_TLSLD_LDST64_DTPREL_LO12 = 0x219 + R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC = 0x21a + R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 = 0x21b + R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC = 0x21c + R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 = 0x21d + R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC = 0x21e + R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 = 0x21f + R_AARCH64_TLSLE_MOVW_TPREL_G2 = 0x220 + R_AARCH64_TLSLE_MOVW_TPREL_G1 = 0x221 + R_AARCH64_TLSLE_MOVW_TPREL_G1_NC = 0x222 + R_AARCH64_TLSLE_MOVW_TPREL_G0 = 0x223 + R_AARCH64_TLSLE_MOVW_TPREL_G0_NC = 0x224 + R_AARCH64_TLSLE_ADD_TPREL_HI12 = 0x225 + R_AARCH64_TLSLE_ADD_TPREL_LO12 = 0x226 + R_AARCH64_TLSLE_ADD_TPREL_LO12_NC = 0x227 + R_AARCH64_TLSLE_LDST8_TPREL_LO12 = 0x228 + R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC = 0x229 + R_AARCH64_TLSLE_LDST16_TPREL_LO12 = 0x22a + R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC = 0x22b + R_AARCH64_TLSLE_LDST32_TPREL_LO12 = 0x22c + R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC = 0x22d + R_AARCH64_TLSLE_LDST64_TPREL_LO12 = 0x22e + R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC = 0x22f + R_AARCH64_TLSDESC_ADR_PAGE = 0x232 + R_AARCH64_TLSDESC_LD64_LO12_NC = 0x233 + R_AARCH64_TLSDESC_ADD_LO12_NC = 0x234 + R_AARCH64_TLSDESC_CALL = 0x239 + +class Relocs_Elf_ARM(Enum): + R_ARM_NONE = 0x00 + R_ARM_PC24 = 0x01 + R_ARM_ABS32 = 0x02 + R_ARM_REL32 = 0x03 + R_ARM_LDR_PC_G0 = 0x04 + R_ARM_ABS16 = 0x05 + R_ARM_ABS12 = 0x06 + R_ARM_THM_ABS5 = 0x07 + R_ARM_ABS8 = 0x08 + R_ARM_SBREL32 = 0x09 + R_ARM_THM_CALL = 0x0a + R_ARM_THM_PC8 = 0x0b + R_ARM_BREL_ADJ = 0x0c + R_ARM_TLS_DESC = 0x0d + R_ARM_THM_SWI8 = 0x0e + R_ARM_XPC25 = 0x0f + R_ARM_THM_XPC22 = 0x10 + R_ARM_TLS_DTPMOD32 = 0x11 + R_ARM_TLS_DTPOFF32 = 0x12 + R_ARM_TLS_TPOFF32 = 0x13 + R_ARM_COPY = 0x14 + R_ARM_GLOB_DAT = 0x15 + R_ARM_JUMP_SLOT = 0x16 + R_ARM_RELATIVE = 0x17 + R_ARM_GOTOFF32 = 0x18 + R_ARM_BASE_PREL = 0x19 + R_ARM_GOT_BREL = 0x1a + R_ARM_PLT32 = 0x1b + R_ARM_CALL = 0x1c + R_ARM_JUMP24 = 0x1d + R_ARM_THM_JUMP24 = 0x1e + R_ARM_BASE_ABS = 0x1f + R_ARM_ALU_PCREL_7_0 = 0x20 + R_ARM_ALU_PCREL_15_8 = 0x21 + R_ARM_ALU_PCREL_23_15 = 0x22 + R_ARM_LDR_SBREL_11_0_NC = 0x23 + R_ARM_ALU_SBREL_19_12_NC = 0x24 + R_ARM_ALU_SBREL_27_20_CK = 0x25 + R_ARM_TARGET1 = 0x26 + R_ARM_SBREL31 = 0x27 + R_ARM_V4BX = 0x28 + R_ARM_TARGET2 = 0x29 + R_ARM_PREL31 = 0x2a + R_ARM_MOVW_ABS_NC = 0x2b + R_ARM_MOVT_ABS = 0x2c + R_ARM_MOVW_PREL_NC = 0x2d + R_ARM_MOVT_PREL = 0x2e + R_ARM_THM_MOVW_ABS_NC = 0x2f + R_ARM_THM_MOVT_ABS = 0x30 + R_ARM_THM_MOVW_PREL_NC = 0x31 + R_ARM_THM_MOVT_PREL = 0x32 + R_ARM_THM_JUMP19 = 0x33 + R_ARM_THM_JUMP6 = 0x34 + R_ARM_THM_ALU_PREL_11_0 = 0x35 + R_ARM_THM_PC12 = 0x36 + R_ARM_ABS32_NOI = 0x37 + R_ARM_REL32_NOI = 0x38 + R_ARM_ALU_PC_G0_NC = 0x39 + R_ARM_ALU_PC_G0 = 0x3a + R_ARM_ALU_PC_G1_NC = 0x3b + R_ARM_ALU_PC_G1 = 0x3c + R_ARM_ALU_PC_G2 = 0x3d + R_ARM_LDR_PC_G1 = 0x3e + R_ARM_LDR_PC_G2 = 0x3f + R_ARM_LDRS_PC_G0 = 0x40 + R_ARM_LDRS_PC_G1 = 0x41 + R_ARM_LDRS_PC_G2 = 0x42 + R_ARM_LDC_PC_G0 = 0x43 + R_ARM_LDC_PC_G1 = 0x44 + R_ARM_LDC_PC_G2 = 0x45 + R_ARM_ALU_SB_G0_NC = 0x46 + R_ARM_ALU_SB_G0 = 0x47 + R_ARM_ALU_SB_G1_NC = 0x48 + R_ARM_ALU_SB_G1 = 0x49 + R_ARM_ALU_SB_G2 = 0x4a + R_ARM_LDR_SB_G0 = 0x4b + R_ARM_LDR_SB_G1 = 0x4c + R_ARM_LDR_SB_G2 = 0x4d + R_ARM_LDRS_SB_G0 = 0x4e + R_ARM_LDRS_SB_G1 = 0x4f + R_ARM_LDRS_SB_G2 = 0x50 + R_ARM_LDC_SB_G0 = 0x51 + R_ARM_LDC_SB_G1 = 0x52 + R_ARM_LDC_SB_G2 = 0x53 + R_ARM_MOVW_BREL_NC = 0x54 + R_ARM_MOVT_BREL = 0x55 + R_ARM_MOVW_BREL = 0x56 + R_ARM_THM_MOVW_BREL_NC = 0x57 + R_ARM_THM_MOVT_BREL = 0x58 + R_ARM_THM_MOVW_BREL = 0x59 + R_ARM_TLS_GOTDESC = 0x5a + R_ARM_TLS_CALL = 0x5b + R_ARM_TLS_DESCSEQ = 0x5c + R_ARM_THM_TLS_CALL = 0x5d + R_ARM_PLT32_ABS = 0x5e + R_ARM_GOT_ABS = 0x5f + R_ARM_GOT_PREL = 0x60 + R_ARM_GOT_BREL12 = 0x61 + R_ARM_GOTOFF12 = 0x62 + R_ARM_GOTRELAX = 0x63 + R_ARM_GNU_VTENTRY = 0x64 + R_ARM_GNU_VTINHERIT = 0x65 + R_ARM_THM_JUMP11 = 0x66 + R_ARM_THM_JUMP8 = 0x67 + R_ARM_TLS_GD32 = 0x68 + R_ARM_TLS_LDM32 = 0x69 + R_ARM_TLS_LDO32 = 0x6a + R_ARM_TLS_IE32 = 0x6b + R_ARM_TLS_LE32 = 0x6c + R_ARM_TLS_LDO12 = 0x6d + R_ARM_TLS_LE12 = 0x6e + R_ARM_TLS_IE12GP = 0x6f + R_ARM_PRIVATE_0 = 0x70 + R_ARM_PRIVATE_1 = 0x71 + R_ARM_PRIVATE_2 = 0x72 + R_ARM_PRIVATE_3 = 0x73 + R_ARM_PRIVATE_4 = 0x74 + R_ARM_PRIVATE_5 = 0x75 + R_ARM_PRIVATE_6 = 0x76 + R_ARM_PRIVATE_7 = 0x77 + R_ARM_PRIVATE_8 = 0x78 + R_ARM_PRIVATE_9 = 0x79 + R_ARM_PRIVATE_10 = 0x7a + R_ARM_PRIVATE_11 = 0x7b + R_ARM_PRIVATE_12 = 0x7c + R_ARM_PRIVATE_13 = 0x7d + R_ARM_PRIVATE_14 = 0x7e + R_ARM_PRIVATE_15 = 0x7f + R_ARM_ME_TOO = 0x80 + R_ARM_THM_TLS_DESCSEQ16 = 0x81 + R_ARM_THM_TLS_DESCSEQ32 = 0x82 + +class Relocs_Elf_Mips(Enum): + R_MIPS_NONE = 0 + R_MIPS_16 = 1 + R_MIPS_32 = 2 + R_MIPS_REL32 = 3 + R_MIPS_26 = 4 + R_MIPS_HI16 = 5 + R_MIPS_LO16 = 6 + R_MIPS_GPREL16 = 7 + R_MIPS_LITERAL = 8 + R_MIPS_GOT16 = 9 + R_MIPS_PC16 = 10 + R_MIPS_CALL16 = 11 + R_MIPS_GPREL32 = 12 + R_MIPS_SHIFT5 = 16 + R_MIPS_SHIFT6 = 17 + R_MIPS_64 = 18 + R_MIPS_GOT_DISP = 19 + R_MIPS_GOT_PAGE = 20 + R_MIPS_GOT_OFST = 21 + R_MIPS_GOT_HI16 = 22 + R_MIPS_GOT_LO16 = 23 + R_MIPS_SUB = 24 + R_MIPS_INSERT_A = 25 + R_MIPS_INSERT_B = 26 + R_MIPS_DELETE = 27 + R_MIPS_HIGHER = 28 + R_MIPS_HIGHEST = 29 + R_MIPS_CALL_HI16 = 30 + R_MIPS_CALL_LO16 = 31 + R_MIPS_SCN_DISP = 32 + R_MIPS_REL16 = 33 + R_MIPS_ADD_IMMEDIATE = 34 + R_MIPS_PJUMP = 35 + R_MIPS_RELGOT = 36 + R_MIPS_JALR = 37 + R_MIPS_TLS_DTPMOD32 = 38 + R_MIPS_TLS_DTPREL32 = 39 + R_MIPS_TLS_DTPMOD64 = 40 + R_MIPS_TLS_DTPREL64 = 41 + R_MIPS_TLS_GD = 42 + R_MIPS_TLS_LDM = 43 + R_MIPS_TLS_DTPREL_HI16 = 44 + R_MIPS_TLS_DTPREL_LO16 = 45 + R_MIPS_TLS_GOTTPREL = 46 + R_MIPS_TLS_TPREL32 = 47 + R_MIPS_TLS_TPREL64 = 48 + R_MIPS_TLS_TPREL_HI16 = 49 + R_MIPS_TLS_TPREL_LO16 = 50 + R_MIPS_GLOB_DAT = 51 + R_MIPS_COPY = 126 + R_MIPS_JUMP_SLOT = 127 + R_MIPS_NUM = 218 + +class Relocs_Elf_Hexagon(Enum): + R_HEX_NONE = 0 + R_HEX_B22_PCREL = 1 + R_HEX_B15_PCREL = 2 + R_HEX_B7_PCREL = 3 + R_HEX_LO16 = 4 + R_HEX_HI16 = 5 + R_HEX_32 = 6 + R_HEX_16 = 7 + R_HEX_8 = 8 + R_HEX_GPREL16_0 = 9 + R_HEX_GPREL16_1 = 10 + R_HEX_GPREL16_2 = 11 + R_HEX_GPREL16_3 = 12 + R_HEX_HL16 = 13 + R_HEX_B13_PCREL = 14 + R_HEX_B9_PCREL = 15 + R_HEX_B32_PCREL_X = 16 + R_HEX_32_6_X = 17 + R_HEX_B22_PCREL_X = 18 + R_HEX_B15_PCREL_X = 19 + R_HEX_B13_PCREL_X = 20 + R_HEX_B9_PCREL_X = 21 + R_HEX_B7_PCREL_X = 22 + R_HEX_16_X = 23 + R_HEX_12_X = 24 + R_HEX_11_X = 25 + R_HEX_10_X = 26 + R_HEX_9_X = 27 + R_HEX_8_X = 28 + R_HEX_7_X = 29 + R_HEX_6_X = 30 + R_HEX_32_PCREL = 31 + R_HEX_COPY = 32 + R_HEX_GLOB_DAT = 33 + R_HEX_JMP_SLOT = 34 + R_HEX_RELATIVE = 35 + R_HEX_PLT_B22_PCREL = 36 + R_HEX_GOTREL_LO16 = 37 + R_HEX_GOTREL_HI16 = 38 + R_HEX_GOTREL_32 = 39 + R_HEX_GOT_LO16 = 40 + R_HEX_GOT_HI16 = 41 + R_HEX_GOT_32 = 42 + R_HEX_GOT_16 = 43 + R_HEX_DTPMOD_32 = 44 + R_HEX_DTPREL_LO16 = 45 + R_HEX_DTPREL_HI16 = 46 + R_HEX_DTPREL_32 = 47 + R_HEX_DTPREL_16 = 48 + R_HEX_GD_PLT_B22_PCREL = 49 + R_HEX_GD_GOT_LO16 = 50 + R_HEX_GD_GOT_HI16 = 51 + R_HEX_GD_GOT_32 = 52 + R_HEX_GD_GOT_16 = 53 + R_HEX_IE_LO16 = 54 + R_HEX_IE_HI16 = 55 + R_HEX_IE_32 = 56 + R_HEX_IE_GOT_LO16 = 57 + R_HEX_IE_GOT_HI16 = 58 + R_HEX_IE_GOT_32 = 59 + R_HEX_IE_GOT_16 = 60 + R_HEX_TPREL_LO16 = 61 + R_HEX_TPREL_HI16 = 62 + R_HEX_TPREL_32 = 63 + R_HEX_TPREL_16 = 64 + R_HEX_6_PCREL_X = 65 + R_HEX_GOTREL_32_6_X = 66 + R_HEX_GOTREL_16_X = 67 + R_HEX_GOTREL_11_X = 68 + R_HEX_GOT_32_6_X = 69 + R_HEX_GOT_16_X = 70 + R_HEX_GOT_11_X = 71 + R_HEX_DTPREL_32_6_X = 72 + R_HEX_DTPREL_16_X = 73 + R_HEX_DTPREL_11_X = 74 + R_HEX_GD_GOT_32_6_X = 75 + R_HEX_GD_GOT_16_X = 76 + R_HEX_GD_GOT_11_X = 77 + R_HEX_IE_32_6_X = 78 + R_HEX_IE_16_X = 79 + R_HEX_IE_GOT_32_6_X = 80 + R_HEX_IE_GOT_16_X = 81 + R_HEX_IE_GOT_11_X = 82 + R_HEX_TPREL_32_6_X = 83 + R_HEX_TPREL_16_X = 84 + R_HEX_TPREL_11_X = 85 + + +class Relocs_Coff_i386(Enum): + IMAGE_REL_I386_ABSOLUTE = 0x0000 + IMAGE_REL_I386_DIR16 = 0x0001 + IMAGE_REL_I386_REL16 = 0x0002 + IMAGE_REL_I386_DIR32 = 0x0006 + IMAGE_REL_I386_DIR32NB = 0x0007 + IMAGE_REL_I386_SEG12 = 0x0009 + IMAGE_REL_I386_SECTION = 0x000A + IMAGE_REL_I386_SECREL = 0x000B + IMAGE_REL_I386_TOKEN = 0x000C + IMAGE_REL_I386_SECREL7 = 0x000D + IMAGE_REL_I386_REL32 = 0x0014 + +class Relocs_Coff_X86_64(Enum): + IMAGE_REL_AMD64_ABSOLUTE = 0x0000 + IMAGE_REL_AMD64_ADDR64 = 0x0001 + IMAGE_REL_AMD64_ADDR32 = 0x0002 + IMAGE_REL_AMD64_ADDR32NB = 0x0003 + IMAGE_REL_AMD64_REL32 = 0x0004 + IMAGE_REL_AMD64_REL32_1 = 0x0005 + IMAGE_REL_AMD64_REL32_2 = 0x0006 + IMAGE_REL_AMD64_REL32_3 = 0x0007 + IMAGE_REL_AMD64_REL32_4 = 0x0008 + IMAGE_REL_AMD64_REL32_5 = 0x0009 + IMAGE_REL_AMD64_SECTION = 0x000A + IMAGE_REL_AMD64_SECREL = 0x000B + IMAGE_REL_AMD64_SECREL7 = 0x000C + IMAGE_REL_AMD64_TOKEN = 0x000D + IMAGE_REL_AMD64_SREL32 = 0x000E + IMAGE_REL_AMD64_PAIR = 0x000F + IMAGE_REL_AMD64_SSPAN32 = 0x0010 + +class Relocs_Coff_ARM(Enum): + IMAGE_REL_ARM_ABSOLUTE = 0x0000 + IMAGE_REL_ARM_ADDR32 = 0x0001 + IMAGE_REL_ARM_ADDR32NB = 0x0002 + IMAGE_REL_ARM_BRANCH24 = 0x0003 + IMAGE_REL_ARM_BRANCH11 = 0x0004 + IMAGE_REL_ARM_TOKEN = 0x0005 + IMAGE_REL_ARM_BLX24 = 0x0008 + IMAGE_REL_ARM_BLX11 = 0x0009 + IMAGE_REL_ARM_SECTION = 0x000E + IMAGE_REL_ARM_SECREL = 0x000F + IMAGE_REL_ARM_MOV32A = 0x0010 + IMAGE_REL_ARM_MOV32T = 0x0011 + IMAGE_REL_ARM_BRANCH20T = 0x0012 + IMAGE_REL_ARM_BRANCH24T = 0x0014 + IMAGE_REL_ARM_BLX23T = 0x0015 + + +class Relocs_Macho_i386(Enum): + RIT_Vanilla = 0 + RIT_Pair = 1 + RIT_Difference = 2 + RIT_Generic_PreboundLazyPointer = 3 + RIT_Generic_LocalDifference = 4 + RIT_Generic_TLV = 5 + +class Relocs_Macho_X86_64(Enum): + RIT_X86_64_Unsigned = 0 + RIT_X86_64_Signed = 1 + RIT_X86_64_Branch = 2 + RIT_X86_64_GOTLoad = 3 + RIT_X86_64_GOT = 4 + RIT_X86_64_Subtractor = 5 + RIT_X86_64_Signed1 = 6 + RIT_X86_64_Signed2 = 7 + RIT_X86_64_Signed4 = 8 + RIT_X86_64_TLV = 9 + +class Relocs_Macho_ARM(Enum): + RIT_Vanilla = 0 + RIT_Pair = 1 + RIT_Difference = 2 + RIT_ARM_LocalDifference = 3 + RIT_ARM_PreboundLazyPointer = 4 + RIT_ARM_Branch24Bit = 5 + RIT_ARM_ThumbBranch22Bit = 6 + RIT_ARM_ThumbBranch32Bit = 7 + RIT_ARM_Half = 8 + RIT_ARM_HalfDifference = 9 + +class Relocs_Macho_PPC(Enum): + PPC_RELOC_VANILLA = 0 + PPC_RELOC_PAIR = 1 + PPC_RELOC_BR14 = 2 + PPC_RELOC_BR24 = 3 + PPC_RELOC_HI16 = 4 + PPC_RELOC_LO16 = 5 + PPC_RELOC_HA16 = 6 + PPC_RELOC_LO14 = 7 + PPC_RELOC_SECTDIFF = 8 + PPC_RELOC_PB_LA_PTR = 9 + PPC_RELOC_HI16_SECTDIFF = 10 + PPC_RELOC_LO16_SECTDIFF = 11 + PPC_RELOC_HA16_SECTDIFF = 12 + PPC_RELOC_JBSR = 13 + PPC_RELOC_LO14_SECTDIFF = 14 + PPC_RELOC_LOCAL_SECTDIFF = 15 + + +craftElf("relocs.obj.elf-x86_64", "x86_64-pc-linux-gnu", Relocs_Elf_X86_64.entries(), "leaq sym@GOTTPOFF(%rip), %rax") +craftElf("relocs.obj.elf-i386", "i386-pc-linux-gnu", Relocs_Elf_i386.entries(), "mov sym@GOTOFF(%ebx), %eax") +#craftElf("relocs-elf-ppc32", "powerpc-unknown-linux-gnu", Relocs_Elf_PPC32.entries(), ...) +craftElf("relocs.obj.elf-ppc64", "powerpc64-unknown-linux-gnu", Relocs_Elf_PPC64.entries(), + ("@t = thread_local global i32 0, align 4", "define i32* @f{0}() nounwind {{ ret i32* @t }}", 2)) +craftElf("relocs.obj.elf-aarch64", "aarch64", Relocs_Elf_AArch64.entries(), "movz x0, #:abs_g0:sym") +craftElf("relocs.obj.elf-arm", "arm-unknown-unknown", Relocs_Elf_ARM.entries(), "b sym") +craftElf("relocs.obj.elf-mips", "mips-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)") +craftElf("relocs.obj.elf-mips64el", "mips64el-unknown-linux", Relocs_Elf_Mips.entries(), "lui $2, %hi(sym)") +#craftElf("relocs.obj.elf-mblaze", "mblaze-unknown-unknown", Relocs_Elf_MBlaze.entries(), ...) +#craftElf("relocs.obj.elf-hexagon", "hexagon-unknown-unknown", Relocs_Elf_Hexagon.entries(), ...) + +craftCoff("relocs.obj.coff-i386", "i386-pc-win32", Relocs_Coff_i386.entries(), "mov foo@imgrel(%ebx, %ecx, 4), %eax") +craftCoff("relocs.obj.coff-x86_64", "x86_64-pc-win32", Relocs_Coff_X86_64.entries(), "mov foo@imgrel(%ebx, %ecx, 4), %eax") +#craftCoff("relocs.obj.coff-arm", "arm-pc-win32", Relocs_Coff_ARM.entries(), "...") + +craftMacho("relocs.obj.macho-i386", "i386-apple-darwin9", Relocs_Macho_i386.entries(), + ("asm", ".subsections_via_symbols; .text; a: ; b:", "call a", 1)) +craftMacho("relocs.obj.macho-x86_64", "x86_64-apple-darwin9", Relocs_Macho_X86_64.entries(), + ("asm", ".subsections_via_symbols; .text; a: ; b:", "call a", 1)) +craftMacho("relocs.obj.macho-arm", "armv7-apple-darwin10", Relocs_Macho_ARM.entries(), "bl sym") +#craftMacho("relocs.obj.macho-ppc", "powerpc-apple-darwin10", Relocs_Macho_PPC.entries(), ...) diff --git a/test/tools/llvm-readobj/Inputs/trivial.obj.macho-arm b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-arm Binary files differnew file mode 100644 index 000000000000..117df9efc1c4 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-arm diff --git a/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc Binary files differnew file mode 100644 index 000000000000..dd2e956499e4 --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc diff --git a/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc64 b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc64 Binary files differnew file mode 100644 index 000000000000..20ec8ef23f0f --- /dev/null +++ b/test/tools/llvm-readobj/Inputs/trivial.obj.macho-ppc64 diff --git a/test/tools/llvm-readobj/program-headers.test b/test/tools/llvm-readobj/program-headers.test new file mode 100644 index 000000000000..2a574bb2e646 --- /dev/null +++ b/test/tools/llvm-readobj/program-headers.test @@ -0,0 +1,74 @@ +RUN: llvm-readobj -program-headers %p/../../Object/Inputs/program-headers.elf-i386 \ +RUN: | FileCheck %s -check-prefix ELF-I386 +RUN: llvm-readobj -program-headers %p/../../Object/Inputs/program-headers.elf-x86-64 \ +RUN: | FileCheck %s -check-prefix ELF-X86-64 + +ELF-I386: ProgramHeaders [ +ELF-I386-NEXT: ProgramHeader { +ELF-I386-NEXT: Type: PT_LOAD (0x1) +ELF-I386-NEXT: Offset: 0x0 +ELF-I386-NEXT: VirtualAddress: 0x8048000 +ELF-I386-NEXT: PhysicalAddress: 0x8048000 +ELF-I386-NEXT: FileSize: 308 +ELF-I386-NEXT: MemSize: 308 +ELF-I386-NEXT: Flags [ (0x5) +ELF-I386-NEXT: PF_R (0x4) +ELF-I386-NEXT: PF_X (0x1) +ELF-I386-NEXT: ] +ELF-I386-NEXT: Alignment: 4096 +ELF-I386-NEXT: } +ELF-I386-NEXT: ProgramHeader { +ELF-I386-NEXT: Type: PT_GNU_STACK (0x6474E551) +ELF-I386-NEXT: Offset: 0x0 +ELF-I386-NEXT: VirtualAddress: 0x0 +ELF-I386-NEXT: PhysicalAddress: 0x0 +ELF-I386-NEXT: FileSize: 0 +ELF-I386-NEXT: MemSize: 0 +ELF-I386-NEXT: Flags [ (0x6) +ELF-I386-NEXT: PF_R (0x4) +ELF-I386-NEXT: PF_W (0x2) +ELF-I386-NEXT: ] +ELF-I386-NEXT: Alignment: 4 +ELF-I386-NEXT: } +ELF-I386-NEXT: ] + +ELF-X86-64: ProgramHeaders [ +ELF-X86-64-NEXT: ProgramHeader { +ELF-X86-64-NEXT: Type: PT_LOAD (0x1) +ELF-X86-64-NEXT: Offset: 0x0 +ELF-X86-64-NEXT: VirtualAddress: 0x400000 +ELF-X86-64-NEXT: PhysicalAddress: 0x400000 +ELF-X86-64-NEXT: FileSize: 312 +ELF-X86-64-NEXT: MemSize: 312 +ELF-X86-64-NEXT: Flags [ (0x5) +ELF-X86-64-NEXT: PF_R (0x4) +ELF-X86-64-NEXT: PF_X (0x1) +ELF-X86-64-NEXT: ] +ELF-X86-64-NEXT: Alignment: 2097152 +ELF-X86-64-NEXT: } +ELF-X86-64-NEXT: ProgramHeader { +ELF-X86-64-NEXT: Type: PT_GNU_EH_FRAME (0x6474E550) +ELF-X86-64-NEXT: Offset: 0xF4 +ELF-X86-64-NEXT: VirtualAddress: 0x4000F4 +ELF-X86-64-NEXT: PhysicalAddress: 0x4000F4 +ELF-X86-64-NEXT: FileSize: 20 +ELF-X86-64-NEXT: MemSize: 20 +ELF-X86-64-NEXT: Flags [ (0x4) +ELF-X86-64-NEXT: PF_R (0x4) +ELF-X86-64-NEXT: ] +ELF-X86-64-NEXT: Alignment: 4 +ELF-X86-64-NEXT: } +ELF-X86-64-NEXT: ProgramHeader { +ELF-X86-64-NEXT: Type: PT_GNU_STACK (0x6474E551) +ELF-X86-64-NEXT: Offset: 0x0 +ELF-X86-64-NEXT: VirtualAddress: 0x0 +ELF-X86-64-NEXT: PhysicalAddress: 0x0 +ELF-X86-64-NEXT: FileSize: 0 +ELF-X86-64-NEXT: MemSize: 0 +ELF-X86-64-NEXT: Flags [ (0x6) +ELF-X86-64-NEXT: PF_R (0x4) +ELF-X86-64-NEXT: PF_W (0x2) +ELF-X86-64-NEXT: ] +ELF-X86-64-NEXT: Alignment: 8 +ELF-X86-64-NEXT: } +ELF-X86-64-NEXT: ] diff --git a/test/tools/llvm-readobj/reloc-types.test b/test/tools/llvm-readobj/reloc-types.test new file mode 100644 index 000000000000..08603bc7fb55 --- /dev/null +++ b/test/tools/llvm-readobj/reloc-types.test @@ -0,0 +1,663 @@ +// Test that libObject and subsequently llvm-readobj shows proper relocation type +// names and values. + +// Todo: ELF-PPC, ELF-HEXAGON + +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-i386 | FileCheck %s -check-prefix ELF-32 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-x86_64 | FileCheck %s -check-prefix ELF-64 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-aarch64 | FileCheck %s -check-prefix ELF-AARCH64 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-arm | FileCheck %s -check-prefix ELF-ARM +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-mips | FileCheck %s -check-prefix ELF-MIPS +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-mips64el | FileCheck %s -check-prefix ELF-MIPS64EL +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-ppc64 | FileCheck %s -check-prefix ELF-PPC64 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.coff-i386 | FileCheck %s -check-prefix COFF-32 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.coff-x86_64 | FileCheck %s -check-prefix COFF-64 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.macho-arm | FileCheck %s -check-prefix MACHO-ARM +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.macho-i386 | FileCheck %s -check-prefix MACHO-32 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.macho-x86_64 | FileCheck %s -check-prefix MACHO-64 + + +ELF-32: Type: R_386_NONE (0) +ELF-32: Type: R_386_32 (1) +ELF-32: Type: R_386_PC32 (2) +ELF-32: Type: R_386_GOT32 (3) +ELF-32: Type: R_386_PLT32 (4) +ELF-32: Type: R_386_COPY (5) +ELF-32: Type: R_386_GLOB_DAT (6) +ELF-32: Type: R_386_JUMP_SLOT (7) +ELF-32: Type: R_386_RELATIVE (8) +ELF-32: Type: R_386_GOTOFF (9) +ELF-32: Type: R_386_GOTPC (10) +ELF-32: Type: R_386_32PLT (11) +ELF-32: Type: R_386_TLS_TPOFF (14) +ELF-32: Type: R_386_TLS_IE (15) +ELF-32: Type: R_386_TLS_GOTIE (16) +ELF-32: Type: R_386_TLS_LE (17) +ELF-32: Type: R_386_TLS_GD (18) +ELF-32: Type: R_386_TLS_LDM (19) +ELF-32: Type: R_386_16 (20) +ELF-32: Type: R_386_PC16 (21) +ELF-32: Type: R_386_8 (22) +ELF-32: Type: R_386_PC8 (23) +ELF-32: Type: R_386_TLS_GD_32 (24) +ELF-32: Type: R_386_TLS_GD_PUSH (25) +ELF-32: Type: R_386_TLS_GD_CALL (26) +ELF-32: Type: R_386_TLS_GD_POP (27) +ELF-32: Type: R_386_TLS_LDM_32 (28) +ELF-32: Type: R_386_TLS_LDM_PUSH (29) +ELF-32: Type: R_386_TLS_LDM_CALL (30) +ELF-32: Type: R_386_TLS_LDM_POP (31) +ELF-32: Type: R_386_TLS_LDO_32 (32) +ELF-32: Type: R_386_TLS_IE_32 (33) +ELF-32: Type: R_386_TLS_LE_32 (34) +ELF-32: Type: R_386_TLS_DTPMOD32 (35) +ELF-32: Type: R_386_TLS_DTPOFF32 (36) +ELF-32: Type: R_386_TLS_TPOFF32 (37) +ELF-32: Type: R_386_TLS_GOTDESC (39) +ELF-32: Type: R_386_TLS_DESC_CALL (40) +ELF-32: Type: R_386_TLS_DESC (41) +ELF-32: Type: R_386_IRELATIVE (42) +_LF-32: Type: R_386_NUM (43) + +ELF-64: Type: R_X86_64_NONE (0) +ELF-64: Type: R_X86_64_64 (1) +ELF-64: Type: R_X86_64_PC32 (2) +ELF-64: Type: R_X86_64_GOT32 (3) +ELF-64: Type: R_X86_64_PLT32 (4) +ELF-64: Type: R_X86_64_COPY (5) +ELF-64: Type: R_X86_64_GLOB_DAT (6) +ELF-64: Type: R_X86_64_JUMP_SLOT (7) +ELF-64: Type: R_X86_64_RELATIVE (8) +ELF-64: Type: R_X86_64_GOTPCREL (9) +ELF-64: Type: R_X86_64_32 (10) +ELF-64: Type: R_X86_64_32S (11) +ELF-64: Type: R_X86_64_16 (12) +ELF-64: Type: R_X86_64_PC16 (13) +ELF-64: Type: R_X86_64_8 (14) +ELF-64: Type: R_X86_64_PC8 (15) +ELF-64: Type: R_X86_64_DTPMOD64 (16) +ELF-64: Type: R_X86_64_DTPOFF64 (17) +ELF-64: Type: R_X86_64_TPOFF64 (18) +ELF-64: Type: R_X86_64_TLSGD (19) +ELF-64: Type: R_X86_64_TLSLD (20) +ELF-64: Type: R_X86_64_DTPOFF32 (21) +ELF-64: Type: R_X86_64_GOTTPOFF (22) +ELF-64: Type: R_X86_64_TPOFF32 (23) +ELF-64: Type: R_X86_64_PC64 (24) +ELF-64: Type: R_X86_64_GOTOFF64 (25) +ELF-64: Type: R_X86_64_GOTPC32 (26) +ELF-64: Type: R_X86_64_GOT64 (27) +ELF-64: Type: R_X86_64_GOTPCREL64 (28) +ELF-64: Type: R_X86_64_GOTPC64 (29) +ELF-64: Type: R_X86_64_GOTPLT64 (30) +ELF-64: Type: R_X86_64_PLTOFF64 (31) +ELF-64: Type: R_X86_64_SIZE32 (32) +ELF-64: Type: R_X86_64_SIZE64 (33) +ELF-64: Type: R_X86_64_GOTPC32_TLSDESC (34) +ELF-64: Type: R_X86_64_TLSDESC_CALL (35) +ELF-64: Type: R_X86_64_TLSDESC (36) +ELF-64: Type: R_X86_64_IRELATIVE (37) + +ELF-PPC: Type: R_PPC_NONE (0) +ELF-PPC: Type: R_PPC_ADDR32 (1) +ELF-PPC: Type: R_PPC_ADDR24 (2) +ELF-PPC: Type: R_PPC_ADDR16 (3) +ELF-PPC: Type: R_PPC_ADDR16_LO (4) +ELF-PPC: Type: R_PPC_ADDR16_HI (5) +ELF-PPC: Type: R_PPC_ADDR16_HA (6) +ELF-PPC: Type: R_PPC_ADDR14 (7) +ELF-PPC: Type: R_PPC_ADDR14_BRTAKEN (8) +ELF-PPC: Type: R_PPC_ADDR14_BRNTAKEN (9) +ELF-PPC: Type: R_PPC_REL24 (10) +ELF-PPC: Type: R_PPC_REL14 (11) +ELF-PPC: Type: R_PPC_REL14_BRTAKEN (12) +ELF-PPC: Type: R_PPC_REL14_BRNTAKEN (13) +ELF-PPC: Type: R_PPC_REL32 (26) +ELF-PPC: Type: R_PPC_TPREL16_LO (70) +ELF-PPC: Type: R_PPC_TPREL16_HA (72) + +ELF-PPC64: Type: R_PPC64_NONE (0) +ELF-PPC64: Type: R_PPC64_ADDR32 (1) +ELF-PPC64: Type: R_PPC64_ADDR16_LO (4) +ELF-PPC64: Type: R_PPC64_ADDR16_HI (5) +ELF-PPC64: Type: R_PPC64_ADDR14 (7) +ELF-PPC64: Type: R_PPC64_REL24 (10) +ELF-PPC64: Type: R_PPC64_REL32 (26) +ELF-PPC64: Type: R_PPC64_ADDR64 (38) +ELF-PPC64: Type: R_PPC64_ADDR16_HIGHER (39) +ELF-PPC64: Type: R_PPC64_ADDR16_HIGHEST (41) +ELF-PPC64: Type: R_PPC64_REL64 (44) +ELF-PPC64: Type: R_PPC64_TOC16 (47) +ELF-PPC64: Type: R_PPC64_TOC16_LO (48) +ELF-PPC64: Type: R_PPC64_TOC16_HA (50) +ELF-PPC64: Type: R_PPC64_TOC (51) +ELF-PPC64: Type: R_PPC64_ADDR16_DS (56) +ELF-PPC64: Type: R_PPC64_ADDR16_LO_DS (57) +ELF-PPC64: Type: R_PPC64_TOC16_DS (63) +ELF-PPC64: Type: R_PPC64_TOC16_LO_DS (64) +ELF-PPC64: Type: R_PPC64_TLS (67) +ELF-PPC64: Type: R_PPC64_TPREL16_LO (70) +ELF-PPC64: Type: R_PPC64_TPREL16_HA (72) +ELF-PPC64: Type: R_PPC64_DTPREL16_LO (75) +ELF-PPC64: Type: R_PPC64_DTPREL16_HA (77) +ELF-PPC64: Type: R_PPC64_GOT_TLSGD16_LO (80) +ELF-PPC64: Type: R_PPC64_GOT_TLSGD16_HA (82) +ELF-PPC64: Type: R_PPC64_GOT_TLSLD16_LO (84) +ELF-PPC64: Type: R_PPC64_GOT_TLSLD16_HA (86) +ELF-PPC64: Type: R_PPC64_GOT_TPREL16_LO_DS (88) +ELF-PPC64: Type: R_PPC64_GOT_TPREL16_HA (90) +ELF-PPC64: Type: R_PPC64_TLSGD (107) +ELF-PPC64: Type: R_PPC64_TLSLD (108) + +ELF-AARCH64: Type: R_AARCH64_NONE (256) +ELF-AARCH64: Type: R_AARCH64_ABS64 (257) +ELF-AARCH64: Type: R_AARCH64_ABS32 (258) +ELF-AARCH64: Type: R_AARCH64_ABS16 (259) +ELF-AARCH64: Type: R_AARCH64_PREL64 (260) +ELF-AARCH64: Type: R_AARCH64_PREL32 (261) +ELF-AARCH64: Type: R_AARCH64_PREL16 (262) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G0 (263) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G0_NC (264) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G1 (265) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G1_NC (266) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G2 (267) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G2_NC (268) +ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G3 (269) +ELF-AARCH64: Type: R_AARCH64_MOVW_SABS_G0 (270) +ELF-AARCH64: Type: R_AARCH64_MOVW_SABS_G1 (271) +ELF-AARCH64: Type: R_AARCH64_MOVW_SABS_G2 (272) +ELF-AARCH64: Type: R_AARCH64_LD_PREL_LO19 (273) +ELF-AARCH64: Type: R_AARCH64_ADR_PREL_LO21 (274) +ELF-AARCH64: Type: R_AARCH64_ADR_PREL_PG_HI21 (275) +ELF-AARCH64: Type: R_AARCH64_ADD_ABS_LO12_NC (277) +ELF-AARCH64: Type: R_AARCH64_LDST8_ABS_LO12_NC (278) +ELF-AARCH64: Type: R_AARCH64_TSTBR14 (279) +ELF-AARCH64: Type: R_AARCH64_CONDBR19 (280) +ELF-AARCH64: Type: R_AARCH64_JUMP26 (282) +ELF-AARCH64: Type: R_AARCH64_CALL26 (283) +ELF-AARCH64: Type: R_AARCH64_LDST16_ABS_LO12_NC (284) +ELF-AARCH64: Type: R_AARCH64_LDST32_ABS_LO12_NC (285) +ELF-AARCH64: Type: R_AARCH64_LDST64_ABS_LO12_NC (286) +ELF-AARCH64: Type: R_AARCH64_LDST128_ABS_LO12_NC (299) +ELF-AARCH64: Type: R_AARCH64_ADR_GOT_PAGE (311) +ELF-AARCH64: Type: R_AARCH64_LD64_GOT_LO12_NC (312) +ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G2 (523) +ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G1 (524) +ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC (525) +ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G0 (526) +ELF-AARCH64: Type: R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC (527) +ELF-AARCH64: Type: R_AARCH64_TLSLD_ADD_DTPREL_HI12 (528) +ELF-AARCH64: Type: R_AARCH64_TLSLD_ADD_DTPREL_LO12 (529) +ELF-AARCH64: Type: R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC (530) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST8_DTPREL_LO12 (531) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC (532) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST16_DTPREL_LO12 (533) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC (534) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST32_DTPREL_LO12 (535) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC (536) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST64_DTPREL_LO12 (537) +ELF-AARCH64: Type: R_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC (538) +ELF-AARCH64: Type: R_AARCH64_TLSIE_MOVW_GOTTPREL_G1 (539) +ELF-AARCH64: Type: R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC (540) +ELF-AARCH64: Type: R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 (541) +ELF-AARCH64: Type: R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC (542) +ELF-AARCH64: Type: R_AARCH64_TLSIE_LD_GOTTPREL_PREL19 (543) +ELF-AARCH64: Type: R_AARCH64_TLSLE_MOVW_TPREL_G2 (544) +ELF-AARCH64: Type: R_AARCH64_TLSLE_MOVW_TPREL_G1 (545) +ELF-AARCH64: Type: R_AARCH64_TLSLE_MOVW_TPREL_G1_NC (546) +ELF-AARCH64: Type: R_AARCH64_TLSLE_MOVW_TPREL_G0 (547) +ELF-AARCH64: Type: R_AARCH64_TLSLE_MOVW_TPREL_G0_NC (548) +ELF-AARCH64: Type: R_AARCH64_TLSLE_ADD_TPREL_HI12 (549) +ELF-AARCH64: Type: R_AARCH64_TLSLE_ADD_TPREL_LO12 (550) +ELF-AARCH64: Type: R_AARCH64_TLSLE_ADD_TPREL_LO12_NC (551) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST8_TPREL_LO12 (552) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC (553) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST16_TPREL_LO12 (554) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC (555) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12 (556) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC (557) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12 (558) +ELF-AARCH64: Type: R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC (559) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADR_PAGE (562) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_LD64_LO12_NC (563) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_ADD_LO12_NC (564) +ELF-AARCH64: Type: R_AARCH64_TLSDESC_CALL (569) + +ELF-ARM: Type: R_ARM_NONE (0) +ELF-ARM: Type: R_ARM_PC24 (1) +ELF-ARM: Type: R_ARM_ABS32 (2) +ELF-ARM: Type: R_ARM_REL32 (3) +ELF-ARM: Type: R_ARM_LDR_PC_G0 (4) +ELF-ARM: Type: R_ARM_ABS16 (5) +ELF-ARM: Type: R_ARM_ABS12 (6) +ELF-ARM: Type: R_ARM_THM_ABS5 (7) +ELF-ARM: Type: R_ARM_ABS8 (8) +ELF-ARM: Type: R_ARM_SBREL32 (9) +ELF-ARM: Type: R_ARM_THM_CALL (10) +ELF-ARM: Type: R_ARM_THM_PC8 (11) +ELF-ARM: Type: R_ARM_BREL_ADJ (12) +ELF-ARM: Type: R_ARM_TLS_DESC (13) +ELF-ARM: Type: R_ARM_THM_SWI8 (14) +ELF-ARM: Type: R_ARM_XPC25 (15) +ELF-ARM: Type: R_ARM_THM_XPC22 (16) +ELF-ARM: Type: R_ARM_TLS_DTPMOD32 (17) +ELF-ARM: Type: R_ARM_TLS_DTPOFF32 (18) +ELF-ARM: Type: R_ARM_TLS_TPOFF32 (19) +ELF-ARM: Type: R_ARM_COPY (20) +ELF-ARM: Type: R_ARM_GLOB_DAT (21) +ELF-ARM: Type: R_ARM_JUMP_SLOT (22) +ELF-ARM: Type: R_ARM_RELATIVE (23) +ELF-ARM: Type: R_ARM_GOTOFF32 (24) +ELF-ARM: Type: R_ARM_BASE_PREL (25) +ELF-ARM: Type: R_ARM_GOT_BREL (26) +ELF-ARM: Type: R_ARM_PLT32 (27) +ELF-ARM: Type: R_ARM_CALL (28) +ELF-ARM: Type: R_ARM_JUMP24 (29) +ELF-ARM: Type: R_ARM_THM_JUMP24 (30) +ELF-ARM: Type: R_ARM_BASE_ABS (31) +ELF-ARM: Type: R_ARM_ALU_PCREL_7_0 (32) +ELF-ARM: Type: R_ARM_ALU_PCREL_15_8 (33) +ELF-ARM: Type: R_ARM_ALU_PCREL_23_15 (34) +ELF-ARM: Type: R_ARM_LDR_SBREL_11_0_NC (35) +ELF-ARM: Type: R_ARM_ALU_SBREL_19_12_NC (36) +ELF-ARM: Type: R_ARM_ALU_SBREL_27_20_CK (37) +ELF-ARM: Type: R_ARM_TARGET1 (38) +ELF-ARM: Type: R_ARM_SBREL31 (39) +ELF-ARM: Type: R_ARM_V4BX (40) +ELF-ARM: Type: R_ARM_TARGET2 (41) +ELF-ARM: Type: R_ARM_PREL31 (42) +ELF-ARM: Type: R_ARM_MOVW_ABS_NC (43) +ELF-ARM: Type: R_ARM_MOVT_ABS (44) +ELF-ARM: Type: R_ARM_MOVW_PREL_NC (45) +ELF-ARM: Type: R_ARM_MOVT_PREL (46) +ELF-ARM: Type: R_ARM_THM_MOVW_ABS_NC (47) +ELF-ARM: Type: R_ARM_THM_MOVT_ABS (48) +ELF-ARM: Type: R_ARM_THM_MOVW_PREL_NC (49) +ELF-ARM: Type: R_ARM_THM_MOVT_PREL (50) +ELF-ARM: Type: R_ARM_THM_JUMP19 (51) +ELF-ARM: Type: R_ARM_THM_JUMP6 (52) +ELF-ARM: Type: R_ARM_THM_ALU_PREL_11_0 (53) +ELF-ARM: Type: R_ARM_THM_PC12 (54) +ELF-ARM: Type: R_ARM_ABS32_NOI (55) +ELF-ARM: Type: R_ARM_REL32_NOI (56) +ELF-ARM: Type: R_ARM_ALU_PC_G0_NC (57) +ELF-ARM: Type: R_ARM_ALU_PC_G0 (58) +ELF-ARM: Type: R_ARM_ALU_PC_G1_NC (59) +ELF-ARM: Type: R_ARM_ALU_PC_G1 (60) +ELF-ARM: Type: R_ARM_ALU_PC_G2 (61) +ELF-ARM: Type: R_ARM_LDR_PC_G1 (62) +ELF-ARM: Type: R_ARM_LDR_PC_G2 (63) +ELF-ARM: Type: R_ARM_LDRS_PC_G0 (64) +ELF-ARM: Type: R_ARM_LDRS_PC_G1 (65) +ELF-ARM: Type: R_ARM_LDRS_PC_G2 (66) +ELF-ARM: Type: R_ARM_LDC_PC_G0 (67) +ELF-ARM: Type: R_ARM_LDC_PC_G1 (68) +ELF-ARM: Type: R_ARM_LDC_PC_G2 (69) +ELF-ARM: Type: R_ARM_ALU_SB_G0_NC (70) +ELF-ARM: Type: R_ARM_ALU_SB_G0 (71) +ELF-ARM: Type: R_ARM_ALU_SB_G1_NC (72) +ELF-ARM: Type: R_ARM_ALU_SB_G1 (73) +ELF-ARM: Type: R_ARM_ALU_SB_G2 (74) +ELF-ARM: Type: R_ARM_LDR_SB_G0 (75) +ELF-ARM: Type: R_ARM_LDR_SB_G1 (76) +ELF-ARM: Type: R_ARM_LDR_SB_G2 (77) +ELF-ARM: Type: R_ARM_LDRS_SB_G0 (78) +ELF-ARM: Type: R_ARM_LDRS_SB_G1 (79) +ELF-ARM: Type: R_ARM_LDRS_SB_G2 (80) +ELF-ARM: Type: R_ARM_LDC_SB_G0 (81) +ELF-ARM: Type: R_ARM_LDC_SB_G1 (82) +ELF-ARM: Type: R_ARM_LDC_SB_G2 (83) +ELF-ARM: Type: R_ARM_MOVW_BREL_NC (84) +ELF-ARM: Type: R_ARM_MOVT_BREL (85) +ELF-ARM: Type: R_ARM_MOVW_BREL (86) +ELF-ARM: Type: R_ARM_THM_MOVW_BREL_NC (87) +ELF-ARM: Type: R_ARM_THM_MOVT_BREL (88) +ELF-ARM: Type: R_ARM_THM_MOVW_BREL (89) +ELF-ARM: Type: R_ARM_TLS_GOTDESC (90) +ELF-ARM: Type: R_ARM_TLS_CALL (91) +ELF-ARM: Type: R_ARM_TLS_DESCSEQ (92) +ELF-ARM: Type: R_ARM_THM_TLS_CALL (93) +ELF-ARM: Type: R_ARM_PLT32_ABS (94) +ELF-ARM: Type: R_ARM_GOT_ABS (95) +ELF-ARM: Type: R_ARM_GOT_PREL (96) +ELF-ARM: Type: R_ARM_GOT_BREL12 (97) +ELF-ARM: Type: R_ARM_GOTOFF12 (98) +ELF-ARM: Type: R_ARM_GOTRELAX (99) +ELF-ARM: Type: R_ARM_GNU_VTENTRY (100) +ELF-ARM: Type: R_ARM_GNU_VTINHERIT (101) +ELF-ARM: Type: R_ARM_THM_JUMP11 (102) +ELF-ARM: Type: R_ARM_THM_JUMP8 (103) +ELF-ARM: Type: R_ARM_TLS_GD32 (104) +ELF-ARM: Type: R_ARM_TLS_LDM32 (105) +ELF-ARM: Type: R_ARM_TLS_LDO32 (106) +ELF-ARM: Type: R_ARM_TLS_IE32 (107) +ELF-ARM: Type: R_ARM_TLS_LE32 (108) +ELF-ARM: Type: R_ARM_TLS_LDO12 (109) +ELF-ARM: Type: R_ARM_TLS_LE12 (110) +ELF-ARM: Type: R_ARM_TLS_IE12GP (111) +ELF-ARM: Type: R_ARM_PRIVATE_0 (112) +ELF-ARM: Type: R_ARM_PRIVATE_1 (113) +ELF-ARM: Type: R_ARM_PRIVATE_2 (114) +ELF-ARM: Type: R_ARM_PRIVATE_3 (115) +ELF-ARM: Type: R_ARM_PRIVATE_4 (116) +ELF-ARM: Type: R_ARM_PRIVATE_5 (117) +ELF-ARM: Type: R_ARM_PRIVATE_6 (118) +ELF-ARM: Type: R_ARM_PRIVATE_7 (119) +ELF-ARM: Type: R_ARM_PRIVATE_8 (120) +ELF-ARM: Type: R_ARM_PRIVATE_9 (121) +ELF-ARM: Type: R_ARM_PRIVATE_10 (122) +ELF-ARM: Type: R_ARM_PRIVATE_11 (123) +ELF-ARM: Type: R_ARM_PRIVATE_12 (124) +ELF-ARM: Type: R_ARM_PRIVATE_13 (125) +ELF-ARM: Type: R_ARM_PRIVATE_14 (126) +ELF-ARM: Type: R_ARM_PRIVATE_15 (127) +ELF-ARM: Type: R_ARM_ME_TOO (128) +ELF-ARM: Type: R_ARM_THM_TLS_DESCSEQ16 (129) +ELF-ARM: Type: R_ARM_THM_TLS_DESCSEQ32 (130) + +ELF-MIPS: Type: R_MIPS_NONE (0) +ELF-MIPS: Type: R_MIPS_16 (1) +ELF-MIPS: Type: R_MIPS_32 (2) +ELF-MIPS: Type: R_MIPS_REL32 (3) +ELF-MIPS: Type: R_MIPS_26 (4) +ELF-MIPS: Type: R_MIPS_HI16 (5) +ELF-MIPS: Type: R_MIPS_LO16 (6) +ELF-MIPS: Type: R_MIPS_GPREL16 (7) +ELF-MIPS: Type: R_MIPS_LITERAL (8) +ELF-MIPS: Type: R_MIPS_GOT16 (9) +ELF-MIPS: Type: R_MIPS_PC16 (10) +ELF-MIPS: Type: R_MIPS_CALL16 (11) +ELF-MIPS: Type: R_MIPS_GPREL32 (12) +ELF-MIPS: Type: R_MIPS_SHIFT5 (16) +ELF-MIPS: Type: R_MIPS_SHIFT6 (17) +ELF-MIPS: Type: R_MIPS_64 (18) +ELF-MIPS: Type: R_MIPS_GOT_DISP (19) +ELF-MIPS: Type: R_MIPS_GOT_PAGE (20) +ELF-MIPS: Type: R_MIPS_GOT_OFST (21) +ELF-MIPS: Type: R_MIPS_GOT_HI16 (22) +ELF-MIPS: Type: R_MIPS_GOT_LO16 (23) +ELF-MIPS: Type: R_MIPS_SUB (24) +ELF-MIPS: Type: R_MIPS_INSERT_A (25) +ELF-MIPS: Type: R_MIPS_INSERT_B (26) +ELF-MIPS: Type: R_MIPS_DELETE (27) +ELF-MIPS: Type: R_MIPS_HIGHER (28) +ELF-MIPS: Type: R_MIPS_HIGHEST (29) +ELF-MIPS: Type: R_MIPS_CALL_HI16 (30) +ELF-MIPS: Type: R_MIPS_CALL_LO16 (31) +ELF-MIPS: Type: R_MIPS_SCN_DISP (32) +ELF-MIPS: Type: R_MIPS_REL16 (33) +ELF-MIPS: Type: R_MIPS_ADD_IMMEDIATE (34) +ELF-MIPS: Type: R_MIPS_PJUMP (35) +ELF-MIPS: Type: R_MIPS_RELGOT (36) +ELF-MIPS: Type: R_MIPS_JALR (37) +ELF-MIPS: Type: R_MIPS_TLS_DTPMOD32 (38) +ELF-MIPS: Type: R_MIPS_TLS_DTPREL32 (39) +ELF-MIPS: Type: R_MIPS_TLS_DTPMOD64 (40) +ELF-MIPS: Type: R_MIPS_TLS_DTPREL64 (41) +ELF-MIPS: Type: R_MIPS_TLS_GD (42) +ELF-MIPS: Type: R_MIPS_TLS_LDM (43) +ELF-MIPS: Type: R_MIPS_TLS_DTPREL_HI16 (44) +ELF-MIPS: Type: R_MIPS_TLS_DTPREL_LO16 (45) +ELF-MIPS: Type: R_MIPS_TLS_GOTTPREL (46) +ELF-MIPS: Type: R_MIPS_TLS_TPREL32 (47) +ELF-MIPS: Type: R_MIPS_TLS_TPREL64 (48) +ELF-MIPS: Type: R_MIPS_TLS_TPREL_HI16 (49) +ELF-MIPS: Type: R_MIPS_TLS_TPREL_LO16 (50) +ELF-MIPS: Type: R_MIPS_GLOB_DAT (51) +ELF-MIPS: Type: R_MIPS_COPY (126) +ELF-MIPS: Type: R_MIPS_JUMP_SLOT (127) +ELF-MIPS: Type: R_MIPS_NUM (218) +ELF-MIPS64EL: Type: R_MIPS_NONE/R_MIPS_NONE/R_MIPS_NONE (0) +ELF-MIPS64EL: Type: R_MIPS_16/R_MIPS_16/R_MIPS_16 (65793) +ELF-MIPS64EL: Type: R_MIPS_32/R_MIPS_32/R_MIPS_32 (131586) +ELF-MIPS64EL: Type: R_MIPS_REL32/R_MIPS_REL32/R_MIPS_REL32 (197379) +ELF-MIPS64EL: Type: R_MIPS_26/R_MIPS_26/R_MIPS_26 (263172) +ELF-MIPS64EL: Type: R_MIPS_HI16/R_MIPS_HI16/R_MIPS_HI16 (328965) +ELF-MIPS64EL: Type: R_MIPS_LO16/R_MIPS_LO16/R_MIPS_LO16 (394758) +ELF-MIPS64EL: Type: R_MIPS_GPREL16/R_MIPS_GPREL16/R_MIPS_GPREL16 (460551) +ELF-MIPS64EL: Type: R_MIPS_LITERAL/R_MIPS_LITERAL/R_MIPS_LITERAL (526344) +ELF-MIPS64EL: Type: R_MIPS_GOT16/R_MIPS_GOT16/R_MIPS_GOT16 (592137) +ELF-MIPS64EL: Type: R_MIPS_PC16/R_MIPS_PC16/R_MIPS_PC16 (657930) +ELF-MIPS64EL: Type: R_MIPS_CALL16/R_MIPS_CALL16/R_MIPS_CALL16 (723723) +ELF-MIPS64EL: Type: R_MIPS_GPREL32/R_MIPS_GPREL32/R_MIPS_GPREL32 (789516) +ELF-MIPS64EL: Type: R_MIPS_SHIFT5/R_MIPS_SHIFT5/R_MIPS_SHIFT5 (1052688) +ELF-MIPS64EL: Type: R_MIPS_SHIFT6/R_MIPS_SHIFT6/R_MIPS_SHIFT6 (1118481) +ELF-MIPS64EL: Type: R_MIPS_64/R_MIPS_64/R_MIPS_64 (1184274) +ELF-MIPS64EL: Type: R_MIPS_GOT_DISP/R_MIPS_GOT_DISP/R_MIPS_GOT_DISP (1250067) +ELF-MIPS64EL: Type: R_MIPS_GOT_PAGE/R_MIPS_GOT_PAGE/R_MIPS_GOT_PAGE (1315860) +ELF-MIPS64EL: Type: R_MIPS_GOT_OFST/R_MIPS_GOT_OFST/R_MIPS_GOT_OFST (1381653) +ELF-MIPS64EL: Type: R_MIPS_GOT_HI16/R_MIPS_GOT_HI16/R_MIPS_GOT_HI16 (1447446) +ELF-MIPS64EL: Type: R_MIPS_GOT_LO16/R_MIPS_GOT_LO16/R_MIPS_GOT_LO16 (1513239) +ELF-MIPS64EL: Type: R_MIPS_SUB/R_MIPS_SUB/R_MIPS_SUB (1579032) +ELF-MIPS64EL: Type: R_MIPS_INSERT_A/R_MIPS_INSERT_A/R_MIPS_INSERT_A (1644825) +ELF-MIPS64EL: Type: R_MIPS_INSERT_B/R_MIPS_INSERT_B/R_MIPS_INSERT_B (1710618) +ELF-MIPS64EL: Type: R_MIPS_DELETE/R_MIPS_DELETE/R_MIPS_DELETE (1776411) +ELF-MIPS64EL: Type: R_MIPS_HIGHER/R_MIPS_HIGHER/R_MIPS_HIGHER (1842204) +ELF-MIPS64EL: Type: R_MIPS_HIGHEST/R_MIPS_HIGHEST/R_MIPS_HIGHEST (1907997) +ELF-MIPS64EL: Type: R_MIPS_CALL_HI16/R_MIPS_CALL_HI16/R_MIPS_CALL_HI16 (1973790) +ELF-MIPS64EL: Type: R_MIPS_CALL_LO16/R_MIPS_CALL_LO16/R_MIPS_CALL_LO16 (2039583) +ELF-MIPS64EL: Type: R_MIPS_SCN_DISP/R_MIPS_SCN_DISP/R_MIPS_SCN_DISP (2105376) +ELF-MIPS64EL: Type: R_MIPS_REL16/R_MIPS_REL16/R_MIPS_REL16 (2171169) +ELF-MIPS64EL: Type: R_MIPS_ADD_IMMEDIATE/R_MIPS_ADD_IMMEDIATE/R_MIPS_ADD_IMMEDIATE (2236962) +ELF-MIPS64EL: Type: R_MIPS_PJUMP/R_MIPS_PJUMP/R_MIPS_PJUMP (2302755) +ELF-MIPS64EL: Type: R_MIPS_RELGOT/R_MIPS_RELGOT/R_MIPS_RELGOT (2368548) +ELF-MIPS64EL: Type: R_MIPS_JALR/R_MIPS_JALR/R_MIPS_JALR (2434341) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPMOD32/R_MIPS_TLS_DTPMOD32/R_MIPS_TLS_DTPMOD32 (2500134) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPREL32/R_MIPS_TLS_DTPREL32/R_MIPS_TLS_DTPREL32 (2565927) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPMOD64/R_MIPS_TLS_DTPMOD64/R_MIPS_TLS_DTPMOD64 (2631720) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPREL64/R_MIPS_TLS_DTPREL64/R_MIPS_TLS_DTPREL64 (2697513) +ELF-MIPS64EL: Type: R_MIPS_TLS_GD/R_MIPS_TLS_GD/R_MIPS_TLS_GD (2763306) +ELF-MIPS64EL: Type: R_MIPS_TLS_LDM/R_MIPS_TLS_LDM/R_MIPS_TLS_LDM (2829099) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPREL_HI16/R_MIPS_TLS_DTPREL_HI16/R_MIPS_TLS_DTPREL_HI16 (2894892) +ELF-MIPS64EL: Type: R_MIPS_TLS_DTPREL_LO16/R_MIPS_TLS_DTPREL_LO16/R_MIPS_TLS_DTPREL_LO16 (2960685) +ELF-MIPS64EL: Type: R_MIPS_TLS_GOTTPREL/R_MIPS_TLS_GOTTPREL/R_MIPS_TLS_GOTTPREL (3026478) +ELF-MIPS64EL: Type: R_MIPS_TLS_TPREL32/R_MIPS_TLS_TPREL32/R_MIPS_TLS_TPREL32 (3092271) +ELF-MIPS64EL: Type: R_MIPS_TLS_TPREL64/R_MIPS_TLS_TPREL64/R_MIPS_TLS_TPREL64 (3158064) +ELF-MIPS64EL: Type: R_MIPS_TLS_TPREL_HI16/R_MIPS_TLS_TPREL_HI16/R_MIPS_TLS_TPREL_HI16 (3223857) +ELF-MIPS64EL: Type: R_MIPS_TLS_TPREL_LO16/R_MIPS_TLS_TPREL_LO16/R_MIPS_TLS_TPREL_LO16 (3289650) +ELF-MIPS64EL: Type: R_MIPS_GLOB_DAT/R_MIPS_GLOB_DAT/R_MIPS_GLOB_DAT (3355443) +ELF-MIPS64EL: Type: R_MIPS_COPY/R_MIPS_COPY/R_MIPS_COPY (8289918) +ELF-MIPS64EL: Type: R_MIPS_JUMP_SLOT/R_MIPS_JUMP_SLOT/R_MIPS_JUMP_SLOT (8355711) +ELF-MIPS64EL: Type: R_MIPS_NUM/R_MIPS_NUM/R_MIPS_NUM (14342874) + +ELF-MBLAZE: Type: R_MICROBLAZE_NONE (0) +ELF-MBLAZE: Type: R_MICROBLAZE_32 (1) +ELF-MBLAZE: Type: R_MICROBLAZE_32_PCREL (2) +ELF-MBLAZE: Type: R_MICROBLAZE_64_PCREL (3) +ELF-MBLAZE: Type: R_MICROBLAZE_32_PCREL_LO (4) +ELF-MBLAZE: Type: R_MICROBLAZE_64 (5) +ELF-MBLAZE: Type: R_MICROBLAZE_32_LO (6) +ELF-MBLAZE: Type: R_MICROBLAZE_SRO32 (7) +ELF-MBLAZE: Type: R_MICROBLAZE_SRW32 (8) +ELF-MBLAZE: Type: R_MICROBLAZE_64_NONE (9) +ELF-MBLAZE: Type: R_MICROBLAZE_32_SYM_OP_SYM (10) +ELF-MBLAZE: Type: R_MICROBLAZE_GNU_VTINHERIT (11) +ELF-MBLAZE: Type: R_MICROBLAZE_GNU_VTENTRY (12) +ELF-MBLAZE: Type: R_MICROBLAZE_GOTPC_64 (13) +ELF-MBLAZE: Type: R_MICROBLAZE_GOT_64 (14) +ELF-MBLAZE: Type: R_MICROBLAZE_PLT_64 (15) +ELF-MBLAZE: Type: R_MICROBLAZE_REL (16) +ELF-MBLAZE: Type: R_MICROBLAZE_JUMP_SLOT (17) +ELF-MBLAZE: Type: R_MICROBLAZE_GLOB_DAT (18) +ELF-MBLAZE: Type: R_MICROBLAZE_GOTOFF_64 (19) +ELF-MBLAZE: Type: R_MICROBLAZE_GOTOFF_32 (20) +ELF-MBLAZE: Type: R_MICROBLAZE_COPY (21) + +ELF-HEXAGON: Type: R_HEX_NONE (0) +ELF-HEXAGON: Type: R_HEX_B22_PCREL (1) +ELF-HEXAGON: Type: R_HEX_B15_PCREL (2) +ELF-HEXAGON: Type: R_HEX_B7_PCREL (3) +ELF-HEXAGON: Type: R_HEX_LO16 (4) +ELF-HEXAGON: Type: R_HEX_HI16 (5) +ELF-HEXAGON: Type: R_HEX_32 (6) +ELF-HEXAGON: Type: R_HEX_16 (7) +ELF-HEXAGON: Type: R_HEX_8 (8) +ELF-HEXAGON: Type: R_HEX_GPREL16_0 (9) +ELF-HEXAGON: Type: R_HEX_GPREL16_1 (10) +ELF-HEXAGON: Type: R_HEX_GPREL16_2 (11) +ELF-HEXAGON: Type: R_HEX_GPREL16_3 (12) +ELF-HEXAGON: Type: R_HEX_HL16 (13) +ELF-HEXAGON: Type: R_HEX_B13_PCREL (14) +ELF-HEXAGON: Type: R_HEX_B9_PCREL (15) +ELF-HEXAGON: Type: R_HEX_B32_PCREL_X (16) +ELF-HEXAGON: Type: R_HEX_32_6_X (17) +ELF-HEXAGON: Type: R_HEX_B22_PCREL_X (18) +ELF-HEXAGON: Type: R_HEX_B15_PCREL_X (19) +ELF-HEXAGON: Type: R_HEX_B13_PCREL_X (20) +ELF-HEXAGON: Type: R_HEX_B9_PCREL_X (21) +ELF-HEXAGON: Type: R_HEX_B7_PCREL_X (22) +ELF-HEXAGON: Type: R_HEX_16_X (23) +ELF-HEXAGON: Type: R_HEX_12_X (24) +ELF-HEXAGON: Type: R_HEX_11_X (25) +ELF-HEXAGON: Type: R_HEX_10_X (26) +ELF-HEXAGON: Type: R_HEX_9_X (27) +ELF-HEXAGON: Type: R_HEX_8_X (28) +ELF-HEXAGON: Type: R_HEX_7_X (29) +ELF-HEXAGON: Type: R_HEX_6_X (30) +ELF-HEXAGON: Type: R_HEX_32_PCREL (31) +ELF-HEXAGON: Type: R_HEX_COPY (32) +ELF-HEXAGON: Type: R_HEX_GLOB_DAT (33) +ELF-HEXAGON: Type: R_HEX_JMP_SLOT (34) +ELF-HEXAGON: Type: R_HEX_RELATIVE (35) +ELF-HEXAGON: Type: R_HEX_PLT_B22_PCREL (36) +ELF-HEXAGON: Type: R_HEX_GOTREL_LO16 (37) +ELF-HEXAGON: Type: R_HEX_GOTREL_HI16 (38) +ELF-HEXAGON: Type: R_HEX_GOTREL_32 (39) +ELF-HEXAGON: Type: R_HEX_GOT_LO16 (40) +ELF-HEXAGON: Type: R_HEX_GOT_HI16 (41) +ELF-HEXAGON: Type: R_HEX_GOT_32 (42) +ELF-HEXAGON: Type: R_HEX_GOT_16 (43) +ELF-HEXAGON: Type: R_HEX_DTPMOD_32 (44) +ELF-HEXAGON: Type: R_HEX_DTPREL_LO16 (45) +ELF-HEXAGON: Type: R_HEX_DTPREL_HI16 (46) +ELF-HEXAGON: Type: R_HEX_DTPREL_32 (47) +ELF-HEXAGON: Type: R_HEX_DTPREL_16 (48) +ELF-HEXAGON: Type: R_HEX_GD_PLT_B22_PCREL (49) +ELF-HEXAGON: Type: R_HEX_GD_GOT_LO16 (50) +ELF-HEXAGON: Type: R_HEX_GD_GOT_HI16 (51) +ELF-HEXAGON: Type: R_HEX_GD_GOT_32 (52) +ELF-HEXAGON: Type: R_HEX_GD_GOT_16 (53) +ELF-HEXAGON: Type: R_HEX_IE_LO16 (54) +ELF-HEXAGON: Type: R_HEX_IE_HI16 (55) +ELF-HEXAGON: Type: R_HEX_IE_32 (56) +ELF-HEXAGON: Type: R_HEX_IE_GOT_LO16 (57) +ELF-HEXAGON: Type: R_HEX_IE_GOT_HI16 (58) +ELF-HEXAGON: Type: R_HEX_IE_GOT_32 (59) +ELF-HEXAGON: Type: R_HEX_IE_GOT_16 (60) +ELF-HEXAGON: Type: R_HEX_TPREL_LO16 (61) +ELF-HEXAGON: Type: R_HEX_TPREL_HI16 (62) +ELF-HEXAGON: Type: R_HEX_TPREL_32 (63) +ELF-HEXAGON: Type: R_HEX_TPREL_16 (64) +ELF-HEXAGON: Type: R_HEX_6_PCREL_X (65) +ELF-HEXAGON: Type: R_HEX_GOTREL_32_6_X (66) +ELF-HEXAGON: Type: R_HEX_GOTREL_16_X (67) +ELF-HEXAGON: Type: R_HEX_GOTREL_11_X (68) +ELF-HEXAGON: Type: R_HEX_GOT_32_6_X (69) +ELF-HEXAGON: Type: R_HEX_GOT_16_X (70) +ELF-HEXAGON: Type: R_HEX_GOT_11_X (71) +ELF-HEXAGON: Type: R_HEX_DTPREL_32_6_X (72) +ELF-HEXAGON: Type: R_HEX_DTPREL_16_X (73) +ELF-HEXAGON: Type: R_HEX_DTPREL_11_X (74) +ELF-HEXAGON: Type: R_HEX_GD_GOT_32_6_X (75) +ELF-HEXAGON: Type: R_HEX_GD_GOT_16_X (76) +ELF-HEXAGON: Type: R_HEX_GD_GOT_11_X (77) +ELF-HEXAGON: Type: R_HEX_IE_32_6_X (78) +ELF-HEXAGON: Type: R_HEX_IE_16_X (79) +ELF-HEXAGON: Type: R_HEX_IE_GOT_32_6_X (80) +ELF-HEXAGON: Type: R_HEX_IE_GOT_16_X (81) +ELF-HEXAGON: Type: R_HEX_IE_GOT_11_X (82) +ELF-HEXAGON: Type: R_HEX_TPREL_32_6_X (83) +ELF-HEXAGON: Type: R_HEX_TPREL_16_X (84) +ELF-HEXAGON: Type: R_HEX_TPREL_11_X (85) + +COFF-32: Type: IMAGE_REL_I386_ABSOLUTE (0) +COFF-32: Type: IMAGE_REL_I386_DIR16 (1) +COFF-32: Type: IMAGE_REL_I386_REL16 (2) +COFF-32: Type: IMAGE_REL_I386_DIR32 (6) +COFF-32: Type: IMAGE_REL_I386_DIR32NB (7) +COFF-32: Type: IMAGE_REL_I386_SEG12 (9) +COFF-32: Type: IMAGE_REL_I386_SECTION (10) +COFF-32: Type: IMAGE_REL_I386_SECREL (11) +COFF-32: Type: IMAGE_REL_I386_TOKEN (12) +COFF-32: Type: IMAGE_REL_I386_SECREL7 (13) +COFF-32: Type: IMAGE_REL_I386_REL32 (20) + +COFF-64: Type: IMAGE_REL_AMD64_ABSOLUTE (0) +COFF-64: Type: IMAGE_REL_AMD64_ADDR64 (1) +COFF-64: Type: IMAGE_REL_AMD64_ADDR32 (2) +COFF-64: Type: IMAGE_REL_AMD64_ADDR32NB (3) +COFF-64: Type: IMAGE_REL_AMD64_REL32 (4) +COFF-64: Type: IMAGE_REL_AMD64_REL32_1 (5) +COFF-64: Type: IMAGE_REL_AMD64_REL32_2 (6) +COFF-64: Type: IMAGE_REL_AMD64_REL32_3 (7) +COFF-64: Type: IMAGE_REL_AMD64_REL32_4 (8) +COFF-64: Type: IMAGE_REL_AMD64_REL32_5 (9) +COFF-64: Type: IMAGE_REL_AMD64_SECTION (10) +COFF-64: Type: IMAGE_REL_AMD64_SECREL (11) +COFF-64: Type: IMAGE_REL_AMD64_SECREL7 (12) +COFF-64: Type: IMAGE_REL_AMD64_TOKEN (13) +COFF-64: Type: IMAGE_REL_AMD64_SREL32 (14) +COFF-64: Type: IMAGE_REL_AMD64_PAIR (15) +COFF-64: Type: IMAGE_REL_AMD64_SSPAN32 (16) + +COFF-ARM: Type: IMAGE_REL_ARM_ABSOLUTE (0x0000) +COFF-ARM: Type: IMAGE_REL_ARM_ADDR32 (0x0001) +COFF-ARM: Type: IMAGE_REL_ARM_ADDR32NB (0x0002) +COFF-ARM: Type: IMAGE_REL_ARM_BRANCH24 (0x0003) +COFF-ARM: Type: IMAGE_REL_ARM_BRANCH11 (0x0004) +COFF-ARM: Type: IMAGE_REL_ARM_TOKEN (0x0005) +COFF-ARM: Type: IMAGE_REL_ARM_BLX24 (0x0008) +COFF-ARM: Type: IMAGE_REL_ARM_BLX11 (0x0009) +COFF-ARM: Type: IMAGE_REL_ARM_SECTION (0x000E) +COFF-ARM: Type: IMAGE_REL_ARM_SECREL (0x000F) +COFF-ARM: Type: IMAGE_REL_ARM_MOV32A (0x0010) +COFF-ARM: Type: IMAGE_REL_ARM_MOV32T (0x0011) +COFF-ARM: Type: IMAGE_REL_ARM_BRANCH20T (0x0012) +COFF-ARM: Type: IMAGE_REL_ARM_BRANCH24T (0x0014) +COFF-ARM: Type: IMAGE_REL_ARM_BLX23T (0x0015) + +MACHO-32: Type: GENERIC_RELOC_VANILLA (0) +MACHO-32: Type: GENERIC_RELOC_PAIR (1) +MACHO-32: Type: GENERIC_RELOC_SECTDIFF (2) +MACHO-32: Type: GENERIC_RELOC_PB_LA_PTR (3) +MACHO-32: Type: GENERIC_RELOC_LOCAL_SECTDIFF (4) +MACHO-32: Type: GENERIC_RELOC_TLV (5) + +MACHO-64: Type: X86_64_RELOC_UNSIGNED (0) +MACHO-64: Type: X86_64_RELOC_SIGNED (1) +MACHO-64: Type: X86_64_RELOC_BRANCH (2) +MACHO-64: Type: X86_64_RELOC_GOT_LOAD (3) +MACHO-64: Type: X86_64_RELOC_GOT (4) +MACHO-64: Type: X86_64_RELOC_SUBTRACTOR (5) +MACHO-64: Type: X86_64_RELOC_SIGNED_1 (6) +MACHO-64: Type: X86_64_RELOC_SIGNED_2 (7) +MACHO-64: Type: X86_64_RELOC_SIGNED_4 (8) +MACHO-64: Type: X86_64_RELOC_TLV (9) + +MACHO-ARM: Type: ARM_RELOC_VANILLA (0) +MACHO-ARM: Type: ARM_RELOC_PAIR (1) +MACHO-ARM: Type: ARM_RELOC_SECTDIFF (2) +MACHO-ARM: Type: ARM_RELOC_LOCAL_SECTDIFF (3) +MACHO-ARM: Type: ARM_RELOC_PB_LA_PTR (4) +MACHO-ARM: Type: ARM_RELOC_BR24 (5) +MACHO-ARM: Type: ARM_THUMB_RELOC_BR22 (6) +MACHO-ARM: Type: ARM_THUMB_32BIT_BRANCH (7) +MACHO-ARM: Type: ARM_RELOC_HALF (8) +MACHO-ARM: Type: ARM_RELOC_HALF_SECTDIFF (9) + +MACHO-PPC: PPC_RELOC_VANILLA (0) +MACHO-PPC: PPC_RELOC_PAIR (1) +MACHO-PPC: PPC_RELOC_BR14 (2) +MACHO-PPC: PPC_RELOC_BR24 (3) +MACHO-PPC: PPC_RELOC_HI16 (4) +MACHO-PPC: PPC_RELOC_LO16 (5) +MACHO-PPC: PPC_RELOC_HA16 (6) +MACHO-PPC: PPC_RELOC_LO14 (7) +MACHO-PPC: PPC_RELOC_SECTDIFF (8) +MACHO-PPC: PPC_RELOC_PB_LA_PTR (9) +MACHO-PPC: PPC_RELOC_HI16_SECTDIFF (10) +MACHO-PPC: PPC_RELOC_LO16_SECTDIFF (11) +MACHO-PPC: PPC_RELOC_HA16_SECTDIFF (12) +MACHO-PPC: PPC_RELOC_JBSR (13) +MACHO-PPC: PPC_RELOC_LO14_SECTDIFF (14) +MACHO-PPC: PPC_RELOC_LOCAL_SECTDIFF (15) diff --git a/test/tools/llvm-readobj/relocations.test b/test/tools/llvm-readobj/relocations.test index 060856537356..dec7f862982c 100644 --- a/test/tools/llvm-readobj/relocations.test +++ b/test/tools/llvm-readobj/relocations.test @@ -3,7 +3,15 @@ RUN: | FileCheck %s -check-prefix COFF RUN: llvm-readobj -r %p/Inputs/trivial.obj.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF RUN: llvm-readobj -r %p/Inputs/trivial.obj.macho-i386 \ -RUN: | FileCheck %s -check-prefix MACHO +RUN: | FileCheck %s -check-prefix MACHO-I386 +RUN: llvm-readobj -r %p/Inputs/trivial.obj.macho-x86-64 \ +RUN: | FileCheck %s -check-prefix MACHO-X86-64 +RUN: llvm-readobj -r %p/Inputs/trivial.obj.macho-ppc \ +RUN: | FileCheck %s -check-prefix MACHO-PPC +RUN: llvm-readobj -r %p/Inputs/trivial.obj.macho-ppc64 \ +RUN: | FileCheck %s -check-prefix MACHO-PPC64 +RUN: llvm-readobj -r -expand-relocs %p/Inputs/trivial.obj.macho-arm \ +RUN: | FileCheck %s -check-prefix MACHO-ARM COFF: Relocations [ COFF-NEXT: Section (1) .text { @@ -22,11 +30,144 @@ ELF-NEXT: 0x1F R_386_PLT32 SomeOtherFunction 0x0 ELF-NEXT: } ELF-NEXT: ] -MACHO: Relocations [ -MACHO-NEXT: Section __text { -MACHO-NEXT: 0x18 GENERIC_RELOC_VANILLA _SomeOtherFunction 0x0 -MACHO-NEXT: 0x13 GENERIC_RELOC_VANILLA _puts 0x0 -MACHO-NEXT: 0xB GENERIC_RELOC_LOCAL_SECTDIFF _main 0x{{[0-9A-F]+}} -MACHO-NEXT: 0x0 GENERIC_RELOC_PAIR _main 0x{{[0-9A-F]+}} -MACHO-NEXT: } -MACHO-NEXT: ] +MACHO-I386: Relocations [ +MACHO-I386-NEXT: Section __text { +MACHO-I386-NEXT: 0x18 1 2 1 GENERIC_RELOC_VANILLA 0 _SomeOtherFunction +MACHO-I386-NEXT: 0x13 1 2 1 GENERIC_RELOC_VANILLA 0 _puts +MACHO-I386-NEXT: 0xB 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 - +MACHO-I386-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 - +MACHO-I386-NEXT: } +MACHO-I386-NEXT: ] + +MACHO-X86-64: Relocations [ +MACHO-X86-64-NEXT: Section __text { +MACHO-X86-64-NEXT: 0xE 1 2 1 X86_64_RELOC_BRANCH 0 _SomeOtherFunction +MACHO-X86-64-NEXT: 0x9 1 2 1 X86_64_RELOC_BRANCH 0 _puts +MACHO-X86-64-NEXT: 0x4 1 2 1 X86_64_RELOC_SIGNED 0 L_.str +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT:] + +MACHO-PPC: Relocations [ +MACHO-PPC-NEXT: Section __text { +MACHO-PPC-NEXT: 0x24 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x0 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0x1C 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x58 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0x18 1 2 0 PPC_RELOC_BR24 0 - +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section __picsymbolstub1 { +MACHO-PPC-NEXT: 0x14 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x0 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0xC 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x20 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section __la_symbol_ptr { +MACHO-PPC-NEXT: 0x0 0 2 1 PPC_RELOC_VANILLA 0 dyld_stub_binding_helper +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: ] + +MACHO-PPC64: Relocations [ +MACHO-PPC64-NEXT: Section __text { +MACHO-PPC64-NEXT: 0x24 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x0 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x1C 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x58 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x18 1 2 0 0 - +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section __picsymbolstub1 { +MACHO-PPC64-NEXT: 0x14 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x0 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0xC 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x24 0 2 n/a 1 - +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section __la_symbol_ptr { +MACHO-PPC64-NEXT: 0x0 0 3 1 0 dyld_stub_binding_helper +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: ] + + +MACHO-ARM: Relocations [ +MACHO-ARM-NEXT: Section __text { +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x38 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_SECTDIFF (2) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x20 +MACHO-ARM-NEXT: PCRel: 1 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_BR24 (5) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x1C +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 1 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_HALF (8) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 1 +MACHO-ARM-NEXT: Extern: 0 +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x18 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 0 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_HALF (8) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 0 +MACHO-ARM-NEXT: Extern: 0 +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0xC +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_SECTDIFF (2) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: ] diff --git a/test/tools/llvm-readobj/sections-ext.test b/test/tools/llvm-readobj/sections-ext.test index 3254040c0553..327f040854f9 100644 --- a/test/tools/llvm-readobj/sections-ext.test +++ b/test/tools/llvm-readobj/sections-ext.test @@ -3,7 +3,15 @@ RUN: | FileCheck %s -check-prefix COFF RUN: llvm-readobj -s -st -sr -sd %p/Inputs/trivial.obj.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF RUN: llvm-readobj -s -st -sr -sd %p/Inputs/trivial.obj.macho-i386 \ -RUN: | FileCheck %s -check-prefix MACHO +RUN: | FileCheck %s -check-prefix MACHO-I386 +RUN: llvm-readobj -s -st -sr -sd %p/Inputs/trivial.obj.macho-x86-64 \ +RUN: | FileCheck %s -check-prefix MACHO-X86-64 +RUN: llvm-readobj -s -st -sr -sd %p/Inputs/trivial.obj.macho-ppc \ +RUN: | FileCheck %s -check-prefix MACHO-PPC +RUN: llvm-readobj -s -st -sr -sd %p/Inputs/trivial.obj.macho-ppc64 \ +RUN: | FileCheck %s -check-prefix MACHO-PPC64 +RUN: llvm-readobj -expand-relocs -s -st -sr -sd %p/Inputs/trivial.obj.macho-arm \ +RUN: | FileCheck %s -check-prefix MACHO-ARM COFF: Sections [ COFF-NEXT: Section { @@ -132,44 +140,702 @@ ELF-NEXT: 0020: FFFFFF31 C083C408 5BC3 |...1....[.| ELF-NEXT: ) ELF-NEXT: } -MACHO: Sections [ -MACHO-NEXT: Section { -MACHO-NEXT: Index: 0 -MACHO-NEXT: Name: __text (5F 5F 74 65 78 74 00 -MACHO-NEXT: Segment: -MACHO-NEXT: Address: 0x0 -MACHO-NEXT: Size: 0x22 -MACHO-NEXT: Offset: 324 -MACHO-NEXT: Alignment: 4 -MACHO-NEXT: RelocationOffset: 0x174 -MACHO-NEXT: RelocationCount: 4 -MACHO-NEXT: Type: 0x0 -MACHO-NEXT: Attributes [ (0x800004) -MACHO-NEXT: PureInstructions (0x800000) -MACHO-NEXT: SomeInstructions (0x4) -MACHO-NEXT: ] -MACHO-NEXT: Reserved1: 0x0 -MACHO-NEXT: Reserved2: 0x0 -MACHO-NEXT: Relocations [ -MACHO-NEXT: 0x18 GENERIC_RELOC_VANILLA _SomeOtherFunction 0x0 -MACHO-NEXT: 0x13 GENERIC_RELOC_VANILLA _puts 0x0 -MACHO-NEXT: 0xB GENERIC_RELOC_LOCAL_SECTDIFF _main 0x{{[0-9A-F]+}} -MACHO-NEXT: 0x0 GENERIC_RELOC_PAIR _main 0x{{[0-9A-F]+}} -MACHO-NEXT: ] -MACHO-NEXT: Symbols [ -MACHO-NEXT: Symbol { -MACHO-NEXT: Name: _main (1) -MACHO-NEXT: Type: 0xF -MACHO-NEXT: Section: __text (0x1) -MACHO-NEXT: RefType: UndefinedNonLazy (0x0) -MACHO-NEXT: Flags [ (0x0) -MACHO-NEXT: ] -MACHO-NEXT: Value: 0x0 -MACHO-NEXT: } -MACHO-NEXT: ] -MACHO-NEXT: SectionData ( -MACHO-NEXT: 0000: 83EC0CE8 00000000 588D801A 00000089 |........X.......| -MACHO-NEXT: 0010: 0424E8E9 FFFFFFE8 E4FFFFFF 31C083C4 |.$..........1...| -MACHO-NEXT: 0020: 0CC3 |..| -MACHO-NEXT: ) -MACHO-NEXT: } +MACHO-I386: Sections [ +MACHO-I386-NEXT: Section { +MACHO-I386-NEXT: Index: 0 +MACHO-I386-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Address: 0x0 +MACHO-I386-NEXT: Size: 0x22 +MACHO-I386-NEXT: Offset: 324 +MACHO-I386-NEXT: Alignment: 4 +MACHO-I386-NEXT: RelocationOffset: 0x174 +MACHO-I386-NEXT: RelocationCount: 4 +MACHO-I386-NEXT: Type: 0x0 +MACHO-I386-NEXT: Attributes [ (0x800004) +MACHO-I386-NEXT: PureInstructions (0x800000) +MACHO-I386-NEXT: SomeInstructions (0x4) +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: Reserved1: 0x0 +MACHO-I386-NEXT: Reserved2: 0x0 +MACHO-I386-NEXT: Relocations [ +MACHO-I386-NEXT: 0x18 1 2 1 GENERIC_RELOC_VANILLA 0 _SomeOtherFunction +MACHO-I386-NEXT: 0x13 1 2 1 GENERIC_RELOC_VANILLA 0 _puts +MACHO-I386-NEXT: 0xB 0 2 n/a GENERIC_RELOC_LOCAL_SECTDIFF 1 - +MACHO-I386-NEXT: 0x0 0 2 n/a GENERIC_RELOC_PAIR 1 - +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: Symbols [ +MACHO-I386-NEXT: Symbol { +MACHO-I386-NEXT: Name: _main (1) +MACHO-I386-NEXT: Type: 0xF +MACHO-I386-NEXT: Section: __text (0x1) +MACHO-I386-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-I386-NEXT: Flags [ (0x0) +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: Value: 0x0 +MACHO-I386-NEXT: } +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: SectionData ( +MACHO-I386-NEXT: 0000: 83EC0CE8 00000000 588D801A 00000089 |........X.......| +MACHO-I386-NEXT: 0010: 0424E8E9 FFFFFFE8 E4FFFFFF 31C083C4 |.$..........1...| +MACHO-I386-NEXT: 0020: 0CC3 |..| +MACHO-I386-NEXT: ) +MACHO-I386-NEXT: } + + +MACHO-X86-64: Sections [ +MACHO-X86-64-NEXT: Section { +MACHO-X86-64-NEXT: Index: 0 +MACHO-X86-64-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Address: 0x0 +MACHO-X86-64-NEXT: Size: 0x16 +MACHO-X86-64-NEXT: Offset: 368 +MACHO-X86-64-NEXT: Alignment: 4 +MACHO-X86-64-NEXT: RelocationOffset: 0x194 +MACHO-X86-64-NEXT: RelocationCount: 3 +MACHO-X86-64-NEXT: Type: 0x0 +MACHO-X86-64-NEXT: Attributes [ (0x800004) +MACHO-X86-64-NEXT: PureInstructions (0x800000) +MACHO-X86-64-NEXT: SomeInstructions (0x4) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Reserved1: 0x0 +MACHO-X86-64-NEXT: Reserved2: 0x0 +MACHO-X86-64-NEXT: Relocations [ +MACHO-X86-64-NEXT: 0xE 1 2 1 X86_64_RELOC_BRANCH 0 _SomeOtherFunction +MACHO-X86-64-NEXT: 0x9 1 2 1 X86_64_RELOC_BRANCH 0 _puts +MACHO-X86-64-NEXT: 0x4 1 2 1 X86_64_RELOC_SIGNED 0 L_.str +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Symbols [ +MACHO-X86-64-NEXT: Symbol { +MACHO-X86-64-NEXT: Name: _main (1) +MACHO-X86-64-NEXT: Type: 0xF +MACHO-X86-64-NEXT: Section: __text (0x1) +MACHO-X86-64-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-X86-64-NEXT: Flags [ (0x0) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Value: 0x0 +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: SectionData ( +MACHO-X86-64-NEXT: 0000: 50488D3D 00000000 E8000000 00E80000 |PH.=............| +MACHO-X86-64-NEXT: 0010: 000031C0 5AC3 |..1.Z.| +MACHO-X86-64-NEXT: ) +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT: Section { +MACHO-X86-64-NEXT: Index: 1 +MACHO-X86-64-NEXT: Name: __cstring (5F 5F 63 73 74 72 69 6E 67 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Address: 0x16 +MACHO-X86-64-NEXT: Size: 0xD +MACHO-X86-64-NEXT: Offset: 390 +MACHO-X86-64-NEXT: Alignment: 0 +MACHO-X86-64-NEXT: RelocationOffset: 0x0 +MACHO-X86-64-NEXT: RelocationCount: 0 +MACHO-X86-64-NEXT: Type: ExtReloc (0x2) +MACHO-X86-64-NEXT: Attributes [ (0x0) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Reserved1: 0x0 +MACHO-X86-64-NEXT: Reserved2: 0x0 +MACHO-X86-64-NEXT: Relocations [ +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Symbols [ +MACHO-X86-64-NEXT: Symbol { +MACHO-X86-64-NEXT: Name: L_.str (32) +MACHO-X86-64-NEXT: Type: Section (0xE) +MACHO-X86-64-NEXT: Section: __cstring (0x2) +MACHO-X86-64-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-X86-64-NEXT: Flags [ (0x0) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Value: 0x16 +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: SectionData ( +MACHO-X86-64-NEXT: 0000: 48656C6C 6F20576F 726C640A 00 |Hello World..| +MACHO-X86-64-NEXT: ) +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT:] + +MACHO-PPC: Sections [ +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 0 +MACHO-PPC-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x0 +MACHO-PPC-NEXT: Size: 0x3C +MACHO-PPC-NEXT: Offset: 528 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x27C +MACHO-PPC-NEXT: RelocationCount: 5 +MACHO-PPC-NEXT: Type: 0x0 +MACHO-PPC-NEXT: Attributes [ (0x800004) +MACHO-PPC-NEXT: PureInstructions (0x800000) +MACHO-PPC-NEXT: SomeInstructions (0x4) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: Relocations [ +MACHO-PPC-NEXT: 0x24 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x0 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0x1C 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x58 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0x18 1 2 0 PPC_RELOC_BR24 0 - +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Symbols [ +MACHO-PPC-NEXT: Symbol { +MACHO-PPC-NEXT: Name: _f (4) +MACHO-PPC-NEXT: Type: 0xF +MACHO-PPC-NEXT: Section: __text (0x1) +MACHO-PPC-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-PPC-NEXT: Flags [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Value: 0x0 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: SectionData ( +MACHO-PPC-NEXT: 0000: 7C0802A6 93E1FFFC 429F0005 7FE802A6 ||.......B.......| +MACHO-PPC-NEXT: 0010: 90010008 9421FFB0 48000029 3C5F0000 |.....!..H..)<_..| +MACHO-PPC-NEXT: 0020: 38210050 80420058 80010008 83E1FFFC |8!.P.B.X........| +MACHO-PPC-NEXT: 0030: 7C0803A6 80620000 4E800020 ||....b..N.. | +MACHO-PPC-NEXT: ) +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 1 +MACHO-PPC-NEXT: Name: __picsymbolstub1 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 31) +MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x40 +MACHO-PPC-NEXT: Size: 0x20 +MACHO-PPC-NEXT: Offset: 592 +MACHO-PPC-NEXT: Alignment: 5 +MACHO-PPC-NEXT: RelocationOffset: 0x2A4 +MACHO-PPC-NEXT: RelocationCount: 4 +MACHO-PPC-NEXT: Type: 0x8 +MACHO-PPC-NEXT: Attributes [ (0x800004) +MACHO-PPC-NEXT: PureInstructions (0x800000) +MACHO-PPC-NEXT: SomeInstructions (0x4) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x20 +MACHO-PPC-NEXT: Relocations [ +MACHO-PPC-NEXT: 0x14 0 2 n/a PPC_RELOC_LO16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x0 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: 0xC 0 2 n/a PPC_RELOC_HA16_SECTDIFF 1 - +MACHO-PPC-NEXT: 0x20 0 2 n/a PPC_RELOC_PAIR 1 - +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Symbols [ +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: SectionData ( +MACHO-PPC-NEXT: 0000: 7C0802A6 429F0005 7D6802A6 3D6B0000 ||...B...}h..=k..| +MACHO-PPC-NEXT: 0010: 7C0803A6 858B0020 7D8903A6 4E800420 ||...... }...N.. | +MACHO-PPC-NEXT: ) +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 2 +MACHO-PPC-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x60 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 624 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x0 +MACHO-PPC-NEXT: RelocationCount: 0 +MACHO-PPC-NEXT: Type: 0x0 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: Relocations [ +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Symbols [ +MACHO-PPC-NEXT: Symbol { +MACHO-PPC-NEXT: Name: _b (1) +MACHO-PPC-NEXT: Type: 0xF +MACHO-PPC-NEXT: Section: __data (0x3) +MACHO-PPC-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-PPC-NEXT: Flags [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Value: 0x60 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: SectionData ( +MACHO-PPC-NEXT: 0000: 0000002A |...*| +MACHO-PPC-NEXT: ) +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 3 +MACHO-PPC-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x64 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 628 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x0 +MACHO-PPC-NEXT: RelocationCount: 0 +MACHO-PPC-NEXT: Type: 0x6 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x1 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: Relocations [ +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Symbols [ +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: SectionData ( +MACHO-PPC-NEXT: 0000: 00000000 |....| +MACHO-PPC-NEXT: ) +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 4 +MACHO-PPC-NEXT: Name: __la_symbol_ptr (5F 5F 6C 61 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x68 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 632 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x2C4 +MACHO-PPC-NEXT: RelocationCount: 1 +MACHO-PPC-NEXT: Type: 0x7 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x2 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: Relocations [ +MACHO-PPC-NEXT: 0x0 0 2 1 PPC_RELOC_VANILLA 0 dyld_stub_binding_helper +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Symbols [ +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: SectionData ( +MACHO-PPC-NEXT: 0000: 00000000 |....| +MACHO-PPC-NEXT: ) +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: ] + + +MACHO-PPC64: Sections [ +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 0 +MACHO-PPC64-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x0 +MACHO-PPC64-NEXT: Size: 0x3C +MACHO-PPC64-NEXT: Offset: 608 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x2D4 +MACHO-PPC64-NEXT: RelocationCount: 5 +MACHO-PPC64-NEXT: Type: 0x0 +MACHO-PPC64-NEXT: Attributes [ (0x800004) +MACHO-PPC64-NEXT: PureInstructions (0x800000) +MACHO-PPC64-NEXT: SomeInstructions (0x4) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: Relocations [ +MACHO-PPC64-NEXT: 0x24 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x0 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x1C 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x58 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x18 1 2 0 0 - +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Symbols [ +MACHO-PPC64-NEXT: Symbol { +MACHO-PPC64-NEXT: Name: _f (4) +MACHO-PPC64-NEXT: Type: 0xF +MACHO-PPC64-NEXT: Section: __text (0x1) +MACHO-PPC64-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-PPC64-NEXT: Flags [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Value: 0x0 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: SectionData ( +MACHO-PPC64-NEXT: 0000: 7C0802A6 FBE1FFF8 429F0005 7FE802A6 ||.......B.......| +MACHO-PPC64-NEXT: 0010: F8010010 F821FF81 48000029 3C5F0000 |.....!..H..)<_..| +MACHO-PPC64-NEXT: 0020: 38210080 E8420058 E8010010 EBE1FFF8 |8!...B.X........| +MACHO-PPC64-NEXT: 0030: 7C0803A6 E8620002 4E800020 ||....b..N.. | +MACHO-PPC64-NEXT: ) +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 1 +MACHO-PPC64-NEXT: Name: __picsymbolstub1 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 31) +MACHO-PPC64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x40 +MACHO-PPC64-NEXT: Size: 0x20 +MACHO-PPC64-NEXT: Offset: 672 +MACHO-PPC64-NEXT: Alignment: 5 +MACHO-PPC64-NEXT: RelocationOffset: 0x2FC +MACHO-PPC64-NEXT: RelocationCount: 4 +MACHO-PPC64-NEXT: Type: 0x8 +MACHO-PPC64-NEXT: Attributes [ (0x800004) +MACHO-PPC64-NEXT: PureInstructions (0x800000) +MACHO-PPC64-NEXT: SomeInstructions (0x4) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x20 +MACHO-PPC64-NEXT: Relocations [ +MACHO-PPC64-NEXT: 0x14 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x0 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0xC 0 2 n/a 1 - +MACHO-PPC64-NEXT: 0x24 0 2 n/a 1 - +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Symbols [ +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: SectionData ( +MACHO-PPC64-NEXT: 0000: 7C0802A6 429F0005 7D6802A6 3D6B0000 ||...B...}h..=k..| +MACHO-PPC64-NEXT: 0010: 7C0803A6 E98B0025 7D8903A6 4E800420 ||......%}...N.. | +MACHO-PPC64-NEXT: ) +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 2 +MACHO-PPC64-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x60 +MACHO-PPC64-NEXT: Size: 0x4 +MACHO-PPC64-NEXT: Offset: 704 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x0 +MACHO-PPC64-NEXT: RelocationCount: 0 +MACHO-PPC64-NEXT: Type: 0x0 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: Relocations [ +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Symbols [ +MACHO-PPC64-NEXT: Symbol { +MACHO-PPC64-NEXT: Name: _b (1) +MACHO-PPC64-NEXT: Type: 0xF +MACHO-PPC64-NEXT: Section: __data (0x3) +MACHO-PPC64-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-PPC64-NEXT: Flags [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Value: 0x60 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: SectionData ( +MACHO-PPC64-NEXT: 0000: 0000002A |...*| +MACHO-PPC64-NEXT: ) +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 3 +MACHO-PPC64-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x64 +MACHO-PPC64-NEXT: Size: 0x8 +MACHO-PPC64-NEXT: Offset: 708 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x0 +MACHO-PPC64-NEXT: RelocationCount: 0 +MACHO-PPC64-NEXT: Type: 0x6 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x1 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: Relocations [ +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Symbols [ +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: SectionData ( +MACHO-PPC64-NEXT: 0000: 00000000 00000000 |........| +MACHO-PPC64-NEXT: ) +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 4 +MACHO-PPC64-NEXT: Name: __la_symbol_ptr (5F 5F 6C 61 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x6C +MACHO-PPC64-NEXT: Size: 0x8 +MACHO-PPC64-NEXT: Offset: 716 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x31C +MACHO-PPC64-NEXT: RelocationCount: 1 +MACHO-PPC64-NEXT: Type: 0x7 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x2 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: Relocations [ +MACHO-PPC64-NEXT: 0x0 0 3 1 0 dyld_stub_binding_helper +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Symbols [ +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: SectionData ( +MACHO-PPC64-NEXT: 0000: 00000000 00000000 |........| +MACHO-PPC64-NEXT: ) +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: ] + +MACHO-ARM: Sections [ +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 0 +MACHO-ARM-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x0 +MACHO-ARM-NEXT: Size: 0x3C +MACHO-ARM-NEXT: Offset: 664 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x2E0 +MACHO-ARM-NEXT: RelocationCount: 9 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x800004) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: SomeInstructions (0x4) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x38 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_SECTDIFF (2) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x20 +MACHO-ARM-NEXT: PCRel: 1 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_BR24 (5) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x1C +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 1 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_HALF (8) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 1 +MACHO-ARM-NEXT: Extern: 0 +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x18 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 0 +MACHO-ARM-NEXT: Extern: 1 +MACHO-ARM-NEXT: Type: ARM_RELOC_HALF (8) +MACHO-ARM-NEXT: Symbol: _g +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 0 +MACHO-ARM-NEXT: Extern: 0 +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0xC +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_SECTDIFF (2) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Relocation { +MACHO-ARM-NEXT: Offset: 0x0 +MACHO-ARM-NEXT: PCRel: 0 +MACHO-ARM-NEXT: Length: 2 +MACHO-ARM-NEXT: Extern: N/A +MACHO-ARM-NEXT: Type: ARM_RELOC_PAIR (1) +MACHO-ARM-NEXT: Symbol: - +MACHO-ARM-NEXT: Scattered: 1 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: Symbol { +MACHO-ARM-NEXT: Name: _f (4) +MACHO-ARM-NEXT: Type: 0xF +MACHO-ARM-NEXT: Section: __text (0x1) +MACHO-ARM-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-ARM-NEXT: Flags [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Value: 0x10 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Symbol { +MACHO-ARM-NEXT: Name: _h (1) +MACHO-ARM-NEXT: Type: 0xF +MACHO-ARM-NEXT: Section: __text (0x1) +MACHO-ARM-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-ARM-NEXT: Flags [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Value: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: 0000: 04009FE5 00009FE7 1EFF2FE1 38000000 |........../.8...| +MACHO-ARM-NEXT: 0010: 80402DE9 0D70A0E1 000000E3 000040E3 |.@-..p........@.| +MACHO-ARM-NEXT: 0020: F6FFFFEB 0C009FE5 00009FE7 000090E5 |................| +MACHO-ARM-NEXT: 0030: 8040BDE8 1EFF2FE1 10000000 |.@..../.....| +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 1 +MACHO-ARM-NEXT: Name: __textcoal_nt (5F 5F 74 65 78 74 63 6F 61 6C 5F 6E 74 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0xB +MACHO-ARM-NEXT: Attributes [ (0x800000) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 2 +MACHO-ARM-NEXT: Name: __const_coal (5F 5F 63 6F 6E 73 74 5F 63 6F 61 6C 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0xB +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 3 +MACHO-ARM-NEXT: Name: __picsymbolstub4 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 34) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x8 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x10 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 4 +MACHO-ARM-NEXT: Name: __StaticInit (5F 5F 53 74 61 74 69 63 49 6E 69 74 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x800000) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 5 +MACHO-ARM-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x4 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: Symbol { +MACHO-ARM-NEXT: Name: _b (10) +MACHO-ARM-NEXT: Type: 0xF +MACHO-ARM-NEXT: Section: __data (0x6) +MACHO-ARM-NEXT: RefType: UndefinedNonLazy (0x0) +MACHO-ARM-NEXT: Flags [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Value: 0x3C +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: 0000: 2A000000 |*...| +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 6 +MACHO-ARM-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-ARM-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x40 +MACHO-ARM-NEXT: Size: 0x8 +MACHO-ARM-NEXT: Offset: 728 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x6 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: Relocations [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Symbols [ +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: SectionData ( +MACHO-ARM-NEXT: 0000: 00000000 00000000 |........| +MACHO-ARM-NEXT: ) +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: ] diff --git a/test/tools/llvm-readobj/sections.test b/test/tools/llvm-readobj/sections.test index e5c6c063b233..16f1131e05bd 100644 --- a/test/tools/llvm-readobj/sections.test +++ b/test/tools/llvm-readobj/sections.test @@ -3,7 +3,15 @@ RUN: | FileCheck %s -check-prefix COFF RUN: llvm-readobj -s %p/Inputs/trivial.obj.elf-i386 \ RUN: | FileCheck %s -check-prefix ELF RUN: llvm-readobj -s %p/Inputs/trivial.obj.macho-i386 \ -RUN: | FileCheck %s -check-prefix MACHO +RUN: | FileCheck %s -check-prefix MACHO-I386 +RUN: llvm-readobj -s %p/Inputs/trivial.obj.macho-x86-64 \ +RUN: | FileCheck %s -check-prefix MACHO-X86-64 +RUN: llvm-readobj -s %p/Inputs/trivial.obj.macho-ppc \ +RUN: | FileCheck %s -check-prefix MACHO-PPC +RUN: llvm-readobj -s %p/Inputs/trivial.obj.macho-ppc64 \ +RUN: | FileCheck %s -check-prefix MACHO-PPC64 +RUN: llvm-readobj -s %p/Inputs/trivial.obj.macho-arm \ +RUN: | FileCheck %s -check-prefix MACHO-ARM COFF: Sections [ COFF-NEXT: Section { @@ -76,38 +84,369 @@ ELF-NEXT: AddressAlignment: 16 ELF-NEXT: EntrySize: 0 ELF-NEXT: } -MACHO: Sections [ -MACHO-NEXT: Section { -MACHO-NEXT: Index: 0 -MACHO-NEXT: Name: __text ( -MACHO-NEXT: Segment: -MACHO-NEXT: Address: 0x0 -MACHO-NEXT: Size: 0x22 -MACHO-NEXT: Offset: 324 -MACHO-NEXT: Alignment: 4 -MACHO-NEXT: RelocationOffset: 0x174 -MACHO-NEXT: RelocationCount: 4 -MACHO-NEXT: Type: 0x0 -MACHO-NEXT: Attributes [ (0x800004) -MACHO-NEXT: PureInstructions (0x800000) -MACHO-NEXT: SomeInstructions (0x4) -MACHO-NEXT: ] -MACHO-NEXT: Reserved1: 0x0 -MACHO-NEXT: Reserved2: 0x0 -MACHO-NEXT: } -MACHO-NEXT: Section { -MACHO-NEXT: Index: 1 -MACHO-NEXT: Name: __cstring ( -MACHO-NEXT: Segment: -MACHO-NEXT: Address: 0x22 -MACHO-NEXT: Size: 0xD -MACHO-NEXT: Offset: 358 -MACHO-NEXT: Alignment: 0 -MACHO-NEXT: RelocationOffset: 0x0 -MACHO-NEXT: RelocationCount: 0 -MACHO-NEXT: Type: ExtReloc (0x2) -MACHO-NEXT: Attributes [ (0x0) -MACHO-NEXT: ] -MACHO-NEXT: Reserved1: 0x0 -MACHO-NEXT: Reserved2: 0x0 -MACHO-NEXT: } +MACHO-I386: Sections [ +MACHO-I386-NEXT: Section { +MACHO-I386-NEXT: Index: 0 +MACHO-I386-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Address: 0x0 +MACHO-I386-NEXT: Size: 0x22 +MACHO-I386-NEXT: Offset: 324 +MACHO-I386-NEXT: Alignment: 4 +MACHO-I386-NEXT: RelocationOffset: 0x174 +MACHO-I386-NEXT: RelocationCount: 4 +MACHO-I386-NEXT: Type: 0x0 +MACHO-I386-NEXT: Attributes [ (0x800004) +MACHO-I386-NEXT: PureInstructions (0x800000) +MACHO-I386-NEXT: SomeInstructions (0x4) +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: Reserved1: 0x0 +MACHO-I386-NEXT: Reserved2: 0x0 +MACHO-I386-NEXT: } +MACHO-I386-NEXT: Section { +MACHO-I386-NEXT: Index: 1 +MACHO-I386-NEXT: Name: __cstring (5F 5F 63 73 74 72 69 6E 67 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-I386-NEXT: Address: 0x22 +MACHO-I386-NEXT: Size: 0xD +MACHO-I386-NEXT: Offset: 358 +MACHO-I386-NEXT: Alignment: 0 +MACHO-I386-NEXT: RelocationOffset: 0x0 +MACHO-I386-NEXT: RelocationCount: 0 +MACHO-I386-NEXT: Type: ExtReloc (0x2) +MACHO-I386-NEXT: Attributes [ (0x0) +MACHO-I386-NEXT: ] +MACHO-I386-NEXT: Reserved1: 0x0 +MACHO-I386-NEXT: Reserved2: 0x0 +MACHO-I386-NEXT: } + + +MACHO-X86-64: Sections [ +MACHO-X86-64-NEXT: Section { +MACHO-X86-64-NEXT: Index: 0 +MACHO-X86-64-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Address: 0x0 +MACHO-X86-64-NEXT: Size: 0x16 +MACHO-X86-64-NEXT: Offset: 368 +MACHO-X86-64-NEXT: Alignment: 4 +MACHO-X86-64-NEXT: RelocationOffset: 0x194 +MACHO-X86-64-NEXT: RelocationCount: 3 +MACHO-X86-64-NEXT: Type: 0x0 +MACHO-X86-64-NEXT: Attributes [ (0x800004) +MACHO-X86-64-NEXT: PureInstructions (0x800000) +MACHO-X86-64-NEXT: SomeInstructions (0x4) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Reserved1: 0x0 +MACHO-X86-64-NEXT: Reserved2: 0x0 +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT: Section { +MACHO-X86-64-NEXT: Index: 1 +MACHO-X86-64-NEXT: Name: __cstring (5F 5F 63 73 74 72 69 6E 67 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-X86-64-NEXT: Address: 0x16 +MACHO-X86-64-NEXT: Size: 0xD +MACHO-X86-64-NEXT: Offset: 390 +MACHO-X86-64-NEXT: Alignment: 0 +MACHO-X86-64-NEXT: RelocationOffset: 0x0 +MACHO-X86-64-NEXT: RelocationCount: 0 +MACHO-X86-64-NEXT: Type: ExtReloc (0x2) +MACHO-X86-64-NEXT: Attributes [ (0x0) +MACHO-X86-64-NEXT: ] +MACHO-X86-64-NEXT: Reserved1: 0x0 +MACHO-X86-64-NEXT: Reserved2: 0x0 +MACHO-X86-64-NEXT: } +MACHO-X86-64-NEXT:] + +MACHO-PPC: Sections [ +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 0 +MACHO-PPC-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x0 +MACHO-PPC-NEXT: Size: 0x3C +MACHO-PPC-NEXT: Offset: 528 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x27C +MACHO-PPC-NEXT: RelocationCount: 5 +MACHO-PPC-NEXT: Type: 0x0 +MACHO-PPC-NEXT: Attributes [ (0x800004) +MACHO-PPC-NEXT: PureInstructions (0x800000) +MACHO-PPC-NEXT: SomeInstructions (0x4) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 1 +MACHO-PPC-NEXT: Name: __picsymbolstub1 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 31) +MACHO-PPC-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x40 +MACHO-PPC-NEXT: Size: 0x20 +MACHO-PPC-NEXT: Offset: 592 +MACHO-PPC-NEXT: Alignment: 5 +MACHO-PPC-NEXT: RelocationOffset: 0x2A4 +MACHO-PPC-NEXT: RelocationCount: 4 +MACHO-PPC-NEXT: Type: 0x8 +MACHO-PPC-NEXT: Attributes [ (0x800004) +MACHO-PPC-NEXT: PureInstructions (0x800000) +MACHO-PPC-NEXT: SomeInstructions (0x4) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x20 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 2 +MACHO-PPC-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x60 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 624 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x0 +MACHO-PPC-NEXT: RelocationCount: 0 +MACHO-PPC-NEXT: Type: 0x0 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x0 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 3 +MACHO-PPC-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x64 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 628 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x0 +MACHO-PPC-NEXT: RelocationCount: 0 +MACHO-PPC-NEXT: Type: 0x6 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x1 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: Section { +MACHO-PPC-NEXT: Index: 4 +MACHO-PPC-NEXT: Name: __la_symbol_ptr (5F 5F 6C 61 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC-NEXT: Address: 0x68 +MACHO-PPC-NEXT: Size: 0x4 +MACHO-PPC-NEXT: Offset: 632 +MACHO-PPC-NEXT: Alignment: 2 +MACHO-PPC-NEXT: RelocationOffset: 0x2C4 +MACHO-PPC-NEXT: RelocationCount: 1 +MACHO-PPC-NEXT: Type: 0x7 +MACHO-PPC-NEXT: Attributes [ (0x0) +MACHO-PPC-NEXT: ] +MACHO-PPC-NEXT: Reserved1: 0x2 +MACHO-PPC-NEXT: Reserved2: 0x0 +MACHO-PPC-NEXT: } +MACHO-PPC-NEXT: ] + +MACHO-PPC64: Sections [ +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 0 +MACHO-PPC64-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x0 +MACHO-PPC64-NEXT: Size: 0x3C +MACHO-PPC64-NEXT: Offset: 608 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x2D4 +MACHO-PPC64-NEXT: RelocationCount: 5 +MACHO-PPC64-NEXT: Type: 0x0 +MACHO-PPC64-NEXT: Attributes [ (0x800004) +MACHO-PPC64-NEXT: PureInstructions (0x800000) +MACHO-PPC64-NEXT: SomeInstructions (0x4) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 1 +MACHO-PPC64-NEXT: Name: __picsymbolstub1 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 31) +MACHO-PPC64-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x40 +MACHO-PPC64-NEXT: Size: 0x20 +MACHO-PPC64-NEXT: Offset: 672 +MACHO-PPC64-NEXT: Alignment: 5 +MACHO-PPC64-NEXT: RelocationOffset: 0x2FC +MACHO-PPC64-NEXT: RelocationCount: 4 +MACHO-PPC64-NEXT: Type: 0x8 +MACHO-PPC64-NEXT: Attributes [ (0x800004) +MACHO-PPC64-NEXT: PureInstructions (0x800000) +MACHO-PPC64-NEXT: SomeInstructions (0x4) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x20 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 2 +MACHO-PPC64-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x60 +MACHO-PPC64-NEXT: Size: 0x4 +MACHO-PPC64-NEXT: Offset: 704 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x0 +MACHO-PPC64-NEXT: RelocationCount: 0 +MACHO-PPC64-NEXT: Type: 0x0 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x0 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 3 +MACHO-PPC64-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x64 +MACHO-PPC64-NEXT: Size: 0x8 +MACHO-PPC64-NEXT: Offset: 708 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x0 +MACHO-PPC64-NEXT: RelocationCount: 0 +MACHO-PPC64-NEXT: Type: 0x6 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x1 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: Section { +MACHO-PPC64-NEXT: Index: 4 +MACHO-PPC64-NEXT: Name: __la_symbol_ptr (5F 5F 6C 61 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-PPC64-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-PPC64-NEXT: Address: 0x6C +MACHO-PPC64-NEXT: Size: 0x8 +MACHO-PPC64-NEXT: Offset: 716 +MACHO-PPC64-NEXT: Alignment: 2 +MACHO-PPC64-NEXT: RelocationOffset: 0x31C +MACHO-PPC64-NEXT: RelocationCount: 1 +MACHO-PPC64-NEXT: Type: 0x7 +MACHO-PPC64-NEXT: Attributes [ (0x0) +MACHO-PPC64-NEXT: ] +MACHO-PPC64-NEXT: Reserved1: 0x2 +MACHO-PPC64-NEXT: Reserved2: 0x0 +MACHO-PPC64-NEXT: } +MACHO-PPC64-NEXT: ] + +MACHO-ARM: Sections [ +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 0 +MACHO-ARM-NEXT: Name: __text (5F 5F 74 65 78 74 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x0 +MACHO-ARM-NEXT: Size: 0x3C +MACHO-ARM-NEXT: Offset: 664 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x2E0 +MACHO-ARM-NEXT: RelocationCount: 9 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x800004) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: SomeInstructions (0x4) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 1 +MACHO-ARM-NEXT: Name: __textcoal_nt (5F 5F 74 65 78 74 63 6F 61 6C 5F 6E 74 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0xB +MACHO-ARM-NEXT: Attributes [ (0x800000) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 2 +MACHO-ARM-NEXT: Name: __const_coal (5F 5F 63 6F 6E 73 74 5F 63 6F 61 6C 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0xB +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 3 +MACHO-ARM-NEXT: Name: __picsymbolstub4 (5F 5F 70 69 63 73 79 6D 62 6F 6C 73 74 75 62 34) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x8 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x10 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 4 +MACHO-ARM-NEXT: Name: __StaticInit (5F 5F 53 74 61 74 69 63 49 6E 69 74 00 00 00 00) +MACHO-ARM-NEXT: Segment: __TEXT (5F 5F 54 45 58 54 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x0 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 0 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x800000) +MACHO-ARM-NEXT: PureInstructions (0x800000) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 5 +MACHO-ARM-NEXT: Name: __data (5F 5F 64 61 74 61 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x3C +MACHO-ARM-NEXT: Size: 0x4 +MACHO-ARM-NEXT: Offset: 724 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x0 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT: Section { +MACHO-ARM-NEXT: Index: 6 +MACHO-ARM-NEXT: Name: __nl_symbol_ptr (5F 5F 6E 6C 5F 73 79 6D 62 6F 6C 5F 70 74 72 00) +MACHO-ARM-NEXT: Segment: __DATA (5F 5F 44 41 54 41 00 00 00 00 00 00 00 00 00 00) +MACHO-ARM-NEXT: Address: 0x40 +MACHO-ARM-NEXT: Size: 0x8 +MACHO-ARM-NEXT: Offset: 728 +MACHO-ARM-NEXT: Alignment: 2 +MACHO-ARM-NEXT: RelocationOffset: 0x0 +MACHO-ARM-NEXT: RelocationCount: 0 +MACHO-ARM-NEXT: Type: 0x6 +MACHO-ARM-NEXT: Attributes [ (0x0) +MACHO-ARM-NEXT: ] +MACHO-ARM-NEXT: Reserved1: 0x0 +MACHO-ARM-NEXT: Reserved2: 0x0 +MACHO-ARM-NEXT: } +MACHO-ARM-NEXT:] |