aboutsummaryrefslogtreecommitdiff
path: root/sys/amd64/include/param.h
Commit message (Collapse)AuthorAgeFilesLines
* sys: Remove $FreeBSD$: one-line .h patternWarner Losh2023-08-231-1/+0
| | | | | | | Remove /^\s*\*+\s*\$FreeBSD\$.*$\n/ Similar commit in current: (cherry picked from commit 2ff63af9b88c)
* amd64: Add MD bits for KASANMark Johnston2021-11-011-0/+4
| | | | | | | | | | | | | | | - Initialize KASAN before executing SYSINITs. - Add a GENERIC-KASAN kernel config, akin to GENERIC-KCSAN. - Increase the kernel stack size if KASAN is enabled. Some of the ASAN instrumentation increases stack usage and it's enough to trigger stack overflows in ZFS. - Mark the trapframe as valid in interrupt handlers if it is assigned to td_intr_frame. Otherwise, an interrupt in a function which creates a poisoned alloca region can trigger false positives. Sponsored by: The FreeBSD Foundation (cherry picked from commit f115c0612131d8f939f6f357f57bdd85bd6a59de)
* amd64: clean up empty lines in .c and .h filesMateusz Guzik2020-09-011-2/+0
| | | | Notes: svn path=/head/; revision=365067
* amd64 pmap: LA57 AKA 5-level pagingKonstantin Belousov2020-08-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since LA57 was moved to the main SDM document with revision 072, it seems that we should have a support for it, and silicons are coming. This patch makes pmap support both LA48 and LA57 hardware. The selection of page table level is done at startup, kernel always receives control from loader with 4-level paging. It is not clear how UEFI spec would adapt LA57, for instance it could hand out control in LA57 mode sometimes. To switch from LA48 to LA57 requires turning off long mode, requesting LA57 in CR4, then re-entering long mode. This is somewhat delicate and done in pmap_bootstrap_la57(). AP startup in LA57 mode is much easier, we only need to toggle a bit in CR4 and load right value in CR3. I decided to not change kernel map for now. Single PML5 entry is created that points to the existing kernel_pml4 (KML4Phys) page, and a pml5 entry to create our recursive mapping for vtopte()/vtopde(). This decision is motivated by the fact that we cannot overcommit for KVA, so large space there is unusable until machines start providing wider physical memory addressing. Another reason is that I do not want to break our fragile autotuning, so the KVA expansion is not included into this first step. Nice side effect is that minidumps are compatible. On the other hand, (very) large address space is definitely immediately useful for some userspace applications. For userspace, numbering of pte entries (or page table pages) is always done for 5-level structures even if we operate in 4-level mode. The pmap_is_la57() function is added to report the mode of the specified pmap, this is done not to allow simultaneous 4-/5-levels (which is not allowed by hw), but to accomodate for EPT which has separate level control and in principle might not allow 5-leve EPT despite x86 paging supports it. Anyway, it does not seems critical to have 5-level EPT support now. Tested by: pho (LA48 hardware) Reviewed by: alc Sponsored by: The FreeBSD Foundation Differential revision: https://reviews.freebsd.org/D25273 Notes: svn path=/head/; revision=364527
* Define MAXCPU consistently between the kernel and KLDs.Mark Johnston2020-02-051-1/+1
| | | | | | | | | | | | | | | | This reverts r177661. The change is no longer very useful since out-of-tree KLDs will be built to target SMP kernels anyway. Moveover it breaks the KBI in !SMP builds since cpuset_t's layout depends on the value of MAXCPU, and several kernel interfaces, notably smp_rendezvous_cpus(), take a cpuset_t as a parameter. PR: 243711 Reviewed by: jhb, kib Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D23512 Notes: svn path=/head/; revision=357585
* spdx: initial adoption of licensing ID tags.Pedro F. Giffuni2017-11-181-0/+2
| | | | | | | | | | | | | | | | | | | | The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts. Special thanks to Wind River for providing access to "The Duke of Highlander" tool: an older (2014) run over FreeBSD tree was useful as a starting point. Initially, only tag files that use BSD 4-Clause "Original" license. RelNotes: yes Differential Revision: https://reviews.freebsd.org/D13133 Notes: svn path=/head/; revision=325966
* Make the sleepq chain hash size configurable per-arch and bump on amd64.Mateusz Guzik2017-10-221-0/+4
| | | | | | | | | | | While here cache-align chains. This shortens longest found chain during poudriere -j 80 from 32 to 16. Pushing this higher up will probably require allocation on boot. Notes: svn path=/head/; revision=324870
* Drop CACHE_LINE_SIZE to 64 bytes on x86Conrad Meyer2017-08-281-1/+1
| | | | | | | | | | | | | | | | | | | | | The actual cache line size has always been 64 bytes. The 128 number arose as an optimization for Core 2 era Intel processors. By default (configurable in BIOS), these CPUs would prefetch adjacent cache lines unintelligently. Newer CPUs prefetch more intelligently. The latest Core 2 era CPU was introduced in September 2008 (Xeon 7400 series, "Dunnington"). If you are still using one of these CPUs, especially in a multi-socket configuration, consider locating the "adjacent cache line prefetch" option in BIOS and disabling it. Reported by: mjg Reviewed by: np Discussed with: jhb Sponsored by: Dell EMC Isilon Notes: svn path=/head/; revision=322989
* Enable DEVICE_NUMA with up to 8 domains by default on amd64.John Baldwin2016-04-121-1/+1
| | | | | | | | | | | | 8 memory domains should handle a quad-socket board with dual-domain processors. Reviewed by: kib Relnotes: maybe? Differential Revision: https://reviews.freebsd.org/D5893 Notes: svn path=/head/; revision=297877
* Use single instance of the identical INKERNEL() and PMC_IN_KERNEL()Konstantin Belousov2015-07-021-0/+3
| | | | | | | | | | | | | | | | macros on amd64 and i386. Move the definition to machine/param.h. kgdb defines INKERNEL() too, the conflict is resolved by renaming kgdb version to PINKERNEL(). On i386, correct the lowest kernel address. After the shared page was introduced, USRSTACK no longer points to the last user address + 1 [*] Submitted by: Oliver Pinter [*] Sponsored by: The FreeBSD Foundation MFC after: 1 week Notes: svn path=/head/; revision=285041
* Bump MAXCPU on amd64 from 64 to 256. In practice APIC only permits 255John Baldwin2014-08-201-1/+1
| | | | | | | | | CPUs (IDs 0 through 254). Getting above that limit requires x2APIC. MFC after: 1 month Notes: svn path=/head/; revision=270223
* Increase the TSS limit by one byte. The processor requires an additional byteNeel Natu2014-05-141-0/+6
| | | | | | | | | | | | | | with all bits set to 1 beyond the I/O permission bitmap. Prior to this change accessing I/O ports [0xFFF8-0xFFFF] would trigger a #GP fault even though the I/O bitmap allowed access to those ports. For more details see section "I/O Permission Bit Map" in the Intel SDM, Vol 1. Reviewed by: kib Notes: svn path=/head/; revision=266093
* Rename VM_NDOMAIN into MAXMEMDOM and move it into machine/param.h inAttilio Rao2013-05-071-0/+4
| | | | | | | | | | | | order to match the MAXCPU concept. The change should also be useful for consolidation and consistency. Sponsored by: EMC / Isilon storage division Obtained from: jeff Reviewed by: alc Notes: svn path=/head/; revision=250338
* As discussed on -current, remove the hardcoded default maxswzone.Dag-Erling Smørgrav2012-08-141-8/+0
| | | | | | | MFC after: 3 weeks Notes: svn path=/head/; revision=239255
* Bump MAXCPU for amd64, ia64 and XLP mips appropriately.Attilio Rao2011-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | From now on, default values for FreeBSD will be 64 maxiumum supported CPUs on amd64 and ia64 and 128 for XLP. All the other architectures seem already capped appropriately (with the exception of sparc64 which needs further support on jalapeno flavour). Bump __FreeBSD_version in order to reflect KBI/KPI brekage introduced during the infrastructure cleanup for supporting MAXCPU > 32. This covers cpumask_t retiral too. The switch is considered completed at the present time, so for whatever bug you may experience that is reconducible to that area, please report immediately. Requested by: marcel, jchandra Tested by: pluknet, sbruno Approved by: re (kib) Notes: svn path=/head/; revision=224217
* Add the possibility to specify from kernel configs MAXCPU value.Attilio Rao2011-07-191-0/+2
| | | | | | | | | | | | | This patch is going to help in cases like mips flavours where you want a more granular support on MAXCPU. No MFC is previewed for this patch. Tested by: pluknet Approved by: re (kib) Notes: svn path=/head/; revision=224207
* When compat32 binary asks for the value of hw.machine_arch, report theKonstantin Belousov2010-07-221-0/+3
| | | | | | | | | | | | | | name of 32bit sibling architecture instead of the host one. Do the same for hw.machine on amd64. Add a safety belt debug.adaptive_machine_arch sysctl, to turn the substitution off. Reviewed by: jhb, nwhitehorn MFC after: 2 weeks Notes: svn path=/head/; revision=210369
* Uppercase the UL suffix on a constant, so Flexelint doesn't worry thatPoul-Henning Kamp2009-11-161-1/+1
| | | | | | | | 'u1' might have been intended. No, that does not make sense and yes I have told them. Notes: svn path=/head/; revision=199319
* Add a new sysctl for reporting all of the supported page sizes.Alan Cox2009-09-181-0/+2
| | | | | | | | Reviewed by: jhb MFC after: 3 weeks Notes: svn path=/head/; revision=197316
* Get rid of the _NO_NAMESPACE_POLLUTION kludge by creating anPoul-Henning Kamp2009-09-081-14/+3
| | | | | | | | architecture specific include file containing the _ALIGN* stuff which <sys/socket.h> needs. Notes: svn path=/head/; revision=196994
* Move multi-include protection back up to the top of the file andPoul-Henning Kamp2009-09-081-4/+4
| | | | | | | name after the physical file rather than the aliased name. Notes: svn path=/head/; revision=196968
* Cleanup ALIGNED_POINTER:Sam Leffler2009-07-051-10/+7
| | | | | | | | | | | | | | o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v) o define as "1" on amd64 and i386 where there is no restriction o make the type returned consistent with ALIGN o remove _ALIGNED_POINTER o make associated comments consistent Reviewed by: bde, imp, marcel Approved by: re (kensmith) Notes: svn path=/head/; revision=195376
* Now that amd64's kernel map is 512GB (SVN rev 192216), there is no reasonAlan Cox2009-06-081-9/+0
| | | | | | | | | to cap its buffer map at 1GB. MFC after: 6 weeks Notes: svn path=/head/; revision=193729
* Bump CACHE_LINE_SIZE to 128 for x86. Intel's manuals explicitly recommendJohn Baldwin2009-05-181-1/+1
| | | | | | | using 128 byte alignment for locks. (See IA-32 SDM Vol 3A 7.11.6.7) Notes: svn path=/head/; revision=192331
* Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizingRobert Watson2009-04-201-2/+0
| | | | | | | | | | | | | | | a fair number of static data structures, making this an unlikely option to try to change without also changing source code. [1] Change default cache line size on ia64, sparc64, and sun4v to 128 bytes, as this was what rtld-elf was already using on those platforms. [2] Suggested by: bde [1], jhb [2] MFC after: 2 weeks Notes: svn path=/head/; revision=191309
* Add description and cautionary note regarding CACHE_LINE_SIZE.Robert Watson2009-04-191-0/+4
| | | | | | | | MFC after: 2 weeks Suggested by: alc Notes: svn path=/head/; revision=191278
* For each architecture, define CACHE_LINE_SHIFT and a derivedRobert Watson2009-04-191-0/+4
| | | | | | | | | | | | | | | | CACHE_LINE_SIZE constant. These constants are intended to over-estimate the cache line size, and be used at compile-time when a run-time tuning alternative isn't appropriate or available. Defaults for all architectures are 64 bytes, except powerpc where it is 128 bytes (used on G5 systems). MFC after: 2 weeks Discussed on: arch@ Notes: svn path=/head/; revision=191276
* Bump MAXCPU to 32 now that 32 CPU x86 systems exist.John Baldwin2008-10-011-1/+1
| | | | | | | | Tested by: rwatson, mdtansca Approved by: peter Notes: svn path=/head/; revision=183525
* Enhance pmap_change_attr() with the ability to demote 1GB page mappings.Alan Cox2008-08-011-0/+1
| | | | Notes: svn path=/head/; revision=181112
* Increase the ceiling on the size of the buffer map.Alan Cox2008-07-191-1/+1
| | | | Notes: svn path=/head/; revision=180623
* When building a kernel module, define MAXCPU the same as SMP soJohn Birrell2008-03-271-1/+1
| | | | | | | that modules work with and without SMP. Notes: svn path=/head/; revision=177661
* By popular demand, move __HAVE_ACPI and __PCI_REROUTE_INTERRUPT intoWarner Losh2006-01-091-0/+3
| | | | | | | | | | | param.h. Per request, I've placed these just after the _NO_NAMESPACE_POLLUTION ifndef. I've not renamed anything yet, but may since we don't need the __. Submitted by: bde, jhb, scottl, many others. Notes: svn path=/head/; revision=154128
* Drop _MACHINE_ARCH and _MACHINE defines (not to be confused withRuslan Ermilov2005-12-061-7/+0
| | | | | | | | | | MACHINE_ARCH and MACHINE). Their purpose was to be able to test in cpp(1), but cpp(1) only understands integer type expressions. Using such unsupported expressions introduced a number of subtle bugs, which were discovered by compiling with -Wundef. Notes: svn path=/head/; revision=153168
* Increase MAXCPU to 16 in SMP kernels so that APIC IDs from 0 to 15 areJohn Baldwin2005-06-291-1/+1
| | | | | | | | | | | allowed for CPUs. Tested by: amd64 at cybernetwork dot org Approved by: re (scottl) MFC after: 1 week Notes: svn path=/head/; revision=147653
* MFi386: whitespace, copyright header, etc updatesPeter Wemm2005-01-211-1/+0
| | | | Notes: svn path=/head/; revision=140553
* Begin all license/copyright comments with /*-Warner Losh2005-01-051-1/+1
| | | | Notes: svn path=/head/; revision=139731
* Remove UAREA_PAGES.David Schultz2004-11-201-1/+0
| | | | | | | Reviewed by: arch@ Notes: svn path=/head/; revision=137914
* Turn PREEMPTION into a kernel option. Make sure that it's defined ifScott Long2004-09-021-5/+0
| | | | | | | | | FULL_PREEMPTION is defined. Add a runtime warning to ULE if PREEMPTION is enabled (code inspired by the PREEMPTION warning in kern_switch.c). This is a possible MT5 candidate. Notes: svn path=/head/; revision=134649
* Turn off PREEMPTION by default while it gets debugged. It's been causingScott Long2004-08-011-0/+3
| | | | | | | | 4 weeks of problems including deadlocks and instant panics. Note that the real bugs are likely in the scheduler. Notes: svn path=/head/; revision=132961
* Implement preemption of kernel threads natively in the scheduler ratherJohn Baldwin2004-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | than as one-off hacks in various other parts of the kernel: - Add a function maybe_preempt() that is called from sched_add() to determine if a thread about to be added to a run queue should be preempted to directly. If it is not safe to preempt or if the new thread does not have a high enough priority, then the function returns false and sched_add() adds the thread to the run queue. If the thread should be preempted to but the current thread is in a nested critical section, then the flag TDF_OWEPREEMPT is set and the thread is added to the run queue. Otherwise, mi_switch() is called immediately and the thread is never added to the run queue since it is switch to directly. When exiting an outermost critical section, if TDF_OWEPREEMPT is set, then clear it and call mi_switch() to perform the deferred preemption. - Remove explicit preemption from ithread_schedule() as calling setrunqueue() now does all the correct work. This also removes the do_switch argument from ithread_schedule(). - Do not use the manual preemption code in mtx_unlock if the architecture supports native preemption. - Don't call mi_switch() in a loop during shutdown to give ithreads a chance to run if the architecture supports native preemption since the ithreads will just preempt DELAY(). - Don't call mi_switch() from the page zeroing idle thread for architectures that support native preemption as it is unnecessary. - Native preemption is enabled on the same archs that supported ithread preemption, namely alpha, i386, and amd64. This change should largely be a NOP for the default case as committed except that we will do fewer context switches in a few cases and will avoid the run queues completely when preempting. Approved by: scottl (with his re@ hat) Notes: svn path=/head/; revision=131481
* Be a little more consistent in the naming of the PML4 defines.Peter Wemm2004-06-071-3/+3
| | | | Notes: svn path=/head/; revision=130218
* Since we have additional kernel virtual address space, allow the bufferAlan Cox2003-12-201-1/+1
| | | | | | | cache to grow to 400M bytes. Notes: svn path=/head/; revision=123692
* Initial landing of SMP support for FreeBSD/amd64.Peter Wemm2003-11-171-0/+4
| | | | | | | | | | | | | | | | | | | - This is heavily derived from John Baldwin's apic/pci cleanup on i386. - I have completely rewritten or drastically cleaned up some other parts. (in particular, bootstrap) - This is still a WIP. It seems that there are some highly bogus bioses on nVidia nForce3-150 boards. I can't stress how broken these boards are. I have a workaround in mind, but right now the Asus SK8N is broken. The Gigabyte K8NPro (nVidia based) is also mind-numbingly hosed. - Most of my testing has been with SCHED_ULE. SCHED_4BSD works. - the apic and acpi components are 'standard'. - If you have an nVidia nForce3-150 board, you are stuck with 'device atpic' in addition, because they somehow managed to forget to connect the 8254 timer to the apic, even though its in the same silicon! ARGH! This directly violates the ACPI spec. Notes: svn path=/head/; revision=122849
* KSTACK_PAGES is a global option.Peter Wemm2003-07-311-0/+2
| | | | Notes: svn path=/head/; revision=118236
* Migrate the thread stack management functions from the machine-dependentAlan Cox2003-06-141-1/+1
| | | | | | | | | | | | | | | | | | | to the machine-independent parts of the VM. At the same time, this introduces vm object locking for the non-i386 platforms. Two details: 1. KSTACK_GUARD has been removed in favor of KSTACK_GUARD_PAGES. The different machine-dependent implementations used various combinations of KSTACK_GUARD and KSTACK_GUARD_PAGES. To disable guard page, set KSTACK_GUARD_PAGES to 0. 2. Remove the (unnecessary) clearing of PG_ZERO in vm_thread_new. In 5.x, (but not 4.x,) PG_ZERO can only be set if VM_ALLOC_ZERO is passed to vm_page_alloc() or vm_page_grab(). Notes: svn path=/head/; revision=116355
* Fix ALIGNED_POINTER(). sizeof((u_int32_t)) is not legal C.Peter Wemm2003-06-041-1/+1
| | | | Notes: svn path=/head/; revision=115795
* Major pmap rework to take advantage of the larger address space on amd64Peter Wemm2003-05-231-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | systems. Of note: - Implement a direct mapped region using 2MB pages. This eliminates the need for temporary mappings when getting ptes. This supports up to 512GB of physical memory for now. This should be enough for a while. - Implement a 4-tier page table system. Most of the infrastructure is there for 128TB of userland virtual address space, but only 512GB is presently enabled due to a mystery bug somewhere. The design of this was heavily inspired by the alpha pmap.c. - The kernel is moved into the negative address space(!). - The kernel has 2GB of KVM available. - Provide a uma memory allocator to use the direct map region to take advantage of the 2MB TLBs. - Fixed some assumptions in the bus_space macros about the ability to fit virtual addresses in an 'int'. Notable missing things: - pmap_growkernel() should be able to grow to 512GB of KVM by expanding downwards below kernbase. The kernel must be at the top 2GB of the negative address space because of gcc code generation strategies. - need to fix the >512GB user vm code. Approved by: re (blanket) Notes: svn path=/head/; revision=115251
* Commit MD parts of a loosely functional AMD64 port. This is based onPeter Wemm2003-05-011-16/+47
| | | | | | | | | | | | | | | | | | | | | | | | | a heavily stripped down FreeBSD/i386 (brutally stripped down actually) to attempt to get a stable base to start from. There is a lot missing still. Worth noting: - The kernel runs at 1GB in order to cheat with the pmap code. pmap uses a variation of the PAE code in order to avoid having to worry about 4 levels of page tables yet. - It boots in 64 bit "long mode" with a tiny trampoline embedded in the i386 loader. This simplifies locore.s greatly. - There are still quite a few fragments of i386-specific code that have not been translated yet, and some that I cheated and wrote dumb C versions of (bcopy etc). - It has both int 0x80 for syscalls (but using registers for argument passing, as is native on the amd64 ABI), and the 'syscall' instruction for syscalls. int 0x80 preserves all registers, 'syscall' does not. - I have tried to minimize looking at the NetBSD code, except in a couple of places (eg: to find which register they use to replace the trashed %rcx register in the syscall instruction). As a result, there is not a lot of similarity. I did look at NetBSD a few times while debugging to get some ideas about what I might have done wrong in my first attempt. Notes: svn path=/head/; revision=114349
* Repocopy from x86_64/... to amd64/...Peter Wemm2003-04-301-8/+7
| | | | | | | | | Rename visible x86_64 references to amd64. Kill MID_MACHINE, its a.out specific, the only platform that supports it is i386. All of the other platforms should remove it too. Notes: svn path=/head/; revision=114346
* Initiate deorbit burn for the i386-only a.out related support. Moves arePeter Wemm2002-09-171-7/+0
| | | | | | | | | | | | | | | | | | under way to move the remnants of the a.out toolchain to ports. As the comment in src/Makefile said, this stuff is deprecated and one should not expect this to remain beyond 4.0-REL. It has already lasted WAY beyond that. Notable exceptions: gcc - I have not touched the a.out generation stuff there. ldd/ldconfig - still have some code to interface with a.out rtld. old as/ld/etc - I have not removed these yet, pending their move to ports. some includes - necessary for ldd/ldconfig for now. Tested on: i386 (extensively), alpha Notes: svn path=/head/; revision=103436
generated by cgit v1.3 (git 2.53.0) at 2026-08-01 10:49:34 +0000