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* MFC 199549, 199997, 204158, 207673, and 208901.Kenneth D. Merry2010-06-112-30/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bring in a number of netfront changes: r199549 | jhb Remove commented out reference to if_watchdog and an assignment of zero to if_timer. Reviewed by: scottl r199997 | gibbs Add media ioctl support and link notifications so that devd will attempt to run dhclient on a netfront (xn) device that is setup for DHCP in /etc/rc.conf. PR: kern/136251 (fixed differently than the submitted patch) r204158 | kmacy - make printf conditional - fix witness warnings by making configuration lock a mutex r207673 | joel Switch to our preferred 2-clause BSD license. Approved by: kmacy r208901 | ken A number of netfront fixes and stability improvements: - Re-enable TSO. This was broken previously due to CSUM_TSO clearing the CSUM_TCP flag, so our checksum flags were incorrectly set going to the netback driver. That was fixed in r206844 in tcp_output.c, so we can turn TSO back on here. - Fix the way transmit slots are calculated, so that we can't overfill the ring. - Avoid sending packets with more fragments/segments than netback can handle. The Linux netback code can only handle packets of MAX_SKB_FRAGS, which turns out to be 18 on machines with 4K pages. We can easily generate packets with 32 or so fragments with TSO turned on. Right now the solution is just to drop the packets (since netback doesn't seem to handle it gracefully), but we should come up with a way to allow a driver to tell the TCP stack the maximum number of fragments it can handle in a single packet. - Fix the way the consumer is tracked in the receive path. It could get out of sync fairly easily. - Use standard Xen ring macros to make it clearer how netfront is using the rings. - Get rid of Linux-ish negative errno return values. - Added more documentation to the driver. - Refactored code to make it easier to read. - Some other minor fixes. Reviewed by: gibbs Sponsored by: Spectra Logic Approved by: re (bz) Notes: svn path=/stable/8/; revision=209061
* MFC r207329, r208716:Attilio Rao2010-06-011-3/+18
| | | | | | | | | | | | | | - Extract the IODEV_PIO interface from ia64 and make it MI. - On i386 and amd64 the old behaviour is kept but multithreaded processes must use the new interface in order to work well. - Support for the other architectures is greatly improved. Sponsored by: Sandvine Incorporated Approved by: re (kib, bz) Notes: svn path=/stable/8/; revision=208723
* MFC r207676:Konstantin Belousov2010-05-121-0/+2
| | | | | | | | Add definitions for Intel AESNI CPUID bits and print the capabilities on boot. Notes: svn path=/stable/8/; revision=207955
* MFC r204051 (by imp):Konstantin Belousov2010-05-081-0/+3
| | | | | | | | | | | | | | | | | | n64 has a different size for KINFO_PROC_SIZE. Approved by: imp MFC r207152: Move the constants specifying the size of struct kinfo_proc into machine-specific header files. Add KINFO_PROC32_SIZE for struct kinfo_proc32 for architectures providing COMPAT_FREEBSD32. Add CTASSERT for the size of struct kinfo_proc32. MFC r207269: Style: use #define<TAB> instead of #define<SPACE>. Notes: svn path=/stable/8/; revision=207793
* MFC r206089, r206684:Fabien Thomas2010-04-161-1/+10
| | | | | | | | | | | | | | | | - Support for uncore counting events: one fixed PMC with the uncore domain clock, 8 programmable PMC. - Westmere based CPU (Xeon 5600, Corei7 980X) support. - New man pages with events list for core and uncore. - Updated Corei7 events with Intel 253669-033US December 2009 doc. There is some removed events in the documentation, they have been kept in the code but documented in the man page as obsolete. - Offcore response events can be setup with rsp token. Sponsored by: NETASQ Notes: svn path=/stable/8/; revision=206701
* MFC 205851:John Baldwin2010-04-141-2/+3
| | | | | | | | | Add a handler for the local APIC error interrupt. For now it just prints out the current value of the local APIC error register when the interrupt fires. Notes: svn path=/stable/8/; revision=206598
* MFC r206459:Konstantin Belousov2010-04-131-0/+4
| | | | | | | | Handle a case when non-canonical address is loaded into the fsbase or gsbase MSR. Notes: svn path=/stable/8/; revision=206554
* MFC r205014,205015:Nathan Whitehorn2010-04-072-0/+10
| | | | | | | | | | | | | | | | Provide groundwork for 32-bit binary compatibility on non-x86 platforms, for upcoming 64-bit PowerPC and MIPS support. This renames the COMPAT_IA32 option to COMPAT_FREEBSD32, removes some IA32-specific code from MI parts of the kernel and enhances the freebsd32 compatibility code to support big-endian platforms. This MFC is required for MFCs of later changes to the freebsd32 compatibility from HEAD. Requested by: kib Notes: svn path=/stable/8/; revision=206336
* MFC r204907, r204913, r205402, r205573, r205573Alan Cox2010-04-052-0/+2
| | | | | | | | | | Implement AMD's recommended workaround for Erratum 383 on Family 10h processors. Enable machine check exceptions by default. Notes: svn path=/stable/8/; revision=206183
* MFC r204641, r204753:Attilio Rao2010-03-301-1/+1
| | | | | | | | | | Improving the clocks auto-tunning by firstly checking if the atrtc may be correctly initialized and just then assign to softclock/profclock. Sponsored by: Sandvine Incorporated Notes: svn path=/stable/8/; revision=205875
* MFC r199852, r202387, r202441, r202534:Attilio Rao2010-03-291-1/+7
| | | | | | | | | | | | Handling all the three clocks with the LAPIC may lead to aliasing for softclock and profclock. Revert the change when the LAPIC started taking charge of all three of them. Sponsored by: Sandvine Incorporated Notes: svn path=/stable/8/; revision=205836
* MFC 205214:John Baldwin2010-03-262-0/+17
| | | | | | | | | | | | | - Extend the machine check record structure to include several fields useful for parsing model-specific and other fields in machine check events including the global machine check capabilities and status registers, CPU identification, and the FreeBSD CPU ID. - Report these added fields in the console log of a machine check so that a record structure can be reconstituted from the console messages. - Parse new architectural errors including memory controller errors. Notes: svn path=/stable/8/; revision=205689
* MFC 205210,205448:John Baldwin2010-03-261-22/+22
| | | | | | | | Remove unneeded type specifiers from 64-bit constants. The compiler infers their natural type from the constants' values. Notes: svn path=/stable/8/; revision=205687
* MFC rev. 202097:Marcel Moolenaar2010-01-221-0/+1
| | | | | | | Use io(4) for I/O port access on ia64, rather than through sysarch(2). Notes: svn path=/stable/8/; revision=202776
* MFC 198134,198149,198170,198171,198391,200948:John Baldwin2010-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Add a facility for associating optional descriptions with active interrupt handlers. This is primarily intended as a way to allow devices that use multiple interrupts (e.g. MSI) to meaningfully distinguish the various interrupt handlers. - Add a new BUS_DESCRIBE_INTR() method to the bus interface to associate a description with an active interrupt handler setup by BUS_SETUP_INTR. It has a default method (bus_generic_describe_intr()) which simply passes the request up to the parent device. - Add a bus_describe_intr() wrapper around BUS_DESCRIBE_INTR() that supports printf(9) style formatting using var args. - Reserve MAXCOMLEN bytes in the intr_handler structure to hold the name of an interrupt handler and copy the name passed to intr_event_add_handler() into that buffer instead of just saving the pointer to the name. - Add a new intr_event_describe_handler() which appends a description string to an interrupt handler's name. - Implement support for interrupt descriptions on amd64, i386, and sparc64 by having the nexus(4) driver supply a custom bus_describe_intr method that invokes a new intr_describe() MD routine which in turn looks up the associated interrupt event and invokes intr_event_describe_handler(). Notes: svn path=/stable/8/; revision=202762
* MFC r200033: mca: improve status checking, recording and reportingAndriy Gapon2009-12-191-0/+1
| | | | Notes: svn path=/stable/8/; revision=200711
* MFC r199968: x86 cpu features: add MOVBE reporting and flagAndriy Gapon2009-12-081-0/+1
| | | | Notes: svn path=/stable/8/; revision=200262
* - MFC r199067,199215,199253Jun Kuriyama2009-11-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add hw.clflush_disable loader tunable to avoid panic (trap 9) at map_invalidate_cache_range() even if CPU is not Intel. - This tunable can be set to -1 (default), 0 and 1. -1 is same as current behavior, which automatically disable CLFLUSH on Intel CPUs without CPUID_SS (should be occured on Xen only). You can specify 1 when this panic happened on non-Intel CPUs (such as AMD's). Because disabling CLFLUSH may reduce performance, you can try with setting 0 on Intel CPUs without SS to use CLFLUSH feature. - Amd64 init_secondary() calls initializecpu() while curthread is still not properly set up. r199067 added the call to TUNABLE_INT_FETCH() to initializecpu() that results in hang because AP are started when kernel environment is already dynamic and thus needs to acquire mutex, that is too early in AP start sequence to work. Extract the code that should be executed only once, because it sets up global variables, from initializecpu() to initializecpucache(), and call the later only from hammer_time() executed on BSP. Now, TUNABLE_INT_FETCH() is done only once at BSP at the early boot stage. Notes: svn path=/stable/8/; revision=199648
* MFC r197070:Attilio Rao2009-11-061-2/+2
| | | | | | | | | | | | | | Consolidate CPUID to CPU family/model macros for amd64 and i386 to reduce unnecessary #ifdef's for shared code between them. This MFC should unbreak the kernel build breakage introduced by r198977. Reported by: kib Pointy hat to: me Notes: svn path=/stable/8/; revision=198989
* MFC 197647: cpufunc.h: unify/correct style of c extension namesAndriy Gapon2009-11-011-3/+3
| | | | Notes: svn path=/stable/8/; revision=198760
* MFC r197316Alan Cox2009-10-311-0/+2
| | | | | | | Add a new sysctl for reporting all of the supported page sizes. Notes: svn path=/stable/8/; revision=198728
* MFC 197439:John Baldwin2009-10-291-0/+3
| | | | | | | | | | | | | Extract the code to find and map the MADT ACPI table during early kernel startup and genericize it so it can be reused to map other tables as well: - Add a routine to walk a list of ACPI subtables such as those used in the APIC and SRAT tables in the MI acpi(4) driver. - Move the routines for mapping and unmapping an ACPI table as well as mapping the RSDT or XSDT and searching for a table with a given signature out into acpica_machdep.c for both amd64 and i386. Notes: svn path=/stable/8/; revision=198610
* MFC r197933:Konstantin Belousov2009-10-201-0/+6
| | | | | | | | | | | | Define architectural load bases for PIE binaries. MFC r198203 (by marius): Change load base for sparc to match default gcc memory layout model. Approved by: re (kensmith) Notes: svn path=/stable/8/; revision=198283
* MFC r197803, r197824, r197910:Attilio Rao2009-10-121-42/+58
| | | | | | | | | | | | | | | | Per their definition, atomic instructions used in conjuction with memory barriers should also ensure that the compiler doesn't reorder paths where they are used. GCC, however, does that aggressively, even in presence of volatile operands. The most reliable way GCC offers for avoid instructions reordering is clobbering "memory". Not all our memory barriers, right now, clobber memory for GCC-like compilers. Fix these cases. Approved by: re (kib) Notes: svn path=/stable/8/; revision=197985
* Adjust the handling of the local APIC PMC interrupt vector:John Baldwin2009-08-142-1/+3
| | | | | | | | | | | | | | | | | | | - Provide lapic_disable_pmc(), lapic_enable_pmc(), and lapic_reenable_pmc() routines in the local APIC code that the hwpmc(4) driver can use to manage the local APIC PMC interrupt vector. - Do not enable the local APIC PMC interrupt vector by default when HWPMC_HOOKS is enabled. Instead, the hwpmc(4) driver explicitly enables the interrupt when it is succesfully initialized and disables the interrupt when it is unloaded. This avoids enabling the interrupt on unsupported CPUs which may result in spurious NMIs. Reported by: rnoland Reviewed by: jkoshy Approved by: re (kib) MFC after: 2 weeks Notes: svn path=/stable/8/; revision=196223
* MFC r196196:Attilio Rao2009-08-132-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Completely remove the option STOP_NMI from the kernel. This option has proven to have a good effect when entering KDB by using a NMI, but it completely violates all the good rules about interrupts disabled while holding a spinlock in other occasions. This can be the cause of deadlocks on events where a normal IPI_STOP is expected. * Add an new IPI called IPI_STOP_HARD on all the supported architectures. This IPI is responsible for sending a stop message among CPUs using a privileged channel when disponible. In other cases it just does match a normal IPI_STOP. Right now the IPI_STOP_HARD functionality uses a NMI on ia32 and amd64 architectures, while on the other has a normal IPI_STOP effect. It is responsibility of maintainers to eventually implement an hard stop when necessary and possible. * Use the new IPI facility in order to implement a new userend SMP kernel function called stop_cpus_hard(). That is specular to stop_cpu() but it does use the privileged channel for the stopping facility. * Let KDB use the newly introduced function stop_cpus_hard() and leave stop_cpus() for all the other cases * Disable interrupts on CPU0 when starting the process of APs suspension. * Style cleanup and comments adding This patch should fix the reboot/shutdown deadlocks many users are constantly reporting on mailing lists. Please don't forget to update your config file with the STOP_NMI option removal Reviewed by: jhb Tested by: pho, bz, rink Approved by: re (kib) Notes: svn path=/stable/8/; revision=196198
* When the page caching attributes are changed, after new mapping isKonstantin Belousov2009-07-222-0/+15
| | | | | | | | | | | | | | | | | | established, OS shall flush the caches on all processors that may have used the mapping previously. This operation is not needed if processors support self-snooping. If not, but clflush instruction is implemented on the CPU, series of the clflush can be used on the mapping region. Otherwise, we have to flush the whole cache. The later operation is very expensive, and AMD-made CPUs do not have self-snooping. Implement cache flush for remapped region by using clflush for amd64, when supported by CPU. Proposed and reviewed by: alc Approved by: re (kensmith) Notes: svn path=/head/; revision=195820
* Add support to the virtual memory system for configuring machine-Alan Cox2009-07-122-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dependent memory attributes: Rename vm_cache_mode_t to vm_memattr_t. The new name reflects the fact that there are machine-dependent memory attributes that have nothing to do with controlling the cache's behavior. Introduce vm_object_set_memattr() for setting the default memory attributes that will be given to an object's pages. Introduce and use pmap_page_{get,set}_memattr() for getting and setting a page's machine-dependent memory attributes. Add full support for these functions on amd64 and i386 and stubs for them on the other architectures. The function pmap_page_set_memattr() is also responsible for any other machine-dependent aspects of changing a page's memory attributes, such as flushing the cache or updating the direct map. The uses include kmem_alloc_contig(), vm_page_alloc(), and the device pager: kmem_alloc_contig() can now be used to allocate kernel memory with non-default memory attributes on amd64 and i386. vm_page_alloc() and the device pager will set the memory attributes for the real or fictitious page according to the object's default memory attributes. Update the various pmap functions on amd64 and i386 that map pages to incorporate each page's memory attributes in the mapping. Notes: (1) Inherent to this design are safety features that prevent the specification of inconsistent memory attributes by different mappings on amd64 and i386. In addition, the device pager provides a warning when a device driver creates a fictitious page with memory attributes that are inconsistent with the real page that the fictitious page is an alias for. (2) Storing the machine-dependent memory attributes for amd64 and i386 as a dedicated "int" in "struct md_page" represents a compromise between space efficiency and the ease of MFCing these changes to RELENG_7. In collaboration with: jhb Approved by: re (kib) Notes: svn path=/head/; revision=195649
* Restore the segment registers and segment base MSRs for amd64 syscallKonstantin Belousov2009-07-091-1/+2
| | | | | | | | | | | | | | | | | | | | return path only when neither thread was context switched while executing syscall code nor syscall explicitely modified LDT or MSRs. Save segment registers in trap handlers before interrupts are enabled, to not allow context switches to happen before registers are saved. Use separated byte in pcb for indication of fast/full return, since pcb_flags are not synchronized with context switches. The change puts back syscall microbenchmark numbers that were slowed down after commit of the support for LDT on amd64. Reviewed by: jeff Tested (and tested, and tested ...) by: pho Approved by: re (kensmith) Notes: svn path=/head/; revision=195486
* Cleanup ALIGNED_POINTER:Sam Leffler2009-07-051-10/+7
| | | | | | | | | | | | | | o add to platforms where it was missing (arm, i386, powerpc, sparc64, sun4v) o define as "1" on amd64 and i386 where there is no restriction o make the type returned consistent with ALIGN o remove _ALIGNED_POINTER o make associated comments consistent Reviewed by: bde, imp, marcel Approved by: re (kensmith) Notes: svn path=/head/; revision=195376
* Improve the handling of cpuset with interrupts.John Baldwin2009-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | - For x86, change the interrupt source method to assign an interrupt source to a specific CPU to return an error value instead of void, thus allowing it to fail. - If moving an interrupt to a CPU fails due to a lack of IDT vectors in the destination CPU, fail the request with ENOSPC rather than panicing. - For MSI interrupts on x86 (but not MSI-X), only allow cpuset to be used on the first interrupt in a group. Moving the first interrupt in a group moves the entire group. - Use the icu_lock to protect intr_next_cpu() on x86 instead of the intr_table_lock to fix a LOR introduced in the last set of MSI changes. - Add a new privilege PRIV_SCHED_CPUSET_INTR for using cpuset with interrupts. Previously, binding an interrupt to a CPU only performed a privilege check if the interrupt had an interrupt thread. Interrupts without a thread could be bound by non-root users as a result. - If an interrupt event's assign_cpu method fails, then restore the original cpuset mask for the associated interrupt thread. Approved by: re (kib) Notes: svn path=/head/; revision=195249
* Correct the #endif comment.Alan Cox2009-06-261-1/+1
| | | | | | | | Noticed by: jmallett Approved by: re (kib) Notes: svn path=/head/; revision=195060
* This change is the next step in implementing the cache control functionalityAlan Cox2009-06-261-0/+45
| | | | | | | | | | | | | | required by video card drivers. Specifically, this change introduces vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all architectures. In addition, this changes adds a vm_cache_mode_t parameter to kmem_alloc_contig() and vm_phys_alloc_contig(). These will be the interfaces for allocating mapped kernel memory and physical memory, respectively, with non-default cache modes. In collaboration with: jhb Notes: svn path=/head/; revision=195033
* Fix kernels compiled without SMP support. Make intr_next_cpu() availableJohn Baldwin2009-06-251-2/+0
| | | | | | | | | | for UP kernels but as a stub that always returns the single CPU's local APIC ID. Reported by: kib Notes: svn path=/head/; revision=195002
* - Restore the behavior of pre-allocating IDT vectors for MSI interrupts.John Baldwin2009-06-251-0/+3
| | | | | | | | | | | | | | | | | | | | | This is mostly important for the multiple MSI message case where the IDT vectors for the entire group need to be allocated together. This also restores the assumptions made by the PCI bus code that it could invoke PCIB_MAP_MSI() once MSI vectors were allocated. - To avoid whiplash with CPU assignments, change the way that CPUs are assigned to interrupt sources on activation. Instead of assigning the CPU via pic_assign_cpu() before calling enable_intr(), allow the different interrupt source drivers to ask the MD interrupt code which CPU to use when they allocate an IDT vector. I/O APIC interrupt pins do this in their pic_enable_intr() routines giving the same behavior as before. MSI sources do it when the IDT vectors are allocated during msi_alloc() and msix_alloc(). - Change the intr_table_lock from an sx lock to a mutex. Tested by: rnoland Notes: svn path=/head/; revision=194985
* Eliminate dead code. These definitions should have been deleted with theAlan Cox2009-06-221-10/+0
| | | | | | | | | introduction of i686_mem.c in r45405. Merge adjacent #ifdef _KERNEL/#endif blocks. Notes: svn path=/head/; revision=194611
* Now that amd64's kernel map is 512GB (SVN rev 192216), there is no reasonAlan Cox2009-06-081-9/+0
| | | | | | | | | to cap its buffer map at 1GB. MFC after: 6 weeks Notes: svn path=/head/; revision=193729
* Bump CACHE_LINE_SIZE to 128 for x86. Intel's manuals explicitly recommendJohn Baldwin2009-05-181-1/+1
| | | | | | | using 128 byte alignment for locks. (See IA-32 SDM Vol 3A 7.11.6.7) Notes: svn path=/head/; revision=192331
* correct range in commentKip Macy2009-05-161-1/+1
| | | | | | | pointed out by alc Notes: svn path=/head/; revision=192227
* update vm map commentKip Macy2009-05-161-1/+0
| | | | | | | pointed out by Larry Rosenman Notes: svn path=/head/; revision=192224
* Increase default kernel map to 512GBKip Macy2009-05-161-2/+2
| | | | | | | | I briefly discussed this with alc. It could lead to problems for greater than 64GB. However, that seems unlikely in practice. Notes: svn path=/head/; revision=192216
* FreeBSD right now support 32 CPUs on all the architectures at least.Attilio Rao2009-05-141-4/+4
| | | | | | | | | | | | | | | | | | | With the arrival of 128+ cores it is necessary to handle more than that. One of the first thing to change is the support for cpumask_t that needs to handle more than 32 bits masking (which happens now). Some places, however, still assume that cpumask_t is a 32 bits mask. Fix that situation by using always correctly cpumask_t when needed. While here, remove the part under STOP_NMI for the Xen support as it is broken in any case. Additively make ipi_nmi_pending as static. Reviewed by: jhb, kmacy Tested by: Giovanni Trematerra <giovanni dot trematerra at gmail dot com> Notes: svn path=/head/; revision=192114
* Implement simple machine check support for amd64 and i386.John Baldwin2009-05-132-0/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - For CPUs that only support MCE (the machine check exception) but not MCA (i.e. Pentium), all this does is print out the value of the machine check registers and then panic when a machine check exception occurs. - For CPUs that support MCA (the machine check architecture), the support is a bit more involved. - First, there is limited support for decoding the CPU-independent MCA error codes in the kernel, and the kernel uses this to output a short description of any machine check events that occur. - When a machine check exception occurs, all of the MCx banks on the current CPU are scanned and any events are reported to the console before panic'ing. - To catch events for correctable errors, a periodic timer kicks off a task which scans the MCx banks on all CPUs. The frequency of these checks is controlled via the "hw.mca.interval" sysctl. - Userland can request an immediate scan of the MCx banks by writing a non-zero value to "hw.mca.force_scan". - If any correctable events are encountered, the appropriate details are stored in a 'struct mca_record' (defined in <machine/mca.h>). The "hw.mca.count" is a count of such records and each record may be queried via the "hw.mca.records" tree by specifying the record index (0 .. count - 1) as the next name in the MIB similar to using PIDs with the kern.proc.* sysctls. The idea is to export machine check events to userland for more detailed processing. - The periodic timer and hw.mca sysctls are only present if the CPU supports MCA. Discussed with: emaste (briefly) MFC after: 1 month Notes: svn path=/head/; revision=192050
* Fix XENHVM build.Doug Rabson2009-05-061-1/+1
| | | | Notes: svn path=/head/; revision=191847
* Rename statclock_disable variable to atrtcclock_disable that it actually is,Alexander Motin2009-05-031-1/+0
| | | | | | | | | | | | | | | | and hide it inside of atrtc driver. Add new tunable hint.atrtc.0.clock controlling it. Setting it to 0 disables using RTC clock as stat-/ profclock sources. Teach i386 and amd64 SMP platforms to emulate stat-/profclocks using i8254 hardclock, when LAPIC and RTC clocks are disabled. This allows to reduce global interrupt rate of idle system down to about 100 interrupts per core, permitting C3 and deeper C-states provide maximum CPU power efficiency. Notes: svn path=/head/; revision=191766
* Add support for using i8254 and rtc timers as event sources for amd64 SMPAlexander Motin2009-05-022-1/+10
| | | | | | | system. Redistribute hard-/stat-/profclock events to other CPUs using IPIs. Notes: svn path=/head/; revision=191744
* - Add support for cpuid leaf 0xb. This allows us to determine theJeff Roberson2009-04-292-4/+7
| | | | | | | | | | | topology of nehalem/corei7 based systems. - Remove the cpu_cores/cpu_logical detection from identcpu. - Describe the layout of the system in cpu_mp_announce(). Sponsored by: Nokia Notes: svn path=/head/; revision=191648
* Don't conditionally define CACHE_LINE_SHIFT, as we anticipate sizingRobert Watson2009-04-201-2/+0
| | | | | | | | | | | | | | | a fair number of static data structures, making this an unlikely option to try to change without also changing source code. [1] Change default cache line size on ia64, sparc64, and sun4v to 128 bytes, as this was what rtld-elf was already using on those platforms. [2] Suggested by: bde [1], jhb [2] MFC after: 2 weeks Notes: svn path=/head/; revision=191309
* Add description and cautionary note regarding CACHE_LINE_SIZE.Robert Watson2009-04-191-0/+4
| | | | | | | | MFC after: 2 weeks Suggested by: alc Notes: svn path=/head/; revision=191278
* For each architecture, define CACHE_LINE_SHIFT and a derivedRobert Watson2009-04-191-0/+4
| | | | | | | | | | | | | | | | CACHE_LINE_SIZE constant. These constants are intended to over-estimate the cache line size, and be used at compile-time when a run-time tuning alternative isn't appropriate or available. Defaults for all architectures are 64 bytes, except powerpc where it is 128 bytes (used on G5 systems). MFC after: 2 weeks Discussed on: arch@ Notes: svn path=/head/; revision=191276
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