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* [arswitch] extend the debug support to be configurable at runtime.Adrian Chadd2016-08-075-38/+80
| | | | | | | | | | | | | | | | | | * remove the DEBUG ifdef; defining it is too far reaching throughout the whole system; * add a bitmask in the softc for controlling debugging; * .. enable said debugging as a sysctl; * add bitmaps for register access, reset and vlans. TODO: * Now that the debug statements are configurable, we definitely could do with more debugging * Move the debugging into the top-level etherswitch driver and have sub-drivers obey. Notes: svn path=/head/; revision=303810
* [etherswitch] add in an initial API for controlling per-port LED behaviour.Adrian Chadd2016-08-045-4/+146
| | | | | | | | | This is just implemented for the AR8327 for now. Submitted by: Dan Nelson <dnelson_1901@yahoo.com> Notes: svn path=/head/; revision=303751
* Update my TODO items.Adrian Chadd2016-07-262-0/+3
| | | | Notes: svn path=/head/; revision=303339
* Remove erroneous lock assertionsStanislav Galabov2016-06-061-2/+0
| | | | | | | | | | | In mediatek etherswitch support, functions mtkswitch_reg_write32_mt7621 and mtkswitch_reg_read32_mt7621 are called without locks held, so lock assertions fail. Remove the lock assertions. Sponsored by: Smartcom - Bulgaria AD Notes: svn path=/head/; revision=301497
* Fix issues with mt762x etherswitch driverStanislav Galabov2016-05-172-9/+20
| | | | | | | | | | | Fix issues that crept in with initial import. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6393 Notes: svn path=/head/; revision=300012
* Introduce basic etherswitch support for Ralink SoCsStanislav Galabov2016-05-166-0/+2103
| | | | | | | | | | | | | | | | This revision introduces basic support for the internal ESW switch found Ralink/Mediatek SoCs such as RT3050, RT3352, RT5350, MT7628; and GSW found in MT7620 and MT7621. It only supports 802.1q VLANs and doesn't support external PHYs at the moment (only the ones that are built into the switch itself). Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D6348 Notes: svn path=/head/; revision=299910
* sys/dev: minor spelling fixes.Pedro F. Giffuni2016-05-031-1/+1
| | | | | | | Most affect comments, very few have user-visible effects. Notes: svn path=/head/; revision=298955
* Cleanup unnecessary semicolons from the kernel.Pedro F. Giffuni2016-04-104-4/+4
| | | | | | | Found with devel/coccinelle. Notes: svn path=/head/; revision=297793
* [mdio] migrate mdiobus out of etherswitch and into a top-level device of its ↵Adrian Chadd2015-12-2615-188/+12
| | | | | | | | | | | | | | own. The mdio driver interface is generally useful for devices that require MDIO without the full MII bus interface. This lifts the driver/interface out of etherswitch(4), and adds a mdio(4) man page. Submitted by: Landon Fuller <landon@landonf.org> Differential Revision: https://reviews.freebsd.org/D4606 Notes: svn path=/head/; revision=292738
* [arswitch] bump the number of ports on the ar934x internal switch.Adrian Chadd2015-12-151-2/+2
| | | | | | | It indeed has more ports by default. Notes: svn path=/head/; revision=292248
* Introduce e6000sw etherswitch supportZbigniew Bodek2015-10-252-0/+1161
| | | | | | | | | | | | | | | | | | | | | Add e6000sw driver supporting Marvell 88E6352, 88E6172, 88E6176 switches. It needs to be attached to mdio interface, exporting SMI access functionality. e6000sw supports port-based VLAN configuration, per-port media changing, accessing PHY and switch registers. e6000sw attaches miibuses and PHY drivers as children. Instead of typical tick as callout, kthread-based tick is used. This combined with SX locks allows MDIO read/write calls to sleep. It is expected, because this hardware requires long delays in SMI read/write procedures, which can not be handled by busy-waiting. Reviewed by: adrian Obtained from: Semihalf Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Differential revision: https://reviews.freebsd.org/D3902 Notes: svn path=/head/; revision=289947
* AR8327: Fix up the ability to configure the vlangroup configuration for the ↵Adrian Chadd2015-10-201-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | CPU port I messed up when doing the reset_vlans method - setting vid[0] = 1 here was making it 'hidden' from configuration (as it needed ETHERSWITCH_VID_VALID as well) and so there was no way to configure vlangroup0. In per-port VLAN mode, vlangroup0 is for the CPU port (port0). Now, it normally wouldn't really matter - the CPU port thus sees all other ports. However there are two CPU ports on the AR8327 and so port0 (arge0) was seeing all traffic on port6 (arge1). If you thus tried to use arge1/port6 for anything (eg a WAN port) in a bridge group then things would very upset very quickly. Whilst here, add a comment to remind myself that yes, it'd be nice if we could specify a boot-time switch config. Tested: * AP135 reference platform w/ AR8327N switch Notes: svn path=/head/; revision=289665
* Fix French typos in etherswitch.Rui Paulo2015-04-181-61/+61
| | | | Notes: svn path=/head/; revision=281686
* Turns out the AR933x looks like the AR7240/AR7241 switch as far as VLANAdrian Chadd2015-03-281-1/+0
| | | | | | | | | | | | | configuration is concerned. So, remove the now-erroneous comment. Tested: * AR9331 - Carambola2, with transmitting dot1q tagged packets around. Notes: svn path=/head/; revision=280796
* Commit 802.1q configuration support for the AR8327.Adrian Chadd2015-03-134-35/+217
| | | | | | | | | | | | | | | | | | | | | | | | | This is slightly different to the other switches - the VLAN table (VTU) programs in the vlan port mapping /and/ the port config (tagged, untagged, passthrough, any.) So: * Add VTU operations to program the VTU (vlan table) * abstract out the mirror-disable function so it's .. well, a function. * setup the port to have a dot1q configuration for dot1q - the port security is VLAN (not per-port VLAN) and requires an entry in the VLAN table; * add set_dot1q / get_dot1q to program the VLAN table; * since the tagged/untagged ports are now programmed into the VTU, rather than global - plumb the ports /and/ untagged ports bitmaps through the arswitch API. Tested: * AP135 - QCA9558 SoC + AR8327N switch Notes: svn path=/head/; revision=279943
* Methodise a couple more of the VLAN methods.Adrian Chadd2015-03-084-12/+18
| | | | Notes: svn path=/head/; revision=279797
* Add per-port vlan support for the AR8327.Adrian Chadd2015-03-086-31/+145
| | | | | | | | | | | | | | | | | | | | | All the per-port support is really doing is applying a port visibility mask to each of the switchports. Everything still look like a single portgroup (vlan id 1), but the per-port visibility mask is modified. Whilst I'm here, also add some initial dot1q support - the pvid stuff is doing the right thing, but it's not useful without the rest of the VLAN table programming. It's enough for me to be able to use the LAN/WAN port distinction on the AP135, where there isn't (for now!) a dedicated PHY for the "WAN" port. Tested: * AP135, QCA9558 SoC + AR8327 switch Notes: svn path=/head/; revision=279790
* Fix up support for the AR8327.Adrian Chadd2015-03-086-66/+237
| | | | | | | | | | | | | | | | | | | | | | | * Even though I got the registers around "right", it seems I'm not tickling the MDIO access correctly for the internal PHY bus. Some of the switches are fine poking at the external PHY registers; others aren't. So, enable direct PHY bus access for the AR8327, and leave the existing code in place for the others. * Go and shuffle the register access around. Whilst here, restore the 2ms delay if changing page. * Comment out some of the stub printf()s; there's some upcoming work to add port VLAN support. Tested: * AP135 development board * Carambola2 - AR9331 SoC Notes: svn path=/head/; revision=279767
* AR8327: Disable energy-efficient ethernet support in the PHYs.Adrian Chadd2015-03-011-18/+31
| | | | | | | | | | | | I noticed that openwrt/linux does this, citing "instability", so until they figure out why I'm going to disable it here as well. Tested: * QCA AP135 - QCA955x SoC + AR8327 switch. Notes: svn path=/head/; revision=279492
* Bump the port mask on the AR8327 ethernet switch from 0x3f to 0x7f.Adrian Chadd2015-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So, it turns out that the AR8327 has 7 ports internally: * GMAC0 / external (CPU) MAC0 * GMAC1 / port1 -> GMAC5 / port5: external switch port PHYs * GMAC6 / external (CPU) MAC1 Now, depending upon how things are wired up, the second CPU port (MAC1) can be wired to either the switch (port6), or through port5's PHY, bypassing the GMAC+switch entirely. Ie, it can pretend to be a boring PHY, saving system designers from having to include a separate PHY for a "WAN" port. Here's the rub - the AP135 board (QCA955x SoC) hooks up arge0 to the second CPU port on the AR8327, but it's hooked up as RGMII. So, in order to hook it up to the rest of the switch, it isn't configured as a separate PHY - OpenWRT has it setup as connected via RGMII to GMAC6 and (I'm guessing) it's set to be a WAN port by configuring up port-based VLANs or something. Thus, with a port mask of 0x3f, GMAC6 was never allowed to receive traffic from any other port. It could transmit fine, but not receive anything. So, now it works enough for me to continue doing board bootstrapping. Note, this isn't enough to make the QCA955x + AR8327 work - there's a bunch of uncommitted work to both the platform SoC (interrupt handling, ethernet, etc) and the ethernet switch (register access space, setup, etc) that needs to happen. However, this particular change is also relevant to other SoCs, like the AR934x and AR7161, both of which can be glued to this switch. Tested: * AP135 development board TODO: * Figure out whether I can somehow abuse another port mode to have this be a pass-through PHY, or whether I should just create some more boot time hints to explicitly set up port-based isolation so this works in a more useful way by default. Notes: svn path=/head/; revision=279490
* Add another register definition for the AR8327.Adrian Chadd2015-02-281-0/+3
| | | | | | | Obtained from: OpenWRT Notes: svn path=/head/; revision=279420
* Add another revision of the AR8327.Adrian Chadd2014-07-261-0/+1
| | | | Notes: svn path=/head/; revision=269147
* Revert r268543.Rui Paulo2014-07-1210-10/+10
| | | | | | | We should probably fix sys/gpio.h instead. Notes: svn path=/head/; revision=268564
* Move iic.h to sys/ so that it's automatically installed in /usr/include/sys.Rui Paulo2014-07-1210-10/+10
| | | | | | | | | | This lets us call iic(4) ioctls without needing the kernel source code and follows the same model of GPIO. MFC after: 3 weeks Notes: svn path=/head/; revision=268543
* Allow the PVID setting on CPU port.Luiz Otavio O Souza2014-07-051-2/+8
| | | | | | | | | Return our static list of supported media for the CPU port. Tested on TP-Link 1043ND. Notes: svn path=/head/; revision=268294
* Initialize the switch vlan table at attachment.Luiz Otavio O Souza2014-07-031-7/+33
| | | | | | | | | | | | | | | | | | Update some comments on code, specifying the correct vlans used on switch setup. Advertise the proper switch operation mode (the rtl8366rb only support dot1q vlans). This fixes the breakage that i introduced on r249752 and make the rtl8366rb switch works again with etherswitchcfg(8). Tested on TP-Link 1043ND. Tested by: me, Harm Weites (harm at weites.com) Notes: svn path=/head/; revision=268233
* Fix the reported status for the switch CPU port which was (wrongly)Luiz Otavio O Souza2014-07-012-2/+2
| | | | | | | | | reporting half-duplex link. Tested on TP-Link WR1043ND. Notes: svn path=/head/; revision=268094
* Add the CPU port flag to the CPU port on rtl8366 (port 5).Luiz Otavio O Souza2014-07-012-4/+8
| | | | | | | | | Do not allow any media change on the switch CPU port. Tested on TP-Link WR1043ND. Notes: svn path=/head/; revision=268093
* Fix the build with debug enabled and remove a variable used only at switchLuiz Otavio O Souza2014-05-092-11/+4
| | | | | | | initialization, it is nonsense keep it around without futher use. Notes: svn path=/head/; revision=265770
* Fix a bug on ip17x switch initialization which will fail as soon as youLuiz Otavio O Souza2014-05-092-2/+2
| | | | | | | | | | disable the debug and diagnosis options from current. We must wait 2ms after the switch reset and not 2us. Tested on RB433UAH. Notes: svn path=/head/; revision=265767
* Add a description here.Adrian Chadd2014-03-021-0/+3
| | | | Notes: svn path=/head/; revision=262684
* Set all of the ports into the same vlangroup; there's only one vlangroupAdrian Chadd2014-03-021-5/+4
| | | | | | | | | | | | | | | (pvid=1) and we already configure them to send to other ports. Setting pvid=portnum would mean that there were separate vlangroups for each ports, but 'leaking' into other ports. The result? All port traffic flooded to all other port traffic. Tested: * DB120, AR9344 + AR8327 switch Notes: svn path=/head/; revision=262683
* Add ATU flush support.Adrian Chadd2014-03-023-1/+79
| | | | | | | | | | | | | | | | | | | | | | The OpenWRT AR8xxx switch support flushes the ATU (address translation unit) after each port link 'up' status change. I've modified this to just flush on any port transition. Whilst here, bump the number of ports on the AR8327 to 6, rather than the default of 5. It's DB120 specific; I'll go and make this configurable later. There's some debugging code in here still; I am still debugging whether this is or isn't working fully. Tested: * DB120, AR9344 + AR8327 switch Obtained from: OpenWRT Notes: svn path=/head/; revision=262681
* Add AR8216 era ATU management/configuration register definitions.Adrian Chadd2014-03-021-6/+31
| | | | | | | Obtained from: OpenWRT Notes: svn path=/head/; revision=262680
* (I think!) make the AR8327 switch correctly handle traffic.Adrian Chadd2014-03-011-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does four things: * it globally disables mirroring; * it globally sets the mirroring on each port to be disabled; * the initial port setup now programs a portmask for the port to allow transmission (forwarding) to all other ports bar itself; * the vlan setup path now programs the portmask for the port to allow transmission (forwarding) to all other ports bar itself. Before this, I hard-coded the portmask to 0x3f which would mean all ports (bar port 6, which currently isn't hooked up to anything.) This means that traffic would be duplicated back out the port it received it. I bet this wasn't .. optimal. In any case, this _seems_ to make DHCP from my macosx laptop work through this access point. I'll do some further testing to ensure it's actually working correctly on all my devices. Tested: * DB120, AR8327 switch Notes: svn path=/head/; revision=262653
* Be paranoid about bit operations here.Adrian Chadd2014-03-011-1/+1
| | | | Notes: svn path=/head/; revision=262634
* Remove now dead code.Adrian Chadd2014-03-011-10/+0
| | | | Notes: svn path=/head/; revision=262632
* Add missing includes and remove two unused ones.Christian Brueffer2014-02-273-2/+9
| | | | | | | | Reviewed by: loos MFC after: 1 week Notes: svn path=/head/; revision=262571
* Add LED setup support for the AR8327.Adrian Chadd2014-02-261-0/+67
| | | | | | | | | | | Tested: * DB120 Obtained from: OpenWRT Notes: svn path=/head/; revision=262519
* Add in the SGMII configuration code. The DB120 doesn't use it, so IAdrian Chadd2014-02-261-2/+55
| | | | | | | | | have no way to evaluate it. Obtained from: OpenWRT Notes: svn path=/head/; revision=262517
* Undo the DB120 hard-coded values in the AR8327 code and fetch it fromAdrian Chadd2014-02-261-22/+209
| | | | | | | | | | | the hints environment. Tested: * DB120 Notes: svn path=/head/; revision=262514
* Add in port0/port6 configuration as part of the platform data code path.Adrian Chadd2014-02-242-45/+59
| | | | | | | | | | | | | It's still hardcoded (for db120) but it is now hardcoded in all the same place (ie, the pdata path.) The port config/status code now checks port0/port6 as appropriate to configure things. Tested: * Qualcomm Atheros DB120, AR8327 switch. Notes: svn path=/head/; revision=262433
* Link the AR8327 to the build.Adrian Chadd2014-02-241-0/+3
| | | | Notes: svn path=/head/; revision=262431
* Add initial AR8327 support.Adrian Chadd2014-02-242-0/+564
| | | | | | | | | | | | | | | | | | | | This is (almost!) enough to actually probe, attach, configure a default port group and do some basic work. It's also totally hard-coded for the Qualcomm Atheros DB120 board - it doesn't yet have any of the code from OpenWRT which parses extra configuration data to know how to program the switch. The LED stuff is also missing. But, it's enough to facilitate board, PHY, switch and VLAN bringup, so I am committing it now. Tested: * Qualcomm Atheros DB120 Obtained from: OpenWRT Notes: svn path=/head/; revision=262430
* Methodize the arswitch VLAN routines.Adrian Chadd2014-02-243-18/+35
| | | | | | | | | | These differ per chipset family in subtle and evil ways. It becomes very noticable on the AR8327 where the layout is just plain wrong. Notes: svn path=/head/; revision=262429
* * Ensure enough ports/phys are available for both the AR8327 and previousAdrian Chadd2014-02-241-3/+16
| | | | | | | | | | | switches. * Add some new VLAN HAL methods that will be used by the VLAN configuration code. The AR933x and later switches use slightly different register layouts (even though the driver currently doesn't support it.) Notes: svn path=/head/; revision=262428
* Extract out the port VLAN flags/setup code and throw it into two newAdrian Chadd2014-02-191-43/+70
| | | | | | | | | | | | | | HAL methods. This allows the AR8327 code to override it as appropriate. Tested: * DB120 - AR8327 and AR9340 on-board switch; only running 'etherswitchcfg' to check configs. The actual VLAN programming wasn't tested. Notes: svn path=/head/; revision=262208
* Add methods for the VLAN port set/get routines.Adrian Chadd2014-02-191-0/+6
| | | | | | | | | | | | The registers (and perhaps the flags) are different for the AR8327, so I'll stub those out until they're written. Tested: * DB120 - both on-chip AR9340 and AR8327 switches. Notes: svn path=/head/; revision=262207
* Turn the port init function into a HAL method and initialise it to theAdrian Chadd2014-02-191-4/+14
| | | | | | | | | default port init code. This needs to be overridden for the AR8327. Notes: svn path=/head/; revision=262206
* Teach the PHY register path about the different MDIO bus addressAdrian Chadd2014-02-191-5/+17
| | | | | | | | | | | for the AR8327. Tested: * AR8327, DB120 Notes: svn path=/head/; revision=262205
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