From 8dbf0223f3b0aaa055ff8d6827e2c26ca9ebf9ae Mon Sep 17 00:00:00 2001 From: Marius Strobl Date: Sat, 20 Jan 2007 14:57:51 +0000 Subject: Add macros for the individual divisor bits as some MC146818A-compatible chips also use them for different purposes. --- sys/dev/mc146818/mc146818reg.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/sys/dev/mc146818/mc146818reg.h b/sys/dev/mc146818/mc146818reg.h index 3aab55f56a5a..7e17aa248d3a 100644 --- a/sys/dev/mc146818/mc146818reg.h +++ b/sys/dev/mc146818/mc146818reg.h @@ -82,6 +82,9 @@ #define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ #define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ +#define MC_REGA_DV0 0x10 /* Divisor 0 */ +#define MC_REGA_DV1 0x20 /* Divisor 1 */ +#define MC_REGA_DV2 0x40 /* Divisor 2 */ #define MC_REGA_UIP 0x80 /* Update in progress; read only. */ #define MC_REGB 0xb /* Control register B */ @@ -139,7 +142,7 @@ * Time base (divisor select) constants (Control register A) */ #define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ -#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ -#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ -#define MC_BASE_NONE 0x60 /* actually, both of these reset */ -#define MC_BASE_RESET 0x70 +#define MC_BASE_1_MHz MC_REGA_DV0 /* 1MHz crystal */ +#define MC_BASE_32_KHz MC_REGA_DV1 /* 32KHz crystal */ +#define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */ +#define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0) -- cgit v1.3