From a7fe922b98bb45be7dce7c1cfe668ec27eeddc74 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 17 Aug 2016 19:33:52 +0000 Subject: Vendor import of llvm release_39 branch r278877: https://llvm.org/svn/llvm-project/llvm/branches/release_39@278877 --- lib/Analysis/InstructionSimplify.cpp | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'lib/Analysis/InstructionSimplify.cpp') diff --git a/lib/Analysis/InstructionSimplify.cpp b/lib/Analysis/InstructionSimplify.cpp index 0cb2c78afb40..aeaf9388579c 100644 --- a/lib/Analysis/InstructionSimplify.cpp +++ b/lib/Analysis/InstructionSimplify.cpp @@ -3400,7 +3400,10 @@ static Value *SimplifySelectInst(Value *CondVal, Value *TrueVal, return TrueVal; if (const auto *ICI = dyn_cast(CondVal)) { - unsigned BitWidth = Q.DL.getTypeSizeInBits(TrueVal->getType()); + // FIXME: This code is nearly duplicated in InstCombine. Using/refactoring + // decomposeBitTestICmp() might help. + unsigned BitWidth = + Q.DL.getTypeSizeInBits(TrueVal->getType()->getScalarType()); ICmpInst::Predicate Pred = ICI->getPredicate(); Value *CmpLHS = ICI->getOperand(0); Value *CmpRHS = ICI->getOperand(1); @@ -4274,7 +4277,8 @@ static bool replaceAndRecursivelySimplifyImpl(Instruction *I, Value *SimpleV, // Gracefully handle edge cases where the instruction is not wired into any // parent block. - if (I->getParent()) + if (I->getParent() && !I->isEHPad() && !isa(I) && + !I->mayHaveSideEffects()) I->eraseFromParent(); } else { Worklist.insert(I); @@ -4302,7 +4306,8 @@ static bool replaceAndRecursivelySimplifyImpl(Instruction *I, Value *SimpleV, // Gracefully handle edge cases where the instruction is not wired into any // parent block. - if (I->getParent()) + if (I->getParent() && !I->isEHPad() && !isa(I) && + !I->mayHaveSideEffects()) I->eraseFromParent(); } return Simplified; -- cgit v1.3