From 1e7804dbd25b8dbf534c850355d70ad215206f4b Mon Sep 17 00:00:00 2001 From: Roman Divacky Date: Fri, 1 Jan 2010 10:31:22 +0000 Subject: Update LLVM to 92395. --- lib/CodeGen/MachineVerifier.cpp | 21 ++------------------- 1 file changed, 2 insertions(+), 19 deletions(-) (limited to 'lib/CodeGen/MachineVerifier.cpp') diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp index 917d0535b2b8..077231904631 100644 --- a/lib/CodeGen/MachineVerifier.cpp +++ b/lib/CodeGen/MachineVerifier.cpp @@ -365,24 +365,6 @@ void MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); - // Start with minimal CFG sanity checks. - MachineFunction::const_iterator MBBI = MBB; - ++MBBI; - if (MBBI != MF->end()) { - // Block is not last in function. - if (!MBB->isSuccessor(MBBI)) { - // Block does not fall through. - if (MBB->empty()) { - report("MBB doesn't fall through but is empty!", MBB); - } - } - } else { - // Block is last in function. - if (MBB->empty()) { - report("MBB is last in function but is empty!", MBB); - } - } - // Call AnalyzeBranch. If it succeeds, there several more conditions to check. MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; @@ -553,7 +535,8 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { report("Explicit operand marked as implicit", MO, MONum); } } else { - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic()) + // ARM adds %reg0 operands to indicate predicates. We'll allow that. + if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } -- cgit v1.3