From 344a3780b2e33f6ca763666c380202b18aab72a3 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 29 Jul 2021 22:15:26 +0200 Subject: Vendor import of llvm-project main 88e66fa60ae5, the last commit before the upstream release/13.x branch was created. --- llvm/lib/CodeGen/RegisterClassInfo.cpp | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'llvm/lib/CodeGen/RegisterClassInfo.cpp') diff --git a/llvm/lib/CodeGen/RegisterClassInfo.cpp b/llvm/lib/CodeGen/RegisterClassInfo.cpp index 0488db3d09cb..797899fb5b86 100644 --- a/llvm/lib/CodeGen/RegisterClassInfo.cpp +++ b/llvm/lib/CodeGen/RegisterClassInfo.cpp @@ -68,6 +68,8 @@ void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { } CalleeSavedRegs = CSR; + RegCosts = TRI->getRegisterCosts(*MF); + // Different reserved registers? const BitVector &RR = MF->getRegInfo().getReservedRegs(); if (Reserved.size() != RR.size() || RR != Reserved) { @@ -100,8 +102,8 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { unsigned N = 0; SmallVector CSRAlias; - unsigned MinCost = 0xff; - unsigned LastCost = ~0u; + uint8_t MinCost = uint8_t(~0u); + uint8_t LastCost = uint8_t(~0u); unsigned LastCostChange = 0; // FIXME: Once targets reserve registers instead of removing them from the @@ -112,7 +114,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { // Remove reserved registers from the allocation order. if (Reserved.test(PhysReg)) continue; - unsigned Cost = TRI->getCostPerUse(PhysReg); + uint8_t Cost = RegCosts[PhysReg]; MinCost = std::min(MinCost, Cost); if (CalleeSavedAliases[PhysReg] && @@ -132,7 +134,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { // CSR aliases go after the volatile registers, preserve the target's order. for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) { unsigned PhysReg = CSRAlias[i]; - unsigned Cost = TRI->getCostPerUse(PhysReg); + uint8_t Cost = RegCosts[PhysReg]; if (Cost != LastCost) LastCostChange = N; RCI.Order[N++] = PhysReg; @@ -149,7 +151,7 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) RCI.ProperSubClass = true; - RCI.MinCost = uint8_t(MinCost); + RCI.MinCost = MinCost; RCI.LastCostChange = LastCostChange; LLVM_DEBUG({ -- cgit v1.3