From f65dcba83ce5035ab88a85fe17628b447eb56e1b Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 2 Dec 2021 22:02:54 +0100 Subject: Vendor import of llvm-project main llvmorg-14-init-11187-g222442ec2d71. --- llvm/lib/Target/AMDGPU/GCNRegPressure.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'llvm/lib/Target/AMDGPU/GCNRegPressure.cpp') diff --git a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp index 3456f9a6156c..82c09378acac 100644 --- a/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp +++ b/llvm/lib/Target/AMDGPU/GCNRegPressure.cpp @@ -74,11 +74,11 @@ unsigned GCNRegPressure::getRegKind(Register Reg, assert(Reg.isVirtual()); const auto RC = MRI.getRegClass(Reg); auto STI = static_cast(MRI.getTargetRegisterInfo()); - return STI->isSGPRClass(RC) ? - (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) : - STI->hasAGPRs(RC) ? - (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) : - (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); + return STI->isSGPRClass(RC) + ? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE) + : STI->isAGPRClass(RC) + ? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE) + : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE); } void GCNRegPressure::inc(unsigned Reg, -- cgit v1.3