From 706b4fc47bbc608932d3b491ae19a3b9cde9497b Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Fri, 17 Jan 2020 20:45:01 +0000 Subject: Vendor import of llvm-project master e26a78e70, the last commit before the llvmorg-11-init tag, from which release/10.x was branched. --- llvm/lib/Target/AMDGPU/R600InstrInfo.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'llvm/lib/Target/AMDGPU/R600InstrInfo.cpp') diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 04a5e93f6213..346296c77377 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -60,8 +60,8 @@ bool R600InstrInfo::isVector(const MachineInstr &MI) const { void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const DebugLoc &DL, unsigned DestReg, - unsigned SrcReg, bool KillSrc) const { + const DebugLoc &DL, MCRegister DestReg, + MCRegister SrcReg, bool KillSrc) const { unsigned VectorComponents = 0; if ((R600::R600_Reg128RegClass.contains(DestReg) || R600::R600_Reg128VerticalRegClass.contains(DestReg)) && @@ -541,7 +541,7 @@ R600InstrInfo::fitsReadPortLimitations(const std::vector &IG, std::vector>> IGSrcs; ValidSwizzle.clear(); - unsigned ConstCount; + unsigned ConstCount = 0; BankSwizzle TransBS = ALU_VEC_012_SCL_210; for (unsigned i = 0, e = IG.size(); i < e; ++i) { IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount)); -- cgit v1.3