From c0981da47d5696fe36474fcf86b4ce03ae3ff818 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Fri, 19 Nov 2021 21:06:13 +0100 Subject: Vendor import of llvm-project main llvmorg-14-init-10186-gff7f2cfa959b. --- llvm/lib/Target/ARM/ARMSubtarget.cpp | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'llvm/lib/Target/ARM/ARMSubtarget.cpp') diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 90f1b693fec6..36c4bbaafcbf 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -295,6 +295,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexA77: case CortexA78: case CortexA78C: + case CortexA710: case CortexR4: case CortexR4F: case CortexR5: @@ -389,7 +390,13 @@ bool ARMSubtarget::enableMachineScheduler() const { return useMachineScheduler(); } -bool ARMSubtarget::enableSubRegLiveness() const { return EnableSubRegLiveness; } +bool ARMSubtarget::enableSubRegLiveness() const { + if (EnableSubRegLiveness.getNumOccurrences()) + return EnableSubRegLiveness; + // Enable SubRegLiveness for MVE to better optimize s subregs for mqpr regs + // and q subregs for qqqqpr regs. + return hasMVEIntegerOps(); +} // This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool ARMSubtarget::enablePostRAScheduler() const { -- cgit v1.3