From 1ee5b3b422a780518a7a6cf55cec8a98738d3fc3 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 9 Jan 2009 10:45:04 +0000 Subject: Fix confusing naming of Marvell ARM CPU specific routines. - The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon. - Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does not require dedicated routines. This will be accompanied by a file rename commit. --- sys/arm/include/cpufunc.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) (limited to 'sys/arm/include') diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h index 0e3b33b6f835..74f21e41188d 100644 --- a/sys/arm/include/cpufunc.h +++ b/sys/arm/include/cpufunc.h @@ -377,17 +377,17 @@ extern unsigned arm10_dcache_sets_inc; extern unsigned arm10_dcache_index_max; extern unsigned arm10_dcache_index_inc; -u_int feroceon_control_ext (u_int, u_int); -void feroceon_setttb (u_int); -void feroceon_dcache_wbinv_range (vm_offset_t, vm_size_t); -void feroceon_dcache_inv_range (vm_offset_t, vm_size_t); -void feroceon_dcache_wb_range (vm_offset_t, vm_size_t); -void feroceon_idcache_wbinv_range (vm_offset_t, vm_size_t); - -void feroceon_l2cache_wbinv_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_inv_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_wb_range (vm_offset_t, vm_size_t); -void feroceon_l2cache_wbinv_all (void); +u_int sheeva_control_ext (u_int, u_int); +void sheeva_setttb (u_int); +void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_inv_range (vm_offset_t, vm_size_t); +void sheeva_dcache_wb_range (vm_offset_t, vm_size_t); +void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t); + +void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t); +void sheeva_l2cache_wbinv_all (void); #endif #ifdef CPU_ARM11 -- cgit v1.3