From 2611aba1801dd557c465c1d81a201f96c4e0b6b0 Mon Sep 17 00:00:00 2001 From: Marius Strobl Date: Mon, 8 Sep 2008 20:38:48 +0000 Subject: USIII and beyond CPUs have stricter requirements when it comes to synchronization needed after stores to internal ASIs in order to make side-effects visible. This mainly requires the MEMBAR #Sync after such stores to be replaced with a FLUSH. We use KERNBASE as the address to FLUSH as it is guaranteed to not trap. Actually, the USII synchronization rules also already require a FLUSH in pretty much all of the cases changed. We're also hitting an additional USIII synchronization rule which requires stores to AA_IMMU_SFSR to be immediately followed by a DONE, FLUSH or RETRY. Doing so triggers a RED state exception though so leave the MEMBAR #Sync. Linux apparently also has gotten away with doing the same for quite some time now, apart from the fact that it's not clear to me why we need to clear the valid bit from the SFSR in the first place. Reviewed by: nwhitehorn --- sys/boot/sparc64/loader/main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'sys/boot') diff --git a/sys/boot/sparc64/loader/main.c b/sys/boot/sparc64/loader/main.c index 34fe4cec1d7f..5091caa52237 100644 --- a/sys/boot/sparc64/loader/main.c +++ b/sys/boot/sparc64/loader/main.c @@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include "bootstrap.h" #include "libofw.h" @@ -461,7 +462,7 @@ itlb_enter_sun4u(u_long vpn, u_long data) stxa(AA_IMMU_TAR, ASI_IMMU, TLB_TAR_VA(vpn) | TLB_TAR_CTX(TLB_CTX_KERNEL)); stxa(0, ASI_ITLB_DATA_IN_REG, data); - membar(Sync); + flush(KERNBASE); wrpr(pstate, reg, 0); } -- cgit v1.3