From 21c4bbedbc71fc9843679168f034fce09625762d Mon Sep 17 00:00:00 2001 From: Ian Lepore Date: Sat, 28 Oct 2017 17:30:49 +0000 Subject: Avoid AXI bus issues due to a MAC reset on imx6sx and imx7. When the FEC is connected to the AXI bus (indicated by AVB flag), a MAC reset while a bus transaction is pending can hang the bus. Instead of resetting, turn off the ENABLE bit, which allows the hardware to complete any in-progress transfers (appending a bad CRC to any partial packet) and release the AXI bus. This could probably be done unconditionally for all hardware variants, but that hasn't been tested. PR: 222634 Submitted by: sebastian.huber@embedded-brains.de --- sys/dev/ffec/if_ffec.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'sys/dev/ffec') diff --git a/sys/dev/ffec/if_ffec.c b/sys/dev/ffec/if_ffec.c index 0ba02c8cdc4f..a25394bd961e 100644 --- a/sys/dev/ffec/if_ffec.c +++ b/sys/dev/ffec/if_ffec.c @@ -1639,8 +1639,21 @@ ffec_attach(device_t dev) /* Try to get the MAC address from the hardware before resetting it. */ ffec_get_hwaddr(sc, eaddr); - /* Reset the hardware. Disables all interrupts. */ - WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); + /* + * Reset the hardware. Disables all interrupts. + * + * When the FEC is connected to the AXI bus (indicated by AVB flag), a + * MAC reset while a bus transaction is pending can hang the bus. + * Instead of resetting, turn off the ENABLE bit, which allows the + * hardware to complete any in-progress transfers (appending a bad CRC + * to any partial packet) and release the AXI bus. This could probably + * be done unconditionally for all hardware variants, but that hasn't + * been tested. + */ + if (sc->fectype & FECFLAG_AVB) + WR4(sc, FEC_ECR_REG, 0); + else + WR4(sc, FEC_ECR_REG, FEC_ECR_RESET); /* Setup interrupt handler. */ error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE, -- cgit v1.3