From 339a44fb62595ffeb01a0a2d2f2ca87942038fb4 Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Tue, 15 Apr 2008 00:46:15 +0000 Subject: Don't touch MSI enable bit in RL_CFG2 register. For unknown reason clearing MSI enable bit for MSI capable hardwares resulted in Tx problems. MSI enable bit is set only when MSI is requested from user. Tested by: remko --- sys/dev/re/if_re.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) (limited to 'sys/dev') diff --git a/sys/dev/re/if_re.c b/sys/dev/re/if_re.c index d81e4d664437..2b0ef3a46503 100644 --- a/sys/dev/re/if_re.c +++ b/sys/dev/re/if_re.c @@ -1185,23 +1185,17 @@ re_attach(dev) device_printf(dev, "Using %d MSI messages\n", msic); sc->rl_msi = 1; + /* Explicitly set MSI enable bit. */ + CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); + cfg = CSR_READ_1(sc, RL_CFG2); + cfg |= RL_CFG2_MSI; + CSR_WRITE_1(sc, RL_CFG2, cfg); + CSR_WRITE_1(sc, RL_EECMD, 0); } else pci_release_msi(dev); } } - /* For MSI capable hardwares, explicitily set/clear MSI enable bit. */ - if (msic != 0) { - CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); - cfg = CSR_READ_1(sc, RL_CFG2); - if (sc->rl_msi != 0) - cfg |= RL_CFG2_MSI; - else - cfg &= ~RL_CFG2_MSI; - CSR_WRITE_1(sc, RL_CFG2, cfg); - CSR_WRITE_1(sc, RL_EECMD, 0); - } - /* Allocate interrupt */ if (sc->rl_msi == 0) { rid = 0; -- cgit v1.3