From fe75646a0234a261c0013bf1840fdac4acaf0cec Mon Sep 17 00:00:00 2001 From: Emmanuel Vadot Date: Mon, 25 Dec 2023 21:06:41 +0100 Subject: usb: dwc3: Move driver under a subdirectory dwc3 is big enough to have its own subdirectory. While here only make it depend on kernel option dwc3 and rk_dwc3 without any SOC options. Sponsored by: Beckhoff Automation GmbH & Co. KG Differential Revision: https://reviews.freebsd.org/D43190 --- sys/arm/allwinner/aw_dwc3.c | 141 -------- sys/arm64/rockchip/rk_dwc3.c | 198 ----------- sys/conf/files.arm | 2 +- sys/conf/files.arm64 | 7 +- sys/dev/usb/controller/dwc3.c | 621 ---------------------------------- sys/dev/usb/controller/dwc3.h | 137 -------- sys/dev/usb/controller/dwc3/aw_dwc3.c | 141 ++++++++ sys/dev/usb/controller/dwc3/dwc3.c | 620 +++++++++++++++++++++++++++++++++ sys/dev/usb/controller/dwc3/dwc3.h | 137 ++++++++ sys/dev/usb/controller/dwc3/rk_dwc3.c | 198 +++++++++++ 10 files changed, 1101 insertions(+), 1101 deletions(-) delete mode 100644 sys/arm/allwinner/aw_dwc3.c delete mode 100644 sys/arm64/rockchip/rk_dwc3.c delete mode 100644 sys/dev/usb/controller/dwc3.c delete mode 100644 sys/dev/usb/controller/dwc3.h create mode 100644 sys/dev/usb/controller/dwc3/aw_dwc3.c create mode 100644 sys/dev/usb/controller/dwc3/dwc3.c create mode 100644 sys/dev/usb/controller/dwc3/dwc3.h create mode 100644 sys/dev/usb/controller/dwc3/rk_dwc3.c (limited to 'sys') diff --git a/sys/arm/allwinner/aw_dwc3.c b/sys/arm/allwinner/aw_dwc3.c deleted file mode 100644 index 5b4d5291c28f..000000000000 --- a/sys/arm/allwinner/aw_dwc3.c +++ /dev/null @@ -1,141 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Emmanuel Vadot - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Rockchip DWC3 glue - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include - -static struct ofw_compat_data compat_data[] = { - { "allwinner,sun50i-h6-dwc3", 1 }, - { NULL, 0 } -}; - -struct aw_dwc3_softc { - struct simplebus_softc sc; - device_t dev; - clk_t clk_bus; - hwreset_t rst_bus; -}; - -static int -aw_dwc3_probe(device_t dev) -{ - phandle_t node; - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) - return (ENXIO); - - /* Binding says that we need a child node for the actual dwc3 controller */ - node = ofw_bus_get_node(dev); - if (OF_child(node) <= 0) - return (ENXIO); - - device_set_desc(dev, "Allwinner H6 DWC3"); - return (BUS_PROBE_DEFAULT); -} - -static int -aw_dwc3_attach(device_t dev) -{ - struct aw_dwc3_softc *sc; - device_t cdev; - phandle_t node, child; - int err; - - sc = device_get_softc(dev); - sc->dev = dev; - node = ofw_bus_get_node(dev); - - /* Enable the clocks */ - if (clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_bus) != 0) { - device_printf(dev, "Cannot get bus clock\n"); - return (ENXIO); - } - err = clk_enable(sc->clk_bus); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_bus)); - return (ENXIO); - } - - /* Put module out of reset */ - if (hwreset_get_by_ofw_name(dev, node, "bus", &sc->rst_bus) == 0) { - if (hwreset_deassert(sc->rst_bus) != 0) { - device_printf(dev, "Cannot deassert reset\n"); - return (ENXIO); - } - } - - simplebus_init(dev, node); - if (simplebus_fill_ranges(node, &sc->sc) < 0) { - device_printf(dev, "could not get ranges\n"); - return (ENXIO); - } - - for (child = OF_child(node); child > 0; child = OF_peer(child)) { - cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); - if (cdev != NULL) - device_probe_and_attach(cdev); - } - - return (bus_generic_attach(dev)); -} - -static device_method_t aw_dwc3_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, aw_dwc3_probe), - DEVMETHOD(device_attach, aw_dwc3_attach), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(aw_dwc3, aw_dwc3_driver, aw_dwc3_methods, - sizeof(struct aw_dwc3_softc), simplebus_driver); -DRIVER_MODULE(aw_dwc3, simplebus, aw_dwc3_driver, 0, 0); diff --git a/sys/arm64/rockchip/rk_dwc3.c b/sys/arm64/rockchip/rk_dwc3.c deleted file mode 100644 index f336490c386e..000000000000 --- a/sys/arm64/rockchip/rk_dwc3.c +++ /dev/null @@ -1,198 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Emmanuel Vadot - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Rockchip DWC3 glue - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -enum rk_dwc3_type { - RK3399 = 1, -}; - -static struct ofw_compat_data compat_data[] = { - { "rockchip,rk3399-dwc3", RK3399 }, - { NULL, 0 } -}; - -struct rk_dwc3_softc { - struct simplebus_softc sc; - device_t dev; - clk_t clk_ref; - clk_t clk_suspend; - clk_t clk_bus; - clk_t clk_axi_perf; - clk_t clk_usb3; - clk_t clk_grf; - hwreset_t rst_usb3; - enum rk_dwc3_type type; -}; - -static int -rk_dwc3_probe(device_t dev) -{ - phandle_t node; - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) - return (ENXIO); - - /* Binding says that we need a child node for the actual dwc3 controller */ - node = ofw_bus_get_node(dev); - if (OF_child(node) <= 0) - return (ENXIO); - - device_set_desc(dev, "Rockchip RK3399 DWC3"); - return (BUS_PROBE_DEFAULT); -} - -static int -rk_dwc3_attach(device_t dev) -{ - struct rk_dwc3_softc *sc; - device_t cdev; - phandle_t node, child; - int err; - - sc = device_get_softc(dev); - sc->dev = dev; - node = ofw_bus_get_node(dev); - sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; - - /* Mandatory clocks */ - if (clk_get_by_ofw_name(dev, 0, "ref_clk", &sc->clk_ref) != 0) { - device_printf(dev, "Cannot get ref_clk clock\n"); - return (ENXIO); - } - err = clk_enable(sc->clk_ref); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_ref)); - return (ENXIO); - } - if (clk_get_by_ofw_name(dev, 0, "suspend_clk", &sc->clk_suspend) != 0) { - device_printf(dev, "Cannot get suspend_clk clock\n"); - return (ENXIO); - } - err = clk_enable(sc->clk_suspend); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_suspend)); - return (ENXIO); - } - if (clk_get_by_ofw_name(dev, 0, "bus_clk", &sc->clk_bus) != 0) { - device_printf(dev, "Cannot get bus_clk clock\n"); - return (ENXIO); - } - err = clk_enable(sc->clk_bus); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_bus)); - return (ENXIO); - } - if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) { - err = clk_enable(sc->clk_grf); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_grf)); - return (ENXIO); - } - } - /* Optional clocks */ - if (clk_get_by_ofw_name(dev, 0, "aclk_usb3_rksoc_axi_perf", &sc->clk_axi_perf) == 0) { - err = clk_enable(sc->clk_axi_perf); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_axi_perf)); - return (ENXIO); - } - } - if (clk_get_by_ofw_name(dev, 0, "aclk_usb3", &sc->clk_usb3) == 0) { - err = clk_enable(sc->clk_usb3); - if (err != 0) { - device_printf(dev, "Could not enable clock %s\n", - clk_get_name(sc->clk_usb3)); - return (ENXIO); - } - } - - /* Put module out of reset */ - if (hwreset_get_by_ofw_name(dev, node, "usb3-otg", &sc->rst_usb3) == 0) { - if (hwreset_deassert(sc->rst_usb3) != 0) { - device_printf(dev, "Cannot deassert reset\n"); - return (ENXIO); - } - } - - simplebus_init(dev, node); - if (simplebus_fill_ranges(node, &sc->sc) < 0) { - device_printf(dev, "could not get ranges\n"); - return (ENXIO); - } - - for (child = OF_child(node); child > 0; child = OF_peer(child)) { - cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); - if (cdev != NULL) - device_probe_and_attach(cdev); - } - - return (bus_generic_attach(dev)); -} - -static device_method_t rk_dwc3_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, rk_dwc3_probe), - DEVMETHOD(device_attach, rk_dwc3_attach), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(rk_dwc3, rk_dwc3_driver, rk_dwc3_methods, - sizeof(struct rk_dwc3_softc), simplebus_driver); -DRIVER_MODULE(rk_dwc3, simplebus, rk_dwc3_driver, 0, 0); diff --git a/sys/conf/files.arm b/sys/conf/files.arm index 075b05e36d78..28e80016d97b 100644 --- a/sys/conf/files.arm +++ b/sys/conf/files.arm @@ -104,7 +104,7 @@ dev/psci/smccc_arm.S optional psci dev/syscons/scgfbrndr.c optional sc dev/uart/uart_cpu_fdt.c optional uart fdt -dev/usb/controller/dwc3.c optional fdt dwc3 +dev/usb/controller/dwc3/dwc3.c optional fdt dwc3 dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_fdt.c optional xhci fdt diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64 index 6c761b37f191..0eed3db41b16 100644 --- a/sys/conf/files.arm64 +++ b/sys/conf/files.arm64 @@ -402,7 +402,6 @@ dev/uart/uart_dev_mu.c optional uart uart_mu fdt dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 -dev/usb/controller/dwc3.c optional xhci acpi dwc3 | xhci fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi @@ -415,6 +414,10 @@ dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt +dev/usb/controller/dwc3/dwc3.c optional xhci acpi dwc3 | xhci fdt dwc3 +dev/usb/controller/dwc3/aw_dwc3.c optional xhci fdt dwc3 aw_dwc3 +dev/usb/controller/dwc3/rk_dwc3.c optional xhci fdt dwc3 rk_dwc3 + dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov @@ -437,7 +440,6 @@ arm/allwinner/a33_codec.c optional fdt sound a33_codec arm/allwinner/a64/sun50i_a64_acodec.c optional fdt sound a64_codec arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt -arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_i2s.c optional fdt sound aw_i2s arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt @@ -664,7 +666,6 @@ arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk3568_combphy.c optional fdt rk_combphy soc_rockchip_rk3568 arm64/rockchip/rk3568_pcie.c optional fdt pci soc_rockchip_rk3568 arm64/rockchip/rk3568_pciephy.c optional fdt pci soc_rockchip_rk3568 -arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 | fdt rk_dwc3 soc_rockchip_rk3568 arm64/rockchip/rk_i2s.c optional fdt sound soc_rockchip_rk3328 | fdt sound soc_rockchip_rk3399 arm64/rockchip/rk_otp.c optional fdt soc_rockchip_rk3568 arm64/rockchip/rk_otp_if.m optional fdt soc_rockchip_rk3568 diff --git a/sys/dev/usb/controller/dwc3.c b/sys/dev/usb/controller/dwc3.c deleted file mode 100644 index bf3001c0389e..000000000000 --- a/sys/dev/usb/controller/dwc3.c +++ /dev/null @@ -1,621 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Emmanuel Vadot - * Copyright (c) 2021-2022 Bjoern A. Zeeb - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -#include "opt_platform.h" -#include "opt_acpi.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef FDT -#include -#endif - -#include - -#include -#include - -#include -#include -#include - -#include -#include -#include -#include - -#ifdef FDT -#include - -#include -#include -#include -#include - -#include -#include -#endif - -#ifdef DEV_ACPI -#include -#include -#include -#endif - -#include "generic_xhci.h" - -struct snps_dwc3_softc { - struct xhci_softc sc; - device_t dev; - struct resource * mem_res; - bus_space_tag_t bst; - bus_space_handle_t bsh; - uint32_t snpsid; - uint32_t snpsversion; - uint32_t snpsrevision; - uint32_t snpsversion_type; -#ifdef FDT - clk_t clk_ref; - clk_t clk_suspend; - clk_t clk_bus; -#endif -}; - -#define DWC3_WRITE(_sc, _off, _val) \ - bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) -#define DWC3_READ(_sc, _off) \ - bus_space_read_4(_sc->bst, _sc->bsh, _off) - -#define IS_DMA_32B 1 - -static void -xhci_interrupt_poll(void *_sc) -{ - struct xhci_softc *sc = _sc; - - USB_BUS_UNLOCK(&sc->sc_bus); - xhci_interrupt(sc); - USB_BUS_LOCK(&sc->sc_bus); - usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); -} - -static int -snps_dwc3_attach_xhci(device_t dev) -{ - struct snps_dwc3_softc *snps_sc = device_get_softc(dev); - struct xhci_softc *sc = &snps_sc->sc; - int err = 0, rid = 0; - - sc->sc_io_res = snps_sc->mem_res; - sc->sc_io_tag = snps_sc->bst; - sc->sc_io_hdl = snps_sc->bsh; - sc->sc_io_size = rman_get_size(snps_sc->mem_res); - - sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, - RF_SHAREABLE | RF_ACTIVE); - if (sc->sc_irq_res == NULL) { - device_printf(dev, "Failed to allocate IRQ\n"); - return (ENXIO); - } - - sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); - if (sc->sc_bus.bdev == NULL) { - device_printf(dev, "Failed to add USB device\n"); - return (ENXIO); - } - - device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); - - sprintf(sc->sc_vendor, "Synopsys"); - device_set_desc(sc->sc_bus.bdev, "Synopsys"); - - if (xhci_use_polling() == 0) { - err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, - NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); - if (err != 0) { - device_printf(dev, "Failed to setup IRQ, %d\n", err); - sc->sc_intr_hdl = NULL; - return (err); - } - } - - err = xhci_init(sc, dev, IS_DMA_32B); - if (err != 0) { - device_printf(dev, "Failed to init XHCI, with error %d\n", err); - return (ENXIO); - } - - usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); - - if (xhci_use_polling() != 0) { - device_printf(dev, "Interrupt polling at %dHz\n", hz); - USB_BUS_LOCK(&sc->sc_bus); - xhci_interrupt_poll(sc); - USB_BUS_UNLOCK(&sc->sc_bus); - } - - err = xhci_start_controller(sc); - if (err != 0) { - device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); - return (ENXIO); - } - - device_printf(sc->sc_bus.bdev, "trying to attach\n"); - err = device_probe_and_attach(sc->sc_bus.bdev); - if (err != 0) { - device_printf(dev, "Failed to initialize USB, with error %d\n", err); - return (ENXIO); - } - - return (0); -} - -#ifdef DWC3_DEBUG -static void -snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc, const char *msg) -{ - struct xhci_softc *xsc; - uint32_t reg; - - if (!bootverbose) - return; - - device_printf(sc->dev, "%s: %s:\n", __func__, msg ? msg : ""); - - reg = DWC3_READ(sc, DWC3_GCTL); - device_printf(sc->dev, "GCTL: %#012x\n", reg); - reg = DWC3_READ(sc, DWC3_GUCTL); - device_printf(sc->dev, "GUCTL: %#012x\n", reg); - reg = DWC3_READ(sc, DWC3_GUCTL1); - device_printf(sc->dev, "GUCTL1: %#012x\n", reg); - reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); - device_printf(sc->dev, "GUSB2PHYCFG0: %#012x\n", reg); - reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); - device_printf(sc->dev, "GUSB3PIPECTL0: %#012x\n", reg); - reg = DWC3_READ(sc, DWC3_DCFG); - device_printf(sc->dev, "DCFG: %#012x\n", reg); - - xsc = &sc->sc; - device_printf(sc->dev, "xhci quirks: %#012x\n", xsc->sc_quirks); -} - -static void -snps_dwc3_dump_ctrlparams(struct snps_dwc3_softc *sc) -{ - const bus_size_t offs[] = { - DWC3_GHWPARAMS0, DWC3_GHWPARAMS1, DWC3_GHWPARAMS2, DWC3_GHWPARAMS3, - DWC3_GHWPARAMS4, DWC3_GHWPARAMS5, DWC3_GHWPARAMS6, DWC3_GHWPARAMS7, - DWC3_GHWPARAMS8, - }; - uint32_t reg; - int i; - - for (i = 0; i < nitems(offs); i++) { - reg = DWC3_READ(sc, offs[i]); - if (bootverbose) - device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg); - } -} -#endif - -static void -snps_dwc3_reset(struct snps_dwc3_softc *sc) -{ - uint32_t gctl, ghwp0, phy2, phy3; - - ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); - - gctl = DWC3_READ(sc, DWC3_GCTL); - gctl |= DWC3_GCTL_CORESOFTRESET; - DWC3_WRITE(sc, DWC3_GCTL, gctl); - - phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); - phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; - if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == - DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) - phy2 &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; - DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); - - phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); - phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; - if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == - DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) - phy3 &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; - DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); - - DELAY(1000); - - phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; - DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); - - phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; - DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); - - gctl &= ~DWC3_GCTL_CORESOFTRESET; - DWC3_WRITE(sc, DWC3_GCTL, gctl); - -} - -static void -snps_dwc3_configure_host(struct snps_dwc3_softc *sc) -{ - uint32_t reg; - - reg = DWC3_READ(sc, DWC3_GCTL); - reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; - reg |= DWC3_GCTL_PRTCAPDIR_HOST; - DWC3_WRITE(sc, DWC3_GCTL, reg); - - /* - * Enable the Host IN Auto Retry feature, making the - * host respond with a non-terminating retry ACK. - * XXX If we ever support more than host mode this needs a dr_mode check. - */ - reg = DWC3_READ(sc, DWC3_GUCTL); - reg |= DWC3_GUCTL_HOST_AUTO_RETRY; - DWC3_WRITE(sc, DWC3_GUCTL, reg); -} - -#ifdef FDT -static void -snps_dwc3_configure_phy(struct snps_dwc3_softc *sc, phandle_t node) -{ - char *phy_type; - uint32_t reg; - int nphy_types; - - phy_type = NULL; - nphy_types = OF_getprop_alloc(node, "phy_type", (void **)&phy_type); - if (nphy_types <= 0) - return; - - reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); - if (strncmp(phy_type, "utmi_wide", 9) == 0) { - reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); - reg |= DWC3_GUSB2PHYCFG0_PHYIF | - DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); - } else { - reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); - reg |= DWC3_GUSB2PHYCFG0_PHYIF | - DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); - } - DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); - OF_prop_free(phy_type); -} -#endif - -static void -snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) -{ - struct xhci_softc *xsc; - uint32_t ghwp0, reg; - - ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); - reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); - if (device_has_property(sc->dev, "snps,dis-u2-freeclk-exists-quirk")) - reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; - else - reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; - if (device_has_property(sc->dev, "snps,dis_u2_susphy_quirk")) - reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; - else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == - DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) - reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; - if (device_has_property(sc->dev, "snps,dis_enblslpm_quirk")) - reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; - else - reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; - DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); - - reg = DWC3_READ(sc, DWC3_GUCTL1); - if (device_has_property(sc->dev, "snps,dis-tx-ipgap-linecheck-quirk")) - reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; - DWC3_WRITE(sc, DWC3_GUCTL1, reg); - - reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); - if (device_has_property(sc->dev, "snps,dis-del-phy-power-chg-quirk")) - reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS; - if (device_has_property(sc->dev, "snps,dis_rxdet_inp3_quirk")) - reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3; - if (device_has_property(sc->dev, "snps,dis_u3_susphy_quirk")) - reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; - else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == - DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) - reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3; - DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); - - /* Port Disable does not work on <= 3.00a. Disable PORT_PED. */ - if ((sc->snpsid & 0xffff) <= 0x300a) { - xsc = &sc->sc; - xsc->sc_quirks |= XHCI_QUIRK_DISABLE_PORT_PED; - } -} - -static int -snps_dwc3_probe_common(device_t dev) -{ - char dr_mode[16] = { 0 }; - ssize_t s; - - s = device_get_property(dev, "dr_mode", dr_mode, sizeof(dr_mode), - DEVICE_PROP_BUFFER); - if (s == -1) { - device_printf(dev, "Cannot determine dr_mode\n"); - return (ENXIO); - } - if (strcmp(dr_mode, "host") != 0) { - device_printf(dev, - "Found dr_mode '%s' but only 'host' supported. s=%zd\n", - dr_mode, s); - return (ENXIO); - } - - device_set_desc(dev, "Synopsys Designware DWC3"); - return (BUS_PROBE_DEFAULT); -} - -static int -snps_dwc3_common_attach(device_t dev, bool is_fdt) -{ - struct snps_dwc3_softc *sc; -#ifdef FDT - phandle_t node; - phy_t usb2_phy, usb3_phy; - uint32_t reg; -#endif - int error, rid; - - sc = device_get_softc(dev); - sc->dev = dev; - - rid = 0; - sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE); - if (sc->mem_res == NULL) { - device_printf(dev, "Failed to map memory\n"); - return (ENXIO); - } - sc->bst = rman_get_bustag(sc->mem_res); - sc->bsh = rman_get_bushandle(sc->mem_res); - - sc->snpsid = DWC3_READ(sc, DWC3_GSNPSID); - sc->snpsversion = DWC3_VERSION(sc->snpsid); - sc->snpsrevision = DWC3_REVISION(sc->snpsid); - if (sc->snpsversion == DWC3_1_IP_ID || - sc->snpsversion == DWC3_2_IP_ID) { - sc->snpsrevision = DWC3_READ(sc, DWC3_1_VER_NUMBER); - sc->snpsversion_type = DWC3_READ(sc, DWC3_1_VER_TYPE); - } - if (bootverbose) { - switch (sc->snpsversion) { - case DWC3_IP_ID: - device_printf(sc->dev, "SNPS Version: DWC3 (%x %x)\n", - sc->snpsversion, sc->snpsrevision); - break; - case DWC3_1_IP_ID: - device_printf(sc->dev, "SNPS Version: DWC3.1 (%x %x %x)\n", - sc->snpsversion, sc->snpsrevision, - sc->snpsversion_type); - break; - case DWC3_2_IP_ID: - device_printf(sc->dev, "SNPS Version: DWC3.2 (%x %x %x)\n", - sc->snpsversion, sc->snpsrevision, - sc->snpsversion_type); - break; - } - } -#ifdef DWC3_DEBUG - snps_dwc3_dump_ctrlparams(sc); -#endif - -#ifdef FDT - if (!is_fdt) - goto skip_phys; - - node = ofw_bus_get_node(dev); - - /* Get the clocks if any */ - if (ofw_bus_is_compatible(dev, "rockchip,rk3328-dwc3") == 1 || - ofw_bus_is_compatible(dev, "rockchip,rk3568-dwc3") == 1) { - if (clk_get_by_ofw_name(dev, node, "ref_clk", &sc->clk_ref) != 0) - device_printf(dev, "Cannot get ref_clk\n"); - if (clk_get_by_ofw_name(dev, node, "suspend_clk", &sc->clk_suspend) != 0) - device_printf(dev, "Cannot get suspend_clk\n"); - if (clk_get_by_ofw_name(dev, node, "bus_clk", &sc->clk_bus) != 0) - device_printf(dev, "Cannot get bus_clk\n"); - } - - if (sc->clk_ref != NULL) { - if (clk_enable(sc->clk_ref) != 0) - device_printf(dev, "Cannot enable ref_clk\n"); - } - if (sc->clk_suspend != NULL) { - if (clk_enable(sc->clk_suspend) != 0) - device_printf(dev, "Cannot enable suspend_clk\n"); - } - if (sc->clk_bus != NULL) { - if (clk_enable(sc->clk_bus) != 0) - device_printf(dev, "Cannot enable bus_clk\n"); - } - - /* Get the phys */ - usb2_phy = usb3_phy = NULL; - error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); - if (error == 0 && usb2_phy != NULL) - phy_enable(usb2_phy); - error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); - if (error == 0 && usb3_phy != NULL) - phy_enable(usb3_phy); - if (sc->snpsversion == DWC3_IP_ID) { - if (sc->snpsrevision >= 0x290A) { - uint32_t hwparams3; - - hwparams3 = DWC3_READ(sc, DWC3_GHWPARAMS3); - if (DWC3_HWPARAMS3_SSPHY(hwparams3) == DWC3_HWPARAMS3_SSPHY_DISABLE) { - reg = DWC3_READ(sc, DWC3_GUCTL1); - if (bootverbose) - device_printf(dev, "Forcing USB2 clock only\n"); - reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; - DWC3_WRITE(sc, DWC3_GUCTL1, reg); - } - } - } - snps_dwc3_configure_phy(sc, node); -skip_phys: -#endif - - snps_dwc3_reset(sc); - snps_dwc3_configure_host(sc); - snps_dwc3_do_quirks(sc); - -#ifdef DWC3_DEBUG - snsp_dwc3_dump_regs(sc, "Pre XHCI init"); -#endif - error = snps_dwc3_attach_xhci(dev); -#ifdef DWC3_DEBUG - snsp_dwc3_dump_regs(sc, "Post XHCI init"); -#endif - -#ifdef FDT - if (error) { - if (sc->clk_ref != NULL) - clk_disable(sc->clk_ref); - if (sc->clk_suspend != NULL) - clk_disable(sc->clk_suspend); - if (sc->clk_bus != NULL) - clk_disable(sc->clk_bus); - } -#endif - return (error); -} - -#ifdef FDT -static struct ofw_compat_data compat_data[] = { - { "snps,dwc3", 1 }, - { NULL, 0 } -}; - -static int -snps_dwc3_fdt_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) - return (ENXIO); - - return (snps_dwc3_probe_common(dev)); -} - -static int -snps_dwc3_fdt_attach(device_t dev) -{ - - return (snps_dwc3_common_attach(dev, true)); -} - -static device_method_t snps_dwc3_fdt_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, snps_dwc3_fdt_probe), - DEVMETHOD(device_attach, snps_dwc3_fdt_attach), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(snps_dwc3_fdt, snps_dwc3_fdt_driver, snps_dwc3_fdt_methods, - sizeof(struct snps_dwc3_softc), generic_xhci_driver); - -DRIVER_MODULE(snps_dwc3_fdt, simplebus, snps_dwc3_fdt_driver, 0, 0); -MODULE_DEPEND(snps_dwc3_fdt, xhci, 1, 1, 1); -#endif - -#ifdef DEV_ACPI -static char *dwc3_acpi_ids[] = { - "808622B7", /* This was an Intel PCI Vendor/Device ID used. */ - "PNP0D10", /* The generic XHCI PNP ID needing extra probe checks. */ - NULL -}; - -static int -snps_dwc3_acpi_probe(device_t dev) -{ - char *match; - int error; - - if (acpi_disabled("snps_dwc3")) - return (ENXIO); - - error = ACPI_ID_PROBE(device_get_parent(dev), dev, dwc3_acpi_ids, &match); - if (error > 0) - return (ENXIO); - - /* - * If we found the Generic XHCI PNP ID we can only attach if we have - * some other means to identify the device as dwc3. - */ - if (strcmp(match, "PNP0D10") == 0) { - /* This is needed in SolidRun's HoneyComb. */ - if (device_has_property(dev, "snps,dis_rxdet_inp3_quirk")) - goto is_dwc3; - - return (ENXIO); - } - -is_dwc3: - return (snps_dwc3_probe_common(dev)); -} - -static int -snps_dwc3_acpi_attach(device_t dev) -{ - - return (snps_dwc3_common_attach(dev, false)); -} - -static device_method_t snps_dwc3_acpi_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, snps_dwc3_acpi_probe), - DEVMETHOD(device_attach, snps_dwc3_acpi_attach), - - DEVMETHOD_END -}; - -DEFINE_CLASS_1(snps_dwc3_acpi, snps_dwc3_acpi_driver, snps_dwc3_acpi_methods, - sizeof(struct snps_dwc3_softc), generic_xhci_driver); - -DRIVER_MODULE(snps_dwc3_acpi, acpi, snps_dwc3_acpi_driver, 0, 0); -MODULE_DEPEND(snps_dwc3_acpi, usb, 1, 1, 1); -#endif diff --git a/sys/dev/usb/controller/dwc3.h b/sys/dev/usb/controller/dwc3.h deleted file mode 100644 index a2063d8cff31..000000000000 --- a/sys/dev/usb/controller/dwc3.h +++ /dev/null @@ -1,137 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause - * - * Copyright (c) 2019 Emmanuel Vadot - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#ifndef _DWC3_H_ -#define _DWC3_H_ - -#define DWC3_IP_ID 0x5533 -#define DWC3_1_IP_ID 0x3331 -#define DWC3_2_IP_ID 0x3332 - -#define DWC3_VERSION_MASK 0xFFFF0000 -#define DWC3_REVISION_MASK 0xFFFF -#define DWC3_VERSION(x) (((x) & DWC3_VERSION_MASK) >> 16) -#define DWC3_REVISION(x) ((x) & DWC3_REVISION_MASK) - -#define DWC3_GSBUSCFG0 0xc100 -#define DWC3_GSBUSCFG1 0xc104 -#define DWC3_GTXTHRCFG 0xc108 -#define DWC3_GRXTHRCFG 0xc10C - -/* Global Core Control Register */ -#define DWC3_GCTL 0xc110 -#define DWC3_GCTL_PRTCAPDIR_MASK (0x3 << 12) -#define DWC3_GCTL_PRTCAPDIR_HOST (0x1 << 12) -#define DWC3_GCTL_PRTCAPDIR_DEVICE (0x2 << 12) -#define DWC3_GCTL_CORESOFTRESET (1 << 11) -#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) - -#define DWC3_GPMSTS 0xc114 -#define DWC3_GSTS 0xc118 - -#define DWC3_GUCTL1 0xc11c -#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) -#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26) - -#define DWC3_GSNPSID 0xc120 -#define DWC3_GGPIO 0xc124 -#define DWC3_GUID 0xc128 -#define DWC3_GUCTL 0xc12C -#define DWC3_GUCTL_HOST_AUTO_RETRY (1 << 14) -#define DWC3_GBUSERRADDRLO 0xc130 -#define DWC3_GBUSERRADDRHI 0xc134 -#define DWC3_GPRTBIMAPLO 0xc138 -#define DWC3_GHWPARAMS0 0xc140 -#define DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE 0x2 -#define DWC3_GHWPARAMS0_MODE_MASK 0x3 -#define DWC3_GHWPARAMS1 0xc144 -#define DWC3_GHWPARAMS2 0xc148 -#define DWC3_GHWPARAMS3 0xc14C -#define DWC3_GHWPARAMS4 0xc150 -#define DWC3_GHWPARAMS5 0xc154 -#define DWC3_GHWPARAMS6 0xc158 -#define DWC3_GHWPARAMS7 0xc15C -#define DWC3_GDBGFIFOSPACE 0xc160 -#define DWC3_GDBGLTSSM 0xc164 -#define DWC3_GDBGLNMCC 0xc168 -#define DWC3_GDBGBMU 0xc16C -#define DWC3_GDBGLSPMUX 0xc170 -#define DWC3_GDBGLSP 0xc174 -#define DWC3_GDBGEPINFO0 0xc178 -#define DWC3_GDBGEPINFO1 0xc17C -#define DWC3_GPRTBIMAP_HSLO 0xc180 -#define DWC3_GPRTBIMAP_FSLO 0xc188 - -#define DWC3_1_VER_NUMBER 0xc1a0 -#define DWC3_1_VER_TYPE 0xc1a4 - -#define DWC3_GUSB2PHYCFG0 0xc200 -#define DWC3_GUSB2PHYCFG0_PHYSOFTRST (1 << 31) -#define DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS (1 << 30) -#define DWC3_GUSB2PHYCFG0_USBTRDTIM(n) ((n) << 10) -#define DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS 9 -#define DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS 5 -#define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) -#define DWC3_GUSB2PHYCFG0_PHYSEL(x) (((x) >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */ -#define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) -#define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4) -#define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3) - -#define DWC3_GUSB3PIPECTL0 0xc2c0 -#define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31) -#define DWC3_GUSB3PIPECTL0_DISRXDETINP3 (1 << 28) -#define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) -#define DWC3_GUSB3PIPECTL0_SUSPENDUSB3 (1 << 17) - -#define DWC3_HWPARAMS3_SSPHY(x) ((x) & 0x3) -#define DWC3_HWPARAMS3_SSPHY_DISABLE 0 -#define DWC3_HWPARAMS3_SSPHY_GEN1 1 -#define DWC3_HWPARAMS3_SSPHY_GEN2 2 - -#define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) -#define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) -#define DWC3_GEVNTADRLO0 0xc400 -#define DWC3_GEVNTADRHI0 0xc404 -#define DWC3_GEVNTSIZ0 0xc408 -#define DWC3_GEVNTCOUNT0 0xc40C -#define DWC3_GHWPARAMS8 0xc600 -#define DWC3_GTXFIFOPRIDEV 0xc610 -#define DWC3_GTXFIFOPRIHST 0xc618 -#define DWC3_GRXFIFOPRIHST 0xc61c -#define DWC3_GFIFOPRIDBC 0xc620 -#define DWC3_GDMAHLRATIO 0xc624 -#define DWC3_GFLADJ 0xc630 -#define DWC3_DCFG 0xc700 -#define DWC3_DCTL 0xc704 -#define DWC3_DEVTEN 0xc708 -#define DWC3_DSTS 0xc70C -#define DWC3_DGCMDPAR 0xc710 -#define DWC3_DGCMD 0xc714 -#define DWC3_DALEPENA 0xc720 - -#endif /* _DWC3_H_ */ diff --git a/sys/dev/usb/controller/dwc3/aw_dwc3.c b/sys/dev/usb/controller/dwc3/aw_dwc3.c new file mode 100644 index 000000000000..5b4d5291c28f --- /dev/null +++ b/sys/dev/usb/controller/dwc3/aw_dwc3.c @@ -0,0 +1,141 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Rockchip DWC3 glue + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include + +static struct ofw_compat_data compat_data[] = { + { "allwinner,sun50i-h6-dwc3", 1 }, + { NULL, 0 } +}; + +struct aw_dwc3_softc { + struct simplebus_softc sc; + device_t dev; + clk_t clk_bus; + hwreset_t rst_bus; +}; + +static int +aw_dwc3_probe(device_t dev) +{ + phandle_t node; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + /* Binding says that we need a child node for the actual dwc3 controller */ + node = ofw_bus_get_node(dev); + if (OF_child(node) <= 0) + return (ENXIO); + + device_set_desc(dev, "Allwinner H6 DWC3"); + return (BUS_PROBE_DEFAULT); +} + +static int +aw_dwc3_attach(device_t dev) +{ + struct aw_dwc3_softc *sc; + device_t cdev; + phandle_t node, child; + int err; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + /* Enable the clocks */ + if (clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_bus) != 0) { + device_printf(dev, "Cannot get bus clock\n"); + return (ENXIO); + } + err = clk_enable(sc->clk_bus); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_bus)); + return (ENXIO); + } + + /* Put module out of reset */ + if (hwreset_get_by_ofw_name(dev, node, "bus", &sc->rst_bus) == 0) { + if (hwreset_deassert(sc->rst_bus) != 0) { + device_printf(dev, "Cannot deassert reset\n"); + return (ENXIO); + } + } + + simplebus_init(dev, node); + if (simplebus_fill_ranges(node, &sc->sc) < 0) { + device_printf(dev, "could not get ranges\n"); + return (ENXIO); + } + + for (child = OF_child(node); child > 0; child = OF_peer(child)) { + cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); + if (cdev != NULL) + device_probe_and_attach(cdev); + } + + return (bus_generic_attach(dev)); +} + +static device_method_t aw_dwc3_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, aw_dwc3_probe), + DEVMETHOD(device_attach, aw_dwc3_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(aw_dwc3, aw_dwc3_driver, aw_dwc3_methods, + sizeof(struct aw_dwc3_softc), simplebus_driver); +DRIVER_MODULE(aw_dwc3, simplebus, aw_dwc3_driver, 0, 0); diff --git a/sys/dev/usb/controller/dwc3/dwc3.c b/sys/dev/usb/controller/dwc3/dwc3.c new file mode 100644 index 000000000000..d97b0b11d44c --- /dev/null +++ b/sys/dev/usb/controller/dwc3/dwc3.c @@ -0,0 +1,620 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Emmanuel Vadot + * Copyright (c) 2021-2022 Bjoern A. Zeeb + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +#include "opt_platform.h" +#include "opt_acpi.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef FDT +#include +#endif + +#include + +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef FDT +#include + +#include +#include +#include +#include + +#include +#include +#endif + +#ifdef DEV_ACPI +#include +#include +#include +#endif + +struct snps_dwc3_softc { + struct xhci_softc sc; + device_t dev; + struct resource * mem_res; + bus_space_tag_t bst; + bus_space_handle_t bsh; + uint32_t snpsid; + uint32_t snpsversion; + uint32_t snpsrevision; + uint32_t snpsversion_type; +#ifdef FDT + clk_t clk_ref; + clk_t clk_suspend; + clk_t clk_bus; +#endif +}; + +#define DWC3_WRITE(_sc, _off, _val) \ + bus_space_write_4(_sc->bst, _sc->bsh, _off, _val) +#define DWC3_READ(_sc, _off) \ + bus_space_read_4(_sc->bst, _sc->bsh, _off) + +#define IS_DMA_32B 1 + +static void +xhci_interrupt_poll(void *_sc) +{ + struct xhci_softc *sc = _sc; + + USB_BUS_UNLOCK(&sc->sc_bus); + xhci_interrupt(sc); + USB_BUS_LOCK(&sc->sc_bus); + usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); +} + +static int +snps_dwc3_attach_xhci(device_t dev) +{ + struct snps_dwc3_softc *snps_sc = device_get_softc(dev); + struct xhci_softc *sc = &snps_sc->sc; + int err = 0, rid = 0; + + sc->sc_io_res = snps_sc->mem_res; + sc->sc_io_tag = snps_sc->bst; + sc->sc_io_hdl = snps_sc->bsh; + sc->sc_io_size = rman_get_size(snps_sc->mem_res); + + sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_SHAREABLE | RF_ACTIVE); + if (sc->sc_irq_res == NULL) { + device_printf(dev, "Failed to allocate IRQ\n"); + return (ENXIO); + } + + sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); + if (sc->sc_bus.bdev == NULL) { + device_printf(dev, "Failed to add USB device\n"); + return (ENXIO); + } + + device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); + + sprintf(sc->sc_vendor, "Synopsys"); + device_set_desc(sc->sc_bus.bdev, "Synopsys"); + + if (xhci_use_polling() == 0) { + err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, + NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); + if (err != 0) { + device_printf(dev, "Failed to setup IRQ, %d\n", err); + sc->sc_intr_hdl = NULL; + return (err); + } + } + + err = xhci_init(sc, dev, IS_DMA_32B); + if (err != 0) { + device_printf(dev, "Failed to init XHCI, with error %d\n", err); + return (ENXIO); + } + + usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); + + if (xhci_use_polling() != 0) { + device_printf(dev, "Interrupt polling at %dHz\n", hz); + USB_BUS_LOCK(&sc->sc_bus); + xhci_interrupt_poll(sc); + USB_BUS_UNLOCK(&sc->sc_bus); + } + + err = xhci_start_controller(sc); + if (err != 0) { + device_printf(dev, "Failed to start XHCI controller, with error %d\n", err); + return (ENXIO); + } + + device_printf(sc->sc_bus.bdev, "trying to attach\n"); + err = device_probe_and_attach(sc->sc_bus.bdev); + if (err != 0) { + device_printf(dev, "Failed to initialize USB, with error %d\n", err); + return (ENXIO); + } + + return (0); +} + +#ifdef DWC3_DEBUG +static void +snsp_dwc3_dump_regs(struct snps_dwc3_softc *sc, const char *msg) +{ + struct xhci_softc *xsc; + uint32_t reg; + + if (!bootverbose) + return; + + device_printf(sc->dev, "%s: %s:\n", __func__, msg ? msg : ""); + + reg = DWC3_READ(sc, DWC3_GCTL); + device_printf(sc->dev, "GCTL: %#012x\n", reg); + reg = DWC3_READ(sc, DWC3_GUCTL); + device_printf(sc->dev, "GUCTL: %#012x\n", reg); + reg = DWC3_READ(sc, DWC3_GUCTL1); + device_printf(sc->dev, "GUCTL1: %#012x\n", reg); + reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); + device_printf(sc->dev, "GUSB2PHYCFG0: %#012x\n", reg); + reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); + device_printf(sc->dev, "GUSB3PIPECTL0: %#012x\n", reg); + reg = DWC3_READ(sc, DWC3_DCFG); + device_printf(sc->dev, "DCFG: %#012x\n", reg); + + xsc = &sc->sc; + device_printf(sc->dev, "xhci quirks: %#012x\n", xsc->sc_quirks); +} + +static void +snps_dwc3_dump_ctrlparams(struct snps_dwc3_softc *sc) +{ + const bus_size_t offs[] = { + DWC3_GHWPARAMS0, DWC3_GHWPARAMS1, DWC3_GHWPARAMS2, DWC3_GHWPARAMS3, + DWC3_GHWPARAMS4, DWC3_GHWPARAMS5, DWC3_GHWPARAMS6, DWC3_GHWPARAMS7, + DWC3_GHWPARAMS8, + }; + uint32_t reg; + int i; + + for (i = 0; i < nitems(offs); i++) { + reg = DWC3_READ(sc, offs[i]); + if (bootverbose) + device_printf(sc->dev, "hwparams[%d]: %#012x\n", i, reg); + } +} +#endif + +static void +snps_dwc3_reset(struct snps_dwc3_softc *sc) +{ + uint32_t gctl, ghwp0, phy2, phy3; + + ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); + + gctl = DWC3_READ(sc, DWC3_GCTL); + gctl |= DWC3_GCTL_CORESOFTRESET; + DWC3_WRITE(sc, DWC3_GCTL, gctl); + + phy2 = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); + phy2 |= DWC3_GUSB2PHYCFG0_PHYSOFTRST; + if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + phy2 &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; + DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); + + phy3 = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); + phy3 |= DWC3_GUSB3PIPECTL0_PHYSOFTRST; + if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + phy3 &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; + DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); + + DELAY(1000); + + phy2 &= ~DWC3_GUSB2PHYCFG0_PHYSOFTRST; + DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, phy2); + + phy3 &= ~DWC3_GUSB3PIPECTL0_PHYSOFTRST; + DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, phy3); + + gctl &= ~DWC3_GCTL_CORESOFTRESET; + DWC3_WRITE(sc, DWC3_GCTL, gctl); + +} + +static void +snps_dwc3_configure_host(struct snps_dwc3_softc *sc) +{ + uint32_t reg; + + reg = DWC3_READ(sc, DWC3_GCTL); + reg &= ~DWC3_GCTL_PRTCAPDIR_MASK; + reg |= DWC3_GCTL_PRTCAPDIR_HOST; + DWC3_WRITE(sc, DWC3_GCTL, reg); + + /* + * Enable the Host IN Auto Retry feature, making the + * host respond with a non-terminating retry ACK. + * XXX If we ever support more than host mode this needs a dr_mode check. + */ + reg = DWC3_READ(sc, DWC3_GUCTL); + reg |= DWC3_GUCTL_HOST_AUTO_RETRY; + DWC3_WRITE(sc, DWC3_GUCTL, reg); +} + +#ifdef FDT +static void +snps_dwc3_configure_phy(struct snps_dwc3_softc *sc, phandle_t node) +{ + char *phy_type; + uint32_t reg; + int nphy_types; + + phy_type = NULL; + nphy_types = OF_getprop_alloc(node, "phy_type", (void **)&phy_type); + if (nphy_types <= 0) + return; + + reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); + if (strncmp(phy_type, "utmi_wide", 9) == 0) { + reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); + reg |= DWC3_GUSB2PHYCFG0_PHYIF | + DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS); + } else { + reg &= ~(DWC3_GUSB2PHYCFG0_PHYIF | DWC3_GUSB2PHYCFG0_USBTRDTIM(0xf)); + reg |= DWC3_GUSB2PHYCFG0_PHYIF | + DWC3_GUSB2PHYCFG0_USBTRDTIM(DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS); + } + DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); + OF_prop_free(phy_type); +} +#endif + +static void +snps_dwc3_do_quirks(struct snps_dwc3_softc *sc) +{ + struct xhci_softc *xsc; + uint32_t ghwp0, reg; + + ghwp0 = DWC3_READ(sc, DWC3_GHWPARAMS0); + reg = DWC3_READ(sc, DWC3_GUSB2PHYCFG0); + if (device_has_property(sc->dev, "snps,dis-u2-freeclk-exists-quirk")) + reg &= ~DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; + else + reg |= DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS; + if (device_has_property(sc->dev, "snps,dis_u2_susphy_quirk")) + reg &= ~DWC3_GUSB2PHYCFG0_SUSPENDUSB20; + else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + reg |= DWC3_GUSB2PHYCFG0_SUSPENDUSB20; + if (device_has_property(sc->dev, "snps,dis_enblslpm_quirk")) + reg &= ~DWC3_GUSB2PHYCFG0_ENBLSLPM; + else + reg |= DWC3_GUSB2PHYCFG0_ENBLSLPM; + DWC3_WRITE(sc, DWC3_GUSB2PHYCFG0, reg); + + reg = DWC3_READ(sc, DWC3_GUCTL1); + if (device_has_property(sc->dev, "snps,dis-tx-ipgap-linecheck-quirk")) + reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS; + DWC3_WRITE(sc, DWC3_GUCTL1, reg); + + reg = DWC3_READ(sc, DWC3_GUSB3PIPECTL0); + if (device_has_property(sc->dev, "snps,dis-del-phy-power-chg-quirk")) + reg &= ~DWC3_GUSB3PIPECTL0_DELAYP1TRANS; + if (device_has_property(sc->dev, "snps,dis_rxdet_inp3_quirk")) + reg |= DWC3_GUSB3PIPECTL0_DISRXDETINP3; + if (device_has_property(sc->dev, "snps,dis_u3_susphy_quirk")) + reg &= ~DWC3_GUSB3PIPECTL0_SUSPENDUSB3; + else if ((ghwp0 & DWC3_GHWPARAMS0_MODE_MASK) == + DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE) + reg |= DWC3_GUSB3PIPECTL0_SUSPENDUSB3; + DWC3_WRITE(sc, DWC3_GUSB3PIPECTL0, reg); + + /* Port Disable does not work on <= 3.00a. Disable PORT_PED. */ + if ((sc->snpsid & 0xffff) <= 0x300a) { + xsc = &sc->sc; + xsc->sc_quirks |= XHCI_QUIRK_DISABLE_PORT_PED; + } +} + +static int +snps_dwc3_probe_common(device_t dev) +{ + char dr_mode[16] = { 0 }; + ssize_t s; + + s = device_get_property(dev, "dr_mode", dr_mode, sizeof(dr_mode), + DEVICE_PROP_BUFFER); + if (s == -1) { + device_printf(dev, "Cannot determine dr_mode\n"); + return (ENXIO); + } + if (strcmp(dr_mode, "host") != 0) { + device_printf(dev, + "Found dr_mode '%s' but only 'host' supported. s=%zd\n", + dr_mode, s); + return (ENXIO); + } + + device_set_desc(dev, "Synopsys Designware DWC3"); + return (BUS_PROBE_DEFAULT); +} + +static int +snps_dwc3_common_attach(device_t dev, bool is_fdt) +{ + struct snps_dwc3_softc *sc; +#ifdef FDT + phandle_t node; + phy_t usb2_phy, usb3_phy; + uint32_t reg; +#endif + int error, rid; + + sc = device_get_softc(dev); + sc->dev = dev; + + rid = 0; + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "Failed to map memory\n"); + return (ENXIO); + } + sc->bst = rman_get_bustag(sc->mem_res); + sc->bsh = rman_get_bushandle(sc->mem_res); + + sc->snpsid = DWC3_READ(sc, DWC3_GSNPSID); + sc->snpsversion = DWC3_VERSION(sc->snpsid); + sc->snpsrevision = DWC3_REVISION(sc->snpsid); + if (sc->snpsversion == DWC3_1_IP_ID || + sc->snpsversion == DWC3_2_IP_ID) { + sc->snpsrevision = DWC3_READ(sc, DWC3_1_VER_NUMBER); + sc->snpsversion_type = DWC3_READ(sc, DWC3_1_VER_TYPE); + } + if (bootverbose) { + switch (sc->snpsversion) { + case DWC3_IP_ID: + device_printf(sc->dev, "SNPS Version: DWC3 (%x %x)\n", + sc->snpsversion, sc->snpsrevision); + break; + case DWC3_1_IP_ID: + device_printf(sc->dev, "SNPS Version: DWC3.1 (%x %x %x)\n", + sc->snpsversion, sc->snpsrevision, + sc->snpsversion_type); + break; + case DWC3_2_IP_ID: + device_printf(sc->dev, "SNPS Version: DWC3.2 (%x %x %x)\n", + sc->snpsversion, sc->snpsrevision, + sc->snpsversion_type); + break; + } + } +#ifdef DWC3_DEBUG + snps_dwc3_dump_ctrlparams(sc); +#endif + +#ifdef FDT + if (!is_fdt) + goto skip_phys; + + node = ofw_bus_get_node(dev); + + /* Get the clocks if any */ + if (ofw_bus_is_compatible(dev, "rockchip,rk3328-dwc3") == 1 || + ofw_bus_is_compatible(dev, "rockchip,rk3568-dwc3") == 1) { + if (clk_get_by_ofw_name(dev, node, "ref_clk", &sc->clk_ref) != 0) + device_printf(dev, "Cannot get ref_clk\n"); + if (clk_get_by_ofw_name(dev, node, "suspend_clk", &sc->clk_suspend) != 0) + device_printf(dev, "Cannot get suspend_clk\n"); + if (clk_get_by_ofw_name(dev, node, "bus_clk", &sc->clk_bus) != 0) + device_printf(dev, "Cannot get bus_clk\n"); + } + + if (sc->clk_ref != NULL) { + if (clk_enable(sc->clk_ref) != 0) + device_printf(dev, "Cannot enable ref_clk\n"); + } + if (sc->clk_suspend != NULL) { + if (clk_enable(sc->clk_suspend) != 0) + device_printf(dev, "Cannot enable suspend_clk\n"); + } + if (sc->clk_bus != NULL) { + if (clk_enable(sc->clk_bus) != 0) + device_printf(dev, "Cannot enable bus_clk\n"); + } + + /* Get the phys */ + usb2_phy = usb3_phy = NULL; + error = phy_get_by_ofw_name(dev, node, "usb2-phy", &usb2_phy); + if (error == 0 && usb2_phy != NULL) + phy_enable(usb2_phy); + error = phy_get_by_ofw_name(dev, node, "usb3-phy", &usb3_phy); + if (error == 0 && usb3_phy != NULL) + phy_enable(usb3_phy); + if (sc->snpsversion == DWC3_IP_ID) { + if (sc->snpsrevision >= 0x290A) { + uint32_t hwparams3; + + hwparams3 = DWC3_READ(sc, DWC3_GHWPARAMS3); + if (DWC3_HWPARAMS3_SSPHY(hwparams3) == DWC3_HWPARAMS3_SSPHY_DISABLE) { + reg = DWC3_READ(sc, DWC3_GUCTL1); + if (bootverbose) + device_printf(dev, "Forcing USB2 clock only\n"); + reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK; + DWC3_WRITE(sc, DWC3_GUCTL1, reg); + } + } + } + snps_dwc3_configure_phy(sc, node); +skip_phys: +#endif + + snps_dwc3_reset(sc); + snps_dwc3_configure_host(sc); + snps_dwc3_do_quirks(sc); + +#ifdef DWC3_DEBUG + snsp_dwc3_dump_regs(sc, "Pre XHCI init"); +#endif + error = snps_dwc3_attach_xhci(dev); +#ifdef DWC3_DEBUG + snsp_dwc3_dump_regs(sc, "Post XHCI init"); +#endif + +#ifdef FDT + if (error) { + if (sc->clk_ref != NULL) + clk_disable(sc->clk_ref); + if (sc->clk_suspend != NULL) + clk_disable(sc->clk_suspend); + if (sc->clk_bus != NULL) + clk_disable(sc->clk_bus); + } +#endif + return (error); +} + +#ifdef FDT +static struct ofw_compat_data compat_data[] = { + { "snps,dwc3", 1 }, + { NULL, 0 } +}; + +static int +snps_dwc3_fdt_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + return (snps_dwc3_probe_common(dev)); +} + +static int +snps_dwc3_fdt_attach(device_t dev) +{ + + return (snps_dwc3_common_attach(dev, true)); +} + +static device_method_t snps_dwc3_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, snps_dwc3_fdt_probe), + DEVMETHOD(device_attach, snps_dwc3_fdt_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(snps_dwc3_fdt, snps_dwc3_fdt_driver, snps_dwc3_fdt_methods, + sizeof(struct snps_dwc3_softc), generic_xhci_driver); + +DRIVER_MODULE(snps_dwc3_fdt, simplebus, snps_dwc3_fdt_driver, 0, 0); +MODULE_DEPEND(snps_dwc3_fdt, xhci, 1, 1, 1); +#endif + +#ifdef DEV_ACPI +static char *dwc3_acpi_ids[] = { + "808622B7", /* This was an Intel PCI Vendor/Device ID used. */ + "PNP0D10", /* The generic XHCI PNP ID needing extra probe checks. */ + NULL +}; + +static int +snps_dwc3_acpi_probe(device_t dev) +{ + char *match; + int error; + + if (acpi_disabled("snps_dwc3")) + return (ENXIO); + + error = ACPI_ID_PROBE(device_get_parent(dev), dev, dwc3_acpi_ids, &match); + if (error > 0) + return (ENXIO); + + /* + * If we found the Generic XHCI PNP ID we can only attach if we have + * some other means to identify the device as dwc3. + */ + if (strcmp(match, "PNP0D10") == 0) { + /* This is needed in SolidRun's HoneyComb. */ + if (device_has_property(dev, "snps,dis_rxdet_inp3_quirk")) + goto is_dwc3; + + return (ENXIO); + } + +is_dwc3: + return (snps_dwc3_probe_common(dev)); +} + +static int +snps_dwc3_acpi_attach(device_t dev) +{ + + return (snps_dwc3_common_attach(dev, false)); +} + +static device_method_t snps_dwc3_acpi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, snps_dwc3_acpi_probe), + DEVMETHOD(device_attach, snps_dwc3_acpi_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(snps_dwc3_acpi, snps_dwc3_acpi_driver, snps_dwc3_acpi_methods, + sizeof(struct snps_dwc3_softc), generic_xhci_driver); + +DRIVER_MODULE(snps_dwc3_acpi, acpi, snps_dwc3_acpi_driver, 0, 0); +MODULE_DEPEND(snps_dwc3_acpi, usb, 1, 1, 1); +#endif diff --git a/sys/dev/usb/controller/dwc3/dwc3.h b/sys/dev/usb/controller/dwc3/dwc3.h new file mode 100644 index 000000000000..a2063d8cff31 --- /dev/null +++ b/sys/dev/usb/controller/dwc3/dwc3.h @@ -0,0 +1,137 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef _DWC3_H_ +#define _DWC3_H_ + +#define DWC3_IP_ID 0x5533 +#define DWC3_1_IP_ID 0x3331 +#define DWC3_2_IP_ID 0x3332 + +#define DWC3_VERSION_MASK 0xFFFF0000 +#define DWC3_REVISION_MASK 0xFFFF +#define DWC3_VERSION(x) (((x) & DWC3_VERSION_MASK) >> 16) +#define DWC3_REVISION(x) ((x) & DWC3_REVISION_MASK) + +#define DWC3_GSBUSCFG0 0xc100 +#define DWC3_GSBUSCFG1 0xc104 +#define DWC3_GTXTHRCFG 0xc108 +#define DWC3_GRXTHRCFG 0xc10C + +/* Global Core Control Register */ +#define DWC3_GCTL 0xc110 +#define DWC3_GCTL_PRTCAPDIR_MASK (0x3 << 12) +#define DWC3_GCTL_PRTCAPDIR_HOST (0x1 << 12) +#define DWC3_GCTL_PRTCAPDIR_DEVICE (0x2 << 12) +#define DWC3_GCTL_CORESOFTRESET (1 << 11) +#define DWC3_GCTL_DSBLCLKGTNG (1 << 0) + +#define DWC3_GPMSTS 0xc114 +#define DWC3_GSTS 0xc118 + +#define DWC3_GUCTL1 0xc11c +#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS (1 << 28) +#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK (1 << 26) + +#define DWC3_GSNPSID 0xc120 +#define DWC3_GGPIO 0xc124 +#define DWC3_GUID 0xc128 +#define DWC3_GUCTL 0xc12C +#define DWC3_GUCTL_HOST_AUTO_RETRY (1 << 14) +#define DWC3_GBUSERRADDRLO 0xc130 +#define DWC3_GBUSERRADDRHI 0xc134 +#define DWC3_GPRTBIMAPLO 0xc138 +#define DWC3_GHWPARAMS0 0xc140 +#define DWC3_GHWPARAMS0_MODE_DUALROLEDEVICE 0x2 +#define DWC3_GHWPARAMS0_MODE_MASK 0x3 +#define DWC3_GHWPARAMS1 0xc144 +#define DWC3_GHWPARAMS2 0xc148 +#define DWC3_GHWPARAMS3 0xc14C +#define DWC3_GHWPARAMS4 0xc150 +#define DWC3_GHWPARAMS5 0xc154 +#define DWC3_GHWPARAMS6 0xc158 +#define DWC3_GHWPARAMS7 0xc15C +#define DWC3_GDBGFIFOSPACE 0xc160 +#define DWC3_GDBGLTSSM 0xc164 +#define DWC3_GDBGLNMCC 0xc168 +#define DWC3_GDBGBMU 0xc16C +#define DWC3_GDBGLSPMUX 0xc170 +#define DWC3_GDBGLSP 0xc174 +#define DWC3_GDBGEPINFO0 0xc178 +#define DWC3_GDBGEPINFO1 0xc17C +#define DWC3_GPRTBIMAP_HSLO 0xc180 +#define DWC3_GPRTBIMAP_FSLO 0xc188 + +#define DWC3_1_VER_NUMBER 0xc1a0 +#define DWC3_1_VER_TYPE 0xc1a4 + +#define DWC3_GUSB2PHYCFG0 0xc200 +#define DWC3_GUSB2PHYCFG0_PHYSOFTRST (1 << 31) +#define DWC3_GUSB2PHYCFG0_U2_FREECLK_EXISTS (1 << 30) +#define DWC3_GUSB2PHYCFG0_USBTRDTIM(n) ((n) << 10) +#define DWC3_GUSB2PHYCFG0_USBTRDTIM_8BITS 9 +#define DWC3_GUSB2PHYCFG0_USBTRDTIM_16BITS 5 +#define DWC3_GUSB2PHYCFG0_ENBLSLPM (1 << 8) +#define DWC3_GUSB2PHYCFG0_PHYSEL(x) (((x) >> 7) & 0x1) /* 0 = USB2.0, 1 = USB1.1 */ +#define DWC3_GUSB2PHYCFG0_SUSPENDUSB20 (1 << 6) +#define DWC3_GUSB2PHYCFG0_ULPI_UTMI_SEL (1 << 4) +#define DWC3_GUSB2PHYCFG0_PHYIF (1 << 3) + +#define DWC3_GUSB3PIPECTL0 0xc2c0 +#define DWC3_GUSB3PIPECTL0_PHYSOFTRST (1 << 31) +#define DWC3_GUSB3PIPECTL0_DISRXDETINP3 (1 << 28) +#define DWC3_GUSB3PIPECTL0_DELAYP1TRANS (1 << 18) +#define DWC3_GUSB3PIPECTL0_SUSPENDUSB3 (1 << 17) + +#define DWC3_HWPARAMS3_SSPHY(x) ((x) & 0x3) +#define DWC3_HWPARAMS3_SSPHY_DISABLE 0 +#define DWC3_HWPARAMS3_SSPHY_GEN1 1 +#define DWC3_HWPARAMS3_SSPHY_GEN2 2 + +#define DWC3_GTXFIFOSIZ(x) (0xc300 + 0x4 * (x)) +#define DWC3_GRXFIFOSIZ(x) (0xc380 + 0x4 * (x)) +#define DWC3_GEVNTADRLO0 0xc400 +#define DWC3_GEVNTADRHI0 0xc404 +#define DWC3_GEVNTSIZ0 0xc408 +#define DWC3_GEVNTCOUNT0 0xc40C +#define DWC3_GHWPARAMS8 0xc600 +#define DWC3_GTXFIFOPRIDEV 0xc610 +#define DWC3_GTXFIFOPRIHST 0xc618 +#define DWC3_GRXFIFOPRIHST 0xc61c +#define DWC3_GFIFOPRIDBC 0xc620 +#define DWC3_GDMAHLRATIO 0xc624 +#define DWC3_GFLADJ 0xc630 +#define DWC3_DCFG 0xc700 +#define DWC3_DCTL 0xc704 +#define DWC3_DEVTEN 0xc708 +#define DWC3_DSTS 0xc70C +#define DWC3_DGCMDPAR 0xc710 +#define DWC3_DGCMD 0xc714 +#define DWC3_DALEPENA 0xc720 + +#endif /* _DWC3_H_ */ diff --git a/sys/dev/usb/controller/dwc3/rk_dwc3.c b/sys/dev/usb/controller/dwc3/rk_dwc3.c new file mode 100644 index 000000000000..f336490c386e --- /dev/null +++ b/sys/dev/usb/controller/dwc3/rk_dwc3.c @@ -0,0 +1,198 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Rockchip DWC3 glue + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +enum rk_dwc3_type { + RK3399 = 1, +}; + +static struct ofw_compat_data compat_data[] = { + { "rockchip,rk3399-dwc3", RK3399 }, + { NULL, 0 } +}; + +struct rk_dwc3_softc { + struct simplebus_softc sc; + device_t dev; + clk_t clk_ref; + clk_t clk_suspend; + clk_t clk_bus; + clk_t clk_axi_perf; + clk_t clk_usb3; + clk_t clk_grf; + hwreset_t rst_usb3; + enum rk_dwc3_type type; +}; + +static int +rk_dwc3_probe(device_t dev) +{ + phandle_t node; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + /* Binding says that we need a child node for the actual dwc3 controller */ + node = ofw_bus_get_node(dev); + if (OF_child(node) <= 0) + return (ENXIO); + + device_set_desc(dev, "Rockchip RK3399 DWC3"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_dwc3_attach(device_t dev) +{ + struct rk_dwc3_softc *sc; + device_t cdev; + phandle_t node, child; + int err; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + + /* Mandatory clocks */ + if (clk_get_by_ofw_name(dev, 0, "ref_clk", &sc->clk_ref) != 0) { + device_printf(dev, "Cannot get ref_clk clock\n"); + return (ENXIO); + } + err = clk_enable(sc->clk_ref); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_ref)); + return (ENXIO); + } + if (clk_get_by_ofw_name(dev, 0, "suspend_clk", &sc->clk_suspend) != 0) { + device_printf(dev, "Cannot get suspend_clk clock\n"); + return (ENXIO); + } + err = clk_enable(sc->clk_suspend); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_suspend)); + return (ENXIO); + } + if (clk_get_by_ofw_name(dev, 0, "bus_clk", &sc->clk_bus) != 0) { + device_printf(dev, "Cannot get bus_clk clock\n"); + return (ENXIO); + } + err = clk_enable(sc->clk_bus); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_bus)); + return (ENXIO); + } + if (clk_get_by_ofw_name(dev, 0, "grf_clk", &sc->clk_grf) == 0) { + err = clk_enable(sc->clk_grf); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_grf)); + return (ENXIO); + } + } + /* Optional clocks */ + if (clk_get_by_ofw_name(dev, 0, "aclk_usb3_rksoc_axi_perf", &sc->clk_axi_perf) == 0) { + err = clk_enable(sc->clk_axi_perf); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_axi_perf)); + return (ENXIO); + } + } + if (clk_get_by_ofw_name(dev, 0, "aclk_usb3", &sc->clk_usb3) == 0) { + err = clk_enable(sc->clk_usb3); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->clk_usb3)); + return (ENXIO); + } + } + + /* Put module out of reset */ + if (hwreset_get_by_ofw_name(dev, node, "usb3-otg", &sc->rst_usb3) == 0) { + if (hwreset_deassert(sc->rst_usb3) != 0) { + device_printf(dev, "Cannot deassert reset\n"); + return (ENXIO); + } + } + + simplebus_init(dev, node); + if (simplebus_fill_ranges(node, &sc->sc) < 0) { + device_printf(dev, "could not get ranges\n"); + return (ENXIO); + } + + for (child = OF_child(node); child > 0; child = OF_peer(child)) { + cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); + if (cdev != NULL) + device_probe_and_attach(cdev); + } + + return (bus_generic_attach(dev)); +} + +static device_method_t rk_dwc3_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk_dwc3_probe), + DEVMETHOD(device_attach, rk_dwc3_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(rk_dwc3, rk_dwc3_driver, rk_dwc3_methods, + sizeof(struct rk_dwc3_softc), simplebus_driver); +DRIVER_MODULE(rk_dwc3, simplebus, rk_dwc3_driver, 0, 0); -- cgit v1.3