From 63faed5b8e4f2755f127fcb8aa440480c0649327 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sat, 14 Apr 2012 13:54:10 +0000 Subject: Vendor import of llvm trunk r154661: http://llvm.org/svn/llvm-project/llvm/trunk@r154661 --- test/CodeGen/CellSPU/and_ops.ll | 3 +++ test/CodeGen/CellSPU/call.ll | 4 --- test/CodeGen/CellSPU/call_indirect.ll | 49 ----------------------------------- test/CodeGen/CellSPU/dg.exp | 5 ---- test/CodeGen/CellSPU/lit.local.cfg | 6 +++++ test/CodeGen/CellSPU/nand.ll | 4 +++ test/CodeGen/CellSPU/or_ops.ll | 3 +++ test/CodeGen/CellSPU/rotate_ops.ll | 2 +- test/CodeGen/CellSPU/select_bits.ll | 3 +++ test/CodeGen/CellSPU/shift_ops.ll | 12 ++++++--- test/CodeGen/CellSPU/shuffles.ll | 12 +++++---- test/CodeGen/CellSPU/struct_1.ll | 3 +++ test/CodeGen/CellSPU/v2i32.ll | 20 ++------------ 13 files changed, 40 insertions(+), 86 deletions(-) delete mode 100644 test/CodeGen/CellSPU/call_indirect.ll delete mode 100644 test/CodeGen/CellSPU/dg.exp create mode 100644 test/CodeGen/CellSPU/lit.local.cfg (limited to 'test/CodeGen/CellSPU') diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index 72478a1ca62d..4203e91068d0 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -5,6 +5,9 @@ ; RUN: grep andhi %t1.s | count 30 ; RUN: grep andbi %t1.s | count 4 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/call.ll b/test/CodeGen/CellSPU/call.ll index 559b266e59df..11cf770145ba 100644 --- a/test/CodeGen/CellSPU/call.ll +++ b/test/CodeGen/CellSPU/call.ll @@ -1,7 +1,3 @@ -; RUN: llc < %s -march=cellspu -regalloc=linearscan > %t1.s -; RUN: grep brsl %t1.s | count 1 -; RUN: grep brasl %t1.s | count 2 -; RUN: grep stqd %t1.s | count 82 ; RUN: llc < %s -march=cellspu | FileCheck %s target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" diff --git a/test/CodeGen/CellSPU/call_indirect.ll b/test/CodeGen/CellSPU/call_indirect.ll deleted file mode 100644 index 141361d5702b..000000000000 --- a/test/CodeGen/CellSPU/call_indirect.ll +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: llc < %s -march=cellspu -asm-verbose=0 -regalloc=linearscan > %t1.s -; RUN: llc < %s -march=cellspu -mattr=large_mem -asm-verbose=0 -regalloc=linearscan > %t2.s -; RUN: grep bisl %t1.s | count 7 -; RUN: grep ila %t1.s | count 1 -; RUN: grep rotqby %t1.s | count 5 -; RUN: grep lqa %t1.s | count 1 -; RUN: grep lqd %t1.s | count 12 -; RUN: grep dispatch_tab %t1.s | count 5 -; RUN: grep bisl %t2.s | count 7 -; RUN: grep ilhu %t2.s | count 2 -; RUN: grep iohl %t2.s | count 2 -; RUN: grep rotqby %t2.s | count 5 -; RUN: grep lqd %t2.s | count 13 -; RUN: grep ilhu %t2.s | count 2 -; RUN: grep ai %t2.s | count 9 -; RUN: grep dispatch_tab %t2.s | count 6 - -; ModuleID = 'call_indirect.bc' -target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128" -target triple = "spu-unknown-elf" - -@dispatch_tab = global [6 x void (i32, float)*] zeroinitializer, align 16 - -define void @dispatcher(i32 %i_arg, float %f_arg) { -entry: - %tmp2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 0), align 16 - tail call void %tmp2( i32 %i_arg, float %f_arg ) - %tmp2.1 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 1), align 4 - tail call void %tmp2.1( i32 %i_arg, float %f_arg ) - %tmp2.2 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 2), align 4 - tail call void %tmp2.2( i32 %i_arg, float %f_arg ) - %tmp2.3 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 3), align 4 - tail call void %tmp2.3( i32 %i_arg, float %f_arg ) - %tmp2.4 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 4), align 4 - tail call void %tmp2.4( i32 %i_arg, float %f_arg ) - %tmp2.5 = load void (i32, float)** getelementptr ([6 x void (i32, float)*]* @dispatch_tab, i32 0, i32 5), align 4 - tail call void %tmp2.5( i32 %i_arg, float %f_arg ) - ret void -} - -@ptr_list = internal global [1 x void ()*] [ void ()* inttoptr (i64 4294967295 to void ()*) ], align 4 -@ptr.a = internal global void ()** getelementptr ([1 x void ()*]* @ptr_list, i32 0, i32 1), align 16 - -define void @double_indirect_call() { - %a = load void ()*** @ptr.a, align 16 - %b = load void ()** %a, align 4 - tail call void %b() - ret void -} diff --git a/test/CodeGen/CellSPU/dg.exp b/test/CodeGen/CellSPU/dg.exp deleted file mode 100644 index d41647991a0a..000000000000 --- a/test/CodeGen/CellSPU/dg.exp +++ /dev/null @@ -1,5 +0,0 @@ -load_lib llvm.exp - -if { [llvm_supports_target CellSPU] } { - RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]] -} diff --git a/test/CodeGen/CellSPU/lit.local.cfg b/test/CodeGen/CellSPU/lit.local.cfg new file mode 100644 index 000000000000..ea00867701b2 --- /dev/null +++ b/test/CodeGen/CellSPU/lit.local.cfg @@ -0,0 +1,6 @@ +config.suffixes = ['.ll', '.c', '.cpp'] + +targets = set(config.root.targets_to_build.split()) +if not 'CellSPU' in targets: + config.unsupported = True + diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll index b770cad8dfce..57ac709c5414 100644 --- a/test/CodeGen/CellSPU/nand.ll +++ b/test/CodeGen/CellSPU/nand.ll @@ -3,6 +3,10 @@ ; RUN: grep and %t1.s | count 94 ; RUN: grep xsbh %t1.s | count 2 ; RUN: grep xshw %t1.s | count 4 + +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll index 4f1febbad79c..f329266a3c23 100644 --- a/test/CodeGen/CellSPU/or_ops.ll +++ b/test/CodeGen/CellSPU/or_ops.ll @@ -6,6 +6,9 @@ ; RUN: grep orbi %t1.s | count 15 ; RUN: FileCheck %s < %t1.s +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/rotate_ops.ll b/test/CodeGen/CellSPU/rotate_ops.ll index b1219e6f56e5..977093527609 100644 --- a/test/CodeGen/CellSPU/rotate_ops.ll +++ b/test/CodeGen/CellSPU/rotate_ops.ll @@ -163,7 +163,7 @@ define i8 @rotri8(i8 %A) { define <2 x float> @test1(<4 x float> %param ) { ; CHECK: test1 -; CHECK: rotqbyi +; CHECK: shufb %el = extractelement <4 x float> %param, i32 1 %vec1 = insertelement <1 x float> undef, float %el, i32 0 %rv = shufflevector <1 x float> %vec1, <1 x float> undef, <2 x i32> diff --git a/test/CodeGen/CellSPU/select_bits.ll b/test/CodeGen/CellSPU/select_bits.ll index c804256f513b..65e0aa6fa0b0 100644 --- a/test/CodeGen/CellSPU/select_bits.ll +++ b/test/CodeGen/CellSPU/select_bits.ll @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=cellspu > %t1.s ; RUN: grep selb %t1.s | count 56 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index 3252c776ecbf..f4aad44ed650 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -march=cellspu > %t1.s ; RUN: grep {shlh } %t1.s | count 10 ; RUN: grep {shlhi } %t1.s | count 3 -; RUN: grep {shl } %t1.s | count 11 +; RUN: grep {shl } %t1.s | count 10 ; RUN: grep {shli } %t1.s | count 3 ; RUN: grep {xshw } %t1.s | count 5 -; RUN: grep {and } %t1.s | count 14 -; RUN: grep {andi } %t1.s | count 2 -; RUN: grep {rotmi } %t1.s | count 2 +; RUN: grep {and } %t1.s | count 15 +; RUN: grep {andi } %t1.s | count 4 +; RUN: grep {rotmi } %t1.s | count 4 ; RUN: grep {rotqmbyi } %t1.s | count 1 ; RUN: grep {rotqmbii } %t1.s | count 2 ; RUN: grep {rotqmby } %t1.s | count 1 @@ -342,3 +342,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %val, <8 x i16> %sh) { %rv = ashr <8 x i16> %val, %sh ret <8 x i16> %rv } + +define <2 x i64> @special_const() { + ret <2 x i64> +} diff --git a/test/CodeGen/CellSPU/shuffles.ll b/test/CodeGen/CellSPU/shuffles.ll index c88a258c26c7..973586bf6cf2 100644 --- a/test/CodeGen/CellSPU/shuffles.ll +++ b/test/CodeGen/CellSPU/shuffles.ll @@ -1,12 +1,14 @@ ; RUN: llc -O1 --march=cellspu < %s | FileCheck %s +;CHECK: shuffle define <4 x float> @shuffle(<4 x float> %param1, <4 x float> %param2) { ; CHECK: cwd {{\$.}}, 0($sp) ; CHECK: shufb {{\$., \$4, \$3, \$.}} %val= shufflevector <4 x float> %param1, <4 x float> %param2, <4 x i32> ret <4 x float> %val } - + +;CHECK: splat define <4 x float> @splat(float %param1) { ; CHECK: lqa ; CHECK: shufb $3 @@ -16,6 +18,7 @@ define <4 x float> @splat(float %param1) { ret <4 x float> %val } +;CHECK: test_insert define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) { %sl2_17_tmp1 = insertelement <2 x float> zeroinitializer, float %val1, i32 0 ;CHECK: lqa $6, @@ -31,6 +34,7 @@ define void @test_insert( <2 x float>* %ptr, float %val1, float %val2 ) { ret void } +;CHECK: test_insert_1 define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) { ;CHECK: cwd $5, 4($sp) ;CHECK: shufb $3, $4, $3, $5 @@ -39,6 +43,7 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) { ret <4 x float> %rv } +;CHECK: test_v2i32 define <2 x i32> @test_v2i32(<4 x i32>%vec) { ;CHECK: rotqbyi $3, $3, 4 @@ -49,17 +54,14 @@ define <2 x i32> @test_v2i32(<4 x i32>%vec) define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec) { -;CHECK: rotqbyi $3, $3, 8 -;CHECK: bi $lr %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <4 x i32> ret <4 x i32> %rv } +;CHECK: test_v4i32_rot4 define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec) { -;CHECK: rotqbyi $3, $3, 4 -;CHECK: bi $lr %rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <4 x i32> ret <4 x i32> %rv diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll index adbb5efa28ba..8c3275080c69 100644 --- a/test/CodeGen/CellSPU/struct_1.ll +++ b/test/CodeGen/CellSPU/struct_1.ll @@ -22,6 +22,9 @@ ; RUN: grep shufb %t2.s | count 7 ; RUN: grep stqd %t2.s | count 7 +; CellSPU legalization is over-sensitive to Legalize's traversal order. +; XFAIL: * + ; ModuleID = 'struct_1.bc' target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128" target triple = "spu" diff --git a/test/CodeGen/CellSPU/v2i32.ll b/test/CodeGen/CellSPU/v2i32.ll index 71d4aba63332..9c5b89613df9 100644 --- a/test/CodeGen/CellSPU/v2i32.ll +++ b/test/CodeGen/CellSPU/v2i32.ll @@ -9,7 +9,8 @@ define %vec @test_ret(%vec %param) define %vec @test_add(%vec %param) { -;CHECK: a {{\$.}}, $3, $3 +;CHECK: shufb +;CHECK: addx %1 = add %vec %param, %param ;CHECK: bi $lr ret %vec %1 @@ -17,21 +18,14 @@ define %vec @test_add(%vec %param) define %vec @test_sub(%vec %param) { -;CHECK: sf {{\$.}}, $4, $3 %1 = sub %vec %param, - ;CHECK: bi $lr ret %vec %1 } define %vec @test_mul(%vec %param) { -;CHECK: mpyu -;CHECK: mpyh -;CHECK: a {{\$., \$., \$.}} -;CHECK: a {{\$., \$., \$.}} %1 = mul %vec %param, %param - ;CHECK: bi $lr ret %vec %1 } @@ -56,22 +50,12 @@ define i32 @test_extract() { define void @test_store( %vec %val, %vec* %ptr) { -;CHECK: stqd $3, 0(${{.}}) -;CHECK: bi $lr store %vec %val, %vec* %ptr ret void } -;Alignment of <2 x i32> is not *directly* defined in the ABI -;It probably is safe to interpret it as an array, thus having 8 byte -;alignment (according to ABI). This tests that the size of -;[2 x <2 x i32>] is 16 bytes, i.e. there is no padding between the -;two arrays define <2 x i32>* @test_alignment( [2 x <2 x i32>]* %ptr) { -; CHECK-NOT: ai $3, $3, 16 -; CHECK: ai $3, $3, 8 -; CHECK: bi $lr %rv = getelementptr [2 x <2 x i32>]* %ptr, i32 0, i32 1 ret <2 x i32>* %rv } -- cgit v1.3