From dd58ef019b700900793a1eb48b52123db01b654e Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 30 Dec 2015 11:46:15 +0000 Subject: Vendor import of llvm trunk r256633: https://llvm.org/svn/llvm-project/llvm/trunk@256633 --- .../CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll | 27 ++ test/CodeGen/Mips/addi.ll | 2 +- test/CodeGen/Mips/adjust-callstack-sp.ll | 2 +- test/CodeGen/Mips/align16.ll | 2 +- test/CodeGen/Mips/alloca16.ll | 2 +- test/CodeGen/Mips/and1.ll | 2 +- test/CodeGen/Mips/asm-large-immediate.ll | 3 +- test/CodeGen/Mips/atomicops.ll | 2 +- test/CodeGen/Mips/beqzc.ll | 2 +- test/CodeGen/Mips/beqzc1.ll | 2 +- test/CodeGen/Mips/br-jmp.ll | 4 +- test/CodeGen/Mips/brconeq.ll | 2 +- test/CodeGen/Mips/brconeqk.ll | 2 +- test/CodeGen/Mips/brconeqz.ll | 2 +- test/CodeGen/Mips/brconge.ll | 2 +- test/CodeGen/Mips/brcongt.ll | 2 +- test/CodeGen/Mips/brconle.ll | 2 +- test/CodeGen/Mips/brconlt.ll | 2 +- test/CodeGen/Mips/brconne.ll | 2 +- test/CodeGen/Mips/brconnek.ll | 2 +- test/CodeGen/Mips/brconnez.ll | 2 +- test/CodeGen/Mips/brind.ll | 2 +- test/CodeGen/Mips/brsize3.ll | 4 +- test/CodeGen/Mips/brsize3a.ll | 2 +- test/CodeGen/Mips/cconv/arguments-varargs.ll | 72 ++-- test/CodeGen/Mips/ci2.ll | 2 +- test/CodeGen/Mips/cmplarge.ll | 2 +- test/CodeGen/Mips/const1.ll | 2 +- test/CodeGen/Mips/const4a.ll | 2 +- test/CodeGen/Mips/const6.ll | 4 +- test/CodeGen/Mips/const6a.ll | 4 +- test/CodeGen/Mips/div.ll | 2 +- test/CodeGen/Mips/div_rem.ll | 2 +- test/CodeGen/Mips/divu.ll | 2 +- test/CodeGen/Mips/divu_remu.ll | 2 +- test/CodeGen/Mips/eh.ll | 2 +- test/CodeGen/Mips/emergency-spill-slot-near-fp.ll | 4 +- test/CodeGen/Mips/emutls_generic.ll | 70 ++++ test/CodeGen/Mips/ex2.ll | 2 +- test/CodeGen/Mips/extins.ll | 2 +- test/CodeGen/Mips/f16abs.ll | 2 +- test/CodeGen/Mips/fixdfsf.ll | 4 +- test/CodeGen/Mips/fp16instrinsmc.ll | 4 +- test/CodeGen/Mips/fp16mix.ll | 6 +- test/CodeGen/Mips/fp16static.ll | 2 +- test/CodeGen/Mips/helloworld.ll | 12 +- test/CodeGen/Mips/hf16_1.ll | 4 +- test/CodeGen/Mips/hf16call32.ll | 408 ++++++++++----------- test/CodeGen/Mips/hf16call32_body.ll | 206 +++++------ test/CodeGen/Mips/hf1_body.ll | 18 +- test/CodeGen/Mips/hfptrcall.ll | 2 +- test/CodeGen/Mips/i32k.ll | 2 +- .../CodeGen/Mips/inlineasm-assembler-directives.ll | 4 +- test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll | 36 +- test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll | 4 +- test/CodeGen/Mips/inlineasm-operand-code.ll | 185 +++++----- test/CodeGen/Mips/inlineasm_constraint.ll | 94 +++-- test/CodeGen/Mips/inlineasmmemop.ll | 8 +- test/CodeGen/Mips/insn-zero-size-bb.ll | 4 +- test/CodeGen/Mips/interrupt-attr-64-error.ll | 9 + test/CodeGen/Mips/interrupt-attr-args-error.ll | 9 + test/CodeGen/Mips/interrupt-attr-error.ll | 9 + test/CodeGen/Mips/interrupt-attr.ll | 244 ++++++++++++ test/CodeGen/Mips/jtstat.ll | 2 +- test/CodeGen/Mips/l3mc.ll | 20 +- test/CodeGen/Mips/lb1.ll | 2 +- test/CodeGen/Mips/lbu1.ll | 2 +- test/CodeGen/Mips/lcb2.ll | 4 +- test/CodeGen/Mips/lcb3c.ll | 2 +- test/CodeGen/Mips/lcb4a.ll | 2 +- test/CodeGen/Mips/lcb5.ll | 2 +- test/CodeGen/Mips/lh1.ll | 2 +- test/CodeGen/Mips/lhu1.ll | 2 +- test/CodeGen/Mips/llcarry.ll | 2 +- test/CodeGen/Mips/llvm-ir/atomicrmx.ll | 26 ++ test/CodeGen/Mips/llvm-ir/call.ll | 14 + test/CodeGen/Mips/llvm-ir/load-atomic.ll | 42 +++ test/CodeGen/Mips/llvm-ir/sqrt.ll | 13 + test/CodeGen/Mips/llvm-ir/store-atomic.ll | 42 +++ test/CodeGen/Mips/madd-msub.ll | 2 +- test/CodeGen/Mips/mbrsize4a.ll | 2 +- test/CodeGen/Mips/mips16-hf-attr-2.ll | 2 +- test/CodeGen/Mips/mips16-hf-attr.ll | 2 +- test/CodeGen/Mips/mips16_32_1.ll | 2 +- test/CodeGen/Mips/mips16_32_10.ll | 2 +- test/CodeGen/Mips/mips16_32_3.ll | 2 +- test/CodeGen/Mips/mips16_32_4.ll | 2 +- test/CodeGen/Mips/mips16_32_5.ll | 2 +- test/CodeGen/Mips/mips16_32_6.ll | 2 +- test/CodeGen/Mips/mips16_32_7.ll | 2 +- test/CodeGen/Mips/mips16_fpret.ll | 8 +- test/CodeGen/Mips/mips16ex.ll | 2 +- test/CodeGen/Mips/mips16fpe.ll | 6 +- test/CodeGen/Mips/misha.ll | 2 +- test/CodeGen/Mips/msa/elm_copy.ll | 5 +- test/CodeGen/Mips/mul.ll | 2 +- test/CodeGen/Mips/mulll.ll | 2 +- test/CodeGen/Mips/mulull.ll | 2 +- test/CodeGen/Mips/nacl-align.ll | 7 +- test/CodeGen/Mips/neg1.ll | 2 +- test/CodeGen/Mips/no-odd-spreg-msa.ll | 24 +- test/CodeGen/Mips/nomips16.ll | 2 +- test/CodeGen/Mips/not1.ll | 2 +- test/CodeGen/Mips/null.ll | 2 +- test/CodeGen/Mips/or1.ll | 2 +- test/CodeGen/Mips/powif64_16.ll | 2 +- test/CodeGen/Mips/rem.ll | 2 +- test/CodeGen/Mips/remu.ll | 2 +- test/CodeGen/Mips/s2rem.ll | 4 +- test/CodeGen/Mips/sb1.ll | 2 +- test/CodeGen/Mips/sel1c.ll | 2 +- test/CodeGen/Mips/sel2c.ll | 2 +- test/CodeGen/Mips/selTBteqzCmpi.ll | 2 +- test/CodeGen/Mips/selTBtnezCmpi.ll | 2 +- test/CodeGen/Mips/selTBtnezSlti.ll | 2 +- test/CodeGen/Mips/seleq.ll | 2 +- test/CodeGen/Mips/seleqk.ll | 2 +- test/CodeGen/Mips/selgek.ll | 2 +- test/CodeGen/Mips/selgt.ll | 2 +- test/CodeGen/Mips/selle.ll | 2 +- test/CodeGen/Mips/selltk.ll | 2 +- test/CodeGen/Mips/selne.ll | 2 +- test/CodeGen/Mips/selnek.ll | 2 +- test/CodeGen/Mips/selpat.ll | 2 +- test/CodeGen/Mips/seteq.ll | 2 +- test/CodeGen/Mips/seteqz.ll | 2 +- test/CodeGen/Mips/setge.ll | 2 +- test/CodeGen/Mips/setgek.ll | 2 +- test/CodeGen/Mips/setle.ll | 2 +- test/CodeGen/Mips/setlt.ll | 2 +- test/CodeGen/Mips/setltk.ll | 2 +- test/CodeGen/Mips/setne.ll | 2 +- test/CodeGen/Mips/setuge.ll | 2 +- test/CodeGen/Mips/setugt.ll | 2 +- test/CodeGen/Mips/setule.ll | 2 +- test/CodeGen/Mips/setult.ll | 2 +- test/CodeGen/Mips/setultk.ll | 2 +- test/CodeGen/Mips/sh1.ll | 2 +- test/CodeGen/Mips/simplebr.ll | 2 +- test/CodeGen/Mips/sitofp-selectcc-opt.ll | 3 +- test/CodeGen/Mips/sll1.ll | 2 +- test/CodeGen/Mips/sll2.ll | 2 +- test/CodeGen/Mips/sr1.ll | 4 +- test/CodeGen/Mips/sra1.ll | 2 +- test/CodeGen/Mips/sra2.ll | 2 +- test/CodeGen/Mips/srl1.ll | 2 +- test/CodeGen/Mips/srl2.ll | 2 +- test/CodeGen/Mips/stchar.ll | 4 +- test/CodeGen/Mips/stldst.ll | 2 +- test/CodeGen/Mips/sub1.ll | 2 +- test/CodeGen/Mips/sub2.ll | 2 +- test/CodeGen/Mips/tail16.ll | 2 +- test/CodeGen/Mips/tailcall.ll | 2 +- test/CodeGen/Mips/tls-alias.ll | 2 +- test/CodeGen/Mips/tls16.ll | 2 +- test/CodeGen/Mips/tls16_2.ll | 2 +- test/CodeGen/Mips/trap1.ll | 2 +- test/CodeGen/Mips/ul1.ll | 2 +- test/CodeGen/Mips/xor1.ll | 2 +- 159 files changed, 1213 insertions(+), 703 deletions(-) create mode 100644 test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll create mode 100644 test/CodeGen/Mips/emutls_generic.ll create mode 100644 test/CodeGen/Mips/interrupt-attr-64-error.ll create mode 100644 test/CodeGen/Mips/interrupt-attr-args-error.ll create mode 100644 test/CodeGen/Mips/interrupt-attr-error.ll create mode 100644 test/CodeGen/Mips/interrupt-attr.ll create mode 100644 test/CodeGen/Mips/llvm-ir/atomicrmx.ll create mode 100644 test/CodeGen/Mips/llvm-ir/load-atomic.ll create mode 100644 test/CodeGen/Mips/llvm-ir/sqrt.ll create mode 100644 test/CodeGen/Mips/llvm-ir/store-atomic.ll (limited to 'test/CodeGen/Mips') diff --git a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll new file mode 100644 index 000000000000..203e5a7e1595 --- /dev/null +++ b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s + +; CHECK: FastISel missed terminator: ret i32 0 + +define i32 @foo() { +entry: + ret i32 0 +} diff --git a/test/CodeGen/Mips/addi.ll b/test/CodeGen/Mips/addi.ll index b6af2ee45687..f1db843caf64 100644 --- a/test/CodeGen/Mips/addi.ll +++ b/test/CodeGen/Mips/addi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16 @i = global i32 6, align 4 @j = global i32 12, align 4 diff --git a/test/CodeGen/Mips/adjust-callstack-sp.ll b/test/CodeGen/Mips/adjust-callstack-sp.ll index 8c61a650a962..e4afcd835005 100644 --- a/test/CodeGen/Mips/adjust-callstack-sp.ll +++ b/test/CodeGen/Mips/adjust-callstack-sp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s -check-prefix=M16 +; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=M16 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 diff --git a/test/CodeGen/Mips/align16.ll b/test/CodeGen/Mips/align16.ll index f385adfaa04c..ac6685dd5524 100644 --- a/test/CodeGen/Mips/align16.ll +++ b/test/CodeGen/Mips/align16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=16 @i = global i32 25, align 4 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/test/CodeGen/Mips/alloca16.ll b/test/CodeGen/Mips/alloca16.ll index be8cc740310b..d728d3bb0b7b 100644 --- a/test/CodeGen/Mips/alloca16.ll +++ b/test/CodeGen/Mips/alloca16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 25, align 4 @jjjj = global i32 35, align 4 diff --git a/test/CodeGen/Mips/and1.ll b/test/CodeGen/Mips/and1.ll index 57076a4d4fcf..a2bf4f080a07 100644 --- a/test/CodeGen/Mips/and1.ll +++ b/test/CodeGen/Mips/and1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/test/CodeGen/Mips/asm-large-immediate.ll b/test/CodeGen/Mips/asm-large-immediate.ll index 246fff615edb..c75b9e4ad12b 100644 --- a/test/CodeGen/Mips/asm-large-immediate.ll +++ b/test/CodeGen/Mips/asm-large-immediate.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -no-integrated-as < %s | FileCheck %s + define void @test() { entry: ; CHECK: /* result: 68719476738 */ diff --git a/test/CodeGen/Mips/atomicops.ll b/test/CodeGen/Mips/atomicops.ll index 0ff9f5c22a84..18a48ca5023b 100644 --- a/test/CodeGen/Mips/atomicops.ll +++ b/test/CodeGen/Mips/atomicops.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [8 x i8] c"%d, %d\0A\00", align 1 diff --git a/test/CodeGen/Mips/beqzc.ll b/test/CodeGen/Mips/beqzc.ll index 37bece884212..c0845f7185e1 100644 --- a/test/CodeGen/Mips/beqzc.ll +++ b/test/CodeGen/Mips/beqzc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/beqzc1.ll b/test/CodeGen/Mips/beqzc1.ll index 1f5575f099fa..144983513edf 100644 --- a/test/CodeGen/Mips/beqzc1.ll +++ b/test/CodeGen/Mips/beqzc1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/br-jmp.ll b/test/CodeGen/Mips/br-jmp.ll index 9ca8d159614f..5e94c755c969 100644 --- a/test/CodeGen/Mips/br-jmp.ll +++ b/test/CodeGen/Mips/br-jmp.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 define void @count(i32 %x, i32 %y, i32 %z) noreturn nounwind readnone { entry: diff --git a/test/CodeGen/Mips/brconeq.ll b/test/CodeGen/Mips/brconeq.ll index f555528bbb64..7c3c31e0ec3c 100644 --- a/test/CodeGen/Mips/brconeq.ll +++ b/test/CodeGen/Mips/brconeq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brconeqk.ll b/test/CodeGen/Mips/brconeqk.ll index 59edae82e5ad..85d257e8d797 100644 --- a/test/CodeGen/Mips/brconeqk.ll +++ b/test/CodeGen/Mips/brconeqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/test/CodeGen/Mips/brconeqz.ll b/test/CodeGen/Mips/brconeqz.ll index 22c566407528..cf1beed49bb4 100644 --- a/test/CodeGen/Mips/brconeqz.ll +++ b/test/CodeGen/Mips/brconeqz.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/test/CodeGen/Mips/brconge.ll b/test/CodeGen/Mips/brconge.ll index 46d19847d9bc..f3f059ff2d54 100644 --- a/test/CodeGen/Mips/brconge.ll +++ b/test/CodeGen/Mips/brconge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brcongt.ll b/test/CodeGen/Mips/brcongt.ll index cefacb8318b0..7dffdb411211 100644 --- a/test/CodeGen/Mips/brcongt.ll +++ b/test/CodeGen/Mips/brcongt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brconle.ll b/test/CodeGen/Mips/brconle.ll index e1f15ecb6b92..99599f84db17 100644 --- a/test/CodeGen/Mips/brconle.ll +++ b/test/CodeGen/Mips/brconle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 -5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brconlt.ll b/test/CodeGen/Mips/brconlt.ll index 049f35c393fe..487018c22f26 100644 --- a/test/CodeGen/Mips/brconlt.ll +++ b/test/CodeGen/Mips/brconlt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/brconne.ll b/test/CodeGen/Mips/brconne.ll index b260320b94e1..e0cbe378fe3c 100644 --- a/test/CodeGen/Mips/brconne.ll +++ b/test/CodeGen/Mips/brconne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 5, align 4 @j = global i32 5, align 4 diff --git a/test/CodeGen/Mips/brconnek.ll b/test/CodeGen/Mips/brconnek.ll index 778a5cce72b3..0b9234fe3b9d 100644 --- a/test/CodeGen/Mips/brconnek.ll +++ b/test/CodeGen/Mips/brconnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @result = global i32 0, align 4 diff --git a/test/CodeGen/Mips/brconnez.ll b/test/CodeGen/Mips/brconnez.ll index 754714b21daf..27cf9e8cacb8 100644 --- a/test/CodeGen/Mips/brconnez.ll +++ b/test/CodeGen/Mips/brconnez.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 0, align 4 @result = global i32 0, align 4 diff --git a/test/CodeGen/Mips/brind.ll b/test/CodeGen/Mips/brind.ll index a3e9b8011a2b..ed2c3b3dddb7 100644 --- a/test/CodeGen/Mips/brind.ll +++ b/test/CodeGen/Mips/brind.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @main.L = internal unnamed_addr constant [5 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* blockaddress(@main, %L3), i8* blockaddress(@main, %L4), i8* null], align 4 @str = private unnamed_addr constant [2 x i8] c"A\00" diff --git a/test/CodeGen/Mips/brsize3.ll b/test/CodeGen/Mips/brsize3.ll index dad0d841d4c6..1e76879409c6 100644 --- a/test/CodeGen/Mips/brsize3.ll +++ b/test/CodeGen/Mips/brsize3.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-no-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-no-short -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-long +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-long ; ModuleID = 'brsize3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/brsize3a.ll b/test/CodeGen/Mips/brsize3a.ll index e1cd5893ceda..24516018b9b7 100644 --- a/test/CodeGen/Mips/brsize3a.ll +++ b/test/CodeGen/Mips/brsize3a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-short ; ModuleID = 'brsize3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/cconv/arguments-varargs.ll b/test/CodeGen/Mips/cconv/arguments-varargs.ll index af217c92dab8..d1a196738aee 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs.ll @@ -55,7 +55,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -89,7 +89,7 @@ entry: ; ALL-DAG: sh [[ARG1]], 2([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -117,12 +117,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i16 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 store volatile i16 %arg1, i16* %e1, align 2 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i16 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 store volatile i16 %arg2, i16* %e2, align 2 @@ -173,7 +173,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -207,7 +207,7 @@ entry: ; ALL-DAG: sw [[ARG1]], 4([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -235,12 +235,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i32 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 store volatile i32 %arg1, i32* %e1, align 4 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i32 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 store volatile i32 %arg2, i32* %e2, align 4 @@ -291,7 +291,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] (and realign pointer for O32) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -328,7 +328,7 @@ entry: ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. @@ -362,12 +362,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i64 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 store volatile i64 %arg1, i64* %e1, align 8 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i64 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 store volatile i64 %arg2, i64* %e2, align 8 @@ -418,7 +418,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -452,7 +452,7 @@ entry: ; ALL-DAG: sh [[ARG1]], 2([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -480,12 +480,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i16 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 store volatile i16 %arg1, i16* %e1, align 2 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i16 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 store volatile i16 %arg2, i16* %e2, align 2 @@ -536,7 +536,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -570,7 +570,7 @@ entry: ; ALL-DAG: sw [[ARG1]], 4([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -598,12 +598,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i32 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 store volatile i32 %arg1, i32* %e1, align 4 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i32 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 store volatile i32 %arg2, i32* %e2, align 4 @@ -654,7 +654,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] (and realign pointer for O32) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -691,7 +691,7 @@ entry: ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. @@ -725,12 +725,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i64 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 store volatile i64 %arg1, i64* %e1, align 8 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i64 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 store volatile i64 %arg2, i64* %e2, align 8 @@ -780,7 +780,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -814,7 +814,7 @@ entry: ; ALL-DAG: sh [[ARG1]], 2([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -842,12 +842,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i16 %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1 store volatile i16 %arg1, i16* %e1, align 2 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i16 %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2 store volatile i16 %arg2, i16* %e2, align 2 @@ -897,7 +897,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -931,7 +931,7 @@ entry: ; ALL-DAG: sw [[ARG1]], 4([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; O32-DAG: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -959,12 +959,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i32 %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1 store volatile i32 %arg1, i32* %e1, align 4 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i32 %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2 store volatile i32 %arg2, i32* %e2, align 4 @@ -1014,7 +1014,7 @@ entry: ; Store [[VA]] ; O32-DAG: sw [[VA]], 0([[SP]]) -; ALL: # ANCHOR1 +; ALL: teqi $zero, 1 ; Increment [[VA]] (and realign pointer for O32) ; O32: lw [[VA:\$[0-9]+]], 0([[SP]]) @@ -1051,7 +1051,7 @@ entry: ; NEW-DAG: ld [[ARG1:\$[0-9]+]], 0([[VA]]) ; NEW-DAG: sd [[ARG1]], 8([[GV]]) -; ALL: # ANCHOR2 +; ALL: teqi $zero, 2 ; Increment [[VA]] again. ; FIXME: We're still aligned from the last one but CodeGen doesn't spot that. @@ -1085,12 +1085,12 @@ entry: %ap2 = bitcast i8** %ap to i8* call void @llvm.va_start(i8* %ap2) - call void asm sideeffect "# ANCHOR1", ""() + call void asm sideeffect "teqi $$zero, 1", ""() %arg1 = va_arg i8** %ap, i64 %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1 store volatile i64 %arg1, i64* %e1, align 8 - call void asm sideeffect "# ANCHOR2", ""() + call void asm sideeffect "teqi $$zero, 2", ""() %arg2 = va_arg i8** %ap, i64 %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2 store volatile i64 %arg2, i64* %e2, align 8 diff --git a/test/CodeGen/Mips/ci2.ll b/test/CodeGen/Mips/ci2.ll index 4687748879ac..bb16fa83fc5c 100644 --- a/test/CodeGen/Mips/ci2.ll +++ b/test/CodeGen/Mips/ci2.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=constisle +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=constisle @i = common global i32 0, align 4 @b = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/cmplarge.ll b/test/CodeGen/Mips/cmplarge.ll index 79019065a905..1ca5b921e0bc 100644 --- a/test/CodeGen/Mips/cmplarge.ll +++ b/test/CodeGen/Mips/cmplarge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=cmp16 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" target triple = "mipsel--linux-gnu" diff --git a/test/CodeGen/Mips/const1.ll b/test/CodeGen/Mips/const1.ll index 1a5d58bd3f95..2bcd405179b2 100644 --- a/test/CodeGen/Mips/const1.ll +++ b/test/CodeGen/Mips/const1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s ; ModuleID = 'const1.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll index c31e54a01036..d1182d7fc6ec 100644 --- a/test/CodeGen/Mips/const4a.ll +++ b/test/CodeGen/Mips/const4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax ; ModuleID = 'const4.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/const6.ll b/test/CodeGen/Mips/const6.ll index 49e98ea78703..c576f573a43b 100644 --- a/test/CodeGen/Mips/const6.ll +++ b/test/CodeGen/Mips/const6.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands -mips-constant-islands-no-load-relaxation < %s | FileCheck %s -check-prefix=no-load-relax ; ModuleID = 'const6.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/const6a.ll b/test/CodeGen/Mips/const6a.ll index 54a3f2234dc2..653cdeb920f3 100644 --- a/test/CodeGen/Mips/const6a.ll +++ b/test/CodeGen/Mips/const6a.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax ; ModuleID = 'const6a.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/div.ll b/test/CodeGen/Mips/div.ll index 731841c554fa..92258bce02d2 100644 --- a/test/CodeGen/Mips/div.ll +++ b/test/CodeGen/Mips/div.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 100, align 4 @jjjj = global i32 -4, align 4 diff --git a/test/CodeGen/Mips/div_rem.ll b/test/CodeGen/Mips/div_rem.ll index e64529cee841..be1e001a24c3 100644 --- a/test/CodeGen/Mips/div_rem.ll +++ b/test/CodeGen/Mips/div_rem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 -4, align 4 diff --git a/test/CodeGen/Mips/divu.ll b/test/CodeGen/Mips/divu.ll index 5bc765a71eb9..ce1b70cacf6f 100644 --- a/test/CodeGen/Mips/divu.ll +++ b/test/CodeGen/Mips/divu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 100, align 4 @jjjj = global i32 4, align 4 diff --git a/test/CodeGen/Mips/divu_remu.ll b/test/CodeGen/Mips/divu_remu.ll index a079440b913f..0e094cbe48ae 100644 --- a/test/CodeGen/Mips/divu_remu.ll +++ b/test/CodeGen/Mips/divu_remu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 4, align 4 diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 2f843d9da9a6..19f3d4d23d64 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -24,7 +24,7 @@ entry: lpad: ; preds = %entry ; CHECK-EL: # %lpad -; CHECK-EL: bne $5 +; CHECK-EL: beq $5 %exn.val = landingpad { i8*, i32 } cleanup diff --git a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index 58dd16c9f9c8..54092b4e3ebe 100644 --- a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -1,5 +1,5 @@ ; Check that register scavenging spill slot is close to $fp. -; RUN: llc -march=mipsel -O0 -fast-isel=false < %s | FileCheck %s +; RUN: llc -march=mipsel -O0 < %s | FileCheck %s ; CHECK: sw ${{.*}}, 8($sp) ; CHECK: lw ${{.*}}, 8($sp) @@ -31,4 +31,4 @@ entry: ret i32 0 } -attributes #0 = { noinline optnone "no-frame-pointer-elim"="true" } +attributes #0 = { noinline "no-frame-pointer-elim"="true" } diff --git a/test/CodeGen/Mips/emutls_generic.ll b/test/CodeGen/Mips/emutls_generic.ll new file mode 100644 index 000000000000..a6cf23aa67ff --- /dev/null +++ b/test/CodeGen/Mips/emutls_generic.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -emulated-tls -mtriple=mipsel-linux-android -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=MIPS_32 %s +; RUN: llc < %s -emulated-tls -mtriple=mips64el-linux-android -relocation-model=pic \ +; RUN: | FileCheck -check-prefix=MIPS_64 %s + +; Make sure that TLS symbols are emitted in expected order. + +@external_x = external thread_local global i32, align 8 +@external_y = thread_local global i8 7, align 2 +@internal_y = internal thread_local global i64 9, align 16 + +define i32* @get_external_x() { +entry: + ret i32* @external_x +} + +define i8* @get_external_y() { +entry: + ret i8* @external_y +} + +define i64* @get_internal_y() { +entry: + ret i64* @internal_y +} + +; MIPS_32-LABEL: get_external_y: +; MIPS_32-LABEL: get_internal_y: +; MIPS_32: lw {{.+}}(__emutls_v.internal_y +; MIPS_32: lw {{.+}}call16(__emutls_get_address +; MIPS_32-NOT: __emutls_t.external_x +; MIPS_32-NOT: __emutls_v.external_x: +; MIPS_32: .data +; MIPS_32: .align 2 +; MIPS_32-LABEL: __emutls_v.external_y: +; MIPS_32: .section .rodata, +; MIPS_32-LABEL: __emutls_t.external_y: +; MIPS_32-NEXT: .byte 7 +; MIPS_32: .data +; MIPS_32: .align 2 +; MIPS_32-LABEL: __emutls_v.internal_y: +; MIPS_32-NEXT: .4byte 8 +; MIPS_32-NEXT: .4byte 16 +; MIPS_32-NEXT: .4byte 0 +; MIPS_32-NEXT: .4byte __emutls_t.internal_y +; MIPS_32-LABEL: __emutls_t.internal_y: +; MIPS_32-NEXT: .8byte 9 + +; MIPS_64-LABEL: get_external_x: +; MIPS_64-LABEL: get_external_y: +; MIPS_64-LABEL: get_internal_y: +; MIPS_64: ld {{.+}}(__emutls_v.internal_y +; MIPS_64: ld {{.+}}call16(__emutls_get_address +; MIPS_64-NOT: __emutls_t.external_x +; MIPS_64-NOT: __emutls_v.external_x: +; MIPS_64-LABEL: __emutls_v.external_y: +; MIPS_64-NOT: __emutls_v.external_x: +; MIPS_64: .section .rodata, +; MIPS_64-LABEL: __emutls_t.external_y: +; MIPS_64-NEXT: .byte 7 +; MIPS_64: .data +; MIPS_64: .align 3 +; MIPS_64-LABEL: __emutls_v.internal_y: +; MIPS_64-NEXT: .8byte 8 +; MIPS_64-NEXT: .8byte 16 +; MIPS_64-NEXT: .8byte 0 +; MIPS_64-NEXT: .8byte __emutls_t.internal_y +; MIPS_64: .section .rodata, +; MIPS_64-LABEL: __emutls_t.internal_y: +; MIPS_64-NEXT: .8byte 9 diff --git a/test/CodeGen/Mips/ex2.ll b/test/CodeGen/Mips/ex2.ll index 7547fdf81e35..87fe77035ec2 100644 --- a/test/CodeGen/Mips/ex2.ll +++ b/test/CodeGen/Mips/ex2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1 @_ZTIPKc = external constant i8* diff --git a/test/CodeGen/Mips/extins.ll b/test/CodeGen/Mips/extins.ll index 6604f89b1843..0b327a91bbfd 100644 --- a/test/CodeGen/Mips/extins.ll +++ b/test/CodeGen/Mips/extins.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=32R2 -; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s -check-prefix=16 +; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s -check-prefix=16 define i32 @ext0_5_9(i32 %s, i32 %pos, i32 %sz) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/f16abs.ll b/test/CodeGen/Mips/f16abs.ll index 838983274e9b..6c33e011719e 100644 --- a/test/CodeGen/Mips/f16abs.ll +++ b/test/CodeGen/Mips/f16abs.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=static @y = global double -1.450000e+00, align 8 @x = common global double 0.000000e+00, align 8 diff --git a/test/CodeGen/Mips/fixdfsf.ll b/test/CodeGen/Mips/fixdfsf.ll index 869579922d51..5eb336bf6499 100644 --- a/test/CodeGen/Mips/fixdfsf.ll +++ b/test/CodeGen/Mips/fixdfsf.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic2 @x = common global double 0.000000e+00, align 8 @y = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/fp16instrinsmc.ll b/test/CodeGen/Mips/fp16instrinsmc.ll index 797be2668d40..258b1bf97d7b 100644 --- a/test/CodeGen/Mips/fp16instrinsmc.ll +++ b/test/CodeGen/Mips/fp16instrinsmc.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=1010111 -mips-os16 < %s | FileCheck %s -check-prefix=fmask @x = global float 1.500000e+00, align 4 @xn = global float -1.900000e+01, align 4 diff --git a/test/CodeGen/Mips/fp16mix.ll b/test/CodeGen/Mips/fp16mix.ll index a94f838fb675..d97759422cf9 100644 --- a/test/CodeGen/Mips/fp16mix.ll +++ b/test/CodeGen/Mips/fp16mix.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -mips32-function-mask=10 -mips-os16 < %s | FileCheck %s -check-prefix=fmask1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10 -mips-os16 < %s | FileCheck %s -check-prefix=fmask1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -mips32-function-mask=01 -mips-os16 < %s | FileCheck %s -check-prefix=fmask2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=01 -mips-os16 < %s | FileCheck %s -check-prefix=fmask2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -mips32-function-mask=10. -mips-os16 < %s | FileCheck %s -check-prefix=fmask1nr +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -mips32-function-mask=10. -mips-os16 < %s | FileCheck %s -check-prefix=fmask1nr ; Function Attrs: nounwind optsize readnone define void @foo1() { diff --git a/test/CodeGen/Mips/fp16static.ll b/test/CodeGen/Mips/fp16static.ll index 4e5059ed39e9..341ecf02cb5c 100644 --- a/test/CodeGen/Mips/fp16static.ll +++ b/test/CodeGen/Mips/fp16static.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 @x = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/helloworld.ll b/test/CodeGen/Mips/helloworld.ll index a0dbdf3afd47..f715313354ea 100644 --- a/test/CodeGen/Mips/helloworld.ll +++ b/test/CodeGen/Mips/helloworld.ll @@ -1,10 +1,10 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=C2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PE +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s | FileCheck %s -check-prefix=ST2 ; -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=SR32 diff --git a/test/CodeGen/Mips/hf16_1.ll b/test/CodeGen/Mips/hf16_1.ll index 103fd2d7fd63..aea241e27195 100644 --- a/test/CodeGen/Mips/hf16_1.ll +++ b/test/CodeGen/Mips/hf16_1.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=1 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=2 @x = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll index 3b3f8f799111..9fc94cac5175 100644 --- a/test/CodeGen/Mips/hf16call32.ll +++ b/test/CodeGen/Mips/hf16call32.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel @x = common global float 0.000000e+00, align 4 @y = common global float 0.000000e+00, align 4 @@ -751,280 +751,280 @@ land.end289: ; preds = %land.rhs286, %land. } declare void @v_sf(float) #1 -; stel: .section .mips16.call.fp.v_sf,"ax",@progbits -; stel: .ent __call_stub_fp_v_sf -; stel: mtc1 $4,$f12 -; stel: lui $25,%hi(v_sf) -; stel: addiu $25,$25,%lo(v_sf) -; stel: jr $25 -; stel: .end __call_stub_fp_v_sf +; stel: .section .mips16.call.fp.v_sf,"ax",@progbits +; stel: .ent __call_stub_fp_v_sf +; stel: mtc1 $4, $f12 +; stel: lui $25, %hi(v_sf) +; stel: addiu $25, $25, %lo(v_sf) +; stel: jr $25 +; stel: .end __call_stub_fp_v_sf declare i32 @printf(i8*, ...) #1 declare void @v_df(double) #1 -; stel: .section .mips16.call.fp.v_df,"ax",@progbits -; stel: .ent __call_stub_fp_v_df +; stel: .section .mips16.call.fp.v_df,"ax",@progbits +; stel: .ent __call_stub_fp_v_df ; stel: #APP -; setl: .set reorder -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: lui $25,%hi(v_df) -; stel: addiu $25,$25,%lo(v_df) -; stel: jr $25 -; stel: .end __call_stub_fp_v_df +; stel: .set reorder +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: lui $25, %hi(v_df) +; stel: addiu $25, $25, %lo(v_df) +; stel: jr $25 +; stel: .end __call_stub_fp_v_df declare void @v_sf_sf(float, float) #1 -; stel: .section .mips16.call.fp.v_sf_sf,"ax",@progbits -; stel: .ent __call_stub_fp_v_sf_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f14 -; stel: lui $25,%hi(v_sf_sf) -; stel: addiu $25,$25,%lo(v_sf_sf) -; stel: jr $25 -; stel: .end __call_stub_fp_v_sf_sf +; stel: .section .mips16.call.fp.v_sf_sf,"ax",@progbits +; stel: .ent __call_stub_fp_v_sf_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f14 +; stel: lui $25, %hi(v_sf_sf) +; stel: addiu $25, $25, %lo(v_sf_sf) +; stel: jr $25 +; stel: .end __call_stub_fp_v_sf_sf declare void @v_sf_df(float, double) #1 -; stel: .section .mips16.call.fp.v_sf_df,"ax",@progbits -; stel: .ent __call_stub_fp_v_sf_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: lui $25,%hi(v_sf_df) -; stel: addiu $25,$25,%lo(v_sf_df) -; stel: jr $25 -; stel: .end __call_stub_fp_v_sf_df +; stel: .section .mips16.call.fp.v_sf_df,"ax",@progbits +; stel: .ent __call_stub_fp_v_sf_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: lui $25, %hi(v_sf_df) +; stel: addiu $25, $25, %lo(v_sf_df) +; stel: jr $25 +; stel: .end __call_stub_fp_v_sf_df declare void @v_df_sf(double, float) #1 -; stel: .section .mips16.call.fp.v_df_sf,"ax",@progbits -; stel: .ent __call_stub_fp_v_df_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: lui $25,%hi(v_df_sf) -; stel: addiu $25,$25,%lo(v_df_sf) -; stel: jr $25 -; stel: .end __call_stub_fp_v_df_sf +; stel: .section .mips16.call.fp.v_df_sf,"ax",@progbits +; stel: .ent __call_stub_fp_v_df_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: lui $25, %hi(v_df_sf) +; stel: addiu $25, $25, %lo(v_df_sf) +; stel: jr $25 +; stel: .end __call_stub_fp_v_df_sf declare void @v_df_df(double, double) #1 -; stel: .section .mips16.call.fp.v_df_df,"ax",@progbits -; stel: .ent __call_stub_fp_v_df_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: lui $25,%hi(v_df_df) -; stel: addiu $25,$25,%lo(v_df_df) -; stel: jr $25 -; stel: .end __call_stub_fp_v_df_df +; stel: .section .mips16.call.fp.v_df_df,"ax",@progbits +; stel: .ent __call_stub_fp_v_df_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: lui $25, %hi(v_df_df) +; stel: addiu $25, $25, %lo(v_df_df) +; stel: jr $25 +; stel: .end __call_stub_fp_v_df_df declare float @sf_v() #1 -; stel: .section .mips16.call.fp.sf_v,"ax",@progbits -; stel: .ent __call_stub_fp_sf_v +; stel: .section .mips16.call.fp.sf_v,"ax",@progbits +; stel: .ent __call_stub_fp_sf_v ; stel: move $18, $31 ; stel: jal sf_v -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_v +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_v declare float @sf_sf(float) #1 -; stel: .section .mips16.call.fp.sf_sf,"ax",@progbits -; stel: .ent __call_stub_fp_sf_sf -; stel: mtc1 $4,$f12 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_sf,"ax",@progbits +; stel: .ent __call_stub_fp_sf_sf +; stel: mtc1 $4, $f12 +; stel: move $18, ${{31|ra}} ; stel: jal sf_sf -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_sf +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_sf declare float @sf_df(double) #1 -; stel: .section .mips16.call.fp.sf_df,"ax",@progbits -; stel: .ent __call_stub_fp_sf_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_df,"ax",@progbits +; stel: .ent __call_stub_fp_sf_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: move $18, ${{31|ra}} ; stel: jal sf_df -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_df +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_df declare float @sf_sf_sf(float, float) #1 -; stel: .section .mips16.call.fp.sf_sf_sf,"ax",@progbits -; stel: .ent __call_stub_fp_sf_sf_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f14 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_sf_sf,"ax",@progbits +; stel: .ent __call_stub_fp_sf_sf_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f14 +; stel: move $18, ${{31|ra}} ; stel: jal sf_sf_sf -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_sf_sf +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_sf_sf declare float @sf_sf_df(float, double) #1 -; stel: .section .mips16.call.fp.sf_sf_df,"ax",@progbits -; stel: .ent __call_stub_fp_sf_sf_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_sf_df,"ax",@progbits +; stel: .ent __call_stub_fp_sf_sf_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: move $18, ${{31|ra}} ; stel: jal sf_sf_df -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_sf_df +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_sf_df declare float @sf_df_sf(double, float) #1 -; stel: .section .mips16.call.fp.sf_df_sf,"ax",@progbits -; stel: .ent __call_stub_fp_sf_df_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_df_sf,"ax",@progbits +; stel: .ent __call_stub_fp_sf_df_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: move $18, ${{31|ra}} ; stel: jal sf_df_sf -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_df_sf +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_df_sf declare float @sf_df_df(double, double) #1 -; stel: .section .mips16.call.fp.sf_df_df,"ax",@progbits -; stel: .ent __call_stub_fp_sf_df_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sf_df_df,"ax",@progbits +; stel: .ent __call_stub_fp_sf_df_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: move $18, ${{31|ra}} ; stel: jal sf_df_df -; stel: mfc1 $2,$f0 -; stel: jr $18 -; stel: .end __call_stub_fp_sf_df_df +; stel: mfc1 $2, $f0 +; stel: jr $18 +; stel: .end __call_stub_fp_sf_df_df declare double @df_v() #1 -; stel: .section .mips16.call.fp.df_v,"ax",@progbits -; stel: .ent __call_stub_fp_df_v +; stel: .section .mips16.call.fp.df_v,"ax",@progbits +; stel: .ent __call_stub_fp_df_v ; stel: move $18, $31 ; stel: jal df_v -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_v +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_v declare double @df_sf(float) #1 -; stel: .section .mips16.call.fp.df_sf,"ax",@progbits -; stel: .ent __call_stub_fp_df_sf -; stel: mtc1 $4,$f12 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_sf,"ax",@progbits +; stel: .ent __call_stub_fp_df_sf +; stel: mtc1 $4, $f12 +; stel: move $18, ${{31|ra}} ; stel: jal df_sf -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_sf +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_sf declare double @df_df(double) #1 -; stel: .section .mips16.call.fp.df_df,"ax",@progbits -; stel: .ent __call_stub_fp_df_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_df,"ax",@progbits +; stel: .ent __call_stub_fp_df_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: move $18, ${{31|ra}} ; stel: jal df_df -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_df +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_df declare double @df_sf_sf(float, float) #1 -; stel: .section .mips16.call.fp.df_sf_sf,"ax",@progbits -; stel: .ent __call_stub_fp_df_sf_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f14 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_sf_sf,"ax",@progbits +; stel: .ent __call_stub_fp_df_sf_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f14 +; stel: move $18, ${{31|ra}} ; stel: jal df_sf_sf -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_sf_sf +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_sf_sf declare double @df_sf_df(float, double) #1 -; stel: .section .mips16.call.fp.df_sf_df,"ax",@progbits -; stel: .ent __call_stub_fp_df_sf_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_sf_df,"ax",@progbits +; stel: .ent __call_stub_fp_df_sf_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: move $18, ${{31|ra}} ; stel: jal df_sf_df -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_sf_df +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_sf_df declare double @df_df_sf(double, float) #1 -; stel: .section .mips16.call.fp.df_df_sf,"ax",@progbits -; stel: .ent __call_stub_fp_df_df_sf -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_df_sf,"ax",@progbits +; stel: .ent __call_stub_fp_df_df_sf +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: move $18, ${{31|ra}} ; stel: jal df_df_sf -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_df_sf +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_df_sf declare double @df_df_df(double, double) #1 -; stel: .section .mips16.call.fp.df_df_df,"ax",@progbits -; stel: .ent __call_stub_fp_df_df_df -; stel: mtc1 $4,$f12 -; stel: mtc1 $5,$f13 -; stel: mtc1 $6,$f14 -; stel: mtc1 $7,$f15 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.df_df_df,"ax",@progbits +; stel: .ent __call_stub_fp_df_df_df +; stel: mtc1 $4, $f12 +; stel: mtc1 $5, $f13 +; stel: mtc1 $6, $f14 +; stel: mtc1 $7, $f15 +; stel: move $18, ${{31|ra}} ; stel: jal df_df_df -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_df_df_df +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_df_df_df declare { float, float } @sc_v() #1 -; stel: .section .mips16.call.fp.sc_v,"ax",@progbits -; stel: .ent __call_stub_fp_sc_v +; stel: .section .mips16.call.fp.sc_v,"ax",@progbits +; stel: .ent __call_stub_fp_sc_v ; stel: move $18, $31 ; stel: jal sc_v -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f2 -; stel: jr $18 -; stel: .end __call_stub_fp_sc_v +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f2 +; stel: jr $18 +; stel: .end __call_stub_fp_sc_v declare { float, float } @sc_sf(float) #1 -; stel: .section .mips16.call.fp.sc_sf,"ax",@progbits -; stel: .ent __call_stub_fp_sc_sf -; stel: mtc1 $4,$f12 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.sc_sf,"ax",@progbits +; stel: .ent __call_stub_fp_sc_sf +; stel: mtc1 $4, $f12 +; stel: move $18, ${{31|ra}} ; stel: jal sc_sf -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f2 -; stel: jr $18 -; stel: .end __call_stub_fp_sc_sf +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f2 +; stel: jr $18 +; stel: .end __call_stub_fp_sc_sf declare { double, double } @dc_v() #1 -; stel: .section .mips16.call.fp.dc_v,"ax",@progbits -; stel: .ent __call_stub_fp_dc_v +; stel: .section .mips16.call.fp.dc_v,"ax",@progbits +; stel: .ent __call_stub_fp_dc_v ; stel: move $18, $31 ; stel: jal dc_v -; stel: mfc1 $4,$f2 -; stel: mfc1 $5,$f3 -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_dc_v +; stel: mfc1 $4, $f2 +; stel: mfc1 $5, $f3 +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_dc_v declare { double, double } @dc_sf(float) #1 -; stel: .section .mips16.call.fp.dc_sf,"ax",@progbits -; stel: .ent __call_stub_fp_dc_sf -; stel: mtc1 $4,$f12 -; stel: move $18, $31 +; stel: .section .mips16.call.fp.dc_sf,"ax",@progbits +; stel: .ent __call_stub_fp_dc_sf +; stel: mtc1 $4, $f12 +; stel: move $18, ${{31|ra}} ; stel: jal dc_sf -; stel: mfc1 $4,$f2 -; stel: mfc1 $5,$f3 -; stel: mfc1 $2,$f0 -; stel: mfc1 $3,$f1 -; stel: jr $18 -; stel: .end __call_stub_fp_dc_sf +; stel: mfc1 $4, $f2 +; stel: mfc1 $5, $f3 +; stel: mfc1 $2, $f0 +; stel: mfc1 $3, $f1 +; stel: jr $18 +; stel: .end __call_stub_fp_dc_sf attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/hf16call32_body.ll b/test/CodeGen/Mips/hf16call32_body.ll index d06256cc564f..1a04fd46f8bd 100644 --- a/test/CodeGen/Mips/hf16call32_body.ll +++ b/test/CodeGen/Mips/hf16call32_body.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=stel @x = external global float @xd = external global double @@ -18,13 +18,13 @@ entry: store float %0, float* @x, align 4 ret void } -; stel: .section .mips16.fn.v_sf,"ax",@progbits -; stel: .ent __fn_stub_v_sf -; stel: la $25,v_sf -; stel: mfc1 $4,$f12 -; stel: jr $25 -; stel: __fn_local_v_sf = v_sf -; stel: .end __fn_stub_v_sf +; stel: .section .mips16.fn.v_sf,"ax",@progbits +; stel: .ent __fn_stub_v_sf +; stel: la $25, v_sf +; stel: mfc1 $4, $f12 +; stel: jr $25 +; stel: __fn_local_v_sf = v_sf +; stel: .end __fn_stub_v_sf declare i32 @printf(i8*, ...) #1 @@ -38,14 +38,14 @@ entry: ret void } -; stel: .section .mips16.fn.v_df,"ax",@progbits -; stel: .ent __fn_stub_v_df -; stel: la $25,v_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: jr $25 -; stel: __fn_local_v_df = v_df -; stel: .end __fn_stub_v_df +; stel: .section .mips16.fn.v_df,"ax",@progbits +; stel: .ent __fn_stub_v_df +; stel: la $25, v_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: jr $25 +; stel: __fn_local_v_df = v_df +; stel: .end __fn_stub_v_df ; Function Attrs: nounwind define void @v_sf_sf(float %p1, float %p2) #0 { @@ -61,14 +61,14 @@ entry: ret void } -; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits -; stel: .ent __fn_stub_v_sf_sf -; stel: la $25,v_sf_sf -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f14 -; stel: jr $25 -; stel: __fn_local_v_sf_sf = v_sf_sf -; stel: .end __fn_stub_v_sf_sf +; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits +; stel: .ent __fn_stub_v_sf_sf +; stel: la $25, v_sf_sf +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f14 +; stel: jr $25 +; stel: __fn_local_v_sf_sf = v_sf_sf +; stel: .end __fn_stub_v_sf_sf ; Function Attrs: nounwind define void @v_sf_df(float %p1, double %p2) #0 { @@ -84,15 +84,15 @@ entry: ret void } -; stel: .section .mips16.fn.v_sf_df,"ax",@progbits -; stel: .ent __fn_stub_v_sf_df -; stel: la $25,v_sf_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $6,$f14 -; stel: mfc1 $7,$f15 -; stel: jr $25 -; stel: __fn_local_v_sf_df = v_sf_df -; stel: .end __fn_stub_v_sf_df +; stel: .section .mips16.fn.v_sf_df,"ax",@progbits +; stel: .ent __fn_stub_v_sf_df +; stel: la $25, v_sf_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $6, $f14 +; stel: mfc1 $7, $f15 +; stel: jr $25 +; stel: __fn_local_v_sf_df = v_sf_df +; stel: .end __fn_stub_v_sf_df ; Function Attrs: nounwind define void @v_df_sf(double %p1, float %p2) #0 { @@ -108,15 +108,15 @@ entry: ret void } -; stel: .section .mips16.fn.v_df_sf,"ax",@progbits -; stel: .ent __fn_stub_v_df_sf -; stel: la $25,v_df_sf -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: mfc1 $6,$f14 -; stel: jr $25 -; stel: __fn_local_v_df_sf = v_df_sf -; stel: .end __fn_stub_v_df_sf +; stel: .section .mips16.fn.v_df_sf,"ax",@progbits +; stel: .ent __fn_stub_v_df_sf +; stel: la $25, v_df_sf +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: mfc1 $6, $f14 +; stel: jr $25 +; stel: __fn_local_v_df_sf = v_df_sf +; stel: .end __fn_stub_v_df_sf ; Function Attrs: nounwind define void @v_df_df(double %p1, double %p2) #0 { @@ -132,16 +132,16 @@ entry: ret void } -; stel: .section .mips16.fn.v_df_df,"ax",@progbits -; stel: .ent __fn_stub_v_df_df -; stel: la $25,v_df_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: mfc1 $6,$f14 -; stel: mfc1 $7,$f15 -; stel: jr $25 -; stel: __fn_local_v_df_df = v_df_df -; stel: .end __fn_stub_v_df_df +; stel: .section .mips16.fn.v_df_df,"ax",@progbits +; stel: .ent __fn_stub_v_df_df +; stel: la $25, v_df_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: mfc1 $6, $f14 +; stel: mfc1 $7, $f15 +; stel: jr $25 +; stel: __fn_local_v_df_df = v_df_df +; stel: .end __fn_stub_v_df_df ; Function Attrs: nounwind define float @sf_v() #0 { @@ -162,13 +162,13 @@ entry: } -; stel: .section .mips16.fn.sf_sf,"ax",@progbits -; stel: .ent __fn_stub_sf_sf -; stel: la $25,sf_sf -; stel: mfc1 $4,$f12 -; stel: jr $25 -; stel: __fn_local_sf_sf = sf_sf -; stel: .end __fn_stub_sf_sf +; stel: .section .mips16.fn.sf_sf,"ax",@progbits +; stel: .ent __fn_stub_sf_sf +; stel: la $25, sf_sf +; stel: mfc1 $4, $f12 +; stel: jr $25 +; stel: __fn_local_sf_sf = sf_sf +; stel: .end __fn_stub_sf_sf ; Function Attrs: nounwind @@ -182,14 +182,14 @@ entry: ret float %1 } -; stel: .section .mips16.fn.sf_df,"ax",@progbits -; stel: .ent __fn_stub_sf_df -; stel: la $25,sf_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: jr $25 -; stel: __fn_local_sf_df = sf_df -; stel: .end __fn_stub_sf_df +; stel: .section .mips16.fn.sf_df,"ax",@progbits +; stel: .ent __fn_stub_sf_df +; stel: la $25, sf_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: jr $25 +; stel: __fn_local_sf_df = sf_df +; stel: .end __fn_stub_sf_df ; Function Attrs: nounwind define float @sf_sf_sf(float %p1, float %p2) #0 { @@ -206,14 +206,14 @@ entry: ret float %2 } -; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits -; stel: .ent __fn_stub_sf_sf_sf -; stel: la $25,sf_sf_sf -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f14 -; stel: jr $25 -; stel: __fn_local_sf_sf_sf = sf_sf_sf -; stel: .end __fn_stub_sf_sf_sf +; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits +; stel: .ent __fn_stub_sf_sf_sf +; stel: la $25, sf_sf_sf +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f14 +; stel: jr $25 +; stel: __fn_local_sf_sf_sf = sf_sf_sf +; stel: .end __fn_stub_sf_sf_sf ; Function Attrs: nounwind define float @sf_sf_df(float %p1, double %p2) #0 { @@ -230,15 +230,15 @@ entry: ret float %2 } -; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits -; stel: .ent __fn_stub_sf_sf_df -; stel: la $25,sf_sf_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $6,$f14 -; stel: mfc1 $7,$f15 -; stel: jr $25 -; stel: __fn_local_sf_sf_df = sf_sf_df -; stel: .end __fn_stub_sf_sf_df +; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits +; stel: .ent __fn_stub_sf_sf_df +; stel: la $25, sf_sf_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $6, $f14 +; stel: mfc1 $7, $f15 +; stel: jr $25 +; stel: __fn_local_sf_sf_df = sf_sf_df +; stel: .end __fn_stub_sf_sf_df ; Function Attrs: nounwind define float @sf_df_sf(double %p1, float %p2) #0 { @@ -255,15 +255,15 @@ entry: ret float %2 } -; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits -; stel: .ent __fn_stub_sf_df_sf -; stel: la $25,sf_df_sf -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: mfc1 $6,$f14 -; stel: jr $25 -; stel: __fn_local_sf_df_sf = sf_df_sf -; stel: .end __fn_stub_sf_df_sf +; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits +; stel: .ent __fn_stub_sf_df_sf +; stel: la $25, sf_df_sf +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: mfc1 $6, $f14 +; stel: jr $25 +; stel: __fn_local_sf_df_sf = sf_df_sf +; stel: .end __fn_stub_sf_df_sf ; Function Attrs: nounwind define float @sf_df_df(double %p1, double %p2) #0 { @@ -280,15 +280,15 @@ entry: ret float %2 } -; stel: .section .mips16.fn.sf_df_df,"ax",@progbits -; stel: .ent __fn_stub_sf_df_df -; stel: la $25,sf_df_df -; stel: mfc1 $4,$f12 -; stel: mfc1 $5,$f13 -; stel: mfc1 $6,$f14 -; stel: mfc1 $7,$f15 -; stel: jr $25 -; stel: __fn_local_sf_df_df = sf_df_df -; stel: .end __fn_stub_sf_df_df +; stel: .section .mips16.fn.sf_df_df,"ax",@progbits +; stel: .ent __fn_stub_sf_df_df +; stel: la $25, sf_df_df +; stel: mfc1 $4, $f12 +; stel: mfc1 $5, $f13 +; stel: mfc1 $6, $f14 +; stel: mfc1 $7, $f15 +; stel: jr $25 +; stel: __fn_local_sf_df_df = sf_df_df +; stel: .end __fn_stub_sf_df_df attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/Mips/hf1_body.ll b/test/CodeGen/Mips/hf1_body.ll index 71a1b960c5b3..adf45109d69a 100644 --- a/test/CodeGen/Mips/hf1_body.ll +++ b/test/CodeGen/Mips/hf1_body.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16 @x = external global float @@ -11,11 +11,11 @@ entry: store float %0, float* @x, align 4 ret void } -; picfp16: .ent __fn_stub_v_sf -; picfp16: .cpload $25 -; picfp16: .set reorder -; picfp16: .reloc 0,R_MIPS_NONE,v_sf -; picfp16: la $25,$__fn_local_v_sf -; picfp16: mfc1 $4,$f12 -; picfp16: jr $25 -; picfp16: .end __fn_stub_v_sf +; picfp16: .ent __fn_stub_v_sf +; picfp16: .cpload $25 +; picfp16: .set reorder +; picfp16: .reloc 0, R_MIPS_NONE, v_sf +; picfp16: la $25, $__fn_local_v_sf +; picfp16: mfc1 $4, $f12 +; picfp16: jr $25 +; picfp16: .end __fn_stub_v_sf diff --git a/test/CodeGen/Mips/hfptrcall.ll b/test/CodeGen/Mips/hfptrcall.ll index c9f1fe973796..f6ce243c3047 100644 --- a/test/CodeGen/Mips/hfptrcall.ll +++ b/test/CodeGen/Mips/hfptrcall.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picel +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picel @ptrsv = global float ()* @sv, align 4 @ptrdv = global double ()* @dv, align 4 diff --git a/test/CodeGen/Mips/i32k.ll b/test/CodeGen/Mips/i32k.ll index ba9cf7342308..57a2e788a301 100644 --- a/test/CodeGen/Mips/i32k.ll +++ b/test/CodeGen/Mips/i32k.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic -mips16-constant-islands=false -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic -mips16-constant-islands=false -O3 < %s | FileCheck %s -check-prefix=16 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 diff --git a/test/CodeGen/Mips/inlineasm-assembler-directives.ll b/test/CodeGen/Mips/inlineasm-assembler-directives.ll index 88ceed4114c2..9f6f1ebb2858 100644 --- a/test/CodeGen/Mips/inlineasm-assembler-directives.ll +++ b/test/CodeGen/Mips/inlineasm-assembler-directives.ll @@ -10,14 +10,14 @@ entry: ; CHECK-NEXT: .set macro ; CHECK-NEXT: .set reorder ; CHECK: addi $9, ${{[2-9][0-9]?}}, 8 -; CHECK: subi ${{[2-9][0-9]?}}, $9, 6 +; CHECK: ori ${{[2-9][0-9]?}}, $9, 6 ; CHECK: .set pop ; CHECK-NEXT: #NO_APP %a = alloca i32, align 4 %b = alloca i32, align 4 store i32 20, i32* %a, align 4 %0 = load i32, i32* %a, align 4 - %1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09subi $0, $$9, 6", "=r,r,~{$1}"(i32 %0) + %1 = call i32 asm sideeffect "addi $$9, $1, 8\0A\09ori $0, $$9, 6", "=r,r,~{$1}"(i32 %0) store i32 %1, i32* %b, align 4 ret void } diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll index 41991d07a4fe..63ee42c0c7cd 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg.ll @@ -7,38 +7,38 @@ define i32 @main() nounwind { entry: ; r with char -;CHECK: #APP -;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},23 -;CHECK: #NO_APP - tail call i8 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i8 27, i8 23) nounwind +;CHECK: #APP +;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 23 +;CHECK: #NO_APP + tail call i8 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i8 27, i8 23) nounwind ; r with short -;CHECK: #APP -;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},13 -;CHECK: #NO_APP - tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i16 17, i16 13) nounwind +;CHECK: #APP +;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 13 +;CHECK: #NO_APP + tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i16 17, i16 13) nounwind ; r with int -;CHECK: #APP -;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3 -;CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,n"(i32 7, i32 3) nounwind +;CHECK: #APP +;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 +;CHECK: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,n"(i32 7, i32 3) nounwind ; Now c with 1024: make sure register $25 is picked ; CHECK: #APP -; CHECK: addiu $25,${{[0-9]+}},1024 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=c,c,I"(i32 4194304, i32 1024) nounwind +; CHECK: addiu $25, ${{[0-9]+}}, 1024 +; CHECK: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=c,c,I"(i32 4194304, i32 1024) nounwind ; Now l with 1024: make sure register lo is picked. We do this by checking the instruction ; after the inline expression for a mflo to pull the value out of lo. ; CHECK: #APP ; CHECK: mtlo ${{[0-9]+}} -; CHECK-NEXT: madd ${{[0-9]+}},${{[0-9]+}} +; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}} ; CHECK: #NO_APP -; CHECK-NEXT: mflo ${{[0-9]+}} +; CHECK-NEXT: mflo ${{[0-9]+}} %bosco = alloca i32, align 4 - call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1,$2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind + call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind store volatile i32 %4, i32* %bosco, align 4 ret i32 0 diff --git a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll index acce63203812..3b078d6f70db 100644 --- a/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll +++ b/test/CodeGen/Mips/inlineasm-cnstrnt-reg64.ll @@ -12,9 +12,9 @@ entry: ; r with long long ;CHECK: #APP -;CHECK: addiu ${{[0-9]+}},${{[0-9]+}},3 +;CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 ;CHECK: #NO_APP - tail call i64 asm sideeffect "addiu $0,$1,$2", "=r,r,i"(i64 7, i64 3) nounwind + tail call i64 asm sideeffect "addiu $0, $1, $2", "=r,r,i"(i64 7, i64 3) nounwind ret i32 0 } diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index b9415ee90cdb..6d41385d18de 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -1,7 +1,9 @@ ; Positive test for inline register constraints ; -; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s -; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s +; RUN: llc -no-integrated-as -march=mipsel < %s | \ +; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s +; RUN: llc -no-integrated-as -march=mips < %s | \ +; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s %union.u_tag = type { i64 } %struct.anon = type { i32, i32 } @@ -10,171 +12,152 @@ ; X with -3 define i32 @constraint_X() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_X: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ; +; ALL-LABEL: constraint_X: +; ALL: #APP +; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 } ; x with -3 define i32 @constraint_x() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_x: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ; +; ALL-LABEL: constraint_x: +; ALL: #APP +; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 } ; d with -3 define i32 @constraint_d() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_d: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3 -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ; +; ALL-LABEL: constraint_d: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 } ; m with -3 define i32 @constraint_m() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_m: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4 -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ; +; ALL-LABEL: constraint_m: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 } ; z with -3 define i32 @constraint_z() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_z: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3 -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ; +; ALL-LABEL: constraint_z: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ; ; z with 0 -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0 -;CHECK_LITTLE_32: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind +; ALL: #APP +; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind ; z with non-zero and the "r"(register) and "J"(integer zero) constraints -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP +; ALL: #APP +; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind ; z with zero and the "r"(register) and "J"(integer zero) constraints -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP +; ALL: #APP +; ALL: mtc0 $0, ${{[0-9]+}} +; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind ; z with non-zero and just the "r"(register) constraint -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP +; ALL: #APP +; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind ; z with zero and just the "r"(register) constraint ; FIXME: Check for $0, instead of other registers. ; We should be using $0 directly in this case, not real registers. ; When the materialization of 0 gets fixed, this test will fail. -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP +; ALL: #APP +; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} +; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind ret i32 0 } -; a long long in 32 bit mode (use to assert) +; A long long in 32 bit mode (use to assert) define i32 @constraint_longlong() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_longlong: -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},3 -;CHECK_LITTLE_32: #NO_APP - tail call i64 asm sideeffect "addiu $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind +; ALL-LABEL: constraint_longlong: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3 +; ALL: #NO_APP + tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind ret i32 0 } -; D, in little endian the source reg will be 4 bytes into the long long +; In little endian the source reg will be 4 bytes into the long long +; In big endian the source reg will also be 4 bytes into the long long define i32 @constraint_D() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_D: -;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP - -; D, in big endian the source reg will also be 4 bytes into the long long -;CHECK_BIG_32-LABEL: constraint_D: -;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_BIG_32: #APP -;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} -;CHECK_BIG_32: #NO_APP +; ALL-LABEL: constraint_D: +; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +; ALL: #APP +; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}} +; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}} +; ALL: #NO_APP %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8 %trunc1 = trunc i64 %bosco to i32 - tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind ret i32 0 } -; L, in little endian the source reg will be 0 bytes into the long long +; In little endian the source reg will be 0 bytes into the long long +; In big endian the source reg will be 4 bytes into the long long define i32 @constraint_L() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_L: -;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP -; L, in big endian the source reg will be 4 bytes into the long long -;CHECK_BIG_32-LABEL: constraint_L: -;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_BIG_32: #APP -;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} -;CHECK_BIG_32: #NO_APP +; ALL-LABEL: constraint_L: +; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +; ALL: #APP +; LE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}} +; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}} +; ALL: #NO_APP %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8 %trunc1 = trunc i64 %bosco to i32 - tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind ret i32 0 } -; M, in little endian the source reg will be 4 bytes into the long long +; In little endian the source reg will be 4 bytes into the long long +; In big endian the source reg will be 0 bytes into the long long define i32 @constraint_M() nounwind { entry: -;CHECK_LITTLE_32-LABEL: constraint_M: -;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_LITTLE_32: #APP -;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}} -;CHECK_LITTLE_32: #NO_APP -; M, in big endian the source reg will be 0 bytes into the long long -;CHECK_BIG_32-LABEL: constraint_M: -;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) -;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) -;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) -;CHECK_BIG_32: #APP -;CHECK_BIG_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}} -;CHECK_BIG_32: #NO_APP +; ALL-LABEL: constraint_M: +; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}}) +; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}}) +; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}}) +; ALL: #APP +; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}} +; BE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}} +; ALL: #NO_APP %bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8 %trunc1 = trunc i64 %bosco to i32 - tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind + tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind ret i32 0 } diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index 868433e0941f..a6ac07182ff5 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -1,55 +1,73 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s - -define i32 @main() nounwind { -entry: +; RUN: llc -no-integrated-as -march=mipsel < %s | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS +define void @constraint_I() nounwind { ; First I with short -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},4096 -; CHECK: #NO_APP - tail call i16 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i16 7, i16 4096) nounwind +; ALL-LABEL: constraint_I: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 4096 +; ALL: #NO_APP + tail call i16 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i16 7, i16 4096) nounwind ; Then I with int -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,I"(i32 7, i32 -3) nounwind +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,I"(i32 7, i32 -3) nounwind + ret void +} +define void @constraint_J() nounwind { ; Now J with 0 -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},0 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind +; ALL-LABEL: constraint_J: +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2\0A\09 ", "=r,r,J"(i32 7, i16 0) nounwind + ret void +} +define void @constraint_K() nounwind { ; Now K with 64 -; CHECK: #APP -; CHECK: addu ${{[0-9]+}},${{[0-9]+}},64 -; CHECK: #NO_APP - tail call i16 asm sideeffect "addu $0,$1,$2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind +; ALL: #APP +; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64 +; ALL: #NO_APP + tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind + ret void +} +define void @constraint_L() nounwind { ; Now L with 0x00100000 -; CHECK: #APP -; CHECK: add ${{[0-9]+}},${{[0-9]+}},${{[0-9]+}} -; CHECK: #NO_APP - tail call i32 asm sideeffect "add $0,$1,$3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind +; ALL: #APP +; ALL: add ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}} +; ALL: #NO_APP + tail call i32 asm sideeffect "add $0, $1, $3\0A\09", "=r,r,L,r"(i32 7, i32 1048576, i32 0) nounwind + ret void +} +define void @constraint_N() nounwind { ; Now N with -3 -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,N"(i32 7, i32 -3) nounwind +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,N"(i32 7, i32 -3) nounwind + ret void +} +define void @constraint_O() nounwind { ; Now O with -3 -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},-3 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,O"(i32 7, i16 -3) nounwind +; ALL: #APP +; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,O"(i32 7, i16 -3) nounwind + ret void +} +define void @constraint_P() nounwind { ; Now P with 65535 -; CHECK: #APP -; CHECK: addiu ${{[0-9]+}},${{[0-9]+}},65535 -; CHECK: #NO_APP - tail call i32 asm sideeffect "addiu $0,$1,$2", "=r,r,P"(i32 7, i32 65535) nounwind - - ret i32 0 +; ALL: #APP +; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 65535 +; ALL: #NO_APP + tail call i32 asm sideeffect "addiu $0, $1, $2", "=r,r,P"(i32 7, i32 65535) nounwind + ret void } diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index 9e9b6cd089ea..bdf3ae55b802 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -26,13 +26,13 @@ entry: ; "D": Second word of a double word. This works for any memory element ; double or single. ; CHECK: #APP -; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}}); +; CHECK: lw ${{[0-9]+}}, 16(${{[0-9]+}}) ; CHECK: #NO_APP ; No "D": First word of a double word. This works for any memory element ; double or single. ; CHECK: #APP -; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}}); +; CHECK: lw ${{[0-9]+}}, 12(${{[0-9]+}}) ; CHECK: #NO_APP @b = common global [20 x i32] zeroinitializer, align 4 @@ -40,8 +40,8 @@ entry: define void @main() { entry: ; Second word: - tail call void asm sideeffect " lw $0, ${1:D};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3)) + tail call void asm sideeffect " lw $0, ${1:D}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3)) ; First word. Notice, no 'D': - tail call void asm sideeffect " lw $0, ${1};", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3)) + tail call void asm sideeffect " lw $0, ${1}", "r,*m,~{$11}"(i32 undef, i32* getelementptr inbounds ([20 x i32], [20 x i32]* @b, i32 0, i32 3)) ret void } diff --git a/test/CodeGen/Mips/insn-zero-size-bb.ll b/test/CodeGen/Mips/insn-zero-size-bb.ll index ea61c994ae1d..d2124c407a0d 100644 --- a/test/CodeGen/Mips/insn-zero-size-bb.ll +++ b/test/CodeGen/Mips/insn-zero-size-bb.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s ; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s -; RUN: llc < %s -march=mips -mcpu=mips16 | FileCheck %s +; RUN: llc < %s -march=mips -mattr=mips16 | FileCheck %s ; Verify that we emit the .insn directive for zero-sized (empty) basic blocks. ; This only really matters for microMIPS and MIPS16. @@ -14,7 +14,7 @@ entry: to label %unreachable unwind label %return unreachable: -; CHECK: ${{.*}}: # %unreachable +; CHECK: {{.*}}: # %unreachable ; CHECK-NEXT: .insn unreachable diff --git a/test/CodeGen/Mips/interrupt-attr-64-error.ll b/test/CodeGen/Mips/interrupt-attr-64-error.ll new file mode 100644 index 000000000000..830c199d91d9 --- /dev/null +++ b/test/CodeGen/Mips/interrupt-attr-64-error.ll @@ -0,0 +1,9 @@ +; RUN: not llc -mcpu=mips64r6 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: FileCheck %s < %t + +; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time. +define i32 @isr_sw0() #0 { + ret i32 0 +} + +attributes #0 = { "interrupt"="sw0" } diff --git a/test/CodeGen/Mips/interrupt-attr-args-error.ll b/test/CodeGen/Mips/interrupt-attr-args-error.ll new file mode 100644 index 000000000000..993629bdbcd6 --- /dev/null +++ b/test/CodeGen/Mips/interrupt-attr-args-error.ll @@ -0,0 +1,9 @@ +; RUN: not llc -mcpu=mips32r2 -march=mipsel -relocation-model=static < %s 2> %t +; RUN: FileCheck %s < %t + +; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! +define i32 @isr_sw0(i8 signext %n) #0 { + ret i32 0 +} + +attributes #0 = { "interrupt"="sw0" } diff --git a/test/CodeGen/Mips/interrupt-attr-error.ll b/test/CodeGen/Mips/interrupt-attr-error.ll new file mode 100644 index 000000000000..f35e98ea14bf --- /dev/null +++ b/test/CodeGen/Mips/interrupt-attr-error.ll @@ -0,0 +1,9 @@ +; RUN: not llc -mcpu=mips32 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: FileCheck %s < %t + +; CHECK: LLVM ERROR: "interrupt" attribute is not supported on pre-MIPS32R2 or MIPS16 targets. +define i32 @isr_sw0() #0 { + ret i32 0 +} + +attributes #0 = { "interrupt"="sw0" } diff --git a/test/CodeGen/Mips/interrupt-attr.ll b/test/CodeGen/Mips/interrupt-attr.ll new file mode 100644 index 000000000000..6cfb0c3ebd54 --- /dev/null +++ b/test/CodeGen/Mips/interrupt-attr.ll @@ -0,0 +1,244 @@ +; RUN: llc -mcpu=mips32r2 -march=mipsel -relocation-model=static -o - %s | FileCheck %s + +define void @isr_sw0() #0 { +; CHECK-LABEL: isr_sw0: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, [[R1:[0-9]+]]($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, [[R2:[0-9]+]]($sp) +; CHECK: ins $27, $zero, 8, 1 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ; Must save all registers +; CHECK: sw $7, {{[0-9]+}}($sp) +; CHECK: sw $6, {{[0-9]+}}($sp) +; CHECK: sw $5, {{[0-9]+}}($sp) +; CHECK: sw $4, {{[0-9]+}}($sp) +; CHECK: sw $3, {{[0-9]+}}($sp) +; CHECK: sw $2, {{[0-9]+}}($sp) +; CHECK: sw $25, {{[0-9]+}}($sp) +; CHECK: sw $24, {{[0-9]+}}($sp) +; CHECK: sw $15, {{[0-9]+}}($sp) +; CHECK: sw $14, {{[0-9]+}}($sp) +; CHECK: sw $13, {{[0-9]+}}($sp) +; CHECK: sw $12, {{[0-9]+}}($sp) +; CHECK: sw $11, {{[0-9]+}}($sp) +; CHECK: sw $10, {{[0-9]+}}($sp) +; CHECK: sw $9, {{[0-9]+}}($sp) +; CHECK: sw $8, {{[0-9]+}}($sp) +; CHECK: sw $ra, [[R5:[0-9]+]]($sp) +; CHECK: sw $gp, {{[0-9]+}}($sp) +; CHECK: sw $1, {{[0-9]+}}($sp) +; CHECK: mflo $26 +; CHECK: sw $26, [[R3:[0-9]+]]($sp) +; CHECK: mfhi $26 +; CHECK: sw $26, [[R4:[0-9]+]]($sp) + call void bitcast (void (...)* @write to void ()*)() +; CHECK: lw $26, [[R4:[0-9]+]]($sp) +; CHECK: mthi $26 +; CHECK: lw $26, [[R3:[0-9]+]]($sp) +; CHECK: mtlo $26 +; CHECK: lw $1, {{[0-9]+}}($sp) +; CHECK: lw $gp, {{[0-9]+}}($sp) +; CHECK: lw $ra, [[R5:[0-9]+]]($sp) +; CHECK: lw $8, {{[0-9]+}}($sp) +; CHECK: lw $9, {{[0-9]+}}($sp) +; CHECK: lw $10, {{[0-9]+}}($sp) +; CHECK: lw $11, {{[0-9]+}}($sp) +; CHECK: lw $12, {{[0-9]+}}($sp) +; CHECK: lw $13, {{[0-9]+}}($sp) +; CHECK: lw $14, {{[0-9]+}}($sp) +; CHECK: lw $15, {{[0-9]+}}($sp) +; CHECK: lw $24, {{[0-9]+}}($sp) +; CHECK: lw $25, {{[0-9]+}}($sp) +; CHECK: lw $2, {{[0-9]+}}($sp) +; CHECK: lw $3, {{[0-9]+}}($sp) +; CHECK: lw $4, {{[0-9]+}}($sp) +; CHECK: lw $5, {{[0-9]+}}($sp) +; CHECK: lw $6, {{[0-9]+}}($sp) +; CHECK: lw $7, {{[0-9]+}}($sp) +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, [[R2:[0-9]+]]($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, [[R1:[0-9]+]]($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + ret void +} + +declare void @write(...) + +define void @isr_sw1() #2 { +; CHECK-LABEL: isr_sw1: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 2 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_hw0() #3 { +; CHECK-LABEL: isr_hw0: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 3 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_hw1() #4 { +; CHECK-LABEL: isr_hw1: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 4 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + + +define void @isr_hw2() #5 { +; CHECK-LABEL: isr_hw2: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 5 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_hw3() #6 { +; CHECK-LABEL: isr_hw3: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 6 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_hw4() #7 { +; CHECK-LABEL: isr_hw4: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 7 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_hw5() #8 { +; CHECK-LABEL: isr_hw5: +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $zero, 8, 8 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +define void @isr_eic() #9 { +; CHECK-LABEL: isr_eic: +; CHECK: mfc0 $26, $13, 0 +; CHECK: ext $26, $26, 10, 6 +; CHECK: mfc0 $27, $14, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: mfc0 $27, $12, 0 +; CHECK: sw $27, {{[0-9]+}}($sp) +; CHECK: ins $27, $26, 10, 6 +; CHECK: ins $27, $zero, 1, 4 +; CHECK: ins $27, $zero, 29, 1 +; CHECK: mtc0 $27, $12, 0 + ret void +; CHECK: di +; CHECK: ehb +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $14, 0 +; CHECK: lw $27, {{[0-9]+}}($sp) +; CHECK: mtc0 $27, $12, 0 +; CHECK: eret + } + +attributes #0 = { "interrupt"="sw0" } +attributes #2 = { "interrupt"="sw1" } +attributes #3 = { "interrupt"="hw0" } +attributes #4 = { "interrupt"="hw1" } +attributes #5 = { "interrupt"="hw2" } +attributes #6 = { "interrupt"="hw3" } +attributes #7 = { "interrupt"="hw4" } +attributes #8 = { "interrupt"="hw5" } +attributes #9 = { "interrupt"="eic" } diff --git a/test/CodeGen/Mips/jtstat.ll b/test/CodeGen/Mips/jtstat.ll index 35f71cf2dc85..5b578d4cffe4 100644 --- a/test/CodeGen/Mips/jtstat.ll +++ b/test/CodeGen/Mips/jtstat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 @s = global i8 115, align 1 @c = common global i8 0, align 1 diff --git a/test/CodeGen/Mips/l3mc.ll b/test/CodeGen/Mips/l3mc.ll index c1bff11595c9..c6855fc03fec 100644 --- a/test/CodeGen/Mips/l3mc.ll +++ b/test/CodeGen/Mips/l3mc.ll @@ -1,22 +1,22 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfsi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfsi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdidf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatdisf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundidf -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixsfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunsdfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixdfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfsi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___fixunssfdi -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=__call_stub_fp___floatundisf @ll1 = global i64 0, align 8 @ll2 = global i64 0, align 8 diff --git a/test/CodeGen/Mips/lb1.ll b/test/CodeGen/Mips/lb1.ll index 21648d7572a5..1e908b81a878 100644 --- a/test/CodeGen/Mips/lb1.ll +++ b/test/CodeGen/Mips/lb1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @c = global i8 -1, align 1 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/test/CodeGen/Mips/lbu1.ll b/test/CodeGen/Mips/lbu1.ll index 28ca27132467..32515411b7d4 100644 --- a/test/CodeGen/Mips/lbu1.ll +++ b/test/CodeGen/Mips/lbu1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @c = global i8 97, align 1 @.str = private unnamed_addr constant [5 x i8] c"%c \0A\00", align 1 diff --git a/test/CodeGen/Mips/lcb2.ll b/test/CodeGen/Mips/lcb2.ll index a6f4968e6d23..b15a5085f5a2 100644 --- a/test/CodeGen/Mips/lcb2.ll +++ b/test/CodeGen/Mips/lcb2.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcb +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcb -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcbn +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands=true < %s | FileCheck %s -check-prefix=lcbn @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/lcb3c.ll b/test/CodeGen/Mips/lcb3c.ll index 4c6f2c036a0b..b953229a15c9 100644 --- a/test/CodeGen/Mips/lcb3c.ll +++ b/test/CodeGen/Mips/lcb3c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -O0 < %s | FileCheck %s -check-prefix=lcb @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/lcb4a.ll b/test/CodeGen/Mips/lcb4a.ll index 9e97b5bf1433..4a99ef26efca 100644 --- a/test/CodeGen/Mips/lcb4a.ll +++ b/test/CodeGen/Mips/lcb4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/lcb5.ll b/test/CodeGen/Mips/lcb5.ll index 41878d5f8817..ec4c3da6515c 100644 --- a/test/CodeGen/Mips/lcb5.ll +++ b/test/CodeGen/Mips/lcb5.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static < %s | FileCheck %s -check-prefix=ci @i = global i32 0, align 4 @j = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/lh1.ll b/test/CodeGen/Mips/lh1.ll index 31967e5a5379..dcab12a38e17 100644 --- a/test/CodeGen/Mips/lh1.ll +++ b/test/CodeGen/Mips/lh1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @s = global i16 -1, align 2 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/test/CodeGen/Mips/lhu1.ll b/test/CodeGen/Mips/lhu1.ll index 413da46d4a31..9a52d6fb269f 100644 --- a/test/CodeGen/Mips/lhu1.ll +++ b/test/CodeGen/Mips/lhu1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @s = global i16 255, align 2 diff --git a/test/CodeGen/Mips/llcarry.ll b/test/CodeGen/Mips/llcarry.ll index f4120ecec175..fcf129420234 100644 --- a/test/CodeGen/Mips/llcarry.ll +++ b/test/CodeGen/Mips/llcarry.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i64 4294967295, align 8 @j = global i64 15, align 8 diff --git a/test/CodeGen/Mips/llvm-ir/atomicrmx.ll b/test/CodeGen/Mips/llvm-ir/atomicrmx.ll new file mode 100644 index 000000000000..9069a6f2d13f --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/atomicrmx.ll @@ -0,0 +1,26 @@ +; RUN: llc -asm-show-inst -march=mipsel -mcpu=mips32r6 < %s | \ +; RUN: FileCheck %s -check-prefix=CHK32 +; RUN: llc -asm-show-inst -march=mips64el -mcpu=mips64r6 < %s | \ +; RUN: FileCheck %s -check-prefix=CHK64 + +@a = common global i32 0, align 4 +@b = common global i64 0, align 8 + + +define i32 @ll_sc(i32 signext %x) { +; CHK32-LABEL: ll_sc + +;CHK32: LL_R6 +;CHK32: SC_R6 + %1 = atomicrmw add i32* @a, i32 %x monotonic + ret i32 %1 +} + +define i64 @lld_scd(i64 signext %x) { +; CHK64-LABEL: lld_scd + +;CHK64: LLD_R6 +;CHK64: SCD_R6 + %1 = atomicrmw add i64* @b, i64 %x monotonic + ret i64 %1 +} diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index 112ab8ee8c7f..22a44da0b069 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -6,6 +6,7 @@ ; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 ; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 @@ -168,3 +169,16 @@ define float @tail_indirect_call_float_void(float ()* %addr) { %1 = tail call float %addr() ret float %1 } + +; Check that passing undef as a double value doesn't cause machine code errors +; for FP64. +declare hidden void @undef_double(i32 %this, double %volume) unnamed_addr align 2 + +define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr align 2 { +; ALL-LABEL: thunk_undef_double: +; O32: # implicit-def: %A2 +; O32: # implicit-def: %A3 +; ALL: jr $25 + tail call void @undef_double(i32 undef, double undef) #8 + ret void +} diff --git a/test/CodeGen/Mips/llvm-ir/load-atomic.ll b/test/CodeGen/Mips/llvm-ir/load-atomic.ll new file mode 100644 index 000000000000..a44b00bff586 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/load-atomic.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 + +define i8 @load_i8(i8* %ptr) { +; ALL-LABEL: load_i8 + +; ALL: lb $2, 0($4) +; ALL: sync + %val = load atomic i8, i8* %ptr acquire, align 1 + ret i8 %val +} + +define i16 @load_i16(i16* %ptr) { +; ALL-LABEL: load_i16 + +; ALL: lh $2, 0($4) +; ALL: sync + %val = load atomic i16, i16* %ptr acquire, align 2 + ret i16 %val +} + +define i32 @load_i32(i32* %ptr) { +; ALL-LABEL: load_i32 + +; ALL: lw $2, 0($4) +; ALL: sync + %val = load atomic i32, i32* %ptr acquire, align 4 + ret i32 %val +} + +define i64 @load_i64(i64* %ptr) { +; M64-LABEL: load_i64 + +; M64: ld $2, 0($4) +; M64: sync + %val = load atomic i64, i64* %ptr acquire, align 8 + ret i64 %val +} diff --git a/test/CodeGen/Mips/llvm-ir/sqrt.ll b/test/CodeGen/Mips/llvm-ir/sqrt.ll new file mode 100644 index 000000000000..1a8892de0ee2 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sqrt.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r2 -mattr=+micromips | FileCheck %s +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s + +define float @sqrt_fn(float %value) #0 { +entry: + %sqrtf = tail call float @sqrtf(float %value) #0 + ret float %sqrtf +} + +declare float @sqrtf(float) + +; CHECK: sqrt.s $f0, $f12 diff --git a/test/CodeGen/Mips/llvm-ir/store-atomic.ll b/test/CodeGen/Mips/llvm-ir/store-atomic.ll new file mode 100644 index 000000000000..6b33f2685d17 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/store-atomic.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL +; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 +; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | \ +; RUN: FileCheck %s -check-prefix=ALL -check-prefix=M64 + +define void @store_i8(i8* %ptr, i8 signext %v) { +; ALL-LABEL: store_i8 + +; ALL: sync +; ALL: sb $5, 0($4) + store atomic i8 %v, i8* %ptr release, align 1 + ret void +} + +define void @store_i16(i16* %ptr, i16 signext %v) { +; ALL-LABEL: store_i16 + +; ALL: sync +; ALL: sh $5, 0($4) + store atomic i16 %v, i16* %ptr release, align 2 + ret void +} + +define void @store_i32(i32* %ptr, i32 signext %v) { +; ALL-LABEL: store_i32 + +; ALL: sync +; ALL: sw $5, 0($4) + store atomic i32 %v, i32* %ptr release, align 4 + ret void +} + +define void @store_i64(i64* %ptr, i64 %v) { +; M64-LABEL: store_i64 + +; M64: sync +; M64: sd $5, 0($4) + store atomic i64 %v, i64* %ptr release, align 8 + ret void +} diff --git a/test/CodeGen/Mips/madd-msub.ll b/test/CodeGen/Mips/madd-msub.ll index b0c3ff6ff9b5..b84d94d31494 100644 --- a/test/CodeGen/Mips/madd-msub.ll +++ b/test/CodeGen/Mips/madd-msub.ll @@ -7,7 +7,7 @@ ; RUN: llc -march=mips -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64R6 ; FIXME: The MIPS16 test should check its output -; RUN: llc -march=mips -mcpu=mips16 < %s +; RUN: llc -march=mips -mattr=mips16 < %s ; ALL-LABEL: madd1: diff --git a/test/CodeGen/Mips/mbrsize4a.ll b/test/CodeGen/Mips/mbrsize4a.ll index 264d2284afc9..9562e55dcc2a 100644 --- a/test/CodeGen/Mips/mbrsize4a.ll +++ b/test/CodeGen/Mips/mbrsize4a.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=static -mips16-constant-islands < %s | FileCheck %s -check-prefix=jal16 @j = global i32 10, align 4 @.str = private unnamed_addr constant [11 x i8] c"at bottom\0A\00", align 1 diff --git a/test/CodeGen/Mips/mips16-hf-attr-2.ll b/test/CodeGen/Mips/mips16-hf-attr-2.ll index 60c6eaad8f76..82c0989c4254 100644 --- a/test/CodeGen/Mips/mips16-hf-attr-2.ll +++ b/test/CodeGen/Mips/mips16-hf-attr-2.ll @@ -1,7 +1,7 @@ ; Check that stubs generation for mips16 hard-float mode does not depend ; on the function 'use-soft-float' attribute's value. ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ -; RUN: -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s +; RUN: -mattr=mips16 -relocation-model=pic < %s | FileCheck %s define void @bar_sf() #1 { ; CHECK: bar_sf: diff --git a/test/CodeGen/Mips/mips16-hf-attr.ll b/test/CodeGen/Mips/mips16-hf-attr.ll index c6ad442fdea2..bcae1e92f7cc 100644 --- a/test/CodeGen/Mips/mips16-hf-attr.ll +++ b/test/CodeGen/Mips/mips16-hf-attr.ll @@ -1,7 +1,7 @@ ; Check that stubs generation for mips16 hard-float mode does not depend ; on the function 'use-soft-float' attribute's value. ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel \ -; RUN: -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s +; RUN: -mattr=mips16 -relocation-model=pic < %s | FileCheck %s define void @bar_hf() #0 { ; CHECK: bar_hf: diff --git a/test/CodeGen/Mips/mips16_32_1.ll b/test/CodeGen/Mips/mips16_32_1.ll index f6096b402f2d..211aa2a0f4b0 100644 --- a/test/CodeGen/Mips/mips16_32_1.ll +++ b/test/CodeGen/Mips/mips16_32_1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic -O3 < %s -mips-mixed-16-32 | FileCheck %s define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_32_10.ll b/test/CodeGen/Mips/mips16_32_10.ll index ff9831ed7622..b256912d7151 100644 --- a/test/CodeGen/Mips/mips16_32_10.ll +++ b/test/CodeGen/Mips/mips16_32_10.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 define void @foo() #0 { entry: diff --git a/test/CodeGen/Mips/mips16_32_3.ll b/test/CodeGen/Mips/mips16_32_3.ll index c5a29a0b8fdb..8891eba8c954 100644 --- a/test/CodeGen/Mips/mips16_32_3.ll +++ b/test/CodeGen/Mips/mips16_32_3.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_32_4.ll b/test/CodeGen/Mips/mips16_32_4.ll index 1238363d907e..2d50881c61b4 100644 --- a/test/CodeGen/Mips/mips16_32_4.ll +++ b/test/CodeGen/Mips/mips16_32_4.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_32_5.ll b/test/CodeGen/Mips/mips16_32_5.ll index 5d4c8a1af563..644ba4c98e34 100644 --- a/test/CodeGen/Mips/mips16_32_5.ll +++ b/test/CodeGen/Mips/mips16_32_5.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_32_6.ll b/test/CodeGen/Mips/mips16_32_6.ll index 63323b608bc5..1afce84b0335 100644 --- a/test/CodeGen/Mips/mips16_32_6.ll +++ b/test/CodeGen/Mips/mips16_32_6.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_32_7.ll b/test/CodeGen/Mips/mips16_32_7.ll index 480a23c8b25e..cc247c054543 100644 --- a/test/CodeGen/Mips/mips16_32_7.ll +++ b/test/CodeGen/Mips/mips16_32_7.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=16 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32 define void @foo() #0 { diff --git a/test/CodeGen/Mips/mips16_fpret.ll b/test/CodeGen/Mips/mips16_fpret.ll index 0f09c4105a17..651feba19808 100644 --- a/test/CodeGen/Mips/mips16_fpret.ll +++ b/test/CodeGen/Mips/mips16_fpret.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=1 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=2 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=3 -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=4 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=1 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=2 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=3 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=4 @x = global float 0x41F487E980000000, align 4 diff --git a/test/CodeGen/Mips/mips16ex.ll b/test/CodeGen/Mips/mips16ex.ll index c3a02261119e..b2521ae872a8 100644 --- a/test/CodeGen/Mips/mips16ex.ll +++ b/test/CodeGen/Mips/mips16ex.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 ;16: main: ;16-NEXT: [[TMP:.*]]: diff --git a/test/CodeGen/Mips/mips16fpe.ll b/test/CodeGen/Mips/mips16fpe.ll index f8b916da3a49..16695e45265a 100644 --- a/test/CodeGen/Mips/mips16fpe.ll +++ b/test/CodeGen/Mips/mips16fpe.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16hf +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16hf @x = global float 5.000000e+00, align 4 @y = global float 1.500000e+01, align 4 @@ -297,7 +297,7 @@ entry: %and2 = and i1 %lnot, %cmp1 %and = zext i1 %and2 to i32 store i32 %and, i32* @ltsf2_result, align 4 -;16hf: lw ${{[0-9]+}}, %call16(__mips16_unordsf2)(${{[0-9]+}}) +;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltsf2)(${{[0-9]+}}) ;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltsf2)(${{[0-9]+}}) ret void } @@ -313,7 +313,7 @@ entry: %and2 = and i1 %lnot, %cmp1 %and = zext i1 %and2 to i32 store i32 %and, i32* @ltdf2_result, align 4 -;16hf: lw ${{[0-9]+}}, %call16(__mips16_unorddf2)(${{[0-9]+}}) +;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltdf2)(${{[0-9]+}}) ;16hf: lw ${{[0-9]+}}, %call16(__mips16_ltdf2)(${{[0-9]+}}) ret void } diff --git a/test/CodeGen/Mips/misha.ll b/test/CodeGen/Mips/misha.ll index 23ad7f6057af..bedea9de5f92 100644 --- a/test/CodeGen/Mips/misha.ll +++ b/test/CodeGen/Mips/misha.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 define i32 @sumc(i8* nocapture %to, i8* nocapture %from, i32) nounwind { entry: diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll index 2a0d74f44524..251b535fd76c 100644 --- a/test/CodeGen/Mips/msa/elm_copy.ll +++ b/test/CodeGen/Mips/msa/elm_copy.ll @@ -170,7 +170,8 @@ declare i32 @llvm.mips.copy.u.w(<4 x i32>, i32) nounwind ; MIPS32-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_copy_u_w_ARG1) ; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_ARG1) ; MIPS-ANY-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]]) -; MIPS-ANY-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1] +; MIPS32-DAG: copy_s.w [[RD:\$[0-9]+]], [[WS]][1] +; MIPS64-DAG: copy_u.w [[RD:\$[0-9]+]], [[WS]][1] ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_w_RES) ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_w_RES) ; MIPS-ANY-DAG: sw [[RD]], 0([[RES]]) @@ -196,7 +197,7 @@ declare i64 @llvm.mips.copy.u.d(<2 x i64>, i32) nounwind ; MIPS64-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]]) ; MIPS32-DAG: copy_s.w [[RD1:\$[0-9]+]], [[WS]][2] ; MIPS32-DAG: copy_s.w [[RD2:\$[0-9]+]], [[WS]][3] -; MIPS64-DAG: copy_u.d [[RD:\$[0-9]+]], [[WS]][1] +; MIPS64-DAG: copy_s.d [[RD:\$[0-9]+]], [[WS]][1] ; MIPS32-DAG: lw [[RES:\$[0-9]+]], %got(llvm_mips_copy_u_d_RES) ; MIPS64-DAG: ld [[RES:\$[0-9]+]], %got_disp(llvm_mips_copy_u_d_RES) ; MIPS32-DAG: sw [[RD1]], 0([[RES]]) diff --git a/test/CodeGen/Mips/mul.ll b/test/CodeGen/Mips/mul.ll index 3231f9cac38e..9e053fc2e7d6 100644 --- a/test/CodeGen/Mips/mul.ll +++ b/test/CodeGen/Mips/mul.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 5, align 4 @jjjj = global i32 -6, align 4 diff --git a/test/CodeGen/Mips/mulll.ll b/test/CodeGen/Mips/mulll.ll index 6e5ba647b8bf..9a2acd417381 100644 --- a/test/CodeGen/Mips/mulll.ll +++ b/test/CodeGen/Mips/mulll.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i64 5, align 8 @jjjj = global i64 -6, align 8 diff --git a/test/CodeGen/Mips/mulull.ll b/test/CodeGen/Mips/mulull.ll index c1334484fb66..fdcb68d036f8 100644 --- a/test/CodeGen/Mips/mulull.ll +++ b/test/CodeGen/Mips/mulull.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i64 5, align 8 @jjjj = global i64 6, align 8 diff --git a/test/CodeGen/Mips/nacl-align.ll b/test/CodeGen/Mips/nacl-align.ll index ec8f3f06afdf..8191c7dec6f2 100644 --- a/test/CodeGen/Mips/nacl-align.ll +++ b/test/CodeGen/Mips/nacl-align.ll @@ -44,18 +44,17 @@ default: ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 111 -; CHECK-NEXT: .align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra -; CHECK-NEXT: addiu $2, $zero, 222 +; CHECK-NEXT: addiu $2, $zero, 555 ; CHECK-NEXT: .align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra -; CHECK-NEXT: addiu $2, $zero, 333 +; CHECK-NEXT: addiu $2, $zero, 222 ; CHECK-NEXT: .align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra -; CHECK-NEXT: addiu $2, $zero, 444 +; CHECK-NEXT: addiu $2, $zero, 333 } diff --git a/test/CodeGen/Mips/neg1.ll b/test/CodeGen/Mips/neg1.ll index 36275a2991f6..dd5d7a09eb28 100644 --- a/test/CodeGen/Mips/neg1.ll +++ b/test/CodeGen/Mips/neg1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/test/CodeGen/Mips/no-odd-spreg-msa.ll b/test/CodeGen/Mips/no-odd-spreg-msa.ll index cf79557cc97f..7213044a2300 100644 --- a/test/CodeGen/Mips/no-odd-spreg-msa.ll +++ b/test/CodeGen/Mips/no-odd-spreg-msa.ll @@ -1,5 +1,9 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg \ +; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=ODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg \ +; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=NOODDSPREG @v4f32 = global <4 x float> zeroinitializer @@ -19,7 +23,7 @@ entry: ; On the other hand, if odd single precision registers are not permitted, it ; must copy $f13 to an even-numbered register before inserting into the ; vector. - call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() %1 = insertelement <4 x float> %0, float %b, i32 0 store <4 x float> %1, <4 x float>* @v4f32 ret void @@ -32,7 +36,7 @@ entry: ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 ; NOODDSPREG: insve.w $w[[W0]][0], $w[[F0]][0] ; ODDSPREG: insve.w $w[[W0]][0], $w13[0] -; ALL: # Clobber +; ALL: teqi $zero, 1 ; ALL-NOT: sdc1 ; ALL-NOT: ldc1 ; ALL: st.w $w[[W0]], 0($[[R0]]) @@ -53,7 +57,7 @@ entry: ; On the other hand, if odd single precision registers are not permitted, it ; must copy $f13 to an even-numbered register before inserting into the ; vector. - call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() %1 = insertelement <4 x float> %0, float %b, i32 1 store <4 x float> %1, <4 x float>* @v4f32 ret void @@ -66,7 +70,7 @@ entry: ; NOODDSPREG: mov.s $f[[F0:[0-9]+]], $f13 ; NOODDSPREG: insve.w $w[[W0]][1], $w[[F0]][0] ; ODDSPREG: insve.w $w[[W0]][1], $w13[0] -; ALL: # Clobber +; ALL: teqi $zero, 1 ; ALL-NOT: sdc1 ; ALL-NOT: ldc1 ; ALL: st.w $w[[W0]], 0($[[R0]]) @@ -83,7 +87,7 @@ entry: ; ; On the other hand, if odd single precision registers are not permitted, it ; must move it to $f12/$w12. - call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() %2 = extractelement <4 x float> %1, i32 0 ret float %2 @@ -94,7 +98,7 @@ entry: ; ALL: ld.w $w12, 0($[[R0]]) ; ALL: move.v $w[[W0:13]], $w12 ; NOODDSPREG: move.v $w[[W0:12]], $w13 -; ALL: # Clobber +; ALL: teqi $zero, 1 ; ALL-NOT: st.w ; ALL-NOT: ld.w ; ALL: mov.s $f0, $f[[W0]] @@ -111,7 +115,7 @@ entry: ; ; On the other hand, if odd single precision registers are not permitted, it ; must be spilled. - call void asm sideeffect "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() + call void asm sideeffect "teqi $$zero, 1", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f12},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() %2 = extractelement <4 x float> %1, i32 1 ret float %2 @@ -124,7 +128,7 @@ entry: ; NOODDSPREG: st.w $w[[W0]], 0($sp) ; ODDSPREG-NOT: st.w ; ODDSPREG-NOT: ld.w -; ALL: # Clobber +; ALL: teqi $zero, 1 ; ODDSPREG-NOT: st.w ; ODDSPREG-NOT: ld.w ; NOODDSPREG: ld.w $w0, 0($sp) diff --git a/test/CodeGen/Mips/nomips16.ll b/test/CodeGen/Mips/nomips16.ll index 418d8ead2c39..749272181884 100644 --- a/test/CodeGen/Mips/nomips16.ll +++ b/test/CodeGen/Mips/nomips16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s @x = global float 0.000000e+00, align 4 @.str = private unnamed_addr constant [20 x i8] c"in main: mips16 %f\0A\00", align 1 diff --git a/test/CodeGen/Mips/not1.ll b/test/CodeGen/Mips/not1.ll index f5ec5b60e421..512480508272 100644 --- a/test/CodeGen/Mips/not1.ll +++ b/test/CodeGen/Mips/not1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/test/CodeGen/Mips/null.ll b/test/CodeGen/Mips/null.ll index bc78a27f199c..67e346d959f9 100644 --- a/test/CodeGen/Mips/null.ll +++ b/test/CodeGen/Mips/null.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 < %s | FileCheck %s -check-prefix=16 define i32 @main() nounwind { diff --git a/test/CodeGen/Mips/or1.ll b/test/CodeGen/Mips/or1.ll index 51b6ebfe8e3b..aabffd111c5e 100644 --- a/test/CodeGen/Mips/or1.ll +++ b/test/CodeGen/Mips/or1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 diff --git a/test/CodeGen/Mips/powif64_16.ll b/test/CodeGen/Mips/powif64_16.ll index 33ec8c40c610..9be1a368b199 100644 --- a/test/CodeGen/Mips/powif64_16.ll +++ b/test/CodeGen/Mips/powif64_16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s declare float @llvm.powi.f32(float %Val, i32 %power) declare double @llvm.powi.f64(double %Val, i32 %power) diff --git a/test/CodeGen/Mips/rem.ll b/test/CodeGen/Mips/rem.ll index 70f957ce15f6..ef16483f39d3 100644 --- a/test/CodeGen/Mips/rem.ll +++ b/test/CodeGen/Mips/rem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 -4, align 4 diff --git a/test/CodeGen/Mips/remu.ll b/test/CodeGen/Mips/remu.ll index 12679727952f..dac4b05cd00a 100644 --- a/test/CodeGen/Mips/remu.ll +++ b/test/CodeGen/Mips/remu.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @iiii = global i32 103, align 4 @jjjj = global i32 4, align 4 diff --git a/test/CodeGen/Mips/s2rem.ll b/test/CodeGen/Mips/s2rem.ll index 65e48fe57c92..715abc072b4b 100644 --- a/test/CodeGen/Mips/s2rem.ll +++ b/test/CodeGen/Mips/s2rem.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=STATIC @xi = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/sb1.ll b/test/CodeGen/Mips/sb1.ll index d2e8510024e5..4724a7f2cfd7 100644 --- a/test/CodeGen/Mips/sb1.ll +++ b/test/CodeGen/Mips/sb1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 97, align 4 @c = common global i8 0, align 1 diff --git a/test/CodeGen/Mips/sel1c.ll b/test/CodeGen/Mips/sel1c.ll index 6753af106e0f..b09be8d41157 100644 --- a/test/CodeGen/Mips/sel1c.ll +++ b/test/CodeGen/Mips/sel1c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/test/CodeGen/Mips/sel2c.ll b/test/CodeGen/Mips/sel2c.ll index 987cccad5bf4..0650147be70c 100644 --- a/test/CodeGen/Mips/sel2c.ll +++ b/test/CodeGen/Mips/sel2c.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=cond-b-short @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/test/CodeGen/Mips/selTBteqzCmpi.ll b/test/CodeGen/Mips/selTBteqzCmpi.ll index 5a72ea01073c..97eba29e99fb 100644 --- a/test/CodeGen/Mips/selTBteqzCmpi.ll +++ b/test/CodeGen/Mips/selTBteqzCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/test/CodeGen/Mips/selTBtnezCmpi.ll b/test/CodeGen/Mips/selTBtnezCmpi.ll index b6407e67f27a..62af3dffb7b3 100644 --- a/test/CodeGen/Mips/selTBtnezCmpi.ll +++ b/test/CodeGen/Mips/selTBtnezCmpi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/test/CodeGen/Mips/selTBtnezSlti.ll b/test/CodeGen/Mips/selTBtnezSlti.ll index 2f1cdb866294..3851fdf093e4 100644 --- a/test/CodeGen/Mips/selTBtnezSlti.ll +++ b/test/CodeGen/Mips/selTBtnezSlti.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 2, align 4 diff --git a/test/CodeGen/Mips/seleq.ll b/test/CodeGen/Mips/seleq.ll index bd25358fb9e6..7d1e034d68c7 100644 --- a/test/CodeGen/Mips/seleq.ll +++ b/test/CodeGen/Mips/seleq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/seleqk.ll b/test/CodeGen/Mips/seleqk.ll index 2eeaa9e33738..a0bfe44eadd6 100644 --- a/test/CodeGen/Mips/seleqk.ll +++ b/test/CodeGen/Mips/seleqk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selgek.ll b/test/CodeGen/Mips/selgek.ll index 38ad95ee01a9..9d9df743db9b 100644 --- a/test/CodeGen/Mips/selgek.ll +++ b/test/CodeGen/Mips/selgek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selgt.ll b/test/CodeGen/Mips/selgt.ll index a2e1e39e742f..94f0f9b50af1 100644 --- a/test/CodeGen/Mips/selgt.ll +++ b/test/CodeGen/Mips/selgt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selle.ll b/test/CodeGen/Mips/selle.ll index 1adefb7846e4..8925aac10c4d 100644 --- a/test/CodeGen/Mips/selle.ll +++ b/test/CodeGen/Mips/selle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selltk.ll b/test/CodeGen/Mips/selltk.ll index db9f8c171b78..106fe9b85d60 100644 --- a/test/CodeGen/Mips/selltk.ll +++ b/test/CodeGen/Mips/selltk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selne.ll b/test/CodeGen/Mips/selne.ll index 9be99d669475..270c0dadd864 100644 --- a/test/CodeGen/Mips/selne.ll +++ b/test/CodeGen/Mips/selne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selnek.ll b/test/CodeGen/Mips/selnek.ll index 5b6aa2afa1af..13ab693adb8b 100644 --- a/test/CodeGen/Mips/selnek.ll +++ b/test/CodeGen/Mips/selnek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/selpat.ll b/test/CodeGen/Mips/selpat.ll index c682d8182a46..ff4bed327f45 100644 --- a/test/CodeGen/Mips/selpat.ll +++ b/test/CodeGen/Mips/selpat.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @t = global i32 10, align 4 @f = global i32 199, align 4 diff --git a/test/CodeGen/Mips/seteq.ll b/test/CodeGen/Mips/seteq.ll index 8fad6122bdbe..76f9bb3ebf9d 100644 --- a/test/CodeGen/Mips/seteq.ll +++ b/test/CodeGen/Mips/seteq.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/seteqz.ll b/test/CodeGen/Mips/seteqz.ll index 8e9a4beac75b..368e85ce886e 100644 --- a/test/CodeGen/Mips/seteqz.ll +++ b/test/CodeGen/Mips/seteqz.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 0, align 4 @j = global i32 99, align 4 diff --git a/test/CodeGen/Mips/setge.ll b/test/CodeGen/Mips/setge.ll index 8fb729964cf5..af69d7b325b9 100644 --- a/test/CodeGen/Mips/setge.ll +++ b/test/CodeGen/Mips/setge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setgek.ll b/test/CodeGen/Mips/setgek.ll index 1148d1b67bda..d6eee1ff6e18 100644 --- a/test/CodeGen/Mips/setgek.ll +++ b/test/CodeGen/Mips/setgek.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @k = global i32 10, align 4 @r1 = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/setle.ll b/test/CodeGen/Mips/setle.ll index fe4a2c37eb54..f7d25054e013 100644 --- a/test/CodeGen/Mips/setle.ll +++ b/test/CodeGen/Mips/setle.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setlt.ll b/test/CodeGen/Mips/setlt.ll index c4211e6dd696..040f8b17f219 100644 --- a/test/CodeGen/Mips/setlt.ll +++ b/test/CodeGen/Mips/setlt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setltk.ll b/test/CodeGen/Mips/setltk.ll index 8c0041111270..79d25b1f130d 100644 --- a/test/CodeGen/Mips/setltk.ll +++ b/test/CodeGen/Mips/setltk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 -5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setne.ll b/test/CodeGen/Mips/setne.ll index 484674e5da32..02692bf9e632 100644 --- a/test/CodeGen/Mips/setne.ll +++ b/test/CodeGen/Mips/setne.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 1, align 4 @j = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setuge.ll b/test/CodeGen/Mips/setuge.ll index 025b4dcefd76..6ae77b6cc1b4 100644 --- a/test/CodeGen/Mips/setuge.ll +++ b/test/CodeGen/Mips/setuge.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setugt.ll b/test/CodeGen/Mips/setugt.ll index 0ce317e0df9e..f8de59b754cf 100644 --- a/test/CodeGen/Mips/setugt.ll +++ b/test/CodeGen/Mips/setugt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setule.ll b/test/CodeGen/Mips/setule.ll index 4255fd27c5cd..8874d4d698b9 100644 --- a/test/CodeGen/Mips/setule.ll +++ b/test/CodeGen/Mips/setule.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setult.ll b/test/CodeGen/Mips/setult.ll index d30107e54dd0..29c7588a153d 100644 --- a/test/CodeGen/Mips/setult.ll +++ b/test/CodeGen/Mips/setult.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/setultk.ll b/test/CodeGen/Mips/setultk.ll index 1b79f103bed7..c1ef0aa0b059 100644 --- a/test/CodeGen/Mips/setultk.ll +++ b/test/CodeGen/Mips/setultk.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @j = global i32 5, align 4 @k = global i32 10, align 4 diff --git a/test/CodeGen/Mips/sh1.ll b/test/CodeGen/Mips/sh1.ll index 3f70b9bc6e68..ccba32a4cca9 100644 --- a/test/CodeGen/Mips/sh1.ll +++ b/test/CodeGen/Mips/sh1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 97, align 4 @s = common global i16 0, align 2 diff --git a/test/CodeGen/Mips/simplebr.ll b/test/CodeGen/Mips/simplebr.ll index 2aeacc903fbe..96dfce915e90 100644 --- a/test/CodeGen/Mips/simplebr.ll +++ b/test/CodeGen/Mips/simplebr.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mips16-hard-float -mattr=+soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mips16-hard-float -mattr=+soft-float -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC16 ; ModuleID = 'simplebr.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/sitofp-selectcc-opt.ll b/test/CodeGen/Mips/sitofp-selectcc-opt.ll index c60fceb1a04c..751fba46d72f 100644 --- a/test/CodeGen/Mips/sitofp-selectcc-opt.ll +++ b/test/CodeGen/Mips/sitofp-selectcc-opt.ll @@ -7,7 +7,7 @@ entry: ; check that this transformation doesn't happen: ; (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) ; -; CHECK-NOT: # double -1.000000e+00 +; CHECK-NOT: # double -1 %tobool1 = icmp ne i32 %a, 0 %not.tobool = icmp ne i64 %b, 0 @@ -19,4 +19,3 @@ entry: store double %add, double* @foo12.d4, align 8 ret double %add } - diff --git a/test/CodeGen/Mips/sll1.ll b/test/CodeGen/Mips/sll1.ll index 4d35b64e0b58..93b814f944c5 100644 --- a/test/CodeGen/Mips/sll1.ll +++ b/test/CodeGen/Mips/sll1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 0, align 4 diff --git a/test/CodeGen/Mips/sll2.ll b/test/CodeGen/Mips/sll2.ll index dc2236b10ccf..f30108d14df8 100644 --- a/test/CodeGen/Mips/sll2.ll +++ b/test/CodeGen/Mips/sll2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 4, align 4 diff --git a/test/CodeGen/Mips/sr1.ll b/test/CodeGen/Mips/sr1.ll index 69655f7b842c..b3fdef0a17b4 100644 --- a/test/CodeGen/Mips/sr1.ll +++ b/test/CodeGen/Mips/sr1.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=NEG +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=static < %s | FileCheck %s -check-prefix=NEG @f = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/sra1.ll b/test/CodeGen/Mips/sra1.ll index 1c7d417cb13a..51282bd8033d 100644 --- a/test/CodeGen/Mips/sra1.ll +++ b/test/CodeGen/Mips/sra1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 -354, align 4 @.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 diff --git a/test/CodeGen/Mips/sra2.ll b/test/CodeGen/Mips/sra2.ll index 771d0f4a79e3..0a2bff9e4080 100644 --- a/test/CodeGen/Mips/sra2.ll +++ b/test/CodeGen/Mips/sra2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 -354, align 4 @j = global i32 3, align 4 diff --git a/test/CodeGen/Mips/srl1.ll b/test/CodeGen/Mips/srl1.ll index a748eabb066f..8e97734bb313 100644 --- a/test/CodeGen/Mips/srl1.ll +++ b/test/CodeGen/Mips/srl1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10654, align 4 @j = global i32 0, align 4 diff --git a/test/CodeGen/Mips/srl2.ll b/test/CodeGen/Mips/srl2.ll index 6e338b39350f..4ccdefdf1413 100644 --- a/test/CodeGen/Mips/srl2.ll +++ b/test/CodeGen/Mips/srl2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10654, align 4 @j = global i32 0, align 4 diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll index 6bc4889931a7..4b3c8fb79315 100644 --- a/test/CodeGen/Mips/stchar.ll +++ b/test/CodeGen/Mips/stchar.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_h +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16_b @.str = private unnamed_addr constant [9 x i8] c"%hd %c \0A\00", align 1 @sp = common global i16* null, align 4 diff --git a/test/CodeGen/Mips/stldst.ll b/test/CodeGen/Mips/stldst.ll index 4eef5ece0589..8aecca4aed67 100644 --- a/test/CodeGen/Mips/stldst.ll +++ b/test/CodeGen/Mips/stldst.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @kkkk = global i32 67, align 4 @llll = global i32 33, align 4 diff --git a/test/CodeGen/Mips/sub1.ll b/test/CodeGen/Mips/sub1.ll index 636ab8f2c5f3..a5e698840264 100644 --- a/test/CodeGen/Mips/sub1.ll +++ b/test/CodeGen/Mips/sub1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1 diff --git a/test/CodeGen/Mips/sub2.ll b/test/CodeGen/Mips/sub2.ll index a97f5e947ca9..d10cddb9e6b9 100644 --- a/test/CodeGen/Mips/sub2.ll +++ b/test/CodeGen/Mips/sub2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @i = global i32 10, align 4 @j = global i32 20, align 4 diff --git a/test/CodeGen/Mips/tail16.ll b/test/CodeGen/Mips/tail16.ll index 13f27fcc513b..75a2a827f258 100644 --- a/test/CodeGen/Mips/tail16.ll +++ b/test/CodeGen/Mips/tail16.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic < %s | FileCheck %s ; Function Attrs: nounwind optsize define float @h() { diff --git a/test/CodeGen/Mips/tailcall.ll b/test/CodeGen/Mips/tailcall.ll index 6a0d64b7eed8..b0868255053a 100644 --- a/test/CodeGen/Mips/tailcall.ll +++ b/test/CodeGen/Mips/tailcall.ll @@ -4,7 +4,7 @@ ; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=STATIC32 ; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -enable-mips-tail-calls \ ; RUN: < %s | FileCheck %s -check-prefix=N64 -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic \ +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \ ; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=PIC16 @g0 = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/tls-alias.ll b/test/CodeGen/Mips/tls-alias.ll index b61f84e03761..5de23103c997 100644 --- a/test/CodeGen/Mips/tls-alias.ll +++ b/test/CodeGen/Mips/tls-alias.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -disable-mips-delay-filler < %s | FileCheck %s @foo = thread_local global i32 42 -@bar = hidden thread_local alias i32* @foo +@bar = hidden thread_local alias i32, i32* @foo define i32* @zed() { ; CHECK-DAG: __tls_get_addr diff --git a/test/CodeGen/Mips/tls16.ll b/test/CodeGen/Mips/tls16.ll index 3d324d7ed1e8..349e381af2b7 100644 --- a/test/CodeGen/Mips/tls16.ll +++ b/test/CodeGen/Mips/tls16.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16 @a = thread_local global i32 4, align 4 diff --git a/test/CodeGen/Mips/tls16_2.ll b/test/CodeGen/Mips/tls16_2.ll index 0a6a4123e116..b232c8534c55 100644 --- a/test/CodeGen/Mips/tls16_2.ll +++ b/test/CodeGen/Mips/tls16_2.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=PIC16 @f.i = internal thread_local unnamed_addr global i32 1, align 4 diff --git a/test/CodeGen/Mips/trap1.ll b/test/CodeGen/Mips/trap1.ll index 90755130e7c2..575574a0a3b1 100644 --- a/test/CodeGen/Mips/trap1.ll +++ b/test/CodeGen/Mips/trap1.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=pic declare void @llvm.trap() diff --git a/test/CodeGen/Mips/ul1.ll b/test/CodeGen/Mips/ul1.ll index ad0992954631..eb5187a8533a 100644 --- a/test/CodeGen/Mips/ul1.ll +++ b/test/CodeGen/Mips/ul1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 %struct.ua = type <{ i16, i32 }> @foo = common global %struct.ua zeroinitializer, align 1 diff --git a/test/CodeGen/Mips/xor1.ll b/test/CodeGen/Mips/xor1.ll index dd51f143bb6c..b203271a042b 100644 --- a/test/CodeGen/Mips/xor1.ll +++ b/test/CodeGen/Mips/xor1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 +; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 @x = global i32 65504, align 4 @y = global i32 60929, align 4 -- cgit v1.3