From 59d6cff90eecf31cb3dd860c4e786674cfdd42eb Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 10 Jun 2013 20:36:52 +0000 Subject: Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3 release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502 --- test/CodeGen/R600/fsub.ll | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) (limited to 'test/CodeGen/R600/fsub.ll') diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index 591aa52676a4..f784cde46cd2 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,8 +1,9 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; CHECK: @fsub_f32 +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -define void @test() { +define void @fsub_f32() { %r0 = call float @llvm.R600.load.input(i32 0) %r1 = call float @llvm.R600.load.input(i32 1) %r2 = fsub float %r0, %r1 @@ -14,3 +15,17 @@ declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) +; CHECK: @fsub_v4f32 +; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} + +define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float> addrspace(1) * %in + %b = load <4 x float> addrspace(1) * %b_ptr + %result = fsub <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} -- cgit v1.3