From 01095a5d43bbfde13731688ddcf6048ebb8b7721 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Sat, 23 Jul 2016 20:41:05 +0000 Subject: Vendor import of llvm release_39 branch r276489: https://llvm.org/svn/llvm-project/llvm/branches/release_39@276489 --- test/CodeGen/AArch64/128bit_load_store.ll | 2 +- .../AArch64/GlobalISel/arm64-irtranslator.ll | 63 + .../AArch64/GlobalISel/arm64-regbankselect.mir | 329 + test/CodeGen/AArch64/a57-csel.ll | 5 +- .../aarch64-2014-08-11-MachineCombinerCrash.ll | 5 +- ...64-DAGCombine-findBetterNeighborChains-crash.ll | 43 + .../AArch64/aarch64-a57-fp-load-balancing.ll | 18 +- test/CodeGen/AArch64/aarch64-be-bv.ll | 198 +- test/CodeGen/AArch64/aarch64-deferred-spilling.ll | 514 - .../AArch64/aarch64-dynamic-stack-layout.ll | 223 +- test/CodeGen/AArch64/aarch64-gep-opt.ll | 3 + .../aarch64-interleaved-accesses-extract-user.ll | 86 + .../AArch64/aarch64-interleaved-accesses.ll | 12 + test/CodeGen/AArch64/aarch64-smull.ll | 4 +- test/CodeGen/AArch64/aarch64-stp-cluster.ll | 149 + test/CodeGen/AArch64/aarch64-tbz.ll | 98 + .../aarch64-tryBitfieldInsertOpFromOr-crash.ll | 36 + test/CodeGen/AArch64/addsub.ll | 8 +- test/CodeGen/AArch64/alloca.ll | 18 +- .../AArch64/arm64-2011-03-17-AsmPrinterCrash.ll | 15 +- test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll | 8 +- test/CodeGen/AArch64/arm64-aapcs-be.ll | 3 +- test/CodeGen/AArch64/arm64-abi-varargs.ll | 2 +- test/CodeGen/AArch64/arm64-abi.ll | 2 +- test/CodeGen/AArch64/arm64-abi_align.ll | 32 +- test/CodeGen/AArch64/arm64-addrmode.ll | 10 +- .../AArch64/arm64-alloc-no-stack-realign.ll | 2 +- test/CodeGen/AArch64/arm64-atomic-128.ll | 6 +- test/CodeGen/AArch64/arm64-atomic.ll | 2 +- test/CodeGen/AArch64/arm64-bitfield-extract.ll | 10 +- test/CodeGen/AArch64/arm64-build-vector.ll | 4 +- test/CodeGen/AArch64/arm64-builtins-linux.ll | 4 +- test/CodeGen/AArch64/arm64-ccmp.ll | 249 +- test/CodeGen/AArch64/arm64-collect-loh.ll | 22 + test/CodeGen/AArch64/arm64-const-addr.ll | 4 +- test/CodeGen/AArch64/arm64-convert-v4f64.ll | 4 +- test/CodeGen/AArch64/arm64-csldst-mmo.ll | 25 + test/CodeGen/AArch64/arm64-detect-vec-redux.ll | 52 + test/CodeGen/AArch64/arm64-extern-weak.ll | 15 +- test/CodeGen/AArch64/arm64-extract.ll | 2 +- .../CodeGen/AArch64/arm64-fast-isel-addr-offset.ll | 16 +- test/CodeGen/AArch64/arm64-fast-isel-alloca.ll | 4 +- test/CodeGen/AArch64/arm64-fast-isel-call.ll | 6 +- test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 4 +- test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 8 +- test/CodeGen/AArch64/arm64-fcopysign.ll | 4 +- test/CodeGen/AArch64/arm64-fma-combines.ll | 136 + test/CodeGen/AArch64/arm64-fml-combines.ll | 128 + test/CodeGen/AArch64/arm64-fp128.ll | 4 +- test/CodeGen/AArch64/arm64-hello.ll | 21 +- test/CodeGen/AArch64/arm64-inline-asm.ll | 16 +- test/CodeGen/AArch64/arm64-join-reserved.ll | 2 +- test/CodeGen/AArch64/arm64-ldp-cluster.ll | 150 + test/CodeGen/AArch64/arm64-memcpy-inline.ll | 6 +- test/CodeGen/AArch64/arm64-misched-basic-A53.ll | 1 + test/CodeGen/AArch64/arm64-misched-memdep-bug.ll | 3 + test/CodeGen/AArch64/arm64-misched-multimmo.ll | 23 + test/CodeGen/AArch64/arm64-movi.ll | 98 +- test/CodeGen/AArch64/arm64-mul.ll | 62 + test/CodeGen/AArch64/arm64-narrow-ldst-merge.ll | 94 +- test/CodeGen/AArch64/arm64-neon-2velem-high.ll | 36 +- test/CodeGen/AArch64/arm64-neon-copy.ll | 41 +- test/CodeGen/AArch64/arm64-nvcast.ll | 6 +- .../AArch64/arm64-patchpoint-webkit_jscc.ll | 58 +- test/CodeGen/AArch64/arm64-patchpoint.ll | 19 +- test/CodeGen/AArch64/arm64-register-pairing.ll | 31 +- test/CodeGen/AArch64/arm64-regress-opt-cmp.mir | 42 + test/CodeGen/AArch64/arm64-rev.ll | 27 + test/CodeGen/AArch64/arm64-shrink-wrapping.ll | 70 +- test/CodeGen/AArch64/arm64-stp-aa.ll | 34 + test/CodeGen/AArch64/arm64-stp.ll | 4 +- .../AArch64/arm64-swizzle-tbl-i16-layout.ll | 4 +- test/CodeGen/AArch64/arm64-this-return.ll | 2 +- test/CodeGen/AArch64/arm64-tls-dynamic-together.ll | 2 +- test/CodeGen/AArch64/arm64-variadic-aapcs.ll | 6 +- test/CodeGen/AArch64/arm64-vclz.ll | 28 + test/CodeGen/AArch64/arm64-vecCmpBr.ll | 8 +- test/CodeGen/AArch64/arm64-vector-ext.ll | 2 +- test/CodeGen/AArch64/arm64-vector-imm.ll | 18 +- test/CodeGen/AArch64/arm64-virtual_base.ll | 2 +- test/CodeGen/AArch64/arm64-vshift.ll | 2 +- test/CodeGen/AArch64/arm64-vshuffle.ll | 2 +- test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll | 72 +- test/CodeGen/AArch64/atomic-ops.ll | 2 +- test/CodeGen/AArch64/bitfield-extract.ll | 98 + test/CodeGen/AArch64/bitfield-insert.ll | 245 +- test/CodeGen/AArch64/bitfield.ll | 2 +- test/CodeGen/AArch64/bitreverse.ll | 17 +- test/CodeGen/AArch64/branch-folder-merge-mmos.ll | 2 +- test/CodeGen/AArch64/bswap-known-bits.ll | 44 + test/CodeGen/AArch64/cmpxchg-O0.ll | 75 + test/CodeGen/AArch64/combine-comparisons-by-cse.ll | 44 +- test/CodeGen/AArch64/complex-int-to-fp.ll | 2 +- test/CodeGen/AArch64/cond-sel.ll | 40 +- test/CodeGen/AArch64/cpus.ll | 3 + test/CodeGen/AArch64/cxx-tlscc.ll | 127 +- test/CodeGen/AArch64/dag-combine-invaraints.ll | 2 +- test/CodeGen/AArch64/directcond.ll | 2 +- test/CodeGen/AArch64/div_minsize.ll | 45 + test/CodeGen/AArch64/emutls.ll | 121 +- test/CodeGen/AArch64/emutls_generic.ll | 9 +- test/CodeGen/AArch64/extern-weak.ll | 15 +- test/CodeGen/AArch64/f16-instructions.ll | 38 +- .../CodeGen/AArch64/fast-isel-branch-cond-split.ll | 4 +- test/CodeGen/AArch64/fast-isel-cmp-vec.ll | 12 +- test/CodeGen/AArch64/fast-isel-gep.ll | 2 +- test/CodeGen/AArch64/fast-isel-tbz.ll | 4 +- test/CodeGen/AArch64/fastcc.ll | 147 +- test/CodeGen/AArch64/fcvt-int.ll | 25 + test/CodeGen/AArch64/fcvt_combine.ll | 8 + test/CodeGen/AArch64/fdiv-combine.ll | 30 +- test/CodeGen/AArch64/fdiv_combine.ll | 4 +- test/CodeGen/AArch64/fp-cond-sel.ll | 6 +- test/CodeGen/AArch64/fp16-v4-instructions.ll | 133 +- test/CodeGen/AArch64/fp16-vector-nvcast.ll | 12 +- test/CodeGen/AArch64/fpimm.ll | 13 +- test/CodeGen/AArch64/func-argpassing.ll | 2 +- test/CodeGen/AArch64/func-calls.ll | 14 +- test/CodeGen/AArch64/gep-nullptr.ll | 23 + test/CodeGen/AArch64/global-merge-3.ll | 4 +- test/CodeGen/AArch64/global-merge-group-by-use.ll | 4 +- test/CodeGen/AArch64/half.ll | 12 + test/CodeGen/AArch64/hints.ll | 2 +- test/CodeGen/AArch64/inlineasm-X-allocation.ll | 17 + test/CodeGen/AArch64/inlineasm-X-constraint.ll | 152 + test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll | 4 +- .../AArch64/ldp-stp-scaled-unscaled-pairs.ll | 125 + test/CodeGen/AArch64/lit.local.cfg | 2 - test/CodeGen/AArch64/local_vars.ll | 15 +- test/CodeGen/AArch64/logical-imm.ll | 4 +- .../AArch64/lower-range-metadata-func-call.ll | 44 + test/CodeGen/AArch64/machine-combiner.ll | 2 +- test/CodeGen/AArch64/machine-copy-remove.ll | 94 + test/CodeGen/AArch64/merge-store-dependency.ll | 63 + test/CodeGen/AArch64/merge-store.ll | 13 +- test/CodeGen/AArch64/misched-fusion.ll | 10 +- test/CodeGen/AArch64/movimm-wzr.mir | 46 + test/CodeGen/AArch64/movw-consts.ll | 10 +- test/CodeGen/AArch64/neg-imm.ll | 46 + test/CodeGen/AArch64/neon-compare-instructions.ll | 57 + test/CodeGen/AArch64/neon-mov.ll | 2 +- test/CodeGen/AArch64/neon-perm.ll | 2 +- test/CodeGen/AArch64/no-quad-ldp-stp.ll | 29 + test/CodeGen/AArch64/nontemporal.ll | 6 +- test/CodeGen/AArch64/nzcv-save.ll | 2 +- test/CodeGen/AArch64/optimize-cond-branch.ll | 48 + test/CodeGen/AArch64/pie.ll | 14 + test/CodeGen/AArch64/preferred-alignment.ll | 28 + test/CodeGen/AArch64/preserve_mostcc.ll | 40 + test/CodeGen/AArch64/recp-fastmath.ll | 79 + test/CodeGen/AArch64/regress-tblgen-chains.ll | 2 +- test/CodeGen/AArch64/rem_crash.ll | 257 + test/CodeGen/AArch64/remat.ll | 10 +- test/CodeGen/AArch64/sibling-call.ll | 2 +- test/CodeGen/AArch64/special-reg.ll | 2 +- test/CodeGen/AArch64/sqrt-fastmath.ll | 160 + test/CodeGen/AArch64/stack-guard-remat-bitcast.ll | 8 +- test/CodeGen/AArch64/stack-protector-target.ll | 19 + test/CodeGen/AArch64/stackmap-frame-setup.ll | 4 +- test/CodeGen/AArch64/stackmap-liveness.ll | 2 +- test/CodeGen/AArch64/subs-to-sub-opt.ll | 23 + test/CodeGen/AArch64/swifterror.ll | 385 + test/CodeGen/AArch64/swiftself.ll | 67 + test/CodeGen/AArch64/tailcall-ccmismatch.ll | 24 + test/CodeGen/AArch64/tailcall-implicit-sret.ll | 2 +- test/CodeGen/AArch64/tailcall_misched_graph.ll | 6 +- test/CodeGen/AArch64/tailmerging_in_mbp.ll | 63 + test/CodeGen/AArch64/vcvt-oversize.ll | 5 +- test/CodeGen/AArch64/vector-fcopysign.ll | 28 +- test/CodeGen/AArch64/vector_merge_dep_check.ll | 41 + test/CodeGen/AMDGPU/32-bit-local-address-space.ll | 6 +- .../AMDGPU/GlobalISel/amdgpu-irtranslator.ll | 12 + test/CodeGen/AMDGPU/add.ll | 27 +- test/CodeGen/AMDGPU/add_i64.ll | 8 +- test/CodeGen/AMDGPU/address-space.ll | 32 - test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll | 106 + test/CodeGen/AMDGPU/addrspacecast.ll | 235 +- test/CodeGen/AMDGPU/amdgcn.private-memory.ll | 31 + test/CodeGen/AMDGPU/amdgcn.work-item-intrinsics.ll | 114 + test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll | 8 + .../AMDGPU/amdgpu-shader-calling-convention.ll | 21 + test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 530 + .../amdgpu.work-item-intrinsics.deprecated.ll | 268 + test/CodeGen/AMDGPU/and-gcn.ll | 27 + test/CodeGen/AMDGPU/and.ll | 289 +- .../CodeGen/AMDGPU/annotate-kernel-features-hsa.ll | 238 + test/CodeGen/AMDGPU/annotate-kernel-features.ll | 8 +- test/CodeGen/AMDGPU/array-ptr-calc-i32.ll | 38 +- test/CodeGen/AMDGPU/array-ptr-calc-i64.ll | 10 +- test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll | 14 +- test/CodeGen/AMDGPU/atomic_load_sub.ll | 4 +- test/CodeGen/AMDGPU/basic-branch.ll | 49 +- test/CodeGen/AMDGPU/bfm.ll | 24 + test/CodeGen/AMDGPU/big_alu.ll | 2345 +++-- test/CodeGen/AMDGPU/bitcast.ll | 36 +- .../CodeGen/AMDGPU/bitreverse-inline-immediates.ll | 158 + test/CodeGen/AMDGPU/bitreverse.ll | 10 - test/CodeGen/AMDGPU/branch-uniformity.ll | 41 + test/CodeGen/AMDGPU/bug-vopc-commute.ll | 49 + test/CodeGen/AMDGPU/call.ll | 18 +- test/CodeGen/AMDGPU/call_fs.ll | 4 +- test/CodeGen/AMDGPU/captured-frame-index.ll | 166 + test/CodeGen/AMDGPU/cayman-loop-bug.ll | 14 +- test/CodeGen/AMDGPU/cf-loop-on-constant.ll | 121 + test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll | 2 +- test/CodeGen/AMDGPU/cgp-addressing-modes.ll | 118 +- test/CodeGen/AMDGPU/cgp-bitfield-extract.ll | 301 + test/CodeGen/AMDGPU/ci-use-flat-for-global.ll | 19 +- test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll | 56 + test/CodeGen/AMDGPU/coalescer_distribute.ll | 53 + test/CodeGen/AMDGPU/commute-compares.ll | 104 +- test/CodeGen/AMDGPU/commute-shifts.ll | 36 +- test/CodeGen/AMDGPU/commute_modifiers.ll | 68 +- test/CodeGen/AMDGPU/complex-folding.ll | 8 +- test/CodeGen/AMDGPU/convergent-inlineasm.ll | 45 + test/CodeGen/AMDGPU/copy-illegal-type.ll | 104 +- test/CodeGen/AMDGPU/ctlz.ll | 10 +- test/CodeGen/AMDGPU/ctlz_zero_undef.ll | 8 +- test/CodeGen/AMDGPU/ctpop.ll | 12 +- test/CodeGen/AMDGPU/ctpop64.ll | 65 +- test/CodeGen/AMDGPU/cube.ll | 46 + test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 130 +- test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll | 33 + test/CodeGen/AMDGPU/debugger-emit-prologue.ll | 80 + test/CodeGen/AMDGPU/debugger-insert-nops.ll | 71 + test/CodeGen/AMDGPU/debugger-reserve-regs.ll | 62 + test/CodeGen/AMDGPU/default-fp-mode.ll | 78 +- test/CodeGen/AMDGPU/detect-dead-lanes.mir | 428 + test/CodeGen/AMDGPU/dot4-folding.ll | 27 - test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll | 12 +- .../ds-negative-offset-addressing-mode-loop.ll | 30 +- test/CodeGen/AMDGPU/ds-sub-offset.ll | 17 +- test/CodeGen/AMDGPU/ds_read2.ll | 52 +- test/CodeGen/AMDGPU/ds_read2_offset_order.ll | 5 +- test/CodeGen/AMDGPU/ds_read2_superreg.ll | 86 +- test/CodeGen/AMDGPU/ds_read2st64.ll | 54 +- test/CodeGen/AMDGPU/ds_write2.ll | 81 +- test/CodeGen/AMDGPU/ds_write2st64.ll | 37 +- test/CodeGen/AMDGPU/dynamic_stackalloc.ll | 2 +- test/CodeGen/AMDGPU/elf.ll | 6 +- test/CodeGen/AMDGPU/endcf-loop-header.ll | 7 +- test/CodeGen/AMDGPU/extload-private.ll | 6 +- test/CodeGen/AMDGPU/extload.ll | 54 +- .../extract-vector-elt-build-vector-combine.ll | 126 + test/CodeGen/AMDGPU/extract-vector-elt-i64.ll | 43 - test/CodeGen/AMDGPU/extract_vector_elt-f64.ll | 29 + test/CodeGen/AMDGPU/extract_vector_elt-i16.ll | 86 + test/CodeGen/AMDGPU/extract_vector_elt-i64.ll | 62 + test/CodeGen/AMDGPU/extract_vector_elt-i8.ll | 151 + test/CodeGen/AMDGPU/extract_vector_elt_i16.ll | 30 - test/CodeGen/AMDGPU/extractelt-to-trunc.ll | 77 + test/CodeGen/AMDGPU/fabs.f64.ll | 6 +- test/CodeGen/AMDGPU/fadd.ll | 4 +- test/CodeGen/AMDGPU/fcanonicalize.ll | 351 + test/CodeGen/AMDGPU/fceil64.ll | 15 +- test/CodeGen/AMDGPU/fcopysign.f64.ll | 4 +- test/CodeGen/AMDGPU/fdiv.f64.ll | 8 +- test/CodeGen/AMDGPU/fdiv.ll | 207 +- test/CodeGen/AMDGPU/fetch-limits.r600.ll | 70 +- test/CodeGen/AMDGPU/fetch-limits.r700+.ll | 84 +- test/CodeGen/AMDGPU/ffloor.f64.ll | 33 +- test/CodeGen/AMDGPU/flat-address-space.ll | 5 +- test/CodeGen/AMDGPU/flat_atomics.ll | 968 ++ test/CodeGen/AMDGPU/flat_atomics_i64.ll | 975 ++ test/CodeGen/AMDGPU/floor.ll | 7 +- test/CodeGen/AMDGPU/fma-combine.ll | 144 +- test/CodeGen/AMDGPU/fma.ll | 2 +- test/CodeGen/AMDGPU/fmad.ll | 8 +- test/CodeGen/AMDGPU/fmax.ll | 8 +- test/CodeGen/AMDGPU/fmax3.f64.ll | 12 +- test/CodeGen/AMDGPU/fmax3.ll | 12 +- test/CodeGen/AMDGPU/fmax_legacy.f64.ll | 12 +- test/CodeGen/AMDGPU/fmax_legacy.ll | 24 +- test/CodeGen/AMDGPU/fmaxnum.ll | 8 +- test/CodeGen/AMDGPU/fmed3.ll | 154 + test/CodeGen/AMDGPU/fmin.ll | 8 +- test/CodeGen/AMDGPU/fmin3.ll | 12 +- test/CodeGen/AMDGPU/fmin_legacy.f64.ll | 12 +- test/CodeGen/AMDGPU/fmin_legacy.ll | 53 +- test/CodeGen/AMDGPU/fminnum.ll | 8 +- test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll | 16 +- test/CodeGen/AMDGPU/fmul.ll | 51 +- test/CodeGen/AMDGPU/fmuladd.ll | 52 +- test/CodeGen/AMDGPU/fneg-fabs.f64.ll | 59 +- test/CodeGen/AMDGPU/fneg.f64.ll | 2 +- test/CodeGen/AMDGPU/fp-classify.ll | 5 +- test/CodeGen/AMDGPU/fp_to_sint.f64.ll | 6 +- test/CodeGen/AMDGPU/fp_to_sint.ll | 4 +- test/CodeGen/AMDGPU/fp_to_uint.f64.ll | 6 +- test/CodeGen/AMDGPU/fpext.ll | 12 +- test/CodeGen/AMDGPU/fract.f64.ll | 111 + test/CodeGen/AMDGPU/fract.ll | 74 + test/CodeGen/AMDGPU/frem.ll | 8 +- test/CodeGen/AMDGPU/fsqrt.f64.ll | 26 + test/CodeGen/AMDGPU/fsqrt.ll | 154 +- test/CodeGen/AMDGPU/fsub.ll | 7 +- test/CodeGen/AMDGPU/fsub64.ll | 4 +- test/CodeGen/AMDGPU/ftrunc.f64.ll | 10 +- test/CodeGen/AMDGPU/ftrunc.ll | 4 +- test/CodeGen/AMDGPU/global-constant.ll | 2 +- test/CodeGen/AMDGPU/global-extload-i1.ll | 302 - test/CodeGen/AMDGPU/global-extload-i16.ll | 302 - test/CodeGen/AMDGPU/global-extload-i32.ll | 308 - test/CodeGen/AMDGPU/global-extload-i8.ll | 299 - test/CodeGen/AMDGPU/global-variable-relocs.ll | 203 + test/CodeGen/AMDGPU/global-zero-initializer.ll | 13 - test/CodeGen/AMDGPU/global_atomics.ll | 687 +- test/CodeGen/AMDGPU/global_atomics_i64.ll | 1037 ++ test/CodeGen/AMDGPU/gv-const-addrspace-fail.ll | 57 - test/CodeGen/AMDGPU/gv-const-addrspace.ll | 37 +- test/CodeGen/AMDGPU/gv-offset-folding.ll | 21 + test/CodeGen/AMDGPU/half.ll | 105 +- test/CodeGen/AMDGPU/hsa-default-device.ll | 11 + test/CodeGen/AMDGPU/hsa-fp-mode.ll | 68 + test/CodeGen/AMDGPU/hsa-func.ll | 61 + test/CodeGen/AMDGPU/hsa-globals.ll | 146 +- test/CodeGen/AMDGPU/hsa-note-no-func.ll | 2 +- test/CodeGen/AMDGPU/hsa.ll | 19 +- test/CodeGen/AMDGPU/i1-copy-implicit-def.ll | 5 +- test/CodeGen/AMDGPU/i1-copy-phi.ll | 13 +- test/CodeGen/AMDGPU/imm.ll | 44 +- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 325 +- test/CodeGen/AMDGPU/indirect-addressing-undef.mir | 327 + test/CodeGen/AMDGPU/indirect-private-64.ll | 101 +- test/CodeGen/AMDGPU/inline-asm.ll | 174 +- test/CodeGen/AMDGPU/input-mods.ll | 8 +- test/CodeGen/AMDGPU/insert_vector_elt.ll | 358 +- test/CodeGen/AMDGPU/invalid-addrspacecast.ll | 8 + .../AMDGPU/invariant-load-no-alias-store.ll | 8 +- test/CodeGen/AMDGPU/jump-address.ll | 8 +- test/CodeGen/AMDGPU/kcache-fold.ll | 24 +- test/CodeGen/AMDGPU/kernarg-stack-alignment.ll | 44 + test/CodeGen/AMDGPU/kernel-args.ll | 54 +- test/CodeGen/AMDGPU/large-alloca-compute.ll | 24 +- test/CodeGen/AMDGPU/large-alloca-graphics.ll | 33 +- .../AMDGPU/large-work-group-promote-alloca.ll | 117 + test/CodeGen/AMDGPU/large-work-group-registers.ll | 41 + test/CodeGen/AMDGPU/lds-alignment.ll | 268 + test/CodeGen/AMDGPU/lds-initializer.ll | 2 +- test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll | 47 + test/CodeGen/AMDGPU/lds-output-queue.ll | 6 +- test/CodeGen/AMDGPU/lds-size.ll | 14 +- test/CodeGen/AMDGPU/lds-zero-initializer.ll | 2 +- test/CodeGen/AMDGPU/literals.ll | 4 +- test/CodeGen/AMDGPU/liveness.mir | 32 + test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll | 47 - test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.global.ll | 30 - test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.local.ll | 31 - test/CodeGen/AMDGPU/llvm.AMDGPU.bfi.ll | 42 - test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll | 60 - test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll | 13 +- test/CodeGen/AMDGPU/llvm.AMDGPU.class.ll | 499 - test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll | 88 +- test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll | 43 - test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll | 31 - test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll | 178 - test/CodeGen/AMDGPU/llvm.AMDGPU.div_scale.ll | 364 - test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll | 60 - test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll | 65 - test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll | 22 - test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll | 33 - test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll | 33 - test/CodeGen/AMDGPU/llvm.AMDGPU.imul24.ll | 16 - test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll | 7 +- test/CodeGen/AMDGPU/llvm.AMDGPU.ldexp.ll | 23 - test/CodeGen/AMDGPU/llvm.AMDGPU.legacy.rsq.ll | 13 - test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll | 17 - test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.f64.ll | 33 - test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.ll | 50 - test/CodeGen/AMDGPU/llvm.AMDGPU.read.workdim.ll | 37 - test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll | 23 - test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll | 23 - test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll | 33 - test/CodeGen/AMDGPU/llvm.AMDGPU.tex.ll | 42 - test/CodeGen/AMDGPU/llvm.AMDGPU.trig_preop.ll | 30 - test/CodeGen/AMDGPU/llvm.AMDGPU.trunc.ll | 17 - test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll | 38 - test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll | 48 - test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll | 48 - test/CodeGen/AMDGPU/llvm.AMDGPU.umul24.ll | 18 - test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll | 17 +- test/CodeGen/AMDGPU/llvm.SI.gather4.ll | 328 +- test/CodeGen/AMDGPU/llvm.SI.getlod.ll | 27 +- test/CodeGen/AMDGPU/llvm.SI.image.ll | 21 +- test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll | 94 + test/CodeGen/AMDGPU/llvm.SI.image.sample.ll | 123 +- test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll | 123 +- test/CodeGen/AMDGPU/llvm.SI.imageload.ll | 132 - test/CodeGen/AMDGPU/llvm.SI.load.dword.ll | 11 +- test/CodeGen/AMDGPU/llvm.SI.packf16.ll | 7 +- test/CodeGen/AMDGPU/llvm.SI.resinfo.ll | 111 - test/CodeGen/AMDGPU/llvm.SI.sample-masked.ll | 96 - test/CodeGen/AMDGPU/llvm.SI.sample.ll | 160 - test/CodeGen/AMDGPU/llvm.SI.sampled.ll | 143 - test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll | 21 +- test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll | 8 +- test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll | 10 +- test/CodeGen/AMDGPU/llvm.SI.tid.ll | 18 - test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll | 387 + test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll | 383 + test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll | 126 + .../AMDGPU/llvm.amdgcn.buffer.load.format.ll | 133 + test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll | 119 + .../AMDGPU/llvm.amdgcn.buffer.store.format.ll | 95 + test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll | 95 + test/CodeGen/AMDGPU/llvm.amdgcn.class.ll | 511 + test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll | 31 + test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll | 178 + test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll | 364 + test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll | 33 + test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll | 24 + test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll | 34 + test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll | 64 + test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll | 64 + .../CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll | 56 + test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll | 123 + test/CodeGen/AMDGPU/llvm.amdgcn.image.ll | 110 + test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll | 9 +- .../AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll | 34 + test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll | 31 + test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll | 14 + test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll | 17 + test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll | 2 +- test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll | 66 + test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll | 59 + test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll | 19 + test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll | 128 + test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll | 46 + test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll | 49 + test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll | 39 + test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll | 68 + test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll | 28 + test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll | 6 +- .../CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll | 16 + test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll | 22 + test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll | 23 + test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll | 45 + test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll | 38 + test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll | 15 + test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll | 30 + test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll | 107 + test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll | 56 + test/CodeGen/AMDGPU/llvm.amdgpu.dp4.ll | 11 - test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll | 4 +- test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll | 13 - test/CodeGen/AMDGPU/llvm.cos.ll | 8 +- test/CodeGen/AMDGPU/llvm.dbg.value.ll | 7 +- test/CodeGen/AMDGPU/llvm.memcpy.ll | 224 +- test/CodeGen/AMDGPU/llvm.pow.ll | 12 +- test/CodeGen/AMDGPU/llvm.r600.dot4.ll | 11 + test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll | 31 + test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll | 36 + test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll | 11 + test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll | 28 + test/CodeGen/AMDGPU/llvm.r600.tex.ll | 65 + test/CodeGen/AMDGPU/llvm.rint.ll | 16 +- test/CodeGen/AMDGPU/llvm.round.f64.ll | 6 +- test/CodeGen/AMDGPU/llvm.round.ll | 6 +- test/CodeGen/AMDGPU/llvm.sin.ll | 90 +- test/CodeGen/AMDGPU/llvm.sqrt.ll | 105 - test/CodeGen/AMDGPU/load-constant-f64.ll | 15 + test/CodeGen/AMDGPU/load-constant-i1.ll | 371 + test/CodeGen/AMDGPU/load-constant-i16.ll | 441 + test/CodeGen/AMDGPU/load-constant-i32.ll | 380 + test/CodeGen/AMDGPU/load-constant-i64.ll | 84 + test/CodeGen/AMDGPU/load-constant-i8.ll | 567 + test/CodeGen/AMDGPU/load-global-f32.ll | 93 + test/CodeGen/AMDGPU/load-global-f64.ll | 94 + test/CodeGen/AMDGPU/load-global-i1.ll | 371 + test/CodeGen/AMDGPU/load-global-i16.ll | 476 + test/CodeGen/AMDGPU/load-global-i32.ll | 521 + test/CodeGen/AMDGPU/load-global-i64.ll | 122 + test/CodeGen/AMDGPU/load-global-i8.ll | 564 + test/CodeGen/AMDGPU/load-i1.ll | 149 - test/CodeGen/AMDGPU/load-input-fold.ll | 13 +- test/CodeGen/AMDGPU/load-local-f32.ll | 110 + test/CodeGen/AMDGPU/load-local-f64.ll | 154 + test/CodeGen/AMDGPU/load-local-i1.ll | 371 + test/CodeGen/AMDGPU/load-local-i16.ll | 454 + test/CodeGen/AMDGPU/load-local-i32.ll | 182 + test/CodeGen/AMDGPU/load-local-i64.ll | 154 + test/CodeGen/AMDGPU/load-local-i8.ll | 556 + test/CodeGen/AMDGPU/load-weird-sizes.ll | 31 + test/CodeGen/AMDGPU/load.ll | 737 -- test/CodeGen/AMDGPU/load.vec.ll | 25 - test/CodeGen/AMDGPU/load64.ll | 31 - test/CodeGen/AMDGPU/local-64.ll | 18 +- test/CodeGen/AMDGPU/local-atomics.ll | 87 +- test/CodeGen/AMDGPU/local-atomics64.ll | 154 +- test/CodeGen/AMDGPU/local-memory-two-objects.ll | 63 - test/CodeGen/AMDGPU/local-memory.amdgcn.ll | 92 + test/CodeGen/AMDGPU/local-memory.ll | 69 +- test/CodeGen/AMDGPU/local-memory.r600.ll | 87 + test/CodeGen/AMDGPU/local-stack-slot-bug.ll | 22 + .../AMDGPU/lower-range-metadata-intrinsic-call.ll | 46 + test/CodeGen/AMDGPU/m0-spill.ll | 2 +- test/CodeGen/AMDGPU/mad-combine.ll | 168 +- test/CodeGen/AMDGPU/mad-sub.ll | 72 +- test/CodeGen/AMDGPU/mad24-get-global-id.ll | 36 + test/CodeGen/AMDGPU/mad_int24.ll | 15 +- test/CodeGen/AMDGPU/mad_uint24.ll | 4 +- test/CodeGen/AMDGPU/madak.ll | 59 +- test/CodeGen/AMDGPU/madmk.ll | 58 +- test/CodeGen/AMDGPU/max-literals.ll | 17 +- test/CodeGen/AMDGPU/max.ll | 183 +- test/CodeGen/AMDGPU/max3.ll | 8 +- test/CodeGen/AMDGPU/merge-stores.ll | 46 +- test/CodeGen/AMDGPU/min.ll | 209 +- test/CodeGen/AMDGPU/min3.ll | 12 +- test/CodeGen/AMDGPU/missing-store.ll | 8 +- .../AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll | 7 +- test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll | 6 +- test/CodeGen/AMDGPU/mubuf.ll | 41 +- test/CodeGen/AMDGPU/mul.ll | 6 +- test/CodeGen/AMDGPU/mul_int24.ll | 4 +- test/CodeGen/AMDGPU/mul_uint24.ll | 4 +- test/CodeGen/AMDGPU/multilevel-break.ll | 41 + test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll | 14 +- .../AMDGPU/no-initializer-constant-addrspace.ll | 15 +- test/CodeGen/AMDGPU/no-shrink-extloads.ll | 32 +- test/CodeGen/AMDGPU/opencl-image-metadata.ll | 2 +- test/CodeGen/AMDGPU/operand-folding.ll | 17 +- test/CodeGen/AMDGPU/or.ll | 2 +- test/CodeGen/AMDGPU/over-max-lds-size.ll | 14 + test/CodeGen/AMDGPU/parallelandifcollapse.ll | 3 +- .../partially-dead-super-register-immediate.ll | 4 +- test/CodeGen/AMDGPU/predicate-dp4.ll | 11 +- test/CodeGen/AMDGPU/predicates.ll | 20 +- test/CodeGen/AMDGPU/private-element-size.ll | 252 + test/CodeGen/AMDGPU/private-memory-atomics.ll | 12 +- test/CodeGen/AMDGPU/private-memory-broken.ll | 2 +- test/CodeGen/AMDGPU/private-memory-r600.ll | 300 + test/CodeGen/AMDGPU/private-memory.ll | 325 - .../AMDGPU/promote-alloca-array-allocation.ll | 50 + .../AMDGPU/promote-alloca-bitcast-function.ll | 3 +- test/CodeGen/AMDGPU/promote-alloca-globals.ll | 35 + .../AMDGPU/promote-alloca-invariant-markers.ll | 25 + test/CodeGen/AMDGPU/promote-alloca-lifetime.ll | 24 + .../AMDGPU/promote-alloca-mem-intrinsics.ll | 65 + test/CodeGen/AMDGPU/promote-alloca-no-opts.ll | 38 + .../AMDGPU/promote-alloca-padding-size-estimate.ll | 130 + test/CodeGen/AMDGPU/promote-alloca-shaders.ll | 29 + .../AMDGPU/promote-alloca-stored-pointer-value.ll | 35 +- test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll | 64 + test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll | 204 + .../CodeGen/AMDGPU/promote-alloca-to-lds-select.ll | 133 + .../AMDGPU/promote-alloca-unhandled-intrinsic.ll | 24 + test/CodeGen/AMDGPU/promote-alloca-volatile.ll | 45 + test/CodeGen/AMDGPU/pv-packing.ll | 13 +- test/CodeGen/AMDGPU/pv.ll | 49 +- test/CodeGen/AMDGPU/r600-encoding.ll | 8 +- test/CodeGen/AMDGPU/r600-export-fix.ll | 22 +- ...-infinite-loop-bug-while-reorganizing-vector.ll | 94 +- test/CodeGen/AMDGPU/r600.private-memory.ll | 26 + test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll | 107 + test/CodeGen/AMDGPU/r600cfg.ll | 18 +- test/CodeGen/AMDGPU/rcp-pattern.ll | 11 + .../AMDGPU/read-register-invalid-subtarget.ll | 14 + .../AMDGPU/read-register-invalid-type-i32.ll | 14 + .../AMDGPU/read-register-invalid-type-i64.ll | 13 + test/CodeGen/AMDGPU/read_register.ll | 81 + test/CodeGen/AMDGPU/readcyclecounter.ll | 25 + test/CodeGen/AMDGPU/reciprocal.ll | 8 +- test/CodeGen/AMDGPU/reduce-load-width-alignment.ll | 38 + .../CodeGen/AMDGPU/reduce-store-width-alignment.ll | 53 + test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll | 43 + test/CodeGen/AMDGPU/register-count-comments.ll | 6 +- test/CodeGen/AMDGPU/rename-disconnected-bug.ll | 33 + test/CodeGen/AMDGPU/rename-independent-subregs.mir | 30 + test/CodeGen/AMDGPU/reorder-stores.ll | 6 +- test/CodeGen/AMDGPU/ret.ll | 43 +- test/CodeGen/AMDGPU/ret_jump.ll | 63 + test/CodeGen/AMDGPU/rotl.ll | 4 +- test/CodeGen/AMDGPU/rsq.ll | 14 +- test/CodeGen/AMDGPU/runtime-metadata.ll | 848 ++ test/CodeGen/AMDGPU/rv7x0_count3.ll | 79 +- test/CodeGen/AMDGPU/s_addk_i32.ll | 93 + test/CodeGen/AMDGPU/s_mulk_i32.ll | 41 + test/CodeGen/AMDGPU/salu-to-valu.ll | 106 +- test/CodeGen/AMDGPU/scalar_to_vector.ll | 21 +- test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll | 17 +- test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll | 14 +- test/CodeGen/AMDGPU/schedule-fs-loop.ll | 14 +- test/CodeGen/AMDGPU/schedule-global-loads.ll | 10 +- test/CodeGen/AMDGPU/schedule-if-2.ll | 4 +- test/CodeGen/AMDGPU/schedule-if.ll | 4 +- test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll | 17 +- .../AMDGPU/schedule-vs-if-nested-loop-failure.ll | 51 +- test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll | 10 +- test/CodeGen/AMDGPU/scratch-buffer.ll | 22 +- test/CodeGen/AMDGPU/sdiv.ll | 60 +- test/CodeGen/AMDGPU/sdivrem24.ll | 124 +- test/CodeGen/AMDGPU/sdivrem64.ll | 78 +- test/CodeGen/AMDGPU/select-i1.ll | 14 +- test/CodeGen/AMDGPU/select-vectors.ll | 81 +- test/CodeGen/AMDGPU/selected-stack-object.ll | 15 + test/CodeGen/AMDGPU/setcc-opt.ll | 117 +- test/CodeGen/AMDGPU/setcc.ll | 36 +- test/CodeGen/AMDGPU/setcc64.ll | 12 +- test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll | 22 + test/CodeGen/AMDGPU/sext-in-reg.ll | 39 +- test/CodeGen/AMDGPU/sgpr-control-flow.ll | 10 +- test/CodeGen/AMDGPU/sgpr-copy.ll | 454 +- test/CodeGen/AMDGPU/shared-op-cycle.ll | 13 +- test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll | 118 + test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll | 386 + test/CodeGen/AMDGPU/shift-i64-opts.ll | 245 + test/CodeGen/AMDGPU/shl.ll | 171 +- test/CodeGen/AMDGPU/shl_add_constant.ll | 16 +- test/CodeGen/AMDGPU/shl_add_ptr.ll | 38 +- test/CodeGen/AMDGPU/si-annotate-cf-assertion.ll | 25 - test/CodeGen/AMDGPU/si-annotate-cf.ll | 95 +- test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll | 24 + .../si-instr-info-correct-implicit-operands.ll | 8 +- test/CodeGen/AMDGPU/si-literal-folding.ll | 4 +- test/CodeGen/AMDGPU/si-lod-bias.ll | 60 +- .../si-lower-control-flow-unreachable-block.ll | 56 + test/CodeGen/AMDGPU/si-scheduler.ll | 61 +- test/CodeGen/AMDGPU/si-sgpr-spill.ll | 3040 +++--- test/CodeGen/AMDGPU/si-spill-cf.ll | 522 +- test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 60 + test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll | 74 +- test/CodeGen/AMDGPU/si-vector-hang.ll | 2 +- test/CodeGen/AMDGPU/sign_extend.ll | 144 +- test/CodeGen/AMDGPU/sint_to_fp.f64.ll | 18 +- test/CodeGen/AMDGPU/sint_to_fp.i64.ll | 15 +- test/CodeGen/AMDGPU/sint_to_fp.ll | 2 +- test/CodeGen/AMDGPU/skip-if-dead.ll | 390 + test/CodeGen/AMDGPU/smed3.ll | 449 + test/CodeGen/AMDGPU/sminmax.ll | 118 +- test/CodeGen/AMDGPU/smrd-vccz-bug.ll | 49 + test/CodeGen/AMDGPU/smrd.ll | 15 +- test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll | 8 +- test/CodeGen/AMDGPU/spill-scavenge-offset.ll | 21 +- test/CodeGen/AMDGPU/split-scalar-i64-add.ll | 4 +- test/CodeGen/AMDGPU/split-smrd.ll | 46 + .../AMDGPU/split-vector-memoperand-offsets.ll | 17 +- test/CodeGen/AMDGPU/sra.ll | 371 +- test/CodeGen/AMDGPU/store-barrier.ll | 17 +- test/CodeGen/AMDGPU/store-v3i64.ll | 121 +- test/CodeGen/AMDGPU/store.ll | 71 +- test/CodeGen/AMDGPU/structurize.ll | 2 +- test/CodeGen/AMDGPU/structurize1.ll | 2 +- test/CodeGen/AMDGPU/sub.ll | 24 +- test/CodeGen/AMDGPU/subreg-coalescer-crash.ll | 8 +- test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 18 +- test/CodeGen/AMDGPU/swizzle-export.ll | 21 +- test/CodeGen/AMDGPU/target-cpu.ll | 112 + test/CodeGen/AMDGPU/tex-clause-antidep.ll | 14 +- test/CodeGen/AMDGPU/texture-input-merge.ll | 16 +- test/CodeGen/AMDGPU/trap.ll | 15 + test/CodeGen/AMDGPU/trunc-bitcast-vector.ll | 92 + test/CodeGen/AMDGPU/trunc-cmp-constant.ll | 17 +- test/CodeGen/AMDGPU/trunc-store.ll | 34 +- test/CodeGen/AMDGPU/trunc.ll | 2 +- test/CodeGen/AMDGPU/udiv.ll | 56 +- test/CodeGen/AMDGPU/udivrem.ll | 72 +- test/CodeGen/AMDGPU/udivrem24.ll | 116 +- test/CodeGen/AMDGPU/udivrem64.ll | 18 +- test/CodeGen/AMDGPU/uint_to_fp.f64.ll | 18 +- test/CodeGen/AMDGPU/uint_to_fp.i64.ll | 2 +- test/CodeGen/AMDGPU/uint_to_fp.ll | 2 +- test/CodeGen/AMDGPU/umed3.ll | 484 + test/CodeGen/AMDGPU/unaligned-load-store.ll | 549 +- test/CodeGen/AMDGPU/undefined-subreg-liverange.ll | 90 + .../AMDGPU/unhandled-loop-condition-assertion.ll | 16 +- .../AMDGPU/uniform-branch-intrinsic-cond.ll | 27 + test/CodeGen/AMDGPU/uniform-cfg.ll | 439 + test/CodeGen/AMDGPU/uniform-crash.ll | 57 + .../AMDGPU/uniform-loop-inside-nonuniform.ll | 67 + test/CodeGen/AMDGPU/unknown-processor.ll | 20 + test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll | 42 +- test/CodeGen/AMDGPU/v_cndmask.ll | 6 +- test/CodeGen/AMDGPU/v_mac.ll | 99 +- test/CodeGen/AMDGPU/valu-i1.ll | 51 +- test/CodeGen/AMDGPU/vector-alloca.ll | 2 +- test/CodeGen/AMDGPU/vector-extract-insert.ll | 84 + .../vgpr-spill-emergency-stack-slot-compute.ll | 48 +- .../AMDGPU/vgpr-spill-emergency-stack-slot.ll | 26 +- test/CodeGen/AMDGPU/vi-removed-intrinsics.ll | 24 + test/CodeGen/AMDGPU/vop-shrink.ll | 10 +- test/CodeGen/AMDGPU/vselect.ll | 56 +- test/CodeGen/AMDGPU/wait.ll | 11 +- test/CodeGen/AMDGPU/waitcnt-flat.ll | 16 + test/CodeGen/AMDGPU/work-item-intrinsics.ll | 275 - test/CodeGen/AMDGPU/wqm.ll | 366 + .../AMDGPU/write-register-vgpr-into-sgpr.ll | 22 + test/CodeGen/AMDGPU/write_register.ll | 80 + test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll | 2 +- test/CodeGen/AMDGPU/xor.ll | 4 +- test/CodeGen/AMDGPU/zero_extend.ll | 4 +- test/CodeGen/AMDGPU/zext-i64-bit-operand.ll | 41 + test/CodeGen/ARM/2009-08-31-LSDA-Name.ll | 8 +- test/CodeGen/ARM/2009-10-16-Scope.ll | 5 +- test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll | 5 +- .../ARM/2010-06-25-Thumb2ITInvalidIterator.ll | 7 +- test/CodeGen/ARM/2010-08-04-StackVariable.ll | 20 +- test/CodeGen/ARM/2010-11-29-PrologueBug.ll | 25 +- test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 13 +- test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll | 2 +- test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll | 4 +- test/CodeGen/ARM/2011-04-26-SchedTweak.ll | 4 +- test/CodeGen/ARM/2011-06-09-TailCallByVal.ll | 2 +- test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 13 +- test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 2 +- .../ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll | 3 +- test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll | 192 + test/CodeGen/ARM/ARMLoadStoreDBG.mir | 164 + test/CodeGen/ARM/Windows/builtin_longjmp.ll | 15 + test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll | 2 +- test/CodeGen/ARM/Windows/chkstk.ll | 4 +- test/CodeGen/ARM/Windows/dbzchk.ll | 192 + test/CodeGen/ARM/Windows/division.ll | 23 +- test/CodeGen/ARM/Windows/dllexport.ll | 75 + test/CodeGen/ARM/Windows/long-calls.ll | 4 +- test/CodeGen/ARM/Windows/no-aeabi.ll | 2 +- test/CodeGen/ARM/Windows/overflow.ll | 77 - test/CodeGen/ARM/Windows/tls.ll | 157 + test/CodeGen/ARM/align.ll | 20 +- test/CodeGen/ARM/arm-and-tst-peephole.ll | 2 +- test/CodeGen/ARM/arm-eabi.ll | 8 + .../ARM/arm-interleaved-accesses-extract-user.ll | 86 + test/CodeGen/ARM/arm-interleaved-accesses.ll | 12 + test/CodeGen/ARM/arm-shrink-wrapping.ll | 4 +- test/CodeGen/ARM/atomic-64bit.ll | 186 +- test/CodeGen/ARM/atomic-op.ll | 111 +- test/CodeGen/ARM/atomic-ops-v8.ll | 76 +- test/CodeGen/ARM/bfx.ll | 16 + test/CodeGen/ARM/build-attributes-encoding.s | 11 +- test/CodeGen/ARM/build-attributes.ll | 203 +- test/CodeGen/ARM/byval_load_align.ll | 2 +- test/CodeGen/ARM/call-tc.ll | 18 +- test/CodeGen/ARM/call.ll | 2 +- test/CodeGen/ARM/carry.ll | 7 +- test/CodeGen/ARM/cdp.ll | 13 + test/CodeGen/ARM/cdp2.ll | 13 + test/CodeGen/ARM/cmpxchg-O0.ll | 113 + test/CodeGen/ARM/cmpxchg-idioms.ll | 65 +- test/CodeGen/ARM/cmpxchg-weak.ll | 6 +- test/CodeGen/ARM/coalesce-dbgvalue.ll | 5 +- test/CodeGen/ARM/code-placement.ll | 6 +- test/CodeGen/ARM/crash-greedy.ll | 2 +- test/CodeGen/ARM/cxx-tlscc.ll | 109 +- test/CodeGen/ARM/dagcombine-anyexttozeroext.ll | 38 +- test/CodeGen/ARM/darwin-tls.ll | 17 + test/CodeGen/ARM/debug-frame-vararg.ll | 5 +- test/CodeGen/ARM/debug-frame.ll | 5 +- test/CodeGen/ARM/debug-info-arg.ll | 5 +- test/CodeGen/ARM/debug-info-blocks.ll | 5 +- test/CodeGen/ARM/debug-info-branch-folding.ll | 9 +- test/CodeGen/ARM/debug-info-d16-reg.ll | 9 +- test/CodeGen/ARM/debug-info-no-frame.ll | 4 +- test/CodeGen/ARM/debug-info-qreg.ll | 9 +- test/CodeGen/ARM/debug-info-s16-reg.ll | 9 +- test/CodeGen/ARM/debug-info-sreg2.ll | 5 +- test/CodeGen/ARM/debug-segmented-stacks.ll | 5 +- test/CodeGen/ARM/debugtrap.ll | 2 +- test/CodeGen/ARM/default-float-abi.ll | 3 + test/CodeGen/ARM/default-reloc.ll | 5 + test/CodeGen/ARM/divmod-eabi.ll | 186 +- test/CodeGen/ARM/eh-resume-darwin.ll | 7 +- test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll | 4 +- test/CodeGen/ARM/ehabi-handlerdata.ll | 4 +- test/CodeGen/ARM/ehabi.ll | 16 + test/CodeGen/ARM/emutls.ll | 74 +- test/CodeGen/ARM/emutls_generic.ll | 18 +- test/CodeGen/ARM/fast-isel-call.ll | 26 +- test/CodeGen/ARM/fast-isel-deadcode.ll | 2 +- test/CodeGen/ARM/fast-isel-intrinsic.ll | 97 +- test/CodeGen/ARM/fast-isel-pie.ll | 19 + test/CodeGen/ARM/fast-isel.ll | 14 +- test/CodeGen/ARM/fast-tail-call.ll | 1 + test/CodeGen/ARM/fp16-promote.ll | 74 + test/CodeGen/ARM/fp16-v3.ll | 26 +- test/CodeGen/ARM/fp16.ll | 15 +- test/CodeGen/ARM/globals.ll | 12 +- test/CodeGen/ARM/half.ll | 8 +- test/CodeGen/ARM/hello.ll | 2 + test/CodeGen/ARM/ifcvt-iter-indbr.ll | 2 +- test/CodeGen/ARM/inlineasm-X-allocation.ll | 21 + test/CodeGen/ARM/inlineasm-X-constraint.ll | 157 + test/CodeGen/ARM/inlineasm-ldr-pseudo.ll | 4 +- test/CodeGen/ARM/inlineasm3.ll | 25 +- test/CodeGen/ARM/interrupt-attr.ll | 8 +- test/CodeGen/ARM/interval-update-remat.ll | 162 + test/CodeGen/ARM/intrinsics-coprocessor.ll | 79 + test/CodeGen/ARM/intrinsics.ll | 39 - test/CodeGen/ARM/invalidated-save-point.ll | 27 + test/CodeGen/ARM/ldc2l.ll | 11 + test/CodeGen/ARM/ldm-base-writeback.ll | 21 + test/CodeGen/ARM/ldr_frame.ll | 11 +- test/CodeGen/ARM/ldrd.ll | 52 +- test/CodeGen/ARM/ldstrex-m.ll | 2 + test/CodeGen/ARM/legalize-unaligned-load.ll | 2 +- test/CodeGen/ARM/litpool-licm.ll | 46 + test/CodeGen/ARM/local-call.ll | 20 + test/CodeGen/ARM/longMAC.ll | 29 + test/CodeGen/ARM/lsr-code-insertion.ll | 4 +- test/CodeGen/ARM/macho-frame-offset.ll | 12 + test/CodeGen/ARM/memcpy-no-inline.ll | 33 + test/CodeGen/ARM/memfunc.ll | 29 +- test/CodeGen/ARM/minsize-call-cse.ll | 28 + test/CodeGen/ARM/movt.ll | 6 +- test/CodeGen/ARM/msr-it-block.ll | 55 + test/CodeGen/ARM/none-macho.ll | 10 +- test/CodeGen/ARM/pic.ll | 4 +- test/CodeGen/ARM/pie.ll | 18 + test/CodeGen/ARM/plt-relative-reloc.ll | 16 + test/CodeGen/ARM/popcnt.ll | 16 + test/CodeGen/ARM/pr26669.ll | 31 + test/CodeGen/ARM/preferred-align.ll | 8 +- test/CodeGen/ARM/rem_crash.ll | 257 + test/CodeGen/ARM/returned-ext.ll | 32 +- test/CodeGen/ARM/sincos.ll | 18 + test/CodeGen/ARM/sjlj-prepare-critical-edge.ll | 4 +- .../ARM/sjljehprepare-lower-empty-struct.ll | 6 +- test/CodeGen/ARM/smul.ll | 111 +- test/CodeGen/ARM/smulw.ll | 26 - test/CodeGen/ARM/special-reg-v8m-base.ll | 142 + test/CodeGen/ARM/special-reg-v8m-main.ll | 214 + test/CodeGen/ARM/ssat.ll | 215 + test/CodeGen/ARM/static-addr-hoisting.ll | 22 + test/CodeGen/ARM/stc2.ll | 11 + test/CodeGen/ARM/struct_byval.ll | 31 +- test/CodeGen/ARM/swift-ios.ll | 68 + test/CodeGen/ARM/swift-return.ll | 133 + test/CodeGen/ARM/swift-vldm.ll | 1 + test/CodeGen/ARM/swifterror.ll | 381 + test/CodeGen/ARM/swiftself.ll | 65 + test/CodeGen/ARM/t2-shrink-ldrpost.ll | 52 + test/CodeGen/ARM/tail-call-builtin.ll | 37 + test/CodeGen/ARM/tail-call-weak.ll | 7 +- test/CodeGen/ARM/this-return.ll | 10 +- test/CodeGen/ARM/thread_pointer.ll | 4 +- test/CodeGen/ARM/thumb-alignment.ll | 6 +- test/CodeGen/ARM/thumb-stub.ll | 10 + test/CodeGen/ARM/thumb1-ldst-opt.ll | 2 +- test/CodeGen/ARM/thumb1-varalloc.ll | 12 +- test/CodeGen/ARM/thumb2-size-opt.ll | 16 + test/CodeGen/ARM/tls-models.ll | 4 +- test/CodeGen/ARM/tls3.ll | 2 +- test/CodeGen/ARM/trap.ll | 67 +- test/CodeGen/ARM/truncstore-dag-combine.ll | 10 +- test/CodeGen/ARM/twoaddrinstr.ll | 1 + test/CodeGen/ARM/urem-opt-size.ll | 45 + test/CodeGen/ARM/v7k-libcalls.ll | 9 + test/CodeGen/ARM/v7k-sincos.ll | 2 +- test/CodeGen/ARM/vcnt.ll | 78 + test/CodeGen/ARM/vcvt_combine.ll | 8 + test/CodeGen/ARM/vdiv_combine.ll | 8 + test/CodeGen/ARM/vfp-libcalls.ll | 2 +- test/CodeGen/ARM/vfp-regs-dwarf.ll | 5 +- test/CodeGen/ARM/vminmax.ll | 17 + test/CodeGen/ARM/warn-stack.ll | 2 +- test/CodeGen/ARM/wide-compares.ll | 52 + test/CodeGen/ARM/widen-vmovs.ll | 2 +- test/CodeGen/ARM/zero-cycle-zero.ll | 2 +- test/CodeGen/BPF/sdiv_error.ll | 9 + test/CodeGen/CPP/2007-06-16-Funcname.ll | 7 - test/CodeGen/CPP/2009-05-01-Long-Double.ll | 13 - test/CodeGen/CPP/2009-05-04-CondBr.ll | 28 - test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll | 6 - test/CodeGen/CPP/atomic.ll | 89 - test/CodeGen/CPP/attributes.ll | 7 - test/CodeGen/CPP/gep.ll | 10 - test/CodeGen/CPP/lit.local.cfg | 3 - test/CodeGen/Generic/MachineBranchProb.ll | 16 +- test/CodeGen/Generic/Makefile | 23 - .../CodeGen/Generic/dont-remove-empty-preheader.ll | 39 + test/CodeGen/Generic/run-pass.ll | 7 - test/CodeGen/Generic/stop-after.ll | 2 +- test/CodeGen/Generic/vector-redux.ll | 237 + test/CodeGen/Hexagon/Atomics.ll | 13 + test/CodeGen/Hexagon/absaddr-store.ll | 1 - test/CodeGen/Hexagon/adde.ll | 2 +- .../CodeGen/Hexagon/avoid-predspill-calleesaved.ll | 49 + test/CodeGen/Hexagon/avoid-predspill.ll | 42 + test/CodeGen/Hexagon/bit-extractu-half.ll | 13 + test/CodeGen/Hexagon/bitconvert-vector.ll | 27 + test/CodeGen/Hexagon/block-addr.ll | 2 +- test/CodeGen/Hexagon/block-ranges-nodef.ll | 55 + test/CodeGen/Hexagon/branch-non-mbb.ll | 46 + test/CodeGen/Hexagon/brev_ld.ll | 26 +- test/CodeGen/Hexagon/brev_st.ll | 19 +- test/CodeGen/Hexagon/builtin-prefetch-offset.ll | 28 + test/CodeGen/Hexagon/builtin-prefetch.ll | 29 + test/CodeGen/Hexagon/callr-dep-edge.ll | 20 + test/CodeGen/Hexagon/cext-check.ll | 2 +- test/CodeGen/Hexagon/cfi-late.ll | 5 +- test/CodeGen/Hexagon/cfi-offset.ll | 43 + test/CodeGen/Hexagon/circ-load-isel.ll | 18 + test/CodeGen/Hexagon/circ_ld.ll | 26 +- test/CodeGen/Hexagon/circ_st.ll | 20 +- test/CodeGen/Hexagon/clr_set_toggle.ll | 17 +- test/CodeGen/Hexagon/const64.ll | 18 + test/CodeGen/Hexagon/csr-func-usedef.ll | 72 + test/CodeGen/Hexagon/eliminate-pred-spill.ll | 144 + test/CodeGen/Hexagon/expand-condsets-pred-undef.ll | 22 + test/CodeGen/Hexagon/extload-combine.ll | 2 +- test/CodeGen/Hexagon/gp-plus-offset-load.ll | 4 +- test/CodeGen/Hexagon/hwloop-dbg.ll | 5 +- test/CodeGen/Hexagon/ifcvt-diamond-bad.ll | 43 + test/CodeGen/Hexagon/inline-asm-qv.ll | 19 + test/CodeGen/Hexagon/insert4.ll | 112 + test/CodeGen/Hexagon/intrinsics/system_user.ll | 13 + test/CodeGen/Hexagon/memops-stack.ll | 147 + test/CodeGen/Hexagon/memops.ll | 126 + test/CodeGen/Hexagon/misched-top-rptracker-sync.ll | 151 + test/CodeGen/Hexagon/newvaluestore.ll | 21 +- test/CodeGen/Hexagon/opt-addr-mode.ll | 107 + test/CodeGen/Hexagon/packetize-tailcall-arg.ll | 22 + test/CodeGen/Hexagon/peephole-op-swap.ll | 30 + test/CodeGen/Hexagon/pic-local.ll | 19 + test/CodeGen/Hexagon/pic-regusage.ll | 69 + test/CodeGen/Hexagon/rdf-copy-undef2.ll | 55 + test/CodeGen/Hexagon/rdf-copy.ll | 2 +- test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll | 37 + test/CodeGen/Hexagon/rdf-inline-asm.ll | 36 + test/CodeGen/Hexagon/rdf-reset-kills.ll | 28 + test/CodeGen/Hexagon/reg-scavengebug-3.ll | 80 + test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll | 100 + test/CodeGen/Hexagon/restore-single-reg.ll | 42 + test/CodeGen/Hexagon/ret-struct-by-val.ll | 18 + test/CodeGen/Hexagon/runtime-stkchk.ll | 44 + test/CodeGen/Hexagon/sdata-array.ll | 13 + test/CodeGen/Hexagon/sdata-basic.ll | 16 + test/CodeGen/Hexagon/section_7275.ll | 54 + test/CodeGen/Hexagon/select-instr-align.ll | 31 + test/CodeGen/Hexagon/static.ll | 8 +- test/CodeGen/Hexagon/store-shift.ll | 50 + test/CodeGen/Hexagon/storerinewabs.ll | 17 + test/CodeGen/Hexagon/struct_args_large.ll | 2 +- test/CodeGen/Hexagon/sube.ll | 4 +- test/CodeGen/Hexagon/tail-dup-subreg-map.ll | 67 + test/CodeGen/Hexagon/tls_pic.ll | 37 + test/CodeGen/Hexagon/tls_static.ll | 28 + test/CodeGen/Hexagon/v60-cur.ll | 62 + test/CodeGen/Hexagon/v60Intrins.ll | 2 +- test/CodeGen/Hexagon/vec-pred-spill1.ll | 80 + test/CodeGen/Hexagon/vector-align.ll | 38 + test/CodeGen/Hexagon/vload-postinc-sel.ll | 52 + test/CodeGen/Hexagon/vselect-pseudo.ll | 33 + test/CodeGen/Hexagon/vsplat-isel.ll | 10 + test/CodeGen/Hexagon/zextloadi1.ll | 21 +- test/CodeGen/Inputs/DbgValueOtherTargets.ll | 5 +- test/CodeGen/Lanai/codemodel.ll | 30 + test/CodeGen/Lanai/comparisons_i32.ll | 96 + test/CodeGen/Lanai/comparisons_i64.ll | 108 + test/CodeGen/Lanai/constant_multiply.ll | 107 + test/CodeGen/Lanai/delay_filler.ll | 41 + test/CodeGen/Lanai/i32.ll | 145 + .../Lanai/lanai-misched-trivial-disjoint.ll | 55 + test/CodeGen/Lanai/lit.local.cfg | 3 + test/CodeGen/Lanai/mem_alu_combiner.ll | 35 + test/CodeGen/Lanai/multiply.ll | 60 + test/CodeGen/Lanai/rshift64.ll | 12 + test/CodeGen/Lanai/select.ll | 41 + test/CodeGen/Lanai/set_and_hi.ll | 15 + test/CodeGen/Lanai/shift.ll | 28 + test/CodeGen/Lanai/stack-frame.ll | 14 + test/CodeGen/Lanai/sub-cmp-peephole.ll | 109 + test/CodeGen/Lanai/subword.ll | 29 + test/CodeGen/MIR/AArch64/cfi-def-cfa.mir | 2 +- .../MIR/AArch64/expected-target-flag-name.mir | 2 +- .../AArch64/generic-virtual-registers-error.mir | 43 + .../MIR/AArch64/invalid-target-flag-name.mir | 2 +- test/CodeGen/MIR/AArch64/machine-dead-copy.mir | 71 + test/CodeGen/MIR/AArch64/machine-scheduler.mir | 35 + test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir | 2 +- .../MIR/AArch64/stack-object-local-offset.mir | 4 +- test/CodeGen/MIR/AArch64/target-flags.mir | 2 +- .../MIR/AMDGPU/expected-target-index-name.mir | 2 +- .../MIR/AMDGPU/invalid-target-index-operand.mir | 2 +- test/CodeGen/MIR/AMDGPU/target-index-operands.mir | 2 +- test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir | 165 - test/CodeGen/MIR/ARM/bundled-instructions.mir | 2 +- test/CodeGen/MIR/ARM/cfi-same-value.mir | 2 +- test/CodeGen/MIR/ARM/expected-closing-brace.mir | 2 +- .../MIR/ARM/extraneous-closing-brace-error.mir | 2 +- test/CodeGen/MIR/ARM/imm-peephole-arm.mir | 60 + test/CodeGen/MIR/ARM/imm-peephole-thumb.mir | 59 + .../MIR/ARM/nested-instruction-bundle-error.mir | 2 +- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir | 65 +- test/CodeGen/MIR/Generic/basic-blocks.mir | 2 +- .../Generic/expected-colon-after-basic-block.mir | 2 +- .../expected-mbb-reference-for-successor-mbb.mir | 2 +- test/CodeGen/MIR/Generic/frame-info.mir | 2 +- .../Generic/function-missing-machine-function.mir | 2 +- .../MIR/Generic/invalid-jump-table-kind.mir | 2 +- .../CodeGen/MIR/Generic/llvm-ir-error-reported.mir | 2 +- test/CodeGen/MIR/Generic/llvmIR.mir | 2 +- test/CodeGen/MIR/Generic/llvmIRMissing.mir | 2 +- .../machine-basic-block-ir-block-reference.mir | 2 +- .../machine-basic-block-redefinition-error.mir | 2 +- .../machine-basic-block-undefined-ir-block.mir | 2 +- .../Generic/machine-basic-block-unknown-name.mir | 2 +- .../machine-function-missing-body-error.mir | 2 +- .../Generic/machine-function-missing-function.mir | 2 +- .../MIR/Generic/machine-function-missing-name.mir | 2 +- .../machine-function-redefinition-error.mir | 2 +- test/CodeGen/MIR/Generic/machine-function.mir | 2 +- test/CodeGen/MIR/Generic/multiRunPass.mir | 20 + test/CodeGen/MIR/Generic/register-info.mir | 2 +- test/CodeGen/MIR/Hexagon/anti-dep-partial.mir | 35 + test/CodeGen/MIR/Hexagon/lit.local.cfg | 2 + test/CodeGen/MIR/Lanai/lit.local.cfg | 2 + test/CodeGen/MIR/Lanai/peephole-compare.mir | 714 ++ ...ted-global-value-or-symbol-after-call-entry.mir | 2 +- test/CodeGen/MIR/Mips/memory-operands.mir | 14 +- .../MIR/NVPTX/expected-floating-point-literal.mir | 2 +- .../NVPTX/floating-point-immediate-operands.mir | 2 +- .../NVPTX/floating-point-invalid-type-error.mir | 2 +- .../MIR/PowerPC/unordered-implicit-registers.mir | 2 +- test/CodeGen/MIR/X86/basic-block-liveins.mir | 2 +- .../X86/basic-block-not-at-start-of-line-error.mir | 2 +- test/CodeGen/MIR/X86/block-address-operands.mir | 2 +- test/CodeGen/MIR/X86/callee-saved-info.mir | 2 +- test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir | 2 +- test/CodeGen/MIR/X86/cfi-def-cfa-register.mir | 2 +- test/CodeGen/MIR/X86/cfi-offset.mir | 2 +- .../X86/constant-pool-item-redefinition-error.mir | 2 +- test/CodeGen/MIR/X86/constant-pool.mir | 2 +- test/CodeGen/MIR/X86/constant-value-error.mir | 2 +- test/CodeGen/MIR/X86/dead-register-flag.mir | 2 +- .../MIR/X86/def-register-already-tied-error.mir | 2 +- .../MIR/X86/duplicate-memory-operand-flag.mir | 2 +- .../MIR/X86/duplicate-register-flag-error.mir | 2 +- .../MIR/X86/early-clobber-register-flag.mir | 2 +- .../MIR/X86/expected-align-in-memory-operand.mir | 2 +- ...ted-alignment-after-align-in-memory-operand.mir | 2 +- .../X86/expected-basic-block-at-start-of-body.mir | 2 +- .../expected-block-reference-in-blockaddress.mir | 2 +- .../MIR/X86/expected-comma-after-cfi-register.mir | 2 +- .../X86/expected-comma-after-memory-operand.mir | 2 +- .../X86/expected-different-implicit-operand.mir | 2 +- .../expected-different-implicit-register-flag.mir | 2 +- .../MIR/X86/expected-from-in-memory-operand.mir | 24 - ...ected-function-reference-after-blockaddress.mir | 2 +- .../expected-global-value-after-blockaddress.mir | 2 +- .../MIR/X86/expected-integer-after-offset-sign.mir | 2 +- .../MIR/X86/expected-integer-after-tied-def.mir | 2 +- .../X86/expected-integer-in-successor-weight.mir | 2 +- .../expected-load-or-store-in-memory-operand.mir | 2 +- test/CodeGen/MIR/X86/expected-machine-operand.mir | 2 +- ...expected-metadata-node-after-debug-location.mir | 7 +- .../X86/expected-metadata-node-after-exclaim.mir | 7 +- .../X86/expected-metadata-node-in-stack-object.mir | 2 +- .../expected-named-register-in-allocation-hint.mir | 2 +- ...ted-named-register-in-callee-saved-register.mir | 2 +- ...expected-named-register-in-functions-livein.mir | 2 +- .../MIR/X86/expected-named-register-livein.mir | 2 +- .../MIR/X86/expected-newline-at-end-of-list.mir | 2 +- test/CodeGen/MIR/X86/expected-number-after-bb.mir | 2 +- .../MIR/X86/expected-offset-after-cfi-operand.mir | 2 +- .../expected-pointer-value-in-memory-operand.mir | 2 +- .../expected-positive-alignment-after-align.mir | 2 +- .../X86/expected-register-after-cfi-operand.mir | 2 +- .../MIR/X86/expected-register-after-flags.mir | 2 +- ...xpected-size-integer-after-memory-operation.mir | 2 +- test/CodeGen/MIR/X86/expected-stack-object.mir | 2 +- .../MIR/X86/expected-subregister-after-colon.mir | 2 +- test/CodeGen/MIR/X86/expected-target-flag-name.mir | 2 +- .../MIR/X86/expected-tied-def-after-lparen.mir | 2 +- .../MIR/X86/expected-value-in-memory-operand.mir | 2 +- ...pected-virtual-register-in-functions-livein.mir | 2 +- test/CodeGen/MIR/X86/external-symbol-operands.mir | 2 +- .../MIR/X86/fixed-stack-memory-operands.mir | 2 +- .../X86/fixed-stack-object-redefinition-error.mir | 2 +- test/CodeGen/MIR/X86/fixed-stack-objects.mir | 2 +- .../MIR/X86/frame-info-save-restore-points.mir | 2 +- .../MIR/X86/frame-info-stack-references.mir | 2 +- .../MIR/X86/frame-setup-instruction-flag.mir | 2 +- test/CodeGen/MIR/X86/function-liveins.mir | 2 +- test/CodeGen/MIR/X86/generic-instr-type-error.mir | 15 + test/CodeGen/MIR/X86/generic-virtual-registers.mir | 48 + test/CodeGen/MIR/X86/global-value-operands.mir | 2 +- test/CodeGen/MIR/X86/immediate-operands.mir | 2 +- test/CodeGen/MIR/X86/implicit-register-flag.mir | 2 +- test/CodeGen/MIR/X86/inline-asm-registers.mir | 2 +- .../MIR/X86/instructions-debug-location.mir | 19 +- .../CodeGen/MIR/X86/invalid-constant-pool-item.mir | 2 +- .../CodeGen/MIR/X86/invalid-metadata-node-type.mir | 8 +- test/CodeGen/MIR/X86/invalid-target-flag-name.mir | 2 +- .../MIR/X86/invalid-tied-def-index-error.mir | 2 +- test/CodeGen/MIR/X86/jump-table-info.mir | 4 +- .../MIR/X86/jump-table-redefinition-error.mir | 2 +- test/CodeGen/MIR/X86/killed-register-flag.mir | 2 +- .../MIR/X86/large-cfi-offset-number-error.mir | 2 +- .../MIR/X86/large-immediate-operand-error.mir | 2 +- test/CodeGen/MIR/X86/large-index-number-error.mir | 2 +- test/CodeGen/MIR/X86/large-offset-number-error.mir | 2 +- .../MIR/X86/large-size-in-memory-operand-error.mir | 2 +- test/CodeGen/MIR/X86/liveout-register-mask.mir | 2 +- .../MIR/X86/machine-basic-block-operands.mir | 2 +- test/CodeGen/MIR/X86/machine-instructions.mir | 2 +- test/CodeGen/MIR/X86/machine-verifier.mir | 2 +- test/CodeGen/MIR/X86/memory-operands.mir | 30 +- test/CodeGen/MIR/X86/metadata-operands.mir | 9 +- test/CodeGen/MIR/X86/missing-closing-quote.mir | 2 +- test/CodeGen/MIR/X86/missing-comma.mir | 2 +- test/CodeGen/MIR/X86/missing-implicit-operand.mir | 2 +- test/CodeGen/MIR/X86/named-registers.mir | 2 +- test/CodeGen/MIR/X86/newline-handling.mir | 2 +- test/CodeGen/MIR/X86/null-register-operands.mir | 2 +- test/CodeGen/MIR/X86/register-mask-operands.mir | 2 +- .../X86/register-operands-target-flag-error.mir | 2 +- .../MIR/X86/simple-register-allocation-hints.mir | 2 +- .../X86/spill-slot-fixed-stack-object-aliased.mir | 2 +- .../spill-slot-fixed-stack-object-immutable.mir | 2 +- .../MIR/X86/spill-slot-fixed-stack-objects.mir | 2 +- test/CodeGen/MIR/X86/stack-object-debug-info.mir | 13 +- test/CodeGen/MIR/X86/stack-object-invalid-name.mir | 2 +- .../stack-object-operand-name-mismatch-error.mir | 2 +- test/CodeGen/MIR/X86/stack-object-operands.mir | 2 +- .../MIR/X86/stack-object-redefinition-error.mir | 2 +- test/CodeGen/MIR/X86/stack-objects.mir | 2 +- test/CodeGen/MIR/X86/standalone-register-error.mir | 2 +- test/CodeGen/MIR/X86/subreg-on-physreg.mir | 12 + .../CodeGen/MIR/X86/subregister-index-operands.mir | 32 + test/CodeGen/MIR/X86/subregister-operands.mir | 2 +- .../MIR/X86/successor-basic-blocks-weights.mir | 2 +- test/CodeGen/MIR/X86/successor-basic-blocks.mir | 2 +- test/CodeGen/MIR/X86/tied-def-operand-invalid.mir | 2 +- test/CodeGen/MIR/X86/undef-register-flag.mir | 2 +- .../MIR/X86/undefined-fixed-stack-object.mir | 2 +- test/CodeGen/MIR/X86/undefined-global-value.mir | 2 +- .../MIR/X86/undefined-ir-block-in-blockaddress.mir | 2 +- .../undefined-ir-block-slot-in-blockaddress.mir | 2 +- test/CodeGen/MIR/X86/undefined-jump-table-id.mir | 2 +- .../MIR/X86/undefined-named-global-value.mir | 2 +- test/CodeGen/MIR/X86/undefined-register-class.mir | 4 +- test/CodeGen/MIR/X86/undefined-stack-object.mir | 2 +- .../MIR/X86/undefined-value-in-memory-operand.mir | 2 +- .../CodeGen/MIR/X86/undefined-virtual-register.mir | 2 +- test/CodeGen/MIR/X86/unknown-instruction.mir | 2 +- .../MIR/X86/unknown-machine-basic-block.mir | 2 +- test/CodeGen/MIR/X86/unknown-metadata-keyword.mir | 2 +- test/CodeGen/MIR/X86/unknown-metadata-node.mir | 7 +- .../MIR/X86/unknown-named-machine-basic-block.mir | 2 +- test/CodeGen/MIR/X86/unknown-register.mir | 2 +- .../MIR/X86/unknown-subregister-index-op.mir | 26 + test/CodeGen/MIR/X86/unknown-subregister-index.mir | 2 +- test/CodeGen/MIR/X86/unrecognized-character.mir | 2 +- .../MIR/X86/used-physical-register-info.mir | 2 +- .../X86/variable-sized-stack-object-size-error.mir | 2 +- .../MIR/X86/variable-sized-stack-objects.mir | 2 +- .../X86/virtual-register-redefinition-error.mir | 2 +- test/CodeGen/MIR/X86/virtual-registers.mir | 2 +- test/CodeGen/MIR/lit.local.cfg | 2 - test/CodeGen/MSP430/spill-to-stack.ll | 40 + test/CodeGen/Mips/2010-07-20-Switch.ll | 6 +- test/CodeGen/Mips/Fast-ISel/callabi.ll | 12 +- .../CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll | 14 +- test/CodeGen/Mips/Fast-ISel/div1.ll | 4 +- test/CodeGen/Mips/Fast-ISel/fastalloca.ll | 2 +- test/CodeGen/Mips/Fast-ISel/fpcmpa.ll | 4 +- test/CodeGen/Mips/Fast-ISel/memtest1.ll | 4 +- test/CodeGen/Mips/Fast-ISel/rem1.ll | 4 +- test/CodeGen/Mips/Fast-ISel/shift.ll | 2 +- test/CodeGen/Mips/abicalls.ll | 8 +- test/CodeGen/Mips/adjust-callstack-sp.ll | 12 +- test/CodeGen/Mips/alloca.ll | 2 +- test/CodeGen/Mips/analyzebranch.ll | 19 +- test/CodeGen/Mips/assertzext-trunc.ll | 62 + test/CodeGen/Mips/atomic.ll | 251 +- test/CodeGen/Mips/atomicCmpSwapPW.ll | 17 + test/CodeGen/Mips/biggot.ll | 4 +- test/CodeGen/Mips/brdelayslot.ll | 19 +- test/CodeGen/Mips/brsize3.ll | 10 +- test/CodeGen/Mips/buildpairextractelementf64.ll | 12 +- test/CodeGen/Mips/call-optimization.ll | 4 +- test/CodeGen/Mips/cannot-copy-registers.ll | 24 + test/CodeGen/Mips/cconv/arguments-float.ll | 16 +- test/CodeGen/Mips/cconv/arguments-fp128.ll | 8 +- .../Mips/cconv/arguments-hard-float-varargs.ll | 16 +- test/CodeGen/Mips/cconv/arguments-hard-float.ll | 16 +- test/CodeGen/Mips/cconv/arguments-hard-fp128.ll | 8 +- ...rguments-small-structures-bigger-than-32bits.ll | 8 +- test/CodeGen/Mips/cconv/arguments-struct.ll | 16 +- test/CodeGen/Mips/cconv/arguments-varargs.ll | 16 +- test/CodeGen/Mips/cconv/arguments.ll | 16 +- test/CodeGen/Mips/cconv/callee-saved-float.ll | 37 +- test/CodeGen/Mips/cconv/callee-saved-fpxx.ll | 16 +- test/CodeGen/Mips/cconv/callee-saved.ll | 32 +- test/CodeGen/Mips/cconv/memory-layout.ll | 54 +- test/CodeGen/Mips/cconv/reserved-space.ll | 16 +- test/CodeGen/Mips/cconv/return-float.ll | 16 +- test/CodeGen/Mips/cconv/return-hard-float.ll | 20 +- test/CodeGen/Mips/cconv/return-hard-fp128.ll | 8 +- test/CodeGen/Mips/cconv/return-hard-struct-f128.ll | 8 +- test/CodeGen/Mips/cconv/return-struct.ll | 19 +- test/CodeGen/Mips/cconv/return.ll | 16 +- test/CodeGen/Mips/cconv/roundl-call.ll | 40 + test/CodeGen/Mips/cconv/stack-alignment.ll | 16 +- test/CodeGen/Mips/cfi_offset.ll | 12 +- test/CodeGen/Mips/check-adde-redundant-moves.ll | 18 +- test/CodeGen/Mips/cmov.ll | 24 +- .../beqc-bnec-register-constraint.ll | 55 + .../Mips/compactbranches/compact-branch-policy.ll | 28 + .../Mips/compactbranches/compact-branches.ll | 206 + .../CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll | 53 + test/CodeGen/Mips/const-mult.ll | 4 +- test/CodeGen/Mips/const4a.ll | 2 +- test/CodeGen/Mips/const6.ll | 4 +- test/CodeGen/Mips/const6a.ll | 2 +- test/CodeGen/Mips/countleading.ll | 21 +- test/CodeGen/Mips/cstmaterialization/stack.ll | 54 + test/CodeGen/Mips/divrem.ll | 68 +- test/CodeGen/Mips/dsp-r1.ll | 3 +- test/CodeGen/Mips/dynamic-stack-realignment.ll | 36 +- test/CodeGen/Mips/eh-dwarf-cfa.ll | 14 +- test/CodeGen/Mips/eh-return32.ll | 6 +- test/CodeGen/Mips/eh-return64.ll | 8 +- test/CodeGen/Mips/eh.ll | 2 +- test/CodeGen/Mips/ehframe-indirect.ll | 18 +- test/CodeGen/Mips/elf_eflags.ll | 12 +- test/CodeGen/Mips/emergency-spill-slot-near-fp.ll | 2 +- test/CodeGen/Mips/emutls_generic.ll | 6 +- test/CodeGen/Mips/fastcc.ll | 8 +- test/CodeGen/Mips/fcmp.ll | 403 +- test/CodeGen/Mips/fcopysign-f32-f64.ll | 38 +- test/CodeGen/Mips/fcopysign.ll | 2 +- test/CodeGen/Mips/fmadd1.ll | 24 +- test/CodeGen/Mips/fp-indexed-ls.ll | 14 +- test/CodeGen/Mips/fp-spill-reload.ll | 2 +- test/CodeGen/Mips/fp16-promote.ll | 2 +- test/CodeGen/Mips/fp64a.ll | 12 +- test/CodeGen/Mips/fpbr.ll | 30 +- test/CodeGen/Mips/fpxx.ll | 20 +- test/CodeGen/Mips/gpreg-lazy-binding.ll | 2 +- test/CodeGen/Mips/hf16call32.ll | 8 +- test/CodeGen/Mips/hf16call32_body.ll | 36 +- test/CodeGen/Mips/hf1_body.ll | 27 +- test/CodeGen/Mips/i64arg.ll | 2 +- test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll | 36 + test/CodeGen/Mips/inlineasm-operand-code.ll | 57 +- test/CodeGen/Mips/inlineasm_constraint.ll | 4 +- test/CodeGen/Mips/inlineasm_constraint_R.ll | 2 +- test/CodeGen/Mips/inlineasm_constraint_ZC.ll | 6 +- test/CodeGen/Mips/inlineasm_constraint_m.ll | 2 +- test/CodeGen/Mips/inlineasmmemop.ll | 2 +- test/CodeGen/Mips/internalfunc.ll | 2 +- test/CodeGen/Mips/interrupt-attr-64-error.ll | 2 +- test/CodeGen/Mips/largeimm1.ll | 12 +- test/CodeGen/Mips/largeimmprinting.ll | 34 +- test/CodeGen/Mips/lazy-binding.ll | 2 +- test/CodeGen/Mips/lcb5.ll | 2 +- test/CodeGen/Mips/llvm-ir/add.ll | 359 +- test/CodeGen/Mips/llvm-ir/and.ll | 633 +- test/CodeGen/Mips/llvm-ir/ashr.ll | 105 +- test/CodeGen/Mips/llvm-ir/call.ll | 67 +- test/CodeGen/Mips/llvm-ir/indirectbr.ll | 27 +- test/CodeGen/Mips/llvm-ir/lh_lhu.ll | 32 + test/CodeGen/Mips/llvm-ir/load-atomic.ll | 4 +- test/CodeGen/Mips/llvm-ir/lshr.ll | 102 +- test/CodeGen/Mips/llvm-ir/mul.ll | 110 +- test/CodeGen/Mips/llvm-ir/not.ll | 239 + test/CodeGen/Mips/llvm-ir/or.ll | 648 +- test/CodeGen/Mips/llvm-ir/ret.ll | 32 +- test/CodeGen/Mips/llvm-ir/sdiv.ll | 115 +- test/CodeGen/Mips/llvm-ir/select-dbl.ll | 358 + test/CodeGen/Mips/llvm-ir/select-flt.ll | 335 + test/CodeGen/Mips/llvm-ir/select-int.ll | 270 + test/CodeGen/Mips/llvm-ir/select.ll | 712 -- test/CodeGen/Mips/llvm-ir/shl.ll | 102 +- test/CodeGen/Mips/llvm-ir/srem.ll | 112 +- test/CodeGen/Mips/llvm-ir/store-atomic.ll | 4 +- test/CodeGen/Mips/llvm-ir/sub.ll | 108 +- test/CodeGen/Mips/llvm-ir/udiv.ll | 97 +- test/CodeGen/Mips/llvm-ir/urem.ll | 126 +- test/CodeGen/Mips/llvm-ir/xor.ll | 164 +- test/CodeGen/Mips/load-store-left-right.ll | 28 +- test/CodeGen/Mips/longbranch.ll | 27 +- test/CodeGen/Mips/lw16-base-reg.ll | 26 + test/CodeGen/Mips/madd-msub.ll | 12 +- test/CodeGen/Mips/micromips-addiu.ll | 2 +- test/CodeGen/Mips/micromips-atomic1.ll | 3 +- test/CodeGen/Mips/micromips-delay-slot.ll | 4 + test/CodeGen/Mips/micromips-lwc1-swc1.ll | 50 + test/CodeGen/Mips/micromips-or16.ll | 29 +- test/CodeGen/Mips/micromips-shift.ll | 2 + test/CodeGen/Mips/micromips-zero-mat-uses.ll | 8 - test/CodeGen/Mips/mips-shf-gprel.s | 27 + test/CodeGen/Mips/mips16fpe.ll | 3 +- test/CodeGen/Mips/mips64-f128.ll | 59 +- test/CodeGen/Mips/mips64extins.ll | 12 +- test/CodeGen/Mips/mips64fpldst.ll | 36 +- test/CodeGen/Mips/mips64instrs.ll | 8 +- test/CodeGen/Mips/mips64intldst.ll | 8 +- test/CodeGen/Mips/mips64muldiv.ll | 8 +- test/CodeGen/Mips/mips64r6/compatibility.ll | 4 +- test/CodeGen/Mips/mips64shift.ll | 29 +- test/CodeGen/Mips/mno-ldc1-sdc1.ll | 133 +- test/CodeGen/Mips/msa/2r.ll | 4 +- test/CodeGen/Mips/msa/2r_vector_scalar.ll | 18 +- test/CodeGen/Mips/msa/2rf.ll | 4 +- test/CodeGen/Mips/msa/2rf_float_int.ll | 4 +- test/CodeGen/Mips/msa/2rf_int_float.ll | 4 +- test/CodeGen/Mips/msa/3r-a.ll | 4 +- test/CodeGen/Mips/msa/3r-b.ll | 4 +- test/CodeGen/Mips/msa/3r-s.ll | 4 +- test/CodeGen/Mips/msa/3r_splat.ll | 4 +- test/CodeGen/Mips/msa/basic_operations.ll | 24 +- test/CodeGen/Mips/msa/basic_operations_float.ll | 12 +- test/CodeGen/Mips/msa/elm_copy.ll | 16 +- test/CodeGen/Mips/msa/elm_cxcmsa.ll | 4 +- test/CodeGen/Mips/msa/elm_insv.ll | 16 +- test/CodeGen/Mips/msa/frameindex.ll | 4 +- test/CodeGen/Mips/msa/i5-b.ll | 4 +- test/CodeGen/Mips/msa/i8.ll | 4 +- test/CodeGen/Mips/msa/vec.ll | 4 +- test/CodeGen/Mips/nacl-align.ll | 14 +- test/CodeGen/Mips/no-odd-spreg-msa.ll | 8 +- test/CodeGen/Mips/no-odd-spreg.ll | 10 +- test/CodeGen/Mips/o32_cc.ll | 7 +- test/CodeGen/Mips/o32_cc_byval.ll | 2 +- test/CodeGen/Mips/octeon.ll | 4 +- test/CodeGen/Mips/octeon_popcnt.ll | 2 +- test/CodeGen/Mips/optimize-pic-o0.ll | 2 +- test/CodeGen/Mips/prevent-hoisting.ll | 8 +- test/CodeGen/Mips/private-addr.ll | 14 + test/CodeGen/Mips/private.ll | 2 +- test/CodeGen/Mips/return-vector.ll | 2 +- test/CodeGen/Mips/rotate.ll | 10 + test/CodeGen/Mips/select.ll | 12 +- test/CodeGen/Mips/selectcc.ll | 8 +- test/CodeGen/Mips/selectiondag-optlevel.ll | 22 + test/CodeGen/Mips/stackcoloring.ll | 2 +- test/CodeGen/Mips/start-asm-file.ll | 24 +- test/CodeGen/Mips/stchar.ll | 50 - test/CodeGen/Mips/stldst.ll | 8 +- test/CodeGen/Mips/tailcall.ll | 15 +- test/CodeGen/Mips/thread-pointer.ll | 12 + test/CodeGen/Mips/tls-models.ll | 2 +- test/CodeGen/Mips/tls.ll | 8 +- test/CodeGen/Mips/unalignedload.ll | 12 +- test/CodeGen/Mips/zeroreg.ll | 14 +- test/CodeGen/NVPTX/MachineSink-call.ll | 23 + test/CodeGen/NVPTX/MachineSink-convergent.ll | 23 + test/CodeGen/NVPTX/TailDuplication-convergent.ll | 45 + test/CodeGen/NVPTX/access-non-generic.ll | 91 +- test/CodeGen/NVPTX/alias.ll | 7 + test/CodeGen/NVPTX/arithmetic-int.ll | 24 + test/CodeGen/NVPTX/bug22322.ll | 12 +- test/CodeGen/NVPTX/bug26185-2.ll | 34 + test/CodeGen/NVPTX/bug26185.ll | 57 + test/CodeGen/NVPTX/convergent-mir-call.ll | 27 + test/CodeGen/NVPTX/debug-file-loc.ll | 43 + test/CodeGen/NVPTX/disable-opt.ll | 12 + test/CodeGen/NVPTX/global-ctor-empty.ll | 5 + test/CodeGen/NVPTX/global-ctor.ll | 9 + test/CodeGen/NVPTX/global-dtor.ll | 9 + test/CodeGen/NVPTX/global-visibility.ll | 16 + test/CodeGen/NVPTX/intrinsic-old.ll | 211 +- test/CodeGen/NVPTX/noduplicate-syncthreads.ll | 8 +- test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll | 13 + test/CodeGen/NVPTX/shfl.ll | 90 + test/CodeGen/NVPTX/sm-version-60.ll | 5 + test/CodeGen/NVPTX/sm-version-61.ll | 5 + test/CodeGen/NVPTX/sm-version-62.ll | 5 + .../speculative-execution-divergent-target.ll | 24 + test/CodeGen/NVPTX/zeroext-32bit.ll | 26 + .../PowerPC/2007-09-07-LoadStoreIdxForms.ll | 21 +- test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll | 2 +- test/CodeGen/PowerPC/2008-07-15-Bswap.ll | 5 - test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll | 2 +- test/CodeGen/PowerPC/2012-11-16-mischedcall.ll | 8 +- test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll | 43 + test/CodeGen/PowerPC/2016-04-17-combine.ll | 26 + test/CodeGen/PowerPC/2016-04-28-setjmp.ll | 48 + test/CodeGen/PowerPC/BreakableToken-reduced.ll | 2 +- test/CodeGen/PowerPC/aantidep-def-ec.mir | 1 + test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 1 + .../PowerPC/aggressive-anti-dep-breaker-subreg.ll | 24 + test/CodeGen/PowerPC/align.ll | 20 +- test/CodeGen/PowerPC/andc.ll | 36 + test/CodeGen/PowerPC/asm-constraints.ll | 62 +- .../PowerPC/asm-printer-topological-order.ll | 15 + test/CodeGen/PowerPC/atomics-fences.ll | 4 +- test/CodeGen/PowerPC/available-externally.ll | 81 +- test/CodeGen/PowerPC/bdzlr.ll | 3 +- test/CodeGen/PowerPC/builtins-ppc-p8vector.ll | 52 +- .../CodeGen/PowerPC/cannonicalize-vector-shifts.ll | 27 + test/CodeGen/PowerPC/code-align.ll | 60 +- .../PowerPC/combine-to-pre-index-store-crash.ll | 25 + test/CodeGen/PowerPC/crsave.ll | 20 + test/CodeGen/PowerPC/crypto_bifs.ll | 1 + test/CodeGen/PowerPC/ctr-minmaxnum.ll | 231 + test/CodeGen/PowerPC/ctrloop-udivti3.ll | 5 +- test/CodeGen/PowerPC/ctrloops-softfloat.ll | 129 + test/CodeGen/PowerPC/ctrloops.ll | 15 +- test/CodeGen/PowerPC/cxx_tlscc64.ll | 43 + test/CodeGen/PowerPC/dbg.ll | 5 +- test/CodeGen/PowerPC/direct-move-profit.ll | 83 + test/CodeGen/PowerPC/ec-input.ll | 24 +- test/CodeGen/PowerPC/ext-bool-trunc-repl.ll | 38 + test/CodeGen/PowerPC/fabs.ll | 31 +- test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll | 187 + test/CodeGen/PowerPC/fast-isel-fpconv.ll | 33 + test/CodeGen/PowerPC/fast-isel-i64offset.ll | 12 + test/CodeGen/PowerPC/fdiv-combine.ll | 10 +- test/CodeGen/PowerPC/fma-assoc.ll | 4 +- test/CodeGen/PowerPC/fma-ext.ll | 4 +- test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll | 36 + test/CodeGen/PowerPC/fma-mutate.ll | 2 +- test/CodeGen/PowerPC/fma.ll | 8 +- test/CodeGen/PowerPC/fp2int2fp-ppcfp128.ll | 4 +- test/CodeGen/PowerPC/hello-reloc.s | 2 +- test/CodeGen/PowerPC/hidden-vis-2.ll | 21 +- test/CodeGen/PowerPC/indirect-hidden.ll | 21 + .../PowerPC/inline-asm-scalar-to-vector-error.ll | 14 + test/CodeGen/PowerPC/lbzux.ll | 5 +- test/CodeGen/PowerPC/load-two-flts.ll | 60 + test/CodeGen/PowerPC/load-v4i8-improved.ll | 23 + test/CodeGen/PowerPC/lsr-postinc-pos.ll | 12 +- test/CodeGen/PowerPC/machine-combiner.ll | 4 + test/CodeGen/PowerPC/multi-return.ll | 21 + test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 2 +- test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 23 + test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 143 + test/CodeGen/PowerPC/optcmp.ll | 8 +- .../PowerPC/p8-scalar_vector_conversions.ll | 12 +- test/CodeGen/PowerPC/p8altivec-shuffles-pred.ll | 3 +- test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll | 970 ++ test/CodeGen/PowerPC/pie.ll | 16 + test/CodeGen/PowerPC/popcnt.ll | 24 +- test/CodeGen/PowerPC/ppc-shrink-wrapping.ll | 7 +- test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll | 21 + test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll | 24 + test/CodeGen/PowerPC/ppc32-i1-vaarg.ll | 4 +- test/CodeGen/PowerPC/ppc64-align-long-double.ll | 16 +- test/CodeGen/PowerPC/ppc64-byval-align.ll | 3 +- test/CodeGen/PowerPC/ppc64-calls.ll | 6 +- test/CodeGen/PowerPC/ppc64-fastcc.ll | 6 +- test/CodeGen/PowerPC/ppc64-linux-func-size.ll | 2 +- test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll | 46 + test/CodeGen/PowerPC/ppc64-sibcall.ll | 191 + test/CodeGen/PowerPC/ppc64-toc.ll | 2 +- test/CodeGen/PowerPC/ppcf128-endian.ll | 8 +- test/CodeGen/PowerPC/ppcf128sf.ll | 179 + test/CodeGen/PowerPC/ppcsoftops.ll | 2 + test/CodeGen/PowerPC/pr17168.ll | 59 +- test/CodeGen/PowerPC/pr24546.ll | 7 +- test/CodeGen/PowerPC/pr25802.ll | 52 - test/CodeGen/PowerPC/pr26180.ll | 14 + test/CodeGen/PowerPC/pr26378.ll | 6 + test/CodeGen/PowerPC/pr26617.ll | 15 + test/CodeGen/PowerPC/pr26690.ll | 8 +- test/CodeGen/PowerPC/pr27078.ll | 15 + test/CodeGen/PowerPC/pr27350.ll | 26 + test/CodeGen/PowerPC/pr28130.ll | 70 + test/CodeGen/PowerPC/preincprep-invoke.ll | 8 +- test/CodeGen/PowerPC/qpx-bv-sint.ll | 6 +- test/CodeGen/PowerPC/qpx-load-splat.ll | 75 + test/CodeGen/PowerPC/qpx-s-sel.ll | 5 +- test/CodeGen/PowerPC/qpx-sel.ll | 5 +- test/CodeGen/PowerPC/qpx-split-vsetcc.ll | 21 +- test/CodeGen/PowerPC/remove-redundant-moves.ll | 107 + test/CodeGen/PowerPC/rlwinm-zero-ext.ll | 57 + test/CodeGen/PowerPC/stack-protector.ll | 17 +- test/CodeGen/PowerPC/stackmap-frame-setup.ll | 4 +- test/CodeGen/PowerPC/stubs.ll | 17 +- test/CodeGen/PowerPC/stwux.ll | 5 +- test/CodeGen/PowerPC/subreg-postra-2.ll | 147 +- test/CodeGen/PowerPC/subreg-postra.ll | 31 +- test/CodeGen/PowerPC/subsumes-pred-regs.ll | 65 - test/CodeGen/PowerPC/svr4-redzone.ll | 18 +- test/CodeGen/PowerPC/swaps-le-2.ll | 2 +- test/CodeGen/PowerPC/swaps-le-7.ll | 55 + test/CodeGen/PowerPC/tailcall-string-rvo.ll | 47 + test/CodeGen/PowerPC/thread-pointer.ll | 17 + test/CodeGen/PowerPC/tls_get_addr_stackframe.ll | 21 +- test/CodeGen/PowerPC/unal-altivec.ll | 18 +- test/CodeGen/PowerPC/unal4-std.ll | 13 +- test/CodeGen/PowerPC/unwind-dw2-g.ll | 5 +- test/CodeGen/PowerPC/vec_abs.ll | 80 + test/CodeGen/PowerPC/vec_cmp.ll | 6 +- test/CodeGen/PowerPC/vec_fneg.ll | 33 +- test/CodeGen/PowerPC/vrsave-spill.ll | 4 +- test/CodeGen/PowerPC/vsx-fma-m.ll | 1 + test/CodeGen/PowerPC/vsx-fma-mutate-undef.ll | 6 +- test/CodeGen/PowerPC/vsx-fma-sp.ll | 2 + test/CodeGen/PowerPC/vsx-infl-copy1.ll | 19 +- test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll | 202 +- test/CodeGen/PowerPC/vsx-word-splats.ll | 147 + test/CodeGen/PowerPC/vsx.ll | 94 +- test/CodeGen/PowerPC/weak_def_can_be_hidden.ll | 8 +- test/CodeGen/PowerPC/xvcmpeqdp-v2f64.ll | 16 +- test/CodeGen/SPARC/2011-01-11-CC.ll | 4 +- test/CodeGen/SPARC/32abi.ll | 140 +- test/CodeGen/SPARC/64abi.ll | 185 +- test/CodeGen/SPARC/LeonFixCALLPassUT.ll | 20 + test/CodeGen/SPARC/LeonFixFSMULDPassUT.ll | 31 + test/CodeGen/SPARC/LeonInsertNOPLoad.ll | 13 + test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll | 43 + .../CodeGen/SPARC/LeonInsertNOPsDoublePrecision.ll | 17 + test/CodeGen/SPARC/LeonItinerariesUT.ll | 50 + test/CodeGen/SPARC/LeonPreventRoundChangePassUT.ll | 65 + test/CodeGen/SPARC/LeonReplaceFMULSPassUT.ll | 19 + test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll | 9 + test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll | 20 + test/CodeGen/SPARC/atomics.ll | 170 +- test/CodeGen/SPARC/float.ll | 9 +- test/CodeGen/SPARC/fp128.ll | 117 +- test/CodeGen/SPARC/func-addr.ll | 51 + test/CodeGen/SPARC/inlineasm.ll | 12 + test/CodeGen/SPARC/missinglabel.ll | 4 +- test/CodeGen/SPARC/sjlj.ll | 88 + test/CodeGen/SPARC/soft-float.ll | 235 + test/CodeGen/SPARC/stack-protector.ll | 33 + test/CodeGen/SPARC/thread-pointer.ll | 11 + test/CodeGen/SPARC/vector-call.ll | 33 + test/CodeGen/SPARC/zerostructcall.ll | 51 + test/CodeGen/SystemZ/Large/branch-range-01.py | 3 + test/CodeGen/SystemZ/Large/branch-range-03.py | 3 + test/CodeGen/SystemZ/Large/branch-range-04.py | 3 + test/CodeGen/SystemZ/Large/branch-range-05.py | 3 + test/CodeGen/SystemZ/Large/branch-range-06.py | 3 + test/CodeGen/SystemZ/Large/branch-range-09.py | 3 + test/CodeGen/SystemZ/Large/branch-range-10.py | 3 + test/CodeGen/SystemZ/Large/branch-range-11.py | 3 + test/CodeGen/SystemZ/Large/branch-range-12.py | 3 + test/CodeGen/SystemZ/alloca-01.ll | 2 +- test/CodeGen/SystemZ/and-xor-01.ll | 14 + test/CodeGen/SystemZ/args-09.ll | 53 + test/CodeGen/SystemZ/args-10.ll | 50 + test/CodeGen/SystemZ/asm-02.ll | 37 +- test/CodeGen/SystemZ/asm-03.ll | 40 +- test/CodeGen/SystemZ/asm-04.ll | 63 +- test/CodeGen/SystemZ/asm-05.ll | 3 - test/CodeGen/SystemZ/atomic-fence-01.ll | 16 + test/CodeGen/SystemZ/atomic-fence-02.ll | 13 + test/CodeGen/SystemZ/atomicrmw-add-01.ll | 24 +- test/CodeGen/SystemZ/atomicrmw-add-02.ll | 30 +- test/CodeGen/SystemZ/atomicrmw-and-01.ll | 33 +- test/CodeGen/SystemZ/atomicrmw-and-02.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-minmax-01.ll | 66 +- test/CodeGen/SystemZ/atomicrmw-minmax-02.ll | 66 +- test/CodeGen/SystemZ/atomicrmw-minmax-03.ll | 36 +- test/CodeGen/SystemZ/atomicrmw-minmax-04.ll | 30 +- test/CodeGen/SystemZ/atomicrmw-nand-01.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-nand-02.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-or-01.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-or-02.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-sub-01.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-sub-02.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-xchg-01.ll | 18 +- test/CodeGen/SystemZ/atomicrmw-xchg-02.ll | 18 +- test/CodeGen/SystemZ/atomicrmw-xor-01.ll | 34 +- test/CodeGen/SystemZ/atomicrmw-xor-02.ll | 34 +- test/CodeGen/SystemZ/backchain.ll | 84 + test/CodeGen/SystemZ/branch-05.ll | 2 +- test/CodeGen/SystemZ/bswap-06.ll | 99 + test/CodeGen/SystemZ/bswap-07.ll | 100 + test/CodeGen/SystemZ/builtins.ll | 14 + test/CodeGen/SystemZ/call-04.ll | 369 + test/CodeGen/SystemZ/call-05.ll | 467 + test/CodeGen/SystemZ/cmpxchg-01.ll | 12 +- test/CodeGen/SystemZ/cmpxchg-02.ll | 14 +- test/CodeGen/SystemZ/cmpxchg-05.ll | 81 + test/CodeGen/SystemZ/cond-li.ll | 23 + test/CodeGen/SystemZ/cond-store-01.ll | 51 +- test/CodeGen/SystemZ/cond-store-02.ll | 51 +- test/CodeGen/SystemZ/cond-store-03.ll | 39 +- test/CodeGen/SystemZ/cond-store-04.ll | 21 +- test/CodeGen/SystemZ/cond-store-05.ll | 27 +- test/CodeGen/SystemZ/cond-store-06.ll | 27 +- test/CodeGen/SystemZ/dyn-alloca-offset.ll | 42 + test/CodeGen/SystemZ/fp-cmp-01.ll | 38 +- test/CodeGen/SystemZ/fp-cmp-02.ll | 16 +- test/CodeGen/SystemZ/fp-cmp-03.ll | 4 +- test/CodeGen/SystemZ/fp-cmp-04.ll | 38 +- test/CodeGen/SystemZ/fp-cmp-05.ll | 12 +- test/CodeGen/SystemZ/fp-copysign-01.ll | 18 +- test/CodeGen/SystemZ/fp-move-01.ll | 1 - test/CodeGen/SystemZ/fp-move-09.ll | 5 +- test/CodeGen/SystemZ/fp-move-10.ll | 4 +- test/CodeGen/SystemZ/fp-move-12.ll | 33 + test/CodeGen/SystemZ/fp-sqrt-01.ll | 4 +- test/CodeGen/SystemZ/fp-sqrt-02.ll | 4 +- test/CodeGen/SystemZ/frameaddr-01.ll | 28 + test/CodeGen/SystemZ/htm-intrinsics.ll | 8 +- test/CodeGen/SystemZ/int-cmp-01.ll | 2 +- test/CodeGen/SystemZ/int-cmp-02.ll | 24 +- test/CodeGen/SystemZ/int-cmp-03.ll | 24 +- test/CodeGen/SystemZ/int-cmp-04.ll | 2 +- test/CodeGen/SystemZ/int-cmp-05.ll | 28 +- test/CodeGen/SystemZ/int-cmp-06.ll | 36 +- test/CodeGen/SystemZ/int-cmp-07.ll | 18 +- test/CodeGen/SystemZ/int-cmp-08.ll | 18 +- test/CodeGen/SystemZ/int-cmp-09.ll | 57 +- test/CodeGen/SystemZ/int-cmp-10.ll | 12 +- test/CodeGen/SystemZ/int-cmp-11.ll | 45 +- test/CodeGen/SystemZ/int-cmp-12.ll | 18 +- test/CodeGen/SystemZ/int-cmp-13.ll | 48 +- test/CodeGen/SystemZ/int-cmp-14.ll | 48 +- test/CodeGen/SystemZ/int-cmp-15.ll | 20 +- test/CodeGen/SystemZ/int-cmp-16.ll | 12 +- test/CodeGen/SystemZ/int-cmp-17.ll | 12 +- test/CodeGen/SystemZ/int-cmp-18.ll | 12 +- test/CodeGen/SystemZ/int-cmp-19.ll | 12 +- test/CodeGen/SystemZ/int-cmp-20.ll | 20 +- test/CodeGen/SystemZ/int-cmp-21.ll | 20 +- test/CodeGen/SystemZ/int-cmp-22.ll | 18 +- test/CodeGen/SystemZ/int-cmp-23.ll | 12 +- test/CodeGen/SystemZ/int-cmp-24.ll | 8 +- test/CodeGen/SystemZ/int-cmp-25.ll | 8 +- test/CodeGen/SystemZ/int-cmp-26.ll | 12 +- test/CodeGen/SystemZ/int-cmp-27.ll | 12 +- test/CodeGen/SystemZ/int-cmp-28.ll | 12 +- test/CodeGen/SystemZ/int-cmp-29.ll | 12 +- test/CodeGen/SystemZ/int-cmp-30.ll | 20 +- test/CodeGen/SystemZ/int-cmp-31.ll | 20 +- test/CodeGen/SystemZ/int-cmp-32.ll | 28 +- test/CodeGen/SystemZ/int-cmp-33.ll | 16 +- test/CodeGen/SystemZ/int-cmp-34.ll | 28 +- test/CodeGen/SystemZ/int-cmp-35.ll | 16 +- test/CodeGen/SystemZ/int-cmp-36.ll | 10 +- test/CodeGen/SystemZ/int-cmp-37.ll | 18 +- test/CodeGen/SystemZ/int-cmp-38.ll | 14 +- test/CodeGen/SystemZ/int-cmp-39.ll | 10 +- test/CodeGen/SystemZ/int-cmp-40.ll | 18 +- test/CodeGen/SystemZ/int-cmp-41.ll | 10 +- test/CodeGen/SystemZ/int-cmp-42.ll | 10 +- test/CodeGen/SystemZ/int-cmp-43.ll | 12 +- test/CodeGen/SystemZ/int-cmp-44.ll | 82 +- test/CodeGen/SystemZ/int-cmp-46.ll | 48 +- test/CodeGen/SystemZ/int-cmp-47.ll | 30 +- test/CodeGen/SystemZ/int-cmp-48.ll | 4 +- test/CodeGen/SystemZ/memchr-01.ll | 2 +- test/CodeGen/SystemZ/memchr-02.ll | 2 +- test/CodeGen/SystemZ/memchr-nobuiltin.ll | 16 + test/CodeGen/SystemZ/memcmp-01.ll | 12 +- test/CodeGen/SystemZ/memcmp-02.ll | 10 +- test/CodeGen/SystemZ/memcmp-nobuiltin.ll | 191 + test/CodeGen/SystemZ/pie.ll | 13 + test/CodeGen/SystemZ/ret-addr-01.ll | 15 + test/CodeGen/SystemZ/risbg-01.ll | 21 + test/CodeGen/SystemZ/risbg-02.ll | 25 + test/CodeGen/SystemZ/rot-01.ll | 35 + test/CodeGen/SystemZ/rot-02.ll | 86 + test/CodeGen/SystemZ/shift-11.ll | 63 + test/CodeGen/SystemZ/shift-12.ll | 106 + test/CodeGen/SystemZ/stack-guard.ll | 35 + test/CodeGen/SystemZ/strcmp-01.ll | 4 +- test/CodeGen/SystemZ/strcmp-02.ll | 4 +- test/CodeGen/SystemZ/strcmp-nobuiltin.ll | 54 + test/CodeGen/SystemZ/strcpy-nobuiltin.ll | 42 + test/CodeGen/SystemZ/strlen-nobuiltin.ll | 25 + test/CodeGen/SystemZ/swift-return.ll | 203 + test/CodeGen/SystemZ/swifterror.ll | 358 + test/CodeGen/SystemZ/swiftself.ll | 66 + test/CodeGen/SystemZ/tdc-01.ll | 95 + test/CodeGen/SystemZ/tdc-02.ll | 96 + test/CodeGen/SystemZ/tdc-03.ll | 139 + test/CodeGen/SystemZ/tdc-04.ll | 85 + test/CodeGen/SystemZ/tdc-05.ll | 97 + test/CodeGen/SystemZ/tdc-06.ll | 48 + test/CodeGen/SystemZ/trap-01.ll | 179 + test/CodeGen/SystemZ/vec-extract-02.ll | 2 +- test/CodeGen/SystemZ/vec-intrinsics.ll | 44 +- test/CodeGen/SystemZ/vec-sub-01.ll | 2 +- test/CodeGen/Thumb/2010-07-01-FuncAlign.ll | 2 +- test/CodeGen/Thumb/2010-07-15-debugOrdering.ll | 18 +- test/CodeGen/Thumb/and_neg.ll | 20 + test/CodeGen/Thumb/barrier.ll | 2 +- test/CodeGen/Thumb/bic_imm.ll | 26 + test/CodeGen/Thumb/constants.ll | 19 + test/CodeGen/Thumb/ldm-merge-struct.ll | 2 +- test/CodeGen/Thumb/ldm-stm-postinc.ll | 81 + test/CodeGen/Thumb/segmented-stacks.ll | 2 +- test/CodeGen/Thumb2/2009-09-01-PostRAProlog.ll | 2 - test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll | 1 - test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll | 4 +- test/CodeGen/Thumb2/2010-03-15-AsmCCClobber.ll | 2 +- test/CodeGen/Thumb2/aligned-constants.ll | 4 +- test/CodeGen/Thumb2/bicbfi.ll | 17 + test/CodeGen/Thumb2/carry.ll | 8 +- test/CodeGen/Thumb2/emit-unwinding.ll | 2 +- test/CodeGen/Thumb2/ldr-str-imm12.ll | 20 +- test/CodeGen/Thumb2/thumb2-call.ll | 18 +- test/CodeGen/Thumb2/thumb2-cbnz.ll | 4 +- test/CodeGen/Thumb2/thumb2-cpsr-liveness.ll | 41 + test/CodeGen/Thumb2/thumb2-ldm.ll | 55 +- test/CodeGen/Thumb2/thumb2-tbb.ll | 2 +- test/CodeGen/Thumb2/tls2.ll | 4 +- test/CodeGen/Thumb2/v8_IT_5.ll | 25 +- test/CodeGen/WebAssembly/address-offsets.ll | 672 ++ test/CodeGen/WebAssembly/byval.ll | 131 + test/CodeGen/WebAssembly/call.ll | 5 +- test/CodeGen/WebAssembly/cfg-stackify.ll | 571 +- test/CodeGen/WebAssembly/comparisons_f32.ll | 2 +- test/CodeGen/WebAssembly/comparisons_f64.ll | 2 +- test/CodeGen/WebAssembly/comparisons_i32.ll | 3 +- test/CodeGen/WebAssembly/comparisons_i64.ll | 3 +- test/CodeGen/WebAssembly/conv.ll | 2 +- test/CodeGen/WebAssembly/cpus.ll | 4 +- test/CodeGen/WebAssembly/dead-vreg.ll | 2 +- test/CodeGen/WebAssembly/divrem-constant.ll | 62 + test/CodeGen/WebAssembly/f32.ll | 2 +- test/CodeGen/WebAssembly/f64.ll | 2 +- test/CodeGen/WebAssembly/fast-isel.ll | 28 + test/CodeGen/WebAssembly/frem.ll | 2 +- test/CodeGen/WebAssembly/func.ll | 5 +- test/CodeGen/WebAssembly/global.ll | 48 +- test/CodeGen/WebAssembly/i128.ll | 280 + .../WebAssembly/i32-load-store-alignment.ll | 212 + test/CodeGen/WebAssembly/i32.ll | 67 +- .../WebAssembly/i64-load-store-alignment.ll | 325 + test/CodeGen/WebAssembly/i64.ll | 67 +- test/CodeGen/WebAssembly/immediates.ll | 37 +- test/CodeGen/WebAssembly/indirect-import.ll | 73 + test/CodeGen/WebAssembly/inline-asm.ll | 6 +- test/CodeGen/WebAssembly/irreducible-cfg.ll | 94 + test/CodeGen/WebAssembly/legalize.ll | 2 +- test/CodeGen/WebAssembly/load-ext.ll | 2 +- test/CodeGen/WebAssembly/load-store-i1.ll | 24 +- test/CodeGen/WebAssembly/load.ll | 3 +- test/CodeGen/WebAssembly/loop-idiom.ll | 53 - test/CodeGen/WebAssembly/mem-intrinsics.ll | 140 + test/CodeGen/WebAssembly/memory-addr32.ll | 12 +- test/CodeGen/WebAssembly/memory-addr64.ll | 12 +- test/CodeGen/WebAssembly/non-executable-stack.ll | 9 + test/CodeGen/WebAssembly/offset-folding.ll | 23 +- test/CodeGen/WebAssembly/offset.ll | 88 +- test/CodeGen/WebAssembly/phi.ll | 2 +- test/CodeGen/WebAssembly/reg-stackify.ll | 404 +- test/CodeGen/WebAssembly/return-int32.ll | 26 +- test/CodeGen/WebAssembly/return-void.ll | 21 +- test/CodeGen/WebAssembly/returned.ll | 4 +- test/CodeGen/WebAssembly/select.ll | 28 +- test/CodeGen/WebAssembly/signext-zeroext.ll | 24 +- test/CodeGen/WebAssembly/store-results.ll | 19 +- test/CodeGen/WebAssembly/store-trunc.ll | 10 +- test/CodeGen/WebAssembly/store.ll | 11 +- test/CodeGen/WebAssembly/switch.ll | 6 +- test/CodeGen/WebAssembly/unreachable.ll | 2 +- test/CodeGen/WebAssembly/unused-argument.ll | 4 +- test/CodeGen/WebAssembly/userstack.ll | 277 +- test/CodeGen/WebAssembly/varargs.ll | 87 +- test/CodeGen/WinEH/wineh-asm.ll | 26 + test/CodeGen/WinEH/wineh-cloning.ll | 5 +- test/CodeGen/WinEH/wineh-nested-unwind.ll | 55 + test/CodeGen/WinEH/wineh-setjmp.ll | 75 + .../CodeGen/WinEH/wineh-statenumbering-cleanups.ll | 1 - test/CodeGen/WinEH/wineh-statenumbering.ll | 73 +- test/CodeGen/X86/2006-05-02-InstrSched1.ll | 4 +- test/CodeGen/X86/2006-11-12-CSRetCC.ll | 9 +- test/CodeGen/X86/2007-08-10-SignExtSubreg.ll | 5 +- test/CodeGen/X86/2007-08-13-AppendingLinkage.ll | 12 - test/CodeGen/X86/2007-10-15-CoalescerCrash.ll | 2 +- .../CodeGen/X86/2008-06-13-NotVolatileLoadStore.ll | 6 +- test/CodeGen/X86/2008-07-19-movups-spills.ll | 64 +- test/CodeGen/X86/2008-07-22-CombinerCrash.ll | 4 +- test/CodeGen/X86/2008-08-17-UComiCodeGenBug.ll | 2 +- test/CodeGen/X86/2008-08-19-SubAndFetch.ll | 12 - test/CodeGen/X86/2008-09-11-CoalescerBug2.ll | 4 +- test/CodeGen/X86/2008-09-29-ReMatBug.ll | 2 +- test/CodeGen/X86/2009-02-12-DebugInfoVLA.ll | 9 +- test/CodeGen/X86/2009-03-05-burr-list-crash.ll | 2 +- test/CodeGen/X86/2009-10-16-Scope.ll | 5 +- test/CodeGen/X86/2010-01-18-DbgValue.ll | 5 +- test/CodeGen/X86/2010-02-01-DbgValueCrash.ll | 5 +- test/CodeGen/X86/2010-05-25-DotDebugLoc.ll | 5 +- test/CodeGen/X86/2010-05-26-DotDebugLoc.ll | 9 +- test/CodeGen/X86/2010-05-28-Crash.ll | 7 +- test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll | 9 +- test/CodeGen/X86/2010-07-06-DbgCrash.ll | 7 +- test/CodeGen/X86/2010-08-04-StackVariable.ll | 8 +- test/CodeGen/X86/2010-09-16-EmptyFilename.ll | 7 +- test/CodeGen/X86/2010-11-02-DbgParameter.ll | 5 +- test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll | 7 +- test/CodeGen/X86/2011-06-14-PreschedRegalias.ll | 2 +- test/CodeGen/X86/2011-09-14-valcoalesce.ll | 2 +- test/CodeGen/X86/2011-10-21-widen-cmp.ll | 2 +- test/CodeGen/X86/2012-01-11-split-cv.ll | 17 +- test/CodeGen/X86/2012-01-12-extract-sv.ll | 9 +- test/CodeGen/X86/2012-04-26-sdglue.ll | 36 +- test/CodeGen/X86/2012-1-10-buildvector.ll | 2 +- test/CodeGen/X86/2012-11-30-handlemove-dbg.ll | 5 +- test/CodeGen/X86/2012-11-30-misched-dbg.ll | 10 +- test/CodeGen/X86/2012-11-30-regpres-dbg.ll | 7 +- test/CodeGen/X86/3addr-16bit.ll | 8 +- test/CodeGen/X86/AppendingLinkage.ll | 4 + test/CodeGen/X86/GC/dynamic-frame-size.ll | 2 +- test/CodeGen/X86/GC/erlang-gc.ll | 4 +- test/CodeGen/X86/GC/ocaml-gc.ll | 4 +- test/CodeGen/X86/MachineSink-DbgValue.ll | 9 +- test/CodeGen/X86/MergeConsecutiveStores.ll | 24 +- test/CodeGen/X86/StackColoring-dbg.ll | 5 +- test/CodeGen/X86/StackColoring.ll | 175 +- test/CodeGen/X86/WidenArith.ll | 22 +- test/CodeGen/X86/abi-isel.ll | 72 +- test/CodeGen/X86/add-nsw-sext.ll | 6 +- test/CodeGen/X86/add.ll | 36 + test/CodeGen/X86/alias-gep.ll | 22 + test/CodeGen/X86/aligned-variadic.ll | 4 +- test/CodeGen/X86/alignment.ll | 4 +- test/CodeGen/X86/all-ones-vector.ll | 139 +- test/CodeGen/X86/and-encoding.ll | 27 +- test/CodeGen/X86/anyext.ll | 39 +- test/CodeGen/X86/atom-lea-sp.ll | 4 +- test/CodeGen/X86/atomic-eflags-reuse.ll | 179 + test/CodeGen/X86/atomic-non-integer.ll | 2 +- test/CodeGen/X86/atomic128.ll | 11 +- test/CodeGen/X86/atomic16.ll | 56 +- test/CodeGen/X86/atomic8.ll | 48 +- test/CodeGen/X86/atomic_mi.ll | 17 + test/CodeGen/X86/avoid-loop-align.ll | 2 +- test/CodeGen/X86/avx-basic.ll | 85 +- test/CodeGen/X86/avx-cast.ll | 11 +- test/CodeGen/X86/avx-intel-ocl.ll | 7 +- test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 3778 +++++++ test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll | 392 +- test/CodeGen/X86/avx-intrinsics-x86.ll | 4341 +++++--- test/CodeGen/X86/avx-intrinsics-x86_64.ll | 1 + test/CodeGen/X86/avx-isa-check.ll | 114 +- test/CodeGen/X86/avx-select.ll | 29 +- test/CodeGen/X86/avx-shift.ll | 9 +- test/CodeGen/X86/avx-shuffle-x86_32.ll | 2 +- test/CodeGen/X86/avx-splat.ll | 14 +- test/CodeGen/X86/avx-trunc.ll | 37 +- test/CodeGen/X86/avx-vbroadcast.ll | 20 +- test/CodeGen/X86/avx-vbroadcastf128.ll | 111 + test/CodeGen/X86/avx-vextractf128.ll | 91 +- test/CodeGen/X86/avx-vperm2x128.ll | 433 +- test/CodeGen/X86/avx-vzeroupper.ll | 5 + test/CodeGen/X86/avx2-conversions.ll | 6 +- test/CodeGen/X86/avx2-intrinsics-fast-isel.ll | 3388 ++++++ test/CodeGen/X86/avx2-intrinsics-x86-upgrade.ll | 361 +- test/CodeGen/X86/avx2-intrinsics-x86.ll | 1342 ++- test/CodeGen/X86/avx2-logic.ll | 29 - test/CodeGen/X86/avx2-nontemporal.ll | 65 +- test/CodeGen/X86/avx2-phaddsub.ll | 51 +- test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll | 110 - test/CodeGen/X86/avx2-pmovxrm.ll | 201 + test/CodeGen/X86/avx2-vbroadcast.ll | 13 +- test/CodeGen/X86/avx2-vbroadcasti128.ll | 129 + test/CodeGen/X86/avx2-vector-shifts.ll | 445 +- test/CodeGen/X86/avx2-vperm.ll | 27 +- test/CodeGen/X86/avx512-any_extend_load.ll | 70 + test/CodeGen/X86/avx512-arith.ll | 142 +- test/CodeGen/X86/avx512-bugfix-23634.ll | 27 +- test/CodeGen/X86/avx512-bugfix-26264.ll | 47 + test/CodeGen/X86/avx512-build-vector.ll | 7 +- test/CodeGen/X86/avx512-calling-conv.ll | 103 +- test/CodeGen/X86/avx512-cmp.ll | 130 +- test/CodeGen/X86/avx512-cvt.ll | 665 +- test/CodeGen/X86/avx512-ext.ll | 713 +- test/CodeGen/X86/avx512-extract-subvector.ll | 290 + test/CodeGen/X86/avx512-fma-intrinsics.ll | 307 +- test/CodeGen/X86/avx512-fma.ll | 35 +- test/CodeGen/X86/avx512-gather-scatter-intrin.ll | 28 +- test/CodeGen/X86/avx512-inc-dec.ll | 2 +- test/CodeGen/X86/avx512-insert-extract.ll | 521 +- test/CodeGen/X86/avx512-intel-ocl.ll | 13 +- test/CodeGen/X86/avx512-intrinsics-fast-isel.ll | 1134 ++ test/CodeGen/X86/avx512-intrinsics-upgrade.ll | 1089 ++ test/CodeGen/X86/avx512-intrinsics.ll | 2823 +++-- test/CodeGen/X86/avx512-logic.ll | 66 + test/CodeGen/X86/avx512-mask-op.ll | 2318 ++-- test/CodeGen/X86/avx512-mask-spills.ll | 126 + test/CodeGen/X86/avx512-mov.ll | 376 +- test/CodeGen/X86/avx512-nontemporal.ll | 16 +- test/CodeGen/X86/avx512-scalarIntrinsics.ll | 66 + test/CodeGen/X86/avx512-select.ll | 138 +- test/CodeGen/X86/avx512-skx-insert-subvec.ll | 73 +- test/CodeGen/X86/avx512-trunc.ll | 15 + test/CodeGen/X86/avx512-unsafe-fp-math.ll | 107 + test/CodeGen/X86/avx512-vbroadcast.ll | 48 +- test/CodeGen/X86/avx512-vec-cmp.ll | 1073 +- test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll | 413 + test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll | 538 + test/CodeGen/X86/avx512bw-intrinsics.ll | 905 +- test/CodeGen/X86/avx512bw-mask-op.ll | 107 +- test/CodeGen/X86/avx512bw-mov.ll | 185 +- test/CodeGen/X86/avx512bw-vec-cmp.ll | 113 +- .../CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll | 244 + test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll | 629 ++ test/CodeGen/X86/avx512bwvl-intrinsics.ll | 4775 +++++---- test/CodeGen/X86/avx512bwvl-mov.ll | 129 +- test/CodeGen/X86/avx512bwvl-vec-cmp.ll | 225 +- test/CodeGen/X86/avx512cdvl-intrinsics.ll | 61 +- test/CodeGen/X86/avx512dq-intrinsics.ll | 277 +- test/CodeGen/X86/avx512dq-mask-op.ll | 55 +- test/CodeGen/X86/avx512dqvl-intrinsics.ll | 1530 ++- test/CodeGen/X86/avx512ifma-intrinsics.ll | 105 + test/CodeGen/X86/avx512ifmavl-intrinsics.ll | 226 + test/CodeGen/X86/avx512vbmi-intrinsics.ll | 95 + test/CodeGen/X86/avx512vbmivl-intrinsics.ll | 195 + test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll | 1391 +++ test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll | 2536 +++++ test/CodeGen/X86/avx512vl-intrinsics.ll | 7025 ++++++------- test/CodeGen/X86/avx512vl-logic.ll | 48 + test/CodeGen/X86/avx512vl-mov.ll | 517 +- test/CodeGen/X86/avx512vl-vbroadcast.ll | 175 + test/CodeGen/X86/avx512vl-vec-cmp.ll | 301 +- test/CodeGen/X86/base-pointer-and-cmpxchg.ll | 51 + test/CodeGen/X86/bit-piece-comment.ll | 5 +- test/CodeGen/X86/bitreverse.ll | 382 +- test/CodeGen/X86/block-placement.ll | 273 +- .../CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll | 165 + test/CodeGen/X86/bmi-intrinsics-fast-isel.ll | 326 + test/CodeGen/X86/bmi.ll | 555 +- test/CodeGen/X86/bool-zext.ll | 37 +- test/CodeGen/X86/br-fold.ll | 6 + test/CodeGen/X86/break-false-dep.ll | 4 +- test/CodeGen/X86/bss_pagealigned.ll | 2 +- test/CodeGen/X86/bswap-vector.ll | 151 +- test/CodeGen/X86/bt.ll | 1225 ++- test/CodeGen/X86/buildvec-insertvec.ll | 2 +- test/CodeGen/X86/byval2.ll | 4 +- test/CodeGen/X86/call-push.ll | 2 +- test/CodeGen/X86/catchpad-dynamic-alloca.ll | 65 + test/CodeGen/X86/catchpad-lifetime.ll | 8 +- test/CodeGen/X86/catchret-regmask.ll | 73 + test/CodeGen/X86/cfstring.ll | 2 +- test/CodeGen/X86/cleanuppad-inalloca.ll | 4 +- test/CodeGen/X86/cleanuppad-realign.ll | 4 +- .../CodeGen/X86/clear_upper_vector_element_bits.ll | 683 ++ test/CodeGen/X86/clz.ll | 755 +- test/CodeGen/X86/cmov-into-branch.ll | 132 +- test/CodeGen/X86/cmov.ll | 4 +- test/CodeGen/X86/cmovcmov.ll | 6 +- test/CodeGen/X86/cmp.ll | 31 +- test/CodeGen/X86/cmpxchg-clobber-flags.ll | 12 +- test/CodeGen/X86/cmpxchg-i1.ll | 6 +- test/CodeGen/X86/cmpxchg-i128-i1.ll | 4 +- test/CodeGen/X86/coalescer-commute3.ll | 2 +- test/CodeGen/X86/code_placement_align_all.ll | 6 +- .../CodeGen/X86/code_placement_cold_loop_blocks.ll | 2 +- .../code_placement_ignore_succ_in_inner_loop.ll | 2 +- test/CodeGen/X86/code_placement_loop_rotation.ll | 2 +- test/CodeGen/X86/code_placement_loop_rotation2.ll | 2 +- test/CodeGen/X86/code_placement_loop_rotation3.ll | 42 + .../code_placement_outline_optional_branches.ll | 2 +- test/CodeGen/X86/combine-multiplies.ll | 10 +- test/CodeGen/X86/combine-or.ll | 59 + test/CodeGen/X86/combine-testm-and.ll | 57 + test/CodeGen/X86/commute-blend-avx2.ll | 67 +- test/CodeGen/X86/commute-blend-sse41.ll | 27 +- test/CodeGen/X86/commute-fcmp.ll | 693 +- test/CodeGen/X86/constructor.ll | 12 +- test/CodeGen/X86/crash-lre-eliminate-dead-def.ll | 268 + test/CodeGen/X86/ctpop-combine.ll | 38 +- test/CodeGen/X86/cxx_tlscc64.ll | 94 +- test/CodeGen/X86/dag-optnone.ll | 15 +- test/CodeGen/X86/darwin-stub.ll | 12 - .../X86/dbg-changes-codegen-branch-folding.ll | 253 +- test/CodeGen/X86/dbg-combine.ll | 5 +- test/CodeGen/X86/debugloc-argsize.ll | 5 +- test/CodeGen/X86/deopt-bundles.ll | 161 + test/CodeGen/X86/deopt-intrinsic-cconv.ll | 34 + test/CodeGen/X86/deopt-intrinsic.ll | 56 + test/CodeGen/X86/dllexport-x86_64.ll | 31 +- test/CodeGen/X86/dllexport.ll | 18 +- test/CodeGen/X86/dwarf-comp-dir.ll | 2 +- test/CodeGen/X86/dynamic-alloca-in-entry.ll | 2 +- test/CodeGen/X86/dynamic-allocas-VLAs.ll | 12 +- test/CodeGen/X86/eflags-copy-expansion.mir | 67 + test/CodeGen/X86/emutls-pic.ll | 26 +- test/CodeGen/X86/emutls-pie.ll | 21 +- test/CodeGen/X86/emutls_generic.ll | 46 +- test/CodeGen/X86/exedepsfix-broadcast.ll | 98 +- test/CodeGen/X86/expand-vr64-gr64-copy.mir | 2 +- test/CodeGen/X86/extractelement-index.ll | 643 +- test/CodeGen/X86/extractelement-load.ll | 91 +- test/CodeGen/X86/extractps.ll | 2 +- test/CodeGen/X86/f16c-intrinsics-fast-isel.ll | 132 + test/CodeGen/X86/fast-isel-call.ll | 44 +- test/CodeGen/X86/fast-isel-cmp-branch2.ll | 5 +- test/CodeGen/X86/fast-isel-cmp-branch3.ll | 5 +- .../CodeGen/X86/fast-isel-float-half-convertion.ll | 2 +- test/CodeGen/X86/fast-isel-nontemporal.ll | 1083 +- test/CodeGen/X86/fast-isel-stackcheck.ll | 8 +- test/CodeGen/X86/fast-isel-vecload.ll | 21 + test/CodeGen/X86/fast-isel-x86-64.ll | 8 + test/CodeGen/X86/fast-isel-x86.ll | 35 +- test/CodeGen/X86/fastmath-float-half-conversion.ll | 4 +- test/CodeGen/X86/fixup-bw-copy.ll | 71 + test/CodeGen/X86/fixup-bw-copy.mir | 156 + test/CodeGen/X86/fixup-bw-inst.ll | 126 + test/CodeGen/X86/float-conv-elim.ll | 2 +- test/CodeGen/X86/fma_patterns.ll | 41 +- test/CodeGen/X86/fold-push.ll | 2 +- test/CodeGen/X86/fold-tied-op.ll | 5 +- test/CodeGen/X86/fold-vector-sext-zext.ll | 153 +- test/CodeGen/X86/force-align-stack-alloca.ll | 14 +- test/CodeGen/X86/fp-logic.ll | 48 + test/CodeGen/X86/fp-une-cmp.ll | 122 +- test/CodeGen/X86/fp128-cast.ll | 267 +- test/CodeGen/X86/fp128-compare.ll | 33 +- test/CodeGen/X86/fp128-select.ll | 35 + test/CodeGen/X86/fpstack-debuginstr-kill.ll | 7 +- test/CodeGen/X86/frame-order.ll | 122 + test/CodeGen/X86/ga-offset.ll | 13 +- test/CodeGen/X86/ga-offset2.ll | 10 + test/CodeGen/X86/global-access-pie.ll | 123 + test/CodeGen/X86/global-sections.ll | 35 +- test/CodeGen/X86/h-registers-3.ll | 28 +- test/CodeGen/X86/haddsub-2.ll | 1017 +- test/CodeGen/X86/haddsub-undef.ll | 321 +- test/CodeGen/X86/haddsub.ll | 307 +- test/CodeGen/X86/half.ll | 71 +- test/CodeGen/X86/hipe-cc.ll | 20 +- test/CodeGen/X86/hipe-cc64.ll | 21 +- test/CodeGen/X86/hipe-prologue.ll | 13 +- test/CodeGen/X86/hoist-invariant-load.ll | 35 +- test/CodeGen/X86/hoist-spill-lpad.ll | 62 + test/CodeGen/X86/hoist-spill.ll | 121 + test/CodeGen/X86/i16lshr8pat.ll | 32 + test/CodeGen/X86/i386-setjmp-pic.ll | 23 + test/CodeGen/X86/i386-shrink-wrapping.ll | 8 +- test/CodeGen/X86/i386-tlscall-fastregalloc.ll | 11 +- test/CodeGen/X86/i686-win-shrink-wrapping.ll | 44 + test/CodeGen/X86/ifunc-asm.ll | 15 + test/CodeGen/X86/implicit-null-check.ll | 42 +- test/CodeGen/X86/implicit-null-checks.mir | 266 + test/CodeGen/X86/inalloca-ctor.ll | 4 +- test/CodeGen/X86/inalloca-invoke.ll | 3 +- test/CodeGen/X86/inalloca-stdcall.ll | 4 +- test/CodeGen/X86/inalloca.ll | 12 +- test/CodeGen/X86/indirect-hidden.ll | 4 +- test/CodeGen/X86/insertelement-zero.ll | 264 +- test/CodeGen/X86/insertps-combine.ll | 159 +- test/CodeGen/X86/interval-update-remat.ll | 161 + test/CodeGen/X86/ipra-inline-asm.ll | 20 + test/CodeGen/X86/ipra-local-linkage.ll | 30 + test/CodeGen/X86/ipra-reg-usage.ll | 12 + test/CodeGen/X86/ipra-transform.ll | 32 + test/CodeGen/X86/lakemont.ll | 9 + test/CodeGen/X86/lea-opt-memop-check-1.ll | 99 + test/CodeGen/X86/lea-opt-memop-check-2.ll | 21 + test/CodeGen/X86/lea-opt.ll | 73 +- test/CodeGen/X86/libcall-sret.ll | 25 +- test/CodeGen/X86/licm-dominance.ll | 61 +- test/CodeGen/X86/licm-symbol.ll | 2 +- test/CodeGen/X86/loc-remat.ll | 55 + test/CodeGen/X86/local_stack_symbol_ordering.ll | 184 + test/CodeGen/X86/localescape.ll | 34 +- test/CodeGen/X86/lock-inst-encoding.ll | 44 - test/CodeGen/X86/loop-blocks.ll | 28 + test/CodeGen/X86/lsr-static-addr.ll | 2 +- test/CodeGen/X86/lzcnt-tzcnt.ll | 209 - test/CodeGen/X86/machine-combiner-int.ll | 37 +- test/CodeGen/X86/machine-copy-prop.mir | 227 + test/CodeGen/X86/machine-cp.ll | 2 +- .../X86/machine-sink-and-implicit-null-checks.ll | 83 + test/CodeGen/X86/machine-trace-metrics-crash.ll | 4 +- test/CodeGen/X86/masked_gather_scatter.ll | 382 +- test/CodeGen/X86/masked_memop.ll | 10434 ++++++++++++++++++- test/CodeGen/X86/materialize-one.ll | 100 - test/CodeGen/X86/materialize.ll | 216 + test/CodeGen/X86/mbp-false-cfg-break.ll | 39 + test/CodeGen/X86/mcinst-lowering.ll | 15 +- test/CodeGen/X86/mcu-abi.ll | 59 +- test/CodeGen/X86/memcmp.ll | 18 +- test/CodeGen/X86/memcpy-from-string.ll | 24 + test/CodeGen/X86/memset-2.ll | 52 +- test/CodeGen/X86/memset-nonzero.ll | 470 + test/CodeGen/X86/memset64-on-x86-32.ll | 58 +- test/CodeGen/X86/merge-consecutive-loads-128.ll | 783 ++ test/CodeGen/X86/merge-consecutive-loads-256.ll | 756 ++ test/CodeGen/X86/merge-consecutive-loads-512.ll | 718 ++ test/CodeGen/X86/merge-sp-update-lea.ll | 32 + .../X86/merge-store-partially-alias-loads.ll | 4 +- test/CodeGen/X86/mfence.ll | 35 +- test/CodeGen/X86/mingw-alloca.ll | 4 +- test/CodeGen/X86/misched-aa-colored.ll | 1 + .../X86/misched-code-difference-with-debug.ll | 15 +- test/CodeGen/X86/misched-ilp.ll | 4 +- test/CodeGen/X86/mmx-bitcast-fold.ll | 12 + test/CodeGen/X86/movgs.ll | 9 +- test/CodeGen/X86/movmsk.ll | 75 +- test/CodeGen/X86/movpc32-check.ll | 5 +- test/CodeGen/X86/movtopush.ll | 112 +- test/CodeGen/X86/movtopush64.ll | 193 + test/CodeGen/X86/mul-i256.ll | 27 + test/CodeGen/X86/mul128.ll | 13 +- test/CodeGen/X86/mul64.ll | 25 +- test/CodeGen/X86/musttail-varargs.ll | 11 +- test/CodeGen/X86/mwaitx.ll | 38 + test/CodeGen/X86/negate-add-zero.ll | 2 +- test/CodeGen/X86/negative-offset.ll | 18 + test/CodeGen/X86/new-remat.ll | 70 + test/CodeGen/X86/no-prolog-kill.ll | 21 + test/CodeGen/X86/no-sse2-avg.ll | 32 + test/CodeGen/X86/nontemporal-2.ll | 1122 +- test/CodeGen/X86/nontemporal-loads.ll | 1638 +++ test/CodeGen/X86/nontemporal.ll | 137 +- test/CodeGen/X86/noreturn-call.ll | 48 + test/CodeGen/X86/null-streamer.ll | 5 +- test/CodeGen/X86/opt-ext-uses.ll | 4 +- test/CodeGen/X86/or-lea.ll | 13 + test/CodeGen/X86/osx-private-labels.ll | 24 +- test/CodeGen/X86/patchable-prologue.ll | 67 + test/CodeGen/X86/patchpoint-verifiable.mir | 2 +- test/CodeGen/X86/peephole-na-phys-copy-folding.ll | 17 +- test/CodeGen/X86/phaddsub.ll | 173 +- test/CodeGen/X86/phi-immediate-factoring.ll | 3 +- test/CodeGen/X86/phys-reg-local-regalloc.ll | 6 +- test/CodeGen/X86/phys_subreg_coalesce-2.ll | 2 +- test/CodeGen/X86/pic.ll | 2 +- test/CodeGen/X86/pic_jumptable.ll | 2 +- test/CodeGen/X86/pie.ll | 45 + test/CodeGen/X86/pku.ll | 2 +- test/CodeGen/X86/pmul.ll | 978 +- test/CodeGen/X86/pop-stack-cleanup.ll | 13 +- test/CodeGen/X86/popcnt.ll | 243 +- test/CodeGen/X86/post-ra-sched.ll | 40 + test/CodeGen/X86/postra-licm.ll | 4 +- test/CodeGen/X86/powi.ll | 5 +- test/CodeGen/X86/pr15267.ll | 16 +- test/CodeGen/X86/pr16360.ll | 17 +- test/CodeGen/X86/pr17764.ll | 14 +- test/CodeGen/X86/pr23664.ll | 2 +- test/CodeGen/X86/pr2585.ll | 32 + test/CodeGen/X86/pr26350.ll | 21 + test/CodeGen/X86/pr2659.ll | 2 +- test/CodeGen/X86/pr26652.ll | 9 + test/CodeGen/X86/pr26757.ll | 34 + test/CodeGen/X86/pr26835.ll | 10 + test/CodeGen/X86/pr26870.ll | 37 + test/CodeGen/X86/pr27071.ll | 29 + test/CodeGen/X86/pr27501.ll | 67 + test/CodeGen/X86/pr27591.ll | 51 + test/CodeGen/X86/pr27681.mir | 87 + test/CodeGen/X86/pr28173.ll | 41 + test/CodeGen/X86/pr28444.ll | 27 + test/CodeGen/X86/pr28472.ll | 11 + test/CodeGen/X86/pr28489.ll | 15 + test/CodeGen/X86/pr28515.ll | 16 + test/CodeGen/X86/pr28560.ll | 13 + test/CodeGen/X86/pr5145.ll | 16 +- test/CodeGen/X86/promote-i16.ll | 16 +- test/CodeGen/X86/ps4-noreturn.ll | 38 + test/CodeGen/X86/pshufb-mask-comments.ll | 66 +- test/CodeGen/X86/psubus.ll | 95 +- test/CodeGen/X86/push-cfi-debug.ll | 7 +- test/CodeGen/X86/push-cfi.ll | 2 +- test/CodeGen/X86/ragreedy-hoist-spill.ll | 10 +- test/CodeGen/X86/reduce-trunc-shl.ll | 28 + .../CodeGen/X86/regalloc-reconcile-broken-hints.ll | 2 +- test/CodeGen/X86/rem.ll | 89 +- test/CodeGen/X86/rem_crash.ll | 3 +- test/CodeGen/X86/return-ext.ll | 138 + test/CodeGen/X86/rtm.ll | 18 +- test/CodeGen/X86/sad.ll | 1001 ++ test/CodeGen/X86/safestack_ssp.ll | 27 + test/CodeGen/X86/segmented-stacks.ll | 34 +- test/CodeGen/X86/seh-catch-all-win32.ll | 8 +- test/CodeGen/X86/seh-safe-div-win32.ll | 4 +- test/CodeGen/X86/seh-safe-div.ll | 8 +- test/CodeGen/X86/seh-stack-realign.ll | 12 +- test/CodeGen/X86/setcc-lowering.ll | 4 +- test/CodeGen/X86/setcc-narrowing.ll | 4 +- test/CodeGen/X86/setcc.ll | 26 +- test/CodeGen/X86/sext-ret-val.ll | 12 +- test/CodeGen/X86/sext-setcc-self.ll | 87 +- test/CodeGen/X86/sext-trunc.ll | 11 +- test/CodeGen/X86/shift-pcmp.ll | 45 +- test/CodeGen/X86/shrink-wrap-chkstk.ll | 8 +- test/CodeGen/X86/shrink_vmul.ll | 865 ++ test/CodeGen/X86/sibcall-5.ll | 10 +- test/CodeGen/X86/sibcall-byval.ll | 6 +- test/CodeGen/X86/sincos-opt.ll | 30 + test/CodeGen/X86/sink-blockfreq.ll | 4 +- test/CodeGen/X86/sink-cheap-instructions.ll | 2 +- test/CodeGen/X86/sjlj-eh.ll | 72 + test/CodeGen/X86/slow-unaligned-mem.ll | 18 +- test/CodeGen/X86/sqrt-fastmath-mir.ll | 52 + test/CodeGen/X86/sqrt-fastmath.ll | 29 +- test/CodeGen/X86/sse-intel-ocl.ll | 2 +- .../CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll | 35 + test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 2303 ++++ test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll | 27 + test/CodeGen/X86/sse-intrinsics-x86.ll | 449 +- test/CodeGen/X86/sse1.ll | 15 + .../X86/sse2-intrinsics-fast-isel-x86_64.ll | 76 + test/CodeGen/X86/sse2-intrinsics-fast-isel.ll | 3849 +++++++ test/CodeGen/X86/sse2-intrinsics-x86-upgrade.ll | 178 +- test/CodeGen/X86/sse2-intrinsics-x86.ll | 937 +- test/CodeGen/X86/sse2.ll | 6 +- test/CodeGen/X86/sse3-avx-addsub-2.ll | 2 +- test/CodeGen/X86/sse3-avx-addsub.ll | 7 +- test/CodeGen/X86/sse3-intrinsics-fast-isel.ll | 13 +- test/CodeGen/X86/sse3.ll | 6 +- test/CodeGen/X86/sse41-intrinsics-fast-isel.ll | 1008 ++ test/CodeGen/X86/sse41-intrinsics-x86-upgrade.ll | 228 +- test/CodeGen/X86/sse41-intrinsics-x86.ll | 355 +- test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll | 196 - test/CodeGen/X86/sse41-pmovxrm.ll | 195 + test/CodeGen/X86/sse41.ll | 53 +- .../X86/sse42-intrinsics-fast-isel-x86_64.ll | 26 + test/CodeGen/X86/sse42-intrinsics-fast-isel.ll | 401 + test/CodeGen/X86/sse42-intrinsics-x86.ll | 197 +- test/CodeGen/X86/sse42.ll | 53 +- test/CodeGen/X86/sse4a-intrinsics-fast-isel.ll | 20 +- test/CodeGen/X86/sse4a-upgrade.ll | 39 + test/CodeGen/X86/sse4a.ll | 77 +- test/CodeGen/X86/sse_partial_update.ll | 84 +- test/CodeGen/X86/ssp-data-layout.ll | 2 +- test/CodeGen/X86/ssp-guard-spill.ll | 54 + test/CodeGen/X86/ssse3-intrinsics-fast-isel.ll | 28 +- test/CodeGen/X86/stack-align.ll | 28 + test/CodeGen/X86/stack-align2.ll | 5 + test/CodeGen/X86/stack-folding-fp-avx1.ll | 59 +- test/CodeGen/X86/stack-folding-fp-avx512vl.ll | 137 + test/CodeGen/X86/stack-folding-fp-sse42.ll | 18 + test/CodeGen/X86/stack-folding-int-avx2.ll | 53 +- test/CodeGen/X86/stack-folding-xop.ll | 40 +- test/CodeGen/X86/stack-protector-dbginfo.ll | 11 +- test/CodeGen/X86/stack-protector-msvc.ll | 40 + test/CodeGen/X86/stack-protector-target.ll | 27 + test/CodeGen/X86/stack-protector-weight.ll | 40 +- test/CodeGen/X86/stack-protector.ll | 462 + test/CodeGen/X86/stack_guard_remat.ll | 2 +- test/CodeGen/X86/stackguard-internal.ll | 15 + test/CodeGen/X86/stackmap-frame-setup.ll | 4 +- test/CodeGen/X86/stackmap-large-constants.ll | 2 +- test/CodeGen/X86/stackmap-liveness.ll | 16 +- test/CodeGen/X86/statepoint-allocas.ll | 4 +- test/CodeGen/X86/statepoint-invoke.ll | 4 +- test/CodeGen/X86/statepoint-stack-usage.ll | 2 +- test/CodeGen/X86/statepoint-stackmap-format.ll | 10 +- test/CodeGen/X86/statepoint-uniqueing.ll | 31 + test/CodeGen/X86/statepoint-vector-bad-spill.ll | 39 + test/CodeGen/X86/statepoint-vector.ll | 2 +- test/CodeGen/X86/stdarg.ll | 2 +- test/CodeGen/X86/store-narrow.ll | 12 +- test/CodeGen/X86/store-zero-and-minus-one.ll | 88 + test/CodeGen/X86/swift-return.ll | 206 + test/CodeGen/X86/swifterror.ll | 359 + test/CodeGen/X86/swiftself.ll | 62 + test/CodeGen/X86/switch-bt.ll | 2 +- test/CodeGen/X86/switch-density.ll | 81 + test/CodeGen/X86/switch-edge-weight.ll | 12 +- test/CodeGen/X86/switch-jump-table.ll | 2 +- test/CodeGen/X86/switch.ll | 77 +- test/CodeGen/X86/tail-call-attrs.ll | 4 +- test/CodeGen/X86/tail-call-casts.ll | 27 + .../X86/tail-call-parameter-attrs-mismatch.ll | 40 + test/CodeGen/X86/tail-merge-unreachable.ll | 34 + test/CodeGen/X86/tail-opts.ll | 2 +- test/CodeGen/X86/tailcall-stackalign.ll | 2 +- .../CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll | 133 + test/CodeGen/X86/tbm-intrinsics-fast-isel.ll | 216 + test/CodeGen/X86/tls-android.ll | 8 +- test/CodeGen/X86/tls-pie.ll | 8 +- test/CodeGen/X86/tls-windows-itanium.ll | 30 + test/CodeGen/X86/tls.ll | 15 + test/CodeGen/X86/trunc-to-bool.ll | 4 +- test/CodeGen/X86/twoaddr-coalesce.ll | 2 +- test/CodeGen/X86/uint_to_fp-2.ll | 13 +- test/CodeGen/X86/uint_to_fp.ll | 33 +- test/CodeGen/X86/umul-with-overflow.ll | 3 +- test/CodeGen/X86/unaligned-load.ll | 4 +- test/CodeGen/X86/unaligned-spill-folding.ll | 2 +- test/CodeGen/X86/unknown-location.ll | 5 +- test/CodeGen/X86/unreachableblockelim.ll | 21 + test/CodeGen/X86/unused_stackslots.ll | 246 + test/CodeGen/X86/update-terminator.mir | 57 + test/CodeGen/X86/urem-i8-constant.ll | 21 +- test/CodeGen/X86/urem-power-of-two.ll | 82 + test/CodeGen/X86/utf16-cfstrings.ll | 2 +- test/CodeGen/X86/v4f32-immediate.ll | 15 +- test/CodeGen/X86/v8i1-masks.ll | 70 +- test/CodeGen/X86/vararg-callee-cleanup.ll | 2 +- test/CodeGen/X86/vec-sign.ll | 30 - test/CodeGen/X86/vec_compare-sse4.ll | 81 +- test/CodeGen/X86/vec_ctbits.ll | 10 +- test/CodeGen/X86/vec_ext_inreg.ll | 74 +- test/CodeGen/X86/vec_extract-avx.ll | 177 +- test/CodeGen/X86/vec_extract-mmx.ll | 147 +- test/CodeGen/X86/vec_extract-sse4.ll | 115 +- test/CodeGen/X86/vec_extract.ll | 142 +- test/CodeGen/X86/vec_fabs.ll | 91 +- test/CodeGen/X86/vec_floor.ll | 361 +- test/CodeGen/X86/vec_fneg.ll | 99 +- test/CodeGen/X86/vec_fp_to_int.ll | 1 + test/CodeGen/X86/vec_fpext.ll | 152 +- test/CodeGen/X86/vec_fptrunc.ll | 168 + test/CodeGen/X86/vec_i64.ll | 43 +- test/CodeGen/X86/vec_ins_extract-1.ll | 87 +- test/CodeGen/X86/vec_ins_extract.ll | 3 +- test/CodeGen/X86/vec_insert-2.ll | 60 +- test/CodeGen/X86/vec_insert-3.ll | 23 +- test/CodeGen/X86/vec_insert-4.ll | 43 +- test/CodeGen/X86/vec_insert-5.ll | 166 +- test/CodeGen/X86/vec_insert-7.ll | 47 +- test/CodeGen/X86/vec_insert-8.ll | 57 +- test/CodeGen/X86/vec_insert-9.ll | 22 +- test/CodeGen/X86/vec_insert-mmx.ll | 90 +- test/CodeGen/X86/vec_int_to_fp.ll | 1697 ++- test/CodeGen/X86/vec_loadsingles.ll | 85 +- test/CodeGen/X86/vec_logical.ll | 99 +- test/CodeGen/X86/vec_partial.ll | 21 +- test/CodeGen/X86/vec_sdiv_to_shift.ll | 285 +- test/CodeGen/X86/vec_set-2.ll | 34 +- test/CodeGen/X86/vec_set-3.ll | 17 +- test/CodeGen/X86/vec_set-4.ll | 46 +- test/CodeGen/X86/vec_set-6.ll | 20 +- test/CodeGen/X86/vec_set-7.ll | 20 +- test/CodeGen/X86/vec_set-8.ll | 19 +- test/CodeGen/X86/vec_set-A.ll | 13 +- test/CodeGen/X86/vec_set-B.ll | 32 +- test/CodeGen/X86/vec_set-C.ll | 19 +- test/CodeGen/X86/vec_set-D.ll | 15 +- test/CodeGen/X86/vec_set-F.ll | 34 +- test/CodeGen/X86/vec_set-H.ll | 30 +- test/CodeGen/X86/vec_set.ll | 43 +- test/CodeGen/X86/vec_setcc.ll | 242 +- test/CodeGen/X86/vec_shift.ll | 41 +- test/CodeGen/X86/vec_shift2.ll | 34 +- test/CodeGen/X86/vec_shift3.ll | 41 +- test/CodeGen/X86/vec_shift4.ll | 64 +- test/CodeGen/X86/vec_shift5.ll | 217 +- test/CodeGen/X86/vec_shift6.ll | 225 +- test/CodeGen/X86/vec_shift7.ll | 23 +- test/CodeGen/X86/vec_ss_load_fold.ll | 109 +- test/CodeGen/X86/vec_uint_to_fp-fastmath.ll | 4 + test/CodeGen/X86/vector-bitreverse.ll | 3772 +++++++ test/CodeGen/X86/vector-blend.ll | 285 +- test/CodeGen/X86/vector-compare-combines.ll | 47 + test/CodeGen/X86/vector-compare-results.ll | 6625 ++++++++++++ test/CodeGen/X86/vector-gep.ll | 9 + test/CodeGen/X86/vector-half-conversions.ll | 3922 +++++++ test/CodeGen/X86/vector-idiv-sdiv-128.ll | 622 ++ test/CodeGen/X86/vector-idiv-sdiv-256.ll | 545 + test/CodeGen/X86/vector-idiv-sdiv-512.ll | 2392 +++++ test/CodeGen/X86/vector-idiv-udiv-128.ll | 592 ++ test/CodeGen/X86/vector-idiv-udiv-256.ll | 551 + test/CodeGen/X86/vector-idiv-udiv-512.ll | 2100 ++++ test/CodeGen/X86/vector-idiv.ll | 1297 +-- test/CodeGen/X86/vector-lzcnt-128.ll | 1216 +-- test/CodeGen/X86/vector-lzcnt-256.ll | 1378 +-- test/CodeGen/X86/vector-lzcnt-512.ll | 171 +- test/CodeGen/X86/vector-pcmp.ll | 495 + test/CodeGen/X86/vector-popcnt-512.ll | 288 +- test/CodeGen/X86/vector-rem.ll | 118 +- test/CodeGen/X86/vector-rotate-128.ll | 97 +- test/CodeGen/X86/vector-rotate-256.ll | 46 +- test/CodeGen/X86/vector-sext.ll | 834 +- test/CodeGen/X86/vector-shift-ashr-128.ll | 53 +- test/CodeGen/X86/vector-shift-ashr-256.ll | 44 +- test/CodeGen/X86/vector-shift-ashr-512.ll | 48 +- test/CodeGen/X86/vector-shift-lshr-128.ll | 71 +- test/CodeGen/X86/vector-shift-lshr-256.ll | 44 +- test/CodeGen/X86/vector-shift-lshr-512.ll | 30 +- test/CodeGen/X86/vector-shift-shl-128.ll | 32 +- test/CodeGen/X86/vector-shift-shl-256.ll | 11 +- test/CodeGen/X86/vector-shift-shl-512.ll | 10 +- test/CodeGen/X86/vector-shuffle-128-v16.ll | 81 +- test/CodeGen/X86/vector-shuffle-128-v2.ll | 142 +- test/CodeGen/X86/vector-shuffle-128-v4.ll | 211 +- test/CodeGen/X86/vector-shuffle-128-v8.ll | 82 +- test/CodeGen/X86/vector-shuffle-256-v16.ll | 338 +- test/CodeGen/X86/vector-shuffle-256-v32.ll | 180 +- test/CodeGen/X86/vector-shuffle-256-v4.ll | 105 +- test/CodeGen/X86/vector-shuffle-256-v8.ll | 250 +- test/CodeGen/X86/vector-shuffle-512-v16.ll | 125 + test/CodeGen/X86/vector-shuffle-512-v32.ll | 74 +- test/CodeGen/X86/vector-shuffle-512-v64.ll | 88 + test/CodeGen/X86/vector-shuffle-512-v8.ll | 364 +- test/CodeGen/X86/vector-shuffle-combining-avx.ll | 242 + test/CodeGen/X86/vector-shuffle-combining-avx2.ll | 324 + .../X86/vector-shuffle-combining-avx512bw.ll | 515 + test/CodeGen/X86/vector-shuffle-combining-ssse3.ll | 267 + test/CodeGen/X86/vector-shuffle-combining-xop.ll | 133 + test/CodeGen/X86/vector-shuffle-combining.ll | 99 +- test/CodeGen/X86/vector-shuffle-sse1.ll | 40 +- test/CodeGen/X86/vector-shuffle-sse41.ll | 59 + test/CodeGen/X86/vector-shuffle-v1.ll | 158 +- test/CodeGen/X86/vector-shuffle-variable-128.ll | 1321 +++ test/CodeGen/X86/vector-shuffle-variable-256.ll | 720 ++ test/CodeGen/X86/vector-trunc-math.ll | 5315 ++++++++++ test/CodeGen/X86/vector-trunc.ll | 44 +- test/CodeGen/X86/vector-tzcnt-128.ll | 818 +- test/CodeGen/X86/vector-tzcnt-256.ll | 446 +- test/CodeGen/X86/vector-tzcnt-512.ll | 693 +- test/CodeGen/X86/vector-zext.ll | 326 +- test/CodeGen/X86/viabs.ll | 703 +- ...gisters-cleared-in-machine-functions-liveins.ll | 4 +- test/CodeGen/X86/vselect-avx.ll | 102 +- test/CodeGen/X86/vselect-minmax.ll | 1 + test/CodeGen/X86/vzero-excess.ll | 94 + test/CodeGen/X86/warn-stack.ll | 2 +- test/CodeGen/X86/weak_def_can_be_hidden.ll | 8 +- test/CodeGen/X86/widen_bitops-0.ll | 307 + test/CodeGen/X86/widen_bitops-1.ll | 235 + test/CodeGen/X86/widen_compare-1.ll | 21 + test/CodeGen/X86/widen_conv-1.ll | 95 +- test/CodeGen/X86/widen_conv-2.ll | 25 +- test/CodeGen/X86/widen_conv-3.ll | 147 +- test/CodeGen/X86/widen_conv-4.ll | 173 +- test/CodeGen/X86/widen_load-1.ll | 4 +- test/CodeGen/X86/widen_load-2.ll | 221 +- test/CodeGen/X86/win-alloca-expander.ll | 154 + test/CodeGen/X86/win-catchpad-csrs.ll | 4 +- test/CodeGen/X86/win-catchpad-varargs.ll | 4 +- test/CodeGen/X86/win-catchpad.ll | 68 +- test/CodeGen/X86/win-cleanuppad.ll | 8 +- test/CodeGen/X86/win32-eh-states.ll | 16 +- test/CodeGen/X86/win32-eh.ll | 50 +- test/CodeGen/X86/win32-seh-catchpad-realign.ll | 2 +- test/CodeGen/X86/win32-seh-catchpad.ll | 8 +- test/CodeGen/X86/win32-seh-nested-finally.ll | 18 +- test/CodeGen/X86/win32_sret.ll | 47 +- test/CodeGen/X86/win64_eh.ll | 4 - test/CodeGen/X86/win_cst_pool.ll | 26 +- test/CodeGen/X86/x86-16.ll | 20 + test/CodeGen/X86/x86-32-intrcc.ll | 18 +- test/CodeGen/X86/x86-32-vector-calling-conv.ll | 24 +- test/CodeGen/X86/x86-64-flags-intrinsics.ll | 2 +- test/CodeGen/X86/x86-64-intrcc.ll | 21 +- test/CodeGen/X86/x86-64-pic.ll | 8 + test/CodeGen/X86/x86-64-plt-relative-reloc.ll | 19 + test/CodeGen/X86/x86-64-stack-and-frame-ptr.ll | 6 +- test/CodeGen/X86/x86-big-ret.ll | 22 + test/CodeGen/X86/x86-flags-intrinsics.ll | 2 +- test/CodeGen/X86/x86-interrupt_cc.ll | 33 + test/CodeGen/X86/x86-interrupt_cld.ll | 17 + test/CodeGen/X86/x86-interrupt_vzeroupper.ll | 19 + test/CodeGen/X86/x86-plt-relative-reloc.ll | 16 + test/CodeGen/X86/x86-shrink-wrap-unwind.ll | 4 +- test/CodeGen/X86/x86-shrink-wrapping.ll | 2 - test/CodeGen/X86/x86-upgrade-avx-vbroadcast.ll | 29 +- test/CodeGen/X86/x86-upgrade-avx2-vbroadcast.ll | 12 +- test/CodeGen/X86/x87.ll | 55 + test/CodeGen/X86/xaluo.ll | 26 +- test/CodeGen/X86/xmulo.ll | 18 +- test/CodeGen/X86/xop-intrinsics-fast-isel.ll | 1111 ++ test/CodeGen/X86/xop-intrinsics-x86_64-upgrade.ll | 727 ++ test/CodeGen/X86/xop-intrinsics-x86_64.ll | 950 +- test/CodeGen/X86/xop-mask-comments.ll | 188 + test/CodeGen/X86/xray-attribute-instrumentation.ll | 13 + .../X86/xray-selective-instrumentation-miss.ll | 9 + test/CodeGen/X86/xray-selective-instrumentation.ll | 9 + test/CodeGen/X86/zext-fold.ll | 7 +- test/CodeGen/XCore/align.ll | 4 +- test/CodeGen/XCore/dwarf_debug.ll | 5 +- test/CodeGen/XCore/epilogue_prologue.ll | 4 +- test/CodeGen/XCore/linkage.ll | 5 +- test/CodeGen/XCore/scavenging.ll | 2 +- test/CodeGen/XCore/threads.ll | 4 +- 2455 files changed, 205633 insertions(+), 47156 deletions(-) create mode 100644 test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll create mode 100644 test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir create mode 100644 test/CodeGen/AArch64/aarch64-DAGCombine-findBetterNeighborChains-crash.ll delete mode 100644 test/CodeGen/AArch64/aarch64-deferred-spilling.ll create mode 100644 test/CodeGen/AArch64/aarch64-interleaved-accesses-extract-user.ll create mode 100644 test/CodeGen/AArch64/aarch64-stp-cluster.ll create mode 100644 test/CodeGen/AArch64/aarch64-tbz.ll create mode 100644 test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll create mode 100644 test/CodeGen/AArch64/arm64-csldst-mmo.ll create mode 100644 test/CodeGen/AArch64/arm64-detect-vec-redux.ll create mode 100644 test/CodeGen/AArch64/arm64-fma-combines.ll create mode 100644 test/CodeGen/AArch64/arm64-fml-combines.ll create mode 100644 test/CodeGen/AArch64/arm64-ldp-cluster.ll create mode 100644 test/CodeGen/AArch64/arm64-misched-multimmo.ll create mode 100644 test/CodeGen/AArch64/arm64-regress-opt-cmp.mir create mode 100644 test/CodeGen/AArch64/bitfield-extract.ll create mode 100644 test/CodeGen/AArch64/bswap-known-bits.ll create mode 100644 test/CodeGen/AArch64/cmpxchg-O0.ll create mode 100644 test/CodeGen/AArch64/div_minsize.ll create mode 100644 test/CodeGen/AArch64/gep-nullptr.ll create mode 100644 test/CodeGen/AArch64/inlineasm-X-allocation.ll create mode 100644 test/CodeGen/AArch64/inlineasm-X-constraint.ll create mode 100644 test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll create mode 100644 test/CodeGen/AArch64/lower-range-metadata-func-call.ll create mode 100644 test/CodeGen/AArch64/machine-copy-remove.ll create mode 100644 test/CodeGen/AArch64/merge-store-dependency.ll create mode 100644 test/CodeGen/AArch64/movimm-wzr.mir create mode 100644 test/CodeGen/AArch64/neg-imm.ll create mode 100644 test/CodeGen/AArch64/no-quad-ldp-stp.ll create mode 100644 test/CodeGen/AArch64/optimize-cond-branch.ll create mode 100644 test/CodeGen/AArch64/pie.ll create mode 100644 test/CodeGen/AArch64/preferred-alignment.ll create mode 100644 test/CodeGen/AArch64/preserve_mostcc.ll create mode 100644 test/CodeGen/AArch64/recp-fastmath.ll create mode 100644 test/CodeGen/AArch64/rem_crash.ll create mode 100644 test/CodeGen/AArch64/sqrt-fastmath.ll create mode 100644 test/CodeGen/AArch64/stack-protector-target.ll create mode 100644 test/CodeGen/AArch64/subs-to-sub-opt.ll create mode 100644 test/CodeGen/AArch64/swifterror.ll create mode 100644 test/CodeGen/AArch64/swiftself.ll create mode 100644 test/CodeGen/AArch64/tailcall-ccmismatch.ll create mode 100644 test/CodeGen/AArch64/tailmerging_in_mbp.ll create mode 100644 test/CodeGen/AArch64/vector_merge_dep_check.ll create mode 100644 test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll delete mode 100644 test/CodeGen/AMDGPU/address-space.ll create mode 100644 test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll create mode 100644 test/CodeGen/AMDGPU/amdgcn.private-memory.ll create mode 100644 test/CodeGen/AMDGPU/amdgcn.work-item-intrinsics.ll create mode 100644 test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll create mode 100644 test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll create mode 100644 test/CodeGen/AMDGPU/amdgpu.private-memory.ll create mode 100644 test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll create mode 100644 test/CodeGen/AMDGPU/and-gcn.ll create mode 100644 test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll create mode 100644 test/CodeGen/AMDGPU/bfm.ll create mode 100644 test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll create mode 100644 test/CodeGen/AMDGPU/branch-uniformity.ll create mode 100644 test/CodeGen/AMDGPU/bug-vopc-commute.ll create mode 100644 test/CodeGen/AMDGPU/captured-frame-index.ll create mode 100644 test/CodeGen/AMDGPU/cf-loop-on-constant.ll create mode 100644 test/CodeGen/AMDGPU/cgp-bitfield-extract.ll create mode 100644 test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll create mode 100644 test/CodeGen/AMDGPU/coalescer_distribute.ll create mode 100644 test/CodeGen/AMDGPU/convergent-inlineasm.ll create mode 100644 test/CodeGen/AMDGPU/cube.ll create mode 100644 test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll create mode 100644 test/CodeGen/AMDGPU/debugger-emit-prologue.ll create mode 100644 test/CodeGen/AMDGPU/debugger-insert-nops.ll create mode 100644 test/CodeGen/AMDGPU/debugger-reserve-regs.ll create mode 100644 test/CodeGen/AMDGPU/detect-dead-lanes.mir delete mode 100644 test/CodeGen/AMDGPU/dot4-folding.ll create mode 100644 test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll delete mode 100644 test/CodeGen/AMDGPU/extract-vector-elt-i64.ll create mode 100644 test/CodeGen/AMDGPU/extract_vector_elt-f64.ll create mode 100644 test/CodeGen/AMDGPU/extract_vector_elt-i16.ll create mode 100644 test/CodeGen/AMDGPU/extract_vector_elt-i64.ll create mode 100644 test/CodeGen/AMDGPU/extract_vector_elt-i8.ll delete mode 100644 test/CodeGen/AMDGPU/extract_vector_elt_i16.ll create mode 100644 test/CodeGen/AMDGPU/extractelt-to-trunc.ll create mode 100644 test/CodeGen/AMDGPU/fcanonicalize.ll create mode 100644 test/CodeGen/AMDGPU/flat_atomics.ll create mode 100644 test/CodeGen/AMDGPU/flat_atomics_i64.ll create mode 100644 test/CodeGen/AMDGPU/fmed3.ll create mode 100644 test/CodeGen/AMDGPU/fract.f64.ll create mode 100644 test/CodeGen/AMDGPU/fract.ll create mode 100644 test/CodeGen/AMDGPU/fsqrt.f64.ll delete mode 100644 test/CodeGen/AMDGPU/global-extload-i1.ll delete mode 100644 test/CodeGen/AMDGPU/global-extload-i16.ll delete mode 100644 test/CodeGen/AMDGPU/global-extload-i32.ll delete mode 100644 test/CodeGen/AMDGPU/global-extload-i8.ll create mode 100644 test/CodeGen/AMDGPU/global-variable-relocs.ll delete mode 100644 test/CodeGen/AMDGPU/global-zero-initializer.ll create mode 100644 test/CodeGen/AMDGPU/global_atomics_i64.ll delete mode 100644 test/CodeGen/AMDGPU/gv-const-addrspace-fail.ll create mode 100644 test/CodeGen/AMDGPU/gv-offset-folding.ll create mode 100644 test/CodeGen/AMDGPU/hsa-default-device.ll create mode 100644 test/CodeGen/AMDGPU/hsa-fp-mode.ll create mode 100644 test/CodeGen/AMDGPU/hsa-func.ll create mode 100644 test/CodeGen/AMDGPU/indirect-addressing-undef.mir create mode 100644 test/CodeGen/AMDGPU/invalid-addrspacecast.ll create mode 100644 test/CodeGen/AMDGPU/kernarg-stack-alignment.ll create mode 100644 test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll create mode 100644 test/CodeGen/AMDGPU/large-work-group-registers.ll create mode 100644 test/CodeGen/AMDGPU/lds-alignment.ll create mode 100644 test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll create mode 100644 test/CodeGen/AMDGPU/liveness.mir delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.global.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.local.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.bfi.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.class.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.div_scale.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.imul24.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.ldexp.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.legacy.rsq.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.f64.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.read.workdim.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.tex.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.trig_preop.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.trunc.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.AMDGPU.umul24.ll create mode 100644 test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.imageload.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.resinfo.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.sample-masked.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.sample.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.sampled.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.SI.tid.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.class.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.image.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll create mode 100644 test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.amdgpu.dp4.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.dot4.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll create mode 100644 test/CodeGen/AMDGPU/llvm.r600.tex.ll delete mode 100644 test/CodeGen/AMDGPU/llvm.sqrt.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-f64.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-i1.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-i16.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-i32.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-i64.ll create mode 100644 test/CodeGen/AMDGPU/load-constant-i8.ll create mode 100644 test/CodeGen/AMDGPU/load-global-f32.ll create mode 100644 test/CodeGen/AMDGPU/load-global-f64.ll create mode 100644 test/CodeGen/AMDGPU/load-global-i1.ll create mode 100644 test/CodeGen/AMDGPU/load-global-i16.ll create mode 100644 test/CodeGen/AMDGPU/load-global-i32.ll create mode 100644 test/CodeGen/AMDGPU/load-global-i64.ll create mode 100644 test/CodeGen/AMDGPU/load-global-i8.ll delete mode 100644 test/CodeGen/AMDGPU/load-i1.ll create mode 100644 test/CodeGen/AMDGPU/load-local-f32.ll create mode 100644 test/CodeGen/AMDGPU/load-local-f64.ll create mode 100644 test/CodeGen/AMDGPU/load-local-i1.ll create mode 100644 test/CodeGen/AMDGPU/load-local-i16.ll create mode 100644 test/CodeGen/AMDGPU/load-local-i32.ll create mode 100644 test/CodeGen/AMDGPU/load-local-i64.ll create mode 100644 test/CodeGen/AMDGPU/load-local-i8.ll create mode 100644 test/CodeGen/AMDGPU/load-weird-sizes.ll delete mode 100644 test/CodeGen/AMDGPU/load.ll delete mode 100644 test/CodeGen/AMDGPU/load.vec.ll delete mode 100644 test/CodeGen/AMDGPU/load64.ll delete mode 100644 test/CodeGen/AMDGPU/local-memory-two-objects.ll create mode 100644 test/CodeGen/AMDGPU/local-memory.amdgcn.ll create mode 100644 test/CodeGen/AMDGPU/local-memory.r600.ll create mode 100644 test/CodeGen/AMDGPU/local-stack-slot-bug.ll create mode 100644 test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll create mode 100644 test/CodeGen/AMDGPU/mad24-get-global-id.ll create mode 100644 test/CodeGen/AMDGPU/multilevel-break.ll create mode 100644 test/CodeGen/AMDGPU/over-max-lds-size.ll create mode 100644 test/CodeGen/AMDGPU/private-element-size.ll create mode 100644 test/CodeGen/AMDGPU/private-memory-r600.ll delete mode 100644 test/CodeGen/AMDGPU/private-memory.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-globals.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-lifetime.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-no-opts.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-shaders.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll create mode 100644 test/CodeGen/AMDGPU/promote-alloca-volatile.ll create mode 100644 test/CodeGen/AMDGPU/r600.private-memory.ll create mode 100644 test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll create mode 100644 test/CodeGen/AMDGPU/rcp-pattern.ll create mode 100644 test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll create mode 100644 test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll create mode 100644 test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll create mode 100644 test/CodeGen/AMDGPU/read_register.ll create mode 100644 test/CodeGen/AMDGPU/readcyclecounter.ll create mode 100644 test/CodeGen/AMDGPU/reduce-load-width-alignment.ll create mode 100644 test/CodeGen/AMDGPU/reduce-store-width-alignment.ll create mode 100644 test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll create mode 100644 test/CodeGen/AMDGPU/rename-disconnected-bug.ll create mode 100644 test/CodeGen/AMDGPU/rename-independent-subregs.mir create mode 100644 test/CodeGen/AMDGPU/ret_jump.ll create mode 100644 test/CodeGen/AMDGPU/runtime-metadata.ll create mode 100644 test/CodeGen/AMDGPU/s_addk_i32.ll create mode 100644 test/CodeGen/AMDGPU/s_mulk_i32.ll create mode 100644 test/CodeGen/AMDGPU/selected-stack-object.ll create mode 100644 test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll create mode 100644 test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll create mode 100644 test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll create mode 100644 test/CodeGen/AMDGPU/shift-i64-opts.ll delete mode 100644 test/CodeGen/AMDGPU/si-annotate-cf-assertion.ll create mode 100644 test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll create mode 100644 test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll create mode 100644 test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll create mode 100644 test/CodeGen/AMDGPU/skip-if-dead.ll create mode 100644 test/CodeGen/AMDGPU/smed3.ll create mode 100644 test/CodeGen/AMDGPU/smrd-vccz-bug.ll create mode 100644 test/CodeGen/AMDGPU/split-smrd.ll create mode 100644 test/CodeGen/AMDGPU/target-cpu.ll create mode 100644 test/CodeGen/AMDGPU/trap.ll create mode 100644 test/CodeGen/AMDGPU/trunc-bitcast-vector.ll create mode 100644 test/CodeGen/AMDGPU/umed3.ll create mode 100644 test/CodeGen/AMDGPU/undefined-subreg-liverange.ll create mode 100644 test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll create mode 100644 test/CodeGen/AMDGPU/uniform-cfg.ll create mode 100644 test/CodeGen/AMDGPU/uniform-crash.ll create mode 100644 test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll create mode 100644 test/CodeGen/AMDGPU/unknown-processor.ll create mode 100644 test/CodeGen/AMDGPU/vector-extract-insert.ll create mode 100644 test/CodeGen/AMDGPU/vi-removed-intrinsics.ll create mode 100644 test/CodeGen/AMDGPU/waitcnt-flat.ll delete mode 100644 test/CodeGen/AMDGPU/work-item-intrinsics.ll create mode 100644 test/CodeGen/AMDGPU/wqm.ll create mode 100644 test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll create mode 100644 test/CodeGen/AMDGPU/write_register.ll create mode 100644 test/CodeGen/AMDGPU/zext-i64-bit-operand.ll create mode 100644 test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll create mode 100644 test/CodeGen/ARM/ARMLoadStoreDBG.mir create mode 100644 test/CodeGen/ARM/Windows/builtin_longjmp.ll create mode 100644 test/CodeGen/ARM/Windows/dbzchk.ll create mode 100644 test/CodeGen/ARM/Windows/dllexport.ll delete mode 100644 test/CodeGen/ARM/Windows/overflow.ll create mode 100644 test/CodeGen/ARM/Windows/tls.ll create mode 100644 test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll create mode 100644 test/CodeGen/ARM/cdp.ll create mode 100644 test/CodeGen/ARM/cdp2.ll create mode 100644 test/CodeGen/ARM/cmpxchg-O0.ll create mode 100644 test/CodeGen/ARM/default-reloc.ll create mode 100644 test/CodeGen/ARM/fast-isel-pie.ll create mode 100644 test/CodeGen/ARM/inlineasm-X-allocation.ll create mode 100644 test/CodeGen/ARM/inlineasm-X-constraint.ll create mode 100644 test/CodeGen/ARM/interval-update-remat.ll create mode 100644 test/CodeGen/ARM/intrinsics-coprocessor.ll delete mode 100644 test/CodeGen/ARM/intrinsics.ll create mode 100644 test/CodeGen/ARM/invalidated-save-point.ll create mode 100644 test/CodeGen/ARM/ldc2l.ll create mode 100644 test/CodeGen/ARM/ldm-base-writeback.ll create mode 100644 test/CodeGen/ARM/litpool-licm.ll create mode 100644 test/CodeGen/ARM/local-call.ll create mode 100644 test/CodeGen/ARM/macho-frame-offset.ll create mode 100644 test/CodeGen/ARM/memcpy-no-inline.ll create mode 100644 test/CodeGen/ARM/minsize-call-cse.ll create mode 100644 test/CodeGen/ARM/msr-it-block.ll create mode 100644 test/CodeGen/ARM/pie.ll create mode 100644 test/CodeGen/ARM/plt-relative-reloc.ll create mode 100644 test/CodeGen/ARM/pr26669.ll create mode 100644 test/CodeGen/ARM/rem_crash.ll delete mode 100644 test/CodeGen/ARM/smulw.ll create mode 100644 test/CodeGen/ARM/special-reg-v8m-base.ll create mode 100644 test/CodeGen/ARM/special-reg-v8m-main.ll create mode 100644 test/CodeGen/ARM/ssat.ll create mode 100644 test/CodeGen/ARM/static-addr-hoisting.ll create mode 100644 test/CodeGen/ARM/stc2.ll create mode 100644 test/CodeGen/ARM/swift-ios.ll create mode 100644 test/CodeGen/ARM/swift-return.ll create mode 100644 test/CodeGen/ARM/swifterror.ll create mode 100644 test/CodeGen/ARM/swiftself.ll create mode 100644 test/CodeGen/ARM/t2-shrink-ldrpost.ll create mode 100644 test/CodeGen/ARM/tail-call-builtin.ll create mode 100644 test/CodeGen/ARM/thumb-stub.ll create mode 100644 test/CodeGen/ARM/urem-opt-size.ll create mode 100644 test/CodeGen/ARM/wide-compares.ll create mode 100644 test/CodeGen/BPF/sdiv_error.ll delete mode 100644 test/CodeGen/CPP/2007-06-16-Funcname.ll delete mode 100644 test/CodeGen/CPP/2009-05-01-Long-Double.ll delete mode 100644 test/CodeGen/CPP/2009-05-04-CondBr.ll delete mode 100644 test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll delete mode 100644 test/CodeGen/CPP/atomic.ll delete mode 100644 test/CodeGen/CPP/attributes.ll delete mode 100644 test/CodeGen/CPP/gep.ll delete mode 100644 test/CodeGen/CPP/lit.local.cfg delete mode 100644 test/CodeGen/Generic/Makefile create mode 100644 test/CodeGen/Generic/dont-remove-empty-preheader.ll delete mode 100644 test/CodeGen/Generic/run-pass.ll create mode 100644 test/CodeGen/Generic/vector-redux.ll create mode 100644 test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll create mode 100644 test/CodeGen/Hexagon/avoid-predspill.ll create mode 100644 test/CodeGen/Hexagon/bit-extractu-half.ll create mode 100644 test/CodeGen/Hexagon/bitconvert-vector.ll create mode 100644 test/CodeGen/Hexagon/block-ranges-nodef.ll create mode 100644 test/CodeGen/Hexagon/branch-non-mbb.ll create mode 100644 test/CodeGen/Hexagon/builtin-prefetch-offset.ll create mode 100644 test/CodeGen/Hexagon/builtin-prefetch.ll create mode 100644 test/CodeGen/Hexagon/callr-dep-edge.ll create mode 100644 test/CodeGen/Hexagon/cfi-offset.ll create mode 100644 test/CodeGen/Hexagon/circ-load-isel.ll create mode 100644 test/CodeGen/Hexagon/const64.ll create mode 100644 test/CodeGen/Hexagon/csr-func-usedef.ll create mode 100644 test/CodeGen/Hexagon/eliminate-pred-spill.ll create mode 100644 test/CodeGen/Hexagon/expand-condsets-pred-undef.ll create mode 100644 test/CodeGen/Hexagon/ifcvt-diamond-bad.ll create mode 100644 test/CodeGen/Hexagon/inline-asm-qv.ll create mode 100644 test/CodeGen/Hexagon/insert4.ll create mode 100644 test/CodeGen/Hexagon/intrinsics/system_user.ll create mode 100644 test/CodeGen/Hexagon/memops-stack.ll create mode 100644 test/CodeGen/Hexagon/misched-top-rptracker-sync.ll create mode 100644 test/CodeGen/Hexagon/opt-addr-mode.ll create mode 100644 test/CodeGen/Hexagon/packetize-tailcall-arg.ll create mode 100644 test/CodeGen/Hexagon/peephole-op-swap.ll create mode 100644 test/CodeGen/Hexagon/pic-local.ll create mode 100644 test/CodeGen/Hexagon/pic-regusage.ll create mode 100644 test/CodeGen/Hexagon/rdf-copy-undef2.ll create mode 100644 test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll create mode 100644 test/CodeGen/Hexagon/rdf-inline-asm.ll create mode 100644 test/CodeGen/Hexagon/rdf-reset-kills.ll create mode 100644 test/CodeGen/Hexagon/reg-scavengebug-3.ll create mode 100644 test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll create mode 100644 test/CodeGen/Hexagon/restore-single-reg.ll create mode 100644 test/CodeGen/Hexagon/ret-struct-by-val.ll create mode 100644 test/CodeGen/Hexagon/runtime-stkchk.ll create mode 100644 test/CodeGen/Hexagon/sdata-array.ll create mode 100644 test/CodeGen/Hexagon/sdata-basic.ll create mode 100644 test/CodeGen/Hexagon/section_7275.ll create mode 100644 test/CodeGen/Hexagon/select-instr-align.ll create mode 100644 test/CodeGen/Hexagon/store-shift.ll create mode 100644 test/CodeGen/Hexagon/storerinewabs.ll create mode 100644 test/CodeGen/Hexagon/tail-dup-subreg-map.ll create mode 100644 test/CodeGen/Hexagon/tls_pic.ll create mode 100644 test/CodeGen/Hexagon/tls_static.ll create mode 100644 test/CodeGen/Hexagon/v60-cur.ll create mode 100644 test/CodeGen/Hexagon/vec-pred-spill1.ll create mode 100644 test/CodeGen/Hexagon/vector-align.ll create mode 100644 test/CodeGen/Hexagon/vload-postinc-sel.ll create mode 100644 test/CodeGen/Hexagon/vselect-pseudo.ll create mode 100644 test/CodeGen/Hexagon/vsplat-isel.ll create mode 100644 test/CodeGen/Lanai/codemodel.ll create mode 100644 test/CodeGen/Lanai/comparisons_i32.ll create mode 100644 test/CodeGen/Lanai/comparisons_i64.ll create mode 100644 test/CodeGen/Lanai/constant_multiply.ll create mode 100644 test/CodeGen/Lanai/delay_filler.ll create mode 100644 test/CodeGen/Lanai/i32.ll create mode 100644 test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll create mode 100644 test/CodeGen/Lanai/lit.local.cfg create mode 100644 test/CodeGen/Lanai/mem_alu_combiner.ll create mode 100644 test/CodeGen/Lanai/multiply.ll create mode 100644 test/CodeGen/Lanai/rshift64.ll create mode 100644 test/CodeGen/Lanai/select.ll create mode 100644 test/CodeGen/Lanai/set_and_hi.ll create mode 100644 test/CodeGen/Lanai/shift.ll create mode 100644 test/CodeGen/Lanai/stack-frame.ll create mode 100644 test/CodeGen/Lanai/sub-cmp-peephole.ll create mode 100644 test/CodeGen/Lanai/subword.ll create mode 100644 test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir create mode 100644 test/CodeGen/MIR/AArch64/machine-dead-copy.mir create mode 100644 test/CodeGen/MIR/AArch64/machine-scheduler.mir delete mode 100644 test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir create mode 100644 test/CodeGen/MIR/ARM/imm-peephole-arm.mir create mode 100644 test/CodeGen/MIR/ARM/imm-peephole-thumb.mir create mode 100644 test/CodeGen/MIR/Generic/multiRunPass.mir create mode 100644 test/CodeGen/MIR/Hexagon/anti-dep-partial.mir create mode 100644 test/CodeGen/MIR/Hexagon/lit.local.cfg create mode 100644 test/CodeGen/MIR/Lanai/lit.local.cfg create mode 100644 test/CodeGen/MIR/Lanai/peephole-compare.mir delete mode 100644 test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir create mode 100644 test/CodeGen/MIR/X86/generic-instr-type-error.mir create mode 100644 test/CodeGen/MIR/X86/generic-virtual-registers.mir create mode 100644 test/CodeGen/MIR/X86/subreg-on-physreg.mir create mode 100644 test/CodeGen/MIR/X86/subregister-index-operands.mir create mode 100644 test/CodeGen/MIR/X86/unknown-subregister-index-op.mir delete mode 100644 test/CodeGen/MIR/lit.local.cfg create mode 100644 test/CodeGen/MSP430/spill-to-stack.ll create mode 100644 test/CodeGen/Mips/assertzext-trunc.ll create mode 100644 test/CodeGen/Mips/atomicCmpSwapPW.ll create mode 100644 test/CodeGen/Mips/cannot-copy-registers.ll create mode 100644 test/CodeGen/Mips/cconv/roundl-call.ll create mode 100644 test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll create mode 100644 test/CodeGen/Mips/compactbranches/compact-branch-policy.ll create mode 100644 test/CodeGen/Mips/compactbranches/compact-branches.ll create mode 100644 test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll create mode 100644 test/CodeGen/Mips/cstmaterialization/stack.ll create mode 100644 test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll create mode 100644 test/CodeGen/Mips/llvm-ir/lh_lhu.ll create mode 100644 test/CodeGen/Mips/llvm-ir/not.ll create mode 100644 test/CodeGen/Mips/llvm-ir/select-dbl.ll create mode 100644 test/CodeGen/Mips/llvm-ir/select-flt.ll create mode 100644 test/CodeGen/Mips/llvm-ir/select-int.ll delete mode 100644 test/CodeGen/Mips/llvm-ir/select.ll create mode 100644 test/CodeGen/Mips/lw16-base-reg.ll create mode 100644 test/CodeGen/Mips/micromips-lwc1-swc1.ll delete mode 100644 test/CodeGen/Mips/micromips-zero-mat-uses.ll create mode 100644 test/CodeGen/Mips/mips-shf-gprel.s create mode 100644 test/CodeGen/Mips/private-addr.ll create mode 100644 test/CodeGen/Mips/selectiondag-optlevel.ll create mode 100644 test/CodeGen/Mips/thread-pointer.ll create mode 100644 test/CodeGen/NVPTX/MachineSink-call.ll create mode 100644 test/CodeGen/NVPTX/MachineSink-convergent.ll create mode 100644 test/CodeGen/NVPTX/TailDuplication-convergent.ll create mode 100644 test/CodeGen/NVPTX/alias.ll create mode 100644 test/CodeGen/NVPTX/bug26185-2.ll create mode 100644 test/CodeGen/NVPTX/bug26185.ll create mode 100644 test/CodeGen/NVPTX/convergent-mir-call.ll create mode 100644 test/CodeGen/NVPTX/debug-file-loc.ll create mode 100644 test/CodeGen/NVPTX/disable-opt.ll create mode 100644 test/CodeGen/NVPTX/global-ctor-empty.ll create mode 100644 test/CodeGen/NVPTX/global-ctor.ll create mode 100644 test/CodeGen/NVPTX/global-dtor.ll create mode 100644 test/CodeGen/NVPTX/global-visibility.ll create mode 100644 test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll create mode 100644 test/CodeGen/NVPTX/shfl.ll create mode 100644 test/CodeGen/NVPTX/sm-version-60.ll create mode 100644 test/CodeGen/NVPTX/sm-version-61.ll create mode 100644 test/CodeGen/NVPTX/sm-version-62.ll create mode 100644 test/CodeGen/NVPTX/speculative-execution-divergent-target.ll create mode 100644 test/CodeGen/NVPTX/zeroext-32bit.ll create mode 100644 test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll create mode 100644 test/CodeGen/PowerPC/2016-04-17-combine.ll create mode 100644 test/CodeGen/PowerPC/2016-04-28-setjmp.ll create mode 100644 test/CodeGen/PowerPC/aggressive-anti-dep-breaker-subreg.ll create mode 100644 test/CodeGen/PowerPC/andc.ll create mode 100644 test/CodeGen/PowerPC/asm-printer-topological-order.ll create mode 100644 test/CodeGen/PowerPC/cannonicalize-vector-shifts.ll create mode 100644 test/CodeGen/PowerPC/combine-to-pre-index-store-crash.ll create mode 100644 test/CodeGen/PowerPC/ctr-minmaxnum.ll create mode 100644 test/CodeGen/PowerPC/ctrloops-softfloat.ll create mode 100644 test/CodeGen/PowerPC/cxx_tlscc64.ll create mode 100644 test/CodeGen/PowerPC/direct-move-profit.ll create mode 100644 test/CodeGen/PowerPC/ext-bool-trunc-repl.ll create mode 100644 test/CodeGen/PowerPC/fast-isel-fcmp-nan.ll create mode 100644 test/CodeGen/PowerPC/fast-isel-fpconv.ll create mode 100644 test/CodeGen/PowerPC/fast-isel-i64offset.ll create mode 100644 test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll create mode 100644 test/CodeGen/PowerPC/indirect-hidden.ll create mode 100644 test/CodeGen/PowerPC/inline-asm-scalar-to-vector-error.ll create mode 100644 test/CodeGen/PowerPC/load-two-flts.ll create mode 100644 test/CodeGen/PowerPC/load-v4i8-improved.ll create mode 100644 test/CodeGen/PowerPC/multi-return.ll create mode 100644 test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll create mode 100644 test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir create mode 100644 test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll create mode 100644 test/CodeGen/PowerPC/pie.ll create mode 100644 test/CodeGen/PowerPC/ppc32-align-long-double-sf.ll create mode 100644 test/CodeGen/PowerPC/ppc32-constant-BE-ppcf128.ll create mode 100644 test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll create mode 100644 test/CodeGen/PowerPC/ppc64-sibcall.ll create mode 100644 test/CodeGen/PowerPC/ppcf128sf.ll delete mode 100644 test/CodeGen/PowerPC/pr25802.ll create mode 100644 test/CodeGen/PowerPC/pr26180.ll create mode 100644 test/CodeGen/PowerPC/pr26378.ll create mode 100644 test/CodeGen/PowerPC/pr26617.ll create mode 100644 test/CodeGen/PowerPC/pr27078.ll create mode 100644 test/CodeGen/PowerPC/pr27350.ll create mode 100644 test/CodeGen/PowerPC/pr28130.ll create mode 100644 test/CodeGen/PowerPC/qpx-load-splat.ll create mode 100644 test/CodeGen/PowerPC/remove-redundant-moves.ll create mode 100644 test/CodeGen/PowerPC/rlwinm-zero-ext.ll delete mode 100644 test/CodeGen/PowerPC/subsumes-pred-regs.ll create mode 100644 test/CodeGen/PowerPC/swaps-le-7.ll create mode 100644 test/CodeGen/PowerPC/tailcall-string-rvo.ll create mode 100644 test/CodeGen/PowerPC/thread-pointer.ll create mode 100644 test/CodeGen/PowerPC/vec_abs.ll create mode 100644 test/CodeGen/PowerPC/vsx-word-splats.ll create mode 100644 test/CodeGen/SPARC/LeonFixCALLPassUT.ll create mode 100755 test/CodeGen/SPARC/LeonFixFSMULDPassUT.ll create mode 100644 test/CodeGen/SPARC/LeonInsertNOPLoad.ll create mode 100755 test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll create mode 100644 test/CodeGen/SPARC/LeonInsertNOPsDoublePrecision.ll create mode 100644 test/CodeGen/SPARC/LeonItinerariesUT.ll create mode 100644 test/CodeGen/SPARC/LeonPreventRoundChangePassUT.ll create mode 100755 test/CodeGen/SPARC/LeonReplaceFMULSPassUT.ll create mode 100644 test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll create mode 100755 test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll create mode 100644 test/CodeGen/SPARC/func-addr.ll create mode 100755 test/CodeGen/SPARC/sjlj.ll create mode 100644 test/CodeGen/SPARC/soft-float.ll create mode 100644 test/CodeGen/SPARC/stack-protector.ll create mode 100644 test/CodeGen/SPARC/thread-pointer.ll create mode 100644 test/CodeGen/SPARC/vector-call.ll create mode 100644 test/CodeGen/SPARC/zerostructcall.ll create mode 100644 test/CodeGen/SystemZ/and-xor-01.ll create mode 100644 test/CodeGen/SystemZ/args-09.ll create mode 100644 test/CodeGen/SystemZ/args-10.ll create mode 100644 test/CodeGen/SystemZ/atomic-fence-01.ll create mode 100644 test/CodeGen/SystemZ/atomic-fence-02.ll create mode 100644 test/CodeGen/SystemZ/backchain.ll create mode 100644 test/CodeGen/SystemZ/bswap-06.ll create mode 100644 test/CodeGen/SystemZ/bswap-07.ll create mode 100644 test/CodeGen/SystemZ/builtins.ll create mode 100644 test/CodeGen/SystemZ/call-04.ll create mode 100644 test/CodeGen/SystemZ/call-05.ll create mode 100644 test/CodeGen/SystemZ/cmpxchg-05.ll create mode 100644 test/CodeGen/SystemZ/cond-li.ll create mode 100644 test/CodeGen/SystemZ/dyn-alloca-offset.ll create mode 100644 test/CodeGen/SystemZ/fp-move-12.ll create mode 100644 test/CodeGen/SystemZ/frameaddr-01.ll create mode 100644 test/CodeGen/SystemZ/memchr-nobuiltin.ll create mode 100644 test/CodeGen/SystemZ/memcmp-nobuiltin.ll create mode 100644 test/CodeGen/SystemZ/pie.ll create mode 100644 test/CodeGen/SystemZ/ret-addr-01.ll create mode 100644 test/CodeGen/SystemZ/rot-01.ll create mode 100644 test/CodeGen/SystemZ/rot-02.ll create mode 100644 test/CodeGen/SystemZ/shift-11.ll create mode 100644 test/CodeGen/SystemZ/shift-12.ll create mode 100644 test/CodeGen/SystemZ/stack-guard.ll create mode 100644 test/CodeGen/SystemZ/strcmp-nobuiltin.ll create mode 100644 test/CodeGen/SystemZ/strcpy-nobuiltin.ll create mode 100644 test/CodeGen/SystemZ/strlen-nobuiltin.ll create mode 100644 test/CodeGen/SystemZ/swift-return.ll create mode 100644 test/CodeGen/SystemZ/swifterror.ll create mode 100644 test/CodeGen/SystemZ/swiftself.ll create mode 100644 test/CodeGen/SystemZ/tdc-01.ll create mode 100644 test/CodeGen/SystemZ/tdc-02.ll create mode 100644 test/CodeGen/SystemZ/tdc-03.ll create mode 100644 test/CodeGen/SystemZ/tdc-04.ll create mode 100644 test/CodeGen/SystemZ/tdc-05.ll create mode 100644 test/CodeGen/SystemZ/tdc-06.ll create mode 100644 test/CodeGen/SystemZ/trap-01.ll create mode 100644 test/CodeGen/Thumb/and_neg.ll create mode 100644 test/CodeGen/Thumb/bic_imm.ll create mode 100644 test/CodeGen/Thumb/constants.ll create mode 100644 test/CodeGen/Thumb/ldm-stm-postinc.ll create mode 100644 test/CodeGen/Thumb2/bicbfi.ll create mode 100644 test/CodeGen/Thumb2/thumb2-cpsr-liveness.ll create mode 100644 test/CodeGen/WebAssembly/address-offsets.ll create mode 100644 test/CodeGen/WebAssembly/byval.ll create mode 100644 test/CodeGen/WebAssembly/divrem-constant.ll create mode 100644 test/CodeGen/WebAssembly/i128.ll create mode 100644 test/CodeGen/WebAssembly/i32-load-store-alignment.ll create mode 100644 test/CodeGen/WebAssembly/i64-load-store-alignment.ll create mode 100644 test/CodeGen/WebAssembly/indirect-import.ll create mode 100644 test/CodeGen/WebAssembly/irreducible-cfg.ll delete mode 100644 test/CodeGen/WebAssembly/loop-idiom.ll create mode 100644 test/CodeGen/WebAssembly/mem-intrinsics.ll create mode 100644 test/CodeGen/WebAssembly/non-executable-stack.ll create mode 100644 test/CodeGen/WinEH/wineh-asm.ll create mode 100644 test/CodeGen/WinEH/wineh-nested-unwind.ll create mode 100644 test/CodeGen/WinEH/wineh-setjmp.ll delete mode 100644 test/CodeGen/X86/2007-08-13-AppendingLinkage.ll delete mode 100644 test/CodeGen/X86/2008-08-19-SubAndFetch.ll create mode 100644 test/CodeGen/X86/AppendingLinkage.ll create mode 100644 test/CodeGen/X86/alias-gep.ll create mode 100644 test/CodeGen/X86/atomic-eflags-reuse.ll create mode 100644 test/CodeGen/X86/avx-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/avx-vbroadcastf128.ll create mode 100644 test/CodeGen/X86/avx2-intrinsics-fast-isel.ll delete mode 100644 test/CodeGen/X86/avx2-pmovxrm-intrinsics.ll create mode 100644 test/CodeGen/X86/avx2-pmovxrm.ll create mode 100644 test/CodeGen/X86/avx2-vbroadcasti128.ll create mode 100644 test/CodeGen/X86/avx512-any_extend_load.ll create mode 100644 test/CodeGen/X86/avx512-bugfix-26264.ll create mode 100644 test/CodeGen/X86/avx512-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/avx512-intrinsics-upgrade.ll create mode 100644 test/CodeGen/X86/avx512-mask-spills.ll create mode 100644 test/CodeGen/X86/avx512-scalarIntrinsics.ll create mode 100644 test/CodeGen/X86/avx512-unsafe-fp-math.ll create mode 100644 test/CodeGen/X86/avx512bw-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/avx512bw-intrinsics-upgrade.ll create mode 100644 test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/avx512bwvl-intrinsics-upgrade.ll create mode 100644 test/CodeGen/X86/avx512ifma-intrinsics.ll create mode 100644 test/CodeGen/X86/avx512ifmavl-intrinsics.ll create mode 100644 test/CodeGen/X86/avx512vbmi-intrinsics.ll create mode 100644 test/CodeGen/X86/avx512vbmivl-intrinsics.ll create mode 100644 test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll create mode 100644 test/CodeGen/X86/avx512vl-vbroadcast.ll create mode 100644 test/CodeGen/X86/base-pointer-and-cmpxchg.ll create mode 100644 test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll create mode 100644 test/CodeGen/X86/bmi-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/catchpad-dynamic-alloca.ll create mode 100644 test/CodeGen/X86/catchret-regmask.ll create mode 100644 test/CodeGen/X86/clear_upper_vector_element_bits.ll create mode 100644 test/CodeGen/X86/code_placement_loop_rotation3.ll create mode 100644 test/CodeGen/X86/combine-testm-and.ll create mode 100644 test/CodeGen/X86/crash-lre-eliminate-dead-def.ll delete mode 100644 test/CodeGen/X86/darwin-stub.ll create mode 100644 test/CodeGen/X86/deopt-bundles.ll create mode 100644 test/CodeGen/X86/deopt-intrinsic-cconv.ll create mode 100644 test/CodeGen/X86/deopt-intrinsic.ll create mode 100644 test/CodeGen/X86/eflags-copy-expansion.mir create mode 100644 test/CodeGen/X86/f16c-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/fixup-bw-copy.ll create mode 100644 test/CodeGen/X86/fixup-bw-copy.mir create mode 100644 test/CodeGen/X86/fixup-bw-inst.ll create mode 100644 test/CodeGen/X86/fp128-select.ll create mode 100644 test/CodeGen/X86/frame-order.ll create mode 100644 test/CodeGen/X86/ga-offset2.ll create mode 100644 test/CodeGen/X86/global-access-pie.ll create mode 100644 test/CodeGen/X86/hoist-spill-lpad.ll create mode 100644 test/CodeGen/X86/hoist-spill.ll create mode 100644 test/CodeGen/X86/i16lshr8pat.ll create mode 100644 test/CodeGen/X86/i386-setjmp-pic.ll create mode 100644 test/CodeGen/X86/i686-win-shrink-wrapping.ll create mode 100644 test/CodeGen/X86/ifunc-asm.ll create mode 100644 test/CodeGen/X86/implicit-null-checks.mir create mode 100644 test/CodeGen/X86/interval-update-remat.ll create mode 100644 test/CodeGen/X86/ipra-inline-asm.ll create mode 100644 test/CodeGen/X86/ipra-local-linkage.ll create mode 100644 test/CodeGen/X86/ipra-reg-usage.ll create mode 100644 test/CodeGen/X86/ipra-transform.ll create mode 100644 test/CodeGen/X86/lakemont.ll create mode 100644 test/CodeGen/X86/lea-opt-memop-check-1.ll create mode 100644 test/CodeGen/X86/lea-opt-memop-check-2.ll create mode 100644 test/CodeGen/X86/loc-remat.ll create mode 100644 test/CodeGen/X86/local_stack_symbol_ordering.ll delete mode 100644 test/CodeGen/X86/lock-inst-encoding.ll create mode 100644 test/CodeGen/X86/machine-copy-prop.mir create mode 100644 test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll delete mode 100644 test/CodeGen/X86/materialize-one.ll create mode 100644 test/CodeGen/X86/materialize.ll create mode 100644 test/CodeGen/X86/mbp-false-cfg-break.ll create mode 100644 test/CodeGen/X86/memcpy-from-string.ll create mode 100644 test/CodeGen/X86/memset-nonzero.ll create mode 100644 test/CodeGen/X86/merge-consecutive-loads-128.ll create mode 100644 test/CodeGen/X86/merge-consecutive-loads-256.ll create mode 100644 test/CodeGen/X86/merge-consecutive-loads-512.ll create mode 100644 test/CodeGen/X86/merge-sp-update-lea.ll create mode 100644 test/CodeGen/X86/mmx-bitcast-fold.ll create mode 100644 test/CodeGen/X86/movtopush64.ll create mode 100644 test/CodeGen/X86/mul-i256.ll create mode 100644 test/CodeGen/X86/mwaitx.ll create mode 100644 test/CodeGen/X86/negative-offset.ll create mode 100644 test/CodeGen/X86/new-remat.ll create mode 100644 test/CodeGen/X86/no-prolog-kill.ll create mode 100644 test/CodeGen/X86/no-sse2-avg.ll create mode 100644 test/CodeGen/X86/nontemporal-loads.ll create mode 100644 test/CodeGen/X86/noreturn-call.ll create mode 100644 test/CodeGen/X86/patchable-prologue.ll create mode 100644 test/CodeGen/X86/pie.ll create mode 100644 test/CodeGen/X86/post-ra-sched.ll create mode 100644 test/CodeGen/X86/pr2585.ll create mode 100644 test/CodeGen/X86/pr26350.ll create mode 100644 test/CodeGen/X86/pr26652.ll create mode 100644 test/CodeGen/X86/pr26757.ll create mode 100644 test/CodeGen/X86/pr26835.ll create mode 100644 test/CodeGen/X86/pr26870.ll create mode 100644 test/CodeGen/X86/pr27071.ll create mode 100644 test/CodeGen/X86/pr27501.ll create mode 100644 test/CodeGen/X86/pr27591.ll create mode 100644 test/CodeGen/X86/pr27681.mir create mode 100644 test/CodeGen/X86/pr28173.ll create mode 100644 test/CodeGen/X86/pr28444.ll create mode 100644 test/CodeGen/X86/pr28472.ll create mode 100644 test/CodeGen/X86/pr28489.ll create mode 100644 test/CodeGen/X86/pr28515.ll create mode 100644 test/CodeGen/X86/pr28560.ll create mode 100644 test/CodeGen/X86/ps4-noreturn.ll create mode 100644 test/CodeGen/X86/reduce-trunc-shl.ll create mode 100644 test/CodeGen/X86/return-ext.ll create mode 100644 test/CodeGen/X86/sad.ll create mode 100644 test/CodeGen/X86/safestack_ssp.ll create mode 100644 test/CodeGen/X86/shrink_vmul.ll create mode 100644 test/CodeGen/X86/sjlj-eh.ll create mode 100644 test/CodeGen/X86/sqrt-fastmath-mir.ll create mode 100644 test/CodeGen/X86/sse-intrinsics-fast-isel-x86_64.ll create mode 100644 test/CodeGen/X86/sse-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/sse-intrinsics-x86-upgrade.ll create mode 100644 test/CodeGen/X86/sse2-intrinsics-fast-isel-x86_64.ll create mode 100644 test/CodeGen/X86/sse2-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/sse41-intrinsics-fast-isel.ll delete mode 100644 test/CodeGen/X86/sse41-pmovxrm-intrinsics.ll create mode 100644 test/CodeGen/X86/sse41-pmovxrm.ll create mode 100644 test/CodeGen/X86/sse42-intrinsics-fast-isel-x86_64.ll create mode 100644 test/CodeGen/X86/sse42-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/sse4a-upgrade.ll create mode 100644 test/CodeGen/X86/ssp-guard-spill.ll create mode 100644 test/CodeGen/X86/stack-folding-fp-avx512vl.ll create mode 100644 test/CodeGen/X86/stack-protector-msvc.ll create mode 100644 test/CodeGen/X86/stack-protector-target.ll create mode 100644 test/CodeGen/X86/stackguard-internal.ll create mode 100644 test/CodeGen/X86/statepoint-uniqueing.ll create mode 100644 test/CodeGen/X86/statepoint-vector-bad-spill.ll create mode 100644 test/CodeGen/X86/store-zero-and-minus-one.ll create mode 100644 test/CodeGen/X86/swift-return.ll create mode 100644 test/CodeGen/X86/swifterror.ll create mode 100644 test/CodeGen/X86/swiftself.ll create mode 100644 test/CodeGen/X86/switch-density.ll create mode 100644 test/CodeGen/X86/tail-call-casts.ll create mode 100644 test/CodeGen/X86/tail-call-parameter-attrs-mismatch.ll create mode 100644 test/CodeGen/X86/tail-merge-unreachable.ll create mode 100644 test/CodeGen/X86/tbm-intrinsics-fast-isel-x86_64.ll create mode 100644 test/CodeGen/X86/tbm-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/tls-windows-itanium.ll create mode 100644 test/CodeGen/X86/unreachableblockelim.ll create mode 100644 test/CodeGen/X86/unused_stackslots.ll create mode 100644 test/CodeGen/X86/update-terminator.mir create mode 100644 test/CodeGen/X86/urem-power-of-two.ll delete mode 100644 test/CodeGen/X86/vec-sign.ll create mode 100644 test/CodeGen/X86/vec_fptrunc.ll create mode 100644 test/CodeGen/X86/vector-bitreverse.ll create mode 100644 test/CodeGen/X86/vector-compare-combines.ll create mode 100644 test/CodeGen/X86/vector-compare-results.ll create mode 100644 test/CodeGen/X86/vector-half-conversions.ll create mode 100644 test/CodeGen/X86/vector-idiv-sdiv-128.ll create mode 100644 test/CodeGen/X86/vector-idiv-sdiv-256.ll create mode 100644 test/CodeGen/X86/vector-idiv-sdiv-512.ll create mode 100644 test/CodeGen/X86/vector-idiv-udiv-128.ll create mode 100644 test/CodeGen/X86/vector-idiv-udiv-256.ll create mode 100644 test/CodeGen/X86/vector-idiv-udiv-512.ll create mode 100644 test/CodeGen/X86/vector-pcmp.ll create mode 100644 test/CodeGen/X86/vector-shuffle-512-v64.ll create mode 100644 test/CodeGen/X86/vector-shuffle-combining-avx.ll create mode 100644 test/CodeGen/X86/vector-shuffle-combining-avx2.ll create mode 100644 test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll create mode 100644 test/CodeGen/X86/vector-shuffle-combining-ssse3.ll create mode 100644 test/CodeGen/X86/vector-shuffle-combining-xop.ll create mode 100644 test/CodeGen/X86/vector-shuffle-sse41.ll create mode 100644 test/CodeGen/X86/vector-shuffle-variable-128.ll create mode 100644 test/CodeGen/X86/vector-shuffle-variable-256.ll create mode 100644 test/CodeGen/X86/vector-trunc-math.ll create mode 100644 test/CodeGen/X86/vzero-excess.ll create mode 100644 test/CodeGen/X86/widen_bitops-0.ll create mode 100644 test/CodeGen/X86/widen_bitops-1.ll create mode 100644 test/CodeGen/X86/widen_compare-1.ll create mode 100644 test/CodeGen/X86/win-alloca-expander.ll create mode 100644 test/CodeGen/X86/x86-16.ll create mode 100644 test/CodeGen/X86/x86-64-pic.ll create mode 100644 test/CodeGen/X86/x86-64-plt-relative-reloc.ll create mode 100644 test/CodeGen/X86/x86-big-ret.ll create mode 100644 test/CodeGen/X86/x86-interrupt_cc.ll create mode 100644 test/CodeGen/X86/x86-interrupt_cld.ll create mode 100644 test/CodeGen/X86/x86-interrupt_vzeroupper.ll create mode 100644 test/CodeGen/X86/x86-plt-relative-reloc.ll create mode 100644 test/CodeGen/X86/x87.ll create mode 100644 test/CodeGen/X86/xop-intrinsics-fast-isel.ll create mode 100644 test/CodeGen/X86/xop-intrinsics-x86_64-upgrade.ll create mode 100644 test/CodeGen/X86/xop-mask-comments.ll create mode 100644 test/CodeGen/X86/xray-attribute-instrumentation.ll create mode 100644 test/CodeGen/X86/xray-selective-instrumentation-miss.ll create mode 100644 test/CodeGen/X86/xray-selective-instrumentation.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/AArch64/128bit_load_store.ll b/test/CodeGen/AArch64/128bit_load_store.ll index 94fd386e0eaf..38d30dba4b8c 100644 --- a/test/CodeGen/AArch64/128bit_load_store.ll +++ b/test/CodeGen/AArch64/128bit_load_store.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=neon | FileCheck %s define void @test_store_f128(fp128* %ptr, fp128 %val) #0 { ; CHECK-LABEL: test_store_f128 diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll new file mode 100644 index 000000000000..7d416d9b0add --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -0,0 +1,63 @@ +; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s +; REQUIRES: global-isel +; This file checks that the translation from llvm IR to generic MachineInstr +; is correct. +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-apple-ios" + +; Tests for add. +; CHECK: name: addi64 +; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1 +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_ADD i64 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %x0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %x0 +define i64 @addi64(i64 %arg1, i64 %arg2) { + %res = add i64 %arg1, %arg2 + ret i64 %res +} + +; Tests for br. +; CHECK: name: uncondbr +; CHECK: body: +; +; Entry basic block. +; CHECK: {{[0-9a-zA-Z._-]+}}: +; +; Make sure we have one successor and only one. +; CHECK-NEXT: successors: %[[END:[0-9a-zA-Z._-]+]]({{0x[a-f0-9]+ / 0x[a-f0-9]+}} = 100.00%) +; +; Check that we emit the correct branch. +; CHECK: G_BR label %[[END]] +; +; Check that end contains the return instruction. +; CHECK: [[END]]: +; CHECK-NEXT: RET_ReallyLR +define void @uncondbr() { + br label %end +end: + ret void +} + +; Tests for or. +; CHECK: name: ori64 +; CHECK: [[ARG1:%[0-9]+]](64) = COPY %x0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](64) = COPY %x1 +; CHECK-NEXT: [[RES:%[0-9]+]](64) = G_OR i64 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %x0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %x0 +define i64 @ori64(i64 %arg1, i64 %arg2) { + %res = or i64 %arg1, %arg2 + ret i64 %res +} + +; CHECK: name: ori32 +; CHECK: [[ARG1:%[0-9]+]](32) = COPY %w0 +; CHECK-NEXT: [[ARG2:%[0-9]+]](32) = COPY %w1 +; CHECK-NEXT: [[RES:%[0-9]+]](32) = G_OR i32 [[ARG1]], [[ARG2]] +; CHECK-NEXT: %w0 = COPY [[RES]] +; CHECK-NEXT: RET_ReallyLR implicit %w0 +define i32 @ori32(i32 %arg1, i32 %arg2) { + %res = or i32 %arg1, %arg2 + ret i32 %res +} diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir new file mode 100644 index 000000000000..f5d85e189d75 --- /dev/null +++ b/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -0,0 +1,329 @@ +# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=FAST +# RUN: llc -O0 -run-pass=regbankselect -global-isel %s -regbankselect-greedy -o - 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY +# REQUIRES: global-isel + +--- | + ; ModuleID = 'generic-virtual-registers-type-error.mir' + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64-apple-ios" + define void @defaultMapping() { + entry: + ret void + } + define void @defaultMappingVector() { + entry: + ret void + } + define void @defaultMapping1Repair() { + entry: + ret void + } + define void @defaultMapping2Repairs() { + entry: + ret void + } + define void @defaultMappingDefRepair() { + entry: + ret void + } + define void @phiPropagation(i32* %src, i32* %dst, i1 %cond) { + entry: + %srcVal = load i32, i32* %src + br i1 %cond, label %end, label %then + then: + %res = add i32 %srcVal, 36 + br label %end + end: + %toStore = phi i32 [ %srcVal, %entry ], [ %res, %then ] + store i32 %toStore, i32* %dst + ret void + } + define void @defaultMappingUseRepairPhysReg() { + entry: + ret void + } + define void @defaultMappingDefRepairPhysReg() { + entry: + ret void + } + define void @greedyMappingOr() { + entry: + ret void + } + define void @greedyMappingOrWithConstraints() { + entry: + ret void + } +... + +--- +# Check that we assign a relevant register bank for %0. +# Based on the type i32, this should be gpr. +name: defaultMapping +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +registers: + - { id: 0, class: _ } +body: | + bb.0.entry: + liveins: %x0 + ; CHECK: %0(32) = G_ADD i32 %x0 + %0(32) = G_ADD i32 %x0, %x0 +... + +--- +# Check that we assign a relevant register bank for %0. +# Based on the type <2 x i32>, this should be fpr. +# FPR is used for both floating point and vector registers. +name: defaultMappingVector +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +registers: + - { id: 0, class: _ } +body: | + bb.0.entry: + liveins: %d0 + ; CHECK: %0(32) = G_ADD <2 x i32> %d0 + %0(32) = G_ADD <2 x i32> %d0, %d0 +... + +--- +# Check that we repair the assignment for %0. +# Indeed based on the source of the copy it should live +# in FPR, but at the use, it should be GPR. +name: defaultMapping1Repair +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + liveins: %s0, %x0 + ; CHECK: %0(32) = COPY %s0 + ; CHECK-NEXT: %2(32) = COPY %0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %2, %x0 + %0(32) = COPY %s0 + %1(32) = G_ADD i32 %0, %x0 +... + +# Check that we repair the assignment for %0 differently for both uses. +name: defaultMapping2Repairs +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: fpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: gpr } +# CHECK-NEXT: - { id: 3, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + liveins: %s0, %x0 + ; CHECK: %0(32) = COPY %s0 + ; CHECK-NEXT: %2(32) = COPY %0 + ; CHECK-NEXT: %3(32) = COPY %0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %2, %3 + %0(32) = COPY %s0 + %1(32) = G_ADD i32 %0, %0 +... + +--- +# Check that we repair the definition of %1. +# %1 is forced to be into FPR, but its definition actually +# requires that it lives in GPR. Make sure regbankselect +# fixes that. +name: defaultMappingDefRepair +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: fpr } +# CHECK-NEXT: - { id: 2, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: fpr } +body: | + bb.0.entry: + liveins: %w0 + ; CHECK: %0(32) = COPY %w0 + ; CHECK-NEXT: %2(32) = G_ADD i32 %0, %w0 + ; CHECK-NEXT: %1(32) = COPY %2 + %0(32) = COPY %w0 + %1(32) = G_ADD i32 %0, %w0 +... + +--- +# Check that we are able to propagate register banks from phis. +name: phiPropagation +isSSA: true +tracksRegLiveness: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr32 } +# CHECK-NEXT: - { id: 1, class: gpr64sp } +# CHECK-NEXT: - { id: 2, class: gpr32 } +# CHECK-NEXT: - { id: 3, class: gpr } +# CHECK-NEXT: - { id: 4, class: gpr } +registers: + - { id: 0, class: gpr32 } + - { id: 1, class: gpr64sp } + - { id: 2, class: gpr32 } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0.entry: + successors: %bb.2.end, %bb.1.then + liveins: %x0, %x1, %w2 + + %0 = LDRWui killed %x0, 0 :: (load 4 from %ir.src) + %1 = COPY %x1 + %2 = COPY %w2 + TBNZW killed %2, 0, %bb.2.end + + bb.1.then: + successors: %bb.2.end + %3(32) = G_ADD i32 %0, %0 + + bb.2.end: + %4(32) = PHI %0, %bb.0.entry, %3, %bb.1.then + STRWui killed %4, killed %1, 0 :: (store 4 into %ir.dst) + RET_ReallyLR +... + +--- +# Make sure we can repair physical register uses as well. +name: defaultMappingUseRepairPhysReg +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: gpr } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } +body: | + bb.0.entry: + liveins: %w0, %s0 + ; CHECK: %0(32) = COPY %w0 + ; CHECK-NEXT: %2(32) = COPY %s0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %0, %2 + %0(32) = COPY %w0 + %1(32) = G_ADD i32 %0, %s0 +... + +--- +# Make sure we can repair physical register defs. +name: defaultMappingDefRepairPhysReg +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: gpr } +registers: + - { id: 0, class: _ } +body: | + bb.0.entry: + liveins: %w0 + ; CHECK: %0(32) = COPY %w0 + ; CHECK-NEXT: %1(32) = G_ADD i32 %0, %0 + ; CHECK-NEXT: %s0 = COPY %1 + %0(32) = COPY %w0 + %s0 = G_ADD i32 %0, %0 +... + +--- +# Check that the greedy mode is able to switch the +# G_OR instruction from fpr to gpr. +name: greedyMappingOr +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: gpr } + +# Fast mode maps vector instruction on FPR. +# FAST-NEXT: - { id: 2, class: fpr } +# Fast mode needs two extra copies. +# FAST-NEXT: - { id: 3, class: fpr } +# FAST-NEXT: - { id: 4, class: fpr } + +# Greedy mode coalesce the computation on the GPR register +# because it is the cheapest. +# GREEDY-NEXT: - { id: 2, class: gpr } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0.entry: + liveins: %x0, %x1 + ; CHECK: %0(64) = COPY %x0 + ; CHECK-NEXT: %1(64) = COPY %x1 + + + ; Fast mode tries to reuse the source of the copy for the destination. + ; Now, the default mapping says that %0 and %1 need to be in FPR. + ; The repairing code insert two copies to materialize that. + ; FAST-NEXT: %3(64) = COPY %0 + ; FAST-NEXT: %4(64) = COPY %1 + ; The mapping of G_OR is on FPR. + ; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4 + + ; Greedy mode remapped the instruction on the GPR bank. + ; GREEDY-NEXT: %2(64) = G_OR <2 x i32> %0, %1 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = G_OR <2 x i32> %0, %1 +... + +--- +# Check that the greedy mode is able to switch the +# G_OR instruction from fpr to gpr, while still honoring +# %2 constraint. +name: greedyMappingOrWithConstraints +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +# CHECK-NEXT: - { id: 1, class: gpr } +# CHECK-NEXT: - { id: 2, class: fpr } + +# Fast mode maps vector instruction on FPR. +# Fast mode needs two extra copies. +# FAST-NEXT: - { id: 3, class: fpr } +# FAST-NEXT: - { id: 4, class: fpr } + +# Greedy mode coalesce the computation on the GPR register because it +# is the cheapest, but will need one extra copy to materialize %2 into a FPR. +# GREEDY-NEXT: - { id: 3, class: gpr } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: fpr } +body: | + bb.0.entry: + liveins: %x0, %x1 + ; CHECK: %0(64) = COPY %x0 + ; CHECK-NEXT: %1(64) = COPY %x1 + + + ; Fast mode tries to reuse the source of the copy for the destination. + ; Now, the default mapping says that %0 and %1 need to be in FPR. + ; The repairing code insert two copies to materialize that. + ; FAST-NEXT: %3(64) = COPY %0 + ; FAST-NEXT: %4(64) = COPY %1 + ; The mapping of G_OR is on FPR. + ; FAST-NEXT: %2(64) = G_OR <2 x i32> %3, %4 + + ; Greedy mode remapped the instruction on the GPR bank. + ; GREEDY-NEXT: %3(64) = G_OR <2 x i32> %0, %1 + ; We need to keep %2 into FPR because we do not know anything about it. + ; GREEDY-NEXT: %2(64) = COPY %3 + %0(64) = COPY %x0 + %1(64) = COPY %x1 + %2(64) = G_OR <2 x i32> %0, %1 +... diff --git a/test/CodeGen/AArch64/a57-csel.ll b/test/CodeGen/AArch64/a57-csel.ll index f5496f777765..3c99a90fe28a 100644 --- a/test/CodeGen/AArch64/a57-csel.ll +++ b/test/CodeGen/AArch64/a57-csel.ll @@ -1,8 +1,9 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -mcpu=cortex-a57 -aarch64-enable-early-ifcvt=false | FileCheck %s -; Check that the select is expanded into a branch sequence. +; Check that the select isn't expanded into a branch sequence +; when the icmp's first operand %x0 is from load. define i64 @f(i64 %a, i64 %b, i64* %c, i64 %d, i64 %e) { - ; CHECK: cbz + ; CHECK: csel %x0 = load i64, i64* %c %x1 = icmp eq i64 %x0, 0 %x2 = select i1 %x1, i64 %a, i64 %b diff --git a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll index 5eb455f3a22c..d12c4c6f9fae 100644 --- a/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll +++ b/test/CodeGen/AArch64/aarch64-2014-08-11-MachineCombinerCrash.ll @@ -44,11 +44,10 @@ attributes #1 = { nounwind readnone } !llvm.module.flags = !{!36, !37} !llvm.ident = !{!38} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.6.0 ", isOptimized: true, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.c", directory: "") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "", line: 140, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 141, file: !1, scope: !1, type: !6, variables: !12) +!4 = distinct !DISubprogram(name: "", line: 140, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 141, file: !1, scope: !1, type: !6, variables: !12) !6 = !DISubroutineType(types: !7) !7 = !{null, !8} !8 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, baseType: !9) diff --git a/test/CodeGen/AArch64/aarch64-DAGCombine-findBetterNeighborChains-crash.ll b/test/CodeGen/AArch64/aarch64-DAGCombine-findBetterNeighborChains-crash.ll new file mode 100644 index 000000000000..73200b581585 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-DAGCombine-findBetterNeighborChains-crash.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -march=arm64 +; Make sure we are not crashing on this test. + +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64-unknown-linux-gnu" + +declare void @extern(i8*) + +; Function Attrs: argmemonly nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) #0 + +; Function Attrs: nounwind +define void @func(float* noalias %arg, i32* noalias %arg1, i8* noalias %arg2, i8* noalias %arg3) #1 { +bb: + %tmp = getelementptr inbounds i8, i8* %arg2, i64 88 + tail call void @llvm.memset.p0i8.i64(i8* noalias %arg2, i8 0, i64 40, i32 8, i1 false) + store i8 0, i8* %arg3 + store i8 2, i8* %arg2 + store float 0.000000e+00, float* %arg + %tmp4 = bitcast i8* %tmp to <4 x float>* + store volatile <4 x float> zeroinitializer, <4 x float>* %tmp4 + store i32 5, i32* %arg1 + tail call void @extern(i8* %tmp) + ret void +} + +; Function Attrs: nounwind +define void @func2(float* noalias %arg, i32* noalias %arg1, i8* noalias %arg2, i8* noalias %arg3) #1 { +bb: + %tmp = getelementptr inbounds i8, i8* %arg2, i64 88 + tail call void @llvm.memset.p0i8.i64(i8* noalias %arg2, i8 0, i64 40, i32 8, i1 false) + store i8 0, i8* %arg3 + store i8 2, i8* %arg2 + store float 0.000000e+00, float* %arg + %tmp4 = bitcast i8* %tmp to <4 x float>* + store <4 x float> zeroinitializer, <4 x float>* %tmp4 + store i32 5, i32* %arg1 + tail call void @extern(i8* %tmp) + ret void +} + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind "target-cpu"="cortex-a53" } diff --git a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll index b0e9d4aa7703..29b71e042611 100644 --- a/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll +++ b/test/CodeGen/AArch64/aarch64-a57-fp-load-balancing.ll @@ -1,7 +1,13 @@ -; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-EVEN -; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A57 --check-prefix CHECK-ODD -; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN -; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD +; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-EVEN +; RUN: llc < %s -mcpu=cortex-a57 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-BALFP --check-prefix CHECK-ODD +; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-EVEN +; RUN: llc < %s -mcpu=cortex-a53 -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-A53 --check-prefix CHECK-ODD + +; The following tests use the balance-fp-ops feature, and should be independent of +; the target cpu. + +; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=1 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-EVEN --check-prefix CHECK-BALFP +; RUN: llc < %s -mtriple=aarch64-linux-gnueabi -mattr=+balance-fp-ops -aarch64-a57-fp-load-balancing-override=2 -aarch64-a57-fp-load-balancing-force-all -enable-misched=false -enable-post-misched=false | FileCheck %s --check-prefix CHECK --check-prefix CHECK-ODD --check-prefix CHECK-BALFP ; Test the AArch64A57FPLoadBalancing pass. This pass relies heavily on register allocation, so ; our test strategy is to: @@ -75,7 +81,7 @@ entry: ; CHECK: fmsub [[x]] ; CHECK: fmadd [[y]] ; CHECK: fmadd [[x]] -; CHECK-A57: stp [[x]], [[y]] +; CHECK-BALFP: stp [[x]], [[y]] ; CHECK-A53-DAG: str [[x]] ; CHECK-A53-DAG: str [[y]] @@ -170,7 +176,7 @@ declare void @g(...) #1 ; CHECK: fmsub [[x]] ; CHECK: fmadd [[y]] ; CHECK: fmadd [[x]] -; CHECK-A57: stp [[x]], [[y]] +; CHECK-BALFP: stp [[x]], [[y]] ; CHECK-A53-DAG: str [[x]] ; CHECK-A53-DAG: str [[y]] diff --git a/test/CodeGen/AArch64/aarch64-be-bv.ll b/test/CodeGen/AArch64/aarch64-be-bv.ll index fb41156c09df..163a86b9ae4c 100644 --- a/test/CodeGen/AArch64/aarch64-be-bv.ll +++ b/test/CodeGen/AArch64/aarch64-be-bv.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: movi_modimm_t1: define i16 @movi_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -17,7 +17,7 @@ define i16 @movi_modimm_t1() nounwind { ; CHECK-LABEL: movi_modimm_t2: define i16 @movi_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #8 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -29,7 +29,7 @@ define i16 @movi_modimm_t2() nounwind { ; CHECK-LABEL: movi_modimm_t3: define i16 @movi_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #16 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -41,7 +41,7 @@ define i16 @movi_modimm_t3() nounwind { ; CHECK-LABEL: movi_modimm_t4: define i16 @movi_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #24 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -53,7 +53,7 @@ define i16 @movi_modimm_t4() nounwind { ; CHECK-LABEL: movi_modimm_t5: define i16 @movi_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -65,7 +65,7 @@ define i16 @movi_modimm_t5() nounwind { ; CHECK-LABEL: movi_modimm_t6: define i16 @movi_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1, lsl #8 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -77,7 +77,7 @@ define i16 @movi_modimm_t6() nounwind { ; CHECK-LABEL: movi_modimm_t7: define i16 @movi_modimm_t7() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #8 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -89,7 +89,7 @@ define i16 @movi_modimm_t7() nounwind { ; CHECK-LABEL: movi_modimm_t8: define i16 @movi_modimm_t8() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #16 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -101,7 +101,7 @@ define i16 @movi_modimm_t8() nounwind { ; CHECK-LABEL: movi_modimm_t9: define i16 @movi_modimm_t9() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #0x1 + ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -149,7 +149,7 @@ define i16 @fmov_modimm_t12() nounwind { ; CHECK-LABEL: mvni_modimm_t1: define i16 @mvni_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -161,7 +161,7 @@ define i16 @mvni_modimm_t1() nounwind { ; CHECK-LABEL: mvni_modimm_t2: define i16 @mvni_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #8 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -173,7 +173,7 @@ define i16 @mvni_modimm_t2() nounwind { ; CHECK-LABEL: mvni_modimm_t3: define i16 @mvni_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #16 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -185,7 +185,7 @@ define i16 @mvni_modimm_t3() nounwind { ; CHECK-LABEL: mvni_modimm_t4: define i16 @mvni_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #24 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #24 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -197,7 +197,7 @@ define i16 @mvni_modimm_t4() nounwind { ; CHECK-LABEL: mvni_modimm_t5: define i16 @mvni_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -209,7 +209,7 @@ define i16 @mvni_modimm_t5() nounwind { ; CHECK-LABEL: mvni_modimm_t6: define i16 @mvni_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1, lsl #8 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1, lsl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -221,7 +221,7 @@ define i16 @mvni_modimm_t6() nounwind { ; CHECK-LABEL: mvni_modimm_t7: define i16 @mvni_modimm_t7() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #8 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #8 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -233,7 +233,7 @@ define i16 @mvni_modimm_t7() nounwind { ; CHECK-LABEL: mvni_modimm_t8: define i16 @mvni_modimm_t8() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #16 + ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #16 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 @@ -245,7 +245,7 @@ define i16 @mvni_modimm_t8() nounwind { ; CHECK-LABEL: bic_modimm_t1: define i16 @bic_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -256,7 +256,7 @@ define i16 @bic_modimm_t1() nounwind { ; CHECK-LABEL: bic_modimm_t2: define i16 @bic_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #8 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -267,7 +267,7 @@ define i16 @bic_modimm_t2() nounwind { ; CHECK-LABEL: bic_modimm_t3: define i16 @bic_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #16 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #16 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -278,7 +278,7 @@ define i16 @bic_modimm_t3() nounwind { ; CHECK-LABEL: bic_modimm_t4: define i16 @bic_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #24 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #24 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -289,7 +289,7 @@ define i16 @bic_modimm_t4() nounwind { ; CHECK-LABEL: bic_modimm_t5: define i16 @bic_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -300,7 +300,7 @@ define i16 @bic_modimm_t5() nounwind { ; CHECK-LABEL: bic_modimm_t6: define i16 @bic_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1, lsl #8 + ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = and <8 x i16> %in, @@ -311,7 +311,7 @@ define i16 @bic_modimm_t6() nounwind { ; CHECK-LABEL: orr_modimm_t1: define i16 @orr_modimm_t1() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -322,7 +322,7 @@ define i16 @orr_modimm_t1() nounwind { ; CHECK-LABEL: orr_modimm_t2: define i16 @orr_modimm_t2() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #8 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -333,7 +333,7 @@ define i16 @orr_modimm_t2() nounwind { ; CHECK-LABEL: orr_modimm_t3: define i16 @orr_modimm_t3() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #16 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #16 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -344,7 +344,7 @@ define i16 @orr_modimm_t3() nounwind { ; CHECK-LABEL: orr_modimm_t4: define i16 @orr_modimm_t4() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #24 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #24 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -355,7 +355,7 @@ define i16 @orr_modimm_t4() nounwind { ; CHECK-LABEL: orr_modimm_t5: define i16 @orr_modimm_t5() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -366,7 +366,7 @@ define i16 @orr_modimm_t5() nounwind { ; CHECK-LABEL: orr_modimm_t6: define i16 @orr_modimm_t6() nounwind { ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}] - ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1, lsl #8 + ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1, lsl #8 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0] %in = load <8 x i16>, <8 x i16>* @vec_v8i16 %rv = or <8 x i16> %in, @@ -385,37 +385,37 @@ declare i64 @f_v2i64(<2 x i64> %arg) ; CHECK-LABEL: modimm_t1_call: define void @modimm_t1_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5 + ; CHECK: movi v{{[0-9]+}}.2s, #5 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -425,37 +425,37 @@ define void @modimm_t1_call() { ; CHECK-LABEL: modimm_t2_call: define void @modimm_t2_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5, lsl #8 + ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #8 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2, lsl #8 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #8 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -465,37 +465,37 @@ define void @modimm_t2_call() { ; CHECK-LABEL: modimm_t3_call: define void @modimm_t3_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5, lsl #16 + ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #16 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2, lsl #16 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #16 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -505,37 +505,37 @@ define void @modimm_t3_call() { ; CHECK-LABEL: modimm_t4_call: define void @modimm_t4_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, lsl #24 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, lsl #24 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, lsl #24 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5, lsl #24 + ; CHECK: movi v{{[0-9]+}}.2s, #5, lsl #24 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, lsl #24 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, lsl #24 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #24 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, lsl #24 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2, lsl #24 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2, lsl #24 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -545,37 +545,37 @@ define void @modimm_t4_call() { ; CHECK-LABEL: modimm_t5_call: define void @modimm_t5_call() { - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x7 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #7 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x6 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #6 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.4h, #0x5 + ; CHECK: movi v{{[0-9]+}}.4h, #5 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x5 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #5 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x4 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #4 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x3 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #3 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].8h, #0x2 + ; CHECK: movi v[[REG:[0-9]+]].8h, #2 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -585,37 +585,37 @@ define void @modimm_t5_call() { ; CHECK-LABEL: modimm_t6_call: define void @modimm_t6_call() { - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #8, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x7, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #7, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x6, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4h, #6, lsl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.4h, #0x5, lsl #8 + ; CHECK: movi v{{[0-9]+}}.4h, #5, lsl #8 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x5, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #5, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x4, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #4, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x3, lsl #8 + ; CHECK: movi v[[REG1:[0-9]+]].8h, #3, lsl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].8h, #0x2, lsl #8 + ; CHECK: movi v[[REG:[0-9]+]].8h, #2, lsl #8 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -625,37 +625,37 @@ define void @modimm_t6_call() { ; CHECK-LABEL: modimm_t7_call: define void @modimm_t7_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, msl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, msl #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5, msl #8 + ; CHECK: movi v{{[0-9]+}}.2s, #5, msl #8 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, msl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, msl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, msl #8 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, msl #8 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2, msl #8 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2, msl #8 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -665,37 +665,37 @@ define void @modimm_t7_call() { ; CHECK-LABEL: modimm_t8_call: define void @modimm_t8_call() { - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #8, msl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #7, msl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].2s, #6, msl #16 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v{{[0-9]+}}.2s, #0x5, msl #16 + ; CHECK: movi v{{[0-9]+}}.2s, #5, msl #16 ; CHECK-NEXT: bl f_v1i64 call i64 @f_v1i64(<1 x i64> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #5, msl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #4, msl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, msl #16 + ; CHECK: movi v[[REG1:[0-9]+]].4s, #3, msl #16 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 call i32 @f_v4i32(<4 x i32> ) - ; CHECK: movi v[[REG:[0-9]+]].4s, #0x2, msl #16 + ; CHECK: movi v[[REG:[0-9]+]].4s, #2, msl #16 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v2i64 call i64 @f_v2i64(<2 x i64> ) @@ -705,29 +705,29 @@ define void @modimm_t8_call() { ; CHECK-LABEL: modimm_t9_call: define void @modimm_t9_call() { - ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x8 + ; CHECK: movi v[[REG1:[0-9]+]].8b, #8 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b ; CHECK-NEXT: bl f_v8i8 call i8 @f_v8i8(<8 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x7 + ; CHECK: movi v[[REG1:[0-9]+]].8b, #7 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h ; CHECK-NEXT: bl f_v4i16 call i16 @f_v4i16(<4 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x6 + ; CHECK: movi v[[REG1:[0-9]+]].8b, #6 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s ; CHECK-NEXT: bl f_v2i32 call i32 @f_v2i32(<2 x i32> ) - ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x5 + ; CHECK: movi v[[REG1:[0-9]+]].16b, #5 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v16i8 call i8 @f_v16i8(<16 x i8> ) - ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x4 + ; CHECK: movi v[[REG1:[0-9]+]].16b, #4 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v8i16 call i16 @f_v8i16(<8 x i16> ) - ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x3 + ; CHECK: movi v[[REG1:[0-9]+]].16b, #3 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8 ; CHECK-NEXT: bl f_v4i32 diff --git a/test/CodeGen/AArch64/aarch64-deferred-spilling.ll b/test/CodeGen/AArch64/aarch64-deferred-spilling.ll deleted file mode 100644 index 7accdced7d44..000000000000 --- a/test/CodeGen/AArch64/aarch64-deferred-spilling.ll +++ /dev/null @@ -1,514 +0,0 @@ -;RUN: llc < %s -mtriple=aarch64--linux-android -regalloc=greedy -enable-deferred-spilling=true -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=DEFERRED -;RUN: llc < %s -mtriple=aarch64--linux-android -regalloc=greedy -enable-deferred-spilling=false -mcpu=cortex-a57 | FileCheck %s --check-prefix=CHECK --check-prefix=REGULAR - -; Check that we do not end up with useless spill code. -; -; Move to the basic block we are interested in. -; -; CHECK: // %if.then.120 -; -; REGULAR: str w21, [sp, #[[OFFSET:[0-9]+]]] // 4-byte Folded Spill -; Check that w21 wouldn't need to be spilled since it is never reused. -; REGULAR-NOT: {{[wx]}}21{{,?}} -; -; Check that w22 is used to carry a value through the call. -; DEFERRED-NOT: str {{[wx]}}22, -; DEFERRED: mov {{[wx]}}22, -; DEFERRED-NOT: str {{[wx]}}22, -; -; CHECK: bl fprintf -; -; DEFERRED-NOT: ldr {{[wx]}}22, -; DEFERRED: mov {{[wx][0-9]+}}, {{[wx]}}22 -; DEFERRED-NOT: ldr {{[wx]}}22, -; -; REGULAR-NOT: {{[wx]}}21{{,?}} -; REGULAR: ldr w21, [sp, #[[OFFSET]]] // 4-byte Folded Reload -; -; End of the basic block we are interested in. -; CHECK: b -; CHECK: {{[^:]+}}: // %sw.bb.123 - -%struct.__sFILE = type { i8*, i32, i32, i32, i32, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } -%struct.__sbuf = type { i8*, i64 } -%struct.DState = type { %struct.bz_stream*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* } -%struct.bz_stream = type { i8*, i32, i32, i32, i8*, i32, i32, i32, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8* } - -@__sF = external global [0 x %struct.__sFILE], align 8 -@.str = private unnamed_addr constant [20 x i8] c"\0A [%d: stuff+mf \00", align 1 - -declare i32 @fprintf(%struct.__sFILE* nocapture, i8* nocapture readonly, ...) - -declare void @bar(i32) - -declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) - -define i32 @foo(%struct.DState* %s) { -entry: - %state = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 1 - %tmp = load i32, i32* %state, align 4 - %cmp = icmp eq i32 %tmp, 10 - %save_i = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 40 - br i1 %cmp, label %if.end.thread, label %if.end - -if.end.thread: ; preds = %entry - %save_j = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 41 - %save_t = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 42 - %save_alphaSize = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 43 - %save_nGroups = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 44 - %save_nSelectors = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 45 - %save_EOB = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 46 - %save_groupNo = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 47 - %save_groupPos = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 48 - %save_nextSym = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 49 - %save_nblockMAX = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 50 - %save_nblock = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 51 - %save_es = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 52 - %save_N = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 53 - %save_curr = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 54 - %save_zt = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 55 - %save_zn = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 56 - %save_zvec = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 57 - %save_zj = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 58 - %tmp1 = bitcast i32* %save_i to i8* - call void @llvm.memset.p0i8.i64(i8* %tmp1, i8 0, i64 108, i32 4, i1 false) - br label %sw.default - -if.end: ; preds = %entry - %.pre = load i32, i32* %save_i, align 4 - %save_j3.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 41 - %.pre406 = load i32, i32* %save_j3.phi.trans.insert, align 4 - %save_t4.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 42 - %.pre407 = load i32, i32* %save_t4.phi.trans.insert, align 4 - %save_alphaSize5.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 43 - %.pre408 = load i32, i32* %save_alphaSize5.phi.trans.insert, align 4 - %save_nGroups6.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 44 - %.pre409 = load i32, i32* %save_nGroups6.phi.trans.insert, align 4 - %save_nSelectors7.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 45 - %.pre410 = load i32, i32* %save_nSelectors7.phi.trans.insert, align 4 - %save_EOB8.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 46 - %.pre411 = load i32, i32* %save_EOB8.phi.trans.insert, align 4 - %save_groupNo9.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 47 - %.pre412 = load i32, i32* %save_groupNo9.phi.trans.insert, align 4 - %save_groupPos10.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 48 - %.pre413 = load i32, i32* %save_groupPos10.phi.trans.insert, align 4 - %save_nextSym11.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 49 - %.pre414 = load i32, i32* %save_nextSym11.phi.trans.insert, align 4 - %save_nblockMAX12.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 50 - %.pre415 = load i32, i32* %save_nblockMAX12.phi.trans.insert, align 4 - %save_nblock13.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 51 - %.pre416 = load i32, i32* %save_nblock13.phi.trans.insert, align 4 - %save_es14.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 52 - %.pre417 = load i32, i32* %save_es14.phi.trans.insert, align 4 - %save_N15.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 53 - %.pre418 = load i32, i32* %save_N15.phi.trans.insert, align 4 - %save_curr16.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 54 - %.pre419 = load i32, i32* %save_curr16.phi.trans.insert, align 4 - %save_zt17.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 55 - %.pre420 = load i32, i32* %save_zt17.phi.trans.insert, align 4 - %save_zn18.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 56 - %.pre421 = load i32, i32* %save_zn18.phi.trans.insert, align 4 - %save_zvec19.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 57 - %.pre422 = load i32, i32* %save_zvec19.phi.trans.insert, align 4 - %save_zj20.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 58 - %.pre423 = load i32, i32* %save_zj20.phi.trans.insert, align 4 - switch i32 %tmp, label %sw.default [ - i32 13, label %sw.bb - i32 14, label %if.end.sw.bb.65_crit_edge - i32 25, label %if.end.sw.bb.123_crit_edge - ] - -if.end.sw.bb.123_crit_edge: ; preds = %if.end - %.pre433 = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 8 - br label %sw.bb.123 - -if.end.sw.bb.65_crit_edge: ; preds = %if.end - %bsLive69.phi.trans.insert = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 8 - %.pre426 = load i32, i32* %bsLive69.phi.trans.insert, align 4 - br label %sw.bb.65 - -sw.bb: ; preds = %if.end - %sunkaddr = ptrtoint %struct.DState* %s to i64 - %sunkaddr485 = add i64 %sunkaddr, 8 - %sunkaddr486 = inttoptr i64 %sunkaddr485 to i32* - store i32 13, i32* %sunkaddr486, align 4 - %bsLive = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 8 - %tmp2 = load i32, i32* %bsLive, align 4 - %cmp28.400 = icmp sgt i32 %tmp2, 7 - br i1 %cmp28.400, label %sw.bb.if.then.29_crit_edge, label %if.end.33.lr.ph - -sw.bb.if.then.29_crit_edge: ; preds = %sw.bb - %sunkaddr487 = ptrtoint %struct.DState* %s to i64 - %sunkaddr488 = add i64 %sunkaddr487, 32 - %sunkaddr489 = inttoptr i64 %sunkaddr488 to i32* - %.pre425 = load i32, i32* %sunkaddr489, align 4 - br label %if.then.29 - -if.end.33.lr.ph: ; preds = %sw.bb - %tmp3 = bitcast %struct.DState* %s to %struct.bz_stream** - %.pre424 = load %struct.bz_stream*, %struct.bz_stream** %tmp3, align 8 - %avail_in.phi.trans.insert = getelementptr inbounds %struct.bz_stream, %struct.bz_stream* %.pre424, i64 0, i32 1 - %.pre430 = load i32, i32* %avail_in.phi.trans.insert, align 4 - %tmp4 = add i32 %.pre430, -1 - br label %if.end.33 - -if.then.29: ; preds = %while.body.backedge, %sw.bb.if.then.29_crit_edge - %tmp5 = phi i32 [ %.pre425, %sw.bb.if.then.29_crit_edge ], [ %or, %while.body.backedge ] - %.lcssa393 = phi i32 [ %tmp2, %sw.bb.if.then.29_crit_edge ], [ %add, %while.body.backedge ] - %sub = add nsw i32 %.lcssa393, -8 - %shr = lshr i32 %tmp5, %sub - %and = and i32 %shr, 255 - %sunkaddr491 = ptrtoint %struct.DState* %s to i64 - %sunkaddr492 = add i64 %sunkaddr491, 36 - %sunkaddr493 = inttoptr i64 %sunkaddr492 to i32* - store i32 %sub, i32* %sunkaddr493, align 4 - %blockSize100k = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 9 - store i32 %and, i32* %blockSize100k, align 4 - %and.off = add nsw i32 %and, -49 - %tmp6 = icmp ugt i32 %and.off, 8 - br i1 %tmp6, label %save_state_and_return, label %if.end.62 - -if.end.33: ; preds = %while.body.backedge, %if.end.33.lr.ph - %lsr.iv482 = phi i32 [ %tmp4, %if.end.33.lr.ph ], [ %lsr.iv.next483, %while.body.backedge ] - %tmp7 = phi i32 [ %tmp2, %if.end.33.lr.ph ], [ %add, %while.body.backedge ] - %cmp35 = icmp eq i32 %lsr.iv482, -1 - br i1 %cmp35, label %save_state_and_return, label %if.end.37 - -if.end.37: ; preds = %if.end.33 - %tmp8 = bitcast %struct.bz_stream* %.pre424 to i8** - %sunkaddr494 = ptrtoint %struct.DState* %s to i64 - %sunkaddr495 = add i64 %sunkaddr494, 32 - %sunkaddr496 = inttoptr i64 %sunkaddr495 to i32* - %tmp9 = load i32, i32* %sunkaddr496, align 4 - %shl = shl i32 %tmp9, 8 - %tmp10 = load i8*, i8** %tmp8, align 8 - %tmp11 = load i8, i8* %tmp10, align 1 - %conv = zext i8 %tmp11 to i32 - %or = or i32 %conv, %shl - store i32 %or, i32* %sunkaddr496, align 4 - %add = add nsw i32 %tmp7, 8 - %sunkaddr497 = ptrtoint %struct.DState* %s to i64 - %sunkaddr498 = add i64 %sunkaddr497, 36 - %sunkaddr499 = inttoptr i64 %sunkaddr498 to i32* - store i32 %add, i32* %sunkaddr499, align 4 - %incdec.ptr = getelementptr inbounds i8, i8* %tmp10, i64 1 - store i8* %incdec.ptr, i8** %tmp8, align 8 - %sunkaddr500 = ptrtoint %struct.bz_stream* %.pre424 to i64 - %sunkaddr501 = add i64 %sunkaddr500, 8 - %sunkaddr502 = inttoptr i64 %sunkaddr501 to i32* - store i32 %lsr.iv482, i32* %sunkaddr502, align 4 - %sunkaddr503 = ptrtoint %struct.bz_stream* %.pre424 to i64 - %sunkaddr504 = add i64 %sunkaddr503, 12 - %sunkaddr505 = inttoptr i64 %sunkaddr504 to i32* - %tmp12 = load i32, i32* %sunkaddr505, align 4 - %inc = add i32 %tmp12, 1 - store i32 %inc, i32* %sunkaddr505, align 4 - %cmp49 = icmp eq i32 %inc, 0 - br i1 %cmp49, label %if.then.51, label %while.body.backedge - -if.then.51: ; preds = %if.end.37 - %sunkaddr506 = ptrtoint %struct.bz_stream* %.pre424 to i64 - %sunkaddr507 = add i64 %sunkaddr506, 16 - %sunkaddr508 = inttoptr i64 %sunkaddr507 to i32* - %tmp13 = load i32, i32* %sunkaddr508, align 4 - %inc53 = add i32 %tmp13, 1 - store i32 %inc53, i32* %sunkaddr508, align 4 - br label %while.body.backedge - -while.body.backedge: ; preds = %if.then.51, %if.end.37 - %lsr.iv.next483 = add i32 %lsr.iv482, -1 - %cmp28 = icmp sgt i32 %add, 7 - br i1 %cmp28, label %if.then.29, label %if.end.33 - -if.end.62: ; preds = %if.then.29 - %sub64 = add nsw i32 %and, -48 - %sunkaddr509 = ptrtoint %struct.DState* %s to i64 - %sunkaddr510 = add i64 %sunkaddr509, 40 - %sunkaddr511 = inttoptr i64 %sunkaddr510 to i32* - store i32 %sub64, i32* %sunkaddr511, align 4 - br label %sw.bb.65 - -sw.bb.65: ; preds = %if.end.62, %if.end.sw.bb.65_crit_edge - %bsLive69.pre-phi = phi i32* [ %bsLive69.phi.trans.insert, %if.end.sw.bb.65_crit_edge ], [ %bsLive, %if.end.62 ] - %tmp14 = phi i32 [ %.pre426, %if.end.sw.bb.65_crit_edge ], [ %sub, %if.end.62 ] - %sunkaddr512 = ptrtoint %struct.DState* %s to i64 - %sunkaddr513 = add i64 %sunkaddr512, 8 - %sunkaddr514 = inttoptr i64 %sunkaddr513 to i32* - store i32 14, i32* %sunkaddr514, align 4 - %cmp70.397 = icmp sgt i32 %tmp14, 7 - br i1 %cmp70.397, label %if.then.72, label %if.end.82.lr.ph - -if.end.82.lr.ph: ; preds = %sw.bb.65 - %tmp15 = bitcast %struct.DState* %s to %struct.bz_stream** - %.pre427 = load %struct.bz_stream*, %struct.bz_stream** %tmp15, align 8 - %avail_in84.phi.trans.insert = getelementptr inbounds %struct.bz_stream, %struct.bz_stream* %.pre427, i64 0, i32 1 - %.pre431 = load i32, i32* %avail_in84.phi.trans.insert, align 4 - %tmp16 = add i32 %.pre431, -1 - br label %if.end.82 - -if.then.72: ; preds = %while.body.68.backedge, %sw.bb.65 - %.lcssa390 = phi i32 [ %tmp14, %sw.bb.65 ], [ %add97, %while.body.68.backedge ] - %sub76 = add nsw i32 %.lcssa390, -8 - %sunkaddr516 = ptrtoint %struct.DState* %s to i64 - %sunkaddr517 = add i64 %sunkaddr516, 36 - %sunkaddr518 = inttoptr i64 %sunkaddr517 to i32* - store i32 %sub76, i32* %sunkaddr518, align 4 - %currBlockNo = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 11 - %tmp17 = load i32, i32* %currBlockNo, align 4 - %inc117 = add nsw i32 %tmp17, 1 - store i32 %inc117, i32* %currBlockNo, align 4 - %verbosity = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 12 - %tmp18 = load i32, i32* %verbosity, align 4 - %cmp118 = icmp sgt i32 %tmp18, 1 - br i1 %cmp118, label %if.then.120, label %sw.bb.123, !prof !0 - -if.end.82: ; preds = %while.body.68.backedge, %if.end.82.lr.ph - %lsr.iv480 = phi i32 [ %tmp16, %if.end.82.lr.ph ], [ %lsr.iv.next481, %while.body.68.backedge ] - %tmp19 = phi i32 [ %tmp14, %if.end.82.lr.ph ], [ %add97, %while.body.68.backedge ] - %cmp85 = icmp eq i32 %lsr.iv480, -1 - br i1 %cmp85, label %save_state_and_return, label %if.end.88 - -if.end.88: ; preds = %if.end.82 - %tmp20 = bitcast %struct.bz_stream* %.pre427 to i8** - %sunkaddr519 = ptrtoint %struct.DState* %s to i64 - %sunkaddr520 = add i64 %sunkaddr519, 32 - %sunkaddr521 = inttoptr i64 %sunkaddr520 to i32* - %tmp21 = load i32, i32* %sunkaddr521, align 4 - %shl90 = shl i32 %tmp21, 8 - %tmp22 = load i8*, i8** %tmp20, align 8 - %tmp23 = load i8, i8* %tmp22, align 1 - %conv93 = zext i8 %tmp23 to i32 - %or94 = or i32 %conv93, %shl90 - store i32 %or94, i32* %sunkaddr521, align 4 - %add97 = add nsw i32 %tmp19, 8 - %sunkaddr522 = ptrtoint %struct.DState* %s to i64 - %sunkaddr523 = add i64 %sunkaddr522, 36 - %sunkaddr524 = inttoptr i64 %sunkaddr523 to i32* - store i32 %add97, i32* %sunkaddr524, align 4 - %incdec.ptr100 = getelementptr inbounds i8, i8* %tmp22, i64 1 - store i8* %incdec.ptr100, i8** %tmp20, align 8 - %sunkaddr525 = ptrtoint %struct.bz_stream* %.pre427 to i64 - %sunkaddr526 = add i64 %sunkaddr525, 8 - %sunkaddr527 = inttoptr i64 %sunkaddr526 to i32* - store i32 %lsr.iv480, i32* %sunkaddr527, align 4 - %sunkaddr528 = ptrtoint %struct.bz_stream* %.pre427 to i64 - %sunkaddr529 = add i64 %sunkaddr528, 12 - %sunkaddr530 = inttoptr i64 %sunkaddr529 to i32* - %tmp24 = load i32, i32* %sunkaddr530, align 4 - %inc106 = add i32 %tmp24, 1 - store i32 %inc106, i32* %sunkaddr530, align 4 - %cmp109 = icmp eq i32 %inc106, 0 - br i1 %cmp109, label %if.then.111, label %while.body.68.backedge - -if.then.111: ; preds = %if.end.88 - %sunkaddr531 = ptrtoint %struct.bz_stream* %.pre427 to i64 - %sunkaddr532 = add i64 %sunkaddr531, 16 - %sunkaddr533 = inttoptr i64 %sunkaddr532 to i32* - %tmp25 = load i32, i32* %sunkaddr533, align 4 - %inc114 = add i32 %tmp25, 1 - store i32 %inc114, i32* %sunkaddr533, align 4 - br label %while.body.68.backedge - -while.body.68.backedge: ; preds = %if.then.111, %if.end.88 - %lsr.iv.next481 = add i32 %lsr.iv480, -1 - %cmp70 = icmp sgt i32 %add97, 7 - br i1 %cmp70, label %if.then.72, label %if.end.82 - -if.then.120: ; preds = %if.then.72 - %call = tail call i32 (%struct.__sFILE*, i8*, ...) @fprintf(%struct.__sFILE* getelementptr inbounds ([0 x %struct.__sFILE], [0 x %struct.__sFILE]* @__sF, i64 0, i64 2), i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str, i64 0, i64 0), i32 %inc117) - br label %sw.bb.123 - -sw.bb.123: ; preds = %if.then.120, %if.then.72, %if.end.sw.bb.123_crit_edge - %bsLive127.pre-phi = phi i32* [ %.pre433, %if.end.sw.bb.123_crit_edge ], [ %bsLive69.pre-phi, %if.then.72 ], [ %bsLive69.pre-phi, %if.then.120 ] - %sunkaddr534 = ptrtoint %struct.DState* %s to i64 - %sunkaddr535 = add i64 %sunkaddr534, 8 - %sunkaddr536 = inttoptr i64 %sunkaddr535 to i32* - store i32 25, i32* %sunkaddr536, align 4 - %tmp26 = load i32, i32* %bsLive127.pre-phi, align 4 - %cmp128.395 = icmp sgt i32 %tmp26, 7 - br i1 %cmp128.395, label %sw.bb.123.if.then.130_crit_edge, label %if.end.140.lr.ph - -sw.bb.123.if.then.130_crit_edge: ; preds = %sw.bb.123 - %sunkaddr537 = ptrtoint %struct.DState* %s to i64 - %sunkaddr538 = add i64 %sunkaddr537, 32 - %sunkaddr539 = inttoptr i64 %sunkaddr538 to i32* - %.pre429 = load i32, i32* %sunkaddr539, align 4 - br label %if.then.130 - -if.end.140.lr.ph: ; preds = %sw.bb.123 - %tmp27 = bitcast %struct.DState* %s to %struct.bz_stream** - %.pre428 = load %struct.bz_stream*, %struct.bz_stream** %tmp27, align 8 - %avail_in142.phi.trans.insert = getelementptr inbounds %struct.bz_stream, %struct.bz_stream* %.pre428, i64 0, i32 1 - %.pre432 = load i32, i32* %avail_in142.phi.trans.insert, align 4 - %tmp28 = add i32 %.pre432, -1 - br label %if.end.140 - -if.then.130: ; preds = %while.body.126.backedge, %sw.bb.123.if.then.130_crit_edge - %tmp29 = phi i32 [ %.pre429, %sw.bb.123.if.then.130_crit_edge ], [ %or152, %while.body.126.backedge ] - %.lcssa = phi i32 [ %tmp26, %sw.bb.123.if.then.130_crit_edge ], [ %add155, %while.body.126.backedge ] - %sub134 = add nsw i32 %.lcssa, -8 - %shr135 = lshr i32 %tmp29, %sub134 - store i32 %sub134, i32* %bsLive127.pre-phi, align 4 - %origPtr = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 13 - %tmp30 = load i32, i32* %origPtr, align 4 - %shl175 = shl i32 %tmp30, 8 - %conv176 = and i32 %shr135, 255 - %or177 = or i32 %shl175, %conv176 - store i32 %or177, i32* %origPtr, align 4 - %nInUse = getelementptr inbounds %struct.DState, %struct.DState* %s, i64 0, i32 27 - %tmp31 = load i32, i32* %nInUse, align 4 - %add179 = add nsw i32 %tmp31, 2 - br label %save_state_and_return - -if.end.140: ; preds = %while.body.126.backedge, %if.end.140.lr.ph - %lsr.iv = phi i32 [ %tmp28, %if.end.140.lr.ph ], [ %lsr.iv.next, %while.body.126.backedge ] - %tmp32 = phi i32 [ %tmp26, %if.end.140.lr.ph ], [ %add155, %while.body.126.backedge ] - %cmp143 = icmp eq i32 %lsr.iv, -1 - br i1 %cmp143, label %save_state_and_return, label %if.end.146 - -if.end.146: ; preds = %if.end.140 - %tmp33 = bitcast %struct.bz_stream* %.pre428 to i8** - %sunkaddr541 = ptrtoint %struct.DState* %s to i64 - %sunkaddr542 = add i64 %sunkaddr541, 32 - %sunkaddr543 = inttoptr i64 %sunkaddr542 to i32* - %tmp34 = load i32, i32* %sunkaddr543, align 4 - %shl148 = shl i32 %tmp34, 8 - %tmp35 = load i8*, i8** %tmp33, align 8 - %tmp36 = load i8, i8* %tmp35, align 1 - %conv151 = zext i8 %tmp36 to i32 - %or152 = or i32 %conv151, %shl148 - store i32 %or152, i32* %sunkaddr543, align 4 - %add155 = add nsw i32 %tmp32, 8 - store i32 %add155, i32* %bsLive127.pre-phi, align 4 - %incdec.ptr158 = getelementptr inbounds i8, i8* %tmp35, i64 1 - store i8* %incdec.ptr158, i8** %tmp33, align 8 - %sunkaddr544 = ptrtoint %struct.bz_stream* %.pre428 to i64 - %sunkaddr545 = add i64 %sunkaddr544, 8 - %sunkaddr546 = inttoptr i64 %sunkaddr545 to i32* - store i32 %lsr.iv, i32* %sunkaddr546, align 4 - %sunkaddr547 = ptrtoint %struct.bz_stream* %.pre428 to i64 - %sunkaddr548 = add i64 %sunkaddr547, 12 - %sunkaddr549 = inttoptr i64 %sunkaddr548 to i32* - %tmp37 = load i32, i32* %sunkaddr549, align 4 - %inc164 = add i32 %tmp37, 1 - store i32 %inc164, i32* %sunkaddr549, align 4 - %cmp167 = icmp eq i32 %inc164, 0 - br i1 %cmp167, label %if.then.169, label %while.body.126.backedge - -if.then.169: ; preds = %if.end.146 - %sunkaddr550 = ptrtoint %struct.bz_stream* %.pre428 to i64 - %sunkaddr551 = add i64 %sunkaddr550, 16 - %sunkaddr552 = inttoptr i64 %sunkaddr551 to i32* - %tmp38 = load i32, i32* %sunkaddr552, align 4 - %inc172 = add i32 %tmp38, 1 - store i32 %inc172, i32* %sunkaddr552, align 4 - br label %while.body.126.backedge - -while.body.126.backedge: ; preds = %if.then.169, %if.end.146 - %lsr.iv.next = add i32 %lsr.iv, -1 - %cmp128 = icmp sgt i32 %add155, 7 - br i1 %cmp128, label %if.then.130, label %if.end.140 - -sw.default: ; preds = %if.end, %if.end.thread - %tmp39 = phi i32 [ 0, %if.end.thread ], [ %.pre, %if.end ] - %tmp40 = phi i32 [ 0, %if.end.thread ], [ %.pre406, %if.end ] - %tmp41 = phi i32 [ 0, %if.end.thread ], [ %.pre407, %if.end ] - %tmp42 = phi i32 [ 0, %if.end.thread ], [ %.pre408, %if.end ] - %tmp43 = phi i32 [ 0, %if.end.thread ], [ %.pre409, %if.end ] - %tmp44 = phi i32 [ 0, %if.end.thread ], [ %.pre410, %if.end ] - %tmp45 = phi i32 [ 0, %if.end.thread ], [ %.pre411, %if.end ] - %tmp46 = phi i32 [ 0, %if.end.thread ], [ %.pre412, %if.end ] - %tmp47 = phi i32 [ 0, %if.end.thread ], [ %.pre413, %if.end ] - %tmp48 = phi i32 [ 0, %if.end.thread ], [ %.pre414, %if.end ] - %tmp49 = phi i32 [ 0, %if.end.thread ], [ %.pre415, %if.end ] - %tmp50 = phi i32 [ 0, %if.end.thread ], [ %.pre416, %if.end ] - %tmp51 = phi i32 [ 0, %if.end.thread ], [ %.pre417, %if.end ] - %tmp52 = phi i32 [ 0, %if.end.thread ], [ %.pre418, %if.end ] - %tmp53 = phi i32 [ 0, %if.end.thread ], [ %.pre419, %if.end ] - %tmp54 = phi i32 [ 0, %if.end.thread ], [ %.pre420, %if.end ] - %tmp55 = phi i32 [ 0, %if.end.thread ], [ %.pre421, %if.end ] - %tmp56 = phi i32 [ 0, %if.end.thread ], [ %.pre422, %if.end ] - %tmp57 = phi i32 [ 0, %if.end.thread ], [ %.pre423, %if.end ] - %save_j3.pre-phi469 = phi i32* [ %save_j, %if.end.thread ], [ %save_j3.phi.trans.insert, %if.end ] - %save_t4.pre-phi467 = phi i32* [ %save_t, %if.end.thread ], [ %save_t4.phi.trans.insert, %if.end ] - %save_alphaSize5.pre-phi465 = phi i32* [ %save_alphaSize, %if.end.thread ], [ %save_alphaSize5.phi.trans.insert, %if.end ] - %save_nGroups6.pre-phi463 = phi i32* [ %save_nGroups, %if.end.thread ], [ %save_nGroups6.phi.trans.insert, %if.end ] - %save_nSelectors7.pre-phi461 = phi i32* [ %save_nSelectors, %if.end.thread ], [ %save_nSelectors7.phi.trans.insert, %if.end ] - %save_EOB8.pre-phi459 = phi i32* [ %save_EOB, %if.end.thread ], [ %save_EOB8.phi.trans.insert, %if.end ] - %save_groupNo9.pre-phi457 = phi i32* [ %save_groupNo, %if.end.thread ], [ %save_groupNo9.phi.trans.insert, %if.end ] - %save_groupPos10.pre-phi455 = phi i32* [ %save_groupPos, %if.end.thread ], [ %save_groupPos10.phi.trans.insert, %if.end ] - %save_nextSym11.pre-phi453 = phi i32* [ %save_nextSym, %if.end.thread ], [ %save_nextSym11.phi.trans.insert, %if.end ] - %save_nblockMAX12.pre-phi451 = phi i32* [ %save_nblockMAX, %if.end.thread ], [ %save_nblockMAX12.phi.trans.insert, %if.end ] - %save_nblock13.pre-phi449 = phi i32* [ %save_nblock, %if.end.thread ], [ %save_nblock13.phi.trans.insert, %if.end ] - %save_es14.pre-phi447 = phi i32* [ %save_es, %if.end.thread ], [ %save_es14.phi.trans.insert, %if.end ] - %save_N15.pre-phi445 = phi i32* [ %save_N, %if.end.thread ], [ %save_N15.phi.trans.insert, %if.end ] - %save_curr16.pre-phi443 = phi i32* [ %save_curr, %if.end.thread ], [ %save_curr16.phi.trans.insert, %if.end ] - %save_zt17.pre-phi441 = phi i32* [ %save_zt, %if.end.thread ], [ %save_zt17.phi.trans.insert, %if.end ] - %save_zn18.pre-phi439 = phi i32* [ %save_zn, %if.end.thread ], [ %save_zn18.phi.trans.insert, %if.end ] - %save_zvec19.pre-phi437 = phi i32* [ %save_zvec, %if.end.thread ], [ %save_zvec19.phi.trans.insert, %if.end ] - %save_zj20.pre-phi435 = phi i32* [ %save_zj, %if.end.thread ], [ %save_zj20.phi.trans.insert, %if.end ] - tail call void @bar(i32 4001) - br label %save_state_and_return - -save_state_and_return: ; preds = %sw.default, %if.end.140, %if.then.130, %if.end.82, %if.end.33, %if.then.29 - %tmp58 = phi i32 [ %tmp39, %sw.default ], [ %.pre, %if.then.29 ], [ %.pre, %if.then.130 ], [ %.pre, %if.end.140 ], [ %.pre, %if.end.82 ], [ %.pre, %if.end.33 ] - %tmp59 = phi i32 [ %tmp40, %sw.default ], [ %.pre406, %if.then.29 ], [ %.pre406, %if.then.130 ], [ %.pre406, %if.end.140 ], [ %.pre406, %if.end.82 ], [ %.pre406, %if.end.33 ] - %tmp60 = phi i32 [ %tmp41, %sw.default ], [ %.pre407, %if.then.29 ], [ %.pre407, %if.then.130 ], [ %.pre407, %if.end.140 ], [ %.pre407, %if.end.82 ], [ %.pre407, %if.end.33 ] - %tmp61 = phi i32 [ %tmp43, %sw.default ], [ %.pre409, %if.then.29 ], [ %.pre409, %if.then.130 ], [ %.pre409, %if.end.140 ], [ %.pre409, %if.end.82 ], [ %.pre409, %if.end.33 ] - %tmp62 = phi i32 [ %tmp44, %sw.default ], [ %.pre410, %if.then.29 ], [ %.pre410, %if.then.130 ], [ %.pre410, %if.end.140 ], [ %.pre410, %if.end.82 ], [ %.pre410, %if.end.33 ] - %tmp63 = phi i32 [ %tmp45, %sw.default ], [ %.pre411, %if.then.29 ], [ %.pre411, %if.then.130 ], [ %.pre411, %if.end.140 ], [ %.pre411, %if.end.82 ], [ %.pre411, %if.end.33 ] - %tmp64 = phi i32 [ %tmp46, %sw.default ], [ %.pre412, %if.then.29 ], [ %.pre412, %if.then.130 ], [ %.pre412, %if.end.140 ], [ %.pre412, %if.end.82 ], [ %.pre412, %if.end.33 ] - %tmp65 = phi i32 [ %tmp47, %sw.default ], [ %.pre413, %if.then.29 ], [ %.pre413, %if.then.130 ], [ %.pre413, %if.end.140 ], [ %.pre413, %if.end.82 ], [ %.pre413, %if.end.33 ] - %tmp66 = phi i32 [ %tmp48, %sw.default ], [ %.pre414, %if.then.29 ], [ %.pre414, %if.then.130 ], [ %.pre414, %if.end.140 ], [ %.pre414, %if.end.82 ], [ %.pre414, %if.end.33 ] - %tmp67 = phi i32 [ %tmp49, %sw.default ], [ %.pre415, %if.then.29 ], [ %.pre415, %if.then.130 ], [ %.pre415, %if.end.140 ], [ %.pre415, %if.end.82 ], [ %.pre415, %if.end.33 ] - %tmp68 = phi i32 [ %tmp51, %sw.default ], [ %.pre417, %if.then.29 ], [ %.pre417, %if.then.130 ], [ %.pre417, %if.end.140 ], [ %.pre417, %if.end.82 ], [ %.pre417, %if.end.33 ] - %tmp69 = phi i32 [ %tmp52, %sw.default ], [ %.pre418, %if.then.29 ], [ %.pre418, %if.then.130 ], [ %.pre418, %if.end.140 ], [ %.pre418, %if.end.82 ], [ %.pre418, %if.end.33 ] - %tmp70 = phi i32 [ %tmp53, %sw.default ], [ %.pre419, %if.then.29 ], [ %.pre419, %if.then.130 ], [ %.pre419, %if.end.140 ], [ %.pre419, %if.end.82 ], [ %.pre419, %if.end.33 ] - %tmp71 = phi i32 [ %tmp54, %sw.default ], [ %.pre420, %if.then.29 ], [ %.pre420, %if.then.130 ], [ %.pre420, %if.end.140 ], [ %.pre420, %if.end.82 ], [ %.pre420, %if.end.33 ] - %tmp72 = phi i32 [ %tmp55, %sw.default ], [ %.pre421, %if.then.29 ], [ %.pre421, %if.then.130 ], [ %.pre421, %if.end.140 ], [ %.pre421, %if.end.82 ], [ %.pre421, %if.end.33 ] - %tmp73 = phi i32 [ %tmp56, %sw.default ], [ %.pre422, %if.then.29 ], [ %.pre422, %if.then.130 ], [ %.pre422, %if.end.140 ], [ %.pre422, %if.end.82 ], [ %.pre422, %if.end.33 ] - %tmp74 = phi i32 [ %tmp57, %sw.default ], [ %.pre423, %if.then.29 ], [ %.pre423, %if.then.130 ], [ %.pre423, %if.end.140 ], [ %.pre423, %if.end.82 ], [ %.pre423, %if.end.33 ] - %save_j3.pre-phi468 = phi i32* [ %save_j3.pre-phi469, %sw.default ], [ %save_j3.phi.trans.insert, %if.then.29 ], [ %save_j3.phi.trans.insert, %if.then.130 ], [ %save_j3.phi.trans.insert, %if.end.140 ], [ %save_j3.phi.trans.insert, %if.end.82 ], [ %save_j3.phi.trans.insert, %if.end.33 ] - %save_t4.pre-phi466 = phi i32* [ %save_t4.pre-phi467, %sw.default ], [ %save_t4.phi.trans.insert, %if.then.29 ], [ %save_t4.phi.trans.insert, %if.then.130 ], [ %save_t4.phi.trans.insert, %if.end.140 ], [ %save_t4.phi.trans.insert, %if.end.82 ], [ %save_t4.phi.trans.insert, %if.end.33 ] - %save_alphaSize5.pre-phi464 = phi i32* [ %save_alphaSize5.pre-phi465, %sw.default ], [ %save_alphaSize5.phi.trans.insert, %if.then.29 ], [ %save_alphaSize5.phi.trans.insert, %if.then.130 ], [ %save_alphaSize5.phi.trans.insert, %if.end.140 ], [ %save_alphaSize5.phi.trans.insert, %if.end.82 ], [ %save_alphaSize5.phi.trans.insert, %if.end.33 ] - %save_nGroups6.pre-phi462 = phi i32* [ %save_nGroups6.pre-phi463, %sw.default ], [ %save_nGroups6.phi.trans.insert, %if.then.29 ], [ %save_nGroups6.phi.trans.insert, %if.then.130 ], [ %save_nGroups6.phi.trans.insert, %if.end.140 ], [ %save_nGroups6.phi.trans.insert, %if.end.82 ], [ %save_nGroups6.phi.trans.insert, %if.end.33 ] - %save_nSelectors7.pre-phi460 = phi i32* [ %save_nSelectors7.pre-phi461, %sw.default ], [ %save_nSelectors7.phi.trans.insert, %if.then.29 ], [ %save_nSelectors7.phi.trans.insert, %if.then.130 ], [ %save_nSelectors7.phi.trans.insert, %if.end.140 ], [ %save_nSelectors7.phi.trans.insert, %if.end.82 ], [ %save_nSelectors7.phi.trans.insert, %if.end.33 ] - %save_EOB8.pre-phi458 = phi i32* [ %save_EOB8.pre-phi459, %sw.default ], [ %save_EOB8.phi.trans.insert, %if.then.29 ], [ %save_EOB8.phi.trans.insert, %if.then.130 ], [ %save_EOB8.phi.trans.insert, %if.end.140 ], [ %save_EOB8.phi.trans.insert, %if.end.82 ], [ %save_EOB8.phi.trans.insert, %if.end.33 ] - %save_groupNo9.pre-phi456 = phi i32* [ %save_groupNo9.pre-phi457, %sw.default ], [ %save_groupNo9.phi.trans.insert, %if.then.29 ], [ %save_groupNo9.phi.trans.insert, %if.then.130 ], [ %save_groupNo9.phi.trans.insert, %if.end.140 ], [ %save_groupNo9.phi.trans.insert, %if.end.82 ], [ %save_groupNo9.phi.trans.insert, %if.end.33 ] - %save_groupPos10.pre-phi454 = phi i32* [ %save_groupPos10.pre-phi455, %sw.default ], [ %save_groupPos10.phi.trans.insert, %if.then.29 ], [ %save_groupPos10.phi.trans.insert, %if.then.130 ], [ %save_groupPos10.phi.trans.insert, %if.end.140 ], [ %save_groupPos10.phi.trans.insert, %if.end.82 ], [ %save_groupPos10.phi.trans.insert, %if.end.33 ] - %save_nextSym11.pre-phi452 = phi i32* [ %save_nextSym11.pre-phi453, %sw.default ], [ %save_nextSym11.phi.trans.insert, %if.then.29 ], [ %save_nextSym11.phi.trans.insert, %if.then.130 ], [ %save_nextSym11.phi.trans.insert, %if.end.140 ], [ %save_nextSym11.phi.trans.insert, %if.end.82 ], [ %save_nextSym11.phi.trans.insert, %if.end.33 ] - %save_nblockMAX12.pre-phi450 = phi i32* [ %save_nblockMAX12.pre-phi451, %sw.default ], [ %save_nblockMAX12.phi.trans.insert, %if.then.29 ], [ %save_nblockMAX12.phi.trans.insert, %if.then.130 ], [ %save_nblockMAX12.phi.trans.insert, %if.end.140 ], [ %save_nblockMAX12.phi.trans.insert, %if.end.82 ], [ %save_nblockMAX12.phi.trans.insert, %if.end.33 ] - %save_nblock13.pre-phi448 = phi i32* [ %save_nblock13.pre-phi449, %sw.default ], [ %save_nblock13.phi.trans.insert, %if.then.29 ], [ %save_nblock13.phi.trans.insert, %if.then.130 ], [ %save_nblock13.phi.trans.insert, %if.end.140 ], [ %save_nblock13.phi.trans.insert, %if.end.82 ], [ %save_nblock13.phi.trans.insert, %if.end.33 ] - %save_es14.pre-phi446 = phi i32* [ %save_es14.pre-phi447, %sw.default ], [ %save_es14.phi.trans.insert, %if.then.29 ], [ %save_es14.phi.trans.insert, %if.then.130 ], [ %save_es14.phi.trans.insert, %if.end.140 ], [ %save_es14.phi.trans.insert, %if.end.82 ], [ %save_es14.phi.trans.insert, %if.end.33 ] - %save_N15.pre-phi444 = phi i32* [ %save_N15.pre-phi445, %sw.default ], [ %save_N15.phi.trans.insert, %if.then.29 ], [ %save_N15.phi.trans.insert, %if.then.130 ], [ %save_N15.phi.trans.insert, %if.end.140 ], [ %save_N15.phi.trans.insert, %if.end.82 ], [ %save_N15.phi.trans.insert, %if.end.33 ] - %save_curr16.pre-phi442 = phi i32* [ %save_curr16.pre-phi443, %sw.default ], [ %save_curr16.phi.trans.insert, %if.then.29 ], [ %save_curr16.phi.trans.insert, %if.then.130 ], [ %save_curr16.phi.trans.insert, %if.end.140 ], [ %save_curr16.phi.trans.insert, %if.end.82 ], [ %save_curr16.phi.trans.insert, %if.end.33 ] - %save_zt17.pre-phi440 = phi i32* [ %save_zt17.pre-phi441, %sw.default ], [ %save_zt17.phi.trans.insert, %if.then.29 ], [ %save_zt17.phi.trans.insert, %if.then.130 ], [ %save_zt17.phi.trans.insert, %if.end.140 ], [ %save_zt17.phi.trans.insert, %if.end.82 ], [ %save_zt17.phi.trans.insert, %if.end.33 ] - %save_zn18.pre-phi438 = phi i32* [ %save_zn18.pre-phi439, %sw.default ], [ %save_zn18.phi.trans.insert, %if.then.29 ], [ %save_zn18.phi.trans.insert, %if.then.130 ], [ %save_zn18.phi.trans.insert, %if.end.140 ], [ %save_zn18.phi.trans.insert, %if.end.82 ], [ %save_zn18.phi.trans.insert, %if.end.33 ] - %save_zvec19.pre-phi436 = phi i32* [ %save_zvec19.pre-phi437, %sw.default ], [ %save_zvec19.phi.trans.insert, %if.then.29 ], [ %save_zvec19.phi.trans.insert, %if.then.130 ], [ %save_zvec19.phi.trans.insert, %if.end.140 ], [ %save_zvec19.phi.trans.insert, %if.end.82 ], [ %save_zvec19.phi.trans.insert, %if.end.33 ] - %save_zj20.pre-phi434 = phi i32* [ %save_zj20.pre-phi435, %sw.default ], [ %save_zj20.phi.trans.insert, %if.then.29 ], [ %save_zj20.phi.trans.insert, %if.then.130 ], [ %save_zj20.phi.trans.insert, %if.end.140 ], [ %save_zj20.phi.trans.insert, %if.end.82 ], [ %save_zj20.phi.trans.insert, %if.end.33 ] - %nblock.1 = phi i32 [ %tmp50, %sw.default ], [ %.pre416, %if.then.29 ], [ 0, %if.then.130 ], [ %.pre416, %if.end.140 ], [ %.pre416, %if.end.82 ], [ %.pre416, %if.end.33 ] - %alphaSize.1 = phi i32 [ %tmp42, %sw.default ], [ %.pre408, %if.then.29 ], [ %add179, %if.then.130 ], [ %.pre408, %if.end.140 ], [ %.pre408, %if.end.82 ], [ %.pre408, %if.end.33 ] - %retVal.0 = phi i32 [ 0, %sw.default ], [ -5, %if.then.29 ], [ -4, %if.then.130 ], [ 0, %if.end.140 ], [ 0, %if.end.82 ], [ 0, %if.end.33 ] - store i32 %tmp58, i32* %save_i, align 4 - store i32 %tmp59, i32* %save_j3.pre-phi468, align 4 - store i32 %tmp60, i32* %save_t4.pre-phi466, align 4 - store i32 %alphaSize.1, i32* %save_alphaSize5.pre-phi464, align 4 - store i32 %tmp61, i32* %save_nGroups6.pre-phi462, align 4 - store i32 %tmp62, i32* %save_nSelectors7.pre-phi460, align 4 - store i32 %tmp63, i32* %save_EOB8.pre-phi458, align 4 - store i32 %tmp64, i32* %save_groupNo9.pre-phi456, align 4 - store i32 %tmp65, i32* %save_groupPos10.pre-phi454, align 4 - store i32 %tmp66, i32* %save_nextSym11.pre-phi452, align 4 - store i32 %tmp67, i32* %save_nblockMAX12.pre-phi450, align 4 - store i32 %nblock.1, i32* %save_nblock13.pre-phi448, align 4 - store i32 %tmp68, i32* %save_es14.pre-phi446, align 4 - store i32 %tmp69, i32* %save_N15.pre-phi444, align 4 - store i32 %tmp70, i32* %save_curr16.pre-phi442, align 4 - store i32 %tmp71, i32* %save_zt17.pre-phi440, align 4 - store i32 %tmp72, i32* %save_zn18.pre-phi438, align 4 - store i32 %tmp73, i32* %save_zvec19.pre-phi436, align 4 - store i32 %tmp74, i32* %save_zj20.pre-phi434, align 4 - ret i32 %retVal.0 -} - -!0 = !{!"branch_weights", i32 10, i32 1} diff --git a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll index 90093f94d0ad..708ae083eb86 100644 --- a/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll +++ b/test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll @@ -1,4 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -disable-post-ra < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios -disable-fp-elim -disable-post-ra < %s | FileCheck %s --check-prefix=CHECK-MACHO ; This test aims to check basic correctness of frame layout & ; frame access code. There are 8 functions in this test file, @@ -97,27 +98,47 @@ entry: ; CHECK-LABEL: novla_nodynamicrealign_call ; CHECK: .cfi_startproc ; Check that used callee-saved registers are saved -; CHECK: stp x20, x19, [sp, #-32]! -; Check that the frame pointer is created: -; CHECK: stp x29, x30, [sp, #16] -; CHECK: add x29, sp, #16 +; CHECK: sub sp, sp, #32 +; CHECK: stp x19, x30, [sp, #16] ; Check correctness of cfi pseudo-instructions -; CHECK: .cfi_def_cfa w29, 16 +; CHECK: .cfi_def_cfa_offset 32 ; CHECK: .cfi_offset w30, -8 -; CHECK: .cfi_offset w29, -16 -; CHECK: .cfi_offset w19, -24 -; CHECK: .cfi_offset w20, -32 -; Check correct access to arguments passed on the stack, through frame pointer -; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] -; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] +; CHECK: .cfi_offset w19, -16 +; Check correct access to arguments passed on the stack, through stack pointer +; CHECK: ldr d[[DARG:[0-9]+]], [sp, #56] +; CHECK: ldr w[[IARG:[0-9]+]], [sp, #40] ; Check correct access to local variable on the stack, through stack pointer ; CHECK: ldr w[[ILOC:[0-9]+]], [sp, #12] ; Check epilogue: -; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldp x19, x30, [sp, #16] ; CHECK: ret ; CHECK: .cfi_endproc +; CHECK-MACHO-LABEL: _novla_nodynamicrealign_call: +; CHECK-MACHO: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK-MACHO: sub sp, sp, #48 +; CHECK-MACHO: stp x20, x19, [sp, #16] +; Check that the frame pointer is created: +; CHECK-MACHO: stp x29, x30, [sp, #32] +; CHECK-MACHO: add x29, sp, #32 +; Check correctness of cfi pseudo-instructions +; CHECK-MACHO: .cfi_def_cfa w29, 16 +; CHECK-MACHO: .cfi_offset w30, -8 +; CHECK-MACHO: .cfi_offset w29, -16 +; CHECK-MACHO: .cfi_offset w19, -24 +; CHECK-MACHO: .cfi_offset w20, -32 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] +; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20] +; Check correct access to local variable on the stack, through stack pointer +; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [sp, #12] +; Check epilogue: +; CHECK-MACHO: ldp x29, x30, [sp, #32] +; CHECK-MACHO: ldp x20, x19, [sp, #16] +; CHECK-MACHO: ret +; CHECK-MACHO: .cfi_endproc + declare i32 @g() #0 @@ -159,7 +180,7 @@ entry: ; CHECK-LABEL: novla_dynamicrealign_call ; CHECK: .cfi_startproc ; Check that used callee-saved registers are saved -; CHECK: stp x20, x19, [sp, #-32]! +; CHECK: str x19, [sp, #-32]! ; Check that the frame pointer is created: ; CHECK: stp x29, x30, [sp, #16] ; CHECK: add x29, sp, #16 @@ -170,8 +191,7 @@ entry: ; CHECK: .cfi_def_cfa w29, 16 ; CHECK: .cfi_offset w30, -8 ; CHECK: .cfi_offset w29, -16 -; CHECK: .cfi_offset w19, -24 -; CHECK: .cfi_offset w20, -32 +; CHECK: .cfi_offset w19, -32 ; Check correct access to arguments passed on the stack, through frame pointer ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] @@ -181,10 +201,39 @@ entry: ; Check that stack pointer get restored from frame pointer. ; CHECK: sub sp, x29, #16 // =16 ; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldr x19, [sp], #32 ; CHECK: ret ; CHECK: .cfi_endproc +; CHECK-MACHO-LABEL: _novla_dynamicrealign_call: +; CHECK-MACHO: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK-MACHO: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK-MACHO: stp x29, x30, [sp, #16] +; CHECK-MACHO: add x29, sp, #16 +; Check the dynamic realignment of the stack pointer to a 128-byte boundary +; CHECK-MACHO: sub x9, sp, #96 +; CHECK-MACHO: and sp, x9, #0xffffffffffffff80 +; Check correctness of cfi pseudo-instructions +; CHECK-MACHO: .cfi_def_cfa w29, 16 +; CHECK-MACHO: .cfi_offset w30, -8 +; CHECK-MACHO: .cfi_offset w29, -16 +; CHECK-MACHO: .cfi_offset w19, -24 +; CHECK-MACHO: .cfi_offset w20, -32 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] +; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20] +; Check correct access to local variable on the stack, through re-aligned stack pointer +; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [sp] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK-MACHO: sub sp, x29, #16 +; CHECK-MACHO: ldp x29, x30, [sp, #16] +; CHECK-MACHO: ldp x20, x19, [sp], #32 +; CHECK-MACHO: ret +; CHECK-MACHO: .cfi_endproc + ; Function Attrs: nounwind define i32 @novla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { @@ -336,7 +385,7 @@ entry: ; CHECK-LABEL: vla_dynamicrealign_call ; CHECK: .cfi_startproc ; Check that used callee-saved registers are saved -; CHECK: stp x22, x21, [sp, #-48]! +; CHECK: str x21, [sp, #-48]! ; CHECK: stp x20, x19, [sp, #16] ; Check that the frame pointer is created: ; CHECK: stp x29, x30, [sp, #32] @@ -354,8 +403,7 @@ entry: ; CHECK: .cfi_offset w29, -16 ; CHECK: .cfi_offset w19, -24 ; CHECK: .cfi_offset w20, -32 -; CHECK: .cfi_offset w21, -40 -; CHECK: .cfi_offset w22, -48 +; CHECK: .cfi_offset w21, -48 ; Check correct access to arguments passed on the stack, through frame pointer ; CHECK: ldr w[[IARG:[0-9]+]], [x29, #24] ; CHECK: ldr d[[DARG:[0-9]+]], [x29, #40] @@ -376,10 +424,57 @@ entry: ; CHECK: sub sp, x29, #32 ; CHECK: ldp x29, x30, [sp, #32] ; CHECK: ldp x20, x19, [sp, #16] -; CHECK: ldp x22, x21, [sp], #48 +; CHECK: ldr x21, [sp], #48 ; CHECK: ret ; CHECK: .cfi_endproc +; CHECK-MACHO-LABEL: _vla_dynamicrealign_call: +; CHECK-MACHO: .cfi_startproc +; Check that used callee-saved registers are saved +; CHECK-MACHO: stp x22, x21, [sp, #-48]! +; CHECK-MACHO: stp x20, x19, [sp, #16] +; Check that the frame pointer is created: +; CHECK-MACHO: stp x29, x30, [sp, #32] +; CHECK-MACHO: add x29, sp, #32 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK-MACHO: sub x9, sp, #80 +; CHECK-MACHO: and sp, x9, #0xffffffffffffff80 +; CHECK-MACHO: mov x19, sp +; Check correctness of cfi pseudo-instructions +; CHECK-MACHO: .cfi_def_cfa w29, 16 +; CHECK-MACHO: .cfi_offset w30, -8 +; CHECK-MACHO: .cfi_offset w29, -16 +; CHECK-MACHO: .cfi_offset w19, -24 +; CHECK-MACHO: .cfi_offset w20, -32 +; CHECK-MACHO: .cfi_offset w21, -40 +; CHECK-MACHO: .cfi_offset w22, -48 +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20] +; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK-MACHO: mov w9, w0 +; CHECK-MACHO: mov x10, sp +; CHECK-MACHO: lsl x9, x9, #2 +; CHECK-MACHO: add x9, x9, #15 +; CHECK-MACHO: and x9, x9, #0x7fffffff0 +; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK-MACHO: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK-MACHO: sub sp, x29, #32 +; CHECK-MACHO: ldp x29, x30, [sp, #32] +; CHECK-MACHO: ldp x20, x19, [sp, #16] +; CHECK-MACHO: ldp x22, x21, [sp], #48 +; CHECK-MACHO: ret +; CHECK-MACHO: .cfi_endproc + ; Function Attrs: nounwind define i32 @vla_dynamicrealign_nocall(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { @@ -398,7 +493,7 @@ entry: ; CHECK-LABEL: vla_dynamicrealign_nocall ; Check that used callee-saved registers are saved -; CHECK: stp x20, x19, [sp, #-32]! +; CHECK: str x19, [sp, #-32]! ; Check that the frame pointer is created: ; CHECK: stp x29, x30, [sp, #16] ; CHECK: add x29, sp, #16 @@ -428,9 +523,44 @@ entry: ; Check that stack pointer get restored from frame pointer. ; CHECK: sub sp, x29, #16 ; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldr x19, [sp], #32 ; CHECK: ret +; CHECK-MACHO-LABEL: _vla_dynamicrealign_nocall: +; Check that used callee-saved registers are saved +; CHECK-MACHO: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK-MACHO: stp x29, x30, [sp, #16] +; CHECK-MACHO: add x29, sp, #16 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK-MACHO: sub x9, sp, #96 +; CHECK-MACHO: and sp, x9, #0xffffffffffffff80 +; CHECK-MACHO: mov x19, sp +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20] +; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK-MACHO: mov w9, w0 +; CHECK-MACHO: mov x10, sp +; CHECK-MACHO: lsl x9, x9, #2 +; CHECK-MACHO: add x9, x9, #15 +; CHECK-MACHO: and x9, x9, #0x7fffffff0 +; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK-MACHO: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK-MACHO: sub sp, x29, #16 +; CHECK-MACHO: ldp x29, x30, [sp, #16] +; CHECK-MACHO: ldp x20, x19, [sp], #32 +; CHECK-MACHO: ret + ; Function Attrs: nounwind define i32 @vla_dynamicrealign_nocall_large_align(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, i32 %i7, i32 %i8, i32 %i9, i32 %i10, double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10) #1 { @@ -449,7 +579,7 @@ entry: ; CHECK-LABEL: vla_dynamicrealign_nocall_large_align ; Check that used callee-saved registers are saved -; CHECK: stp x20, x19, [sp, #-32]! +; CHECK: stp x28, x19, [sp, #-32]! ; Check that the frame pointer is created: ; CHECK: stp x29, x30, [sp, #16] ; CHECK: add x29, sp, #16 @@ -479,9 +609,44 @@ entry: ; Check that stack pointer get restored from frame pointer. ; CHECK: sub sp, x29, #16 ; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldp x28, x19, [sp], #32 ; CHECK: ret +; CHECK-MACHO-LABEL: _vla_dynamicrealign_nocall_large_align: +; Check that used callee-saved registers are saved +; CHECK-MACHO: stp x20, x19, [sp, #-32]! +; Check that the frame pointer is created: +; CHECK-MACHO: stp x29, x30, [sp, #16] +; CHECK-MACHO: add x29, sp, #16 +; Check that the stack pointer gets re-aligned to 128 +; bytes & the base pointer (x19) gets initialized to +; this 128-byte aligned area for local variables & +; spill slots +; CHECK-MACHO: sub x9, sp, #7, lsl #12 +; CHECK-MACHO: and sp, x9, #0xffffffffffff8000 +; CHECK-MACHO: mov x19, sp +; Check correct access to arguments passed on the stack, through frame pointer +; CHECK-MACHO: ldr w[[IARG:[0-9]+]], [x29, #20] +; CHECK-MACHO: ldr d[[DARG:[0-9]+]], [x29, #32] +; Check correct reservation of 16-byte aligned VLA (size in w0) on stack +; and set-up of base pointer (x19). +; CHECK-MACHO: mov w9, w0 +; CHECK-MACHO: mov x10, sp +; CHECK-MACHO: lsl x9, x9, #2 +; CHECK-MACHO: add x9, x9, #15 +; CHECK-MACHO: and x9, x9, #0x7fffffff0 +; CHECK-MACHO: sub x[[VLASPTMP:[0-9]+]], x10, x9 +; CHECK-MACHO: mov sp, x[[VLASPTMP]] +; Check correct access to local variable, through base pointer +; CHECK-MACHO: ldr w[[ILOC:[0-9]+]], [x19] +; CHECK-MACHO: ldr w[[VLA:[0-9]+]], [x[[VLASPTMP]]] +; Check epilogue: +; Check that stack pointer get restored from frame pointer. +; CHECK-MACHO: sub sp, x29, #16 +; CHECK-MACHO: ldp x29, x30, [sp, #16] +; CHECK-MACHO: ldp x20, x19, [sp], #32 +; CHECK-MACHO: ret + define void @realign_conditional(i1 %b) { entry: @@ -509,7 +674,7 @@ bb1: define void @realign_conditional2(i1 %b) { entry: - %tmp = alloca i8, i32 4 + %tmp = alloca i8, i32 16 br i1 %b, label %bb0, label %bb1 bb0: @@ -522,18 +687,18 @@ bb1: ; CHECK-LABEL: realign_conditional2 ; Extra realignment in the prologue (performance issue). +; CHECK: tbz {{.*}} .[[LABEL:.*]] ; CHECK: sub x9, sp, #32 // =32 ; CHECK: and sp, x9, #0xffffffffffffffe0 ; CHECK: mov x19, sp -; CHECK: tbz {{.*}} .[[LABEL:.*]] ; Stack is realigned in a non-entry BB. ; CHECK: sub [[REG:x[01-9]+]], sp, #64 ; CHECK: and sp, [[REG]], #0xffffffffffffffe0 ; CHECK: .[[LABEL]]: ; CHECK: ret -attributes #0 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } !1 = !{!2, !2, i64 0} !2 = !{!"int", !3, i64 0} diff --git a/test/CodeGen/AArch64/aarch64-gep-opt.ll b/test/CodeGen/AArch64/aarch64-gep-opt.ll index 93e2ff14ac71..cae00a9b1cb3 100644 --- a/test/CodeGen/AArch64/aarch64-gep-opt.ll +++ b/test/CodeGen/AArch64/aarch64-gep-opt.ll @@ -1,6 +1,9 @@ ; RUN: llc -O3 -aarch64-gep-opt=true -verify-machineinstrs %s -o - | FileCheck %s +; RUN: llc -O3 -aarch64-gep-opt=true -mattr=-use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s +; RUN: llc -O3 -aarch64-gep-opt=true -mattr=+use-aa -print-after=codegenprepare < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s ; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cyclone < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s ; RUN: llc -O3 -aarch64-gep-opt=true -print-after=codegenprepare -mcpu=cortex-a53 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s + target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" target triple = "aarch64-linux-gnueabi" diff --git a/test/CodeGen/AArch64/aarch64-interleaved-accesses-extract-user.ll b/test/CodeGen/AArch64/aarch64-interleaved-accesses-extract-user.ll new file mode 100644 index 000000000000..8628c4288c69 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-interleaved-accesses-extract-user.ll @@ -0,0 +1,86 @@ +; RUN: opt < %s -mtriple=aarch64 -interleaved-access -S | FileCheck %s + +; CHECK-LABEL: @extract_user_basic( +; CHECK: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %ldN, 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 1 +define void @extract_user_basic(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + br i1 %C, label %if.then, label %if.merge + +if.then: + %E = extractelement <8 x i32> %L, i32 2 + br label %if.merge + +if.merge: + ret void +} + +; CHECK-LABEL: @extract_user_multi( +; CHECK: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %ldN, 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 1 +define void @extract_user_multi(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + br i1 %C, label %if.then, label %if.merge + +if.then: + %E1 = extractelement <8 x i32> %L, i32 0 + br label %if.merge + +if.merge: + %E2 = extractelement <8 x i32> %L, i32 2 + ret void +} + +; CHECK-LABEL: @extract_user_multi_no_dom( +; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +define void @extract_user_multi_no_dom(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %E1 = extractelement <8 x i32> %L, i32 0 + br i1 %C, label %if.then, label %if.merge + +if.then: + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E2 = extractelement <8 x i32> %L, i32 2 + br label %if.merge + +if.merge: + ret void +} + +; CHECK-LABEL: @extract_user_wrong_const_index( +; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +define void @extract_user_wrong_const_index(<8 x i32>* %A) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 1 + ret void +} + +; CHECK-LABEL: @extract_user_undef_index( +; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +define void @extract_user_undef_index(<8 x i32>* %A) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 undef + ret void +} + +; CHECK-LABEL: @extract_user_var_index( +; CHECK-NOT: %ldN = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0v4i32 +define void @extract_user_var_index(<8 x i32>* %A, i32 %I) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 %I + ret void +} diff --git a/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll b/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll index 1bc2a3ccb1ca..845050156baa 100644 --- a/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll +++ b/test/CodeGen/AArch64/aarch64-interleaved-accesses.ll @@ -268,3 +268,15 @@ define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind { store <3 x float> %tmp1, <3 x float>* %p, align 16 ret void } + +; NEON-LABEL: load_factor2_with_extract_user: +; NEON: ld2 { v0.4s, v1.4s }, [x0] +; NEON: mov w0, v0.s[1] +; NONEON-LABEL: load_factor2_with_extract_user: +; NONEON-NOT: ld2 +define i32 @load_factor2_with_extract_user(<8 x i32>* %a) { + %1 = load <8 x i32>, <8 x i32>* %a, align 8 + %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> + %3 = extractelement <8 x i32> %1, i32 2 + ret i32 %3 +} diff --git a/test/CodeGen/AArch64/aarch64-smull.ll b/test/CodeGen/AArch64/aarch64-smull.ll index ec0e2de92d0d..1c8d13a00b2a 100644 --- a/test/CodeGen/AArch64/aarch64-smull.ll +++ b/test/CodeGen/AArch64/aarch64-smull.ll @@ -234,7 +234,7 @@ define <8 x i16> @smull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind { define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind { ; Do not use SMULL if the BUILD_VECTOR element values are too big. ; CHECK-LABEL: smull_noextvec_v8i8_v8i16: -; CHECK: movz +; CHECK: mov ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h %tmp3 = sext <8 x i8> %arg to <8 x i16> %tmp4 = mul <8 x i16> %tmp3, @@ -268,7 +268,7 @@ define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind { define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind { ; Do not use SMULL if the BUILD_VECTOR element values are too big. ; CHECK-LABEL: umull_noextvec_v8i8_v8i16: -; CHECK: movz +; CHECK: mov ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h %tmp3 = zext <8 x i8> %arg to <8 x i16> %tmp4 = mul <8 x i16> %tmp3, diff --git a/test/CodeGen/AArch64/aarch64-stp-cluster.ll b/test/CodeGen/AArch64/aarch64-stp-cluster.ll new file mode 100644 index 000000000000..5cab38eafb52 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-stp-cluster.ll @@ -0,0 +1,149 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -aarch64-stp-suppress=false -o - 2>&1 > /dev/null | FileCheck %s + +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: stp_i64_scale:BB#0 +; CHECK:Cluster ld/st SU(4) - SU(3) +; CHECK:Cluster ld/st SU(2) - SU(5) +; CHECK:SU(4): STRXui %vreg1, %vreg0, 1 +; CHECK:SU(3): STRXui %vreg1, %vreg0, 2 +; CHECK:SU(2): STRXui %vreg1, %vreg0, 3 +; CHECK:SU(5): STRXui %vreg1, %vreg0, 4 +define i64 @stp_i64_scale(i64* nocapture %P, i64 %v) { +entry: + %arrayidx = getelementptr inbounds i64, i64* %P, i64 3 + store i64 %v, i64* %arrayidx + %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2 + store i64 %v, i64* %arrayidx1 + %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1 + store i64 %v, i64* %arrayidx2 + %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4 + store i64 %v, i64* %arrayidx3 + ret i64 %v +} + +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: stp_i32_scale:BB#0 +; CHECK:Cluster ld/st SU(4) - SU(3) +; CHECK:Cluster ld/st SU(2) - SU(5) +; CHECK:SU(4): STRWui %vreg1, %vreg0, 1 +; CHECK:SU(3): STRWui %vreg1, %vreg0, 2 +; CHECK:SU(2): STRWui %vreg1, %vreg0, 3 +; CHECK:SU(5): STRWui %vreg1, %vreg0, 4 +define i32 @stp_i32_scale(i32* nocapture %P, i32 %v) { +entry: + %arrayidx = getelementptr inbounds i32, i32* %P, i32 3 + store i32 %v, i32* %arrayidx + %arrayidx1 = getelementptr inbounds i32, i32* %P, i32 2 + store i32 %v, i32* %arrayidx1 + %arrayidx2 = getelementptr inbounds i32, i32* %P, i32 1 + store i32 %v, i32* %arrayidx2 + %arrayidx3 = getelementptr inbounds i32, i32* %P, i32 4 + store i32 %v, i32* %arrayidx3 + ret i32 %v +} + +; CHECK:********** MI Scheduling ********** +; CHECK-LABEL:stp_i64_unscale:BB#0 entry +; CHECK:Cluster ld/st SU(5) - SU(2) +; CHECK:Cluster ld/st SU(4) - SU(3) +; CHECK:SU(5): STURXi %vreg1, %vreg0, -32 +; CHECK:SU(2): STURXi %vreg1, %vreg0, -24 +; CHECK:SU(4): STURXi %vreg1, %vreg0, -16 +; CHECK:SU(3): STURXi %vreg1, %vreg0, -8 +define void @stp_i64_unscale(i64* nocapture %P, i64 %v) #0 { +entry: + %arrayidx = getelementptr inbounds i64, i64* %P, i64 -3 + store i64 %v, i64* %arrayidx + %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 -1 + store i64 %v, i64* %arrayidx1 + %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 -2 + store i64 %v, i64* %arrayidx2 + %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 -4 + store i64 %v, i64* %arrayidx3 + ret void +} + +; CHECK:********** MI Scheduling ********** +; CHECK-LABEL:stp_i32_unscale:BB#0 entry +; CHECK:Cluster ld/st SU(5) - SU(2) +; CHECK:Cluster ld/st SU(4) - SU(3) +; CHECK:SU(5): STURWi %vreg1, %vreg0, -16 +; CHECK:SU(2): STURWi %vreg1, %vreg0, -12 +; CHECK:SU(4): STURWi %vreg1, %vreg0, -8 +; CHECK:SU(3): STURWi %vreg1, %vreg0, -4 +define void @stp_i32_unscale(i32* nocapture %P, i32 %v) #0 { +entry: + %arrayidx = getelementptr inbounds i32, i32* %P, i32 -3 + store i32 %v, i32* %arrayidx + %arrayidx1 = getelementptr inbounds i32, i32* %P, i32 -1 + store i32 %v, i32* %arrayidx1 + %arrayidx2 = getelementptr inbounds i32, i32* %P, i32 -2 + store i32 %v, i32* %arrayidx2 + %arrayidx3 = getelementptr inbounds i32, i32* %P, i32 -4 + store i32 %v, i32* %arrayidx3 + ret void +} + +; CHECK:********** MI Scheduling ********** +; CHECK-LABEL:stp_double:BB#0 +; CHECK:Cluster ld/st SU(3) - SU(4) +; CHECK:Cluster ld/st SU(2) - SU(5) +; CHECK:SU(3): STRDui %vreg1, %vreg0, 1 +; CHECK:SU(4): STRDui %vreg1, %vreg0, 2 +; CHECK:SU(2): STRDui %vreg1, %vreg0, 3 +; CHECK:SU(5): STRDui %vreg1, %vreg0, 4 +define void @stp_double(double* nocapture %P, double %v) { +entry: + %arrayidx = getelementptr inbounds double, double* %P, i64 3 + store double %v, double* %arrayidx + %arrayidx1 = getelementptr inbounds double, double* %P, i64 1 + store double %v, double* %arrayidx1 + %arrayidx2 = getelementptr inbounds double, double* %P, i64 2 + store double %v, double* %arrayidx2 + %arrayidx3 = getelementptr inbounds double, double* %P, i64 4 + store double %v, double* %arrayidx3 + ret void +} + +; CHECK:********** MI Scheduling ********** +; CHECK-LABEL:stp_float:BB#0 +; CHECK:Cluster ld/st SU(3) - SU(4) +; CHECK:Cluster ld/st SU(2) - SU(5) +; CHECK:SU(3): STRSui %vreg1, %vreg0, 1 +; CHECK:SU(4): STRSui %vreg1, %vreg0, 2 +; CHECK:SU(2): STRSui %vreg1, %vreg0, 3 +; CHECK:SU(5): STRSui %vreg1, %vreg0, 4 +define void @stp_float(float* nocapture %P, float %v) { +entry: + %arrayidx = getelementptr inbounds float, float* %P, i64 3 + store float %v, float* %arrayidx + %arrayidx1 = getelementptr inbounds float, float* %P, i64 1 + store float %v, float* %arrayidx1 + %arrayidx2 = getelementptr inbounds float, float* %P, i64 2 + store float %v, float* %arrayidx2 + %arrayidx3 = getelementptr inbounds float, float* %P, i64 4 + store float %v, float* %arrayidx3 + ret void +} + +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: stp_volatile:BB#0 +; CHECK-NOT: Cluster ld/st +; CHECK:SU(2): STRXui %vreg1, %vreg0, 3; mem:Volatile +; CHECK:SU(3): STRXui %vreg1, %vreg0, 2; mem:Volatile +; CHECK:SU(4): STRXui %vreg1, %vreg0, 1; mem:Volatile +; CHECK:SU(5): STRXui %vreg1, %vreg0, 4; mem:Volatile +define i64 @stp_volatile(i64* nocapture %P, i64 %v) { +entry: + %arrayidx = getelementptr inbounds i64, i64* %P, i64 3 + store volatile i64 %v, i64* %arrayidx + %arrayidx1 = getelementptr inbounds i64, i64* %P, i64 2 + store volatile i64 %v, i64* %arrayidx1 + %arrayidx2 = getelementptr inbounds i64, i64* %P, i64 1 + store volatile i64 %v, i64* %arrayidx2 + %arrayidx3 = getelementptr inbounds i64, i64* %P, i64 4 + store volatile i64 %v, i64* %arrayidx3 + ret i64 %v +} + diff --git a/test/CodeGen/AArch64/aarch64-tbz.ll b/test/CodeGen/AArch64/aarch64-tbz.ll new file mode 100644 index 000000000000..f4ebcc70674b --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-tbz.ll @@ -0,0 +1,98 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnueabi < %s | FileCheck %s + +; CHECK-LABEL: test1 +; CHECK: tbz {{w[0-9]}}, #3, {{.LBB0_3}} +; CHECK: tbz w[[REG1:[0-9]+]], #2, {{.LBB0_3}} +; CHECK-NOT: and [[REG2:x[0-9]+]], x[[REG1]], #0x4 +; CHECK-NOT: cbz [[REG2]], {{.LBB0_3}} + +; CHECK: b +define void @test1(i64 %A, i64 %B) { +entry: + %and = and i64 %A, 4 + %notlhs = icmp eq i64 %and, 0 + %and.1 = and i64 %B, 8 + %0 = icmp eq i64 %and.1, 0 + %1 = or i1 %0, %notlhs + br i1 %1, label %if.end3, label %if.then2 + +if.then2: ; preds = %entry + tail call void @foo(i64 %A, i64 %B) + br label %if.end3 + +if.end3: ; preds = %if.then2, %entry + ret void +} + +; CHECK-LABEL: test2 +; CHECK: cbz {{x[0-9]}}, {{.LBB1_3}} +; CHECK: tbz w[[REG1:[0-9]+]], #3, {{.LBB1_3}} +; CHECK-NOT: and [REG2:x[0-9]+], x[[REG1]], #0x08 +; CHECK-NOT: cbz [[REG2]], {{.LBB1_3}} + +define void @test2(i64 %A, i64* readonly %B) #0 { +entry: + %tobool = icmp eq i64* %B, null + %and = and i64 %A, 8 + %tobool1 = icmp eq i64 %and, 0 + %or.cond = or i1 %tobool, %tobool1 + br i1 %or.cond, label %if.end3, label %if.then2 + +if.then2: ; preds = %entry + %0 = load i64, i64* %B, align 4 + tail call void @foo(i64 %A, i64 %0) + br label %if.end3 + +if.end3: ; preds = %entry, %if.then2 + ret void +} + +; Make sure we use the W variant when log2(mask) is < 32. +; CHECK-LABEL: test3 +; CHECK: tbz {{w[0-9]}}, #3, {{.LBB2_3}} +; CHECK: tbz w[[REG1:[0-9]+]], #28, {{.LBB2_3}} +; CHECK-NOT: and [[REG2:x[0-9]+]], x[[REG1]] +; CHECK-NOT: cbz [[REG2]], {{.LBB2_3}} +define void @test3(i64 %A, i64 %B) { +entry: + %shift = shl i64 1, 28 + %and = and i64 %A, %shift + %notlhs = icmp eq i64 %and, 0 + %and.1 = and i64 %B, 8 + %0 = icmp eq i64 %and.1, 0 + %1 = or i1 %0, %notlhs + br i1 %1, label %if.then2, label %if.end3 + +if.then2: ; preds = %entry + tail call void @foo(i64 %A, i64 %B) + br label %if.end3 + +if.end3: ; preds = %if.then2, %entry + ret void +} + +; CHECK-LABEL: test4 +; CHECK: tbz {{w[0-9]}}, #3, {{.LBB3_3}} +; CHECK: tbz [[REG1:x[0-9]+]], #35, {{.LBB3_3}} +; CHECK-NOT: and [[REG2:x[0-9]+]], x[[REG1]] +; CHECK-NOT: cbz [[REG2]], {{.LBB2_3}} +define void @test4(i64 %A, i64 %B) { +entry: + %shift = shl i64 1, 35 + %and = and i64 %A, %shift + %notlhs = icmp eq i64 %and, 0 + %and.1 = and i64 %B, 8 + %0 = icmp eq i64 %and.1, 0 + %1 = or i1 %0, %notlhs + br i1 %1, label %if.then2, label %if.end3 + +if.then2: ; preds = %entry + tail call void @foo(i64 %A, i64 %B) + br label %if.end3 + +if.end3: ; preds = %if.then2, %entry + ret void +} + + +declare void @foo(i64, i64) diff --git a/test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll b/test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll new file mode 100644 index 000000000000..3c986ba2e513 --- /dev/null +++ b/test/CodeGen/AArch64/aarch64-tryBitfieldInsertOpFromOr-crash.ll @@ -0,0 +1,36 @@ +; RUN: llc <%s +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-gnu" + +; Function Attrs: noreturn nounwind +define void @foo(i32* %d) { +entry: + %0 = ptrtoint i32* %d to i64 + %1 = and i64 %0, -36028797018963969 + %2 = inttoptr i64 %1 to i32* + %arrayidx5 = getelementptr inbounds i32, i32* %2, i64 1 + %arrayidx6 = getelementptr inbounds i32, i32* %2, i64 2 + %arrayidx7 = getelementptr inbounds i32, i32* %2, i64 3 + br label %for.cond + +for.cond: ; preds = %for.cond, %entry + %B.0 = phi i32* [ %d, %entry ], [ %12, %for.cond ] + %3 = ptrtoint i32* %B.0 to i64 + %4 = and i64 %3, -36028797018963969 + %5 = inttoptr i64 %4 to i32* + %6 = load i32, i32* %5, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %5, i64 1 + %7 = load i32, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32* %5, i64 2 + %8 = load i32, i32* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %5, i64 3 + %9 = load i32, i32* %arrayidx3, align 4 + store i32 %6, i32* %2, align 4 + store i32 %7, i32* %arrayidx5, align 4 + store i32 %8, i32* %arrayidx6, align 4 + store i32 %9, i32* %arrayidx7, align 4 + %10 = ptrtoint i32* %arrayidx1 to i64 + %11 = or i64 %10, 36028797018963968 + %12 = inttoptr i64 %11 to i32* + br label %for.cond +} diff --git a/test/CodeGen/AArch64/addsub.ll b/test/CodeGen/AArch64/addsub.ll index d6350a6db0ee..c0235cd5d9ef 100644 --- a/test/CodeGen/AArch64/addsub.ll +++ b/test/CodeGen/AArch64/addsub.ll @@ -5,6 +5,7 @@ ; loads and stores. @var_i32 = global i32 42 +@var2_i32 = global i32 43 @var_i64 = global i64 0 ; Add pure 12-bit immediates: @@ -106,6 +107,7 @@ define void @sub_med() { define void @testing() { ; CHECK-LABEL: testing: %val = load i32, i32* @var_i32 + %val2 = load i32, i32* @var2_i32 ; CHECK: cmp {{w[0-9]+}}, #4095 ; CHECK: b.ne [[RET:.?LBB[0-9]+_[0-9]+]] @@ -117,7 +119,7 @@ test2: ; CHECK: b.lo [[RET]] %newval2 = add i32 %val, 1 store i32 %newval2, i32* @var_i32 - %cmp_pos_big = icmp ult i32 %val, 14610432 + %cmp_pos_big = icmp ult i32 %val2, 14610432 br i1 %cmp_pos_big, label %ret, label %test3 test3: @@ -133,7 +135,7 @@ test4: ; CHECK: b.gt [[RET]] %newval4 = add i32 %val, 3 store i32 %newval4, i32* @var_i32 - %cmp_pos_sgt = icmp sgt i32 %val, 321 + %cmp_pos_sgt = icmp sgt i32 %val2, 321 br i1 %cmp_pos_sgt, label %ret, label %test5 test5: @@ -141,7 +143,7 @@ test5: ; CHECK: b.gt [[RET]] %newval5 = add i32 %val, 4 store i32 %newval5, i32* @var_i32 - %cmp_neg_uge = icmp sgt i32 %val, -444 + %cmp_neg_uge = icmp sgt i32 %val2, -444 br i1 %cmp_neg_uge, label %ret, label %test6 test6: diff --git a/test/CodeGen/AArch64/alloca.ll b/test/CodeGen/AArch64/alloca.ll index 45754377b2d9..ab7a631dc248 100644 --- a/test/CodeGen/AArch64/alloca.ll +++ b/test/CodeGen/AArch64/alloca.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=aarch64-linux-gnu -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-ios -disable-post-ra -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK-MACHO ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -mattr=-fp-armv8 -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOFP-ARM64 %s declare void @use_addr(i8*) @@ -113,14 +114,21 @@ define void @test_variadic_alloca(i64 %n, ...) { define void @test_alloca_large_frame(i64 %n) { ; CHECK-LABEL: test_alloca_large_frame: +; CHECK-MACHO-LABEL: test_alloca_large_frame: -; CHECK: stp x20, x19, [sp, #-32]! +; CHECK: stp x28, x19, [sp, #-32]! ; CHECK: stp x29, x30, [sp, #16] ; CHECK: add x29, sp, #16 ; CHECK: sub sp, sp, #1953, lsl #12 ; CHECK: sub sp, sp, #512 +; CHECK-MACHO: stp x20, x19, [sp, #-32]! +; CHECK-MACHO: stp x29, x30, [sp, #16] +; CHECK-MACHO: add x29, sp, #16 +; CHECK-MACHO: sub sp, sp, #1953, lsl #12 +; CHECK-MACHO: sub sp, sp, #512 + %addr1 = alloca i8, i64 %n %addr2 = alloca i64, i64 1000000 @@ -130,7 +138,11 @@ define void @test_alloca_large_frame(i64 %n) { ; CHECK: sub sp, x29, #16 ; CHECK: ldp x29, x30, [sp, #16] -; CHECK: ldp x20, x19, [sp], #32 +; CHECK: ldp x28, x19, [sp], #32 + +; CHECK-MACHO: sub sp, x29, #16 +; CHECK-MACHO: ldp x29, x30, [sp, #16] +; CHECK-MACHO: ldp x20, x19, [sp], #32 } declare i8* @llvm.stacksave() diff --git a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll index a66ea0df2e98..caafde0a1bb2 100644 --- a/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll +++ b/test/CodeGen/AArch64/arm64-2011-03-17-AsmPrinterCrash.ll @@ -18,22 +18,21 @@ if.else295: ; preds = %entry declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone -!llvm.dbg.gv = !{!0} -!llvm.dbg.sp = !{!1, !7, !10, !11, !12} +!llvm.dbg.cu = !{!0} !0 = !DIGlobalVariable(name: "vsplive", line: 617, isLocal: true, isDefinition: true, scope: !1, file: !2, type: !6) -!1 = distinct !DISubprogram(name: "drt_vsprintf", line: 616, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) +!1 = distinct !DISubprogram(name: "drt_vsprintf", line: 616, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, file: !20, scope: !2, type: !4) !2 = !DIFile(filename: "print.i", directory: "/Volumes/Ebi/echeng/radars/r9146594") -!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)", isOptimized: true, emissionKind: 0, file: !20, enums: !21, retainedTypes: !21) +!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (http://llvm.org/git/clang.git git:/git/puzzlebox/clang.git/ c4d1aea01c4444eb81bdbf391f1be309127c3cf1)", isOptimized: true, emissionKind: FullDebug, file: !20, enums: !21, retainedTypes: !21, globals: !{!0}) !4 = !DISubroutineType(types: !5) !5 = !{!6} !6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!7 = distinct !DISubprogram(name: "putc_mem", line: 30, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8) +!7 = distinct !DISubprogram(name: "putc_mem", line: 30, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, file: !20, scope: !2, type: !8) !8 = !DISubroutineType(types: !9) !9 = !{null} -!10 = distinct !DISubprogram(name: "print_double", line: 203, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) -!11 = distinct !DISubprogram(name: "print_number", line: 75, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !4) -!12 = distinct !DISubprogram(name: "get_flags", line: 508, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, file: !20, scope: !2, type: !8) +!10 = distinct !DISubprogram(name: "print_double", line: 203, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, file: !20, scope: !2, type: !4) +!11 = distinct !DISubprogram(name: "print_number", line: 75, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, file: !20, scope: !2, type: !4) +!12 = distinct !DISubprogram(name: "get_flags", line: 508, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !3, file: !20, scope: !2, type: !8) !13 = !DILocation(line: 653, column: 5, scope: !14) !14 = distinct !DILexicalBlock(line: 652, column: 35, file: !20, scope: !15) !15 = distinct !DILexicalBlock(line: 616, column: 1, file: !20, scope: !1) diff --git a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll index 8784abdadfab..6d8c639adb95 100644 --- a/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll +++ b/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT +; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-NOOPT +; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=apple -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-OPT +; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-NOOPT +; RUN: llc < %s -verify-machineinstrs -march=arm64 -aarch64-neon-syntax=generic -aarch64-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC -check-prefix=GENERIC-OPT define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone { ; CHECK-LABEL: bar: diff --git a/test/CodeGen/AArch64/arm64-aapcs-be.ll b/test/CodeGen/AArch64/arm64-aapcs-be.ll index e77952e4b8a1..74b6ae16142e 100644 --- a/test/CodeGen/AArch64/arm64-aapcs-be.ll +++ b/test/CodeGen/AArch64/arm64-aapcs-be.ll @@ -32,7 +32,8 @@ define float @test_block_addr([8 x float], [1 x float] %in) { define void @test_block_addr_callee() { ; CHECK-LABEL: test_block_addr_callee: -; CHECK: str {{[a-z0-9]+}}, [sp, #-16]! +; CHECK: sub sp, sp, #32 +; CHECK: str {{[a-z0-9]+}}, [sp, #16] ; CHECK: bl test_block_addr %val = insertvalue [1 x float] undef, float 0.0, 0 call float @test_block_addr([8 x float] undef, [1 x float] %val) diff --git a/test/CodeGen/AArch64/arm64-abi-varargs.ll b/test/CodeGen/AArch64/arm64-abi-varargs.ll index 03414b56144c..c92703651385 100644 --- a/test/CodeGen/AArch64/arm64-abi-varargs.ll +++ b/test/CodeGen/AArch64/arm64-abi-varargs.ll @@ -125,7 +125,7 @@ entry: define void @bar(i32 %x, <4 x i32> %y) nounwind { entry: ; CHECK-LABEL: bar: -; CHECK: str {{q[0-9]+}}, [sp, #16] +; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16] ; CHECK: str {{x[0-9]+}}, [sp] %x.addr = alloca i32, align 4 %y.addr = alloca <4 x i32>, align 16 diff --git a/test/CodeGen/AArch64/arm64-abi.ll b/test/CodeGen/AArch64/arm64-abi.ll index 36a682242aaa..fb52b1d99fc9 100644 --- a/test/CodeGen/AArch64/arm64-abi.ll +++ b/test/CodeGen/AArch64/arm64-abi.ll @@ -130,7 +130,7 @@ entry: ; CHECK-LABEL: test3 ; CHECK: str [[REG_1:d[0-9]+]], [sp, #8] ; FAST-LABEL: test3 -; FAST: sub sp, sp, #32 +; FAST: sub sp, sp, #48 ; FAST: mov x[[ADDR:[0-9]+]], sp ; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8] %0 = load <2 x i32>, <2 x i32>* %in, align 8 diff --git a/test/CodeGen/AArch64/arm64-abi_align.ll b/test/CodeGen/AArch64/arm64-abi_align.ll index dc9884f12f57..e76adb4abc02 100644 --- a/test/CodeGen/AArch64/arm64-abi_align.ll +++ b/test/CodeGen/AArch64/arm64-abi_align.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s -; RUN: llc < %s -O0 | FileCheck -check-prefix=FAST %s +; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false -disable-fp-elim | FileCheck %s +; RUN: llc < %s -O0 -disable-fp-elim | FileCheck -check-prefix=FAST %s target triple = "arm64-apple-darwin" ; rdar://12648441 @@ -74,7 +74,7 @@ define i32 @caller38_stack() #1 { entry: ; CHECK-LABEL: caller38_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] %0 = load i64, i64* bitcast (%struct.s38* @g38 to i64*), align 4 %1 = load i64, i64* bitcast (%struct.s38* @g38_2 to i64*), align 4 @@ -128,7 +128,7 @@ entry: ; CHECK-LABEL: caller39_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] %0 = load i128, i128* bitcast (%struct.s39* @g39 to i128*), align 16 %1 = load i128, i128* bitcast (%struct.s39* @g39_2 to i128*), align 16 @@ -184,7 +184,7 @@ entry: ; CHECK-LABEL: caller40_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #24] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] %0 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40 to [2 x i64]*), align 4 %1 = load [2 x i64], [2 x i64]* bitcast (%struct.s40* @g40_2 to [2 x i64]*), align 4 @@ -238,7 +238,7 @@ entry: ; CHECK-LABEL: caller41_stack ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #32] ; CHECK: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #16] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] %0 = load i128, i128* bitcast (%struct.s41* @g41 to i128*), align 16 %1 = load i128, i128* bitcast (%struct.s41* @g41_2 to i128*), align 16 @@ -291,7 +291,7 @@ entry: ; Space for s2 is allocated at sp ; FAST-LABEL: caller42 -; FAST: sub sp, sp, #96 +; FAST: sub sp, sp, #112 ; Space for s1 is allocated at fp-24 = sp+72 ; Space for s2 is allocated at sp+48 ; FAST: sub x[[A:[0-9]+]], x29, #24 @@ -317,8 +317,8 @@ declare i32 @f42_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, define i32 @caller42_stack() #3 { entry: ; CHECK-LABEL: caller42_stack -; CHECK: mov x29, sp -; CHECK: sub sp, sp, #96 +; CHECK: sub sp, sp, #112 +; CHECK: add x29, sp, #96 ; CHECK: stur {{x[0-9]+}}, [x29, #-16] ; CHECK: stur {{q[0-9]+}}, [x29, #-32] ; CHECK: str {{x[0-9]+}}, [sp, #48] @@ -330,7 +330,7 @@ entry: ; CHECK: sub x[[A:[0-9]+]], x29, #32 ; Address of s1 is passed on stack at sp+8 ; CHECK: str x[[A]], [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] ; FAST-LABEL: caller42_stack @@ -399,7 +399,7 @@ entry: ; Space for s2 is allocated at sp ; FAST-LABEL: caller43 -; FAST: mov x29, sp +; FAST: add x29, sp, #64 ; Space for s1 is allocated at sp+32 ; Space for s2 is allocated at sp ; FAST: add x1, sp, #32 @@ -429,8 +429,8 @@ declare i32 @f43_stack(i32 %i, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6, define i32 @caller43_stack() #3 { entry: ; CHECK-LABEL: caller43_stack -; CHECK: mov x29, sp -; CHECK: sub sp, sp, #96 +; CHECK: sub sp, sp, #112 +; CHECK: add x29, sp, #96 ; CHECK: stur {{q[0-9]+}}, [x29, #-16] ; CHECK: stur {{q[0-9]+}}, [x29, #-32] ; CHECK: str {{q[0-9]+}}, [sp, #48] @@ -442,11 +442,11 @@ entry: ; CHECK: sub x[[A:[0-9]+]], x29, #32 ; Address of s1 is passed on stack at sp+8 ; CHECK: str x[[A]], [sp, #8] -; CHECK: movz w[[C:[0-9]+]], #0x9 +; CHECK: mov w[[C:[0-9]+]], #9 ; CHECK: str w[[C]], [sp] ; FAST-LABEL: caller43_stack -; FAST: sub sp, sp, #96 +; FAST: sub sp, sp, #112 ; Space for s1 is allocated at fp-32 = sp+64 ; Space for s2 is allocated at sp+32 ; FAST: sub x[[A:[0-9]+]], x29, #32 @@ -508,7 +508,7 @@ entry: ; "i64 %0" should be in register x7. ; "i32 8" should be on stack at [sp]. ; CHECK: ldr x7, [{{x[0-9]+}}] -; CHECK: str {{w[0-9]+}}, [sp, #-16]! +; CHECK: str {{w[0-9]+}}, [sp] ; FAST-LABEL: i64_split ; FAST: ldr x7, [{{x[0-9]+}}] ; FAST: mov x[[R0:[0-9]+]], sp diff --git a/test/CodeGen/AArch64/arm64-addrmode.ll b/test/CodeGen/AArch64/arm64-addrmode.ll index c22d0312b24d..0e651a910d7b 100644 --- a/test/CodeGen/AArch64/arm64-addrmode.ll +++ b/test/CodeGen/AArch64/arm64-addrmode.ll @@ -82,7 +82,7 @@ define void @t7(i64 %a) { define void @t8(i64 %a) { ; CHECK-LABEL: t8: -; CHECK: movn [[REG:x[0-9]+]], #0x1235 +; CHECK: mov [[REG:x[0-9]+]], #-4662 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = sub i64 %a, 4662 ;-4662 is 0xffffffffffffedca %2 = inttoptr i64 %1 to i64* @@ -92,7 +92,7 @@ define void @t8(i64 %a) { define void @t9(i64 %a) { ; CHECK-LABEL: t9: -; CHECK: movn [[REG:x[0-9]+]], #0x1235, lsl #16 +; CHECK: mov [[REG:x[0-9]+]], #-305463297 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = add i64 -305463297, %a ;-305463297 is 0xffffffffedcaffff %2 = inttoptr i64 %1 to i64* @@ -102,7 +102,7 @@ define void @t9(i64 %a) { define void @t10(i64 %a) { ; CHECK-LABEL: t10: -; CHECK: movz [[REG:x[0-9]+]], #0x123, lsl #48 +; CHECK: mov [[REG:x[0-9]+]], #81909218222800896 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]] %1 = add i64 %a, 81909218222800896 ;0x123000000000000 %2 = inttoptr i64 %1 to i64* @@ -112,8 +112,8 @@ define void @t10(i64 %a) { define void @t11(i64 %a) { ; CHECK-LABEL: t11: -; CHECK: movz w[[NUM:[0-9]+]], #0x123, lsl #16 -; CHECK: movk w[[NUM:[0-9]+]], #0x4567 +; CHECK: mov w[[NUM:[0-9]+]], #19070976 +; CHECK: movk w[[NUM:[0-9]+]], #17767 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]] %1 = add i64 %a, 19088743 ;0x1234567 %2 = inttoptr i64 %1 to i64* diff --git a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll index bf2d2cfa6066..71bf2039eaa1 100644 --- a/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll +++ b/test/CodeGen/AArch64/arm64-alloc-no-stack-realign.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=false | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-darwin -enable-misched=false -enable-post-misched=false | FileCheck %s ; rdar://12713765 ; Make sure we are not creating stack objects that are assumed to be 64-byte diff --git a/test/CodeGen/AArch64/arm64-atomic-128.ll b/test/CodeGen/AArch64/arm64-atomic-128.ll index 44c24c51f0df..d7188f31c567 100644 --- a/test/CodeGen/AArch64/arm64-atomic-128.ll +++ b/test/CodeGen/AArch64/arm64-atomic-128.ll @@ -190,7 +190,7 @@ define void @atomic_store_seq_cst(i128 %in, i128* %p) { ; CHECK-LABEL: atomic_store_seq_cst: ; CHECK-NOT: dmb ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: -; CHECK: ldaxp xzr, xzr, [x2] +; CHECK: ldaxp xzr, [[IGNORED:x[0-9]+]], [x2] ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK-NOT: dmb @@ -202,7 +202,7 @@ define void @atomic_store_release(i128 %in, i128* %p) { ; CHECK-LABEL: atomic_store_release: ; CHECK-NOT: dmb ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: -; CHECK: ldxp xzr, xzr, [x2] +; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2] ; CHECK: stlxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK-NOT: dmb @@ -214,7 +214,7 @@ define void @atomic_store_relaxed(i128 %in, i128* %p) { ; CHECK-LABEL: atomic_store_relaxed: ; CHECK-NOT: dmb ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]: -; CHECK: ldxp xzr, xzr, [x2] +; CHECK: ldxp xzr, [[IGNORED:x[0-9]+]], [x2] ; CHECK: stxp [[SUCCESS:w[0-9]+]], x0, x1, [x2] ; CHECK: cbnz [[SUCCESS]], [[LABEL]] ; CHECK-NOT: dmb diff --git a/test/CodeGen/AArch64/arm64-atomic.ll b/test/CodeGen/AArch64/arm64-atomic.ll index 5d8d60de5fc5..fef137b1023f 100644 --- a/test/CodeGen/AArch64/arm64-atomic.ll +++ b/test/CodeGen/AArch64/arm64-atomic.ll @@ -103,7 +103,7 @@ define i64 @fetch_and_nand_64(i64* %p) #0 { define i32 @fetch_and_or(i32* %p) #0 { ; CHECK-LABEL: fetch_and_or: -; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5 +; CHECK: mov [[OLDVAL_REG:w[0-9]+]], #5 ; CHECK: [[TRYBB:.?LBB[0-9_]+]]: ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0] ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]] diff --git a/test/CodeGen/AArch64/arm64-bitfield-extract.ll b/test/CodeGen/AArch64/arm64-bitfield-extract.ll index 5dca92941211..402e16ccdb21 100644 --- a/test/CodeGen/AArch64/arm64-bitfield-extract.ll +++ b/test/CodeGen/AArch64/arm64-bitfield-extract.ll @@ -41,7 +41,7 @@ define i32 @bar(i64 %cav1.coerce) nounwind { define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind optsize ssp { ; CHECK-LABEL: fct1: -; CHECK: ubfx +; CHECK: ubfx x{{[0-9]+}}, x{{[0-9]+}} ; CHECK-NOT: and ; CHECK: ret @@ -348,8 +348,8 @@ entry: ; CHECK-LABEL: fct16: ; CHECK: ldr [[REG1:w[0-9]+]], ; Create the constant -; CHECK: movz [[REGCST:w[0-9]+]], #0x1a, lsl #16 -; CHECK: movk [[REGCST]], #0x8160 +; CHECK: mov [[REGCST:w[0-9]+]], #1703936 +; CHECK: movk [[REGCST]], #33120 ; Do the masking ; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]] ; CHECK-NEXT: bfxil [[REG2]], w1, #16, #3 @@ -377,8 +377,8 @@ entry: ; CHECK-LABEL: fct17: ; CHECK: ldr [[REG1:x[0-9]+]], ; Create the constant -; CHECK: movz w[[REGCST:[0-9]+]], #0x1a, lsl #16 -; CHECK: movk w[[REGCST]], #0x8160 +; CHECK: mov w[[REGCST:[0-9]+]], #1703936 +; CHECK: movk w[[REGCST]], #33120 ; Do the masking ; CHECK: and [[REG2:x[0-9]+]], [[REG1]], x[[REGCST]] ; CHECK-NEXT: bfxil [[REG2]], x1, #16, #3 diff --git a/test/CodeGen/AArch64/arm64-build-vector.ll b/test/CodeGen/AArch64/arm64-build-vector.ll index d0f6db080551..1a6c3687dcb0 100644 --- a/test/CodeGen/AArch64/arm64-build-vector.ll +++ b/test/CodeGen/AArch64/arm64-build-vector.ll @@ -36,7 +36,7 @@ define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind { define <8 x i16> @build_all_zero(<8 x i16> %a) #1 { ; CHECK-LABEL: build_all_zero: -; CHECK: movz w[[GREG:[0-9]+]], #0xae80 +; CHECK: mov w[[GREG:[0-9]+]], #44672 ; CHECK-NEXT: fmov s[[FREG:[0-9]+]], w[[GREG]] ; CHECK-NEXT: mul.8h v0, v0, v[[FREG]] %b = add <8 x i16> %a, @@ -56,4 +56,4 @@ define <8 x i16> @concat_2_build_vector(<4 x i16> %in0) { %vshl_n2 = shl <4 x i16> %vshl_n, %shuffle.i = shufflevector <4 x i16> %vshl_n2, <4 x i16> zeroinitializer, <8 x i32> ret <8 x i16> %shuffle.i -} \ No newline at end of file +} diff --git a/test/CodeGen/AArch64/arm64-builtins-linux.ll b/test/CodeGen/AArch64/arm64-builtins-linux.ll index 34fa1b471561..6caf3a2a18ef 100644 --- a/test/CodeGen/AArch64/arm64-builtins-linux.ll +++ b/test/CodeGen/AArch64/arm64-builtins-linux.ll @@ -1,11 +1,11 @@ ; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s ; Function Attrs: nounwind readnone -declare i8* @llvm.aarch64.thread.pointer() #1 +declare i8* @llvm.thread.pointer() #1 define i8* @thread_pointer() { ; CHECK: thread_pointer: ; CHECK: mrs {{x[0-9]+}}, TPIDR_EL0 - %1 = tail call i8* @llvm.aarch64.thread.pointer() + %1 = tail call i8* @llvm.thread.pointer() ret i8* %1 } diff --git a/test/CodeGen/AArch64/arm64-ccmp.ll b/test/CodeGen/AArch64/arm64-ccmp.ll index 72d3b8331162..748bbcca079f 100644 --- a/test/CodeGen/AArch64/arm64-ccmp.ll +++ b/test/CodeGen/AArch64/arm64-ccmp.ll @@ -317,24 +317,6 @@ define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) { ret i64 %sel } -; CHECK-LABEL: select_complicated -define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) { -; CHECK: ldr [[REG:d[0-9]+]], -; CHECK: fcmp d0, d2 -; CHECK-NEXT: fmov d2, #13.00000000 -; CHECK-NEXT: fccmp d1, d2, #4, ne -; CHECK-NEXT: fccmp d0, d1, #1, ne -; CHECK-NEXT: fccmp d0, d1, #4, vc -; CEHCK-NEXT: csel w0, w0, w1, eq - %1 = fcmp one double %v1, %v2 - %2 = fcmp oeq double %v2, 13.0 - %3 = fcmp oeq double %v1, 42.0 - %or0 = or i1 %2, %3 - %or1 = or i1 %1, %or0 - %sel = select i1 %or1, i16 %a, i16 %b - ret i16 %sel -} - ; CHECK-LABEL: gccbug define i64 @gccbug(i64 %x0, i64 %x1) { ; CHECK: cmp x0, #2 @@ -443,3 +425,234 @@ define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) { store volatile i32 %ext, i32* @g ret i64 %sel } + +; The following is not possible to implement with a single cmp;ccmp;csel +; sequence. +; CHECK-LABEL: select_noccmp3 +define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) { + %c0 = icmp slt i32 %v0, 0 + %c1 = icmp sgt i32 %v0, 13 + %c2 = icmp slt i32 %v0, 22 + %c3 = icmp sgt i32 %v0, 44 + %c4 = icmp eq i32 %v0, 99 + %c5 = icmp eq i32 %v0, 77 + %or0 = or i1 %c0, %c1 + %or1 = or i1 %c2, %c3 + %and0 = and i1 %or0, %or1 + %or2 = or i1 %c4, %c5 + %and1 = and i1 %and0, %or2 + %sel = select i1 %and1, i32 %v1, i32 %v2 + ret i32 %sel +} + +; Test the IR CCs that expand to two cond codes. + +; CHECK-LABEL: select_and_olt_one: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #4, mi +; CHECK-NEXT: fccmp d2, d3, #1, ne +; CHECK-NEXT: csel w0, w0, w1, vc +; CHECK-NEXT: ret +define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp one double %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_and_one_olt: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d0, d1, #1, ne +; CHECK-NEXT: fccmp d2, d3, #0, vc +; CHECK-NEXT: csel w0, w0, w1, mi +; CHECK-NEXT: ret +define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp one double %v0, %v1 + %c1 = fcmp olt double %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_and_olt_ueq: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #0, mi +; CHECK-NEXT: fccmp d2, d3, #8, le +; CHECK-NEXT: csel w0, w0, w1, pl +; CHECK-NEXT: ret +define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp ueq double %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_and_ueq_olt: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d0, d1, #8, le +; CHECK-NEXT: fccmp d2, d3, #0, pl +; CHECK-NEXT: csel w0, w0, w1, mi +; CHECK-NEXT: ret +define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp ueq double %v0, %v1 + %c1 = fcmp olt double %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_olt_one: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #0, pl +; CHECK-NEXT: fccmp d2, d3, #8, le +; CHECK-NEXT: csel w0, w0, w1, mi +; CHECK-NEXT: ret +define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp one double %v2, %v3 + %cr = or i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_one_olt: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d0, d1, #1, ne +; CHECK-NEXT: fccmp d2, d3, #8, vs +; CHECK-NEXT: csel w0, w0, w1, mi +; CHECK-NEXT: ret +define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp one double %v0, %v1 + %c1 = fcmp olt double %v2, %v3 + %cr = or i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_olt_ueq: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #4, pl +; CHECK-NEXT: fccmp d2, d3, #1, ne +; CHECK-NEXT: csel w0, w0, w1, vs +; CHECK-NEXT: ret +define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp ueq double %v2, %v3 + %cr = or i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_ueq_olt: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d0, d1, #8, le +; CHECK-NEXT: fccmp d2, d3, #8, mi +; CHECK-NEXT: csel w0, w0, w1, mi +; CHECK-NEXT: ret +define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp ueq double %v0, %v1 + %c1 = fcmp olt double %v2, %v3 + %cr = or i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_olt_ogt_ueq: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #0, pl +; CHECK-NEXT: fccmp d4, d5, #4, le +; CHECK-NEXT: fccmp d4, d5, #1, ne +; CHECK-NEXT: csel w0, w0, w1, vs +; CHECK-NEXT: ret +define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp ogt double %v2, %v3 + %c2 = fcmp ueq double %v4, %v5 + %c3 = or i1 %c1, %c0 + %cr = or i1 %c2, %c3 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: select_or_olt_ueq_ogt: +; CHECK-LABEL: ; BB#0: +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: fccmp d2, d3, #4, pl +; CHECK-NEXT: fccmp d2, d3, #1, ne +; CHECK-NEXT: fccmp d4, d5, #0, vc +; CHECK-NEXT: csel w0, w0, w1, gt +; CHECK-NEXT: ret +define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 { + %c0 = fcmp olt double %v0, %v1 + %c1 = fcmp ueq double %v2, %v3 + %c2 = fcmp ogt double %v4, %v5 + %c3 = or i1 %c1, %c0 + %cr = or i1 %c2, %c3 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; Verify that we correctly promote f16. + +; CHECK-LABEL: half_select_and_olt_oge: +; CHECK-LABEL: ; BB#0: +; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0 +; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1 +; CHECK-NEXT: fcmp [[S0]], [[S1]] +; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2 +; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3 +; CHECK-NEXT: fccmp [[S2]], [[S3]], #8, mi +; CHECK-NEXT: csel w0, w0, w1, ge +; CHECK-NEXT: ret +define i32 @half_select_and_olt_oge(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt half %v0, %v1 + %c1 = fcmp oge half %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; CHECK-LABEL: half_select_and_olt_one: +; CHECK-LABEL: ; BB#0: +; CHECK-DAG: fcvt [[S0:s[0-9]+]], h0 +; CHECK-DAG: fcvt [[S1:s[0-9]+]], h1 +; CHECK-NEXT: fcmp [[S0]], [[S1]] +; CHECK-DAG: fcvt [[S2:s[0-9]+]], h2 +; CHECK-DAG: fcvt [[S3:s[0-9]+]], h3 +; CHECK-NEXT: fccmp [[S2]], [[S3]], #4, mi +; CHECK-NEXT: fccmp [[S2]], [[S3]], #1, ne +; CHECK-NEXT: csel w0, w0, w1, vc +; CHECK-NEXT: ret +define i32 @half_select_and_olt_one(half %v0, half %v1, half %v2, half %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt half %v0, %v1 + %c1 = fcmp one half %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +; Also verify that we don't try to generate f128 FCCMPs, using RT calls instead. + +; CHECK-LABEL: f128_select_and_olt_oge: +; CHECK: bl ___lttf2 +; CHECK: bl ___getf2 +define i32 @f128_select_and_olt_oge(fp128 %v0, fp128 %v1, fp128 %v2, fp128 %v3, i32 %a, i32 %b) #0 { + %c0 = fcmp olt fp128 %v0, %v1 + %c1 = fcmp oge fp128 %v2, %v3 + %cr = and i1 %c1, %c0 + %sel = select i1 %cr, i32 %a, i32 %b + ret i32 %sel +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/arm64-collect-loh.ll b/test/CodeGen/AArch64/arm64-collect-loh.ll index 59147d401a30..3fc0d45f065c 100644 --- a/test/CodeGen/AArch64/arm64-collect-loh.ll +++ b/test/CodeGen/AArch64/arm64-collect-loh.ll @@ -613,6 +613,7 @@ define <1 x i8> @getL() { ; CHECK-NEXT: adrp [[ADRP_REG:x[0-9]+]], _L@GOTPAGE ; CHECK-NEXT: [[LDRGOT_LABEL:Lloh[0-9]+]]: ; CHECK-NEXT: ldr [[LDRGOT_REG:x[0-9]+]], {{\[}}[[ADRP_REG]], _L@GOTPAGEOFF] +; CHECK-NEXT: ; kill ; Ultimately we should generate str b0, but right now, we match the vector ; variant which does not allow to fold the immediate into the store. ; CHECK-NEXT: st1.b { v0 }[0], {{\[}}[[LDRGOT_REG]]] @@ -654,4 +655,25 @@ define void @uninterestingSub(i8* nocapture %row) #0 { ret void } +@.str.89 = external unnamed_addr constant [12 x i8], align 1 +@.str.90 = external unnamed_addr constant [5 x i8], align 1 +; CHECK-LABEL: test_r274582 +define void @test_r274582() { +entry: + br i1 undef, label %if.then.i, label %if.end.i +if.then.i: + ret void +if.end.i: +; CHECK: .loh AdrpAdrp Lloh91, Lloh93 +; CHECK: .loh AdrpLdr Lloh91, Lloh92 +; CHECK: .loh AdrpLdrGot Lloh93, Lloh95 +; CHECK: .loh AdrpLdrGot Lloh94, Lloh96 + %mul.i.i.i = fmul double undef, 1.000000e-06 + %add.i.i.i = fadd double undef, %mul.i.i.i + %sub.i.i = fsub double %add.i.i.i, undef + call void (i8*, ...) @callee(i8* getelementptr inbounds ([12 x i8], [12 x i8]* @.str.89, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8], [5 x i8]* @.str.90, i64 0, i64 0), double %sub.i.i) + unreachable +} +declare void @callee(i8* nocapture readonly, ...) + attributes #0 = { "target-cpu"="cyclone" } diff --git a/test/CodeGen/AArch64/arm64-const-addr.ll b/test/CodeGen/AArch64/arm64-const-addr.ll index ffc153344d3a..e55db2904489 100644 --- a/test/CodeGen/AArch64/arm64-const-addr.ll +++ b/test/CodeGen/AArch64/arm64-const-addr.ll @@ -5,8 +5,8 @@ ; Test if the constant base address gets only materialized once. define i32 @test1() nounwind { ; CHECK-LABEL: test1 -; CHECK: movz w8, #0x40f, lsl #16 -; CHECK-NEXT: movk w8, #0xc000 +; CHECK: mov w8, #68091904 +; CHECK-NEXT: movk w8, #49152 ; CHECK-NEXT: ldp w9, w10, [x8, #4] ; CHECK: ldr w8, [x8, #12] %at = inttoptr i64 68141056 to %T* diff --git a/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/test/CodeGen/AArch64/arm64-convert-v4f64.ll index b8da39910312..ed061122f311 100644 --- a/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -23,8 +23,8 @@ define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d ; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d ; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d -; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA0]].4s -; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA2]].4s +; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA2]].4s +; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA0]].4s ; CHECK: xtn v0.8b, v[[TMP1]].8h %tmp1 = load <8 x double>, <8 x double>* %ptr %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> diff --git a/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/test/CodeGen/AArch64/arm64-csldst-mmo.ll new file mode 100644 index 000000000000..0b8f7a19b484 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -0,0 +1,25 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; REQUIRES: asserts + +@G = external global [0 x i32], align 4 + +; Check that MMOs are added to epilogue calle-save restore loads so +; that the store to G is not considered dependant on the callee-save +; loads. +; +; CHECK: Before post-MI-sched: +; CHECK-LABEL: # Machine code for function test1: +; CHECK: SU(2): STRWui %WZR +; CHECK: SU(3): %X21, %X20 = LDPXi %SP +; CHECK: Predecessors: +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: out SU(0) +; CHECK-NEXT: ch SU(0) +; CHECK-NEXT: Successors: +define void @test1() { +entry: + tail call void asm sideeffect "nop", "~{x20},~{x21},~{x22},~{x23}"() nounwind + store i32 0, i32* getelementptr inbounds ([0 x i32], [0 x i32]* @G, i64 0, i64 0), align 4 + ret void +} diff --git a/test/CodeGen/AArch64/arm64-detect-vec-redux.ll b/test/CodeGen/AArch64/arm64-detect-vec-redux.ll new file mode 100644 index 000000000000..68130f1c9f88 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-detect-vec-redux.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=arm64-darwin-unknown < %s + +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64" + +; Function Attrs: nounwind readnone +define i32 @dotests_56() #0 { +entry: + %vqshrn_n4 = tail call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> zeroinitializer, i32 19) + %shuffle.i109 = shufflevector <2 x i32> %vqshrn_n4, <2 x i32> undef, <4 x i32> + %neg = xor <4 x i32> %shuffle.i109, + %shuffle = shufflevector <4 x i32> %neg, <4 x i32> undef, <2 x i32> + %mul = mul <2 x i32> %shuffle, bitcast (<1 x i64> to <2 x i32>), i32 0), i32 sub (i32 0, i32 extractelement (<2 x i32> bitcast (<1 x i64> to <2 x i32>), i32 0))), i32 undef> + %shuffle27 = shufflevector <2 x i32> %mul, <2 x i32> undef, <4 x i32> zeroinitializer + %0 = bitcast <4 x i32> %shuffle27 to <8 x i16> + %shuffle.i108 = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> + %vqshrn_n38 = tail call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %shuffle.i108, i32 1) + %shuffle.i = shufflevector <8 x i8> %vqshrn_n38, <8 x i8> undef, <16 x i32> + %1 = bitcast <16 x i8> %shuffle.i to <2 x i64> + %vpaddq_v2.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> undef, <2 x i64> %1) #2 + %vqdmlal2.i = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> undef, <2 x i32> undef) #2 + %vqdmlal_v3.i = tail call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %vpaddq_v2.i, <2 x i64> %vqdmlal2.i) #2 + %vmovn.i = trunc <2 x i64> %vqdmlal_v3.i to <2 x i32> + %vqdmulh_v2.i = tail call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %vmovn.i, <2 x i32> zeroinitializer) #2 + %2 = bitcast <2 x i32> %vqdmulh_v2.i to <1 x i64> + %vget_lane = extractelement <1 x i64> %2, i32 0 + %cmp = icmp ne i64 %vget_lane, -7395147708962464393 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Function Attrs: nounwind readnone +declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) #1 + +; Function Attrs: nounwind readnone +declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32) #1 + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) #1 + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) #1 + +; Function Attrs: nounwind readnone +declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) #1 + +; Function Attrs: nounwind readnone +declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>) #1 + +attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AArch64/arm64-extern-weak.ll b/test/CodeGen/AArch64/arm64-extern-weak.ll index 020c07c739d9..f00efbcea780 100644 --- a/test/CodeGen/AArch64/arm64-extern-weak.ll +++ b/test/CodeGen/AArch64/arm64-extern-weak.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=pic -o - < %s | FileCheck %s -; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK-STATIC %s +; RUN: llc -mtriple=arm64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=arm64-none-linux-gnu -code-model=large -o - < %s | FileCheck --check-prefix=CHECK-LARGE %s declare extern_weak i32 @var() @@ -13,11 +13,6 @@ define i32()* @foo() { ; CHECK: adrp x[[VAR:[0-9]+]], :got:var ; CHECK: ldr x0, [x[[VAR]], :got_lo12:var] -; CHECK-STATIC: .LCPI0_0: -; CHECK-STATIC-NEXT: .xword var -; CHECK-STATIC: adrp x[[VAR:[0-9]+]], .LCPI0_0 -; CHECK-STATIC: ldr x0, [x[[VAR]], :lo12:.LCPI0_0] - ; In the large model, the usual relocations are absolute and can ; materialise 0. ; CHECK-LARGE: movz x0, #:abs_g3:var @@ -36,11 +31,6 @@ define i32* @bar() { ; CHECK: add x0, [[ARR_VAR]], #20 ret i32* %addr -; CHECK-STATIC: .LCPI1_0: -; CHECK-STATIC-NEXT: .xword arr_var -; CHECK-STATIC: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, :lo12:.LCPI1_0] -; CHECK-STATIC: add x0, [[BASE]], #20 - ; In the large model, the usual relocations are absolute and can ; materialise 0. ; CHECK-LARGE: movz [[ARR_VAR:x[0-9]+]], #:abs_g3:arr_var @@ -56,9 +46,6 @@ define i32* @wibble() { ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var -; CHECK-STATIC: adrp [[BASE:x[0-9]+]], defined_weak_var -; CHECK-STATIC: add x0, [[BASE]], :lo12:defined_weak_var - ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var diff --git a/test/CodeGen/AArch64/arm64-extract.ll b/test/CodeGen/AArch64/arm64-extract.ll index 01984662d23a..6e07c4ce4ccb 100644 --- a/test/CodeGen/AArch64/arm64-extract.ll +++ b/test/CodeGen/AArch64/arm64-extract.ll @@ -1,4 +1,4 @@ -; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \ +; RUN: llc -verify-machineinstrs < %s \ ; RUN: -march=arm64 | FileCheck %s define i64 @ror_i64(i64 %in) { diff --git a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll index e4dc948c4603..9dae7a6f5b69 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-addr-offset.ll @@ -6,10 +6,10 @@ ; Load an address with an offset larget then LDR imm can handle define i32 @foo() nounwind { entry: -; CHECK: @foo +; CHECK-LABEL: @foo ; CHECK: adrp x[[REG:[0-9]+]], _sortlist@GOTPAGE ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist@GOTPAGEOFF] -; CHECK: movz x[[REG2:[0-9]+]], #0x4e20 +; CHECK: mov x[[REG2:[0-9]+]], #20000 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr w0, [x[[REG3]]] ; CHECK: ret @@ -19,10 +19,10 @@ entry: define i64 @foo2() nounwind { entry: -; CHECK: @foo2 +; CHECK-LABEL: @foo2 ; CHECK: adrp x[[REG:[0-9]+]], _sortlist2@GOTPAGE ; CHECK: ldr x[[REG1:[0-9]+]], [x[[REG]], _sortlist2@GOTPAGEOFF] -; CHECK: movz x[[REG2:[0-9]+]], #0x9c40 +; CHECK: mov x[[REG2:[0-9]+]], #40000 ; CHECK: add x[[REG3:[0-9]+]], x[[REG1]], x[[REG2]] ; CHECK: ldr x0, [x[[REG3]]] ; CHECK: ret @@ -36,10 +36,10 @@ entry: define signext i8 @foo3() nounwind ssp { entry: -; CHECK: @foo3 -; CHECK: movz x[[REG:[0-9]+]], #0xb3a, lsl #32 -; CHECK: movk x[[REG]], #0x73ce, lsl #16 -; CHECK: movk x[[REG]], #0x2ff2 +; CHECK-LABEL: @foo3 +; CHECK: mov x[[REG:[0-9]+]], #12343736008704 +; CHECK: movk x[[REG]], #29646, lsl #16 +; CHECK: movk x[[REG]], #12274 %0 = load i8*, i8** @pd2, align 8 %arrayidx = getelementptr inbounds i8, i8* %0, i64 12345678901234 %1 = load i8, i8* %arrayidx, align 1 diff --git a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll index a506607a0a5d..bdc24aea2144 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-alloca.ll @@ -1,5 +1,5 @@ ; This test should cause the TargetMaterializeAlloca to be invoked -; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -disable-fp-elim < %s | FileCheck %s %struct.S1Ty = type { i64 } %struct.S2Ty = type { %struct.S1Ty, %struct.S1Ty } @@ -14,7 +14,7 @@ entry: define void @main() nounwind { entry: ; CHECK: main -; CHECK: mov x29, sp +; CHECK: add x29, sp, #16 ; CHECK: mov [[REG:x[0-9]+]], sp ; CHECK-NEXT: add x0, [[REG]], #8 %E = alloca %struct.S2Ty, align 4 diff --git a/test/CodeGen/AArch64/arm64-fast-isel-call.ll b/test/CodeGen/AArch64/arm64-fast-isel-call.ll index d6957f9191e2..59c4e38e5467 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-call.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-call.ll @@ -1,6 +1,6 @@ -; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s -; RUN: llc -O0 -fast-isel-abort=2 -code-model=large -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE -; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE +; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -disable-fp-elim -mtriple=arm64-apple-darwin < %s | FileCheck %s +; RUN: llc -O0 -fast-isel-abort=2 -code-model=large -verify-machineinstrs -disable-fp-elim -mtriple=arm64-apple-darwin < %s | FileCheck %s --check-prefix=LARGE +; RUN: llc -O0 -fast-isel-abort=2 -code-model=small -verify-machineinstrs -disable-fp-elim -mtriple=aarch64_be-linux-gnu < %s | FileCheck %s --check-prefix=CHECK-BE define void @call0() nounwind { entry: diff --git a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll index ab29824ccb60..85d000b8606b 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-gv.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-gv.ll @@ -18,8 +18,8 @@ entry: ; CHECK: @Rand ; CHECK: adrp [[REG1:x[0-9]+]], _seed@GOTPAGE ; CHECK: ldr [[REG2:x[0-9]+]], {{\[}}[[REG1]], _seed@GOTPAGEOFF{{\]}} -; CHECK: movz [[REG3:x[0-9]+]], #0x3619 -; CHECK: movz [[REG4:x[0-9]+]], #0x51d +; CHECK: mov [[REG3:x[0-9]+]], #13849 +; CHECK: mov [[REG4:x[0-9]+]], #1309 ; CHECK: ldr [[REG5:x[0-9]+]], {{\[}}[[REG2]]{{\]}} ; CHECK: mul [[REG6:x[0-9]+]], [[REG5]], [[REG4]] ; CHECK: add [[REG7:x[0-9]+]], [[REG6]], [[REG3]] diff --git a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll index bb2889eaf4be..a8f30ad4777d 100644 --- a/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll +++ b/test/CodeGen/AArch64/arm64-fast-isel-intrinsic.ll @@ -8,7 +8,7 @@ define void @t1() { ; ARM64: adrp x8, _message@PAGE ; ARM64: add x0, x8, _message@PAGEOFF ; ARM64: mov w9, wzr -; ARM64: movz x2, #0x50 +; ARM64: mov x2, #80 ; ARM64: uxtb w1, w9 ; ARM64: bl _memset call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i8 0, i64 80, i32 16, i1 false) @@ -23,7 +23,7 @@ define void @t2() { ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x8, _message@PAGE ; ARM64: add x1, x8, _message@PAGEOFF -; ARM64: movz x2, #0x50 +; ARM64: mov x2, #80 ; ARM64: bl _memcpy call void @llvm.memcpy.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 80, i32 16, i1 false) ret void @@ -37,7 +37,7 @@ define void @t3() { ; ARM64: ldr x0, [x8, _temp@GOTPAGEOFF] ; ARM64: adrp x8, _message@PAGE ; ARM64: add x1, x8, _message@PAGEOFF -; ARM64: movz x2, #0x14 +; ARM64: mov x2, #20 ; ARM64: bl _memmove call void @llvm.memmove.p0i8.p0i8.i64(i8* getelementptr inbounds ([80 x i8], [80 x i8]* @temp, i32 0, i32 0), i8* getelementptr inbounds ([80 x i8], [80 x i8]* @message, i32 0, i32 0), i64 20, i32 16, i1 false) ret void @@ -137,7 +137,7 @@ define void @t8() { define void @test_distant_memcpy(i8* %dst) { ; ARM64-LABEL: test_distant_memcpy: ; ARM64: mov [[ARRAY:x[0-9]+]], sp -; ARM64: movz [[OFFSET:x[0-9]+]], #0x1f40 +; ARM64: mov [[OFFSET:x[0-9]+]], #8000 ; ARM64: add x[[ADDR:[0-9]+]], [[ARRAY]], [[OFFSET]] ; ARM64: ldrb [[BYTE:w[0-9]+]], [x[[ADDR]]] ; ARM64: strb [[BYTE]], [x0] diff --git a/test/CodeGen/AArch64/arm64-fcopysign.ll b/test/CodeGen/AArch64/arm64-fcopysign.ll index feffd41f002a..9bcc8eeca219 100644 --- a/test/CodeGen/AArch64/arm64-fcopysign.ll +++ b/test/CodeGen/AArch64/arm64-fcopysign.ll @@ -5,7 +5,7 @@ define float @test1(float %x, float %y) nounwind { entry: ; CHECK-LABEL: test1: -; CHECK: movi.4s v2, #0x80, lsl #24 +; CHECK: movi.4s v2, #128, lsl #24 ; CHECK: bit.16b v0, v1, v2 %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 @@ -37,7 +37,7 @@ define float @test4() nounwind { entry: ; CHECK-LABEL: test4: ; CHECK: fcvt s0, d0 -; CHECK: movi.4s v[[CONST:[0-9]+]], #0x80, lsl #24 +; CHECK: movi.4s v[[CONST:[0-9]+]], #128, lsl #24 ; CHECK: bit.16b v{{[0-9]+}}, v0, v[[CONST]] %0 = tail call double (...) @bar() nounwind %1 = fptrunc double %0 to float diff --git a/test/CodeGen/AArch64/arm64-fma-combines.ll b/test/CodeGen/AArch64/arm64-fma-combines.ll new file mode 100644 index 000000000000..ab875c06cc62 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-fma-combines.ll @@ -0,0 +1,136 @@ +; RUN: llc < %s -O=3 -mtriple=arm64-apple-ios -mcpu=cyclone -enable-unsafe-fp-math | FileCheck %s +define void @foo_2d(double* %src) { +; CHECK-LABEL: %entry +; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +; CHECK: fmul {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} +entry: + %arrayidx1 = getelementptr inbounds double, double* %src, i64 5 + %arrayidx2 = getelementptr inbounds double, double* %src, i64 11 + %tmp = bitcast double* %arrayidx1 to <2 x double>* + %tmp1 = load double, double* %arrayidx2, align 8 + %tmp2 = load double, double* %arrayidx1, align 8 + %fmul = fmul fast double %tmp1, %tmp1 + %fmul2 = fmul fast double %tmp2, 0x3F94AFD6A052BF5B + %fadd = fadd fast double %fmul, %fmul2 + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmla.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmla.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +; CHECK: fmla.d {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds double, double* %src, i64 %indvars.iv.next + %tmp3 = load double, double* %arrayidx3, align 8 + %add = fadd fast double %tmp3, %tmp3 + %mul = fmul fast double %add, %fadd + %e1 = insertelement <2 x double> undef, double %add, i32 0 + %e2 = insertelement <2 x double> %e1, double %add, i32 1 + %add2 = fadd fast <2 x double> %e2, + %e3 = insertelement <2 x double> undef, double %mul, i32 0 + %e4 = insertelement <2 x double> %e3, double %mul, i32 1 + %mul2 = fmul fast <2 x double> %add2, + %e5 = insertelement <2 x double> undef, double %add, i32 0 + %e6 = insertelement <2 x double> %e5, double %add, i32 1 + %add3 = fadd fast <2 x double> %mul2, + %mulx = fmul fast <2 x double> %add2, %e2 + %addx = fadd fast <2 x double> %mulx, %e4 + %e7 = insertelement <2 x double> undef, double %mul, i32 0 + %e8 = insertelement <2 x double> %e7, double %mul, i32 1 + %e9 = fmul fast <2 x double> %addx, %add3 + store <2 x double> %e9, <2 x double>* %tmp, align 8 + %e10 = extractelement <2 x double> %add3, i32 0 + %mul3 = fmul fast double %mul, %e10 + %add4 = fadd fast double %mul3, %mul + store double %add4, double* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} +define void @foo_2s(float* %src) { +entry: + %arrayidx1 = getelementptr inbounds float, float* %src, i64 5 + %arrayidx2 = getelementptr inbounds float, float* %src, i64 11 + %tmp = bitcast float* %arrayidx1 to <2 x float>* + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmla.2s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmla.2s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +; CHECK: fmla.s {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds float, float* %src, i64 %indvars.iv.next + %tmp1 = load float, float* %arrayidx3, align 8 + %add = fadd fast float %tmp1, %tmp1 + %mul = fmul fast float %add, %add + %e1 = insertelement <2 x float> undef, float %add, i32 0 + %e2 = insertelement <2 x float> %e1, float %add, i32 1 + %add2 = fadd fast <2 x float> %e2, + %e3 = insertelement <2 x float> undef, float %mul, i32 0 + %e4 = insertelement <2 x float> %e3, float %mul, i32 1 + %mul2 = fmul fast <2 x float> %add2, + %e5 = insertelement <2 x float> undef, float %add, i32 0 + %e6 = insertelement <2 x float> %e5, float %add, i32 1 + %add3 = fadd fast <2 x float> %mul2, + %mulx = fmul fast <2 x float> %add2, %e2 + %addx = fadd fast <2 x float> %mulx, %e4 + %e7 = insertelement <2 x float> undef, float %mul, i32 0 + %e8 = insertelement <2 x float> %e7, float %mul, i32 1 + %e9 = fmul fast <2 x float> %addx, %add3 + store <2 x float> %e9, <2 x float>* %tmp, align 8 + %e10 = extractelement <2 x float> %add3, i32 0 + %mul3 = fmul fast float %mul, %e10 + %add4 = fadd fast float %mul3, %mul + store float %add4, float* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} +define void @foo_4s(float* %src) { +entry: + %arrayidx1 = getelementptr inbounds float, float* %src, i64 5 + %arrayidx2 = getelementptr inbounds float, float* %src, i64 11 + %tmp = bitcast float* %arrayidx1 to <4 x float>* + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmla.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmla.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds float, float* %src, i64 %indvars.iv.next + %tmp1 = load float, float* %arrayidx3, align 8 + %add = fadd fast float %tmp1, %tmp1 + %mul = fmul fast float %add, %add + %e1 = insertelement <4 x float> undef, float %add, i32 0 + %e2 = insertelement <4 x float> %e1, float %add, i32 1 + %add2 = fadd fast <4 x float> %e2, + %e3 = insertelement <4 x float> undef, float %mul, i32 0 + %e4 = insertelement <4 x float> %e3, float %mul, i32 1 + %mul2 = fmul fast <4 x float> %add2, + %e5 = insertelement <4 x float> undef, float %add, i32 0 + %e6 = insertelement <4 x float> %e5, float %add, i32 1 + %add3 = fadd fast <4 x float> %mul2, + %mulx = fmul fast <4 x float> %add2, %e2 + %addx = fadd fast <4 x float> %mulx, %e4 + %e7 = insertelement <4 x float> undef, float %mul, i32 0 + %e8 = insertelement <4 x float> %e7, float %mul, i32 1 + %e9 = fmul fast <4 x float> %addx, %add3 + store <4 x float> %e9, <4 x float>* %tmp, align 8 + %e10 = extractelement <4 x float> %add3, i32 0 + %mul3 = fmul fast float %mul, %e10 + store float %mul3, float* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/CodeGen/AArch64/arm64-fml-combines.ll b/test/CodeGen/AArch64/arm64-fml-combines.ll new file mode 100644 index 000000000000..840d1dcbf060 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-fml-combines.ll @@ -0,0 +1,128 @@ +; RUN: llc < %s -O=3 -mtriple=arm64-apple-ios -mcpu=cyclone -enable-unsafe-fp-math | FileCheck %s +define void @foo_2d(double* %src) { +entry: + %arrayidx1 = getelementptr inbounds double, double* %src, i64 5 + %arrayidx2 = getelementptr inbounds double, double* %src, i64 11 + %tmp = bitcast double* %arrayidx1 to <2 x double>* + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmls.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmls.2d {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +; CHECK: fmls.d {{d[0-9]+}}, {{d[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = sub nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds double, double* %src, i64 %indvars.iv.next + %tmp1 = load double, double* %arrayidx3, align 8 + %add = fadd fast double %tmp1, %tmp1 + %mul = fmul fast double %add, %add + %e1 = insertelement <2 x double> undef, double %add, i32 0 + %e2 = insertelement <2 x double> %e1, double %add, i32 1 + %sub2 = fsub fast <2 x double> %e2, + %e3 = insertelement <2 x double> undef, double %mul, i32 0 + %e4 = insertelement <2 x double> %e3, double %mul, i32 1 + %mul2 = fmul fast <2 x double> %sub2, + %e5 = insertelement <2 x double> undef, double %add, i32 0 + %e6 = insertelement <2 x double> %e5, double %add, i32 1 + %sub3 = fsub fast <2 x double> , %mul2 + %mulx = fmul fast <2 x double> %sub2, %e2 + %subx = fsub fast <2 x double> %e4, %mulx + %e7 = insertelement <2 x double> undef, double %mul, i32 0 + %e8 = insertelement <2 x double> %e7, double %mul, i32 1 + %e9 = fmul fast <2 x double> %subx, %sub3 + store <2 x double> %e9, <2 x double>* %tmp, align 8 + %e10 = extractelement <2 x double> %sub3, i32 0 + %mul3 = fmul fast double %mul, %e10 + %sub4 = fsub fast double %mul, %mul3 + store double %sub4, double* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} +define void @foo_2s(float* %src) { +entry: + %arrayidx1 = getelementptr inbounds float, float* %src, i64 5 + %arrayidx2 = getelementptr inbounds float, float* %src, i64 11 + %tmp = bitcast float* %arrayidx1 to <2 x float>* + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmls.2s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmls.2s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +; CHECK: fmls.s {{s[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds float, float* %src, i64 %indvars.iv.next + %tmp1 = load float, float* %arrayidx3, align 8 + %add = fadd fast float %tmp1, %tmp1 + %mul = fmul fast float %add, %add + %e1 = insertelement <2 x float> undef, float %add, i32 0 + %e2 = insertelement <2 x float> %e1, float %add, i32 1 + %add2 = fsub fast <2 x float> %e2, + %e3 = insertelement <2 x float> undef, float %mul, i32 0 + %e4 = insertelement <2 x float> %e3, float %mul, i32 1 + %mul2 = fmul fast <2 x float> %add2, + %e5 = insertelement <2 x float> undef, float %add, i32 0 + %e6 = insertelement <2 x float> %e5, float %add, i32 1 + %add3 = fsub fast <2 x float> , %mul2 + %mulx = fmul fast <2 x float> %add2, %e2 + %addx = fsub fast <2 x float> %e4, %mulx + %e7 = insertelement <2 x float> undef, float %mul, i32 0 + %e8 = insertelement <2 x float> %e7, float %mul, i32 1 + %e9 = fmul fast <2 x float> %addx, %add3 + store <2 x float> %e9, <2 x float>* %tmp, align 8 + %e10 = extractelement <2 x float> %add3, i32 0 + %mul3 = fmul fast float %mul, %e10 + %add4 = fsub fast float %mul, %mul3 + store float %add4, float* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} +define void @foo_4s(float* %src) { +entry: + %arrayidx1 = getelementptr inbounds float, float* %src, i64 5 + %arrayidx2 = getelementptr inbounds float, float* %src, i64 11 + %tmp = bitcast float* %arrayidx1 to <4 x float>* + br label %for.body + +; CHECK-LABEL: %for.body +; CHECK: fmls.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; CHECK: fmls.4s {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}[0] +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %arrayidx3 = getelementptr inbounds float, float* %src, i64 %indvars.iv.next + %tmp1 = load float, float* %arrayidx3, align 8 + %add = fadd fast float %tmp1, %tmp1 + %mul = fmul fast float %add, %add + %e1 = insertelement <4 x float> undef, float %add, i32 0 + %e2 = insertelement <4 x float> %e1, float %add, i32 1 + %add2 = fadd fast <4 x float> %e2, + %e3 = insertelement <4 x float> undef, float %mul, i32 0 + %e4 = insertelement <4 x float> %e3, float %mul, i32 1 + %mul2 = fmul fast <4 x float> %add2, + %e5 = insertelement <4 x float> undef, float %add, i32 0 + %e6 = insertelement <4 x float> %e5, float %add, i32 1 + %add3 = fsub fast <4 x float> , %mul2 + %mulx = fmul fast <4 x float> %add2, %e2 + %addx = fsub fast <4 x float> %e4, %mulx + %e7 = insertelement <4 x float> undef, float %mul, i32 0 + %e8 = insertelement <4 x float> %e7, float %mul, i32 1 + %e9 = fmul fast <4 x float> %addx, %add3 + store <4 x float> %e9, <4 x float>* %tmp, align 8 + %e10 = extractelement <4 x float> %add3, i32 0 + %mul3 = fmul fast float %mul, %e10 + store float %mul3, float* %arrayidx2, align 8 + %exitcond = icmp eq i64 %indvars.iv.next, 25 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} diff --git a/test/CodeGen/AArch64/arm64-fp128.ll b/test/CodeGen/AArch64/arm64-fp128.ll index 097fe2ca6ed9..bcb196e40456 100644 --- a/test/CodeGen/AArch64/arm64-fp128.ll +++ b/test/CodeGen/AArch64/arm64-fp128.ll @@ -174,11 +174,11 @@ define i32 @test_br_cc() { iftrue: ret i32 42 ; CHECK-NEXT: BB# -; CHECK-NEXT: movz w0, #0x2a +; CHECK-NEXT: mov w0, #42 ; CHECK: ret iffalse: ret i32 29 -; CHECK: movz w0, #0x1d +; CHECK: mov w0, #29 ; CHECK: ret } diff --git a/test/CodeGen/AArch64/arm64-hello.ll b/test/CodeGen/AArch64/arm64-hello.ll index 895bfe4b3915..caaf8615cd4a 100644 --- a/test/CodeGen/AArch64/arm64-hello.ll +++ b/test/CodeGen/AArch64/arm64-hello.ll @@ -1,28 +1,25 @@ -; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -disable-post-ra -disable-fp-elim | FileCheck %s ; RUN: llc < %s -mtriple=arm64-linux-gnu -disable-post-ra | FileCheck %s --check-prefix=CHECK-LINUX ; CHECK-LABEL: main: -; CHECK: stp x29, x30, [sp, #-16]! -; CHECK-NEXT: mov x29, sp -; CHECK-NEXT: sub sp, sp, #16 +; CHECK: sub sp, sp, #32 +; CHECK-NEXT: stp x29, x30, [sp, #16] +; CHECK-NEXT: add x29, sp, #16 ; CHECK-NEXT: stur wzr, [x29, #-4] ; CHECK: adrp x0, L_.str@PAGE ; CHECK: add x0, x0, L_.str@PAGEOFF ; CHECK-NEXT: bl _puts -; CHECK-NEXT: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ldp x29, x30, [sp, #16] +; CHECK-NEXT: add sp, sp, #32 ; CHECK-NEXT: ret ; CHECK-LINUX-LABEL: main: -; CHECK-LINUX: stp x29, x30, [sp, #-16]! -; CHECK-LINUX-NEXT: mov x29, sp -; CHECK-LINUX-NEXT: sub sp, sp, #16 -; CHECK-LINUX-NEXT: stur wzr, [x29, #-4] +; CHECK-LINUX: str x30, [sp, #-16]! +; CHECK-LINUX-NEXT: str wzr, [sp, #12] ; CHECK-LINUX: adrp x0, .L.str ; CHECK-LINUX: add x0, x0, :lo12:.L.str ; CHECK-LINUX-NEXT: bl puts -; CHECK-LINUX-NEXT: mov sp, x29 -; CHECK-LINUX-NEXT: ldp x29, x30, [sp], #16 +; CHECK-LINUX-NEXT: ldr x30, [sp], #16 ; CHECK-LINUX-NEXT: ret @.str = private unnamed_addr constant [7 x i8] c"hello\0A\00" diff --git a/test/CodeGen/AArch64/arm64-inline-asm.ll b/test/CodeGen/AArch64/arm64-inline-asm.ll index ac6e8a7731c6..4d4adb10d556 100644 --- a/test/CodeGen/AArch64/arm64-inline-asm.ll +++ b/test/CodeGen/AArch64/arm64-inline-asm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-ios -aarch64-neon-syntax=apple -no-integrated-as -disable-post-ra | FileCheck %s ; rdar://9167275 @@ -232,3 +232,17 @@ define void @test_zero_reg(i32* %addr) { ret void } + +define <2 x float> @test_vreg_64bit(<2 x float> %in) nounwind { + ; CHECK-LABEL: test_vreg_64bit: + %1 = tail call <2 x float> asm sideeffect "fadd ${0}.2s, ${1}.2s, ${1}.2s", "={v14},w"(<2 x float> %in) nounwind + ; CHECK fadd v14.2s, v0.2s, v0.2s: + ret <2 x float> %1 +} + +define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind { + ; CHECK-LABEL: test_vreg_128bit: + %1 = tail call <4 x float> asm sideeffect "fadd ${0}.4s, ${1}.4s, ${1}.4s", "={v14},w"(<4 x float> %in) nounwind + ; CHECK fadd v14.4s, v0.4s, v0.4s: + ret <4 x float> %1 +} diff --git a/test/CodeGen/AArch64/arm64-join-reserved.ll b/test/CodeGen/AArch64/arm64-join-reserved.ll index c65cf95be2e5..dee034483541 100644 --- a/test/CodeGen/AArch64/arm64-join-reserved.ll +++ b/test/CodeGen/AArch64/arm64-join-reserved.ll @@ -5,7 +5,7 @@ target triple = "arm64-apple-macosx10" ; A move isn't necessary. ; ; CHECK-LABEL: g: -; CHECK: str xzr, [sp, #-16]! +; CHECK: str xzr, [sp] ; CHECK: bl ; CHECK: ret define void @g() nounwind ssp { diff --git a/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/test/CodeGen/AArch64/arm64-ldp-cluster.ll new file mode 100644 index 000000000000..0cfbe5958f4d --- /dev/null +++ b/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -0,0 +1,150 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m1 -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck --check-prefix=EXYNOS %s + +; Test ldr clustering. +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldr_int:BB#0 +; CHECK: Cluster ld/st SU(1) - SU(2) +; CHECK: SU(1): %vreg{{[0-9]+}} = LDRWui +; CHECK: SU(2): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldr_int:BB#0 +; EXYNOS: Cluster ld/st SU(1) - SU(2) +; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRWui +define i32 @ldr_int(i32* %a) nounwind { + %p1 = getelementptr inbounds i32, i32* %a, i32 1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 2 + %tmp2 = load i32, i32* %p2, align 2 + %tmp3 = add i32 %tmp1, %tmp2 + ret i32 %tmp3 +} + +; Test ldpsw clustering +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldp_sext_int:BB#0 +; CHECK: Cluster ld/st SU(1) - SU(2) +; CHECK: SU(1): %vreg{{[0-9]+}} = LDRSWui +; CHECK: SU(2): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldp_sext_int:BB#0 +; EXYNOS: Cluster ld/st SU(1) - SU(2) +; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRSWui +define i64 @ldp_sext_int(i32* %p) nounwind { + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = sext i32 %tmp to i64 + %sexttmp1 = sext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + ret i64 %add +} + +; Test ldur clustering. +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldur_int:BB#0 +; CHECK: Cluster ld/st SU(2) - SU(1) +; CHECK: SU(1): %vreg{{[0-9]+}} = LDURWi +; CHECK: SU(2): %vreg{{[0-9]+}} = LDURWi +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldur_int:BB#0 +; EXYNOS: Cluster ld/st SU(2) - SU(1) +; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDURWi +; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDURWi +define i32 @ldur_int(i32* %a) nounwind { + %p1 = getelementptr inbounds i32, i32* %a, i32 -1 + %tmp1 = load i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 -2 + %tmp2 = load i32, i32* %p2, align 2 + %tmp3 = add i32 %tmp1, %tmp2 + ret i32 %tmp3 +} + +; Test sext + zext clustering. +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldp_half_sext_zext_int:BB#0 +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): %vreg{{[0-9]+}} = LDRSWui +; CHECK: SU(4): %vreg{{[0-9]+}}:sub_32 = LDRWui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldp_half_sext_zext_int:BB#0 +; EXYNOS: Cluster ld/st SU(3) - SU(4) +; EXYNOS: SU(3): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: SU(4): %vreg{{[0-9]+}}:sub_32 = LDRWui +define i64 @ldp_half_sext_zext_int(i64* %q, i32* %p) nounwind { + %tmp0 = load i64, i64* %q, align 4 + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = sext i32 %tmp to i64 + %sexttmp1 = zext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + %add1 = add nsw i64 %add, %tmp0 + ret i64 %add1 +} + +; Test zext + sext clustering. +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldp_half_zext_sext_int:BB#0 +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): %vreg{{[0-9]+}}:sub_32 = LDRWui +; CHECK: SU(4): %vreg{{[0-9]+}} = LDRSWui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldp_half_zext_sext_int:BB#0 +; EXYNOS: Cluster ld/st SU(3) - SU(4) +; EXYNOS: SU(3): %vreg{{[0-9]+}}:sub_32 = LDRWui +; EXYNOS: SU(4): %vreg{{[0-9]+}} = LDRSWui +define i64 @ldp_half_zext_sext_int(i64* %q, i32* %p) nounwind { + %tmp0 = load i64, i64* %q, align 4 + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = zext i32 %tmp to i64 + %sexttmp1 = sext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + %add1 = add nsw i64 %add, %tmp0 + ret i64 %add1 +} + +; Verify we don't cluster volatile loads. +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldr_int_volatile:BB#0 +; CHECK-NOT: Cluster ld/st +; CHECK: SU(1): %vreg{{[0-9]+}} = LDRWui +; CHECK: SU(2): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldr_int_volatile:BB#0 +; EXYNOS-NOT: Cluster ld/st +; EXYNOS: SU(1): %vreg{{[0-9]+}} = LDRWui +; EXYNOS: SU(2): %vreg{{[0-9]+}} = LDRWui +define i32 @ldr_int_volatile(i32* %a) nounwind { + %p1 = getelementptr inbounds i32, i32* %a, i32 1 + %tmp1 = load volatile i32, i32* %p1, align 2 + %p2 = getelementptr inbounds i32, i32* %a, i32 2 + %tmp2 = load volatile i32, i32* %p2, align 2 + %tmp3 = add i32 %tmp1, %tmp2 + ret i32 %tmp3 +} + +; Test ldq clustering (no clustering for Exynos). +; CHECK: ********** MI Scheduling ********** +; CHECK-LABEL: ldq_cluster:BB#0 +; CHECK: Cluster ld/st SU(1) - SU(3) +; CHECK: SU(1): %vreg{{[0-9]+}} = LDRQui +; CHECK: SU(3): %vreg{{[0-9]+}} = LDRQui +; EXYNOS: ********** MI Scheduling ********** +; EXYNOS-LABEL: ldq_cluster:BB#0 +; EXYNOS-NOT: Cluster ld/st +define <2 x i64> @ldq_cluster(i64* %p) { + %a1 = bitcast i64* %p to <2 x i64>* + %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8 + %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2 + %a2 = bitcast i64* %add.ptr2 to <2 x i64>* + %tmp2 = add nsw <2 x i64> %tmp1, %tmp1 + %tmp3 = load <2 x i64>, <2 x i64>* %a2, align 8 + %res = mul nsw <2 x i64> %tmp2, %tmp3 + ret <2 x i64> %res +} diff --git a/test/CodeGen/AArch64/arm64-memcpy-inline.ll b/test/CodeGen/AArch64/arm64-memcpy-inline.ll index 2f91ce252336..23e90100fb94 100644 --- a/test/CodeGen/AArch64/arm64-memcpy-inline.ll +++ b/test/CodeGen/AArch64/arm64-memcpy-inline.ll @@ -40,7 +40,7 @@ entry: define void @t2(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t2: -; CHECK: movz [[REG3:w[0-9]+]] +; CHECK: mov [[REG3:w[0-9]+]] ; CHECK: movk [[REG3]], ; CHECK: str [[REG3]], [x0, #32] ; CHECK: ldp [[DEST1:q[0-9]+]], [[DEST2:q[0-9]+]], [x{{[0-9]+}}] @@ -75,9 +75,9 @@ define void @t5(i8* nocapture %C) nounwind { entry: ; CHECK-LABEL: t5: ; CHECK: strb wzr, [x0, #6] -; CHECK: movz [[REG7:w[0-9]+]], #0x5453 +; CHECK: mov [[REG7:w[0-9]+]], #21587 ; CHECK: strh [[REG7]], [x0, #4] -; CHECK: movz [[REG8:w[0-9]+]], +; CHECK: mov [[REG8:w[0-9]+]], ; CHECK: movk [[REG8]], ; CHECK: str [[REG8]], [x0] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str5, i64 0, i64 0), i64 7, i32 1, i1 false) diff --git a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll index 6db21043f670..8b270abef59a 100644 --- a/test/CodeGen/AArch64/arm64-misched-basic-A53.ll +++ b/test/CodeGen/AArch64/arm64-misched-basic-A53.ll @@ -1,5 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - -misched-limit=2 2>&1 > /dev/null | FileCheck %s ; ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled ; much higher than the ADD instructions in order to hide latency. When not diff --git a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 770521b75280..292fbb744cea 100644 --- a/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -9,6 +9,9 @@ ; CHECK: Successors: ; CHECK-NEXT: val SU(5): Latency=4 Reg=%vreg2 ; CHECK-NEXT: ch SU(4): Latency=0 +; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 +; CHECK: Successors: +; CHECK: ch SU(4): Latency=0 ; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 ; CHECK: SU(5): %W0 = COPY %vreg2; GPR32:%vreg2 ; CHECK: ** ScheduleDAGMI::schedule picking next node diff --git a/test/CodeGen/AArch64/arm64-misched-multimmo.ll b/test/CodeGen/AArch64/arm64-misched-multimmo.ll new file mode 100644 index 000000000000..d4e8aa1a0a06 --- /dev/null +++ b/test/CodeGen/AArch64/arm64-misched-multimmo.ll @@ -0,0 +1,23 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -enable-misched=0 -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s + + +@G1 = common global [100 x i32] zeroinitializer, align 4 +@G2 = common global [100 x i32] zeroinitializer, align 4 + +; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling. +; +; CHECK-LABEL: # Machine code for function foo: Properties: , %W{{[0-9]+}} = LDPWi +; CHECK: Successors: +; CHECK-NOT: ch SU(4) +; CHECK: SU(3) +; CHECK: SU(4): STRWui %WZR, %X{{[0-9]+}} +define i32 @foo() { +entry: + %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 0), align 4 + %1 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G2, i64 0, i64 1), align 4 + store i32 0, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @G1, i64 0, i64 0), align 4 + %add = add nsw i32 %1, %0 + ret i32 %add +} diff --git a/test/CodeGen/AArch64/arm64-movi.ll b/test/CodeGen/AArch64/arm64-movi.ll index 2cd368d909dc..344e2224ab43 100644 --- a/test/CodeGen/AArch64/arm64-movi.ll +++ b/test/CodeGen/AArch64/arm64-movi.ll @@ -7,21 +7,21 @@ ; 64-bit immed with 32-bit pattern size, rotated by 0. define i64 @test64_32_rot0() nounwind { ; CHECK-LABEL: test64_32_rot0: -; CHECK: orr x0, xzr, #0x700000007 +; CHECK: mov x0, #30064771079 ret i64 30064771079 } ; 64-bit immed with 32-bit pattern size, rotated by 2. define i64 @test64_32_rot2() nounwind { ; CHECK-LABEL: test64_32_rot2: -; CHECK: orr x0, xzr, #0xc0000003c0000003 +; CHECK: mov x0, #-4611686002321260541 ret i64 13835058071388291075 } ; 64-bit immed with 4-bit pattern size, rotated by 3. define i64 @test64_4_rot3() nounwind { ; CHECK-LABEL: test64_4_rot3: -; CHECK: orr x0, xzr, #0xeeeeeeeeeeeeeeee +; CHECK: mov x0, #-1229782938247303442 ret i64 17216961135462248174 } @@ -35,7 +35,7 @@ define i32 @test32_32_rot16() nounwind { ; 32-bit immed with 2-bit pattern size, rotated by 1. define i32 @test32_2_rot1() nounwind { ; CHECK-LABEL: test32_2_rot1: -; CHECK: orr w0, wzr, #0xaaaaaaaa +; CHECK: mov w0, #-1431655766 ret i32 2863311530 } @@ -45,30 +45,30 @@ define i32 @test32_2_rot1() nounwind { define i32 @movz() nounwind { ; CHECK-LABEL: movz: -; CHECK: movz w0, #0x5 +; CHECK: mov w0, #5 ret i32 5 } define i64 @movz_3movk() nounwind { ; CHECK-LABEL: movz_3movk: -; CHECK: movz x0, #0x5, lsl #48 -; CHECK-NEXT: movk x0, #0x1234, lsl #32 -; CHECK-NEXT: movk x0, #0xabcd, lsl #16 -; CHECK-NEXT: movk x0, #0x5678 +; CHECK: mov x0, #1407374883553280 +; CHECK-NEXT: movk x0, #4660, lsl #32 +; CHECK-NEXT: movk x0, #43981, lsl #16 +; CHECK-NEXT: movk x0, #22136 ret i64 1427392313513592 } define i64 @movz_movk_skip1() nounwind { ; CHECK-LABEL: movz_movk_skip1: -; CHECK: movz x0, #0x5, lsl #32 -; CHECK-NEXT: movk x0, #0x4321, lsl #16 +; CHECK: mov x0, #21474836480 +; CHECK-NEXT: movk x0, #17185, lsl #16 ret i64 22601072640 } define i64 @movz_skip1_movk() nounwind { ; CHECK-LABEL: movz_skip1_movk: -; CHECK: movz x0, #0x8654, lsl #32 -; CHECK-NEXT: movk x0, #0x1234 +; CHECK: mov x0, #147695335374848 +; CHECK-NEXT: movk x0, #4660 ret i64 147695335379508 } @@ -78,14 +78,14 @@ define i64 @movz_skip1_movk() nounwind { define i64 @movn() nounwind { ; CHECK-LABEL: movn: -; CHECK: movn x0, #0x29 +; CHECK: mov x0, #-42 ret i64 -42 } define i64 @movn_skip1_movk() nounwind { ; CHECK-LABEL: movn_skip1_movk: -; CHECK: movn x0, #0x29, lsl #32 -; CHECK-NEXT: movk x0, #0x1234 +; CHECK: mov x0, #-176093659137 +; CHECK-NEXT: movk x0, #4660 ret i64 -176093720012 } @@ -96,107 +96,107 @@ define i64 @movn_skip1_movk() nounwind { define i64 @orr_movk1() nounwind { ; CHECK-LABEL: orr_movk1: -; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: mov x0, #72056494543077120 +; CHECK: movk x0, #57005, lsl #16 ret i64 72056498262245120 } define i64 @orr_movk2() nounwind { ; CHECK-LABEL: orr_movk2: -; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #0xdead, lsl #48 +; CHECK: mov x0, #72056494543077120 +; CHECK: movk x0, #57005, lsl #48 ret i64 -2400982650836746496 } define i64 @orr_movk3() nounwind { ; CHECK-LABEL: orr_movk3: -; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #0xdead, lsl #32 +; CHECK: mov x0, #72056494543077120 +; CHECK: movk x0, #57005, lsl #32 ret i64 72020953688702720 } define i64 @orr_movk4() nounwind { ; CHECK-LABEL: orr_movk4: -; CHECK: orr x0, xzr, #0xffff0000ffff0 -; CHECK: movk x0, #0xdead +; CHECK: mov x0, #72056494543077120 +; CHECK: movk x0, #57005 ret i64 72056494543068845 } ; rdar://14987618 define i64 @orr_movk5() nounwind { ; CHECK-LABEL: orr_movk5: -; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: mov x0, #-71777214294589696 +; CHECK: movk x0, #57005, lsl #16 ret i64 -71777214836900096 } define i64 @orr_movk6() nounwind { ; CHECK-LABEL: orr_movk6: -; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #0xdead, lsl #16 -; CHECK: movk x0, #0xdead, lsl #48 +; CHECK: mov x0, #-71777214294589696 +; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #57005, lsl #48 ret i64 -2400982647117578496 } define i64 @orr_movk7() nounwind { ; CHECK-LABEL: orr_movk7: -; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #0xdead, lsl #48 +; CHECK: mov x0, #-71777214294589696 +; CHECK: movk x0, #57005, lsl #48 ret i64 -2400982646575268096 } define i64 @orr_movk8() nounwind { ; CHECK-LABEL: orr_movk8: -; CHECK: orr x0, xzr, #0xff00ff00ff00ff00 -; CHECK: movk x0, #0xdead -; CHECK: movk x0, #0xdead, lsl #48 +; CHECK: mov x0, #-71777214294589696 +; CHECK: movk x0, #57005 +; CHECK: movk x0, #57005, lsl #48 ret i64 -2400982646575276371 } ; rdar://14987715 define i64 @orr_movk9() nounwind { ; CHECK-LABEL: orr_movk9: -; CHECK: orr x0, xzr, #0xffffff000000000 -; CHECK: movk x0, #0xff00 -; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: mov x0, #1152921435887370240 +; CHECK: movk x0, #65280 +; CHECK: movk x0, #57005, lsl #16 ret i64 1152921439623315200 } define i64 @orr_movk10() nounwind { ; CHECK-LABEL: orr_movk10: -; CHECK: orr x0, xzr, #0xfffffffffffff00 -; CHECK: movk x0, #0xdead, lsl #16 +; CHECK: mov x0, #1152921504606846720 +; CHECK: movk x0, #57005, lsl #16 ret i64 1152921504047824640 } define i64 @orr_movk11() nounwind { ; CHECK-LABEL: orr_movk11: -; CHECK: orr x0, xzr, #0xfff00000000000ff -; CHECK: movk x0, #0xdead, lsl #16 -; CHECK: movk x0, #0xffff, lsl #32 +; CHECK: mov x0, #-4503599627370241 +; CHECK: movk x0, #57005, lsl #16 +; CHECK: movk x0, #65535, lsl #32 ret i64 -4222125209747201 } define i64 @orr_movk12() nounwind { ; CHECK-LABEL: orr_movk12: -; CHECK: orr x0, xzr, #0xfff00000000000ff -; CHECK: movk x0, #0xdead, lsl #32 +; CHECK: mov x0, #-4503599627370241 +; CHECK: movk x0, #57005, lsl #32 ret i64 -4258765016661761 } define i64 @orr_movk13() nounwind { ; CHECK-LABEL: orr_movk13: -; CHECK: orr x0, xzr, #0xfffff000000 -; CHECK: movk x0, #0xdead -; CHECK: movk x0, #0xdead, lsl #48 +; CHECK: mov x0, #17592169267200 +; CHECK: movk x0, #57005 +; CHECK: movk x0, #57005, lsl #48 ret i64 -2401245434149282131 } ; rdar://13944082 define i64 @g() nounwind { ; CHECK-LABEL: g: -; CHECK: movz x0, #0xffff, lsl #48 -; CHECK: movk x0, #0x2 +; CHECK: mov x0, #-281474976710656 +; CHECK: movk x0, #2 entry: ret i64 -281474976710654 } diff --git a/test/CodeGen/AArch64/arm64-mul.ll b/test/CodeGen/AArch64/arm64-mul.ll index 2e7986d67d9e..a424dc761bc8 100644 --- a/test/CodeGen/AArch64/arm64-mul.ll +++ b/test/CodeGen/AArch64/arm64-mul.ll @@ -88,3 +88,65 @@ entry: %tmp4 = sub i64 0, %tmp3 ret i64 %tmp4 } + +define i64 @t9(i32 %a) nounwind { +entry: +; CHECK-LABEL: t9: +; CHECK: umull {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + %tmp1 = zext i32 %a to i64 + %tmp2 = mul i64 %tmp1, 139968 + ret i64 %tmp2 +} + +; Check 64-bit multiplication is used for constants > 32 bits. +define i64 @t10(i32 %a) nounwind { +entry: +; CHECK-LABEL: t10: +; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}} + %tmp1 = sext i32 %a to i64 + %tmp2 = mul i64 %tmp1, 2147483650 ; = 2^31 + 2 + ret i64 %tmp2 +} + +; Check the sext_inreg case. +define i64 @t11(i64 %a) nounwind { +entry: +; CHECK-LABEL: t11: +; CHECK: smnegl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} + %tmp1 = trunc i64 %a to i32 + %tmp2 = sext i32 %tmp1 to i64 + %tmp3 = mul i64 %tmp2, -2395238 + %tmp4 = sub i64 0, %tmp3 + ret i64 %tmp4 +} + +define i64 @t12(i64 %a, i64 %b) nounwind { +entry: +; CHECK-LABEL: t12: +; CHECK: smaddl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + %tmp1 = trunc i64 %a to i32 + %tmp2 = sext i32 %tmp1 to i64 + %tmp3 = mul i64 %tmp2, -34567890 + %tmp4 = add i64 %b, %tmp3 + ret i64 %tmp4 +} + +define i64 @t13(i32 %a, i64 %b) nounwind { +entry: +; CHECK-LABEL: t13: +; CHECK: umsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + %tmp1 = zext i32 %a to i64 + %tmp3 = mul i64 %tmp1, 12345678 + %tmp4 = sub i64 %b, %tmp3 + ret i64 %tmp4 +} + +define i64 @t14(i32 %a, i64 %b) nounwind { +entry: +; CHECK-LABEL: t14: +; CHECK: smsubl {{x[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{x[0-9]+}} + %tmp1 = sext i32 %a to i64 + %tmp3 = mul i64 %tmp1, -12345678 + %tmp4 = sub i64 %b, %tmp3 + ret i64 %tmp4 +} diff --git a/test/CodeGen/AArch64/arm64-narrow-ldst-merge.ll b/test/CodeGen/AArch64/arm64-narrow-ldst-merge.ll index 5276ac334a71..be5b7e9b2966 100644 --- a/test/CodeGen/AArch64/arm64-narrow-ldst-merge.ll +++ b/test/CodeGen/AArch64/arm64-narrow-ldst-merge.ll @@ -1,5 +1,6 @@ -; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=LE -; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=BE +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=cortex-a57 -verify-machineinstrs -enable-narrow-ld-merge=true | FileCheck %s --check-prefix=CHECK --check-prefix=LE +; RUN: llc < %s -mtriple aarch64_be--none-eabi -mcpu=cortex-a57 -verify-machineinstrs -enable-narrow-ld-merge=true | FileCheck %s --check-prefix=CHECK --check-prefix=BE +; RUN: llc < %s -mtriple aarch64--none-eabi -mcpu=kryo -verify-machineinstrs -enable-narrow-ld-merge=true | FileCheck %s --check-prefix=CHECK --check-prefix=LE ; CHECK-LABEL: Ldrh_merge ; CHECK-NOT: ldrh @@ -352,6 +353,56 @@ entry: ret void } +; CHECK-LABEL: Strw_zero +; CHECK: str xzr +define void @Strw_zero(i32* nocapture %P, i32 %n) { +entry: + %idxprom = sext i32 %n to i64 + %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom + store i32 0, i32* %arrayidx + %add = add nsw i32 %n, 1 + %idxprom1 = sext i32 %add to i64 + %arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1 + store i32 0, i32* %arrayidx2 + ret void +} + +; CHECK-LABEL: Strw_zero_nonzero +; CHECK: stp wzr, w1 +define void @Strw_zero_nonzero(i32* nocapture %P, i32 %n) { +entry: + %idxprom = sext i32 %n to i64 + %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom + store i32 0, i32* %arrayidx + %add = add nsw i32 %n, 1 + %idxprom1 = sext i32 %add to i64 + %arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1 + store i32 %n, i32* %arrayidx2 + ret void +} + +; CHECK-LABEL: Strw_zero_4 +; CHECK: stp xzr +define void @Strw_zero_4(i32* nocapture %P, i32 %n) { +entry: + %idxprom = sext i32 %n to i64 + %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom + store i32 0, i32* %arrayidx + %add = add nsw i32 %n, 1 + %idxprom1 = sext i32 %add to i64 + %arrayidx2 = getelementptr inbounds i32, i32* %P, i64 %idxprom1 + store i32 0, i32* %arrayidx2 + %add3 = add nsw i32 %n, 2 + %idxprom4 = sext i32 %add3 to i64 + %arrayidx5 = getelementptr inbounds i32, i32* %P, i64 %idxprom4 + store i32 0, i32* %arrayidx5 + %add6 = add nsw i32 %n, 3 + %idxprom7 = sext i32 %add6 to i64 + %arrayidx8 = getelementptr inbounds i32, i32* %P, i64 %idxprom7 + store i32 0, i32* %arrayidx8 + ret void +} + ; CHECK-LABEL: Sturb_zero ; CHECK: sturh wzr define void @Sturb_zero(i8* nocapture %P, i32 %n) #0 { @@ -404,3 +455,42 @@ entry: store i16 0, i16* %arrayidx9 ret void } + +; CHECK-LABEL: Sturw_zero +; CHECK: stur xzr +define void @Sturw_zero(i32* nocapture %P, i32 %n) { +entry: + %sub = add nsw i32 %n, -3 + %idxprom = sext i32 %sub to i64 + %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom + store i32 0, i32* %arrayidx + %sub1 = add nsw i32 %n, -4 + %idxprom2 = sext i32 %sub1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %P, i64 %idxprom2 + store i32 0, i32* %arrayidx3 + ret void +} + +; CHECK-LABEL: Sturw_zero_4 +; CHECK: stp xzr, xzr +define void @Sturw_zero_4(i32* nocapture %P, i32 %n) { +entry: + %sub = add nsw i32 %n, -3 + %idxprom = sext i32 %sub to i64 + %arrayidx = getelementptr inbounds i32, i32* %P, i64 %idxprom + store i32 0, i32* %arrayidx + %sub1 = add nsw i32 %n, -4 + %idxprom2 = sext i32 %sub1 to i64 + %arrayidx3 = getelementptr inbounds i32, i32* %P, i64 %idxprom2 + store i32 0, i32* %arrayidx3 + %sub4 = add nsw i32 %n, -2 + %idxprom5 = sext i32 %sub4 to i64 + %arrayidx6 = getelementptr inbounds i32, i32* %P, i64 %idxprom5 + store i32 0, i32* %arrayidx6 + %sub7 = add nsw i32 %n, -1 + %idxprom8 = sext i32 %sub7 to i64 + %arrayidx9 = getelementptr inbounds i32, i32* %P, i64 %idxprom8 + store i32 0, i32* %arrayidx9 + ret void +} + diff --git a/test/CodeGen/AArch64/arm64-neon-2velem-high.ll b/test/CodeGen/AArch64/arm64-neon-2velem-high.ll index 3ff1e61d0298..575acf723753 100644 --- a/test/CodeGen/AArch64/arm64-neon-2velem-high.ll +++ b/test/CodeGen/AArch64/arm64-neon-2velem-high.ll @@ -18,7 +18,7 @@ entry: define <4 x i32> @test_vmull_high_n_s16_imm(<8 x i16> %a) #0 { ; CHECK-LABEL: test_vmull_high_n_s16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: smull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -42,7 +42,7 @@ entry: define <2 x i64> @test_vmull_high_n_s32_imm(<4 x i32> %a) #0 { ; CHECK-LABEL: test_vmull_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1, msl #8 +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #1, msl #8 ; CHECK-NEXT: smull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -68,7 +68,7 @@ entry: define <4 x i32> @test_vmull_high_n_u16_imm(<8 x i16> %a) #0 { ; CHECK-LABEL: test_vmull_high_n_u16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x11, lsl #8 +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #17, lsl #8 ; CHECK-NEXT: umull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -92,7 +92,7 @@ entry: define <2 x i64> @test_vmull_high_n_u32_imm(<4 x i32> %a) #0 { ; CHECK-LABEL: test_vmull_high_n_u32_imm: -; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].4s, #0x1, msl #8 +; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].4s, #1, msl #8 ; CHECK-NEXT: umull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -118,7 +118,7 @@ entry: define <4 x i32> @test_vqdmull_high_n_s16_imm(<8 x i16> %a) #0 { ; CHECK-LABEL: test_vqdmull_high_n_s16_imm: -; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].8h, #0x11, lsl #8 +; CHECK-NEXT: mvni [[REPLICATE:v[0-9]+]].8h, #17, lsl #8 ; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -142,7 +142,7 @@ entry: define <2 x i64> @test_vqdmull_high_n_s32_imm(<4 x i32> %a) #0 { ; CHECK-LABEL: test_vqdmull_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: sqdmull2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -169,7 +169,7 @@ entry: define <4 x i32> @test_vmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vmlal_high_n_s16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: smlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -195,7 +195,7 @@ entry: define <2 x i64> @test_vmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vmlal_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: smlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -223,7 +223,7 @@ entry: define <4 x i32> @test_vmlal_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vmlal_high_n_u16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: umlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -249,7 +249,7 @@ entry: define <2 x i64> @test_vmlal_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vmlal_high_n_u32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: umlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -277,7 +277,7 @@ entry: define <4 x i32> @test_vqdmlal_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vqdmlal_high_n_s16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -303,7 +303,7 @@ entry: define <2 x i64> @test_vqdmlal_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vqdmlal_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: sqdmlal2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -331,7 +331,7 @@ entry: define <4 x i32> @test_vmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vmlsl_high_n_s16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: smlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -357,7 +357,7 @@ entry: define <2 x i64> @test_vmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vmlsl_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: smlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -385,7 +385,7 @@ entry: define <4 x i32> @test_vmlsl_high_n_u16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vmlsl_high_n_u16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: umlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -411,7 +411,7 @@ entry: define <2 x i64> @test_vmlsl_high_n_u32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vmlsl_high_n_u32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: umlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: @@ -439,7 +439,7 @@ entry: define <4 x i32> @test_vqdmlsl_high_n_s16_imm(<4 x i32> %a, <8 x i16> %b) #0 { ; CHECK-LABEL: test_vqdmlsl_high_n_s16_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].8h, #29 ; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, [[REPLICATE]].8h ; CHECK-NEXT: ret entry: @@ -465,7 +465,7 @@ entry: define <2 x i64> @test_vqdmlsl_high_n_s32_imm(<2 x i64> %a, <4 x i32> %b) #0 { ; CHECK-LABEL: test_vqdmlsl_high_n_s32_imm: -; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #0x1d +; CHECK-NEXT: movi [[REPLICATE:v[0-9]+]].4s, #29 ; CHECK-NEXT: sqdmlsl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, [[REPLICATE]].4s ; CHECK-NEXT: ret entry: diff --git a/test/CodeGen/AArch64/arm64-neon-copy.ll b/test/CodeGen/AArch64/arm64-neon-copy.ll index 83b1cac70f5c..e91a1a42c233 100644 --- a/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -902,6 +902,43 @@ define <8 x i8> @getl(<16 x i8> %x) #0 { ret <8 x i8> %vecinit14 } +; CHECK-LABEL: test_extracts_inserts_varidx_extract: +; CHECK: str q0 +; CHECK: add x[[PTR:[0-9]+]], {{.*}}, w0, sxtw #1 +; CHECK-DAG: ld1 { v[[R:[0-9]+]].h }[0], [x[[PTR]]] +; CHECK-DAG: ins v[[R]].h[1], v0.h[1] +; CHECK-DAG: ins v[[R]].h[2], v0.h[2] +; CHECK-DAG: ins v[[R]].h[3], v0.h[3] +define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) { + %tmp = extractelement <8 x i16> %x, i32 %idx + %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0 + %tmp3 = extractelement <8 x i16> %x, i32 1 + %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1 + %tmp5 = extractelement <8 x i16> %x, i32 2 + %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2 + %tmp7 = extractelement <8 x i16> %x, i32 3 + %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 3 + ret <4 x i16> %tmp8 +} + +; CHECK-LABEL: test_extracts_inserts_varidx_insert: +; CHECK: str h0, [{{.*}}, w0, sxtw #1] +; CHECK-DAG: ldr d[[R:[0-9]+]] +; CHECK-DAG: ins v[[R]].h[1], v0.h[1] +; CHECK-DAG: ins v[[R]].h[2], v0.h[2] +; CHECK-DAG: ins v[[R]].h[3], v0.h[3] +define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) { + %tmp = extractelement <8 x i16> %x, i32 0 + %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx + %tmp3 = extractelement <8 x i16> %x, i32 1 + %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1 + %tmp5 = extractelement <8 x i16> %x, i32 2 + %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2 + %tmp7 = extractelement <8 x i16> %x, i32 3 + %tmp8 = insertelement <4 x i16> %tmp6, i16 %tmp7, i32 3 + ret <4 x i16> %tmp8 +} + define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) { ; CHECK-LABEL: test_dup_v2i32_v4i16: ; CHECK: dup v0.4h, v0.h[2] @@ -1368,7 +1405,7 @@ define <4 x i16> @concat_vector_v4i16_const() { define <4 x i16> @concat_vector_v4i16_const_one() { ; CHECK-LABEL: concat_vector_v4i16_const_one: -; CHECK: movi {{v[0-9]+}}.4h, #0x1 +; CHECK: movi {{v[0-9]+}}.4h, #1 %r = shufflevector <1 x i16> , <1 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %r } @@ -1396,7 +1433,7 @@ define <8 x i16> @concat_vector_v8i16_const() { define <8 x i16> @concat_vector_v8i16_const_one() { ; CHECK-LABEL: concat_vector_v8i16_const_one: -; CHECK: movi {{v[0-9]+}}.8h, #0x1 +; CHECK: movi {{v[0-9]+}}.8h, #1 %r = shufflevector <1 x i16> , <1 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %r } diff --git a/test/CodeGen/AArch64/arm64-nvcast.ll b/test/CodeGen/AArch64/arm64-nvcast.ll index 3cb1bf25fc34..c3a1640ab012 100644 --- a/test/CodeGen/AArch64/arm64-nvcast.ll +++ b/test/CodeGen/AArch64/arm64-nvcast.ll @@ -2,7 +2,7 @@ ; CHECK-LABEL: _test: ; CHECK: fmov.2d v0, #2.00000000 -; CHECK: str q0, [sp] +; CHECK: str q0, [sp, #-16]! ; CHECK: mov x8, sp ; CHECK: ldr s0, [x8, w1, sxtw #2] ; CHECK: str s0, [x0] @@ -15,8 +15,8 @@ entry: } ; CHECK-LABEL: _test2 -; CHECK: movi.16b v0, #0x3f -; CHECK: str q0, [sp] +; CHECK: movi.16b v0, #63 +; CHECK: str q0, [sp, #-16]! ; CHECK: mov x8, sp ; CHECK: ldr s0, [x8, w1, sxtw #2] ; CHECK: str s0, [x0] diff --git a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll index c2006ccdd064..caf4498276ce 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint-webkit_jscc.ll @@ -1,5 +1,12 @@ -; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone < %s | FileCheck %s ; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -fast-isel < %s | FileCheck %s --check-prefix=FAST +; RUN: llc -mtriple=arm64-apple-darwin -enable-misched=0 -mcpu=cyclone -filetype=obj -o %t %s +; RUN: llvm-objdump -triple arm64-apple-darwin -d %t | FileCheck %s --check-prefix CHECK-ENCODING + +; CHECK-ENCODING-NOT: +; CHECK-ENCODING: mov x16, #281470681743360 +; CHECK-ENCODING: movk x16, #57005, lsl #16 +; CHECK-ENCODING: movk x16, #48879 ; One argument will be passed in register, the other will be pushed on the stack. ; Return value in x0. @@ -7,20 +14,20 @@ define void @jscall_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: ; CHECK-LABEL: jscall_patchpoint_codegen: ; CHECK: Ltmp -; CHECK: str x{{.+}}, [sp, #-16]! +; CHECK: str x{{.+}}, [sp] ; CHECK-NEXT: mov x0, x{{.+}} ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #0xffff, lsl #32 -; CHECK-NEXT: movk x16, #0xdead, lsl #16 -; CHECK-NEXT: movk x16, #0xbeef +; CHECK-NEXT: mov x16, #281470681743360 +; CHECK: movk x16, #57005, lsl #16 +; CHECK: movk x16, #48879 ; CHECK-NEXT: blr x16 ; FAST-LABEL: jscall_patchpoint_codegen: ; FAST: Ltmp -; FAST: str x{{.+}}, [sp, #-16]! +; FAST: str x{{.+}}, [sp] ; FAST: Ltmp -; FAST-NEXT: movz x16, #0xffff, lsl #32 -; FAST-NEXT: movk x16, #0xdead, lsl #16 -; FAST-NEXT: movk x16, #0xbeef +; FAST-NEXT: mov x16, #281470681743360 +; FAST-NEXT: movk x16, #57005, lsl #16 +; FAST-NEXT: movk x16, #48879 ; FAST-NEXT: blr x16 %resolveCall2 = inttoptr i64 281474417671919 to i8* %result = tail call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* %resolveCall2, i32 2, i64 %p4, i64 %p2) @@ -41,22 +48,22 @@ entry: ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2 ; CHECK-NEXT: str x[[REG]], [sp] ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #0xffff, lsl #32 -; CHECK-NEXT: movk x16, #0xdead, lsl #16 -; CHECK-NEXT: movk x16, #0xbeef +; CHECK-NEXT: mov x16, #281470681743360 +; CHECK-NEXT: movk x16, #57005, lsl #16 +; CHECK-NEXT: movk x16, #48879 ; CHECK-NEXT: blr x16 ; FAST-LABEL: jscall_patchpoint_codegen2: ; FAST: Ltmp ; FAST: orr [[REG1:x[0-9]+]], xzr, #0x2 ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6 -; FAST-NEXT: str [[REG1]], [sp, #-32]! +; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST: Ltmp -; FAST-NEXT: movz x16, #0xffff, lsl #32 -; FAST-NEXT: movk x16, #0xdead, lsl #16 -; FAST-NEXT: movk x16, #0xbeef +; FAST-NEXT: mov x16, #281470681743360 +; FAST-NEXT: movk x16, #57005, lsl #16 +; FAST-NEXT: movk x16, #48879 ; FAST-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 6, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6) @@ -68,7 +75,7 @@ define i64 @jscall_patchpoint_codegen3(i64 %callee) { entry: ; CHECK-LABEL: jscall_patchpoint_codegen3: ; CHECK: Ltmp -; CHECK: movz w[[REG:[0-9]+]], #0xa +; CHECK: mov w[[REG:[0-9]+]], #10 ; CHECK-NEXT: str x[[REG]], [sp, #48] ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x8 ; CHECK-NEXT: str w[[REG]], [sp, #36] @@ -79,9 +86,9 @@ entry: ; CHECK-NEXT: orr w[[REG:[0-9]+]], wzr, #0x2 ; CHECK-NEXT: str x[[REG]], [sp] ; CHECK: Ltmp -; CHECK-NEXT: movz x16, #0xffff, lsl #32 -; CHECK-NEXT: movk x16, #0xdead, lsl #16 -; CHECK-NEXT: movk x16, #0xbeef +; CHECK-NEXT: mov x16, #281470681743360 +; CHECK-NEXT: movk x16, #57005, lsl #16 +; CHECK-NEXT: movk x16, #48879 ; CHECK-NEXT: blr x16 ; FAST-LABEL: jscall_patchpoint_codegen3: ; FAST: Ltmp @@ -89,16 +96,16 @@ entry: ; FAST-NEXT: orr [[REG2:w[0-9]+]], wzr, #0x4 ; FAST-NEXT: orr [[REG3:x[0-9]+]], xzr, #0x6 ; FAST-NEXT: orr [[REG4:w[0-9]+]], wzr, #0x8 -; FAST-NEXT: movz [[REG5:x[0-9]+]], #0xa -; FAST-NEXT: str [[REG1]], [sp, #-64]! +; FAST-NEXT: mov [[REG5:x[0-9]+]], #10 +; FAST-NEXT: str [[REG1]], [sp] ; FAST-NEXT: str [[REG2]], [sp, #16] ; FAST-NEXT: str [[REG3]], [sp, #24] ; FAST-NEXT: str [[REG4]], [sp, #36] ; FAST-NEXT: str [[REG5]], [sp, #48] ; FAST: Ltmp -; FAST-NEXT: movz x16, #0xffff, lsl #32 -; FAST-NEXT: movk x16, #0xdead, lsl #16 -; FAST-NEXT: movk x16, #0xbeef +; FAST-NEXT: mov x16, #281470681743360 +; FAST-NEXT: movk x16, #57005, lsl #16 +; FAST-NEXT: movk x16, #48879 ; FAST-NEXT: blr x16 %call = inttoptr i64 281474417671919 to i8* %result = call webkit_jscc i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 7, i32 20, i8* %call, i32 10, i64 %callee, i64 2, i64 undef, i32 4, i32 undef, i64 6, i32 undef, i32 8, i32 undef, i64 10) @@ -115,4 +122,3 @@ define webkit_jscc zeroext i16 @test_i16(i16 zeroext %a, i16 zeroext %b) { declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) - diff --git a/test/CodeGen/AArch64/arm64-patchpoint.ll b/test/CodeGen/AArch64/arm64-patchpoint.ll index d9ec7e50ff80..2f9004bb22e6 100644 --- a/test/CodeGen/AArch64/arm64-patchpoint.ll +++ b/test/CodeGen/AArch64/arm64-patchpoint.ll @@ -6,13 +6,13 @@ define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { entry: ; CHECK-LABEL: trivial_patchpoint_codegen: -; CHECK: movz x16, #0xdead, lsl #32 -; CHECK-NEXT: movk x16, #0xbeef, lsl #16 -; CHECK-NEXT: movk x16, #0xcafe +; CHECK: mov x16, #244834610708480 +; CHECK-NEXT: movk x16, #48879, lsl #16 +; CHECK-NEXT: movk x16, #51966 ; CHECK-NEXT: blr x16 -; CHECK: movz x16, #0xdead, lsl #32 -; CHECK-NEXT: movk x16, #0xbeef, lsl #16 -; CHECK-NEXT: movk x16, #0xcaff +; CHECK: mov x16, #244834610708480 +; CHECK-NEXT: movk x16, #48879, lsl #16 +; CHECK-NEXT: movk x16, #51967 ; CHECK-NEXT: blr x16 ; CHECK: ret %resolveCall2 = inttoptr i64 244837814094590 to i8* @@ -26,10 +26,11 @@ entry: ; as a leaf function. ; ; CHECK-LABEL: caller_meta_leaf -; CHECK: mov x29, sp -; CHECK-NEXT: sub sp, sp, #32 +; CHECK: sub sp, sp, #48 +; CHECK-NEXT: stp x29, x30, [sp, #32] +; CHECK-NEXT: add x29, sp, #32 ; CHECK: Ltmp -; CHECK: mov sp, x29 +; CHECK: add sp, sp, #48 ; CHECK: ret define void @caller_meta_leaf() { diff --git a/test/CodeGen/AArch64/arm64-register-pairing.ll b/test/CodeGen/AArch64/arm64-register-pairing.ll index 99defb1aad7c..eac7e5cb3363 100644 --- a/test/CodeGen/AArch64/arm64-register-pairing.ll +++ b/test/CodeGen/AArch64/arm64-register-pairing.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=arm64-apple-ios < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck -check-prefix CHECK-NOTMACHO %s ; ; rdar://14075006 @@ -13,7 +14,7 @@ define void @odd() nounwind { ; CHECK: stp x24, x23, [sp, #96] ; CHECK: stp x22, x21, [sp, #112] ; CHECK: stp x20, x19, [sp, #128] -; CHECK: movz x0, #0x2a +; CHECK: mov x0, #42 ; CHECK: ldp x20, x19, [sp, #128] ; CHECK: ldp x22, x21, [sp, #112] ; CHECK: ldp x24, x23, [sp, #96] @@ -23,6 +24,19 @@ define void @odd() nounwind { ; CHECK: ldp d11, d10, [sp, #32] ; CHECK: ldp d13, d12, [sp, #16] ; CHECK: ldp d15, d14, [sp], #144 + +; CHECK-NOTMACHO-LABEL: odd: +; CHECK-NOTMACHO: stp d14, d12, [sp, #-80]! +; CHECK-NOTMACHO: stp d10, d8, [sp, #16] +; CHECK-NOTMACHO: str x27, [sp, #32] +; CHECK-NOTMACHO: stp x25, x23, [sp, #48] +; CHECK-NOTMACHO: stp x21, x19, [sp, #64] +; CHECK-NOTMACHO: mov x0, #42 +; CHECK-NOTMACHO: ldp x21, x19, [sp, #64] +; CHECK-NOTMACHO: ldp x25, x23, [sp, #48] +; CHECK-NOTMACHO: ldr x27, [sp, #32] +; CHECK-NOTMACHO: ldp d10, d8, [sp, #16] +; CHECK-NOTMACHO: ldp d14, d12, [sp], #80 call void asm sideeffect "mov x0, #42", "~{x0},~{x19},~{x21},~{x23},~{x25},~{x27},~{d8},~{d10},~{d12},~{d14}"() nounwind ret void } @@ -38,7 +52,7 @@ define void @even() nounwind { ; CHECK: stp x24, x23, [sp, #96] ; CHECK: stp x22, x21, [sp, #112] ; CHECK: stp x20, x19, [sp, #128] -; CHECK: movz x0, #0x2a +; CHECK: mov x0, #42 ; CHECK: ldp x20, x19, [sp, #128] ; CHECK: ldp x22, x21, [sp, #112] ; CHECK: ldp x24, x23, [sp, #96] @@ -48,6 +62,19 @@ define void @even() nounwind { ; CHECK: ldp d11, d10, [sp, #32] ; CHECK: ldp d13, d12, [sp, #16] ; CHECK: ldp d15, d14, [sp], #144 + +; CHECK-NOTMACHO-LABEL: even: +; CHECK-NOTMACHO: stp d15, d13, [sp, #-80]! +; CHECK-NOTMACHO: stp d11, d9, [sp, #16] +; CHECK-NOTMACHO: str x28, [sp, #32] +; CHECK-NOTMACHO: stp x26, x24, [sp, #48] +; CHECK-NOTMACHO: stp x22, x20, [sp, #64] +; CHECK-NOTMACHO: mov x0, #42 +; CHECK-NOTMACHO: ldp x22, x20, [sp, #64] +; CHECK-NOTMACHO: ldp x26, x24, [sp, #48] +; CHECK-NOTMACHO: ldr x28, [sp, #32] +; CHECK-NOTMACHO: ldp d11, d9, [sp, #16] +; CHECK-NOTMACHO: ldp d15, d13, [sp], #80 call void asm sideeffect "mov x0, #42", "~{x0},~{x20},~{x22},~{x24},~{x26},~{x28},~{d9},~{d11},~{d13},~{d15}"() nounwind ret void } diff --git a/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir new file mode 100644 index 000000000000..3948c0457bcd --- /dev/null +++ b/test/CodeGen/AArch64/arm64-regress-opt-cmp.mir @@ -0,0 +1,42 @@ +# RUN: rm -f %S/arm64-regress-opt-cmp.s +# RUN: llc -mtriple=aarch64-linux-gnu -run-pass peephole-opt -o - %s 2>&1 | FileCheck %s +# CHECK: %1 = ANDWri {{.*}} +# CHECK-NEXT: %wzr = SUBSWri {{.*}} +--- | + define i32 @test01() nounwind { + entry: + %0 = select i1 true, i32 1, i32 0 + %1 = and i32 %0, 65535 + %2 = icmp ugt i32 %1, 0 + br i1 %2, label %if.then, label %if.end + + if.then: ; preds = %entry + ret i32 1 + + if.end: ; preds = %entry + ret i32 0 + } +... +--- +name: test01 +registers: + - { id: 0, class: gpr32 } + - { id: 1, class: gpr32common } +body: | + bb.0.entry: + successors: %bb.2.if.end, %bb.1.if.then + + %0 = MOVi32imm 1 + %1 = ANDWri killed %1, 15 + %wzr = SUBSWri killed %1, 0, 0, implicit-def %nzcv + Bcc 9, %bb.2.if.end, implicit %nzcv + + bb.1.if.then: + %w0 = MOVi32imm 1 + RET_ReallyLR implicit %w0 + + bb.2.if.end: + %w0 = MOVi32imm 0 + RET_ReallyLR implicit %w0 + +... diff --git a/test/CodeGen/AArch64/arm64-rev.ll b/test/CodeGen/AArch64/arm64-rev.ll index 74356d76d3c8..4980d7e3b275 100644 --- a/test/CodeGen/AArch64/arm64-rev.ll +++ b/test/CodeGen/AArch64/arm64-rev.ll @@ -16,6 +16,33 @@ entry: ret i64 %0 } +; Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high 16-bits +; of %a are zero. This optimizes rev + lsr 16 to rev16. +define i32 @test_rev_w_srl16(i16 %a) { +entry: +; CHECK-LABEL: test_rev_w_srl16: +; CHECK: and [[REG:w[0-9]+]], w0, #0xffff +; CHECK: rev16 w0, [[REG]] +; CHECK-NOT: lsr + %0 = zext i16 %a to i32 + %1 = tail call i32 @llvm.bswap.i32(i32 %0) + %2 = lshr i32 %1, 16 + ret i32 %2 +} + +; Canonicalize (srl (bswap x), 32) to (rotr (bswap x), 32) if the high 32-bits +; of %a are zero. This optimizes rev + lsr 32 to rev32. +define i64 @test_rev_x_srl32(i32 %a) { +entry: +; CHECK-LABEL: test_rev_x_srl32: +; CHECK: rev32 x0, {{x[0-9]+}} +; CHECK-NOT: lsr + %0 = zext i32 %a to i64 + %1 = tail call i64 @llvm.bswap.i64(i64 %0) + %2 = lshr i64 %1, 32 + ret i64 %2 +} + declare i32 @llvm.bswap.i32(i32) nounwind readnone declare i64 @llvm.bswap.i64(i64) nounwind readnone diff --git a/test/CodeGen/AArch64/arm64-shrink-wrapping.ll b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll index 4d751f501d4a..16ae7ef8e1b7 100644 --- a/test/CodeGen/AArch64/arm64-shrink-wrapping.ll +++ b/test/CodeGen/AArch64/arm64-shrink-wrapping.ll @@ -1,5 +1,5 @@ -; RUN: llc %s -o - -enable-shrink-wrap=true -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE -; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE +; RUN: llc %s -o - -enable-shrink-wrap=true -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE +; RUN: llc %s -o - -enable-shrink-wrap=false -disable-post-ra -disable-fp-elim | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" target triple = "arm64-apple-ios" @@ -13,9 +13,9 @@ target triple = "arm64-apple-ios" ; ENABLE-NEXT: b.ge [[EXIT_LABEL:LBB[0-9_]+]] ; ; Prologue code. -; CHECK: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]], [sp, #-16]! -; CHECK-NEXT: mov [[SAVE_SP]], sp -; CHECK-NEXT: sub sp, sp, #16 +; CHECK: sub sp, sp, #32 +; CHECK-NEXT: stp [[SAVE_SP:x[0-9]+]], [[CSR:x[0-9]+]], [sp, #16] +; CHECK-NEXT: add [[SAVE_SP]], sp, #16 ; ; Compare the arguments and jump to exit. ; After the prologue is set. @@ -29,12 +29,12 @@ target triple = "arm64-apple-ios" ; Set the first argument to zero. ; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: bl _doSomething -; +; ; Without shrink-wrapping, epilogue is in the exit block. ; DISABLE: [[EXIT_LABEL]]: ; Epilogue code. -; CHECK-NEXT: mov sp, [[SAVE_SP]] -; CHECK-NEXT: ldp [[SAVE_SP]], [[CSR]], [sp], #16 +; CHECK-NEXT: ldp x{{[0-9]+}}, [[CSR]], [sp, #16] +; CHECK-NEXT: add sp, sp, #32 ; ; With shrink-wrapping, exit block is a simple return. ; ENABLE: [[EXIT_LABEL]]: @@ -73,7 +73,7 @@ declare i32 @doSomething(i32, i32*) ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; ; CHECK: mov [[SUM:w[0-9]+]], wzr -; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa +; CHECK-NEXT: mov [[IV:w[0-9]+]], #10 ; ; Next BB. ; CHECK: [[LOOP:LBB[0-9_]+]]: ; %for.body @@ -140,7 +140,7 @@ declare i32 @something(...) ; CHECK-NEXT: stp [[CSR3:x[0-9]+]], [[CSR4:x[0-9]+]], [sp, #16] ; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #16 ; CHECK: mov [[SUM:w[0-9]+]], wzr -; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa +; CHECK-NEXT: mov [[IV:w[0-9]+]], #10 ; Next BB. ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body ; CHECK: bl _something @@ -184,7 +184,7 @@ for.end: ; preds = %for.body ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; ; CHECK: mov [[SUM:w[0-9]+]], wzr -; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa +; CHECK-NEXT: mov [[IV:w[0-9]+]], #10 ; ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body ; CHECK: bl _something @@ -255,7 +255,7 @@ declare void @somethingElse(...) ; ; CHECK: bl _somethingElse ; CHECK-NEXT: mov [[SUM:w[0-9]+]], wzr -; CHECK-NEXT: movz [[IV:w[0-9]+]], #0xa +; CHECK-NEXT: mov [[IV:w[0-9]+]], #10 ; ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body ; CHECK: bl _something @@ -332,11 +332,11 @@ entry: ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; ; Sum is merged with the returned register. -; CHECK: mov [[SUM:w0]], wzr -; CHECK-NEXT: add [[VA_BASE:x[0-9]+]], sp, #16 +; CHECK: add [[VA_BASE:x[0-9]+]], sp, #16 ; CHECK-NEXT: str [[VA_BASE]], [sp, #8] ; CHECK-NEXT: cmp w1, #1 ; CHECK-NEXT: b.lt [[IFEND_LABEL:LBB[0-9_]+]] +; CHECK: mov [[SUM:w0]], wzr ; ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body ; CHECK: ldr [[VA_ADDR:x[0-9]+]], [sp, #8] @@ -347,18 +347,18 @@ entry: ; CHECK-NEXT: sub w1, w1, #1 ; CHECK-NEXT: cbnz w1, [[LOOP_LABEL]] ; -; DISABLE-NEXT: b [[IFEND_LABEL]] +; DISABLE-NEXT: b ; DISABLE: [[ELSE_LABEL]]: ; %if.else ; DISABLE: lsl w0, w1, #1 ; +; ENABLE: [[ELSE_LABEL]]: ; %if.else +; ENABLE: lsl w0, w1, #1 +; ENABLE-NEXT: ret +; ; CHECK: [[IFEND_LABEL]]: ; Epilogue code. ; CHECK: add sp, sp, #16 ; CHECK-NEXT: ret -; -; ENABLE: [[ELSE_LABEL]]: ; %if.else -; ENABLE: lsl w0, w1, #1 -; ENABLE-NEXT: ret define i32 @variadicFunc(i32 %cond, i32 %count, ...) #0 { entry: %ap = alloca i8*, align 8 @@ -409,7 +409,7 @@ declare void @llvm.va_end(i8*) ; ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; -; CHECK: movz [[IV:w[0-9]+]], #0xa +; CHECK: mov [[IV:w[0-9]+]], #10 ; ; CHECK: [[LOOP_LABEL:LBB[0-9_]+]]: ; %for.body ; Inline asm statement. @@ -454,9 +454,9 @@ if.end: ; preds = %for.body, %if.else ; ENABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; ; Prologue code. -; CHECK: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #-16]! -; CHECK-NEXT: mov [[NEW_SP:x[0-9]+]], sp -; CHECK-NEXT: sub sp, sp, #48 +; CHECK: sub sp, sp, #64 +; CHECK-NEXT: stp [[CSR1:x[0-9]+]], [[CSR2:x[0-9]+]], [sp, #48] +; CHECK-NEXT: add [[NEW_SP:x[0-9]+]], sp, #48 ; ; DISABLE: cbz w0, [[ELSE_LABEL:LBB[0-9_]+]] ; Setup of the varags. @@ -473,8 +473,8 @@ if.end: ; preds = %for.body, %if.else ; DISABLE: [[IFEND_LABEL]]: ; %if.end ; ; Epilogue code. -; CHECK: mov sp, [[NEW_SP]] -; CHECK-NEXT: ldp [[CSR1]], [[CSR2]], [sp], #16 +; CHECK: ldp [[CSR1]], [[CSR2]], [sp, #48] +; CHECK-NEXT: add sp, sp, #64 ; CHECK-NEXT: ret ; ; ENABLE: [[ELSE_LABEL]]: ; %if.else @@ -511,7 +511,7 @@ declare i32 @someVariadicFunc(i32, ...) ; CHECK: and [[TEST:w[0-9]+]], w0, #0xff ; CHECK-NEXT: cbnz [[TEST]], [[ABORT:LBB[0-9_]+]] ; -; CHECK: movz w0, #0x2a +; CHECK: mov w0, #42 ; ; DISABLE-NEXT: ldp ; @@ -631,16 +631,20 @@ end: ret void } -; Don't do shrink-wrapping when we need to re-align the stack pointer. -; See bug 26642. +; Re-aligned stack pointer. See bug 26642. Avoid clobbering live +; values in the prologue when re-aligning the stack pointer. ; CHECK-LABEL: stack_realign: -; CHECK-NOT: lsl w[[LSL1:[0-9]+]], w0, w1 -; CHECK-NOT: lsl w[[LSL2:[0-9]+]], w1, w0 +; ENABLE-DAG: lsl w[[LSL1:[0-9]+]], w0, w1 +; ENABLE-DAG: lsl w[[LSL2:[0-9]+]], w1, w0 +; DISABLE-NOT: lsl w[[LSL1:[0-9]+]], w0, w1 +; DISABLE-NOT: lsl w[[LSL2:[0-9]+]], w1, w0 ; CHECK: stp x29, x30, [sp, #-16]! ; CHECK: mov x29, sp -; CHECK: sub x{{[0-9]+}}, sp, #16 -; CHECK-DAG: lsl w[[LSL1:[0-9]+]], w0, w1 -; CHECK-DAG: lsl w[[LSL2:[0-9]+]], w1, w0 +; ENABLE-NOT: sub x[[LSL1]], sp, #16 +; ENABLE-NOT: sub x[[LSL2]], sp, #16 +; DISABLE: sub x{{[0-9]+}}, sp, #16 +; DISABLE-DAG: lsl w[[LSL1:[0-9]+]], w0, w1 +; DISABLE-DAG: lsl w[[LSL2:[0-9]+]], w1, w0 ; CHECK-DAG: str w[[LSL1]], ; CHECK-DAG: str w[[LSL2]], diff --git a/test/CodeGen/AArch64/arm64-stp-aa.ll b/test/CodeGen/AArch64/arm64-stp-aa.ll index 82d343d976b5..2a45745fedb5 100644 --- a/test/CodeGen/AArch64/arm64-stp-aa.ll +++ b/test/CodeGen/AArch64/arm64-stp-aa.ll @@ -109,3 +109,37 @@ define double @stp_double_aa_after(double %d0, double %a, double %b, double* noc store double %b, double* %add.ptr, align 8 ret double %tmp } + +; Check that the stores %c and %d are paired after the fadd instruction, +; and then the stores %a and %d are paired after proving that they do not +; depend on the the (%c, %d) pair. +; +; CHECK-LABEL: st1: +; CHECK: stp q0, q1, [x{{[0-9]+}}] +; CHECK: fadd +; CHECK: stp q2, q0, [x{{[0-9]+}}, #32] +define void @st1(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* %base, i64 %index) { +entry: + %a0 = getelementptr inbounds float, float* %base, i64 %index + %b0 = getelementptr float, float* %a0, i64 4 + %c0 = getelementptr float, float* %a0, i64 8 + %d0 = getelementptr float, float* %a0, i64 12 + + %a1 = bitcast float* %a0 to <4 x float>* + %b1 = bitcast float* %b0 to <4 x float>* + %c1 = bitcast float* %c0 to <4 x float>* + %d1 = bitcast float* %d0 to <4 x float>* + + store <4 x float> %c, <4 x float> * %c1, align 4 + store <4 x float> %a, <4 x float> * %a1, align 4 + + ; This fadd forces the compiler to pair %c and %e after fadd, and leave the + ; stores %a and %b separated by a stp. The dependence analysis needs then to + ; prove that it is safe to move %b past the stp to be paired with %a. + %e = fadd fast <4 x float> %d, %a + + store <4 x float> %e, <4 x float>* %d1, align 4 + store <4 x float> %b, <4 x float>* %b1, align 4 + + ret void +} diff --git a/test/CodeGen/AArch64/arm64-stp.ll b/test/CodeGen/AArch64/arm64-stp.ll index 98242d0bb57e..5664c7d118c3 100644 --- a/test/CodeGen/AArch64/arm64-stp.ll +++ b/test/CodeGen/AArch64/arm64-stp.ll @@ -100,9 +100,9 @@ entry: ; Read of %b to compute %tmp2 shouldn't prevent formation of stp ; CHECK-LABEL: stp_int_rar_hazard -; CHECK: stp w0, w1, [x2] ; CHECK: ldr [[REG:w[0-9]+]], [x2, #8] -; CHECK: add w0, [[REG]], w1 +; CHECK: add w8, [[REG]], w1 +; CHECK: stp w0, w1, [x2] ; CHECK: ret define i32 @stp_int_rar_hazard(i32 %a, i32 %b, i32* nocapture %p) nounwind { store i32 %a, i32* %p, align 4 diff --git a/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll b/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll index 4ab2bee0ed16..2eedde557644 100644 --- a/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll +++ b/test/CodeGen/AArch64/arm64-swizzle-tbl-i16-layout.ll @@ -4,7 +4,7 @@ ; getting both the endianness wrong and the element indexing wrong. define <8 x i16> @foo(<8 x i16> %a) nounwind readnone { ; CHECK: .section __TEXT,__literal16,16byte_literals -; CHECK: .align 4 +; CHECK: .p2align 4 ; CHECK:lCPI0_0: ; CHECK: .byte 0 ; 0x0 ; CHECK: .byte 1 ; 0x1 @@ -24,7 +24,7 @@ define <8 x i16> @foo(<8 x i16> %a) nounwind readnone { ; CHECK: .byte 9 ; 0x9 ; CHECK: .section __TEXT,__text,regular,pure_instructions ; CHECK: .globl _foo -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK:_foo: ; @foo ; CHECK: adrp [[BASE:x[0-9]+]], lCPI0_0@PAGE ; CHECK: ldr q[[REG:[0-9]+]], {{\[}}[[BASE]], lCPI0_0@PAGEOFF] diff --git a/test/CodeGen/AArch64/arm64-this-return.ll b/test/CodeGen/AArch64/arm64-this-return.ll index 3be1a69237d7..9fc68f476b77 100644 --- a/test/CodeGen/AArch64/arm64-this-return.ll +++ b/test/CodeGen/AArch64/arm64-this-return.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm64 | FileCheck %s +; RUN: llc < %s -march=arm64 -aarch64-this-return-forwarding | FileCheck %s %struct.A = type { i8 } %struct.B = type { i32 } diff --git a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll index c95eca062ff6..bb9ad46ba63d 100644 --- a/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll +++ b/test/CodeGen/AArch64/arm64-tls-dynamic-together.ll @@ -40,7 +40,7 @@ define i32 @test_emulated_init() { ; EMU-NOT: __emutls_v.general_dynamic_var: -; EMU: .align 3 +; EMU: .p2align 3 ; EMU-LABEL: __emutls_v.emulated_init_var: ; EMU-NEXT: .xword 4 ; EMU-NEXT: .xword 8 diff --git a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll index 8702b41023d0..16ddf690fe95 100644 --- a/test/CodeGen/AArch64/arm64-variadic-aapcs.ll +++ b/test/CodeGen/AArch64/arm64-variadic-aapcs.ll @@ -32,7 +32,7 @@ define void @test_simple(i32 %n, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #128 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x37 +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-56 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] ; CHECK: orr [[VR_OFFS:w[0-9]+]], wzr, #0xffffff80 @@ -70,10 +70,10 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) { ; CHECK: add [[VR_TOP:x[0-9]+]], [[VR_TOPTMP]], #112 ; CHECK: str [[VR_TOP]], [x[[VA_LIST]], #16] -; CHECK: movn [[GR_OFFS:w[0-9]+]], #0x27 +; CHECK: mov [[GR_OFFS:w[0-9]+]], #-40 ; CHECK: str [[GR_OFFS]], [x[[VA_LIST]], #24] -; CHECK: movn [[VR_OFFS:w[0-9]+]], #0x6f +; CHECK: mov [[VR_OFFS:w[0-9]+]], #-11 ; CHECK: str [[VR_OFFS]], [x[[VA_LIST]], #28] %addr = bitcast %va_list* @var to i8* diff --git a/test/CodeGen/AArch64/arm64-vclz.ll b/test/CodeGen/AArch64/arm64-vclz.ll index cf5670a0354f..10118f0d5638 100644 --- a/test/CodeGen/AArch64/arm64-vclz.ll +++ b/test/CodeGen/AArch64/arm64-vclz.ll @@ -48,6 +48,18 @@ define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp { ret <2 x i32> %vclz1.i } +define <1 x i64> @test_vclz_u64(<1 x i64> %a) nounwind readnone ssp { + ; CHECK-LABEL: test_vclz_u64: + %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind + ret <1 x i64> %vclz1.i +} + +define <1 x i64> @test_vclz_s64(<1 x i64> %a) nounwind readnone ssp { + ; CHECK-LABEL: test_vclz_s64: + %vclz1.i = tail call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %a, i1 false) nounwind + ret <1 x i64> %vclz1.i +} + define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp { ; CHECK-LABEL: test_vclzq_u8: ; CHECK: clz.16b v0, v0 @@ -96,12 +108,28 @@ define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp { ret <4 x i32> %vclz1.i } +define <2 x i64> @test_vclzq_u64(<2 x i64> %a) nounwind readnone ssp { + ; CHECK-LABEL: test_vclzq_u64: + %vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind + ret <2 x i64> %vclz1.i +} + +define <2 x i64> @test_vclzq_s64(<2 x i64> %a) nounwind readnone ssp { + ; CHECK-LABEL: test_vclzq_s64: + %vclz1.i = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) nounwind + ret <2 x i64> %vclz1.i +} + +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone + declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone +declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone + declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone diff --git a/test/CodeGen/AArch64/arm64-vecCmpBr.ll b/test/CodeGen/AArch64/arm64-vecCmpBr.ll index c7321e4b7d07..0c496fedfc2a 100644 --- a/test/CodeGen/AArch64/arm64-vecCmpBr.ll +++ b/test/CodeGen/AArch64/arm64-vecCmpBr.ll @@ -59,7 +59,7 @@ define i32 @anyNonZero64(<4 x i16> %a) #0 { ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] ; CHECK: [[LABEL]]: -; CHECK-NEXT: movz w0, #0 +; CHECK-NEXT: mov w0, #0 entry: %0 = bitcast <4 x i16> %a to <8 x i8> @@ -83,7 +83,7 @@ define i32 @anyNonZero128(<8 x i16> %a) #0 { ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] ; CHECK: [[LABEL]]: -; CHECK-NEXT: movz w0, #0 +; CHECK-NEXT: mov w0, #0 entry: %0 = bitcast <8 x i16> %a to <16 x i8> %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %0) #3 @@ -152,7 +152,7 @@ define i32 @allNonZero64(<4 x i16> %a) #0 { ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] ; CHECK: [[LABEL]]: -; CHECK-NEXT: movz w0, #0 +; CHECK-NEXT: mov w0, #0 entry: %0 = bitcast <4 x i16> %a to <8 x i8> %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3 @@ -175,7 +175,7 @@ define i32 @allNonZero128(<8 x i16> %a) #0 { ; CHECK-NEXT: fmov w[[REGNO2:[0-9]+]], s[[REGNO1]] ; CHECK-NEXT: cbz w[[REGNO2]], [[LABEL:[A-Z_0-9]+]] ; CHECK: [[LABEL]]: -; CHECK-NEXT: movz w0, #0 +; CHECK-NEXT: mov w0, #0 entry: %0 = bitcast <8 x i16> %a to <16 x i8> %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3 diff --git a/test/CodeGen/AArch64/arm64-vector-ext.ll b/test/CodeGen/AArch64/arm64-vector-ext.ll index 921cf6a6f0d1..241c3dcb9825 100644 --- a/test/CodeGen/AArch64/arm64-vector-ext.ll +++ b/test/CodeGen/AArch64/arm64-vector-ext.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s ;CHECK: @func30 -;CHECK: movi.4h v1, #0x1 +;CHECK: movi.4h v1, #1 ;CHECK: and.8b v0, v0, v1 ;CHECK: ushll.4s v0, v0, #0 ;CHECK: str q0, [x0] diff --git a/test/CodeGen/AArch64/arm64-vector-imm.ll b/test/CodeGen/AArch64/arm64-vector-imm.ll index d3de88d2049d..aa3ffd261d4b 100644 --- a/test/CodeGen/AArch64/arm64-vector-imm.ll +++ b/test/CodeGen/AArch64/arm64-vector-imm.ll @@ -50,35 +50,35 @@ define <2 x double> @foo(<2 x double> %bar) nounwind { define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t1: -; CHECK: movi.4s v0, #0x4b +; CHECK: movi.4s v0, #75 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t2: -; CHECK: movi.4s v0, #0x4b, lsl #8 +; CHECK: movi.4s v0, #75, lsl #8 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t3: -; CHECK: movi.4s v0, #0x4b, lsl #16 +; CHECK: movi.4s v0, #75, lsl #16 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t4: -; CHECK: movi.4s v0, #0x4b, lsl #24 +; CHECK: movi.4s v0, #75, lsl #24 ret <4 x i32> } define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_8h_imm_t5: -; CHECK: movi.8h v0, #0x4b +; CHECK: movi.8h v0, #75 ret <8 x i16> } @@ -86,28 +86,28 @@ entry: define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_8h_imm_t6: -; CHECK: movi.8h v0, #0x4b, lsl #8 +; CHECK: movi.8h v0, #75, lsl #8 ret <8 x i16> } define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t7: -; CHECK: movi.4s v0, #0x4b, msl #8 +; CHECK: movi.4s v0, #75, msl #8 ret <4 x i32> } define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_4s_imm_t8: -; CHECK: movi.4s v0, #0x4b, msl #16 +; CHECK: movi.4s v0, #75, msl #16 ret <4 x i32> } define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp { entry: ; CHECK-LABEL: movi_16b_imm_t9: -; CHECK: movi.16b v0, #0x4b +; CHECK: movi.16b v0, #75 ret <16 x i8> } diff --git a/test/CodeGen/AArch64/arm64-virtual_base.ll b/test/CodeGen/AArch64/arm64-virtual_base.ll index 703d81a8d4fe..4ecfde4f83e2 100644 --- a/test/CodeGen/AArch64/arm64-virtual_base.ll +++ b/test/CodeGen/AArch64/arm64-virtual_base.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O3 -march arm64 | FileCheck %s +; RUN: llc < %s -O3 -mtriple=arm64-apple-ios -disable-post-ra | FileCheck %s ; %struct.Counter_Struct = type { i64, i64 } diff --git a/test/CodeGen/AArch64/arm64-vshift.ll b/test/CodeGen/AArch64/arm64-vshift.ll index d5a12483db40..b5a6788979e2 100644 --- a/test/CodeGen/AArch64/arm64-vshift.ll +++ b/test/CodeGen/AArch64/arm64-vshift.ll @@ -1315,7 +1315,7 @@ define <8 x i8> @uqshli8b(<8 x i8>* %A) nounwind { define <8 x i8> @uqshli8b_1(<8 x i8>* %A) nounwind { ;CHECK-LABEL: uqshli8b_1: -;CHECK: movi.8b [[REG:v[0-9]+]], #0x8 +;CHECK: movi.8b [[REG:v[0-9]+]], #8 ;CHECK: uqshl.8b v0, v0, [[REG]] %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> ) diff --git a/test/CodeGen/AArch64/arm64-vshuffle.ll b/test/CodeGen/AArch64/arm64-vshuffle.ll index 15ea21b7638d..b4f57675ace3 100644 --- a/test/CodeGen/AArch64/arm64-vshuffle.ll +++ b/test/CodeGen/AArch64/arm64-vshuffle.ll @@ -36,7 +36,7 @@ bb: } ; CHECK: test3 -; CHECK: movi.4s v{{[0-9]+}}, #0x1 +; CHECK: movi.4s v{{[0-9]+}}, #1 define <16 x i1> @test3(i1* %ptr, i32 %v) { bb: %Shuff = shufflevector <16 x i1> , <16 x i1> undef, diff --git a/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll b/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll index 349bb6fd78af..ae77f7e099db 100644 --- a/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll +++ b/test/CodeGen/AArch64/arm64-zero-cycle-zeroing.ll @@ -1,44 +1,52 @@ -; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s +; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s -check-prefix=CYCLONE --check-prefix=ALL +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo < %s | FileCheck %s -check-prefix=KRYO --check-prefix=ALL + ; rdar://11481771 ; rdar://13713797 define void @t1() nounwind ssp { entry: -; CHECK-LABEL: t1: -; CHECK-NOT: fmov -; CHECK: movi.2d v0, #0000000000000000 -; CHECK: movi.2d v1, #0000000000000000 -; CHECK: movi.2d v2, #0000000000000000 -; CHECK: movi.2d v3, #0000000000000000 +; ALL-LABEL: t1: +; ALL-NOT: fmov +; CYCLONE: movi.2d v0, #0000000000000000 +; CYCLONE: movi.2d v1, #0000000000000000 +; CYCLONE: movi.2d v2, #0000000000000000 +; CYCLONE: movi.2d v3, #0000000000000000 +; KRYO: movi v0.2d, #0000000000000000 +; KRYO: movi v1.2d, #0000000000000000 +; KRYO: movi v2.2d, #0000000000000000 +; KRYO: movi v3.2d, #0000000000000000 tail call void @bar(double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00) nounwind ret void } define void @t2() nounwind ssp { entry: -; CHECK-LABEL: t2: -; CHECK-NOT: mov w0, wzr -; CHECK: movz w0, #0 -; CHECK: movz w1, #0 +; ALL-LABEL: t2: +; ALL-NOT: mov w0, wzr +; ALL: mov w0, #0 +; ALL: mov w1, #0 tail call void @bari(i32 0, i32 0) nounwind ret void } define void @t3() nounwind ssp { entry: -; CHECK-LABEL: t3: -; CHECK-NOT: mov x0, xzr -; CHECK: movz x0, #0 -; CHECK: movz x1, #0 +; ALL-LABEL: t3: +; ALL-NOT: mov x0, xzr +; ALL: mov x0, #0 +; ALL: mov x1, #0 tail call void @barl(i64 0, i64 0) nounwind ret void } define void @t4() nounwind ssp { -; CHECK-LABEL: t4: -; CHECK-NOT: fmov -; CHECK: movi.2d v0, #0000000000000000 -; CHECK: movi.2d v1, #0000000000000000 +; ALL-LABEL: t4: +; ALL-NOT: fmov +; CYCLONE: movi.2d v0, #0000000000000000 +; CYCLONE: movi.2d v1, #0000000000000000 +; KRYO: movi v0.2d, #0000000000000000 +; KRYO: movi v1.2d, #0000000000000000 tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind ret void } @@ -47,3 +55,29 @@ declare void @bar(double, double, double, double) declare void @bari(i32, i32) declare void @barl(i64, i64) declare void @barf(float, float) + +; We used to produce spills+reloads for a Q register with zero cycle zeroing +; enabled. +; ALL-LABEL: foo: +; ALL-NOT: str {{q[0-9]+}} +; ALL-NOT: ldr {{q[0-9]+}} +define double @foo(i32 %n) { +entry: + br label %for.body + +for.body: + %phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ] + %i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %conv21 = sitofp i32 %i.076 to double + %call = tail call fast double @sin(double %conv21) + %cmp.i = fcmp fast olt double %phi0, %call + %v0 = select i1 %cmp.i, double %call, double %phi0 + %inc = add nuw nsw i32 %i.076, 1 + %cmp = icmp slt i32 %inc, %n + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret double %v0 +} + +declare double @sin(double) diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index 900d2072925f..9fac8d8a868a 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG diff --git a/test/CodeGen/AArch64/bitfield-extract.ll b/test/CodeGen/AArch64/bitfield-extract.ll new file mode 100644 index 000000000000..5e727b669e22 --- /dev/null +++ b/test/CodeGen/AArch64/bitfield-extract.ll @@ -0,0 +1,98 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; CHECK-LABEL: @test1 +; CHECK: sbfx {{x[0-9]+}}, x0, #23, #9 +define i64 @test1(i32 %a) { + %tmp = ashr i32 %a, 23 + %ext = sext i32 %tmp to i64 + %res = add i64 %ext, 1 + ret i64 %res +} + +; CHECK-LABEL: @test2 +; CHECK: sbfx w0, w0, #23, #8 +define signext i8 @test2(i32 %a) { + %tmp = ashr i32 %a, 23 + %res = trunc i32 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test3 +; CHECK: sbfx w0, w0, #23, #8 +define signext i8 @test3(i32 %a) { + %tmp = lshr i32 %a, 23 + %res = trunc i32 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test4 +; CHECK: sbfx w0, w0, #15, #16 +define signext i16 @test4(i32 %a) { + %tmp = lshr i32 %a, 15 + %res = trunc i32 %tmp to i16 + ret i16 %res +} + +; CHECK-LABEL: @test5 +; CHECK: sbfx w0, w0, #16, #8 +define signext i8 @test5(i64 %a) { + %tmp = lshr i64 %a, 16 + %res = trunc i64 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test6 +; CHECK: sbfx x0, x0, #30, #8 +define signext i8 @test6(i64 %a) { + %tmp = lshr i64 %a, 30 + %res = trunc i64 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test7 +; CHECK: sbfx x0, x0, #23, #16 +define signext i16 @test7(i64 %a) { + %tmp = lshr i64 %a, 23 + %res = trunc i64 %tmp to i16 + ret i16 %res +} + +; CHECK-LABEL: @test8 +; CHECK: asr w0, w0, #25 +define signext i8 @test8(i32 %a) { + %tmp = ashr i32 %a, 25 + %res = trunc i32 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test9 +; CHECK: lsr w0, w0, #25 +define signext i8 @test9(i32 %a) { + %tmp = lshr i32 %a, 25 + %res = trunc i32 %tmp to i8 + ret i8 %res +} + +; CHECK-LABEL: @test10 +; CHECK: lsr x0, x0, #49 +define signext i16 @test10(i64 %a) { + %tmp = lshr i64 %a, 49 + %res = trunc i64 %tmp to i16 + ret i16 %res +} + +; SHR with multiple uses is fine as SXTH and SBFX are both aliases of SBFM. +; However, allowing the transformation means the SHR and SBFX can execute in +; parallel. +; +; CHECK-LABEL: @test11 +; CHECK: lsr x1, x0, #23 +; CHECK: sbfx x0, x0, #23, #16 +define void @test11(i64 %a) { + %tmp = lshr i64 %a, 23 + %res = trunc i64 %tmp to i16 + call void @use(i16 %res, i64 %tmp) + ret void +} + +declare void @use(i16 signext, i64) diff --git a/test/CodeGen/AArch64/bitfield-insert.ll b/test/CodeGen/AArch64/bitfield-insert.ll index 509b547a5c82..735be244d457 100644 --- a/test/CodeGen/AArch64/bitfield-insert.ll +++ b/test/CodeGen/AArch64/bitfield-insert.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s ; First, a simple example from Clang. The registers could plausibly be ; different, but probably won't be. @@ -237,3 +237,246 @@ define i32 @test_nouseful_bits(i8 %a, i32 %b) { %shl.4 = shl i32 %or.3, 8 ; A A A 0 ret i32 %shl.4 } + +define void @test_nouseful_strb(i32* %ptr32, i8* %ptr8, i32 %x) { +entry: +; CHECK-LABEL: @test_nouseful_strb +; CHECK: ldr [[REG1:w[0-9]+]], +; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8 +; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3 +; CHECK-NEXT: strb [[REG1]], +; CHECK-NEXT: ret + %0 = load i32, i32* %ptr32, align 8 + %and = and i32 %0, -8 + %shr = lshr i32 %x, 16 + %and1 = and i32 %shr, 7 + %or = or i32 %and, %and1 + %trunc = trunc i32 %or to i8 + store i8 %trunc, i8* %ptr8 + ret void +} + +define void @test_nouseful_strh(i32* %ptr32, i16* %ptr16, i32 %x) { +entry: +; CHECK-LABEL: @test_nouseful_strh +; CHECK: ldr [[REG1:w[0-9]+]], +; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0 +; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4 +; CHECK-NEXT: strh [[REG1]], +; CHECK-NEXT: ret + %0 = load i32, i32* %ptr32, align 8 + %and = and i32 %0, -16 + %shr = lshr i32 %x, 16 + %and1 = and i32 %shr, 15 + %or = or i32 %and, %and1 + %trunc = trunc i32 %or to i16 + store i16 %trunc, i16* %ptr16 + ret void +} + +define void @test_nouseful_sturb(i32* %ptr32, i8* %ptr8, i32 %x) { +entry: +; CHECK-LABEL: @test_nouseful_sturb +; CHECK: ldr [[REG1:w[0-9]+]], +; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xf8 +; CHECK-NEXT: bfxil [[REG1]], w2, #16, #3 +; CHECK-NEXT: sturb [[REG1]], +; CHECK-NEXT: ret + %0 = load i32, i32* %ptr32, align 8 + %and = and i32 %0, -8 + %shr = lshr i32 %x, 16 + %and1 = and i32 %shr, 7 + %or = or i32 %and, %and1 + %trunc = trunc i32 %or to i8 + %gep = getelementptr i8, i8* %ptr8, i64 -1 + store i8 %trunc, i8* %gep + ret void +} + +define void @test_nouseful_sturh(i32* %ptr32, i16* %ptr16, i32 %x) { +entry: +; CHECK-LABEL: @test_nouseful_sturh +; CHECK: ldr [[REG1:w[0-9]+]], +; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xfff0 +; CHECK-NEXT: bfxil [[REG1]], w2, #16, #4 +; CHECK-NEXT: sturh [[REG1]], +; CHECK-NEXT: ret + %0 = load i32, i32* %ptr32, align 8 + %and = and i32 %0, -16 + %shr = lshr i32 %x, 16 + %and1 = and i32 %shr, 15 + %or = or i32 %and, %and1 + %trunc = trunc i32 %or to i16 + %gep = getelementptr i16, i16* %ptr16, i64 -1 + store i16 %trunc, i16* %gep + ret void +} + +; The next set of tests generate a BFXIL from 'or (and X, Mask0Imm), +; (and Y, Mask1Imm)' iff Mask0Imm and ~Mask1Imm are equivalent and one of the +; MaskImms is a shifted mask (e.g., 0x000ffff0). + +; CHECK-LABEL: @test_or_and_and1 +; CHECK: lsr w8, w1, #4 +; CHECK: bfi w0, w8, #4, #12 +define i32 @test_or_and_and1(i32 %a, i32 %b) { +entry: + %and = and i32 %a, -65521 ; 0xffff000f + %and1 = and i32 %b, 65520 ; 0x0000fff0 + %or = or i32 %and1, %and + ret i32 %or +} + +; CHECK-LABEL: @test_or_and_and2 +; CHECK: lsr w8, w0, #4 +; CHECK: bfi w1, w8, #4, #12 +define i32 @test_or_and_and2(i32 %a, i32 %b) { +entry: + %and = and i32 %a, 65520 ; 0x0000fff0 + %and1 = and i32 %b, -65521 ; 0xffff000f + %or = or i32 %and1, %and + ret i32 %or +} + +; CHECK-LABEL: @test_or_and_and3 +; CHECK: lsr x8, x1, #16 +; CHECK: bfi x0, x8, #16, #32 +define i64 @test_or_and_and3(i64 %a, i64 %b) { +entry: + %and = and i64 %a, -281474976645121 ; 0xffff00000000ffff + %and1 = and i64 %b, 281474976645120 ; 0x0000ffffffff0000 + %or = or i64 %and1, %and + ret i64 %or +} + +; Don't convert 'and' with multiple uses. +; CHECK-LABEL: @test_or_and_and4 +; CHECK: and w8, w0, #0xffff000f +; CHECK: and w9, w1, #0xfff0 +; CHECK: orr w0, w9, w8 +; CHECK: str w8, [x2 +define i32 @test_or_and_and4(i32 %a, i32 %b, i32* %ptr) { +entry: + %and = and i32 %a, -65521 + store i32 %and, i32* %ptr, align 4 + %and2 = and i32 %b, 65520 + %or = or i32 %and2, %and + ret i32 %or +} + +; Don't convert 'and' with multiple uses. +; CHECK-LABEL: @test_or_and_and5 +; CHECK: and w8, w1, #0xfff0 +; CHECK: and w9, w0, #0xffff000f +; CHECK: orr w0, w8, w9 +; CHECK: str w8, [x2] +define i32 @test_or_and_and5(i32 %a, i32 %b, i32* %ptr) { +entry: + %and = and i32 %b, 65520 + store i32 %and, i32* %ptr, align 4 + %and1 = and i32 %a, -65521 + %or = or i32 %and, %and1 + ret i32 %or +} + +; CHECK-LABEL: @test1 +; CHECK: mov [[REG:w[0-9]+]], #5 +; CHECK: bfxil w0, [[REG]], #0, #4 +define i32 @test1(i32 %a) { + %1 = and i32 %a, -16 ; 0xfffffff0 + %2 = or i32 %1, 5 ; 0x00000005 + ret i32 %2 +} + +; CHECK-LABEL: @test2 +; CHECK: mov [[REG:w[0-9]+]], #10 +; CHECK: bfi w0, [[REG]], #22, #4 +define i32 @test2(i32 %a) { + %1 = and i32 %a, -62914561 ; 0xfc3fffff + %2 = or i32 %1, 41943040 ; 0x06400000 + ret i32 %2 +} + +; CHECK-LABEL: @test3 +; CHECK: mov [[REG:x[0-9]+]], #5 +; CHECK: bfxil x0, [[REG]], #0, #3 +define i64 @test3(i64 %a) { + %1 = and i64 %a, -8 ; 0xfffffffffffffff8 + %2 = or i64 %1, 5 ; 0x0000000000000005 + ret i64 %2 +} + +; CHECK-LABEL: @test4 +; CHECK: mov [[REG:x[0-9]+]], #9 +; CHECK: bfi x0, [[REG]], #1, #7 +define i64 @test4(i64 %a) { + %1 = and i64 %a, -255 ; 0xffffffffffffff01 + %2 = or i64 %1, 18 ; 0x0000000000000012 + ret i64 %2 +} + +; Don't generate BFI/BFXIL if the immediate can be encoded in the ORR. +; CHECK-LABEL: @test5 +; CHECK: and [[REG:w[0-9]+]], w0, #0xfffffff0 +; CHECK: orr w0, [[REG]], #0x6 +define i32 @test5(i32 %a) { + %1 = and i32 %a, 4294967280 ; 0xfffffff0 + %2 = or i32 %1, 6 ; 0x00000006 + ret i32 %2 +} + +; BFXIL will use the same constant as the ORR, so we don't care how the constant +; is materialized (it's an equal cost either way). +; CHECK-LABEL: @test6 +; CHECK: mov [[REG:w[0-9]+]], #720896 +; CHECK: movk [[REG]], #23250 +; CHECK: bfxil w0, [[REG]], #0, #20 +define i32 @test6(i32 %a) { + %1 = and i32 %a, 4293918720 ; 0xfff00000 + %2 = or i32 %1, 744146 ; 0x000b5ad2 + ret i32 %2 +} + +; BFIs that require the same number of instruction to materialize the constant +; as the original ORR are okay. +; CHECK-LABEL: @test7 +; CHECK: mov [[REG:w[0-9]+]], #327680 +; CHECK: movk [[REG]], #44393 +; CHECK: bfi w0, [[REG]], #1, #19 +define i32 @test7(i32 %a) { + %1 = and i32 %a, 4293918721 ; 0xfff00001 + %2 = or i32 %1, 744146 ; 0x000b5ad2 + ret i32 %2 +} + +; BFIs that require more instructions to materialize the constant as compared +; to the original ORR are not okay. In this case we would be replacing the +; 'and' with a 'movk', which would decrease ILP while using the same number of +; instructions. +; CHECK-LABEL: @test8 +; CHECK: mov [[REG2:x[0-9]+]], #157599529959424 +; CHECK: and [[REG1:x[0-9]+]], x0, #0xff000000000000ff +; CHECK: movk [[REG2]], #31059, lsl #16 +; CHECK: orr x0, [[REG1]], [[REG2]] +define i64 @test8(i64 %a) { + %1 = and i64 %a, -72057594037927681 ; 0xff000000000000ff + %2 = or i64 %1, 157601565442048 ; 0x00008f5679530000 + ret i64 %2 +} + +; This test exposed an issue with an overly aggressive assert. The bit of code +; that is expected to catch this case is unable to deal with the trunc, which +; results in a failing check due to a mismatch between the BFI opcode and +; the expected value type of the OR. +; CHECK-LABEL: @test9 +; CHECK: lsr x0, x0, #12 +; CHECK: lsr [[REG:w[0-9]+]], w1, #23 +; CHECK: bfi w0, [[REG]], #23, #9 +define i32 @test9(i64 %b, i32 %e) { + %c = lshr i64 %b, 12 + %d = trunc i64 %c to i32 + %f = and i32 %d, 8388607 + %g = and i32 %e, -8388608 + %h = or i32 %g, %f + ret i32 %h +} diff --git a/test/CodeGen/AArch64/bitfield.ll b/test/CodeGen/AArch64/bitfield.ll index 5f19b6943b8e..8bd1279544b8 100644 --- a/test/CodeGen/AArch64/bitfield.ll +++ b/test/CodeGen/AArch64/bitfield.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s @var32 = global i32 0 @var64 = global i64 0 diff --git a/test/CodeGen/AArch64/bitreverse.ll b/test/CodeGen/AArch64/bitreverse.ll index 936e3554b397..2eee7cfd8b97 100644 --- a/test/CodeGen/AArch64/bitreverse.ll +++ b/test/CodeGen/AArch64/bitreverse.ll @@ -7,6 +7,7 @@ declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone define <2 x i16> @f(<2 x i16> %a) { ; CHECK-LABEL: f: +; CHECK: rev32 ; CHECK: ushr %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a) ret <2 x i16> %b @@ -47,14 +48,14 @@ define <8 x i8> @g_vec(<8 x i8> %a) { ; Try and match as much of the sequence as precisely as possible. ; CHECK-LABEL: g_vec: -; CHECK-DAG: movi [[M1:v.*]], #0x80 -; CHECK-DAG: movi [[M2:v.*]], #0x40 -; CHECK-DAG: movi [[M3:v.*]], #0x20 -; CHECK-DAG: movi [[M4:v.*]], #0x10 -; CHECK-DAG: movi [[M5:v.*]], #0x8 -; CHECK-DAG: movi [[M6:v.*]], #0x4{{$}} -; CHECK-DAG: movi [[M7:v.*]], #0x2{{$}} -; CHECK-DAG: movi [[M8:v.*]], #0x1{{$}} +; CHECK-DAG: movi [[M1:v.*]], #128 +; CHECK-DAG: movi [[M2:v.*]], #64 +; CHECK-DAG: movi [[M3:v.*]], #32 +; CHECK-DAG: movi [[M4:v.*]], #16 +; CHECK-DAG: movi [[M5:v.*]], #8{{$}} +; CHECK-DAG: movi [[M6:v.*]], #4{{$}} +; CHECK-DAG: movi [[M7:v.*]], #2{{$}} +; CHECK-DAG: movi [[M8:v.*]], #1{{$}} ; CHECK-DAG: shl [[S1:v.*]], v0.8b, #7 ; CHECK-DAG: shl [[S2:v.*]], v0.8b, #5 ; CHECK-DAG: shl [[S3:v.*]], v0.8b, #3 diff --git a/test/CodeGen/AArch64/branch-folder-merge-mmos.ll b/test/CodeGen/AArch64/branch-folder-merge-mmos.ll index 3f9c0239fe41..e3af90ae4831 100644 --- a/test/CodeGen/AArch64/branch-folder-merge-mmos.ll +++ b/test/CodeGen/AArch64/branch-folder-merge-mmos.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu -stop-after branch-folder -o /dev/null < %s | FileCheck %s +; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu -stop-after branch-folder -o - < %s | FileCheck %s target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" ; Function Attrs: norecurse nounwind diff --git a/test/CodeGen/AArch64/bswap-known-bits.ll b/test/CodeGen/AArch64/bswap-known-bits.ll new file mode 100644 index 000000000000..e5de7953d1b8 --- /dev/null +++ b/test/CodeGen/AArch64/bswap-known-bits.ll @@ -0,0 +1,44 @@ +; RUN: llc < %s -mtriple=aarch64-apple-darwin | FileCheck %s + +declare i16 @llvm.bswap.i16(i16) +declare i32 @llvm.bswap.i32(i32) + +; CHECK-LABEL: @test1 +; CHECK: orr w0, wzr, #0x1 +define i1 @test1(i16 %arg) { + %a = or i16 %arg, 511 + %b = call i16 @llvm.bswap.i16(i16 %a) + %and = and i16 %b, 256 + %res = icmp eq i16 %and, 256 + ret i1 %res +} + +; CHECK-LABEL: @test2 +; CHECK: orr w0, wzr, #0x1 +define i1 @test2(i16 %arg) { + %a = or i16 %arg, 1 + %b = call i16 @llvm.bswap.i16(i16 %a) + %and = and i16 %b, 256 + %res = icmp eq i16 %and, 256 + ret i1 %res +} + +; CHECK-LABEL: @test3 +; CHECK: orr w0, wzr, #0x1 +define i1 @test3(i16 %arg) { + %a = or i16 %arg, 256 + %b = call i16 @llvm.bswap.i16(i16 %a) + %and = and i16 %b, 1 + %res = icmp eq i16 %and, 1 + ret i1 %res +} + +; CHECK-LABEL: @test4 +; CHECK: orr w0, wzr, #0x1 +define i1 @test4(i32 %arg) { + %a = or i32 %arg, 2147483647 ; i32_MAX + %b = call i32 @llvm.bswap.i32(i32 %a) + %and = and i32 %b, 127 + %res = icmp eq i32 %and, 127 + ret i1 %res +} diff --git a/test/CodeGen/AArch64/cmpxchg-O0.ll b/test/CodeGen/AArch64/cmpxchg-O0.ll new file mode 100644 index 000000000000..c79d82a63774 --- /dev/null +++ b/test/CodeGen/AArch64/cmpxchg-O0.ll @@ -0,0 +1,75 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 %s -o - | FileCheck %s + +define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_8: +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldaxrb [[OLD:w[0-9]+]], [x0] +; CHECK: cmp [[OLD]], w1, uxtb +; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: stlxrb [[STATUS:w[3-9]]], w2, [x0] +; CHECK: cbnz [[STATUS]], [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 +; CHECK: cset {{w[0-9]+}}, eq + %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic + ret { i8, i1 } %res +} + +define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_16: +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldaxrh [[OLD:w[0-9]+]], [x0] +; CHECK: cmp [[OLD]], w1, uxth +; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: stlxrh [[STATUS:w[3-9]]], w2, [x0] +; CHECK: cbnz [[STATUS]], [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 +; CHECK: cset {{w[0-9]+}}, eq + %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic + ret { i16, i1 } %res +} + +define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_32: +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldaxr [[OLD:w[0-9]+]], [x0] +; CHECK: cmp [[OLD]], w1 +; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: stlxr [[STATUS:w[3-9]]], w2, [x0] +; CHECK: cbnz [[STATUS]], [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: subs {{w[0-9]+}}, [[OLD]], w1 +; CHECK: cset {{w[0-9]+}}, eq + %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic + ret { i32, i1 } %res +} + +define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_64: +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldaxr [[OLD:x[0-9]+]], [x0] +; CHECK: cmp [[OLD]], x1 +; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: stlxr [[STATUS:w[3-9]]], x2, [x0] +; CHECK: cbnz [[STATUS]], [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: subs {{x[0-9]+}}, [[OLD]], x1 +; CHECK: cset {{w[0-9]+}}, eq + %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic + ret { i64, i1 } %res +} + +define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_128: +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [x0] +; CHECK: cmp [[OLD_LO]], x2 +; CHECK: sbcs xzr, [[OLD_HI]], x3 +; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, [x0] +; CHECK: cbnz [[STATUS]], [[RETRY]] +; CHECK: [[DONE]]: + %res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic + ret { i128, i1 } %res +} diff --git a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll index 004267f4e4e0..1f8e0efa0675 100644 --- a/test/CodeGen/AArch64/combine-comparisons-by-cse.ll +++ b/test/CodeGen/AArch64/combine-comparisons-by-cse.ll @@ -405,11 +405,11 @@ return: ; preds = %land.lhs.true, %con define void @cmp_shifted(i32 %in, i32 %lhs, i32 %rhs) { ; CHECK-LABEL: cmp_shifted: -; CHECK: cmp w0, #1 -; [...] ; CHECK: cmp w0, #2, lsl #12 +; [...] +; CHECK: cmp w0, #1 - %tst_low = icmp sgt i32 %in, 0 + %tst_low = icmp sgt i32 %in, 8191 br i1 %tst_low, label %true, label %false true: @@ -417,7 +417,7 @@ true: ret void false: - %tst = icmp sgt i32 %in, 8191 + %tst = icmp sgt i32 %in, 0 br i1 %tst, label %truer, label %falser truer: @@ -429,6 +429,42 @@ falser: ret void } +define i32 @combine_gt_ge_sel(i64 %v, i64* %p) #0 { +; CHECK-LABEL: combine_gt_ge_sel +; CHECK: ldr [[reg1:w[0-9]*]], +; CHECK: cmp [[reg1]], #0 +; CHECK: csel {{.*}}, gt +entry: + %0 = load i32, i32* @a, align 4 + %cmp = icmp sgt i32 %0, 0 + %m = select i1 %cmp, i64 %v, i64 0 + store i64 %m, i64* %p + br i1 %cmp, label %lor.lhs.false, label %land.lhs.true + +land.lhs.true: ; preds = %entry + %1 = load i32, i32* @b, align 4 + %2 = load i32, i32* @c, align 4 + %cmp1 = icmp eq i32 %1, %2 + br i1 %cmp1, label %return, label %land.lhs.true3 + +lor.lhs.false: ; preds = %entry + %cmp2 = icmp sgt i32 %0, 1 + br i1 %cmp2, label %land.lhs.true3, label %if.end + +land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true + %3 = load i32, i32* @b, align 4 + %4 = load i32, i32* @d, align 4 + %cmp4 = icmp eq i32 %3, %4 + br i1 %cmp4, label %return, label %if.end + +if.end: ; preds = %land.lhs.true3, %lor.lhs.false + br label %return + +return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true + %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ] + ret i32 %retval.0 +} + declare i32 @zoo(i32) declare double @yoo(i32) diff --git a/test/CodeGen/AArch64/complex-int-to-fp.ll b/test/CodeGen/AArch64/complex-int-to-fp.ll index 1102553ab551..227c626ba15d 100644 --- a/test/CodeGen/AArch64/complex-int-to-fp.ll +++ b/test/CodeGen/AArch64/complex-int-to-fp.ll @@ -155,7 +155,7 @@ define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone { } define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone { ; CHECK-LABEL: test_unsigned_v4i8_to_v4f32 -; CHECK: bic.4h v0, #0xff, lsl #8 +; CHECK: bic.4h v0, #255, lsl #8 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0 ; CHECK: ucvtf.4s v0, [[VAL32]] diff --git a/test/CodeGen/AArch64/cond-sel.ll b/test/CodeGen/AArch64/cond-sel.ll index dfc83aacfcfc..b39cea1f6192 100644 --- a/test/CodeGen/AArch64/cond-sel.ll +++ b/test/CodeGen/AArch64/cond-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s @var32 = global i32 0 @@ -10,8 +10,8 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK-DAG: movz [[W52:w[0-9]+]], #{{52|0x34}} -; CHECK-DAG: movz [[W42:w[0-9]+]], #{{42|0x2a}} +; CHECK-DAG: mov [[W52:w[0-9]+]], #{{52|0x34}} +; CHECK-DAG: mov [[W42:w[0-9]+]], #{{42|0x2a}} ; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi %rhs64 = sext i32 %rhs32 to i64 @@ -34,8 +34,8 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r ; CHECK-NOFP-NOT: fcmp %val1 = select i1 %tst1, i32 42, i32 52 store i32 %val1, i32* @var32 -; CHECK: movz [[W52:w[0-9]+]], #{{52|0x34}} -; CHECK: movz [[W42:w[0-9]+]], #{{42|0x2a}} +; CHECK: mov [[W52:w[0-9]+]], #{{52|0x34}} +; CHECK: mov [[W42:w[0-9]+]], #{{42|0x2a}} ; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi ; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt @@ -46,7 +46,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r %val2 = select i1 %tst2, i64 9, i64 15 store i64 %val2, i64* @var64 ; CHECK: orr w[[CONST15:[0-9]+]], wzr, #0xf -; CHECK: movz {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}} +; CHECK: mov {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}} ; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq ; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs @@ -135,6 +135,34 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { ; CHECK: ret } +define void @test_csinv0(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) minsize { +; CHECK-LABEL: test_csinv0: + + %tst1 = icmp ugt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, i32 0, i32 -1 + store volatile i32 %val1, i32* @var32 +; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]] +; CHECK: csetm {{w[0-9]+}}, ls + + %rhs2 = add i32 %rhs32, 42 + %tst2 = icmp sle i32 %lhs32, %rhs2 + %val2 = select i1 %tst2, i32 -1, i32 %rhs2 + store volatile i32 %val2, i32* @var32 +; CHECK: cmp [[LHS2:w[0-9]+]], [[RHS2:w[0-9]+]] +; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt + +; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls). + %rhs3 = mul i64 %rhs64, 19 + %tst3 = icmp ugt i64 %lhs64, %rhs3 + %val3 = select i1 %tst3, i64 %rhs3, i64 -1 + store volatile i64 %val3, i64* @var64 +; CHECK: cmp [[LHS3:x[0-9]+]], [[RHS3:x[0-9]+]] +; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi + + ret void +; CHECK: ret +} + define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize { ; CHECK-LABEL: test_csneg: diff --git a/test/CodeGen/AArch64/cpus.ll b/test/CodeGen/AArch64/cpus.ll index 9c2a4fd55d1b..3296e38b64f4 100644 --- a/test/CodeGen/AArch64/cpus.ll +++ b/test/CodeGen/AArch64/cpus.ll @@ -6,7 +6,10 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a73 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=vulcan 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID ; CHECK-NOT: {{.*}} is not a recognized processor for this target diff --git a/test/CodeGen/AArch64/cxx-tlscc.ll b/test/CodeGen/AArch64/cxx-tlscc.ll index 9996c0d3aba8..a36aad51ca82 100644 --- a/test/CodeGen/AArch64/cxx-tlscc.ll +++ b/test/CodeGen/AArch64/cxx-tlscc.ll @@ -1,8 +1,10 @@ ; RUN: llc < %s -mtriple=aarch64-apple-ios | FileCheck %s -; RUN: llc < %s -mtriple=aarch64-apple-ios -enable-shrink-wrap=true | FileCheck --check-prefix=CHECK %s +; RUN: llc < %s -mtriple=aarch64-apple-ios -enable-shrink-wrap=true | FileCheck %s ; Shrink wrapping currently does not kick in because we have a TLS CALL ; in the entry block and it will clobber the link register. +; RUN: llc < %s -mtriple=aarch64-apple-ios -O0 | FileCheck --check-prefix=CHECK-O0 %s + %struct.S = type { i8 } @sg = internal thread_local global %struct.S zeroinitializer, align 1 @@ -42,7 +44,9 @@ __tls_init.exit: ; CHECK-NOT: stp d3, d2 ; CHECK-NOT: stp d1, d0 ; CHECK-NOT: stp x20, x19 -; CHECK-NOT: stp x14, x13 +; FIXME: The splitting logic in the register allocator fails to split along +; control flow here, we used to get this right by accident before... +; CHECK-NOTXX: stp x14, x13 ; CHECK-NOT: stp x12, x11 ; CHECK-NOT: stp x10, x9 ; CHECK-NOT: stp x8, x7 @@ -61,7 +65,7 @@ __tls_init.exit: ; CHECK-NOT: ldp x8, x7 ; CHECK-NOT: ldp x10, x9 ; CHECK-NOT: ldp x12, x11 -; CHECK-NOT: ldp x14, x13 +; CHECK-NOTXX: ldp x14, x13 ; CHECK-NOT: ldp x20, x19 ; CHECK-NOT: ldp d1, d0 ; CHECK-NOT: ldp d3, d2 @@ -76,6 +80,52 @@ __tls_init.exit: ; CHECK-NOT: ldp d29, d28 ; CHECK-NOT: ldp d31, d30 +; CHECK-O0-LABEL: _ZTW2sg +; CHECK-O0: stp d31, d30 +; CHECK-O0: stp d29, d28 +; CHECK-O0: stp d27, d26 +; CHECK-O0: stp d25, d24 +; CHECK-O0: stp d23, d22 +; CHECK-O0: stp d21, d20 +; CHECK-O0: stp d19, d18 +; CHECK-O0: stp d17, d16 +; CHECK-O0: stp d7, d6 +; CHECK-O0: stp d5, d4 +; CHECK-O0: stp d3, d2 +; CHECK-O0: stp d1, d0 +; CHECK-O0: stp x14, x13 +; CHECK-O0: stp x12, x11 +; CHECK-O0: stp x10, x9 +; CHECK-O0: stp x8, x7 +; CHECK-O0: stp x6, x5 +; CHECK-O0: stp x4, x3 +; CHECK-O0: stp x2, x1 +; CHECK-O0: blr +; CHECK-O0: tbnz w{{.*}}, #0, [[BB_end:.?LBB0_[0-9]+]] +; CHECK-O0: blr +; CHECK-O0: tlv_atexit +; CHECK-O0: [[BB_end]]: +; CHECK-O0: blr +; CHECK-O0: ldp x2, x1 +; CHECK-O0: ldp x4, x3 +; CHECK-O0: ldp x6, x5 +; CHECK-O0: ldp x8, x7 +; CHECK-O0: ldp x10, x9 +; CHECK-O0: ldp x12, x11 +; CHECK-O0: ldp x14, x13 +; CHECK-O0: ldp d1, d0 +; CHECK-O0: ldp d3, d2 +; CHECK-O0: ldp d5, d4 +; CHECK-O0: ldp d7, d6 +; CHECK-O0: ldp d17, d16 +; CHECK-O0: ldp d19, d18 +; CHECK-O0: ldp d21, d20 +; CHECK-O0: ldp d23, d22 +; CHECK-O0: ldp d25, d24 +; CHECK-O0: ldp d27, d26 +; CHECK-O0: ldp d29, d28 +; CHECK-O0: ldp d31, d30 + ; CHECK-LABEL: _ZTW4sum1 ; CHECK-NOT: stp d31, d30 ; CHECK-NOT: stp d29, d28 @@ -98,6 +148,77 @@ __tls_init.exit: ; CHECK-NOT: stp x4, x3 ; CHECK-NOT: stp x2, x1 ; CHECK: blr + +; CHECK-O0-LABEL: _ZTW4sum1 +; CHECK-O0-NOT: vstr +; CHECK-O0-NOT: vldr define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind { ret i32* @sum1 } + +; Make sure at O0, we don't generate spilling/reloading of the CSRs. +; CHECK-O0-LABEL: tls_test2 +; CHECK-O0-NOT: stp d31, d30 +; CHECK-O0-NOT: stp d29, d28 +; CHECK-O0-NOT: stp d27, d26 +; CHECK-O0-NOT: stp d25, d24 +; CHECK-O0-NOT: stp d23, d22 +; CHECK-O0-NOT: stp d21, d20 +; CHECK-O0-NOT: stp d19, d18 +; CHECK-O0-NOT: stp d17, d16 +; CHECK-O0-NOT: stp d7, d6 +; CHECK-O0-NOT: stp d5, d4 +; CHECK-O0-NOT: stp d3, d2 +; CHECK-O0-NOT: stp d1, d0 +; CHECK-O0-NOT: stp x20, x19 +; CHECK-O0-NOT: stp x14, x13 +; CHECK-O0-NOT: stp x12, x11 +; CHECK-O0-NOT: stp x10, x9 +; CHECK-O0-NOT: stp x8, x7 +; CHECK-O0-NOT: stp x6, x5 +; CHECK-O0-NOT: stp x4, x3 +; CHECK-O0-NOT: stp x2, x1 +; CHECK-O0: bl {{.*}}tls_helper +; CHECK-O0-NOT: ldp x2, x1 +; CHECK-O0-NOT: ldp x4, x3 +; CHECK-O0-NOT: ldp x6, x5 +; CHECK-O0-NOT: ldp x8, x7 +; CHECK-O0-NOT: ldp x10, x9 +; CHECK-O0-NOT: ldp x12, x11 +; CHECK-O0-NOT: ldp x14, x13 +; CHECK-O0-NOT: ldp x20, x19 +; CHECK-O0-NOT: ldp d1, d0 +; CHECK-O0-NOT: ldp d3, d2 +; CHECK-O0-NOT: ldp d5, d4 +; CHECK-O0-NOT: ldp d7, d6 +; CHECK-O0-NOT: ldp d17, d16 +; CHECK-O0-NOT: ldp d19, d18 +; CHECK-O0-NOT: ldp d21, d20 +; CHECK-O0-NOT: ldp d23, d22 +; CHECK-O0-NOT: ldp d25, d24 +; CHECK-O0-NOT: ldp d27, d26 +; CHECK-O0-NOT: ldp d29, d28 +; CHECK-O0-NOT: ldp d31, d30 +; CHECK-O0: ret +%class.C = type { i32 } +@tC = internal thread_local global %class.C zeroinitializer, align 4 +declare cxx_fast_tlscc void @tls_helper() +define cxx_fast_tlscc %class.C* @tls_test2() #1 { + call cxx_fast_tlscc void @tls_helper() + ret %class.C* @tC +} + +; Make sure we do not allow tail call when caller and callee have different +; calling conventions. +declare %class.C* @_ZN1CD1Ev(%class.C* readnone returned %this) +; CHECK-LABEL: tls_test +; CHECK: bl __tlv_atexit +define cxx_fast_tlscc void @__tls_test() { +entry: + store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4 + %0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1 + ret void +} + +attributes #0 = { nounwind "no-frame-pointer-elim"="true" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AArch64/dag-combine-invaraints.ll b/test/CodeGen/AArch64/dag-combine-invaraints.ll index ac2d057ff3c9..20ba3fea8377 100644 --- a/test/CodeGen/AArch64/dag-combine-invaraints.ll +++ b/test/CodeGen/AArch64/dag-combine-invaraints.ll @@ -24,7 +24,7 @@ main_: ret i32 0 ; CHECK: main: -; CHECK-DAG: movz +; CHECK-DAG: mov ; CHECK-DAG: orr ; CHECK: csel } diff --git a/test/CodeGen/AArch64/directcond.ll b/test/CodeGen/AArch64/directcond.ll index fbea4a6e5838..f89d7603fd3e 100644 --- a/test/CodeGen/AArch64/directcond.ll +++ b/test/CodeGen/AArch64/directcond.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-atomic-cfg-tidy=0 | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 -aarch64-atomic-cfg-tidy=0 | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -aarch64-atomic-cfg-tidy=0 | FileCheck --check-prefix=CHECK-NOFP %s define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) { diff --git a/test/CodeGen/AArch64/div_minsize.ll b/test/CodeGen/AArch64/div_minsize.ll new file mode 100644 index 000000000000..43f12340f19f --- /dev/null +++ b/test/CodeGen/AArch64/div_minsize.ll @@ -0,0 +1,45 @@ +; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s + +define i32 @testsize1(i32 %x) minsize nounwind { +entry: + %div = sdiv i32 %x, 32 + ret i32 %div +; CHECK-LABEL: testsize1 +; CHECK: sdiv +} + +define i32 @testsize2(i32 %x) minsize nounwind { +entry: + %div = sdiv i32 %x, 33 + ret i32 %div +; CHECK-LABEL: testsize2 +; CHECK: sdiv +} + +define i32 @testsize3(i32 %x) minsize nounwind { +entry: + %div = udiv i32 %x, 32 + ret i32 %div +; CHECK-LABEL: testsize3 +; CHECK: lsr +} + +define i32 @testsize4(i32 %x) minsize nounwind { +entry: + %div = udiv i32 %x, 33 + ret i32 %div +; CHECK-LABEL: testsize4 +; CHECK: udiv +} + +define <8 x i16> @sdiv_vec8x16_minsize(<8 x i16> %var) minsize { +entry: +; CHECK: sdiv_vec8x16_minsize +; CHECK: sshr v1.8h, v0.8h, #15 +; CHECK: usra v0.8h, v1.8h, #11 +; CHECK: sshr v0.8h, v0.8h, #5 +; CHECK: ret + %0 = sdiv <8 x i16> %var, + ret <8 x i16> %0 +} + diff --git a/test/CodeGen/AArch64/emutls.ll b/test/CodeGen/AArch64/emutls.ll index ac5762edba98..36b0ae47bd4a 100644 --- a/test/CodeGen/AArch64/emutls.ll +++ b/test/CodeGen/AArch64/emutls.ll @@ -1,5 +1,5 @@ ; RUN: llc -emulated-tls -mtriple=aarch64-linux-android \ -; RUN: -relocation-model=pic < %s | FileCheck -check-prefix=ARM64 %s +; RUN: -relocation-model=pic -disable-fp-elim < %s | FileCheck -check-prefix=ARM64 %s ; Copied from X86/emutls.ll @@ -54,63 +54,160 @@ entry: ret i32* @i1 } +define i32 @f5() nounwind { +; ARM64-LABEL: f5: +; ARM64: adrp x0, __emutls_v.i3 +; ARM64: add x0, x0, :lo12:__emutls_v.i3 +; ARM64: bl __emutls_get_address +; ARM64-NEXT: ldr w0, [x0] + +entry: + %tmp1 = load i32, i32* @i3 + ret i32 %tmp1 +} + +define i32* @f6() { +; ARM64-LABEL: f6: +; ARM64: adrp x0, __emutls_v.i3 +; ARM64: add x0, x0, :lo12:__emutls_v.i3 +; ARM64-NEXT: bl __emutls_get_address +; ARM64-NEXT: ldp x29, x30, [sp] + +entry: + ret i32* @i3 +} + +; Simple test of comdat __thread variables. +; template struct A { static __thread T x; }; +; template T __thread A::x; +; int getIntX() { return A::x++; } +; float getFloatX() { return A::x++; } + +$_ZN1AIiE1xE = comdat any +$_ZN1AIfE1xE = comdat any +@_ZN1AIiE1xE = linkonce_odr thread_local global i32 0, comdat, align 4 +@_ZN1AIfE1xE = linkonce_odr thread_local global float 0.000000e+00, comdat, align 4 + +define i32 @_Z7getIntXv() { +; ARM64-LABEL: _Z7getIntXv: +; ARM64: adrp x0, :got:__emutls_v._ZN1AIiE1xE +; ARM64: ldr x0, [x0, :got_lo12:__emutls_v._ZN1AIiE1xE] +; ARM64-NEXT: bl __emutls_get_address +; ARM64-NEXT: ldr {{.*}}, [x0] +; ARM64: add +; ARM64: str {{.*}}, [x0] + +entry: + %0 = load i32, i32* @_ZN1AIiE1xE, align 4 + %inc = add nsw i32 %0, 1 + store i32 %inc, i32* @_ZN1AIiE1xE, align 4 + ret i32 %0 +} + +define float @_Z9getFloatXv() { +; ARM64-LABEL: _Z9getFloatXv: +; ARM64: adrp x0, :got:__emutls_v._ZN1AIfE1xE +; ARM64: ldr x0, [x0, :got_lo12:__emutls_v._ZN1AIfE1xE] +; ARM64-NEXT: bl __emutls_get_address +; ARM64-NEXT: ldr {{.*}}, [x0] +; ARM64: fadd s{{.*}}, s +; ARM64: str s{{.*}}, [x0] + +entry: + %0 = load float, float* @_ZN1AIfE1xE, align 4 + %inc = fadd float %0, 1.000000e+00 + store float %inc, float* @_ZN1AIfE1xE, align 4 + ret float %0 +} + + ;;;;;;;;;;;;;; 64-bit __emutls_v. and __emutls_t. -; ARM64 .section .data.rel.local, +; ARM64: .data{{$}} +; ARM64: .globl __emutls_v.i1 ; ARM64-LABEL: __emutls_v.i1: ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 0 ; ARM64-NEXT: .xword __emutls_t.i1 -; ARM64 .section .rodata, +; ARM64: .section .rodata, ; ARM64-LABEL: __emutls_t.i1: ; ARM64-NEXT: .word 15 ; ARM64-NOT: __emutls_v.i2 -; ARM64 .section .data.rel.local, +; ARM64: .data{{$}} +; ARM64-NOT: .globl ; ARM64-LABEL: __emutls_v.i3: ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 0 ; ARM64-NEXT: .xword __emutls_t.i3 -; ARM64 .section .rodata, +; ARM64: .section .rodata, ; ARM64-LABEL: __emutls_t.i3: ; ARM64-NEXT: .word 15 -; ARM64 .section .data.rel.local, +; ARM64: .hidden __emutls_v.i4 +; ARM64: .data{{$}} +; ARM64: .globl __emutls_v.i4 ; ARM64-LABEL: __emutls_v.i4: ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 4 ; ARM64-NEXT: .xword 0 ; ARM64-NEXT: .xword __emutls_t.i4 -; ARM64 .section .rodata, +; ARM64: .section .rodata, ; ARM64-LABEL: __emutls_t.i4: ; ARM64-NEXT: .word 15 ; ARM64-NOT: __emutls_v.i5: -; ARM64 .hidden __emutls_v.i5 +; ARM64: .hidden __emutls_v.i5 ; ARM64-NOT: __emutls_v.i5: -; ARM64 .section .data.rel.local, +; ARM64: .data{{$}} +; ARM64: .globl __emutls_v.s1 ; ARM64-LABEL: __emutls_v.s1: ; ARM64-NEXT: .xword 2 ; ARM64-NEXT: .xword 2 ; ARM64-NEXT: .xword 0 ; ARM64-NEXT: .xword __emutls_t.s1 -; ARM64 .section .rodata, +; ARM64: .section .rodata, ; ARM64-LABEL: __emutls_t.s1: ; ARM64-NEXT: .hword 15 -; ARM64 .section .data.rel.local, +; ARM64: .data{{$}} ; ARM64-LABEL: __emutls_v.b1: ; ARM64-NEXT: .xword 1 ; ARM64-NEXT: .xword 1 ; ARM64-NEXT: .xword 0 ; ARM64-NEXT: .xword 0 -; ARM64-NOT: __emutls_t.b1 +; ARM64-NOT: __emutls_t.b1 + +; ARM64: .section .data.__emutls_v._ZN1AIiE1xE,{{.*}},__emutls_v._ZN1AIiE1xE,comdat +; ARM64: .weak __emutls_v._ZN1AIiE1xE +; ARM64: .p2align 3 +; ARM64-LABEL: __emutls_v._ZN1AIiE1xE: +; ARM64-NEXT: .xword 4 +; ARM64-NEXT: .xword 4 +; ARM64-NEXT: .xword 0 +; ARM64-NEXT: .xword 0 + +; ARM64: .section .data.__emutls_v._ZN1AIfE1xE,{{.*}},__emutls_v._ZN1AIfE1xE,comdat +; ARM64: .weak __emutls_v._ZN1AIfE1xE +; ARM64: .p2align 3 +; ARM64-LABEL: __emutls_v._ZN1AIfE1xE: +; ARM64-NEXT: .xword 4 +; ARM64-NEXT: .xword 4 +; ARM64-NEXT: .xword 0 +; ARM64-NEXT: .xword __emutls_t._ZN1AIfE1xE + +; ARM64: .section .rodata.__emutls_t._ZN1AIfE1xE,{{.*}},__emutls_t._ZN1AIfE1xE,comdat +; ARM64: .weak __emutls_t._ZN1AIfE1xE +; ARM64: .p2align 2 +; ARM64-LABEL: __emutls_t._ZN1AIfE1xE: +; ARM64-NEXT: .word 0 +; ARM64-NEXT: .size diff --git a/test/CodeGen/AArch64/emutls_generic.ll b/test/CodeGen/AArch64/emutls_generic.ll index 7664db3df8d2..03473cf80ee4 100644 --- a/test/CodeGen/AArch64/emutls_generic.ll +++ b/test/CodeGen/AArch64/emutls_generic.ll @@ -37,7 +37,9 @@ entry: ; ARM_64: __emutls_get_address ; ARM_64-NOT: __emutls_t.external_x ; ARM_64-NOT: __emutls_v.external_x: -; ARM_64: .align 3 +; ARM_64: .data{{$}} +; ARM_64: .globl __emutls_v.external_y +; ARM_64: .p2align 3 ; ARM_64-LABEL: __emutls_v.external_y: ; ARM_64-NEXT: .xword 1 ; ARM_64-NEXT: .xword 2 @@ -47,8 +49,9 @@ entry: ; ARM_64: .section .rodata, ; ARM_64-LABEL: __emutls_t.external_y: ; ARM_64-NEXT: .byte 7 -; ARM_64: .data -; ARM_64: .align 3 +; ARM_64: .data{{$}} +; ARM_64-NOT: .globl __emutls_v +; ARM_64: .p2align 3 ; ARM_64-LABEL: __emutls_v.internal_y: ; ARM_64-NEXT: .xword 8 ; ARM_64-NEXT: .xword 16 diff --git a/test/CodeGen/AArch64/extern-weak.ll b/test/CodeGen/AArch64/extern-weak.ll index 2203c0c4e698..921009cf821d 100644 --- a/test/CodeGen/AArch64/extern-weak.ll +++ b/test/CodeGen/AArch64/extern-weak.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=pic -o - %s | FileCheck %s -; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK-STATIC %s +; RUN: llc -mtriple=aarch64-none-linux-gnu -relocation-model=static -o - < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=aarch64-none-linux-gnu -code-model=large -o - %s | FileCheck --check-prefix=CHECK-LARGE %s declare extern_weak i32 @var() @@ -14,11 +14,6 @@ define i32()* @foo() { ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:var ; CHECK: ldr x0, [x[[ADDRHI]], :got_lo12:var] -; CHECK-STATIC: .LCPI0_0: -; CHECK-STATIC-NEXT: .xword var -; CHECK-STATIC: adrp x[[VAR:[0-9]+]], .LCPI0_0 -; CHECK-STATIC: ldr x0, [x[[VAR]], :lo12:.LCPI0_0] - ; In the large model, the usual relocations are absolute and can ; materialise 0. ; CHECK-LARGE: movz x0, #:abs_g3:var @@ -38,11 +33,6 @@ define i32* @bar() { ; CHECK: ldr [[BASE:x[0-9]+]], [x[[ADDRHI]], :got_lo12:arr_var] ; CHECK: add x0, [[BASE]], #20 -; CHECK-STATIC: .LCPI1_0: -; CHECK-STATIC-NEXT: .xword arr_var -; CHECK-STATIC: ldr [[BASE:x[0-9]+]], [{{x[0-9]+}}, :lo12:.LCPI1_0] -; CHECK-STATIC: add x0, [[BASE]], #20 - ret i32* %addr ; In the large model, the usual relocations are absolute and can @@ -61,9 +51,6 @@ define i32* @wibble() { ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var ; CHECK: add x0, [[BASE]], :lo12:defined_weak_var -; CHECK-STATIC: adrp [[BASE:x[0-9]+]], defined_weak_var -; CHECK-STATIC: add x0, [[BASE]], :lo12:defined_weak_var - ; CHECK-LARGE: movz x0, #:abs_g3:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var diff --git a/test/CodeGen/AArch64/f16-instructions.ll b/test/CodeGen/AArch64/f16-instructions.ll index e8ecb13b3564..f50504a9a260 100644 --- a/test/CodeGen/AArch64/f16-instructions.ll +++ b/test/CodeGen/AArch64/f16-instructions.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple aarch64-unknown-unknown -aarch64-neon-syntax=apple -asm-verbose=false -disable-post-ra -disable-fp-elim | FileCheck %s target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" @@ -446,6 +446,34 @@ define half @test_sitofp_i64(i64 %a) #0 { ret half %r } +; CHECK-LABEL: test_uitofp_i32_fadd: +; CHECK-NEXT: ucvtf s1, w0 +; CHECK-NEXT: fcvt h1, s1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 { + %c = uitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + +; CHECK-LABEL: test_sitofp_i32_fadd: +; CHECK-NEXT: scvtf s1, w0 +; CHECK-NEXT: fcvt h1, s1 +; CHECK-NEXT: fcvt s0, h0 +; CHECK-NEXT: fcvt s1, h1 +; CHECK-NEXT: fadd s0, s0, s1 +; CHECK-NEXT: fcvt h0, s0 +; CHECK-NEXT: ret +define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 { + %c = sitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + ; CHECK-LABEL: test_fptrunc_float: ; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: ret @@ -695,7 +723,7 @@ define half @test_maxnum(half %a, half %b) #0 { ; CHECK-LABEL: test_copysign: ; CHECK-NEXT: fcvt s1, h1 ; CHECK-NEXT: fcvt s0, h0 -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: ret @@ -706,7 +734,7 @@ define half @test_copysign(half %a, half %b) #0 { ; CHECK-LABEL: test_copysign_f32: ; CHECK-NEXT: fcvt s0, h0 -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: ret @@ -719,7 +747,7 @@ define half @test_copysign_f32(half %a, float %b) #0 { ; CHECK-LABEL: test_copysign_f64: ; CHECK-NEXT: fcvt s1, d1 ; CHECK-NEXT: fcvt s0, h0 -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: fcvt h0, s0 ; CHECK-NEXT: ret @@ -735,7 +763,7 @@ define half @test_copysign_f64(half %a, double %b) #0 { ; CHECK-LABEL: test_copysign_extended: ; CHECK-NEXT: fcvt s1, h1 ; CHECK-NEXT: fcvt s0, h0 -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: ret define float @test_copysign_extended(half %a, half %b) #0 { diff --git a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll index e04a62b85c8e..2240296c89ff 100644 --- a/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll +++ b/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll @@ -19,8 +19,8 @@ bb4: } ; CHECK-LABEL: test_and -; CHECK: cbz w0, {{LBB[0-9]+_2}} -; CHECK: cbnz w1, {{LBB[0-9]+_3}} +; CHECK: cbnz w0, {{LBB[0-9]+_2}} +; CHECK: cbz w1, {{LBB[0-9]+_1}} define i64 @test_and(i32 %a, i32 %b) { bb1: %0 = icmp ne i32 %a, 0 diff --git a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll index 2855419a1ca0..2a0139ed9b08 100644 --- a/test/CodeGen/AArch64/fast-isel-cmp-vec.ll +++ b/test/CodeGen/AArch64/fast-isel-cmp-vec.ll @@ -11,7 +11,7 @@ define <2 x i32> @icmp_v2i32(<2 x i32> %a) { ; CHECK: ; BB#0: ; CHECK-NEXT: cmeq.2s [[CMP:v[0-9]+]], v0, #0 ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret %c = icmp eq <2 x i32> %a, zeroinitializer @@ -26,7 +26,7 @@ define <2 x i32> @icmp_constfold_v2i32(<2 x i32> %a) { ; CHECK: ; BB#0: ; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.2s [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b v0, v[[CMP]], [[MASK]] ; CHECK-NEXT: ret %1 = icmp eq <2 x i32> %a, %a @@ -42,7 +42,7 @@ define <4 x i32> @icmp_v4i32(<4 x i32> %a) { ; CHECK-NEXT: cmeq.4s [[CMP:v[0-9]+]], v0, #0 ; CHECK-NEXT: xtn.4h [[CMPV4I16:v[0-9]+]], [[CMP]] ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], [[CMPV4I16]], [[MASK]] ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0 ; CHECK-NEXT: ret @@ -58,7 +58,7 @@ define <4 x i32> @icmp_constfold_v4i32(<4 x i32> %a) { ; CHECK: ; BB#0: ; CHECK-NEXT: movi d[[CMP:[0-9]+]], #0xffffffffffffffff ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.4h [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.8b [[ZEXT:v[0-9]+]], v[[CMP]], [[MASK]] ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0 ; CHECK-NEXT: ret @@ -74,7 +74,7 @@ define <16 x i8> @icmp_v16i8(<16 x i8> %a) { ; CHECK: ; BB#0: ; CHECK-NEXT: cmeq.16b [[CMP:v[0-9]+]], v0, #0 ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret %c = icmp eq <16 x i8> %a, zeroinitializer @@ -89,7 +89,7 @@ define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) { ; CHECK: ; BB#0: ; CHECK-NEXT: movi.2d [[CMP:v[0-9]+]], #0xffffffffffffffff ; CHECK-NEXT: ; BB#1: -; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #0x1 +; CHECK-NEXT: movi.16b [[MASK:v[0-9]+]], #1 ; CHECK-NEXT: and.16b v0, [[CMP]], [[MASK]] ; CHECK-NEXT: ret %1 = icmp eq <16 x i8> %a, %a diff --git a/test/CodeGen/AArch64/fast-isel-gep.ll b/test/CodeGen/AArch64/fast-isel-gep.ll index 33adcdc3c464..0cb1fd8465d4 100644 --- a/test/CodeGen/AArch64/fast-isel-gep.ll +++ b/test/CodeGen/AArch64/fast-isel-gep.ll @@ -33,7 +33,7 @@ define i32* @test_array3(i32* %a) { define i32* @test_array4(i32* %a) { ; CHECK-LABEL: test_array4 -; CHECK: movz [[REG:x[0-9]+]], #0x1008 +; CHECK: mov [[REG:x[0-9]+]], #4104 ; CHECK-NEXR: add x0, x0, [[REG]] %1 = getelementptr inbounds i32, i32* %a, i64 1026 ret i32* %1 diff --git a/test/CodeGen/AArch64/fast-isel-tbz.ll b/test/CodeGen/AArch64/fast-isel-tbz.ll index 598826763787..c35ae4230dd4 100644 --- a/test/CodeGen/AArch64/fast-isel-tbz.ll +++ b/test/CodeGen/AArch64/fast-isel-tbz.ll @@ -1,5 +1,5 @@ -; RUN: llc -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s +; RUN: llc -disable-peephole -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck %s +; RUN: llc -disable-peephole -fast-isel -fast-isel-abort=1 -aarch64-atomic-cfg-tidy=0 -verify-machineinstrs -mtriple=aarch64-apple-darwin < %s | FileCheck --check-prefix=CHECK --check-prefix=FAST %s define i32 @icmp_eq_i8(i8 zeroext %a) { ; CHECK-LABEL: icmp_eq_i8 diff --git a/test/CodeGen/AArch64/fastcc.ll b/test/CodeGen/AArch64/fastcc.ll index f021eb232618..fcc852263b48 100644 --- a/test/CodeGen/AArch64/fastcc.ll +++ b/test/CodeGen/AArch64/fastcc.ll @@ -1,18 +1,21 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-fp-elim -tailcallopt | FileCheck %s -check-prefix CHECK-TAIL +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-fp-elim | FileCheck %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-fp-elim -tailcallopt -aarch64-redzone | FileCheck %s -check-prefix CHECK-TAIL-RZ ; Without tailcallopt fastcc still means the caller cleans up the ; stack, so try to make sure this is respected. define fastcc void @func_stack0() { ; CHECK-LABEL: func_stack0: -; CHECK: mov x29, sp -; CHECK: str w{{[0-9]+}}, [sp, #-32]! +; CHECK: sub sp, sp, #48 +; CHECK: add x29, sp, #32 +; CHECK: str w{{[0-9]+}}, [sp] ; CHECK-TAIL-LABEL: func_stack0: -; CHECK-TAIL: stp x29, x30, [sp, #-16]! -; CHECK-TAIL-NEXT: mov x29, sp -; CHECK-TAIL: str w{{[0-9]+}}, [sp, #-32]! +; CHECK-TAIL: sub sp, sp, #48 +; CHECK-TAIL-NEXT: stp x29, x30, [sp, #32] +; CHECK-TAIL-NEXT: add x29, sp, #32 +; CHECK-TAIL: str w{{[0-9]+}}, [sp] call fastcc void @func_stack8([8 x i32] undef, i32 42) @@ -41,27 +44,29 @@ define fastcc void @func_stack0() { ; CHECK-TAIL-NOT: sub sp, sp ret void -; CHECK: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK: ldp x29, x30, [sp, #32] +; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: ret -; CHECK-TAIL: mov sp, x29 -; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16 +; CHECK-TAIL: ldp x29, x30, [sp, #32] +; CHECK-TAIL-NEXT: add sp, sp, #48 ; CHECK-TAIL-NEXT: ret } define fastcc void @func_stack8([8 x i32], i32 %stacked) { ; CHECK-LABEL: func_stack8: -; CHECK: stp x29, x30, [sp, #-16]! -; CHECK: mov x29, sp -; CHECK: str w{{[0-9]+}}, [sp, #-32]! +; CHECK: sub sp, sp, #48 +; CHECK: stp x29, x30, [sp, #32] +; CHECK: add x29, sp, #32 +; CHECK: str w{{[0-9]+}}, [sp] ; CHECK-TAIL-LABEL: func_stack8: -; CHECK-TAIL: stp x29, x30, [sp, #-16]! -; CHECK-TAIL: mov x29, sp -; CHECK-TAIL: str w{{[0-9]+}}, [sp, #-32]! +; CHECK-TAIL: sub sp, sp, #48 +; CHECK-TAIL: stp x29, x30, [sp, #32] +; CHECK-TAIL: add x29, sp, #32 +; CHECK-TAIL: str w{{[0-9]+}}, [sp] call fastcc void @func_stack8([8 x i32] undef, i32 42) @@ -90,22 +95,22 @@ define fastcc void @func_stack8([8 x i32], i32 %stacked) { ; CHECK-TAIL-NOT: sub sp, sp ret void -; CHECK: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK-NEXT: ldp x29, x30, [sp, #32] +; CHECK: add sp, sp, #48 ; CHECK-NEXT: ret -; CHECK-TAIL: mov sp, x29 -; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16 +; CHECK-TAIL: ldp x29, x30, [sp, #32] +; CHECK-TAIL-NEXT: add sp, sp, #64 ; CHECK-TAIL-NEXT: ret } define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) { ; CHECK-LABEL: func_stack32: -; CHECK: mov x29, sp +; CHECK: add x29, sp, #32 ; CHECK-TAIL-LABEL: func_stack32: -; CHECK-TAIL: mov x29, sp +; CHECK-TAIL: add x29, sp, #32 call fastcc void @func_stack8([8 x i32] undef, i32 42) @@ -134,11 +139,99 @@ define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) { ; CHECK-TAIL-NOT: sub sp, sp ret void -; CHECK: mov sp, x29 -; CHECK-NEXT: ldp x29, x30, [sp], #16 +; CHECK: ldp x29, x30, [sp, #32] +; CHECK-NEXT: add sp, sp, #48 ; CHECK-NEXT: ret -; CHECK-TAIL: mov sp, x29 -; CHECK-TAIL-NEXT: ldp x29, x30, [sp], #16 +; CHECK-TAIL: ldp x29, x30, [sp, #32] +; CHECK-TAIL-NEXT: add sp, sp, #80 ; CHECK-TAIL-NEXT: ret } + +; Check that arg stack pop is done after callee-save restore when no frame pointer is used. +define fastcc void @func_stack32_leaf([8 x i32], i128 %stacked0, i128 %stacked1) { +; CHECK-LABEL: func_stack32_leaf: +; CHECK: str x20, [sp, #-16]! +; CHECK: nop +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr x20, [sp], #16 +; CHECK-NEXT: ret + +; CHECK-TAIL-LABEL: func_stack32_leaf: +; CHECK-TAIL: str x20, [sp, #-16]! +; CHECK-TAIL: nop +; CHECK-TAIL-NEXT: //NO_APP +; CHECK-TAIL-NEXT: ldr x20, [sp], #16 +; CHECK-TAIL-NEXT: add sp, sp, #32 +; CHECK-TAIL-NEXT: ret + +; CHECK-TAIL-RZ-LABEL: func_stack32_leaf: +; CHECK-TAIL-RZ: str x20, [sp, #-16]! +; CHECK-TAIL-RZ-NOT: sub sp, sp +; CHECK-TAIL-RZ: nop +; CHECK-TAIL-RZ-NEXT: //NO_APP +; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16 +; CHECK-TAIL-RZ-NEXT: add sp, sp, #32 +; CHECK-TAIL-RZ-NEXT: ret + + ; Make sure there is a callee-save register to save/restore. + call void asm sideeffect "nop", "~{x20}"() nounwind + ret void +} + +; Check that arg stack pop is done after callee-save restore when no frame pointer is used. +define fastcc void @func_stack32_leaf_local([8 x i32], i128 %stacked0, i128 %stacked1) { +; CHECK-LABEL: func_stack32_leaf_local: +; CHECK: sub sp, sp, #32 +; CHECK-NEXT: str x20, [sp, #16] +; CHECK: nop +; CHECK-NEXT: //NO_APP +; CHECK-NEXT: ldr x20, [sp, #16] +; CHECK-NEXT: add sp, sp, #32 +; CHECK-NEXT: ret + +; CHECK-TAIL-LABEL: func_stack32_leaf_local: +; CHECK-TAIL: sub sp, sp, #32 +; CHECK-TAIL-NEXT: str x20, [sp, #16] +; CHECK-TAIL: nop +; CHECK-TAIL-NEXT: //NO_APP +; CHECK-TAIL-NEXT: ldr x20, [sp, #16] +; CHECK-TAIL-NEXT: add sp, sp, #64 +; CHECK-TAIL-NEXT: ret + +; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local: +; CHECK-TAIL-RZ: str x20, [sp, #-16]! +; CHECK-TAIL-RZ-NOT: sub sp, sp +; CHECK-TAIL-RZ: nop +; CHECK-TAIL-RZ-NEXT: //NO_APP +; CHECK-TAIL-RZ-NEXT: ldr x20, [sp], #16 +; CHECK-TAIL-RZ-NEXT: add sp, sp, #32 +; CHECK-TAIL-RZ-NEXT: ret + + %val0 = alloca [2 x i64], align 8 + + ; Make sure there is a callee-save register to save/restore. + call void asm sideeffect "nop", "~{x20}"() nounwind + ret void +} + +; Check that arg stack pop is done after callee-save restore when no frame pointer is used. +define fastcc void @func_stack32_leaf_local_nocs([8 x i32], i128 %stacked0, i128 %stacked1) { +; CHECK-LABEL: func_stack32_leaf_local_nocs: +; CHECK: sub sp, sp, #16 +; CHECK: add sp, sp, #16 +; CHECK-NEXT: ret + +; CHECK-TAIL-LABEL: func_stack32_leaf_local_nocs: +; CHECK-TAIL: sub sp, sp, #16 +; CHECK-TAIL: add sp, sp, #48 +; CHECK-TAIL-NEXT: ret + +; CHECK-TAIL-RZ-LABEL: func_stack32_leaf_local_nocs: +; CHECK-TAIL-RZ: add sp, sp, #32 +; CHECK-TAIL-RZ-NEXT: ret + + %val0 = alloca [2 x i64], align 8 + + ret void +} diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index d549c7e78421..e52b601b1454 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -149,3 +149,28 @@ define double @test_bitcasti64todouble(i64 %in) { ret double %res } + +define double @bitcast_fabs(double %x) { +; CHECK-LABEL: bitcast_fabs: +; CHECK: ; BB#0: +; CHECK-NEXT: fabs d0, d0 +; CHECK-NEXT: ret +; + %bc1 = bitcast double %x to i64 + %and = and i64 %bc1, 9223372036854775807 + %bc2 = bitcast i64 %and to double + ret double %bc2 +} + +define float @bitcast_fneg(float %x) { +; CHECK-LABEL: bitcast_fneg: +; CHECK: ; BB#0: +; CHECK-NEXT: fneg s0, s0 +; CHECK-NEXT: ret +; + %bc1 = bitcast float %x to i32 + %xor = xor i32 %bc1, 2147483648 + %bc2 = bitcast i32 %xor to float + ret float %bc2 +} + diff --git a/test/CodeGen/AArch64/fcvt_combine.ll b/test/CodeGen/AArch64/fcvt_combine.ll index 093ce4a4cd85..5644fa28533b 100644 --- a/test/CodeGen/AArch64/fcvt_combine.ll +++ b/test/CodeGen/AArch64/fcvt_combine.ll @@ -152,3 +152,11 @@ define <2 x i32> @test14(<2 x float> %f) { %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> ret <2 x i32> %vcvt.i } + +; CHECK-LABEL: test_illegal_fp_to_int: +; CHECK: fcvtzs.4s v0, v0, #2 +define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { + %scale = fmul <3 x float> %in, + %val = fptosi <3 x float> %scale to <3 x i32> + ret <3 x i32> %val +} diff --git a/test/CodeGen/AArch64/fdiv-combine.ll b/test/CodeGen/AArch64/fdiv-combine.ll index 389eefd97b28..9ec64a854ca3 100644 --- a/test/CodeGen/AArch64/fdiv-combine.ll +++ b/test/CodeGen/AArch64/fdiv-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=aarch64 < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-unknown-unknown < %s | FileCheck %s ; Following test cases check: ; a / D; b / D; c / D; @@ -6,8 +6,8 @@ ; recip = 1.0 / D; a * recip; b * recip; c * recip; define void @three_fdiv_float(float %D, float %a, float %b, float %c) #0 { ; CHECK-LABEL: three_fdiv_float: -; CHECK: fdiv -; CHECK-NEXT-NOT: fdiv +; CHECK: fdiv s +; CHECK-NOT: fdiv ; CHECK: fmul ; CHECK: fmul ; CHECK: fmul @@ -20,8 +20,8 @@ define void @three_fdiv_float(float %D, float %a, float %b, float %c) #0 { define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 { ; CHECK-LABEL: three_fdiv_double: -; CHECK: fdiv -; CHECK-NEXT-NOT: fdiv +; CHECK: fdiv d +; CHECK-NOT: fdiv ; CHECK: fmul ; CHECK: fmul ; CHECK: fmul @@ -34,8 +34,8 @@ define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 { define void @three_fdiv_4xfloat(<4 x float> %D, <4 x float> %a, <4 x float> %b, <4 x float> %c) #0 { ; CHECK-LABEL: three_fdiv_4xfloat: -; CHECK: fdiv -; CHECK-NEXT-NOT: fdiv +; CHECK: fdiv v +; CHECK-NOT: fdiv ; CHECK: fmul ; CHECK: fmul ; CHECK: fmul @@ -48,8 +48,8 @@ define void @three_fdiv_4xfloat(<4 x float> %D, <4 x float> %a, <4 x float> %b, define void @three_fdiv_2xdouble(<2 x double> %D, <2 x double> %a, <2 x double> %b, <2 x double> %c) #0 { ; CHECK-LABEL: three_fdiv_2xdouble: -; CHECK: fdiv -; CHECK-NEXT-NOT: fdiv +; CHECK: fdiv v +; CHECK-NOT: fdiv ; CHECK: fmul ; CHECK: fmul ; CHECK: fmul @@ -64,9 +64,9 @@ define void @three_fdiv_2xdouble(<2 x double> %D, <2 x double> %a, <2 x double> ; calculates a reciprocal. define void @two_fdiv_float(float %D, float %a, float %b) #0 { ; CHECK-LABEL: two_fdiv_float: -; CHECK: fdiv -; CHECK: fdiv -; CHECK-NEXT-NOT: fmul +; CHECK: fdiv s +; CHECK: fdiv s +; CHECK-NOT: fmul %div = fdiv float %a, %D %div1 = fdiv float %b, %D tail call void @foo_2f(float %div, float %div1) @@ -75,9 +75,9 @@ define void @two_fdiv_float(float %D, float %a, float %b) #0 { define void @two_fdiv_double(double %D, double %a, double %b) #0 { ; CHECK-LABEL: two_fdiv_double: -; CHECK: fdiv -; CHECK: fdiv -; CHECK-NEXT-NOT: fmul +; CHECK: fdiv d +; CHECK: fdiv d +; CHECK-NOT: fmul %div = fdiv double %a, %D %div1 = fdiv double %b, %D tail call void @foo_2d(double %div, double %div1) diff --git a/test/CodeGen/AArch64/fdiv_combine.ll b/test/CodeGen/AArch64/fdiv_combine.ll index 6f38a267ec3f..8ebee3c68287 100644 --- a/test/CodeGen/AArch64/fdiv_combine.ll +++ b/test/CodeGen/AArch64/fdiv_combine.ll @@ -38,7 +38,7 @@ entry: ; Test which should not fold due to power of 2 out of range. ; CHECK-LABEL: @test4 ; CHECK: scvtf.2s v0, v0 -; CHECK: movi.2s v1, #0x50, lsl #24 +; CHECK: movi.2s v1, #80, lsl #24 ; CHECK: fdiv.2s v0, v0, v1 ; CHECK: ret define <2 x float> @test4(<2 x i32> %in) { @@ -96,7 +96,7 @@ define <4 x float> @test8(<4 x i16> %in) { ; CHECK-LABEL: @test9 ; CHECK: ucvtf.2d v0, v0 ; CHECK: fcvtn v0.2s, v0.2d -; CHECK: movi.2s v1, #0x40, lsl #24 +; CHECK: movi.2s v1, #64, lsl #24 ; CHECK: fdiv.2s v0, v0, v1 ; CHECK: ret define <2 x float> @test9(<2 x i64> %in) { diff --git a/test/CodeGen/AArch64/fp-cond-sel.ll b/test/CodeGen/AArch64/fp-cond-sel.ll index b4f4d77cd0bc..4d9cb21ddc3d 100644 --- a/test/CodeGen/AArch64/fp-cond-sel.ll +++ b/test/CodeGen/AArch64/fp-cond-sel.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s @varfloat = global float 0.0 @vardouble = global double 0.0 @@ -12,8 +12,8 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) { %tst1 = icmp ugt i32 %lhs32, %rhs32 %val1 = select i1 %tst1, float 0.0, float 1.0 store float %val1, float* @varfloat -; CHECK: movi v[[FLT0:[0-9]+]].2d, #0 -; CHECK: fmov s[[FLT1:[0-9]+]], #1.0 +; CHECK-DAG: movi v[[FLT0:[0-9]+]].2d, #0 +; CHECK-DAG: fmov s[[FLT1:[0-9]+]], #1.0 ; CHECK: fcsel {{s[0-9]+}}, s[[FLT0]], s[[FLT1]], hi %rhs64 = sext i32 %rhs32 to i64 diff --git a/test/CodeGen/AArch64/fp16-v4-instructions.ll b/test/CodeGen/AArch64/fp16-v4-instructions.ll index b892f1902b03..b39ff08db39a 100644 --- a/test/CodeGen/AArch64/fp16-v4-instructions.ll +++ b/test/CodeGen/AArch64/fp16-v4-instructions.ll @@ -15,7 +15,7 @@ entry: define <4 x half> @build_h4(<4 x half> %a) { entry: ; CHECK-LABEL: build_h4: -; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd +; CHECK: mov [[GPR:w[0-9]+]], #15565 ; CHECK: dup v0.4h, [[GPR]] ret <4 x half> } @@ -176,7 +176,7 @@ define <4 x half> @sitofp_i64(<4 x i64> %a) #0 { define <4 x half> @uitofp_i8(<4 x i8> %a) #0 { ; CHECK-LABEL: uitofp_i8: -; CHECK-NEXT: bic v0.4h, #0xff, lsl #8 +; CHECK-NEXT: bic v0.4h, #255, lsl #8 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]] ; CHECK-NEXT: fcvtn v0.4h, [[OP2]] @@ -277,10 +277,10 @@ define <4 x i16> @fptoui_i16(<4 x half> %a) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, ne -; CHECK-DAG: csel {{.*}}, wzr, ne -; CHECK-DAG: csel {{.*}}, wzr, ne -; CHECK-DAG: csel {{.*}}, wzr, ne +; CHECK-DAG: csetm {{.*}}, ne +; CHECK-DAG: csetm {{.*}}, ne +; CHECK-DAG: csetm {{.*}}, ne +; CHECK-DAG: csetm {{.*}}, ne define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp une <4 x half> %a, %b ret <4 x i1> %1 @@ -296,14 +296,14 @@ define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, vs -; CHECK-DAG: csel {{.*}}, vs -; CHECK-DAG: csel {{.*}}, vs -; CHECK-DAG: csel {{.*}}, vs +; CHECK-DAG: csetm [[REG1:w[0-9]+]], eq +; CHECK-DAG: csetm [[REG2:w[0-9]+]], eq +; CHECK-DAG: csetm [[REG3:w[0-9]+]], eq +; CHECK-DAG: csetm [[REG4:w[0-9]+]], eq +; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, vc +; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, vc +; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, vc +; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, vc define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ueq <4 x half> %a, %b ret <4 x i1> %1 @@ -319,10 +319,10 @@ define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, hi -; CHECK-DAG: csel {{.*}}, wzr, hi -; CHECK-DAG: csel {{.*}}, wzr, hi -; CHECK-DAG: csel {{.*}}, wzr, hi +; CHECK-DAG: csetm {{.*}}, hi +; CHECK-DAG: csetm {{.*}}, hi +; CHECK-DAG: csetm {{.*}}, hi +; CHECK-DAG: csetm {{.*}}, hi define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ugt <4 x half> %a, %b ret <4 x i1> %1 @@ -338,10 +338,10 @@ define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, pl -; CHECK-DAG: csel {{.*}}, wzr, pl -; CHECK-DAG: csel {{.*}}, wzr, pl -; CHECK-DAG: csel {{.*}}, wzr, pl +; CHECK-DAG: csetm {{.*}}, pl +; CHECK-DAG: csetm {{.*}}, pl +; CHECK-DAG: csetm {{.*}}, pl +; CHECK-DAG: csetm {{.*}}, pl define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp uge <4 x half> %a, %b ret <4 x i1> %1 @@ -357,10 +357,10 @@ define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, lt -; CHECK-DAG: csel {{.*}}, wzr, lt -; CHECK-DAG: csel {{.*}}, wzr, lt -; CHECK-DAG: csel {{.*}}, wzr, lt +; CHECK-DAG: csetm {{.*}}, lt +; CHECK-DAG: csetm {{.*}}, lt +; CHECK-DAG: csetm {{.*}}, lt +; CHECK-DAG: csetm {{.*}}, lt define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ult <4 x half> %a, %b ret <4 x i1> %1 @@ -376,10 +376,10 @@ define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, le -; CHECK-DAG: csel {{.*}}, wzr, le -; CHECK-DAG: csel {{.*}}, wzr, le -; CHECK-DAG: csel {{.*}}, wzr, le +; CHECK-DAG: csetm {{.*}}, le +; CHECK-DAG: csetm {{.*}}, le +; CHECK-DAG: csetm {{.*}}, le +; CHECK-DAG: csetm {{.*}}, le define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ule <4 x half> %a, %b ret <4 x i1> %1 @@ -395,10 +395,10 @@ define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, vs -; CHECK-DAG: csel {{.*}}, wzr, vs -; CHECK-DAG: csel {{.*}}, wzr, vs -; CHECK-DAG: csel {{.*}}, wzr, vs +; CHECK-DAG: csetm {{.*}}, vs +; CHECK-DAG: csetm {{.*}}, vs +; CHECK-DAG: csetm {{.*}}, vs +; CHECK-DAG: csetm {{.*}}, vs define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp uno <4 x half> %a, %b ret <4 x i1> %1 @@ -414,14 +414,15 @@ define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, gt -; CHECK-DAG: csel {{.*}}, gt -; CHECK-DAG: csel {{.*}}, gt -; CHECK-DAG: csel {{.*}}, gt +; CHECK-DAG: csetm [[REG1:w[0-9]+]], mi +; CHECK-DAG: csetm [[REG2:w[0-9]+]], mi +; CHECK-DAG: csetm [[REG3:w[0-9]+]], mi +; CHECK-DAG: csetm [[REG4:w[0-9]+]], mi +; CHECK-DAG: csinv {{.*}}, [[REG1]], wzr, le +; CHECK-DAG: csinv {{.*}}, [[REG2]], wzr, le +; CHECK-DAG: csinv {{.*}}, [[REG3]], wzr, le +; CHECK-DAG: csinv {{.*}}, [[REG4]], wzr, le + define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp one <4 x half> %a, %b ret <4 x i1> %1 @@ -437,10 +438,10 @@ define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq -; CHECK-DAG: csel {{.*}}, wzr, eq +; CHECK-DAG: csetm {{.*}}, eq +; CHECK-DAG: csetm {{.*}}, eq +; CHECK-DAG: csetm {{.*}}, eq +; CHECK-DAG: csetm {{.*}}, eq define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp oeq <4 x half> %a, %b ret <4 x i1> %1 @@ -456,10 +457,10 @@ define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, gt -; CHECK-DAG: csel {{.*}}, wzr, gt -; CHECK-DAG: csel {{.*}}, wzr, gt -; CHECK-DAG: csel {{.*}}, wzr, gt +; CHECK-DAG: csetm {{.*}}, gt +; CHECK-DAG: csetm {{.*}}, gt +; CHECK-DAG: csetm {{.*}}, gt +; CHECK-DAG: csetm {{.*}}, gt define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ogt <4 x half> %a, %b ret <4 x i1> %1 @@ -475,10 +476,10 @@ define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, ge -; CHECK-DAG: csel {{.*}}, wzr, ge -; CHECK-DAG: csel {{.*}}, wzr, ge -; CHECK-DAG: csel {{.*}}, wzr, ge +; CHECK-DAG: csetm {{.*}}, ge +; CHECK-DAG: csetm {{.*}}, ge +; CHECK-DAG: csetm {{.*}}, ge +; CHECK-DAG: csetm {{.*}}, ge define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp oge <4 x half> %a, %b ret <4 x i1> %1 @@ -494,10 +495,10 @@ define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi -; CHECK-DAG: csel {{.*}}, wzr, mi +; CHECK-DAG: csetm {{.*}}, mi +; CHECK-DAG: csetm {{.*}}, mi +; CHECK-DAG: csetm {{.*}}, mi +; CHECK-DAG: csetm {{.*}}, mi define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp olt <4 x half> %a, %b ret <4 x i1> %1 @@ -513,10 +514,10 @@ define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, ls -; CHECK-DAG: csel {{.*}}, wzr, ls -; CHECK-DAG: csel {{.*}}, wzr, ls -; CHECK-DAG: csel {{.*}}, wzr, ls +; CHECK-DAG: csetm {{.*}}, ls +; CHECK-DAG: csetm {{.*}}, ls +; CHECK-DAG: csetm {{.*}}, ls +; CHECK-DAG: csetm {{.*}}, ls define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ole <4 x half> %a, %b ret <4 x i1> %1 @@ -532,10 +533,10 @@ define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 { ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt ; CHECK-DAG: fcvt -; CHECK-DAG: csel {{.*}}, wzr, vc -; CHECK-DAG: csel {{.*}}, wzr, vc -; CHECK-DAG: csel {{.*}}, wzr, vc -; CHECK-DAG: csel {{.*}}, wzr, vc +; CHECK-DAG: csetm {{.*}}, vc +; CHECK-DAG: csetm {{.*}}, vc +; CHECK-DAG: csetm {{.*}}, vc +; CHECK-DAG: csetm {{.*}}, vc define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 { %1 = fcmp ord <4 x half> %a, %b ret <4 x i1> %1 diff --git a/test/CodeGen/AArch64/fp16-vector-nvcast.ll b/test/CodeGen/AArch64/fp16-vector-nvcast.ll index 83e0df74c3da..018c88c5f3eb 100644 --- a/test/CodeGen/AArch64/fp16-vector-nvcast.ll +++ b/test/CodeGen/AArch64/fp16-vector-nvcast.ll @@ -3,7 +3,7 @@ ; Test pattern (v4f16 (AArch64NvCast (v2i32 FPR64:$src))) define void @nvcast_v2i32(<4 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v2i32: -; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #0xab, lsl #16 +; CHECK-NEXT: movi v[[REG:[0-9]+]].2s, #171, lsl #16 ; CHECK-NEXT: str d[[REG]], [x0] ; CHECK-NEXT: ret store volatile <4 x half> , <4 x half>* %a @@ -14,7 +14,7 @@ define void @nvcast_v2i32(<4 x half>* %a) #0 { ; Test pattern (v4f16 (AArch64NvCast (v4i16 FPR64:$src))) define void @nvcast_v4i16(<4 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v4i16: -; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #0xab +; CHECK-NEXT: movi v[[REG:[0-9]+]].4h, #171 ; CHECK-NEXT: str d[[REG]], [x0] ; CHECK-NEXT: ret store volatile <4 x half> , <4 x half>* %a @@ -25,7 +25,7 @@ define void @nvcast_v4i16(<4 x half>* %a) #0 { ; Test pattern (v4f16 (AArch64NvCast (v8i8 FPR64:$src))) define void @nvcast_v8i8(<4 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v8i8: -; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #0xab +; CHECK-NEXT: movi v[[REG:[0-9]+]].8b, #171 ; CHECK-NEXT: str d[[REG]], [x0] ; CHECK-NEXT: ret store volatile <4 x half> , <4 x half>* %a @@ -46,7 +46,7 @@ define void @nvcast_f64(<4 x half>* %a) #0 { ; Test pattern (v8f16 (AArch64NvCast (v4i32 FPR128:$src))) define void @nvcast_v4i32(<8 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v4i32: -; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #0xab, lsl #16 +; CHECK-NEXT: movi v[[REG:[0-9]+]].4s, #171, lsl #16 ; CHECK-NEXT: str q[[REG]], [x0] ; CHECK-NEXT: ret store volatile <8 x half> , <8 x half>* %a @@ -57,7 +57,7 @@ define void @nvcast_v4i32(<8 x half>* %a) #0 { ; Test pattern (v8f16 (AArch64NvCast (v8i16 FPR128:$src))) define void @nvcast_v8i16(<8 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v8i16: -; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #0xab +; CHECK-NEXT: movi v[[REG:[0-9]+]].8h, #171 ; CHECK-NEXT: str q[[REG]], [x0] ; CHECK-NEXT: ret store volatile <8 x half> , <8 x half>* %a @@ -68,7 +68,7 @@ define void @nvcast_v8i16(<8 x half>* %a) #0 { ; Test pattern (v8f16 (AArch64NvCast (v16i8 FPR128:$src))) define void @nvcast_v16i8(<8 x half>* %a) #0 { ; CHECK-LABEL: nvcast_v16i8: -; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #0xab +; CHECK-NEXT: movi v[[REG:[0-9]+]].16b, #171 ; CHECK-NEXT: str q[[REG]], [x0] ; CHECK-NEXT: ret store volatile <8 x half> , <8 x half>* %a diff --git a/test/CodeGen/AArch64/fpimm.ll b/test/CodeGen/AArch64/fpimm.ll index 6acb11108afc..b4faef750a2c 100644 --- a/test/CodeGen/AArch64/fpimm.ll +++ b/test/CodeGen/AArch64/fpimm.ll @@ -38,20 +38,19 @@ define void @check_double() { } ; LARGE-LABEL: check_float2 -; LARGE: movz [[REG:w[0-9]+]], #0x4049, lsl #16 -; LARGE-NEXT: movk [[REG]], #0xfdb +; LARGE: mov [[REG:w[0-9]+]], #1078525952 +; LARGE-NEXT: movk [[REG]], #4059 ; LARGE-NEXT: fmov s0, [[REG]] define float @check_float2() { ret float 3.14159274101257324218750 } ; LARGE-LABEL: check_double2 -; LARGE: movz [[REG:x[0-9]+]], #0x4009, lsl #48 -; LARGE-NEXT: movk [[REG]], #0x21fb, lsl #32 -; LARGE-NEXT: movk [[REG]], #0x5444, lsl #16 -; LARGE-NEXT: movk [[REG]], #0x2d18 +; LARGE: mov [[REG:x[0-9]+]], #4614219293217783808 +; LARGE-NEXT: movk [[REG]], #8699, lsl #32 +; LARGE-NEXT: movk [[REG]], #21572, lsl #16 +; LARGE-NEXT: movk [[REG]], #11544 ; LARGE-NEXT: fmov d0, [[REG]] define double @check_double2() { ret double 3.1415926535897931159979634685441851615905761718750 } - diff --git a/test/CodeGen/AArch64/func-argpassing.ll b/test/CodeGen/AArch64/func-argpassing.ll index 2ea13e388867..cf6545dab385 100644 --- a/test/CodeGen/AArch64/func-argpassing.ll +++ b/test/CodeGen/AArch64/func-argpassing.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-post-ra | FileCheck --check-prefix=CHECK %s +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -disable-post-ra | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 -disable-post-ra | FileCheck --check-prefix=CHECK-NOFP %s %myStruct = type { i64 , i8, i32 } diff --git a/test/CodeGen/AArch64/func-calls.ll b/test/CodeGen/AArch64/func-calls.ll index 2f45666ba13a..40ed607b06cc 100644 --- a/test/CodeGen/AArch64/func-calls.ll +++ b/test/CodeGen/AArch64/func-calls.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-neon | FileCheck --check-prefix=CHECK-NONEON %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64_be-none-linux-gnu | FileCheck --check-prefix=CHECK-BE %s @@ -89,11 +89,11 @@ define void @check_stack_args() { ; that varstruct is passed on the stack. Rather dependent on how a ; memcpy gets created, but the following works for now. -; CHECK-DAG: str {{q[0-9]+}}, [sp, #-16] +; CHECK-DAG: str {{q[0-9]+}}, [sp] ; CHECK-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0 ; CHECK: mov v0.16b, v[[FINAL_DOUBLE]].16b -; CHECK-NONEON-DAG: str {{q[0-9]+}}, [sp, #-16]! +; CHECK-NONEON-DAG: str {{q[0-9]+}}, [sp] ; CHECK-NONEON-DAG: fmov d[[FINAL_DOUBLE:[0-9]+]], #1.0 ; CHECK-NONEON: fmov d0, d[[FINAL_DOUBLE]] @@ -104,10 +104,10 @@ define void @check_stack_args() { float -2.0, float -8.0, float 16.0, float 1.0, float 64.0) -; CHECK: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16 +; CHECK: mov [[SIXTY_FOUR:w[0-9]+]], #1115684864 ; CHECK: str [[SIXTY_FOUR]], [sp] -; CHECK-NONEON: movz [[SIXTY_FOUR:w[0-9]+]], #0x4280, lsl #16 +; CHECK-NONEON: mov [[SIXTY_FOUR:w[0-9]+]], #1115684864 ; CHECK-NONEON: str [[SIXTY_FOUR]], [sp] ; CHECK: bl stacked_fpu @@ -139,9 +139,9 @@ define void @check_i128_align() { call void @check_i128_regalign(i32 0, i128 42) ; CHECK-NOT: mov x1 -; CHECK-LE: movz x2, #{{0x2a|42}} +; CHECK-LE: mov x2, #{{0x2a|42}} ; CHECK-LE: mov x3, xzr -; CHECK-BE: movz {{x|w}}3, #{{0x2a|42}} +; CHECK-BE: mov {{x|w}}3, #{{0x2a|42}} ; CHECK-BE: mov x2, xzr ; CHECK: bl check_i128_regalign diff --git a/test/CodeGen/AArch64/gep-nullptr.ll b/test/CodeGen/AArch64/gep-nullptr.ll new file mode 100644 index 000000000000..4c2bc504cd04 --- /dev/null +++ b/test/CodeGen/AArch64/gep-nullptr.ll @@ -0,0 +1,23 @@ +; RUN: llc -O3 -aarch64-gep-opt=true < %s |FileCheck %s +target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128" +target triple = "aarch64--linux-gnu" + +%structA = type { i8, i8, i8, i8, i8, i8, [4 x i8], i8, i8, [2 x i32], [2 x %unionMV], [4 x [2 x %unionMV]], [4 x [2 x %unionMV]], [4 x i8], i8*, i8*, i32, i8* } +%unionMV = type { i32 } + +; Function Attrs: nounwind +define void @test(%structA* %mi_block) { +entry: + br i1 undef, label %for.body13.us, label %if.else + +; Just make sure we don't get a compiler ICE due to dereferncing a nullptr. +; CHECK-LABEL: test +for.body13.us: ; preds = %entry + %indvars.iv.next40 = or i64 0, 1 + %packed4.i.us.1 = getelementptr inbounds %structA, %structA* %mi_block, i64 0, i32 11, i64 0, i64 %indvars.iv.next40, i32 0 + unreachable + +if.else: ; preds = %entry + ret void +} + diff --git a/test/CodeGen/AArch64/global-merge-3.ll b/test/CodeGen/AArch64/global-merge-3.ll index 6895380ca63e..481be4017b00 100644 --- a/test/CodeGen/AArch64/global-merge-3.ll +++ b/test/CodeGen/AArch64/global-merge-3.ll @@ -21,7 +21,7 @@ define void @f1(i32 %a1, i32 %a2, i32 %a3) { } ;CHECK: .type .L_MergedGlobals,@object // @_MergedGlobals -;CHECK: .align 4 +;CHECK: .p2align 4 ;CHECK: .L_MergedGlobals: ;CHECK: .size .L_MergedGlobals, 4004 @@ -29,7 +29,7 @@ define void @f1(i32 %a1, i32 %a2, i32 %a3) { ;CHECK: .local .L_MergedGlobals.1 ;CHECK: .comm .L_MergedGlobals.1,4000,16 -;CHECK-APPLE-IOS: .align 4 +;CHECK-APPLE-IOS: .p2align 4 ;CHECK-APPLE-IOS: l__MergedGlobals: ;CHECK-APPLE-IOS: .long 1 ;CHECK-APPLE-IOS: .space 4000 diff --git a/test/CodeGen/AArch64/global-merge-group-by-use.ll b/test/CodeGen/AArch64/global-merge-group-by-use.ll index 8b3fc97c9e2e..434c787b28da 100644 --- a/test/CodeGen/AArch64/global-merge-group-by-use.ll +++ b/test/CodeGen/AArch64/global-merge-group-by-use.ll @@ -64,8 +64,8 @@ define void @f3(i32 %a1, i32 %a2) #0 { define void @f4(i32 %a1, i32 %a2, i32 %a3) #0 { ; CHECK-NEXT: adrp x8, [[SET3]]@PAGE ; CHECK-NEXT: add x8, x8, [[SET3]]@PAGEOFF -; CHECK-NEXT: stp w0, w1, [x8, #4] -; CHECK-NEXT: str w2, [x8] +; CHECK-NEXT: stp w2, w0, [x8] +; CHECK-NEXT: str w1, [x8, #8] ; CHECK-NEXT: ret store i32 %a1, i32* @m4, align 4 store i32 %a2, i32* @n4, align 4 diff --git a/test/CodeGen/AArch64/half.ll b/test/CodeGen/AArch64/half.ll index d4cbbc918a84..154d85c9bb61 100644 --- a/test/CodeGen/AArch64/half.ll +++ b/test/CodeGen/AArch64/half.ll @@ -81,3 +81,15 @@ define void @test_trunc64(double %in, half* %addr) { store half %val16, half* %addr ret void } + +define i16 @test_fccmp(i1 %a) { +;CHECK-LABEL: test_fccmp: +;CHECK: fcmp + %cmp0 = fcmp ogt half 0xH3333, undef + %cmp1 = fcmp ogt half 0xH2222, undef + %x = select i1 %cmp0, i16 0, i16 undef + %or = or i1 %cmp1, %cmp0 + %y = select i1 %or, i16 4, i16 undef + %r = add i16 %x, %y + ret i16 %r +} diff --git a/test/CodeGen/AArch64/hints.ll b/test/CodeGen/AArch64/hints.ll index d7d9e23af1f1..f23c7b00f224 100644 --- a/test/CodeGen/AArch64/hints.ll +++ b/test/CodeGen/AArch64/hints.ll @@ -63,5 +63,5 @@ entry: } ; CHECK-LABEL: hint_undefined -; CHECK: hint #0x8 +; CHECK: hint #8 diff --git a/test/CodeGen/AArch64/inlineasm-X-allocation.ll b/test/CodeGen/AArch64/inlineasm-X-allocation.ll new file mode 100644 index 000000000000..1d7a24e3e6e7 --- /dev/null +++ b/test/CodeGen/AArch64/inlineasm-X-allocation.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64-none-eabi -mattr=-fp-armv8 %s -o - | FileCheck %s -check-prefix=nofp + +; In the novfp case, the compiler is forced to assign a core register, +; even if the input is a float. + +; nofp-LABEL: f1 +; nofp-CHECK: ldr x0, [sp] + +; This can be generated by a function such as: +; void f1(float f) {asm volatile ("ldr $0, [sp]" : : "X" (f));} + +define void @f1(float %f) { +entry: + call void asm sideeffect "ldr $0, [sp]", "X" (float %f) nounwind + + ret void +} diff --git a/test/CodeGen/AArch64/inlineasm-X-constraint.ll b/test/CodeGen/AArch64/inlineasm-X-constraint.ll new file mode 100644 index 000000000000..77652cc071ef --- /dev/null +++ b/test/CodeGen/AArch64/inlineasm-X-constraint.ll @@ -0,0 +1,152 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o - | FileCheck %s + +; The following functions test the use case where an X constraint is used to +; add a dependency between an assembly instruction (vmsr in this case) and +; another instruction. In each function, we use a different type for the +; X constraint argument. +; +; We can something similar from the following C code: +; double f1(double f, int pscr_value) { +; asm volatile("msr fpsr,%1" : "=X" ((f)): "r" (pscr_value)); +; return f+f; +; } + +; CHECK-LABEL: f1 +; CHECK: msr FPSR +; CHECK: fadd d + +define double @f1(double %f, i32 %pscr_value) { +entry: + %f.addr = alloca double, align 8 + store double %f, double* %f.addr, align 8 + call void asm sideeffect "msr fpsr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwind + %0 = load double, double* %f.addr, align 8 + %add = fadd double %0, %0 + ret double %add +} + +; int f2(int f, int pscr_value) { +; asm volatile("msr fpsr,$1" : "=X" ((f)): "r" (pscr_value)); +; return f*f; +; } + +; CHECK-LABEL: f2 +; CHECK: msr FPSR +; CHECK: mul +define i32 @f2(i32 %f, i32 %pscr_value) { +entry: + %f.addr = alloca i32, align 4 + store i32 %f, i32* %f.addr, align 4 + call void asm sideeffect "msr fpsr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind + %0 = load i32, i32* %f.addr, align 4 + %mul = mul i32 %0, %0 + ret i32 %mul +} + +; typedef signed char int8_t; +; typedef __attribute__((neon_vector_type(8))) int8_t int8x8_t; +; void f3 (void) +; { +; int8x8_t vector_res_int8x8; +; unsigned int fpscr; +; asm volatile ("msr fpsr,$1" : "=X" ((vector_res_int8x8)) : "r" (fpscr)); +; return vector_res_int8x8 * vector_res_int8x8; +; } + +; CHECK-LABEL: f3 +; CHECK: msr FPSR +; CHECK: mul +define <8 x i8> @f3() { +entry: + %vector_res_int8x8 = alloca <8 x i8>, align 8 + %0 = getelementptr inbounds <8 x i8>, <8 x i8>* %vector_res_int8x8, i32 0, i32 0 + call void asm sideeffect "msr fpsr,$1", "=*X,r"(<8 x i8>* nonnull %vector_res_int8x8, i32 undef) nounwind + %1 = load <8 x i8>, <8 x i8>* %vector_res_int8x8, align 8 + %mul = mul <8 x i8> %1, %1 + ret <8 x i8> %mul +} + +; We can emit integer constants. +; We can get this from: +; void f() { +; int x = 2; +; asm volatile ("add x0, x0, %0" : : "X" (x)); +; } +; +; CHECK-LABEL: f4 +; CHECK: add x0, x0, #2 +define void @f4() { +entry: + tail call void asm sideeffect "add x0, x0, $0", "X"(i32 2) + ret void +} + +; We can emit function labels. This is equivalent to the following C code: +; void f(void) { +; void (*x)(void) = &foo; +; asm volatile ("bl %0" : : "X" (x)); +; } +; CHECK-LABEL: f5 +; CHECK: bl f4 +define void @f5() { +entry: + tail call void asm sideeffect "bl $0", "X"(void ()* nonnull @f4) + ret void +} + +declare void @foo(...) + +; This tests the behavior of the X constraint when used on functions pointers, +; or functions with a cast. In the first asm call we figure out that this +; is a function pointer and emit the label. However, in the second asm call +; we can't see through the bitcast and we end up having to lower this constraint +; to something else. This is not ideal, but it is a correct behaviour according +; to the definition of the X constraint. +; +; In this case (and other cases where we could have emitted something else), +; what we're doing with the X constraint is not particularly useful either, +; since the user could have used "r" in this situation for the same effect. + +; CHECK-LABEL: f6 +; CHECK: bl foo +; CHECK: br x + +define void @f6() nounwind { +entry: + tail call void asm sideeffect "bl $0", "X"(void (...)* @foo) nounwind + tail call void asm sideeffect "br $0", "X"(void (...)* bitcast (void ()* @f4 to void (...)*)) nounwind + ret void +} + +; The following IR can be generated from C code with a function like: +; void a() { +; void* a = &&A; +; asm volatile ("bl %0" : : "X" (a)); +; A: +; return; +; } +; +; Ideally this would give the block address of bb, but it requires us to see +; through blockaddress, which we can't do at the moment. This might break some +; existing use cases where a user would expect to get a block label and instead +; gets the block address in a register. However, note that according to the +; "no constraints" definition this behaviour is correct (although not very nice). + +; CHECK-LABEL: f7 +; CHECK: bl +define void @f7() { + call void asm sideeffect "br $0", "X"( i8* blockaddress(@f7, %bb) ) + br label %bb +bb: + ret void +} + +; If we use a constraint "=*X", we should get a store back to *%x (in x0). +; CHECK-LABEL: f8 +; CHECK: add [[Dest:x[0-9]+]], x0, x0 +; CHECK: str [[Dest]], [x0] +define void @f8(i64 *%x) { +entry: + tail call void asm sideeffect "add $0, x0, x0", "=*X"(i64 *%x) + ret void +} diff --git a/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll b/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll index 645214ac8ec7..ca24fc9c8807 100644 --- a/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll +++ b/test/CodeGen/AArch64/inlineasm-ldr-pseudo.ll @@ -5,7 +5,7 @@ ; RUN: llc -mtriple=aarch64 < %s -filetype=obj | llvm-objdump -arch=aarch64 -d - | FileCheck %s ; CHECK-LABEL: foo: -; CHECK: a0 79 95 d2 movz x0, #0xabcd +; CHECK: a0 79 95 d2 mov x0, #43981 ; CHECK: c0 03 5f d6 ret define i32 @foo() nounwind { entry: @@ -22,5 +22,3 @@ entry: %0 = tail call i32 asm sideeffect "ldr $0,=0x10001", "=r"() nounwind ret i32 %0 } - - diff --git a/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll b/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll new file mode 100644 index 000000000000..f65694ab80a1 --- /dev/null +++ b/test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll @@ -0,0 +1,125 @@ +; RUN: llc < %s -march=aarch64 -aarch64-neon-syntax=apple -aarch64-stp-suppress=false -verify-machineinstrs -asm-verbose=false | FileCheck %s + +; CHECK-LABEL: test_strd_sturd: +; CHECK-NEXT: stp d0, d1, [x0, #-8] +; CHECK-NEXT: ret +define void @test_strd_sturd(float* %ptr, <2 x float> %v1, <2 x float> %v2) #0 { + %tmp1 = bitcast float* %ptr to <2 x float>* + store <2 x float> %v2, <2 x float>* %tmp1, align 16 + %add.ptr = getelementptr inbounds float, float* %ptr, i64 -2 + %tmp = bitcast float* %add.ptr to <2 x float>* + store <2 x float> %v1, <2 x float>* %tmp, align 16 + ret void +} + +; CHECK-LABEL: test_sturd_strd: +; CHECK-NEXT: stp d0, d1, [x0, #-8] +; CHECK-NEXT: ret +define void @test_sturd_strd(float* %ptr, <2 x float> %v1, <2 x float> %v2) #0 { + %add.ptr = getelementptr inbounds float, float* %ptr, i64 -2 + %tmp = bitcast float* %add.ptr to <2 x float>* + store <2 x float> %v1, <2 x float>* %tmp, align 16 + %tmp1 = bitcast float* %ptr to <2 x float>* + store <2 x float> %v2, <2 x float>* %tmp1, align 16 + ret void +} + +; CHECK-LABEL: test_strq_sturq: +; CHECK-NEXT: stp q0, q1, [x0, #-16] +; CHECK-NEXT: ret +define void @test_strq_sturq(double* %ptr, <2 x double> %v1, <2 x double> %v2) #0 { + %tmp1 = bitcast double* %ptr to <2 x double>* + store <2 x double> %v2, <2 x double>* %tmp1, align 16 + %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2 + %tmp = bitcast double* %add.ptr to <2 x double>* + store <2 x double> %v1, <2 x double>* %tmp, align 16 + ret void +} + +; CHECK-LABEL: test_sturq_strq: +; CHECK-NEXT: stp q0, q1, [x0, #-16] +; CHECK-NEXT: ret +define void @test_sturq_strq(double* %ptr, <2 x double> %v1, <2 x double> %v2) #0 { + %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2 + %tmp = bitcast double* %add.ptr to <2 x double>* + store <2 x double> %v1, <2 x double>* %tmp, align 16 + %tmp1 = bitcast double* %ptr to <2 x double>* + store <2 x double> %v2, <2 x double>* %tmp1, align 16 + ret void +} + +; CHECK-LABEL: test_ldrx_ldurx: +; CHECK-NEXT: ldp [[V0:x[0-9]+]], [[V1:x[0-9]+]], [x0, #-8] +; CHECK-NEXT: add x0, [[V0]], [[V1]] +; CHECK-NEXT: ret +define i64 @test_ldrx_ldurx(i64* %p) #0 { + %tmp = load i64, i64* %p, align 4 + %add.ptr = getelementptr inbounds i64, i64* %p, i64 -1 + %tmp1 = load i64, i64* %add.ptr, align 4 + %add = add nsw i64 %tmp1, %tmp + ret i64 %add +} + +; CHECK-LABEL: test_ldurx_ldrx: +; CHECK-NEXT: ldp [[V0:x[0-9]+]], [[V1:x[0-9]+]], [x0, #-8] +; CHECK-NEXT: add x0, [[V0]], [[V1]] +; CHECK-NEXT: ret +define i64 @test_ldurx_ldrx(i64* %p) #0 { + %add.ptr = getelementptr inbounds i64, i64* %p, i64 -1 + %tmp1 = load i64, i64* %add.ptr, align 4 + %tmp = load i64, i64* %p, align 4 + %add = add nsw i64 %tmp1, %tmp + ret i64 %add +} + +; CHECK-LABEL: test_ldrsw_ldursw: +; CHECK-NEXT: ldpsw [[V0:x[0-9]+]], [[V1:x[0-9]+]], [x0, #-4] +; CHECK-NEXT: add x0, [[V0]], [[V1]] +; CHECK-NEXT: ret +define i64 @test_ldrsw_ldursw(i32* %p) #0 { + %tmp = load i32, i32* %p, align 4 + %add.ptr = getelementptr inbounds i32, i32* %p, i64 -1 + %tmp1 = load i32, i32* %add.ptr, align 4 + %sexttmp = sext i32 %tmp to i64 + %sexttmp1 = sext i32 %tmp1 to i64 + %add = add nsw i64 %sexttmp1, %sexttmp + ret i64 %add +} + +; Also make sure we only match valid offsets. +; CHECK-LABEL: test_ldrq_ldruq_invalidoffset: +; CHECK-NEXT: ldr q[[V0:[0-9]+]], [x0] +; CHECK-NEXT: ldur q[[V1:[0-9]+]], [x0, #24] +; CHECK-NEXT: add.2d v0, v[[V0]], v[[V1]] +; CHECK-NEXT: ret +define <2 x i64> @test_ldrq_ldruq_invalidoffset(i64* %p) #0 { + %a1 = bitcast i64* %p to <2 x i64>* + %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8 + %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 3 + %a2 = bitcast i64* %add.ptr2 to <2 x i64>* + %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8 + %add = add nsw <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %add +} + +; Pair an unscaled store with a scaled store where the scaled store has a +; non-zero offset. This should not hit an assert. +; CHECK-LABEL: test_stur_str_no_assert +; CHECK: stp xzr, xzr, [sp, #16] +; CHECK: ret +define void @test_stur_str_no_assert() #0 { +entry: + %a1 = alloca i64, align 4 + %a2 = alloca [12 x i8], align 4 + %0 = bitcast i64* %a1 to i8* + %C = getelementptr inbounds [12 x i8], [12 x i8]* %a2, i64 0, i64 4 + %1 = bitcast i8* %C to i64* + store i64 0, i64* %1, align 4 + call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 8, i32 8, i1 false) + ret void +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) + + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AArch64/lit.local.cfg b/test/CodeGen/AArch64/lit.local.cfg index f4626c7e0a43..f4f77c5aa312 100644 --- a/test/CodeGen/AArch64/lit.local.cfg +++ b/test/CodeGen/AArch64/lit.local.cfg @@ -1,7 +1,5 @@ import re -config.suffixes = ['.ll'] - if not 'AArch64' in config.root.targets: config.unsupported = True diff --git a/test/CodeGen/AArch64/local_vars.ll b/test/CodeGen/AArch64/local_vars.ll index 332d660eef36..6e33ab2d0beb 100644 --- a/test/CodeGen/AArch64/local_vars.ll +++ b/test/CodeGen/AArch64/local_vars.ll @@ -24,24 +24,25 @@ define void @trivial_func() nounwind { } define void @trivial_fp_func() { -; CHECK-WITHFP-AARCH64-LABEL: trivial_fp_func: -; CHECK-WITHFP-AARCH64: sub sp, sp, #16 -; CHECK-WITHFP-AARCH64: stp x29, x30, [sp] -; CHECK-WITHFP-AARCH64-NEXT: mov x29, sp +; CHECK-LABEL: trivial_fp_func: +; CHECK: str x30, [sp, #-16]! +; CHECK-NOT: mov x29, sp ; CHECK-WITHFP-ARM64-LABEL: trivial_fp_func: ; CHECK-WITHFP-ARM64: stp x29, x30, [sp, #-16]! ; CHECK-WITHFP-ARM64-NEXT: mov x29, sp ; Dont't really care, but it would be a Bad Thing if this came after the epilogue. +; CHECK-WITHFP-ARM64: bl foo ; CHECK: bl foo call void @foo() ret void -; CHECK-WITHFP: ldp x29, x30, [sp] -; CHECK-WITHFP: add sp, sp, #16 +; CHECK: ldr x30, [sp], #16 +; CHECK-NEXT: ret -; CHECK-WITHFP: ret +; CHECK-WITHFP-ARM64: ldp x29, x30, [sp], #16 +; CHECK-WITHFP-ARM64-NEXT: ret } define void @stack_local() { diff --git a/test/CodeGen/AArch64/logical-imm.ll b/test/CodeGen/AArch64/logical-imm.ll index a5e4a9956de7..6f562230d937 100644 --- a/test/CodeGen/AArch64/logical-imm.ll +++ b/test/CodeGen/AArch64/logical-imm.ll @@ -73,11 +73,11 @@ define void @test_mov(i32 %in32, i64 %in64) { ; CHECK-LABEL: test_mov: %val0 = add i32 %in32, 2863311530 store i32 %val0, i32* @var32 -; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa +; CHECK: mov {{w[0-9]+}}, #-1431655766 %val1 = add i64 %in64, 11068046444225730969 store i64 %val1, i64* @var64 -; CHECK: orr {{x[0-9]+}}, xzr, #0x9999999999999999 +; CHECK: mov {{x[0-9]+}}, #-7378697629483820647 ret void ; CHECK: ret diff --git a/test/CodeGen/AArch64/lower-range-metadata-func-call.ll b/test/CodeGen/AArch64/lower-range-metadata-func-call.ll new file mode 100644 index 000000000000..fd4b2f5ba305 --- /dev/null +++ b/test/CodeGen/AArch64/lower-range-metadata-func-call.ll @@ -0,0 +1,44 @@ +; RUN: llc -march=aarch64 -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s + +; and can be eliminated +; CHECK-LABEL: {{^}}test_call_known_max_range: +; CHECK: bl foo +; CHECK-NOT: and +; CHECK: ret +define i32 @test_call_known_max_range() #0 { +entry: + %id = tail call i32 @foo(), !range !0 + %and = and i32 %id, 1023 + ret i32 %and +} + +; CHECK-LABEL: {{^}}test_call_known_trunc_1_bit_range: +; CHECK: bl foo +; CHECK: and w{{[0-9]+}}, w0, #0x1ff +; CHECK: ret +define i32 @test_call_known_trunc_1_bit_range() #0 { +entry: + %id = tail call i32 @foo(), !range !0 + %and = and i32 %id, 511 + ret i32 %and +} + +; CHECK-LABEL: {{^}}test_call_known_max_range_m1: +; CHECK: bl foo +; CHECK: and w{{[0-9]+}}, w0, #0xff +; CHECK: ret +define i32 @test_call_known_max_range_m1() #0 { +entry: + %id = tail call i32 @foo(), !range !1 + %and = and i32 %id, 255 + ret i32 %and +} + + +declare i32 @foo() + +attributes #0 = { norecurse nounwind } +attributes #1 = { nounwind readnone } + +!0 = !{i32 0, i32 1024} +!1 = !{i32 0, i32 1023} diff --git a/test/CodeGen/AArch64/machine-combiner.ll b/test/CodeGen/AArch64/machine-combiner.ll index 56a742fd6c3a..0bd416ad1721 100644 --- a/test/CodeGen/AArch64/machine-combiner.ll +++ b/test/CodeGen/AArch64/machine-combiner.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-post-ra < %s | FileCheck %s ; Verify that the first two adds are independent regardless of how the inputs are ; commuted. The destination registers are used as source registers for the third add. diff --git a/test/CodeGen/AArch64/machine-copy-remove.ll b/test/CodeGen/AArch64/machine-copy-remove.ll new file mode 100644 index 000000000000..75954f83c19c --- /dev/null +++ b/test/CodeGen/AArch64/machine-copy-remove.ll @@ -0,0 +1,94 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: f_XX: +; CHECK: cbz x[[REG:[0-9]+]], [[BB:.LBB.*]] +; CHECK: [[BB]]: +; CHECK-NOT: mov x[[REG]], xzr +define i64 @f_XX(i64 %n, i64* nocapture readonly %P) { +entry: + %tobool = icmp eq i64 %n, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i64, i64* %P + br label %if.end + +if.end: ; preds = %entry, %if.then + %a.0 = phi i64 [ %0, %if.then ], [ 0, %entry ] + ret i64 %a.0 +} + +; CHECK-LABEL: f_WW: +; CHECK: cbz w[[REG:[0-9]+]], [[BB:.LBB.*]] +; CHECK: [[BB]]: +; CHECK-NOT: mov w[[REG]], wzr +define i32 @f_WW(i32 %n, i32* nocapture readonly %P) { +entry: + %tobool = icmp eq i32 %n, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i32, i32* %P + br label %if.end + +if.end: ; preds = %entry, %if.then + %a.0 = phi i32 [ %0, %if.then ], [ 0, %entry ] + ret i32 %a.0 +} + +; CHECK-LABEL: f_XW: +; CHECK: cbz x[[REG:[0-9]+]], [[BB:.LBB.*]] +; CHECK: [[BB]]: +; CHECK-NOT: mov w[[REG]], wzr +define i32 @f_XW(i64 %n, i32* nocapture readonly %P) { +entry: + %tobool = icmp eq i64 %n, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i32, i32* %P + br label %if.end + +if.end: ; preds = %entry, %if.then + %a.0 = phi i32 [ %0, %if.then ], [ 0, %entry ] + ret i32 %a.0 +} + +; CHECK-LABEL: f_WX: +; CHECK: cbz w[[REG:[0-9]+]], [[BB:.LBB.*]] +; CHECK: [[BB]]: +; CHECK: mov x[[REG]], xzr +; Do not remove the mov in this case because we do not know if the upper bits +; of the X register are zero. +define i64 @f_WX(i32 %n, i64* nocapture readonly %P) { +entry: + %tobool = icmp eq i32 %n, 0 + br i1 %tobool, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i64, i64* %P + br label %if.end + +if.end: ; preds = %entry, %if.then + %a.0 = phi i64 [ %0, %if.then ], [ 0, %entry ] + ret i64 %a.0 +} + +; CHECK-LABEL: test_superreg: +; CHECK: cbz x[[REG:[0-9]+]], [[BB:.LBB.*]] +; CHECK: [[BB]]: +; CHECK: str x[[REG]], [x1] +; CHECK-NOT: mov w[[REG]], wzr +; Because we returned w0 but x0 was marked live-in to the block, we didn't +; remove the on the str leading to a verification failure. +define i32 @test_superreg(i64 %in, i64* %dest) { + %tst = icmp eq i64 %in, 0 + br i1 %tst, label %true, label %false + +false: + ret i32 42 + +true: + store volatile i64 %in, i64* %dest + ret i32 0 +} diff --git a/test/CodeGen/AArch64/merge-store-dependency.ll b/test/CodeGen/AArch64/merge-store-dependency.ll new file mode 100644 index 000000000000..c68cee91a3cf --- /dev/null +++ b/test/CodeGen/AArch64/merge-store-dependency.ll @@ -0,0 +1,63 @@ +; RUN: llc -mcpu cortex-a53 -march aarch64 %s -o - | FileCheck %s --check-prefix=A53 + +; PR26827 - Merge stores causes wrong dependency. +%struct1 = type { %struct1*, %struct1*, i32, i32, i16, i16, void (i32, i32, i8*)*, i8* } +@gv0 = internal unnamed_addr global i32 0, align 4 +@gv1 = internal unnamed_addr global %struct1** null, align 8 + +define void @test(%struct1* %fde, i32 %fd, void (i32, i32, i8*)* %func, i8* %arg) { +;CHECK-LABEL: test +entry: +; A53: mov [[DATA:w[0-9]+]], w1 +; A53: str q{{[0-9]+}}, {{.*}} +; A53: str q{{[0-9]+}}, {{.*}} +; A53: str [[DATA]], {{.*}} + + %0 = bitcast %struct1* %fde to i8* + tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 40, i32 8, i1 false) + %state = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 4 + store i16 256, i16* %state, align 8 + %fd1 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 2 + store i32 %fd, i32* %fd1, align 8 + %force_eof = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 3 + store i32 0, i32* %force_eof, align 4 + %func2 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 6 + store void (i32, i32, i8*)* %func, void (i32, i32, i8*)** %func2, align 8 + %arg3 = getelementptr inbounds %struct1, %struct1* %fde, i64 0, i32 7 + store i8* %arg, i8** %arg3, align 8 + %call = tail call i32 (i32, i32, ...) @fcntl(i32 %fd, i32 4, i8* %0) #6 + %1 = load i32, i32* %fd1, align 8 + %cmp.i = icmp slt i32 %1, 0 + br i1 %cmp.i, label %if.then.i, label %while.body.i.preheader +if.then.i: + unreachable + +while.body.i.preheader: + %2 = load i32, i32* @gv0, align 4 + %3 = icmp eq i32* %fd1, @gv0 + br i1 %3, label %while.body.i.split, label %while.body.i.split.ver.us.preheader + +while.body.i.split.ver.us.preheader: + br label %while.body.i.split.ver.us + +while.body.i.split.ver.us: + %.reg2mem21.0 = phi i32 [ %mul.i.ver.us, %while.body.i.split.ver.us ], [ %2, %while.body.i.split.ver.us.preheader ] + %mul.i.ver.us = shl nsw i32 %.reg2mem21.0, 1 + %4 = icmp sgt i32 %mul.i.ver.us, %1 + br i1 %4, label %while.end.i, label %while.body.i.split.ver.us + +while.body.i.split: + br label %while.body.i.split + +while.end.i: + %call.i = tail call i8* @foo() + store i8* %call.i, i8** bitcast (%struct1*** @gv1 to i8**), align 8 + br label %exit + +exit: + ret void +} + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) +declare i32 @fcntl(i32, i32, ...) +declare noalias i8* @foo() diff --git a/test/CodeGen/AArch64/merge-store.ll b/test/CodeGen/AArch64/merge-store.ll index 86f5edd5da1d..981d16f762ff 100644 --- a/test/CodeGen/AArch64/merge-store.ll +++ b/test/CodeGen/AArch64/merge-store.ll @@ -1,5 +1,5 @@ -; RUN: llc -march aarch64 %s -o - | FileCheck %s -; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mcpu=cyclone | FileCheck %s --check-prefix=CYCLONE +; RUN: llc -mtriple=aarch64-unknown-unknown %s -mcpu=cyclone -o - | FileCheck %s --check-prefix=CYCLONE --check-prefix=CHECK +; RUN: llc -march aarch64 %s -mattr=-slow-misaligned-128store -o - | FileCheck %s --check-prefix=MISALIGNED --check-prefix=CHECK @g0 = external global <3 x float>, align 16 @g1 = external global <3 x float>, align 4 @@ -38,9 +38,12 @@ define void @merge_vec_extract_stores(<4 x float> %v1, <2 x float>* %ptr) { store <2 x float> %shuffle1, <2 x float>* %idx1, align 8 ret void -; CHECK-LABEL: merge_vec_extract_stores -; CHECK: stur q0, [x0, #24] -; CHECK-NEXT: ret +; MISALIGNED-LABEL: merge_vec_extract_stores +; MISALIGNED: stur q0, [x0, #24] +; MISALIGNED-NEXT: ret + +; FIXME: Ideally we would like to use a generic target for this test, but this relies +; on suppressing store pairs. ; CYCLONE-LABEL: merge_vec_extract_stores ; CYCLONE: ext v1.16b, v0.16b, v0.16b, #8 diff --git a/test/CodeGen/AArch64/misched-fusion.ll b/test/CodeGen/AArch64/misched-fusion.ll index d38869329034..0f4c0ac84ce5 100644 --- a/test/CodeGen/AArch64/misched-fusion.ll +++ b/test/CodeGen/AArch64/misched-fusion.ll @@ -1,4 +1,6 @@ +; RUN: llc -o - %s -mattr=+macroop-fusion,+use-postra-scheduler | FileCheck %s ; RUN: llc -o - %s -mcpu=cyclone | FileCheck %s + target triple = "arm64-apple-ios" declare void @foobar(i32 %v0, i32 %v1) @@ -8,12 +10,12 @@ declare void @foobar(i32 %v0, i32 %v1) ; CHECK: add w[[ADDRES:[0-9]+]], w1, #7 ; CHECK: sub w[[SUBRES:[0-9]+]], w0, #13 ; CHECK-NEXT: cbnz w[[SUBRES]], [[SKIPBLOCK:LBB[0-9_]+]] -; CHECK: mov x0, x[[ADDRES]] -; CHECK: mov x1, x[[SUBRES]] +; CHECK: mov [[REGTY:[x,w]]]0, [[REGTY]][[ADDRES]] +; CHECK: mov [[REGTY]]1, [[REGTY]][[SUBRES]] ; CHECK: bl _foobar ; CHECK: [[SKIPBLOCK]]: -; CHECK: mov x0, x[[SUBRES]] -; CHECK: mov x1, x[[ADDRES]] +; CHECK: mov [[REGTY]]0, [[REGTY]][[SUBRES]] +; CHECK: mov [[REGTY]]1, [[REGTY]][[ADDRES]] ; CHECK: bl _foobar define void @test_sub_cbz(i32 %a0, i32 %a1) { entry: diff --git a/test/CodeGen/AArch64/movimm-wzr.mir b/test/CodeGen/AArch64/movimm-wzr.mir new file mode 100644 index 000000000000..d54e7bef54cd --- /dev/null +++ b/test/CodeGen/AArch64/movimm-wzr.mir @@ -0,0 +1,46 @@ +# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - 2>&1 | FileCheck %s + +--- | + ; ModuleID = 'simple.ll' + source_filename = "simple.ll" + target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--linux-gnu" + + define i32 @test_mov_0() { + ret i32 42 + } + +... +--- +name: test_mov_0 +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: false +tracksSubRegLiveness: false +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0 (%ir-block.0): + %wzr = MOVi32imm 42 + %xzr = MOVi64imm 42 + RET_ReallyLR implicit killed %w0 + +... + +# CHECK: bb.0 +# CHECK-NEXT: RET %lr diff --git a/test/CodeGen/AArch64/movw-consts.ll b/test/CodeGen/AArch64/movw-consts.ll index 93c181271755..def6072e0bca 100644 --- a/test/CodeGen/AArch64/movw-consts.ll +++ b/test/CodeGen/AArch64/movw-consts.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK +; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s define i64 @test0() { ; CHECK-LABEL: test0: @@ -53,19 +53,19 @@ define i64 @test7() { ; couldn't. Useful even for i64 define i64 @test8() { ; CHECK-LABEL: test8: -; CHECK: movn w0, #{{60875|0xedcb}} +; CHECK: mov w0, #-60876 ret i64 4294906420 } define i64 @test9() { ; CHECK-LABEL: test9: -; CHECK: movn x0, #0 +; CHECK: mov x0, #-1 ret i64 -1 } define i64 @test10() { ; CHECK-LABEL: test10: -; CHECK: movn x0, #{{60875|0xedcb}}, lsl #16 +; CHECK: mov x0, #-3989504001 ret i64 18446744069720047615 } @@ -110,7 +110,7 @@ define void @test15() { define void @test16() { ; CHECK-LABEL: test16: -; CHECK: movn {{w[0-9]+}}, #0 +; CHECK: mov {{w[0-9]+}}, #-1 store i32 -1, i32* @var32 ret void } diff --git a/test/CodeGen/AArch64/neg-imm.ll b/test/CodeGen/AArch64/neg-imm.ll new file mode 100644 index 000000000000..375d3dbfd0d5 --- /dev/null +++ b/test/CodeGen/AArch64/neg-imm.ll @@ -0,0 +1,46 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s +; LSR used to pick a sub-optimal solution due to the target responding +; conservatively to isLegalAddImmediate for negative values. + +declare void @foo(i32) + +define void @test(i32 %px) { +; CHECK_LABEL: test: +; CHECK_LABEL: %entry +; CHECK: subs +; CHECK-NEXT: csel +entry: + %sub = add nsw i32 %px, -1 + %cmp = icmp slt i32 %px, 1 + %.sub = select i1 %cmp, i32 0, i32 %sub + br label %for.body + +for.body: +; CHECK_LABEL: %for.body +; CHECK: cmp +; CHECK-NEXT: b.eq +; CHECK-LABEL: %if.then3 + %x.015 = phi i32 [ %inc, %for.inc ], [ %.sub, %entry ] + %cmp2 = icmp eq i32 %x.015, %px + br i1 %cmp2, label %for.inc, label %if.then3 + +if.then3: + tail call void @foo(i32 %x.015) + br label %for.inc + +for.inc: +; CHECK_LABEL: %for.inc +; CHECK: add +; CHECK-NEXT: cmp +; CHECK: b.le +; CHECK_LABEL: %for.cond.cleanup + %inc = add nsw i32 %x.015, 1 + %cmp1 = icmp sgt i32 %x.015, %px + br i1 %cmp1, label %for.cond.cleanup.loopexit, label %for.body + +for.cond.cleanup.loopexit: + br label %for.cond.cleanup + +for.cond.cleanup: + ret void +} diff --git a/test/CodeGen/AArch64/neon-compare-instructions.ll b/test/CodeGen/AArch64/neon-compare-instructions.ll index 6d89dfbacf41..887cb5dd698a 100644 --- a/test/CodeGen/AArch64/neon-compare-instructions.ll +++ b/test/CodeGen/AArch64/neon-compare-instructions.ll @@ -802,6 +802,63 @@ define <2 x i64> @cmgez2xi64(<2 x i64> %A) { } +define <8 x i8> @cmgez8xi8_alt(<8 x i8> %A) { +; CHECK-LABEL: cmgez8xi8_alt: +; CHECK: cmge {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} + %sign = ashr <8 x i8> %A, + %not = xor <8 x i8> %sign, + ret <8 x i8> %not +} + +define <16 x i8> @cmgez16xi8_alt(<16 x i8> %A) { +; CHECK-LABEL: cmgez16xi8_alt: +; CHECK: cmge {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}} + %sign = ashr <16 x i8> %A, + %not = xor <16 x i8> %sign, + ret <16 x i8> %not +} + +define <4 x i16> @cmgez4xi16_alt(<4 x i16> %A) { +; CHECK-LABEL: cmgez4xi16_alt: +; CHECK: cmge {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}} + %sign = ashr <4 x i16> %A, + %not = xor <4 x i16> %sign, + ret <4 x i16> %not +} + +define <8 x i16> @cmgez8xi16_alt(<8 x i16> %A) { +; CHECK-LABEL: cmgez8xi16_alt: +; CHECK: cmge {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}} + %sign = ashr <8 x i16> %A, + %not = xor <8 x i16> %sign, + ret <8 x i16> %not +} + +define <2 x i32> @cmgez2xi32_alt(<2 x i32> %A) { +; CHECK-LABEL: cmgez2xi32_alt: +; CHECK: cmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}} + %sign = ashr <2 x i32> %A, + %not = xor <2 x i32> %sign, + ret <2 x i32> %not +} + +define <4 x i32> @cmgez4xi32_alt(<4 x i32> %A) { +; CHECK-LABEL: cmgez4xi32_alt: +; CHECK: cmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}} + %sign = ashr <4 x i32> %A, + %not = xor <4 x i32> %sign, + ret <4 x i32> %not +} + +define <2 x i64> @cmgez2xi64_alt(<2 x i64> %A) { +; CHECK-LABEL: cmgez2xi64_alt: +; CHECK: cmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}} + %sign = ashr <2 x i64> %A, + %not = xor <2 x i64> %sign, + ret <2 x i64> %not +} + + define <8 x i8> @cmgtz8xi8(<8 x i8> %A) { ; CHECK-LABEL: cmgtz8xi8: ; CHECK: cmgt {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}} diff --git a/test/CodeGen/AArch64/neon-mov.ll b/test/CodeGen/AArch64/neon-mov.ll index 40649aeb1b8e..7882f5189413 100644 --- a/test/CodeGen/AArch64/neon-mov.ll +++ b/test/CodeGen/AArch64/neon-mov.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s define <8 x i8> @movi8b() { ; CHECK-LABEL: movi8b: diff --git a/test/CodeGen/AArch64/neon-perm.ll b/test/CodeGen/AArch64/neon-perm.ll index 41e391dcd76c..b9914356f301 100644 --- a/test/CodeGen/AArch64/neon-perm.ll +++ b/test/CodeGen/AArch64/neon-perm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s %struct.int8x8x2_t = type { [2 x <8 x i8>] } %struct.int16x4x2_t = type { [2 x <4 x i16>] } diff --git a/test/CodeGen/AArch64/no-quad-ldp-stp.ll b/test/CodeGen/AArch64/no-quad-ldp-stp.ll new file mode 100644 index 000000000000..19d371adbdf0 --- /dev/null +++ b/test/CodeGen/AArch64/no-quad-ldp-stp.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=aarch64 -mattr=+no-quad-ldst-pairs -verify-machineinstrs -asm-verbose=false | FileCheck %s +; RUN: llc < %s -march=aarch64 -mcpu=exynos-m1 -verify-machineinstrs -asm-verbose=false | FileCheck %s + +; CHECK-LABEL: test_nopair_st +; CHECK: str +; CHECK: stur +; CHECK-NOT: stp +define void @test_nopair_st(double* %ptr, <2 x double> %v1, <2 x double> %v2) { + %tmp1 = bitcast double* %ptr to <2 x double>* + store <2 x double> %v2, <2 x double>* %tmp1, align 16 + %add.ptr = getelementptr inbounds double, double* %ptr, i64 -2 + %tmp = bitcast double* %add.ptr to <2 x double>* + store <2 x double> %v1, <2 x double>* %tmp, align 16 + ret void +} + +; CHECK-LABEL: test_nopair_ld +; CHECK: ldr +; CHECK: ldr +; CHECK-NOT: ldp +define <2 x i64> @test_nopair_ld(i64* %p) { + %a1 = bitcast i64* %p to <2 x i64>* + %tmp1 = load <2 x i64>, < 2 x i64>* %a1, align 8 + %add.ptr2 = getelementptr inbounds i64, i64* %p, i64 2 + %a2 = bitcast i64* %add.ptr2 to <2 x i64>* + %tmp2 = load <2 x i64>, <2 x i64>* %a2, align 8 + %add = add nsw <2 x i64> %tmp1, %tmp2 + ret <2 x i64> %add +} diff --git a/test/CodeGen/AArch64/nontemporal.ll b/test/CodeGen/AArch64/nontemporal.ll index db9779e03190..d8785f845c29 100644 --- a/test/CodeGen/AArch64/nontemporal.ll +++ b/test/CodeGen/AArch64/nontemporal.ll @@ -112,7 +112,7 @@ define void @test_stnp_v1i64(<1 x i64>* %p, <1 x i64> %v) #0 { define void @test_stnp_i64(i64* %p, i64 %v) #0 { ; CHECK-LABEL: test_stnp_i64: -; CHECK-NEXT: ubfx x[[HI:[0-9]+]], x1, #0, #32 +; CHECK-NEXT: lsr x[[HI:[0-9]+]], x1, #32 ; CHECK-NEXT: stnp w1, w[[HI]], [x0] ; CHECK-NEXT: ret store i64 %v, i64* %p, align 1, !nontemporal !0 @@ -162,7 +162,7 @@ define void @test_stnp_v2f32_offset_neg(<2 x float>* %p, <2 x float> %v) #0 { define void @test_stnp_i64_offset(i64* %p, i64 %v) #0 { ; CHECK-LABEL: test_stnp_i64_offset: -; CHECK-NEXT: ubfx x[[HI:[0-9]+]], x1, #0, #32 +; CHECK-NEXT: lsr x[[HI:[0-9]+]], x1, #32 ; CHECK-NEXT: stnp w1, w[[HI]], [x0, #8] ; CHECK-NEXT: ret %tmp0 = getelementptr i64, i64* %p, i32 1 @@ -172,7 +172,7 @@ define void @test_stnp_i64_offset(i64* %p, i64 %v) #0 { define void @test_stnp_i64_offset_neg(i64* %p, i64 %v) #0 { ; CHECK-LABEL: test_stnp_i64_offset_neg: -; CHECK-NEXT: ubfx x[[HI:[0-9]+]], x1, #0, #32 +; CHECK-NEXT: lsr x[[HI:[0-9]+]], x1, #32 ; CHECK-NEXT: stnp w1, w[[HI]], [x0, #-8] ; CHECK-NEXT: ret %tmp0 = getelementptr i64, i64* %p, i32 -1 diff --git a/test/CodeGen/AArch64/nzcv-save.ll b/test/CodeGen/AArch64/nzcv-save.ll index f8f42ec9b1a9..9329f3962934 100644 --- a/test/CodeGen/AArch64/nzcv-save.ll +++ b/test/CodeGen/AArch64/nzcv-save.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=aarch64 < %s | FileCheck %s +; RUN: llc -verify-machineinstrs -march=aarch64 < %s | FileCheck %s ; CHECK: mrs [[NZCV_SAVE:x[0-9]+]], NZCV ; CHECK: msr NZCV, [[NZCV_SAVE]] diff --git a/test/CodeGen/AArch64/optimize-cond-branch.ll b/test/CodeGen/AArch64/optimize-cond-branch.ll new file mode 100644 index 000000000000..4e3ca6f16e78 --- /dev/null +++ b/test/CodeGen/AArch64/optimize-cond-branch.ll @@ -0,0 +1,48 @@ +; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s +target triple = "arm64--" + +; AArch64InstrInfo::optimizeCondBranch() optimizes the +; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction. +; It forgot to clear the a flag resulting in a MachineVerifier complaint. +; +; Writing a stable/simple test is tricky since most tbz instructions are already +; formed in SelectionDAG, optimizeCondBranch() only triggers if the and +; instruction is in a different block than the conditional jump. +; +; CHECK-LABEL: func +; CHECK-NOT: and +; CHECK: tbnz +define void @func() { + %c0 = icmp sgt i64 0, 0 + br i1 %c0, label %b1, label %b6 + +b1: + br i1 undef, label %b3, label %b2 + +b2: + %v0 = tail call i32 @extfunc() + br label %b5 + +b3: + %v1 = load i32, i32* undef, align 4 + %v2 = and i32 %v1, 256 + br label %b5 + +b5: + %v3 = phi i32 [ %v2, %b3 ], [ %v0, %b2 ] + %c1 = icmp eq i32 %v3, 0 + br i1 %c1, label %b8, label %b7 + +b6: + tail call i32 @extfunc() + ret void + +b7: + tail call i32 @extfunc() + ret void + +b8: + ret void +} + +declare i32 @extfunc() diff --git a/test/CodeGen/AArch64/pie.ll b/test/CodeGen/AArch64/pie.ll new file mode 100644 index 000000000000..5cd27a8761cc --- /dev/null +++ b/test/CodeGen/AArch64/pie.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple aarch64-pc-linux -relocation-model=pic < %s | FileCheck %s + +@g1 = global i32 42 + +define i32* @get_g1() { +; CHECK: get_g1: +; CHECK: adrp x0, g1 +; CHECK-NEXT: add x0, x0, :lo12:g1 + ret i32* @g1 +} + +!llvm.module.flags = !{!0} + +!0 = !{i32 1, !"PIE Level", i32 2} diff --git a/test/CodeGen/AArch64/preferred-alignment.ll b/test/CodeGen/AArch64/preferred-alignment.ll new file mode 100644 index 000000000000..c032e83d268f --- /dev/null +++ b/test/CodeGen/AArch64/preferred-alignment.ll @@ -0,0 +1,28 @@ +; RUN: llc -mtriple=aarch64 -O0 < %s | FileCheck %s + +; Function Attrs: nounwind +define i32 @foo() #0 { +entry: + %c = alloca i8, align 1 +; CHECK: add x0, sp, #12 + %s = alloca i16, align 2 +; CHECK-NEXT: add x1, sp, #8 + %i = alloca i32, align 4 +; CHECK-NEXT: add x2, sp, #4 + %call = call i32 @bar(i8* %c, i16* %s, i32* %i) + %0 = load i8, i8* %c, align 1 + %conv = zext i8 %0 to i32 + %add = add nsw i32 %call, %conv + %1 = load i16, i16* %s, align 2 + %conv1 = sext i16 %1 to i32 + %add2 = add nsw i32 %add, %conv1 + %2 = load i32, i32* %i, align 4 + %add3 = add nsw i32 %add2, %2 + ret i32 %add3 +} + +declare i32 @bar(i8*, i16*, i32*) #1 + +attributes #0 = { nounwind "no-frame-pointer-elim"="false" } +attributes #1 = { "no-frame-pointer-elim"="false" } + diff --git a/test/CodeGen/AArch64/preserve_mostcc.ll b/test/CodeGen/AArch64/preserve_mostcc.ll new file mode 100644 index 000000000000..7f0968c8eb33 --- /dev/null +++ b/test/CodeGen/AArch64/preserve_mostcc.ll @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=arm64-apple-ios-8.0.0 | FileCheck %s + +declare void @standard_cc_func() +declare preserve_mostcc void @preserve_mostcc_func() + +; Registers r9-r15 should be saved before the call of a function +; with a standard calling convention. +define preserve_mostcc void @preserve_mostcc1() nounwind { +entry: +;CHECK-LABEL: preserve_mostcc1 +;CHECK-NOT: stp +;CHECK-NOT: str +;CHECK: str x15 +;CHECK-NEXT: stp x14, x13, +;CHECK-NEXT: stp x12, x11, +;CHECK-NEXT: stp x10, x9, +;CHECK: bl _standard_cc_func + call void @standard_cc_func() +;CHECK: ldp x10, x9, +;CHECK-NEXT: ldp x12, x11, +;CHECK-NEXT: ldp x14, x13, +;CHECK-NEXT: ldr x15 + ret void +} + +; Registers r9-r15 don't need to be saved if one +; function with preserve_mostcc calling convention calls another +; function with preserve_mostcc calling convention, because the +; callee wil save these registers anyways. +define preserve_mostcc void @preserve_mostcc2() nounwind { +entry: +;CHECK-LABEL: preserve_mostcc2 +;CHECK-NOT: x14 +;CHECK: stp x29, x30, +;CHECK-NOT: x14 +;CHECK: bl _preserve_mostcc_func + call preserve_mostcc void @preserve_mostcc_func() + ret void +} + diff --git a/test/CodeGen/AArch64/recp-fastmath.ll b/test/CodeGen/AArch64/recp-fastmath.ll new file mode 100644 index 000000000000..710739b2cc5f --- /dev/null +++ b/test/CodeGen/AArch64/recp-fastmath.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=!div,!vec-div | FileCheck %s --check-prefix=FAULT +; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=div,vec-div | FileCheck %s + +define float @frecp(float %x) #0 { + %div = fdiv fast float 1.0, %x + ret float %div + +; FAULT-LABEL: frecp: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fmov +; FAULT-NEXT: fdiv + +; CHECK-LABEL: frecp: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: frecpe +; CHECK-NEXT: fmov +} + +define <2 x float> @f2recp(<2 x float> %x) #0 { + %div = fdiv fast <2 x float> , %x + ret <2 x float> %div + +; FAULT-LABEL: f2recp: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fmov +; FAULT-NEXT: fdiv + +; CHECK-LABEL: f2recp: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frecpe +} + +define <4 x float> @f4recp(<4 x float> %x) #0 { + %div = fdiv fast <4 x float> , %x + ret <4 x float> %div + +; FAULT-LABEL: f4recp: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fmov +; FAULT-NEXT: fdiv + +; CHECK-LABEL: f4recp: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frecpe +} + +define double @drecp(double %x) #0 { + %div = fdiv fast double 1.0, %x + ret double %div + +; FAULT-LABEL: drecp: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fmov +; FAULT-NEXT: fdiv + +; CHECK-LABEL: drecp: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: frecpe +; CHECK-NEXT: fmov +} + +define <2 x double> @d2recp(<2 x double> %x) #0 { + %div = fdiv fast <2 x double> , %x + ret <2 x double> %div + +; FAULT-LABEL: d2recp: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fmov +; FAULT-NEXT: fdiv + +; CHECK-LABEL: d2recp: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frecpe +} + +attributes #0 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AArch64/regress-tblgen-chains.ll b/test/CodeGen/AArch64/regress-tblgen-chains.ll index ba34873eaa5b..4bec512403c4 100644 --- a/test/CodeGen/AArch64/regress-tblgen-chains.ll +++ b/test/CodeGen/AArch64/regress-tblgen-chains.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -disable-fp-elim -o - %s | FileCheck %s ; When generating DAG selection tables, TableGen used to only flag an ; instruction as needing a chain on its own account if it had a built-in pattern diff --git a/test/CodeGen/AArch64/rem_crash.ll b/test/CodeGen/AArch64/rem_crash.ll new file mode 100644 index 000000000000..71f1a80e24e2 --- /dev/null +++ b/test/CodeGen/AArch64/rem_crash.ll @@ -0,0 +1,257 @@ +; RUN: llc < %s -march=aarch64 + +define i8 @test_minsize_uu8(i8 %x) minsize optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_ss8(i8 %x) minsize optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_us8(i8 %x) minsize optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_su8(i8 %x) minsize optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i16 @test_minsize_uu16(i16 %x) minsize optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_ss16(i16 %x) minsize optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_us16(i16 %x) minsize optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_su16(i16 %x) minsize optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i32 @test_minsize_uu32(i32 %x) minsize optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_ss32(i32 %x) minsize optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_us32(i32 %x) minsize optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_su32(i32 %x) minsize optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i64 @test_minsize_uu64(i64 %x) minsize optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_ss64(i64 %x) minsize optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_us64(i64 %x) minsize optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_su64(i64 %x) minsize optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i8 @test_uu8(i8 %x) optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_ss8(i8 %x) optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_us8(i8 %x) optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_su8(i8 %x) optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i16 @test_uu16(i16 %x) optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_ss16(i16 %x) optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_us16(i16 %x) optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_su16(i16 %x) optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i32 @test_uu32(i32 %x) optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_ss32(i32 %x) optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_us32(i32 %x) optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_su32(i32 %x) optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i64 @test_uu64(i64 %x) optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_ss64(i64 %x) optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_us64(i64 %x) optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_su64(i64 %x) optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} diff --git a/test/CodeGen/AArch64/remat.ll b/test/CodeGen/AArch64/remat.ll index c2721e70190a..b2ca1cca0812 100644 --- a/test/CodeGen/AArch64/remat.ll +++ b/test/CodeGen/AArch64/remat.ll @@ -2,7 +2,11 @@ ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=kryo -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=vulcan -o - %s | FileCheck %s +; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s %X = type { i64, i64, i64 } declare void @f(%X*) @@ -11,9 +15,11 @@ entry: %tmp = alloca %X call void @f(%X* %tmp) ; CHECK: add x0, sp, #8 -; CHECK-NEXT-NOT: mov +; CHECK-NOT: mov +; CHECK-NEXT: bl f call void @f(%X* %tmp) ; CHECK: add x0, sp, #8 -; CHECK-NEXT-NOT: mov +; CHECK-NOT: mov +; CHECK-NEXT: bl f ret void } diff --git a/test/CodeGen/AArch64/sibling-call.ll b/test/CodeGen/AArch64/sibling-call.ll index a68fdec4cfbc..925d1881f563 100644 --- a/test/CodeGen/AArch64/sibling-call.ll +++ b/test/CodeGen/AArch64/sibling-call.ll @@ -92,6 +92,6 @@ define void @indirect_tail() { tail call void %fptr(i32 42) ret void ; CHECK: ldr [[FPTR:x[1-9]+]], [{{x[0-9]+}}, {{#?}}:lo12:func] -; CHECK: movz w0, #{{42|0x2a}} +; CHECK: mov w0, #{{42|0x2a}} ; CHECK: br [[FPTR]] } diff --git a/test/CodeGen/AArch64/special-reg.ll b/test/CodeGen/AArch64/special-reg.ll index 91c32158d420..4b8c75b70985 100644 --- a/test/CodeGen/AArch64/special-reg.ll +++ b/test/CodeGen/AArch64/special-reg.ll @@ -35,7 +35,7 @@ entry: define void @write_daifset() nounwind { entry: ; CHECK-LABEL: write_daifset: -; CHECK: msr DAIFSET, #2 +; CHECK: msr DAIFSet, #2 call void @llvm.write_register.i64(metadata !2, i64 2) ret void } diff --git a/test/CodeGen/AArch64/sqrt-fastmath.ll b/test/CodeGen/AArch64/sqrt-fastmath.ll new file mode 100644 index 000000000000..0d9533fd27fc --- /dev/null +++ b/test/CodeGen/AArch64/sqrt-fastmath.ll @@ -0,0 +1,160 @@ +; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=!sqrt,!vec-sqrt | FileCheck %s --check-prefix=FAULT +; RUN: llc < %s -mtriple=aarch64 -mattr=neon -recip=sqrt,vec-sqrt | FileCheck %s +; RUN: llc < %s -mtriple=aarch64 -mattr=neon,-use-reverse-square-root | FileCheck %s --check-prefix=FAULT +; RUN: llc < %s -mtriple=aarch64 -mattr=neon,+use-reverse-square-root | FileCheck %s + +declare float @llvm.sqrt.f32(float) #1 +declare double @llvm.sqrt.f64(double) #1 +declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1 +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) #1 +declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) #1 + +define float @fsqrt(float %a) #0 { + %1 = tail call fast float @llvm.sqrt.f32(float %a) + ret float %1 + +; FAULT-LABEL: fsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: fsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define <2 x float> @f2sqrt(<2 x float> %a) #0 { + %1 = tail call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> %a) #2 + ret <2 x float> %1 + +; FAULT-LABEL: f2sqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: f2sqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: mov +; CHECK-NEXT: frsqrte +} + +define <4 x float> @f4sqrt(<4 x float> %a) #0 { + %1 = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) #2 + ret <4 x float> %1 + +; FAULT-LABEL: f4sqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: f4sqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: mov +; CHECK-NEXT: frsqrte +} + +define double @dsqrt(double %a) #0 { + %1 = tail call fast double @llvm.sqrt.f64(double %a) + ret double %1 + +; FAULT-LABEL: dsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: dsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define <2 x double> @d2sqrt(<2 x double> %a) #0 { + %1 = tail call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) #2 + ret <2 x double> %1 + +; FAULT-LABEL: d2sqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: d2sqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: mov +; CHECK-NEXT: frsqrte +} + +define float @frsqrt(float %a) #0 { + %1 = tail call fast float @llvm.sqrt.f32(float %a) + %2 = fdiv fast float 1.000000e+00, %1 + ret float %2 + +; FAULT-LABEL: frsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: frsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define <2 x float> @f2rsqrt(<2 x float> %a) #0 { + %1 = tail call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> %a) #2 + %2 = fdiv fast <2 x float> , %1 + ret <2 x float> %2 + +; FAULT-LABEL: f2rsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: f2rsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define <4 x float> @f4rsqrt(<4 x float> %a) #0 { + %1 = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) #2 + %2 = fdiv fast <4 x float> , %1 + ret <4 x float> %2 + +; FAULT-LABEL: f4rsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: f4rsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define double @drsqrt(double %a) #0 { + %1 = tail call fast double @llvm.sqrt.f64(double %a) + %2 = fdiv fast double 1.000000e+00, %1 + ret double %2 + +; FAULT-LABEL: drsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: drsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +define <2 x double> @d2rsqrt(<2 x double> %a) #0 { + %1 = tail call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> %a) #2 + %2 = fdiv fast <2 x double> , %1 + ret <2 x double> %2 + +; FAULT-LABEL: d2rsqrt: +; FAULT-NEXT: BB#0 +; FAULT-NEXT: fsqrt + +; CHECK-LABEL: d2rsqrt: +; CHECK-NEXT: BB#0 +; CHECK-NEXT: fmov +; CHECK-NEXT: frsqrte +} + +attributes #0 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll index eb4937e75f61..6f1515a98264 100644 --- a/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll +++ b/test/CodeGen/AArch64/stack-guard-remat-bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-ios -relocation-model=pic -disable-fp-elim | FileCheck %s @__stack_chk_guard = external global i64* @@ -6,10 +6,14 @@ ; CHECK: adrp [[R0:x[0-9]+]], ___stack_chk_guard@GOTPAGE ; CHECK: ldr [[R1:x[0-9]+]], {{\[}}[[R0]], ___stack_chk_guard@GOTPAGEOFF{{\]}} +; Load the stack guard for the second time, just in case the previous value gets spilled. +; CHECK: adrp [[GUARD_PAGE:x[0-9]+]], ___stack_chk_guard@GOTPAGE ; CHECK: ldr [[R2:x[0-9]+]], {{\[}}[[R1]]{{\]}} ; CHECK: stur [[R2]], {{\[}}x29, [[SLOT0:[0-9#\-]+]]{{\]}} ; CHECK: ldur [[R3:x[0-9]+]], {{\[}}x29, [[SLOT0]]{{\]}} -; CHECK: sub [[R4:x[0-9]+]], [[R2]], [[R3]] +; CHECK: ldr [[GUARD_ADDR:x[0-9]+]], {{\[}}[[GUARD_PAGE]], ___stack_chk_guard@GOTPAGEOFF{{\]}} +; CHECK: ldr [[GUARD:x[0-9]+]], {{\[}}[[GUARD_ADDR]]{{\]}} +; CHECK: sub [[R4:x[0-9]+]], [[GUARD]], [[R3]] ; CHECK: cbnz [[R4]], LBB define i32 @test_stack_guard_remat2() { diff --git a/test/CodeGen/AArch64/stack-protector-target.ll b/test/CodeGen/AArch64/stack-protector-target.ll new file mode 100644 index 000000000000..d4d806289bff --- /dev/null +++ b/test/CodeGen/AArch64/stack-protector-target.ll @@ -0,0 +1,19 @@ +; Test target-specific stack cookie location. +; RUN: llc -mtriple=aarch64-linux-android < %s -o - | FileCheck --check-prefix=ANDROID-AARCH64 %s + +define void @_Z1fv() sspreq { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @_Z7CapturePi(i32* nonnull %x) + ret void +} + +declare void @_Z7CapturePi(i32*) + +; ANDROID-AARCH64: mrs [[A:.*]], TPIDR_EL0 +; ANDROID-AARCH64: ldr [[B:.*]], {{\[}}[[A]], #40] +; ANDROID-AARCH64: str [[B]], [sp, +; ANDROID-AARCH64: ldr [[C:.*]], {{\[}}[[A]], #40] +; ANDROID-AARCH64: ldr [[D:.*]], [sp, +; ANDROID-AARCH64: cmp [[C]], [[D]] diff --git a/test/CodeGen/AArch64/stackmap-frame-setup.ll b/test/CodeGen/AArch64/stackmap-frame-setup.ll index 4712012b0d25..5646703fa403 100644 --- a/test/CodeGen/AArch64/stackmap-frame-setup.ll +++ b/test/CodeGen/AArch64/stackmap-frame-setup.ll @@ -1,5 +1,5 @@ -; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=aarch64-apple-darwin -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL -; RUN: llc -o /dev/null -verify-machineinstrs -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -stop-after machine-sink %s | FileCheck %s --check-prefix=FAST-ISEL +; RUN: llc -o - -verify-machineinstrs -mtriple=aarch64-apple-darwin -stop-after machine-sink %s | FileCheck %s --check-prefix=ISEL +; RUN: llc -o - -verify-machineinstrs -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -stop-after machine-sink %s | FileCheck %s --check-prefix=FAST-ISEL define void @caller_meta_leaf() { entry: diff --git a/test/CodeGen/AArch64/stackmap-liveness.ll b/test/CodeGen/AArch64/stackmap-liveness.ll index 6b37aac16f9e..224a9c418526 100644 --- a/test/CodeGen/AArch64/stackmap-liveness.ll +++ b/test/CodeGen/AArch64/stackmap-liveness.ll @@ -37,7 +37,7 @@ define i64 @stackmap_liveness(i1 %c) { ; CHECK-NEXT: .byte 0 ; CHECK-NEXT: .byte 8 ; Align -; CHECK-NEXT: .align 3 +; CHECK-NEXT: .p2align 3 %1 = select i1 %c, i64 1, i64 2 call anyregcc void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 1, i32 32, i8* null, i32 0) ret i64 %1 diff --git a/test/CodeGen/AArch64/subs-to-sub-opt.ll b/test/CodeGen/AArch64/subs-to-sub-opt.ll new file mode 100644 index 000000000000..f33e24e777fe --- /dev/null +++ b/test/CodeGen/AArch64/subs-to-sub-opt.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=aarch64-linux-gnu -O3 -o - %s | FileCheck %s + +@a = external global i8, align 1 +@b = external global i8, align 1 + +; Test that SUBS is replaced by SUB if condition flags are not used. +define i32 @test01() nounwind { +; CHECK: ldrb {{.*}} +; CHECK-NEXT: ldrb {{.*}} +; CHECK-NEXT: sub {{.*}} +; CHECK-NEXT: cmn {{.*}} +entry: + %0 = load i8, i8* @a, align 1 + %conv = zext i8 %0 to i32 + %1 = load i8, i8* @b, align 1 + %conv1 = zext i8 %1 to i32 + %s = sub nsw i32 %conv1, %conv + %cmp0 = icmp eq i32 %s, -1 + %cmp1 = sext i1 %cmp0 to i8 + store i8 %cmp1, i8* @a + ret i32 0 +} + diff --git a/test/CodeGen/AArch64/swifterror.ll b/test/CodeGen/AArch64/swifterror.ll new file mode 100644 index 000000000000..a0bfffdef95e --- /dev/null +++ b/test/CodeGen/AArch64/swifterror.ll @@ -0,0 +1,385 @@ +; RUN: llc -verify-machineinstrs -disable-fp-elim < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck --check-prefix=CHECK-APPLE %s +; RUN: llc -verify-machineinstrs -disable-fp-elim -O0 < %s -mtriple=aarch64-apple-ios -disable-post-ra | FileCheck --check-prefix=CHECK-O0 %s + +declare i8* @malloc(i64) +declare void @free(i8*) +%swift_error = type {i64, i8} + +; This tests the basic usage of a swifterror parameter. "foo" is the function +; that takes a swifterror parameter and "caller" is the caller of "foo". +define float @foo(%swift_error** swifterror %error_ptr_ref) { +; CHECK-APPLE-LABEL: foo: +; CHECK-APPLE: orr w0, wzr, #0x10 +; CHECK-APPLE: malloc +; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-APPLE: strb [[ID]], [x0, #8] +; CHECK-APPLE: mov x19, x0 +; CHECK-APPLE-NOT: x19 + +; CHECK-O0-LABEL: foo: +; CHECK-O0: orr w{{.*}}, wzr, #0x10 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID2:x[0-9]+]], x0 +; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-O0: strb [[ID]], [x0, #8] +; CHECK-O0: mov x19, [[ID2]] +; CHECK-O0-NOT: x19 +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 +} + +; "caller" calls "foo" that takes a swifterror parameter. +define float @caller(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller: +; CHECK-APPLE: mov [[ID:x[0-9]+]], x0 +; CHECK-APPLE: mov x19, xzr +; CHECK-APPLE: bl {{.*}}foo +; CHECK-APPLE: cbnz x19 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] +; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov x0, x19 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller: +; CHECK-O0: mov x19 +; CHECK-O0: bl {{.*}}foo +; CHECK-O0: mov [[ID:x[0-9]+]], x19 +; CHECK-O0: cbnz [[ID]] +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "caller2" is the caller of "foo", it calls "foo" inside a loop. +define float @caller2(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller2: +; CHECK-APPLE: mov [[ID:x[0-9]+]], x0 +; CHECK-APPLE: fmov [[CMP:s[0-9]+]], #1.0 +; CHECK-APPLE: mov x19, xzr +; CHECK-APPLE: bl {{.*}}foo +; CHECK-APPLE: cbnz x19 +; CHECK-APPLE: fcmp s0, [[CMP]] +; CHECK-APPLE: b.le +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] +; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov x0, x19 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller2: +; CHECK-O0: mov x19 +; CHECK-O0: bl {{.*}}foo +; CHECK-O0: mov [[ID:x[0-9]+]], x19 +; CHECK-O0: cbnz [[ID]] +entry: + %error_ptr_ref = alloca swifterror %swift_error* + br label %bb_loop +bb_loop: + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %cmp = fcmp ogt float %call, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "foo_if" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition. +define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) { +; CHECK-APPLE-LABEL: foo_if: +; CHECK-APPLE: cbz w0 +; CHECK-APPLE: orr w0, wzr, #0x10 +; CHECK-APPLE: malloc +; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-APPLE: strb [[ID]], [x0, #8] +; CHECK-APPLE: mov x19, x0 +; CHECK-APPLE-NOT: x19 +; CHECK-APPLE: ret + +; CHECK-O0-LABEL: foo_if: +; spill x19 +; CHECK-O0: str x19 +; CHECK-O0: cbz w0 +; CHECK-O0: orr w{{.*}}, wzr, #0x10 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID:x[0-9]+]], x0 +; CHECK-O0: orr [[ID2:w[0-9]+]], wzr, #0x1 +; CHECK-O0: strb [[ID2]], [x0, #8] +; CHECK-O0: mov x19, [[ID]] +; CHECK-O0: ret +; reload from stack +; CHECK-O0: ldr x19 +; CHECK-O0: ret +entry: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %normal + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 + +normal: + ret float 0.0 +} + +; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition inside a loop. +define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) { +; CHECK-APPLE-LABEL: foo_loop: +; CHECK-APPLE: mov x0, x19 +; CHECK-APPLE: cbz +; CHECK-APPLE: orr w0, wzr, #0x10 +; CHECK-APPLE: malloc +; CHECK-APPLE: strb w{{.*}}, [x0, #8] +; CHECK-APPLE: fcmp +; CHECK-APPLE: b.le +; CHECK-APPLE: mov x19, x0 +; CHECK-APPLE: ret + +; CHECK-O0-LABEL: foo_loop: +; spill x19 +; CHECK-O0: str x19 +; CHECk-O0: cbz +; CHECK-O0: orr w{{.*}}, wzr, #0x10 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID:x[0-9]+]], x0 +; CHECK-O0: strb w{{.*}}, [{{.*}}[[ID]], #8] +; spill x0 +; CHECK-O0: str x0 +; CHECK-O0: fcmp +; CHECK-O0: b.le +; reload from stack +; CHECK-O0: ldr x19 +; CHECK-O0: ret +entry: + br label %bb_loop + +bb_loop: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %bb_cont + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + br label %bb_cont + +bb_cont: + %cmp = fcmp ogt float %cc2, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + ret float 0.0 +} + +%struct.S = type { i32, i32, i32, i32, i32, i32 } + +; "foo_sret" is a function that takes a swifterror parameter, it also has a sret +; parameter. +define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +; CHECK-APPLE-LABEL: foo_sret: +; CHECK-APPLE: mov [[SRET:x[0-9]+]], x8 +; CHECK-APPLE: orr w0, wzr, #0x10 +; CHECK-APPLE: malloc +; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-APPLE: strb [[ID]], [x0, #8] +; CHECK-APPLE: str w{{.*}}, [{{.*}}[[SRET]], #4] +; CHECK-APPLE: mov x19, x0 +; CHECK-APPLE-NOT: x19 + +; CHECK-O0-LABEL: foo_sret: +; CHECK-O0: orr w{{.*}}, wzr, #0x10 +; spill x8 +; CHECK-O0-DAG: str x8 +; spill x19 +; CHECK-O0-DAG: str x19 +; CHECK-O0: malloc +; CHECK-O0: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-O0: strb [[ID]], [x0, #8] +; reload from stack +; CHECK-O0: ldr [[SRET:x[0-9]+]] +; CHECK-O0: str w{{.*}}, [{{.*}}[[SRET]], #4] +; CHECK-O0: mov x19 +; CHECK-O0-NOT: x19 +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + %v2 = getelementptr inbounds %struct.S, %struct.S* %agg.result, i32 0, i32 1 + store i32 %val1, i32* %v2 + ret void +} + +; "caller3" calls "foo_sret" that takes a swifterror parameter. +define float @caller3(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller3: +; CHECK-APPLE: mov [[ID:x[0-9]+]], x0 +; CHECK-APPLE: mov x19, xzr +; CHECK-APPLE: bl {{.*}}foo_sret +; CHECK-APPLE: cbnz x19 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] +; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov x0, x19 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller3: +; spill x0 +; CHECK-O0: str x0 +; CHECK-O0: mov x19 +; CHECK-O0: bl {{.*}}foo_sret +; CHECK-O0: mov [[ID2:x[0-9]+]], x19 +; CHECK-O0: cbnz [[ID2]] +; Access part of the error object and save it to error_ref +; reload from stack +; CHECK-O0: ldrb [[CODE:w[0-9]+]] +; CHECK-O0: ldr [[ID:x[0-9]+]] +; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK_O0: bl {{.*}}free +entry: + %s = alloca %struct.S, align 8 + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "foo_vararg" is a function that takes a swifterror parameter, it also has +; variable number of arguments. +declare void @llvm.va_start(i8*) nounwind +define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) { +; CHECK-APPLE-LABEL: foo_vararg: +; CHECK-APPLE: orr w0, wzr, #0x10 +; CHECK-APPLE: malloc +; CHECK-APPLE: orr [[ID:w[0-9]+]], wzr, #0x1 +; CHECK-APPLE: add [[ARGS:x[0-9]+]], [[TMP:x[0-9]+]], #16 +; CHECK-APPLE: strb [[ID]], [x0, #8] + +; First vararg +; CHECK-APPLE-DAG: orr {{x[0-9]+}}, [[ARGS]], #0x8 +; CHECK-APPLE-DAG: ldr {{w[0-9]+}}, [{{.*}}[[TMP]], #16] +; CHECK-APPLE: add {{x[0-9]+}}, {{x[0-9]+}}, #8 +; Second vararg +; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}] +; CHECK-APPLE: add {{x[0-9]+}}, {{x[0-9]+}}, #8 +; Third vararg +; CHECK-APPLE: ldr {{w[0-9]+}}, [{{x[0-9]+}}] + +; CHECK-APPLE: mov x19, x0 +; CHECK-APPLE-NOT: x19 +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + + %args = alloca i8*, align 8 + %a10 = alloca i32, align 4 + %a11 = alloca i32, align 4 + %a12 = alloca i32, align 4 + %v10 = bitcast i8** %args to i8* + call void @llvm.va_start(i8* %v10) + %v11 = va_arg i8** %args, i32 + store i32 %v11, i32* %a10, align 4 + %v12 = va_arg i8** %args, i32 + store i32 %v12, i32* %a11, align 4 + %v13 = va_arg i8** %args, i32 + store i32 %v13, i32* %a12, align 4 + + ret float 1.0 +} + +; "caller4" calls "foo_vararg" that takes a swifterror parameter. +define float @caller4(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller4: + +; CHECK-APPLE: mov [[ID:x[0-9]+]], x0 +; CHECK-APPLE: stp {{x[0-9]+}}, {{x[0-9]+}}, [sp, #8] +; CHECK-APPLE: str {{x[0-9]+}}, [sp] + +; CHECK-APPLE: mov x19, xzr +; CHECK-APPLE: bl {{.*}}foo_vararg +; CHECK-APPLE: cbnz x19 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrb [[CODE:w[0-9]+]], [x19, #8] +; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov x0, x19 +; CHECK_APPLE: bl {{.*}}free +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + + %a10 = alloca i32, align 4 + %a11 = alloca i32, align 4 + %a12 = alloca i32, align 4 + store i32 10, i32* %a10, align 4 + store i32 11, i32* %a11, align 4 + store i32 12, i32* %a12, align 4 + %v10 = load i32, i32* %a10, align 4 + %v11 = load i32, i32* %a11, align 4 + %v12 = load i32, i32* %a12, align 4 + + %call = call float (%swift_error**, ...) @foo_vararg(%swift_error** swifterror %error_ptr_ref, i32 %v10, i32 %v11, i32 %v12) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont + +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} diff --git a/test/CodeGen/AArch64/swiftself.ll b/test/CodeGen/AArch64/swiftself.ll new file mode 100644 index 000000000000..a60aed6b0f2b --- /dev/null +++ b/test/CodeGen/AArch64/swiftself.ll @@ -0,0 +1,67 @@ +; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT %s +; RUN: llc -O0 -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=aarch64-unknown-linux-gnu -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT %s + +; Parameter with swiftself should be allocated to x20. +; CHECK-LABEL: swiftself_param: +; CHECK: mov x0, x20 +; CHECK-NEXT: ret +define i8* @swiftself_param(i8* swiftself %addr0) { + ret i8 *%addr0 +} + +; Check that x20 is used to pass a swiftself argument. +; CHECK-LABEL: call_swiftself: +; CHECK: mov x20, x0 +; CHECK: bl {{_?}}swiftself_param +; CHECK: ret +define i8 *@call_swiftself(i8* %arg) { + %res = call i8 *@swiftself_param(i8* swiftself %arg) + ret i8 *%res +} + +; x20 should be saved by the callee even if used for swiftself +; CHECK-LABEL: swiftself_clobber: +; CHECK: {{stp|str}} {{.*}}x20{{.*}}sp +; ... +; CHECK: {{ldp|ldr}} {{.*}}x20{{.*}}sp +; CHECK: ret +define i8 *@swiftself_clobber(i8* swiftself %addr0) { + call void asm sideeffect "", "~{x20}"() + ret i8 *%addr0 +} + +; Demonstrate that we do not need any movs when calling multiple functions +; with swiftself argument. +; CHECK-LABEL: swiftself_passthrough: +; OPT-NOT: mov{{.*}}x20 +; OPT: bl {{_?}}swiftself_param +; OPT-NOT: mov{{.*}}x20 +; OPT-NEXT: bl {{_?}}swiftself_param +; OPT: ret +define void @swiftself_passthrough(i8* swiftself %addr0) { + call i8 *@swiftself_param(i8* swiftself %addr0) + call i8 *@swiftself_param(i8* swiftself %addr0) + ret void +} + +; We can use a tail call if the callee swiftself is the same as the caller one. +; CHECK-LABEL: swiftself_tail: +; OPT: b {{_?}}swiftself_param +; OPT-NOT: ret +define i8* @swiftself_tail(i8* swiftself %addr0) { + call void asm sideeffect "", "~{x20}"() + %res = tail call i8* @swiftself_param(i8* swiftself %addr0) + ret i8* %res +} + +; We can not use a tail call if the callee swiftself is not the same as the +; caller one. +; CHECK-LABEL: swiftself_notail: +; CHECK: mov x20, x0 +; CHECK: bl {{_?}}swiftself_param +; CHECK: ret +define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind { + %res = tail call i8* @swiftself_param(i8* swiftself %addr1) + ret i8* %res +} diff --git a/test/CodeGen/AArch64/tailcall-ccmismatch.ll b/test/CodeGen/AArch64/tailcall-ccmismatch.ll new file mode 100644 index 000000000000..ab96e609dd46 --- /dev/null +++ b/test/CodeGen/AArch64/tailcall-ccmismatch.ll @@ -0,0 +1,24 @@ +; RUN: llc -o - %s | FileCheck %s +target triple="aarch64--" + +declare void @somefunc() +define preserve_mostcc void @test_ccmismatch_notail() { +; Ensure that no tail call is used here, as the called function somefunc does +; not preserve enough registers for preserve_mostcc. +; CHECK-LABEL: test_ccmismatch_notail: +; CHECK-NOT: b somefunc +; CHECK: bl somefunc + tail call void @somefunc() + ret void +} + +declare preserve_mostcc void @some_preserve_most_func() +define void @test_ccmismatch_tail() { +; We can perform a tail call here, because some_preserve_most_func preserves +; all registers necessary for test_ccmismatch_tail. +; CHECK-LABEL: test_ccmismatch_tail: +; CHECK-NOT: bl some_preserve_most_func +; CHECK: b some_preserve_most_func + tail call preserve_mostcc void @some_preserve_most_func() + ret void +} diff --git a/test/CodeGen/AArch64/tailcall-implicit-sret.ll b/test/CodeGen/AArch64/tailcall-implicit-sret.ll index 5d6805998d22..3955877b09b7 100644 --- a/test/CodeGen/AArch64/tailcall-implicit-sret.ll +++ b/test/CodeGen/AArch64/tailcall-implicit-sret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -asm-verbose=false | FileCheck %s +; RUN: llc < %s -mtriple arm64-apple-darwin -aarch64-load-store-opt=false -disable-post-ra -asm-verbose=false | FileCheck %s ; Disable the load/store optimizer to avoid having LDP/STPs and simplify checks. target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" diff --git a/test/CodeGen/AArch64/tailcall_misched_graph.ll b/test/CodeGen/AArch64/tailcall_misched_graph.ll index 343ffab57e35..59a3be905f17 100644 --- a/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -37,6 +37,8 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: SU({{.*}}): [[VRB]] = LDRXui ; CHECK-NOT: SU ; CHECK: Successors: -; CHECK: ch SU([[DEPSTORE:.*]]): Latency=0 +; CHECK: ch SU([[DEPSTOREB:.*]]): Latency=0 +; CHECK: ch SU([[DEPSTOREA:.*]]): Latency=0 -; CHECK: SU([[DEPSTORE]]): STRXui %vreg0, +; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, +; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, diff --git a/test/CodeGen/AArch64/tailmerging_in_mbp.ll b/test/CodeGen/AArch64/tailmerging_in_mbp.ll new file mode 100644 index 000000000000..d850801ee54a --- /dev/null +++ b/test/CodeGen/AArch64/tailmerging_in_mbp.ll @@ -0,0 +1,63 @@ +; RUN: llc <%s -march=aarch64 -verify-machine-dom-info | FileCheck %s + +; CHECK-LABEL: test: +; CHECK: LBB0_7: +; CHECK: b.hi +; CHECK-NEXT: b +; CHECK-NEXT: LBB0_8: +; CHECK-NEXT: mov x8, x9 +; CHECK-NEXT: LBB0_9: +define i64 @test(i64 %n, i64* %a, i64* %b, i64* %c, i64* %d, i64* %e, i64* %f) { +entry: + %cmp28 = icmp sgt i64 %n, 1 + br i1 %cmp28, label %for.body, label %for.end + +for.body: ; preds = %for.body.lr.ph, %if.end + %j = phi i64 [ %n, %entry ], [ %div, %if.end ] + %div = lshr i64 %j, 1 + %a.arrayidx = getelementptr inbounds i64, i64* %a, i64 %div + %a.j = load i64, i64* %a.arrayidx + %b.arrayidx = getelementptr inbounds i64, i64* %b, i64 %div + %b.j = load i64, i64* %b.arrayidx + %cmp.i = icmp slt i64 %a.j, %b.j + br i1 %cmp.i, label %for.end.loopexit, label %cond.false.i + +cond.false.i: ; preds = %for.body + %cmp4.i = icmp sgt i64 %a.j, %b.j + br i1 %cmp4.i, label %if.end, label %cond.false6.i + +cond.false6.i: ; preds = %cond.false.i + %c.arrayidx = getelementptr inbounds i64, i64* %c, i64 %div + %c.j = load i64, i64* %c.arrayidx + %d.arrayidx = getelementptr inbounds i64, i64* %d, i64 %div + %d.j = load i64, i64* %d.arrayidx + %cmp9.i = icmp slt i64 %c.j, %d.j + br i1 %cmp9.i, label %for.end.loopexit, label %cond.false11.i + +cond.false11.i: ; preds = %cond.false6.i + %cmp14.i = icmp sgt i64 %c.j, %d.j + br i1 %cmp14.i, label %if.end, label %cond.false12.i + +cond.false12.i: ; preds = %cond.false11.i + %e.arrayidx = getelementptr inbounds i64, i64* %e, i64 %div + %e.j = load i64, i64* %e.arrayidx + %f.arrayidx = getelementptr inbounds i64, i64* %f, i64 %div + %f.j = load i64, i64* %f.arrayidx + %cmp19.i = icmp sgt i64 %e.j, %f.j + br i1 %cmp19.i, label %if.end, label %for.end.loopexit + +if.end: ; preds = %cond.false12.i, %cond.false11.i, %cond.false.i + %cmp = icmp ugt i64 %j, 3 + br i1 %cmp, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %cond.false12.i, %cond.false6.i, %for.body, %if.end + %j.0.lcssa.ph = phi i64 [ %j, %cond.false12.i ], [ %j, %cond.false6.i ], [ %j, %for.body ], [ %div, %if.end ] + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + %j.0.lcssa = phi i64 [ %n, %entry ], [ %j.0.lcssa.ph, %for.end.loopexit ] + %j.2 = add i64 %j.0.lcssa, %n + %j.3 = mul i64 %j.2, %n + %j.4 = add i64 %j.3, 10 + ret i64 %j.4 +} diff --git a/test/CodeGen/AArch64/vcvt-oversize.ll b/test/CodeGen/AArch64/vcvt-oversize.ll index 066a4b666204..b6e25cfadaa9 100644 --- a/test/CodeGen/AArch64/vcvt-oversize.ll +++ b/test/CodeGen/AArch64/vcvt-oversize.ll @@ -2,8 +2,9 @@ define <8 x i8> @float_to_i8(<8 x float>* %in) { ; CHECK-LABEL: float_to_i8: -; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s -; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s +; CHECK: ldp q1, q0, [x0] +; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v1.4s, v1.4s +; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v0.4s, v0.4s ; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s ; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s ; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s diff --git a/test/CodeGen/AArch64/vector-fcopysign.ll b/test/CodeGen/AArch64/vector-fcopysign.ll index 865a0a5b8580..47d75d5ecc61 100644 --- a/test/CodeGen/AArch64/vector-fcopysign.ll +++ b/test/CodeGen/AArch64/vector-fcopysign.ll @@ -7,7 +7,7 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" ; WidenVecRes same define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 { ; CHECK-LABEL: test_copysign_v1f32_v1f32: -; CHECK-NEXT: movi.2s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.2s v2, #128, lsl #24 ; CHECK-NEXT: bit.8b v0, v1, v2 ; CHECK-NEXT: ret %r = call <1 x float> @llvm.copysign.v1f32(<1 x float> %a, <1 x float> %b) @@ -18,7 +18,7 @@ define <1 x float> @test_copysign_v1f32_v1f32(<1 x float> %a, <1 x float> %b) #0 define <1 x float> @test_copysign_v1f32_v1f64(<1 x float> %a, <1 x double> %b) #0 { ; CHECK-LABEL: test_copysign_v1f32_v1f64: ; CHECK-NEXT: fcvt s1, d1 -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: ret %tmp0 = fptrunc <1 x double> %b to <1 x float> @@ -59,7 +59,7 @@ declare <1 x double> @llvm.copysign.v1f64(<1 x double> %a, <1 x double> %b) #0 define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0 { ; CHECK-LABEL: test_copysign_v2f32_v2f32: -; CHECK-NEXT: movi.2s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.2s v2, #128, lsl #24 ; CHECK-NEXT: bit.8b v0, v1, v2 ; CHECK-NEXT: ret %r = call <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) @@ -69,7 +69,7 @@ define <2 x float> @test_copysign_v2f32_v2f32(<2 x float> %a, <2 x float> %b) #0 define <2 x float> @test_copysign_v2f32_v2f64(<2 x float> %a, <2 x double> %b) #0 { ; CHECK-LABEL: test_copysign_v2f32_v2f64: ; CHECK-NEXT: fcvtn v1.2s, v1.2d -; CHECK-NEXT: movi.2s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.2s v2, #128, lsl #24 ; CHECK-NEXT: bit.8b v0, v1, v2 ; CHECK-NEXT: ret %tmp0 = fptrunc <2 x double> %b to <2 x float> @@ -83,7 +83,7 @@ declare <2 x float> @llvm.copysign.v2f32(<2 x float> %a, <2 x float> %b) #0 define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0 { ; CHECK-LABEL: test_copysign_v4f32_v4f32: -; CHECK-NEXT: movi.4s v2, #0x80, lsl #24 +; CHECK-NEXT: movi.4s v2, #128, lsl #24 ; CHECK-NEXT: bit.16b v0, v1, v2 ; CHECK-NEXT: ret %r = call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> %b) @@ -94,21 +94,21 @@ define <4 x float> @test_copysign_v4f32_v4f32(<4 x float> %a, <4 x float> %b) #0 define <4 x float> @test_copysign_v4f32_v4f64(<4 x float> %a, <4 x double> %b) #0 { ; CHECK-LABEL: test_copysign_v4f32_v4f64: ; CHECK-NEXT: mov s3, v0[1] -; CHECK-NEXT: mov d4, v1[1] -; CHECK-NEXT: movi.4s v5, #0x80, lsl #24 -; CHECK-NEXT: fcvt s1, d1 +; CHECK-NEXT: movi.4s v4, #128, lsl #24 +; CHECK-NEXT: fcvt s5, d1 ; CHECK-NEXT: mov s6, v0[2] ; CHECK-NEXT: mov s7, v0[3] -; CHECK-NEXT: fcvt s16, d2 -; CHECK-NEXT: bit.16b v0, v1, v5 -; CHECK-NEXT: bit.16b v6, v16, v5 -; CHECK-NEXT: fcvt s1, d4 -; CHECK-NEXT: bit.16b v3, v1, v5 +; CHECK-NEXT: bit.16b v0, v5, v4 +; CHECK-NEXT: fcvt s5, d2 +; CHECK-NEXT: bit.16b v6, v5, v4 +; CHECK-NEXT: mov d1, v1[1] +; CHECK-NEXT: fcvt s1, d1 +; CHECK-NEXT: bit.16b v3, v1, v4 ; CHECK-NEXT: mov d1, v2[1] ; CHECK-NEXT: fcvt s1, d1 ; CHECK-NEXT: ins.s v0[1], v3[0] ; CHECK-NEXT: ins.s v0[2], v6[0] -; CHECK-NEXT: bit.16b v7, v1, v5 +; CHECK-NEXT: bit.16b v7, v1, v4 ; CHECK-NEXT: ins.s v0[3], v7[0] ; CHECK-NEXT: ret %tmp0 = fptrunc <4 x double> %b to <4 x float> diff --git a/test/CodeGen/AArch64/vector_merge_dep_check.ll b/test/CodeGen/AArch64/vector_merge_dep_check.ll new file mode 100644 index 000000000000..9220947e8362 --- /dev/null +++ b/test/CodeGen/AArch64/vector_merge_dep_check.ll @@ -0,0 +1,41 @@ +; RUN: llc --combiner-alias-analysis=false < %s | FileCheck %s +; RUN: llc --combiner-alias-analysis=true < %s | FileCheck %s + +; This test checks that we do not merge stores together which have +; dependencies through their non-chain operands (e.g. one store is the +; chain ancestor of a load whose value is used in as the data for the +; other store). Merging in such cases creates a loop in the DAG. + +target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android" + +%"class.std::__1::complex.0.20.56.60.64.72.76.88.92.112.140.248" = type { float, float } + +; Function Attrs: noinline norecurse nounwind ssp uwtable +define void @fn(<2 x i64>* %argA, <2 x i64>* %argB, i64* %a) #0 align 2 { + %_p_vec_full = load <2 x i64>, <2 x i64>* %argA, align 4, !alias.scope !1, !noalias !3 + %x = extractelement <2 x i64> %_p_vec_full, i32 1 + store i64 %x, i64* %a, align 8, !alias.scope !4, !noalias !9 + %_p_vec_full155 = load <2 x i64>, <2 x i64>* %argB, align 4, !alias.scope !1, !noalias !3 + %y = extractelement <2 x i64> %_p_vec_full155, i32 0 + %scevgep41 = getelementptr i64, i64* %a, i64 -1 + store i64 %y, i64* %scevgep41, align 8, !alias.scope !4, !noalias !9 + ret void +} + +; CHECK: ret + +attributes #0 = { noinline norecurse nounwind ssp uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "polly-optimized" "stack-protector-buffer-size"="8" "target-features"="+crc,+crypto,+neon" "unsafe-fp-math"="false" "use-soft-float"="false" } + +!llvm.ident = !{!0} + +!0 = !{!"Snapdragon LLVM ARM Compiler 3.8.0 (based on LLVM 3.8.0)"} +!1 = distinct !{!1, !2, !"polly.alias.scope.rhs"} +!2 = distinct !{!2, !"polly.alias.scope.domain"} +!3 = !{!4, !5, !6, !7, !8} +!4 = distinct !{!4, !2, !"polly.alias.scope.blockB"} +!5 = distinct !{!5, !2, !"polly.alias.scope.add28.lcssa.reg2mem"} +!6 = distinct !{!6, !2, !"polly.alias.scope.count.0.lcssa.reg2mem"} +!7 = distinct !{!7, !2, !"polly.alias.scope.mul"} +!8 = distinct !{!8, !2, !"polly.alias.scope.add28.us.lcssa.reg2mem"} +!9 = !{!1, !5, !6, !7, !8} diff --git a/test/CodeGen/AMDGPU/32-bit-local-address-space.ll b/test/CodeGen/AMDGPU/32-bit-local-address-space.ll index c7bcfd2ddab2..ff8c90457876 100644 --- a/test/CodeGen/AMDGPU/32-bit-local-address-space.ll +++ b/test/CodeGen/AMDGPU/32-bit-local-address-space.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and @@ -91,12 +91,12 @@ define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %ti @ptr = addrspace(3) global i32 addrspace(3)* undef -@dst = addrspace(3) global [16384 x i32] undef +@dst = addrspace(3) global [16383 x i32] undef ; FUNC-LABEL: {{^}}global_ptr: ; SI: ds_write_b32 define void @global_ptr() nounwind { - store i32 addrspace(3)* getelementptr ([16384 x i32], [16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr + store i32 addrspace(3)* getelementptr ([16383 x i32], [16383 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr ret void } diff --git a/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll new file mode 100644 index 000000000000..62b09dfedf15 --- /dev/null +++ b/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel %s -o - 2>&1 | FileCheck %s +; REQUIRES: global-isel +; This file checks that the translation from llvm IR to generic MachineInstr +; is correct. + +; Tests for add. +; CHECK: name: addi32 +; CHECK: G_ADD i32 +define i32 @addi32(i32 %arg1, i32 %arg2) { + %res = add i32 %arg1, %arg2 + ret i32 %res +} diff --git a/test/CodeGen/AMDGPU/add.ll b/test/CodeGen/AMDGPU/add.ll index 2ddfa9649ac9..f37247361ece 100644 --- a/test/CodeGen/AMDGPU/add.ll +++ b/test/CodeGen/AMDGPU/add.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ;FUNC-LABEL: {{^}}test1: ;EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} @@ -123,12 +123,11 @@ entry: ; SI: s_add_u32 ; SI: s_addc_u32 -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] -; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-DAG: ADDC_UINT ; EG-DAG: ADD_INT -; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-NOT: SUB define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: @@ -145,12 +144,11 @@ entry: ; FUNC-LABEL: {{^}}add64_sgpr_vgpr: ; SI-NOT: v_addc_u32_e32 s -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] -; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-DAG: ADDC_UINT ; EG-DAG: ADD_INT -; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-NOT: SUB define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: @@ -165,12 +163,11 @@ entry: ; SI: s_add_u32 ; SI: s_addc_u32 -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] -; EG-DAG: ADD_INT {{[* ]*}}[[LO]] +; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-DAG: ADDC_UINT ; EG-DAG: ADD_INT -; EG-DAG: ADD_INT {{[* ]*}}[[HI]] +; EG-DAG: ADD_INT {{[* ]*}} ; EG-NOT: SUB define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: diff --git a/test/CodeGen/AMDGPU/add_i64.ll b/test/CodeGen/AMDGPU/add_i64.ll index 8346add7df97..3d360b7d0b7a 100644 --- a/test/CodeGen/AMDGPU/add_i64.ll +++ b/test/CodeGen/AMDGPU/add_i64.ll @@ -1,13 +1,13 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() readnone +declare i32 @llvm.amdgcn.workitem.id.x() readnone ; SI-LABEL: {{^}}test_i64_vreg: ; SI: v_add_i32 ; SI: v_addc_u32 define void @test_i64_vreg(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.r600.read.tidig.x() readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr i64, i64 addrspace(1)* %inB, i32 %tid %a = load i64, i64 addrspace(1)* %a_ptr @@ -59,7 +59,7 @@ define void @test_v2i64_sreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> %a, ; SI: v_add_i32 ; SI: v_addc_u32 define void @test_v2i64_vreg(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %inA, <2 x i64> addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.r600.read.tidig.x() readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone %a_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inA, i32 %tid %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %inB, i32 %tid %a = load <2 x i64>, <2 x i64> addrspace(1)* %a_ptr diff --git a/test/CodeGen/AMDGPU/address-space.ll b/test/CodeGen/AMDGPU/address-space.ll deleted file mode 100644 index 3aa2f653bf9c..000000000000 --- a/test/CodeGen/AMDGPU/address-space.ll +++ /dev/null @@ -1,32 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s - -; Test that codegenprepare understands address space sizes - -%struct.foo = type { [3 x float], [3 x float] } - -; CHECK-LABEL: {{^}}do_as_ptr_calcs: -; CHECK: s_load_dword [[SREG1:s[0-9]+]], -; CHECK: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]] -; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:12 -; CHECK-DAG: ds_read_b32 v{{[0-9]+}}, [[VREG1]] offset:20 -define void @do_as_ptr_calcs(%struct.foo addrspace(3)* nocapture %ptr) nounwind { -entry: - %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 - %y = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2 - br label %bb32 - -bb32: - %a = load float, float addrspace(3)* %x, align 4 - %b = load float, float addrspace(3)* %y, align 4 - %cmp = fcmp one float %a, %b - br i1 %cmp, label %bb34, label %bb33 - -bb33: - unreachable - -bb34: - unreachable -} - - diff --git a/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll b/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll new file mode 100644 index 000000000000..67a193999204 --- /dev/null +++ b/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll @@ -0,0 +1,106 @@ +; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s + +declare void @llvm.memcpy.p1i32.p4i32.i32(i32 addrspace(1)* nocapture, i32 addrspace(4)* nocapture, i32, i32, i1) #0 + +@lds.i32 = unnamed_addr addrspace(3) global i32 undef, align 4 +@lds.arr = unnamed_addr addrspace(3) global [256 x i32] undef, align 4 + +@global.i32 = unnamed_addr addrspace(1) global i32 undef, align 4 +@global.arr = unnamed_addr addrspace(1) global [256 x i32] undef, align 4 + +; HSA: @store_cast_0_flat_to_group_addrspacecast() #1 +define void @store_cast_0_flat_to_group_addrspacecast() #1 { + store i32 7, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*) + ret void +} + +; HSA: @store_cast_0_group_to_flat_addrspacecast() #2 +define void @store_cast_0_group_to_flat_addrspacecast() #1 { + store i32 7, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*) + ret void +} + +; HSA: define void @store_constant_cast_group_gv_to_flat() #2 +define void @store_constant_cast_group_gv_to_flat() #1 { + store i32 7, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds.i32 to i32 addrspace(4)*) + ret void +} + +; HSA: @store_constant_cast_group_gv_gep_to_flat() #2 +define void @store_constant_cast_group_gv_gep_to_flat() #1 { + store i32 7, i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) + ret void +} + +; HSA: @store_constant_cast_global_gv_to_flat() #1 +define void @store_constant_cast_global_gv_to_flat() #1 { + store i32 7, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global.i32 to i32 addrspace(4)*) + ret void +} + +; HSA: @store_constant_cast_global_gv_gep_to_flat() #1 +define void @store_constant_cast_global_gv_gep_to_flat() #1 { + store i32 7, i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(1)* @global.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) + ret void +} + +; HSA: @load_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #2 +define void @load_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #1 { + %val = load i32, i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; HSA: @atomicrmw_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #2 +define void @atomicrmw_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #1 { + %val = atomicrmw add i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8), i32 1 seq_cst + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; HSA: @cmpxchg_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #2 +define void @cmpxchg_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #1 { + %val = cmpxchg i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8), i32 0, i32 1 seq_cst seq_cst + %val0 = extractvalue { i32, i1 } %val, 0 + store i32 %val0, i32 addrspace(1)* %out + ret void +} + +; HSA: @memcpy_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #2 +define void @memcpy_constant_cast_group_gv_gep_to_flat(i32 addrspace(1)* %out) #1 { + call void @llvm.memcpy.p1i32.p4i32.i32(i32 addrspace(1)* %out, i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8), i32 32, i32 4, i1 false) + ret void +} + +; Can't just search the pointer value +; HSA: @store_value_constant_cast_lds_gv_gep_to_flat(i32 addrspace(4)* addrspace(1)* %out) #2 +define void @store_value_constant_cast_lds_gv_gep_to_flat(i32 addrspace(4)* addrspace(1)* %out) #1 { + store i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8), i32 addrspace(4)* addrspace(1)* %out + ret void +} + +; Can't just search pointer types +; HSA: @store_ptrtoint_value_constant_cast_lds_gv_gep_to_flat(i64 addrspace(1)* %out) #2 +define void @store_ptrtoint_value_constant_cast_lds_gv_gep_to_flat(i64 addrspace(1)* %out) #1 { + store i64 ptrtoint (i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) to i64), i64 addrspace(1)* %out + ret void +} + +; Cast group to flat, do GEP, cast back to group +; HSA: @store_constant_cast_group_gv_gep_to_flat_to_group() #2 +define void @store_constant_cast_group_gv_gep_to_flat_to_group() #1 { + store i32 7, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) to i32 addrspace(3)*) + ret void +} + +; HSA: @ret_constant_cast_group_gv_gep_to_flat_to_group() #2 +define i32 addrspace(3)* @ret_constant_cast_group_gv_gep_to_flat_to_group() #1 { + ret i32 addrspace(3)* addrspacecast (i32 addrspace(4)* getelementptr ([256 x i32], [256 x i32] addrspace(4)* addrspacecast ([256 x i32] addrspace(3)* @lds.arr to [256 x i32] addrspace(4)*), i64 0, i64 8) to i32 addrspace(3)*) +} + +; HSA: attributes #0 = { argmemonly nounwind } +; HSA: attributes #1 = { nounwind } +; HSA: attributes #2 = { nounwind "amdgpu-queue-ptr" } + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/addrspacecast.ll b/test/CodeGen/AMDGPU/addrspacecast.ll index 61bcd4b3c093..5a173e954f8d 100644 --- a/test/CodeGen/AMDGPU/addrspacecast.ll +++ b/test/CodeGen/AMDGPU/addrspacecast.ll @@ -1,18 +1,208 @@ -; RUN: not llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=HSA %s -; ERROR: unsupported addrspacecast not implemented +; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_dispatch_ptr = 0 +; HSA: enable_sgpr_queue_ptr = 1 -; XUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s -; XUN: llc -O0 -march=amdgcn -mcpu=bonaire -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s -; XUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-NO-PROMOTE %s -; XUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=+promote-alloca < %s | FileCheck -check-prefix=CHECK -check-prefix=CHECK-PROMOTE %s +; HSA-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} +; HSA-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10{{$}} + +; HSA-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] +; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] + +; HSA-DAG: v_cmp_ne_i32_e64 vcc, -1, [[PTR]] +; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]] +; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 + +; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] +define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { + %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* + store volatile i32 7, i32 addrspace(4)* %stof + ret void +} + +; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_dispatch_ptr = 0 +; HSA: enable_sgpr_queue_ptr = 1 + +; HSA-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} +; HSA-DAG: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11{{$}} + +; HSA-DAG: v_mov_b32_e32 [[VAPERTURE:v[0-9]+]], [[APERTURE]] +; HSA-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] + +; HSA-DAG: v_cmp_ne_i32_e64 vcc, -1, [[PTR]] +; HSA-DAG: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]] +; HSA-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 + +; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] +define void @use_private_to_flat_addrspacecast(i32* %ptr) #0 { + %stof = addrspacecast i32* %ptr to i32 addrspace(4)* + store volatile i32 7, i32 addrspace(4)* %stof + ret void +} + +; no-op +; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: +; HSA: enable_sgpr_queue_ptr = 0 + +; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} +; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] +; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 +; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] +define void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { + %stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* + store volatile i32 7, i32 addrspace(4)* %stof + ret void +} + +; no-op +; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: +; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} +; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] +; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] +; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} +define void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 { + %stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* + %ld = load volatile i32, i32 addrspace(4)* %stof + ret void +} + +; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_dispatch_ptr = 0 +; HSA: enable_sgpr_queue_ptr = 0 + +; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} +; HSA-DAG: v_cmp_ne_i64_e64 vcc, 0, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} +; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] +; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] +; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} +; HSA: ds_write_b32 [[CASTPTR]], v[[K]] +define void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #0 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* + store volatile i32 0, i32 addrspace(3)* %ftos + ret void +} + +; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_dispatch_ptr = 0 +; HSA: enable_sgpr_queue_ptr = 0 + +; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} +; HSA-DAG: v_cmp_ne_i64_e64 vcc, 0, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} +; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] +; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] +; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} +; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +define void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #0 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32* + store volatile i32 0, i32* %ftos + ret void +} + +; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: +; HSA: enable_sgpr_queue_ptr = 0 + +; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 +; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] +; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 +; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] +define void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* + store volatile i32 0, i32 addrspace(1)* %ftos + ret void +} + +; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: +; HSA: enable_sgpr_queue_ptr = 0 + +; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 +; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 +define void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #0 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* + load volatile i32, i32 addrspace(2)* %ftos + ret void +} + +; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: +; HSA: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 +; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] +; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} +; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] +define void @cast_0_group_to_flat_addrspacecast() #0 { + %cast = addrspacecast i32 addrspace(3)* null to i32 addrspace(4)* + store i32 7, i32 addrspace(4)* %cast + ret void +} + +; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: +; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} +; HSA: ds_write_b32 [[PTR]], [[K]] +define void @cast_0_flat_to_group_addrspacecast() #0 { + %cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(3)* + store i32 7, i32 addrspace(3)* %cast + ret void +} + +; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: +; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} +; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] +define void @cast_neg1_group_to_flat_addrspacecast() #0 { + %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32 addrspace(4)* + store i32 7, i32 addrspace(4)* %cast + ret void +} + +; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: +; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} +; HSA: ds_write_b32 [[PTR]], [[K]] +define void @cast_neg1_flat_to_group_addrspacecast() #0 { + %cast = addrspacecast i32 addrspace(4)* inttoptr (i64 -1 to i32 addrspace(4)*) to i32 addrspace(3)* + store i32 7, i32 addrspace(3)* %cast + ret void +} + +; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast: +; HSA: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x11 +; HSA-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] +; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} +; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] +define void @cast_0_private_to_flat_addrspacecast() #0 { + %cast = addrspacecast i32* null to i32 addrspace(4)* + store i32 7, i32 addrspace(4)* %cast + ret void +} + +; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: +; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} +; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} +; HSA: buffer_store_dword [[K]], [[PTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen +define void @cast_0_flat_to_private_addrspacecast() #0 { + %cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(0)* + store i32 7, i32* %cast + ret void +} ; Disable optimizations in case there are optimizations added that ; specialize away generic pointer accesses. -; CHECK-LABEL: {{^}}branch_use_flat_i32: -; CHECK: flat_store_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} -; CHECK: s_endpgm +; HSA-LABEL: {{^}}branch_use_flat_i32: +; HSA: flat_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} +; HSA: s_endpgm define void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { entry: %cmp = icmp ne i32 %c, 0 @@ -34,33 +224,30 @@ end: ret void } -; TODO: This should not be zero when registers are used for small -; scratch allocations again. - ; Check for prologue initializing special SGPRs pointing to scratch. -; CHECK-LABEL: {{^}}store_flat_scratch: -; CHECK: s_movk_i32 flat_scratch_lo, 0 -; CHECK-NO-PROMOTE: s_movk_i32 flat_scratch_hi, 0x28{{$}} -; CHECK-PROMOTE: s_movk_i32 flat_scratch_hi, 0x0{{$}} -; CHECK: flat_store_dword -; CHECK: s_barrier -; CHECK: flat_load_dword +; HSA-LABEL: {{^}}store_flat_scratch: +; HSA-DAG: s_mov_b32 flat_scratch_lo, s9 +; HSA-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11 +; HSA: s_lshr_b32 flat_scratch_hi, [[ADD]], 8 +; HSA: flat_store_dword +; HSA: s_barrier +; HSA: flat_load_dword define void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { %alloca = alloca i32, i32 9, align 4 - %x = call i32 @llvm.r600.read.tidig.x() #3 + %x = call i32 @llvm.amdgcn.workitem.id.x() #2 %pptr = getelementptr i32, i32* %alloca, i32 %x %fptr = addrspacecast i32* %pptr to i32 addrspace(4)* store i32 %x, i32 addrspace(4)* %fptr ; Dummy call - call void @llvm.AMDGPU.barrier.local() #1 + call void @llvm.amdgcn.s.barrier() #1 %reload = load i32, i32 addrspace(4)* %fptr, align 4 store i32 %reload, i32 addrspace(1)* %out, align 4 ret void } -declare void @llvm.AMDGPU.barrier.local() #1 -declare i32 @llvm.r600.read.tidig.x() #3 +declare void @llvm.amdgcn.s.barrier() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #2 attributes #0 = { nounwind } attributes #1 = { nounwind convergent } -attributes #3 = { nounwind readnone } +attributes #2 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/amdgcn.private-memory.ll b/test/CodeGen/AMDGPU/amdgcn.private-memory.ll new file mode 100644 index 000000000000..ad6843770fd6 --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgcn.private-memory.ll @@ -0,0 +1,31 @@ +; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s +; RUN: llc -mattr=+promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE -check-prefix=HSA %s +; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s +; RUN: llc -mattr=-promote-alloca,-flat-for-global -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA -check-prefix=HSA %s +; RUN: llc -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-PROMOTE %s +; RUN: llc -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-ALLOCA %s + + +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + + +; Make sure we don't overwrite workitem information with private memory + +; GCN-LABEL: {{^}}work_item_info: +; GCN-NOT: v0 +; GCN: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, v0, v{{[0-9]+}} +; GCN: buffer_store_dword [[RESULT]] +define void @work_item_info(i32 addrspace(1)* %out, i32 %in) { +entry: + %0 = alloca [2 x i32] + %1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 + %2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 + store i32 0, i32* %1 + store i32 1, i32* %2 + %3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in + %4 = load i32, i32* %3 + %5 = call i32 @llvm.amdgcn.workitem.id.x() + %6 = add i32 %4, %5 + store i32 %6, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/amdgcn.work-item-intrinsics.ll b/test/CodeGen/AMDGPU/amdgcn.work-item-intrinsics.ll new file mode 100644 index 000000000000..b1b3b9930d1f --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgcn.work-item-intrinsics.ll @@ -0,0 +1,114 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}workdim: + +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +define void @workdim (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.read.workdim() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; The workgroup.id values are stored in sgprs offset by the number of user +; sgprs. + +; FUNC-LABEL: {{^}}workgroup_id_x: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}} +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @workgroup_id_x(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workgroup.id.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}workgroup_id_y: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3 +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +define void @workgroup_id_y(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workgroup.id.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}workgroup_id_z: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}} +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @workgroup_id_z(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workgroup.id.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 132{{$}} + +; FUNC-LABEL: {{^}}workitem_id_x: +; GCN-NOHSA: buffer_store_dword v0 +define void @workitem_id_x(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workitem.id.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 2180{{$}} + +; FUNC-LABEL: {{^}}workitem_id_y: + +; GCN-NOHSA: buffer_store_dword v1 +define void @workitem_id_y(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workitem.id.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 4228{{$}} + +; FUNC-LABEL: {{^}}workitem_id_z: +; GCN-NOHSA: buffer_store_dword v2 +define void @workitem_id_z(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.workitem.id.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.amdgcn.workgroup.id.x() #0 +declare i32 @llvm.amdgcn.workgroup.id.y() #0 +declare i32 @llvm.amdgcn.workgroup.id.z() #0 + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i32 @llvm.amdgcn.workitem.id.y() #0 +declare i32 @llvm.amdgcn.workitem.id.z() #0 + +declare i32 @llvm.amdgcn.read.workdim() #0 diff --git a/test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll b/test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll new file mode 100644 index 000000000000..a12132f425d9 --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgpu-codegenprepare.ll @@ -0,0 +1,8 @@ +; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare < %s | FileCheck %s +; RUN: opt -S -amdgpu-codegenprepare < %s +; Make sure this doesn't crash with no triple + +; CHECK-LABEL: @foo( +define void @foo() { + ret void +} diff --git a/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll b/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll new file mode 100644 index 000000000000..dd16907b748c --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgpu-shader-calling-convention.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + + +; GCN-LABEL: {{^}}shader_cc: +; GCN: v_add_i32_e32 v0, vcc, s8, v0 +define amdgpu_cs float @shader_cc(<4 x i32> inreg, <4 x i32> inreg, i32 inreg %w, float %v) { + %vi = bitcast float %v to i32 + %x = add i32 %vi, %w + %xf = bitcast i32 %x to float + ret float %xf +} + +; GCN-LABEL: {{^}}kernel_cc: +; GCN: s_endpgm +define float @kernel_cc(<4 x i32> inreg, <4 x i32> inreg, i32 inreg %w, float %v) { + %vi = bitcast float %v to i32 + %x = add i32 %vi, %w + %xf = bitcast i32 %x to float + ret float %xf +} diff --git a/test/CodeGen/AMDGPU/amdgpu.private-memory.ll b/test/CodeGen/AMDGPU/amdgpu.private-memory.ll new file mode 100644 index 000000000000..7b5158629091 --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgpu.private-memory.ll @@ -0,0 +1,530 @@ +; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC +; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE +; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC +; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA +; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC +; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC + +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -check-prefix=HSAOPT -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -check-prefix=NOHSAOPT -check-prefix=OPT %s + +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC + + +; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4 +; HSAOPT: @high_alignment.stack = internal unnamed_addr addrspace(3) global [256 x [8 x i32]] undef, align 16 + + +; FUNC-LABEL: {{^}}mova_same_clause: +; OPT-LABEL: @mova_same_clause( + +; R600: LDS_WRITE +; R600: LDS_WRITE +; R600: LDS_READ +; R600: LDS_READ + +; HSA-PROMOTE: .amd_kernel_code_t +; HSA-PROMOTE: workgroup_group_segment_byte_size = 5120 +; HSA-PROMOTE: .end_amd_kernel_code_t + +; FIXME: These should be merged +; HSA-PROMOTE: s_load_dword s{{[0-9]+}}, s[4:5], 0x1 +; HSA-PROMOTE: s_load_dword s{{[0-9]+}}, s[4:5], 0x2 + +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_write_b32 +; SI-PROMOTE: ds_read_b32 +; SI-PROMOTE: ds_read_b32 + +; HSA-ALLOCA: .amd_kernel_code_t +; FIXME: Creating the emergency stack slots causes us to over-estimate scratch +; by 4 bytes. +; HSA-ALLOCA: workitem_private_segment_byte_size = 24 +; HSA-ALLOCA: .end_amd_kernel_code_t + +; HSA-ALLOCA: s_mov_b32 flat_scratch_lo, s7 +; HSA-ALLOCA: s_add_u32 s6, s6, s9 +; HSA-ALLOCA: s_lshr_b32 flat_scratch_hi, s6, 8 + +; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 +; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 + + +; HSAOPT: [[DISPATCH_PTR:%[0-9]+]] = call noalias nonnull dereferenceable(64) i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() +; HSAOPT: [[CAST_DISPATCH_PTR:%[0-9]+]] = bitcast i8 addrspace(2)* [[DISPATCH_PTR]] to i32 addrspace(2)* +; HSAOPT: [[GEP0:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(2)* [[CAST_DISPATCH_PTR]], i64 1 +; HSAOPT: [[LDXY:%[0-9]+]] = load i32, i32 addrspace(2)* [[GEP0]], align 4, !invariant.load !0 +; HSAOPT: [[GEP1:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(2)* [[CAST_DISPATCH_PTR]], i64 2 +; HSAOPT: [[LDZU:%[0-9]+]] = load i32, i32 addrspace(2)* [[GEP1]], align 4, !range !1, !invariant.load !0 +; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 16 + +; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.x(), !range !1 +; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.y(), !range !1 +; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.z(), !range !1 + +; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]] +; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]] +; HSAOPT: [[Y_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[WORKITEM_ID_Y]], [[LDZU]] +; HSAOPT: [[ADD_YZ_X_X_YZ_SIZE:%[0-9]+]] = add i32 [[YZ_X_XID]], [[Y_X_Z_SIZE]] +; HSAOPT: [[ADD_ZID:%[0-9]+]] = add i32 [[ADD_YZ_X_X_YZ_SIZE]], [[WORKITEM_ID_Z]] + +; HSAOPT: [[LOCAL_GEP:%[0-9]+]] = getelementptr inbounds [256 x [5 x i32]], [256 x [5 x i32]] addrspace(3)* @mova_same_clause.stack, i32 0, i32 [[ADD_ZID]] +; HSAOPT: %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(3)* [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}} +; HSAOPT: %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(3)* [[LOCAL_GEP]], i32 0, i32 {{%[0-9]+}} +; HSAOPT: %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(3)* [[LOCAL_GEP]], i32 0, i32 0 +; HSAOPT: %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(3)* [[LOCAL_GEP]], i32 0, i32 1 + + +; NOHSAOPT: call i32 @llvm.r600.read.local.size.y(), !range !0 +; NOHSAOPT: call i32 @llvm.r600.read.local.size.z(), !range !0 +; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.x(), !range !0 +; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.y(), !range !0 +; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.z(), !range !0 +define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; OPT-LABEL: @high_alignment( +; OPT: getelementptr inbounds [256 x [8 x i32]], [256 x [8 x i32]] addrspace(3)* @high_alignment.stack, i32 0, i32 %{{[0-9]+}} +define void @high_alignment(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca [8 x i32], align 16 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; FUNC-LABEL: {{^}}no_replace_inbounds_gep: +; OPT-LABEL: @no_replace_inbounds_gep( +; OPT: alloca [5 x i32] + +; SI-NOT: ds_write +define void @no_replace_inbounds_gep(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; This test checks that the stack offset is calculated correctly for structs. +; All register loads/stores should be optimized away, so there shouldn't be +; any MOVA instructions. +; +; XXX: This generated code has unnecessary MOVs, we should be able to optimize +; this. + +; FUNC-LABEL: {{^}}multiple_structs: +; OPT-LABEL: @multiple_structs( + +; R600-NOT: MOVA_INT +; SI-NOT: v_movrel +; SI-NOT: v_movrel +%struct.point = type { i32, i32 } + +define void @multiple_structs(i32 addrspace(1)* %out) #0 { +entry: + %a = alloca %struct.point + %b = alloca %struct.point + %a.x.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 + %a.y.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 1 + %b.x.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 + %b.y.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 1 + store i32 0, i32* %a.x.ptr + store i32 1, i32* %a.y.ptr + store i32 2, i32* %b.x.ptr + store i32 3, i32* %b.y.ptr + %a.indirect.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 + %b.indirect.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 + %a.indirect = load i32, i32* %a.indirect.ptr + %b.indirect = load i32, i32* %b.indirect.ptr + %0 = add i32 %a.indirect, %b.indirect + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; Test direct access of a private array inside a loop. The private array +; loads and stores should be lowered to copies, so there shouldn't be any +; MOVA instructions. + +; FUNC-LABEL: {{^}}direct_loop: +; R600-NOT: MOVA_INT +; SI-NOT: v_movrel + +define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { +entry: + %prv_array_const = alloca [2 x i32] + %prv_array = alloca [2 x i32] + %a = load i32, i32 addrspace(1)* %in + %b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %b = load i32, i32 addrspace(1)* %b_src_ptr + %a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 + store i32 %a, i32* %a_dst_ptr + %b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1 + store i32 %b, i32* %b_dst_ptr + br label %for.body + +for.body: + %inc = phi i32 [0, %entry], [%count, %for.body] + %x_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 + %x = load i32, i32* %x_ptr + %y_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 + %y = load i32, i32* %y_ptr + %xy = add i32 %x, %y + store i32 %xy, i32* %y_ptr + %count = add i32 %inc, 1 + %done = icmp eq i32 %count, 4095 + br i1 %done, label %for.end, label %for.body + +for.end: + %value_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 + %value = load i32, i32* %value_ptr + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}short_array: + +; R600: MOVA_INT + +; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x68,0xe0 +; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:2 ; encoding: [0x02,0x10,0x68,0xe0 +; SI-PROMOTE: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} +define void @short_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %0 = alloca [2 x i16] + %1 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 0 + %2 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 1 + store i16 0, i16* %1 + store i16 1, i16* %2 + %3 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 %index + %4 = load i16, i16* %3 + %5 = sext i16 %4 to i32 + store i32 %5, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}char_array: + +; R600: MOVA_INT + +; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x60,0xe0 +; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:1 ; encoding: [0x01,0x10,0x60,0xe0 +define void @char_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %0 = alloca [2 x i8] + %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0 + %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1 + store i8 0, i8* %1 + store i8 1, i8* %2 + %3 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 %index + %4 = load i8, i8* %3 + %5 = sext i8 %4 to i32 + store i32 %5, i32 addrspace(1)* %out + ret void + +} + +; Test that two stack objects are not stored in the same register +; The second stack object should be in T3.X +; FUNC-LABEL: {{^}}no_overlap: +; R600_CHECK: MOV +; R600_CHECK: [[CHAN:[XYZW]]]+ +; R600-NOT: [[CHAN]]+ +; SI: v_mov_b32_e32 v3 +define void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 { +entry: + %0 = alloca [3 x i8], align 1 + %1 = alloca [2 x i8], align 1 + %2 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 0 + %3 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 1 + %4 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 2 + %5 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 0 + %6 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 1 + store i8 0, i8* %2 + store i8 1, i8* %3 + store i8 2, i8* %4 + store i8 1, i8* %5 + store i8 0, i8* %6 + %7 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 %in + %8 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 %in + %9 = load i8, i8* %7 + %10 = load i8, i8* %8 + %11 = add i8 %9, %10 + %12 = sext i8 %11 to i32 + store i32 %12, i32 addrspace(1)* %out + ret void +} + +define void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i8]] + %gep0 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1 + store i8 0, i8* %gep0 + store i8 1, i8* %gep1 + %gep2 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index + %load = load i8, i8* %gep2 + %sext = sext i8 %load to i32 + store i32 %sext, i32 addrspace(1)* %out + ret void +} + +define void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i64]] + %gep0 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1 + store i64 0, i64* %gep0 + store i64 1, i64* %gep1 + %gep2 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index + %load = load i64, i64* %gep2 + store i64 %load, i64 addrspace(1)* %out + ret void +} + +%struct.pair32 = type { i32, i32 } + +define void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x %struct.pair32]] + %gep0 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1 + %gep1 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0 + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x %struct.pair32] + %gep0 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1 + %gep1 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0 + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind { +entry: + %tmp = alloca [2 x i32] + %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 + %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 + store i32 0, i32* %tmp1 + store i32 1, i32* %tmp2 + %cmp = icmp eq i32 %in, 0 + %sel = select i1 %cmp, i32* %tmp1, i32* %tmp2 + %load = load i32, i32* %sel + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it +; finds one, it should stop trying to promote. + +; FUNC-LABEL: ptrtoint: +; SI-NOT: ds_write +; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen +; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:5 ; +define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32] + %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + store i32 5, i32* %tmp0 + %tmp1 = ptrtoint [16 x i32]* %alloca to i32 + %tmp2 = add i32 %tmp1, 5 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = getelementptr i32, i32* %tmp3, i32 %b + %tmp5 = load i32, i32* %tmp4 + store i32 %tmp5, i32 addrspace(1)* %out + ret void +} + +; OPT-LABEL: @pointer_typed_alloca( +; OPT: getelementptr inbounds [256 x i32 addrspace(1)*], [256 x i32 addrspace(1)*] addrspace(3)* @pointer_typed_alloca.A.addr, i32 0, i32 %{{[0-9]+}} +; OPT: load i32 addrspace(1)*, i32 addrspace(1)* addrspace(3)* %{{[0-9]+}}, align 4 +define void @pointer_typed_alloca(i32 addrspace(1)* %A) { +entry: + %A.addr = alloca i32 addrspace(1)*, align 4 + store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 + %ld0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 + %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0 + store i32 1, i32 addrspace(1)* %arrayidx, align 4 + %ld1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 + %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1 + store i32 2, i32 addrspace(1)* %arrayidx1, align 4 + %ld2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %ld2, i32 2 + store i32 3, i32 addrspace(1)* %arrayidx2, align 4 + ret void +} + +; HSAOPT: !0 = !{} +; HSAOPT: !1 = !{i32 0, i32 2048} + +; NOHSAOPT: !0 = !{i32 0, i32 2048} + + +; FUNC-LABEL: v16i32_stack: + +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT + +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword + +define void @v16i32_stack(<16 x i32> addrspace(1)* %out, i32 %a) { + %alloca = alloca [2 x <16 x i32>] + %tmp0 = getelementptr [2 x <16 x i32>], [2 x <16 x i32>]* %alloca, i32 0, i32 %a + %tmp5 = load <16 x i32>, <16 x i32>* %tmp0 + store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: v16float_stack: + +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT +; R600: MOVA_INT + +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword +; SI: buffer_load_dword + +define void @v16float_stack(<16 x float> addrspace(1)* %out, i32 %a) { + %alloca = alloca [2 x <16 x float>] + %tmp0 = getelementptr [2 x <16 x float>], [2 x <16 x float>]* %alloca, i32 0, i32 %a + %tmp5 = load <16 x float>, <16 x float>* %tmp0 + store <16 x float> %tmp5, <16 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: v2float_stack: + +; R600: MOVA_INT +; R600: MOVA_INT + +; SI: buffer_load_dword +; SI: buffer_load_dword + +define void @v2float_stack(<2 x float> addrspace(1)* %out, i32 %a) { + %alloca = alloca [16 x <2 x float>] + %tmp0 = getelementptr [16 x <2 x float>], [16 x <2 x float>]* %alloca, i32 0, i32 %a + %tmp5 = load <2 x float>, <2 x float>* %tmp0 + store <2 x float> %tmp5, <2 x float> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="2" } diff --git a/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll b/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll new file mode 100644 index 000000000000..853788b92aae --- /dev/null +++ b/test/CodeGen/AMDGPU/amdgpu.work-item-intrinsics.deprecated.ll @@ -0,0 +1,268 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; Legacy intrinsics that just read implicit parameters + +; FUNC-LABEL: {{^}}workdim_legacy: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[2].Z +define void @workdim_legacy (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.AMDGPU.read.workdim() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}ngroups_x: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[0].X +define void @ngroups_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}ngroups_y: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y +define void @ngroups_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}ngroups_z: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z +define void @ngroups_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.ngroups.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_size_x: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[0].W +define void @global_size_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_size_y: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[1].X +define void @global_size_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_size_z: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y +define void @global_size_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.global.size.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_size_x: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z +define void @local_size_x (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_size_y: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[1].W +define void @local_size_y (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_size_z: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20 +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[2].X +define void @local_size_z (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.local.size.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; Legacy use of r600 intrinsics by GCN + +; The tgid values are stored in sgprs offset by the number of user +; sgprs. + +; FUNC-LABEL: {{^}}tgid_x_legacy: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}} +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @tgid_x_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tgid_y_legacy: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3 +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +define void @tgid_y_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tgid_z_legacy: +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}} +; GCN-NOHSA: buffer_store_dword [[VVAL]] + +; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @tgid_z_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 132{{$}} + +; FUNC-LABEL: {{^}}tidig_x_legacy: +; GCN-NOHSA: buffer_store_dword v0 +define void @tidig_x_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 2180{{$}} + +; FUNC-LABEL: {{^}}tidig_y_legacy: + +; GCN-NOHSA: buffer_store_dword v1 +define void @tidig_y_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-NOHSA: .section .AMDGPU.config +; GCN-NOHSA: .long 47180 +; GCN-NOHSA-NEXT: .long 4228{{$}} + +; FUNC-LABEL: {{^}}tidig_z_legacy: +; GCN-NOHSA: buffer_store_dword v2 +define void @tidig_z_legacy(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.r600.read.ngroups.x() #0 +declare i32 @llvm.r600.read.ngroups.y() #0 +declare i32 @llvm.r600.read.ngroups.z() #0 + +declare i32 @llvm.r600.read.global.size.x() #0 +declare i32 @llvm.r600.read.global.size.y() #0 +declare i32 @llvm.r600.read.global.size.z() #0 + +declare i32 @llvm.r600.read.local.size.x() #0 +declare i32 @llvm.r600.read.local.size.y() #0 +declare i32 @llvm.r600.read.local.size.z() #0 + +declare i32 @llvm.r600.read.tgid.x() #0 +declare i32 @llvm.r600.read.tgid.y() #0 +declare i32 @llvm.r600.read.tgid.z() #0 + +declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.r600.read.tidig.y() #0 +declare i32 @llvm.r600.read.tidig.z() #0 + +declare i32 @llvm.AMDGPU.read.workdim() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/and-gcn.ll b/test/CodeGen/AMDGPU/and-gcn.ll new file mode 100644 index 000000000000..dde5f8c21769 --- /dev/null +++ b/test/CodeGen/AMDGPU/and-gcn.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}v_and_i64_br: +; SI: v_and_b32 +; SI: v_and_b32 +define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { +entry: + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 + br i1 %tmp0, label %if, label %endif + +if: + %a = load i64, i64 addrspace(1)* %aptr, align 8 + %b = load i64, i64 addrspace(1)* %bptr, align 8 + %and = and i64 %a, %b + br label %endif + +endif: + %tmp1 = phi i64 [%and, %if], [0, %entry] + store i64 %tmp1, i64 addrspace(1)* %out, align 8 + ret void +} + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/and.ll b/test/CodeGen/AMDGPU/and.ll index f83fb16101fb..0046bc93826e 100644 --- a/test/CodeGen/AMDGPU/and.ll +++ b/test/CodeGen/AMDGPU/and.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() #0 @@ -177,50 +177,78 @@ define void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) { ret void } -; FUNC-LABEL: {{^}}s_and_constant_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} +; FUNC-LABEL: {{^}}s_and_constant_i64: +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}} +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}} +; SI: buffer_store_dwordx2 define void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) { - %and = and i64 %a, 281474976710655 + %and = and i64 %a, 549756338176 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}v_and_i64: -; SI: v_and_b32 -; SI: v_and_b32 -define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { - %a = load i64, i64 addrspace(1)* %aptr, align 8 - %b = load i64, i64 addrspace(1)* %bptr, align 8 - %and = and i64 %a, %b +; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64: +; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}} +; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}} +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}} +define void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { + %and0 = and i64 %a, 549756338176 + %and1 = and i64 %b, 549756338176 + store volatile i64 %and0, i64 addrspace(1)* %out + store volatile i64 %and1, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64: +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}} +; SI-NOT: and +; SI: buffer_store_dwordx2 +define void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i64 %a) { + %and = and i64 %a, 1234567 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}v_and_i64_br: +; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64: +; SI: s_load_dword [[A:s[0-9]+]] +; SI: s_load_dword [[B:s[0-9]+]] +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_lshl_b32 [[A]], [[A]], 1 +; SI: s_lshl_b32 [[B]], [[B]], 1 +; SI: s_and_b32 s{{[0-9]+}}, [[A]], 62 +; SI: s_and_b32 s{{[0-9]+}}, [[B]], 62 +; SI-NOT: and +; SI: buffer_store_dwordx2 +define void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 %a, i64 %b, i64 %c) { + %shl.a = shl i64 %a, 1 + %shl.b = shl i64 %b, 1 + %and0 = and i64 %shl.a, 62 + %and1 = and i64 %shl.b, 62 + %add0 = add i64 %and0, %c + %add1 = add i64 %and1, %c + store volatile i64 %add0, i64 addrspace(1)* %out + store volatile i64 %add1, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_and_i64: ; SI: v_and_b32 ; SI: v_and_b32 -define void @v_and_i64_br(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr, i32 %cond) { -entry: - %tmp0 = icmp eq i32 %cond, 0 - br i1 %tmp0, label %if, label %endif - -if: +define void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) { %a = load i64, i64 addrspace(1)* %aptr, align 8 %b = load i64, i64 addrspace(1)* %bptr, align 8 %and = and i64 %a, %b - br label %endif - -endif: - %tmp1 = phi i64 [%and, %if], [0, %entry] - store i64 %tmp1, i64 addrspace(1)* %out, align 8 + store i64 %and, i64 addrspace(1)* %out, align 8 ret void } ; FUNC-LABEL: {{^}}v_and_constant_i64: -; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207 -; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}} -; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], {{v[0-9]+}} -; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], {{v[0-9]+}} +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}} +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}} ; SI: buffer_store_dwordx2 define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load i64, i64 addrspace(1)* %aptr, align 8 @@ -229,10 +257,54 @@ define void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) ret void } -; FIXME: Should replace and 0 +; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64: +; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} +; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} +; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}} +; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}} +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]] +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]] +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]] +; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]] +; SI: buffer_store_dwordx2 +; SI: buffer_store_dwordx2 +define void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { + %a = load volatile i64, i64 addrspace(1)* %aptr + %b = load volatile i64, i64 addrspace(1)* %aptr + %and0 = and i64 %a, 1231231234567 + %and1 = and i64 %b, 1231231234567 + store volatile i64 %and0, i64 addrspace(1)* %out + store volatile i64 %and1, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64: +; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}} +; SI-NOT: and +; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}} +; SI-NOT: and +; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]] +; SI-NOT: and +; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]] +; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]] +; SI-NOT: and +; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]] +define void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { + %a = load volatile i64, i64 addrspace(1)* %aptr + %b = load volatile i64, i64 addrspace(1)* %aptr + %and0 = and i64 %a, 63 + %and1 = and i64 %b, 63 + store volatile i64 %and0, i64 addrspace(1)* %out + store volatile i64 %and1, i64 addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant: -; SI: v_and_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} -; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: and +; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]] +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load i64, i64 addrspace(1)* %aptr, align 8 %and = and i64 %a, 1234567 @@ -240,10 +312,12 @@ define void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* ret void } -; FIXME: Replace and 0 with mov 0 ; FUNC-LABEL: {{^}}v_and_inline_imm_i64: +; SI: buffer_load_dword v{{[0-9]+}} +; SI-NOT: and ; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}} -; SI: v_and_b32_e32 {{v[0-9]+}}, 0, {{v[0-9]+}} +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { %a = load i64, i64 addrspace(1)* %aptr, align 8 %and = and i64 %a, 64 @@ -252,15 +326,39 @@ define void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %apt } ; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 64 +; SI: s_load_dword +; SI-NOT: and +; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64 +; SI-NOT: and +; SI: buffer_store_dword define void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 64 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } +; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink: +; SI: s_load_dword [[A:s[0-9]+]] +; SI: s_lshl_b32 [[A]], [[A]], 1{{$}} +; SI-NOT: and +; SI: s_and_b32 s{{[0-9]+}}, [[A]], 64 +; SI-NOT: and +; SI: s_add_u32 +; SI-NEXT: s_addc_u32 +define void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i64 %b) { + %shl = shl i64 %a, 1 + %and = and i64 %shl, 64 + %add = add i64 %and, %b + store i64 %add, i64 addrspace(1)* %out, align 8 + ret void +} + ; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 1 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -268,7 +366,14 @@ define void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a } ; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 4607182418800017408 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -276,7 +381,14 @@ define void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* } ; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 13830554455654793216 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -284,47 +396,85 @@ define void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace( } ; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 4602678819172646912 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 +; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64: +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 13826050856027422720 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 2.0 +; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64: +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 4611686018427387904 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -2.0 +; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64: +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 13835058055282163712 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 +; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64: +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 4616189618054758400 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64 -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 +; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64: +; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0 + +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 13839561654909534208 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -335,22 +485,26 @@ define void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace( ; Test with the 64-bit integer bitpattern for a 32-bit float in the ; low 32-bits, which is not a valid 64-bit inline immmediate. -; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64 -; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0 -; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}} -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} +; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64: +; SI: s_load_dword s +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 1082130432 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FIXME: Copy of -1 register -; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64 -; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0 -; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}} -; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]] -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}} +; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64: +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, -1065353216 store i64 %and, i64 addrspace(1)* %out, align 8 @@ -358,20 +512,25 @@ define void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrsp } ; Shift into upper 32-bits -; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_4.0_i64 -; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0 -; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 4647714815446351872 store i64 %and, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64 -; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0 -; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} -; SI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}} +; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64: +; SI: s_load_dwordx2 +; SI: s_load_dwordx2 +; SI-NOT: and +; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0 +; SI-NOT: and +; SI: buffer_store_dwordx2 define void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { %and = and i64 %a, 13871086852301127680 store i64 %and, i64 addrspace(1)* %out, align 8 diff --git a/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll b/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll new file mode 100644 index 000000000000..084a6933da26 --- /dev/null +++ b/test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll @@ -0,0 +1,238 @@ +; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s + +declare i32 @llvm.amdgcn.workgroup.id.x() #0 +declare i32 @llvm.amdgcn.workgroup.id.y() #0 +declare i32 @llvm.amdgcn.workgroup.id.z() #0 + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i32 @llvm.amdgcn.workitem.id.y() #0 +declare i32 @llvm.amdgcn.workitem.id.z() #0 + +declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 +declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 + +; HSA: define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { +define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workgroup.id.x() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_y(i32 addrspace(1)* %ptr) #2 { +define void @use_tgid_y(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workgroup.id.y() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #2 { +define void @multi_use_tgid_y(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workgroup.id.y() + store volatile i32 %val0, i32 addrspace(1)* %ptr + %val1 = call i32 @llvm.amdgcn.workgroup.id.y() + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_x_y(i32 addrspace(1)* %ptr) #2 { +define void @use_tgid_x_y(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workgroup.id.x() + %val1 = call i32 @llvm.amdgcn.workgroup.id.y() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_z(i32 addrspace(1)* %ptr) #3 { +define void @use_tgid_z(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workgroup.id.z() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_x_z(i32 addrspace(1)* %ptr) #3 { +define void @use_tgid_x_z(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workgroup.id.x() + %val1 = call i32 @llvm.amdgcn.workgroup.id.z() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_y_z(i32 addrspace(1)* %ptr) #4 { +define void @use_tgid_y_z(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workgroup.id.y() + %val1 = call i32 @llvm.amdgcn.workgroup.id.z() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #4 { +define void @use_tgid_x_y_z(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workgroup.id.x() + %val1 = call i32 @llvm.amdgcn.workgroup.id.y() + %val2 = call i32 @llvm.amdgcn.workgroup.id.z() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + store volatile i32 %val2, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_x(i32 addrspace(1)* %ptr) #1 { +define void @use_tidig_x(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workitem.id.x() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_y(i32 addrspace(1)* %ptr) #5 { +define void @use_tidig_y(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workitem.id.y() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_z(i32 addrspace(1)* %ptr) #6 { +define void @use_tidig_z(i32 addrspace(1)* %ptr) #1 { + %val = call i32 @llvm.amdgcn.workitem.id.z() + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 { +define void @use_tidig_x_tgid_x(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workitem.id.x() + %val1 = call i32 @llvm.amdgcn.workgroup.id.x() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #7 { +define void @use_tidig_y_tgid_y(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workitem.id.y() + %val1 = call i32 @llvm.amdgcn.workgroup.id.y() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #8 { +define void @use_tidig_x_y_z(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workitem.id.x() + %val1 = call i32 @llvm.amdgcn.workitem.id.y() + %val2 = call i32 @llvm.amdgcn.workitem.id.z() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + store volatile i32 %val2, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_all_workitems(i32 addrspace(1)* %ptr) #9 { +define void @use_all_workitems(i32 addrspace(1)* %ptr) #1 { + %val0 = call i32 @llvm.amdgcn.workitem.id.x() + %val1 = call i32 @llvm.amdgcn.workitem.id.y() + %val2 = call i32 @llvm.amdgcn.workitem.id.z() + %val3 = call i32 @llvm.amdgcn.workgroup.id.x() + %val4 = call i32 @llvm.amdgcn.workgroup.id.y() + %val5 = call i32 @llvm.amdgcn.workgroup.id.z() + store volatile i32 %val0, i32 addrspace(1)* %ptr + store volatile i32 %val1, i32 addrspace(1)* %ptr + store volatile i32 %val2, i32 addrspace(1)* %ptr + store volatile i32 %val3, i32 addrspace(1)* %ptr + store volatile i32 %val4, i32 addrspace(1)* %ptr + store volatile i32 %val5, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #10 { +define void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { + %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() + %bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* + %val = load i32, i32 addrspace(2)* %bc + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_queue_ptr(i32 addrspace(1)* %ptr) #11 { +define void @use_queue_ptr(i32 addrspace(1)* %ptr) #1 { + %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr() + %bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* + %val = load i32, i32 addrspace(2)* %bc + store i32 %val, i32 addrspace(1)* %ptr + ret void +} + +; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 { +define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { + %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* + store volatile i32 0, i32 addrspace(4)* %stof + ret void +} + +; HSA: define void @use_private_to_flat_addrspacecast(i32* %ptr) #11 { +define void @use_private_to_flat_addrspacecast(i32* %ptr) #1 { + %stof = addrspacecast i32* %ptr to i32 addrspace(4)* + store volatile i32 0, i32 addrspace(4)* %stof + ret void +} + +; HSA: define void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { +define void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* + store volatile i32 0, i32 addrspace(3)* %ftos + ret void +} + +; HSA: define void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { +define void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32* + store volatile i32 0, i32* %ftos + ret void +} + +; No-op addrspacecast should not use queue ptr +; HSA: define void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { +define void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { + %stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* + store volatile i32 0, i32 addrspace(4)* %stof + ret void +} + +; HSA: define void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { +define void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { + %stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* + %ld = load volatile i32, i32 addrspace(4)* %stof + ret void +} + +; HSA: define void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { +define void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* + store volatile i32 0, i32 addrspace(1)* %ftos + ret void +} + +; HSA: define void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { +define void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { + %ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* + %ld = load volatile i32, i32 addrspace(2)* %ftos + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + +; HSA: attributes #0 = { nounwind readnone } +; HSA: attributes #1 = { nounwind } +; HSA: attributes #2 = { nounwind "amdgpu-work-group-id-y" } +; HSA: attributes #3 = { nounwind "amdgpu-work-group-id-z" } +; HSA: attributes #4 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" } +; HSA: attributes #5 = { nounwind "amdgpu-work-item-id-y" } +; HSA: attributes #6 = { nounwind "amdgpu-work-item-id-z" } +; HSA: attributes #7 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-item-id-y" } +; HSA: attributes #8 = { nounwind "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } +; HSA: attributes #9 = { nounwind "amdgpu-work-group-id-y" "amdgpu-work-group-id-z" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" } +; HSA: attributes #10 = { nounwind "amdgpu-dispatch-ptr" } +; HSA: attributes #11 = { nounwind "amdgpu-queue-ptr" } diff --git a/test/CodeGen/AMDGPU/annotate-kernel-features.ll b/test/CodeGen/AMDGPU/annotate-kernel-features.ll index b116c72322bb..a4e7bb67d507 100644 --- a/test/CodeGen/AMDGPU/annotate-kernel-features.ll +++ b/test/CodeGen/AMDGPU/annotate-kernel-features.ll @@ -1,5 +1,4 @@ -; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA -check-prefix=ALL %s -; RUN: opt -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=NOHSA -check-prefix=ALL %s +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=NOHSA -check-prefix=ALL %s declare i32 @llvm.r600.read.tgid.x() #0 declare i32 @llvm.r600.read.tgid.y() #0 @@ -13,11 +12,6 @@ declare i32 @llvm.r600.read.local.size.x() #0 declare i32 @llvm.r600.read.local.size.y() #0 declare i32 @llvm.r600.read.local.size.z() #0 -declare i32 @llvm.r600.read.global.size.x() #0 -declare i32 @llvm.r600.read.global.size.y() #0 -declare i32 @llvm.r600.read.global.size.z() #0 - - ; ALL: define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { define void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { %val = call i32 @llvm.r600.read.tgid.x() diff --git a/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll b/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll index f8a74222d566..b00fff0a6f9a 100644 --- a/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll +++ b/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll @@ -1,8 +1,9 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+promote-alloca < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s -declare i32 @llvm.SI.tid() nounwind readnone -declare void @llvm.AMDGPU.barrier.local() nounwind convergent +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 +declare void @llvm.amdgcn.s.barrier() #2 ; The required pointer calculations for the alloca'd actually requires ; an add and won't be folded into the addressing, which fails with a @@ -14,31 +15,38 @@ declare void @llvm.AMDGPU.barrier.local() nounwind convergent ; FIXME: We end up with zero argument for ADD, because ; SIRegisterInfo::eliminateFrameIndex() blindly replaces the frame index ; with the appropriate offset. We should fold this into the store. + ; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 0, v{{[0-9]+}} -; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}] +; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 +; SI-ALLOCA: s_barrier +; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 ; ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this ; alloca to a vector. It currently fails because it does not know how ; to interpret: -; getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b +; getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b -; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16 +; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64 ; SI-PROMOTE: ds_write_b32 [[PTRREG]] -define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) { - %alloca = alloca [4 x i32], i32 4, align 16 - %tid = call i32 @llvm.SI.tid() readnone - %a_ptr = getelementptr i32, i32 addrspace(1)* %inA, i32 %tid - %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid +define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 { + %alloca = alloca [16 x i32], align 16 + %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); + %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) + %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid + %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid %a = load i32, i32 addrspace(1)* %a_ptr %b = load i32, i32 addrspace(1)* %b_ptr %result = add i32 %a, %b - %alloca_ptr = getelementptr [4 x i32], [4 x i32]* %alloca, i32 1, i32 %b + %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b store i32 %result, i32* %alloca_ptr, align 4 ; Dummy call - call void @llvm.AMDGPU.barrier.local() nounwind convergent + call void @llvm.amdgcn.s.barrier() %reload = load i32, i32* %alloca_ptr, align 4 - %out_ptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid store i32 %reload, i32 addrspace(1)* %out_ptr, align 4 ret void } +attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="1" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind convergent } diff --git a/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll b/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll index a3ae3c3aea16..b914edf2928e 100644 --- a/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll +++ b/test/CodeGen/AMDGPU/array-ptr-calc-i64.ll @@ -1,13 +1,15 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.SI.tid() readnone +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 ; SI-LABEL: {{^}}test_array_ptr_calc: ; SI-DAG: v_mul_lo_i32 ; SI-DAG: v_mul_hi_i32 ; SI: s_endpgm define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) { - %tid = call i32 @llvm.SI.tid() readnone + %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) %a_ptr = getelementptr [1025 x i32], [1025 x i32] addrspace(1)* %inA, i32 %tid, i32 0 %b_ptr = getelementptr i32, i32 addrspace(1)* %inB, i32 %tid %a = load i32, i32 addrspace(1)* %a_ptr @@ -16,3 +18,5 @@ define void @test_array_ptr_calc(i32 addrspace(1)* noalias %out, [1025 x i32] ad store i32 %result, i32 addrspace(1)* %out ret void } + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll b/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll index ef2560ef1849..6a2716cc903e 100644 --- a/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll +++ b/test/CodeGen/AMDGPU/atomic_cmp_swap_local.ll @@ -3,11 +3,11 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i32_offset: -; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7 ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SICI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; VI: s_load_dword [[SWAP:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; GCN: v_mov_b32_e32 [[VCMP:v[0-9]+]], 7 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 [[VSWAP:v[0-9]+]], [[SWAP]] ; GCN: ds_cmpst_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[VCMP]], [[VSWAP]] offset:16 @@ -21,12 +21,12 @@ define void @lds_atomic_cmpxchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrs } ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_ret_i64_offset: +; SICI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SICI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd +; VI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0 -; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd -; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN-DAG: v_mov_b32_e32 v[[LOSWAPV:[0-9]+]], s[[LOSWAP]] ; GCN-DAG: v_mov_b32_e32 v[[HISWAPV:[0-9]+]], s[[HISWAP]] @@ -75,8 +75,8 @@ define void @lds_atomic_cmpxchg_noret_i32_offset(i32 addrspace(3)* %ptr, i32 %sw ; FUNC-LABEL: {{^}}lds_atomic_cmpxchg_noret_i64_offset: ; SICI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SICI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb -; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 -; VI: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 +; VI-DAG: s_load_dwordx2 s{{\[}}[[LOSWAP:[0-9]+]]:[[HISWAP:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GCN-DAG: v_mov_b32_e32 v[[LOVCMP:[0-9]+]], 7 ; GCN-DAG: v_mov_b32_e32 v[[HIVCMP:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] diff --git a/test/CodeGen/AMDGPU/atomic_load_sub.ll b/test/CodeGen/AMDGPU/atomic_load_sub.ll index 4c6f45525b9e..184d07ffad9c 100644 --- a/test/CodeGen/AMDGPU/atomic_load_sub.ll +++ b/test/CodeGen/AMDGPU/atomic_load_sub.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}atomic_sub_local: ; R600: LDS_SUB * diff --git a/test/CodeGen/AMDGPU/basic-branch.ll b/test/CodeGen/AMDGPU/basic-branch.ll index abdc4afef472..ff730a085255 100644 --- a/test/CodeGen/AMDGPU/basic-branch.ll +++ b/test/CodeGen/AMDGPU/basic-branch.ll @@ -1,9 +1,23 @@ -; XFAIL: * -; RUN: llc -O0 -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s +; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCNNOOPT -check-prefix=GCN %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCNOPT -check-prefix=GCN %s -; CHECK-LABEL: {{^}}test_branch( -define void @test_branch(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) nounwind { +; GCN-LABEL: {{^}}test_branch: +; GCNNOOPT: v_writelane_b32 +; GCNNOOPT: v_writelane_b32 +; GCNNOOPT: v_writelane_b32 +; GCN: s_cbranch_scc1 [[END:BB[0-9]+_[0-9]+]] + +; GCN: ; BB#1 +; GCNNOOPT: v_readlane_b32 +; GCNNOOPT: v_readlane_b32 +; GCN: buffer_store_dword +; GCN: s_endpgm + +; GCN: {{^}}[[END]] +; GCN: s_endpgm +define void @test_branch(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i32 %val) #0 { %cmp = icmp ne i32 %val, 0 br i1 %cmp, label %store, label %end @@ -14,3 +28,28 @@ store: end: ret void } + +; GCN-LABEL: {{^}}test_brcc_i1: +; GCN: buffer_load_ubyte +; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, +; GCN: v_cmp_eq_i32_e32 vcc, +; GCN: s_cbranch_vccnz [[END:BB[0-9]+_[0-9]+]] + +; GCN: buffer_store_dword +; GCN: s_endpgm + +; GCN: {{^}}[[END]] +; GCN: s_endpgm +define void @test_brcc_i1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in, i1 %val) #0 { + %cmp0 = icmp ne i1 %val, 0 + br i1 %cmp0, label %store, label %end + +store: + store i32 222, i32 addrspace(1)* %out + ret void + +end: + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/bfm.ll b/test/CodeGen/AMDGPU/bfm.ll new file mode 100644 index 000000000000..73db87d7ae9e --- /dev/null +++ b/test/CodeGen/AMDGPU/bfm.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}bfm_pattern: +; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} +define void @bfm_pattern(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { + %a = shl i32 1, %x + %b = sub i32 %a, 1 + %c = shl i32 %b, %y + store i32 %c, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}bfm_pattern_simple: +; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0 +define void @bfm_pattern_simple(i32 addrspace(1)* %out, i32 %x) #0 { + %a = shl i32 1, %x + %b = sub i32 %a, 1 + store i32 %b, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/big_alu.ll b/test/CodeGen/AMDGPU/big_alu.ll index 2671c5d102b3..0ab22b350f50 100644 --- a/test/CodeGen/AMDGPU/big_alu.ll +++ b/test/CodeGen/AMDGPU/big_alu.ll @@ -1,1173 +1,1312 @@ -;RUN: llc < %s -march=r600 -mcpu=cedar +; RUN: llc -march=r600 -mcpu=cedar < %s -;This test ensures that R600 backend can handle ifcvt properly -;and do not generate ALU clauses with more than 128 instructions. +; This test ensures that R600 backend can handle ifcvt properly -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) #0 { +define amdgpu_ps void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7, <4 x float> inreg %reg8, <4 x float> inreg %reg9) { main_body: - %0 = extractelement <4 x float> %reg0, i32 0 - %1 = extractelement <4 x float> %reg0, i32 1 - %2 = extractelement <4 x float> %reg0, i32 2 - %3 = extractelement <4 x float> %reg0, i32 3 - %4 = extractelement <4 x float> %reg1, i32 0 - %5 = extractelement <4 x float> %reg9, i32 0 - %6 = extractelement <4 x float> %reg8, i32 0 - %7 = fcmp ugt float %6, 0.000000e+00 - %8 = select i1 %7, float %4, float %5 - %9 = extractelement <4 x float> %reg1, i32 1 - %10 = extractelement <4 x float> %reg9, i32 1 - %11 = extractelement <4 x float> %reg8, i32 0 - %12 = fcmp ugt float %11, 0.000000e+00 - %13 = select i1 %12, float %9, float %10 - %14 = extractelement <4 x float> %reg1, i32 2 - %15 = extractelement <4 x float> %reg9, i32 2 - %16 = extractelement <4 x float> %reg8, i32 0 - %17 = fcmp ugt float %16, 0.000000e+00 - %18 = select i1 %17, float %14, float %15 - %19 = extractelement <4 x float> %reg1, i32 3 - %20 = extractelement <4 x float> %reg9, i32 3 - %21 = extractelement <4 x float> %reg8, i32 0 - %22 = extractelement <4 x float> %reg2, i32 0 - %23 = extractelement <4 x float> %reg2, i32 1 - %24 = extractelement <4 x float> %reg2, i32 2 - %25 = extractelement <4 x float> %reg2, i32 3 - %26 = extractelement <4 x float> %reg3, i32 0 - %27 = extractelement <4 x float> %reg3, i32 1 - %28 = extractelement <4 x float> %reg3, i32 2 - %29 = extractelement <4 x float> %reg3, i32 3 - %30 = extractelement <4 x float> %reg4, i32 0 - %31 = extractelement <4 x float> %reg4, i32 1 - %32 = extractelement <4 x float> %reg4, i32 2 - %33 = extractelement <4 x float> %reg4, i32 3 - %34 = extractelement <4 x float> %reg5, i32 0 - %35 = extractelement <4 x float> %reg5, i32 1 - %36 = extractelement <4 x float> %reg5, i32 2 - %37 = extractelement <4 x float> %reg5, i32 3 - %38 = extractelement <4 x float> %reg6, i32 0 - %39 = extractelement <4 x float> %reg6, i32 1 - %40 = extractelement <4 x float> %reg6, i32 2 - %41 = extractelement <4 x float> %reg6, i32 3 - %42 = extractelement <4 x float> %reg7, i32 0 - %43 = extractelement <4 x float> %reg7, i32 1 - %44 = extractelement <4 x float> %reg7, i32 2 - %45 = extractelement <4 x float> %reg7, i32 3 - %46 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %47 = extractelement <4 x float> %46, i32 0 - %48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %49 = extractelement <4 x float> %48, i32 1 - %50 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) - %51 = extractelement <4 x float> %50, i32 2 - %52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) - %53 = extractelement <4 x float> %52, i32 0 - %54 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %55 = extractelement <4 x float> %54, i32 0 - %56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %57 = extractelement <4 x float> %56, i32 1 - %58 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %59 = extractelement <4 x float> %58, i32 2 - %60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) - %61 = extractelement <4 x float> %60, i32 3 - %62 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %63 = extractelement <4 x float> %62, i32 0 - %64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %65 = extractelement <4 x float> %64, i32 1 - %66 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %67 = extractelement <4 x float> %66, i32 2 - %68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %69 = extractelement <4 x float> %68, i32 0 - %70 = fcmp oge float %69, 3.500000e+00 - %71 = sext i1 %70 to i32 - %72 = bitcast i32 %71 to float - %73 = bitcast float %72 to i32 - %74 = icmp ne i32 %73, 0 - %. = select i1 %74, float 0.000000e+00, float 0.000000e+00 - %75 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %76 = extractelement <4 x float> %75, i32 0 - %77 = fcmp oge float %76, 2.000000e+00 - %78 = sext i1 %77 to i32 - %79 = bitcast i32 %78 to float - %80 = bitcast float %79 to i32 - %81 = icmp ne i32 %80, 0 - br i1 %81, label %IF137, label %ENDIF136 + %tmp = extractelement <4 x float> %reg0, i32 0 + %tmp1 = extractelement <4 x float> %reg0, i32 1 + %tmp2 = extractelement <4 x float> %reg0, i32 2 + %tmp3 = extractelement <4 x float> %reg0, i32 3 + %tmp4 = extractelement <4 x float> %reg1, i32 0 + %tmp5 = extractelement <4 x float> %reg9, i32 0 + %tmp6 = extractelement <4 x float> %reg8, i32 0 + %tmp7 = fcmp ugt float %tmp6, 0.000000e+00 + %tmp8 = select i1 %tmp7, float %tmp4, float %tmp5 + %tmp9 = extractelement <4 x float> %reg1, i32 1 + %tmp10 = extractelement <4 x float> %reg9, i32 1 + %tmp11 = extractelement <4 x float> %reg8, i32 0 + %tmp12 = fcmp ugt float %tmp11, 0.000000e+00 + %tmp13 = select i1 %tmp12, float %tmp9, float %tmp10 + %tmp14 = extractelement <4 x float> %reg1, i32 2 + %tmp15 = extractelement <4 x float> %reg9, i32 2 + %tmp16 = extractelement <4 x float> %reg8, i32 0 + %tmp17 = fcmp ugt float %tmp16, 0.000000e+00 + %tmp18 = select i1 %tmp17, float %tmp14, float %tmp15 + %tmp19 = extractelement <4 x float> %reg1, i32 3 + %tmp20 = extractelement <4 x float> %reg9, i32 3 + %tmp21 = extractelement <4 x float> %reg8, i32 0 + %tmp22 = extractelement <4 x float> %reg2, i32 0 + %tmp23 = extractelement <4 x float> %reg2, i32 1 + %tmp24 = extractelement <4 x float> %reg2, i32 2 + %tmp25 = extractelement <4 x float> %reg2, i32 3 + %tmp26 = extractelement <4 x float> %reg3, i32 0 + %tmp27 = extractelement <4 x float> %reg3, i32 1 + %tmp28 = extractelement <4 x float> %reg3, i32 2 + %tmp29 = extractelement <4 x float> %reg3, i32 3 + %tmp30 = extractelement <4 x float> %reg4, i32 0 + %tmp31 = extractelement <4 x float> %reg4, i32 1 + %tmp32 = extractelement <4 x float> %reg4, i32 2 + %tmp33 = extractelement <4 x float> %reg4, i32 3 + %tmp34 = extractelement <4 x float> %reg5, i32 0 + %tmp35 = extractelement <4 x float> %reg5, i32 1 + %tmp36 = extractelement <4 x float> %reg5, i32 2 + %tmp37 = extractelement <4 x float> %reg5, i32 3 + %tmp38 = extractelement <4 x float> %reg6, i32 0 + %tmp39 = extractelement <4 x float> %reg6, i32 1 + %tmp40 = extractelement <4 x float> %reg6, i32 2 + %tmp41 = extractelement <4 x float> %reg6, i32 3 + %tmp42 = extractelement <4 x float> %reg7, i32 0 + %tmp43 = extractelement <4 x float> %reg7, i32 1 + %tmp44 = extractelement <4 x float> %reg7, i32 2 + %tmp45 = extractelement <4 x float> %reg7, i32 3 + %tmp46 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %tmp47 = extractelement <4 x float> %tmp46, i32 0 + %tmp48 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %tmp49 = extractelement <4 x float> %tmp48, i32 1 + %tmp50 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 11) + %tmp51 = extractelement <4 x float> %tmp50, i32 2 + %tmp52 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 12) + %tmp53 = extractelement <4 x float> %tmp52, i32 0 + %tmp54 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %tmp55 = extractelement <4 x float> %tmp54, i32 0 + %tmp56 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %tmp57 = extractelement <4 x float> %tmp56, i32 1 + %tmp58 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %tmp59 = extractelement <4 x float> %tmp58, i32 2 + %tmp60 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) + %tmp61 = extractelement <4 x float> %tmp60, i32 3 + %tmp62 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %tmp63 = extractelement <4 x float> %tmp62, i32 0 + %tmp64 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %tmp65 = extractelement <4 x float> %tmp64, i32 1 + %tmp66 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) + %tmp67 = extractelement <4 x float> %tmp66, i32 2 + %tmp68 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp69 = extractelement <4 x float> %tmp68, i32 0 + %tmp70 = fcmp oge float %tmp69, 3.500000e+00 + %tmp71 = sext i1 %tmp70 to i32 + %tmp72 = bitcast i32 %tmp71 to float + %tmp73 = bitcast float %tmp72 to i32 + %tmp74 = icmp ne i32 %tmp73, 0 + %. = select i1 %tmp74, float 0.000000e+00, float 0.000000e+00 + %tmp75 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp76 = extractelement <4 x float> %tmp75, i32 0 + %tmp77 = fcmp oge float %tmp76, 2.000000e+00 + %tmp78 = sext i1 %tmp77 to i32 + %tmp79 = bitcast i32 %tmp78 to float + %tmp80 = bitcast float %tmp79 to i32 + %tmp81 = icmp ne i32 %tmp80, 0 + br i1 %tmp81, label %IF137, label %ENDIF136 IF137: ; preds = %main_body - %82 = insertelement <4 x float> undef, float %30, i32 0 - %83 = insertelement <4 x float> %82, float %31, i32 1 - %84 = insertelement <4 x float> %83, float %32, i32 2 - %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3 - %86 = insertelement <4 x float> undef, float %30, i32 0 - %87 = insertelement <4 x float> %86, float %31, i32 1 - %88 = insertelement <4 x float> %87, float %32, i32 2 - %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3 - %90 = call float @llvm.AMDGPU.dp4(<4 x float> %85, <4 x float> %89) - %91 = call float @llvm.AMDGPU.rsq.f32(float %90) - %92 = fmul float %30, %91 - %93 = fmul float %31, %91 - %94 = fmul float %32, %91 - %95 = insertelement <4 x float> undef, float %92, i32 0 - %96 = insertelement <4 x float> %95, float %93, i32 1 - %97 = insertelement <4 x float> %96, float %94, i32 2 - %98 = insertelement <4 x float> %97, float 0.000000e+00, i32 3 - %99 = insertelement <4 x float> undef, float %37, i32 0 - %100 = insertelement <4 x float> %99, float %38, i32 1 - %101 = insertelement <4 x float> %100, float %39, i32 2 - %102 = insertelement <4 x float> %101, float 0.000000e+00, i32 3 - %103 = call float @llvm.AMDGPU.dp4(<4 x float> %98, <4 x float> %102) - %104 = insertelement <4 x float> undef, float %92, i32 0 - %105 = insertelement <4 x float> %104, float %93, i32 1 - %106 = insertelement <4 x float> %105, float %94, i32 2 - %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 3 - %108 = insertelement <4 x float> undef, float %40, i32 0 - %109 = insertelement <4 x float> %108, float %41, i32 1 - %110 = insertelement <4 x float> %109, float %42, i32 2 - %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 3 - %112 = call float @llvm.AMDGPU.dp4(<4 x float> %107, <4 x float> %111) - %113 = fsub float -0.000000e+00, %92 - %114 = fsub float -0.000000e+00, %93 - %115 = fsub float -0.000000e+00, %94 - %116 = insertelement <4 x float> undef, float %34, i32 0 - %117 = insertelement <4 x float> %116, float %35, i32 1 - %118 = insertelement <4 x float> %117, float %36, i32 2 - %119 = insertelement <4 x float> %118, float 0.000000e+00, i32 3 - %120 = insertelement <4 x float> undef, float %113, i32 0 - %121 = insertelement <4 x float> %120, float %114, i32 1 - %122 = insertelement <4 x float> %121, float %115, i32 2 - %123 = insertelement <4 x float> %122, float 0.000000e+00, i32 3 - %124 = call float @llvm.AMDGPU.dp4(<4 x float> %119, <4 x float> %123) - %125 = fdiv float 1.000000e+00, %124 - %126 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %127 = extractelement <4 x float> %126, i32 0 - %128 = fmul float %127, %125 - %129 = fmul float %103, %128 - %130 = fmul float %112, %128 - %131 = bitcast float %. to i32 - %132 = sitofp i32 %131 to float - %133 = fdiv float 1.000000e+00, %132 - %134 = bitcast float %. to i32 - %135 = add i32 %134, -1 - %136 = bitcast i32 %135 to float - %137 = bitcast float %136 to i32 + %tmp82 = insertelement <4 x float> undef, float %tmp30, i32 0 + %tmp83 = insertelement <4 x float> %tmp82, float %tmp31, i32 1 + %tmp84 = insertelement <4 x float> %tmp83, float %tmp32, i32 2 + %tmp85 = insertelement <4 x float> %tmp84, float 0.000000e+00, i32 3 + %tmp86 = insertelement <4 x float> undef, float %tmp30, i32 0 + %tmp87 = insertelement <4 x float> %tmp86, float %tmp31, i32 1 + %tmp88 = insertelement <4 x float> %tmp87, float %tmp32, i32 2 + %tmp89 = insertelement <4 x float> %tmp88, float 0.000000e+00, i32 3 + %tmp90 = call float @llvm.r600.dot4(<4 x float> %tmp85, <4 x float> %tmp89) + %tmp91 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp90) + %tmp92 = fmul float %tmp30, %tmp91 + %tmp93 = fmul float %tmp31, %tmp91 + %tmp94 = fmul float %tmp32, %tmp91 + %tmp95 = insertelement <4 x float> undef, float %tmp92, i32 0 + %tmp96 = insertelement <4 x float> %tmp95, float %tmp93, i32 1 + %tmp97 = insertelement <4 x float> %tmp96, float %tmp94, i32 2 + %tmp98 = insertelement <4 x float> %tmp97, float 0.000000e+00, i32 3 + %tmp99 = insertelement <4 x float> undef, float %tmp37, i32 0 + %tmp100 = insertelement <4 x float> %tmp99, float %tmp38, i32 1 + %tmp101 = insertelement <4 x float> %tmp100, float %tmp39, i32 2 + %tmp102 = insertelement <4 x float> %tmp101, float 0.000000e+00, i32 3 + %tmp103 = call float @llvm.r600.dot4(<4 x float> %tmp98, <4 x float> %tmp102) + %tmp104 = insertelement <4 x float> undef, float %tmp92, i32 0 + %tmp105 = insertelement <4 x float> %tmp104, float %tmp93, i32 1 + %tmp106 = insertelement <4 x float> %tmp105, float %tmp94, i32 2 + %tmp107 = insertelement <4 x float> %tmp106, float 0.000000e+00, i32 3 + %tmp108 = insertelement <4 x float> undef, float %tmp40, i32 0 + %tmp109 = insertelement <4 x float> %tmp108, float %tmp41, i32 1 + %tmp110 = insertelement <4 x float> %tmp109, float %tmp42, i32 2 + %tmp111 = insertelement <4 x float> %tmp110, float 0.000000e+00, i32 3 + %tmp112 = call float @llvm.r600.dot4(<4 x float> %tmp107, <4 x float> %tmp111) + %tmp113 = fsub float -0.000000e+00, %tmp92 + %tmp114 = fsub float -0.000000e+00, %tmp93 + %tmp115 = fsub float -0.000000e+00, %tmp94 + %tmp116 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp117 = insertelement <4 x float> %tmp116, float %tmp35, i32 1 + %tmp118 = insertelement <4 x float> %tmp117, float %tmp36, i32 2 + %tmp119 = insertelement <4 x float> %tmp118, float 0.000000e+00, i32 3 + %tmp120 = insertelement <4 x float> undef, float %tmp113, i32 0 + %tmp121 = insertelement <4 x float> %tmp120, float %tmp114, i32 1 + %tmp122 = insertelement <4 x float> %tmp121, float %tmp115, i32 2 + %tmp123 = insertelement <4 x float> %tmp122, float 0.000000e+00, i32 3 + %tmp124 = call float @llvm.r600.dot4(<4 x float> %tmp119, <4 x float> %tmp123) + %tmp125 = fdiv float 1.000000e+00, %tmp124 + %tmp126 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %tmp127 = extractelement <4 x float> %tmp126, i32 0 + %tmp128 = fmul float %tmp127, %tmp125 + %tmp129 = fmul float %tmp103, %tmp128 + %tmp130 = fmul float %tmp112, %tmp128 + %tmp131 = bitcast float %. to i32 + %tmp132 = sitofp i32 %tmp131 to float + %tmp133 = fdiv float 1.000000e+00, %tmp132 + %tmp134 = bitcast float %. to i32 + %tmp135 = add i32 %tmp134, -1 + %tmp136 = bitcast i32 %tmp135 to float + %tmp137 = bitcast float %tmp136 to i32 br label %LOOP -ENDIF136: ; preds = %main_body, %ENDIF154 - %temp68.1 = phi float [ %600, %ENDIF154 ], [ 0.000000e+00, %main_body ] - %temp69.0 = phi float [ %602, %ENDIF154 ], [ 0.000000e+00, %main_body ] - %temp70.0 = phi float [ %604, %ENDIF154 ], [ 1.000000e+00, %main_body ] - %138 = fmul float %26, 0x3F847AE140000000 - %139 = fmul float %27, 0x3F847AE140000000 - %140 = fmul float %28, 0x3F847AE140000000 - %141 = insertelement <4 x float> undef, float %138, i32 0 - %142 = insertelement <4 x float> %141, float %139, i32 1 - %143 = insertelement <4 x float> %142, float %140, i32 2 - %144 = insertelement <4 x float> %143, float 0.000000e+00, i32 3 - %145 = extractelement <4 x float> %144, i32 0 - %146 = extractelement <4 x float> %144, i32 1 - %147 = extractelement <4 x float> %144, i32 2 - %148 = extractelement <4 x float> %144, i32 3 - %149 = insertelement <4 x float> undef, float %145, i32 0 - %150 = insertelement <4 x float> %149, float %146, i32 1 - %151 = insertelement <4 x float> %150, float %147, i32 2 - %152 = insertelement <4 x float> %151, float %148, i32 3 - %153 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %152, i32 16, i32 0, i32 3) - %154 = extractelement <4 x float> %153, i32 0 - %155 = extractelement <4 x float> %153, i32 1 - %156 = extractelement <4 x float> %153, i32 2 - %157 = extractelement <4 x float> %153, i32 3 - %158 = fmul float %26, 0x3F45A07B40000000 - %159 = fmul float %27, 0x3F45A07B40000000 - %160 = fmul float %28, 0x3F45A07B40000000 - %161 = insertelement <4 x float> undef, float %158, i32 0 - %162 = insertelement <4 x float> %161, float %159, i32 1 - %163 = insertelement <4 x float> %162, float %160, i32 2 - %164 = insertelement <4 x float> %163, float 0.000000e+00, i32 3 - %165 = extractelement <4 x float> %164, i32 0 - %166 = extractelement <4 x float> %164, i32 1 - %167 = extractelement <4 x float> %164, i32 2 - %168 = extractelement <4 x float> %164, i32 3 - %169 = insertelement <4 x float> undef, float %165, i32 0 - %170 = insertelement <4 x float> %169, float %166, i32 1 - %171 = insertelement <4 x float> %170, float %167, i32 2 - %172 = insertelement <4 x float> %171, float %168, i32 3 - %173 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %172, i32 16, i32 0, i32 3) - %174 = extractelement <4 x float> %173, i32 0 - %175 = extractelement <4 x float> %173, i32 1 - %176 = extractelement <4 x float> %173, i32 2 - %177 = extractelement <4 x float> %173, i32 3 - %178 = fmul float %176, 3.000000e+03 - %179 = fadd float %178, %28 - %180 = fdiv float 1.000000e+00, %33 - %181 = fmul float %32, %180 - %182 = call float @fabs(float %181) - %183 = fmul float %174, 0x3FD99999A0000000 - %184 = fadd float %183, 0x3FAEB851E0000000 - %185 = fmul float %175, 0x3FE3333340000000 - %186 = fadd float %185, %184 - %187 = fmul float %176, 2.000000e+00 - %188 = fadd float %187, %186 - %189 = fmul float %177, 4.000000e+00 - %190 = fadd float %189, %188 - %191 = fmul float %154, 0x3FB99999A0000000 - %192 = fadd float %191, %190 - %193 = fmul float %155, 0x3FD99999A0000000 - %194 = fadd float %193, %192 - %195 = fmul float %156, 0x3FE99999A0000000 - %196 = fadd float %195, %194 - %197 = fmul float %157, 0x4000CCCCC0000000 - %198 = fadd float %197, %196 - %199 = fmul float 0xBE5EFB4CC0000000, %182 - %200 = fmul float %199, %182 - %201 = call float @llvm.AMDIL.exp.(float %200) - %202 = call float @llvm.AMDGPU.lrp(float %201, float %198, float 0x3FA99999A0000000) - %203 = fadd float %202, 0x3FF4CCCCC0000000 - %204 = fmul float %203, 0x3FE1C71C80000000 - %205 = call float @llvm.AMDIL.clamp.(float %204, float 0.000000e+00, float 1.000000e+00) - %206 = fadd float %202, 0x3FF4CCCCC0000000 - %207 = fmul float %206, 0x3FE1C71C80000000 - %208 = call float @llvm.AMDIL.clamp.(float %207, float 0.000000e+00, float 1.000000e+00) - %209 = fadd float %202, 2.000000e+00 - %210 = fmul float %209, 0x3FD611A7A0000000 - %211 = call float @llvm.AMDIL.clamp.(float %210, float 0.000000e+00, float 1.000000e+00) - %212 = fmul float 2.000000e+00, %205 - %213 = fsub float -0.000000e+00, %212 - %214 = fadd float 3.000000e+00, %213 - %215 = fmul float %205, %214 - %216 = fmul float %205, %215 - %217 = fmul float 2.000000e+00, %208 - %218 = fsub float -0.000000e+00, %217 - %219 = fadd float 3.000000e+00, %218 - %220 = fmul float %208, %219 - %221 = fmul float %208, %220 - %222 = fmul float 2.000000e+00, %211 - %223 = fsub float -0.000000e+00, %222 - %224 = fadd float 3.000000e+00, %223 - %225 = fmul float %211, %224 - %226 = fmul float %211, %225 - %227 = fmul float %26, 0x3F368B5CC0000000 - %228 = fmul float %27, 0x3F368B5CC0000000 - %229 = insertelement <4 x float> undef, float %227, i32 0 - %230 = insertelement <4 x float> %229, float %228, i32 1 - %231 = insertelement <4 x float> %230, float 0.000000e+00, i32 2 - %232 = insertelement <4 x float> %231, float 0.000000e+00, i32 3 - %233 = extractelement <4 x float> %232, i32 0 - %234 = extractelement <4 x float> %232, i32 1 - %235 = insertelement <4 x float> undef, float %233, i32 0 - %236 = insertelement <4 x float> %235, float %234, i32 1 - %237 = insertelement <4 x float> %236, float undef, i32 2 - %238 = insertelement <4 x float> %237, float undef, i32 3 - %239 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %238, i32 17, i32 1, i32 2) - %240 = extractelement <4 x float> %239, i32 0 - %241 = insertelement <4 x float> undef, float %240, i32 0 - %242 = insertelement <4 x float> %241, float %228, i32 1 - %243 = insertelement <4 x float> %242, float 0.000000e+00, i32 2 - %244 = insertelement <4 x float> %243, float 0.000000e+00, i32 3 - %245 = extractelement <4 x float> %244, i32 0 - %246 = insertelement <4 x float> undef, float %245, i32 0 - %247 = insertelement <4 x float> %246, float undef, i32 1 - %248 = insertelement <4 x float> %247, float undef, i32 2 - %249 = insertelement <4 x float> %248, float undef, i32 3 - %250 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %249, i32 18, i32 2, i32 1) - %251 = extractelement <4 x float> %250, i32 0 - %252 = extractelement <4 x float> %250, i32 1 - %253 = extractelement <4 x float> %250, i32 2 - %254 = extractelement <4 x float> %250, i32 3 - %255 = fmul float %251, %216 - %256 = fmul float %252, %221 - %257 = fmul float %253, %226 - %258 = fmul float %254, 0.000000e+00 - %259 = fadd float %202, 0x3FF4CCCCC0000000 - %260 = fmul float %259, 0x3FE1C71C80000000 - %261 = call float @llvm.AMDIL.clamp.(float %260, float 0.000000e+00, float 1.000000e+00) - %262 = fadd float %202, 0x3FF4CCCCC0000000 - %263 = fmul float %262, 0x3FE1C71C80000000 - %264 = call float @llvm.AMDIL.clamp.(float %263, float 0.000000e+00, float 1.000000e+00) - %265 = fadd float %202, 2.000000e+00 - %266 = fmul float %265, 0x3FD611A7A0000000 - %267 = call float @llvm.AMDIL.clamp.(float %266, float 0.000000e+00, float 1.000000e+00) - %268 = fmul float 2.000000e+00, %261 - %269 = fsub float -0.000000e+00, %268 - %270 = fadd float 3.000000e+00, %269 - %271 = fmul float %261, %270 - %272 = fmul float %261, %271 - %273 = fmul float 2.000000e+00, %264 - %274 = fsub float -0.000000e+00, %273 - %275 = fadd float 3.000000e+00, %274 - %276 = fmul float %264, %275 - %277 = fmul float %264, %276 - %278 = fmul float 2.000000e+00, %267 - %279 = fsub float -0.000000e+00, %278 - %280 = fadd float 3.000000e+00, %279 - %281 = fmul float %267, %280 - %282 = fmul float %267, %281 - %283 = fmul float %26, 0x3F22DFD6A0000000 - %284 = fmul float %27, 0x3F22DFD6A0000000 - %285 = insertelement <4 x float> undef, float %283, i32 0 - %286 = insertelement <4 x float> %285, float %284, i32 1 - %287 = insertelement <4 x float> %286, float 0.000000e+00, i32 2 - %288 = insertelement <4 x float> %287, float 0.000000e+00, i32 3 - %289 = extractelement <4 x float> %288, i32 0 - %290 = extractelement <4 x float> %288, i32 1 - %291 = insertelement <4 x float> undef, float %289, i32 0 - %292 = insertelement <4 x float> %291, float %290, i32 1 - %293 = insertelement <4 x float> %292, float undef, i32 2 - %294 = insertelement <4 x float> %293, float undef, i32 3 - %295 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %294, i32 19, i32 3, i32 2) - %296 = extractelement <4 x float> %295, i32 0 - %297 = extractelement <4 x float> %295, i32 1 - %298 = extractelement <4 x float> %295, i32 2 - %299 = extractelement <4 x float> %295, i32 3 - %300 = fmul float %296, %272 - %301 = fmul float %297, %277 - %302 = fmul float %298, %282 - %303 = fmul float %299, 0.000000e+00 - %304 = fmul float %temp68.1, %37 - %305 = fmul float %temp68.1, %38 - %306 = fmul float %temp68.1, %39 - %307 = fmul float %temp69.0, %40 - %308 = fadd float %307, %304 - %309 = fmul float %temp69.0, %41 - %310 = fadd float %309, %305 - %311 = fmul float %temp69.0, %42 - %312 = fadd float %311, %306 - %313 = fmul float %temp70.0, %34 - %314 = fadd float %313, %308 - %315 = fmul float %temp70.0, %35 - %316 = fadd float %315, %310 - %317 = fmul float %temp70.0, %36 - %318 = fadd float %317, %312 - %319 = insertelement <4 x float> undef, float %314, i32 0 - %320 = insertelement <4 x float> %319, float %316, i32 1 - %321 = insertelement <4 x float> %320, float %318, i32 2 - %322 = insertelement <4 x float> %321, float 0.000000e+00, i32 3 - %323 = insertelement <4 x float> undef, float %314, i32 0 - %324 = insertelement <4 x float> %323, float %316, i32 1 - %325 = insertelement <4 x float> %324, float %318, i32 2 - %326 = insertelement <4 x float> %325, float 0.000000e+00, i32 3 - %327 = call float @llvm.AMDGPU.dp4(<4 x float> %322, <4 x float> %326) - %328 = call float @llvm.AMDGPU.rsq.f32(float %327) - %329 = fmul float %314, %328 - %330 = fmul float %316, %328 - %331 = fmul float %318, %328 - %332 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %333 = extractelement <4 x float> %332, i32 0 - %334 = fsub float -0.000000e+00, %333 - %335 = fadd float 1.000000e+00, %334 - %336 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %337 = extractelement <4 x float> %336, i32 0 - %338 = fsub float -0.000000e+00, %337 - %339 = fadd float 1.000000e+00, %338 - %340 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) - %341 = extractelement <4 x float> %340, i32 0 - %342 = fsub float -0.000000e+00, %341 - %343 = fadd float 1.000000e+00, %342 - %344 = fsub float -0.000000e+00, %335 - %345 = fadd float %202, %344 - %346 = fsub float -0.000000e+00, %339 - %347 = fadd float %202, %346 - %348 = fadd float %347, 0xBFE3333340000000 - %349 = fsub float -0.000000e+00, %202 - %350 = fsub float -0.000000e+00, %343 - %351 = fadd float %349, %350 - %352 = insertelement <4 x float> undef, float %43, i32 0 - %353 = insertelement <4 x float> %352, float %44, i32 1 - %354 = insertelement <4 x float> %353, float %45, i32 2 - %355 = insertelement <4 x float> %354, float 0.000000e+00, i32 3 - %356 = insertelement <4 x float> undef, float %43, i32 0 - %357 = insertelement <4 x float> %356, float %44, i32 1 - %358 = insertelement <4 x float> %357, float %45, i32 2 - %359 = insertelement <4 x float> %358, float 0.000000e+00, i32 3 - %360 = call float @llvm.AMDGPU.dp4(<4 x float> %355, <4 x float> %359) - %361 = call float @llvm.AMDGPU.rsq.f32(float %360) - %362 = fmul float %45, %361 - %363 = call float @fabs(float %362) - %364 = fmul float %176, 0x3FECCCCCC0000000 - %365 = fadd float %364, %363 - %366 = fadd float %365, 0xBFEFAE1480000000 - %367 = fmul float %366, 0xC023FFFFC0000000 - %368 = call float @llvm.AMDIL.clamp.(float %367, float 0.000000e+00, float 1.000000e+00) - %369 = fsub float -0.000000e+00, %335 - %370 = fadd float %202, %369 - %371 = fadd float %370, 0x3FBEB851E0000000 - %372 = fsub float -0.000000e+00, %339 - %373 = fadd float %202, %372 - %374 = fadd float %373, 0xBFE0A3D700000000 - %375 = fsub float -0.000000e+00, %202 - %376 = fsub float -0.000000e+00, %343 - %377 = fadd float %375, %376 - %378 = insertelement <4 x float> undef, float %43, i32 0 - %379 = insertelement <4 x float> %378, float %44, i32 1 - %380 = insertelement <4 x float> %379, float %45, i32 2 - %381 = insertelement <4 x float> %380, float 0.000000e+00, i32 3 - %382 = insertelement <4 x float> undef, float %43, i32 0 - %383 = insertelement <4 x float> %382, float %44, i32 1 - %384 = insertelement <4 x float> %383, float %45, i32 2 - %385 = insertelement <4 x float> %384, float 0.000000e+00, i32 3 - %386 = call float @llvm.AMDGPU.dp4(<4 x float> %381, <4 x float> %385) - %387 = call float @llvm.AMDGPU.rsq.f32(float %386) - %388 = fmul float %45, %387 - %389 = call float @fabs(float %388) - %390 = fmul float %176, 0x3FF51EB860000000 - %391 = fadd float %390, %389 - %392 = fadd float %391, 0xBFEFAE1480000000 - %393 = fmul float %392, 0xC0490001A0000000 - %394 = call float @llvm.AMDIL.clamp.(float %393, float 0.000000e+00, float 1.000000e+00) - %395 = fmul float 2.000000e+00, %368 - %396 = fsub float -0.000000e+00, %395 - %397 = fadd float 3.000000e+00, %396 - %398 = fmul float %368, %397 - %399 = fmul float %368, %398 - %400 = call float @llvm.AMDGPU.lrp(float %399, float %255, float %345) - %401 = call float @llvm.AMDGPU.lrp(float %399, float %256, float %348) - %402 = call float @llvm.AMDGPU.lrp(float %399, float %257, float %351) - %403 = call float @llvm.AMDGPU.lrp(float %399, float %258, float 0.000000e+00) - %404 = fmul float 2.000000e+00, %394 - %405 = fsub float -0.000000e+00, %404 - %406 = fadd float 3.000000e+00, %405 - %407 = fmul float %394, %406 - %408 = fmul float %394, %407 - %409 = call float @llvm.AMDGPU.lrp(float %408, float %255, float %371) - %410 = call float @llvm.AMDGPU.lrp(float %408, float %256, float %374) - %411 = call float @llvm.AMDGPU.lrp(float %408, float %257, float %377) - %412 = call float @llvm.AMDGPU.lrp(float %408, float %258, float 0x3FD3333340000000) - %413 = fcmp oge float 2.200000e+03, %179 - %414 = sext i1 %413 to i32 - %415 = bitcast i32 %414 to float - %416 = bitcast float %415 to i32 - %417 = icmp ne i32 %416, 0 - br i1 %417, label %IF161, label %ENDIF160 +ENDIF136: ; preds = %ENDIF154, %main_body + %temp68.1 = phi float [ %tmp603, %ENDIF154 ], [ 0.000000e+00, %main_body ] + %temp69.0 = phi float [ %tmp605, %ENDIF154 ], [ 0.000000e+00, %main_body ] + %temp70.0 = phi float [ %tmp607, %ENDIF154 ], [ 1.000000e+00, %main_body ] + %tmp138 = fmul float %tmp26, 0x3F847AE140000000 + %tmp139 = fmul float %tmp27, 0x3F847AE140000000 + %tmp140 = fmul float %tmp28, 0x3F847AE140000000 + %tmp141 = insertelement <4 x float> undef, float %tmp138, i32 0 + %tmp142 = insertelement <4 x float> %tmp141, float %tmp139, i32 1 + %tmp143 = insertelement <4 x float> %tmp142, float %tmp140, i32 2 + %tmp144 = insertelement <4 x float> %tmp143, float 0.000000e+00, i32 3 + %tmp145 = extractelement <4 x float> %tmp144, i32 0 + %tmp146 = extractelement <4 x float> %tmp144, i32 1 + %tmp147 = extractelement <4 x float> %tmp144, i32 2 + %tmp148 = extractelement <4 x float> %tmp144, i32 3 + %tmp149 = insertelement <4 x float> undef, float %tmp145, i32 0 + %tmp150 = insertelement <4 x float> %tmp149, float %tmp146, i32 1 + %tmp151 = insertelement <4 x float> %tmp150, float %tmp147, i32 2 + %tmp152 = insertelement <4 x float> %tmp151, float %tmp148, i32 3 + %tmp153 = shufflevector <4 x float> %tmp152, <4 x float> %tmp152, <4 x i32> + %tmp154 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp153, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp155 = extractelement <4 x float> %tmp154, i32 0 + %tmp156 = extractelement <4 x float> %tmp154, i32 1 + %tmp157 = extractelement <4 x float> %tmp154, i32 2 + %tmp158 = extractelement <4 x float> %tmp154, i32 3 + %tmp159 = fmul float %tmp26, 0x3F45A07B40000000 + %tmp160 = fmul float %tmp27, 0x3F45A07B40000000 + %tmp161 = fmul float %tmp28, 0x3F45A07B40000000 + %tmp162 = insertelement <4 x float> undef, float %tmp159, i32 0 + %tmp163 = insertelement <4 x float> %tmp162, float %tmp160, i32 1 + %tmp164 = insertelement <4 x float> %tmp163, float %tmp161, i32 2 + %tmp165 = insertelement <4 x float> %tmp164, float 0.000000e+00, i32 3 + %tmp166 = extractelement <4 x float> %tmp165, i32 0 + %tmp167 = extractelement <4 x float> %tmp165, i32 1 + %tmp168 = extractelement <4 x float> %tmp165, i32 2 + %tmp169 = extractelement <4 x float> %tmp165, i32 3 + %tmp170 = insertelement <4 x float> undef, float %tmp166, i32 0 + %tmp171 = insertelement <4 x float> %tmp170, float %tmp167, i32 1 + %tmp172 = insertelement <4 x float> %tmp171, float %tmp168, i32 2 + %tmp173 = insertelement <4 x float> %tmp172, float %tmp169, i32 3 + %tmp174 = shufflevector <4 x float> %tmp173, <4 x float> %tmp173, <4 x i32> + %tmp175 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp174, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp176 = extractelement <4 x float> %tmp175, i32 0 + %tmp177 = extractelement <4 x float> %tmp175, i32 1 + %tmp178 = extractelement <4 x float> %tmp175, i32 2 + %tmp179 = extractelement <4 x float> %tmp175, i32 3 + %tmp180 = fmul float %tmp178, 3.000000e+03 + %tmp181 = fadd float %tmp180, %tmp28 + %tmp182 = fdiv float 1.000000e+00, %tmp33 + %tmp183 = fmul float %tmp32, %tmp182 + %tmp184 = call float @llvm.fabs.f32(float %tmp183) + %tmp185 = fmul float %tmp176, 0x3FD99999A0000000 + %tmp186 = fadd float %tmp185, 0x3FAEB851E0000000 + %tmp187 = fmul float %tmp177, 0x3FE3333340000000 + %tmp188 = fadd float %tmp187, %tmp186 + %tmp189 = fmul float %tmp178, 2.000000e+00 + %tmp190 = fadd float %tmp189, %tmp188 + %tmp191 = fmul float %tmp179, 4.000000e+00 + %tmp192 = fadd float %tmp191, %tmp190 + %tmp193 = fmul float %tmp155, 0x3FB99999A0000000 + %tmp194 = fadd float %tmp193, %tmp192 + %tmp195 = fmul float %tmp156, 0x3FD99999A0000000 + %tmp196 = fadd float %tmp195, %tmp194 + %tmp197 = fmul float %tmp157, 0x3FE99999A0000000 + %tmp198 = fadd float %tmp197, %tmp196 + %tmp199 = fmul float %tmp158, 0x4000CCCCC0000000 + %tmp200 = fadd float %tmp199, %tmp198 + %tmp201 = fmul float 0xBE5EFB4CC0000000, %tmp184 + %tmp202 = fmul float %tmp201, %tmp184 + %tmp203 = call float @llvm.exp2.f32(float %tmp202) + %one.sub.a.i = fsub float 1.000000e+00, %tmp203 + %one.sub.ac.i = fmul float %one.sub.a.i, 0x3FA99999A0000000 + %mul.i = fmul float %tmp200, 0x3FA99999A0000000 + %result.i = fadd float %mul.i, %one.sub.ac.i + %tmp204 = fadd float %result.i, 0x3FF4CCCCC0000000 + %tmp205 = fmul float %tmp204, 0x3FE1C71C80000000 + %tmp206 = call float @llvm.AMDGPU.clamp.f32(float %tmp205, float 0.000000e+00, float 1.000000e+00) + %tmp207 = fadd float %result.i, 0x3FF4CCCCC0000000 + %tmp208 = fmul float %tmp207, 0x3FE1C71C80000000 + %tmp209 = call float @llvm.AMDGPU.clamp.f32(float %tmp208, float 0.000000e+00, float 1.000000e+00) + %tmp210 = fadd float %result.i, 2.000000e+00 + %tmp211 = fmul float %tmp210, 0x3FD611A7A0000000 + %tmp212 = call float @llvm.AMDGPU.clamp.f32(float %tmp211, float 0.000000e+00, float 1.000000e+00) + %tmp213 = fmul float 2.000000e+00, %tmp206 + %tmp214 = fsub float -0.000000e+00, %tmp213 + %tmp215 = fadd float 3.000000e+00, %tmp214 + %tmp216 = fmul float %tmp206, %tmp215 + %tmp217 = fmul float %tmp206, %tmp216 + %tmp218 = fmul float 2.000000e+00, %tmp209 + %tmp219 = fsub float -0.000000e+00, %tmp218 + %tmp220 = fadd float 3.000000e+00, %tmp219 + %tmp221 = fmul float %tmp209, %tmp220 + %tmp222 = fmul float %tmp209, %tmp221 + %tmp223 = fmul float 2.000000e+00, %tmp212 + %tmp224 = fsub float -0.000000e+00, %tmp223 + %tmp225 = fadd float 3.000000e+00, %tmp224 + %tmp226 = fmul float %tmp212, %tmp225 + %tmp227 = fmul float %tmp212, %tmp226 + %tmp228 = fmul float %tmp26, 0x3F368B5CC0000000 + %tmp229 = fmul float %tmp27, 0x3F368B5CC0000000 + %tmp230 = insertelement <4 x float> undef, float %tmp228, i32 0 + %tmp231 = insertelement <4 x float> %tmp230, float %tmp229, i32 1 + %tmp232 = insertelement <4 x float> %tmp231, float 0.000000e+00, i32 2 + %tmp233 = insertelement <4 x float> %tmp232, float 0.000000e+00, i32 3 + %tmp234 = extractelement <4 x float> %tmp233, i32 0 + %tmp235 = extractelement <4 x float> %tmp233, i32 1 + %tmp236 = insertelement <4 x float> undef, float %tmp234, i32 0 + %tmp237 = insertelement <4 x float> %tmp236, float %tmp235, i32 1 + %tmp238 = insertelement <4 x float> %tmp237, float undef, i32 2 + %tmp239 = insertelement <4 x float> %tmp238, float undef, i32 3 + %tmp240 = shufflevector <4 x float> %tmp239, <4 x float> %tmp239, <4 x i32> + %tmp241 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp240, i32 0, i32 0, i32 0, i32 17, i32 1, i32 1, i32 1, i32 1, i32 1) + %tmp242 = extractelement <4 x float> %tmp241, i32 0 + %tmp243 = insertelement <4 x float> undef, float %tmp242, i32 0 + %tmp244 = insertelement <4 x float> %tmp243, float %tmp229, i32 1 + %tmp245 = insertelement <4 x float> %tmp244, float 0.000000e+00, i32 2 + %tmp246 = insertelement <4 x float> %tmp245, float 0.000000e+00, i32 3 + %tmp247 = extractelement <4 x float> %tmp246, i32 0 + %tmp248 = insertelement <4 x float> undef, float %tmp247, i32 0 + %tmp249 = insertelement <4 x float> %tmp248, float undef, i32 1 + %tmp250 = insertelement <4 x float> %tmp249, float undef, i32 2 + %tmp251 = insertelement <4 x float> %tmp250, float undef, i32 3 + %tmp252 = shufflevector <4 x float> %tmp251, <4 x float> %tmp251, <4 x i32> + %tmp253 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp252, i32 0, i32 0, i32 0, i32 18, i32 2, i32 1, i32 1, i32 1, i32 1) + %tmp254 = extractelement <4 x float> %tmp253, i32 0 + %tmp255 = extractelement <4 x float> %tmp253, i32 1 + %tmp256 = extractelement <4 x float> %tmp253, i32 2 + %tmp257 = extractelement <4 x float> %tmp253, i32 3 + %tmp258 = fmul float %tmp254, %tmp217 + %tmp259 = fmul float %tmp255, %tmp222 + %tmp260 = fmul float %tmp256, %tmp227 + %tmp261 = fmul float %tmp257, 0.000000e+00 + %tmp262 = fadd float %result.i, 0x3FF4CCCCC0000000 + %tmp263 = fmul float %tmp262, 0x3FE1C71C80000000 + %tmp264 = call float @llvm.AMDGPU.clamp.f32(float %tmp263, float 0.000000e+00, float 1.000000e+00) + %tmp265 = fadd float %result.i, 0x3FF4CCCCC0000000 + %tmp266 = fmul float %tmp265, 0x3FE1C71C80000000 + %tmp267 = call float @llvm.AMDGPU.clamp.f32(float %tmp266, float 0.000000e+00, float 1.000000e+00) + %tmp268 = fadd float %result.i, 2.000000e+00 + %tmp269 = fmul float %tmp268, 0x3FD611A7A0000000 + %tmp270 = call float @llvm.AMDGPU.clamp.f32(float %tmp269, float 0.000000e+00, float 1.000000e+00) + %tmp271 = fmul float 2.000000e+00, %tmp264 + %tmp272 = fsub float -0.000000e+00, %tmp271 + %tmp273 = fadd float 3.000000e+00, %tmp272 + %tmp274 = fmul float %tmp264, %tmp273 + %tmp275 = fmul float %tmp264, %tmp274 + %tmp276 = fmul float 2.000000e+00, %tmp267 + %tmp277 = fsub float -0.000000e+00, %tmp276 + %tmp278 = fadd float 3.000000e+00, %tmp277 + %tmp279 = fmul float %tmp267, %tmp278 + %tmp280 = fmul float %tmp267, %tmp279 + %tmp281 = fmul float 2.000000e+00, %tmp270 + %tmp282 = fsub float -0.000000e+00, %tmp281 + %tmp283 = fadd float 3.000000e+00, %tmp282 + %tmp284 = fmul float %tmp270, %tmp283 + %tmp285 = fmul float %tmp270, %tmp284 + %tmp286 = fmul float %tmp26, 0x3F22DFD6A0000000 + %tmp287 = fmul float %tmp27, 0x3F22DFD6A0000000 + %tmp288 = insertelement <4 x float> undef, float %tmp286, i32 0 + %tmp289 = insertelement <4 x float> %tmp288, float %tmp287, i32 1 + %tmp290 = insertelement <4 x float> %tmp289, float 0.000000e+00, i32 2 + %tmp291 = insertelement <4 x float> %tmp290, float 0.000000e+00, i32 3 + %tmp292 = extractelement <4 x float> %tmp291, i32 0 + %tmp293 = extractelement <4 x float> %tmp291, i32 1 + %tmp294 = insertelement <4 x float> undef, float %tmp292, i32 0 + %tmp295 = insertelement <4 x float> %tmp294, float %tmp293, i32 1 + %tmp296 = insertelement <4 x float> %tmp295, float undef, i32 2 + %tmp297 = insertelement <4 x float> %tmp296, float undef, i32 3 + %tmp298 = shufflevector <4 x float> %tmp297, <4 x float> %tmp297, <4 x i32> + %tmp299 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp298, i32 0, i32 0, i32 0, i32 19, i32 3, i32 1, i32 1, i32 1, i32 1) + %tmp300 = extractelement <4 x float> %tmp299, i32 0 + %tmp301 = extractelement <4 x float> %tmp299, i32 1 + %tmp302 = extractelement <4 x float> %tmp299, i32 2 + %tmp303 = extractelement <4 x float> %tmp299, i32 3 + %tmp304 = fmul float %tmp300, %tmp275 + %tmp305 = fmul float %tmp301, %tmp280 + %tmp306 = fmul float %tmp302, %tmp285 + %tmp307 = fmul float %tmp303, 0.000000e+00 + %tmp308 = fmul float %temp68.1, %tmp37 + %tmp309 = fmul float %temp68.1, %tmp38 + %tmp310 = fmul float %temp68.1, %tmp39 + %tmp311 = fmul float %temp69.0, %tmp40 + %tmp312 = fadd float %tmp311, %tmp308 + %tmp313 = fmul float %temp69.0, %tmp41 + %tmp314 = fadd float %tmp313, %tmp309 + %tmp315 = fmul float %temp69.0, %tmp42 + %tmp316 = fadd float %tmp315, %tmp310 + %tmp317 = fmul float %temp70.0, %tmp34 + %tmp318 = fadd float %tmp317, %tmp312 + %tmp319 = fmul float %temp70.0, %tmp35 + %tmp320 = fadd float %tmp319, %tmp314 + %tmp321 = fmul float %temp70.0, %tmp36 + %tmp322 = fadd float %tmp321, %tmp316 + %tmp323 = insertelement <4 x float> undef, float %tmp318, i32 0 + %tmp324 = insertelement <4 x float> %tmp323, float %tmp320, i32 1 + %tmp325 = insertelement <4 x float> %tmp324, float %tmp322, i32 2 + %tmp326 = insertelement <4 x float> %tmp325, float 0.000000e+00, i32 3 + %tmp327 = insertelement <4 x float> undef, float %tmp318, i32 0 + %tmp328 = insertelement <4 x float> %tmp327, float %tmp320, i32 1 + %tmp329 = insertelement <4 x float> %tmp328, float %tmp322, i32 2 + %tmp330 = insertelement <4 x float> %tmp329, float 0.000000e+00, i32 3 + %tmp331 = call float @llvm.r600.dot4(<4 x float> %tmp326, <4 x float> %tmp330) + %tmp332 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp331) + %tmp333 = fmul float %tmp318, %tmp332 + %tmp334 = fmul float %tmp320, %tmp332 + %tmp335 = fmul float %tmp322, %tmp332 + %tmp336 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %tmp337 = extractelement <4 x float> %tmp336, i32 0 + %tmp338 = fsub float -0.000000e+00, %tmp337 + %tmp339 = fadd float 1.000000e+00, %tmp338 + %tmp340 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %tmp341 = extractelement <4 x float> %tmp340, i32 0 + %tmp342 = fsub float -0.000000e+00, %tmp341 + %tmp343 = fadd float 1.000000e+00, %tmp342 + %tmp344 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %tmp345 = extractelement <4 x float> %tmp344, i32 0 + %tmp346 = fsub float -0.000000e+00, %tmp345 + %tmp347 = fadd float 1.000000e+00, %tmp346 + %tmp348 = fsub float -0.000000e+00, %tmp339 + %tmp349 = fadd float %result.i, %tmp348 + %tmp350 = fsub float -0.000000e+00, %tmp343 + %tmp351 = fadd float %result.i, %tmp350 + %tmp352 = fadd float %tmp351, 0xBFE3333340000000 + %tmp353 = fsub float -0.000000e+00, %result.i + %tmp354 = fsub float -0.000000e+00, %tmp347 + %tmp355 = fadd float %tmp353, %tmp354 + %tmp356 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp357 = insertelement <4 x float> %tmp356, float %tmp44, i32 1 + %tmp358 = insertelement <4 x float> %tmp357, float %tmp45, i32 2 + %tmp359 = insertelement <4 x float> %tmp358, float 0.000000e+00, i32 3 + %tmp360 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp361 = insertelement <4 x float> %tmp360, float %tmp44, i32 1 + %tmp362 = insertelement <4 x float> %tmp361, float %tmp45, i32 2 + %tmp363 = insertelement <4 x float> %tmp362, float 0.000000e+00, i32 3 + %tmp364 = call float @llvm.r600.dot4(<4 x float> %tmp359, <4 x float> %tmp363) + %tmp365 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp364) + %tmp366 = fmul float %tmp45, %tmp365 + %tmp367 = call float @llvm.fabs.f32(float %tmp366) + %tmp368 = fmul float %tmp178, 0x3FECCCCCC0000000 + %tmp369 = fadd float %tmp368, %tmp367 + %tmp370 = fadd float %tmp369, 0xBFEFAE1480000000 + %tmp371 = fmul float %tmp370, 0xC023FFFFC0000000 + %tmp372 = call float @llvm.AMDGPU.clamp.f32(float %tmp371, float 0.000000e+00, float 1.000000e+00) + %tmp373 = fsub float -0.000000e+00, %tmp339 + %tmp374 = fadd float %result.i, %tmp373 + %tmp375 = fadd float %tmp374, 0x3FBEB851E0000000 + %tmp376 = fsub float -0.000000e+00, %tmp343 + %tmp377 = fadd float %result.i, %tmp376 + %tmp378 = fadd float %tmp377, 0xBFE0A3D700000000 + %tmp379 = fsub float -0.000000e+00, %result.i + %tmp380 = fsub float -0.000000e+00, %tmp347 + %tmp381 = fadd float %tmp379, %tmp380 + %tmp382 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp383 = insertelement <4 x float> %tmp382, float %tmp44, i32 1 + %tmp384 = insertelement <4 x float> %tmp383, float %tmp45, i32 2 + %tmp385 = insertelement <4 x float> %tmp384, float 0.000000e+00, i32 3 + %tmp386 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp387 = insertelement <4 x float> %tmp386, float %tmp44, i32 1 + %tmp388 = insertelement <4 x float> %tmp387, float %tmp45, i32 2 + %tmp389 = insertelement <4 x float> %tmp388, float 0.000000e+00, i32 3 + %tmp390 = call float @llvm.r600.dot4(<4 x float> %tmp385, <4 x float> %tmp389) + %tmp391 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp390) + %tmp392 = fmul float %tmp45, %tmp391 + %tmp393 = call float @llvm.fabs.f32(float %tmp392) + %tmp394 = fmul float %tmp178, 0x3FF51EB860000000 + %tmp395 = fadd float %tmp394, %tmp393 + %tmp396 = fadd float %tmp395, 0xBFEFAE1480000000 + %tmp397 = fmul float %tmp396, 0xC0490001A0000000 + %tmp398 = call float @llvm.AMDGPU.clamp.f32(float %tmp397, float 0.000000e+00, float 1.000000e+00) + %tmp399 = fmul float 2.000000e+00, %tmp372 + %tmp400 = fsub float -0.000000e+00, %tmp399 + %tmp401 = fadd float 3.000000e+00, %tmp400 + %tmp402 = fmul float %tmp372, %tmp401 + %tmp403 = fmul float %tmp372, %tmp402 + %one.sub.a.i169 = fsub float 1.000000e+00, %tmp403 + %one.sub.ac.i170 = fmul float %one.sub.a.i169, %tmp349 + %mul.i171 = fmul float %tmp258, %tmp349 + %result.i172 = fadd float %mul.i171, %one.sub.ac.i170 + %one.sub.a.i165 = fsub float 1.000000e+00, %tmp403 + %one.sub.ac.i166 = fmul float %one.sub.a.i165, %tmp352 + %mul.i167 = fmul float %tmp259, %tmp352 + %result.i168 = fadd float %mul.i167, %one.sub.ac.i166 + %one.sub.a.i161 = fsub float 1.000000e+00, %tmp403 + %one.sub.ac.i162 = fmul float %one.sub.a.i161, %tmp355 + %mul.i163 = fmul float %tmp260, %tmp355 + %result.i164 = fadd float %mul.i163, %one.sub.ac.i162 + %one.sub.a.i157 = fsub float 1.000000e+00, %tmp403 + %one.sub.ac.i158 = fmul float %one.sub.a.i157, 0.000000e+00 + %mul.i159 = fmul float %tmp261, 0.000000e+00 + %result.i160 = fadd float %mul.i159, %one.sub.ac.i158 + %tmp404 = fmul float 2.000000e+00, %tmp398 + %tmp405 = fsub float -0.000000e+00, %tmp404 + %tmp406 = fadd float 3.000000e+00, %tmp405 + %tmp407 = fmul float %tmp398, %tmp406 + %tmp408 = fmul float %tmp398, %tmp407 + %one.sub.a.i153 = fsub float 1.000000e+00, %tmp408 + %one.sub.ac.i154 = fmul float %one.sub.a.i153, %tmp375 + %mul.i155 = fmul float %tmp258, %tmp375 + %result.i156 = fadd float %mul.i155, %one.sub.ac.i154 + %one.sub.a.i149 = fsub float 1.000000e+00, %tmp408 + %one.sub.ac.i150 = fmul float %one.sub.a.i149, %tmp378 + %mul.i151 = fmul float %tmp259, %tmp378 + %result.i152 = fadd float %mul.i151, %one.sub.ac.i150 + %one.sub.a.i145 = fsub float 1.000000e+00, %tmp408 + %one.sub.ac.i146 = fmul float %one.sub.a.i145, %tmp381 + %mul.i147 = fmul float %tmp260, %tmp381 + %result.i148 = fadd float %mul.i147, %one.sub.ac.i146 + %one.sub.a.i141 = fsub float 1.000000e+00, %tmp408 + %one.sub.ac.i142 = fmul float %one.sub.a.i141, 0x3FD3333340000000 + %mul.i143 = fmul float %tmp261, 0x3FD3333340000000 + %result.i144 = fadd float %mul.i143, %one.sub.ac.i142 + %tmp409 = fcmp oge float 2.200000e+03, %tmp181 + %tmp410 = sext i1 %tmp409 to i32 + %tmp411 = bitcast i32 %tmp410 to float + %tmp412 = bitcast float %tmp411 to i32 + %tmp413 = icmp ne i32 %tmp412, 0 + br i1 %tmp413, label %IF161, label %ENDIF160 LOOP: ; preds = %ENDIF139, %IF137 - %temp88.0 = phi float [ 0.000000e+00, %IF137 ], [ %446, %ENDIF139 ] + %temp88.0 = phi float [ 0.000000e+00, %IF137 ], [ %tmp443, %ENDIF139 ] %temp92.0 = phi float [ 1.000000e+00, %IF137 ], [ %.temp92.0, %ENDIF139 ] - %temp96.0 = phi float [ 0.000000e+00, %IF137 ], [ %477, %ENDIF139 ] - %418 = bitcast float %temp96.0 to i32 - %419 = icmp sge i32 %418, %137 - %420 = sext i1 %419 to i32 - %421 = bitcast i32 %420 to float - %422 = bitcast float %421 to i32 - %423 = icmp ne i32 %422, 0 - br i1 %423, label %IF140, label %ENDIF139 + %temp96.0 = phi float [ 0.000000e+00, %IF137 ], [ %tmp475, %ENDIF139 ] + %tmp414 = bitcast float %temp96.0 to i32 + %tmp415 = icmp sge i32 %tmp414, %tmp137 + %tmp416 = sext i1 %tmp415 to i32 + %tmp417 = bitcast i32 %tmp416 to float + %tmp418 = bitcast float %tmp417 to i32 + %tmp419 = icmp ne i32 %tmp418, 0 + br i1 %tmp419, label %IF140, label %ENDIF139 IF140: ; preds = %LOOP - %424 = fmul float %133, 5.000000e-01 - %425 = fmul float %129, %temp92.0 - %426 = fadd float %425, %22 - %427 = fmul float %130, %temp92.0 - %428 = fadd float %427, %23 - %429 = insertelement <4 x float> undef, float %426, i32 0 - %430 = insertelement <4 x float> %429, float %428, i32 1 - %431 = insertelement <4 x float> %430, float 0.000000e+00, i32 2 - %432 = insertelement <4 x float> %431, float 0.000000e+00, i32 3 - %433 = extractelement <4 x float> %432, i32 0 - %434 = extractelement <4 x float> %432, i32 1 - %435 = insertelement <4 x float> undef, float %433, i32 0 - %436 = insertelement <4 x float> %435, float %434, i32 1 - %437 = insertelement <4 x float> %436, float undef, i32 2 - %438 = insertelement <4 x float> %437, float undef, i32 3 - %439 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %438, i32 20, i32 4, i32 2) - %440 = extractelement <4 x float> %439, i32 3 - %441 = fcmp oge float %temp92.0, %440 - %442 = sext i1 %441 to i32 - %443 = bitcast i32 %442 to float - %444 = bitcast float %443 to i32 - %445 = icmp ne i32 %444, 0 - br i1 %445, label %IF146, label %ENDIF145 + %tmp420 = fmul float %tmp133, 5.000000e-01 + %tmp421 = fmul float %tmp129, %temp92.0 + %tmp422 = fadd float %tmp421, %tmp22 + %tmp423 = fmul float %tmp130, %temp92.0 + %tmp424 = fadd float %tmp423, %tmp23 + %tmp425 = insertelement <4 x float> undef, float %tmp422, i32 0 + %tmp426 = insertelement <4 x float> %tmp425, float %tmp424, i32 1 + %tmp427 = insertelement <4 x float> %tmp426, float 0.000000e+00, i32 2 + %tmp428 = insertelement <4 x float> %tmp427, float 0.000000e+00, i32 3 + %tmp429 = extractelement <4 x float> %tmp428, i32 0 + %tmp430 = extractelement <4 x float> %tmp428, i32 1 + %tmp431 = insertelement <4 x float> undef, float %tmp429, i32 0 + %tmp432 = insertelement <4 x float> %tmp431, float %tmp430, i32 1 + %tmp433 = insertelement <4 x float> %tmp432, float undef, i32 2 + %tmp434 = insertelement <4 x float> %tmp433, float undef, i32 3 + %tmp435 = shufflevector <4 x float> %tmp434, <4 x float> %tmp434, <4 x i32> + %tmp436 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp435, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp437 = extractelement <4 x float> %tmp436, i32 3 + %tmp438 = fcmp oge float %temp92.0, %tmp437 + %tmp439 = sext i1 %tmp438 to i32 + %tmp440 = bitcast i32 %tmp439 to float + %tmp441 = bitcast float %tmp440 to i32 + %tmp442 = icmp ne i32 %tmp441, 0 + br i1 %tmp442, label %IF146, label %ENDIF145 ENDIF139: ; preds = %LOOP - %446 = fadd float %temp88.0, %133 - %447 = fmul float %129, %446 - %448 = fadd float %447, %22 - %449 = fmul float %130, %446 - %450 = fadd float %449, %23 - %451 = insertelement <4 x float> undef, float %448, i32 0 - %452 = insertelement <4 x float> %451, float %450, i32 1 - %453 = insertelement <4 x float> %452, float 0.000000e+00, i32 2 - %454 = insertelement <4 x float> %453, float 0.000000e+00, i32 3 - %455 = extractelement <4 x float> %454, i32 0 - %456 = extractelement <4 x float> %454, i32 1 - %457 = insertelement <4 x float> undef, float %455, i32 0 - %458 = insertelement <4 x float> %457, float %456, i32 1 - %459 = insertelement <4 x float> %458, float undef, i32 2 - %460 = insertelement <4 x float> %459, float undef, i32 3 - %461 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %460, i32 20, i32 4, i32 2) - %462 = extractelement <4 x float> %461, i32 3 - %463 = fcmp olt float 0x3FEFDF3B60000000, %temp92.0 - %464 = sext i1 %463 to i32 - %465 = bitcast i32 %464 to float - %466 = fcmp oge float %446, %462 - %467 = sext i1 %466 to i32 - %468 = bitcast i32 %467 to float - %469 = bitcast float %465 to i32 - %470 = bitcast float %468 to i32 - %471 = and i32 %469, %470 - %472 = bitcast i32 %471 to float - %473 = bitcast float %472 to i32 - %474 = icmp ne i32 %473, 0 - %.temp92.0 = select i1 %474, float %446, float %temp92.0 - %475 = bitcast float %temp96.0 to i32 - %476 = add i32 %475, 1 - %477 = bitcast i32 %476 to float + %tmp443 = fadd float %temp88.0, %tmp133 + %tmp444 = fmul float %tmp129, %tmp443 + %tmp445 = fadd float %tmp444, %tmp22 + %tmp446 = fmul float %tmp130, %tmp443 + %tmp447 = fadd float %tmp446, %tmp23 + %tmp448 = insertelement <4 x float> undef, float %tmp445, i32 0 + %tmp449 = insertelement <4 x float> %tmp448, float %tmp447, i32 1 + %tmp450 = insertelement <4 x float> %tmp449, float 0.000000e+00, i32 2 + %tmp451 = insertelement <4 x float> %tmp450, float 0.000000e+00, i32 3 + %tmp452 = extractelement <4 x float> %tmp451, i32 0 + %tmp453 = extractelement <4 x float> %tmp451, i32 1 + %tmp454 = insertelement <4 x float> undef, float %tmp452, i32 0 + %tmp455 = insertelement <4 x float> %tmp454, float %tmp453, i32 1 + %tmp456 = insertelement <4 x float> %tmp455, float undef, i32 2 + %tmp457 = insertelement <4 x float> %tmp456, float undef, i32 3 + %tmp458 = shufflevector <4 x float> %tmp457, <4 x float> %tmp457, <4 x i32> + %tmp459 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp458, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp460 = extractelement <4 x float> %tmp459, i32 3 + %tmp461 = fcmp olt float 0x3FEFDF3B60000000, %temp92.0 + %tmp462 = sext i1 %tmp461 to i32 + %tmp463 = bitcast i32 %tmp462 to float + %tmp464 = fcmp oge float %tmp443, %tmp460 + %tmp465 = sext i1 %tmp464 to i32 + %tmp466 = bitcast i32 %tmp465 to float + %tmp467 = bitcast float %tmp463 to i32 + %tmp468 = bitcast float %tmp466 to i32 + %tmp469 = and i32 %tmp467, %tmp468 + %tmp470 = bitcast i32 %tmp469 to float + %tmp471 = bitcast float %tmp470 to i32 + %tmp472 = icmp ne i32 %tmp471, 0 + %.temp92.0 = select i1 %tmp472, float %tmp443, float %temp92.0 + %tmp473 = bitcast float %temp96.0 to i32 + %tmp474 = add i32 %tmp473, 1 + %tmp475 = bitcast i32 %tmp474 to float br label %LOOP IF146: ; preds = %IF140 - %478 = fmul float 2.000000e+00, %424 - %479 = fsub float -0.000000e+00, %478 - %480 = fadd float %temp92.0, %479 + %tmp476 = fmul float 2.000000e+00, %tmp420 + %tmp477 = fsub float -0.000000e+00, %tmp476 + %tmp478 = fadd float %temp92.0, %tmp477 br label %ENDIF145 -ENDIF145: ; preds = %IF140, %IF146 - %temp88.1 = phi float [ %480, %IF146 ], [ %temp92.0, %IF140 ] - %481 = fadd float %temp88.1, %424 - %482 = fmul float %424, 5.000000e-01 - %483 = fmul float %129, %481 - %484 = fadd float %483, %22 - %485 = fmul float %130, %481 - %486 = fadd float %485, %23 - %487 = insertelement <4 x float> undef, float %484, i32 0 - %488 = insertelement <4 x float> %487, float %486, i32 1 - %489 = insertelement <4 x float> %488, float 0.000000e+00, i32 2 - %490 = insertelement <4 x float> %489, float %440, i32 3 - %491 = extractelement <4 x float> %490, i32 0 - %492 = extractelement <4 x float> %490, i32 1 - %493 = insertelement <4 x float> undef, float %491, i32 0 - %494 = insertelement <4 x float> %493, float %492, i32 1 - %495 = insertelement <4 x float> %494, float undef, i32 2 - %496 = insertelement <4 x float> %495, float undef, i32 3 - %497 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %496, i32 20, i32 4, i32 2) - %498 = extractelement <4 x float> %497, i32 3 - %499 = fcmp oge float %481, %498 - %500 = sext i1 %499 to i32 - %501 = bitcast i32 %500 to float - %502 = bitcast float %501 to i32 - %503 = icmp ne i32 %502, 0 - br i1 %503, label %IF149, label %ENDIF148 +ENDIF145: ; preds = %IF146, %IF140 + %temp88.1 = phi float [ %tmp478, %IF146 ], [ %temp92.0, %IF140 ] + %tmp479 = fadd float %temp88.1, %tmp420 + %tmp480 = fmul float %tmp420, 5.000000e-01 + %tmp481 = fmul float %tmp129, %tmp479 + %tmp482 = fadd float %tmp481, %tmp22 + %tmp483 = fmul float %tmp130, %tmp479 + %tmp484 = fadd float %tmp483, %tmp23 + %tmp485 = insertelement <4 x float> undef, float %tmp482, i32 0 + %tmp486 = insertelement <4 x float> %tmp485, float %tmp484, i32 1 + %tmp487 = insertelement <4 x float> %tmp486, float 0.000000e+00, i32 2 + %tmp488 = insertelement <4 x float> %tmp487, float %tmp437, i32 3 + %tmp489 = extractelement <4 x float> %tmp488, i32 0 + %tmp490 = extractelement <4 x float> %tmp488, i32 1 + %tmp491 = insertelement <4 x float> undef, float %tmp489, i32 0 + %tmp492 = insertelement <4 x float> %tmp491, float %tmp490, i32 1 + %tmp493 = insertelement <4 x float> %tmp492, float undef, i32 2 + %tmp494 = insertelement <4 x float> %tmp493, float undef, i32 3 + %tmp495 = shufflevector <4 x float> %tmp494, <4 x float> %tmp494, <4 x i32> + %tmp496 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp495, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp497 = extractelement <4 x float> %tmp496, i32 3 + %tmp498 = fcmp oge float %tmp479, %tmp497 + %tmp499 = sext i1 %tmp498 to i32 + %tmp500 = bitcast i32 %tmp499 to float + %tmp501 = bitcast float %tmp500 to i32 + %tmp502 = icmp ne i32 %tmp501, 0 + br i1 %tmp502, label %IF149, label %ENDIF148 IF149: ; preds = %ENDIF145 - %504 = fmul float 2.000000e+00, %482 - %505 = fsub float -0.000000e+00, %504 - %506 = fadd float %481, %505 + %tmp503 = fmul float 2.000000e+00, %tmp480 + %tmp504 = fsub float -0.000000e+00, %tmp503 + %tmp505 = fadd float %tmp479, %tmp504 br label %ENDIF148 -ENDIF148: ; preds = %ENDIF145, %IF149 - %temp88.2 = phi float [ %506, %IF149 ], [ %481, %ENDIF145 ] - %temp92.2 = phi float [ %481, %IF149 ], [ %temp92.0, %ENDIF145 ] - %507 = fadd float %temp88.2, %482 - %508 = fmul float %482, 5.000000e-01 - %509 = fmul float %129, %507 - %510 = fadd float %509, %22 - %511 = fmul float %130, %507 - %512 = fadd float %511, %23 - %513 = insertelement <4 x float> undef, float %510, i32 0 - %514 = insertelement <4 x float> %513, float %512, i32 1 - %515 = insertelement <4 x float> %514, float 0.000000e+00, i32 2 - %516 = insertelement <4 x float> %515, float %498, i32 3 - %517 = extractelement <4 x float> %516, i32 0 - %518 = extractelement <4 x float> %516, i32 1 - %519 = insertelement <4 x float> undef, float %517, i32 0 - %520 = insertelement <4 x float> %519, float %518, i32 1 - %521 = insertelement <4 x float> %520, float undef, i32 2 - %522 = insertelement <4 x float> %521, float undef, i32 3 - %523 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %522, i32 20, i32 4, i32 2) - %524 = extractelement <4 x float> %523, i32 3 - %525 = fcmp oge float %507, %524 - %526 = sext i1 %525 to i32 - %527 = bitcast i32 %526 to float - %528 = bitcast float %527 to i32 - %529 = icmp ne i32 %528, 0 - br i1 %529, label %IF152, label %ENDIF151 +ENDIF148: ; preds = %IF149, %ENDIF145 + %temp88.2 = phi float [ %tmp505, %IF149 ], [ %tmp479, %ENDIF145 ] + %temp92.2 = phi float [ %tmp479, %IF149 ], [ %temp92.0, %ENDIF145 ] + %tmp506 = fadd float %temp88.2, %tmp480 + %tmp507 = fmul float %tmp480, 5.000000e-01 + %tmp508 = fmul float %tmp129, %tmp506 + %tmp509 = fadd float %tmp508, %tmp22 + %tmp510 = fmul float %tmp130, %tmp506 + %tmp511 = fadd float %tmp510, %tmp23 + %tmp512 = insertelement <4 x float> undef, float %tmp509, i32 0 + %tmp513 = insertelement <4 x float> %tmp512, float %tmp511, i32 1 + %tmp514 = insertelement <4 x float> %tmp513, float 0.000000e+00, i32 2 + %tmp515 = insertelement <4 x float> %tmp514, float %tmp497, i32 3 + %tmp516 = extractelement <4 x float> %tmp515, i32 0 + %tmp517 = extractelement <4 x float> %tmp515, i32 1 + %tmp518 = insertelement <4 x float> undef, float %tmp516, i32 0 + %tmp519 = insertelement <4 x float> %tmp518, float %tmp517, i32 1 + %tmp520 = insertelement <4 x float> %tmp519, float undef, i32 2 + %tmp521 = insertelement <4 x float> %tmp520, float undef, i32 3 + %tmp522 = shufflevector <4 x float> %tmp521, <4 x float> %tmp521, <4 x i32> + %tmp523 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp522, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp524 = extractelement <4 x float> %tmp523, i32 3 + %tmp525 = fcmp oge float %tmp506, %tmp524 + %tmp526 = sext i1 %tmp525 to i32 + %tmp527 = bitcast i32 %tmp526 to float + %tmp528 = bitcast float %tmp527 to i32 + %tmp529 = icmp ne i32 %tmp528, 0 + br i1 %tmp529, label %IF152, label %ENDIF151 IF152: ; preds = %ENDIF148 - %530 = fmul float 2.000000e+00, %508 - %531 = fsub float -0.000000e+00, %530 - %532 = fadd float %507, %531 + %tmp530 = fmul float 2.000000e+00, %tmp507 + %tmp531 = fsub float -0.000000e+00, %tmp530 + %tmp532 = fadd float %tmp506, %tmp531 br label %ENDIF151 -ENDIF151: ; preds = %ENDIF148, %IF152 - %temp88.3 = phi float [ %532, %IF152 ], [ %507, %ENDIF148 ] - %temp92.3 = phi float [ %507, %IF152 ], [ %temp92.2, %ENDIF148 ] - %533 = fadd float %temp88.3, %508 - %534 = fmul float %508, 5.000000e-01 - %535 = fmul float %129, %533 - %536 = fadd float %535, %22 - %537 = fmul float %130, %533 - %538 = fadd float %537, %23 - %539 = insertelement <4 x float> undef, float %536, i32 0 - %540 = insertelement <4 x float> %539, float %538, i32 1 - %541 = insertelement <4 x float> %540, float 0.000000e+00, i32 2 - %542 = insertelement <4 x float> %541, float %524, i32 3 - %543 = extractelement <4 x float> %542, i32 0 - %544 = extractelement <4 x float> %542, i32 1 - %545 = insertelement <4 x float> undef, float %543, i32 0 - %546 = insertelement <4 x float> %545, float %544, i32 1 - %547 = insertelement <4 x float> %546, float undef, i32 2 - %548 = insertelement <4 x float> %547, float undef, i32 3 - %549 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %548, i32 20, i32 4, i32 2) - %550 = extractelement <4 x float> %549, i32 3 - %551 = fcmp oge float %533, %550 - %552 = sext i1 %551 to i32 - %553 = bitcast i32 %552 to float - %554 = bitcast float %553 to i32 - %555 = icmp ne i32 %554, 0 - br i1 %555, label %IF155, label %ENDIF154 +ENDIF151: ; preds = %IF152, %ENDIF148 + %temp88.3 = phi float [ %tmp532, %IF152 ], [ %tmp506, %ENDIF148 ] + %temp92.3 = phi float [ %tmp506, %IF152 ], [ %temp92.2, %ENDIF148 ] + %tmp533 = fadd float %temp88.3, %tmp507 + %tmp534 = fmul float %tmp507, 5.000000e-01 + %tmp535 = fmul float %tmp129, %tmp533 + %tmp536 = fadd float %tmp535, %tmp22 + %tmp537 = fmul float %tmp130, %tmp533 + %tmp538 = fadd float %tmp537, %tmp23 + %tmp539 = insertelement <4 x float> undef, float %tmp536, i32 0 + %tmp540 = insertelement <4 x float> %tmp539, float %tmp538, i32 1 + %tmp541 = insertelement <4 x float> %tmp540, float 0.000000e+00, i32 2 + %tmp542 = insertelement <4 x float> %tmp541, float %tmp524, i32 3 + %tmp543 = extractelement <4 x float> %tmp542, i32 0 + %tmp544 = extractelement <4 x float> %tmp542, i32 1 + %tmp545 = insertelement <4 x float> undef, float %tmp543, i32 0 + %tmp546 = insertelement <4 x float> %tmp545, float %tmp544, i32 1 + %tmp547 = insertelement <4 x float> %tmp546, float undef, i32 2 + %tmp548 = insertelement <4 x float> %tmp547, float undef, i32 3 + %tmp549 = shufflevector <4 x float> %tmp548, <4 x float> %tmp548, <4 x i32> + %tmp550 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp549, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp551 = extractelement <4 x float> %tmp550, i32 3 + %tmp552 = fcmp oge float %tmp533, %tmp551 + %tmp553 = sext i1 %tmp552 to i32 + %tmp554 = bitcast i32 %tmp553 to float + %tmp555 = bitcast float %tmp554 to i32 + %tmp556 = icmp ne i32 %tmp555, 0 + br i1 %tmp556, label %IF155, label %ENDIF154 IF155: ; preds = %ENDIF151 - %556 = fmul float 2.000000e+00, %534 - %557 = fsub float -0.000000e+00, %556 - %558 = fadd float %533, %557 + %tmp557 = fmul float 2.000000e+00, %tmp534 + %tmp558 = fsub float -0.000000e+00, %tmp557 + %tmp559 = fadd float %tmp533, %tmp558 br label %ENDIF154 -ENDIF154: ; preds = %ENDIF151, %IF155 - %temp88.4 = phi float [ %558, %IF155 ], [ %533, %ENDIF151 ] - %temp92.4 = phi float [ %533, %IF155 ], [ %temp92.3, %ENDIF151 ] - %559 = fadd float %temp88.4, %534 - %560 = fmul float %129, %559 - %561 = fadd float %560, %22 - %562 = fmul float %130, %559 - %563 = fadd float %562, %23 - %564 = insertelement <4 x float> undef, float %561, i32 0 - %565 = insertelement <4 x float> %564, float %563, i32 1 - %566 = insertelement <4 x float> %565, float 0.000000e+00, i32 2 - %567 = insertelement <4 x float> %566, float %550, i32 3 - %568 = extractelement <4 x float> %567, i32 0 - %569 = extractelement <4 x float> %567, i32 1 - %570 = insertelement <4 x float> undef, float %568, i32 0 - %571 = insertelement <4 x float> %570, float %569, i32 1 - %572 = insertelement <4 x float> %571, float undef, i32 2 - %573 = insertelement <4 x float> %572, float undef, i32 3 - %574 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %573, i32 20, i32 4, i32 2) - %575 = extractelement <4 x float> %574, i32 3 - %576 = fcmp oge float %559, %575 - %577 = sext i1 %576 to i32 - %578 = bitcast i32 %577 to float - %579 = bitcast float %578 to i32 - %580 = icmp ne i32 %579, 0 - %.temp92.4 = select i1 %580, float %559, float %temp92.4 - %581 = fmul float %129, %.temp92.4 - %582 = fadd float %581, %22 - %583 = fmul float %130, %.temp92.4 - %584 = fadd float %583, %23 - %585 = insertelement <4 x float> undef, float %582, i32 0 - %586 = insertelement <4 x float> %585, float %584, i32 1 - %587 = insertelement <4 x float> %586, float 0.000000e+00, i32 2 - %588 = insertelement <4 x float> %587, float %575, i32 3 - %589 = extractelement <4 x float> %588, i32 0 - %590 = extractelement <4 x float> %588, i32 1 - %591 = insertelement <4 x float> undef, float %589, i32 0 - %592 = insertelement <4 x float> %591, float %590, i32 1 - %593 = insertelement <4 x float> %592, float undef, i32 2 - %594 = insertelement <4 x float> %593, float undef, i32 3 - %595 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %594, i32 20, i32 4, i32 2) - %596 = extractelement <4 x float> %595, i32 0 - %597 = extractelement <4 x float> %595, i32 1 - %598 = extractelement <4 x float> %595, i32 2 - %599 = fmul float %596, 2.000000e+00 - %600 = fadd float %599, -1.000000e+00 - %601 = fmul float %597, 2.000000e+00 - %602 = fadd float %601, -1.000000e+00 - %603 = fmul float %598, 2.000000e+00 - %604 = fadd float %603, -1.000000e+00 +ENDIF154: ; preds = %IF155, %ENDIF151 + %temp88.4 = phi float [ %tmp559, %IF155 ], [ %tmp533, %ENDIF151 ] + %temp92.4 = phi float [ %tmp533, %IF155 ], [ %temp92.3, %ENDIF151 ] + %tmp560 = fadd float %temp88.4, %tmp534 + %tmp561 = fmul float %tmp129, %tmp560 + %tmp562 = fadd float %tmp561, %tmp22 + %tmp563 = fmul float %tmp130, %tmp560 + %tmp564 = fadd float %tmp563, %tmp23 + %tmp565 = insertelement <4 x float> undef, float %tmp562, i32 0 + %tmp566 = insertelement <4 x float> %tmp565, float %tmp564, i32 1 + %tmp567 = insertelement <4 x float> %tmp566, float 0.000000e+00, i32 2 + %tmp568 = insertelement <4 x float> %tmp567, float %tmp551, i32 3 + %tmp569 = extractelement <4 x float> %tmp568, i32 0 + %tmp570 = extractelement <4 x float> %tmp568, i32 1 + %tmp571 = insertelement <4 x float> undef, float %tmp569, i32 0 + %tmp572 = insertelement <4 x float> %tmp571, float %tmp570, i32 1 + %tmp573 = insertelement <4 x float> %tmp572, float undef, i32 2 + %tmp574 = insertelement <4 x float> %tmp573, float undef, i32 3 + %tmp575 = shufflevector <4 x float> %tmp574, <4 x float> %tmp574, <4 x i32> + %tmp576 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp575, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp577 = extractelement <4 x float> %tmp576, i32 3 + %tmp578 = fcmp oge float %tmp560, %tmp577 + %tmp579 = sext i1 %tmp578 to i32 + %tmp580 = bitcast i32 %tmp579 to float + %tmp581 = bitcast float %tmp580 to i32 + %tmp582 = icmp ne i32 %tmp581, 0 + %.temp92.4 = select i1 %tmp582, float %tmp560, float %temp92.4 + %tmp583 = fmul float %tmp129, %.temp92.4 + %tmp584 = fadd float %tmp583, %tmp22 + %tmp585 = fmul float %tmp130, %.temp92.4 + %tmp586 = fadd float %tmp585, %tmp23 + %tmp587 = insertelement <4 x float> undef, float %tmp584, i32 0 + %tmp588 = insertelement <4 x float> %tmp587, float %tmp586, i32 1 + %tmp589 = insertelement <4 x float> %tmp588, float 0.000000e+00, i32 2 + %tmp590 = insertelement <4 x float> %tmp589, float %tmp577, i32 3 + %tmp591 = extractelement <4 x float> %tmp590, i32 0 + %tmp592 = extractelement <4 x float> %tmp590, i32 1 + %tmp593 = insertelement <4 x float> undef, float %tmp591, i32 0 + %tmp594 = insertelement <4 x float> %tmp593, float %tmp592, i32 1 + %tmp595 = insertelement <4 x float> %tmp594, float undef, i32 2 + %tmp596 = insertelement <4 x float> %tmp595, float undef, i32 3 + %tmp597 = shufflevector <4 x float> %tmp596, <4 x float> %tmp596, <4 x i32> + %tmp598 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp597, i32 0, i32 0, i32 0, i32 20, i32 4, i32 1, i32 1, i32 1, i32 1) + %tmp599 = extractelement <4 x float> %tmp598, i32 0 + %tmp600 = extractelement <4 x float> %tmp598, i32 1 + %tmp601 = extractelement <4 x float> %tmp598, i32 2 + %tmp602 = fmul float %tmp599, 2.000000e+00 + %tmp603 = fadd float %tmp602, -1.000000e+00 + %tmp604 = fmul float %tmp600, 2.000000e+00 + %tmp605 = fadd float %tmp604, -1.000000e+00 + %tmp606 = fmul float %tmp601, 2.000000e+00 + %tmp607 = fadd float %tmp606, -1.000000e+00 br label %ENDIF136 IF161: ; preds = %ENDIF136 - %605 = fmul float %202, 0x3FB99999A0000000 - %606 = fcmp uge float 0x3FE4CCCCC0000000, %605 - %607 = select i1 %606, float 0x3FE4CCCCC0000000, float %605 - %608 = fcmp uge float %607, 5.000000e-01 - %609 = select i1 %608, float 5.000000e-01, float %607 - %610 = call float @llvm.AMDGPU.lrp(float %609, float %400, float %300) - %611 = call float @llvm.AMDGPU.lrp(float %609, float %401, float %301) - %612 = call float @llvm.AMDGPU.lrp(float %609, float %402, float %302) - %613 = call float @llvm.AMDGPU.lrp(float %609, float %403, float %303) - %614 = insertelement <4 x float> undef, float %329, i32 0 - %615 = insertelement <4 x float> %614, float %330, i32 1 - %616 = insertelement <4 x float> %615, float %331, i32 2 - %617 = insertelement <4 x float> %616, float 0.000000e+00, i32 3 - %618 = insertelement <4 x float> undef, float %63, i32 0 - %619 = insertelement <4 x float> %618, float %65, i32 1 - %620 = insertelement <4 x float> %619, float %67, i32 2 - %621 = insertelement <4 x float> %620, float 0.000000e+00, i32 3 - %622 = call float @llvm.AMDGPU.dp4(<4 x float> %617, <4 x float> %621) - %623 = fcmp uge float 0x3FE6666660000000, %622 - %624 = select i1 %623, float 0x3FE6666660000000, float %622 - %625 = fmul float %8, %624 - %626 = fmul float %13, %624 - %627 = fmul float %18, %624 - %628 = insertelement <4 x float> undef, float %34, i32 0 - %629 = insertelement <4 x float> %628, float %35, i32 1 - %630 = insertelement <4 x float> %629, float %36, i32 2 - %631 = insertelement <4 x float> %630, float 0.000000e+00, i32 3 - %632 = insertelement <4 x float> undef, float %63, i32 0 - %633 = insertelement <4 x float> %632, float %65, i32 1 - %634 = insertelement <4 x float> %633, float %67, i32 2 - %635 = insertelement <4 x float> %634, float 0.000000e+00, i32 3 - %636 = call float @llvm.AMDGPU.dp4(<4 x float> %631, <4 x float> %635) - %637 = fcmp uge float 0x3FECCCCCC0000000, %636 - %638 = select i1 %637, float 0x3FECCCCCC0000000, float %636 - %639 = fmul float %625, %638 - %640 = fmul float %626, %638 - %641 = fmul float %627, %638 + %tmp608 = fmul float %result.i, 0x3FB99999A0000000 + %tmp609 = fcmp uge float 0x3FE4CCCCC0000000, %tmp608 + %tmp610 = select i1 %tmp609, float 0x3FE4CCCCC0000000, float %tmp608 + %tmp611 = fcmp uge float %tmp610, 5.000000e-01 + %tmp612 = select i1 %tmp611, float 5.000000e-01, float %tmp610 + %one.sub.a.i137 = fsub float 1.000000e+00, %tmp612 + %one.sub.ac.i138 = fmul float %one.sub.a.i137, %tmp304 + %mul.i139 = fmul float %result.i172, %tmp304 + %result.i140 = fadd float %mul.i139, %one.sub.ac.i138 + %one.sub.a.i133 = fsub float 1.000000e+00, %tmp612 + %one.sub.ac.i134 = fmul float %one.sub.a.i133, %tmp305 + %mul.i135 = fmul float %result.i168, %tmp305 + %result.i136 = fadd float %mul.i135, %one.sub.ac.i134 + %one.sub.a.i129 = fsub float 1.000000e+00, %tmp612 + %one.sub.ac.i130 = fmul float %one.sub.a.i129, %tmp306 + %mul.i131 = fmul float %result.i164, %tmp306 + %result.i132 = fadd float %mul.i131, %one.sub.ac.i130 + %one.sub.a.i125 = fsub float 1.000000e+00, %tmp612 + %one.sub.ac.i126 = fmul float %one.sub.a.i125, %tmp307 + %mul.i127 = fmul float %result.i160, %tmp307 + %result.i128 = fadd float %mul.i127, %one.sub.ac.i126 + %tmp613 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp614 = insertelement <4 x float> %tmp613, float %tmp334, i32 1 + %tmp615 = insertelement <4 x float> %tmp614, float %tmp335, i32 2 + %tmp616 = insertelement <4 x float> %tmp615, float 0.000000e+00, i32 3 + %tmp617 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp618 = insertelement <4 x float> %tmp617, float %tmp65, i32 1 + %tmp619 = insertelement <4 x float> %tmp618, float %tmp67, i32 2 + %tmp620 = insertelement <4 x float> %tmp619, float 0.000000e+00, i32 3 + %tmp621 = call float @llvm.r600.dot4(<4 x float> %tmp616, <4 x float> %tmp620) + %tmp622 = fcmp uge float 0x3FE6666660000000, %tmp621 + %tmp623 = select i1 %tmp622, float 0x3FE6666660000000, float %tmp621 + %tmp624 = fmul float %tmp8, %tmp623 + %tmp625 = fmul float %tmp13, %tmp623 + %tmp626 = fmul float %tmp18, %tmp623 + %tmp627 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp628 = insertelement <4 x float> %tmp627, float %tmp35, i32 1 + %tmp629 = insertelement <4 x float> %tmp628, float %tmp36, i32 2 + %tmp630 = insertelement <4 x float> %tmp629, float 0.000000e+00, i32 3 + %tmp631 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp632 = insertelement <4 x float> %tmp631, float %tmp65, i32 1 + %tmp633 = insertelement <4 x float> %tmp632, float %tmp67, i32 2 + %tmp634 = insertelement <4 x float> %tmp633, float 0.000000e+00, i32 3 + %tmp635 = call float @llvm.r600.dot4(<4 x float> %tmp630, <4 x float> %tmp634) + %tmp636 = fcmp uge float 0x3FECCCCCC0000000, %tmp635 + %tmp637 = select i1 %tmp636, float 0x3FECCCCCC0000000, float %tmp635 + %tmp638 = fmul float %tmp624, %tmp637 + %tmp639 = fmul float %tmp625, %tmp637 + %tmp640 = fmul float %tmp626, %tmp637 br label %ENDIF160 -ENDIF160: ; preds = %ENDIF136, %IF161 - %temp84.0 = phi float [ %610, %IF161 ], [ %255, %ENDIF136 ] - %temp85.0 = phi float [ %611, %IF161 ], [ %256, %ENDIF136 ] - %temp86.0 = phi float [ %612, %IF161 ], [ %257, %ENDIF136 ] - %temp87.0 = phi float [ %613, %IF161 ], [ %258, %ENDIF136 ] - %temp92.6 = phi float [ %639, %IF161 ], [ %415, %ENDIF136 ] - %temp93.0 = phi float [ %640, %IF161 ], [ 0.000000e+00, %ENDIF136 ] - %temp94.0 = phi float [ %641, %IF161 ], [ 0.000000e+00, %ENDIF136 ] - %642 = fcmp olt float 2.200000e+03, %179 - %643 = sext i1 %642 to i32 - %644 = bitcast i32 %643 to float - %645 = fcmp olt float %179, 2.300000e+03 - %646 = sext i1 %645 to i32 - %647 = bitcast i32 %646 to float - %648 = bitcast float %644 to i32 - %649 = bitcast float %647 to i32 - %650 = and i32 %648, %649 - %651 = bitcast i32 %650 to float - %652 = bitcast float %651 to i32 - %653 = icmp ne i32 %652, 0 - br i1 %653, label %IF164, label %ENDIF163 +ENDIF160: ; preds = %IF161, %ENDIF136 + %temp84.0 = phi float [ %result.i140, %IF161 ], [ %tmp258, %ENDIF136 ] + %temp85.0 = phi float [ %result.i136, %IF161 ], [ %tmp259, %ENDIF136 ] + %temp86.0 = phi float [ %result.i132, %IF161 ], [ %tmp260, %ENDIF136 ] + %temp87.0 = phi float [ %result.i128, %IF161 ], [ %tmp261, %ENDIF136 ] + %temp92.6 = phi float [ %tmp638, %IF161 ], [ %tmp411, %ENDIF136 ] + %temp93.0 = phi float [ %tmp639, %IF161 ], [ 0.000000e+00, %ENDIF136 ] + %temp94.0 = phi float [ %tmp640, %IF161 ], [ 0.000000e+00, %ENDIF136 ] + %tmp641 = fcmp olt float 2.200000e+03, %tmp181 + %tmp642 = sext i1 %tmp641 to i32 + %tmp643 = bitcast i32 %tmp642 to float + %tmp644 = fcmp olt float %tmp181, 2.300000e+03 + %tmp645 = sext i1 %tmp644 to i32 + %tmp646 = bitcast i32 %tmp645 to float + %tmp647 = bitcast float %tmp643 to i32 + %tmp648 = bitcast float %tmp646 to i32 + %tmp649 = and i32 %tmp647, %tmp648 + %tmp650 = bitcast i32 %tmp649 to float + %tmp651 = bitcast float %tmp650 to i32 + %tmp652 = icmp ne i32 %tmp651, 0 + br i1 %tmp652, label %IF164, label %ENDIF163 IF164: ; preds = %ENDIF160 - %654 = fmul float %202, 5.000000e-01 - %655 = fcmp uge float 0x3FE4CCCCC0000000, %654 - %656 = select i1 %655, float 0x3FE4CCCCC0000000, float %654 - %657 = fcmp uge float %656, 0x3FD6666660000000 - %658 = select i1 %657, float 0x3FD6666660000000, float %656 - %659 = call float @llvm.AMDGPU.lrp(float %658, float %400, float %300) - %660 = call float @llvm.AMDGPU.lrp(float %658, float %401, float %301) - %661 = call float @llvm.AMDGPU.lrp(float %658, float %402, float %302) - %662 = call float @llvm.AMDGPU.lrp(float %658, float %403, float %303) - %663 = insertelement <4 x float> undef, float %329, i32 0 - %664 = insertelement <4 x float> %663, float %330, i32 1 - %665 = insertelement <4 x float> %664, float %331, i32 2 - %666 = insertelement <4 x float> %665, float 0.000000e+00, i32 3 - %667 = insertelement <4 x float> undef, float %63, i32 0 - %668 = insertelement <4 x float> %667, float %65, i32 1 - %669 = insertelement <4 x float> %668, float %67, i32 2 - %670 = insertelement <4 x float> %669, float 0.000000e+00, i32 3 - %671 = call float @llvm.AMDGPU.dp4(<4 x float> %666, <4 x float> %670) - %672 = fcmp uge float 0x3FE6666660000000, %671 - %673 = select i1 %672, float 0x3FE6666660000000, float %671 - %674 = fmul float %8, %673 - %675 = fmul float %13, %673 - %676 = fmul float %18, %673 - %677 = insertelement <4 x float> undef, float %34, i32 0 - %678 = insertelement <4 x float> %677, float %35, i32 1 - %679 = insertelement <4 x float> %678, float %36, i32 2 - %680 = insertelement <4 x float> %679, float 0.000000e+00, i32 3 - %681 = insertelement <4 x float> undef, float %63, i32 0 - %682 = insertelement <4 x float> %681, float %65, i32 1 - %683 = insertelement <4 x float> %682, float %67, i32 2 - %684 = insertelement <4 x float> %683, float 0.000000e+00, i32 3 - %685 = call float @llvm.AMDGPU.dp4(<4 x float> %680, <4 x float> %684) - %686 = fcmp uge float 0x3FECCCCCC0000000, %685 - %687 = select i1 %686, float 0x3FECCCCCC0000000, float %685 - %688 = fmul float %674, %687 - %689 = fmul float %675, %687 - %690 = fmul float %676, %687 + %tmp653 = fmul float %result.i, 5.000000e-01 + %tmp654 = fcmp uge float 0x3FE4CCCCC0000000, %tmp653 + %tmp655 = select i1 %tmp654, float 0x3FE4CCCCC0000000, float %tmp653 + %tmp656 = fcmp uge float %tmp655, 0x3FD6666660000000 + %tmp657 = select i1 %tmp656, float 0x3FD6666660000000, float %tmp655 + %one.sub.a.i121 = fsub float 1.000000e+00, %tmp657 + %one.sub.ac.i122 = fmul float %one.sub.a.i121, %tmp304 + %mul.i123 = fmul float %result.i172, %tmp304 + %result.i124 = fadd float %mul.i123, %one.sub.ac.i122 + %one.sub.a.i117 = fsub float 1.000000e+00, %tmp657 + %one.sub.ac.i118 = fmul float %one.sub.a.i117, %tmp305 + %mul.i119 = fmul float %result.i168, %tmp305 + %result.i120 = fadd float %mul.i119, %one.sub.ac.i118 + %one.sub.a.i113 = fsub float 1.000000e+00, %tmp657 + %one.sub.ac.i114 = fmul float %one.sub.a.i113, %tmp306 + %mul.i115 = fmul float %result.i164, %tmp306 + %result.i116 = fadd float %mul.i115, %one.sub.ac.i114 + %one.sub.a.i109 = fsub float 1.000000e+00, %tmp657 + %one.sub.ac.i110 = fmul float %one.sub.a.i109, %tmp307 + %mul.i111 = fmul float %result.i160, %tmp307 + %result.i112 = fadd float %mul.i111, %one.sub.ac.i110 + %tmp658 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp659 = insertelement <4 x float> %tmp658, float %tmp334, i32 1 + %tmp660 = insertelement <4 x float> %tmp659, float %tmp335, i32 2 + %tmp661 = insertelement <4 x float> %tmp660, float 0.000000e+00, i32 3 + %tmp662 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp663 = insertelement <4 x float> %tmp662, float %tmp65, i32 1 + %tmp664 = insertelement <4 x float> %tmp663, float %tmp67, i32 2 + %tmp665 = insertelement <4 x float> %tmp664, float 0.000000e+00, i32 3 + %tmp666 = call float @llvm.r600.dot4(<4 x float> %tmp661, <4 x float> %tmp665) + %tmp667 = fcmp uge float 0x3FE6666660000000, %tmp666 + %tmp668 = select i1 %tmp667, float 0x3FE6666660000000, float %tmp666 + %tmp669 = fmul float %tmp8, %tmp668 + %tmp670 = fmul float %tmp13, %tmp668 + %tmp671 = fmul float %tmp18, %tmp668 + %tmp672 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp673 = insertelement <4 x float> %tmp672, float %tmp35, i32 1 + %tmp674 = insertelement <4 x float> %tmp673, float %tmp36, i32 2 + %tmp675 = insertelement <4 x float> %tmp674, float 0.000000e+00, i32 3 + %tmp676 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp677 = insertelement <4 x float> %tmp676, float %tmp65, i32 1 + %tmp678 = insertelement <4 x float> %tmp677, float %tmp67, i32 2 + %tmp679 = insertelement <4 x float> %tmp678, float 0.000000e+00, i32 3 + %tmp680 = call float @llvm.r600.dot4(<4 x float> %tmp675, <4 x float> %tmp679) + %tmp681 = fcmp uge float 0x3FECCCCCC0000000, %tmp680 + %tmp682 = select i1 %tmp681, float 0x3FECCCCCC0000000, float %tmp680 + %tmp683 = fmul float %tmp669, %tmp682 + %tmp684 = fmul float %tmp670, %tmp682 + %tmp685 = fmul float %tmp671, %tmp682 br label %ENDIF163 -ENDIF163: ; preds = %ENDIF160, %IF164 - %temp84.1 = phi float [ %659, %IF164 ], [ %temp84.0, %ENDIF160 ] - %temp85.1 = phi float [ %660, %IF164 ], [ %temp85.0, %ENDIF160 ] - %temp86.1 = phi float [ %661, %IF164 ], [ %temp86.0, %ENDIF160 ] - %temp87.1 = phi float [ %662, %IF164 ], [ %temp87.0, %ENDIF160 ] - %temp92.7 = phi float [ %688, %IF164 ], [ %temp92.6, %ENDIF160 ] - %temp93.1 = phi float [ %689, %IF164 ], [ %temp93.0, %ENDIF160 ] - %temp94.1 = phi float [ %690, %IF164 ], [ %temp94.0, %ENDIF160 ] - %691 = fcmp oge float %179, 2.300000e+03 - %692 = sext i1 %691 to i32 - %693 = bitcast i32 %692 to float - %694 = fcmp olt float %179, 2.480000e+03 - %695 = sext i1 %694 to i32 - %696 = bitcast i32 %695 to float - %697 = bitcast float %693 to i32 - %698 = bitcast float %696 to i32 - %699 = and i32 %697, %698 - %700 = bitcast i32 %699 to float - %701 = bitcast float %700 to i32 - %702 = icmp ne i32 %701, 0 - br i1 %702, label %IF167, label %ENDIF166 +ENDIF163: ; preds = %IF164, %ENDIF160 + %temp84.1 = phi float [ %result.i124, %IF164 ], [ %temp84.0, %ENDIF160 ] + %temp85.1 = phi float [ %result.i120, %IF164 ], [ %temp85.0, %ENDIF160 ] + %temp86.1 = phi float [ %result.i116, %IF164 ], [ %temp86.0, %ENDIF160 ] + %temp87.1 = phi float [ %result.i112, %IF164 ], [ %temp87.0, %ENDIF160 ] + %temp92.7 = phi float [ %tmp683, %IF164 ], [ %temp92.6, %ENDIF160 ] + %temp93.1 = phi float [ %tmp684, %IF164 ], [ %temp93.0, %ENDIF160 ] + %temp94.1 = phi float [ %tmp685, %IF164 ], [ %temp94.0, %ENDIF160 ] + %tmp686 = fcmp oge float %tmp181, 2.300000e+03 + %tmp687 = sext i1 %tmp686 to i32 + %tmp688 = bitcast i32 %tmp687 to float + %tmp689 = fcmp olt float %tmp181, 2.480000e+03 + %tmp690 = sext i1 %tmp689 to i32 + %tmp691 = bitcast i32 %tmp690 to float + %tmp692 = bitcast float %tmp688 to i32 + %tmp693 = bitcast float %tmp691 to i32 + %tmp694 = and i32 %tmp692, %tmp693 + %tmp695 = bitcast i32 %tmp694 to float + %tmp696 = bitcast float %tmp695 to i32 + %tmp697 = icmp ne i32 %tmp696, 0 + br i1 %tmp697, label %IF167, label %ENDIF166 IF167: ; preds = %ENDIF163 - %703 = fmul float %202, 5.000000e-01 - %704 = fcmp uge float 0x3FE4CCCCC0000000, %703 - %705 = select i1 %704, float 0x3FE4CCCCC0000000, float %703 - %706 = fcmp uge float %705, 0x3FD3333340000000 - %707 = select i1 %706, float 0x3FD3333340000000, float %705 - %708 = call float @llvm.AMDGPU.lrp(float %707, float %409, float %300) - %709 = call float @llvm.AMDGPU.lrp(float %707, float %410, float %301) - %710 = call float @llvm.AMDGPU.lrp(float %707, float %411, float %302) - %711 = call float @llvm.AMDGPU.lrp(float %707, float %412, float %303) - %712 = insertelement <4 x float> undef, float %329, i32 0 - %713 = insertelement <4 x float> %712, float %330, i32 1 - %714 = insertelement <4 x float> %713, float %331, i32 2 - %715 = insertelement <4 x float> %714, float 0.000000e+00, i32 3 - %716 = insertelement <4 x float> undef, float %63, i32 0 - %717 = insertelement <4 x float> %716, float %65, i32 1 - %718 = insertelement <4 x float> %717, float %67, i32 2 - %719 = insertelement <4 x float> %718, float 0.000000e+00, i32 3 - %720 = call float @llvm.AMDGPU.dp4(<4 x float> %715, <4 x float> %719) - %721 = fcmp uge float 0x3FEB333340000000, %720 - %722 = select i1 %721, float 0x3FEB333340000000, float %720 - %723 = fmul float %8, %722 - %724 = fmul float %13, %722 - %725 = fmul float %18, %722 - %726 = insertelement <4 x float> undef, float %34, i32 0 - %727 = insertelement <4 x float> %726, float %35, i32 1 - %728 = insertelement <4 x float> %727, float %36, i32 2 - %729 = insertelement <4 x float> %728, float 0.000000e+00, i32 3 - %730 = insertelement <4 x float> undef, float %63, i32 0 - %731 = insertelement <4 x float> %730, float %65, i32 1 - %732 = insertelement <4 x float> %731, float %67, i32 2 - %733 = insertelement <4 x float> %732, float 0.000000e+00, i32 3 - %734 = call float @llvm.AMDGPU.dp4(<4 x float> %729, <4 x float> %733) - %735 = fcmp uge float 0x3FECCCCCC0000000, %734 - %736 = select i1 %735, float 0x3FECCCCCC0000000, float %734 - %737 = fmul float %723, %736 - %738 = fmul float %724, %736 - %739 = fmul float %725, %736 + %tmp698 = fmul float %result.i, 5.000000e-01 + %tmp699 = fcmp uge float 0x3FE4CCCCC0000000, %tmp698 + %tmp700 = select i1 %tmp699, float 0x3FE4CCCCC0000000, float %tmp698 + %tmp701 = fcmp uge float %tmp700, 0x3FD3333340000000 + %tmp702 = select i1 %tmp701, float 0x3FD3333340000000, float %tmp700 + %one.sub.a.i105 = fsub float 1.000000e+00, %tmp702 + %one.sub.ac.i106 = fmul float %one.sub.a.i105, %tmp304 + %mul.i107 = fmul float %result.i156, %tmp304 + %result.i108 = fadd float %mul.i107, %one.sub.ac.i106 + %one.sub.a.i101 = fsub float 1.000000e+00, %tmp702 + %one.sub.ac.i102 = fmul float %one.sub.a.i101, %tmp305 + %mul.i103 = fmul float %result.i152, %tmp305 + %result.i104 = fadd float %mul.i103, %one.sub.ac.i102 + %one.sub.a.i97 = fsub float 1.000000e+00, %tmp702 + %one.sub.ac.i98 = fmul float %one.sub.a.i97, %tmp306 + %mul.i99 = fmul float %result.i148, %tmp306 + %result.i100 = fadd float %mul.i99, %one.sub.ac.i98 + %one.sub.a.i93 = fsub float 1.000000e+00, %tmp702 + %one.sub.ac.i94 = fmul float %one.sub.a.i93, %tmp307 + %mul.i95 = fmul float %result.i144, %tmp307 + %result.i96 = fadd float %mul.i95, %one.sub.ac.i94 + %tmp703 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp704 = insertelement <4 x float> %tmp703, float %tmp334, i32 1 + %tmp705 = insertelement <4 x float> %tmp704, float %tmp335, i32 2 + %tmp706 = insertelement <4 x float> %tmp705, float 0.000000e+00, i32 3 + %tmp707 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp708 = insertelement <4 x float> %tmp707, float %tmp65, i32 1 + %tmp709 = insertelement <4 x float> %tmp708, float %tmp67, i32 2 + %tmp710 = insertelement <4 x float> %tmp709, float 0.000000e+00, i32 3 + %tmp711 = call float @llvm.r600.dot4(<4 x float> %tmp706, <4 x float> %tmp710) + %tmp712 = fcmp uge float 0x3FEB333340000000, %tmp711 + %tmp713 = select i1 %tmp712, float 0x3FEB333340000000, float %tmp711 + %tmp714 = fmul float %tmp8, %tmp713 + %tmp715 = fmul float %tmp13, %tmp713 + %tmp716 = fmul float %tmp18, %tmp713 + %tmp717 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp718 = insertelement <4 x float> %tmp717, float %tmp35, i32 1 + %tmp719 = insertelement <4 x float> %tmp718, float %tmp36, i32 2 + %tmp720 = insertelement <4 x float> %tmp719, float 0.000000e+00, i32 3 + %tmp721 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp722 = insertelement <4 x float> %tmp721, float %tmp65, i32 1 + %tmp723 = insertelement <4 x float> %tmp722, float %tmp67, i32 2 + %tmp724 = insertelement <4 x float> %tmp723, float 0.000000e+00, i32 3 + %tmp725 = call float @llvm.r600.dot4(<4 x float> %tmp720, <4 x float> %tmp724) + %tmp726 = fcmp uge float 0x3FECCCCCC0000000, %tmp725 + %tmp727 = select i1 %tmp726, float 0x3FECCCCCC0000000, float %tmp725 + %tmp728 = fmul float %tmp714, %tmp727 + %tmp729 = fmul float %tmp715, %tmp727 + %tmp730 = fmul float %tmp716, %tmp727 br label %ENDIF166 -ENDIF166: ; preds = %ENDIF163, %IF167 - %temp84.2 = phi float [ %708, %IF167 ], [ %temp84.1, %ENDIF163 ] - %temp85.2 = phi float [ %709, %IF167 ], [ %temp85.1, %ENDIF163 ] - %temp86.2 = phi float [ %710, %IF167 ], [ %temp86.1, %ENDIF163 ] - %temp87.2 = phi float [ %711, %IF167 ], [ %temp87.1, %ENDIF163 ] - %temp92.8 = phi float [ %737, %IF167 ], [ %temp92.7, %ENDIF163 ] - %temp93.2 = phi float [ %738, %IF167 ], [ %temp93.1, %ENDIF163 ] - %temp94.2 = phi float [ %739, %IF167 ], [ %temp94.1, %ENDIF163 ] - %740 = fcmp oge float %179, 2.480000e+03 - %741 = sext i1 %740 to i32 - %742 = bitcast i32 %741 to float - %743 = fcmp olt float %179, 2.530000e+03 - %744 = sext i1 %743 to i32 - %745 = bitcast i32 %744 to float - %746 = bitcast float %742 to i32 - %747 = bitcast float %745 to i32 - %748 = and i32 %746, %747 - %749 = bitcast i32 %748 to float - %750 = bitcast float %749 to i32 - %751 = icmp ne i32 %750, 0 - br i1 %751, label %IF170, label %ENDIF169 +ENDIF166: ; preds = %IF167, %ENDIF163 + %temp84.2 = phi float [ %result.i108, %IF167 ], [ %temp84.1, %ENDIF163 ] + %temp85.2 = phi float [ %result.i104, %IF167 ], [ %temp85.1, %ENDIF163 ] + %temp86.2 = phi float [ %result.i100, %IF167 ], [ %temp86.1, %ENDIF163 ] + %temp87.2 = phi float [ %result.i96, %IF167 ], [ %temp87.1, %ENDIF163 ] + %temp92.8 = phi float [ %tmp728, %IF167 ], [ %temp92.7, %ENDIF163 ] + %temp93.2 = phi float [ %tmp729, %IF167 ], [ %temp93.1, %ENDIF163 ] + %temp94.2 = phi float [ %tmp730, %IF167 ], [ %temp94.1, %ENDIF163 ] + %tmp731 = fcmp oge float %tmp181, 2.480000e+03 + %tmp732 = sext i1 %tmp731 to i32 + %tmp733 = bitcast i32 %tmp732 to float + %tmp734 = fcmp olt float %tmp181, 2.530000e+03 + %tmp735 = sext i1 %tmp734 to i32 + %tmp736 = bitcast i32 %tmp735 to float + %tmp737 = bitcast float %tmp733 to i32 + %tmp738 = bitcast float %tmp736 to i32 + %tmp739 = and i32 %tmp737, %tmp738 + %tmp740 = bitcast i32 %tmp739 to float + %tmp741 = bitcast float %tmp740 to i32 + %tmp742 = icmp ne i32 %tmp741, 0 + br i1 %tmp742, label %IF170, label %ENDIF169 IF170: ; preds = %ENDIF166 - %752 = fmul float %202, 5.000000e-01 - %753 = fcmp uge float 0x3FE4CCCCC0000000, %752 - %754 = select i1 %753, float 0x3FE4CCCCC0000000, float %752 - %755 = fcmp uge float %754, 0x3FC99999A0000000 - %756 = select i1 %755, float 0x3FC99999A0000000, float %754 - %757 = call float @llvm.AMDGPU.lrp(float %756, float %409, float %300) - %758 = call float @llvm.AMDGPU.lrp(float %756, float %410, float %301) - %759 = call float @llvm.AMDGPU.lrp(float %756, float %411, float %302) - %760 = call float @llvm.AMDGPU.lrp(float %756, float %412, float %303) - %761 = insertelement <4 x float> undef, float %329, i32 0 - %762 = insertelement <4 x float> %761, float %330, i32 1 - %763 = insertelement <4 x float> %762, float %331, i32 2 - %764 = insertelement <4 x float> %763, float 0.000000e+00, i32 3 - %765 = insertelement <4 x float> undef, float %63, i32 0 - %766 = insertelement <4 x float> %765, float %65, i32 1 - %767 = insertelement <4 x float> %766, float %67, i32 2 - %768 = insertelement <4 x float> %767, float 0.000000e+00, i32 3 - %769 = call float @llvm.AMDGPU.dp4(<4 x float> %764, <4 x float> %768) - %770 = fcmp uge float 0x3FEB333340000000, %769 - %771 = select i1 %770, float 0x3FEB333340000000, float %769 - %772 = fmul float %8, %771 - %773 = fmul float %13, %771 - %774 = fmul float %18, %771 - %775 = insertelement <4 x float> undef, float %34, i32 0 - %776 = insertelement <4 x float> %775, float %35, i32 1 - %777 = insertelement <4 x float> %776, float %36, i32 2 - %778 = insertelement <4 x float> %777, float 0.000000e+00, i32 3 - %779 = insertelement <4 x float> undef, float %63, i32 0 - %780 = insertelement <4 x float> %779, float %65, i32 1 - %781 = insertelement <4 x float> %780, float %67, i32 2 - %782 = insertelement <4 x float> %781, float 0.000000e+00, i32 3 - %783 = call float @llvm.AMDGPU.dp4(<4 x float> %778, <4 x float> %782) - %784 = fcmp uge float 0x3FECCCCCC0000000, %783 - %785 = select i1 %784, float 0x3FECCCCCC0000000, float %783 - %786 = fmul float %772, %785 - %787 = fmul float %773, %785 - %788 = fmul float %774, %785 + %tmp743 = fmul float %result.i, 5.000000e-01 + %tmp744 = fcmp uge float 0x3FE4CCCCC0000000, %tmp743 + %tmp745 = select i1 %tmp744, float 0x3FE4CCCCC0000000, float %tmp743 + %tmp746 = fcmp uge float %tmp745, 0x3FC99999A0000000 + %tmp747 = select i1 %tmp746, float 0x3FC99999A0000000, float %tmp745 + %one.sub.a.i89 = fsub float 1.000000e+00, %tmp747 + %one.sub.ac.i90 = fmul float %one.sub.a.i89, %tmp304 + %mul.i91 = fmul float %result.i156, %tmp304 + %result.i92 = fadd float %mul.i91, %one.sub.ac.i90 + %one.sub.a.i85 = fsub float 1.000000e+00, %tmp747 + %one.sub.ac.i86 = fmul float %one.sub.a.i85, %tmp305 + %mul.i87 = fmul float %result.i152, %tmp305 + %result.i88 = fadd float %mul.i87, %one.sub.ac.i86 + %one.sub.a.i81 = fsub float 1.000000e+00, %tmp747 + %one.sub.ac.i82 = fmul float %one.sub.a.i81, %tmp306 + %mul.i83 = fmul float %result.i148, %tmp306 + %result.i84 = fadd float %mul.i83, %one.sub.ac.i82 + %one.sub.a.i77 = fsub float 1.000000e+00, %tmp747 + %one.sub.ac.i78 = fmul float %one.sub.a.i77, %tmp307 + %mul.i79 = fmul float %result.i144, %tmp307 + %result.i80 = fadd float %mul.i79, %one.sub.ac.i78 + %tmp748 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp749 = insertelement <4 x float> %tmp748, float %tmp334, i32 1 + %tmp750 = insertelement <4 x float> %tmp749, float %tmp335, i32 2 + %tmp751 = insertelement <4 x float> %tmp750, float 0.000000e+00, i32 3 + %tmp752 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp753 = insertelement <4 x float> %tmp752, float %tmp65, i32 1 + %tmp754 = insertelement <4 x float> %tmp753, float %tmp67, i32 2 + %tmp755 = insertelement <4 x float> %tmp754, float 0.000000e+00, i32 3 + %tmp756 = call float @llvm.r600.dot4(<4 x float> %tmp751, <4 x float> %tmp755) + %tmp757 = fcmp uge float 0x3FEB333340000000, %tmp756 + %tmp758 = select i1 %tmp757, float 0x3FEB333340000000, float %tmp756 + %tmp759 = fmul float %tmp8, %tmp758 + %tmp760 = fmul float %tmp13, %tmp758 + %tmp761 = fmul float %tmp18, %tmp758 + %tmp762 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp763 = insertelement <4 x float> %tmp762, float %tmp35, i32 1 + %tmp764 = insertelement <4 x float> %tmp763, float %tmp36, i32 2 + %tmp765 = insertelement <4 x float> %tmp764, float 0.000000e+00, i32 3 + %tmp766 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp767 = insertelement <4 x float> %tmp766, float %tmp65, i32 1 + %tmp768 = insertelement <4 x float> %tmp767, float %tmp67, i32 2 + %tmp769 = insertelement <4 x float> %tmp768, float 0.000000e+00, i32 3 + %tmp770 = call float @llvm.r600.dot4(<4 x float> %tmp765, <4 x float> %tmp769) + %tmp771 = fcmp uge float 0x3FECCCCCC0000000, %tmp770 + %tmp772 = select i1 %tmp771, float 0x3FECCCCCC0000000, float %tmp770 + %tmp773 = fmul float %tmp759, %tmp772 + %tmp774 = fmul float %tmp760, %tmp772 + %tmp775 = fmul float %tmp761, %tmp772 br label %ENDIF169 -ENDIF169: ; preds = %ENDIF166, %IF170 - %temp84.3 = phi float [ %757, %IF170 ], [ %temp84.2, %ENDIF166 ] - %temp85.3 = phi float [ %758, %IF170 ], [ %temp85.2, %ENDIF166 ] - %temp86.3 = phi float [ %759, %IF170 ], [ %temp86.2, %ENDIF166 ] - %temp87.3 = phi float [ %760, %IF170 ], [ %temp87.2, %ENDIF166 ] - %temp92.9 = phi float [ %786, %IF170 ], [ %temp92.8, %ENDIF166 ] - %temp93.3 = phi float [ %787, %IF170 ], [ %temp93.2, %ENDIF166 ] - %temp94.3 = phi float [ %788, %IF170 ], [ %temp94.2, %ENDIF166 ] - %789 = fcmp oge float %179, 2.530000e+03 - %790 = sext i1 %789 to i32 - %791 = bitcast i32 %790 to float - %792 = fcmp olt float %179, 2.670000e+03 - %793 = sext i1 %792 to i32 - %794 = bitcast i32 %793 to float - %795 = bitcast float %791 to i32 - %796 = bitcast float %794 to i32 - %797 = and i32 %795, %796 - %798 = bitcast i32 %797 to float - %799 = bitcast float %798 to i32 - %800 = icmp ne i32 %799, 0 - br i1 %800, label %IF173, label %ENDIF172 +ENDIF169: ; preds = %IF170, %ENDIF166 + %temp84.3 = phi float [ %result.i92, %IF170 ], [ %temp84.2, %ENDIF166 ] + %temp85.3 = phi float [ %result.i88, %IF170 ], [ %temp85.2, %ENDIF166 ] + %temp86.3 = phi float [ %result.i84, %IF170 ], [ %temp86.2, %ENDIF166 ] + %temp87.3 = phi float [ %result.i80, %IF170 ], [ %temp87.2, %ENDIF166 ] + %temp92.9 = phi float [ %tmp773, %IF170 ], [ %temp92.8, %ENDIF166 ] + %temp93.3 = phi float [ %tmp774, %IF170 ], [ %temp93.2, %ENDIF166 ] + %temp94.3 = phi float [ %tmp775, %IF170 ], [ %temp94.2, %ENDIF166 ] + %tmp776 = fcmp oge float %tmp181, 2.530000e+03 + %tmp777 = sext i1 %tmp776 to i32 + %tmp778 = bitcast i32 %tmp777 to float + %tmp779 = fcmp olt float %tmp181, 2.670000e+03 + %tmp780 = sext i1 %tmp779 to i32 + %tmp781 = bitcast i32 %tmp780 to float + %tmp782 = bitcast float %tmp778 to i32 + %tmp783 = bitcast float %tmp781 to i32 + %tmp784 = and i32 %tmp782, %tmp783 + %tmp785 = bitcast i32 %tmp784 to float + %tmp786 = bitcast float %tmp785 to i32 + %tmp787 = icmp ne i32 %tmp786, 0 + br i1 %tmp787, label %IF173, label %ENDIF172 IF173: ; preds = %ENDIF169 - %801 = fmul float %202, 5.000000e-01 - %802 = fcmp uge float 0x3FE4CCCCC0000000, %801 - %803 = select i1 %802, float 0x3FE4CCCCC0000000, float %801 - %804 = fcmp uge float %803, 0x3FB99999A0000000 - %805 = select i1 %804, float 0x3FB99999A0000000, float %803 - %806 = call float @llvm.AMDGPU.lrp(float %805, float %400, float %300) - %807 = call float @llvm.AMDGPU.lrp(float %805, float %401, float %301) - %808 = call float @llvm.AMDGPU.lrp(float %805, float %402, float %302) - %809 = call float @llvm.AMDGPU.lrp(float %805, float %403, float %303) - %810 = insertelement <4 x float> undef, float %329, i32 0 - %811 = insertelement <4 x float> %810, float %330, i32 1 - %812 = insertelement <4 x float> %811, float %331, i32 2 - %813 = insertelement <4 x float> %812, float 0.000000e+00, i32 3 - %814 = insertelement <4 x float> undef, float %63, i32 0 - %815 = insertelement <4 x float> %814, float %65, i32 1 - %816 = insertelement <4 x float> %815, float %67, i32 2 - %817 = insertelement <4 x float> %816, float 0.000000e+00, i32 3 - %818 = call float @llvm.AMDGPU.dp4(<4 x float> %813, <4 x float> %817) - %819 = fcmp uge float 0x3FEB333340000000, %818 - %820 = select i1 %819, float 0x3FEB333340000000, float %818 - %821 = fmul float %8, %820 - %822 = fmul float %13, %820 - %823 = fmul float %18, %820 - %824 = insertelement <4 x float> undef, float %34, i32 0 - %825 = insertelement <4 x float> %824, float %35, i32 1 - %826 = insertelement <4 x float> %825, float %36, i32 2 - %827 = insertelement <4 x float> %826, float 0.000000e+00, i32 3 - %828 = insertelement <4 x float> undef, float %63, i32 0 - %829 = insertelement <4 x float> %828, float %65, i32 1 - %830 = insertelement <4 x float> %829, float %67, i32 2 - %831 = insertelement <4 x float> %830, float 0.000000e+00, i32 3 - %832 = call float @llvm.AMDGPU.dp4(<4 x float> %827, <4 x float> %831) - %833 = fcmp uge float 0x3FECCCCCC0000000, %832 - %834 = select i1 %833, float 0x3FECCCCCC0000000, float %832 - %835 = fmul float %821, %834 - %836 = fmul float %822, %834 - %837 = fmul float %823, %834 + %tmp788 = fmul float %result.i, 5.000000e-01 + %tmp789 = fcmp uge float 0x3FE4CCCCC0000000, %tmp788 + %tmp790 = select i1 %tmp789, float 0x3FE4CCCCC0000000, float %tmp788 + %tmp791 = fcmp uge float %tmp790, 0x3FB99999A0000000 + %tmp792 = select i1 %tmp791, float 0x3FB99999A0000000, float %tmp790 + %one.sub.a.i73 = fsub float 1.000000e+00, %tmp792 + %one.sub.ac.i74 = fmul float %one.sub.a.i73, %tmp304 + %mul.i75 = fmul float %result.i172, %tmp304 + %result.i76 = fadd float %mul.i75, %one.sub.ac.i74 + %one.sub.a.i69 = fsub float 1.000000e+00, %tmp792 + %one.sub.ac.i70 = fmul float %one.sub.a.i69, %tmp305 + %mul.i71 = fmul float %result.i168, %tmp305 + %result.i72 = fadd float %mul.i71, %one.sub.ac.i70 + %one.sub.a.i65 = fsub float 1.000000e+00, %tmp792 + %one.sub.ac.i66 = fmul float %one.sub.a.i65, %tmp306 + %mul.i67 = fmul float %result.i164, %tmp306 + %result.i68 = fadd float %mul.i67, %one.sub.ac.i66 + %one.sub.a.i61 = fsub float 1.000000e+00, %tmp792 + %one.sub.ac.i62 = fmul float %one.sub.a.i61, %tmp307 + %mul.i63 = fmul float %result.i160, %tmp307 + %result.i64 = fadd float %mul.i63, %one.sub.ac.i62 + %tmp793 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp794 = insertelement <4 x float> %tmp793, float %tmp334, i32 1 + %tmp795 = insertelement <4 x float> %tmp794, float %tmp335, i32 2 + %tmp796 = insertelement <4 x float> %tmp795, float 0.000000e+00, i32 3 + %tmp797 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp798 = insertelement <4 x float> %tmp797, float %tmp65, i32 1 + %tmp799 = insertelement <4 x float> %tmp798, float %tmp67, i32 2 + %tmp800 = insertelement <4 x float> %tmp799, float 0.000000e+00, i32 3 + %tmp801 = call float @llvm.r600.dot4(<4 x float> %tmp796, <4 x float> %tmp800) + %tmp802 = fcmp uge float 0x3FEB333340000000, %tmp801 + %tmp803 = select i1 %tmp802, float 0x3FEB333340000000, float %tmp801 + %tmp804 = fmul float %tmp8, %tmp803 + %tmp805 = fmul float %tmp13, %tmp803 + %tmp806 = fmul float %tmp18, %tmp803 + %tmp807 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp808 = insertelement <4 x float> %tmp807, float %tmp35, i32 1 + %tmp809 = insertelement <4 x float> %tmp808, float %tmp36, i32 2 + %tmp810 = insertelement <4 x float> %tmp809, float 0.000000e+00, i32 3 + %tmp811 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp812 = insertelement <4 x float> %tmp811, float %tmp65, i32 1 + %tmp813 = insertelement <4 x float> %tmp812, float %tmp67, i32 2 + %tmp814 = insertelement <4 x float> %tmp813, float 0.000000e+00, i32 3 + %tmp815 = call float @llvm.r600.dot4(<4 x float> %tmp810, <4 x float> %tmp814) + %tmp816 = fcmp uge float 0x3FECCCCCC0000000, %tmp815 + %tmp817 = select i1 %tmp816, float 0x3FECCCCCC0000000, float %tmp815 + %tmp818 = fmul float %tmp804, %tmp817 + %tmp819 = fmul float %tmp805, %tmp817 + %tmp820 = fmul float %tmp806, %tmp817 br label %ENDIF172 -ENDIF172: ; preds = %ENDIF169, %IF173 - %temp84.4 = phi float [ %806, %IF173 ], [ %temp84.3, %ENDIF169 ] - %temp85.4 = phi float [ %807, %IF173 ], [ %temp85.3, %ENDIF169 ] - %temp86.4 = phi float [ %808, %IF173 ], [ %temp86.3, %ENDIF169 ] - %temp87.4 = phi float [ %809, %IF173 ], [ %temp87.3, %ENDIF169 ] - %temp92.10 = phi float [ %835, %IF173 ], [ %temp92.9, %ENDIF169 ] - %temp93.4 = phi float [ %836, %IF173 ], [ %temp93.3, %ENDIF169 ] - %temp94.4 = phi float [ %837, %IF173 ], [ %temp94.3, %ENDIF169 ] - %838 = fcmp oge float %179, 2.670000e+03 - %839 = sext i1 %838 to i32 - %840 = bitcast i32 %839 to float - %841 = bitcast float %840 to i32 - %842 = icmp ne i32 %841, 0 - br i1 %842, label %IF176, label %ENDIF175 +ENDIF172: ; preds = %IF173, %ENDIF169 + %temp84.4 = phi float [ %result.i76, %IF173 ], [ %temp84.3, %ENDIF169 ] + %temp85.4 = phi float [ %result.i72, %IF173 ], [ %temp85.3, %ENDIF169 ] + %temp86.4 = phi float [ %result.i68, %IF173 ], [ %temp86.3, %ENDIF169 ] + %temp87.4 = phi float [ %result.i64, %IF173 ], [ %temp87.3, %ENDIF169 ] + %temp92.10 = phi float [ %tmp818, %IF173 ], [ %temp92.9, %ENDIF169 ] + %temp93.4 = phi float [ %tmp819, %IF173 ], [ %temp93.3, %ENDIF169 ] + %temp94.4 = phi float [ %tmp820, %IF173 ], [ %temp94.3, %ENDIF169 ] + %tmp821 = fcmp oge float %tmp181, 2.670000e+03 + %tmp822 = sext i1 %tmp821 to i32 + %tmp823 = bitcast i32 %tmp822 to float + %tmp824 = bitcast float %tmp823 to i32 + %tmp825 = icmp ne i32 %tmp824, 0 + br i1 %tmp825, label %IF176, label %ENDIF175 IF176: ; preds = %ENDIF172 - %843 = fmul float %202, 0x3FB99999A0000000 - %844 = fcmp uge float 0.000000e+00, %843 - %845 = select i1 %844, float 0.000000e+00, float %843 - %846 = fcmp uge float %845, 0x3FD99999A0000000 - %847 = select i1 %846, float 0x3FD99999A0000000, float %845 - %848 = call float @llvm.AMDGPU.lrp(float %847, float %400, float %300) - %849 = call float @llvm.AMDGPU.lrp(float %847, float %401, float %301) - %850 = call float @llvm.AMDGPU.lrp(float %847, float %402, float %302) - %851 = call float @llvm.AMDGPU.lrp(float %847, float %403, float %303) - %852 = insertelement <4 x float> undef, float %329, i32 0 - %853 = insertelement <4 x float> %852, float %330, i32 1 - %854 = insertelement <4 x float> %853, float %331, i32 2 - %855 = insertelement <4 x float> %854, float 0.000000e+00, i32 3 - %856 = insertelement <4 x float> undef, float %63, i32 0 - %857 = insertelement <4 x float> %856, float %65, i32 1 - %858 = insertelement <4 x float> %857, float %67, i32 2 - %859 = insertelement <4 x float> %858, float 0.000000e+00, i32 3 - %860 = call float @llvm.AMDGPU.dp4(<4 x float> %855, <4 x float> %859) - %861 = fcmp uge float 0x3FEB333340000000, %860 - %862 = select i1 %861, float 0x3FEB333340000000, float %860 - %863 = fmul float %8, %862 - %864 = fmul float %13, %862 - %865 = fmul float %18, %862 - %866 = insertelement <4 x float> undef, float %34, i32 0 - %867 = insertelement <4 x float> %866, float %35, i32 1 - %868 = insertelement <4 x float> %867, float %36, i32 2 - %869 = insertelement <4 x float> %868, float 0.000000e+00, i32 3 - %870 = insertelement <4 x float> undef, float %63, i32 0 - %871 = insertelement <4 x float> %870, float %65, i32 1 - %872 = insertelement <4 x float> %871, float %67, i32 2 - %873 = insertelement <4 x float> %872, float 0.000000e+00, i32 3 - %874 = call float @llvm.AMDGPU.dp4(<4 x float> %869, <4 x float> %873) - %875 = fcmp uge float 0x3FECCCCCC0000000, %874 - %876 = select i1 %875, float 0x3FECCCCCC0000000, float %874 - %877 = fmul float %863, %876 - %878 = fmul float %864, %876 - %879 = fmul float %865, %876 + %tmp826 = fmul float %result.i, 0x3FB99999A0000000 + %tmp827 = fcmp uge float 0.000000e+00, %tmp826 + %tmp828 = select i1 %tmp827, float 0.000000e+00, float %tmp826 + %tmp829 = fcmp uge float %tmp828, 0x3FD99999A0000000 + %tmp830 = select i1 %tmp829, float 0x3FD99999A0000000, float %tmp828 + %one.sub.a.i57 = fsub float 1.000000e+00, %tmp830 + %one.sub.ac.i58 = fmul float %one.sub.a.i57, %tmp304 + %mul.i59 = fmul float %result.i172, %tmp304 + %result.i60 = fadd float %mul.i59, %one.sub.ac.i58 + %one.sub.a.i53 = fsub float 1.000000e+00, %tmp830 + %one.sub.ac.i54 = fmul float %one.sub.a.i53, %tmp305 + %mul.i55 = fmul float %result.i168, %tmp305 + %result.i56 = fadd float %mul.i55, %one.sub.ac.i54 + %one.sub.a.i49 = fsub float 1.000000e+00, %tmp830 + %one.sub.ac.i50 = fmul float %one.sub.a.i49, %tmp306 + %mul.i51 = fmul float %result.i164, %tmp306 + %result.i52 = fadd float %mul.i51, %one.sub.ac.i50 + %one.sub.a.i45 = fsub float 1.000000e+00, %tmp830 + %one.sub.ac.i46 = fmul float %one.sub.a.i45, %tmp307 + %mul.i47 = fmul float %result.i160, %tmp307 + %result.i48 = fadd float %mul.i47, %one.sub.ac.i46 + %tmp831 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp832 = insertelement <4 x float> %tmp831, float %tmp334, i32 1 + %tmp833 = insertelement <4 x float> %tmp832, float %tmp335, i32 2 + %tmp834 = insertelement <4 x float> %tmp833, float 0.000000e+00, i32 3 + %tmp835 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp836 = insertelement <4 x float> %tmp835, float %tmp65, i32 1 + %tmp837 = insertelement <4 x float> %tmp836, float %tmp67, i32 2 + %tmp838 = insertelement <4 x float> %tmp837, float 0.000000e+00, i32 3 + %tmp839 = call float @llvm.r600.dot4(<4 x float> %tmp834, <4 x float> %tmp838) + %tmp840 = fcmp uge float 0x3FEB333340000000, %tmp839 + %tmp841 = select i1 %tmp840, float 0x3FEB333340000000, float %tmp839 + %tmp842 = fmul float %tmp8, %tmp841 + %tmp843 = fmul float %tmp13, %tmp841 + %tmp844 = fmul float %tmp18, %tmp841 + %tmp845 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp846 = insertelement <4 x float> %tmp845, float %tmp35, i32 1 + %tmp847 = insertelement <4 x float> %tmp846, float %tmp36, i32 2 + %tmp848 = insertelement <4 x float> %tmp847, float 0.000000e+00, i32 3 + %tmp849 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp850 = insertelement <4 x float> %tmp849, float %tmp65, i32 1 + %tmp851 = insertelement <4 x float> %tmp850, float %tmp67, i32 2 + %tmp852 = insertelement <4 x float> %tmp851, float 0.000000e+00, i32 3 + %tmp853 = call float @llvm.r600.dot4(<4 x float> %tmp848, <4 x float> %tmp852) + %tmp854 = fcmp uge float 0x3FECCCCCC0000000, %tmp853 + %tmp855 = select i1 %tmp854, float 0x3FECCCCCC0000000, float %tmp853 + %tmp856 = fmul float %tmp842, %tmp855 + %tmp857 = fmul float %tmp843, %tmp855 + %tmp858 = fmul float %tmp844, %tmp855 br label %ENDIF175 -ENDIF175: ; preds = %ENDIF172, %IF176 - %temp84.5 = phi float [ %848, %IF176 ], [ %temp84.4, %ENDIF172 ] - %temp85.5 = phi float [ %849, %IF176 ], [ %temp85.4, %ENDIF172 ] - %temp86.5 = phi float [ %850, %IF176 ], [ %temp86.4, %ENDIF172 ] - %temp87.5 = phi float [ %851, %IF176 ], [ %temp87.4, %ENDIF172 ] - %temp92.11 = phi float [ %877, %IF176 ], [ %temp92.10, %ENDIF172 ] - %temp93.5 = phi float [ %878, %IF176 ], [ %temp93.4, %ENDIF172 ] - %temp94.5 = phi float [ %879, %IF176 ], [ %temp94.4, %ENDIF172 ] - %880 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) - %881 = extractelement <4 x float> %880, i32 0 - %882 = fcmp olt float %881, %179 - %883 = sext i1 %882 to i32 - %884 = bitcast i32 %883 to float - %885 = bitcast float %884 to i32 - %886 = icmp ne i32 %885, 0 - br i1 %886, label %IF179, label %ENDIF178 +ENDIF175: ; preds = %IF176, %ENDIF172 + %temp84.5 = phi float [ %result.i60, %IF176 ], [ %temp84.4, %ENDIF172 ] + %temp85.5 = phi float [ %result.i56, %IF176 ], [ %temp85.4, %ENDIF172 ] + %temp86.5 = phi float [ %result.i52, %IF176 ], [ %temp86.4, %ENDIF172 ] + %temp87.5 = phi float [ %result.i48, %IF176 ], [ %temp87.4, %ENDIF172 ] + %temp92.11 = phi float [ %tmp856, %IF176 ], [ %temp92.10, %ENDIF172 ] + %temp93.5 = phi float [ %tmp857, %IF176 ], [ %temp93.4, %ENDIF172 ] + %temp94.5 = phi float [ %tmp858, %IF176 ], [ %temp94.4, %ENDIF172 ] + %tmp859 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 10) + %tmp860 = extractelement <4 x float> %tmp859, i32 0 + %tmp861 = fcmp olt float %tmp860, %tmp181 + %tmp862 = sext i1 %tmp861 to i32 + %tmp863 = bitcast i32 %tmp862 to float + %tmp864 = bitcast float %tmp863 to i32 + %tmp865 = icmp ne i32 %tmp864, 0 + br i1 %tmp865, label %IF179, label %ENDIF178 IF179: ; preds = %ENDIF175 - %887 = fadd float %202, 1.000000e+00 - %888 = fadd float %202, 1.000000e+00 - %889 = fadd float %202, 1.000000e+00 - %890 = insertelement <4 x float> undef, float %43, i32 0 - %891 = insertelement <4 x float> %890, float %44, i32 1 - %892 = insertelement <4 x float> %891, float %45, i32 2 - %893 = insertelement <4 x float> %892, float 0.000000e+00, i32 3 - %894 = insertelement <4 x float> undef, float %43, i32 0 - %895 = insertelement <4 x float> %894, float %44, i32 1 - %896 = insertelement <4 x float> %895, float %45, i32 2 - %897 = insertelement <4 x float> %896, float 0.000000e+00, i32 3 - %898 = call float @llvm.AMDGPU.dp4(<4 x float> %893, <4 x float> %897) - %899 = call float @llvm.AMDGPU.rsq.f32(float %898) - %900 = fmul float %45, %899 - %901 = call float @fabs(float %900) - %902 = fmul float %176, 0x3FECCCCCC0000000 - %903 = fadd float %902, %901 - %904 = fadd float %903, 0xBFEFAE1480000000 - %905 = fmul float %904, 0xC043FFFE20000000 - %906 = call float @llvm.AMDIL.clamp.(float %905, float 0.000000e+00, float 1.000000e+00) - %907 = fmul float 2.000000e+00, %906 - %908 = fsub float -0.000000e+00, %907 - %909 = fadd float 3.000000e+00, %908 - %910 = fmul float %906, %909 - %911 = fmul float %906, %910 - %912 = call float @llvm.AMDGPU.lrp(float %911, float %temp84.5, float %887) - %913 = call float @llvm.AMDGPU.lrp(float %911, float %temp85.5, float %888) - %914 = call float @llvm.AMDGPU.lrp(float %911, float %temp86.5, float %889) - %915 = call float @llvm.AMDGPU.lrp(float %911, float %temp87.5, float 0.000000e+00) - %916 = fmul float %202, 5.000000e-01 - %917 = fcmp uge float 0x3FE4CCCCC0000000, %916 - %918 = select i1 %917, float 0x3FE4CCCCC0000000, float %916 - %919 = fcmp uge float %918, 0x3FE3333340000000 - %920 = select i1 %919, float 0x3FE3333340000000, float %918 - %921 = call float @llvm.AMDGPU.lrp(float %920, float %912, float %temp84.5) - %922 = call float @llvm.AMDGPU.lrp(float %920, float %913, float %temp85.5) - %923 = call float @llvm.AMDGPU.lrp(float %920, float %914, float %temp86.5) - %924 = call float @llvm.AMDGPU.lrp(float %920, float %915, float %temp87.5) - %925 = insertelement <4 x float> undef, float %329, i32 0 - %926 = insertelement <4 x float> %925, float %330, i32 1 - %927 = insertelement <4 x float> %926, float %331, i32 2 - %928 = insertelement <4 x float> %927, float 0.000000e+00, i32 3 - %929 = insertelement <4 x float> undef, float %63, i32 0 - %930 = insertelement <4 x float> %929, float %65, i32 1 - %931 = insertelement <4 x float> %930, float %67, i32 2 - %932 = insertelement <4 x float> %931, float 0.000000e+00, i32 3 - %933 = call float @llvm.AMDGPU.dp4(<4 x float> %928, <4 x float> %932) - %934 = fcmp uge float 0x3FE99999A0000000, %933 - %935 = select i1 %934, float 0x3FE99999A0000000, float %933 - %936 = fmul float %8, %935 - %937 = fmul float %13, %935 - %938 = fmul float %18, %935 - %939 = insertelement <4 x float> undef, float %34, i32 0 - %940 = insertelement <4 x float> %939, float %35, i32 1 - %941 = insertelement <4 x float> %940, float %36, i32 2 - %942 = insertelement <4 x float> %941, float 0.000000e+00, i32 3 - %943 = insertelement <4 x float> undef, float %63, i32 0 - %944 = insertelement <4 x float> %943, float %65, i32 1 - %945 = insertelement <4 x float> %944, float %67, i32 2 - %946 = insertelement <4 x float> %945, float 0.000000e+00, i32 3 - %947 = call float @llvm.AMDGPU.dp4(<4 x float> %942, <4 x float> %946) - %948 = fcmp uge float 0x3FECCCCCC0000000, %947 - %949 = select i1 %948, float 0x3FECCCCCC0000000, float %947 - %950 = fmul float %936, %949 - %951 = fmul float %937, %949 - %952 = fmul float %938, %949 + %tmp866 = fadd float %result.i, 1.000000e+00 + %tmp867 = fadd float %result.i, 1.000000e+00 + %tmp868 = fadd float %result.i, 1.000000e+00 + %tmp869 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp870 = insertelement <4 x float> %tmp869, float %tmp44, i32 1 + %tmp871 = insertelement <4 x float> %tmp870, float %tmp45, i32 2 + %tmp872 = insertelement <4 x float> %tmp871, float 0.000000e+00, i32 3 + %tmp873 = insertelement <4 x float> undef, float %tmp43, i32 0 + %tmp874 = insertelement <4 x float> %tmp873, float %tmp44, i32 1 + %tmp875 = insertelement <4 x float> %tmp874, float %tmp45, i32 2 + %tmp876 = insertelement <4 x float> %tmp875, float 0.000000e+00, i32 3 + %tmp877 = call float @llvm.r600.dot4(<4 x float> %tmp872, <4 x float> %tmp876) + %tmp878 = call float @llvm.r600.recipsqrt.clamped.f32(float %tmp877) + %tmp879 = fmul float %tmp45, %tmp878 + %tmp880 = call float @llvm.fabs.f32(float %tmp879) + %tmp881 = fmul float %tmp178, 0x3FECCCCCC0000000 + %tmp882 = fadd float %tmp881, %tmp880 + %tmp883 = fadd float %tmp882, 0xBFEFAE1480000000 + %tmp884 = fmul float %tmp883, 0xC043FFFE20000000 + %tmp885 = call float @llvm.AMDGPU.clamp.f32(float %tmp884, float 0.000000e+00, float 1.000000e+00) + %tmp886 = fmul float 2.000000e+00, %tmp885 + %tmp887 = fsub float -0.000000e+00, %tmp886 + %tmp888 = fadd float 3.000000e+00, %tmp887 + %tmp889 = fmul float %tmp885, %tmp888 + %tmp890 = fmul float %tmp885, %tmp889 + %one.sub.a.i41 = fsub float 1.000000e+00, %tmp890 + %one.sub.ac.i42 = fmul float %one.sub.a.i41, %tmp866 + %mul.i43 = fmul float %temp84.5, %tmp866 + %result.i44 = fadd float %mul.i43, %one.sub.ac.i42 + %one.sub.a.i37 = fsub float 1.000000e+00, %tmp890 + %one.sub.ac.i38 = fmul float %one.sub.a.i37, %tmp867 + %mul.i39 = fmul float %temp85.5, %tmp867 + %result.i40 = fadd float %mul.i39, %one.sub.ac.i38 + %one.sub.a.i33 = fsub float 1.000000e+00, %tmp890 + %one.sub.ac.i34 = fmul float %one.sub.a.i33, %tmp868 + %mul.i35 = fmul float %temp86.5, %tmp868 + %result.i36 = fadd float %mul.i35, %one.sub.ac.i34 + %one.sub.a.i29 = fsub float 1.000000e+00, %tmp890 + %one.sub.ac.i30 = fmul float %one.sub.a.i29, 0.000000e+00 + %mul.i31 = fmul float %temp87.5, 0.000000e+00 + %result.i32 = fadd float %mul.i31, %one.sub.ac.i30 + %tmp891 = fmul float %result.i, 5.000000e-01 + %tmp892 = fcmp uge float 0x3FE4CCCCC0000000, %tmp891 + %tmp893 = select i1 %tmp892, float 0x3FE4CCCCC0000000, float %tmp891 + %tmp894 = fcmp uge float %tmp893, 0x3FE3333340000000 + %tmp895 = select i1 %tmp894, float 0x3FE3333340000000, float %tmp893 + %one.sub.a.i25 = fsub float 1.000000e+00, %tmp895 + %one.sub.ac.i26 = fmul float %one.sub.a.i25, %temp84.5 + %mul.i27 = fmul float %result.i44, %temp84.5 + %result.i28 = fadd float %mul.i27, %one.sub.ac.i26 + %one.sub.a.i21 = fsub float 1.000000e+00, %tmp895 + %one.sub.ac.i22 = fmul float %one.sub.a.i21, %temp85.5 + %mul.i23 = fmul float %result.i40, %temp85.5 + %result.i24 = fadd float %mul.i23, %one.sub.ac.i22 + %one.sub.a.i17 = fsub float 1.000000e+00, %tmp895 + %one.sub.ac.i18 = fmul float %one.sub.a.i17, %temp86.5 + %mul.i19 = fmul float %result.i36, %temp86.5 + %result.i20 = fadd float %mul.i19, %one.sub.ac.i18 + %one.sub.a.i13 = fsub float 1.000000e+00, %tmp895 + %one.sub.ac.i14 = fmul float %one.sub.a.i13, %temp87.5 + %mul.i15 = fmul float %result.i32, %temp87.5 + %result.i16 = fadd float %mul.i15, %one.sub.ac.i14 + %tmp896 = insertelement <4 x float> undef, float %tmp333, i32 0 + %tmp897 = insertelement <4 x float> %tmp896, float %tmp334, i32 1 + %tmp898 = insertelement <4 x float> %tmp897, float %tmp335, i32 2 + %tmp899 = insertelement <4 x float> %tmp898, float 0.000000e+00, i32 3 + %tmp900 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp901 = insertelement <4 x float> %tmp900, float %tmp65, i32 1 + %tmp902 = insertelement <4 x float> %tmp901, float %tmp67, i32 2 + %tmp903 = insertelement <4 x float> %tmp902, float 0.000000e+00, i32 3 + %tmp904 = call float @llvm.r600.dot4(<4 x float> %tmp899, <4 x float> %tmp903) + %tmp905 = fcmp uge float 0x3FE99999A0000000, %tmp904 + %tmp906 = select i1 %tmp905, float 0x3FE99999A0000000, float %tmp904 + %tmp907 = fmul float %tmp8, %tmp906 + %tmp908 = fmul float %tmp13, %tmp906 + %tmp909 = fmul float %tmp18, %tmp906 + %tmp910 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp911 = insertelement <4 x float> %tmp910, float %tmp35, i32 1 + %tmp912 = insertelement <4 x float> %tmp911, float %tmp36, i32 2 + %tmp913 = insertelement <4 x float> %tmp912, float 0.000000e+00, i32 3 + %tmp914 = insertelement <4 x float> undef, float %tmp63, i32 0 + %tmp915 = insertelement <4 x float> %tmp914, float %tmp65, i32 1 + %tmp916 = insertelement <4 x float> %tmp915, float %tmp67, i32 2 + %tmp917 = insertelement <4 x float> %tmp916, float 0.000000e+00, i32 3 + %tmp918 = call float @llvm.r600.dot4(<4 x float> %tmp913, <4 x float> %tmp917) + %tmp919 = fcmp uge float 0x3FECCCCCC0000000, %tmp918 + %tmp920 = select i1 %tmp919, float 0x3FECCCCCC0000000, float %tmp918 + %tmp921 = fmul float %tmp907, %tmp920 + %tmp922 = fmul float %tmp908, %tmp920 + %tmp923 = fmul float %tmp909, %tmp920 br label %ENDIF178 -ENDIF178: ; preds = %ENDIF175, %IF179 - %temp84.6 = phi float [ %921, %IF179 ], [ %temp84.5, %ENDIF175 ] - %temp85.6 = phi float [ %922, %IF179 ], [ %temp85.5, %ENDIF175 ] - %temp86.6 = phi float [ %923, %IF179 ], [ %temp86.5, %ENDIF175 ] - %temp87.6 = phi float [ %924, %IF179 ], [ %temp87.5, %ENDIF175 ] - %temp92.12 = phi float [ %950, %IF179 ], [ %temp92.11, %ENDIF175 ] - %temp93.6 = phi float [ %951, %IF179 ], [ %temp93.5, %ENDIF175 ] - %temp94.6 = phi float [ %952, %IF179 ], [ %temp94.5, %ENDIF175 ] - %953 = fmul float %55, %temp92.12 - %954 = fmul float %57, %temp93.6 - %955 = fmul float %59, %temp94.6 - %956 = fmul float %61, 0.000000e+00 - %957 = fmul float %temp84.6, %953 - %958 = fmul float %temp85.6, %954 - %959 = fmul float %temp86.6, %955 - %960 = fmul float %temp87.6, %956 - %961 = fmul float %2, -2.000000e+00 - %962 = fadd float %961, 1.000000e+00 - %963 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) - %964 = extractelement <4 x float> %963, i32 2 - %965 = fsub float -0.000000e+00, %964 - %966 = fadd float %962, %965 - %967 = fdiv float 1.000000e+00, %966 - %968 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) - %969 = extractelement <4 x float> %968, i32 2 - %970 = fmul float %969, %967 - %971 = fsub float -0.000000e+00, %53 - %972 = fmul float %971, %53 - %973 = fmul float %972, %970 - %974 = fmul float %973, %970 - %975 = fmul float %974, 0x3FF7154760000000 - %976 = call float @llvm.AMDIL.exp.(float %975) - %977 = fcmp oeq float %53, 1.000000e+00 - %978 = sext i1 %977 to i32 - %979 = bitcast i32 %978 to float - %980 = bitcast float %979 to i32 - %981 = icmp ne i32 %980, 0 - %.184 = select i1 %981, float 1.000000e+00, float %976 - %982 = call float @llvm.AMDGPU.lrp(float %.184, float %957, float %47) - %983 = call float @llvm.AMDGPU.lrp(float %.184, float %958, float %49) - %984 = call float @llvm.AMDGPU.lrp(float %.184, float %959, float %51) - %985 = insertelement <4 x float> undef, float %982, i32 0 - %986 = insertelement <4 x float> %985, float %983, i32 1 - %987 = insertelement <4 x float> %986, float %984, i32 2 - %988 = insertelement <4 x float> %987, float %960, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %988, i32 0, i32 0) +ENDIF178: ; preds = %IF179, %ENDIF175 + %temp84.6 = phi float [ %result.i28, %IF179 ], [ %temp84.5, %ENDIF175 ] + %temp85.6 = phi float [ %result.i24, %IF179 ], [ %temp85.5, %ENDIF175 ] + %temp86.6 = phi float [ %result.i20, %IF179 ], [ %temp86.5, %ENDIF175 ] + %temp87.6 = phi float [ %result.i16, %IF179 ], [ %temp87.5, %ENDIF175 ] + %temp92.12 = phi float [ %tmp921, %IF179 ], [ %temp92.11, %ENDIF175 ] + %temp93.6 = phi float [ %tmp922, %IF179 ], [ %temp93.5, %ENDIF175 ] + %temp94.6 = phi float [ %tmp923, %IF179 ], [ %temp94.5, %ENDIF175 ] + %tmp924 = fmul float %tmp55, %temp92.12 + %tmp925 = fmul float %tmp57, %temp93.6 + %tmp926 = fmul float %tmp59, %temp94.6 + %tmp927 = fmul float %tmp61, 0.000000e+00 + %tmp928 = fmul float %temp84.6, %tmp924 + %tmp929 = fmul float %temp85.6, %tmp925 + %tmp930 = fmul float %temp86.6, %tmp926 + %tmp931 = fmul float %temp87.6, %tmp927 + %tmp932 = fmul float %tmp2, -2.000000e+00 + %tmp933 = fadd float %tmp932, 1.000000e+00 + %tmp934 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 23) + %tmp935 = extractelement <4 x float> %tmp934, i32 2 + %tmp936 = fsub float -0.000000e+00, %tmp935 + %tmp937 = fadd float %tmp933, %tmp936 + %tmp938 = fdiv float 1.000000e+00, %tmp937 + %tmp939 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 24) + %tmp940 = extractelement <4 x float> %tmp939, i32 2 + %tmp941 = fmul float %tmp940, %tmp938 + %tmp942 = fsub float -0.000000e+00, %tmp53 + %tmp943 = fmul float %tmp942, %tmp53 + %tmp944 = fmul float %tmp943, %tmp941 + %tmp945 = fmul float %tmp944, %tmp941 + %tmp946 = fmul float %tmp945, 0x3FF7154760000000 + %tmp947 = call float @llvm.exp2.f32(float %tmp946) + %tmp948 = fcmp oeq float %tmp53, 1.000000e+00 + %tmp949 = sext i1 %tmp948 to i32 + %tmp950 = bitcast i32 %tmp949 to float + %tmp951 = bitcast float %tmp950 to i32 + %tmp952 = icmp ne i32 %tmp951, 0 + %.184 = select i1 %tmp952, float 1.000000e+00, float %tmp947 + %one.sub.a.i9 = fsub float 1.000000e+00, %.184 + %one.sub.ac.i10 = fmul float %one.sub.a.i9, %tmp47 + %mul.i11 = fmul float %tmp928, %tmp47 + %result.i12 = fadd float %mul.i11, %one.sub.ac.i10 + %one.sub.a.i5 = fsub float 1.000000e+00, %.184 + %one.sub.ac.i6 = fmul float %one.sub.a.i5, %tmp49 + %mul.i7 = fmul float %tmp929, %tmp49 + %result.i8 = fadd float %mul.i7, %one.sub.ac.i6 + %one.sub.a.i1 = fsub float 1.000000e+00, %.184 + %one.sub.ac.i2 = fmul float %one.sub.a.i1, %tmp51 + %mul.i3 = fmul float %tmp930, %tmp51 + %result.i4 = fadd float %mul.i3, %one.sub.ac.i2 + %tmp953 = insertelement <4 x float> undef, float %result.i12, i32 0 + %tmp954 = insertelement <4 x float> %tmp953, float %result.i8, i32 1 + %tmp955 = insertelement <4 x float> %tmp954, float %result.i4, i32 2 + %tmp956 = insertelement <4 x float> %tmp955, float %tmp931, i32 3 + call void @llvm.r600.store.swizzle(<4 x float> %tmp956, i32 0, i32 0) ret void } -; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +; Function Attrs: nounwind readnone +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #0 -; Function Attrs: readnone -declare float @llvm.AMDGPU.rsq.f32(float) #1 +; Function Attrs: nounwind readnone +declare float @llvm.r600.recipsqrt.clamped.f32(float) #0 -; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 +; Function Attrs: nounwind readonly +declare float @llvm.fabs.f32(float) #1 -; Function Attrs: readonly -declare float @fabs(float) #2 +; Function Attrs: nounwind readnone +declare float @llvm.exp2.f32(float) #0 -; Function Attrs: readnone -declare float @llvm.AMDIL.exp.(float) #1 +; Function Attrs: nounwind readnone +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0 -; Function Attrs: readnone -declare float @llvm.AMDGPU.lrp(float, float, float) #1 +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -; Function Attrs: readnone -declare float @llvm.AMDIL.clamp.(float, float, float) #1 +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } -attributes #1 = { readnone } -attributes #2 = { readonly } +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/bitcast.ll b/test/CodeGen/AMDGPU/bitcast.ll index fd56d956bf31..87ef5978ebfc 100644 --- a/test/CodeGen/AMDGPU/bitcast.ll +++ b/test/CodeGen/AMDGPU/bitcast.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; This test just checks that the compiler doesn't crash. @@ -7,7 +7,7 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float ; FUNC-LABEL: {{^}}v32i8_to_v8i32: ; SI: s_endpgm -define void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { +define amdgpu_ps void @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { entry: %1 = load <32 x i8>, <32 x i8> addrspace(2)* %0 %2 = bitcast <32 x i8> %1 to <8 x i32> @@ -76,4 +76,34 @@ define void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace ret void } -attributes #0 = { "ShaderType"="0" } +; FUNC-LABEL: {{^}}bitcast_v2i64_to_v2f64: +define void @bitcast_v2i64_to_v2f64(i32 %cond, <2 x double> addrspace(1)* %out, <2 x i64> %value) { +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x i64> %value to <2 x double> + br label %end + +end: + %phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if] + store <2 x double> %phi, <2 x double> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}bitcast_v2f64_to_v2i64: +define void @bitcast_v2f64_to_v2i64(i32 %cond, <2 x i64> addrspace(1)* %out, <2 x double> %value) { +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %end + +if: + %cast = bitcast <2 x double> %value to <2 x i64> + br label %end + +end: + %phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if] + store <2 x i64> %phi, <2 x i64> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll b/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll new file mode 100644 index 000000000000..150e3430a5e9 --- /dev/null +++ b/test/CodeGen/AMDGPU/bitreverse-inline-immediates.ll @@ -0,0 +1,158 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Test that materialization constants that are the bit reversed of +; inline immediates are replaced with bfrev of the inline immediate to +; save code size. + +; GCN-LABEL: {{^}}materialize_0_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_0_i32(i32 addrspace(1)* %out) { + store i32 0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_0_i64: +; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_0_i64(i64 addrspace(1)* %out) { + store i64 0, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_neg1_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -1{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_neg1_i32(i32 addrspace(1)* %out) { + store i32 -1, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_neg1_i64: +; GCN: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} +; GCN: v_mov_b32_e32 v[[HIK:[0-9]+]], v[[LOK]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_neg1_i64(i64 addrspace(1)* %out) { + store i64 -1, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_signbit_i32: +; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_signbit_i32(i32 addrspace(1)* %out) { + store i32 -2147483648, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_signbit_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} +; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 1{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_signbit_i64(i64 addrspace(1)* %out) { + store i64 -9223372036854775808, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_neg16_i32: +; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], -16{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_neg16_i32(i32 addrspace(1)* %out) { + store i32 268435455, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_neg16_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} +; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], -16{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_neg16_i64(i64 addrspace(1)* %out) { + store i64 1152921504606846975, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_neg17_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0xf7ffffff{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_neg17_i32(i32 addrspace(1)* %out) { + store i32 -134217729, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_neg17_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], -1{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0xf7ffffff{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_neg17_i64(i64 addrspace(1)* %out) { + store i64 -576460752303423489, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_64_i32: +; GCN: v_bfrev_b32_e32 [[K:v[0-9]+]], 64{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_64_i32(i32 addrspace(1)* %out) { + store i32 33554432, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_64_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} +; GCN-DAG: v_bfrev_b32_e32 v[[HIK:[0-9]+]], 64{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_64_i64(i64 addrspace(1)* %out) { + store i64 144115188075855872, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_65_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x82000000{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_65_i32(i32 addrspace(1)* %out) { + store i32 -2113929216, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_65_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0x82000000{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_65_i64(i64 addrspace(1)* %out) { + store i64 -9079256848778919936, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_3_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], -2.0{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_3_i32(i32 addrspace(1)* %out) { + store i32 -1073741824, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_3_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], -2.0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_3_i64(i64 addrspace(1)* %out) { + store i64 -4611686018427387904, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_1.0_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1fc{{$}} +; GCN: buffer_store_dword [[K]] +define void @materialize_rev_1.0_i32(i32 addrspace(1)* %out) { + store i32 508, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}materialize_rev_1.0_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOK:[0-9]+]], 0x1fc{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HIK:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LOK]]:[[HIK]]{{\]}} +define void @materialize_rev_1.0_i64(i64 addrspace(1)* %out) { + store i64 508, i64 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/bitreverse.ll b/test/CodeGen/AMDGPU/bitreverse.ll index 0ef7d5184c1f..62e7904f4382 100644 --- a/test/CodeGen/AMDGPU/bitreverse.ll +++ b/test/CodeGen/AMDGPU/bitreverse.ll @@ -11,8 +11,6 @@ declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) #1 declare <2 x i64> @llvm.bitreverse.v2i64(<2 x i64>) #1 declare <4 x i64> @llvm.bitreverse.v4i64(<4 x i64>) #1 -declare i32 @llvm.AMDGPU.brev(i32) #1 - ; FUNC-LABEL: {{^}}s_brev_i16: ; SI: s_brev_b32 define void @s_brev_i16(i16 addrspace(1)* noalias %out, i16 %val) #0 { @@ -103,13 +101,5 @@ define void @v_brev_v2i64(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrsp ret void } -; FUNC-LABEL: {{^}}legacy_s_brev_i32: -; SI: s_brev_b32 -define void @legacy_s_brev_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind { - %brev = call i32 @llvm.AMDGPU.brev(i32 %val) #1 - store i32 %brev, i32 addrspace(1)* %out - ret void -} - attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/branch-uniformity.ll b/test/CodeGen/AMDGPU/branch-uniformity.ll new file mode 100644 index 000000000000..d1a1f93f0210 --- /dev/null +++ b/test/CodeGen/AMDGPU/branch-uniformity.ll @@ -0,0 +1,41 @@ +; RUN: llc -mtriple=amdgcn-- < %s | FileCheck %s + +; The branch instruction in LOOP49 has a uniform condition, but PHI instructions +; introduced by the structurizecfg pass previously caused a false divergence +; which ended up in an assertion (or incorrect code) because +; SIAnnotateControlFlow and structurizecfg had different ideas about which +; branches are uniform. +; +; CHECK-LABEL: {{^}}main: +; CHECK: ; %LOOP49 +; CHECK: v_cmp_ne_i32_e32 vcc, +; CHECK: s_cbranch_vccnz +; CHECK: ; %ENDIF53 +define amdgpu_vs float @main(i32 %in) { +main_body: + %cmp = mul i32 %in, 2 + br label %LOOP + +LOOP: ; preds = %ENDLOOP48, %main_body + %counter = phi i32 [ 0, %main_body ], [ %counter.next, %ENDLOOP48 ] + %v.LOOP = phi i32 [ 0, %main_body ], [ %v.ENDLOOP48, %ENDLOOP48 ] + %tmp7 = icmp slt i32 %cmp, %counter + br i1 %tmp7, label %IF, label %LOOP49 + +IF: ; preds = %LOOP + %r = bitcast i32 %v.LOOP to float + ret float %r + +LOOP49: ; preds = %LOOP + %tmp8 = icmp ne i32 %counter, 0 + br i1 %tmp8, label %ENDLOOP48, label %ENDIF53 + +ENDLOOP48: ; preds = %ENDIF53, %LOOP49 + %v.ENDLOOP48 = phi i32 [ %v.LOOP, %LOOP49 ], [ %v.ENDIF53, %ENDIF53 ] + %counter.next = add i32 %counter, 1 + br label %LOOP + +ENDIF53: ; preds = %LOOP49 + %v.ENDIF53 = add i32 %v.LOOP, %counter + br label %ENDLOOP48 +} diff --git a/test/CodeGen/AMDGPU/bug-vopc-commute.ll b/test/CodeGen/AMDGPU/bug-vopc-commute.ll new file mode 100644 index 000000000000..990671102757 --- /dev/null +++ b/test/CodeGen/AMDGPU/bug-vopc-commute.ll @@ -0,0 +1,49 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s + +target triple = "amdgcn--" + +; CHECK-LABEL: {{^}}main: +; +; Test for compilation only. This generated an invalid machine instruction +; by trying to commute the operands of a V_CMP_EQ_i32_e32 instruction, both +; of which were in SGPRs. +define amdgpu_vs float @main(i32 %v) { +main_body: + %d1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 960) + %d2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 976) + br i1 undef, label %ENDIF56, label %IF57 + +IF57: ; preds = %ENDIF + %v.1 = mul i32 %v, 2 + br label %ENDIF56 + +ENDIF56: ; preds = %IF57, %ENDIF + %v.2 = phi i32 [ %v, %main_body ], [ %v.1, %IF57 ] + %d1.i = bitcast float %d1 to i32 + %cc1 = icmp eq i32 %d1.i, 0 + br i1 %cc1, label %ENDIF59, label %IF60 + +IF60: ; preds = %ENDIF56 + %v.3 = mul i32 %v.2, 2 + br label %ENDIF59 + +ENDIF59: ; preds = %IF60, %ENDIF56 + %v.4 = phi i32 [ %v.2, %ENDIF56 ], [ %v.3, %IF60 ] + %d2.i = bitcast float %d2 to i32 + %cc2 = icmp eq i32 %d2.i, 0 + br i1 %cc2, label %ENDIF62, label %IF63 + +IF63: ; preds = %ENDIF59 + unreachable + +ENDIF62: ; preds = %ENDIF59 + %r = bitcast i32 %v.4 to float + ret float %r +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/call.ll b/test/CodeGen/AMDGPU/call.ll index e769fd11c282..a3e986d367e1 100644 --- a/test/CodeGen/AMDGPU/call.ll +++ b/test/CodeGen/AMDGPU/call.ll @@ -1,8 +1,10 @@ -; RUN: not llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s +; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -march=r600 -mcpu=cypress < %s 2>&1 | FileCheck %s -; CHECK: error: unsupported call to function external_function in test_call_external +; CHECK: in function test_call_external{{.*}}: unsupported call to function external_function +; CHECK: in function test_call{{.*}}: unsupported call to function defined_function +; CHECK: in function test_tail_call{{.*}}: unsupported call to function defined_function declare i32 @external_function(i32) nounwind @@ -31,3 +33,13 @@ define void @test_call(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { store i32 %result, i32 addrspace(1)* %out ret void } + +define void @test_tail_call(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %a = load i32, i32 addrspace(1)* %in + %b = load i32, i32 addrspace(1)* %b_ptr + %c = tail call i32 @defined_function(i32 %b) nounwind + %result = add i32 %a, %c + store i32 %result, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/call_fs.ll b/test/CodeGen/AMDGPU/call_fs.ll index 87bebbc49d52..a5a2d28ff716 100644 --- a/test/CodeGen/AMDGPU/call_fs.ll +++ b/test/CodeGen/AMDGPU/call_fs.ll @@ -10,8 +10,6 @@ ; R600:CALL_FS ; encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x89] -define void @call_fs() #0 { +define amdgpu_vs void @call_fs() { ret void } - -attributes #0 = { "ShaderType"="1" } ; Vertex Shader diff --git a/test/CodeGen/AMDGPU/captured-frame-index.ll b/test/CodeGen/AMDGPU/captured-frame-index.ll new file mode 100644 index 000000000000..161c46b486eb --- /dev/null +++ b/test/CodeGen/AMDGPU/captured-frame-index.ll @@ -0,0 +1,166 @@ +; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}stored_fi_to_lds: +; GCN: s_load_dword [[LDSPTR:s[0-9]+]] +; GCN: v_mov_b32_e32 [[ZERO1:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO1]] +; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] +; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]] +define void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { + %tmp = alloca float + store float 4.0, float *%tmp + store float* %tmp, float* addrspace(3)* %ptr + ret void +} + +; Offset is applied +; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects: +; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:4{{$}} + +; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]] + +; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] +; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO]] + +; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}} +; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]] +define void @stored_fi_to_lds_2_small_objects(float* addrspace(3)* %ptr) #0 { + %tmp0 = alloca float + %tmp1 = alloca float + store float 4.0, float* %tmp0 + store float 4.0, float* %tmp1 + store volatile float* %tmp0, float* addrspace(3)* %ptr + store volatile float* %tmp1, float* addrspace(3)* %ptr + ret void +} + +; Same frame index is used multiple times in the store +; GCN-LABEL: {{^}}stored_fi_to_self: +; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}} +; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[K]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +; GCN: buffer_store_dword [[ZERO]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +define void @stored_fi_to_self() #0 { + %tmp = alloca i32* + + ; Avoid optimizing everything out + store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp + %bitcast = bitcast i32** %tmp to i32* + store volatile i32* %bitcast, i32** %tmp + ret void +} + +; GCN-LABEL: {{^}}stored_fi_to_self_offset: +; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}} +; GCN: buffer_store_dword [[K0]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x4d2{{$}} +; GCN: buffer_store_dword [[K1]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:2048{{$}} + +; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x800{{$}} +; GCN: buffer_store_dword [[OFFSETK]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:2048{{$}} +define void @stored_fi_to_self_offset() #0 { + %tmp0 = alloca [512 x i32] + %tmp1 = alloca i32* + + ; Avoid optimizing everything out + %tmp0.cast = bitcast [512 x i32]* %tmp0 to i32* + store volatile i32 32, i32* %tmp0.cast + + store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp1 + + %bitcast = bitcast i32** %tmp1 to i32* + store volatile i32* %bitcast, i32** %tmp1 + ret void +} + +; GCN-LABEL: {{^}}stored_fi_to_fi: +; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:4{{$}} +; GCN: buffer_store_dword v{{[0-9]+}}, [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:8{{$}} + +; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}} +; GCN: buffer_store_dword [[FI1]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:8{{$}} + +; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 8{{$}} +; GCN: buffer_store_dword [[FI2]], [[ZERO]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:4{{$}} +define void @stored_fi_to_fi() #0 { + %tmp0 = alloca i32* + %tmp1 = alloca i32* + %tmp2 = alloca i32* + store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp0 + store volatile i32* inttoptr (i32 5678 to i32*), i32** %tmp1 + store volatile i32* inttoptr (i32 9999 to i32*), i32** %tmp2 + + %bitcast1 = bitcast i32** %tmp1 to i32* + %bitcast2 = bitcast i32** %tmp2 to i32* ; at offset 8 + + store volatile i32* %bitcast1, i32** %tmp2 ; store offset 4 at offset 8 + store volatile i32* %bitcast2, i32** %tmp1 ; store offset 8 at offset 4 + ret void +} + +; GCN-LABEL: {{^}}stored_fi_to_global: +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen +; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[FI]] +define void @stored_fi_to_global(float* addrspace(1)* %ptr) #0 { + %tmp = alloca float + store float 0.0, float *%tmp + store float* %tmp, float* addrspace(1)* %ptr + ret void +} + +; Offset is applied +; GCN-LABEL: {{^}}stored_fi_to_global_2_small_objects: +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen + +; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 4{{$}} +; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} + +; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 8{{$}} +; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @stored_fi_to_global_2_small_objects(float* addrspace(1)* %ptr) #0 { + %tmp0 = alloca float + %tmp1 = alloca float + %tmp2 = alloca float + store volatile float 0.0, float *%tmp0 + store volatile float 0.0, float *%tmp1 + store volatile float 0.0, float *%tmp2 + store volatile float* %tmp1, float* addrspace(1)* %ptr + store volatile float* %tmp2, float* addrspace(1)* %ptr + ret void +} + +; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset: +; GCN: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc +; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[BASE_0]], v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen + +; GCN: v_mov_b32_e32 [[V_BASE_1_OFF_0:v[0-9]+]], [[BASE_1_OFF_0]] +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}} +; GCN: s_add_i32 [[BASE_1_OFF_1:s[0-9]+]], 0, 56 +; GCN: buffer_store_dword [[K]], [[V_BASE_1_OFF_0]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: v_mov_b32_e32 [[V_BASE_1_OFF_1:v[0-9]+]], [[BASE_1_OFF_1]] +; GCN: buffer_store_dword [[V_BASE_1_OFF_1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @stored_fi_to_global_huge_frame_offset(i32* addrspace(1)* %ptr) #0 { + %tmp0 = alloca [4096 x i32] + %tmp1 = alloca [4096 x i32] + %gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 0 + store volatile i32 0, i32* %gep0.tmp0 + %gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 4095 + store volatile i32 999, i32* %gep1.tmp0 + %gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 14 + store i32* %gep0.tmp1, i32* addrspace(1)* %ptr + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/cayman-loop-bug.ll b/test/CodeGen/AMDGPU/cayman-loop-bug.ll index c7b8c4037316..34e6669434f1 100644 --- a/test/CodeGen/AMDGPU/cayman-loop-bug.ll +++ b/test/CodeGen/AMDGPU/cayman-loop-bug.ll @@ -8,25 +8,29 @@ ; CHECK-NOT: ALU_PUSH_BEFORE ; CHECK: END_LOOP ; CHECK: END_LOOP -define void @main (<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @main (<4 x float> inreg %reg0) { entry: br label %outer_loop + outer_loop: %cnt = phi i32 [0, %entry], [%cnt_incr, %inner_loop] %cond = icmp eq i32 %cnt, 16 br i1 %cond, label %outer_loop_body, label %exit + outer_loop_body: %cnt_incr = add i32 %cnt, 1 br label %inner_loop + inner_loop: %cnt2 = phi i32 [0, %outer_loop_body], [%cnt2_incr, %inner_loop_body] - %cond2 = icmp eq i32 %cnt2, 16 - br i1 %cond, label %inner_loop_body, label %outer_loop + %n = load volatile i32, i32 addrspace(1)* undef + %cond2 = icmp slt i32 %cnt2, %n + br i1 %cond2, label %inner_loop_body, label %outer_loop + inner_loop_body: %cnt2_incr = add i32 %cnt2, 1 br label %inner_loop + exit: ret void } - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file diff --git a/test/CodeGen/AMDGPU/cf-loop-on-constant.ll b/test/CodeGen/AMDGPU/cf-loop-on-constant.ll new file mode 100644 index 000000000000..759c48b3a9cf --- /dev/null +++ b/test/CodeGen/AMDGPU/cf-loop-on-constant.ll @@ -0,0 +1,121 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s + +; GCN-LABEL: {{^}}test_loop: +; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: +; GCN: ds_read_b32 +; GCN: ds_write_b32 +; GCN: s_branch [[LABEL]] +; GCN: s_endpgm +define void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind { +entry: + %cmp = icmp eq i32 %n, -1 + br i1 %cmp, label %for.exit, label %for.body + +for.exit: + ret void + +for.body: + %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %tmp = add i32 %indvar, 32 + %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp + %vecload = load float, float addrspace(3)* %arrayidx, align 4 + %add = fadd float %vecload, 1.0 + store float %add, float addrspace(3)* %arrayidx, align 8 + %inc = add i32 %indvar, 1 + br label %for.body +} + +; GCN-LABEL: @loop_const_true +; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: +; GCN: ds_read_b32 +; GCN: ds_write_b32 +; GCN: s_branch [[LABEL]] +define void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind { +entry: + br label %for.body + +for.exit: + ret void + +for.body: + %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %tmp = add i32 %indvar, 32 + %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp + %vecload = load float, float addrspace(3)* %arrayidx, align 4 + %add = fadd float %vecload, 1.0 + store float %add, float addrspace(3)* %arrayidx, align 8 + %inc = add i32 %indvar, 1 + br i1 true, label %for.body, label %for.exit +} + +; GCN-LABEL: {{^}}loop_const_false: +; GCN-NOT: s_branch +; GCN: s_endpgm +define void @loop_const_false(float addrspace(3)* %ptr, i32 %n) nounwind { +entry: + br label %for.body + +for.exit: + ret void + +; XXX - Should there be an S_ENDPGM? +for.body: + %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %tmp = add i32 %indvar, 32 + %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp + %vecload = load float, float addrspace(3)* %arrayidx, align 4 + %add = fadd float %vecload, 1.0 + store float %add, float addrspace(3)* %arrayidx, align 8 + %inc = add i32 %indvar, 1 + br i1 false, label %for.body, label %for.exit +} + +; GCN-LABEL: {{^}}loop_const_undef: +; GCN-NOT: s_branch +; GCN: s_endpgm +define void @loop_const_undef(float addrspace(3)* %ptr, i32 %n) nounwind { +entry: + br label %for.body + +for.exit: + ret void + +; XXX - Should there be an s_endpgm? +for.body: + %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %tmp = add i32 %indvar, 32 + %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp + %vecload = load float, float addrspace(3)* %arrayidx, align 4 + %add = fadd float %vecload, 1.0 + store float %add, float addrspace(3)* %arrayidx, align 8 + %inc = add i32 %indvar, 1 + br i1 undef, label %for.body, label %for.exit +} + +; GCN-LABEL: {{^}}loop_arg_0: +; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} +; GCN: v_cmp_eq_i32_e32 vcc, 1, + +; GCN: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, exec, vcc +; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]] +; GCN: s_cbranch_vccnz [[LOOPBB]] +; GCN-NEXT: ; BB#2 +; GCN-NEXT: s_endpgm +define void @loop_arg_0(float addrspace(3)* %ptr, i32 %n, i1 %cond) nounwind { +entry: + br label %for.body + +for.exit: + ret void + +for.body: + %indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ] + %tmp = add i32 %indvar, 32 + %arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp + %vecload = load float, float addrspace(3)* %arrayidx, align 4 + %add = fadd float %vecload, 1.0 + store float %add, float addrspace(3)* %arrayidx, align 8 + %inc = add i32 %indvar, 1 + br i1 %cond, label %for.body, label %for.exit +} diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll index 1c5bed3b905f..82f88a079307 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll @@ -42,7 +42,7 @@ done: ; OPT: br label ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32: -; CI: buffer_load_dword {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 +; CI: buffer_load_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 define void @test_sink_noop_addrspacecast_flat_to_global_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { entry: %out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 diff --git a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll index 698494265a7d..916d667ec492 100644 --- a/test/CodeGen/AMDGPU/cgp-addressing-modes.ll +++ b/test/CodeGen/AMDGPU/cgp-addressing-modes.ll @@ -1,11 +1,9 @@ ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI %s -; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s - -declare i32 @llvm.r600.read.tidig.x() #0 +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; OPT-LABEL: @test_sink_global_small_offset_i32( ; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in @@ -15,11 +13,12 @@ declare i32 @llvm.r600.read.tidig.x() #0 ; GCN-LABEL: {{^}}test_sink_global_small_offset_i32: ; GCN: {{^}}BB0_2: -define void @test_sink_global_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond) { +define void @test_sink_global_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 7 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -41,14 +40,15 @@ done: ; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset: ; GCN: s_and_saveexec_b64 -; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} +; GCN: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; GCN: {{^}}BB1_2: ; GCN: s_or_b64 exec -define void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) { +define void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -67,14 +67,15 @@ done: ; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset: ; GCN: s_and_saveexec_b64 -; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}} +; GCN: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}} ; GCN: {{^}}BB2_2: ; GCN: s_or_b64 exec -define void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) { +define void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -93,14 +94,15 @@ done: ; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset: ; GCN: s_and_saveexec_b64 -; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} +; GCN: buffer_load_sbyte {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; GCN: {{^}}BB3_2: ; GCN: s_or_b64 exec -define void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) { +define void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999 %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -127,14 +129,15 @@ done: ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}} ; GCN: {{^}}BB4_2: -define void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) { +define void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { entry: %alloca = alloca [512 x i32], align 4 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %add.arg = add i32 %arg, 8 %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1023 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -163,14 +166,15 @@ done: ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; GCN: {{^}}BB5_2: -define void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) { +define void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { entry: %alloca = alloca [512 x i32], align 4 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %add.arg = add i32 %arg, 8 %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -190,18 +194,17 @@ done: } ; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32: -; VI-DAG: s_movk_i32 flat_scratch_lo, 0x0 -; VI-DAG: s_movk_i32 flat_scratch_hi, 0x0 ; GCN: s_and_saveexec_b64 ; CI: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; VI: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; GCN: {{^}}BB6_2: -define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset, i32 %cond) { +define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset) { entry: %offset.ext = zext i32 %offset to i64 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -230,11 +233,12 @@ attributes #1 = { nounwind } ; GCN: s_and_saveexec_b64 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x7{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 7 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -258,11 +262,12 @@ done: ; GCN: s_and_saveexec_b64 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xff{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_8_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_8_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 255 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -290,11 +295,12 @@ done: ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_8_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_8_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 256 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -321,11 +327,12 @@ done: ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_32_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_32_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 4294967295 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -351,11 +358,12 @@ done: ; GCN: s_addc_u32 ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_32_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_32_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 17179869181 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -380,11 +388,12 @@ done: ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xffffc{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_20_bit_byte_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_20_bit_byte_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 262143 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -417,11 +426,12 @@ done: ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; GCN: s_or_b64 exec, exec -define void @test_sink_constant_max_20_bit_byte_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %cond) { +define void @test_sink_constant_max_20_bit_byte_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { entry: %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 262144 - %tmp0 = icmp eq i32 %cond, 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp0 = icmp eq i32 %tid, 0 br i1 %tmp0, label %endif, label %if if: @@ -436,3 +446,35 @@ endif: done: ret void } + +%struct.foo = type { [3 x float], [3 x float] } + +; OPT-LABEL: @sink_ds_address( +; OPT: ptrtoint %struct.foo addrspace(3)* %ptr to i64 + +; GCN-LABEL: {{^}}sink_ds_address: +; GCN: s_load_dword [[SREG1:s[0-9]+]], +; GCN: v_mov_b32_e32 [[VREG1:v[0-9]+]], [[SREG1]] +; GCN-DAG: ds_read2_b32 v[{{[0-9+:[0-9]+}}], [[VREG1]] offset0:3 offset1:5 +define void @sink_ds_address(%struct.foo addrspace(3)* nocapture %ptr) nounwind { +entry: + %x = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 0 + %y = getelementptr inbounds %struct.foo, %struct.foo addrspace(3)* %ptr, i32 0, i32 1, i32 2 + br label %bb32 + +bb32: + %a = load float, float addrspace(3)* %x, align 4 + %b = load float, float addrspace(3)* %y, align 4 + %cmp = fcmp one float %a, %b + br i1 %cmp, label %bb34, label %bb33 + +bb33: + unreachable + +bb34: + unreachable +} + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll b/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll new file mode 100644 index 000000000000..33daf0292ae1 --- /dev/null +++ b/test/CodeGen/AMDGPU/cgp-bitfield-extract.ll @@ -0,0 +1,301 @@ +; RUN: opt -S -mtriple=amdgcn-- -codegenprepare < %s | FileCheck -check-prefix=OPT %s +; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -codegenprepare < %s | FileCheck -check-prefix=OPT %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +; This particular case will actually be worse in terms of code size +; from sinking into both. + +; OPT-LABEL: @sink_ubfe_i32( +; OPT: entry: +; OPT-NEXT: br i1 + +; OPT: bb0: +; OPT: %0 = lshr i32 %arg1, 8 +; OPT-NEXT: %val0 = and i32 %0, 255 +; OPT: br label + +; OPT: bb1: +; OPT: %1 = lshr i32 %arg1, 8 +; OPT-NEXT: %val1 = and i32 %1, 127 +; OPT: br label + +; OPT: ret: +; OPT: store +; OPT: ret + + +; GCN-LABEL: {{^}}sink_ubfe_i32: +; GCN-NOT: lshr +; GCN: s_cbranch_vccnz + +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80008 +; GCN: BB0_2: +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70008 + +; GCN: BB0_3: +; GCN: buffer_store_dword +; GCN: s_endpgm +define void @sink_ubfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 { +entry: + %shr = lshr i32 %arg1, 8 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i32 %shr, 255 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i32 %shr, 127 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i32 %phi, i32 addrspace(1)* %out + ret void +} + +; OPT-LABEL: @sink_sbfe_i32( +; OPT: entry: +; OPT-NEXT: br i1 + +; OPT: bb0: +; OPT: %0 = ashr i32 %arg1, 8 +; OPT-NEXT: %val0 = and i32 %0, 255 +; OPT: br label + +; OPT: bb1: +; OPT: %1 = ashr i32 %arg1, 8 +; OPT-NEXT: %val1 = and i32 %1, 127 +; OPT: br label + +; OPT: ret: +; OPT: store +; OPT: ret + +; GCN-LABEL: {{^}}sink_sbfe_i32: +define void @sink_sbfe_i32(i32 addrspace(1)* %out, i32 %arg1) #0 { +entry: + %shr = ashr i32 %arg1, 8 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i32 %shr, 255 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i32 %shr, 127 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i32 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i32 %phi, i32 addrspace(1)* %out + ret void +} + + +; OPT-LABEL: @sink_ubfe_i16( +; OPT: entry: +; OPT-NEXT: br i1 + +; OPT: bb0: +; OPT: %0 = lshr i16 %arg1, 4 +; OPT-NEXT: %val0 = and i16 %0, 255 +; OPT: br label + +; OPT: bb1: +; OPT: %1 = lshr i16 %arg1, 4 +; OPT-NEXT: %val1 = and i16 %1, 127 +; OPT: br label + +; OPT: ret: +; OPT: store +; OPT: ret + + +; GCN-LABEL: {{^}}sink_ubfe_i16: +; GCN-NOT: lshr +; GCN: s_cbranch_vccnz + +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80004 +; GCN: BB2_2: +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70004 + +; GCN: BB2_3: +; GCN: buffer_store_short +; GCN: s_endpgm +define void @sink_ubfe_i16(i16 addrspace(1)* %out, i16 %arg1) #0 { +entry: + %shr = lshr i16 %arg1, 4 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i16 %shr, 255 + store volatile i16 0, i16 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i16 %shr, 127 + store volatile i16 0, i16 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i16 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i16 %phi, i16 addrspace(1)* %out + ret void +} + +; We don't really want to sink this one since it isn't reducible to a +; 32-bit BFE on one half of the integer. + +; OPT-LABEL: @sink_ubfe_i64_span_midpoint( +; OPT: entry: +; OPT-NOT: lshr +; OPT: br i1 + +; OPT: bb0: +; OPT: %0 = lshr i64 %arg1, 30 +; OPT-NEXT: %val0 = and i64 %0, 255 + +; OPT: bb1: +; OPT: %1 = lshr i64 %arg1, 30 +; OPT-NEXT: %val1 = and i64 %1, 127 + +; OPT: ret: +; OPT: store +; OPT: ret + +; GCN-LABEL: {{^}}sink_ubfe_i64_span_midpoint: +; GCN: s_cbranch_vccnz BB3_2 + +; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30 +; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0xff + +; GCN: BB3_2: +; GCN: s_lshr_b64 s{{\[}}[[LO:[0-9]+]]:{{[0-9]+}}], s{{\[[0-9]+:[0-9]+\]}}, 30 +; GCN: s_and_b32 s{{[0-9]+}}, s[[LO]], 0x7f + +; GCN: BB3_3: +; GCN: buffer_store_dwordx2 +define void @sink_ubfe_i64_span_midpoint(i64 addrspace(1)* %out, i64 %arg1) #0 { +entry: + %shr = lshr i64 %arg1, 30 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i64 %shr, 255 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i64 %shr, 127 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i64 %phi, i64 addrspace(1)* %out + ret void +} + +; OPT-LABEL: @sink_ubfe_i64_low32( +; OPT: entry: +; OPT-NOT: lshr +; OPT: br i1 + +; OPT: bb0: +; OPT: %0 = lshr i64 %arg1, 15 +; OPT-NEXT: %val0 = and i64 %0, 255 + +; OPT: bb1: +; OPT: %1 = lshr i64 %arg1, 15 +; OPT-NEXT: %val1 = and i64 %1, 127 + +; OPT: ret: +; OPT: store +; OPT: ret + +; GCN-LABEL: {{^}}sink_ubfe_i64_low32: + +; GCN: s_cbranch_vccnz BB4_2 + +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x8000f + +; GCN: BB4_2: +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x7000f + +; GCN: BB4_3: +; GCN: buffer_store_dwordx2 +define void @sink_ubfe_i64_low32(i64 addrspace(1)* %out, i64 %arg1) #0 { +entry: + %shr = lshr i64 %arg1, 15 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i64 %shr, 255 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i64 %shr, 127 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i64 %phi, i64 addrspace(1)* %out + ret void +} + +; OPT-LABEL: @sink_ubfe_i64_high32( +; OPT: entry: +; OPT-NOT: lshr +; OPT: br i1 + +; OPT: bb0: +; OPT: %0 = lshr i64 %arg1, 35 +; OPT-NEXT: %val0 = and i64 %0, 255 + +; OPT: bb1: +; OPT: %1 = lshr i64 %arg1, 35 +; OPT-NEXT: %val1 = and i64 %1, 127 + +; OPT: ret: +; OPT: store +; OPT: ret + +; GCN-LABEL: {{^}}sink_ubfe_i64_high32: +; GCN: s_cbranch_vccnz BB5_2 +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80003 + +; GCN: BB5_2: +; GCN: s_bfe_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x70003 + +; GCN: BB5_3: +; GCN: buffer_store_dwordx2 +define void @sink_ubfe_i64_high32(i64 addrspace(1)* %out, i64 %arg1) #0 { +entry: + %shr = lshr i64 %arg1, 35 + br i1 undef, label %bb0, label %bb1 + +bb0: + %val0 = and i64 %shr, 255 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +bb1: + %val1 = and i64 %shr, 127 + store volatile i32 0, i32 addrspace(1)* undef + br label %ret + +ret: + %phi = phi i64 [ %val0, %bb0 ], [ %val1, %bb1 ] + store i64 %phi, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/ci-use-flat-for-global.ll b/test/CodeGen/AMDGPU/ci-use-flat-for-global.ll index 1a37e3c75fa3..8227d4c873ee 100644 --- a/test/CodeGen/AMDGPU/ci-use-flat-for-global.ll +++ b/test/CodeGen/AMDGPU/ci-use-flat-for-global.ll @@ -1,11 +1,22 @@ -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck -check-prefix=HSA-DEFAULT %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck -check-prefix=HSA-NODEFAULT %s -; RUN: llc < %s -mtriple=amdgcn -mcpu=kaveri | FileCheck -check-prefix=NOHSA-DEFAULT %s -; RUN: llc < %s -mtriple=amdgcn -mcpu=kaveri -mattr=+flat-for-global | FileCheck -check-prefix=NOHSA-NODEFAULT %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-DEFAULT -check-prefix=ALL %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-NODEFAULT -check-prefix=ALL %s +; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=NOHSA-DEFAULT -check-prefix=ALL %s +; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=NOHSA-NODEFAULT -check-prefix=ALL %s +; There are no stack objects even though flat is used by default, so +; flat_scratch_init should be disabled. + +; ALL-LABEL: {{^}}test: +; HSA: .amd_kernel_code_t +; HSA: enable_sgpr_flat_scratch_init = 0 +; HSA: .end_amd_kernel_code_t + +; ALL-NOT: flat_scr + ; HSA-DEFAULT: flat_store_dword ; HSA-NODEFAULT: buffer_store_dword + ; NOHSA-DEFAULT: buffer_store_dword ; NOHSA-NODEFAULT: flat_store_dword define void @test(i32 addrspace(1)* %out) { diff --git a/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll b/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll new file mode 100644 index 000000000000..2c4c07c193af --- /dev/null +++ b/test/CodeGen/AMDGPU/cndmask-no-def-vcc.ll @@ -0,0 +1,56 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i1 @llvm.amdgcn.class.f32(float, i32) + +; Produces error after adding an implicit def to v_cndmask_b32 + +; GCN-LABEL: {{^}}vcc_shrink_vcc_def: +; GCN: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} +; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc +; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}} +define void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) { +bb0: + %tmp = icmp sgt i32 %arg1, 4 + %c = icmp eq i32 %arg3, 0 + %tmp4 = select i1 %c, float %arg, float 1.000000e+00 + %tmp5 = fcmp ogt float %arg2, 0.000000e+00 + %tmp6 = fcmp olt float %arg2, 1.000000e+00 + %tmp7 = fcmp olt float %arg, %tmp4 + %tmp8 = and i1 %tmp5, %tmp6 + %tmp9 = and i1 %tmp8, %tmp7 + br i1 %tmp9, label %bb1, label %bb2 + +bb1: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb2 + +bb2: + ret void +} + +; The undef flag on the condition src must be preserved on the +; implicit vcc use to avoid verifier errors. + +; GCN-LABEL: {{^}}preserve_condition_undef_flag: +; GCN-NOT: vcc +; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc +; GCN: v_cndmask_b32_e64 v1, 0, 1, s{{\[[0-9]+:[0-9]+\]}} +define void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) { +bb0: + %tmp = icmp sgt i32 %arg1, 4 + %undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef) + %tmp4 = select i1 %undef, float %arg, float 1.000000e+00 + %tmp5 = fcmp ogt float %arg2, 0.000000e+00 + %tmp6 = fcmp olt float %arg2, 1.000000e+00 + %tmp7 = fcmp olt float %arg, %tmp4 + %tmp8 = and i1 %tmp5, %tmp6 + %tmp9 = and i1 %tmp8, %tmp7 + br i1 %tmp9, label %bb1, label %bb2 + +bb1: + store volatile i32 0, i32 addrspace(1)* undef + br label %bb2 + +bb2: + ret void +} diff --git a/test/CodeGen/AMDGPU/coalescer_distribute.ll b/test/CodeGen/AMDGPU/coalescer_distribute.ll new file mode 100644 index 000000000000..7ca2612598c8 --- /dev/null +++ b/test/CodeGen/AMDGPU/coalescer_distribute.ll @@ -0,0 +1,53 @@ +; RUN: llc -o /dev/null %s +; This testcase produces a situation with unused value numbers in subregister +; liveranges that get distributed by ConnectedVNInfoEqClasses. +target triple = "amdgcn--" + +define spir_kernel void @hoge() { +bb: + %tmp = tail call i32 @llvm.r600.read.tidig.x() + br i1 undef, label %bb2, label %bb23 + +bb2: + br i1 undef, label %bb6, label %bb8 + +bb6: + %tmp7 = or i64 undef, undef + br label %bb8 + +bb8: + %tmp9 = phi i64 [ %tmp7, %bb6 ], [ undef, %bb2 ] + %tmp10 = icmp eq i32 %tmp, 0 + br i1 %tmp10, label %bb11, label %bb23 + +bb11: + br i1 undef, label %bb20, label %bb17 + +bb17: + br label %bb20 + +bb20: + %tmp21 = phi i64 [ undef, %bb17 ], [ %tmp9, %bb11 ] + %tmp22 = trunc i64 %tmp21 to i32 + br label %bb23 + +bb23: + %tmp24 = phi i32 [ %tmp22, %bb20 ], [ undef, %bb8 ], [ undef, %bb ] + br label %bb25 + +bb25: + %tmp26 = phi i32 [ %tmp24, %bb23 ], [ undef, %bb25 ] + br i1 undef, label %bb25, label %bb30 + +bb30: + br i1 undef, label %bb32, label %bb34 + +bb32: + %tmp33 = zext i32 %tmp26 to i64 + br label %bb34 + +bb34: + ret void +} + +declare i32 @llvm.r600.read.tidig.x() diff --git a/test/CodeGen/AMDGPU/commute-compares.ll b/test/CodeGen/AMDGPU/commute-compares.ll index 31766047a358..731b47cd9ee2 100644 --- a/test/CodeGen/AMDGPU/commute-compares.ll +++ b/test/CodeGen/AMDGPU/commute-compares.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 ; -------------------------------------------------------------------------------- ; i32 compares @@ -9,7 +9,7 @@ declare i32 @llvm.r600.read.tidig.x() #0 ; GCN-LABEL: {{^}}commute_eq_64_i32: ; GCN: v_cmp_eq_i32_e32 vcc, 64, v{{[0-9]+}} define void @commute_eq_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -22,7 +22,7 @@ define void @commute_eq_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 ; GCN-LABEL: {{^}}commute_ne_64_i32: ; GCN: v_cmp_ne_i32_e32 vcc, 64, v{{[0-9]+}} define void @commute_ne_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -37,7 +37,7 @@ define void @commute_ne_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3039 ; GCN: v_cmp_ne_i32_e32 vcc, [[K]], v{{[0-9]+}} define void @commute_ne_litk_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -50,7 +50,7 @@ define void @commute_ne_litk_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ; GCN-LABEL: {{^}}commute_ugt_64_i32: ; GCN: v_cmp_lt_u32_e32 vcc, 64, v{{[0-9]+}} define void @commute_ugt_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -63,7 +63,7 @@ define void @commute_ugt_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_uge_64_i32: ; GCN: v_cmp_lt_u32_e32 vcc, 63, v{{[0-9]+}} define void @commute_uge_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -76,7 +76,7 @@ define void @commute_uge_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_ult_64_i32: ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}} define void @commute_ult_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -89,7 +89,7 @@ define void @commute_ult_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_ule_63_i32: ; GCN: v_cmp_gt_u32_e32 vcc, 64, v{{[0-9]+}} define void @commute_ule_63_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -105,7 +105,7 @@ define void @commute_ule_63_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) # ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x41{{$}} ; GCN: v_cmp_gt_u32_e32 vcc, [[K]], v{{[0-9]+}} define void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -118,7 +118,7 @@ define void @commute_ule_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_sgt_neg1_i32: ; GCN: v_cmp_lt_i32_e32 vcc, -1, v{{[0-9]+}} define void @commute_sgt_neg1_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -131,7 +131,7 @@ define void @commute_sgt_neg1_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ; GCN-LABEL: {{^}}commute_sge_neg2_i32: ; GCN: v_cmp_lt_i32_e32 vcc, -3, v{{[0-9]+}} define void @commute_sge_neg2_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -144,7 +144,7 @@ define void @commute_sge_neg2_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) ; GCN-LABEL: {{^}}commute_slt_neg16_i32: ; GCN: v_cmp_gt_i32_e32 vcc, -16, v{{[0-9]+}} define void @commute_slt_neg16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -157,7 +157,7 @@ define void @commute_slt_neg16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in ; GCN-LABEL: {{^}}commute_sle_5_i32: ; GCN: v_cmp_gt_i32_e32 vcc, 6, v{{[0-9]+}} define void @commute_sle_5_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i32, i32 addrspace(1)* %gep.in @@ -174,7 +174,7 @@ define void @commute_sle_5_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #1 ; GCN-LABEL: {{^}}commute_eq_64_i64: ; GCN: v_cmp_eq_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}} define void @commute_eq_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -187,7 +187,7 @@ define void @commute_eq_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 ; GCN-LABEL: {{^}}commute_ne_64_i64: ; GCN: v_cmp_ne_i64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ne_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -200,7 +200,7 @@ define void @commute_ne_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 ; GCN-LABEL: {{^}}commute_ugt_64_i64: ; GCN: v_cmp_lt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ugt_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -213,7 +213,7 @@ define void @commute_ugt_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_uge_64_i64: ; GCN: v_cmp_lt_u64_e32 vcc, 63, v{{\[[0-9]+:[0-9]+\]}} define void @commute_uge_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -226,7 +226,7 @@ define void @commute_uge_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_ult_64_i64: ; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ult_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -239,7 +239,7 @@ define void @commute_ult_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_ule_63_i64: ; GCN: v_cmp_gt_u64_e32 vcc, 64, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ule_63_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -255,7 +255,7 @@ define void @commute_ule_63_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) # ; GCN-DAG: s_movk_i32 s[[KLO:[0-9]+]], 0x41{{$}} ; GCN: v_cmp_gt_u64_e32 vcc, s{{\[}}[[KLO]]:{{[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -268,7 +268,7 @@ define void @commute_ule_64_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) # ; GCN-LABEL: {{^}}commute_sgt_neg1_i64: ; GCN: v_cmp_lt_i64_e32 vcc, -1, v{{\[[0-9]+:[0-9]+\]}} define void @commute_sgt_neg1_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -281,7 +281,7 @@ define void @commute_sgt_neg1_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) ; GCN-LABEL: {{^}}commute_sge_neg2_i64: ; GCN: v_cmp_lt_i64_e32 vcc, -3, v{{\[[0-9]+:[0-9]+\]}} define void @commute_sge_neg2_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -294,7 +294,7 @@ define void @commute_sge_neg2_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) ; GCN-LABEL: {{^}}commute_slt_neg16_i64: ; GCN: v_cmp_gt_i64_e32 vcc, -16, v{{\[[0-9]+:[0-9]+\]}} define void @commute_slt_neg16_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -307,7 +307,7 @@ define void @commute_slt_neg16_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in ; GCN-LABEL: {{^}}commute_sle_5_i64: ; GCN: v_cmp_gt_i64_e32 vcc, 6, v{{\[[0-9]+:[0-9]+\]}} define void @commute_sle_5_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %gep.in @@ -325,7 +325,7 @@ define void @commute_sle_5_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 ; GCN-LABEL: {{^}}commute_oeq_2.0_f32: ; GCN: v_cmp_eq_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_oeq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -339,7 +339,7 @@ define void @commute_oeq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ogt_2.0_f32: ; GCN: v_cmp_lt_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ogt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -352,7 +352,7 @@ define void @commute_ogt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_oge_2.0_f32: ; GCN: v_cmp_le_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_oge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -365,7 +365,7 @@ define void @commute_oge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_olt_2.0_f32: ; GCN: v_cmp_gt_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_olt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -378,7 +378,7 @@ define void @commute_olt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ole_2.0_f32: ; GCN: v_cmp_ge_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ole_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -391,7 +391,7 @@ define void @commute_ole_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_one_2.0_f32: ; GCN: v_cmp_lg_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_one_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -404,7 +404,7 @@ define void @commute_one_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ord_2.0_f32: ; GCN: v_cmp_o_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]] define void @commute_ord_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -417,7 +417,7 @@ define void @commute_ord_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ueq_2.0_f32: ; GCN: v_cmp_nlg_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ueq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -430,7 +430,7 @@ define void @commute_ueq_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ugt_2.0_f32: ; GCN: v_cmp_nge_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ugt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -443,7 +443,7 @@ define void @commute_ugt_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_uge_2.0_f32: ; GCN: v_cmp_ngt_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_uge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -456,7 +456,7 @@ define void @commute_uge_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ult_2.0_f32: ; GCN: v_cmp_nle_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ult_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -469,7 +469,7 @@ define void @commute_ult_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_ule_2.0_f32: ; GCN: v_cmp_nlt_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_ule_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -482,7 +482,7 @@ define void @commute_ule_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_une_2.0_f32: ; GCN: v_cmp_neq_f32_e32 vcc, 2.0, v{{[0-9]+}} define void @commute_une_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -495,7 +495,7 @@ define void @commute_une_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_uno_2.0_f32: ; GCN: v_cmp_u_f32_e32 vcc, [[REG:v[0-9]+]], [[REG]] define void @commute_uno_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load float, float addrspace(1)* %gep.in @@ -513,7 +513,7 @@ define void @commute_uno_2.0_f32(i32 addrspace(1)* %out, float addrspace(1)* %in ; GCN-LABEL: {{^}}commute_oeq_2.0_f64: ; GCN: v_cmp_eq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_oeq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -527,7 +527,7 @@ define void @commute_oeq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ogt_2.0_f64: ; GCN: v_cmp_lt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ogt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -540,7 +540,7 @@ define void @commute_ogt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_oge_2.0_f64: ; GCN: v_cmp_le_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_oge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -553,7 +553,7 @@ define void @commute_oge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_olt_2.0_f64: ; GCN: v_cmp_gt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_olt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -566,7 +566,7 @@ define void @commute_olt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ole_2.0_f64: ; GCN: v_cmp_ge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ole_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -579,7 +579,7 @@ define void @commute_ole_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_one_2.0_f64: ; GCN: v_cmp_lg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_one_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -592,7 +592,7 @@ define void @commute_one_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ord_2.0_f64: ; GCN: v_cmp_o_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]] define void @commute_ord_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -605,7 +605,7 @@ define void @commute_ord_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ueq_2.0_f64: ; GCN: v_cmp_nlg_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ueq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -618,7 +618,7 @@ define void @commute_ueq_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ugt_2.0_f64: ; GCN: v_cmp_nge_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ugt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -631,7 +631,7 @@ define void @commute_ugt_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_uge_2.0_f64: ; GCN: v_cmp_ngt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_uge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -644,7 +644,7 @@ define void @commute_uge_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ult_2.0_f64: ; GCN: v_cmp_nle_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ult_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -657,7 +657,7 @@ define void @commute_ult_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_ule_2.0_f64: ; GCN: v_cmp_nlt_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_ule_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -670,7 +670,7 @@ define void @commute_ule_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_une_2.0_f64: ; GCN: v_cmp_neq_f64_e32 vcc, 2.0, v{{\[[0-9]+:[0-9]+\]}} define void @commute_une_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in @@ -683,7 +683,7 @@ define void @commute_une_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %i ; GCN-LABEL: {{^}}commute_uno_2.0_f64: ; GCN: v_cmp_u_f64_e32 vcc, [[REG:v\[[0-9]+:[0-9]+\]]], [[REG]] define void @commute_uno_2.0_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %val = load double, double addrspace(1)* %gep.in diff --git a/test/CodeGen/AMDGPU/commute-shifts.ll b/test/CodeGen/AMDGPU/commute-shifts.ll index f88cf6470c4f..862f236514ca 100644 --- a/test/CodeGen/AMDGPU/commute-shifts.ll +++ b/test/CodeGen/AMDGPU/commute-shifts.ll @@ -4,30 +4,26 @@ ; GCN-LABEL: {{^}}main: ; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}} ; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1 - -define void @main() #0 { -main_body: - %0 = fptosi float undef to i32 - %1 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> undef, <32 x i8> undef, i32 2) - %2 = extractelement <4 x i32> %1, i32 0 - %3 = and i32 %0, 7 - %4 = shl i32 1, %3 - %5 = and i32 %2, %4 - %6 = icmp eq i32 %5, 0 - %.10 = select i1 %6, float 0.000000e+00, float undef - %7 = call i32 @llvm.SI.packf16(float undef, float %.10) - %8 = bitcast i32 %7 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %8, float undef, float %8) +define amdgpu_ps void @main(float %arg0, float %arg1) #0 { +bb: + %tmp = fptosi float %arg0 to i32 + %tmp1 = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp2.f = extractelement <4 x float> %tmp1, i32 0 + %tmp2 = bitcast float %tmp2.f to i32 + %tmp3 = and i32 %tmp, 7 + %tmp4 = shl i32 1, %tmp3 + %tmp5 = and i32 %tmp2, %tmp4 + %tmp6 = icmp eq i32 %tmp5, 0 + %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1 + %tmp8 = call i32 @llvm.SI.packf16(float undef, float %tmp7) + %tmp9 = bitcast i32 %tmp8 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %tmp9, float undef, float %tmp9) ret void } -; Function Attrs: nounwind readnone -declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1 - -; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 declare i32 @llvm.SI.packf16(float, float) #1 - declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/commute_modifiers.ll b/test/CodeGen/AMDGPU/commute_modifiers.ll index 7fc36eabb780..bce3fe998c8a 100644 --- a/test/CodeGen/AMDGPU/commute_modifiers.ll +++ b/test/CodeGen/AMDGPU/commute_modifiers.ll @@ -1,15 +1,15 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 declare float @llvm.fabs.f32(float) #1 declare float @llvm.fma.f32(float, float, float) nounwind readnone ; FUNC-LABEL: @commute_add_imm_fabs_f32 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, |[[X]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %x = load float, float addrspace(1)* %gep.0 %x.fabs = call float @llvm.fabs.f32(float %x) #1 @@ -21,9 +21,9 @@ define void @commute_add_imm_fabs_f32(float addrspace(1)* %out, float addrspace( ; FUNC-LABEL: @commute_mul_imm_fneg_fabs_f32 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], -4.0, |[[X]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %x = load float, float addrspace(1)* %gep.0 %x.fabs = call float @llvm.fabs.f32(float %x) #1 @@ -36,9 +36,9 @@ define void @commute_mul_imm_fneg_fabs_f32(float addrspace(1)* %out, float addrs ; FUNC-LABEL: @commute_mul_imm_fneg_f32 ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: v_mul_f32_e32 [[REG:v[0-9]+]], -4.0, [[X]] -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %x = load float, float addrspace(1)* %gep.0 %x.fneg = fsub float -0.000000e+00, %x @@ -52,9 +52,9 @@ define void @commute_mul_imm_fneg_f32(float addrspace(1)* %out, float addrspace( ; SI: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: v_mov_b32_e32 [[K:v[0-9]+]], 0x44800000 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], |[[X]]|, [[K]] -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %x = load float, float addrspace(1)* %gep.0 %x.fabs = call float @llvm.fabs.f32(float %x) #1 @@ -67,13 +67,13 @@ define void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace( ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 %y.fabs = call float @llvm.fabs.f32(float %y) #1 %z = fadd float %x, %y.fabs store float %z, float addrspace(1)* %out @@ -84,13 +84,13 @@ define void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -[[Y]] -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 %y.fneg = fsub float -0.000000e+00, %y %z = fmul float %x, %y.fneg store float %z, float addrspace(1)* %out @@ -101,13 +101,13 @@ define void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -|[[Y]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 %y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs %z = fmul float %x, %y.fabs.fneg @@ -120,13 +120,13 @@ define void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, |[[Y]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 %x.fabs = call float @llvm.fabs.f32(float %x) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1 %z = fmul float %x.fabs, %y.fabs @@ -138,13 +138,13 @@ define void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrs ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, -|[[Y]]| -; SI-NEXT: buffer_store_dword [[REG]] +; SI: buffer_store_dword [[REG]] define void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 %x.fabs = call float @llvm.fabs.f32(float %x) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs @@ -159,16 +159,16 @@ define void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float ; SI-LABEL: {{^}}fma_a_2.0_neg_b_f32 ; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], |[[R2]]| +; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, |[[R2]]| ; SI: buffer_store_dword [[RESULT]] define void @fma_a_2.0_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r2.fabs = call float @llvm.fabs.f32(float %r2) diff --git a/test/CodeGen/AMDGPU/complex-folding.ll b/test/CodeGen/AMDGPU/complex-folding.ll index a5399a71324c..acf81ba7b5dd 100644 --- a/test/CodeGen/AMDGPU/complex-folding.ll +++ b/test/CodeGen/AMDGPU/complex-folding.ll @@ -2,18 +2,16 @@ ; CHECK: {{^}}main: ; CHECK-NOT: MOV -define void @main(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @main(<4 x float> inreg %reg0) { entry: %0 = extractelement <4 x float> %reg0, i32 0 %1 = call float @fabs(float %0) %2 = fptoui float %1 to i32 %3 = bitcast i32 %2 to float %4 = insertelement <4 x float> undef, float %3, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %4, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %4, i32 0, i32 0) ret void } declare float @fabs(float ) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/convergent-inlineasm.ll b/test/CodeGen/AMDGPU/convergent-inlineasm.ll new file mode 100644 index 000000000000..55a38e576ad1 --- /dev/null +++ b/test/CodeGen/AMDGPU/convergent-inlineasm.ll @@ -0,0 +1,45 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +; GCN-LABEL: {{^}}convergent_inlineasm: +; GCN: BB#0: +; GCN: v_cmp_ne_i32_e64 +; GCN: BB#1: +define void @convergent_inlineasm(i64 addrspace(1)* nocapture %arg) { +bb: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 1) #1 + %tmp2 = icmp eq i32 %tmp, 8 + br i1 %tmp2, label %bb3, label %bb5 + +bb3: ; preds = %bb + %tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp + store i64 %tmp1, i64 addrspace(1)* %arg, align 8 + br label %bb5 + +bb5: ; preds = %bb3, %bb + ret void +} + +; GCN-LABEL: {{^}}nonconvergent_inlineasm: +; GCN: BB#1: +; GCN: v_cmp_ne_i32_e64 +; GCN: BB1_2: +define void @nonconvergent_inlineasm(i64 addrspace(1)* nocapture %arg) { +bb: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 1) + %tmp2 = icmp eq i32 %tmp, 8 + br i1 %tmp2, label %bb3, label %bb5 + +bb3: ; preds = %bb + %tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp + store i64 %tmp1, i64 addrspace(1)* %arg, align 8 + br label %bb5 + +bb5: ; preds = %bb3, %bb + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { convergent nounwind readnone } diff --git a/test/CodeGen/AMDGPU/copy-illegal-type.ll b/test/CodeGen/AMDGPU/copy-illegal-type.ll index 8b397566066a..00d2257f4adc 100644 --- a/test/CodeGen/AMDGPU/copy-illegal-type.ll +++ b/test/CodeGen/AMDGPU/copy-illegal-type.ll @@ -54,31 +54,12 @@ define void @test_copy_v4i8_x4(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace( } ; FUNC-LABEL: {{^}}test_copy_v4i8_extra_use: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI_DAG: buffer_store_byte - -; After scalarizing v4i8 loads is fixed. -; XSI: buffer_load_dword -; XSI: V_BFE -; XSI: V_ADD -; XSI: V_ADD -; XSI: V_ADD -; XSI: buffer_store_dword -; XSI: buffer_store_dword +; SI: buffer_load_dword +; SI-DAG: v_lshrrev_b32 +; SI: v_and_b32 +; SI: v_or_b32 +; SI-DAG: buffer_store_dword +; SI-DAG: buffer_store_dword ; SI: s_endpgm define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %in) nounwind { @@ -90,34 +71,14 @@ define void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> add } ; FUNC-LABEL: {{^}}test_copy_v4i8_x2_extra_use: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: v_add -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI_DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI-DAG: buffer_store_byte -; SI_DAG: buffer_store_byte - -; XSI: buffer_load_dword -; XSI: BFE -; XSI: buffer_store_dword -; XSI: V_ADD -; XSI: buffer_store_dword -; XSI-NEXT: buffer_store_dword - +; SI: buffer_load_dword +; SI-DAG: v_lshrrev_b32 +; SI-DAG: v_add_i32 +; SI-DAG: v_and_b32 +; SI-DAG: v_or_b32 +; SI-DAG: buffer_store_dword +; SI: buffer_store_dword +; SI: buffer_store_dword ; SI: s_endpgm define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind { %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 @@ -128,21 +89,50 @@ define void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> ret void } -; FUNC-LABEL: {{^}}test_copy_v3i8: -; SI-NOT: bfe -; SI-NOT: bfi +; FUNC-LABEL: {{^}}test_copy_v3i8_align4: +; SI: buffer_load_dword +; SI-DAG: buffer_store_short v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; SI-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} ; SI: s_endpgm -define void @test_copy_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { +define void @test_copy_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { %val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4 store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 4 ret void } +; FUNC-LABEL: {{^}}test_copy_v3i8_align2: +; SI-DAG: buffer_load_ushort v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; SI-DAG: buffer_load_ubyte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} +; SI-DAG: buffer_store_short v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; SI-DAG: buffer_store_byte v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} +; SI: s_endpgm +define void @test_copy_v3i8_align2(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { + %val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 2 + store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 2 + ret void +} + +; FUNC-LABEL: {{^}}test_copy_v3i8_align1: +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte +; SI: buffer_load_ubyte + +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: s_endpgm +define void @test_copy_v3i8_align1(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) nounwind { + %val = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 1 + store <3 x i8> %val, <3 x i8> addrspace(1)* %out, align 1 + ret void +} + ; FUNC-LABEL: {{^}}test_copy_v4i8_volatile_load: ; SI: buffer_load_ubyte ; SI: buffer_load_ubyte ; SI: buffer_load_ubyte ; SI: buffer_load_ubyte +; SI: buffer_store_dword ; SI: s_endpgm define void @test_copy_v4i8_volatile_load(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { %val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 diff --git a/test/CodeGen/AMDGPU/ctlz.ll b/test/CodeGen/AMDGPU/ctlz.ll index baedf47eef0d..6d2d260177e5 100644 --- a/test/CodeGen/AMDGPU/ctlz.ll +++ b/test/CodeGen/AMDGPU/ctlz.ll @@ -116,11 +116,11 @@ define void @v_ctlz_i8(i8 addrspace(1)* noalias %out, i8 addrspace(1)* noalias % ; SI-DAG: s_flbit_i32_b32 [[FFBH_LO:s[0-9]+]], s[[LO]] ; SI-DAG: s_add_i32 [[ADD:s[0-9]+]], [[FFBH_LO]], 32 ; SI-DAG: s_flbit_i32_b32 [[FFBH_HI:s[0-9]+]], s[[HI]] -; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[FFBH_LO]] +; SI-DAG: v_mov_b32_e32 [[VFFBH_LO:v[0-9]+]], [[ADD]] ; SI-DAG: v_mov_b32_e32 [[VFFBH_HI:v[0-9]+]], [[FFBH_HI]] ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]] ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} -; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} +; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} define void @s_ctlz_i64(i64 addrspace(1)* noalias %out, i64 %val) nounwind { %ctlz = call i64 @llvm.ctlz.i64(i64 %val, i1 false) store i64 %ctlz, i64 addrspace(1)* %out @@ -136,7 +136,8 @@ define void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind } ; FUNC-LABEL: {{^}}v_ctlz_i64: -; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} +; SI-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; SI-DAG: v_cmp_eq_i32_e64 [[CMPHI:s\[[0-9]+:[0-9]+\]]], 0, v[[HI]] ; SI-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] ; SI-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] @@ -145,8 +146,7 @@ define void @s_ctlz_i64_trunc(i32 addrspace(1)* noalias %out, i64 %val) nounwind ; SI-DAG: v_or_b32_e32 [[OR:v[0-9]+]], v[[LO]], v[[HI]] ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[OR]] ; SI-DAG: v_cndmask_b32_e64 v[[CLTZ_LO:[0-9]+]], v[[CTLZ:[0-9]+]], 64, vcc -; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} -; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CLTZ_LO]]:[[CTLZ_HI]]{{\]}} +; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CLTZ_LO]]:[[CTLZ_HI]]{{\]}} define void @v_ctlz_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/AMDGPU/ctlz_zero_undef.ll b/test/CodeGen/AMDGPU/ctlz_zero_undef.ll index c1f84cd460cf..65e8205317b6 100644 --- a/test/CodeGen/AMDGPU/ctlz_zero_undef.ll +++ b/test/CodeGen/AMDGPU/ctlz_zero_undef.ll @@ -116,14 +116,14 @@ define void @s_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 %va } ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i64: -; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; SI-DAG: {{buffer|flat}}_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; SI-DAG: v_cmp_eq_i32_e64 [[CMPHI:s\[[0-9]+:[0-9]+\]]], 0, v[[HI]] ; SI-DAG: v_ffbh_u32_e32 [[FFBH_LO:v[0-9]+]], v[[LO]] ; SI-DAG: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, 32, [[FFBH_LO]] ; SI-DAG: v_ffbh_u32_e32 [[FFBH_HI:v[0-9]+]], v[[HI]] ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]] ; SI-DAG: v_mov_b32_e32 v[[CTLZ_HI:[0-9]+]], 0{{$}} -; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} +; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}} define void @v_ctlz_zero_undef_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid @@ -149,7 +149,7 @@ define void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 add ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_eq_neg1: ; SI: buffer_load_dword [[VAL:v[0-9]+]], ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI-NEXT: buffer_store_dword [[RESULT]], +; SI: buffer_store_dword [[RESULT]], define void @v_ctlz_zero_undef_i32_sel_eq_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { %val = load i32, i32 addrspace(1)* %valptr %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone @@ -162,7 +162,7 @@ define void @v_ctlz_zero_undef_i64_trunc(i32 addrspace(1)* noalias %out, i64 add ; FUNC-LABEL: {{^}}v_ctlz_zero_undef_i32_sel_ne_neg1: ; SI: buffer_load_dword [[VAL:v[0-9]+]], ; SI: v_ffbh_u32_e32 [[RESULT:v[0-9]+]], [[VAL]] -; SI-NEXT: buffer_store_dword [[RESULT]], +; SI: buffer_store_dword [[RESULT]], define void @v_ctlz_zero_undef_i32_sel_ne_neg1(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %valptr) nounwind { %val = load i32, i32 addrspace(1)* %valptr %ctlz = call i32 @llvm.ctlz.i32(i32 %val, i1 true) nounwind readnone diff --git a/test/CodeGen/AMDGPU/ctpop.ll b/test/CodeGen/AMDGPU/ctpop.ll index 0a031c5e24d1..e53ad13464e8 100644 --- a/test/CodeGen/AMDGPU/ctpop.ll +++ b/test/CodeGen/AMDGPU/ctpop.ll @@ -60,9 +60,9 @@ define void @v_ctpop_add_chain_i32(i32 addrspace(1)* noalias %out, i32 addrspace ; FUNC-LABEL: {{^}}v_ctpop_add_sgpr_i32: ; GCN: buffer_load_dword [[VAL0:v[0-9]+]], -; GCN-NEXT: s_waitcnt +; GCN: s_waitcnt ; GCN-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL0]], s{{[0-9]+}} -; GCN-NEXT: buffer_store_dword [[RESULT]], +; GCN: buffer_store_dword [[RESULT]], ; GCN: s_endpgm define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in0, i32 addrspace(1)* noalias %in1, i32 %sval) nounwind { %val0 = load i32, i32 addrspace(1)* %in0, align 4 @@ -203,8 +203,8 @@ define void @v_ctpop_i32_add_inline_constant_inv(i32 addrspace(1)* noalias %out, } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_literal: -; GCN: buffer_load_dword [[VAL:v[0-9]+]], -; GCN: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], +; GCN-DAG: v_mov_b32_e32 [[LIT:v[0-9]+]], 0x1869f ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]] ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[LIT]] ; GCN: buffer_store_dword [[RESULT]], @@ -250,8 +250,8 @@ define void @v_ctpop_i32_add_var_inv(i32 addrspace(1)* noalias %out, i32 addrspa } ; FUNC-LABEL: {{^}}v_ctpop_i32_add_vvar_inv: -; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], {{0$}} -; GCN-DAG: buffer_load_dword [[VAR:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:16 +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], {{0$}} +; GCN-DAG: buffer_load_dword [[VAR:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16 ; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] ; VI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], [[VAR]] ; GCN: buffer_store_dword [[RESULT]], diff --git a/test/CodeGen/AMDGPU/ctpop64.ll b/test/CodeGen/AMDGPU/ctpop64.ll index ec2971e98032..d0976b7d45b8 100644 --- a/test/CodeGen/AMDGPU/ctpop64.ll +++ b/test/CodeGen/AMDGPU/ctpop64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s declare i64 @llvm.ctpop.i64(i64) nounwind readnone @@ -7,6 +7,9 @@ declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone +declare i65 @llvm.ctpop.i65(i65) nounwind readnone +declare i128 @llvm.ctpop.i128(i128) nounwind readnone + ; FUNC-LABEL: {{^}}s_ctpop_i64: ; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c @@ -110,15 +113,13 @@ define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrs ret void } -; FIXME: We currently disallow SALU instructions in all branches, -; but there are some cases when the should be allowed. - ; FUNC-LABEL: {{^}}ctpop_i64_in_br: -; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd -; VI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34 -; GCN: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}} +; SI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd +; VI-DAG: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34 +; GCN-DAG: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}} +; GCN-DAG: s_mov_b32 [[ZERO:s[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]] -; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]] +; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[ZERO]] ; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}} ; GCN: s_endpgm define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) { @@ -140,3 +141,51 @@ endif: store i64 %tmp5, i64 addrspace(1)* %out ret void } + +; FUNC-LABEL: {{^}}s_ctpop_i128: +; GCN: s_bcnt1_i32_b64 [[SRESULT0:s[0-9]+]], +; GCN: s_bcnt1_i32_b64 [[SRESULT1:s[0-9]+]], +; GCN: s_add_i32 s{{[0-9]+}}, [[SRESULT1]], [[SRESULT0]] +; GCN: s_endpgm +define void @s_ctpop_i128(i32 addrspace(1)* noalias %out, i128 %val) nounwind { + %ctpop = call i128 @llvm.ctpop.i128(i128 %val) nounwind readnone + %truncctpop = trunc i128 %ctpop to i32 + store i32 %truncctpop, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}s_ctpop_i65: +; GCN: s_and_b32 +; GCN: s_bcnt1_i32_b64 [[REG0:s[0-9]+]], +; GCN: s_bcnt1_i32_b64 [[REG1:s[0-9]+]], +; GCN: s_add_i32 {{s[0-9]+}}, [[REG0]], [[REG1]] +; GCN: s_endpgm +define void @s_ctpop_i65(i32 addrspace(1)* noalias %out, i65 %val) nounwind { + %ctpop = call i65 @llvm.ctpop.i65(i65 %val) nounwind readnone + %truncctpop = trunc i65 %ctpop to i32 + store i32 %truncctpop, i32 addrspace(1)* %out, align 4 + ret void +} + +; FIXME: Should not have extra add + +; FUNC-LABEL: {{^}}v_ctpop_i128: +; GCN: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} + +; GCN-DAG: v_bcnt_u32_b32_e64 [[MIDRESULT0:v[0-9]+]], v{{[0-9]+}}, 0 +; GCN-DAG: v_bcnt_u32_b32{{_e32|_e64}} [[MIDRESULT1:v[0-9]+]], v[[VAL3]], [[MIDRESULT0]] + +; GCN-DAG: v_bcnt_u32_b32_e64 [[MIDRESULT2:v[0-9]+]], v[[VAL0]], 0 +; GCN-DAG: v_bcnt_u32_b32{{_e32|_e64}} [[MIDRESULT3:v[0-9]+]], v{{[0-9]+}}, [[MIDRESULT2]] + +; GCN: v_add_i32_e32 [[RESULT:v[0-9]+]], vcc, [[MIDRESULT1]], [[MIDRESULT2]] + +; GCN: buffer_store_dword [[RESULT]], +; GCN: s_endpgm +define void @v_ctpop_i128(i32 addrspace(1)* noalias %out, i128 addrspace(1)* noalias %in) nounwind { + %val = load i128, i128 addrspace(1)* %in, align 8 + %ctpop = call i128 @llvm.ctpop.i128(i128 %val) nounwind readnone + %truncctpop = trunc i128 %ctpop to i32 + store i32 %truncctpop, i32 addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/cube.ll b/test/CodeGen/AMDGPU/cube.ll new file mode 100644 index 000000000000..ab99af5864e9 --- /dev/null +++ b/test/CodeGen/AMDGPU/cube.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare float @llvm.amdgcn.cubeid(float, float, float) #0 +declare float @llvm.amdgcn.cubesc(float, float, float) #0 +declare float @llvm.amdgcn.cubetc(float, float, float) #0 +declare float @llvm.amdgcn.cubema(float, float, float) #0 + +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 + + +; GCN-LABEL: {{^}}cube: +; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN: buffer_store_dwordx4 +define void @cube(<4 x float> addrspace(1)* %out, float %a, float %b, float %c) #1 { + %cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c) + %cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c) + %cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c) + %cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c) + + %vec0 = insertelement <4 x float> undef, float %cubeid, i32 0 + %vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1 + %vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2 + %vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3 + store <4 x float> %vec3, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}legacy_cube: +; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; GCN: buffer_store_dwordx4 +define void @legacy_cube(<4 x float> addrspace(1)* %out, <4 x float> %abcx) #1 { + %cube = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %abcx) + store <4 x float> %cube, <4 x float> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + diff --git a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll index 834922c62cbd..dcd48c97434d 100644 --- a/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll +++ b/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; SI-LABEL: {{^}}load_i8_to_f32: @@ -15,12 +15,9 @@ define void @load_i8_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* n } ; SI-LABEL: {{^}}load_v2i8_to_v2f32: -; SI: buffer_load_ushort [[LOADREG:v[0-9]+]], -; SI-NOT: bfe -; SI-NOT: lshr -; SI-NOT: and -; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LOADREG]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG]] +; SI: buffer_load_ushort [[LD:v[0-9]+]] +; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[LD]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LD]] ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> addrspace(1)* noalias %in) nounwind { %load = load <2 x i8>, <2 x i8> addrspace(1)* %in, align 2 @@ -30,11 +27,11 @@ define void @load_v2i8_to_v2f32(<2 x float> addrspace(1)* noalias %out, <2 x i8> } ; SI-LABEL: {{^}}load_v3i8_to_v3f32: -; SI-NOT: bfe +; SI: buffer_load_dword [[VAL:v[0-9]+]] ; SI-NOT: v_cvt_f32_ubyte3_e32 -; SI-DAG: v_cvt_f32_ubyte2_e32 -; SI-DAG: v_cvt_f32_ubyte1_e32 -; SI-DAG: v_cvt_f32_ubyte0_e32 +; SI-DAG: v_cvt_f32_ubyte2_e32 v{{[0-9]+}}, [[VAL]] +; SI-DAG: v_cvt_f32_ubyte1_e32 v[[HIRESULT:[0-9]+]], [[VAL]] +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[VAL]] ; SI: buffer_store_dwordx2 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, define void @load_v3i8_to_v3f32(<3 x float> addrspace(1)* noalias %out, <3 x i8> addrspace(1)* noalias %in) nounwind { %load = load <3 x i8>, <3 x i8> addrspace(1)* %in, align 4 @@ -62,20 +59,20 @@ define void @load_v4i8_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> ; This should not be adding instructions to shift into the correct ; position in the word for the component. +; FIXME: Packing bytes ; SI-LABEL: {{^}}load_v4i8_to_v4f32_unaligned: ; SI: buffer_load_ubyte [[LOADREG3:v[0-9]+]] ; SI: buffer_load_ubyte [[LOADREG2:v[0-9]+]] ; SI: buffer_load_ubyte [[LOADREG1:v[0-9]+]] ; SI: buffer_load_ubyte [[LOADREG0:v[0-9]+]] -; SI-NOT: v_lshlrev_b32 -; SI-NOT: v_or_b32 - -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], [[LOADREG0]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG1]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, [[LOADREG2]] -; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]], [[LOADREG3]] +; SI-DAG: v_lshlrev_b32 +; SI-DAG: v_or_b32 +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[LORESULT:[0-9]+]], +; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, +; SI-DAG: v_cvt_f32_ubyte0_e32 v{{[0-9]+}}, +; SI-DAG: v_cvt_f32_ubyte0_e32 v[[HIRESULT:[0-9]+]] -; SI: buffer_store_dwordx4 v{{\[}}[[LORESULT]]:[[HIRESULT]]{{\]}}, +; SI: buffer_store_dwordx4 define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 %cvt = uitofp <4 x i8> %load to <4 x float> @@ -83,26 +80,25 @@ define void @load_v4i8_to_v4f32_unaligned(<4 x float> addrspace(1)* noalias %out ret void } -; XXX - This should really still be able to use the v_cvt_f32_ubyte0 -; for each component, but computeKnownBits doesn't handle vectors very -; well. - +; Instructions still emitted to repack bytes for add use. ; SI-LABEL: {{^}}load_v4i8_to_v4f32_2_uses: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: v_cvt_f32_ubyte0_e32 -; SI: v_cvt_f32_ubyte0_e32 -; SI: v_cvt_f32_ubyte0_e32 -; SI: v_cvt_f32_ubyte0_e32 - -; XXX - replace with this when v4i8 loads aren't scalarized anymore. -; XSI: buffer_load_dword -; XSI: v_cvt_f32_u32_e32 -; XSI: v_cvt_f32_u32_e32 -; XSI: v_cvt_f32_u32_e32 -; XSI: v_cvt_f32_u32_e32 +; SI: buffer_load_dword +; SI-DAG: v_cvt_f32_ubyte0_e32 +; SI-DAG: v_cvt_f32_ubyte1_e32 +; SI-DAG: v_cvt_f32_ubyte2_e32 +; SI-DAG: v_cvt_f32_ubyte3_e32 + +; SI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 24 +; SI-DAG: v_lshrrev_b32_e32 v{{[0-9]+}}, 16 +; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 16 +; SI-DAG: v_lshlrev_b32_e32 v{{[0-9]+}}, 8 +; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xffff, +; SI-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff00, +; SI-DAG: v_add_i32 + +; SI: buffer_store_dwordx4 +; SI: buffer_store_dword + ; SI: s_endpgm define void @load_v4i8_to_v4f32_2_uses(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out2, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 @@ -170,9 +166,9 @@ define void @i8_zext_inreg_hi1_to_f32(float addrspace(1)* noalias %out, i32 addr ret void } - ; We don't get these ones because of the zext, but instcombine removes ; them so it shouldn't really matter. +; SI-LABEL: {{^}}i8_zext_i32_to_f32: define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1)* noalias %in) nounwind { %load = load i8, i8 addrspace(1)* %in, align 1 %ext = zext i8 %load to i32 @@ -181,6 +177,7 @@ define void @i8_zext_i32_to_f32(float addrspace(1)* noalias %out, i8 addrspace(1 ret void } +; SI-LABEL: {{^}}v4i8_zext_v4i32_to_v4f32: define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %in) nounwind { %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 1 %ext = zext <4 x i8> %load to <4 x i32> @@ -188,3 +185,58 @@ define void @v4i8_zext_v4i32_to_v4f32(<4 x float> addrspace(1)* noalias %out, <4 store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16 ret void } + +; SI-LABEL: {{^}}extract_byte0_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte0_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %and = and i32 %val, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte1_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte1_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 8 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte2_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte2_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 16 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}extract_byte3_to_f32: +; SI: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOT: [[VAL]] +; SI: v_cvt_f32_ubyte3_e32 [[CONV:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[CONV]] +define void @extract_byte3_to_f32(float addrspace(1)* noalias %out, i32 addrspace(1)* noalias %in) nounwind { + %val = load i32, i32 addrspace(1)* %in + %srl = lshr i32 %val, 24 + %and = and i32 %srl, 255 + %cvt = uitofp i32 %and to float + store float %cvt, float addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll b/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll new file mode 100644 index 000000000000..a32c16dfac38 --- /dev/null +++ b/test/CodeGen/AMDGPU/dagcombine-reassociate-bug.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; Test for a bug where DAGCombiner::ReassociateOps() was creating adds +; with offset in the first operand and base pointers in the second. + +; CHECK-LABEL: {{^}}store_same_base_ptr: +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR:v\[[0-9]+:[0-9]+\]]], [[SADDR:s\[[0-9]+:[0-9]+\]]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] +; CHECK: buffer_store_dword v{{[0-9]+}}, [[VADDR]], [[SADDR]] + +define void @store_same_base_ptr(i32 addrspace(1)* %out) { +entry: + %id = call i32 @llvm.amdgcn.workitem.id.x() #0 + %offset = sext i32 %id to i64 + %offset0 = add i64 %offset, 1027 + %ptr0 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset0 + store volatile i32 3, i32 addrspace(1)* %ptr0 + %offset1 = add i64 %offset, 1026 + %ptr1 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset1 + store volatile i32 2, i32 addrspace(1)* %ptr1 + %offset2 = add i64 %offset, 1025 + %ptr2 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset2 + store volatile i32 1, i32 addrspace(1)* %ptr2 + %offset3 = add i64 %offset, 1024 + %ptr3 = getelementptr i32, i32 addrspace(1)* %out, i64 %offset3 + store volatile i32 0, i32 addrspace(1)* %ptr3 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/debugger-emit-prologue.ll b/test/CodeGen/AMDGPU/debugger-emit-prologue.ll new file mode 100644 index 000000000000..49a7e722f29c --- /dev/null +++ b/test/CodeGen/AMDGPU/debugger-emit-prologue.ll @@ -0,0 +1,80 @@ +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-emit-prologue -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s --check-prefix=NOATTR + +; CHECK: debug_wavefront_private_segment_offset_sgpr = [[SOFF:[0-9]+]] +; CHECK: debug_private_segment_buffer_sgpr = [[SREG:[0-9]+]] + +; CHECK: v_mov_b32_e32 [[WGIDX:v[0-9]+]], s{{[0-9]+}} +; CHECK: buffer_store_dword [[WGIDX]], off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] +; CHECK: buffer_store_dword v0, off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] offset:16 + +; CHECK: v_mov_b32_e32 [[WGIDY:v[0-9]+]], s{{[0-9]+}} +; CHECK: buffer_store_dword [[WGIDY]], off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] offset:4 +; CHECK: buffer_store_dword v1, off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] offset:20 + +; CHECK: v_mov_b32_e32 [[WGIDZ:v[0-9]+]], s{{[0-9]+}} +; CHECK: buffer_store_dword [[WGIDZ]], off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] offset:8 +; CHECK: buffer_store_dword v2, off, s[{{[0-9]+:[0-9]+}}], s[[SOFF]] offset:24 + +; CHECK: DebuggerWavefrontPrivateSegmentOffsetSGPR: s[[SOFF]] +; CHECK: DebuggerPrivateSegmentBufferSGPR: s[[SREG]] + +; NOATTR-NOT: DebuggerWavefrontPrivateSegmentOffsetSGPR +; NOATTR-NOT: DebuggerPrivateSegmentBufferSGPR + +; Function Attrs: nounwind +define void @test(i32 addrspace(1)* %A) #0 !dbg !12 { +entry: + %A.addr = alloca i32 addrspace(1)*, align 4 + store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 + store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 + %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 + store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 + %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 + store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 + ret void, !dbg !26 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="fiji" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!opencl.kernels = !{!3} +!llvm.module.flags = !{!9, !10} +!llvm.ident = !{!11} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 269772)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "test01.cl", directory: "/home/kzhuravl/Lightning/testing") +!2 = !{} +!3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} +!4 = !{!"kernel_arg_addr_space", i32 1} +!5 = !{!"kernel_arg_access_qual", !"none"} +!6 = !{!"kernel_arg_type", !"int*"} +!7 = !{!"kernel_arg_base_type", !"int*"} +!8 = !{!"kernel_arg_type_qual", !""} +!9 = !{i32 2, !"Dwarf Version", i32 2} +!10 = !{i32 2, !"Debug Info Version", i32 3} +!11 = !{!"clang version 3.9.0 (trunk 269772)"} +!12 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !13, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!13 = !DISubroutineType(types: !14) +!14 = !{null, !15} +!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64, align: 32) +!16 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!17 = !DILocalVariable(name: "A", arg: 1, scope: !12, file: !1, line: 1, type: !15) +!18 = !DIExpression() +!19 = !DILocation(line: 1, column: 30, scope: !12) +!20 = !DILocation(line: 2, column: 3, scope: !12) +!21 = !DILocation(line: 2, column: 8, scope: !12) +!22 = !DILocation(line: 3, column: 3, scope: !12) +!23 = !DILocation(line: 3, column: 8, scope: !12) +!24 = !DILocation(line: 4, column: 3, scope: !12) +!25 = !DILocation(line: 4, column: 8, scope: !12) +!26 = !DILocation(line: 5, column: 1, scope: !12) diff --git a/test/CodeGen/AMDGPU/debugger-insert-nops.ll b/test/CodeGen/AMDGPU/debugger-insert-nops.ll new file mode 100644 index 000000000000..6638f4e25821 --- /dev/null +++ b/test/CodeGen/AMDGPU/debugger-insert-nops.ll @@ -0,0 +1,71 @@ +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-insert-nops -verify-machineinstrs < %s | FileCheck %s + +; CHECK: test01.cl:2:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 + +; CHECK: test01.cl:3:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 + +; CHECK: test01.cl:4:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 + +; CHECK: test01.cl:5:{{[0-9]+}} +; CHECK-NEXT: s_nop 0 +; CHECK-NEXT: s_endpgm + +; Function Attrs: nounwind +define void @test(i32 addrspace(1)* %A) #0 !dbg !12 { +entry: + %A.addr = alloca i32 addrspace(1)*, align 4 + store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 + store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 + %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 + store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 + %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 + store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 + ret void, !dbg !26 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!opencl.kernels = !{!3} +!llvm.module.flags = !{!9, !10} +!llvm.ident = !{!11} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "test01.cl", directory: "/home/kzhuravl/Lightning/testing") +!2 = !{} +!3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} +!4 = !{!"kernel_arg_addr_space", i32 1} +!5 = !{!"kernel_arg_access_qual", !"none"} +!6 = !{!"kernel_arg_type", !"int*"} +!7 = !{!"kernel_arg_base_type", !"int*"} +!8 = !{!"kernel_arg_type_qual", !""} +!9 = !{i32 2, !"Dwarf Version", i32 2} +!10 = !{i32 2, !"Debug Info Version", i32 3} +!11 = !{!"clang version 3.9.0 (trunk 268929)"} +!12 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !13, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!13 = !DISubroutineType(types: !14) +!14 = !{null, !15} +!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64, align: 32) +!16 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!17 = !DILocalVariable(name: "A", arg: 1, scope: !12, file: !1, line: 1, type: !15) +!18 = !DIExpression() +!19 = !DILocation(line: 1, column: 30, scope: !12) +!20 = !DILocation(line: 2, column: 3, scope: !12) +!21 = !DILocation(line: 2, column: 8, scope: !12) +!22 = !DILocation(line: 3, column: 3, scope: !12) +!23 = !DILocation(line: 3, column: 8, scope: !12) +!24 = !DILocation(line: 4, column: 3, scope: !12) +!25 = !DILocation(line: 4, column: 8, scope: !12) +!26 = !DILocation(line: 5, column: 1, scope: !12) diff --git a/test/CodeGen/AMDGPU/debugger-reserve-regs.ll b/test/CodeGen/AMDGPU/debugger-reserve-regs.ll new file mode 100644 index 000000000000..d30bb20bb03a --- /dev/null +++ b/test/CodeGen/AMDGPU/debugger-reserve-regs.ll @@ -0,0 +1,62 @@ +; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=+amdgpu-debugger-reserve-regs -verify-machineinstrs < %s | FileCheck %s +; CHECK: reserved_vgpr_first = {{[0-9]+}} +; CHECK-NEXT: reserved_vgpr_count = 4 +; CHECK: ReservedVGPRFirst: {{[0-9]+}} +; CHECK-NEXT: ReservedVGPRCount: 4 + +; Function Attrs: nounwind +define void @test(i32 addrspace(1)* %A) #0 !dbg !12 { +entry: + %A.addr = alloca i32 addrspace(1)*, align 4 + store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 + call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !17, metadata !18), !dbg !19 + %0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !20 + %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i32 0, !dbg !20 + store i32 1, i32 addrspace(1)* %arrayidx, align 4, !dbg !21 + %1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !22 + %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %1, i32 1, !dbg !22 + store i32 2, i32 addrspace(1)* %arrayidx1, align 4, !dbg !23 + %2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !24 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %2, i32 2, !dbg !24 + store i32 3, i32 addrspace(1)* %arrayidx2, align 4, !dbg !25 + ret void, !dbg !26 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!opencl.kernels = !{!3} +!llvm.module.flags = !{!9, !10} +!llvm.ident = !{!11} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (trunk 268929)", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "test01.cl", directory: "/home/kzhuravl/Lightning/testing") +!2 = !{} +!3 = !{void (i32 addrspace(1)*)* @test, !4, !5, !6, !7, !8} +!4 = !{!"kernel_arg_addr_space", i32 1} +!5 = !{!"kernel_arg_access_qual", !"none"} +!6 = !{!"kernel_arg_type", !"int*"} +!7 = !{!"kernel_arg_base_type", !"int*"} +!8 = !{!"kernel_arg_type_qual", !""} +!9 = !{i32 2, !"Dwarf Version", i32 2} +!10 = !{i32 2, !"Debug Info Version", i32 3} +!11 = !{!"clang version 3.9.0 (trunk 268929)"} +!12 = distinct !DISubprogram(name: "test", scope: !1, file: !1, line: 1, type: !13, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!13 = !DISubroutineType(types: !14) +!14 = !{null, !15} +!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 64, align: 32) +!16 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) +!17 = !DILocalVariable(name: "A", arg: 1, scope: !12, file: !1, line: 1, type: !15) +!18 = !DIExpression() +!19 = !DILocation(line: 1, column: 30, scope: !12) +!20 = !DILocation(line: 2, column: 3, scope: !12) +!21 = !DILocation(line: 2, column: 8, scope: !12) +!22 = !DILocation(line: 3, column: 3, scope: !12) +!23 = !DILocation(line: 3, column: 8, scope: !12) +!24 = !DILocation(line: 4, column: 3, scope: !12) +!25 = !DILocation(line: 4, column: 8, scope: !12) +!26 = !DILocation(line: 5, column: 1, scope: !12) diff --git a/test/CodeGen/AMDGPU/default-fp-mode.ll b/test/CodeGen/AMDGPU/default-fp-mode.ll index da8e91454b98..723e3c27ad6b 100644 --- a/test/CodeGen/AMDGPU/default-fp-mode.ll +++ b/test/CodeGen/AMDGPU/default-fp-mode.ll @@ -1,36 +1,62 @@ -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=FP32-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=BOTH-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=NO-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=+fp64-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=FP32-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=BOTH-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals,-fp64-denormals < %s | FileCheck -check-prefix=NO-DENORMAL -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp64-denormals < %s | FileCheck -check-prefix=DEFAULT -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -; FUNC-LABEL: {{^}}test_kernel: +; GCN-LABEL: {{^}}test_default_si: +; GCN: FloatMode: 192 +; GCN: IeeeMode: 0 +define void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} -; DEFAULT: FloatMode: 192 -; DEFAULT: IeeeMode: 0 +; GCN-LABEL: {{^}}test_default_vi: +; GCN: FloatMode: 192 +; GCN: IeeeMode: 0 +define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} -; FP64-DENORMAL: FloatMode: 192 -; FP64-DENORMAL: IeeeMode: 0 +; GCN-LABEL: {{^}}test_f64_denormals: +; GCN: FloatMode: 192 +; GCN: IeeeMode: 0 +define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} -; FP32-DENORMAL: FloatMode: 48 -; FP32-DENORMAL: IeeeMode: 0 +; GCN-LABEL: {{^}}test_f32_denormals: +; GCNL: FloatMode: 48 +; GCN: IeeeMode: 0 +define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} -; BOTH-DENORMAL: FloatMode: 240 -; BOTH-DENORMAL: IeeeMode: 0 +; GCN-LABEL: {{^}}test_f32_f64_denormals: +; GCN: FloatMode: 240 +; GCN: IeeeMode: 0 +define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} -; NO-DENORMAL: FloatMode: 0 -; NO-DENORMAL: IeeeMode: 0 -define void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind { +; GCN-LABEL: {{^}}test_no_denormals +; GCN: FloatMode: 0 +; GCN: IeeeMode: 0 +define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 { store float 0.0, float addrspace(1)* %out0 store double 0.0, double addrspace(1)* %out1 ret void } + +attributes #0 = { nounwind "target-cpu"="tahiti" } +attributes #1 = { nounwind "target-cpu"="fiji" } +attributes #2 = { nounwind "target-features"="+fp64-denormals" } +attributes #3 = { nounwind "target-features"="+fp32-denormals" } +attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" } +attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" } diff --git a/test/CodeGen/AMDGPU/detect-dead-lanes.mir b/test/CodeGen/AMDGPU/detect-dead-lanes.mir new file mode 100644 index 000000000000..f7f953c144da --- /dev/null +++ b/test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -0,0 +1,428 @@ +# RUN: llc -march=amdgcn -run-pass detect-dead-lanes -o - %s | FileCheck %s +--- | + define void @test0() { ret void } + define void @test1() { ret void } + define void @test2() { ret void } + define void @test3() { ret void } + define void @test4() { ret void } + define void @test5() { ret void } + define void @loop0() { ret void } + define void @loop1() { ret void } + define void @loop2() { ret void } +... +--- +# Combined use/def transfer check, the basics. +# CHECK-LABEL: name: test0 +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: S_NOP 0, implicit-def %1 +# CHECK: S_NOP 0, implicit-def dead %2 +# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %3:sub0 +# CHECK: S_NOP 0, implicit %3:sub1 +# CHECK: S_NOP 0, implicit undef %3:sub2 +# CHECK: %4 = COPY %3:sub0_sub1 +# CHECK: %5 = COPY undef %3:sub2_sub3 +# CHECK: S_NOP 0, implicit %4:sub0 +# CHECK: S_NOP 0, implicit %4:sub1 +# CHECK: S_NOP 0, implicit undef %5:sub0 +name: test0 +isSSA: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_32 } + - { id: 2, class: sreg_32 } + - { id: 3, class: sreg_128 } + - { id: 4, class: sreg_64 } + - { id: 5, class: sreg_64 } +body: | + bb.0: + S_NOP 0, implicit-def %0 + S_NOP 0, implicit-def %1 + S_NOP 0, implicit-def %2 + %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3 + S_NOP 0, implicit %3:sub0 + S_NOP 0, implicit %3:sub1 + S_NOP 0, implicit %3:sub2 + %4 = COPY %3:sub0_sub1 + %5 = COPY %3:sub2_sub3 + S_NOP 0, implicit %4:sub0 + S_NOP 0, implicit %4:sub1 + S_NOP 0, implicit %5:sub0 +... +--- +# Check defined lanes transfer; Includes checking for some special cases like +# undef operands or IMPLICIT_DEF definitions. +# CHECK-LABEL: name: test1 +# CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}} +# CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}} +# CHECK: %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %1:sub0 +# CHECK: S_NOP 0, implicit undef %1:sub1 +# CHECK: S_NOP 0, implicit %1:sub2 +# CHECK: S_NOP 0, implicit %1:sub3 +# CHECK: S_NOP 0, implicit %2:sub0 +# CHECK: S_NOP 0, implicit undef %2:sub1 + +# CHECK: %3 = IMPLICIT_DEF +# CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}} +# CHECK: S_NOP 0, implicit undef %4:sub0 +# CHECK: S_NOP 0, implicit undef %4:sub1 +# CHECK: S_NOP 0, implicit %4:sub2 +# CHECK: S_NOP 0, implicit undef %4:sub3 + +# CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}} +# CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}} +# CHECK: %7 = EXTRACT_SUBREG %5, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %5 +# CHECK: S_NOP 0, implicit %6 +# CHECK: S_NOP 0, implicit undef %7 + +# CHECK: %8 = IMPLICIT_DEF +# CHECK: %9 = EXTRACT_SUBREG undef %8, {{[0-9]+}} +# CHECK: S_NOP 0, implicit undef %9 + +# CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}} +# CHECK: S_NOP 0, implicit undef %10 +name: test1 +isSSA: true +registers: + - { id: 0, class: sreg_128 } + - { id: 1, class: sreg_128 } + - { id: 2, class: sreg_64 } + - { id: 3, class: sreg_32 } + - { id: 4, class: sreg_128 } + - { id: 5, class: sreg_64 } + - { id: 6, class: sreg_32 } + - { id: 7, class: sreg_32 } + - { id: 8, class: sreg_64 } + - { id: 9, class: sreg_32 } + - { id: 10, class: sreg_128 } +body: | + bb.0: + %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2 + %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3 + %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0 + S_NOP 0, implicit %1:sub0 + S_NOP 0, implicit %1:sub1 + S_NOP 0, implicit %1:sub2 + S_NOP 0, implicit %1:sub3 + S_NOP 0, implicit %2:sub0 + S_NOP 0, implicit %2:sub1 + + %3 = IMPLICIT_DEF + %4 = INSERT_SUBREG %0, %3, %subreg.sub0 + S_NOP 0, implicit %4:sub0 + S_NOP 0, implicit %4:sub1 + S_NOP 0, implicit %4:sub2 + S_NOP 0, implicit %4:sub3 + + %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1 + %6 = EXTRACT_SUBREG %5, %subreg.sub0 + %7 = EXTRACT_SUBREG %5, %subreg.sub1 + S_NOP 0, implicit %5 + S_NOP 0, implicit %6 + S_NOP 0, implicit %7 + + %8 = IMPLICIT_DEF + %9 = EXTRACT_SUBREG %8, %subreg.sub1 + S_NOP 0, implicit %9 + + %10 = EXTRACT_SUBREG undef %0, %subreg.sub2_sub3 + S_NOP 0, implicit %10 +... +--- +# Check used lanes transfer; Includes checking for some special cases like +# undef operands. +# CHECK-LABEL: name: test2 +# CHECK: S_NOP 0, implicit-def dead %0 +# CHECK: S_NOP 0, implicit-def %1 +# CHECK: S_NOP 0, implicit-def %2 +# CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %3:sub1 +# CHECK: S_NOP 0, implicit %3:sub3 + +# CHECK: S_NOP 0, implicit-def %4 +# CHECK: S_NOP 0, implicit-def dead %5 +# CHECK: %6 = REG_SEQUENCE %4, {{[0-9]+}}, undef %5, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %6 + +# CHECK: S_NOP 0, implicit-def dead %7 +# CHECK: S_NOP 0, implicit-def %8 +# CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %9:sub2 + +# CHECK: S_NOP 0, implicit-def %10 +# CHECK: S_NOP 0, implicit-def dead %11 +# CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %12:sub3 + +# CHECK: S_NOP 0, implicit-def %13 +# CHECK: S_NOP 0, implicit-def dead %14 +# CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}} +# CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %16:sub1 + +name: test2 +isSSA: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_32 } + - { id: 2, class: sreg_64 } + - { id: 3, class: sreg_128 } + - { id: 4, class: sreg_32 } + - { id: 5, class: sreg_32 } + - { id: 6, class: sreg_64 } + - { id: 7, class: sreg_128 } + - { id: 8, class: sreg_64 } + - { id: 9, class: sreg_128 } + - { id: 10, class: sreg_128 } + - { id: 11, class: sreg_64 } + - { id: 12, class: sreg_128 } + - { id: 13, class: sreg_64 } + - { id: 14, class: sreg_64 } + - { id: 15, class: sreg_128 } + - { id: 16, class: sreg_64 } +body: | + bb.0: + S_NOP 0, implicit-def %0 + S_NOP 0, implicit-def %1 + S_NOP 0, implicit-def %2 + %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3 + S_NOP 0, implicit %3:sub1 + S_NOP 0, implicit %3:sub3 + + S_NOP 0, implicit-def %4 + S_NOP 0, implicit-def %5 + %6 = REG_SEQUENCE %4, %subreg.sub0, undef %5, %subreg.sub1 + S_NOP 0, implicit %6 + + S_NOP 0, implicit-def %7 + S_NOP 0, implicit-def %8 + %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3 + S_NOP 0, implicit %9:sub2 + + S_NOP 0, implicit-def %10 + S_NOP 0, implicit-def %11 + %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1 + S_NOP 0, implicit %12:sub3 + + S_NOP 0, implicit-def %13 + S_NOP 0, implicit-def %14 + %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3 + %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1 + S_NOP 0, implicit %16:sub1 +... +--- +# Check that copies to physregs use all lanes, copies from physregs define all +# lanes. So we should not get a dead/undef flag here. +# CHECK-LABEL: name: test3 +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: %vcc = COPY %0 +# CHECK: %1 = COPY %vcc +# CHECK: S_NOP 0, implicit %1 +name: test3 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_64 } + - { id: 1, class: sreg_64 } +body: | + bb.0: + S_NOP 0, implicit-def %0 + %vcc = COPY %0 + + %1 = COPY %vcc + S_NOP 0, implicit %1 +... +--- +# Check that implicit-def/kill do not count as def/uses. +# CHECK-LABEL: name: test4 +# CHECK: S_NOP 0, implicit-def dead %0 +# CHECK: KILL undef %0 +# CHECK: %1 = IMPLICIT_DEF +# CHECK: S_NOP 0, implicit undef %1 +name: test4 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_64 } + - { id: 1, class: sreg_64 } +body: | + bb.0: + S_NOP 0, implicit-def %0 + KILL %0 + + %1 = IMPLICIT_DEF + S_NOP 0, implicit %1 +... +--- +# Check that unused inputs are marked as undef, even if the vreg itself is +# used. +# CHECK-LABEL: name: test5 +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}} +# CHECK: S_NOP 0, implicit %1:sub1 +name: test5 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_64 } +body: | + bb.0: + S_NOP 0, implicit-def %0 + %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1 + S_NOP 0, implicit %1:sub1 +... +--- +# Check "optimistic" dataflow fixpoint in phi-loops. +# CHECK-LABEL: name: loop0 +# CHECK: bb.0: +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: S_NOP 0, implicit-def dead %1 +# CHECK: S_NOP 0, implicit-def dead %2 +# CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, undef %1, {{[0-9]+}}, undef %2, {{[0-9]+}} + +# CHECK: bb.1: +# CHECK: %4 = PHI %3, %bb.0, %5, %bb.1 + +# CHECK: bb.2: +# CHECK: S_NOP 0, implicit %4:sub0 +# CHECK: S_NOP 0, implicit undef %4:sub3 +name: loop0 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_32 } + - { id: 2, class: sreg_32 } + - { id: 3, class: sreg_128 } + - { id: 4, class: sreg_128 } + - { id: 5, class: sreg_128 } +body: | + bb.0: + successors: %bb.1 + S_NOP 0, implicit-def %0 + S_NOP 0, implicit-def %1 + S_NOP 0, implicit-def %2 + %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2 + S_BRANCH %bb.1 + + bb.1: + successors: %bb.1, %bb.2 + %4 = PHI %3, %bb.0, %5, %bb.1 + + ; let's swiffle some lanes around for fun... + %5 = REG_SEQUENCE %4:sub0, %subreg.sub0, %4:sub2, %subreg.sub1, %4:sub1, %subreg.sub2, %4:sub3, %subreg.sub3 + + S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc + S_BRANCH %bb.2 + + bb.2: + S_NOP 0, implicit %4:sub0 + S_NOP 0, implicit %4:sub3 +... +--- +# Check a loop that needs to be traversed multiple times to reach the fixpoint +# for the used lanes. The example reads sub3 lane at the end, however with each +# loop iteration we should get 1 more lane marked as we cycles the sublanes +# along. Sublanes sub0, sub1 and sub3 are rotate in the loop so only sub2 +# should be dead. +# CHECK-LABEL: name: loop1 +# CHECK: bb.0: +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: S_NOP 0, implicit-def %1 +# CHECK: S_NOP 0, implicit-def dead %2 +# CHECK: S_NOP 0, implicit-def %3 +# CHECK: %4 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}, %3, {{[0-9]+}} + +# CHECK: bb.1: +# CHECK: %5 = PHI %4, %bb.0, %6, %bb.1 + +# CHECK: %6 = REG_SEQUENCE %5:sub1, {{[0-9]+}}, %5:sub3, {{[0-9]+}}, undef %5:sub2, {{[0-9]+}}, %5:sub0, {{[0-9]+}} + +# CHECK: bb.2: +# CHECK: S_NOP 0, implicit %6:sub3 +name: loop1 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_32 } + - { id: 2, class: sreg_32 } + - { id: 3, class: sreg_32 } + - { id: 4, class: sreg_128 } + - { id: 5, class: sreg_128 } + - { id: 6, class: sreg_128 } +body: | + bb.0: + successors: %bb.1 + S_NOP 0, implicit-def %0 + S_NOP 0, implicit-def %1 + S_NOP 0, implicit-def dead %2 + S_NOP 0, implicit-def %3 + %4 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3 + S_BRANCH %bb.1 + + bb.1: + successors: %bb.1, %bb.2 + %5 = PHI %4, %bb.0, %6, %bb.1 + + ; rotate lanes, but skip sub2 lane... + %6 = REG_SEQUENCE %5:sub1, %subreg.sub0, %5:sub3, %subreg.sub1, %5:sub2, %subreg.sub2, %5:sub0, %subreg.sub3 + + S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc + S_BRANCH %bb.2 + + bb.2: + S_NOP 0, implicit %6:sub3 +... +--- +# Similar to loop1 test, but check for fixpoint of defined lanes. +# Lanes are rotate between sub0, sub2, sub3 so only sub1 should be dead/undef. +# CHECK-LABEL: name: loop2 +# CHECK: bb.0: +# CHECK: S_NOP 0, implicit-def %0 +# CHECK: %1 = REG_SEQUENCE %0, {{[0-9]+}} + +# CHECK: bb.1: +# CHECK: %2 = PHI %1, %bb.0, %3, %bb.1 + +# CHECK: %3 = REG_SEQUENCE %2:sub3, {{[0-9]+}}, undef %2:sub1, {{[0-9]+}}, %2:sub0, {{[0-9]+}}, %2:sub2, {{[0-9]+}} + +# CHECK: bb.2: +# CHECK: S_NOP 0, implicit %2:sub0 +# CHECK: S_NOP 0, implicit undef %2:sub1 +# CHECK: S_NOP 0, implicit %2:sub2 +# CHECK: S_NOP 0, implicit %2:sub3 +name: loop2 +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: sreg_32 } + - { id: 1, class: sreg_128 } + - { id: 2, class: sreg_128 } + - { id: 3, class: sreg_128 } +body: | + bb.0: + successors: %bb.1 + S_NOP 0, implicit-def %0 + %1 = REG_SEQUENCE %0, %subreg.sub0 + S_BRANCH %bb.1 + + bb.1: + successors: %bb.1, %bb.2 + %2 = PHI %1, %bb.0, %3, %bb.1 + + ; rotate subreg lanes, skipping sub1 + %3 = REG_SEQUENCE %2:sub3, %subreg.sub0, %2:sub1, %subreg.sub1, %2:sub0, %subreg.sub2, %2:sub2, %subreg.sub3 + + S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc + S_BRANCH %bb.2 + + bb.2: + S_NOP 0, implicit %2:sub0 + S_NOP 0, implicit undef %2:sub1 + S_NOP 0, implicit %2:sub2 + S_NOP 0, implicit %2:sub3 +... diff --git a/test/CodeGen/AMDGPU/dot4-folding.ll b/test/CodeGen/AMDGPU/dot4-folding.ll deleted file mode 100644 index 4df7b63bf98e..000000000000 --- a/test/CodeGen/AMDGPU/dot4-folding.ll +++ /dev/null @@ -1,27 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; Exactly one constant vector can be folded into dot4, which means exactly -; 4 MOV instructions -; CHECK: {{^}}main: -; CHECK: MOV -; CHECK: MOV -; CHECK: MOV -; CHECK: MOV -; CHECK-NOT: MOV -; CHECK-NOT: MOV -; CHECK-NOT: MOV -; CHECK-NOT: MOV - -define void @main(float addrspace(1)* %out) { -main_body: - %0 = load <4 x float>, <4 x float> addrspace(8)* null - %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %2 = call float @llvm.AMDGPU.dp4(<4 x float> %0,<4 x float> %1) - %3 = insertelement <4 x float> undef, float %2, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %3, i32 0, i32 0) - ret void -} - -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) -attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll b/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll index 171883e4c74b..5e1ebfde3e10 100644 --- a/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll +++ b/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll @@ -7,12 +7,11 @@ ; GCN-LABEL: {{^}}reschedule_global_load_lds_store: ; GCN: buffer_load_dword ; GCN: buffer_load_dword -; GCN: ds_write_b32 -; GCN: ds_write_b32 +; GCN: ds_write2_b32 ; GCN: s_endpgm define void @reschedule_global_load_lds_store(i32 addrspace(1)* noalias %gptr0, i32 addrspace(1)* noalias %gptr1, i32 addrspace(3)* noalias %lptr, i32 %c) #0 { entry: - %tid = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx = shl i32 %tid, 2 %gep0 = getelementptr i32, i32 addrspace(1)* %gptr0, i32 %idx %gep1 = getelementptr i32, i32 addrspace(1)* %gptr1, i32 %idx @@ -25,7 +24,7 @@ for.body: ; preds = %for.body, %entry %gptr0.phi = phi i32 addrspace(1)* [ %gep0, %entry ], [ %gep0.inc, %for.body ] %gptr1.phi = phi i32 addrspace(1)* [ %gep1, %entry ], [ %gep1.inc, %for.body ] %lptr0.phi = phi i32 addrspace(3)* [ %gep2, %entry ], [ %gep2.inc, %for.body ] - %lptr1 = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 1 + %lptr1 = getelementptr i32, i32 addrspace(3)* %lptr0.phi, i32 2 %val0 = load i32, i32 addrspace(1)* %gep0 store i32 %val0, i32 addrspace(3)* %lptr0.phi %val1 = load i32, i32 addrspace(1)* %gep1 @@ -42,10 +41,7 @@ exit: ; preds = %for.body, %entry } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll b/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll index e657991557e3..f461d6978f13 100644 --- a/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll +++ b/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll @@ -1,31 +1,31 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s +; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=SI --check-prefix=CHECK %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s +; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt,+unsafe-ds-offset-folding < %s | FileCheck -check-prefix=CI --check-prefix=CHECK %s -declare i32 @llvm.r600.read.tidig.x() #0 -declare void @llvm.AMDGPU.barrier.local() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare void @llvm.amdgcn.s.barrier() #1 ; Function Attrs: nounwind ; CHECK-LABEL: {{^}}signed_ds_offset_addressing_loop: ; CHECK: BB0_1: ; CHECK: v_add_i32_e32 [[VADDR:v[0-9]+]], ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] -; SI-DAG: v_add_i32_e32 [[VADDR4:v[0-9]+]], vcc, 4, [[VADDR]] -; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR4]] +; SI-DAG: v_add_i32_e32 [[VADDR8:v[0-9]+]], vcc, 8, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR8]] ; SI-DAG: v_add_i32_e32 [[VADDR0x80:v[0-9]+]], vcc, 0x80, [[VADDR]] ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x80]] -; SI-DAG: v_add_i32_e32 [[VADDR0x84:v[0-9]+]], vcc, 0x84, [[VADDR]] -; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x84]] +; SI-DAG: v_add_i32_e32 [[VADDR0x88:v[0-9]+]], vcc, 0x88, [[VADDR]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x88]] ; SI-DAG: v_add_i32_e32 [[VADDR0x100:v[0-9]+]], vcc, 0x100, [[VADDR]] ; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR0x100]] -; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:1 -; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:33 +; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset1:2 +; CI-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[VADDR]] offset0:32 offset1:34 ; CI-DAG: ds_read_b32 v{{[0-9]+}}, [[VADDR]] offset:256 ; CHECK: s_endpgm define void @signed_ds_offset_addressing_loop(float addrspace(1)* noalias nocapture %out, float addrspace(3)* noalias nocapture readonly %lptr, i32 %n) #2 { entry: - %x.i = tail call i32 @llvm.r600.read.tidig.x() #0 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %mul = shl nsw i32 %x.i, 1 br label %for.body @@ -33,16 +33,16 @@ for.body: ; preds = %for.body, %entry %sum.03 = phi float [ 0.000000e+00, %entry ], [ %add13, %for.body ] %offset.02 = phi i32 [ %mul, %entry ], [ %add14, %for.body ] %k.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - tail call void @llvm.AMDGPU.barrier.local() #1 + tail call void @llvm.amdgcn.s.barrier() #1 %arrayidx = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %offset.02 %tmp = load float, float addrspace(3)* %arrayidx, align 4 - %add1 = add nsw i32 %offset.02, 1 + %add1 = add nsw i32 %offset.02, 2 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add1 %tmp1 = load float, float addrspace(3)* %arrayidx2, align 4 %add3 = add nsw i32 %offset.02, 32 %arrayidx4 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add3 %tmp2 = load float, float addrspace(3)* %arrayidx4, align 4 - %add5 = add nsw i32 %offset.02, 33 + %add5 = add nsw i32 %offset.02, 34 %arrayidx6 = getelementptr inbounds float, float addrspace(3)* %lptr, i32 %add5 %tmp3 = load float, float addrspace(3)* %arrayidx6, align 4 %add7 = add nsw i32 %offset.02, 64 @@ -67,4 +67,4 @@ for.end: ; preds = %for.body attributes #0 = { nounwind readnone } attributes #1 = { convergent nounwind } -attributes #2 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AMDGPU/ds-sub-offset.ll b/test/CodeGen/AMDGPU/ds-sub-offset.ll index 7d6eddb01993..16fb019ae0f3 100644 --- a/test/CodeGen/AMDGPU/ds-sub-offset.ll +++ b/test/CodeGen/AMDGPU/ds-sub-offset.ll @@ -1,7 +1,6 @@ ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s -declare void @llvm.AMDGPU.barrier.local() #2 -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 @lds.obj = addrspace(3) global [256 x i32] undef, align 4 @@ -12,7 +11,7 @@ declare i32 @llvm.r600.read.tidig.x() #0 ; GCN: ds_write_b32 [[BASEPTR]], [[VAL]] offset:12 define void @write_ds_sub0_offset0_global() #0 { entry: - %x.i = call i32 @llvm.r600.read.tidig.x() #1 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 %sub1 = sub i32 0, %x.i %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 @@ -26,7 +25,7 @@ entry: ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN: ds_write_b8 [[NEG]], [[K]] offset:65535 define void @add_x_shl_neg_to_sub_max_offset() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add = add i32 65535, %shl @@ -41,7 +40,7 @@ define void @add_x_shl_neg_to_sub_max_offset() #1 { ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 13 ; GCN: ds_write_b8 [[NEG]], [[K]]{{$}} define void @add_x_shl_neg_to_sub_max_offset_p1() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add = add i32 65536, %shl @@ -60,7 +59,7 @@ define void @add_x_shl_neg_to_sub_max_offset_p1() #1 { ; GCN: ds_write_b32 [[NEG]], [[K]] offset:456{{$}} ; GCN: s_endpgm define void @add_x_shl_neg_to_sub_multi_use() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add0 = add i32 123, %shl @@ -82,7 +81,7 @@ define void @add_x_shl_neg_to_sub_multi_use() #1 { ; GCN: ds_write_b32 [[NEG]], [[K]] offset:123{{$}} ; GCN: s_endpgm define void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add = add i32 123, %shl @@ -97,7 +96,7 @@ define void @add_x_shl_neg_to_sub_multi_use_same_offset() #1 { ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SCALED]] ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset0:254 offset1:255 define void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add = add i32 1019, %shl @@ -111,7 +110,7 @@ define void @add_x_shl_neg_to_sub_misaligned_i64_max_offset() #1 { ; GCN-DAG: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0x3fc, [[SCALED]] ; GCN: ds_write2_b32 [[NEG]], {{v[0-9]+}}, {{v[0-9]+}} offset1:1{{$}} define void @add_x_shl_neg_to_sub_misaligned_i64_max_offset_p1() #1 { - %x.i = call i32 @llvm.r600.read.tidig.x() #0 + %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %neg = sub i32 0, %x.i %shl = shl i32 %neg, 2 %add = add i32 1020, %shl diff --git a/test/CodeGen/AMDGPU/ds_read2.ll b/test/CodeGen/AMDGPU/ds_read2.ll index 5170d9c82712..6e30cff9609d 100644 --- a/test/CodeGen/AMDGPU/ds_read2.ll +++ b/test/CodeGen/AMDGPU/ds_read2.ll @@ -13,7 +13,7 @@ ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @simple_read2_f32(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -32,7 +32,7 @@ define void @simple_read2_f32(float addrspace(1)* %out) #0 { ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 255 @@ -50,7 +50,7 @@ define void @simple_read2_f32_max_offset(float addrspace(1)* %out) #0 { ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 ; SI: s_endpgm define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 257 @@ -67,7 +67,7 @@ define void @simple_read2_f32_too_far(float addrspace(1)* %out) #0 { ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 ; SI: s_endpgm define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 0 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -99,7 +99,7 @@ define void @simple_read2_f32_x2(float addrspace(1)* %out) #0 { ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 ; SI: s_endpgm define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 0 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -109,7 +109,7 @@ define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 { %val1 = load float, float addrspace(3)* %arrayidx1, align 4 %sum.0 = fadd float %val0, %val1 - call void @llvm.AMDGPU.barrier.local() #2 + call void @llvm.amdgcn.s.barrier() #2 %idx.2 = add nsw i32 %tid.x, 11 %arrayidx2 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.2 @@ -134,7 +134,7 @@ define void @simple_read2_f32_x2_barrier(float addrspace(1)* %out) #0 { ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, [[BASEADDR]] offset0:11 offset1:27 ; SI: s_endpgm define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -171,7 +171,7 @@ define void @simple_read2_f32_x2_nonzero_base(float addrspace(1)* %out) #0 { ; SI: ds_read_b32 ; SI: s_endpgm define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0 %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1 @@ -197,7 +197,7 @@ define void @read2_ptr_is_subreg_arg_f32(float addrspace(1)* %out, <2 x float ad ; SI: ds_read_b32 ; SI: s_endpgm define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x float addrspace(3)*> %lds.ptr) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %index.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 %index.1 = insertelement <2 x i32> %index.0, i32 8, i32 0 %gep = getelementptr inbounds float, <2 x float addrspace(3)*> %lds.ptr, <2 x i32> %index.1 @@ -220,7 +220,7 @@ define void @read2_ptr_is_subreg_arg_offset_f32(float addrspace(1)* %out, <2 x f ; SI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset1:8{{$}} ; SI: s_endpgm define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %ptr.0 = insertelement <2 x [512 x float] addrspace(3)*> undef, [512 x float] addrspace(3)* @lds, i32 0 %ptr.1 = insertelement <2 x [512 x float] addrspace(3)*> %ptr.0, [512 x float] addrspace(3)* @lds, i32 1 %x.i.v.0 = insertelement <2 x i32> undef, i32 %x.i, i32 0 @@ -244,7 +244,7 @@ define void @read2_ptr_is_subreg_f32(float addrspace(1)* %out) #0 { ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 ; SI: s_endpgm define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load volatile float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -262,7 +262,7 @@ define void @simple_read2_f32_volatile_0(float addrspace(1)* %out) #0 { ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:32 ; SI: s_endpgm define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -281,7 +281,7 @@ define void @simple_read2_f32_volatile_1(float addrspace(1)* %out) #0 { ; SI-NOT: ds_read2_b32 ; SI: s_endpgm define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 1 %add.x = add nsw i32 %x.i, 8 @@ -297,7 +297,7 @@ define void @unaligned_read2_f32(float addrspace(1)* %out, float addrspace(3)* % ; SI-NOT: ds_read2_b32 ; SI: s_endpgm define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 2 %add.x = add nsw i32 %x.i, 8 @@ -316,7 +316,7 @@ define void @misaligned_2_simple_read2_f32(float addrspace(1)* %out, float addrs ; SI: buffer_store_dwordx2 [[RESULT]] ; SI: s_endpgm define void @simple_read2_f64(double addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 8 @@ -332,7 +332,7 @@ define void @simple_read2_f64(double addrspace(1)* %out) #0 { ; SI: ds_read2_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:255 ; SI: s_endpgm define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 255 @@ -350,7 +350,7 @@ define void @simple_read2_f64_max_offset(double addrspace(1)* %out) #0 { ; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:2056 ; SI: s_endpgm define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 257 @@ -368,7 +368,7 @@ define void @simple_read2_f64_too_far(double addrspace(1)* %out) #0 { ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:14 offset1:15 ; SI: s_endpgm define void @misaligned_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 7 @@ -438,8 +438,8 @@ define void @load_misaligned64_constant_large_offsets(i64 addrspace(1)* %out) { @sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4 define void @sgemm_inner_loop_read2_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb) #0 { - %x.i = tail call i32 @llvm.r600.read.tgid.x() #1 - %y.i = tail call i32 @llvm.r600.read.tidig.y() #1 + %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1 + %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #1 %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i %tmp16 = load float, float addrspace(3)* %arrayidx44, align 4 %add47 = add nsw i32 %x.i, 1 @@ -494,20 +494,20 @@ define void @misaligned_read2_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %in) } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 +declare i32 @llvm.amdgcn.workgroup.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.y() #1 +declare i32 @llvm.amdgcn.workgroup.id.y() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 +declare i32 @llvm.amdgcn.workitem.id.y() #1 ; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 +declare void @llvm.amdgcn.s.barrier() #2 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/ds_read2_offset_order.ll b/test/CodeGen/AMDGPU/ds_read2_offset_order.ll index d362c46bbf96..57e190e0cca0 100644 --- a/test/CodeGen/AMDGPU/ds_read2_offset_order.ll +++ b/test/CodeGen/AMDGPU/ds_read2_offset_order.ll @@ -8,9 +8,8 @@ ; SI-LABEL: {{^}}offset_order: -; SI: ds_read2st64_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset1:4{{$}} -; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:3 offset1:2 -; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:12 offset1:14 +; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:2 offset1:3 +; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:14 offset1:12 ; SI: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:44 define void @offset_order(float addrspace(1)* %out) { diff --git a/test/CodeGen/AMDGPU/ds_read2_superreg.ll b/test/CodeGen/AMDGPU/ds_read2_superreg.ll index 0061aaf2cdbd..9d8375d64037 100644 --- a/test/CodeGen/AMDGPU/ds_read2_superreg.ll +++ b/test/CodeGen/AMDGPU/ds_read2_superreg.ll @@ -13,7 +13,7 @@ ; CI: buffer_store_dwordx2 [[RESULT]] ; CI: s_endpgm define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i @@ -27,7 +27,7 @@ define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) ; CI: buffer_store_dwordx2 [[RESULT]] ; CI: s_endpgm define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i @@ -44,7 +44,7 @@ define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 { ; CI: buffer_store_dword v[[ADD2]] ; CI: s_endpgm define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4 %elt0 = extractelement <4 x float> %val0, i32 0 @@ -69,7 +69,7 @@ define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 { ; CI: buffer_store_dword v[[ADD1]] ; CI: s_endpgm define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4 %elt0 = extractelement <3 x float> %val0, i32 0 @@ -85,17 +85,11 @@ define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 { } ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8: -; CI-DAG: ds_read2_b64 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}} - -; FIXME: These moves shouldn't be necessary, it should be able to -; store the same register if offset1 was the non-zero offset. - -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: buffer_store_dwordx4 +; CI: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} +; CI: buffer_store_dwordx4 [[REG_ZW]] ; CI: s_endpgm define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i @@ -104,13 +98,11 @@ define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) } ; CI-LABEL: {{^}}simple_read2_v4f32_superreg: -; CI: ds_read2_b64 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: buffer_store_dwordx4 +; CI-DAG: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} +; CI: buffer_store_dwordx4 [[REG_ZW]] ; CI: s_endpgm define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i @@ -120,17 +112,13 @@ define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 { ; FIXME: Extra moves shuffling superregister ; CI-LABEL: {{^}}simple_read2_v8f32_superreg: -; CI: ds_read2_b64 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT7:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:3{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: ds_read2_b64 v{{\[}}[[REG_ELT6:[0-9]+]]:[[REG_ELT5:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: buffer_store_dwordx4 -; CI: buffer_store_dwordx4 +; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} +; CI-DAG: ds_read2_b64 [[VEC_LO:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} +; CI-DAG: buffer_store_dwordx4 [[VEC_HI]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16 +; CI-DAG: buffer_store_dwordx4 [[VEC_LO]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}} ; CI: s_endpgm define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i %val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0 %out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i @@ -140,25 +128,18 @@ define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 { ; FIXME: Extra moves shuffling superregister ; CI-LABEL: {{^}}simple_read2_v16f32_superreg: -; CI: ds_read2_b64 v{{\[}}[[REG_ELT11:[0-9]+]]:[[REG_ELT15:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:3{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: ds_read2_b64 v{{\[}}[[REG_ELT14:[0-9]+]]:[[REG_ELT13:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:7{{$}} -; CI: ds_read2_b64 v{{\[}}[[REG_ELT14:[0-9]+]]:[[REG_ELT13:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:6 offset1:4{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 -; CI: ds_read2_b64 v{{\[}}[[REG_ELT12:[0-9]+]]:[[REG_ELT10:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2{{$}} -; CI: v_mov_b32 -; CI: v_mov_b32 - +; CI-DAG: ds_read2_b64 [[VEC0_3:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}} +; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}} +; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}} +; CI-DAG: ds_read2_b64 [[VEC12_15:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:6 offset1:7{{$}} ; CI: s_waitcnt lgkmcnt(0) -; CI: buffer_store_dwordx4 -; CI: buffer_store_dwordx4 -; CI: buffer_store_dwordx4 -; CI: buffer_store_dwordx4 +; CI-DAG: buffer_store_dwordx4 [[VEC0_3]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64{{$}} +; CI-DAG: buffer_store_dwordx4 [[VEC4_7]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16 +; CI-DAG: buffer_store_dwordx4 [[VEC8_11]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32 +; CI-DAG: buffer_store_dwordx4 [[VEC12_15]], v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48 ; CI: s_endpgm define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i %val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0 %out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i @@ -173,7 +154,7 @@ define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 { ; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}} ; CI: s_endpgm define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 @@ -196,7 +177,7 @@ define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspa ; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}} ; CI: s_endpgm define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2 @@ -218,20 +199,11 @@ define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspa } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.y() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 - -; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 +declare i32 @llvm.amdgcn.workitem.id.y() #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/ds_read2st64.ll b/test/CodeGen/AMDGPU/ds_read2st64.ll index 4a0571ea16f2..7a8a206033ba 100644 --- a/test/CodeGen/AMDGPU/ds_read2st64.ll +++ b/test/CodeGen/AMDGPU/ds_read2st64.ll @@ -11,7 +11,7 @@ ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 64 @@ -30,7 +30,7 @@ define void @simple_read2st64_f32_0_1(float addrspace(1)* %out) #0 { ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -44,13 +44,13 @@ define void @simple_read2st64_f32_1_2(float addrspace(1)* %out, float addrspace( } ; SI-LABEL: @simple_read2st64_f32_max_offset -; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1 offset1:255 +; SI: ds_read2st64_b32 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:255 offset1:1 ; SI: s_waitcnt lgkmcnt(0) -; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[HI_VREG]], v[[LO_VREG]] +; SI: v_add_f32_e32 [[RESULT:v[0-9]+]], v[[LO_VREG]], v[[HI_VREG]] ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -65,12 +65,12 @@ define void @simple_read2st64_f32_max_offset(float addrspace(1)* %out, float add ; SI-LABEL: @simple_read2st64_f32_over_max_offset ; SI-NOT: ds_read2st64_b32 -; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} -; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 -; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]] +; SI-DAG: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} +; SI-DAG: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256 +; SI-DAG: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]{{$}} ; SI: s_endpgm define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -87,7 +87,7 @@ define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, floa ; SI-NOT: ds_read2st64_b32 ; SI: s_endpgm define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %val0 = load float, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 63 @@ -103,7 +103,7 @@ define void @odd_invalid_read2st64_f32_0(float addrspace(1)* %out) #0 { ; SI-NOT: ds_read2st64_b32 ; SI: s_endpgm define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -123,7 +123,7 @@ define void @odd_invalid_read2st64_f32_1(float addrspace(1)* %out) #0 { ; SI: buffer_store_dwordx2 [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 64 @@ -142,7 +142,7 @@ define void @simple_read2st64_f64_0_1(double addrspace(1)* %out) #0 { ; SI: buffer_store_dwordx2 [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %val0 = load double, double addrspace(3)* %arrayidx0, align 8 @@ -162,7 +162,7 @@ define void @simple_read2st64_f64_1_2(double addrspace(1)* %out, double addrspac ; SI: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:128 offset1:129 ; SI: s_endpgm define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 64 @@ -176,13 +176,13 @@ define void @misaligned_read2st64_f64(double addrspace(1)* %out, double addrspac ; The maximum is not the usual 0xff because 0xff * 8 * 64 > 0xffff ; SI-LABEL: @simple_read2st64_f64_max_offset -; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:4 offset1:127 +; SI: ds_read2st64_b64 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:127 offset1:4 ; SI: s_waitcnt lgkmcnt(0) -; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO_VREG]]:{{[0-9]+\]}}, v{{\[[0-9]+}}:[[HI_VREG]]{{\]}} +; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+}}:[[HI_VREG]]{{\]}}, v{{\[}}[[LO_VREG]]:{{[0-9]+\]}} ; SI: buffer_store_dwordx2 [[RESULT]] ; SI: s_endpgm define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 256 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %val0 = load double, double addrspace(3)* %arrayidx0, align 8 @@ -197,12 +197,12 @@ define void @simple_read2st64_f64_max_offset(double addrspace(1)* %out, double a ; SI-LABEL: @simple_read2st64_f64_over_max_offset ; SI-NOT: ds_read2st64_b64 -; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} ; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset:512 +; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], vcc, 0x10000, {{v[0-9]+}} ; SI: ds_read_b64 {{v\[[0-9]+:[0-9]+\]}}, [[BIGADD]] ; SI: s_endpgm define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %val0 = load double, double addrspace(3)* %arrayidx0, align 8 @@ -219,7 +219,7 @@ define void @simple_read2st64_f64_over_max_offset(double addrspace(1)* %out, dou ; SI-NOT: ds_read2st64_b64 ; SI: s_endpgm define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %add.x.0 = add nsw i32 %x.i, 64 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 %val0 = load double, double addrspace(3)* %arrayidx0, align 8 @@ -240,7 +240,7 @@ define void @invalid_read2st64_f64_odd_offset(double addrspace(1)* %out, double ; SI: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:8 ; SI: s_endpgm define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i %val0 = load double, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 8 @@ -253,16 +253,10 @@ define void @byte_size_only_divisible_64_read2_f64(double addrspace(1)* %out, do } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.y() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 +declare i32 @llvm.amdgcn.workitem.id.y() #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/ds_write2.ll b/test/CodeGen/AMDGPU/ds_write2.ll index 9d3a293f3b89..45fcc01b2add 100644 --- a/test/CodeGen/AMDGPU/ds_write2.ll +++ b/test/CodeGen/AMDGPU/ds_write2.ll @@ -10,7 +10,7 @@ ; SI: ds_write2_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:8 ; SI: s_endpgm define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i %val = load float, float addrspace(1)* %in.gep, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -28,11 +28,11 @@ define void @simple_write2_one_val_f32(float addrspace(1)* %C, float addrspace(1 ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 ; SI: s_endpgm define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %val0 = load float, float addrspace(1)* %in.gep.0, align 4 - %val1 = load float, float addrspace(1)* %in.gep.1, align 4 + %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i store float %val0, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -47,11 +47,11 @@ define void @simple_write2_two_val_f32(float addrspace(1)* %C, float addrspace(1 ; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 ; SI: s_endpgm define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i - %val0 = load float, float addrspace(1)* %in0.gep, align 4 - %val1 = load float, float addrspace(1)* %in1.gep, align 4 + %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 + %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i store volatile float %val0, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -66,11 +66,11 @@ define void @simple_write2_two_val_f32_volatile_0(float addrspace(1)* %C, float ; SI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:32 ; SI: s_endpgm define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i - %val0 = load float, float addrspace(1)* %in0.gep, align 4 - %val1 = load float, float addrspace(1)* %in1.gep, align 4 + %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 + %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i store float %val0, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 8 @@ -87,11 +87,11 @@ define void @simple_write2_two_val_f32_volatile_1(float addrspace(1)* %C, float ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 ; SI: s_endpgm define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1 - %val0 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8 - %val1 = load <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8 + %val0 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8 + %val1 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8 %val0.0 = extractelement <2 x float> %val0, i32 0 %val1.1 = extractelement <2 x float> %val1, i32 1 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -108,7 +108,7 @@ define void @simple_write2_two_val_subreg2_mixed_f32(float addrspace(1)* %C, <2 ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 ; SI: s_endpgm define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x float> addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i %val = load <2 x float>, <2 x float> addrspace(1)* %in.gep, align 8 %val0 = extractelement <2 x float> %val, i32 0 @@ -127,7 +127,7 @@ define void @simple_write2_two_val_subreg2_f32(float addrspace(1)* %C, <2 x floa ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset1:8 ; SI: s_endpgm define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x float> addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 %x.i %val = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 16 %val0 = extractelement <4 x float> %val, i32 0 @@ -147,11 +147,11 @@ define void @simple_write2_two_val_subreg4_f32(float addrspace(1)* %C, <4 x floa ; SI: ds_write2_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 ; SI: s_endpgm define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %val0 = load float, float addrspace(1)* %in.gep.0, align 4 - %val1 = load float, float addrspace(1)* %in.gep.1, align 4 + %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i store float %val0, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 255 @@ -165,7 +165,7 @@ define void @simple_write2_two_val_max_offset_f32(float addrspace(1)* %C, float ; SI: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:1028 ; SI: s_endpgm define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i %val0 = load float, float addrspace(1)* %in0.gep, align 4 @@ -179,11 +179,11 @@ define void @simple_write2_two_val_too_far_f32(float addrspace(1)* %C, float add } ; SI-LABEL: @simple_write2_two_val_f32_x2 -; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset1:8 -; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL0]] offset1:11 +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL1:v[0-9]+]], [[VAL1]] offset0:8 offset1:27 ; SI: s_endpgm define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x %val0 = load float, float addrspace(1)* %in0.gep, align 4 @@ -209,11 +209,11 @@ define void @simple_write2_two_val_f32_x2(float addrspace(1)* %C, float addrspac } ; SI-LABEL: @simple_write2_two_val_f32_x2_nonzero_base -; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL1:v[0-9]+]] offset0:3 offset1:8 -; SI-NEXT: ds_write2_b32 [[BASEADDR]], [[VAL0]], [[VAL1]] offset0:11 offset1:27 +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL0:v[0-9]+]], [[VAL0]] offset0:3 offset1:11 +; SI: ds_write2_b32 [[BASEADDR:v[0-9]+]], [[VAL1:v[0-9]+]], [[VAL1]] offset0:8 offset1:27 ; SI: s_endpgm define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %tid.x %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %tid.x %val0 = load float, float addrspace(1)* %in0.gep, align 4 @@ -244,7 +244,7 @@ define void @simple_write2_two_val_f32_x2_nonzero_base(float addrspace(1)* %C, f ; SI: ds_write_b32 ; SI: s_endpgm define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float addrspace(1)* %in0, float addrspace(1)* %in1, <2 x float addrspace(3)*> %lds.ptr) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i %val0 = load float, float addrspace(1)* %in0.gep, align 4 @@ -271,7 +271,7 @@ define void @write2_ptr_subreg_arg_two_val_f32(float addrspace(1)* %C, float add ; SI: ds_write2_b64 [[VPTR]], [[VAL]], [[VAL]] offset1:8 ; SI: s_endpgm define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i %val = load double, double addrspace(1)* %in.gep, align 8 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i @@ -289,7 +289,7 @@ define void @simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace ; SI: ds_write2_b32 [[VPTR]], v[[VAL0]], v[[VAL1]] offset0:14 offset1:15 ; SI: s_endpgm define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i %val = load double, double addrspace(1)* %in.gep, align 8 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i @@ -307,11 +307,11 @@ define void @misaligned_simple_write2_one_val_f64(double addrspace(1)* %C, doubl ; SI: ds_write2_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset1:8 ; SI: s_endpgm define void @simple_write2_two_val_f64(double addrspace(1)* %C, double addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 - %val0 = load double, double addrspace(1)* %in.gep.0, align 8 - %val1 = load double, double addrspace(1)* %in.gep.1, align 8 + %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 + %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 %arrayidx0 = getelementptr inbounds [512 x double], [512 x double] addrspace(3)* @lds.f64, i32 0, i32 %x.i store double %val0, double addrspace(3)* %arrayidx0, align 8 %add.x = add nsw i32 %x.i, 8 @@ -372,8 +372,8 @@ define void @store_misaligned64_constant_large_offsets() { @sgemm.lB = internal unnamed_addr addrspace(3) global [776 x float] undef, align 4 define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tgid.x() #1 - %y.i = tail call i32 @llvm.r600.read.tidig.y() #1 + %x.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1 + %y.i = tail call i32 @llvm.amdgcn.workitem.id.y() #1 %val = load float, float addrspace(1)* %in %arrayidx44 = getelementptr inbounds [264 x float], [264 x float] addrspace(3)* @sgemm.lA, i32 0, i32 %x.i store float %val, float addrspace(3)* %arrayidx44, align 4 @@ -411,7 +411,7 @@ define void @write2_sgemm_sequence(float addrspace(1)* %C, i32 %lda, i32 %ldb, f ; CI: ds_write2_b32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} offset0:1{{$}} ; CI: s_endpgm define void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, <4 x float> addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in %val0 = load <4 x float>, <4 x float> addrspace(1)* %in.gep, align 4 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(3)* %out, i32 %x.i @@ -420,20 +420,17 @@ define void @simple_write2_v4f32_superreg_align4(<4 x float> addrspace(3)* %out, } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 +declare i32 @llvm.amdgcn.workgroup.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.y() #1 +declare i32 @llvm.amdgcn.workgroup.id.y() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 - -; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 +declare i32 @llvm.amdgcn.workitem.id.y() #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/ds_write2st64.ll b/test/CodeGen/AMDGPU/ds_write2st64.ll index 5a1024ccf6d7..872e77361406 100644 --- a/test/CodeGen/AMDGPU/ds_write2st64.ll +++ b/test/CodeGen/AMDGPU/ds_write2st64.ll @@ -8,7 +8,7 @@ ; SI: ds_write2st64_b32 [[VPTR]], [[VAL]], [[VAL]] offset1:1 ; SI: s_endpgm define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr float, float addrspace(1)* %in, i32 %x.i %val = load float, float addrspace(1)* %in.gep, align 4 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i @@ -26,11 +26,11 @@ define void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float add ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 ; SI: s_endpgm define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %val0 = load float, float addrspace(1)* %in.gep.0, align 4 - %val1 = load float, float addrspace(1)* %in.gep.1, align 4 + %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %add.x.0 = add nsw i32 %x.i, 128 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0 store float %val0, float addrspace(3)* %arrayidx0, align 4 @@ -47,11 +47,11 @@ define void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float add ; SI: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 ; SI: s_endpgm define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %val0 = load float, float addrspace(1)* %in.gep.0, align 4 - %val1 = load float, float addrspace(1)* %in.gep.1, align 4 + %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i store float %val0, float addrspace(3)* %arrayidx0, align 4 %add.x = add nsw i32 %x.i, 16320 @@ -67,11 +67,11 @@ define void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, fl ; SI: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 ; SI: s_endpgm define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 - %val0 = load double, double addrspace(1)* %in.gep.0, align 8 - %val1 = load double, double addrspace(1)* %in.gep.1, align 8 + %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 + %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 %add.x.0 = add nsw i32 %x.i, 256 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %add.x.0 store double %val0, double addrspace(3)* %arrayidx0, align 8 @@ -86,7 +86,7 @@ define void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, d ; SI: ds_write2_b64 {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset1:8 ; SI: s_endpgm define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { - %x.i = tail call i32 @llvm.r600.read.tidig.x() #1 + %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr double, double addrspace(1)* %in, i32 %x.i %val = load double, double addrspace(1)* %in.gep, align 8 %arrayidx0 = getelementptr inbounds double, double addrspace(3)* %lds, i32 %x.i @@ -98,20 +98,11 @@ define void @byte_size_only_divisible_64_write2st64_f64(double addrspace(1)* %C, } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.y() #1 +declare i32 @llvm.amdgcn.workitem.id.y() #1 -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 - -; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 - -; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 - -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/dynamic_stackalloc.ll b/test/CodeGen/AMDGPU/dynamic_stackalloc.ll index f4409a0984a9..580dc00f935e 100644 --- a/test/CodeGen/AMDGPU/dynamic_stackalloc.ll +++ b/test/CodeGen/AMDGPU/dynamic_stackalloc.ll @@ -2,7 +2,7 @@ ; RUN: not llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -march=r600 -mcpu=cypress < %s 2>&1 | FileCheck %s -; CHECK: error: unsupported dynamic alloca in test_dynamic_stackalloc +; CHECK: in function test_dynamic_stackalloc{{.*}}: unsupported dynamic alloca define void @test_dynamic_stackalloc(i32 addrspace(1)* %out, i32 %n) { %alloca = alloca i32, i32 %n diff --git a/test/CodeGen/AMDGPU/elf.ll b/test/CodeGen/AMDGPU/elf.ll index 90af6782c4b4..c62e57c6eaac 100644 --- a/test/CodeGen/AMDGPU/elf.ll +++ b/test/CodeGen/AMDGPU/elf.ll @@ -22,9 +22,9 @@ ; CONFIG-NEXT: .long 45096 ; TYPICAL-NEXT: .long 0 ; TONGA-NEXT: .long 576 -; CONFIG: .align 256 +; CONFIG: .p2align 8 ; CONFIG: test: -define void @test(i32 %p) #0 { +define amdgpu_ps void @test(i32 %p) { %i = add i32 %p, 2 %r = bitcast i32 %i to float call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %r, float %r, float %r, float %r) @@ -32,5 +32,3 @@ define void @test(i32 %p) #0 { } declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } ; Pixel Shader diff --git a/test/CodeGen/AMDGPU/endcf-loop-header.ll b/test/CodeGen/AMDGPU/endcf-loop-header.ll index 267a323c5063..c67095438ee5 100644 --- a/test/CodeGen/AMDGPU/endcf-loop-header.ll +++ b/test/CodeGen/AMDGPU/endcf-loop-header.ll @@ -12,8 +12,9 @@ ; CHECK: [[LOOP_LABEL:[0-9A-Za-z_]+]]: ; %loop{{$}} ; CHECK-NOT: s_or_b64 exec, exec ; CHECK: s_cbranch_execnz [[LOOP_LABEL]] -define void @test(i32 addrspace(1)* %out, i32 %cond) { +define void @test(i32 addrspace(1)* %out) { entry: + %cond = call i32 @llvm.r600.read.tidig.x() #0 %tmp0 = icmp eq i32 %cond, 0 br i1 %tmp0, label %if, label %loop @@ -32,3 +33,7 @@ done: store i32 %inc, i32 addrspace(1)* %tmp3 ret void } + +declare i32 @llvm.r600.read.tidig.x() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/extload-private.ll b/test/CodeGen/AMDGPU/extload-private.ll index 294c3a9c6782..3f27370d7037 100644 --- a/test/CodeGen/AMDGPU/extload-private.ll +++ b/test/CodeGen/AMDGPU/extload-private.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}load_i8_sext_private: ; SI: buffer_load_sbyte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen @@ -39,7 +39,7 @@ entry: define void @load_i16_zext_private(i32 addrspace(1)* %out) { entry: %tmp0 = alloca i16 - %tmp1 = load i16, i16* %tmp0 + %tmp1 = load volatile i16, i16* %tmp0 %tmp2 = zext i16 %tmp1 to i32 store i32 %tmp2, i32 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/extload.ll b/test/CodeGen/AMDGPU/extload.ll index 662eb7a9716b..2cb5cf0422dc 100644 --- a/test/CodeGen/AMDGPU/extload.ll +++ b/test/CodeGen/AMDGPU/extload.ll @@ -1,53 +1,65 @@ -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FIXME: This seems to not ever actually become an extload +; FUNC-LABEL: {{^}}global_anyext_load_i8: +; GCN: buffer_load_dword v{{[0-9]+}} +; GCN: buffer_store_dword v{{[0-9]+}} -; FUNC-LABEL: {{^}}anyext_load_i8: ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]], ; EG: VTX_READ_32 [[VAL]] - -define void @anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind { +define void @global_anyext_load_i8(i8 addrspace(1)* nocapture noalias %out, i8 addrspace(1)* nocapture noalias %src) nounwind { %cast = bitcast i8 addrspace(1)* %src to i32 addrspace(1)* - %load = load i32, i32 addrspace(1)* %cast, align 1 + %load = load i32, i32 addrspace(1)* %cast %x = bitcast i32 %load to <4 x i8> %castOut = bitcast i8 addrspace(1)* %out to <4 x i8> addrspace(1)* - store <4 x i8> %x, <4 x i8> addrspace(1)* %castOut, align 1 + store <4 x i8> %x, <4 x i8> addrspace(1)* %castOut ret void } -; FUNC-LABEL: {{^}}anyext_load_i16: +; FUNC-LABEL: {{^}}global_anyext_load_i16: +; GCN: buffer_load_dword v{{[0-9]+}} +; GCN: buffer_store_dword v{{[0-9]+}} + ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+.[XYZW]]], ; EG: VTX_READ_32 [[VAL]] - -define void @anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind { +define void @global_anyext_load_i16(i16 addrspace(1)* nocapture noalias %out, i16 addrspace(1)* nocapture noalias %src) nounwind { %cast = bitcast i16 addrspace(1)* %src to i32 addrspace(1)* - %load = load i32, i32 addrspace(1)* %cast, align 1 + %load = load i32, i32 addrspace(1)* %cast %x = bitcast i32 %load to <2 x i16> %castOut = bitcast i16 addrspace(1)* %out to <2 x i16> addrspace(1)* - store <2 x i16> %x, <2 x i16> addrspace(1)* %castOut, align 1 + store <2 x i16> %x, <2 x i16> addrspace(1)* %castOut ret void } -; FUNC-LABEL: {{^}}anyext_load_lds_i8: +; FUNC-LABEL: {{^}}local_anyext_load_i8: +; GCN: ds_read_b32 v{{[0-9]+}} +; GCN: ds_write_b32 v{{[0-9]+}} + ; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]] ; EG: LDS_WRITE * [[VAL]] -define void @anyext_load_lds_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind { +define void @local_anyext_load_i8(i8 addrspace(3)* nocapture noalias %out, i8 addrspace(3)* nocapture noalias %src) nounwind { %cast = bitcast i8 addrspace(3)* %src to i32 addrspace(3)* - %load = load i32, i32 addrspace(3)* %cast, align 1 + %load = load i32, i32 addrspace(3)* %cast %x = bitcast i32 %load to <4 x i8> %castOut = bitcast i8 addrspace(3)* %out to <4 x i8> addrspace(3)* - store <4 x i8> %x, <4 x i8> addrspace(3)* %castOut, align 1 + store <4 x i8> %x, <4 x i8> addrspace(3)* %castOut ret void } -; FUNC-LABEL: {{^}}anyext_load_lds_i16: +; FUNC-LABEL: {{^}}local_anyext_load_i16: +; GCN: ds_read_b32 v{{[0-9]+}} +; GCN: ds_write_b32 v{{[0-9]+}} + ; EG: LDS_READ_RET {{.*}}, [[VAL:T[0-9]+.[XYZW]]] ; EG: LDS_WRITE * [[VAL]] -define void @anyext_load_lds_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind { +define void @local_anyext_load_i16(i16 addrspace(3)* nocapture noalias %out, i16 addrspace(3)* nocapture noalias %src) nounwind { %cast = bitcast i16 addrspace(3)* %src to i32 addrspace(3)* - %load = load i32, i32 addrspace(3)* %cast, align 1 + %load = load i32, i32 addrspace(3)* %cast %x = bitcast i32 %load to <2 x i16> %castOut = bitcast i16 addrspace(3)* %out to <2 x i16> addrspace(3)* - store <2 x i16> %x, <2 x i16> addrspace(3)* %castOut, align 1 + store <2 x i16> %x, <2 x i16> addrspace(3)* %castOut ret void } diff --git a/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll b/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll new file mode 100644 index 000000000000..4edff152e66e --- /dev/null +++ b/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll @@ -0,0 +1,126 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32: +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword + +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 + +; GCN: buffer_store_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dword +define void @store_build_vector_multiple_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0, + <4 x i32> addrspace(1)* noalias %out1, + i32 addrspace(1)* noalias %out2, + i32 addrspace(1)* %in) { + %elt0 = load volatile i32, i32 addrspace(1)* %in + %elt1 = load volatile i32, i32 addrspace(1)* %in + %elt2 = load volatile i32, i32 addrspace(1)* %in + %elt3 = load volatile i32, i32 addrspace(1)* %in + + %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0 + %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1 + %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2 + %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3 + + store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0 + store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out1 + + %extract0 = extractelement <4 x i32> %vec3, i32 0 + %extract1 = extractelement <4 x i32> %vec3, i32 1 + %extract2 = extractelement <4 x i32> %vec3, i32 2 + %extract3 = extractelement <4 x i32> %vec3, i32 3 + + store volatile i32 %extract0, i32 addrspace(1)* %out2 + store volatile i32 %extract1, i32 addrspace(1)* %out2 + store volatile i32 %extract2, i32 addrspace(1)* %out2 + store volatile i32 %extract3, i32 addrspace(1)* %out2 + + ret void +} + +; GCN-LABEL: {{^}}store_build_vector_multiple_extract_uses_v4i32: +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword + +; GCN: buffer_store_dwordx4 + +; GCN: buffer_store_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dword +define void @store_build_vector_multiple_extract_uses_v4i32(<4 x i32> addrspace(1)* noalias %out0, + <4 x i32> addrspace(1)* noalias %out1, + i32 addrspace(1)* noalias %out2, + i32 addrspace(1)* %in) { + %elt0 = load volatile i32, i32 addrspace(1)* %in + %elt1 = load volatile i32, i32 addrspace(1)* %in + %elt2 = load volatile i32, i32 addrspace(1)* %in + %elt3 = load volatile i32, i32 addrspace(1)* %in + + %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0 + %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1 + %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2 + %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3 + + %extract0 = extractelement <4 x i32> %vec3, i32 0 + %extract1 = extractelement <4 x i32> %vec3, i32 1 + %extract2 = extractelement <4 x i32> %vec3, i32 2 + %extract3 = extractelement <4 x i32> %vec3, i32 3 + + %op0 = add i32 %extract0, 3 + %op1 = sub i32 %extract1, 9 + %op2 = xor i32 %extract2, 1231412 + %op3 = and i32 %extract3, 258233412312 + + store <4 x i32> %vec3, <4 x i32> addrspace(1)* %out0 + + store volatile i32 %op0, i32 addrspace(1)* %out2 + store volatile i32 %op1, i32 addrspace(1)* %out2 + store volatile i32 %op2, i32 addrspace(1)* %out2 + store volatile i32 %op3, i32 addrspace(1)* %out2 + + ret void +} + +; GCN-LABEL: {{^}}store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64: +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword +; GCN: buffer_load_dword + +; GCN: buffer_store_dwordx4 + +; GCN: buffer_store_dwordx2 +; GCN: buffer_store_dwordx2 +define void @store_build_vector_multiple_uses_v4i32_bitcast_to_v2i64(<2 x i64> addrspace(1)* noalias %out0, + <4 x i32> addrspace(1)* noalias %out1, + i64 addrspace(1)* noalias %out2, + i32 addrspace(1)* %in) { + %elt0 = load volatile i32, i32 addrspace(1)* %in + %elt1 = load volatile i32, i32 addrspace(1)* %in + %elt2 = load volatile i32, i32 addrspace(1)* %in + %elt3 = load volatile i32, i32 addrspace(1)* %in + + %vec0 = insertelement <4 x i32> undef, i32 %elt0, i32 0 + %vec1 = insertelement <4 x i32> %vec0, i32 %elt1, i32 1 + %vec2 = insertelement <4 x i32> %vec1, i32 %elt2, i32 2 + %vec3 = insertelement <4 x i32> %vec2, i32 %elt3, i32 3 + + %bc.vec3 = bitcast <4 x i32> %vec3 to <2 x i64> + store <2 x i64> %bc.vec3, <2 x i64> addrspace(1)* %out0 + + %extract0 = extractelement <2 x i64> %bc.vec3, i32 0 + %extract1 = extractelement <2 x i64> %bc.vec3, i32 1 + + store volatile i64 %extract0, i64 addrspace(1)* %out2 + store volatile i64 %extract1, i64 addrspace(1)* %out2 + + ret void +} diff --git a/test/CodeGen/AMDGPU/extract-vector-elt-i64.ll b/test/CodeGen/AMDGPU/extract-vector-elt-i64.ll deleted file mode 100644 index e32559139623..000000000000 --- a/test/CodeGen/AMDGPU/extract-vector-elt-i64.ll +++ /dev/null @@ -1,43 +0,0 @@ -; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s - -; How the replacement of i64 stores with v2i32 stores resulted in -; breaking other users of the bitcast if they already existed - -; GCN-LABEL: {{^}}extract_vector_elt_select_error: -; GCN: buffer_store_dword -; GCN: buffer_store_dword -; GCN: buffer_store_dwordx2 -define void @extract_vector_elt_select_error(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %val) nounwind { - %vec = bitcast i64 %val to <2 x i32> - %elt0 = extractelement <2 x i32> %vec, i32 0 - %elt1 = extractelement <2 x i32> %vec, i32 1 - - store volatile i32 %elt0, i32 addrspace(1)* %out - store volatile i32 %elt1, i32 addrspace(1)* %out - store volatile i64 %val, i64 addrspace(1)* %in - ret void -} - - -define void @extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo) nounwind { - %p0 = extractelement <2 x i64> %foo, i32 0 - %p1 = extractelement <2 x i64> %foo, i32 1 - %out1 = getelementptr i64, i64 addrspace(1)* %out, i32 1 - store volatile i64 %p1, i64 addrspace(1)* %out - store volatile i64 %p0, i64 addrspace(1)* %out1 - ret void -} - -define void @dyn_extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo, i32 %elt) nounwind { - %dynelt = extractelement <2 x i64> %foo, i32 %elt - store volatile i64 %dynelt, i64 addrspace(1)* %out - ret void -} - -define void @dyn_extract_vector_elt_v2i64_2(i64 addrspace(1)* %out, <2 x i64> addrspace(1)* %foo, i32 %elt, <2 x i64> %arst) nounwind { - %load = load volatile <2 x i64>, <2 x i64> addrspace(1)* %foo - %or = or <2 x i64> %load, %arst - %dynelt = extractelement <2 x i64> %or, i32 %elt - store volatile i64 %dynelt, i64 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll b/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll new file mode 100644 index 000000000000..d0b19c825ee9 --- /dev/null +++ b/test/CodeGen/AMDGPU/extract_vector_elt-f64.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}extract_vector_elt_v3f64_2: +; GCN: buffer_load_dwordx4 +; GCN: buffer_load_dwordx2 +; GCN: buffer_store_dwordx2 +define void @extract_vector_elt_v3f64_2(double addrspace(1)* %out, <3 x double> addrspace(1)* %in) #0 { + %ld = load volatile <3 x double>, <3 x double> addrspace(1)* %in + %elt = extractelement <3 x double> %ld, i32 2 + store volatile double %elt, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3f64: +define void @dyn_extract_vector_elt_v3f64(double addrspace(1)* %out, <3 x double> %foo, i32 %elt) #0 { + %dynelt = extractelement <3 x double> %foo, i32 %elt + store volatile double %dynelt, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4f64: +define void @dyn_extract_vector_elt_v4f64(double addrspace(1)* %out, <4 x double> %foo, i32 %elt) #0 { + %dynelt = extractelement <4 x double> %foo, i32 %elt + store volatile double %dynelt, double addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll new file mode 100644 index 000000000000..e012cb07163b --- /dev/null +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i16.ll @@ -0,0 +1,86 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}extract_vector_elt_v2i16: +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_store_short +; GCN: buffer_store_short +define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) #0 { + %p0 = extractelement <2 x i16> %foo, i32 0 + %p1 = extractelement <2 x i16> %foo, i32 1 + %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10 + store i16 %p1, i16 addrspace(1)* %out, align 2 + store i16 %p0, i16 addrspace(1)* %out1, align 2 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v3i16: +; GCN: buffer_load_ushort +; GCN: buffer_store_short +; GCN: buffer_store_short +define void @extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo) #0 { + %p0 = extractelement <3 x i16> %foo, i32 0 + %p1 = extractelement <3 x i16> %foo, i32 2 + %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 + store i16 %p1, i16 addrspace(1)* %out, align 2 + store i16 %p0, i16 addrspace(1)* %out1, align 2 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v4i16: +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_store_short +; GCN: buffer_store_short +define void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) #0 { + %p0 = extractelement <4 x i16> %foo, i32 0 + %p1 = extractelement <4 x i16> %foo, i32 2 + %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10 + store i16 %p1, i16 addrspace(1)* %out, align 2 + store i16 %p0, i16 addrspace(1)* %out1, align 2 + ret void +} + + +; FUNC-LABEL: {{^}}dynamic_extract_vector_elt_v3i16: +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort + +; GCN: buffer_store_short +; GCN: buffer_store_short +; GCN: buffer_store_short + +; GCN: buffer_store_short +; GCN: buffer_load_ushort +; GCN: buffer_store_short +define void @dynamic_extract_vector_elt_v3i16(i16 addrspace(1)* %out, <3 x i16> %foo, i32 %idx) #0 { + %p0 = extractelement <3 x i16> %foo, i32 %idx + %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 + store i16 %p0, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}dynamic_extract_vector_elt_v4i16: +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort + +; GCN: buffer_store_short +; GCN: buffer_store_short +; GCN: buffer_store_short +; GCN: buffer_store_short + +; GCN: buffer_store_short +; GCN: buffer_load_ushort +; GCN: buffer_store_short +define void @dynamic_extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo, i32 %idx) #0 { + %p0 = extractelement <4 x i16> %foo, i32 %idx + %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 + store i16 %p0, i16 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll new file mode 100644 index 000000000000..0a51c39f026f --- /dev/null +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i64.ll @@ -0,0 +1,62 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; How the replacement of i64 stores with v2i32 stores resulted in +; breaking other users of the bitcast if they already existed + +; GCN-LABEL: {{^}}extract_vector_elt_select_error: +; GCN: buffer_store_dword +; GCN: buffer_store_dword +; GCN: buffer_store_dwordx2 +define void @extract_vector_elt_select_error(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %val) #0 { + %vec = bitcast i64 %val to <2 x i32> + %elt0 = extractelement <2 x i32> %vec, i32 0 + %elt1 = extractelement <2 x i32> %vec, i32 1 + + store volatile i32 %elt0, i32 addrspace(1)* %out + store volatile i32 %elt1, i32 addrspace(1)* %out + store volatile i64 %val, i64 addrspace(1)* %in + ret void +} + +; GCN-LABEL: {{^}}extract_vector_elt_v2i64: +define void @extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo) #0 { + %p0 = extractelement <2 x i64> %foo, i32 0 + %p1 = extractelement <2 x i64> %foo, i32 1 + %out1 = getelementptr i64, i64 addrspace(1)* %out, i32 1 + store volatile i64 %p1, i64 addrspace(1)* %out + store volatile i64 %p0, i64 addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64: +define void @dyn_extract_vector_elt_v2i64(i64 addrspace(1)* %out, <2 x i64> %foo, i32 %elt) #0 { + %dynelt = extractelement <2 x i64> %foo, i32 %elt + store volatile i64 %dynelt, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v2i64_2: +define void @dyn_extract_vector_elt_v2i64_2(i64 addrspace(1)* %out, <2 x i64> addrspace(1)* %foo, i32 %elt, <2 x i64> %arst) #0 { + %load = load volatile <2 x i64>, <2 x i64> addrspace(1)* %foo + %or = or <2 x i64> %load, %arst + %dynelt = extractelement <2 x i64> %or, i32 %elt + store volatile i64 %dynelt, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v3i64: +define void @dyn_extract_vector_elt_v3i64(i64 addrspace(1)* %out, <3 x i64> %foo, i32 %elt) #0 { + %dynelt = extractelement <3 x i64> %foo, i32 %elt + store volatile i64 %dynelt, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}dyn_extract_vector_elt_v4i64: +define void @dyn_extract_vector_elt_v4i64(i64 addrspace(1)* %out, <4 x i64> %foo, i32 %elt) #0 { + %dynelt = extractelement <4 x i64> %foo, i32 %elt + store volatile i64 %dynelt, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll b/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll new file mode 100644 index 000000000000..9005bfa07c2b --- /dev/null +++ b/test/CodeGen/AMDGPU/extract_vector_elt-i8.ll @@ -0,0 +1,151 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}extract_vector_elt_v1i8: +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +define void @extract_vector_elt_v1i8(i8 addrspace(1)* %out, <1 x i8> %foo) #0 { + %p0 = extractelement <1 x i8> %foo, i32 0 + store i8 %p0, i8 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v2i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v2i8(i8 addrspace(1)* %out, <2 x i8> %foo) #0 { + %p0 = extractelement <2 x i8> %foo, i32 0 + %p1 = extractelement <2 x i8> %foo, i32 1 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v3i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v3i8(i8 addrspace(1)* %out, <3 x i8> %foo) #0 { + %p0 = extractelement <3 x i8> %foo, i32 0 + %p1 = extractelement <3 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v4i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v4i8(i8 addrspace(1)* %out, <4 x i8> %foo) #0 { + %p0 = extractelement <4 x i8> %foo, i32 0 + %p1 = extractelement <4 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v8i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v8i8(i8 addrspace(1)* %out, <8 x i8> %foo) #0 { + %p0 = extractelement <8 x i8> %foo, i32 0 + %p1 = extractelement <8 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v16i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v16i8(i8 addrspace(1)* %out, <16 x i8> %foo) #0 { + %p0 = extractelement <16 x i8> %foo, i32 0 + %p1 = extractelement <16 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v32i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v32i8(i8 addrspace(1)* %out, <32 x i8> %foo) #0 { + %p0 = extractelement <32 x i8> %foo, i32 0 + %p1 = extractelement <32 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}extract_vector_elt_v64i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +define void @extract_vector_elt_v64i8(i8 addrspace(1)* %out, <64 x i8> %foo) #0 { + %p0 = extractelement <64 x i8> %foo, i32 0 + %p1 = extractelement <64 x i8> %foo, i32 2 + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p1, i8 addrspace(1)* %out + store i8 %p0, i8 addrspace(1)* %out1 + ret void +} + +; FUNC-LABEL: {{^}}dynamic_extract_vector_elt_v3i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +define void @dynamic_extract_vector_elt_v3i8(i8 addrspace(1)* %out, <3 x i8> %foo, i32 %idx) #0 { + %p0 = extractelement <3 x i8> %foo, i32 %idx + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p0, i8 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}dynamic_extract_vector_elt_v4i8: +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_load_ubyte +; GCN: buffer_store_byte +define void @dynamic_extract_vector_elt_v4i8(i8 addrspace(1)* %out, <4 x i8> %foo, i32 %idx) #0 { + %p0 = extractelement <4 x i8> %foo, i32 %idx + %out1 = getelementptr i8, i8 addrspace(1)* %out, i32 1 + store i8 %p0, i8 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/extract_vector_elt_i16.ll b/test/CodeGen/AMDGPU/extract_vector_elt_i16.ll deleted file mode 100644 index c7572efc6f5b..000000000000 --- a/test/CodeGen/AMDGPU/extract_vector_elt_i16.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}extract_vector_elt_v2i16: -; SI: buffer_load_ushort -; SI: buffer_load_ushort -; SI: buffer_store_short -; SI: buffer_store_short -define void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> %foo) nounwind { - %p0 = extractelement <2 x i16> %foo, i32 0 - %p1 = extractelement <2 x i16> %foo, i32 1 - %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 - store i16 %p1, i16 addrspace(1)* %out, align 2 - store i16 %p0, i16 addrspace(1)* %out1, align 2 - ret void -} - -; FUNC-LABEL: {{^}}extract_vector_elt_v4i16: -; SI: buffer_load_ushort -; SI: buffer_load_ushort -; SI: buffer_store_short -; SI: buffer_store_short -define void @extract_vector_elt_v4i16(i16 addrspace(1)* %out, <4 x i16> %foo) nounwind { - %p0 = extractelement <4 x i16> %foo, i32 0 - %p1 = extractelement <4 x i16> %foo, i32 2 - %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 1 - store i16 %p1, i16 addrspace(1)* %out, align 2 - store i16 %p0, i16 addrspace(1)* %out1, align 2 - ret void -} diff --git a/test/CodeGen/AMDGPU/extractelt-to-trunc.ll b/test/CodeGen/AMDGPU/extractelt-to-trunc.ll new file mode 100644 index 000000000000..e160c20a03a0 --- /dev/null +++ b/test/CodeGen/AMDGPU/extractelt-to-trunc.ll @@ -0,0 +1,77 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Make sure the add and load are reduced to 32-bits even with the +; bitcast to vector. +; GCN-LABEL: {{^}}bitcast_int_to_vector_extract_0: +; GCN-DAG: s_load_dword [[B:s[0-9]+]] +; GCN-DAG: buffer_load_dword [[A:v[0-9]+]] +; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, [[B]], [[A]] +; GCN: buffer_store_dword [[ADD]] +define void @bitcast_int_to_vector_extract_0(i32 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { + %a = load i64, i64 addrspace(1)* %in + %add = add i64 %a, %b + %val.bc = bitcast i64 %add to <2 x i32> + %extract = extractelement <2 x i32> %val.bc, i32 0 + store i32 %extract, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}bitcast_fp_to_vector_extract_0: +; GCN: buffer_load_dwordx2 +; GCN: v_add_f64 +; GCN: buffer_store_dword v +define void @bitcast_fp_to_vector_extract_0(i32 addrspace(1)* %out, double addrspace(1)* %in, double %b) { + %a = load double, double addrspace(1)* %in + %add = fadd double %a, %b + %val.bc = bitcast double %add to <2 x i32> + %extract = extractelement <2 x i32> %val.bc, i32 0 + store i32 %extract, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}bitcast_int_to_fpvector_extract_0: +; GCN: buffer_load_dwordx2 +; GCN: v_add_i32 +; GCN: buffer_store_dword +define void @bitcast_int_to_fpvector_extract_0(float addrspace(1)* %out, i64 addrspace(1)* %in, i64 %b) { + %a = load i64, i64 addrspace(1)* %in + %add = add i64 %a, %b + %val.bc = bitcast i64 %add to <2 x float> + %extract = extractelement <2 x float> %val.bc, i32 0 + store float %extract, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}no_extract_volatile_load_extract0: +; GCN: buffer_load_dwordx4 +; GCN: buffer_store_dword v +define void @no_extract_volatile_load_extract0(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +entry: + %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %elt0 = extractelement <4 x i32> %vec, i32 0 + store i32 %elt0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}no_extract_volatile_load_extract2: +; GCN: buffer_load_dwordx4 +; GCN: buffer_store_dword v + +define void @no_extract_volatile_load_extract2(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +entry: + %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %elt2 = extractelement <4 x i32> %vec, i32 2 + store i32 %elt2, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}no_extract_volatile_load_dynextract: +; GCN: buffer_load_dwordx4 +; GCN: buffer_store_dword v +define void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { +entry: + %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %eltN = extractelement <4 x i32> %vec, i32 %idx + store i32 %eltN, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/fabs.f64.ll b/test/CodeGen/AMDGPU/fabs.f64.ll index 3c6136c1a7bd..db8093047a36 100644 --- a/test/CodeGen/AMDGPU/fabs.f64.ll +++ b/test/CodeGen/AMDGPU/fabs.f64.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare double @fabs(double) readnone declare double @llvm.fabs.f64(double) readnone @@ -11,7 +11,7 @@ declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone ; SI: v_and_b32 ; SI: s_endpgm define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tidext = sext i32 %tid to i64 %gep = getelementptr double, double addrspace(1)* %in, i64 %tidext %val = load double, double addrspace(1)* %gep, align 8 diff --git a/test/CodeGen/AMDGPU/fadd.ll b/test/CodeGen/AMDGPU/fadd.ll index 5fac328c5981..11436794ac98 100644 --- a/test/CodeGen/AMDGPU/fadd.ll +++ b/test/CodeGen/AMDGPU/fadd.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; FUNC-LABEL: {{^}}fadd_f32: ; R600: ADD {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W diff --git a/test/CodeGen/AMDGPU/fcanonicalize.ll b/test/CodeGen/AMDGPU/fcanonicalize.ll new file mode 100644 index 000000000000..981d88dfe94e --- /dev/null +++ b/test/CodeGen/AMDGPU/fcanonicalize.ll @@ -0,0 +1,351 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare float @llvm.canonicalize.f32(float) #0 +declare double @llvm.canonicalize.f64(double) #0 + +; GCN-LABEL: {{^}}v_test_canonicalize_var_f32: +; GCN: v_mul_f32_e32 [[REG:v[0-9]+]], 1.0, {{v[0-9]+}} +; GCN: buffer_store_dword [[REG]] +define void @v_test_canonicalize_var_f32(float addrspace(1)* %out) #1 { + %val = load float, float addrspace(1)* %out + %canonicalized = call float @llvm.canonicalize.f32(float %val) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_canonicalize_var_f32: +; GCN: v_mul_f32_e64 [[REG:v[0-9]+]], 1.0, {{s[0-9]+}} +; GCN: buffer_store_dword [[REG]] +define void @s_test_canonicalize_var_f32(float addrspace(1)* %out, float %val) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float %val) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_p0_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float 0.0) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_n0_f32: +; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_n0_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float -0.0) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_p1_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_p1_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float 1.0) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_n1_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_n1_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float -1.0) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_literal_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x41800000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_literal_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float 16.0) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal0_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_no_denormals_fold_canonicalize_denormal0_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fffff{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_denormals_fold_canonicalize_denormal0_f32(float addrspace(1)* %out) #3 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 8388607 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal1_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_no_denormals_fold_canonicalize_denormal1_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 2155872255 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x807fffff{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_denormals_fold_canonicalize_denormal1_f32(float addrspace(1)* %out) #3 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 2155872255 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_qnan_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float 0x7FF8000000000000) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_qnan_value_neg1_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 -1 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_qnan_value_neg2_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 -2 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_snan0_value_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 2139095041 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_snan1_value_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 2143289343 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_snan2_value_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 4286578689 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_f32: +; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000{{$}} +; GCN: buffer_store_dword [[REG]] +define void @test_fold_canonicalize_snan3_value_f32(float addrspace(1)* %out) #1 { + %canonicalized = call float @llvm.canonicalize.f32(float bitcast (i32 4290772991 to float)) + store float %canonicalized, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_test_canonicalize_var_f64: +; GCN: v_mul_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, {{v\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 [[REG]] +define void @v_test_canonicalize_var_f64(double addrspace(1)* %out) #1 { + %val = load double, double addrspace(1)* %out + %canonicalized = call double @llvm.canonicalize.f64(double %val) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_canonicalize_var_f64: +; GCN: v_mul_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, {{s\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 [[REG]] +define void @s_test_canonicalize_var_f64(double addrspace(1)* %out, double %val) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double %val) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_p0_f64: +; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_p0_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double 0.0) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_n0_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN-DAG: v_bfrev_b32_e32 v[[HI:[0-9]+]], 1{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_n0_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double -0.0) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_p1_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x3ff00000{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_p1_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double 1.0) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_n1_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xbff00000{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_n1_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double -1.0) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_literal_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x40300000{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_literal_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double 16.0) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal0_f64: +; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_no_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #2 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal0_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0xfffff{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_denormals_fold_canonicalize_denormal0_f64(double addrspace(1)* %out) #3 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 4503599627370495 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_no_denormals_fold_canonicalize_denormal1_f64: +; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], v[[LO]]{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_no_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #2 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_denormals_fold_canonicalize_denormal1_f64: +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], -1{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x800fffff{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_denormals_fold_canonicalize_denormal1_f64(double addrspace(1)* %out) #3 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9227875636482146303 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_qnan_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double 0x7FF8000000000000) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg1_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_qnan_value_neg1_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -1 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_qnan_value_neg2_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_qnan_value_neg2_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 -2 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan0_value_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_snan0_value_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9218868437227405313 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan1_value_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_snan1_value_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 9223372036854775807 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan2_value_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_snan2_value_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18442240474082181121 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}test_fold_canonicalize_snan3_value_f64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0x7ff80000{{$}} +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_fold_canonicalize_snan3_value_f64(double addrspace(1)* %out) #1 { + %canonicalized = call double @llvm.canonicalize.f64(double bitcast (i64 18446744073709551615 to double)) + store double %canonicalized, double addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } +attributes #2 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" } +attributes #3 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" } diff --git a/test/CodeGen/AMDGPU/fceil64.ll b/test/CodeGen/AMDGPU/fceil64.ll index c8ef5b101c4d..fb5853b808e4 100644 --- a/test/CodeGen/AMDGPU/fceil64.ll +++ b/test/CodeGen/AMDGPU/fceil64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s @@ -12,11 +12,11 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone ; FUNC-LABEL: {{^}}fceil_f64: ; CI: v_ceil_f64_e32 ; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 -; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 -; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 -; SI: s_lshr_b64 -; SI: s_not_b64 -; SI: s_and_b64 +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI-DAG: s_add_i32 [[SEXP1:s[0-9]+]], [[SEXP]], 0xfffffc01 +; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP1]] +; SI-DAG: s_not_b64 +; SI-DAG: s_and_b64 ; SI-DAG: cmp_gt_i32 ; SI-DAG: cndmask_b32 ; SI-DAG: cndmask_b32 @@ -25,8 +25,7 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone ; SI-DAG: cndmask_b32 ; SI-DAG: v_cmp_lt_f64 ; SI-DAG: v_cmp_lg_f64 -; SI: s_and_b64 -; SI: v_cndmask_b32 +; SI-DAG: v_cndmask_b32 ; SI: v_cndmask_b32 ; SI: v_add_f64 ; SI: s_endpgm diff --git a/test/CodeGen/AMDGPU/fcopysign.f64.ll b/test/CodeGen/AMDGPU/fcopysign.f64.ll index 3d8c55993089..738a35fb3b89 100644 --- a/test/CodeGen/AMDGPU/fcopysign.f64.ll +++ b/test/CodeGen/AMDGPU/fcopysign.f64.ll @@ -13,8 +13,8 @@ declare <4 x double> @llvm.copysign.v4f64(<4 x double>, <4 x double>) nounwind r ; GCN-DAG: v_mov_b32_e32 v[[VSIGN_HI:[0-9]+]], s[[SSIGN_HI]] ; GCN-DAG: v_mov_b32_e32 v[[VMAG_HI:[0-9]+]], s[[SMAG_HI]] ; GCN-DAG: s_mov_b32 [[SCONST:s[0-9]+]], 0x7fffffff -; GCN: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]] -; GCN: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] +; GCN-DAG: v_bfi_b32 v[[VRESULT_HI:[0-9]+]], [[SCONST]], v[[VMAG_HI]], v[[VSIGN_HI]] +; GCN-DAG: v_mov_b32_e32 v[[VMAG_LO:[0-9]+]], s[[SMAG_LO]] ; GCN: buffer_store_dwordx2 v{{\[}}[[VMAG_LO]]:[[VRESULT_HI]]{{\]}} ; GCN: s_endpgm define void @test_copysign_f64(double addrspace(1)* %out, double %mag, double %sign) nounwind { diff --git a/test/CodeGen/AMDGPU/fdiv.f64.ll b/test/CodeGen/AMDGPU/fdiv.f64.ll index 7c022e38c808..3343b681b9fe 100644 --- a/test/CodeGen/AMDGPU/fdiv.f64.ll +++ b/test/CodeGen/AMDGPU/fdiv.f64.ll @@ -4,8 +4,8 @@ ; COMMON-LABEL: {{^}}fdiv_f64: -; COMMON-DAG: buffer_load_dwordx2 [[NUM:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0 -; COMMON-DAG: buffer_load_dwordx2 [[DEN:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; COMMON-DAG: buffer_load_dwordx2 [[NUM:v\[[0-9]+:[0-9]+\]]], off, {{s\[[0-9]+:[0-9]+\]}}, 0 +; COMMON-DAG: buffer_load_dwordx2 [[DEN:v\[[0-9]+:[0-9]+\]]], off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; CI-DAG: v_div_scale_f64 [[SCALE0:v\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, [[DEN]], [[DEN]], [[NUM]] ; CI-DAG: v_div_scale_f64 [[SCALE1:v\[[0-9]+:[0-9]+\]]], vcc, [[NUM]], [[DEN]], [[NUM]] @@ -31,8 +31,8 @@ ; COMMON: s_endpgm define void @fdiv_f64(double addrspace(1)* %out, double addrspace(1)* %in) nounwind { %gep.1 = getelementptr double, double addrspace(1)* %in, i32 1 - %num = load double, double addrspace(1)* %in - %den = load double, double addrspace(1)* %gep.1 + %num = load volatile double, double addrspace(1)* %in + %den = load volatile double, double addrspace(1)* %gep.1 %result = fdiv double %num, %den store double %result, double addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/fdiv.ll b/test/CodeGen/AMDGPU/fdiv.ll index 7cbf87336399..4021233e7785 100644 --- a/test/CodeGen/AMDGPU/fdiv.ll +++ b/test/CodeGen/AMDGPU/fdiv.ll @@ -1,19 +1,32 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=I754 -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -amdgpu-fast-fdiv < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=I754 -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=UNSAFE-FP -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; These tests check that fdiv is expanded correctly and also test that the ; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate ; instruction groups. +; These test check that fdiv using unsafe_fp_math, coarse fp div, and IEEE754 fp div. + ; FUNC-LABEL: {{^}}fdiv_f32: -; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z -; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y -; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS -; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS + +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 ; SI-DAG: v_rcp_f32 ; SI-DAG: v_mul_f32 + +; I754-DAG: v_div_scale_f32 +; I754-DAG: v_rcp_f32 +; I754-DAG: v_fma_f32 +; I754-DAG: v_mul_f32 +; I754-DAG: v_fma_f32 +; I754-DAG: v_div_fixup_f32 define void @fdiv_f32(float addrspace(1)* %out, float %a, float %b) { entry: %0 = fdiv float %a, %b @@ -21,7 +34,37 @@ entry: ret void } +; FUNC-LABEL: {{^}}fdiv_f32_fast_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_f32_fast_math(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fdiv fast float %a, %b + store float %0, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}fdiv_f32_arcp_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS + +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_f32_arcp_math(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fdiv arcp float %a, %b + store float %0, float addrspace(1)* %out + ret void +} ; FUNC-LABEL: {{^}}fdiv_v2f32: ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z @@ -29,10 +72,22 @@ entry: ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + ; SI-DAG: v_rcp_f32 ; SI-DAG: v_mul_f32 ; SI-DAG: v_rcp_f32 ; SI-DAG: v_mul_f32 + +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_fixup_f32 +; I754: v_div_fixup_f32 define void @fdiv_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fdiv <2 x float> %a, %b @@ -40,6 +95,50 @@ entry: ret void } +; FUNC-LABEL: {{^}}fdiv_v2f32_fast_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS + +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_v2f32_fast_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fdiv fast <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}fdiv_v2f32_arcp_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS + +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_rcp_f32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_v2f32_arcp_math(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { +entry: + %0 = fdiv arcp <2 x float> %a, %b + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}fdiv_v4f32: ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} @@ -50,6 +149,15 @@ entry: ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS ; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + ; SI-DAG: v_rcp_f32 ; SI-DAG: v_mul_f32 ; SI-DAG: v_rcp_f32 @@ -58,6 +166,19 @@ entry: ; SI-DAG: v_mul_f32 ; SI-DAG: v_rcp_f32 ; SI-DAG: v_mul_f32 + +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_scale_f32 +; I754: v_div_fixup_f32 +; I754: v_div_fixup_f32 +; I754: v_div_fixup_f32 +; I754: v_div_fixup_f32 define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float>, <4 x float> addrspace(1) * %in @@ -66,3 +187,75 @@ define void @fdiv_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1) store <4 x float> %result, <4 x float> addrspace(1)* %out ret void } + +; FUNC-LABEL: {{^}}fdiv_v4f32_fast_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS + +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_v4f32_fast_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float>, <4 x float> addrspace(1) * %in + %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr + %result = fdiv fast <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}fdiv_v4f32_arcp_math: +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS +; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS + +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_rcp_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 +; UNSAFE-FP: v_mul_f32_e32 + +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +; SI-DAG: v_rcp_f32 +; SI-DAG: v_mul_f32 +define void @fdiv_v4f32_arcp_math(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { + %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 + %a = load <4 x float>, <4 x float> addrspace(1) * %in + %b = load <4 x float>, <4 x float> addrspace(1) * %b_ptr + %result = fdiv arcp <4 x float> %a, %b + store <4 x float> %result, <4 x float> addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/fetch-limits.r600.ll b/test/CodeGen/AMDGPU/fetch-limits.r600.ll index e7160ef5d726..5cb0c616d15f 100644 --- a/test/CodeGen/AMDGPU/fetch-limits.r600.ll +++ b/test/CodeGen/AMDGPU/fetch-limits.r600.ll @@ -7,42 +7,50 @@ ; CHECK: Fetch clause ; CHECK: Fetch clause -define void @fetch_limits_r600() #0 { +define amdgpu_ps void @fetch_limits_r600() { entry: - %0 = load <4 x float>, <4 x float> addrspace(8)* null - %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) - %3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) - %4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) - %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) - %6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) - %7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) - %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) - %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1) - %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1) - %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1) - %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1) - %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1) - %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1) - %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1) - %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1) - %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) - %a = fadd <4 x float> %res0, %res1 - %b = fadd <4 x float> %res2, %res3 - %c = fadd <4 x float> %res4, %res5 - %d = fadd <4 x float> %res6, %res7 - %e = fadd <4 x float> %res8, %a - + %tmp = load <4 x float>, <4 x float> addrspace(8)* null + %tmp1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) + %tmp2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 2) + %tmp3 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 3) + %tmp4 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 4) + %tmp5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) + %tmp6 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 6) + %tmp7 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) + %tmp8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) + %tmp9 = shufflevector <4 x float> %tmp, <4 x float> %tmp, <4 x i32> + %tmp10 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp9, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp11 = shufflevector <4 x float> %tmp1, <4 x float> %tmp1, <4 x i32> + %tmp12 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp11, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp13 = shufflevector <4 x float> %tmp2, <4 x float> %tmp2, <4 x i32> + %tmp14 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp15 = shufflevector <4 x float> %tmp3, <4 x float> %tmp3, <4 x i32> + %tmp16 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp17 = shufflevector <4 x float> %tmp4, <4 x float> %tmp4, <4 x i32> + %tmp18 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp17, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp19 = shufflevector <4 x float> %tmp5, <4 x float> %tmp5, <4 x i32> + %tmp20 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp19, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp21 = shufflevector <4 x float> %tmp6, <4 x float> %tmp6, <4 x i32> + %tmp22 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp23 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp24 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp25 = shufflevector <4 x float> %tmp8, <4 x float> %tmp8, <4 x i32> + %tmp26 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp25, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %a = fadd <4 x float> %tmp10, %tmp12 + %b = fadd <4 x float> %tmp14, %tmp16 + %c = fadd <4 x float> %tmp18, %tmp20 + %d = fadd <4 x float> %tmp22, %tmp24 + %e = fadd <4 x float> %tmp26, %a %bc = fadd <4 x float> %b, %c %de = fadd <4 x float> %d, %e - %bcde = fadd <4 x float> %bc, %de - - call void @llvm.R600.store.swizzle(<4 x float> %bcde, i32 0, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %bcde, i32 0, i32 1) ret void } -attributes #0 = { "ShaderType"="0" } ; Pixel Shader +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) + +; Function Attrs: readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/fetch-limits.r700+.ll b/test/CodeGen/AMDGPU/fetch-limits.r700+.ll index acaea2aa7943..d8f7c0daa8de 100644 --- a/test/CodeGen/AMDGPU/fetch-limits.r700+.ll +++ b/test/CodeGen/AMDGPU/fetch-limits.r700+.ll @@ -16,7 +16,7 @@ ; CHECK: Fetch clause ; CHECK: Fetch clause -define void @fetch_limits_r700() #0 { +define amdgpu_ps void @fetch_limits_r700() { entry: %0 = load <4 x float>, <4 x float> addrspace(8)* null %1 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) @@ -35,47 +35,63 @@ entry: %14 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 14) %15 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 15) %16 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 16) - %res0 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %0, i32 0, i32 0, i32 1) - %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %1, i32 0, i32 0, i32 1) - %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %2, i32 0, i32 0, i32 1) - %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %3, i32 0, i32 0, i32 1) - %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %4, i32 0, i32 0, i32 1) - %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %5, i32 0, i32 0, i32 1) - %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %6, i32 0, i32 0, i32 1) - %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %7, i32 0, i32 0, i32 1) - %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) - %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %9, i32 0, i32 0, i32 1) - %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %10, i32 0, i32 0, i32 1) - %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %11, i32 0, i32 0, i32 1) - %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %12, i32 0, i32 0, i32 1) - %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %13, i32 0, i32 0, i32 1) - %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %14, i32 0, i32 0, i32 1) - %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %15, i32 0, i32 0, i32 1) - %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %16, i32 0, i32 0, i32 1) - %a = fadd <4 x float> %res0, %res1 - %b = fadd <4 x float> %res2, %res3 - %c = fadd <4 x float> %res4, %res5 - %d = fadd <4 x float> %res6, %res7 - %e = fadd <4 x float> %res8, %res9 - %f = fadd <4 x float> %res10, %res11 - %g = fadd <4 x float> %res12, %res13 - %h = fadd <4 x float> %res14, %res15 - %i = fadd <4 x float> %res16, %a - + %17 = shufflevector <4 x float> %0, <4 x float> %0, <4 x i32> + %18 = call <4 x float> @llvm.r600.tex(<4 x float> %17, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %19 = shufflevector <4 x float> %1, <4 x float> %1, <4 x i32> + %20 = call <4 x float> @llvm.r600.tex(<4 x float> %19, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %21 = shufflevector <4 x float> %2, <4 x float> %2, <4 x i32> + %22 = call <4 x float> @llvm.r600.tex(<4 x float> %21, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %23 = shufflevector <4 x float> %3, <4 x float> %3, <4 x i32> + %24 = call <4 x float> @llvm.r600.tex(<4 x float> %23, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %25 = shufflevector <4 x float> %4, <4 x float> %4, <4 x i32> + %26 = call <4 x float> @llvm.r600.tex(<4 x float> %25, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %27 = shufflevector <4 x float> %5, <4 x float> %5, <4 x i32> + %28 = call <4 x float> @llvm.r600.tex(<4 x float> %27, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %29 = shufflevector <4 x float> %6, <4 x float> %6, <4 x i32> + %30 = call <4 x float> @llvm.r600.tex(<4 x float> %29, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %31 = shufflevector <4 x float> %7, <4 x float> %7, <4 x i32> + %32 = call <4 x float> @llvm.r600.tex(<4 x float> %31, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %33 = shufflevector <4 x float> %8, <4 x float> %8, <4 x i32> + %34 = call <4 x float> @llvm.r600.tex(<4 x float> %33, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %35 = shufflevector <4 x float> %9, <4 x float> %9, <4 x i32> + %36 = call <4 x float> @llvm.r600.tex(<4 x float> %35, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %37 = shufflevector <4 x float> %10, <4 x float> %10, <4 x i32> + %38 = call <4 x float> @llvm.r600.tex(<4 x float> %37, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %39 = shufflevector <4 x float> %11, <4 x float> %11, <4 x i32> + %40 = call <4 x float> @llvm.r600.tex(<4 x float> %39, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %41 = shufflevector <4 x float> %12, <4 x float> %12, <4 x i32> + %42 = call <4 x float> @llvm.r600.tex(<4 x float> %41, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %43 = shufflevector <4 x float> %13, <4 x float> %13, <4 x i32> + %44 = call <4 x float> @llvm.r600.tex(<4 x float> %43, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %45 = shufflevector <4 x float> %14, <4 x float> %14, <4 x i32> + %46 = call <4 x float> @llvm.r600.tex(<4 x float> %45, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %47 = shufflevector <4 x float> %15, <4 x float> %15, <4 x i32> + %48 = call <4 x float> @llvm.r600.tex(<4 x float> %47, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %49 = shufflevector <4 x float> %16, <4 x float> %16, <4 x i32> + %50 = call <4 x float> @llvm.r600.tex(<4 x float> %49, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %a = fadd <4 x float> %18, %20 + %b = fadd <4 x float> %22, %24 + %c = fadd <4 x float> %26, %28 + %d = fadd <4 x float> %30, %32 + %e = fadd <4 x float> %34, %36 + %f = fadd <4 x float> %38, %40 + %g = fadd <4 x float> %42, %44 + %h = fadd <4 x float> %46, %48 + %i = fadd <4 x float> %50, %a %bc = fadd <4 x float> %b, %c %de = fadd <4 x float> %d, %e %fg = fadd <4 x float> %f, %g %hi = fadd <4 x float> %h, %i - %bcde = fadd <4 x float> %bc, %de %fghi = fadd <4 x float> %fg, %hi - %bcdefghi = fadd <4 x float> %bcde, %fghi - call void @llvm.R600.store.swizzle(<4 x float> %bcdefghi, i32 0, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %bcdefghi, i32 0, i32 1) ret void } -attributes #0 = { "ShaderType"="0" } ; Pixel Shader +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) + +; Function Attrs: readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/ffloor.f64.ll b/test/CodeGen/AMDGPU/ffloor.f64.ll index 45f8382c3929..ea708a2b7bbd 100644 --- a/test/CodeGen/AMDGPU/ffloor.f64.ll +++ b/test/CodeGen/AMDGPU/ffloor.f64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s @@ -13,8 +13,8 @@ declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone ; FUNC-LABEL: {{^}}ffloor_f64: ; CI: v_floor_f64_e32 ; SI: v_fract_f64_e32 -; SI: v_min_f64 -; SI: v_cmp_class_f64_e64 +; SI-DAG: v_min_f64 +; SI-DAG: v_cmp_class_f64_e64 ; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e64 ; SI: v_add_f64 @@ -28,8 +28,8 @@ define void @ffloor_f64(double addrspace(1)* %out, double %x) { ; FUNC-LABEL: {{^}}ffloor_f64_neg: ; CI: v_floor_f64_e64 ; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT:s[[0-9]+:[0-9]+]]] -; SI: v_min_f64 -; SI: v_cmp_class_f64_e64 +; SI-DAG: v_min_f64 +; SI-DAG: v_cmp_class_f64_e64 ; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e64 ; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -[[INPUT]] @@ -44,8 +44,8 @@ define void @ffloor_f64_neg(double addrspace(1)* %out, double %x) { ; FUNC-LABEL: {{^}}ffloor_f64_neg_abs: ; CI: v_floor_f64_e64 ; SI: v_fract_f64_e64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT:s[[0-9]+:[0-9]+]]]| -; SI: v_min_f64 -; SI: v_cmp_class_f64_e64 +; SI-DAG: v_min_f64 +; SI-DAG: v_cmp_class_f64_e64 ; SI: v_cndmask_b32_e64 ; SI: v_cndmask_b32_e64 ; SI: v_add_f64 {{v[[0-9]+:[0-9]+]}}, -|[[INPUT]]| @@ -67,15 +67,16 @@ define void @ffloor_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) { ret void } -; FIXME-FUNC-LABEL: {{^}}ffloor_v3f64: -; FIXME-CI: v_floor_f64_e32 -; FIXME-CI: v_floor_f64_e32 -; FIXME-CI: v_floor_f64_e32 -; define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { -; %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone -; store <3 x double> %y, <3 x double> addrspace(1)* %out -; ret void -; } +; FUNC-LABEL: {{^}}ffloor_v3f64: +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI: v_floor_f64_e32 +; CI-NOT: v_floor_f64_e32 +define void @ffloor_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) { + %y = call <3 x double> @llvm.floor.v3f64(<3 x double> %x) nounwind readnone + store <3 x double> %y, <3 x double> addrspace(1)* %out + ret void +} ; FUNC-LABEL: {{^}}ffloor_v4f64: ; CI: v_floor_f64_e32 diff --git a/test/CodeGen/AMDGPU/flat-address-space.ll b/test/CodeGen/AMDGPU/flat-address-space.ll index 86e0c07323bb..5ca57fd3d350 100644 --- a/test/CodeGen/AMDGPU/flat-address-space.ll +++ b/test/CodeGen/AMDGPU/flat-address-space.ll @@ -17,7 +17,7 @@ ; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]] ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] -; CHECK: flat_store_dword v[[DATA]], v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} +; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]] define void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { %fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* store i32 %x, i32 addrspace(4)* %fptr, align 4 @@ -127,9 +127,6 @@ define void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* ret void } -declare void @llvm.AMDGPU.barrier.local() #1 -declare i32 @llvm.r600.read.tidig.x() #3 - attributes #0 = { nounwind } attributes #1 = { nounwind convergent } attributes #3 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/flat_atomics.ll b/test/CodeGen/AMDGPU/flat_atomics.ll new file mode 100644 index 000000000000..7400dbcf8909 --- /dev/null +++ b/test/CodeGen/AMDGPU/flat_atomics.ll @@ -0,0 +1,968 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}atomic_add_i32_offset: +; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_add_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_ret_offset: +; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset: +; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_add_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: +; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32: +; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_add_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_ret: +; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_addr64: +; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_add_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64: +; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_offset: +; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_and_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_ret_offset: +; GCN: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset: +; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_and_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: +; GCN: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32: +; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_and_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_ret: +; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_addr64: +; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_and_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64: +; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_offset: +; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_sub_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_ret_offset: +; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset: +; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_sub_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: +; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32: +; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_sub_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_ret: +; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_addr64: +; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_sub_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64: +; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_offset: +; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_max_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_ret_offset: +; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset: +; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_max_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: +; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32: +; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_max_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_ret: +; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_addr64: +; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_max_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64: +; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_offset: +; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umax_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_ret_offset: +; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset: +; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umax_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: +; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32: +; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umax_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_ret: +; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_addr64: +; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umax_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64: +; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_offset: +; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_min_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_ret_offset: +; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset: +; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_min_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: +; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32: +; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_min_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_ret: +; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_addr64: +; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_min_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64: +; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_offset: +; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umin_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_ret_offset: +; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset: +; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umin_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: +; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32: +; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umin_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_ret: +; GCN: flat_atomic_umin v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_addr64: +; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_umin_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64: +; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]{{$}} + define void @atomic_umin_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_offset: +; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_or_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_ret_offset: +; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset: +; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_or_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: +; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32: +; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_or_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_ret: +; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_addr64: +; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_or_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64: +; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_offset: +; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_xchg_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_ret_offset: +; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset: +; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_xchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: +; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32: +; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_xchg_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_ret: +; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_addr64: +; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_xchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64: +; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; CMP_SWAP + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset: +; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32_offset(i32 addrspace(4)* %out, i32 %in, i32 %old) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: +; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] +define void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst + %flag = extractvalue { i32, i1 } %val, 0 + store i32 %flag, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: +; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: +; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] +define void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst + %flag = extractvalue { i32, i1 } %val, 0 + store i32 %flag, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32: +; GCN: flat_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32(i32 addrspace(4)* %out, i32 %in, i32 %old) { +entry: + %val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret: +; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] +define void @atomic_cmpxchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { +entry: + %val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst + %flag = extractvalue { i32, i1 } %val, 0 + store i32 %flag, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64: +; GCN: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: +; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] +define void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst + %flag = extractvalue { i32, i1 } %val, 0 + store i32 %flag, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_offset: +; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_xor_i32_offset(i32 addrspace(4)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_ret_offset: +; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + %val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset: +; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_xor_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: +; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32: +; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} +define void @atomic_xor_i32(i32 addrspace(4)* %out, i32 %in) { +entry: + %val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_ret: +; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { +entry: + %val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_addr64: +; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} +define void @atomic_xor_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64: +; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i32_offset: +; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i32_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %in, i32 4 + %val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 + store i32 %val, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i32: +; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i32(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { +entry: + %val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4 + store i32 %val, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i32_addr64_offset: +; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i32_addr64_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 + store i32 %val, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i32_addr64: +; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i32_addr64(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index + %val = load atomic i32, i32 addrspace(4)* %ptr seq_cst, align 4 + store i32 %val, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i32_offset: +; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_offset(i32 %in, i32 addrspace(4)* %out) { +entry: + %gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 + store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i32: +; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32(i32 %in, i32 addrspace(4)* %out) { +entry: + store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset: +; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i32_addr64: +; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_addr64(i32 %in, i32 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index + store atomic i32 %in, i32 addrspace(4)* %ptr seq_cst, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/test/CodeGen/AMDGPU/flat_atomics_i64.ll new file mode 100644 index 000000000000..0bd6c2dd5b86 --- /dev/null +++ b/test/CodeGen/AMDGPU/flat_atomics_i64.ll @@ -0,0 +1,975 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}atomic_add_i64_offset: +; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} +define void @atomic_add_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: +; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: +; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} +define void @atomic_add_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: +; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64: +; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_add_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret: +; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_addr64: +; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_add_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64: +; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_add_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_offset: +; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_offset: +; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset: +; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset: +; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64: +; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret: +; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_addr64: +; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64: +; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_and_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_offset: +; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset: +; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset: +; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset: +; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64: +; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret: +; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_addr64: +; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64: +; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_sub_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_offset: +; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_offset: +; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset: +; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset: +; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64: +; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret: +; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_addr64: +; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64: +; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_max_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_offset: +; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset: +; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset: +; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset: +; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64: +; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret: +; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_addr64: +; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64: +; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umax_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_offset: +; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_offset: +; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset: +; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset: +; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64: +; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret: +; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_addr64: +; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64: +; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_min_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_offset: +; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset: +; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset: +; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset: +; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64: +; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret: +; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_addr64: +; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64: +; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_umin_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_offset: +; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_offset: +; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset: +; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset: +; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64: +; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret: +; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_addr64: +; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64: +; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_or_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_offset: +; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xchg_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset: +; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset: +; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset: +; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64: +; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xchg_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret: +; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_addr64: +; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64: +; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_offset: +; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64_offset(i64 addrspace(4)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset: +; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset: +; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset: +; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64: +; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64(i64 addrspace(4)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret: +; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_addr64: +; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64: +; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_xor_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i64_offset: +; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %in, i64 4 + %val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 + store i64 %val, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i64: +; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i64(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { +entry: + %val = load atomic i64, i64 addrspace(4)* %in seq_cst, align 8 + store i64 %val, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i64_addr64_offset: +; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i64_addr64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 + store i64 %val, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_load_i64_addr64: +; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] +define void @atomic_load_i64_addr64(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index + %val = load atomic i64, i64 addrspace(4)* %ptr seq_cst, align 8 + store i64 %val, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i64_offset: +; GCN: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +define void @atomic_store_i64_offset(i64 %in, i64 addrspace(4)* %out) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i64: +; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}] glc +define void @atomic_store_i64(i64 %in, i64 addrspace(4)* %out) { +entry: + store atomic i64 %in, i64 addrspace(4)* %out seq_cst, align 8 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i64_addr64_offset: +; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}] glc{{$}} +define void @atomic_store_i64_addr64_offset(i64 %in, i64 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 + ret void +} + +; GCN-LABEL: {{^}}atomic_store_i64_addr64: +; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}] glc{{$}} +define void @atomic_store_i64_addr64(i64 %in, i64 addrspace(4)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + store atomic i64 %in, i64 addrspace(4)* %ptr seq_cst, align 8 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_offset: +; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_offset(i64 addrspace(4)* %out, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_soffset: +; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_soffset(i64 addrspace(4)* %out, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 9000 + %val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: +; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 + %val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: +; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: +; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 + %val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64: +; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64(i64 addrspace(4)* %out, i64 %in, i64 %old) { +entry: + %val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret: +; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { +entry: + %val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(4)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64: +; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: +; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index + %val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(4)* %out2 + ret void +} diff --git a/test/CodeGen/AMDGPU/floor.ll b/test/CodeGen/AMDGPU/floor.ll index c6bfb8567a0f..43e58b942220 100644 --- a/test/CodeGen/AMDGPU/floor.ll +++ b/test/CodeGen/AMDGPU/floor.ll @@ -1,15 +1,14 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s ; CHECK: FLOOR * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = call float @floor(float %r0) %vec = insertelement <4 x float> undef, float %r1, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @floor(float) readonly -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/fma-combine.ll b/test/CodeGen/AMDGPU/fma-combine.ll index 6f3437048ed8..19deefe4d4a5 100644 --- a/test/CodeGen/AMDGPU/fma-combine.ll +++ b/test/CodeGen/AMDGPU/fma-combine.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-FASTFMAF -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -check-prefix=SI-SLOWFMAF -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 declare double @llvm.fabs.f64(double) #0 declare double @llvm.fma.f64(double, double, double) #0 declare float @llvm.fma.f32(float, float, float) #0 @@ -14,15 +14,15 @@ declare float @llvm.fma.f32(float, float, float) #0 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 %mul = fmul double %a, %b %fma = fadd double %mul, %c @@ -42,7 +42,7 @@ define void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addr ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI: s_endpgm define void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -50,16 +50,16 @@ define void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1 - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 - %d = load double, double addrspace(1)* %gep.3 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 + %d = load volatile double, double addrspace(1)* %gep.3 %mul = fmul double %a, %b %fma0 = fadd double %mul, %c %fma1 = fadd double %mul, %d - store double %fma0, double addrspace(1)* %gep.out.0 - store double %fma1, double addrspace(1)* %gep.out.1 + store volatile double %fma0, double addrspace(1)* %gep.out.0 + store volatile double %fma1, double addrspace(1)* %gep.out.1 ret void } @@ -71,15 +71,15 @@ define void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 %mul = fmul double %a, %b %fma = fadd double %c, %mul @@ -95,15 +95,15 @@ define void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addr ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 %mul = fmul double %a, %b %fma = fsub double %mul, %c @@ -123,7 +123,7 @@ define void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI: s_endpgm define void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -131,16 +131,16 @@ define void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, d %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1 - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 - %d = load double, double addrspace(1)* %gep.3 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 + %d = load volatile double, double addrspace(1)* %gep.3 %mul = fmul double %a, %b %fma0 = fsub double %mul, %c %fma1 = fsub double %mul, %d - store double %fma0, double addrspace(1)* %gep.out.0 - store double %fma1, double addrspace(1)* %gep.out.1 + store volatile double %fma0, double addrspace(1)* %gep.out.0 + store volatile double %fma1, double addrspace(1)* %gep.out.1 ret void } @@ -152,15 +152,15 @@ define void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, d ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 %mul = fmul double %a, %b %fma = fsub double %c, %mul @@ -180,7 +180,7 @@ define void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI: s_endpgm define void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -188,16 +188,16 @@ define void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, d %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1 - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 - %d = load double, double addrspace(1)* %gep.3 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 + %d = load volatile double, double addrspace(1)* %gep.3 %mul = fmul double %a, %b %fma0 = fsub double %c, %mul %fma1 = fsub double %d, %mul - store double %fma0, double addrspace(1)* %gep.out.0 - store double %fma1, double addrspace(1)* %gep.out.1 + store volatile double %fma0, double addrspace(1)* %gep.out.0 + store volatile double %fma1, double addrspace(1)* %gep.out.1 ret void } @@ -209,15 +209,15 @@ define void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, d ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 %mul = fmul double %a, %b %mul.neg = fsub double -0.0, %mul @@ -238,7 +238,7 @@ define void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI: s_endpgm define void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -246,18 +246,18 @@ define void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %o %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1 - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 - %d = load double, double addrspace(1)* %gep.3 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 + %d = load volatile double, double addrspace(1)* %gep.3 %mul = fmul double %a, %b %mul.neg = fsub double -0.0, %mul %fma0 = fsub double %mul.neg, %c %fma1 = fsub double %mul.neg, %d - store double %fma0, double addrspace(1)* %gep.out.0 - store double %fma1, double addrspace(1)* %gep.out.1 + store volatile double %fma0, double addrspace(1)* %gep.out.0 + store volatile double %fma1, double addrspace(1)* %gep.out.1 ret void } @@ -272,7 +272,7 @@ define void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %o ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI: s_endpgm define void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -280,18 +280,18 @@ define void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %o %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1 - %a = load double, double addrspace(1)* %gep.0 - %b = load double, double addrspace(1)* %gep.1 - %c = load double, double addrspace(1)* %gep.2 - %d = load double, double addrspace(1)* %gep.3 + %a = load volatile double, double addrspace(1)* %gep.0 + %b = load volatile double, double addrspace(1)* %gep.1 + %c = load volatile double, double addrspace(1)* %gep.2 + %d = load volatile double, double addrspace(1)* %gep.3 %mul = fmul double %a, %b %mul.neg = fsub double -0.0, %mul %fma0 = fsub double %mul.neg, %c %fma1 = fsub double %mul, %d - store double %fma0, double addrspace(1)* %gep.out.0 - store double %fma1, double addrspace(1)* %gep.out.1 + store volatile double %fma0, double addrspace(1)* %gep.out.0 + store volatile double %fma1, double addrspace(1)* %gep.out.1 ret void } @@ -307,7 +307,7 @@ define void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %o ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -315,11 +315,11 @@ define void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias % %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %x = load double, double addrspace(1)* %gep.0 - %y = load double, double addrspace(1)* %gep.1 - %z = load double, double addrspace(1)* %gep.2 - %u = load double, double addrspace(1)* %gep.3 - %v = load double, double addrspace(1)* %gep.4 + %x = load volatile double, double addrspace(1)* %gep.0 + %y = load volatile double, double addrspace(1)* %gep.1 + %z = load volatile double, double addrspace(1)* %gep.2 + %u = load volatile double, double addrspace(1)* %gep.3 + %v = load volatile double, double addrspace(1)* %gep.4 %tmp0 = fmul double %u, %v %tmp1 = call double @llvm.fma.f64(double %x, double %y, double %tmp0) #0 @@ -342,7 +342,7 @@ define void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias % ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @aggressive_combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 @@ -350,11 +350,11 @@ define void @aggressive_combine_to_fma_fsub_1_f64(double addrspace(1)* noalias % %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid - %x = load double, double addrspace(1)* %gep.0 - %y = load double, double addrspace(1)* %gep.1 - %z = load double, double addrspace(1)* %gep.2 - %u = load double, double addrspace(1)* %gep.3 - %v = load double, double addrspace(1)* %gep.4 + %x = load volatile double, double addrspace(1)* %gep.0 + %y = load volatile double, double addrspace(1)* %gep.1 + %z = load volatile double, double addrspace(1)* %gep.2 + %u = load volatile double, double addrspace(1)* %gep.3 + %v = load volatile double, double addrspace(1)* %gep.4 %tmp0 = fmul double %u, %v %tmp1 = call double @llvm.fma.f64(double %y, double %z, double %tmp0) #0 @@ -373,8 +373,8 @@ define void @aggressive_combine_to_fma_fsub_1_f64(double addrspace(1)* noalias % define void @test_f32_mul_add_x_one_y(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { - %x = load float, float addrspace(1)* %in1 - %y = load float, float addrspace(1)* %in2 + %x = load volatile float, float addrspace(1)* %in1 + %y = load volatile float, float addrspace(1)* %in2 %a = fadd float %x, 1.0 %m = fmul float %a, %y store float %m, float addrspace(1)* %out @@ -386,8 +386,8 @@ define void @test_f32_mul_add_x_one_y(float addrspace(1)* %out, define void @test_f32_mul_y_add_x_one(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { - %x = load float, float addrspace(1)* %in1 - %y = load float, float addrspace(1)* %in2 + %x = load volatile float, float addrspace(1)* %in1 + %y = load volatile float, float addrspace(1)* %in2 %a = fadd float %x, 1.0 %m = fmul float %y, %a store float %m, float addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/fma.ll b/test/CodeGen/AMDGPU/fma.ll index d6024aa0b4c5..d04a5946b98c 100644 --- a/test/CodeGen/AMDGPU/fma.ll +++ b/test/CodeGen/AMDGPU/fma.ll @@ -61,7 +61,7 @@ define void @fma_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* } ; FUNC-LABEL: @fma_commute_mul_inline_imm_f32 -; SI: v_fma_f32 {{v[0-9]+}}, 2.0, {{v[0-9]+}}, {{v[0-9]+}} +; SI: v_fma_f32 {{v[0-9]+}}, {{v[0-9]+}}, 2.0, {{v[0-9]+}} define void @fma_commute_mul_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid diff --git a/test/CodeGen/AMDGPU/fmad.ll b/test/CodeGen/AMDGPU/fmad.ll index 935e35123f45..9c39bee753be 100644 --- a/test/CodeGen/AMDGPU/fmad.ll +++ b/test/CodeGen/AMDGPU/fmad.ll @@ -2,18 +2,16 @@ ;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = extractelement <4 x float> %reg0, i32 2 %r3 = fmul float %r0, %r1 %r4 = fadd float %r3, %r2 %vec = insertelement <4 x float> undef, float %r4, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @fabs(float ) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/fmax.ll b/test/CodeGen/AMDGPU/fmax.ll index d7127f485c74..763040522718 100644 --- a/test/CodeGen/AMDGPU/fmax.ll +++ b/test/CodeGen/AMDGPU/fmax.ll @@ -2,16 +2,14 @@ ;CHECK: MAX * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = fcmp oge float %r0, %r1 %r3 = select i1 %r2, float %r0, float %r1 %vec = insertelement <4 x float> undef, float %r3, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/fmax3.f64.ll b/test/CodeGen/AMDGPU/fmax3.f64.ll index f78c71b28264..9bbfe1e95c5b 100644 --- a/test/CodeGen/AMDGPU/fmax3.f64.ll +++ b/test/CodeGen/AMDGPU/fmax3.f64.ll @@ -4,9 +4,9 @@ declare double @llvm.maxnum.f64(double, double) nounwind readnone ; SI-LABEL: {{^}}test_fmax3_f64: -; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0{{$}} -; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:8 -; SI-DAG: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}}], 0 offset:16 +; SI-DAG: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}} +; SI-DAG: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8 +; SI-DAG: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16 ; SI: v_max_f64 [[REGA]], [[REGA]], [[REGB]] ; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGC]] ; SI: buffer_store_dwordx2 [[RESULT]], @@ -14,9 +14,9 @@ declare double @llvm.maxnum.f64(double, double) nounwind readnone define void @test_fmax3_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { %bptr = getelementptr double, double addrspace(1)* %aptr, i32 1 %cptr = getelementptr double, double addrspace(1)* %aptr, i32 2 - %a = load double, double addrspace(1)* %aptr, align 8 - %b = load double, double addrspace(1)* %bptr, align 8 - %c = load double, double addrspace(1)* %cptr, align 8 + %a = load volatile double, double addrspace(1)* %aptr, align 8 + %b = load volatile double, double addrspace(1)* %bptr, align 8 + %c = load volatile double, double addrspace(1)* %cptr, align 8 %f0 = call double @llvm.maxnum.f64(double %a, double %b) nounwind readnone %f1 = call double @llvm.maxnum.f64(double %f0, double %c) nounwind readnone store double %f1, double addrspace(1)* %out, align 8 diff --git a/test/CodeGen/AMDGPU/fmax3.ll b/test/CodeGen/AMDGPU/fmax3.ll index c3028a6217d5..c0fde6e97f6f 100644 --- a/test/CodeGen/AMDGPU/fmax3.ll +++ b/test/CodeGen/AMDGPU/fmax3.ll @@ -11,9 +11,9 @@ declare float @llvm.maxnum.f32(float, float) nounwind readnone ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind { - %a = load float, float addrspace(1)* %aptr, align 4 - %b = load float, float addrspace(1)* %bptr, align 4 - %c = load float, float addrspace(1)* %cptr, align 4 + %a = load volatile float, float addrspace(1)* %aptr, align 4 + %b = load volatile float, float addrspace(1)* %bptr, align 4 + %c = load volatile float, float addrspace(1)* %cptr, align 4 %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone %f1 = call float @llvm.maxnum.f32(float %f0, float %c) nounwind readnone store float %f1, float addrspace(1)* %out, align 4 @@ -29,9 +29,9 @@ define void @test_fmax3_olt_0(float addrspace(1)* %out, float addrspace(1)* %apt ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm define void @test_fmax3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind { - %a = load float, float addrspace(1)* %aptr, align 4 - %b = load float, float addrspace(1)* %bptr, align 4 - %c = load float, float addrspace(1)* %cptr, align 4 + %a = load volatile float, float addrspace(1)* %aptr, align 4 + %b = load volatile float, float addrspace(1)* %bptr, align 4 + %c = load volatile float, float addrspace(1)* %cptr, align 4 %f0 = call float @llvm.maxnum.f32(float %a, float %b) nounwind readnone %f1 = call float @llvm.maxnum.f32(float %c, float %f0) nounwind readnone store float %f1, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/AMDGPU/fmax_legacy.f64.ll b/test/CodeGen/AMDGPU/fmax_legacy.f64.ll index 828243888ac7..da498caa6b54 100644 --- a/test/CodeGen/AMDGPU/fmax_legacy.f64.ll +++ b/test/CodeGen/AMDGPU/fmax_legacy.f64.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; Make sure we don't try to form FMAX_LEGACY nodes with f64 -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; FUNC-LABEL: @test_fmax_legacy_uge_f64 define void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -20,7 +20,7 @@ define void @test_fmax_legacy_uge_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmax_legacy_oge_f64 define void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -35,7 +35,7 @@ define void @test_fmax_legacy_oge_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmax_legacy_ugt_f64 define void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -50,7 +50,7 @@ define void @test_fmax_legacy_ugt_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmax_legacy_ogt_f64 define void @test_fmax_legacy_ogt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 diff --git a/test/CodeGen/AMDGPU/fmax_legacy.ll b/test/CodeGen/AMDGPU/fmax_legacy.ll index d374fb67350c..4a4c92a38a35 100644 --- a/test/CodeGen/AMDGPU/fmax_legacy.ll +++ b/test/CodeGen/AMDGPU/fmax_legacy.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s -; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s +; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FIXME: Should replace unsafe-fp-math with no signed zeros. @@ -18,8 +18,8 @@ define void @test_fmax_legacy_uge_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp uge float %a, %b %val = select i1 %cmp, float %a, float %b @@ -38,8 +38,8 @@ define void @test_fmax_legacy_oge_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp oge float %a, %b %val = select i1 %cmp, float %a, float %b @@ -58,8 +58,8 @@ define void @test_fmax_legacy_ugt_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ugt float %a, %b %val = select i1 %cmp, float %a, float %b @@ -78,8 +78,8 @@ define void @test_fmax_legacy_ogt_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ogt float %a, %b %val = select i1 %cmp, float %a, float %b @@ -142,8 +142,8 @@ define void @test_fmax_legacy_ogt_f32_multi_use(float addrspace(1)* %out0, i1 ad %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ogt float %a, %b %val = select i1 %cmp, float %a, float %b diff --git a/test/CodeGen/AMDGPU/fmaxnum.ll b/test/CodeGen/AMDGPU/fmaxnum.ll index 3029bd02e4db..a2b33a794d99 100644 --- a/test/CodeGen/AMDGPU/fmaxnum.ll +++ b/test/CodeGen/AMDGPU/fmaxnum.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare float @llvm.maxnum.f32(float, float) #0 declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #0 @@ -207,7 +207,7 @@ define void @constant_fold_fmax_f32_p0_n0(float addrspace(1)* %out) nounwind { ; FUNC-LABEL: @constant_fold_fmax_f32_n0_p0 ; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; SI: buffer_store_dword [[REG]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] @@ -221,7 +221,7 @@ define void @constant_fold_fmax_f32_n0_p0(float addrspace(1)* %out) nounwind { ; FUNC-LABEL: @constant_fold_fmax_f32_n0_n0 ; SI-NOT: v_max_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; SI: buffer_store_dword [[REG]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] diff --git a/test/CodeGen/AMDGPU/fmed3.ll b/test/CodeGen/AMDGPU/fmed3.ll new file mode 100644 index 000000000000..e66678069130 --- /dev/null +++ b/test/CodeGen/AMDGPU/fmed3.ll @@ -0,0 +1,154 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=NOSNAN -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mattr=+fp-exceptions -verify-machineinstrs < %s | FileCheck -check-prefix=SNAN -check-prefix=GCN %s + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare float @llvm.minnum.f32(float, float) #0 +declare float @llvm.maxnum.f32(float, float) #0 +declare double @llvm.minnum.f64(double, double) #0 +declare double @llvm.maxnum.f64(double, double) #0 + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f32: +; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0 + +; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +define void @v_test_fmed3_r_i_i_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float %a, float 2.0) + %med = call float @llvm.minnum.f32(float %max, float 4.0) + + store float %med, float addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute0_f32: +; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0 + +; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +define void @v_test_fmed3_r_i_i_commute0_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float 2.0, float %a) + %med = call float @llvm.minnum.f32(float 4.0, float %max) + + store float %med, float addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_commute1_f32: +; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0 + +; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +define void @v_test_fmed3_r_i_i_commute1_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float %a, float 2.0) + %med = call float @llvm.minnum.f32(float 4.0, float %max) + + store float %med, float addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_constant_order_f32: +; GCN: v_max_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +; GCN: v_min_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +define void @v_test_fmed3_r_i_i_constant_order_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float %a, float 4.0) + %med = call float @llvm.minnum.f32(float %max, float 2.0) + + store float %med, float addrspace(1)* %outgep + ret void +} + + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_multi_use_f32: +; GCN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +; GCN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +define void @v_test_fmed3_r_i_i_multi_use_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float %a, float 2.0) + %med = call float @llvm.minnum.f32(float %max, float 4.0) + + store volatile float %med, float addrspace(1)* %outgep + store volatile float %max, float addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_f64: +; GCN: v_max_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, 2.0 +; GCN: v_min_f64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, 4.0 +define void @v_test_fmed3_r_i_i_f64(double addrspace(1)* %out, double addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr double, double addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr double, double addrspace(1)* %out, i32 %tid + %a = load double, double addrspace(1)* %gep0 + + %max = call double @llvm.maxnum.f64(double %a, double 2.0) + %med = call double @llvm.minnum.f64(double %max, double 4.0) + + store double %med, double addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_fmed3_r_i_i_no_nans_f32: +; GCN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0 +define void @v_test_fmed3_r_i_i_no_nans_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #2 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + %max = call float @llvm.maxnum.f32(float %a, float 2.0) + %med = call float @llvm.minnum.f32(float %max, float 4.0) + + store float %med, float addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_legacy_fmed3_r_i_i_f32: +; NOSNAN: v_med3_f32 v{{[0-9]+}}, v{{[0-9]+}}, 2.0, 4.0 + +; SNAN: v_max_f32_e32 v{{[0-9]+}}, 2.0, v{{[0-9]+}} +; SNAN: v_min_f32_e32 v{{[0-9]+}}, 4.0, v{{[0-9]+}} +define void @v_test_legacy_fmed3_r_i_i_f32(float addrspace(1)* %out, float addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep0 + + ; fmax_legacy + %cmp0 = fcmp ule float %a, 2.0 + %max = select i1 %cmp0, float 2.0, float %a + + ; fmin_legacy + %cmp1 = fcmp uge float %max, 4.0 + %med = select i1 %cmp1, float 4.0, float %max + + store float %med, float addrspace(1)* %outgep + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="false" } +attributes #2 = { nounwind "unsafe-fp-math"="false" "no-nans-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/fmin.ll b/test/CodeGen/AMDGPU/fmin.ll index defa8c09638a..d044a7a0542c 100644 --- a/test/CodeGen/AMDGPU/fmin.ll +++ b/test/CodeGen/AMDGPU/fmin.ll @@ -2,16 +2,14 @@ ;CHECK: MIN * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = fcmp uge float %r0, %r1 %r3 = select i1 %r2, float %r1, float %r0 %vec = insertelement <4 x float> undef, float %r3, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/fmin3.ll b/test/CodeGen/AMDGPU/fmin3.ll index 0a76699b43e1..2d1facfc3a40 100644 --- a/test/CodeGen/AMDGPU/fmin3.ll +++ b/test/CodeGen/AMDGPU/fmin3.ll @@ -12,9 +12,9 @@ declare float @llvm.minnum.f32(float, float) nounwind readnone ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind { - %a = load float, float addrspace(1)* %aptr, align 4 - %b = load float, float addrspace(1)* %bptr, align 4 - %c = load float, float addrspace(1)* %cptr, align 4 + %a = load volatile float, float addrspace(1)* %aptr, align 4 + %b = load volatile float, float addrspace(1)* %bptr, align 4 + %c = load volatile float, float addrspace(1)* %cptr, align 4 %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone %f1 = call float @llvm.minnum.f32(float %f0, float %c) nounwind readnone store float %f1, float addrspace(1)* %out, align 4 @@ -30,9 +30,9 @@ define void @test_fmin3_olt_0(float addrspace(1)* %out, float addrspace(1)* %apt ; SI: buffer_store_dword [[RESULT]], ; SI: s_endpgm define void @test_fmin3_olt_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) nounwind { - %a = load float, float addrspace(1)* %aptr, align 4 - %b = load float, float addrspace(1)* %bptr, align 4 - %c = load float, float addrspace(1)* %cptr, align 4 + %a = load volatile float, float addrspace(1)* %aptr, align 4 + %b = load volatile float, float addrspace(1)* %bptr, align 4 + %c = load volatile float, float addrspace(1)* %cptr, align 4 %f0 = call float @llvm.minnum.f32(float %a, float %b) nounwind readnone %f1 = call float @llvm.minnum.f32(float %c, float %f0) nounwind readnone store float %f1, float addrspace(1)* %out, align 4 diff --git a/test/CodeGen/AMDGPU/fmin_legacy.f64.ll b/test/CodeGen/AMDGPU/fmin_legacy.f64.ll index e19a48f3f7e2..6982ee0c0cb3 100644 --- a/test/CodeGen/AMDGPU/fmin_legacy.f64.ll +++ b/test/CodeGen/AMDGPU/fmin_legacy.f64.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; FUNC-LABEL: @test_fmin_legacy_f64 define void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double> inreg %reg0) #0 { @@ -15,7 +15,7 @@ define void @test_fmin_legacy_f64(<4 x double> addrspace(1)* %out, <4 x double> ; FUNC-LABEL: @test_fmin_legacy_ule_f64 define void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -30,7 +30,7 @@ define void @test_fmin_legacy_ule_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmin_legacy_ole_f64 define void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -45,7 +45,7 @@ define void @test_fmin_legacy_ole_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmin_legacy_olt_f64 define void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 @@ -60,7 +60,7 @@ define void @test_fmin_legacy_olt_f64(double addrspace(1)* %out, double addrspac ; FUNC-LABEL: @test_fmin_legacy_ult_f64 define void @test_fmin_legacy_ult_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 diff --git a/test/CodeGen/AMDGPU/fmin_legacy.ll b/test/CodeGen/AMDGPU/fmin_legacy.ll index 69a0a520a476..79acd02e6d1f 100644 --- a/test/CodeGen/AMDGPU/fmin_legacy.ll +++ b/test/CodeGen/AMDGPU/fmin_legacy.ll @@ -1,16 +1,20 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -enable-no-nans-fp-math -enable-unsafe-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NONAN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FIXME: Should replace unsafe-fp-math with no signed zeros. declare i32 @llvm.r600.read.tidig.x() #1 -; FUNC-LABEL: @test_fmin_legacy_f32 +; The two inputs to the instruction are different SGPRs from the same +; super register, so we can't fold both SGPR operands even though they +; are both the same register. + +; FUNC-LABEL: {{^}}s_test_fmin_legacy_subreg_inputs_f32: ; EG: MIN * -; SI-SAFE: v_min_legacy_f32_e64 -; SI-NONAN: v_min_f32_e64 -define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 { +; SI-SAFE: v_min_legacy_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} +; SI-NONAN: v_min_f32_e32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_fmin_legacy_subreg_inputs_f32(<4 x float> addrspace(1)* %out, <4 x float> inreg %reg0) #0 { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = fcmp uge float %r0, %r1 @@ -20,6 +24,23 @@ define void @test_fmin_legacy_f32(<4 x float> addrspace(1)* %out, <4 x float> in ret void } +; FUNC-LABEL: {{^}}s_test_fmin_legacy_ule_f32: +; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc + +; SI-SAFE-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]] +; SI-NONAN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] + +; SI-SAFE: v_min_legacy_f32_e32 {{v[0-9]+}}, [[B]], [[VA]] +; SI-NONAN: v_min_f32_e32 {{v[0-9]+}}, [[A]], [[VB]] + +define void @s_test_fmin_legacy_ule_f32(float addrspace(1)* %out, float %a, float %b) #0 { + %cmp = fcmp ule float %a, %b + %val = select i1 %cmp, float %a, float %b + store float %val, float addrspace(1)* %out, align 4 + ret void +} + ; FUNC-LABEL: @test_fmin_legacy_ule_f32 ; SI: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 @@ -30,8 +51,8 @@ define void @test_fmin_legacy_ule_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ule float %a, %b %val = select i1 %cmp, float %a, float %b @@ -49,8 +70,8 @@ define void @test_fmin_legacy_ole_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ole float %a, %b %val = select i1 %cmp, float %a, float %b @@ -68,8 +89,8 @@ define void @test_fmin_legacy_olt_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp olt float %a, %b %val = select i1 %cmp, float %a, float %b @@ -87,8 +108,8 @@ define void @test_fmin_legacy_ult_f32(float addrspace(1)* %out, float addrspace( %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ult float %a, %b %val = select i1 %cmp, float %a, float %b @@ -172,8 +193,8 @@ define void @test_fmin_legacy_ole_f32_multi_use(float addrspace(1)* %out0, i1 ad %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %cmp = fcmp ole float %a, %b %val0 = select i1 %cmp, float %a, float %b diff --git a/test/CodeGen/AMDGPU/fminnum.ll b/test/CodeGen/AMDGPU/fminnum.ll index 4d7b52540d85..04cb01260bc0 100644 --- a/test/CodeGen/AMDGPU/fminnum.ll +++ b/test/CodeGen/AMDGPU/fminnum.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare float @llvm.minnum.f32(float, float) #0 @@ -206,7 +206,7 @@ define void @constant_fold_fmin_f32_p0_n0(float addrspace(1)* %out) nounwind { ; FUNC-LABEL: @constant_fold_fmin_f32_n0_p0 ; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; SI: buffer_store_dword [[REG]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] @@ -220,7 +220,7 @@ define void @constant_fold_fmin_f32_n0_p0(float addrspace(1)* %out) nounwind { ; FUNC-LABEL: @constant_fold_fmin_f32_n0_n0 ; SI-NOT: v_min_f32_e32 -; SI: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; SI: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; SI: buffer_store_dword [[REG]] ; EG: MEM_RAT_CACHELESS STORE_RAW [[OUT:T[0-9]+\.[XYZW]]] diff --git a/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll b/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll index 1ee92b2f7c08..867c5c252b6c 100644 --- a/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll +++ b/test/CodeGen/AMDGPU/fmul-2-combine-multi-use.ll @@ -36,8 +36,8 @@ define void @multiple_use_fadd_fmac(float addrspace(1)* %out, float %x, float %y %out.gep.1 = getelementptr float, float addrspace(1)* %out, i32 1 %mul2 = fmul fast float %x, 2.0 %mad = fadd fast float %mul2, %y - store float %mul2, float addrspace(1)* %out - store float %mad, float addrspace(1)* %out.gep.1 + store volatile float %mul2, float addrspace(1)* %out + store volatile float %mad, float addrspace(1)* %out.gep.1 ret void } @@ -52,8 +52,8 @@ define void @multiple_use_fadd_fmad(float addrspace(1)* %out, float %x, float %y %x.abs = call float @llvm.fabs.f32(float %x) %mul2 = fmul fast float %x.abs, 2.0 %mad = fadd fast float %mul2, %y - store float %mul2, float addrspace(1)* %out - store float %mad, float addrspace(1)* %out.gep.1 + store volatile float %mul2, float addrspace(1)* %out + store volatile float %mad, float addrspace(1)* %out.gep.1 ret void } @@ -66,8 +66,8 @@ define void @multiple_use_fadd_multi_fmad(float addrspace(1)* %out, float %x, fl %mul2 = fmul fast float %x.abs, 2.0 %mad0 = fadd fast float %mul2, %y %mad1 = fadd fast float %mul2, %z - store float %mad0, float addrspace(1)* %out - store float %mad1, float addrspace(1)* %out.gep.1 + store volatile float %mad0, float addrspace(1)* %out + store volatile float %mad1, float addrspace(1)* %out.gep.1 ret void } @@ -80,7 +80,7 @@ define void @fmul_x2_xn2(float addrspace(1)* %out, float %x, float %y) #0 { %mul2 = fmul fast float %x, 2.0 %muln2 = fmul fast float %x, -2.0 %mul = fmul fast float %mul2, %muln2 - store float %mul, float addrspace(1)* %out + store volatile float %mul, float addrspace(1)* %out ret void } @@ -94,7 +94,7 @@ define void @fmul_x2_xn3(float addrspace(1)* %out, float %x, float %y) #0 { %mul2 = fmul fast float %x, 2.0 %muln2 = fmul fast float %x, -3.0 %mul = fmul fast float %mul2, %muln2 - store float %mul, float addrspace(1)* %out + store volatile float %mul, float addrspace(1)* %out ret void } diff --git a/test/CodeGen/AMDGPU/fmul.ll b/test/CodeGen/AMDGPU/fmul.ll index addc409c9eb1..9064ad3814d6 100644 --- a/test/CodeGen/AMDGPU/fmul.ll +++ b/test/CodeGen/AMDGPU/fmul.ll @@ -1,12 +1,11 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s - ; FUNC-LABEL: {{^}}fmul_f32: -; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W +; GCN: v_mul_f32 -; SI: v_mul_f32 +; R600: MUL_IEEE {{\** *}}{{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].W define void @fmul_f32(float addrspace(1)* %out, float %a, float %b) { entry: %0 = fmul float %a, %b @@ -14,16 +13,16 @@ entry: ret void } -declare float @llvm.R600.load.input(i32) readnone +declare float @llvm.r600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) ; FUNC-LABEL: {{^}}fmul_v2f32: +; GCN: v_mul_f32 +; GCN: v_mul_f32 + ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}} - -; SI: v_mul_f32 -; SI: v_mul_f32 define void @fmul_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fmul <2 x float> %a, %b @@ -32,15 +31,15 @@ entry: } ; FUNC-LABEL: {{^}}fmul_v4f32: +; GCN: v_mul_f32 +; GCN: v_mul_f32 +; GCN: v_mul_f32 +; GCN: v_mul_f32 + ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; R600: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -; SI: v_mul_f32 -; SI: v_mul_f32 -; SI: v_mul_f32 -; SI: v_mul_f32 define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float>, <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float>, <4 x float> addrspace(1) * %in @@ -51,9 +50,9 @@ define void @fmul_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1) } ; FUNC-LABEL: {{^}}test_mul_2_k: -; SI: v_mul_f32 -; SI-NOT: v_mul_f32 -; SI: s_endpgm +; GCN: v_mul_f32 +; GCN-NOT: v_mul_f32 +; GCN: s_endpgm define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 2.0 %z = fmul float %y, 3.0 @@ -62,10 +61,10 @@ define void @test_mul_2_k(float addrspace(1)* %out, float %x) #0 { } ; FUNC-LABEL: {{^}}test_mul_2_k_inv: -; SI: v_mul_f32 -; SI-NOT: v_mul_f32 -; SI-NOT: v_mad_f32 -; SI: s_endpgm +; GCN: v_mul_f32 +; GCN-NOT: v_mul_f32 +; GCN-NOT: v_mad_f32 +; GCN: s_endpgm define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { %y = fmul float %x, 3.0 %z = fmul float %y, 2.0 @@ -76,10 +75,10 @@ define void @test_mul_2_k_inv(float addrspace(1)* %out, float %x) #0 { ; There should be three multiplies here; %a should be used twice (once ; negated), not duplicated into mul x, 5.0 and mul x, -5.0. ; FUNC-LABEL: {{^}}test_mul_twouse: -; SI: v_mul_f32 -; SI: v_mul_f32 -; SI: v_mul_f32 -; SI-NOT: v_mul_f32 +; GCN: v_mul_f32 +; GCN: v_mul_f32 +; GCN: v_mul_f32 +; GCN-NOT: v_mul_f32 define void @test_mul_twouse(float addrspace(1)* %out, float %x, float %y) #0 { %a = fmul float %x, 5.0 %b = fsub float -0.0, %a @@ -89,4 +88,4 @@ define void @test_mul_twouse(float addrspace(1)* %out, float %x, float %y) #0 { ret void } -attributes #0 = { "less-precise-fpmad"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "unsafe-fp-math"="true" } +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/fmuladd.ll b/test/CodeGen/AMDGPU/fmuladd.ll index 600f0cb83578..c80374df4950 100644 --- a/test/CodeGen/AMDGPU/fmuladd.ll +++ b/test/CodeGen/AMDGPU/fmuladd.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s declare float @llvm.fmuladd.f32(float, float, float) declare double @llvm.fmuladd.f64(double, double, double) -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare float @llvm.fabs.f32(float) nounwind readnone ; CHECK-LABEL: {{^}}fmuladd_f32: @@ -37,13 +37,13 @@ define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1, ; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]] ; CHECK: buffer_store_dword [[R2]] define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2) store float %r3, float addrspace(1)* %gep.out @@ -56,13 +56,13 @@ define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* % ; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]] ; CHECK: buffer_store_dword [[R2]] define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2) store float %r3, float addrspace(1)* %gep.out @@ -77,13 +77,13 @@ define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* % define void @fadd_a_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r0 = load float, float addrspace(1)* %gep.0 - %r1 = load float, float addrspace(1)* %gep.1 + %r0 = load volatile float, float addrspace(1)* %gep.0 + %r1 = load volatile float, float addrspace(1)* %gep.1 %add.0 = fadd float %r0, %r0 %add.1 = fadd float %add.0, %r1 @@ -99,13 +99,13 @@ define void @fadd_a_a_b_f32(float addrspace(1)* %out, define void @fadd_b_a_a_f32(float addrspace(1)* %out, float addrspace(1)* %in1, float addrspace(1)* %in2) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r0 = load float, float addrspace(1)* %gep.0 - %r1 = load float, float addrspace(1)* %gep.1 + %r0 = load volatile float, float addrspace(1)* %gep.0 + %r1 = load volatile float, float addrspace(1)* %gep.1 %add.0 = fadd float %r0, %r0 %add.1 = fadd float %r1, %add.0 @@ -119,13 +119,13 @@ define void @fadd_b_a_a_f32(float addrspace(1)* %out, ; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]] ; CHECK: buffer_store_dword [[R2]] define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2) store float %r3, float addrspace(1)* %gep.out @@ -139,13 +139,13 @@ define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1 ; CHECK: v_mac_f32_e32 [[R2]], 2.0, [[R1]] ; CHECK: buffer_store_dword [[R2]] define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r1.fneg = fsub float -0.000000e+00, %r1 @@ -161,13 +161,13 @@ define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspa ; CHECK: v_mac_f32_e32 [[R2]], -2.0, [[R1]] ; CHECK: buffer_store_dword [[R2]] define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r1.fneg = fsub float -0.000000e+00, %r1 @@ -183,13 +183,13 @@ define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1 ; CHECK: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] ; CHECK: buffer_store_dword [[RESULT]] define void @fmuladd_2.0_a_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %r2.fneg = fsub float -0.000000e+00, %r2 diff --git a/test/CodeGen/AMDGPU/fneg-fabs.f64.ll b/test/CodeGen/AMDGPU/fneg-fabs.f64.ll index 8830e8273661..b03f318f4571 100644 --- a/test/CodeGen/AMDGPU/fneg-fabs.f64.ll +++ b/test/CodeGen/AMDGPU/fneg-fabs.f64.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; FIXME: Check something here. Currently it seems fabs + fneg aren't ; into 2 modifiers, although theoretically that should work. -; FUNC-LABEL: {{^}}fneg_fabs_fadd_f64: -; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}| +; GCN-LABEL: {{^}}fneg_fabs_fadd_f64: +; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|v{{\[[0-9]+:[0-9]+\]}}| define void @fneg_fabs_fadd_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs @@ -24,8 +24,8 @@ define void @v_fneg_fabs_fadd_f64(double addrspace(1)* %out, double addrspace(1) ret void } -; FUNC-LABEL: {{^}}fneg_fabs_fmul_f64: -; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}| +; GCN-LABEL: {{^}}fneg_fabs_fmul_f64: +; GCN: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, -|{{v\[[0-9]+:[0-9]+\]}}| define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) { %fabs = call double @llvm.fabs.f64(double %x) %fsub = fsub double -0.000000e+00, %fabs @@ -34,7 +34,7 @@ define void @fneg_fabs_fmul_f64(double addrspace(1)* %out, double %x, double %y) ret void } -; FUNC-LABEL: {{^}}fneg_fabs_free_f64: +; GCN-LABEL: {{^}}fneg_fabs_free_f64: define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) { %bc = bitcast i64 %in to double %fabs = call double @llvm.fabs.f64(double %bc) @@ -43,9 +43,9 @@ define void @fneg_fabs_free_f64(double addrspace(1)* %out, i64 %in) { ret void } -; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f64: -; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN-LABEL: {{^}}fneg_fabs_fn_free_f64: +; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}} +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) { %bc = bitcast i64 %in to double %fabs = call double @fabs(double %bc) @@ -54,13 +54,14 @@ define void @fneg_fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) { ret void } -; FUNC-LABEL: {{^}}fneg_fabs_f64: -; SI: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}} -; SI: s_load_dwordx2 -; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]] -; SI-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]] -; SI: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}} +; GCN-LABEL: {{^}}fneg_fabs_f64: +; GCN-DAG: s_load_dwordx2 +; GCN-DAG: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}} +; SI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xb +; VI-DAG: s_load_dwordx2 s{{\[}}[[LO_X:[0-9]+]]:[[HI_X:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x2c +; GCN-DAG: v_or_b32_e32 v[[HI_V:[0-9]+]], s[[HI_X]], [[IMMREG]] +; GCN-DAG: v_mov_b32_e32 v[[LO_V:[0-9]+]], s[[LO_X]] +; GCN: buffer_store_dwordx2 v{{\[}}[[LO_V]]:[[HI_V]]{{\]}} define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) { %fabs = call double @llvm.fabs.f64(double %in) %fsub = fsub double -0.000000e+00, %fabs @@ -68,11 +69,11 @@ define void @fneg_fabs_f64(double addrspace(1)* %out, double %in) { ret void } -; FUNC-LABEL: {{^}}fneg_fabs_v2f64: -; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI-NOT: 0x80000000 -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN-LABEL: {{^}}fneg_fabs_v2f64: +; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}} +; GCN-NOT: 0x80000000 +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) { %fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in) %fsub = fsub <2 x double> , %fabs @@ -80,13 +81,13 @@ define void @fneg_fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) ret void } -; FUNC-LABEL: {{^}}fneg_fabs_v4f64: -; SI: v_mov_b32_e32 [[IMMREG:v[0-9]+]], 0x80000000 -; SI-NOT: 0x80000000 -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] -; SI: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN-LABEL: {{^}}fneg_fabs_v4f64: +; GCN: v_bfrev_b32_e32 [[IMMREG:v[0-9]+]], 1{{$}} +; GCN-NOT: 0x80000000 +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] +; GCN: v_or_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}, [[IMMREG]] define void @fneg_fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) { %fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in) %fsub = fsub <4 x double> , %fabs diff --git a/test/CodeGen/AMDGPU/fneg.f64.ll b/test/CodeGen/AMDGPU/fneg.f64.ll index aa6df209035b..7627a4d32250 100644 --- a/test/CodeGen/AMDGPU/fneg.f64.ll +++ b/test/CodeGen/AMDGPU/fneg.f64.ll @@ -39,7 +39,7 @@ define void @fneg_v4f64(<4 x double> addrspace(1)* nocapture %out, <4 x double> ; unless the target returns true for isNegFree() ; FUNC-LABEL: {{^}}fneg_free_f64: -; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, 0, -{{s\[[0-9]+:[0-9]+\]$}} +; GCN: v_add_f64 {{v\[[0-9]+:[0-9]+\]}}, -{{s\[[0-9]+:[0-9]+\]}}, 0{{$}} define void @fneg_free_f64(double addrspace(1)* %out, i64 %in) { %bc = bitcast i64 %in to double %fsub = fsub double 0.0, %bc diff --git a/test/CodeGen/AMDGPU/fp-classify.ll b/test/CodeGen/AMDGPU/fp-classify.ll index 4fac5176fac9..b7ffaed70c5a 100644 --- a/test/CodeGen/AMDGPU/fp-classify.ll +++ b/test/CodeGen/AMDGPU/fp-classify.ll @@ -1,9 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i1 @llvm.AMDGPU.class.f32(float, i32) #1 -declare i1 @llvm.AMDGPU.class.f64(double, i32) #1 -declare i32 @llvm.r600.read.tidig.x() #1 declare float @llvm.fabs.f32(float) #1 declare double @llvm.fabs.f64(double) #1 diff --git a/test/CodeGen/AMDGPU/fp_to_sint.f64.ll b/test/CodeGen/AMDGPU/fp_to_sint.f64.ll index 12df6606e8ff..be23e10d7087 100644 --- a/test/CodeGen/AMDGPU/fp_to_sint.f64.ll +++ b/test/CodeGen/AMDGPU/fp_to_sint.f64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; FUNC-LABEL: @fp_to_sint_f64_i32 ; SI: v_cvt_i32_f64_e32 @@ -47,7 +47,7 @@ define void @fp_to_sint_v4f64_v4i32(<4 x i32> addrspace(1)* %out, <4 x double> % ; CI-DAG: v_cvt_i32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] ; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @fp_to_sint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep = getelementptr double, double addrspace(1)* %in, i32 %tid %val = load double, double addrspace(1)* %gep, align 8 %cast = fptosi double %val to i64 diff --git a/test/CodeGen/AMDGPU/fp_to_sint.ll b/test/CodeGen/AMDGPU/fp_to_sint.ll index 301a94b4904c..b39aeadc8cce 100644 --- a/test/CodeGen/AMDGPU/fp_to_sint.ll +++ b/test/CodeGen/AMDGPU/fp_to_sint.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=EG --check-prefix=FUNC declare float @llvm.fabs.f32(float) #0 diff --git a/test/CodeGen/AMDGPU/fp_to_uint.f64.ll b/test/CodeGen/AMDGPU/fp_to_uint.f64.ll index 41bc2a780014..760019ebdc08 100644 --- a/test/CodeGen/AMDGPU/fp_to_uint.f64.ll +++ b/test/CodeGen/AMDGPU/fp_to_uint.f64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; SI-LABEL: {{^}}fp_to_uint_i32_f64: ; SI: v_cvt_u32_f64_e32 @@ -47,7 +47,7 @@ define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> % ; CI-DAG: v_cvt_u32_f64_e32 v[[HI:[0-9]+]], [[FLOOR]] ; CI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep = getelementptr double, double addrspace(1)* %in, i32 %tid %val = load double, double addrspace(1)* %gep, align 8 %cast = fptoui double %val to i64 diff --git a/test/CodeGen/AMDGPU/fpext.ll b/test/CodeGen/AMDGPU/fpext.ll index 734a43be2296..ad06bdd90a9f 100644 --- a/test/CodeGen/AMDGPU/fpext.ll +++ b/test/CodeGen/AMDGPU/fpext.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}fpext_f32_to_f64: @@ -18,6 +18,16 @@ define void @fpext_v2f32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x float> % ret void } +; FUNC-LABEL: {{^}}fpext_v3f32_to_v3f64: +; SI: v_cvt_f64_f32_e32 +; SI: v_cvt_f64_f32_e32 +; SI: v_cvt_f64_f32_e32 +define void @fpext_v3f32_to_v3f64(<3 x double> addrspace(1)* %out, <3 x float> %in) { + %result = fpext <3 x float> %in to <3 x double> + store <3 x double> %result, <3 x double> addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}fpext_v4f32_to_v4f64: ; SI: v_cvt_f64_f32_e32 ; SI: v_cvt_f64_f32_e32 diff --git a/test/CodeGen/AMDGPU/fract.f64.ll b/test/CodeGen/AMDGPU/fract.f64.ll new file mode 100644 index 000000000000..68b884363ec5 --- /dev/null +++ b/test/CodeGen/AMDGPU/fract.f64.ll @@ -0,0 +1,111 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s + +; RUN: llc -march=amdgcn -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=SI-UNSAFE -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=VI-UNSAFE -check-prefix=FUNC %s + +declare double @llvm.fabs.f64(double) #0 +declare double @llvm.floor.f64(double) #0 + +; FUNC-LABEL: {{^}}fract_f64: +; SI-DAG: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] +; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 +; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] +; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} +; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]] + +; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; CI: v_floor_f64_e32 [[FLOORX:v\[[0-9]+:[0-9]+\]]], [[X]] +; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[FLOORX]] + +; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; GCN-UNSAFE: v_fract_f64_e32 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]] + +; GCN: buffer_store_dwordx2 [[FRACT]] +define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 { + %x = load double, double addrspace(1)* %src + %floor.x = call double @llvm.floor.f64(double %x) + %fract = fsub double %x, %floor.x + store double %fract, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}fract_f64_neg: +; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] +; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 +; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] +; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} +; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO]]:[[HI]]{{\]}}, -[[SUB0]] + +; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -[[X]] +; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]], -[[FLOORX]] + +; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -[[X]] + +; GCN: buffer_store_dwordx2 [[FRACT]] +define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) #1 { + %x = load double, double addrspace(1)* %src + %neg.x = fsub double -0.0, %x + %floor.neg.x = call double @llvm.floor.f64(double %neg.x) + %fract = fsub double %neg.x, %floor.neg.x + store double %fract, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}fract_f64_neg_abs: +; SI-DAG: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]| +; SI-DAG: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 +; SI-DAG: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff +; SI-DAG: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] +; SI-DAG: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 +; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] +; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] +; SI: v_add_f64 [[SUB0:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO]]:[[HI]]{{\]}}|, -v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} +; SI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO]]:[[HI]]{{\]}}|, -[[SUB0]] + +; CI: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; CI: v_floor_f64_e64 [[FLOORX:v\[[0-9]+:[0-9]+\]]], -|[[X]]| +; CI: v_add_f64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]|, -[[FLOORX]] + +; GCN-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; GCN-UNSAFE: v_fract_f64_e64 [[FRACT:v\[[0-9]+:[0-9]+\]]], -|[[X]]| + +; GCN: buffer_store_dwordx2 [[FRACT]] +define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) #1 { + %x = load double, double addrspace(1)* %src + %abs.x = call double @llvm.fabs.f64(double %x) + %neg.abs.x = fsub double -0.0, %abs.x + %floor.neg.abs.x = call double @llvm.floor.f64(double %neg.abs.x) + %fract = fsub double %neg.abs.x, %floor.neg.abs.x + store double %fract, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}multi_use_floor_fract_f64: +; VI-UNSAFE: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]] +; VI-UNSAFE-DAG: v_floor_f64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[X]] +; VI-UNSAFE-DAG: v_fract_f64_e32 [[FRACT:v\[[0-9]+:[0-9]+\]]], [[X]] +; VI-UNSAFE: buffer_store_dwordx2 [[FLOOR]] +; VI-UNSAFE: buffer_store_dwordx2 [[FRACT]] +define void @multi_use_floor_fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) #1 { + %x = load double, double addrspace(1)* %src + %floor.x = call double @llvm.floor.f64(double %x) + %fract = fsub double %x, %floor.x + store volatile double %floor.x, double addrspace(1)* %out + store volatile double %fract, double addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/fract.ll b/test/CodeGen/AMDGPU/fract.ll new file mode 100644 index 000000000000..7d713f483047 --- /dev/null +++ b/test/CodeGen/AMDGPU/fract.ll @@ -0,0 +1,74 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-SAFE -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN-UNSAFE -check-prefix=GCN %s + +declare float @llvm.fabs.f32(float) #0 +declare float @llvm.floor.f32(float) #0 + +; GCN-LABEL: {{^}}fract_f32: +; GCN-SAFE: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]] +; GCN-SAFE: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]] + +; GCN-UNSAFE: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]] + +; GCN: buffer_store_dword [[RESULT]] +define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) #1 { + %x = load float, float addrspace(1)* %src + %floor.x = call float @llvm.floor.f32(float %x) + %fract = fsub float %x, %floor.x + store float %fract, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}fract_f32_neg: +; GCN-SAFE: v_floor_f32_e64 [[FLR:v[0-9]+]], -[[INPUT:v[0-9]+]] +; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]] + +; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]] + +; GCN: buffer_store_dword [[RESULT]] +define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) #1 { + %x = load float, float addrspace(1)* %src + %x.neg = fsub float -0.0, %x + %floor.x.neg = call float @llvm.floor.f32(float %x.neg) + %fract = fsub float %x.neg, %floor.x.neg + store float %fract, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}fract_f32_neg_abs: +; GCN-SAFE: v_floor_f32_e64 [[FLR:v[0-9]+]], -|[[INPUT:v[0-9]+]]| +; GCN-SAFE: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]] + +; GCN-UNSAFE: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]| + +; GCN: buffer_store_dword [[RESULT]] +define void @fract_f32_neg_abs(float addrspace(1)* %out, float addrspace(1)* %src) #1 { + %x = load float, float addrspace(1)* %src + %abs.x = call float @llvm.fabs.f32(float %x) + %neg.abs.x = fsub float -0.0, %abs.x + %floor.neg.abs.x = call float @llvm.floor.f32(float %neg.abs.x) + %fract = fsub float %neg.abs.x, %floor.neg.abs.x + store float %fract, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}multi_use_floor_fract_f32: +; GCN-UNSAFE-DAG: v_floor_f32_e32 [[FLOOR:v[0-9]+]], [[INPUT:v[0-9]+]] +; GCN-UNSAFE-DAG: v_fract_f32_e32 [[FRACT:v[0-9]+]], [[INPUT:v[0-9]+]] + +; GCN-UNSAFE: buffer_store_dword [[FLOOR]] +; GCN-UNSAFE: buffer_store_dword [[FRACT]] +define void @multi_use_floor_fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) #1 { + %x = load float, float addrspace(1)* %src + %floor.x = call float @llvm.floor.f32(float %x) + %fract = fsub float %x, %floor.x + store volatile float %floor.x, float addrspace(1)* %out + store volatile float %fract, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/frem.ll b/test/CodeGen/AMDGPU/frem.ll index f245ef08cb9d..e0fc263294ab 100644 --- a/test/CodeGen/AMDGPU/frem.ll +++ b/test/CodeGen/AMDGPU/frem.ll @@ -5,11 +5,13 @@ ; FUNC-LABEL: {{^}}frem_f32: ; GCN-DAG: buffer_load_dword [[X:v[0-9]+]], {{.*$}} ; GCN-DAG: buffer_load_dword [[Y:v[0-9]+]], {{.*}} offset:16 -; GCN-DAG: v_cmp -; GCN-DAG: v_mul_f32 +; GCN: v_div_scale_f32 + ; GCN: v_rcp_f32_e32 +; GCN: v_fma_f32 ; GCN: v_mul_f32_e32 -; GCN: v_mul_f32_e32 +; GCN: v_div_fmas_f32 +; GCN: v_div_fixup_f32 ; GCN: v_trunc_f32_e32 ; GCN: v_mad_f32 ; GCN: s_endpgm diff --git a/test/CodeGen/AMDGPU/fsqrt.f64.ll b/test/CodeGen/AMDGPU/fsqrt.f64.ll new file mode 100644 index 000000000000..ce0881c329be --- /dev/null +++ b/test/CodeGen/AMDGPU/fsqrt.f64.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}v_safe_fsqrt_f64: +; GCN: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +define void @v_safe_fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #1 { + %r0 = load double, double addrspace(1)* %in + %r1 = call double @llvm.sqrt.f64(double %r0) + store double %r1, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_unsafe_fsqrt_f64: +; GCN: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +define void @v_unsafe_fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) #2 { + %r0 = load double, double addrspace(1)* %in + %r1 = call double @llvm.sqrt.f64(double %r0) + store double %r1, double addrspace(1)* %out + ret void +} + +declare double @llvm.sqrt.f64(double %Val) #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "unsafe-fp-math"="false" } +attributes #2 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/fsqrt.ll b/test/CodeGen/AMDGPU/fsqrt.ll index 04101346cdf9..f98cac6ade3a 100644 --- a/test/CodeGen/AMDGPU/fsqrt.ll +++ b/test/CodeGen/AMDGPU/fsqrt.ll @@ -1,29 +1,143 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s + ; Run with unsafe-fp-math to make sure nothing tries to turn this into 1 / rsqrt(x) -; CHECK: {{^}}fsqrt_f32: -; CHECK: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}} +; FUNC-LABEL: {{^}}v_safe_fsqrt_f32: +; GCN: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}} +define void @v_safe_fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #1 { + %r0 = load float, float addrspace(1)* %in + %r1 = call float @llvm.sqrt.f32(float %r0) + store float %r1, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_unsafe_fsqrt_f32: +; GCN: v_sqrt_f32_e32 {{v[0-9]+, v[0-9]+}} +define void @v_unsafe_fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) #2 { + %r0 = load float, float addrspace(1)* %in + %r1 = call float @llvm.sqrt.f32(float %r0) + store float %r1, float addrspace(1)* %out + ret void +} + + +; FUNC-LABEL: {{^}}s_sqrt_f32: +; GCN: v_sqrt_f32_e32 + +; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z +; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS +define void @s_sqrt_f32(float addrspace(1)* %out, float %in) #1 { +entry: + %fdiv = call float @llvm.sqrt.f32(float %in) + store float %fdiv, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}s_sqrt_v2f32: +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 + +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS +define void @s_sqrt_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) #1 { +entry: + %fdiv = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) + store <2 x float> %fdiv, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}s_sqrt_v4f32: +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 + +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].W +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS +; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X +; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS +define void @s_sqrt_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) #1 { +entry: + %fdiv = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) + store <4 x float> %fdiv, <4 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}elim_redun_check_neg0: +; GCN: v_sqrt_f32_e32 +; GCN-NOT: v_cndmask +define void @elim_redun_check_neg0(float addrspace(1)* %out, float %in) #1 { +entry: + %sqrt = call float @llvm.sqrt.f32(float %in) + %cmp = fcmp olt float %in, -0.000000e+00 + %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt + store float %res, float addrspace(1)* %out + ret void +} -define void @fsqrt_f32(float addrspace(1)* %out, float addrspace(1)* %in) { - %r0 = load float, float addrspace(1)* %in - %r1 = call float @llvm.sqrt.f32(float %r0) - store float %r1, float addrspace(1)* %out - ret void +; FUNC-LABEL: {{^}}elim_redun_check_pos0: +; GCN: v_sqrt_f32_e32 +; GCN-NOT: v_cndmask +define void @elim_redun_check_pos0(float addrspace(1)* %out, float %in) #1 { +entry: + %sqrt = call float @llvm.sqrt.f32(float %in) + %cmp = fcmp olt float %in, 0.000000e+00 + %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt + store float %res, float addrspace(1)* %out + ret void } -; CHECK: {{^}}fsqrt_f64: -; CHECK: v_sqrt_f64_e32 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}} +; FUNC-LABEL: {{^}}elim_redun_check_ult: +; GCN: v_sqrt_f32_e32 +; GCN-NOT: v_cndmask +define void @elim_redun_check_ult(float addrspace(1)* %out, float %in) #1 { +entry: + %sqrt = call float @llvm.sqrt.f32(float %in) + %cmp = fcmp ult float %in, -0.000000e+00 + %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt + store float %res, float addrspace(1)* %out + ret void +} -define void @fsqrt_f64(double addrspace(1)* %out, double addrspace(1)* %in) { - %r0 = load double, double addrspace(1)* %in - %r1 = call double @llvm.sqrt.f64(double %r0) - store double %r1, double addrspace(1)* %out - ret void +; FUNC-LABEL: {{^}}elim_redun_check_v2: +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 +; GCN-NOT: v_cndmask +define void @elim_redun_check_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) #1 { +entry: + %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) + %cmp = fcmp olt <2 x float> %in, + %res = select <2 x i1> %cmp, <2 x float> , <2 x float> %sqrt + store <2 x float> %res, <2 x float> addrspace(1)* %out + ret void } -declare float @llvm.sqrt.f32(float %Val) -declare double @llvm.sqrt.f64(double %Val) +; FUNC-LABEL: {{^}}elim_redun_check_v2_ult +; GCN: v_sqrt_f32_e32 +; GCN: v_sqrt_f32_e32 +; GCN-NOT: v_cndmask +define void @elim_redun_check_v2_ult(<2 x float> addrspace(1)* %out, <2 x float> %in) #1 { +entry: + %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) + %cmp = fcmp ult <2 x float> %in, + %res = select <2 x i1> %cmp, <2 x float> , <2 x float> %sqrt + store <2 x float> %res, <2 x float> addrspace(1)* %out + ret void +} + +declare float @llvm.sqrt.f32(float %in) #0 +declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) #0 +declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "unsafe-fp-math"="false" } +attributes #2 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/fsub.ll b/test/CodeGen/AMDGPU/fsub.ll index 38d573258a5e..3429df33c015 100644 --- a/test/CodeGen/AMDGPU/fsub.ll +++ b/test/CodeGen/AMDGPU/fsub.ll @@ -1,7 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s - +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}v_fsub_f32: ; SI: v_subrev_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} @@ -24,7 +23,7 @@ define void @s_fsub_f32(float addrspace(1)* %out, float %a, float %b) { ret void } -declare float @llvm.R600.load.input(i32) readnone +declare float @llvm.r600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) diff --git a/test/CodeGen/AMDGPU/fsub64.ll b/test/CodeGen/AMDGPU/fsub64.ll index f34a48e30a86..f1b970a4f5fe 100644 --- a/test/CodeGen/AMDGPU/fsub64.ll +++ b/test/CodeGen/AMDGPU/fsub64.ll @@ -47,7 +47,7 @@ define void @s_fsub_f64(double addrspace(1)* %out, double %a, double %b) { } ; SI-LABEL: {{^}}s_fsub_imm_f64: -; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], 4.0, -s\[[0-9]+:[0-9]+\]}} +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}, 4.0 define void @s_fsub_imm_f64(double addrspace(1)* %out, double %a, double %b) { %sub = fsub double 4.0, %a store double %sub, double addrspace(1)* %out @@ -55,7 +55,7 @@ define void @s_fsub_imm_f64(double addrspace(1)* %out, double %a, double %b) { } ; SI-LABEL: {{^}}s_fsub_imm_inv_f64: -; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -4.0, s\[[0-9]+:[0-9]+\]}} +; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\]}}, -4.0 define void @s_fsub_imm_inv_f64(double addrspace(1)* %out, double %a, double %b) { %sub = fsub double %a, 4.0 store double %sub, double addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/ftrunc.f64.ll b/test/CodeGen/AMDGPU/ftrunc.f64.ll index 83a8ad8901d2..c4138ad79c28 100644 --- a/test/CodeGen/AMDGPU/ftrunc.f64.ll +++ b/test/CodeGen/AMDGPU/ftrunc.f64.ll @@ -24,11 +24,11 @@ define void @v_ftrunc_f64(double addrspace(1)* %out, double addrspace(1)* %in) { ; CI: v_trunc_f64_e32 ; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014 -; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 -; SI: s_add_i32 s{{[0-9]+}}, [[SEXP]], 0xfffffc01 -; SI: s_lshr_b64 -; SI: s_not_b64 -; SI: s_and_b64 +; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000 +; SI-DAG: s_add_i32 [[SEXP1:s[0-9]+]], [[SEXP]], 0xfffffc01 +; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP1]] +; SI-DAG: s_not_b64 +; SI-DAG: s_and_b64 ; SI-DAG: cmp_gt_i32 ; SI-DAG: cndmask_b32 ; SI-DAG: cndmask_b32 diff --git a/test/CodeGen/AMDGPU/ftrunc.ll b/test/CodeGen/AMDGPU/ftrunc.ll index edc08609a8aa..1beeab65ade3 100644 --- a/test/CodeGen/AMDGPU/ftrunc.ll +++ b/test/CodeGen/AMDGPU/ftrunc.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG --check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI --check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG --check-prefix=FUNC %s declare float @llvm.trunc.f32(float) nounwind readnone declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone diff --git a/test/CodeGen/AMDGPU/global-constant.ll b/test/CodeGen/AMDGPU/global-constant.ll index bc5f031cd4a2..0f2fc836a245 100644 --- a/test/CodeGen/AMDGPU/global-constant.ll +++ b/test/CodeGen/AMDGPU/global-constant.ll @@ -12,7 +12,7 @@ ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], readonly ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0 ; NOHSA: .text -; HSA: .hsatext +; HSA: .text ; GCN: readonly: ; GCN: readonly2: define void @main(i32 %index, float addrspace(1)* %out) { diff --git a/test/CodeGen/AMDGPU/global-extload-i1.ll b/test/CodeGen/AMDGPU/global-extload-i1.ll deleted file mode 100644 index bd9557d730fb..000000000000 --- a/test/CodeGen/AMDGPU/global-extload-i1.ll +++ /dev/null @@ -1,302 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; FIXME: Evergreen broken - -; FUNC-LABEL: {{^}}zextload_global_i1_to_i32: -; SI: buffer_load_ubyte -; SI: buffer_store_dword -; SI: s_endpgm -define void @zextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %a = load i1, i1 addrspace(1)* %in - %ext = zext i1 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i1_to_i32: -; SI: buffer_load_ubyte -; SI: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}} -; SI: buffer_store_dword -; SI: s_endpgm -define void @sextload_global_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %a = load i1, i1 addrspace(1)* %in - %ext = sext i1 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i32: -; SI: s_endpgm -define void @zextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i1>, <1 x i1> addrspace(1)* %in - %ext = zext <1 x i1> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i32: -; SI: s_endpgm -define void @sextload_global_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i1>, <1 x i1> addrspace(1)* %in - %ext = sext <1 x i1> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i32: -; SI: s_endpgm -define void @zextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i1>, <2 x i1> addrspace(1)* %in - %ext = zext <2 x i1> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i32: -; SI: s_endpgm -define void @sextload_global_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i1>, <2 x i1> addrspace(1)* %in - %ext = sext <2 x i1> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i32: -; SI: s_endpgm -define void @zextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i1>, <4 x i1> addrspace(1)* %in - %ext = zext <4 x i1> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i32: -; SI: s_endpgm -define void @sextload_global_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i1>, <4 x i1> addrspace(1)* %in - %ext = sext <4 x i1> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i32: -; SI: s_endpgm -define void @zextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i1>, <8 x i1> addrspace(1)* %in - %ext = zext <8 x i1> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i32: -; SI: s_endpgm -define void @sextload_global_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i1>, <8 x i1> addrspace(1)* %in - %ext = sext <8 x i1> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i32: -; SI: s_endpgm -define void @zextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i1>, <16 x i1> addrspace(1)* %in - %ext = zext <16 x i1> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i32: -; SI: s_endpgm -define void @sextload_global_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i1>, <16 x i1> addrspace(1)* %in - %ext = sext <16 x i1> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i32: -; XSI: s_endpgm -; define void @zextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in -; %ext = zext <32 x i1> %load to <32 x i32> -; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i32: -; XSI: s_endpgm -; define void @sextload_global_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in -; %ext = sext <32 x i1> %load to <32 x i32> -; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i32: -; XSI: s_endpgm -; define void @zextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in -; %ext = zext <64 x i1> %load to <64 x i32> -; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i32: -; XSI: s_endpgm -; define void @sextload_global_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in -; %ext = sext <64 x i1> %load to <64 x i32> -; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out -; ret void -; } - -; FUNC-LABEL: {{^}}zextload_global_i1_to_i64: -; SI: buffer_load_ubyte [[LOAD:v[0-9]+]], -; SI: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}} -; SI: buffer_store_dwordx2 -define void @zextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %a = load i1, i1 addrspace(1)* %in - %ext = zext i1 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i1_to_i64: -; SI: buffer_load_ubyte [[LOAD:v[0-9]+]], -; SI: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}} -; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]] -; SI: buffer_store_dwordx2 -define void @sextload_global_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %a = load i1, i1 addrspace(1)* %in - %ext = sext i1 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i1_to_v1i64: -; SI: s_endpgm -define void @zextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i1>, <1 x i1> addrspace(1)* %in - %ext = zext <1 x i1> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i1_to_v1i64: -; SI: s_endpgm -define void @sextload_global_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i1>, <1 x i1> addrspace(1)* %in - %ext = sext <1 x i1> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i1_to_v2i64: -; SI: s_endpgm -define void @zextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i1>, <2 x i1> addrspace(1)* %in - %ext = zext <2 x i1> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i1_to_v2i64: -; SI: s_endpgm -define void @sextload_global_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i1>, <2 x i1> addrspace(1)* %in - %ext = sext <2 x i1> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i1_to_v4i64: -; SI: s_endpgm -define void @zextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i1>, <4 x i1> addrspace(1)* %in - %ext = zext <4 x i1> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i1_to_v4i64: -; SI: s_endpgm -define void @sextload_global_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i1>, <4 x i1> addrspace(1)* %in - %ext = sext <4 x i1> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i1_to_v8i64: -; SI: s_endpgm -define void @zextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i1>, <8 x i1> addrspace(1)* %in - %ext = zext <8 x i1> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i1_to_v8i64: -; SI: s_endpgm -define void @sextload_global_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i1>, <8 x i1> addrspace(1)* %in - %ext = sext <8 x i1> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i1_to_v16i64: -; SI: s_endpgm -define void @zextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i1>, <16 x i1> addrspace(1)* %in - %ext = zext <16 x i1> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i1_to_v16i64: -; SI: s_endpgm -define void @sextload_global_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i1>, <16 x i1> addrspace(1)* %in - %ext = sext <16 x i1> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; XFUNC-LABEL: {{^}}zextload_global_v32i1_to_v32i64: -; XSI: s_endpgm -; define void @zextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in -; %ext = zext <32 x i1> %load to <32 x i64> -; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v32i1_to_v32i64: -; XSI: s_endpgm -; define void @sextload_global_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i1>, <32 x i1> addrspace(1)* %in -; %ext = sext <32 x i1> %load to <32 x i64> -; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}zextload_global_v64i1_to_v64i64: -; XSI: s_endpgm -; define void @zextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in -; %ext = zext <64 x i1> %load to <64 x i64> -; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v64i1_to_v64i64: -; XSI: s_endpgm -; define void @sextload_global_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i1>, <64 x i1> addrspace(1)* %in -; %ext = sext <64 x i1> %load to <64 x i64> -; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out -; ret void -; } diff --git a/test/CodeGen/AMDGPU/global-extload-i16.ll b/test/CodeGen/AMDGPU/global-extload-i16.ll deleted file mode 100644 index 103a40dee270..000000000000 --- a/test/CodeGen/AMDGPU/global-extload-i16.ll +++ /dev/null @@ -1,302 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; FIXME: cypress is broken because the bigger testcases spill and it's not implemented - -; FUNC-LABEL: {{^}}zextload_global_i16_to_i32: -; SI: buffer_load_ushort -; SI: buffer_store_dword -; SI: s_endpgm -define void @zextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { - %a = load i16, i16 addrspace(1)* %in - %ext = zext i16 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i16_to_i32: -; SI: buffer_load_sshort -; SI: buffer_store_dword -; SI: s_endpgm -define void @sextload_global_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { - %a = load i16, i16 addrspace(1)* %in - %ext = sext i16 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i16_to_v1i32: -; SI: buffer_load_ushort -; SI: s_endpgm -define void @zextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i16>, <1 x i16> addrspace(1)* %in - %ext = zext <1 x i16> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i16_to_v1i32: -; SI: buffer_load_sshort -; SI: s_endpgm -define void @sextload_global_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i16>, <1 x i16> addrspace(1)* %in - %ext = sext <1 x i16> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i32: -; SI: s_endpgm -define void @zextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i16>, <2 x i16> addrspace(1)* %in - %ext = zext <2 x i16> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i32: -; SI: s_endpgm -define void @sextload_global_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i16>, <2 x i16> addrspace(1)* %in - %ext = sext <2 x i16> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i32: -; SI: s_endpgm -define void @zextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i16>, <4 x i16> addrspace(1)* %in - %ext = zext <4 x i16> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i32: -; SI: s_endpgm -define void @sextload_global_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i16>, <4 x i16> addrspace(1)* %in - %ext = sext <4 x i16> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i32: -; SI: s_endpgm -define void @zextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i16>, <8 x i16> addrspace(1)* %in - %ext = zext <8 x i16> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i32: -; SI: s_endpgm -define void @sextload_global_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i16>, <8 x i16> addrspace(1)* %in - %ext = sext <8 x i16> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i32: -; SI: s_endpgm -define void @zextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i16>, <16 x i16> addrspace(1)* %in - %ext = zext <16 x i16> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i32: -; SI: s_endpgm -define void @sextload_global_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i16>, <16 x i16> addrspace(1)* %in - %ext = sext <16 x i16> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i32: -; SI: s_endpgm -define void @zextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i16>, <32 x i16> addrspace(1)* %in - %ext = zext <32 x i16> %load to <32 x i32> - store <32 x i32> %ext, <32 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i32: -; SI: s_endpgm -define void @sextload_global_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i16>, <32 x i16> addrspace(1)* %in - %ext = sext <32 x i16> %load to <32 x i32> - store <32 x i32> %ext, <32 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i32: -; SI: s_endpgm -define void @zextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <64 x i16>, <64 x i16> addrspace(1)* %in - %ext = zext <64 x i16> %load to <64 x i32> - store <64 x i32> %ext, <64 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i32: -; SI: s_endpgm -define void @sextload_global_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <64 x i16>, <64 x i16> addrspace(1)* %in - %ext = sext <64 x i16> %load to <64 x i32> - store <64 x i32> %ext, <64 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_i16_to_i64: -; SI: buffer_load_ushort v[[LO:[0-9]+]], -; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} -; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] -define void @zextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { - %a = load i16, i16 addrspace(1)* %in - %ext = zext i16 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i16_to_i64: -; SI: buffer_load_sshort [[LOAD:v[0-9]+]], -; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: buffer_store_dwordx2 -define void @sextload_global_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { - %a = load i16, i16 addrspace(1)* %in - %ext = sext i16 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i16_to_v1i64: -; SI: s_endpgm -define void @zextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i16>, <1 x i16> addrspace(1)* %in - %ext = zext <1 x i16> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i16_to_v1i64: -; SI: s_endpgm -define void @sextload_global_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i16>, <1 x i16> addrspace(1)* %in - %ext = sext <1 x i16> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i16_to_v2i64: -; SI: s_endpgm -define void @zextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i16>, <2 x i16> addrspace(1)* %in - %ext = zext <2 x i16> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i16_to_v2i64: -; SI: s_endpgm -define void @sextload_global_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i16>, <2 x i16> addrspace(1)* %in - %ext = sext <2 x i16> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i16_to_v4i64: -; SI: s_endpgm -define void @zextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i16>, <4 x i16> addrspace(1)* %in - %ext = zext <4 x i16> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i16_to_v4i64: -; SI: s_endpgm -define void @sextload_global_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i16>, <4 x i16> addrspace(1)* %in - %ext = sext <4 x i16> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i16_to_v8i64: -; SI: s_endpgm -define void @zextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i16>, <8 x i16> addrspace(1)* %in - %ext = zext <8 x i16> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i16_to_v8i64: -; SI: s_endpgm -define void @sextload_global_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i16>, <8 x i16> addrspace(1)* %in - %ext = sext <8 x i16> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i16_to_v16i64: -; SI: s_endpgm -define void @zextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i16>, <16 x i16> addrspace(1)* %in - %ext = zext <16 x i16> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i16_to_v16i64: -; SI: s_endpgm -define void @sextload_global_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i16>, <16 x i16> addrspace(1)* %in - %ext = sext <16 x i16> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v32i16_to_v32i64: -; SI: s_endpgm -define void @zextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i16>, <32 x i16> addrspace(1)* %in - %ext = zext <32 x i16> %load to <32 x i64> - store <32 x i64> %ext, <32 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v32i16_to_v32i64: -; SI: s_endpgm -define void @sextload_global_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i16>, <32 x i16> addrspace(1)* %in - %ext = sext <32 x i16> %load to <32 x i64> - store <32 x i64> %ext, <32 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v64i16_to_v64i64: -; SI: s_endpgm -define void @zextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <64 x i16>, <64 x i16> addrspace(1)* %in - %ext = zext <64 x i16> %load to <64 x i64> - store <64 x i64> %ext, <64 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v64i16_to_v64i64: -; SI: s_endpgm -define void @sextload_global_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* nocapture %in) nounwind { - %load = load <64 x i16>, <64 x i16> addrspace(1)* %in - %ext = sext <64 x i16> %load to <64 x i64> - store <64 x i64> %ext, <64 x i64> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/global-extload-i32.ll b/test/CodeGen/AMDGPU/global-extload-i32.ll deleted file mode 100644 index e5e6be2199c3..000000000000 --- a/test/CodeGen/AMDGPU/global-extload-i32.ll +++ /dev/null @@ -1,308 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}zextload_global_i32_to_i64: -; SI: buffer_load_dword v[[LO:[0-9]+]], -; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} -; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] -define void @zextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %a = load i32, i32 addrspace(1)* %in - %ext = zext i32 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i32_to_i64: -; SI: buffer_load_dword [[LOAD:v[0-9]+]], -; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: buffer_store_dwordx2 -define void @sextload_global_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %a = load i32, i32 addrspace(1)* %in - %ext = sext i32 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i32_to_v1i64: -; SI: buffer_load_dword -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @zextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i32>, <1 x i32> addrspace(1)* %in - %ext = zext <1 x i32> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i32_to_v1i64: -; SI: buffer_load_dword -; SI: v_ashrrev_i32 -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @sextload_global_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i32>, <1 x i32> addrspace(1)* %in - %ext = sext <1 x i32> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i32_to_v2i64: -; SI: buffer_load_dwordx2 -; SI: buffer_store_dwordx4 -; SI: s_endpgm -define void @zextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i32>, <2 x i32> addrspace(1)* %in - %ext = zext <2 x i32> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i32_to_v2i64: -; SI: buffer_load_dwordx2 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 -; SI: s_endpgm -define void @sextload_global_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i32>, <2 x i32> addrspace(1)* %in - %ext = sext <2 x i32> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i32_to_v4i64: -; SI: buffer_load_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: s_endpgm -define void @zextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i32>, <4 x i32> addrspace(1)* %in - %ext = zext <4 x i32> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i32_to_v4i64: -; SI: buffer_load_dwordx4 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI: s_endpgm -define void @sextload_global_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i32>, <4 x i32> addrspace(1)* %in - %ext = sext <4 x i32> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i32_to_v8i64: -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI: s_endpgm -define void @zextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i32>, <8 x i32> addrspace(1)* %in - %ext = zext <8 x i32> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i32_to_v8i64: -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI: s_endpgm -define void @sextload_global_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i32>, <8 x i32> addrspace(1)* %in - %ext = sext <8 x i32> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i32_to_v16i64: -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: buffer_store_dwordx4 -; SI: s_endpgm -define void @sextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i32>, <16 x i32> addrspace(1)* %in - %ext = sext <16 x i32> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i32_to_v16i64 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 - -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: s_endpgm -define void @zextload_global_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i32>, <16 x i32> addrspace(1)* %in - %ext = zext <16 x i32> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v32i32_to_v32i64: -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 - - -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 -; SI-DAG: v_ashrrev_i32 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI: s_endpgm -define void @sextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i32>, <32 x i32> addrspace(1)* %in - %ext = sext <32 x i32> %load to <32 x i64> - store <32 x i64> %ext, <32 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v32i32_to_v32i64: -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 -; SI: buffer_load_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 -; SI-DAG: buffer_store_dwordx4 - -; SI: s_endpgm -define void @zextload_global_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* nocapture %in) nounwind { - %load = load <32 x i32>, <32 x i32> addrspace(1)* %in - %ext = zext <32 x i32> %load to <32 x i64> - store <32 x i64> %ext, <32 x i64> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/global-extload-i8.ll b/test/CodeGen/AMDGPU/global-extload-i8.ll deleted file mode 100644 index b31d5361d5a2..000000000000 --- a/test/CodeGen/AMDGPU/global-extload-i8.ll +++ /dev/null @@ -1,299 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}zextload_global_i8_to_i32: -; SI: buffer_load_ubyte -; SI: buffer_store_dword -; SI: s_endpgm -define void @zextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { - %a = load i8, i8 addrspace(1)* %in - %ext = zext i8 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i8_to_i32: -; SI: buffer_load_sbyte -; SI: buffer_store_dword -; SI: s_endpgm -define void @sextload_global_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { - %a = load i8, i8 addrspace(1)* %in - %ext = sext i8 %a to i32 - store i32 %ext, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i32: -; SI: s_endpgm -define void @zextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i8>, <1 x i8> addrspace(1)* %in - %ext = zext <1 x i8> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i32: -; SI: s_endpgm -define void @sextload_global_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i8>, <1 x i8> addrspace(1)* %in - %ext = sext <1 x i8> %load to <1 x i32> - store <1 x i32> %ext, <1 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i32: -; SI: s_endpgm -define void @zextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i8>, <2 x i8> addrspace(1)* %in - %ext = zext <2 x i8> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i32: -; SI: s_endpgm -define void @sextload_global_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i8>, <2 x i8> addrspace(1)* %in - %ext = sext <2 x i8> %load to <2 x i32> - store <2 x i32> %ext, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i32: -; SI: s_endpgm -define void @zextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i8>, <4 x i8> addrspace(1)* %in - %ext = zext <4 x i8> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i32: -; SI: s_endpgm -define void @sextload_global_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i8>, <4 x i8> addrspace(1)* %in - %ext = sext <4 x i8> %load to <4 x i32> - store <4 x i32> %ext, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i32: -; SI: s_endpgm -define void @zextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i8>, <8 x i8> addrspace(1)* %in - %ext = zext <8 x i8> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i32: -; SI: s_endpgm -define void @sextload_global_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i8>, <8 x i8> addrspace(1)* %in - %ext = sext <8 x i8> %load to <8 x i32> - store <8 x i32> %ext, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i32: -; SI: s_endpgm -define void @zextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i8>, <16 x i8> addrspace(1)* %in - %ext = zext <16 x i8> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i32: -; SI: s_endpgm -define void @sextload_global_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i8>, <16 x i8> addrspace(1)* %in - %ext = sext <16 x i8> %load to <16 x i32> - store <16 x i32> %ext, <16 x i32> addrspace(1)* %out - ret void -} - -; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i32: -; XSI: s_endpgm -; define void @zextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in -; %ext = zext <32 x i8> %load to <32 x i32> -; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i32: -; XSI: s_endpgm -; define void @sextload_global_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in -; %ext = sext <32 x i8> %load to <32 x i32> -; store <32 x i32> %ext, <32 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i32: -; XSI: s_endpgm -; define void @zextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in -; %ext = zext <64 x i8> %load to <64 x i32> -; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i32: -; XSI: s_endpgm -; define void @sextload_global_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in -; %ext = sext <64 x i8> %load to <64 x i32> -; store <64 x i32> %ext, <64 x i32> addrspace(1)* %out -; ret void -; } - -; FUNC-LABEL: {{^}}zextload_global_i8_to_i64: -; SI: buffer_load_ubyte v[[LO:[0-9]+]], -; SI: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} -; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] -define void @zextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { - %a = load i8, i8 addrspace(1)* %in - %ext = zext i8 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_i8_to_i64: -; SI: buffer_load_sbyte [[LOAD:v[0-9]+]], -; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[LOAD]] -; SI: buffer_store_dwordx2 -define void @sextload_global_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { - %a = load i8, i8 addrspace(1)* %in - %ext = sext i8 %a to i64 - store i64 %ext, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v1i8_to_v1i64: -; SI: s_endpgm -define void @zextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i8>, <1 x i8> addrspace(1)* %in - %ext = zext <1 x i8> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v1i8_to_v1i64: -; SI: s_endpgm -define void @sextload_global_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <1 x i8>, <1 x i8> addrspace(1)* %in - %ext = sext <1 x i8> %load to <1 x i64> - store <1 x i64> %ext, <1 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v2i8_to_v2i64: -; SI: s_endpgm -define void @zextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i8>, <2 x i8> addrspace(1)* %in - %ext = zext <2 x i8> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v2i8_to_v2i64: -; SI: s_endpgm -define void @sextload_global_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <2 x i8>, <2 x i8> addrspace(1)* %in - %ext = sext <2 x i8> %load to <2 x i64> - store <2 x i64> %ext, <2 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v4i8_to_v4i64: -; SI: s_endpgm -define void @zextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i8>, <4 x i8> addrspace(1)* %in - %ext = zext <4 x i8> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v4i8_to_v4i64: -; SI: s_endpgm -define void @sextload_global_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <4 x i8>, <4 x i8> addrspace(1)* %in - %ext = sext <4 x i8> %load to <4 x i64> - store <4 x i64> %ext, <4 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v8i8_to_v8i64: -; SI: s_endpgm -define void @zextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i8>, <8 x i8> addrspace(1)* %in - %ext = zext <8 x i8> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v8i8_to_v8i64: -; SI: s_endpgm -define void @sextload_global_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <8 x i8>, <8 x i8> addrspace(1)* %in - %ext = sext <8 x i8> %load to <8 x i64> - store <8 x i64> %ext, <8 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}zextload_global_v16i8_to_v16i64: -; SI: s_endpgm -define void @zextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i8>, <16 x i8> addrspace(1)* %in - %ext = zext <16 x i8> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}sextload_global_v16i8_to_v16i64: -; SI: s_endpgm -define void @sextload_global_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* nocapture %in) nounwind { - %load = load <16 x i8>, <16 x i8> addrspace(1)* %in - %ext = sext <16 x i8> %load to <16 x i64> - store <16 x i64> %ext, <16 x i64> addrspace(1)* %out - ret void -} - -; XFUNC-LABEL: {{^}}zextload_global_v32i8_to_v32i64: -; XSI: s_endpgm -; define void @zextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in -; %ext = zext <32 x i8> %load to <32 x i64> -; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v32i8_to_v32i64: -; XSI: s_endpgm -; define void @sextload_global_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <32 x i8>, <32 x i8> addrspace(1)* %in -; %ext = sext <32 x i8> %load to <32 x i64> -; store <32 x i64> %ext, <32 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}zextload_global_v64i8_to_v64i64: -; XSI: s_endpgm -; define void @zextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in -; %ext = zext <64 x i8> %load to <64 x i64> -; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out -; ret void -; } - -; XFUNC-LABEL: {{^}}sextload_global_v64i8_to_v64i64: -; XSI: s_endpgm -; define void @sextload_global_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* nocapture %in) nounwind { -; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in -; %ext = sext <64 x i8> %load to <64 x i64> -; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out -; ret void -; } diff --git a/test/CodeGen/AMDGPU/global-variable-relocs.ll b/test/CodeGen/AMDGPU/global-variable-relocs.ll new file mode 100644 index 000000000000..c39394a3527d --- /dev/null +++ b/test/CodeGen/AMDGPU/global-variable-relocs.ll @@ -0,0 +1,203 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck %s + +@private = private addrspace(1) global [256 x i32] zeroinitializer +@internal = internal addrspace(1) global [256 x i32] zeroinitializer +@available_externally = available_externally addrspace(1) global [256 x i32] zeroinitializer +@linkonce = linkonce addrspace(1) global [256 x i32] zeroinitializer +@weak= weak addrspace(1) global [256 x i32] zeroinitializer +@common = common addrspace(1) global [256 x i32] zeroinitializer +@extern_weak = extern_weak addrspace(1) global [256 x i32] +@linkonce_odr = linkonce_odr addrspace(1) global [256 x i32] zeroinitializer +@weak_odr = weak_odr addrspace(1) global [256 x i32] zeroinitializer +@external = external addrspace(1) global [256 x i32] +@external_w_init = addrspace(1) global [256 x i32] zeroinitializer + +; CHECK-LABEL: private_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], private+8 +; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @private_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @private, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: internal_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[ADDR_LO:[0-9]+]], s[[PC_LO]], internal+8 +; CHECK: s_addc_u32 s[[ADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[ADDR_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[ADDR_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @internal_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @internal, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: available_externally_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], available_externally@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @available_externally_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @available_externally, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: linkonce_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @linkonce_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: weak_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @weak_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: common_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], common@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @common_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @common, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: extern_weak_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], extern_weak@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @extern_weak_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @extern_weak, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: linkonce_odr_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], linkonce_odr@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @linkonce_odr_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @linkonce_odr, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: weak_odr_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], weak_odr@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @weak_odr_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @weak_odr, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: external_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @external_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: external_w_init_test: +; CHECK: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} +; CHECK: s_add_u32 s[[GOTADDR_LO:[0-9]+]], s[[PC_LO]], external_w_init@GOTPCREL+4 +; CHECK: s_addc_u32 s[[GOTADDR_HI:[0-9]+]], s[[PC_HI]], 0 +; CHECK: s_load_dwordx2 s{{\[}}[[ADDR_LO:[0-9]+]]:[[ADDR_HI:[0-9]+]]{{\]}}, s{{\[}}[[GOTADDR_LO]]:[[GOTADDR_HI]]{{\]}}, 0x0 +; CHECK: s_add_u32 s[[GEP_LO:[0-9]+]], s[[ADDR_LO]], 4 +; CHECK: s_addc_u32 s[[GEP_HI:[0-9]+]], s[[ADDR_HI]], 0 +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[GEP_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[GEP_HI]] +; CHECK: flat_load_dword v{{[0-9]+}}, v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @external_w_init_test(i32 addrspace(1)* %out) { + %ptr = getelementptr [256 x i32], [256 x i32] addrspace(1)* @external_w_init, i32 0, i32 1 + %val = load i32, i32 addrspace(1)* %ptr + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; CHECK: .local private +; CHECK: .local internal +; CHECK: .weak linkonce +; CHECK: .weak weak +; CHECK: .weak linkonce_odr +; CHECK: .weak weak_odr +; CHECK-NOT: external{{$}} +; CHECK: .globl external_w_init diff --git a/test/CodeGen/AMDGPU/global-zero-initializer.ll b/test/CodeGen/AMDGPU/global-zero-initializer.ll deleted file mode 100644 index 45aa8bf4e1d7..000000000000 --- a/test/CodeGen/AMDGPU/global-zero-initializer.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s -; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s - -; CHECK: error: unsupported initializer for address space in load_init_global_global - -@lds = addrspace(1) global [256 x i32] zeroinitializer - -define void @load_init_global_global(i32 addrspace(1)* %out, i1 %p) { - %gep = getelementptr [256 x i32], [256 x i32] addrspace(1)* @lds, i32 0, i32 10 - %ld = load i32, i32 addrspace(1)* %gep - store i32 %ld, i32 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/global_atomics.ll b/test/CodeGen/AMDGPU/global_atomics.ll index 6786e4a2f375..743ad7c278be 100644 --- a/test/CodeGen/AMDGPU/global_atomics.ll +++ b/test/CodeGen/AMDGPU/global_atomics.ll @@ -1,921 +1,1044 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=VI --check-prefix=FUNC %s - +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}atomic_add_i32_offset: -; GCN: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_add_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_add_i32_soffset: +; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x8ca0 +; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}} +define void @atomic_add_i32_soffset(i32 addrspace(1)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 9000 + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_add_i32_huge_offset: +; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac +; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd +; SI: buffer_atomic_add v{{[0-9]+}}, v{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_add +define void @atomic_add_i32_huge_offset(i32 addrspace(1)* %out, i32 %in) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 47224239175595 + + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_offset: -; GCN: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset: ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} - define void @atomic_add_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_add_i32: -; GCN: buffer_atomic_add v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_add_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_ret: -; GCN: buffer_atomic_add [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_add [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile add i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_addr64: ; SI: buffer_atomic_add v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_add_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_add_i32_ret_addr64: ; SI: buffer_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_add_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile add i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_offset: -; GCN: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_and v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_and_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_offset: -; GCN: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset: ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_and_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: ; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile and i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_and_i32: -; GCN: buffer_atomic_and v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_and v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_and_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_ret: -; GCN: buffer_atomic_and [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_and [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile and i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_addr64: ; SI: buffer_atomic_and v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_and_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_and_i32_ret_addr64: ; SI: buffer_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_and_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile and i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_offset: -; GCN: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_sub v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_sub_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_offset: -; GCN: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_sub [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset: ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_sub_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: ; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile sub i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32: -; GCN: buffer_atomic_sub v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_sub v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_sub_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret: -; GCN: buffer_atomic_sub [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_sub [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile sub i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_addr64: ; SI: buffer_atomic_sub v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_sub_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_sub_i32_ret_addr64: ; SI: buffer_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_sub_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile sub i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_offset: -; GCN: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_smax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_max_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_offset: -; GCN: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_smax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset: ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_max_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: ; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile max i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_max_i32: -; GCN: buffer_atomic_smax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_smax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_max_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_ret: -; GCN: buffer_atomic_smax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_smax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile max i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_addr64: ; SI: buffer_atomic_smax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_max_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_max_i32_ret_addr64: ; SI: buffer_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_max_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile max i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_offset: -; GCN: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_umax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_umax_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_offset: -; GCN: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_umax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset: ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umax_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: ; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile umax i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32: -; GCN: buffer_atomic_umax v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_umax v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umax_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret: -; GCN: buffer_atomic_umax [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_umax [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile umax i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_addr64: ; SI: buffer_atomic_umax v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umax_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umax_i32_ret_addr64: ; SI: buffer_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umax_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile umax i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_offset: -; GCN: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_smin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_min_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_offset: -; GCN: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_smin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset: ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_min_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: ; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile min i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_min_i32: -; GCN: buffer_atomic_smin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_smin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_min_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_ret: -; GCN: buffer_atomic_smin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_smin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile min i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_addr64: ; SI: buffer_atomic_smin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_min_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_min_i32_ret_addr64: ; SI: buffer_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_min_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile min i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_offset: -; GCN: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_umin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_umin_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_offset: -; GCN: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_umin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset: ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umin_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: ; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile umin i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32: -; GCN: buffer_atomic_umin v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_umin v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_umin_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret: -; SI: buffer_atomic_umin [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; SI: buffer_atomic_umin [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile umin i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_addr64: ; SI: buffer_atomic_umin v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_umin_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_umin_i32_ret_addr64: ; SI: buffer_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_umin_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile umin i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_offset: -; GCN: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_or v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_or_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_offset: -; GCN: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_or [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset: ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_or_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: ; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile or i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_or_i32: -; GCN: buffer_atomic_or v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_or v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_or_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_ret: -; GCN: buffer_atomic_or [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_or [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile or i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_addr64: ; SI: buffer_atomic_or v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_or_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_or_i32_ret_addr64: ; SI: buffer_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_or_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile or i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_offset: -; GCN: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_swap v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_xchg_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_offset: -; GCN: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_swap [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64_offset: ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} + +; VI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}{{$}} define void @atomic_xchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: ; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 + ; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile xchg i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32: -; GCN: buffer_atomic_swap v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_swap v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xchg_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret: -; GCN: buffer_atomic_swap [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_swap [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile xchg i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64: ; SI: buffer_atomic_swap v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xchg_i32_ret_addr64: ; SI: buffer_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile xchg i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_offset: +; GCN: buffer_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +define void @atomic_cmpxchg_i32_offset(i32 addrspace(1)* %out, i32 %in, i32 %old) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: +; GCN: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_store_dword v[[RET]] +define void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst + %extract0 = extractvalue { i32, i1 } %val, 0 + store i32 %extract0, i32 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: +; SI: buffer_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} + +; VI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: +; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} +; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dword v[[RET]] +define void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = cmpxchg volatile i32 addrspace(1)* %gep, i32 %old, i32 %in seq_cst seq_cst + %extract0 = extractvalue { i32, i1 } %val, 0 + store i32 %extract0, i32 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32: +; GCN: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_cmpxchg_i32(i32 addrspace(1)* %out, i32 %in, i32 %old) { +entry: + %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_ret: +; GCN: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dword v[[RET]] +define void @atomic_cmpxchg_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i32 %old) { +entry: + %val = cmpxchg volatile i32 addrspace(1)* %out, i32 %old, i32 %in seq_cst seq_cst + %extract0 = extractvalue { i32, i1 } %val, 0 + store i32 %extract0, i32 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64: +; SI: buffer_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: +; SI: buffer_atomic_cmpswap v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dword v[[RET]] +define void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index, i32 %old) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + %val = cmpxchg volatile i32 addrspace(1)* %ptr, i32 %old, i32 %in seq_cst seq_cst + %extract0 = extractvalue { i32, i1 } %val, 0 + store i32 %extract0, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_offset: -; GCN: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} +; GCN: buffer_atomic_xor v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} define void @atomic_xor_i32_offset(i32 addrspace(1)* %out, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_offset: -; GCN: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; GCN: buffer_atomic_xor [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %gep = getelementptr i32, i32 addrspace(1)* %out, i32 4 - %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset: ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xor_i32_addr64_offset(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: ; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 - %0 = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = atomicrmw volatile xor i32 addrspace(1)* %gep, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32: -; GCN: buffer_atomic_xor v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +; GCN: buffer_atomic_xor v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} define void @atomic_xor_i32(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst + %val = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret: -; GCN: buffer_atomic_xor [[RET:v[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_atomic_xor [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc ; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in) { entry: - %0 = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile xor i32 addrspace(1)* %out, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_addr64: ; SI: buffer_atomic_xor v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} define void @atomic_xor_i32_addr64(i32 addrspace(1)* %out, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst + %val = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst ret void } ; FUNC-LABEL: {{^}}atomic_xor_i32_ret_addr64: ; SI: buffer_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} -; VI: s_movk_i32 flat_scratch_lo, 0x0 -; VI: s_movk_i32 flat_scratch_hi, 0x0 ; VI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: buffer_store_dword [[RET]] define void @atomic_xor_i32_ret_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %out2, i32 %in, i64 %index) { entry: %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index - %0 = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst - store i32 %0, i32 addrspace(1)* %out2 + %val = atomicrmw volatile xor i32 addrspace(1)* %ptr, i32 %in seq_cst + store i32 %val, i32 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i32_offset: +; SI: buffer_load_dword [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GCN: buffer_store_dword [[RET]] +define void @atomic_load_i32_offset(i32 addrspace(1)* %in, i32 addrspace(1)* %out) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %in, i64 4 + %val = load atomic i32, i32 addrspace(1)* %gep seq_cst, align 4 + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i32: +; SI: buffer_load_dword [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc +; GCN: buffer_store_dword [[RET]] +define void @atomic_load_i32(i32 addrspace(1)* %in, i32 addrspace(1)* %out) { +entry: + %val = load atomic i32, i32 addrspace(1)* %in seq_cst, align 4 + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i32_addr64_offset: +; SI: buffer_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} +; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dword [[RET]] +define void @atomic_load_i32_addr64_offset(i32 addrspace(1)* %in, i32 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %in, i64 %index + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + %val = load atomic i32, i32 addrspace(1)* %gep seq_cst, align 4 + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i32_addr64: +; SI: buffer_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dword [[RET]] +define void @atomic_load_i32_addr64(i32 addrspace(1)* %in, i32 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %in, i64 %index + %val = load atomic i32, i32 addrspace(1)* %ptr seq_cst, align 4 + store i32 %val, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i32_offset: +; SI: buffer_store_dword {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}} +; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_offset(i32 %in, i32 addrspace(1)* %out) { +entry: + %gep = getelementptr i32, i32 addrspace(1)* %out, i64 4 + store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i32: +; SI: buffer_store_dword {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc{{$}} +; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32(i32 %in, i32 addrspace(1)* %out) { +entry: + store atomic i32 %in, i32 addrspace(1)* %out seq_cst, align 4 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i32_addr64_offset: +; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:16 glc{{$}} +; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 4 + store atomic i32 %in, i32 addrspace(1)* %gep seq_cst, align 4 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i32_addr64: +; SI: buffer_store_dword {{v[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} glc{{$}} +define void @atomic_store_i32_addr64(i32 %in, i32 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i32, i32 addrspace(1)* %out, i64 %index + store atomic i32 %in, i32 addrspace(1)* %ptr seq_cst, align 4 ret void } diff --git a/test/CodeGen/AMDGPU/global_atomics_i64.ll b/test/CodeGen/AMDGPU/global_atomics_i64.ll new file mode 100644 index 000000000000..2bae66d5aea8 --- /dev/null +++ b/test/CodeGen/AMDGPU/global_atomics_i64.ll @@ -0,0 +1,1037 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +; GCN-LABEL: {{^}}atomic_add_i64_offset: +; GCN: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_add_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: +; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_add_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: +; CI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} +define void @atomic_add_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: +; CI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_add_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64: +; GCN: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_add_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret: +; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_add_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_addr64: +; CI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_add_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64: +; CI: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_add_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile add i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_offset: +; GCN: buffer_atomic_and_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_and_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_offset: +; GCN: buffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_and_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset: +; CI: buffer_atomic_and_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset: +; CI: buffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_and_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64: +; GCN: buffer_atomic_and_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_and_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret: +; GCN: buffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_and_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_addr64: +; CI: buffer_atomic_and_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_and_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64: +; CI: buffer_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_and_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile and i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_offset: +; GCN: buffer_atomic_sub_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_sub_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset: +; GCN: buffer_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_sub_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset: +; CI: buffer_atomic_sub_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset: +; CI: buffer_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_sub_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64: +; GCN: buffer_atomic_sub_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_sub_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret: +; GCN: buffer_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_sub_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_addr64: +; CI: buffer_atomic_sub_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_sub_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64: +; CI: buffer_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_sub_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile sub i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_offset: +; GCN: buffer_atomic_smax_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_max_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_offset: +; GCN: buffer_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_max_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset: +; CI: buffer_atomic_smax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset: +; CI: buffer_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_max_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64: +; GCN: buffer_atomic_smax_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_max_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret: +; GCN: buffer_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_max_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_addr64: +; CI: buffer_atomic_smax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_max_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64: +; CI: buffer_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_max_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile max i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_offset: +; GCN: buffer_atomic_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_umax_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset: +; GCN: buffer_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umax_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset: +; CI: buffer_atomic_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset: +; CI: buffer_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umax_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64: +; GCN: buffer_atomic_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_umax_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret: +; GCN: buffer_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umax_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_addr64: +; CI: buffer_atomic_umax_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umax_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64: +; CI: buffer_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umax_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile umax i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_offset: +; GCN: buffer_atomic_smin_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_min_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_offset: +; GCN: buffer_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_min_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset: +; CI: buffer_atomic_smin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset: +; CI: buffer_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_min_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64: +; GCN: buffer_atomic_smin_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_min_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret: +; GCN: buffer_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_min_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_addr64: +; CI: buffer_atomic_smin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_min_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64: +; CI: buffer_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_min_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile min i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_offset: +; GCN: buffer_atomic_umin_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_umin_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset: +; GCN: buffer_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umin_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset: +; CI: buffer_atomic_umin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset: +; CI: buffer_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umin_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64: +; GCN: buffer_atomic_umin_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_umin_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret: +; CI: buffer_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umin_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_addr64: +; CI: buffer_atomic_umin_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_umin_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64: +; CI: buffer_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_umin_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile umin i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_offset: +; GCN: buffer_atomic_or_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_or_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_offset: +; GCN: buffer_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_or_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset: +; CI: buffer_atomic_or_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset: +; CI: buffer_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_or_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64: +; GCN: buffer_atomic_or_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_or_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret: +; GCN: buffer_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_or_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_addr64: +; CI: buffer_atomic_or_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_or_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64: +; CI: buffer_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_or_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile or i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_offset: +; GCN: buffer_atomic_swap_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_xchg_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset: +; GCN: buffer_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset: +; CI: buffer_atomic_swap_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} +define void @atomic_xchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset: +; CI: buffer_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64: +; GCN: buffer_atomic_swap_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_xchg_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret: +; GCN: buffer_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_addr64: +; CI: buffer_atomic_swap_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64: +; CI: buffer_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile xchg i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_offset: +; GCN: buffer_atomic_xor_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_xor_i64_offset(i64 addrspace(1)* %out, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset: +; GCN: buffer_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xor_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset: +; CI: buffer_atomic_xor_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} +; VI: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %gep, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset: +; CI: buffer_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xor_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %gep, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64: +; GCN: buffer_atomic_xor_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_xor_i64(i64 addrspace(1)* %out, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %out, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret: +; GCN: buffer_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xor_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in) { +entry: + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %out, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_addr64: +; CI: buffer_atomic_xor_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} +define void @atomic_xor_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %ptr, i64 %in seq_cst + ret void +} + +; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64: +; CI: buffer_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_xor_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %tmp0 = atomicrmw volatile xor i64 addrspace(1)* %ptr, i64 %in seq_cst + store i64 %tmp0, i64 addrspace(1)* %out2 + ret void +} + + + + + + + + + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_offset: +; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} +define void @atomic_cmpxchg_i64_offset(i64 addrspace(1)* %out, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_soffset: +; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x11940 +; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}} +define void @atomic_cmpxchg_i64_soffset(i64 addrspace(1)* %out, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 9000 + %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: +; GCN: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: +; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32{{$}} + +; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: +; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %val = cmpxchg volatile i64 addrspace(1)* %gep, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64: +; GCN: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}} +define void @atomic_cmpxchg_i64(i64 addrspace(1)* %out, i64 %in, i64 %old) { +entry: + %val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret: +; GCN: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %old) { +entry: + %val = cmpxchg volatile i64 addrspace(1)* %out, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_addr64: +; CI: buffer_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64{{$}} +; VI: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} +define void @atomic_cmpxchg_i64_addr64(i64 addrspace(1)* %out, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst + ret void +} + +; FUNC-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: +; CI: buffer_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[RET]]: +define void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %out2, i64 %in, i64 %index, i64 %old) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %val = cmpxchg volatile i64 addrspace(1)* %ptr, i64 %old, i64 %in seq_cst seq_cst + %extract0 = extractvalue { i64, i1 } %val, 0 + store i64 %extract0, i64 addrspace(1)* %out2 + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i64_offset: +; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_load_i64_offset(i64 addrspace(1)* %in, i64 addrspace(1)* %out) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %in, i64 4 + %val = load atomic i64, i64 addrspace(1)* %gep seq_cst, align 8 + store i64 %val, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i64: +; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_load_i64(i64 addrspace(1)* %in, i64 addrspace(1)* %out) { +entry: + %val = load atomic i64, i64 addrspace(1)* %in seq_cst, align 8 + store i64 %val, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i64_addr64_offset: +; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_load_i64_addr64_offset(i64 addrspace(1)* %in, i64 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %in, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + %val = load atomic i64, i64 addrspace(1)* %gep seq_cst, align 8 + store i64 %val, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_load_i64_addr64: +; CI: buffer_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} +; GCN: buffer_store_dwordx2 [[RET]] +define void @atomic_load_i64_addr64(i64 addrspace(1)* %in, i64 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %in, i64 %index + %val = load atomic i64, i64 addrspace(1)* %ptr seq_cst, align 8 + store i64 %val, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i64_offset: +; CI: buffer_store_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 glc{{$}} +; VI: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} +define void @atomic_store_i64_offset(i64 %in, i64 addrspace(1)* %out) { +entry: + %gep = getelementptr i64, i64 addrspace(1)* %out, i64 4 + store atomic i64 %in, i64 addrspace(1)* %gep seq_cst, align 8 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i64: +; CI: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 glc +; VI: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}] glc +define void @atomic_store_i64(i64 %in, i64 addrspace(1)* %out) { +entry: + store atomic i64 %in, i64 addrspace(1)* %out seq_cst, align 8 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i64_addr64_offset: +; CI: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 offset:32 glc{{$}} +; VI: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}] glc{{$}} +define void @atomic_store_i64_addr64_offset(i64 %in, i64 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i64 4 + store atomic i64 %in, i64 addrspace(1)* %gep seq_cst, align 8 + ret void +} + +; FUNC-LABEL: {{^}}atomic_store_i64_addr64: +; CI: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}} +; VI: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}] glc{{$}} +define void @atomic_store_i64_addr64(i64 %in, i64 addrspace(1)* %out, i64 %index) { +entry: + %ptr = getelementptr i64, i64 addrspace(1)* %out, i64 %index + store atomic i64 %in, i64 addrspace(1)* %ptr seq_cst, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/gv-const-addrspace-fail.ll b/test/CodeGen/AMDGPU/gv-const-addrspace-fail.ll deleted file mode 100644 index 014b0a5482ab..000000000000 --- a/test/CodeGen/AMDGPU/gv-const-addrspace-fail.ll +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - - -@a = internal addrspace(2) constant [1 x i8] [ i8 7 ], align 1 - -; FUNC-LABEL: {{^}}test_i8: -; EG: CF_END -; SI: buffer_store_byte -; SI: s_endpgm -define void @test_i8( i32 %s, i8 addrspace(1)* %out) #3 { - %arrayidx = getelementptr inbounds [1 x i8], [1 x i8] addrspace(2)* @a, i32 0, i32 %s - %1 = load i8, i8 addrspace(2)* %arrayidx, align 1 - store i8 %1, i8 addrspace(1)* %out - ret void -} - -@b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2 - -; FUNC-LABEL: {{^}}test_i16: -; EG: CF_END -; SI: buffer_store_short -; SI: s_endpgm -define void @test_i16( i32 %s, i16 addrspace(1)* %out) #3 { - %arrayidx = getelementptr inbounds [1 x i16], [1 x i16] addrspace(2)* @b, i32 0, i32 %s - %1 = load i16, i16 addrspace(2)* %arrayidx, align 2 - store i16 %1, i16 addrspace(1)* %out - ret void -} - -%struct.bar = type { float, [5 x i8] } - -; The illegal i8s aren't handled -@struct_bar_gv = internal addrspace(2) constant [1 x %struct.bar] [ %struct.bar { float 16.0, [5 x i8] [i8 0, i8 1, i8 2, i8 3, i8 4] } ] - -; FUNC-LABEL: {{^}}struct_bar_gv_load: -define void @struct_bar_gv_load(i8 addrspace(1)* %out, i32 %index) { - %gep = getelementptr inbounds [1 x %struct.bar], [1 x %struct.bar] addrspace(2)* @struct_bar_gv, i32 0, i32 0, i32 1, i32 %index - %load = load i8, i8 addrspace(2)* %gep, align 1 - store i8 %load, i8 addrspace(1)* %out, align 1 - ret void -} - - -; The private load isn't scalarzied. -@array_vector_gv = internal addrspace(2) constant [4 x <4 x i32>] [ <4 x i32> , - <4 x i32> , - <4 x i32> , - <4 x i32> ] - -; FUNC-LABEL: {{^}}array_vector_gv_load: -define void @array_vector_gv_load(<4 x i32> addrspace(1)* %out, i32 %index) { - %gep = getelementptr inbounds [4 x <4 x i32>], [4 x <4 x i32>] addrspace(2)* @array_vector_gv, i32 0, i32 %index - %load = load <4 x i32>, <4 x i32> addrspace(2)* %gep, align 16 - store <4 x i32> %load, <4 x i32> addrspace(1)* %out, align 16 - ret void -} diff --git a/test/CodeGen/AMDGPU/gv-const-addrspace.ll b/test/CodeGen/AMDGPU/gv-const-addrspace.ll index d4d13125cfbf..1f9b536cd80b 100644 --- a/test/CodeGen/AMDGPU/gv-const-addrspace.ll +++ b/test/CodeGen/AMDGPU/gv-const-addrspace.ll @@ -1,6 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s @b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2 @@ -10,13 +11,10 @@ ; FUNC-LABEL: {{^}}float: ; GCN: s_load_dword -; EG-DAG: MOV {{\** *}}T2.X -; EG-DAG: MOV {{\** *}}T3.X -; EG-DAG: MOV {{\** *}}T4.X -; EG-DAG: MOV {{\** *}}T5.X -; EG-DAG: MOV {{\** *}}T6.X -; EG: MOVA_INT - +; EG: VTX_READ_32 +; EG: @float_gv +; EG-NOT: MOVA_INT +; EG-NOT: MOV define void @float(float addrspace(1)* %out, i32 %index) { entry: %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index @@ -31,13 +29,10 @@ entry: ; GCN: s_load_dword -; EG-DAG: MOV {{\** *}}T2.X -; EG-DAG: MOV {{\** *}}T3.X -; EG-DAG: MOV {{\** *}}T4.X -; EG-DAG: MOV {{\** *}}T5.X -; EG-DAG: MOV {{\** *}}T6.X -; EG: MOVA_INT - +; EG: VTX_READ_32 +; EG: @i32_gv +; EG-NOT: MOVA_INT +; EG-NOT: MOV define void @i32(i32 addrspace(1)* %out, i32 %index) { entry: %0 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index @@ -54,6 +49,10 @@ entry: ; FUNC-LABEL: {{^}}struct_foo_gv_load: ; GCN: s_load_dword +; EG: VTX_READ_32 +; EG: @struct_foo_gv +; EG-NOT: MOVA_INT +; EG-NOT: MOV define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { %gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index %load = load i32, i32 addrspace(2)* %gep, align 4 @@ -68,6 +67,11 @@ define void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { ; FUNC-LABEL: {{^}}array_v1_gv_load: ; GCN: s_load_dword + +; EG: VTX_READ_32 +; EG: @array_v1_gv +; EG-NOT: MOVA_INT +; EG-NOT: MOV define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) { %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4 @@ -75,6 +79,11 @@ define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) { ret void } +; FUNC-LABEL: {{^}}gv_addressing_in_branch: + +; EG: VTX_READ_32 +; EG: @float_gv +; EG-NOT: MOVA_INT define void @gv_addressing_in_branch(float addrspace(1)* %out, i32 %index, i32 %a) { entry: %0 = icmp eq i32 0, %a diff --git a/test/CodeGen/AMDGPU/gv-offset-folding.ll b/test/CodeGen/AMDGPU/gv-offset-folding.ll new file mode 100644 index 000000000000..c75fdb35dd0e --- /dev/null +++ b/test/CodeGen/AMDGPU/gv-offset-folding.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -relocation-model=static < %s | FileCheck %s + +@lds = external addrspace(3) global [4 x i32] + +; Function Attrs: nounwind + +; Offset folding is an optimization done for global variables with relocations, +; which allows you to store the offset in the r_addend of the relocation entry. +; The offset is apllied to the variables address at link time, which eliminates +; the need to emit shader instructions to do this calculation. +; We don't use relocations for local memory, so we should never fold offsets +; for local memory globals. + +; CHECK-LABEL: lds_no_offset: +; CHECK ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:4 +define void @lds_no_offset() { +entry: + %ptr = getelementptr [4 x i32], [4 x i32] addrspace(3)* @lds, i32 0, i32 1 + store i32 0, i32 addrspace(3)* %ptr + ret void +} diff --git a/test/CodeGen/AMDGPU/half.ll b/test/CodeGen/AMDGPU/half.ll index a02cbf43c400..d21d66176a14 100644 --- a/test/CodeGen/AMDGPU/half.ll +++ b/test/CodeGen/AMDGPU/half.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; half args should be promoted to float @@ -13,10 +13,11 @@ define void @load_f16_arg(half addrspace(1)* %out, half %arg) #0 { } ; GCN-LABEL: {{^}}load_v2f16_arg: -; GCN-DAG: buffer_load_ushort [[V0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 -; GCN-DAG: buffer_load_ushort [[V1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46 -; GCN-DAG: buffer_store_short [[V0]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_short [[V1]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} +; GCN-DAG: buffer_load_ushort [[V0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 +; GCN-DAG: buffer_load_ushort [[V1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46 +; GCN: v_lshlrev_b32_e32 [[HI:v[0-9]+]], 16, [[V1]] +; GCN: v_or_b32_e32 [[PACKED:v[0-9]+]], [[V0]], [[HI]] +; GCN: buffer_store_dword [[PACKED]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: s_endpgm define void @load_v2f16_arg(<2 x half> addrspace(1)* %out, <2 x half> %arg) #0 { store <2 x half> %arg, <2 x half> addrspace(1)* %out @@ -42,10 +43,7 @@ define void @load_v3f16_arg(<3 x half> addrspace(1)* %out, <3 x half> %arg) #0 { ; GCN: buffer_load_ushort ; GCN: buffer_load_ushort ; GCN: buffer_load_ushort -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short +; GCN: buffer_store_dwordx2 ; GCN: s_endpgm define void @load_v4f16_arg(<4 x half> addrspace(1)* %out, <4 x half> %arg) #0 { store <4 x half> %arg, <4 x half> addrspace(1)* %out @@ -280,11 +278,11 @@ define void @global_extload_f16_to_f32(float addrspace(1)* %out, half addrspace( } ; GCN-LABEL: {{^}}global_extload_v2f16_to_v2f32: -; GCN-DAG: buffer_load_ushort [[LOAD0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_load_ushort [[LOAD1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} -; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT0:[0-9]+]], [[LOAD0]] -; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT1:[0-9]+]], [[LOAD1]] -; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[CVT0]]:[[CVT1]]{{\]}} +; GCN: buffer_load_dword [[LOAD:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN: v_cvt_f32_f16_e32 v[[CVT0:[0-9]+]], [[LOAD]] +; GCN: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, [[LOAD]] +; GCN: v_cvt_f32_f16_e32 v[[CVT1:[0-9]+]], [[HI]] +; GCN: buffer_store_dwordx2 v{{\[}}[[CVT0]]:[[CVT1]]{{\]}} ; GCN: s_endpgm define void @global_extload_v2f16_to_v2f32(<2 x float> addrspace(1)* %out, <2 x half> addrspace(1)* %in) #0 { %val = load <2 x half>, <2 x half> addrspace(1)* %in @@ -318,22 +316,8 @@ define void @global_extload_v8f16_to_v8f32(<8 x float> addrspace(1)* %out, <8 x } ; GCN-LABEL: {{^}}global_extload_v16f16_to_v16f32: -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort -; GCN: buffer_load_ushort +; GCN: buffer_load_dwordx4 +; GCN: buffer_load_dwordx4 ; GCN: v_cvt_f32_f16_e32 ; GCN: v_cvt_f32_f16_e32 @@ -378,10 +362,10 @@ define void @global_extload_f16_to_f64(double addrspace(1)* %out, half addrspace } ; GCN-LABEL: {{^}}global_extload_v2f16_to_v2f64: -; GCN-DAG: buffer_load_ushort [[LOAD0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_load_ushort [[LOAD1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:2{{$}} -; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT0:[0-9]+]], [[LOAD0]] -; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT1:[0-9]+]], [[LOAD1]] +; GCN-DAG: buffer_load_dword [[LOAD:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: v_lshrrev_b32_e32 [[HI:v[0-9]+]], 16, [[LOAD]] +; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT0:[0-9]+]], [[LOAD]] +; GCN-DAG: v_cvt_f32_f16_e32 v[[CVT1:[0-9]+]], [[HI]] ; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[CVT2_LO:[0-9]+]]:[[CVT2_HI:[0-9]+]]{{\]}}, v[[CVT0]] ; GCN-DAG: v_cvt_f64_f32_e32 v{{\[}}[[CVT3_LO:[0-9]+]]:[[CVT3_HI:[0-9]+]]{{\]}}, v[[CVT1]] ; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[CVT2_LO]]:[[CVT3_HI]]{{\]}} @@ -396,22 +380,18 @@ define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x ; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f64: ; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] -; SI: v_lshr_b64 v{{\[[0-9]+:[0-9]+\]}}, [[LOAD]], 32 -; VI: v_lshrrev_b64 v{{\[[0-9]+:[0-9]+\]}}, 32, [[LOAD]] -; GCN: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} - -; GCN: v_cvt_f32_f16_e32 -; GCN: v_cvt_f32_f16_e32 -; GCN: v_cvt_f32_f16_e32 -; GCN-NOT: v_cvt_f32_f16_e32 +; GCN-DAG: v_cvt_f32_f16_e32 +; GCN-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} +; GCN-DAG: v_cvt_f32_f16_e32 +; GCN-DAG: v_cvt_f32_f16_e32 ; GCN: v_cvt_f64_f32_e32 ; GCN: v_cvt_f64_f32_e32 ; GCN: v_cvt_f64_f32_e32 ; GCN-NOT: v_cvt_f64_f32_e32 -; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 ; GCN: s_endpgm define void @global_extload_v3f16_to_v3f64(<3 x double> addrspace(1)* %out, <3 x half> addrspace(1)* %in) #0 { %val = load <3 x half>, <3 x half> addrspace(1)* %in @@ -459,8 +439,9 @@ define void @global_truncstore_f32_to_f16(half addrspace(1)* %out, float addrspa ; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} ; GCN-DAG: v_cvt_f16_f32_e32 [[CVT0:v[0-9]+]], v[[LO]] ; GCN-DAG: v_cvt_f16_f32_e32 [[CVT1:v[0-9]+]], v[[HI]] -; GCN-DAG: buffer_store_short [[CVT0]] -; GCN-DAG: buffer_store_short [[CVT1]] +; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[CVT1]] +; GCN-DAG: v_or_b32_e32 [[PACKED:v[0-9]+]], [[CVT0]], [[SHL]] +; GCN-DAG: buffer_store_dword [[PACKED]] ; GCN: s_endpgm define void @global_truncstore_v2f32_to_v2f16(<2 x half> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 { %val = load <2 x float>, <2 x float> addrspace(1)* %in @@ -491,10 +472,7 @@ define void @global_truncstore_v3f32_to_v3f16(<3 x half> addrspace(1)* %out, <3 ; GCN: v_cvt_f16_f32_e32 ; GCN: v_cvt_f16_f32_e32 ; GCN: v_cvt_f16_f32_e32 -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short +; GCN: buffer_store_dwordx2 ; GCN: s_endpgm define void @global_truncstore_v4f32_to_v4f16(<4 x half> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 { %val = load <4 x float>, <4 x float> addrspace(1)* %in @@ -514,14 +492,7 @@ define void @global_truncstore_v4f32_to_v4f16(<4 x half> addrspace(1)* %out, <4 ; GCN: v_cvt_f16_f32_e32 ; GCN: v_cvt_f16_f32_e32 ; GCN: v_cvt_f16_f32_e32 -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short -; GCN: buffer_store_short +; GCN: buffer_store_dwordx4 ; GCN: s_endpgm define void @global_truncstore_v8f32_to_v8f16(<8 x half> addrspace(1)* %out, <8 x float> addrspace(1)* %in) #0 { %val = load <8 x float>, <8 x float> addrspace(1)* %in @@ -551,22 +522,8 @@ define void @global_truncstore_v8f32_to_v8f16(<8 x half> addrspace(1)* %out, <8 ; GCN-DAG: v_cvt_f16_f32_e32 ; GCN-DAG: v_cvt_f16_f32_e32 ; GCN-DAG: v_cvt_f16_f32_e32 -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short -; GCN-DAG: buffer_store_short +; GCN-DAG: buffer_store_dwordx4 +; GCN-DAG: buffer_store_dwordx4 ; GCN: s_endpgm define void @global_truncstore_v16f32_to_v16f16(<16 x half> addrspace(1)* %out, <16 x float> addrspace(1)* %in) #0 { %val = load <16 x float>, <16 x float> addrspace(1)* %in diff --git a/test/CodeGen/AMDGPU/hsa-default-device.ll b/test/CodeGen/AMDGPU/hsa-default-device.ll new file mode 100644 index 000000000000..631d6def4442 --- /dev/null +++ b/test/CodeGen/AMDGPU/hsa-default-device.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s + +; Make sure that with an HSA triple, we don't default to an +; unsupported device. + +; CHECK: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" +define void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind { + store float 0.0, float addrspace(1)* %out0 + ret void +} + diff --git a/test/CodeGen/AMDGPU/hsa-fp-mode.ll b/test/CodeGen/AMDGPU/hsa-fp-mode.ll new file mode 100644 index 000000000000..36aa6779d382 --- /dev/null +++ b/test/CodeGen/AMDGPU/hsa-fp-mode.ll @@ -0,0 +1,68 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}test_default_ci: +; GCN: compute_pgm_rsrc1_float_mode = 192 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}test_default_vi: +; GCN: compute_pgm_rsrc1_float_mode = 192 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}test_f64_denormals: +; GCN: compute_pgm_rsrc1_float_mode = 192 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}test_f32_denormals: +; GCN: compute_pgm_rsrc1_float_mode = 48 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}test_f32_f64_denormals: +; GCN: compute_pgm_rsrc1_float_mode = 240 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +; GCN-LABEL: {{^}}test_no_denormals: +; GCN: compute_pgm_rsrc1_float_mode = 0 +; GCN: compute_pgm_rsrc1_dx10_clamp = 1 +; GCN: compute_pgm_rsrc1_ieee_mode = 0 +define void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 { + store float 0.0, float addrspace(1)* %out0 + store double 0.0, double addrspace(1)* %out1 + ret void +} + +attributes #0 = { nounwind "target-cpu"="kaveri" } +attributes #1 = { nounwind "target-cpu"="fiji" } +attributes #2 = { nounwind "target-features"="-fp32-denormals,+fp64-denormals" } +attributes #3 = { nounwind "target-features"="+fp32-denormals,-fp64-denormals" } +attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" } +attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-denormals" } diff --git a/test/CodeGen/AMDGPU/hsa-func.ll b/test/CodeGen/AMDGPU/hsa-func.ll new file mode 100644 index 000000000000..28c8b5d73b02 --- /dev/null +++ b/test/CodeGen/AMDGPU/hsa-func.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF + +; The SHT_NOTE section contains the output from the .hsa_code_object_* +; directives. + +; ELF: Section { +; ELF: Name: .text +; ELF: Type: SHT_PROGBITS (0x1) +; ELF: Flags [ (0x6) +; ELF: SHF_ALLOC (0x2) +; ELF: SHF_EXECINSTR (0x4) +; ELF: } + +; ELF: SHT_NOTE +; ELF: 0000: 04000000 08000000 01000000 414D4400 +; ELF: 0010: 02000000 01000000 04000000 1B000000 + +; ELF: 0020: 03000000 414D4400 04000700 07000000 +; ELF: 0030: 00000000 00000000 414D4400 414D4447 +; ELF: 0040: 50550000 + +; ELF: Symbol { +; ELF: Name: simple +; ELF: Size: 288 +; ELF: Type: Function (0x2) +; ELF: } + +; HSA: .hsa_code_object_version 2,1 +; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" +; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" + +; HSA: .text + +; HSA-NOT: .amdgpu_hsa_kernel simple +; HSA: {{^}}simple: +; HSA: .amd_kernel_code_t +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: .end_amd_kernel_code_t +; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0 + +; Make sure we are setting the ATC bit: +; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000 +; On VI+ we also need to set MTYPE = 2 +; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000 +; Make sure we generate flat store for HSA +; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} + +; HSA: .Lfunc_end0: +; HSA: .size simple, .Lfunc_end0-simple + +define void @simple(i32 addrspace(1)* %out) { +entry: + store i32 0, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/hsa-globals.ll b/test/CodeGen/AMDGPU/hsa-globals.ll index 90322ac3dc01..df478fbcf3b5 100644 --- a/test/CodeGen/AMDGPU/hsa-globals.ll +++ b/test/CodeGen/AMDGPU/hsa-globals.ll @@ -1,14 +1,11 @@ ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=ASM %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s | FileCheck %s --check-prefix=ELF +@linkonce_odr_global_program = linkonce_odr addrspace(1) global i32 0 +@linkonce_global_program = linkonce addrspace(1) global i32 0 @internal_global_program = internal addrspace(1) global i32 0 @common_global_program = common addrspace(1) global i32 0 @external_global_program = addrspace(1) global i32 0 -@internal_global_agent = internal addrspace(1) global i32 0, section ".hsadata_global_agent" -@common_global_agent = common addrspace(1) global i32 0, section ".hsadata_global_agent" -@external_global_agent = addrspace(1) global i32 0, section ".hsadata_global_agent" - @internal_readonly = internal unnamed_addr addrspace(2) constant i32 0 @external_readonly = unnamed_addr addrspace(2) constant i32 0 @@ -16,133 +13,38 @@ define void @test() { ret void } -; ASM: .amdgpu_hsa_module_global internal_global -; ASM: .size internal_global_program, 4 -; ASM: .hsadata_global_program -; ASM: internal_global_program: -; ASM: .long 0 - -; ASM: .amdgpu_hsa_module_global common_global -; ASM: .size common_global_program, 4 -; ASM: .hsadata_global_program -; ASM: common_global_program: +; ASM: .type linkonce_odr_global_program,@object +; ASM: .section .bss,#alloc,#write +; ASM: .weak linkonce_odr_global_program +; ASM: linkonce_odr_global_program: ; ASM: .long 0 +; ASM: .size linkonce_odr_global_program, 4 -; ASM: .amdgpu_hsa_program_global external_global -; ASM: .size external_global_program, 4 -; ASM: .hsadata_global_program -; ASM: external_global_program: +; ASM: .type linkonce_global_program,@object +; ASM: .weak linkonce_global_program +; ASM: linkonce_global_program: ; ASM: .long 0 +; ASM: .size linkonce_global_program, 4 -; ASM: .amdgpu_hsa_module_global internal_global -; ASM: .size internal_global_agent, 4 -; ASM: .hsadata_global_agent -; ASM: internal_global_agent: -; ASM: .long 0 +; ASM: .type internal_global_program,@object +; ASM: .local internal_global_program +; ASM: .comm internal_global_program,4,2 -; ASM: .amdgpu_hsa_module_global common_global -; ASM: .size common_global_agent, 4 -; ASM: .hsadata_global_agent -; ASM: common_global_agent: -; ASM: .long 0 +; ASM: .type common_global_program,@object +; ASM: .comm common_global_program,4,2 -; ASM: .amdgpu_hsa_program_global external_global -; ASM: .size external_global_agent, 4 -; ASM: .hsadata_global_agent -; ASM: external_global_agent: +; ASM: external_global_program: ; ASM: .long 0 +; ASM: .size external_global_program, 4 -; ASM: .amdgpu_hsa_module_global internal_readonly -; ASM: .size internal_readonly, 4 -; ASM: .hsatext +; ASM: .type internal_readonly,@object +; ASM: .text ; ASM: internal_readonly: ; ASM: .long 0 +; ASM: .size internal_readonly, 4 -; ASM: .amdgpu_hsa_program_global external_readonly -; ASM: .size external_readonly, 4 -; ASM: .hsatext +; ASM: .type external_readonly,@object +; ASM: .globl external_readonly ; ASM: external_readonly: ; ASM: .long 0 - -; ELF: Section { -; ELF: Name: .hsadata_global_program -; ELF: Type: SHT_PROGBITS (0x1) -; ELF: Flags [ (0x100003) -; ELF: SHF_ALLOC (0x2) -; ELF: SHF_AMDGPU_HSA_GLOBAL (0x100000) -; ELF: SHF_WRITE (0x1) -; ELF: ] -; ELF: } - -; ELF: Section { -; ELF: Name: .hsadata_global_agent -; ELF: Type: SHT_PROGBITS (0x1) -; ELF: Flags [ (0x900003) -; ELF: SHF_ALLOC (0x2) -; ELF: SHF_AMDGPU_HSA_AGENT (0x800000) -; ELF: SHF_AMDGPU_HSA_GLOBAL (0x100000) -; ELF: SHF_WRITE (0x1) -; ELF: ] -; ELF: } - -; ELF: Symbol { -; ELF: Name: common_global_agent -; ELF: Size: 4 -; ELF: Binding: Local -; ELF: Section: .hsadata_global_agent -; ELF: } - -; ELF: Symbol { -; ELF: Name: common_global_program -; ELF: Size: 4 -; ELF: Binding: Local -; ELF: Section: .hsadata_global_program -; ELF: } - -; ELF: Symbol { -; ELF: Name: internal_global_agent -; ELF: Size: 4 -; ELF: Binding: Local -; ELF: Type: Object -; ELF: Section: .hsadata_global_agent -; ELF: } - -; ELF: Symbol { -; ELF: Name: internal_global_program -; ELF: Size: 4 -; ELF: Binding: Local -; ELF: Type: Object -; ELF: Section: .hsadata_global_program -; ELF: } - -; ELF: Symbol { -; ELF: Name: internal_readonly -; ELF: Size: 4 -; ELF: Binding: Local -; ELF: Type: Object -; ELF: Section: .hsatext -; ELF: } - -; ELF: Symbol { -; ELF: Name: external_global_agent -; ELF: Size: 4 -; ELF: Binding: Global -; ELF: Type: Object -; ELF: Section: .hsadata_global_agent -; ELF: } - -; ELF: Symbol { -; ELF: Name: external_global_program -; ELF: Size: 4 -; ELF: Binding: Global -; ELF: Type: Object -; ELF: Section: .hsadata_global_program -; ELF: } - -; ELF: Symbol { -; ELF: Name: external_readonly -; ELF: Size: 4 -; ELF: Binding: Global -; ELF: Type: Object -; ELF: Section: .hsatext -; ELF: } +; ASM: .size external_readonly, 4 diff --git a/test/CodeGen/AMDGPU/hsa-note-no-func.ll b/test/CodeGen/AMDGPU/hsa-note-no-func.ll index f82e98e79545..1b4a0f3090b8 100644 --- a/test/CodeGen/AMDGPU/hsa-note-no-func.ll +++ b/test/CodeGen/AMDGPU/hsa-note-no-func.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo | FileCheck --check-prefix=HSA --check-prefix=HSA-VI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji | FileCheck --check-prefix=HSA --check-prefix=HSA-FIJI %s -; HSA: .hsa_code_object_version 1,0 +; HSA: .hsa_code_object_version 2,1 ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" ; HSA-FIJI: .hsa_code_object_isa 8,0,3,"AMD","AMDGPU" diff --git a/test/CodeGen/AMDGPU/hsa.ll b/test/CodeGen/AMDGPU/hsa.ll index c089dfd9a971..82d7da188ca3 100644 --- a/test/CodeGen/AMDGPU/hsa.ll +++ b/test/CodeGen/AMDGPU/hsa.ll @@ -9,34 +9,31 @@ ; directives. ; ELF: Section { -; ELF: Name: .hsatext +; ELF: Name: .text ; ELF: Type: SHT_PROGBITS (0x1) -; ELF: Flags [ (0xC00007) +; ELF: Flags [ (0x6) ; ELF: SHF_ALLOC (0x2) -; ELF: SHF_AMDGPU_HSA_AGENT (0x800000) -; ELF: SHF_AMDGPU_HSA_CODE (0x400000) ; ELF: SHF_EXECINSTR (0x4) -; ELF: SHF_WRITE (0x1) ; ELF: } ; ELF: SHT_NOTE ; ELF: 0000: 04000000 08000000 01000000 414D4400 -; ELF: 0010: 01000000 00000000 04000000 1B000000 +; ELF: 0010: 02000000 01000000 04000000 1B000000 ; ELF: 0020: 03000000 414D4400 04000700 07000000 ; ELF: 0030: 00000000 00000000 414D4400 414D4447 ; ELF: 0040: 50550000 ; ELF: Symbol { ; ELF: Name: simple -; ELF: Size: 296 +; ELF: Size: 288 ; ELF: Type: AMDGPU_HSA_KERNEL (0xA) ; ELF: } -; HSA: .hsa_code_object_version 1,0 +; HSA: .hsa_code_object_version 2,1 ; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" -; HSA: .hsatext +; HSA: .text ; HSA: .amdgpu_hsa_kernel simple ; HSA: {{^}}simple: @@ -51,12 +48,12 @@ ; On VI+ we also need to set MTYPE = 2 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000 ; Make sure we generate flat store for HSA -; HSA: flat_store_dword v{{[0-9]+}} +; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} ; HSA: .Lfunc_end0: ; HSA: .size simple, .Lfunc_end0-simple -define void @simple(i32 addrspace(1)* %out) { +define amdgpu_kernel void @simple(i32 addrspace(1)* %out) { entry: store i32 0, i32 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll b/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll index b11a21137642..d6309a2dd5de 100644 --- a/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll +++ b/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll @@ -4,9 +4,8 @@ ; SILowerI1Copies was not handling IMPLICIT_DEF ; SI-LABEL: {{^}}br_implicit_def: ; SI: BB#0: -; SI-NEXT: s_and_saveexec_b64 -; SI-NEXT: s_xor_b64 -; SI-NEXT: BB#1: +; SI-NEXT: s_and_b64 vcc, exec +; SI-NEXT: s_cbranch_vccnz define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 { bb: br i1 undef, label %bb1, label %bb2 diff --git a/test/CodeGen/AMDGPU/i1-copy-phi.ll b/test/CodeGen/AMDGPU/i1-copy-phi.ll index 105cd06b330a..4d50dc2f4023 100644 --- a/test/CodeGen/AMDGPU/i1-copy-phi.ll +++ b/test/CodeGen/AMDGPU/i1-copy-phi.ll @@ -10,9 +10,11 @@ ; SI: s_and_saveexec_b64 ; SI: s_xor_b64 ; SI: s_endpgm -define void @br_i1_phi(i32 %arg, i1 %arg1) #0 { +define void @br_i1_phi(i32 %arg) { bb: - br i1 %arg1, label %bb2, label %bb3 + %tidig = call i32 @llvm.r600.read.tidig.x() #0 + %cmp = trunc i32 %tidig to i1 + br i1 %cmp, label %bb2, label %bb3 bb2: ; preds = %bb br label %bb3 @@ -22,9 +24,14 @@ bb3: ; preds = %bb2, %bb br i1 %tmp, label %bb4, label %bb6 bb4: ; preds = %bb3 - %tmp5 = mul i32 undef, %arg + %val = load volatile i32, i32 addrspace(1)* undef + %tmp5 = mul i32 %val, %arg br label %bb6 bb6: ; preds = %bb4, %bb3 ret void } + +declare i32 @llvm.r600.read.tidig.x() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/imm.ll b/test/CodeGen/AMDGPU/imm.ll index 8db9ea4ccf31..674eceee8122 100644 --- a/test/CodeGen/AMDGPU/imm.ll +++ b/test/CodeGen/AMDGPU/imm.ll @@ -23,7 +23,7 @@ entry: ; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64: ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} -; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000 +; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}} ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) { store i64 -9223372036854775808, i64 addrspace(1) *%out @@ -31,7 +31,7 @@ define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) { } ; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32: -; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; CHECK: buffer_store_dword [[REG]] define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) { store i32 -2147483648, i32 addrspace(1)* %out @@ -47,7 +47,7 @@ define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) { } ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32: -; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x80000000 +; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}} ; CHECK: buffer_store_dword [[REG]] define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) { store float -0.0, float addrspace(1)* %out @@ -322,7 +322,7 @@ define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) { ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0{{$}} ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0.0 @@ -333,7 +333,7 @@ define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 0.5, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.5 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0.5 @@ -344,7 +344,7 @@ define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -0.5, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -0.5 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, -0.5 @@ -355,7 +355,7 @@ define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 1.0 @@ -366,7 +366,7 @@ define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, -1.0 @@ -377,7 +377,7 @@ define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 2.0 @@ -388,7 +388,7 @@ define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, -2.0 @@ -399,7 +399,7 @@ define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 4.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 4.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 4.0 @@ -410,7 +410,7 @@ define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -4.0, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -4.0 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, -4.0 @@ -422,7 +422,7 @@ define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_1_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 1, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1{{$}} ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0x0000000000000001 @@ -433,7 +433,7 @@ define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_2_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 2, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2{{$}} ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0x0000000000000002 @@ -444,7 +444,7 @@ define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_16_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 16, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 16 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0x0000000000000010 @@ -455,7 +455,7 @@ define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -1, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0xffffffffffffffff @@ -466,7 +466,7 @@ define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -2, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0xfffffffffffffffe @@ -477,7 +477,7 @@ define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], -16, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -16 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0xfffffffffffffff0 @@ -488,7 +488,7 @@ define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_63_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 63, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 63 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0x000000000000003F @@ -499,7 +499,7 @@ define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}add_inline_imm_64_f64: ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c -; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], 64, [[VAL]] +; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 64 ; CHECK: buffer_store_dwordx2 [[REG]] define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { %y = fadd double %x, 0x0000000000000040 @@ -510,7 +510,7 @@ define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) { ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64: ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0 -; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0 +; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], v[[LO_VREG]]{{$}} ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { store double 0.0, double addrspace(1)* %out @@ -520,7 +520,7 @@ define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) { ; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64: ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}} -; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x80000000 +; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}} ; CHECK: buffer_store_dwordx2 v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}} define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) { store double -0.0, double addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/indirect-addressing-si.ll b/test/CodeGen/AMDGPU/indirect-addressing-si.ll index e40cac22725c..66cec88e760c 100644 --- a/test/CodeGen/AMDGPU/indirect-addressing-si.ll +++ b/test/CodeGen/AMDGPU/indirect-addressing-si.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; Tests for indirect addressing on SI, which is implemented using dynamic ; indexing of vectors. @@ -87,13 +87,34 @@ entry: ; CHECK: s_cbranch_execnz define void @extract_neg_offset_vgpr(i32 addrspace(1)* %out) { entry: - %id = call i32 @llvm.r600.read.tidig.x() #1 + %id = call i32 @llvm.amdgcn.workitem.id.x() #1 %index = add i32 %id, -512 %value = extractelement <4 x i32> , i32 %index store i32 %value, i32 addrspace(1)* %out ret void } +; CHECK-LABEL: {{^}}extract_undef_offset_sgpr: +define void @extract_undef_offset_sgpr(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %value = extractelement <4 x i32> %ld, i32 undef + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}insert_undef_offset_sgpr_vector_src: +; CHECK: buffer_load_dwordx4 +; CHECK: s_mov_b32 m0, +; CHECK-NEXT: v_movreld_b32 +define void @insert_undef_offset_sgpr_vector_src(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { +entry: + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %value = insertelement <4 x i32> %ld, i32 5, i32 undef + store <4 x i32> %value, <4 x i32> addrspace(1)* %out + ret void +} + ; CHECK-LABEL: {{^}}insert_w_offset: ; CHECK: s_mov_b32 m0 ; CHECK-NEXT: v_movreld_b32_e32 @@ -152,7 +173,7 @@ entry: ; CHECK: s_cbranch_execnz define void @insert_neg_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) { entry: - %id = call i32 @llvm.r600.read.tidig.x() #1 + %id = call i32 @llvm.amdgcn.workitem.id.x() #1 %index = add i32 %id, -512 %value = insertelement <4 x i32> , i32 5, i32 %index store <4 x i32> %value, <4 x i32> addrspace(1)* %out @@ -167,12 +188,304 @@ entry: ; CHECK: s_cbranch_execnz define void @insert_neg_inline_offset_vgpr(i32 addrspace(1)* %in, <4 x i32> addrspace(1)* %out) { entry: - %id = call i32 @llvm.r600.read.tidig.x() #1 + %id = call i32 @llvm.amdgcn.workitem.id.x() #1 %index = add i32 %id, -16 %value = insertelement <4 x i32> , i32 5, i32 %index store <4 x i32> %value, <4 x i32> addrspace(1)* %out ret void } -declare i32 @llvm.r600.read.tidig.x() #1 +; When the block is split to insert the loop, make sure any other +; places that need to be expanded in the same block are also handled. + +; CHECK-LABEL: {{^}}extract_vgpr_offset_multiple_in_block: + +; CHECK-DAG: {{buffer|flat}}_load_dword [[IDX0:v[0-9]+]] +; CHECK-DAG: s_mov_b32 [[S_ELT0:s[0-9]+]], 7 +; CHECK-DAG: s_mov_b32 [[S_ELT1:s[0-9]+]], 9 +; CHECK-DAG: v_mov_b32_e32 [[VEC_ELT0:v[0-9]+]], [[S_ELT0]] +; CHECK-DAG: v_mov_b32_e32 [[VEC_ELT1:v[0-9]+]], [[S_ELT1]] +; CHECK: s_waitcnt vmcnt(0) + +; CHECK: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec + +; CHECK: [[LOOP0:BB[0-9]+_[0-9]+]]: +; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]] +; CHECK: s_mov_b32 m0, vcc_lo +; CHECK: v_cmp_eq_u32_e32 vcc, m0, [[IDX0]] +; CHECK: s_and_saveexec_b64 vcc, vcc +; CHECK-NEXT: v_movrels_b32_e32 [[MOVREL0:v[0-9]+]], [[VEC_ELT0]] +; CHECK-NEXT: s_xor_b64 exec, exec, vcc +; CHECK: s_cbranch_execnz [[LOOP0]] + +; FIXME: Redundant copy +; CHECK: s_mov_b64 exec, [[MASK]] +; CHECK: s_mov_b64 [[MASK2:s\[[0-9]+:[0-9]+\]]], exec + +; CHECK: [[LOOP1:BB[0-9]+_[0-9]+]]: +; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]] +; CHECK: s_mov_b32 m0, vcc_lo +; CHECK: v_cmp_eq_u32_e32 vcc, m0, [[IDX0]] +; CHECK: s_and_saveexec_b64 vcc, vcc +; CHECK-NEXT: v_movrels_b32_e32 [[MOVREL1:v[0-9]+]], [[VEC_ELT1]] +; CHECK-NEXT: s_xor_b64 exec, exec, vcc +; CHECK: s_cbranch_execnz [[LOOP1]] + +; CHECK: buffer_store_dword [[MOVREL0]] +; CHECK: buffer_store_dword [[MOVREL1]] +define void @extract_vgpr_offset_multiple_in_block(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 { +entry: + %id = call i32 @llvm.amdgcn.workitem.id.x() #1 + %id.ext = zext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %id.ext + %idx0 = load volatile i32, i32 addrspace(1)* %gep + %idx1 = add i32 %idx0, 1 + %val0 = extractelement <4 x i32> , i32 %idx0 + %live.out.reg = call i32 asm sideeffect "s_mov_b32 $0, 17", "={SGPR4}" () + %val1 = extractelement <4 x i32> , i32 %idx1 + store volatile i32 %val0, i32 addrspace(1)* %out0 + store volatile i32 %val1, i32 addrspace(1)* %out0 + %cmp = icmp eq i32 %id, 0 + br i1 %cmp, label %bb1, label %bb2 + +bb1: + store volatile i32 %live.out.reg, i32 addrspace(1)* undef + br label %bb2 + +bb2: + ret void +} + +; CHECK-LABEL: {{^}}insert_vgpr_offset_multiple_in_block: +; CHECK-DAG: s_load_dwordx4 s{{\[}}[[S_ELT0:[0-9]+]]:[[S_ELT3:[0-9]+]]{{\]}} +; CHECK-DAG: {{buffer|flat}}_load_dword [[IDX0:v[0-9]+]] +; CHECK-DAG: v_mov_b32_e32 [[VEC_ELT0:v[0-9]+]], s[[S_ELT0]] +; CHECK-DAG: v_mov_b32 [[INS0:v[0-9]+]], 62 +; CHECK-DAG: s_waitcnt vmcnt(0) + +; CHECK: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec + +; CHECK: [[LOOP0:BB[0-9]+_[0-9]+]]: +; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]] +; CHECK: s_mov_b32 m0, vcc_lo +; CHECK: v_cmp_eq_u32_e32 vcc, m0, [[IDX0]] +; CHECK: s_and_saveexec_b64 vcc, vcc +; CHECK-NEXT: v_movreld_b32_e32 v[[MOVREL0:[0-9]+]], [[INS0]] +; CHECK-NEXT: s_xor_b64 exec, exec, vcc +; CHECK: s_cbranch_execnz [[LOOP0]] + +; FIXME: Redundant copy +; CHECK: s_mov_b64 exec, [[MASK]] +; CHECK: v_mov_b32_e32 [[INS1:v[0-9]+]], 63 +; CHECK: s_mov_b64 [[MASK]], exec + +; CHECK: [[LOOP1:BB[0-9]+_[0-9]+]]: +; CHECK: v_readfirstlane_b32 vcc_lo, [[IDX0]] +; CHECK: s_mov_b32 m0, vcc_lo +; CHECK: v_cmp_eq_u32_e32 vcc, m0, [[IDX0]] +; CHECK: s_and_saveexec_b64 vcc, vcc +; CHECK-NEXT: v_movreld_b32_e32 v[[MOVREL1:[0-9]+]], [[INS1]] +; CHECK-NEXT: s_xor_b64 exec, exec, vcc +; CHECK: s_cbranch_execnz [[LOOP1]] + +; CHECK: buffer_store_dwordx4 v{{\[}}[[MOVREL0]]: + +; CHECK: buffer_store_dword [[INS0]] +define void @insert_vgpr_offset_multiple_in_block(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, i32 addrspace(1)* %in, <4 x i32> %vec0) #0 { +entry: + %id = call i32 @llvm.amdgcn.workitem.id.x() #1 + %id.ext = zext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %id.ext + %idx0 = load volatile i32, i32 addrspace(1)* %gep + %idx1 = add i32 %idx0, 1 + %live.out.val = call i32 asm sideeffect "v_mov_b32 $0, 62", "=v"() + %vec1 = insertelement <4 x i32> %vec0, i32 %live.out.val, i32 %idx0 + %vec2 = insertelement <4 x i32> %vec1, i32 63, i32 %idx1 + store volatile <4 x i32> %vec2, <4 x i32> addrspace(1)* %out0 + %cmp = icmp eq i32 %id, 0 + br i1 %cmp, label %bb1, label %bb2 + +bb1: + store volatile i32 %live.out.val, i32 addrspace(1)* undef + br label %bb2 + +bb2: + ret void +} + +; CHECK-LABEL: {{^}}extract_adjacent_blocks: +; CHECK: s_load_dword [[ARG:s[0-9]+]] +; CHECK: s_cmp_lg_i32 +; CHECK: s_cbranch_scc0 [[BB4:BB[0-9]+_[0-9]+]] + +; CHECK: buffer_load_dwordx4 +; CHECK: s_mov_b32 m0, +; CHECK: v_movrels_b32_e32 +; CHECK: s_branch [[ENDBB:BB[0-9]+_[0-9]+]] + +; CHECK: [[BB4]]: +; CHECK: buffer_load_dwordx4 +; CHECK: s_mov_b32 m0, +; CHECK: v_movrels_b32_e32 + +; CHECK: [[ENDBB]]: +; CHECK: buffer_store_dword +; CHECK: s_endpgm +define void @extract_adjacent_blocks(i32 %arg) #0 { +bb: + %tmp = icmp eq i32 %arg, 0 + br i1 %tmp, label %bb1, label %bb4 + +bb1: + %tmp2 = load volatile <4 x float>, <4 x float> addrspace(1)* undef + %tmp3 = extractelement <4 x float> %tmp2, i32 undef + br label %bb7 + +bb4: + %tmp5 = load volatile <4 x float>, <4 x float> addrspace(1)* undef + %tmp6 = extractelement <4 x float> %tmp5, i32 undef + br label %bb7 + +bb7: + %tmp8 = phi float [ %tmp3, %bb1 ], [ %tmp6, %bb4 ] + store volatile float %tmp8, float addrspace(1)* undef + ret void +} + +; CHECK-LABEL: {{^}}insert_adjacent_blocks: +; CHECK: s_load_dword [[ARG:s[0-9]+]] +; CHECK: s_cmp_lg_i32 +; CHECK: s_cbranch_scc0 [[BB4:BB[0-9]+_[0-9]+]] + +; CHECK: buffer_load_dwordx4 +; CHECK: s_mov_b32 m0, +; CHECK: v_movreld_b32_e32 +; CHECK: s_branch [[ENDBB:BB[0-9]+_[0-9]+]] + +; CHECK: [[BB4]]: +; CHECK: buffer_load_dwordx4 +; CHECK: s_mov_b32 m0, +; CHECK: v_movreld_b32_e32 + +; CHECK: [[ENDBB]]: +; CHECK: buffer_store_dword +; CHECK: s_endpgm +define void @insert_adjacent_blocks(i32 %arg, float %val0) #0 { +bb: + %tmp = icmp eq i32 %arg, 0 + br i1 %tmp, label %bb1, label %bb4 + +bb1: ; preds = %bb + %tmp2 = load volatile <4 x float>, <4 x float> addrspace(1)* undef + %tmp3 = insertelement <4 x float> %tmp2, float %val0, i32 undef + br label %bb7 + +bb4: ; preds = %bb + %tmp5 = load volatile <4 x float>, <4 x float> addrspace(1)* undef + %tmp6 = insertelement <4 x float> %tmp5, float %val0, i32 undef + br label %bb7 + +bb7: ; preds = %bb4, %bb1 + %tmp8 = phi <4 x float> [ %tmp3, %bb1 ], [ %tmp6, %bb4 ] + store volatile <4 x float> %tmp8, <4 x float> addrspace(1)* undef + ret void +} + +; FIXME: Should be able to fold zero input to movreld to inline imm? + +; CHECK-LABEL: {{^}}multi_same_block: +; CHECK: s_load_dword [[ARG:s[0-9]+]] +; CHECK-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; CHECK-DAG: s_add_i32 m0, [[ARG]], -16 +; CHECK: v_movreld_b32_e32 v{{[0-9]+}}, [[ZERO]] + +; CHECK: s_add_i32 m0, [[ARG]], -14 +; CHECK: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} + +; CHECK: s_mov_b32 m0, -1 +; CHECK: ds_write_b32 +; CHECK: ds_write_b32 +; CHECK: s_endpgm +define void @multi_same_block(i32 %arg) #0 { +bb: + %tmp1 = add i32 %arg, -16 + %tmp2 = insertelement <6 x float> , float 0.000000e+00, i32 %tmp1 + %tmp3 = add i32 %arg, -16 + %tmp4 = insertelement <6 x float> , float 0x3FB99999A0000000, i32 %tmp3 + %tmp5 = bitcast <6 x float> %tmp2 to <6 x i32> + %tmp6 = extractelement <6 x i32> %tmp5, i32 1 + %tmp7 = bitcast <6 x float> %tmp4 to <6 x i32> + %tmp8 = extractelement <6 x i32> %tmp7, i32 5 + store volatile i32 %tmp6, i32 addrspace(3)* undef, align 4 + store volatile i32 %tmp8, i32 addrspace(3)* undef, align 4 + ret void +} + +; offset puts outside of superegister bounaries, so clamp to 1st element. +; CHECK-LABEL: {{^}}extract_largest_inbounds_offset: +; CHECK: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]{{\]}} +; CHECK: s_load_dword [[IDX:s[0-9]+]] +; CHECK: s_mov_b32 m0, [[IDX]] +; CHECK-NEXT: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[HI_ELT]] +; CHECK: buffer_store_dword [[EXTRACT]] +define void @extract_largest_inbounds_offset(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { +entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %offset = add i32 %idx, 3 + %value = extractelement <4 x i32> %ld, i32 %offset + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABL: {{^}}extract_out_of_bounds_offset: +; CHECK: buffer_load_dwordx4 v{{\[}}[[LO_ELT:[0-9]+]]:[[HI_ELT:[0-9]+]]{{\]}} +; CHECK: s_load_dword [[IDX:s[0-9]+]] +; CHECK: s_add_i32 m0, [[IDX]], 4 +; CHECK-NEXT: v_movrels_b32_e32 [[EXTRACT:v[0-9]+]], v[[LO_ELT]] +; CHECK: buffer_store_dword [[EXTRACT]] +define void @extract_out_of_bounds_offset(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { +entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %offset = add i32 %idx, 4 + %value = extractelement <4 x i32> %ld, i32 %offset + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; Test that the or is folded into the base address register instead of +; added to m0 + +; GCN-LABEL: {{^}}extractelement_v4i32_or_index: +; GCN: s_load_dword [[IDX_IN:s[0-9]+]] +; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]] +; GCN-NOT: [[IDX_SHL]] +; GCN: s_mov_b32 m0, [[IDX_SHL]] +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} +define void @extractelement_v4i32_or_index(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx.in) { +entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %idx.shl = shl i32 %idx.in, 2 + %idx = or i32 %idx.shl, 1 + %value = extractelement <4 x i32> %ld, i32 %idx + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}insertelement_v4f32_or_index: +; GCN: s_load_dword [[IDX_IN:s[0-9]+]] +; GCN: s_lshl_b32 [[IDX_SHL:s[0-9]+]], [[IDX_IN]] +; GCN-NOT: [[IDX_SHL]] +; GCN: s_mov_b32 m0, [[IDX_SHL]] +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} +define void @insertelement_v4f32_or_index(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %idx.in) nounwind { + %idx.shl = shl i32 %idx.in, 2 + %idx = or i32 %idx.shl, 1 + %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %idx + store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/indirect-addressing-undef.mir b/test/CodeGen/AMDGPU/indirect-addressing-undef.mir new file mode 100644 index 000000000000..7cd35d41f30c --- /dev/null +++ b/test/CodeGen/AMDGPU/indirect-addressing-undef.mir @@ -0,0 +1,327 @@ +# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-lower-control-flow -o - %s | FileCheck %s +# Getting an undef that is specifically a VGPR is tricky from IR + +# CHECK-LABEL: name: extract_undef_offset_vgpr{{$}} +# CHECK: bb.1: +# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%) +# CHECK: liveins: %vgpr0_vgpr1_vgpr2_vgpr3{{$}} + +# CHECK: V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec +# CHECK: %vgpr0 = V_MOVRELS_B32_e32 %vgpr0, implicit %m0, implicit %exec, implicit %vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_CBRANCH_EXECNZ %bb.1, implicit %exec + +# CHECK: bb.2: +# CHECK: liveins: %sgpr6_sgpr7, %sgpr4_sgpr5_sgpr6_sgpr7, %sgpr4, %sgpr5, %sgpr6, %sgpr7, %sgpr4_sgpr5, %vgpr0_vgpr1_vgpr2_vgpr3, %vgpr0, %vgpr1, %vgpr2, %vgpr3, %vgpr0_vgpr1, %vgpr2_vgpr3, %vgpr0_vgpr1_vgpr2, %vgpr1_vgpr2, %vgpr1_vgpr2_vgpr3, %sgpr0_sgpr1, %sgpr0, %sgpr1{{$}} + + +--- | + target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" + + define void @extract_undef_offset_vgpr(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %value = extractelement <4 x i32> %ld, i32 undef + store i32 %value, i32 addrspace(1)* %out + ret void + } + + define void @extract_undef_neg_offset_vgpr(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + entry: + %ld = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in + %value = extractelement <4 x i32> %ld, i32 undef + store i32 %value, i32 addrspace(1)* %out + ret void + } + + define void @insert_undef_offset_vgpr(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + entry: + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %value = insertelement <4 x i32> %ld, i32 5, i32 undef + store <4 x i32> %value, <4 x i32> addrspace(1)* %out + ret void + } + + define void @insert_undef_neg_offset_vgpr(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + entry: + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %value = insertelement <4 x i32> %ld, i32 5, i32 undef + store <4 x i32> %value, <4 x i32> addrspace(1)* %out + ret void + } + + define void @insert_undef_value_offset_vgpr(<4 x i32> addrspace(1)*%out, <4 x i32> addrspace(1)* %in, i32 %idx) { + entry: + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %value = insertelement <4 x i32> %ld, i32 undef, i32 %idx + store <4 x i32> %value, <4 x i32> addrspace(1)* %out + ret void + } + +... +--- +name: extract_undef_offset_vgpr +alignment: 0 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + S_WAITCNT 127 + %vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_DWORDX4_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + S_WAITCNT 3952 + %vgpr0, dead %sgpr0_sgpr1 = SI_INDIRECT_SRC_V4 killed %vgpr0_vgpr1_vgpr2_vgpr3, undef %vgpr10, 0, implicit-def dead %exec, implicit-def dead %vcc, implicit-def dead %m0, implicit %exec + S_WAITCNT 127 + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM + +... + +# CHECK-LABEL: name: extract_undef_neg_offset_vgpr{{$}} +# CHECK: bb.1: +# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%) +# CHECK: liveins: %vgpr0_vgpr1_vgpr2_vgpr3{{$}} + +# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec +# CHECK: %m0 = S_MOV_B32 %vcc_lo +# CHECK: %m0 = S_ADD_I32 %m0, -7, implicit-def %scc +# CHECK: %vgpr0 = V_MOVRELS_B32_e32 %vgpr0, implicit %m0, implicit %exec, implicit %vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_CBRANCH_EXECNZ %bb.1, implicit %exec + +# CHECK: bb.2: +# CHECK: liveins: %sgpr6_sgpr7, %sgpr4_sgpr5_sgpr6_sgpr7, %sgpr4, %sgpr5, %sgpr6, %sgpr7, %sgpr4_sgpr5, %vgpr0_vgpr1_vgpr2_vgpr3, %vgpr0, %vgpr1, %vgpr2, %vgpr3, %vgpr0_vgpr1, %vgpr2_vgpr3, %vgpr0_vgpr1_vgpr2, %vgpr1_vgpr2, %vgpr1_vgpr2_vgpr3, %sgpr0_sgpr1, %sgpr0, %sgpr1 + +name: extract_undef_neg_offset_vgpr +alignment: 0 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11 + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + S_WAITCNT 127 + %vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_DWORDX4_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 + S_WAITCNT 3952 + %vgpr0, dead %sgpr0_sgpr1 = SI_INDIRECT_SRC_V4 killed %vgpr0_vgpr1_vgpr2_vgpr3, undef %vgpr10, -7, implicit-def dead %exec, implicit-def dead %vcc, implicit-def dead %m0, implicit %exec + S_WAITCNT 127 + BUFFER_STORE_DWORD_OFFSET killed %vgpr0, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec + S_ENDPGM + +... + +# CHECK-LABEL: name: insert_undef_offset_vgpr{{$}} +# CHECK: bb.1: +# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%) +# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}} + +# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec +# CHECK: %m0 = S_MOV_B32 %vcc_lo +# CHECK: %vgpr0 = V_MOVRELD_B32_e32 %vgpr4, implicit %m0, implicit %exec, implicit %vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_CBRANCH_EXECNZ %bb.1, implicit %exec + +# CHECK: bb.2: +# CHECK: liveins: %sgpr6_sgpr7, %sgpr7, %sgpr4_sgpr5, %sgpr5, %sgpr4_sgpr5_sgpr6_sgpr7, %sgpr6, %sgpr4, %vgpr0_vgpr1_vgpr2_vgpr3, %vgpr0, %vgpr1, %vgpr2, %vgpr3, %vgpr0_vgpr1, %vgpr2_vgpr3, %vgpr0_vgpr1_vgpr2, %vgpr1_vgpr2, %vgpr1_vgpr2_vgpr3, %vgpr4, %sgpr0_sgpr1, %sgpr0, %sgpr1 + +name: insert_undef_offset_vgpr +alignment: 0 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr4 = V_MOV_B32_e32 5, implicit %exec + S_WAITCNT 127 + %vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_DWORDX4_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (load 16 from %ir.in) + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + S_WAITCNT 3952 + %vgpr0_vgpr1_vgpr2_vgpr3, dead %sgpr0_sgpr1 = SI_INDIRECT_DST_V4 %vgpr0_vgpr1_vgpr2_vgpr3, undef %vgpr10, 0, killed %vgpr4, implicit-def dead %exec, implicit-def dead %vcc, implicit-def dead %m0, implicit %exec + S_WAITCNT 127 + BUFFER_STORE_DWORDX4_OFFSET killed %vgpr0_vgpr1_vgpr2_vgpr3, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (store 16 into %ir.out) + S_ENDPGM + +... + +# CHECK-LABEL: name: insert_undef_neg_offset_vgpr{{$}} +# CHECK: bb.1: +# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%) +# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}} + +# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec +# CHECK: %m0 = S_MOV_B32 %vcc_lo +# CHECK: %m0 = S_ADD_I32 %m0, -7, implicit-def %scc +# CHECK: %vgpr0 = V_MOVRELD_B32_e32 %vgpr4, implicit %m0, implicit %exec, implicit %vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_CBRANCH_EXECNZ %bb.1, implicit %exec + +# CHECK: bb.2: +# CHECK: liveins: %sgpr6_sgpr7, %sgpr7, %sgpr4_sgpr5, %sgpr5, %sgpr4_sgpr5_sgpr6_sgpr7, %sgpr6, %sgpr4, %vgpr0_vgpr1_vgpr2_vgpr3, %vgpr0, %vgpr1, %vgpr2, %vgpr3, %vgpr0_vgpr1, %vgpr2_vgpr3, %vgpr0_vgpr1_vgpr2, %vgpr1_vgpr2, %vgpr1_vgpr2_vgpr3, %vgpr4, %sgpr0_sgpr1, %sgpr0, %sgpr1{{$}} + +name: insert_undef_neg_offset_vgpr +alignment: 0 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr4 = V_MOV_B32_e32 5, implicit %exec + S_WAITCNT 127 + %vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_DWORDX4_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (load 16 from %ir.in) + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + S_WAITCNT 3952 + %vgpr0_vgpr1_vgpr2_vgpr3, dead %sgpr0_sgpr1 = SI_INDIRECT_DST_V4 %vgpr0_vgpr1_vgpr2_vgpr3, undef %vgpr10, -7, killed %vgpr4, implicit-def dead %exec, implicit-def dead %vcc, implicit-def dead %m0, implicit %exec + S_WAITCNT 127 + BUFFER_STORE_DWORDX4_OFFSET killed %vgpr0_vgpr1_vgpr2_vgpr3, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (store 16 into %ir.out) + S_ENDPGM + +... + +# CHECK-LABEL: insert_undef_value_offset_vgpr{{$}} +# CHECK: bb.1: +# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%) +# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}} + +# CHECK: %vcc_lo = V_READFIRSTLANE_B32 %vgpr4, implicit %exec +# CHECK: %m0 = S_MOV_B32 %vcc_lo +# CHECK: %vgpr0 = V_MOVRELD_B32_e32 undef %vgpr10, implicit %m0, implicit %exec, implicit %vgpr0_vgpr1_vgpr2_vgpr3 +# CHECK: S_CBRANCH_EXECNZ %bb.1, implicit %exec + +# CHECK: bb.2: +# CHECK: liveins: %sgpr6_sgpr7, %sgpr7, %sgpr4_sgpr5, %sgpr5, %sgpr4_sgpr5_sgpr6_sgpr7, %sgpr6, %sgpr4, %vgpr0_vgpr1_vgpr2_vgpr3, %vgpr0, %vgpr1, %vgpr2, %vgpr3, %vgpr0_vgpr1, %vgpr2_vgpr3, %vgpr0_vgpr1_vgpr2, %vgpr1_vgpr2, %vgpr1_vgpr2_vgpr3, %vgpr4, %sgpr0_sgpr1, %sgpr0, %sgpr1{{$}} + +name: insert_undef_value_offset_vgpr +alignment: 0 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: true +liveins: + - { reg: '%sgpr0_sgpr1' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %sgpr0_sgpr1 + + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 11 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + %sgpr7 = S_MOV_B32 61440 + %sgpr6 = S_MOV_B32 -1 + %vgpr4 = V_MOV_B32_e32 2, implicit %exec + S_WAITCNT 127 + %vgpr0_vgpr1_vgpr2_vgpr3 = BUFFER_LOAD_DWORDX4_OFFSET %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (load 16 from %ir.in) + %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM killed %sgpr0_sgpr1, 9 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`) + S_WAITCNT 3952 + %vgpr0_vgpr1_vgpr2_vgpr3, dead %sgpr0_sgpr1 = SI_INDIRECT_DST_V4 %vgpr0_vgpr1_vgpr2_vgpr3, killed %vgpr4, 0, undef %vgpr10, implicit-def dead %exec, implicit-def dead %vcc, implicit-def dead %m0, implicit %exec + S_WAITCNT 127 + BUFFER_STORE_DWORDX4_OFFSET killed %vgpr0_vgpr1_vgpr2_vgpr3, killed %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (store 16 into %ir.out) + S_ENDPGM + +... diff --git a/test/CodeGen/AMDGPU/indirect-private-64.ll b/test/CodeGen/AMDGPU/indirect-private-64.ll index 2a3b29f54fa9..1f851f9de535 100644 --- a/test/CodeGen/AMDGPU/indirect-private-64.ll +++ b/test/CodeGen/AMDGPU/indirect-private-64.ll @@ -1,24 +1,31 @@ -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s +; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA16 -check-prefix=SI %s +; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA4 -check-prefix=SI %s +; RUN: llc -march=amdgcn -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=CI-ALLOCA16 -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=CI-PROMOTE -check-prefix=SI %s - -declare void @llvm.AMDGPU.barrier.local() convergent nounwind +declare void @llvm.amdgcn.s.barrier() #0 ; SI-LABEL: {{^}}private_access_f64_alloca: -; SI-ALLOCA: buffer_store_dwordx2 -; SI-ALLOCA: buffer_load_dwordx2 +; SI-ALLOCA16: buffer_store_dwordx2 +; SI-ALLOCA16: buffer_load_dwordx2 + +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_read_b64 -define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) nounwind { +; CI-PROMOTE: ds_write_b64 +; CI-PROMOTE: ds_read_b64 +define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 { %val = load double, double addrspace(1)* %in, align 8 - %array = alloca double, i32 16, align 8 - %ptr = getelementptr double, double* %array, i32 %b + %array = alloca [16 x double], align 8 + %ptr = getelementptr inbounds [16 x double], [16 x double]* %array, i32 0, i32 %b store double %val, double* %ptr, align 8 - call void @llvm.AMDGPU.barrier.local() convergent nounwind + call void @llvm.amdgcn.s.barrier() %result = load double, double* %ptr, align 8 store double %result, double addrspace(1)* %out, align 8 ret void @@ -26,19 +33,30 @@ define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double ; SI-LABEL: {{^}}private_access_v2f64_alloca: -; SI-ALLOCA: buffer_store_dwordx4 -; SI-ALLOCA: buffer_load_dwordx4 +; SI-ALLOCA16: buffer_store_dwordx4 +; SI-ALLOCA16: buffer_load_dwordx4 + +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64 -define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) nounwind { +; CI-PROMOTE: ds_write2_b64 +; CI-PROMOTE: ds_read2_b64 +define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 { %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16 - %array = alloca <2 x double>, i32 16, align 16 - %ptr = getelementptr <2 x double>, <2 x double>* %array, i32 %b + %array = alloca [8 x <2 x double>], align 16 + %ptr = getelementptr inbounds [8 x <2 x double>], [8 x <2 x double>]* %array, i32 0, i32 %b store <2 x double> %val, <2 x double>* %ptr, align 16 - call void @llvm.AMDGPU.barrier.local() convergent nounwind + call void @llvm.amdgcn.s.barrier() %result = load <2 x double>, <2 x double>* %ptr, align 16 store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16 ret void @@ -46,17 +64,25 @@ define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out ; SI-LABEL: {{^}}private_access_i64_alloca: -; SI-ALLOCA: buffer_store_dwordx2 -; SI-ALLOCA: buffer_load_dwordx2 +; SI-ALLOCA16: buffer_store_dwordx2 +; SI-ALLOCA16: buffer_load_dwordx2 + +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v + ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_read_b64 -define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) nounwind { +; CI-PROMOTE: ds_write_b64 +; CI-PROMOTE: ds_read_b64 +define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 { %val = load i64, i64 addrspace(1)* %in, align 8 - %array = alloca i64, i32 16, align 8 - %ptr = getelementptr i64, i64* %array, i32 %b + %array = alloca [8 x i64], align 8 + %ptr = getelementptr inbounds [8 x i64], [8 x i64]* %array, i32 0, i32 %b store i64 %val, i64* %ptr, align 8 - call void @llvm.AMDGPU.barrier.local() convergent nounwind + call void @llvm.amdgcn.s.barrier() %result = load i64, i64* %ptr, align 8 store i64 %result, i64 addrspace(1)* %out, align 8 ret void @@ -64,20 +90,35 @@ define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrs ; SI-LABEL: {{^}}private_access_v2i64_alloca: -; SI-ALLOCA: buffer_store_dwordx4 -; SI-ALLOCA: buffer_load_dwordx4 +; SI-ALLOCA16: buffer_store_dwordx4 +; SI-ALLOCA16: buffer_load_dwordx4 + +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v +; SI-ALLOCA4: buffer_store_dword v + +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v +; SI-ALLOCA4: buffer_load_dword v ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64 -define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) nounwind { +; CI-PROMOTE: ds_write2_b64 +; CI-PROMOTE: ds_read2_b64 +define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 { %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16 - %array = alloca <2 x i64>, i32 16, align 16 - %ptr = getelementptr <2 x i64>, <2 x i64>* %array, i32 %b + %array = alloca [8 x <2 x i64>], align 16 + %ptr = getelementptr inbounds [8 x <2 x i64>], [8 x <2 x i64>]* %array, i32 0, i32 %b store <2 x i64> %val, <2 x i64>* %ptr, align 16 - call void @llvm.AMDGPU.barrier.local() convergent nounwind + call void @llvm.amdgcn.s.barrier() %result = load <2 x i64>, <2 x i64>* %ptr, align 16 store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16 ret void } + +attributes #0 = { convergent nounwind } +attributes #1 = { nounwind "amdgpu-max-waves-per-eu"="2" "amdgpu-max-work-group-size"="64" } diff --git a/test/CodeGen/AMDGPU/inline-asm.ll b/test/CodeGen/AMDGPU/inline-asm.ll index 9c8d3534f8ad..1f5b8be15e2e 100644 --- a/test/CodeGen/AMDGPU/inline-asm.ll +++ b/test/CodeGen/AMDGPU/inline-asm.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s -; CHECK: {{^}}inline_asm: +; CHECK-LABEL: {{^}}inline_asm: ; CHECK: s_endpgm ; CHECK: s_endpgm define void @inline_asm(i32 addrspace(1)* %out) { @@ -11,13 +11,175 @@ entry: ret void } -; CHECK: {{^}}inline_asm_shader: +; CHECK-LABEL: {{^}}inline_asm_shader: ; CHECK: s_endpgm ; CHECK: s_endpgm -define void @inline_asm_shader() #0 { +define amdgpu_ps void @inline_asm_shader() { entry: call void asm sideeffect "s_endpgm", ""() ret void } -attributes #0 = { "ShaderType"="0" } + +; CHECK: {{^}}branch_on_asm: +; Make sure inline assembly is treted as divergent. +; CHECK: s_mov_b32 s{{[0-9]+}}, 0 +; CHECK: s_and_saveexec_b64 +define void @branch_on_asm(i32 addrspace(1)* %out) { + %zero = call i32 asm "s_mov_b32 $0, 0", "=s"() + %cmp = icmp eq i32 %zero, 0 + br i1 %cmp, label %if, label %endif + +if: + store i32 0, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + +; CHECK-LABEL: {{^}}v_cmp_asm: +; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} +; CHECK: v_cmp_ne_i32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]] +; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]] +; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]] +; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} +define void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { + %sgpr = tail call i64 asm "v_cmp_ne_i32_e64 $0, 0, $1", "=s,v"(i32 %in) + store i64 %sgpr, i64 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm: +; CHECK: codeLenInByte = 12 +define void @code_size_inline_asm(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "v_nop_e64", ""() + ret void +} + +; All inlineasm instructions are assumed to be the maximum size +; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst: +; CHECK: codeLenInByte = 12 +define void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "v_nop_e32", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst: +; CHECK: codeLenInByte = 20 +define void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect " + v_nop_e64 + v_nop_e64 + ", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline: +; CHECK: codeLenInByte = 20 +define void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect " + v_nop_e64 + + v_nop_e64 + ", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; comment", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect " +; comment", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; comment +", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; first comment ; second comment", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace: +; CHECK: codeLenInByte = 4 +define void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; first comment;second comment", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0: +; CHECK: codeLenInByte = 20 +define void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; comment + v_nop_e64 ; inline comment +; separate comment + v_nop_e64 + + ; trailing comment + ; extra comment + ", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1: +; CHECK: codeLenInByte = 20 +define void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "v_nop_e64 ; inline comment +; separate comment + v_nop_e64 + + ; trailing comment + ; extra comment + ", ""() + ret void +} + +; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands: +; CHECK: codeLenInByte = 20 +define void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) { +entry: + call void asm sideeffect "; comment + v_add_i32_e32 v0, vcc, v1, v2 ; inline comment +; separate comment + v_bfrev_b32_e32 v0, 1 + + ; trailing comment + ; extra comment + ", ""() + ret void +} diff --git a/test/CodeGen/AMDGPU/input-mods.ll b/test/CodeGen/AMDGPU/input-mods.ll index 1c4d285cbcb1..720790df7e16 100644 --- a/test/CodeGen/AMDGPU/input-mods.ll +++ b/test/CodeGen/AMDGPU/input-mods.ll @@ -9,18 +9,16 @@ ;CM: EXP_IEEE T{{[0-9]+}}.Z (MASKED), -|T{{[0-9]+}}.X| ;CM: EXP_IEEE * T{{[0-9]+}}.W (MASKED), -|T{{[0-9]+}}.X| -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = call float @llvm.fabs.f32(float %r0) %r2 = fsub float -0.000000e+00, %r1 %r3 = call float @llvm.exp2.f32(float %r2) %vec = insertelement <4 x float> undef, float %r3, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @llvm.exp2.f32(float) readnone declare float @llvm.fabs.f32(float) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/insert_vector_elt.ll b/test/CodeGen/AMDGPU/insert_vector_elt.ll index 7f9579e59782..367e7f734556 100644 --- a/test/CodeGen/AMDGPU/insert_vector_elt.ll +++ b/test/CodeGen/AMDGPU/insert_vector_elt.ll @@ -1,5 +1,5 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=+max-private-element-size-16 < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; FIXME: Broken on evergreen ; FIXME: For some reason the 8 and 16 vectors are being stored as @@ -9,168 +9,296 @@ ; FIXME: Why is the constant moved into the intermediate register and ; not just directly into the vector component? -; SI-LABEL: {{^}}insertelement_v4f32_0: -; s_load_dwordx4 s{{[}}[[LOW_REG:[0-9]+]]: -; v_mov_b32_e32 -; v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 5.000000e+00 -; v_mov_b32_e32 v[[LOW_REG]], [[CONSTREG]] -; buffer_store_dwordx4 v{{[}}[[LOW_REG]]: +; GCN-LABEL: {{^}}insertelement_v4f32_0: +; GCN: s_load_dwordx4 +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 0x40a00000 +; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] +; GCN: buffer_store_dwordx4 v{{\[}}[[LOW_REG]]: define void @insertelement_v4f32_0(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 0 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}insertelement_v4f32_1: +; GCN-LABEL: {{^}}insertelement_v4f32_1: define void @insertelement_v4f32_1(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 1 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}insertelement_v4f32_2: +; GCN-LABEL: {{^}}insertelement_v4f32_2: define void @insertelement_v4f32_2(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 2 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}insertelement_v4f32_3: +; GCN-LABEL: {{^}}insertelement_v4f32_3: define void @insertelement_v4f32_3(<4 x float> addrspace(1)* %out, <4 x float> %a) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 3 store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}insertelement_v4i32_0: +; GCN-LABEL: {{^}}insertelement_v4i32_0: define void @insertelement_v4i32_0(<4 x i32> addrspace(1)* %out, <4 x i32> %a) nounwind { %vecins = insertelement <4 x i32> %a, i32 999, i32 0 store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v2f32: -; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 -; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] -; SI: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: +; GCN-LABEL: {{^}}insertelement_v3f32_1: +define void @insertelement_v3f32_1(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { + %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 1 + store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 + ret void +} + +; GCN-LABEL: {{^}}insertelement_v3f32_2: +define void @insertelement_v3f32_2(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { + %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 2 + store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 + ret void +} + +; GCN-LABEL: {{^}}insertelement_v3f32_3: +define void @insertelement_v3f32_3(<3 x float> addrspace(1)* %out, <3 x float> %a) nounwind { + %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 3 + store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 + ret void +} + +; GCN-LABEL: {{^}}insertelement_to_sgpr: +; GCN-NOT: v_readfirstlane +define amdgpu_ps <4 x float> @insertelement_to_sgpr() nounwind { + %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef + %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 + %tmp2 = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> %tmp1, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + ret <4 x float> %tmp2 +} + +; GCN-LABEL: {{^}}dynamic_insertelement_v2f32: +; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 +; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; GCN: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: define void @dynamic_insertelement_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, i32 %b) nounwind { %vecins = insertelement <2 x float> %a, float 5.000000e+00, i32 %b store <2 x float> %vecins, <2 x float> addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v4f32: -; SI: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 -; SI: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] -; SI: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: +; GCN-LABEL: {{^}}dynamic_insertelement_v3f32: +; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 +; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: +; GCN-DAG: buffer_store_dword v +define void @dynamic_insertelement_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %a, i32 %b) nounwind { + %vecins = insertelement <3 x float> %a, float 5.000000e+00, i32 %b + store <3 x float> %vecins, <3 x float> addrspace(1)* %out, align 16 + ret void +} + +; GCN-LABEL: {{^}}dynamic_insertelement_v4f32: +; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 0x40a00000 +; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; GCN: buffer_store_dwordx4 {{v\[}}[[LOW_RESULT_REG]]: define void @dynamic_insertelement_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, i32 %b) nounwind { %vecins = insertelement <4 x float> %a, float 5.000000e+00, i32 %b store <4 x float> %vecins, <4 x float> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v8f32: -; SI: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v8f32: +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 define void @dynamic_insertelement_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %a, i32 %b) nounwind { %vecins = insertelement <8 x float> %a, float 5.000000e+00, i32 %b store <8 x float> %vecins, <8 x float> addrspace(1)* %out, align 32 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v16f32: -; SI: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v16f32: +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, v{{[0-9]+}} +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 define void @dynamic_insertelement_v16f32(<16 x float> addrspace(1)* %out, <16 x float> %a, i32 %b) nounwind { %vecins = insertelement <16 x float> %a, float 5.000000e+00, i32 %b store <16 x float> %vecins, <16 x float> addrspace(1)* %out, align 64 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v2i32: -; SI: buffer_store_dwordx2 +; GCN-LABEL: {{^}}dynamic_insertelement_v2i32: +; GCN: v_movreld_b32 +; GCN: buffer_store_dwordx2 define void @dynamic_insertelement_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, i32 %b) nounwind { %vecins = insertelement <2 x i32> %a, i32 5, i32 %b store <2 x i32> %vecins, <2 x i32> addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v4i32: -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v3i32: +; GCN: v_mov_b32_e32 [[CONST:v[0-9]+]], 5 +; GCN: v_movreld_b32_e32 v[[LOW_RESULT_REG:[0-9]+]], [[CONST]] +; GCN-DAG: buffer_store_dwordx2 {{v\[}}[[LOW_RESULT_REG]]: +; GCN-DAG: buffer_store_dword v +define void @dynamic_insertelement_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, i32 %b) nounwind { + %vecins = insertelement <3 x i32> %a, i32 5, i32 %b + store <3 x i32> %vecins, <3 x i32> addrspace(1)* %out, align 16 + ret void +} + +; GCN-LABEL: {{^}}dynamic_insertelement_v4i32: +; GCN: v_movreld_b32 +; GCN: buffer_store_dwordx4 define void @dynamic_insertelement_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, i32 %b) nounwind { %vecins = insertelement <4 x i32> %a, i32 5, i32 %b store <4 x i32> %vecins, <4 x i32> addrspace(1)* %out, align 16 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v8i32: -; FIXMESI: buffer_store_dwordx4 -; FIXMESI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v8i32: +; GCN: v_movreld_b32 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 define void @dynamic_insertelement_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, i32 %b) nounwind { %vecins = insertelement <8 x i32> %a, i32 5, i32 %b store <8 x i32> %vecins, <8 x i32> addrspace(1)* %out, align 32 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v16i32: -; FIXMESI: buffer_store_dwordx4 -; FIXMESI: buffer_store_dwordx4 -; FIXMESI: buffer_store_dwordx4 -; FIXMESI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v16i32: +; GCN: v_movreld_b32 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 define void @dynamic_insertelement_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> %a, i32 %b) nounwind { %vecins = insertelement <16 x i32> %a, i32 5, i32 %b store <16 x i32> %vecins, <16 x i32> addrspace(1)* %out, align 64 ret void } - -; SI-LABEL: {{^}}dynamic_insertelement_v2i16: -; FIXMESI: buffer_store_dwordx2 +; GCN-LABEL: {{^}}dynamic_insertelement_v2i16: define void @dynamic_insertelement_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %a, i32 %b) nounwind { %vecins = insertelement <2 x i16> %a, i16 5, i32 %b store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v4i16: -; FIXMESI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v3i16: +define void @dynamic_insertelement_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> %a, i32 %b) nounwind { + %vecins = insertelement <3 x i16> %a, i16 5, i32 %b + store <3 x i16> %vecins, <3 x i16> addrspace(1)* %out, align 8 + ret void +} + +; GCN-LABEL: {{^}}dynamic_insertelement_v4i16: +; GCN: buffer_load_ushort v{{[0-9]+}}, off +; GCN: buffer_load_ushort v{{[0-9]+}}, off +; GCN: buffer_load_ushort v{{[0-9]+}}, off +; GCN: buffer_load_ushort v{{[0-9]+}}, off + +; GCN-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:6 +; GCN-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:4 +; GCN-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:2 +; GCN-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} +; GCN: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort + +; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off define void @dynamic_insertelement_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, i32 %b) nounwind { %vecins = insertelement <4 x i16> %a, i16 5, i32 %b - store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out, align 16 + store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out, align 8 ret void } +; GCN-LABEL: {{^}}dynamic_insertelement_v2i8: +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off + +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:1 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} -; SI-LABEL: {{^}}dynamic_insertelement_v2i8: -; FIXMESI: BUFFER_STORE_USHORT +; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte + +; GCN: buffer_store_short v{{[0-9]+}}, off define void @dynamic_insertelement_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> %a, i32 %b) nounwind { %vecins = insertelement <2 x i8> %a, i8 5, i32 %b store <2 x i8> %vecins, <2 x i8> addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v4i8: -; FIXMESI: buffer_store_dword +; GCN-LABEL: {{^}}dynamic_insertelement_v3i8: +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off + +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:2 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:1 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte + +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, off +; GCN-DAG: buffer_store_short v{{[0-9]+}}, off +define void @dynamic_insertelement_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> %a, i32 %b) nounwind { + %vecins = insertelement <3 x i8> %a, i8 5, i32 %b + store <3 x i8> %vecins, <3 x i8> addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}dynamic_insertelement_v4i8: +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off +; GCN: buffer_load_ubyte v{{[0-9]+}}, off + +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:3 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:2 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:1 +; GCN-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} + +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte +; GCN: buffer_load_ubyte + +; GCN: buffer_store_dword v{{[0-9]+}}, off define void @dynamic_insertelement_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, i32 %b) nounwind { %vecins = insertelement <4 x i8> %a, i8 5, i32 %b - store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 16 + store <4 x i8> %vecins, <4 x i8> addrspace(1)* %out, align 4 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v8i8: -; FIXMESI: buffer_store_dwordx2 +; GCN-LABEL: {{^}}dynamic_insertelement_v8i8: define void @dynamic_insertelement_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> %a, i32 %b) nounwind { %vecins = insertelement <8 x i8> %a, i8 5, i32 %b - store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 16 + store <8 x i8> %vecins, <8 x i8> addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v16i8: -; FIXMESI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}dynamic_insertelement_v16i8: define void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> %a, i32 %b) nounwind { %vecins = insertelement <16 x i8> %a, i8 5, i32 %b store <16 x i8> %vecins, <16 x i8> addrspace(1)* %out, align 16 @@ -179,7 +307,7 @@ define void @dynamic_insertelement_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> ; This test requires handling INSERT_SUBREG in SIFixSGPRCopies. Check that ; the compiler doesn't crash. -; SI-LABEL: {{^}}insert_split_bb: +; GCN-LABEL: {{^}}insert_split_bb: define void @insert_split_bb(<2 x i32> addrspace(1)* %out, i32 addrspace(1)* %in, i32 %a, i32 %b) { entry: %0 = insertelement <2 x i32> undef, i32 %a, i32 0 @@ -203,30 +331,30 @@ endif: ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v2f64: -; SI: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}} -; SI-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} -; SI-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 0{{$}} +; GCN-LABEL: {{^}}dynamic_insertelement_v2f64: +; GCN: s_load_dword [[IDX:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0x11|0x44}}{{$}} +; GCN-DAG: s_lshl_b32 [[SCALEDIDX:s[0-9]+]], [[IDX]], 1{{$}} +; GCN-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 0{{$}} -; SI: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} -; SI: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} -; SI: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} -; SI: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} +; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} -; SI: s_mov_b32 m0, [[SCALEDIDX]] -; SI: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT0]] +; GCN: s_mov_b32 m0, [[SCALEDIDX]] +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT0]] ; Increment to next element. ; FIXME: Should be able to manipulate m0 directly instead of add and ; copy. -; SI: s_or_b32 [[IDX1:s[0-9]+]], [[SCALEDIDX]], 1 -; SI-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 -; SI-DAG: s_mov_b32 m0, [[IDX1]] -; SI: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] +; FIXME: Should avoid resetting m0 to same value +; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0x40200000 +; GCN-DAG: s_mov_b32 m0, [[SCALEDIDX]] +; GCN: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] -; SI: buffer_store_dwordx4 -; SI: s_endpgm +; GCN: buffer_store_dwordx4 +; GCN: s_endpgm define void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %a, i32 %b) nounwind { %vecins = insertelement <2 x double> %a, double 8.0, i32 %b store <2 x double> %vecins, <2 x double> addrspace(1)* %out, align 16 @@ -234,44 +362,52 @@ define void @dynamic_insertelement_v2f64(<2 x double> addrspace(1)* %out, <2 x d } ; FIXME: Inline immediate should be folded into v_movreld_b32. -; SI-LABEL: {{^}}dynamic_insertelement_v2i64: +; GCN-LABEL: {{^}}dynamic_insertelement_v2i64: -; SI-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 5{{$}} -; SI-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0{{$}} +; GCN-DAG: v_mov_b32_e32 [[ELT0:v[0-9]+]], 5{{$}} +; GCN-DAG: v_mov_b32_e32 [[ELT1:v[0-9]+]], 0{{$}} -; SI-DAG: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT0]] -; SI-DAG: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] +; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT0]] +; GCN-DAG: v_movreld_b32_e32 v{{[0-9]+}}, [[ELT1]] -; SI: buffer_store_dwordx4 -; SI: s_endpgm +; GCN: buffer_store_dwordx4 +; GCN: s_endpgm define void @dynamic_insertelement_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> %a, i32 %b) nounwind { %vecins = insertelement <2 x i64> %a, i64 5, i32 %b store <2 x i64> %vecins, <2 x i64> addrspace(1)* %out, align 8 ret void } +; GCN-LABEL: {{^}}dynamic_insertelement_v3i64: +define void @dynamic_insertelement_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %a, i32 %b) nounwind { + %vecins = insertelement <3 x i64> %a, i64 5, i32 %b + store <3 x i64> %vecins, <3 x i64> addrspace(1)* %out, align 32 + ret void +} + ; FIXME: Should be able to do without stack access. The used stack ; space is also 2x what should be required. -; SI-LABEL: {{^}}dynamic_insertelement_v4f64: -; SI: SCRATCH_RSRC_DWORD +; GCN-LABEL: {{^}}dynamic_insertelement_v4f64: +; GCN: SCRATCH_RSRC_DWORD ; Stack store -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} + +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} ; Write element -; SI: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; Stack reload -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; Store result -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: s_endpgm -; SI: ScratchSize: 64 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: s_endpgm +; GCN: ScratchSize: 64 define void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %a, i32 %b) nounwind { %vecins = insertelement <4 x double> %a, double 8.0, i32 %b @@ -279,29 +415,31 @@ define void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)* %out, <4 x d ret void } -; SI-LABEL: {{^}}dynamic_insertelement_v8f64: -; SI: SCRATCH_RSRC_DWORD +; GCN-LABEL: {{^}}dynamic_insertelement_v8f64: +; GCN: SCRATCH_RSRC_DWORD -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:32{{$}} -; SI-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:48{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:32{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:48{{$}} -; SI: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} -; SI-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:16{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 -; SI: s_endpgm -; SI: ScratchSize: 128 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: buffer_store_dwordx4 +; GCN: s_endpgm +; GCN: ScratchSize: 128 define void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) nounwind { %vecins = insertelement <8 x double> %a, double 8.0, i32 %b store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16 ret void } + +declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) nounwind readnone diff --git a/test/CodeGen/AMDGPU/invalid-addrspacecast.ll b/test/CodeGen/AMDGPU/invalid-addrspacecast.ll new file mode 100644 index 000000000000..c29434f5eca2 --- /dev/null +++ b/test/CodeGen/AMDGPU/invalid-addrspacecast.ll @@ -0,0 +1,8 @@ +; RUN: not llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca < %s 2>&1 | FileCheck -check-prefix=ERROR %s + +; ERROR: error: :0:0: in function use_group_to_global_addrspacecast void (i32 addrspace(3)*): invalid addrspacecast +define void @use_group_to_global_addrspacecast(i32 addrspace(3)* %ptr) { + %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(1)* + store volatile i32 0, i32 addrspace(1)* %stof + ret void +} diff --git a/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll b/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll index 2a01a621fc42..347170f79e32 100644 --- a/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll +++ b/test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll @@ -7,8 +7,8 @@ ; from constant/invariant memory. ; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_global_pointer_load: -; GCN: buffer_load_dwordx2 [[PTR:v\[[0-9]+:[0-9]+\]]], -; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b +; GCN-DAG: buffer_load_dwordx2 [[PTR:v\[[0-9]+:[0-9]+\]]], +; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b ; GCN: buffer_store_dword [[K]], [[PTR]] define void @test_merge_store_constant_i16_invariant_global_pointer_load(i16 addrspace(1)* addrspace(1)* dereferenceable(4096) nonnull %in) #0 { %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(1)* %in, !invariant.load !0 @@ -21,7 +21,7 @@ define void @test_merge_store_constant_i16_invariant_global_pointer_load(i16 add ; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_constant_pointer_load: ; GCN: s_load_dwordx2 s{{\[}}[[SPTR_LO:[0-9]+]]:[[SPTR_HI:[0-9]+]]{{\]}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b -; GCN: buffer_store_dword [[K]], s{{\[}}[[SPTR_LO]]: +; GCN: buffer_store_dword [[K]], off, s{{\[}}[[SPTR_LO]]: define void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 addrspace(1)* addrspace(2)* dereferenceable(4096) nonnull %in) #0 { %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(2)* %in, !invariant.load !0 %ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1 @@ -32,4 +32,4 @@ define void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 a !0 = !{} -attributes #0 = { nounwind } \ No newline at end of file +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/jump-address.ll b/test/CodeGen/AMDGPU/jump-address.ll index f55912e37401..9fde31f922cd 100644 --- a/test/CodeGen/AMDGPU/jump-address.ll +++ b/test/CodeGen/AMDGPU/jump-address.ll @@ -4,7 +4,7 @@ ; CHECK: EXPORT ; CHECK-NOT: EXPORT -define void @main() #0 { +define amdgpu_ps void @main() { main_body: %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) %1 = extractelement <4 x float> %0, i32 0 @@ -36,7 +36,7 @@ ENDIF: ; preds = %IF13, %ELSE, %main_ %17 = insertelement <4 x float> %16, float %temp1.0, i32 1 %18 = insertelement <4 x float> %17, float %temp2.0, i32 2 %19 = insertelement <4 x float> %18, float %temp3.0, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %19, i32 0, i32 0) ret void IF13: ; preds = %ELSE @@ -47,6 +47,4 @@ IF13: ; preds = %ELSE br label %ENDIF } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/kcache-fold.ll b/test/CodeGen/AMDGPU/kcache-fold.ll index 7e2291cfdc35..43448fbd7b33 100644 --- a/test/CodeGen/AMDGPU/kcache-fold.ll +++ b/test/CodeGen/AMDGPU/kcache-fold.ll @@ -36,15 +36,15 @@ main_body: %29 = extractelement <4 x float> %28, i32 3 %30 = fcmp ogt float %25, 0.000000e+00 %31 = select i1 %30, float %27, float %29 - %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) - %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) - %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00) - %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00) + %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00) + %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00) + %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00) + %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00) %36 = insertelement <4 x float> undef, float %32, i32 0 %37 = insertelement <4 x float> %36, float %33, i32 1 %38 = insertelement <4 x float> %37, float %34, i32 2 %39 = insertelement <4 x float> %38, float %35, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %39, i32 0, i32 0) ret void } @@ -84,17 +84,17 @@ main_body: %29 = extractelement <4 x float> %28, i32 2 %30 = fcmp ogt float %25, 0.000000e+00 %31 = select i1 %30, float %27, float %29 - %32 = call float @llvm.AMDIL.clamp.(float %7, float 0.000000e+00, float 1.000000e+00) - %33 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) - %34 = call float @llvm.AMDIL.clamp.(float %23, float 0.000000e+00, float 1.000000e+00) - %35 = call float @llvm.AMDIL.clamp.(float %31, float 0.000000e+00, float 1.000000e+00) + %32 = call float @llvm.AMDGPU.clamp.f32(float %7, float 0.000000e+00, float 1.000000e+00) + %33 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00) + %34 = call float @llvm.AMDGPU.clamp.f32(float %23, float 0.000000e+00, float 1.000000e+00) + %35 = call float @llvm.AMDGPU.clamp.f32(float %31, float 0.000000e+00, float 1.000000e+00) %36 = insertelement <4 x float> undef, float %32, i32 0 %37 = insertelement <4 x float> %36, float %33, i32 1 %38 = insertelement <4 x float> %37, float %34, i32 2 %39 = insertelement <4 x float> %38, float %35, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %39, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %39, i32 0, i32 0) ret void } -declare float @llvm.AMDIL.clamp.(float, float, float) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare float @llvm.AMDGPU.clamp.f32(float, float, float) readnone +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll b/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll new file mode 100644 index 000000000000..21c92dbc9098 --- /dev/null +++ b/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll @@ -0,0 +1,44 @@ +; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; Test that the alignment of kernel arguments does not impact the +; alignment of the stack + +; CHECK-LABEL: {{^}}no_args: +; CHECK: ScratchSize: 8{{$}} +define void @no_args() { + %alloca = alloca i8 + store volatile i8 0, i8* %alloca + ret void +} + +; CHECK-LABEL: {{^}}force_align32: +; CHECK: ScratchSize: 8{{$}} +define void @force_align32(<8 x i32>) { + %alloca = alloca i8 + store volatile i8 0, i8* %alloca + ret void +} + +; CHECK-LABEL: {{^}}force_align64: +; CHECK: ScratchSize: 8{{$}} +define void @force_align64(<16 x i32>) { + %alloca = alloca i8 + store volatile i8 0, i8* %alloca + ret void +} + +; CHECK-LABEL: {{^}}force_align128: +; CHECK: ScratchSize: 8{{$}} +define void @force_align128(<32 x i32>) { + %alloca = alloca i8 + store volatile i8 0, i8* %alloca + ret void +} + +; CHECK-LABEL: {{^}}force_align256: +; CHECK: ScratchSize: 8{{$}} +define void @force_align256(<64 x i32>) { + %alloca = alloca i8 + store volatile i8 0, i8* %alloca + ret void +} diff --git a/test/CodeGen/AMDGPU/kernel-args.ll b/test/CodeGen/AMDGPU/kernel-args.ll index e9d98ac89e72..7567b38e0cea 100644 --- a/test/CodeGen/AMDGPU/kernel-args.ll +++ b/test/CodeGen/AMDGPU/kernel-args.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC @@ -475,3 +475,55 @@ entry: ; store <1 x i64> %a, <1 x i64> addrspace(1)* %out, align 8 ; ret void ; } + +; FUNC-LABEL: {{^}}i1_arg: +; SI: buffer_load_ubyte +; SI: v_and_b32_e32 +; SI: buffer_store_byte +; SI: s_endpgm +define void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { + store i1 %x, i1 addrspace(1)* %out, align 1 + ret void +} + +; FUNC-LABEL: {{^}}i1_arg_zext_i32: +; SI: buffer_load_ubyte +; SI: buffer_store_dword +; SI: s_endpgm +define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { + %ext = zext i1 %x to i32 + store i32 %ext, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}i1_arg_zext_i64: +; SI: buffer_load_ubyte +; SI: buffer_store_dwordx2 +; SI: s_endpgm +define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { + %ext = zext i1 %x to i64 + store i64 %ext, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}i1_arg_sext_i32: +; SI: buffer_load_ubyte +; SI: buffer_store_dword +; SI: s_endpgm +define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { + %ext = sext i1 %x to i32 + store i32 %ext, i32addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}i1_arg_sext_i64: +; SI: buffer_load_ubyte +; SI: v_bfe_i32 +; SI: v_ashrrev_i32 +; SI: buffer_store_dwordx2 +; SI: s_endpgm +define void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { + %ext = sext i1 %x to i64 + store i64 %ext, i64 addrspace(1)* %out, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/large-alloca-compute.ll b/test/CodeGen/AMDGPU/large-alloca-compute.ll index 84380b421051..099f0639b34c 100644 --- a/test/CodeGen/AMDGPU/large-alloca-compute.ll +++ b/test/CodeGen/AMDGPU/large-alloca-compute.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s -; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s +; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s +; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s @@ -7,17 +7,19 @@ ; ALL-LABEL: {{^}}large_alloca_compute_shader: -; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 -; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 -; GCN: s_mov_b32 s10, -1 -; CI: s_mov_b32 s11, 0x80f000 -; VI: s_mov_b32 s11, 0x800000 +; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 +; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0 +; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 +; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1 +; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1 +; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000 +; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000 ; GCNHSA: .amd_kernel_code_t ; GCNHSA: compute_pgm_rsrc2_scratch_en = 1 -; GCNHSA: compute_pgm_rsrc2_user_sgpr = 6 +; GCNHSA: compute_pgm_rsrc2_user_sgpr = 8 ; GCNHSA: compute_pgm_rsrc2_tgid_x_en = 1 ; GCNHSA: compute_pgm_rsrc2_tgid_y_en = 0 ; GCNHSA: compute_pgm_rsrc2_tgid_z_en = 0 @@ -29,7 +31,7 @@ ; GCNHSA: enable_sgpr_queue_ptr = 0 ; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1 ; GCNHSA: enable_sgpr_dispatch_id = 0 -; GCNHSA: enable_sgpr_flat_scratch_init = 0 +; GCNHSA: enable_sgpr_flat_scratch_init = 1 ; GCNHSA: enable_sgpr_private_segment_size = 0 ; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0 ; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0 @@ -39,8 +41,8 @@ ; GCNHSA: .end_amd_kernel_code_t -; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen -; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s7 offen +; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen +; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen ; Scratch size = alloca size + emergency stack slot ; ALL: ; ScratchSize: 32772 diff --git a/test/CodeGen/AMDGPU/large-alloca-graphics.ll b/test/CodeGen/AMDGPU/large-alloca-graphics.ll index b6f8093313cb..fb0e15eb0cb9 100644 --- a/test/CodeGen/AMDGPU/large-alloca-graphics.ll +++ b/test/CodeGen/AMDGPU/large-alloca-graphics.ll @@ -2,17 +2,17 @@ ; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; ALL-LABEL: {{^}}large_alloca_pixel_shader: -; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 -; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 -; GCN: s_mov_b32 s10, -1 -; CI: s_mov_b32 s11, 0x80f000 -; VI: s_mov_b32 s11, 0x800000 +; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 +; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 +; GCN-DAG: s_mov_b32 s10, -1 +; CI-DAG: s_mov_b32 s11, 0xe8f000 +; VI-DAG: s_mov_b32 s11, 0xe80000 -; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen -; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen +; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen ; ALL: ; ScratchSize: 32772 -define void @large_alloca_pixel_shader(i32 %x, i32 %y) #1 { +define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 { %large = alloca [8192 x i32], align 4 %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 store volatile i32 %x, i32* %gep @@ -23,17 +23,17 @@ define void @large_alloca_pixel_shader(i32 %x, i32 %y) #1 { } ; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg: -; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 -; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 -; GCN: s_mov_b32 s10, -1 -; CI: s_mov_b32 s11, 0x80f000 -; VI: s_mov_b32 s11, 0x800000 +; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 +; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 +; GCN-DAG: s_mov_b32 s10, -1 +; CI-DAG: s_mov_b32 s11, 0xe8f000 +; VI-DAG: s_mov_b32 s11, 0xe80000 -; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen -; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s1 offen +; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen ; ALL: ; ScratchSize: 32772 -define void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #1 { +define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 { %large = alloca [8192 x i32], align 4 %gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 store volatile i32 %x, i32* %gep @@ -44,4 +44,3 @@ define void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #1 { } attributes #0 = { nounwind } -attributes #1 = { nounwind "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll b/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll new file mode 100644 index 000000000000..f661939214c0 --- /dev/null +++ b/test/CodeGen/AMDGPU/large-work-group-promote-alloca.ll @@ -0,0 +1,117 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck %s + +; CHECK: @promote_alloca_size_63.stack = internal unnamed_addr addrspace(3) global [63 x [5 x i32]] undef, align 4 + +define void @promote_alloca_size_63(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; CHECK: @promote_alloca_size_256.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4 + +define void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #1 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; CHECK: @promote_alloca_size_1600.stack = internal unnamed_addr addrspace(3) global [1600 x [5 x i32]] undef, align 4 + +define void @promote_alloca_size_1600(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #2 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; CHECK: @occupancy_0( +; CHECK: alloca [5 x i32] +define void @occupancy_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #3 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; CHECK: @occupancy_max( +; CHECK: alloca [5 x i32] +define void @occupancy_max(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #4 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +attributes #0 = { nounwind "amdgpu-max-work-group-size"="63" } +attributes #1 = { nounwind "amdgpu-max-waves-per-eu"="3" "amdgpu-max-work-group-size"="256" } +attributes #2 = { nounwind "amdgpu-max-waves-per-eu"="1" "amdgpu-max-work-group-size"="1600" } +attributes #3 = { nounwind "amdgpu-max-waves-per-eu"="0" } +attributes #4 = { nounwind "amdgpu-max-waves-per-eu"="-1" } diff --git a/test/CodeGen/AMDGPU/large-work-group-registers.ll b/test/CodeGen/AMDGPU/large-work-group-registers.ll new file mode 100644 index 000000000000..468633da56d8 --- /dev/null +++ b/test/CodeGen/AMDGPU/large-work-group-registers.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=amdgcn -mcpu=tonga -post-RA-scheduler=0 < %s | FileCheck %s + +; CHECK: NumVgprs: 64 +define void @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, [16 x <8 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, <3 x i32> inreg, <3 x i32> inreg, <3 x i32>) #0 { +main_body: + %8 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %4, i64 0, i64 8 + %9 = load <4 x i32>, <4 x i32> addrspace(2)* %8, align 16, !tbaa !0 + %10 = extractelement <3 x i32> %7, i32 0 + %11 = extractelement <3 x i32> %7, i32 1 + %12 = mul i32 %10, %11 + %bc = bitcast <3 x i32> %7 to <3 x float> + %13 = extractelement <3 x float> %bc, i32 1 + %14 = insertelement <512 x float> undef, float %13, i32 %12 + call void @llvm.amdgcn.s.barrier() + %15 = extractelement <3 x i32> %6, i32 0 + %16 = extractelement <3 x i32> %7, i32 0 + %17 = shl i32 %15, 5 + %18 = add i32 %17, %16 + %19 = shl i32 %18, 4 + %20 = extractelement <3 x i32> %7, i32 1 + %21 = shl i32 %20, 2 + %22 = sext i32 %21 to i64 + %23 = getelementptr i8, i8 addrspace(3)* null, i64 %22 + %24 = bitcast i8 addrspace(3)* %23 to i32 addrspace(3)* + %25 = load i32, i32 addrspace(3)* %24, align 4 + %26 = extractelement <512 x float> %14, i32 %25 + %27 = insertelement <4 x float> undef, float %26, i32 0 + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %27, <4 x i32> %9, i32 0, i32 %19, i1 false, i1 false) + ret void +} + +declare void @llvm.amdgcn.s.barrier() #1 + +declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #2 + +attributes #0 = { "amdgpu-max-work-group-size"="1024" } +attributes #1 = { convergent nounwind } +attributes #2 = { nounwind } + +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} diff --git a/test/CodeGen/AMDGPU/lds-alignment.ll b/test/CodeGen/AMDGPU/lds-alignment.ll new file mode 100644 index 000000000000..99334585e589 --- /dev/null +++ b/test/CodeGen/AMDGPU/lds-alignment.ll @@ -0,0 +1,268 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-prefix=FUNC %s + +@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 +@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 + +@lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8 +@lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32 + +@lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef +@lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef + +declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture readonly, i32, i32, i1) #0 +declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture readonly, i32, i32, i1) #0 + + +; HSA-LABEL: {{^}}test_no_round_size_1: +; HSA: workgroup_group_segment_byte_size = 38 +define void @test_no_round_size_1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 4, i1 false) + ret void +} + +; There are two objects, so one requires padding to to be correctly +; aligned after the other. + +; (38 -> 48) + 38 = 92 + +; I don't think it is necessary to add padding after since if there +; were to be a dynamically sized LDS kernel arg, the runtime should +; add the alignment padding if necessary alignment padding if needed. + +; HSA-LABEL: {{^}}test_round_size_2: +; HSA: workgroup_group_segment_byte_size = 86 +; HSA: group_segment_alignment = 4 +define void @test_round_size_2(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 4, i1 false) + + %lds.align16.1.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.1 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.1.bc, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.1.bc, i32 38, i32 4, i1 false) + + ret void +} + +; 38 + (10 pad) + 38 +; HSA-LABEL: {{^}}test_round_size_2_align_8: +; HSA: workgroup_group_segment_byte_size = 86 +; HSA: group_segment_alignment = 4 +define void @test_round_size_2_align_8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; HSA-LABEL: {{^}}test_round_local_lds_and_arg: +; HSA: workgroup_group_segment_byte_size = 38 +; HSA: group_segment_alignment = 4 +define void @test_round_local_lds_and_arg(i8 addrspace(1)* %out, i8 addrspace(1)* %in, i8 addrspace(3)* %lds.arg) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.arg, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.arg, i32 38, i32 4, i1 false) + ret void +} + +; HSA-LABEL: {{^}}test_round_lds_arg: +; HSA: workgroup_group_segment_byte_size = 0 +; HSA: group_segment_alignment = 4 +define void @test_round_lds_arg(i8 addrspace(1)* %out, i8 addrspace(1)* %in, i8 addrspace(3)* %lds.arg) #1 { + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.arg, i8 addrspace(1)* %in, i32 38, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.arg, i32 38, i32 4, i1 false) + ret void +} + +; FIXME: Parameter alignment not considered +; HSA-LABEL: {{^}}test_high_align_lds_arg: +; HSA: workgroup_group_segment_byte_size = 0 +; HSA: group_segment_alignment = 4 +define void @test_high_align_lds_arg(i8 addrspace(1)* %out, i8 addrspace(1)* %in, i8 addrspace(3)* align 64 %lds.arg) #1 { + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.arg, i8 addrspace(1)* %in, i32 38, i32 64, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.arg, i32 38, i32 64, i1 false) + ret void +} + +; (7 * 8) + (39 * 4) = 212 +; HSA-LABEL: {{^}}test_missing_alignment_size_2_order0: +; HSA: workgroup_group_segment_byte_size = 212 +; HSA: group_segment_alignment = 4 +define void @test_missing_alignment_size_2_order0(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.missing.align.0.bc = bitcast [39 x i32] addrspace(3)* @lds.missing.align.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.missing.align.0.bc, i8 addrspace(1)* %in, i32 160, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.missing.align.0.bc, i32 160, i32 4, i1 false) + + %lds.missing.align.1.bc = bitcast [7 x i64] addrspace(3)* @lds.missing.align.1 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.missing.align.1.bc, i8 addrspace(1)* %in, i32 56, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.missing.align.1.bc, i32 56, i32 8, i1 false) + + ret void +} + +; (39 * 4) + (4 pad) + (7 * 8) = 216 +; HSA-LABEL: {{^}}test_missing_alignment_size_2_order1: +; HSA: workgroup_group_segment_byte_size = 216 +; HSA: group_segment_alignment = 4 +define void @test_missing_alignment_size_2_order1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.missing.align.1.bc = bitcast [7 x i64] addrspace(3)* @lds.missing.align.1 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.missing.align.1.bc, i8 addrspace(1)* %in, i32 56, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.missing.align.1.bc, i32 56, i32 8, i1 false) + + %lds.missing.align.0.bc = bitcast [39 x i32] addrspace(3)* @lds.missing.align.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.missing.align.0.bc, i8 addrspace(1)* %in, i32 160, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.missing.align.0.bc, i32 160, i32 4, i1 false) + + ret void +} +; Test how the size needed for padding changes based on when the +; global is encountered during lowering. There should be a consistent +; order to minimize padding waste. +; +; The way global addresses are lowered now, this is in inverse of +; first use order which isn't great. +; +; This should be the optimal order for these globals. If sorted to +; minimize padding, the minimum possible size is: align 32, align 8, +; align 16 + + +; align 32, 16, 8 +; 38 + (10 pad) + 38 + (10 pad) + 38 = 134 +; HSA-LABEL: {{^}}test_round_size_3_order0: +; HSA: workgroup_group_segment_byte_size = 134 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order0(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; align 32, 8, 16 +; 38 (+ 2 pad) + 38 + (18 pad) + 38 = 134 +; HSA-LABEL: {{^}}test_round_size_3_order1: +; HSA: workgroup_group_segment_byte_size = 134 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; align 16, 32, 8 +; 38 + (26 pad) + 38 + (10 pad) + 38 = 150 +; HSA-LABEL: {{^}}test_round_size_3_order2: +; HSA: workgroup_group_segment_byte_size = 150 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order2(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; align 16, 8, 32 +; 38 + (2 pad) + 38 + (2 pad) + 38 +; HSA-LABEL: {{^}}test_round_size_3_order3: +; HSA: workgroup_group_segment_byte_size = 118 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order3(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; align 8, 32, 16 +; 38 + (26 pad) + 38 + (2 pad) + 38 = 142 +; HSA-LABEL: {{^}}test_round_size_3_order4: +; HSA: workgroup_group_segment_byte_size = 142 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order4(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +; align 8, 16, 32 +; 38 + (10 pad) + 38 + (2 pad) + 38 = 126 +; HSA-LABEL: {{^}}test_round_size_3_order5: +; HSA: workgroup_group_segment_byte_size = 126 +; HSA: group_segment_alignment = 4 +define void @test_round_size_3_order5(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { + %lds.align8.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align8.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align8.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align8.0.bc, i32 38, i32 8, i1 false) + + %lds.align16.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align16.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align16.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align16.0.bc, i32 38, i32 8, i1 false) + + %lds.align32.0.bc = bitcast [38 x i8] addrspace(3)* @lds.align32.0 to i8 addrspace(3)* + call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %lds.align32.0.bc, i8 addrspace(1)* %in, i32 38, i32 8, i1 false) + call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out, i8 addrspace(3)* %lds.align32.0.bc, i32 38, i32 8, i1 false) + + ret void +} + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind } +attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/lds-initializer.ll b/test/CodeGen/AMDGPU/lds-initializer.ll index bf8df63be9fd..9875814b03d3 100644 --- a/test/CodeGen/AMDGPU/lds-initializer.ll +++ b/test/CodeGen/AMDGPU/lds-initializer.ll @@ -1,7 +1,7 @@ ; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s -; CHECK: error: unsupported initializer for address space in load_init_lds_global +; CHECK: in function load_init_lds_global{{.*}}: unsupported initializer for address space @lds = addrspace(3) global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8] diff --git a/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll b/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll new file mode 100644 index 000000000000..0c734c6d99dd --- /dev/null +++ b/test/CodeGen/AMDGPU/lds-m0-init-in-loop.ll @@ -0,0 +1,47 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Make sure that m0 is not reinitialized in the loop. + +; GCN-LABEL: {{^}}copy_local_to_global_loop_m0_init: +; GCN: s_cbranch_scc1 BB0_3 + +; Initialize in preheader +; GCN: s_mov_b32 m0, -1 + +; GCN: BB0_2: +; GCN: ds_read_b32 +; GCN: buffer_store_dword + +; GCN: s_cbranch_vccz BB0_2 + +; GCN: BB0_3: +; GCN-NEXT: s_endpgm +define void @copy_local_to_global_loop_m0_init(i32 addrspace(1)* noalias nocapture %out, i32 addrspace(3)* noalias nocapture readonly %in, i32 %n) #0 { +bb: + %tmp = icmp sgt i32 %n, 0 + br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge + +.lr.ph.preheader: ; preds = %bb + br label %.lr.ph + +._crit_edge.loopexit: ; preds = %.lr.ph + br label %._crit_edge + +._crit_edge: ; preds = %._crit_edge.loopexit, %bb + ret void + +.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader + %indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ] + %i.01 = phi i32 [ %tmp4, %.lr.ph ], [ 0, %.lr.ph.preheader ] + %tmp1 = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %i.01 + %tmp2 = load i32, i32 addrspace(3)* %tmp1, align 4 + %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %indvars.iv + store i32 %tmp2, i32 addrspace(1)* %tmp3, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %tmp4 = add nuw nsw i32 %i.01, 1 + %lftr.wideiv = trunc i64 %indvars.iv.next to i32 + %exitcond = icmp eq i32 %lftr.wideiv, %n + br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/lds-output-queue.ll b/test/CodeGen/AMDGPU/lds-output-queue.ll index 44ffc36af149..abe472e423fc 100644 --- a/test/CodeGen/AMDGPU/lds-output-queue.ll +++ b/test/CodeGen/AMDGPU/lds-output-queue.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck %s +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck %s ; ; This test checks that the lds input queue will is empty at the end of ; the ALU clause. @@ -14,7 +14,7 @@ define void @lds_input_queue(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 entry: %0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(3)* @local_mem, i32 0, i32 %index %1 = load i32, i32 addrspace(3)* %0 - call void @llvm.AMDGPU.barrier.local() + call void @llvm.r600.group.barrier() ; This will start a new clause for the vertex fetch %2 = load i32, i32 addrspace(1)* %in @@ -23,7 +23,7 @@ entry: ret void } -declare void @llvm.AMDGPU.barrier.local() +declare void @llvm.r600.group.barrier() nounwind convergent ; The machine scheduler does not do proper alias analysis and assumes that ; loads from global values (Note that a global value is different that a diff --git a/test/CodeGen/AMDGPU/lds-size.ll b/test/CodeGen/AMDGPU/lds-size.ll index 3e8328659fdb..1607713090e3 100644 --- a/test/CodeGen/AMDGPU/lds-size.ll +++ b/test/CodeGen/AMDGPU/lds-size.ll @@ -1,11 +1,17 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=ALL -check-prefix=GCN %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s ; This test makes sure we do not double count global values when they are ; used in different basic blocks. -; CHECK: .long 166120 -; CHECK-NEXT: .long 1 -; CHECK-LABEL: {{^}}test: +; GCN: .long 47180 +; GCN-NEXT: .long 32900 + +; EG: .long 166120 +; EG-NEXT: .long 1 +; ALL: {{^}}test: + +; GCN: ; LDSByteSize: 4 bytes/workgroup (compile time only) @lds = internal unnamed_addr addrspace(3) global i32 undef, align 4 define void @test(i32 addrspace(1)* %out, i32 %cond) { diff --git a/test/CodeGen/AMDGPU/lds-zero-initializer.ll b/test/CodeGen/AMDGPU/lds-zero-initializer.ll index fb51bc0e50c2..cb5d73fb0d8b 100644 --- a/test/CodeGen/AMDGPU/lds-zero-initializer.ll +++ b/test/CodeGen/AMDGPU/lds-zero-initializer.ll @@ -1,7 +1,7 @@ ; RUN: not llc -march=amdgcn -mcpu=SI < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck %s -; CHECK: error: unsupported initializer for address space in load_zeroinit_lds_global +; CHECK: in function load_zeroinit_lds_global{{.*}}: unsupported initializer for address space @lds = addrspace(3) global [256 x i32] zeroinitializer diff --git a/test/CodeGen/AMDGPU/literals.ll b/test/CodeGen/AMDGPU/literals.ll index 9d2320cb2d19..82fbb7f46186 100644 --- a/test/CodeGen/AMDGPU/literals.ll +++ b/test/CodeGen/AMDGPU/literals.ll @@ -54,11 +54,11 @@ entry: ; CHECK-NEXT: DOT4 * T[[GPR]].W (MASKED), 1.0 define void @inline_literal_dot4(float addrspace(1)* %out) { entry: - %0 = call float @llvm.AMDGPU.dp4(<4 x float> , <4 x float> ) + %0 = call float @llvm.r600.dot4(<4 x float> , <4 x float> ) store float %0, float addrspace(1)* %out ret void } -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/liveness.mir b/test/CodeGen/AMDGPU/liveness.mir new file mode 100644 index 000000000000..ce49294d5b36 --- /dev/null +++ b/test/CodeGen/AMDGPU/liveness.mir @@ -0,0 +1,32 @@ +# RUN: llc -march=amdgcn -run-pass liveintervals -verify-machineinstrs -o /dev/null -debug-only=regalloc %s 2>&1 | FileCheck %s +# REQUIRES: asserts +# We currently maintain a main liveness range which operates like a superset of +# all subregister liveranges. We may need to create additional SSA values at +# merge point in this main liverange even though none of the subregister +# liveranges needed it. +# +# Should see three distinct value numbers: +# CHECK: %vreg0 [{{.*}}:0)[{{.*}}:1)[{{.*}}:2) 0@{{[0-9]+[Berd]}} 1@{{[0-9]+[Berd]}} 2@{{[0-9]+B-phi}} +--- | + define void @test0() { ret void } +... +--- +name: test0 +registers: + - { id: 0, class: sreg_64 } +body: | + bb.0: + successors: %bb.1, %bb.2 + S_NOP 0, implicit-def undef %0:sub0 + S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc + S_BRANCH %bb.2 + + bb.1: + successors: %bb.2 + S_NOP 0, implicit-def %0:sub1 + S_NOP 0, implicit %0:sub1 + S_BRANCH %bb.2 + + bb.2: + S_NOP 0, implicit %0:sub0 +... diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll deleted file mode 100644 index ca8ddbae9fbc..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.abs.ll +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.abs(i32) nounwind readnone - -; Legacy name -declare i32 @llvm.AMDIL.abs.i32(i32) nounwind readnone - -; FUNC-LABEL: {{^}}s_abs_i32: -; SI: s_abs_i32 - -; EG: SUB_INT -; EG: MAX_INT -define void @s_abs_i32(i32 addrspace(1)* %out, i32 %src) nounwind { - %abs = call i32 @llvm.AMDGPU.abs(i32 %src) nounwind readnone - store i32 %abs, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}v_abs_i32: -; SI: v_sub_i32_e32 -; SI: v_max_i32_e32 -; SI: s_endpgm - -; EG: SUB_INT -; EG: MAX_INT -define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind { - %val = load i32, i32 addrspace(1)* %src, align 4 - %abs = call i32 @llvm.AMDGPU.abs(i32 %val) nounwind readnone - store i32 %abs, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}abs_i32_legacy_amdil: -; SI: v_sub_i32_e32 -; SI: v_max_i32_e32 -; SI: s_endpgm - -; EG: SUB_INT -; EG: MAX_INT -define void @abs_i32_legacy_amdil(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind { - %val = load i32, i32 addrspace(1)* %src, align 4 - %abs = call i32 @llvm.AMDIL.abs.i32(i32 %val) nounwind readnone - store i32 %abs, i32 addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.global.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.global.ll deleted file mode 100644 index db883972d646..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.global.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}test_barrier_global: -; EG: GROUP_BARRIER -; SI: buffer_store_dword -; SI: s_waitcnt -; SI: s_barrier - -define void @test_barrier_global(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tidig.x() - %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0 - store i32 %0, i32 addrspace(1)* %1 - call void @llvm.AMDGPU.barrier.global() - %2 = call i32 @llvm.r600.read.local.size.x() - %3 = sub i32 %2, 1 - %4 = sub i32 %3, %0 - %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4 - %6 = load i32, i32 addrspace(1)* %5 - store i32 %6, i32 addrspace(1)* %1 - ret void -} - -declare void @llvm.AMDGPU.barrier.global() - -declare i32 @llvm.r600.read.tidig.x() #0 -declare i32 @llvm.r600.read.local.size.x() #0 - -attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.local.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.local.ll deleted file mode 100644 index 48fb2e0b1a8d..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.barrier.local.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}test_barrier_local: -; EG: GROUP_BARRIER - -; SI: buffer_store_dword -; SI: s_waitcnt -; SI: s_barrier - -define void @test_barrier_local(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tidig.x() - %1 = getelementptr i32, i32 addrspace(1)* %out, i32 %0 - store i32 %0, i32 addrspace(1)* %1 - call void @llvm.AMDGPU.barrier.local() - %2 = call i32 @llvm.r600.read.local.size.x() - %3 = sub i32 %2, 1 - %4 = sub i32 %3, %0 - %5 = getelementptr i32, i32 addrspace(1)* %out, i32 %4 - %6 = load i32, i32 addrspace(1)* %5 - store i32 %6, i32 addrspace(1)* %1 - ret void -} - -declare void @llvm.AMDGPU.barrier.local() - -declare i32 @llvm.r600.read.tidig.x() #0 -declare i32 @llvm.r600.read.local.size.x() #0 - -attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.bfi.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.bfi.ll deleted file mode 100644 index 517a55abc098..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.bfi.ll +++ /dev/null @@ -1,42 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.bfi(i32, i32, i32) nounwind readnone - -; FUNC-LABEL: {{^}}bfi_arg_arg_arg: -; SI: v_bfi_b32 -; EG: BFI_INT -define void @bfi_arg_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { - %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 %src1) nounwind readnone - store i32 %bfi, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfi_arg_arg_imm: -; SI: v_bfi_b32 -; EG: BFI_INT -define void @bfi_arg_arg_imm(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { - %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 %src1, i32 123) nounwind readnone - store i32 %bfi, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfi_arg_imm_arg: -; SI: v_bfi_b32 -; EG: BFI_INT -define void @bfi_arg_imm_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src2) nounwind { - %bfi = call i32 @llvm.AMDGPU.bfi(i32 %src0, i32 123, i32 %src2) nounwind readnone - store i32 %bfi, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfi_imm_arg_arg: -; SI: v_bfi_b32 -; EG: BFI_INT -define void @bfi_imm_arg_arg(i32 addrspace(1)* %out, i32 %src1, i32 %src2) nounwind { - %bfi = call i32 @llvm.AMDGPU.bfi(i32 123, i32 %src1, i32 %src2) nounwind readnone - store i32 %bfi, i32 addrspace(1)* %out, align 4 - ret void -} - diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll deleted file mode 100644 index 50492289d744..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.bfm.ll +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.bfm(i32, i32) nounwind readnone - -; FUNC-LABEL: {{^}}bfm_arg_arg: -; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} -; EG: BFM_INT -define void @bfm_arg_arg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { - %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 %src1) nounwind readnone - store i32 %bfm, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfm_arg_imm: -; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x7b -; EG: BFM_INT -define void @bfm_arg_imm(i32 addrspace(1)* %out, i32 %src0) nounwind { - %bfm = call i32 @llvm.AMDGPU.bfm(i32 %src0, i32 123) nounwind readnone - store i32 %bfm, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfm_imm_arg: -; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, {{s[0-9]+}} -; EG: BFM_INT -define void @bfm_imm_arg(i32 addrspace(1)* %out, i32 %src1) nounwind { - %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 %src1) nounwind readnone - store i32 %bfm, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfm_imm_imm: -; SI: s_bfm_b32 {{s[0-9]+}}, 0x7b, 0x1c8 -; EG: BFM_INT -define void @bfm_imm_imm(i32 addrspace(1)* %out) nounwind { - %bfm = call i32 @llvm.AMDGPU.bfm(i32 123, i32 456) nounwind readnone - store i32 %bfm, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}bfm_pattern: -; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} -define void @bfm_pattern(i32 addrspace(1)* %out, i32 %x, i32 %y) { - %a = shl i32 1, %x - %b = sub i32 %a, 1 - %c = shl i32 %b, %y - store i32 %c, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}bfm_pattern_simple: -; SI: s_bfm_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0 -define void @bfm_pattern_simple(i32 addrspace(1)* %out, i32 %x) { - %a = shl i32 1, %x - %b = sub i32 %a, 1 - store i32 %b, i32 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll index 11ec963ab314..cfe4cc00ee81 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.clamp.ll @@ -1,10 +1,9 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare float @llvm.fabs.f32(float) nounwind readnone declare float @llvm.AMDGPU.clamp.f32(float, float, float) nounwind readnone -declare float @llvm.AMDIL.clamp.f32(float, float, float) nounwind readnone ; FUNC-LABEL: {{^}}clamp_0_1_f32: ; SI: s_load_dword [[ARG:s[0-9]+]], @@ -55,13 +54,3 @@ define void @clamp_fneg_fabs_0_1_f32(float addrspace(1)* %out, float %src) nounw store float %clamp, float addrspace(1)* %out, align 4 ret void } - -; FUNC-LABEL: {{^}}clamp_0_1_amdil_legacy_f32: -; SI: s_load_dword [[ARG:s[0-9]+]], -; SI: v_add_f32_e64 [[RESULT:v[0-9]+]], 0, [[ARG]] clamp{{$}} -; SI: buffer_store_dword [[RESULT]] -define void @clamp_0_1_amdil_legacy_f32(float addrspace(1)* %out, float %src) nounwind { - %clamp = call float @llvm.AMDIL.clamp.f32(float %src, float 0.0, float 1.0) nounwind readnone - store float %clamp, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.class.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.class.ll deleted file mode 100644 index 80eb3b93f8e5..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.class.ll +++ /dev/null @@ -1,499 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s - -declare i1 @llvm.AMDGPU.class.f32(float, i32) #1 -declare i1 @llvm.AMDGPU.class.f64(double, i32) #1 -declare i32 @llvm.r600.read.tidig.x() #1 -declare float @llvm.fabs.f32(float) #1 -declare double @llvm.fabs.f64(double) #1 - -; SI-LABEL: {{^}}test_class_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fabs_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { - %a.fabs = call float @llvm.fabs.f32(float %a) #1 - %result = call i1 @llvm.AMDGPU.class.f32(float %a.fabs, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fneg_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fneg_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { - %a.fneg = fsub float -0.0, %a - %result = call i1 @llvm.AMDGPU.class.f32(float %a.fneg, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fneg_fabs_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fneg_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { - %a.fabs = call float @llvm.fabs.f32(float %a) #1 - %a.fneg.fabs = fsub float -0.0, %a.fabs - %result = call i1 @llvm.AMDGPU.class.f32(float %a.fneg.fabs, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_1_f32: -; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 1{{$}} -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_1_f32(i32 addrspace(1)* %out, float %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_64_f32: -; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 64{{$}} -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_64_f32(i32 addrspace(1)* %out, float %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 64) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; Set all 10 bits of mask -; SI-LABEL: {{^}}test_class_full_mask_f32: -; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}} -; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_full_mask_f32(i32 addrspace(1)* %out, float %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1023) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_9bit_mask_f32: -; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} -; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_9bit_mask_f32(i32 addrspace(1)* %out, float %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 511) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}v_test_class_full_mask_f32: -; SI-DAG: buffer_load_dword [[VA:v[0-9]+]] -; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} -; SI: v_cmp_class_f32_e32 vcc, [[VA]], [[MASK]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 511) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f32: -; SI-DAG: buffer_load_dword [[VB:v[0-9]+]] -; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %b = load i32, i32 addrspace(1)* %gep.in - - %result = call i1 @llvm.AMDGPU.class.f32(float 1.0, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; FIXME: Why isn't this using a literal constant operand? -; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f32: -; SI-DAG: buffer_load_dword [[VB:v[0-9]+]] -; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000 -; SI: v_cmp_class_f32_e32 vcc, [[VK]], [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_lit_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %b = load i32, i32 addrspace(1)* %gep.in - - %result = call i1 @llvm.AMDGPU.class.f32(float 1024.0, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_f64: -; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fabs_f64: -; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { - %a.fabs = call double @llvm.fabs.f64(double %a) #1 - %result = call i1 @llvm.AMDGPU.class.f64(double %a.fabs, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fneg_f64: -; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fneg_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { - %a.fneg = fsub double -0.0, %a - %result = call i1 @llvm.AMDGPU.class.f64(double %a.fneg, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_fneg_fabs_f64: -; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]] -; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_fneg_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { - %a.fabs = call double @llvm.fabs.f64(double %a) #1 - %a.fneg.fabs = fsub double -0.0, %a.fabs - %result = call i1 @llvm.AMDGPU.class.f64(double %a.fneg.fabs, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_1_f64: -; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 1{{$}} -; SI: s_endpgm -define void @test_class_1_f64(i32 addrspace(1)* %out, double %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 1) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_64_f64: -; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 64{{$}} -; SI: s_endpgm -define void @test_class_64_f64(i32 addrspace(1)* %out, double %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 64) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; Set all 9 bits of mask -; SI-LABEL: {{^}}test_class_full_mask_f64: -; SI: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} -; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[MASK]] -; SI-NOT: vcc -; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI-NEXT: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_full_mask_f64(i32 addrspace(1)* %out, double %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 511) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}v_test_class_full_mask_f64: -; SI-DAG: buffer_load_dwordx2 [[VA:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} -; SI: v_cmp_class_f64_e32 vcc, [[VA]], [[MASK]] -; SI-NOT: vcc -; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load double, double addrspace(1)* %in - - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 511) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f64: -; XSI: v_cmp_class_f64_e32 vcc, 1.0, -; SI: v_cmp_class_f64_e32 vcc, -; SI: s_endpgm -define void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %b = load i32, i32 addrspace(1)* %gep.in - - %result = call i1 @llvm.AMDGPU.class.f64(double 1.0, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f64: -; SI: v_cmp_class_f64_e32 vcc, s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} -; SI: s_endpgm -define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %b = load i32, i32 addrspace(1)* %gep.in - - %result = call i1 @llvm.AMDGPU.class.f64(double 1024.0, i32 %b) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %gep.out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_fold_or_class_f32_0: -; SI-NOT: v_cmp_class -; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 3{{$}} -; SI-NOT: v_cmp_class -; SI: s_endpgm -define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 3) #1 - %or = or i1 %class0, %class1 - - %sext = sext i1 %or to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_fold_or3_class_f32_0: -; SI-NOT: v_cmp_class -; SI: v_cmp_class_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}} -; SI-NOT: v_cmp_class -; SI: s_endpgm -define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1 - %class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1 - %or.0 = or i1 %class0, %class1 - %or.1 = or i1 %or.0, %class2 - - %sext = sext i1 %or.1 to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_fold_or_all_tests_class_f32_0: -; SI-NOT: v_cmp_class -; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}} -; SI: v_cmp_class_f32_e32 vcc, v{{[0-9]+}}, [[MASK]]{{$}} -; SI-NOT: v_cmp_class -; SI: s_endpgm -define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1 - %class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1 - %class3 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1 - %class4 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 16) #1 - %class5 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 32) #1 - %class6 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 64) #1 - %class7 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 128) #1 - %class8 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 256) #1 - %class9 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 512) #1 - %or.0 = or i1 %class0, %class1 - %or.1 = or i1 %or.0, %class2 - %or.2 = or i1 %or.1, %class3 - %or.3 = or i1 %or.2, %class4 - %or.4 = or i1 %or.3, %class5 - %or.5 = or i1 %or.4, %class6 - %or.6 = or i1 %or.5, %class7 - %or.7 = or i1 %or.6, %class8 - %or.8 = or i1 %or.7, %class9 - %sext = sext i1 %or.8 to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_fold_or_class_f32_1: -; SI-NOT: v_cmp_class -; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 12{{$}} -; SI-NOT: v_cmp_class -; SI: s_endpgm -define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1 - %or = or i1 %class0, %class1 - - %sext = sext i1 %or to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_fold_or_class_f32_2: -; SI-NOT: v_cmp_class -; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}} -; SI-NOT: v_cmp_class -; SI: s_endpgm -define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1 - %or = or i1 %class0, %class1 - - %sext = sext i1 %or to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_no_fold_or_class_f32_0: -; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 4{{$}} -; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 8{{$}} -; SI: s_or_b64 -; SI: s_endpgm -define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 - %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.in - - %class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1 - %class1 = call i1 @llvm.AMDGPU.class.f32(float %b, i32 8) #1 - %or = or i1 %class0, %class1 - - %sext = sext i1 %or to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_0_f32: -; SI-NOT: v_cmp_class -; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_class_0_f64: -; SI-NOT: v_cmp_class -; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} -; SI: buffer_store_dword [[RESULT]] -; SI: s_endpgm -define void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 { - %result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 0) #1 - %sext = sext i1 %result to i32 - store i32 %sext, i32 addrspace(1)* %out, align 4 - ret void -} - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll index e95a51093cb7..78b88122229b 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.cube.ll @@ -1,59 +1,57 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -; CHECK: {{^}}cube: +; CHECK-LABEL: {{^}}cube: ; CHECK: CUBE T{{[0-9]}}.X ; CHECK: CUBE T{{[0-9]}}.Y ; CHECK: CUBE T{{[0-9]}}.Z ; CHECK: CUBE * T{{[0-9]}}.W -define void @cube() #0 { +define amdgpu_ps void @cube() { main_body: - %0 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %1 = extractelement <4 x float> %0, i32 3 - %2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %3 = extractelement <4 x float> %2, i32 0 - %4 = fdiv float %3, %1 - %5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %6 = extractelement <4 x float> %5, i32 1 - %7 = fdiv float %6, %1 - %8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) - %9 = extractelement <4 x float> %8, i32 2 - %10 = fdiv float %9, %1 - %11 = insertelement <4 x float> undef, float %4, i32 0 - %12 = insertelement <4 x float> %11, float %7, i32 1 - %13 = insertelement <4 x float> %12, float %10, i32 2 - %14 = insertelement <4 x float> %13, float 1.000000e+00, i32 3 - %15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %14) - %16 = extractelement <4 x float> %15, i32 0 - %17 = extractelement <4 x float> %15, i32 1 - %18 = extractelement <4 x float> %15, i32 2 - %19 = extractelement <4 x float> %15, i32 3 - %20 = call float @fabs(float %18) - %21 = fdiv float 1.000000e+00, %20 - %22 = fmul float %16, %21 - %23 = fadd float %22, 1.500000e+00 - %24 = fmul float %17, %21 - %25 = fadd float %24, 1.500000e+00 - %26 = insertelement <4 x float> undef, float %25, i32 0 - %27 = insertelement <4 x float> %26, float %23, i32 1 - %28 = insertelement <4 x float> %27, float %19, i32 2 - %29 = insertelement <4 x float> %28, float %25, i32 3 - %30 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %29, i32 16, i32 0, i32 4) - call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0) + %tmp = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp1 = extractelement <4 x float> %tmp, i32 3 + %tmp2 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp3 = extractelement <4 x float> %tmp2, i32 0 + %tmp4 = fdiv float %tmp3, %tmp1 + %tmp5 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp6 = extractelement <4 x float> %tmp5, i32 1 + %tmp7 = fdiv float %tmp6, %tmp1 + %tmp8 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 9) + %tmp9 = extractelement <4 x float> %tmp8, i32 2 + %tmp10 = fdiv float %tmp9, %tmp1 + %tmp11 = insertelement <4 x float> undef, float %tmp4, i32 0 + %tmp12 = insertelement <4 x float> %tmp11, float %tmp7, i32 1 + %tmp13 = insertelement <4 x float> %tmp12, float %tmp10, i32 2 + %tmp14 = insertelement <4 x float> %tmp13, float 1.000000e+00, i32 3 + %tmp15 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp14) + %tmp16 = extractelement <4 x float> %tmp15, i32 0 + %tmp17 = extractelement <4 x float> %tmp15, i32 1 + %tmp18 = extractelement <4 x float> %tmp15, i32 2 + %tmp19 = extractelement <4 x float> %tmp15, i32 3 + %tmp20 = call float @llvm.fabs.f32(float %tmp18) + %tmp21 = fdiv float 1.000000e+00, %tmp20 + %tmp22 = fmul float %tmp16, %tmp21 + %tmp23 = fadd float %tmp22, 1.500000e+00 + %tmp24 = fmul float %tmp17, %tmp21 + %tmp25 = fadd float %tmp24, 1.500000e+00 + %tmp26 = insertelement <4 x float> undef, float %tmp25, i32 0 + %tmp27 = insertelement <4 x float> %tmp26, float %tmp23, i32 1 + %tmp28 = insertelement <4 x float> %tmp27, float %tmp19, i32 2 + %tmp29 = insertelement <4 x float> %tmp28, float %tmp25, i32 3 + %tmp30 = shufflevector <4 x float> %tmp29, <4 x float> %tmp29, <4 x i32> + %tmp31 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp30, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %tmp31, i32 0, i32 0) ret void } ; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1 +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 -; Function Attrs: readnone -declare float @fabs(float) #1 +; Function Attrs: nounwind readnone +declare float @llvm.fabs.f32(float) #0 -; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } -attributes #1 = { readnone } +; Function Attrs: readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll deleted file mode 100644 index 8b32f696449e..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.cvt_f32_ubyte.ll +++ /dev/null @@ -1,43 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI %s - -declare float @llvm.AMDGPU.cvt.f32.ubyte0(i32) nounwind readnone -declare float @llvm.AMDGPU.cvt.f32.ubyte1(i32) nounwind readnone -declare float @llvm.AMDGPU.cvt.f32.ubyte2(i32) nounwind readnone -declare float @llvm.AMDGPU.cvt.f32.ubyte3(i32) nounwind readnone - -; SI-LABEL: {{^}}test_unpack_byte0_to_float: -; SI: v_cvt_f32_ubyte0 -define void @test_unpack_byte0_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %val = load i32, i32 addrspace(1)* %in, align 4 - %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte0(i32 %val) nounwind readnone - store float %cvt, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_unpack_byte1_to_float: -; SI: v_cvt_f32_ubyte1 -define void @test_unpack_byte1_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %val = load i32, i32 addrspace(1)* %in, align 4 - %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte1(i32 %val) nounwind readnone - store float %cvt, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_unpack_byte2_to_float: -; SI: v_cvt_f32_ubyte2 -define void @test_unpack_byte2_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %val = load i32, i32 addrspace(1)* %in, align 4 - %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte2(i32 %val) nounwind readnone - store float %cvt, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_unpack_byte3_to_float: -; SI: v_cvt_f32_ubyte3 -define void @test_unpack_byte3_to_float(float addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %val = load i32, i32 addrspace(1)* %in, align 4 - %cvt = call float @llvm.AMDGPU.cvt.f32.ubyte3(i32 %val) nounwind readnone - store float %cvt, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll deleted file mode 100644 index 55ca9c7536e5..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fixup.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s - -declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone -declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone - -; GCN-LABEL: {{^}}test_div_fixup_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 -; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 -; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] -; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] -; GCN: buffer_store_dword [[RESULT]], -; GCN: s_endpgm -define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { - %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fixup_f64: -; GCN: v_div_fixup_f64 -define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { - %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone - store double %result, double addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll deleted file mode 100644 index 7dc094ed1b4b..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_fmas.ll +++ /dev/null @@ -1,178 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s -; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s - -; FIXME: Enable for VI. - -declare i32 @llvm.r600.read.tidig.x() nounwind readnone -declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone -declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone - -; GCN-LABEL: {{^}}test_div_fmas_f32: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 -; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 -; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] -; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] -; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]] -; GCN: buffer_store_dword [[RESULT]], -; GCN: s_endpgm -define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0: -; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]] -; SI: buffer_store_dword [[RESULT]], -; SI: s_endpgm -define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] -; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] -; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]] -; SI: buffer_store_dword [[RESULT]], -; SI: s_endpgm -define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2: -; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] -; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0 -; SI: buffer_store_dword [[RESULT]], -; SI: s_endpgm -define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f64: -; GCN: v_div_fmas_f64 -define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { - %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone - store double %result, double addrspace(1)* %out, align 8 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: -; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} -; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { - %cmp = icmp eq i32 %i, 0 - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc: -; SI: s_mov_b64 vcc, 0 -; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc: -; SI: s_mov_b64 vcc, -1 -; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} -; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} - -; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} -; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} -; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] -; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] -; SI: s_endpgm -define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 - %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 - %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 - - %a = load float, float addrspace(1)* %gep.a - %b = load float, float addrspace(1)* %gep.b - %c = load float, float addrspace(1)* %gep.c - - %cmp0 = icmp eq i32 %tid, 0 - %cmp1 = icmp ne i32 %d, 0 - %and = and i1 %cmp0, %cmp1 - - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone - store float %result, float addrspace(1)* %gep.out, align 4 - ret void -} - -; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: -; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}} -; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc -; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]] - -; SI: buffer_load_dword [[LOAD:v[0-9]+]] -; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]] -; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc - - -; SI: BB9_2: -; SI: s_or_b64 exec, exec, [[SAVE]] -; SI: v_cmp_ne_i32_e32 vcc, 0, v0 -; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} -; SI: buffer_store_dword -; SI: s_endpgm -define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind { -entry: - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 - %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 - %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 - - %a = load float, float addrspace(1)* %gep.a - %b = load float, float addrspace(1)* %gep.b - %c = load float, float addrspace(1)* %gep.c - - %cmp0 = icmp eq i32 %tid, 0 - br i1 %cmp0, label %bb, label %exit - -bb: - %val = load i32, i32 addrspace(1)* %dummy - %cmp1 = icmp ne i32 %val, 0 - br label %exit - -exit: - %cond = phi i1 [false, %entry], [%cmp1, %bb] - %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone - store float %result, float addrspace(1)* %gep.out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_scale.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.div_scale.ll deleted file mode 100644 index de830de039c7..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.div_scale.ll +++ /dev/null @@ -1,364 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s - -declare i32 @llvm.r600.read.tidig.x() nounwind readnone -declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind readnone -declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone -declare float @llvm.fabs.f32(float) nounwind readnone - -; SI-LABEL @test_div_scale_f32_1: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_2: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f64_1: -; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 - - %a = load double, double addrspace(1)* %gep.0, align 8 - %b = load double, double addrspace(1)* %gep.1, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f64_1: -; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 - - %a = load double, double addrspace(1)* %gep.0, align 8 - %b = load double, double addrspace(1)* %gep.1, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f32_scalar_num_1: -; SI-DAG: buffer_load_dword [[B:v[0-9]+]] -; SI-DAG: s_load_dword [[A:s[0-9]+]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr float, float addrspace(1)* %in, i32 %tid - - %b = load float, float addrspace(1)* %gep, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_scalar_num_2: -; SI-DAG: buffer_load_dword [[B:v[0-9]+]] -; SI-DAG: s_load_dword [[A:s[0-9]+]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr float, float addrspace(1)* %in, i32 %tid - - %b = load float, float addrspace(1)* %gep, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_scalar_den_1: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]] -; SI-DAG: s_load_dword [[B:s[0-9]+]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr float, float addrspace(1)* %in, i32 %tid - - %a = load float, float addrspace(1)* %gep, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_scalar_den_2: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]] -; SI-DAG: s_load_dword [[B:s[0-9]+]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr float, float addrspace(1)* %in, i32 %tid - - %a = load float, float addrspace(1)* %gep, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f64_scalar_num_1: -; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr double, double addrspace(1)* %in, i32 %tid - - %b = load double, double addrspace(1)* %gep, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f64_scalar_num_2: -; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr double, double addrspace(1)* %in, i32 %tid - - %b = load double, double addrspace(1)* %gep, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f64_scalar_den_1: -; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr double, double addrspace(1)* %in, i32 %tid - - %a = load double, double addrspace(1)* %gep, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f64_scalar_den_2: -; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] -; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep = getelementptr double, double addrspace(1)* %in, i32 %tid - - %a = load double, double addrspace(1)* %gep, align 8 - - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f32_all_scalar_1: -; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind { - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_all_scalar_2: -; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc -; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind { - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f64_all_scalar_1: -; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]] -; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]] -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}} -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind { - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f64_all_scalar_2: -; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]] -; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]] -; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]] -; SI: buffer_store_dwordx2 [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind { - %result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone - %result0 = extractvalue { double, i1 } %result, 0 - store double %result0, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL @test_div_scale_f32_inline_imm_num: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[A]], 1.0 -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_inline_imm_den: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], 2.0, 2.0, [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_fabs_num: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], |[[A]]| -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 - - %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a.fabs, float %b, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL @test_div_scale_f32_fabs_den: -; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 -; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], |[[B]]|, |[[B]]|, [[A]] -; SI: buffer_store_dword [[RESULT0]] -; SI: s_endpgm -define void @test_div_scale_f32_fabs_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid - %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 - - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 - - %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone - - %result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b.fabs, i1 false) nounwind readnone - %result0 = extractvalue { float, i1 } %result, 0 - store float %result0, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll deleted file mode 100644 index 6049dca04012..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.f64.ll +++ /dev/null @@ -1,60 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s - -declare double @llvm.fabs.f64(double %Val) -declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone - -; FUNC-LABEL: {{^}}fract_f64: -; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] -; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 -; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] -; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] -; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] -; CI: buffer_store_dwordx2 [[FRC]] -define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { - %val = load double, double addrspace(1)* %src, align 4 - %fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone - store double %fract, double addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}fract_f64_neg: -; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]] -; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 -; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] -; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] -; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] -; CI: buffer_store_dwordx2 [[FRC]] -define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { - %val = load double, double addrspace(1)* %src, align 4 - %neg = fsub double 0.0, %val - %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone - store double %fract, double addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}fract_f64_neg_abs: -; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]| -; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1 -; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff -; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]] -; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3 -; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]] -; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]] -; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]] -; CI: buffer_store_dwordx2 [[FRC]] -define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind { - %val = load double, double addrspace(1)* %src, align 4 - %abs = call double @llvm.fabs.f64(double %val) - %neg = fsub double 0.0, %abs - %fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone - store double %fract, double addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll deleted file mode 100644 index 7501b4b75465..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.fract.ll +++ /dev/null @@ -1,65 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare float @llvm.fabs.f32(float %Val) -declare float @llvm.AMDGPU.fract.f32(float) nounwind readnone - -; Legacy name -declare float @llvm.AMDIL.fraction.f32(float) nounwind readnone - -; FUNC-LABEL: {{^}}fract_f32: -; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]] -; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]] -; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]] -; GCN: buffer_store_dword [[RESULT]] -; EG: FRACT -define void @fract_f32(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { - %val = load float, float addrspace(1)* %src, align 4 - %fract = call float @llvm.AMDGPU.fract.f32(float %val) nounwind readnone - store float %fract, float addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}fract_f32_legacy_amdil: -; CI: v_fract_f32_e32 [[RESULT:v[0-9]+]], [[INPUT:v[0-9]+]] -; SI: v_floor_f32_e32 [[FLR:v[0-9]+]], [[INPUT:v[0-9]+]] -; SI: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[FLR]], [[INPUT]] -; GCN: buffer_store_dword [[RESULT]] -; EG: FRACT -define void @fract_f32_legacy_amdil(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { - %val = load float, float addrspace(1)* %src, align 4 - %fract = call float @llvm.AMDIL.fraction.f32(float %val) nounwind readnone - store float %fract, float addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}fract_f32_neg: -; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT:v[0-9]+]] -; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -[[INPUT:v[0-9]+]] -; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -[[INPUT]], [[FLR]] -; GCN: buffer_store_dword [[RESULT]] -; EG: FRACT -define void @fract_f32_neg(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { - %val = load float, float addrspace(1)* %src, align 4 - %neg = fsub float 0.0, %val - %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone - store float %fract, float addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}fract_f32_neg_abs: -; CI: v_fract_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT:v[0-9]+]]| -; SI: v_floor_f32_e64 [[FLR:v[0-9]+]], -|[[INPUT:v[0-9]+]]| -; SI: v_sub_f32_e64 [[RESULT:v[0-9]+]], -|[[INPUT]]|, [[FLR]] -; GCN: buffer_store_dword [[RESULT]] -; EG: FRACT -define void @fract_f32_neg_abs(float addrspace(1)* %out, float addrspace(1)* %src) nounwind { - %val = load float, float addrspace(1)* %src, align 4 - %abs = call float @llvm.fabs.f32(float %val) - %neg = fsub float 0.0, %abs - %fract = call float @llvm.AMDGPU.fract.f32(float %neg) nounwind readnone - store float %fract, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll deleted file mode 100644 index 42102e30f071..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.imad24.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s - -; FIXME: Store of i32 seems to be broken pre-EG somehow? - -declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) nounwind readnone - -; FUNC-LABEL: {{^}}test_imad24: -; SI: v_mad_i32_i24 -; CM: MULADD_INT24 -; R600: MULLO_INT -; R600: ADD_INT -define void @test_imad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { - %mad = call i32 @llvm.AMDGPU.imad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone - store i32 %mad, i32 addrspace(1)* %out, align 4 - ret void -} - diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll deleted file mode 100644 index 46662f96c290..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.imax.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_imax: -; SI: v_max_i32_e32 -define void @vector_imax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %load) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_imax: -; SI: s_max_i32 -define void @scalar_imax(i32 %p0, i32 %p1) #0 { -entry: - %max = call i32 @llvm.AMDGPU.imax(i32 %p0, i32 %p1) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.imax(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll deleted file mode 100644 index 34b454e23755..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.imin.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_imin: -; SI: v_min_i32_e32 -define void @vector_imin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %load) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_imin: -; SI: s_min_i32 -define void @scalar_imin(i32 %p0, i32 %p1) #0 { -entry: - %min = call i32 @llvm.AMDGPU.imin(i32 %p0, i32 %p1) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.imin(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.imul24.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.imul24.ll deleted file mode 100644 index fdc1172260b9..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.imul24.ll +++ /dev/null @@ -1,16 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone - -; FUNC-LABEL: {{^}}test_imul24: -; SI: v_mul_i32_i24 -; CM: MUL_INT24 -; R600: MULLO_INT -define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { - %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone - store i32 %mul, i32 addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll index 057708e7b5cc..59997d27683d 100644 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll +++ b/test/CodeGen/AMDGPU/llvm.AMDGPU.kill.ll @@ -5,7 +5,7 @@ ; SI-NOT: v_cmpx_le_f32 ; SI: s_mov_b64 exec, 0 -define void @kill_gs_const() #0 { +define amdgpu_gs void @kill_gs_const() { main_body: %0 = icmp ule i32 0, 3 %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00 @@ -21,7 +21,7 @@ main_body: ; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}} ; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}} ; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]] -define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 { +define amdgpu_ps void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) { entry: %tmp0 = fcmp olt float %13, 0.0 call void @llvm.AMDGPU.kill(float %14) @@ -33,7 +33,4 @@ entry: declare void @llvm.AMDGPU.kill(float) declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="2" } -attributes #1 = { "ShaderType"="0" } - !0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.ldexp.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.ldexp.ll deleted file mode 100644 index a59c0ce6d675..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.ldexp.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s - -declare float @llvm.AMDGPU.ldexp.f32(float, i32) nounwind readnone -declare double @llvm.AMDGPU.ldexp.f64(double, i32) nounwind readnone - -; SI-LABEL: {{^}}test_ldexp_f32: -; SI: v_ldexp_f32 -; SI: s_endpgm -define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind { - %result = call float @llvm.AMDGPU.ldexp.f32(float %a, i32 %b) nounwind readnone - store float %result, float addrspace(1)* %out, align 4 - ret void -} - -; SI-LABEL: {{^}}test_ldexp_f64: -; SI: v_ldexp_f64 -; SI: s_endpgm -define void @test_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind { - %result = call double @llvm.AMDGPU.ldexp.f64(double %a, i32 %b) nounwind readnone - store double %result, double addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.legacy.rsq.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.legacy.rsq.ll deleted file mode 100644 index 4cafd563685e..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.legacy.rsq.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare float @llvm.AMDGPU.legacy.rsq(float) nounwind readnone - -; FUNC-LABEL: {{^}}rsq_legacy_f32: -; SI: v_rsq_legacy_f32_e32 -; EG: RECIPSQRT_IEEE -define void @rsq_legacy_f32(float addrspace(1)* %out, float %src) nounwind { - %rsq = call float @llvm.AMDGPU.legacy.rsq(float %src) nounwind readnone - store float %rsq, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll deleted file mode 100644 index 83b56a5029d3..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.mul.ll +++ /dev/null @@ -1,17 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} - -define void @test(<4 x float> inreg %reg0) #0 { - %r0 = extractelement <4 x float> %reg0, i32 0 - %r1 = extractelement <4 x float> %reg0, i32 1 - %r2 = call float @llvm.AMDGPU.mul( float %r0, float %r1) - %vec = insertelement <4 x float> undef, float %r2, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) - ret void -} - -declare float @llvm.AMDGPU.mul(float ,float ) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } \ No newline at end of file diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.f64.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.f64.ll deleted file mode 100644 index d2a655bf909c..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.f64.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s - -declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone -declare double @llvm.sqrt.f64(double) nounwind readnone - -; FUNC-LABEL: {{^}}rcp_f64: -; SI: v_rcp_f64_e32 -define void @rcp_f64(double addrspace(1)* %out, double %src) nounwind { - %rcp = call double @llvm.AMDGPU.rcp.f64(double %src) nounwind readnone - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} - -; FUNC-LABEL: {{^}}rcp_pat_f64: -; SI: v_rcp_f64_e32 -define void @rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { - %rcp = fdiv double 1.0, %src - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} - -; FUNC-LABEL: {{^}}rsq_rcp_pat_f64: -; SI-UNSAFE: v_rsq_f64_e32 -; SI-SAFE-NOT: v_rsq_f64_e32 -; SI-SAFE: v_sqrt_f64 -; SI-SAFE: v_rcp_f64 -define void @rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) nounwind { - %sqrt = call double @llvm.sqrt.f64(double %src) nounwind readnone - %rcp = call double @llvm.AMDGPU.rcp.f64(double %sqrt) nounwind readnone - store double %rcp, double addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.ll deleted file mode 100644 index edd6e9a72f1b..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.rcp.ll +++ /dev/null @@ -1,50 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s -; XUN: llc -march=amdgcn -mcpu=SI -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -enable-unsafe-fp-math -verify-machineinstrs < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI -check-prefix=FUNC %s -; XUN: llc -march=amdgcn -mcpu=tonga -mattr=+fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE-SPDENORM -check-prefix=SI -check-prefix=FUNC %s - -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare float @llvm.AMDGPU.rcp.f32(float) nounwind readnone -declare double @llvm.AMDGPU.rcp.f64(double) nounwind readnone - -declare float @llvm.sqrt.f32(float) nounwind readnone - -; FUNC-LABEL: {{^}}rcp_f32: -; SI: v_rcp_f32_e32 -; EG: RECIP_IEEE -define void @rcp_f32(float addrspace(1)* %out, float %src) nounwind { - %rcp = call float @llvm.AMDGPU.rcp.f32(float %src) nounwind readnone - store float %rcp, float addrspace(1)* %out, align 4 - ret void -} - -; FIXME: Evergreen only ever does unsafe fp math. -; FUNC-LABEL: {{^}}rcp_pat_f32: - -; SI-SAFE: v_rcp_f32_e32 -; XSI-SAFE-SPDENORM-NOT: v_rcp_f32_e32 - -; EG: RECIP_IEEE - -define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { - %rcp = fdiv float 1.0, %src - store float %rcp, float addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}rsq_rcp_pat_f32: -; SI-UNSAFE: v_rsq_f32_e32 -; SI-SAFE: v_sqrt_f32_e32 -; SI-SAFE: v_rcp_f32_e32 - -; EG: RECIPSQRT_IEEE -define void @rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { - %sqrt = call float @llvm.sqrt.f32(float %src) nounwind readnone - %rcp = call float @llvm.AMDGPU.rcp.f32(float %sqrt) nounwind readnone - store float %rcp, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.read.workdim.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.read.workdim.ll deleted file mode 100644 index 2e299e30b8c7..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.read.workdim.ll +++ /dev/null @@ -1,37 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}read_workdim: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV * [[VAL]], KC0[2].Z - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @read_workdim(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.AMDGPU.read.workdim() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}read_workdim_known_bits: -; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb -; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c -; GCN-NOT: 0xff -; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN: buffer_store_dword [[VVAL]] -define void @read_workdim_known_bits(i32 addrspace(1)* %out) { -entry: - %dim = call i32 @llvm.AMDGPU.read.workdim() #0 - %shl = shl i32 %dim, 24 - %shr = lshr i32 %shl, 24 - store i32 %shr, i32 addrspace(1)* %out - ret void -} - -declare i32 @llvm.AMDGPU.read.workdim() #0 - -attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll deleted file mode 100644 index 67f1d22c7178..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.f64.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s - -declare double @llvm.AMDGPU.rsq.clamped.f64(double) nounwind readnone - -; FUNC-LABEL: {{^}}rsq_clamped_f64: -; SI: v_rsq_clamp_f64_e32 - -; VI: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[2:3] -; TODO: this constant should be folded: -; VI: s_mov_b32 s[[ALLBITS:[0-9+]]], -1 -; VI: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff -; VI: s_mov_b32 s[[LOW1:[0-9+]]], s[[ALLBITS]] -; VI: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]] -; VI: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff -; VI: s_mov_b32 s[[LOW2:[0-9+]]], s[[ALLBITS]] -; VI: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW2]]:[[HIGH2]]] - -define void @rsq_clamped_f64(double addrspace(1)* %out, double %src) nounwind { - %rsq_clamped = call double @llvm.AMDGPU.rsq.clamped.f64(double %src) nounwind readnone - store double %rsq_clamped, double addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll deleted file mode 100644 index eeff2536b232..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.clamped.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - - -declare float @llvm.AMDGPU.rsq.clamped.f32(float) nounwind readnone - -; FUNC-LABEL: {{^}}rsq_clamped_f32: -; SI: v_rsq_clamp_f32_e32 - -; VI: v_rsq_f32_e32 [[RSQ:v[0-9]+]], {{s[0-9]+}} -; VI: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]] -; TODO: this constant should be folded: -; VI: v_mov_b32_e32 [[MINFLT:v[0-9]+]], 0xff7fffff -; VI: v_max_f32_e32 {{v[0-9]+}}, [[MIN]], [[MINFLT]] - -; EG: RECIPSQRT_CLAMPED - -define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind { - %rsq_clamped = call float @llvm.AMDGPU.rsq.clamped.f32(float %src) nounwind readnone - store float %rsq_clamped, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll deleted file mode 100644 index 36b72f14db19..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.rsq.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -declare float @llvm.AMDGPU.rsq.f32(float) nounwind readnone - -; FUNC-LABEL: {{^}}rsq_f32: -; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} -; EG: RECIPSQRT_IEEE -define void @rsq_f32(float addrspace(1)* %out, float %src) nounwind { - %rsq = call float @llvm.AMDGPU.rsq.f32(float %src) nounwind readnone - store float %rsq, float addrspace(1)* %out, align 4 - ret void -} - -; TODO: Really these should be constant folded -; FUNC-LABEL: {{^}}rsq_f32_constant_4.0 -; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0 -; EG: RECIPSQRT_IEEE -define void @rsq_f32_constant_4.0(float addrspace(1)* %out) nounwind { - %rsq = call float @llvm.AMDGPU.rsq.f32(float 4.0) nounwind readnone - store float %rsq, float addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}rsq_f32_constant_100.0 -; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000 -; EG: RECIPSQRT_IEEE -define void @rsq_f32_constant_100.0(float addrspace(1)* %out) nounwind { - %rsq = call float @llvm.AMDGPU.rsq.f32(float 100.0) nounwind readnone - store float %rsq, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.tex.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.tex.ll deleted file mode 100644 index 10206609bb57..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.tex.ll +++ /dev/null @@ -1,42 +0,0 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s - -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:UUNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYYW}} RID:0 SID:0 CT:NNUN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYYZ}} RID:0 SID:0 CT:NNUN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN -;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN -;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN - -define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { - %addr = load <4 x float>, <4 x float> addrspace(1)* %in - %res1 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %addr, i32 0, i32 0, i32 1) - %res2 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res1, i32 0, i32 0, i32 2) - %res3 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res2, i32 0, i32 0, i32 3) - %res4 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res3, i32 0, i32 0, i32 4) - %res5 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res4, i32 0, i32 0, i32 5) - %res6 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res5, i32 0, i32 0, i32 6) - %res7 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res6, i32 0, i32 0, i32 7) - %res8 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res7, i32 0, i32 0, i32 8) - %res9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res8, i32 0, i32 0, i32 9) - %res10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res9, i32 0, i32 0, i32 10) - %res11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res10, i32 0, i32 0, i32 11) - %res12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res11, i32 0, i32 0, i32 12) - %res13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res12, i32 0, i32 0, i32 13) - %res14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res13, i32 0, i32 0, i32 14) - %res15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res14, i32 0, i32 0, i32 15) - %res16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %res15, i32 0, i32 0, i32 16) - store <4 x float> %res16, <4 x float> addrspace(1)* %out - ret void -} - -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.trig_preop.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.trig_preop.ll deleted file mode 100644 index 6b546a7e17c1..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.trig_preop.ll +++ /dev/null @@ -1,30 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s - -declare double @llvm.AMDGPU.trig.preop.f64(double, i32) nounwind readnone - -; SI-LABEL: {{^}}test_trig_preop_f64: -; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]] -; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], -; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]] -; SI: buffer_store_dwordx2 [[RESULT]], -; SI: s_endpgm -define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %a = load double, double addrspace(1)* %aptr, align 8 - %b = load i32, i32 addrspace(1)* %bptr, align 4 - %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 %b) nounwind readnone - store double %result, double addrspace(1)* %out, align 8 - ret void -} - -; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment: -; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], -; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7 -; SI: buffer_store_dwordx2 [[RESULT]], -; SI: s_endpgm -define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { - %a = load double, double addrspace(1)* %aptr, align 8 - %result = call double @llvm.AMDGPU.trig.preop.f64(double %a, i32 7) nounwind readnone - store double %result, double addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.trunc.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.trunc.ll deleted file mode 100644 index a30a8e083eb6..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.trunc.ll +++ /dev/null @@ -1,17 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s - -; R600: {{^}}amdgpu_trunc: -; R600: TRUNC {{\*? *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z -; SI: {{^}}amdgpu_trunc: -; SI: v_trunc_f32 - -define void @amdgpu_trunc(float addrspace(1)* %out, float %x) { -entry: - %0 = call float @llvm.AMDGPU.trunc(float %x) - store float %0, float addrspace(1)* %out - ret void -} - -declare float @llvm.AMDGPU.trunc(float ) readnone diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll deleted file mode 100644 index 77a073b0cb03..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.umad24.ll +++ /dev/null @@ -1,38 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=rv770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.umad24(i32, i32, i32) nounwind readnone -declare i32 @llvm.r600.read.tidig.x() nounwind readnone - -; FUNC-LABEL: {{^}}test_umad24: -; SI: v_mad_u32_u24 -; EG: MULADD_UINT24 -; R600: MULLO_UINT -; R600: ADD_INT -define void @test_umad24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { - %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 %src1, i32 %src2) nounwind readnone - store i32 %mad, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}commute_umad24: -; SI-DAG: buffer_load_dword [[SRC0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} -; SI-DAG: buffer_load_dword [[SRC2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; SI: v_mad_u32_u24 [[RESULT:v[0-9]+]], 4, [[SRC0]], [[SRC2]] -; SI: buffer_store_dword [[RESULT]] -define void @commute_umad24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %src0.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %src2.gep = getelementptr i32, i32 addrspace(1)* %src0.gep, i32 1 - - %src0 = load i32, i32 addrspace(1)* %src0.gep, align 4 - %src2 = load i32, i32 addrspace(1)* %src2.gep, align 4 - %mad = call i32 @llvm.AMDGPU.umad24(i32 %src0, i32 4, i32 %src2) nounwind readnone - store i32 %mad, i32 addrspace(1)* %out.gep, align 4 - ret void -} - diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll deleted file mode 100644 index a97d103016d3..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.umax.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_umax: -; SI: v_max_u32_e32 -define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_umax: -; SI: s_max_u32 -define void @scalar_umax(i32 %p0, i32 %p1) #0 { -entry: - %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) - %bc = bitcast i32 %max to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}trunc_zext_umax: -; SI: buffer_load_ubyte [[VREG:v[0-9]+]], -; SI: v_max_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: and -; SI: buffer_store_short [[RESULT]], -define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { - %tmp5 = load i8, i8 addrspace(1)* %src, align 1 - %tmp2 = zext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone - %tmp4 = trunc i32 %tmp3 to i8 - %tmp6 = zext i8 %tmp4 to i16 - store i16 %tmp6, i16 addrspace(1)* %out, align 2 - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.umax(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll deleted file mode 100644 index 2acd10e0c631..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.umin.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=SI %s - -; SI-LABEL: {{^}}vector_umin: -; SI: v_min_u32_e32 -define void @vector_umin(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { -main_body: - %load = load i32, i32 addrspace(1)* %in, align 4 - %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %load) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}scalar_umin: -; SI: s_min_u32 -define void @scalar_umin(i32 %p0, i32 %p1) #0 { -entry: - %min = call i32 @llvm.AMDGPU.umin(i32 %p0, i32 %p1) - %bc = bitcast i32 %min to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) - ret void -} - -; SI-LABEL: {{^}}trunc_zext_umin: -; SI: buffer_load_ubyte [[VREG:v[0-9]+]], -; SI: v_min_u32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] -; SI-NOT: and -; SI: buffer_store_short [[RESULT]], -define void @trunc_zext_umin(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { - %tmp5 = load i8, i8 addrspace(1)* %src, align 1 - %tmp2 = zext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.umin(i32 %tmp2, i32 0) nounwind readnone - %tmp4 = trunc i32 %tmp3 to i8 - %tmp6 = zext i8 %tmp4 to i16 - store i16 %tmp6, i16 addrspace(1)* %out, align 2 - ret void -} - -; Function Attrs: readnone -declare i32 @llvm.AMDGPU.umin(i32, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { nounwind } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.AMDGPU.umul24.ll b/test/CodeGen/AMDGPU/llvm.AMDGPU.umul24.ll deleted file mode 100644 index 76624a078b3a..000000000000 --- a/test/CodeGen/AMDGPU/llvm.AMDGPU.umul24.ll +++ /dev/null @@ -1,18 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=r600 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s -; XUN: llc -march=r600 -mcpu=r770 -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s - -declare i32 @llvm.AMDGPU.umul24(i32, i32) nounwind readnone - -; FUNC-LABEL: {{^}}test_umul24: -; SI: v_mul_u32_u24 -; R600: MUL_UINT24 -; R600: MULLO_UINT -define void @test_umul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1) nounwind { - %mul = call i32 @llvm.AMDGPU.umul24(i32 %src0, i32 %src1) nounwind readnone - store i32 %mul, i32 addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll b/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll index fdc324087015..ca1faebb77e7 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll @@ -10,7 +10,7 @@ ;GCN: v_interp_p1_f32 ;GCN: v_interp_p2_f32 -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { +define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) { main_body: %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4) @@ -25,7 +25,7 @@ main_body: ; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug: ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]] -define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { +define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) { main_body: %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7) %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) @@ -42,19 +42,18 @@ main_body: } ; Function Attrs: readnone -declare float @fabs(float) #2 +declare float @fabs(float) #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.SI.packf16(float, float) #1 +declare i32 @llvm.SI.packf16(float, float) #0 ; Function Attrs: nounwind readnone -declare float @llvm.SI.fs.constant(i32, i32, i32) #1 +declare float @llvm.SI.fs.constant(i32, i32, i32) #0 ; Function Attrs: nounwind readnone -declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } -attributes #2 = { readnone } +attributes #0 = { nounwind readnone } +attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.gather4.ll b/test/CodeGen/AMDGPU/llvm.SI.gather4.ll index 275cb580bc9b..aef9f660436e 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.gather4.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.gather4.ll @@ -2,10 +2,10 @@ ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}gather4_v2: -;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_v2() #0 { +;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_v2() { main_body: - %r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -15,10 +15,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4: -;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4() #0 { +;CHECK: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4() { main_body: - %r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -28,10 +28,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl: -;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_cl() #0 { +;CHECK: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_cl() { main_body: - %r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -41,10 +41,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l: -;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_l() #0 { +;CHECK: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_l() { main_body: - %r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -54,10 +54,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b: -;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b() #0 { +;CHECK: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -67,10 +67,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl: -;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b_cl() #0 { +;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b_cl() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -80,10 +80,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl_v8: -;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b_cl_v8() #0 { +;CHECK: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b_cl_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -93,10 +93,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz_v2: -;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_lz_v2() #0 { +;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_lz_v2() { main_body: - %r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -106,10 +106,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz: -;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_lz() #0 { +;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_lz() { main_body: - %r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -121,10 +121,10 @@ main_body: ;CHECK-LABEL: {{^}}gather4_o: -;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_o() #0 { +;CHECK: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -134,10 +134,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl_o: -;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_cl_o() #0 { +;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_cl_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -147,10 +147,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_cl_o_v8: -;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_cl_o_v8() #0 { +;CHECK: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_cl_o_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -160,10 +160,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l_o: -;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_l_o() #0 { +;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_l_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -173,10 +173,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_l_o_v8: -;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_l_o_v8() #0 { +;CHECK: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_l_o_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -186,10 +186,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_o: -;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b_o() #0 { +;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -199,10 +199,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_o_v8: -;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b_o_v8() #0 { +;CHECK: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b_o_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -212,10 +212,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_b_cl_o: -;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_b_cl_o() #0 { +;CHECK: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_b_cl_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -225,10 +225,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_lz_o: -;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_lz_o() #0 { +;CHECK: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_lz_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -240,10 +240,10 @@ main_body: ;CHECK-LABEL: {{^}}gather4_c: -;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c() #0 { +;CHECK: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -253,10 +253,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl: -;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_cl() #0 { +;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_cl() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -266,10 +266,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl_v8: -;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_cl_v8() #0 { +;CHECK: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_cl_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -279,10 +279,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l: -;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_l() #0 { +;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_l() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -292,10 +292,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l_v8: -;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_l_v8() #0 { +;CHECK: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_l_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -305,10 +305,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b: -;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_b() #0 { +;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_b() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -318,10 +318,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_v8: -;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_b_v8() #0 { +;CHECK: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_b_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -331,10 +331,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_cl: -;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_b_cl() #0 { +;CHECK: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_b_cl() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -344,10 +344,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz: -;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_lz() #0 { +;CHECK: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_lz() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -359,10 +359,10 @@ main_body: ;CHECK-LABEL: {{^}}gather4_c_o: -;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_o() #0 { +;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -372,10 +372,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_o_v8: -;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_o_v8() #0 { +;CHECK: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_o_v8() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -385,10 +385,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_cl_o: -;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_cl_o() #0 { +;CHECK: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_cl_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -398,10 +398,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_l_o: -;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_l_o() #0 { +;CHECK: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_l_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -411,10 +411,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_o: -;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_b_o() #0 { +;CHECK: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_b_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -424,10 +424,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_b_cl_o: -;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_b_cl_o() #0 { +;CHECK: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_b_cl_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -437,10 +437,10 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz_o: -;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_lz_o() #0 { +;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_lz_o() { main_body: - %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 %r2 = extractelement <4 x float> %r, i32 2 @@ -450,60 +450,76 @@ main_body: } ;CHECK-LABEL: {{^}}gather4_c_lz_o_v8: -;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 1, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @gather4_c_lz_o_v8() #0 { -main_body: - %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) - %r0 = extractelement <4 x float> %r, i32 0 - %r1 = extractelement <4 x float> %r, i32 1 - %r2 = extractelement <4 x float> %r, i32 2 - %r3 = extractelement <4 x float> %r, i32 3 - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) - ret void -} - - - -declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 - -declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 - -declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 - -declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +;CHECK: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define amdgpu_ps void @gather4_c_lz_o_v8() { +main_body: + %r = call <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r0 = extractelement <4 x float> %r, i32 0 + %r1 = extractelement <4 x float> %r, i32 1 + %r2 = extractelement <4 x float> %r, i32 2 + %r3 = extractelement <4 x float> %r, i32 3 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) + ret void +} + +;CHECK-LABEL: {{^}}gather4_sgpr_bug: +; +; This crashed at some point due to a bug in FixSGPRCopies. Derived from the +; report in https://bugs.freedesktop.org/show_bug.cgi?id=96877 +; +;CHECK: s_load_dwordx4 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 +;CHECK: s_waitcnt lgkmcnt(0) +;CHECK: s_mov_b32 s[[LO]], 0 +;CHECK: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]] dmask:0x8 +define amdgpu_ps float @gather4_sgpr_bug() { +main_body: + %tmp = load <4 x i32>, <4 x i32> addrspace(2)* undef, align 16 + %tmp1 = insertelement <4 x i32> %tmp, i32 0, i32 0 + %tmp2 = call <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> %tmp1, i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp4 = extractelement <4 x float> %tmp2, i32 1 + %tmp9 = fadd float undef, %tmp4 + ret float %tmp9 +} + +declare <4 x float> @llvm.SI.gather4.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.lz.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +declare <4 x float> @llvm.SI.gather4.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.l.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.b.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +declare <4 x float> @llvm.SI.gather4.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.l.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.b.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.b.cl.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +declare <4 x float> @llvm.SI.gather4.c.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.l.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.b.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.b.cl.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.gather4.c.lz.o.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.getlod.ll b/test/CodeGen/AMDGPU/llvm.SI.getlod.ll index 06ee98e91b31..ac34d31b97c1 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.getlod.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.getlod.ll @@ -2,10 +2,10 @@ ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}getlod: -;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @getlod() #0 { +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da +define amdgpu_ps void @getlod() { main_body: - %r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.getlod.i32(i32 undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1) @@ -13,10 +13,10 @@ main_body: } ;CHECK-LABEL: {{^}}getlod_v2: -;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @getlod_v2() #0 { +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da +define amdgpu_ps void @getlod_v2() { main_body: - %r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.getlod.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1) @@ -24,10 +24,10 @@ main_body: } ;CHECK-LABEL: {{^}}getlod_v4: -;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, -1, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @getlod_v4() #0 { +;CHECK: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x3 da +define amdgpu_ps void @getlod_v4() { main_body: - %r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) + %r = call <4 x float> @llvm.SI.getlod.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 1, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 %r1 = extractelement <4 x float> %r, i32 1 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r0, float %r1) @@ -35,11 +35,10 @@ main_body: } -declare <4 x float> @llvm.SI.getlod.i32(i32, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.getlod.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.getlod.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.getlod.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.getlod.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.getlod.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.image.ll b/test/CodeGen/AMDGPU/llvm.SI.image.ll index 0fac8d799562..50341e3e207f 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.image.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.image.ll @@ -2,8 +2,8 @@ ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s ;CHECK-LABEL: {{^}}image_load: -;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @image_load() #0 { +;CHECK: image_load {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @image_load() { main_body: %r = call <4 x float> @llvm.SI.image.load.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -15,8 +15,8 @@ main_body: } ;CHECK-LABEL: {{^}}image_load_mip: -;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @image_load_mip() #0 { +;CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @image_load_mip() { main_body: %r = call <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32> undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -28,8 +28,8 @@ main_body: } ;CHECK-LABEL: {{^}}getresinfo: -;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} -define void @getresinfo() #0 { +;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @getresinfo() { main_body: %r = call <4 x float> @llvm.SI.getresinfo.i32(i32 undef, <8 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -40,11 +40,10 @@ main_body: ret void } -declare <4 x float> @llvm.SI.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.getresinfo.i32(i32, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.getresinfo.i32(i32, <8 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll b/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll new file mode 100644 index 000000000000..7cdd9559994e --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.SI.image.sample-masked.ll @@ -0,0 +1,94 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s + +; CHECK-LABEL: {{^}}v1: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xd +define amdgpu_ps void @v1(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 2 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: {{^}}v2: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xb +define amdgpu_ps void @v2(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 1 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: {{^}}v3: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xe +define amdgpu_ps void @v3(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 2 + %4 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: {{^}}v4: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x7 +define amdgpu_ps void @v4(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 1 + %4 = extractelement <4 x float> %1, i32 2 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) + ret void +} + +; CHECK-LABEL: {{^}}v5: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xa +define amdgpu_ps void @v5(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +; CHECK-LABEL: {{^}}v6: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x6 +define amdgpu_ps void @v6(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 1 + %3 = extractelement <4 x float> %1, i32 2 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +; CHECK-LABEL: {{^}}v7: +; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x9 +define amdgpu_ps void @v7(i32 %a1) { +entry: + %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 + %1 = call <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32> %0, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %2 = extractelement <4 x float> %1, i32 0 + %3 = extractelement <4 x float> %1, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) + ret void +} + +declare <4 x float> @llvm.SI.image.sample.v1i32(<1 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) readnone + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/AMDGPU/llvm.SI.image.sample.ll b/test/CodeGen/AMDGPU/llvm.SI.image.sample.ll index 4bc638a28063..60077dc218fd 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.image.sample.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.image.sample.ll @@ -3,8 +3,8 @@ ;CHECK-LABEL: {{^}}sample: ;CHECK: s_wqm -;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample() #0 { +;CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample() { main_body: %r = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -17,8 +17,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cl: ;CHECK: s_wqm -;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cl() #0 { +;CHECK: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -31,8 +31,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_d: ;CHECK-NOT: s_wqm -;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_d() #0 { +;CHECK: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_d() { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -45,8 +45,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_d_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_d_cl() #0 { +;CHECK: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_d_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -59,8 +59,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_l: ;CHECK-NOT: s_wqm -;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_l() #0 { +;CHECK: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_l() { main_body: %r = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -73,8 +73,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_b: ;CHECK: s_wqm -;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_b() #0 { +;CHECK: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_b() { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -87,8 +87,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_b_cl: ;CHECK: s_wqm -;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_b_cl() #0 { +;CHECK: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_b_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -101,8 +101,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_lz: ;CHECK-NOT: s_wqm -;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_lz() #0 { +;CHECK: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_lz() { main_body: %r = call <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -115,8 +115,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cd: ;CHECK-NOT: s_wqm -;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cd() #0 { +;CHECK: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cd() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -129,8 +129,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cd_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cd_cl() #0 { +;CHECK: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cd_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -143,8 +143,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c: ;CHECK: s_wqm -;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c() #0 { +;CHECK: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -157,8 +157,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cl: ;CHECK: s_wqm -;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cl() #0 { +;CHECK: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -171,8 +171,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_d: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_d() #0 { +;CHECK: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_d() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -185,8 +185,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_d_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_d_cl() #0 { +;CHECK: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_d_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -199,8 +199,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_l: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_l() #0 { +;CHECK: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_l() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -213,8 +213,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_b: ;CHECK: s_wqm -;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_b() #0 { +;CHECK: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_b() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -227,8 +227,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_b_cl: ;CHECK: s_wqm -;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_b_cl() #0 { +;CHECK: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_b_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -241,8 +241,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_lz: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_lz() #0 { +;CHECK: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_lz() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -255,8 +255,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cd: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cd() #0 { +;CHECK: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cd() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -269,8 +269,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cd_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cd_cl() #0 { +;CHECK: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cd_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -282,29 +282,28 @@ main_body: } -declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 -declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.d.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.d.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.b.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.lz.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cd.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cd.cl.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll b/test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll index 9d8935414ed9..34d4f6825690 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.image.sample.o.ll @@ -3,8 +3,8 @@ ;CHECK-LABEL: {{^}}sample: ;CHECK: s_wqm -;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample() #0 { +;CHECK: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample() { main_body: %r = call <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -17,8 +17,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cl: ;CHECK: s_wqm -;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cl() #0 { +;CHECK: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -31,8 +31,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_d: ;CHECK-NOT: s_wqm -;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_d() #0 { +;CHECK: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_d() { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -45,8 +45,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_d_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_d_cl() #0 { +;CHECK: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_d_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -59,8 +59,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_l: ;CHECK-NOT: s_wqm -;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_l() #0 { +;CHECK: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_l() { main_body: %r = call <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -73,8 +73,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_b: ;CHECK: s_wqm -;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_b() #0 { +;CHECK: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_b() { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -87,8 +87,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_b_cl: ;CHECK: s_wqm -;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_b_cl() #0 { +;CHECK: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_b_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -101,8 +101,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_lz: ;CHECK-NOT: s_wqm -;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_lz() #0 { +;CHECK: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_lz() { main_body: %r = call <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -115,8 +115,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cd: ;CHECK-NOT: s_wqm -;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cd() #0 { +;CHECK: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cd() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -129,8 +129,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_cd_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_cd_cl() #0 { +;CHECK: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_cd_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -143,8 +143,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c: ;CHECK: s_wqm -;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c() #0 { +;CHECK: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -157,8 +157,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cl: ;CHECK: s_wqm -;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cl() #0 { +;CHECK: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -171,8 +171,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_d: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_d() #0 { +;CHECK: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_d() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -185,8 +185,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_d_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_d_cl() #0 { +;CHECK: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_d_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -199,8 +199,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_l: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_l() #0 { +;CHECK: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_l() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -213,8 +213,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_b: ;CHECK: s_wqm -;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_b() #0 { +;CHECK: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_b() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -227,8 +227,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_b_cl: ;CHECK: s_wqm -;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_b_cl() #0 { +;CHECK: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_b_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -241,8 +241,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_lz: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_lz() #0 { +;CHECK: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_lz() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -255,8 +255,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cd: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cd() #0 { +;CHECK: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cd() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -269,8 +269,8 @@ main_body: ;CHECK-LABEL: {{^}}sample_c_cd_cl: ;CHECK-NOT: s_wqm -;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} -define void @sample_c_cd_cl() #0 { +;CHECK: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @sample_c_cd_cl() { main_body: %r = call <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %r0 = extractelement <4 x float> %r, i32 0 @@ -282,29 +282,28 @@ main_body: } -declare <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.image.sample.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 -declare <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 -declare <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare <4 x float> @llvm.SI.image.sample.c.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.d.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.d.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.l.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.b.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.b.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.lz.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cd.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 +declare <4 x float> @llvm.SI.image.sample.c.cd.cl.o.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.imageload.ll b/test/CodeGen/AMDGPU/llvm.SI.imageload.ll deleted file mode 100644 index b67716c3b665..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.imageload.ll +++ /dev/null @@ -1,132 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s - -;CHECK-DAG: image_load {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 -;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v[0-9]+}}, 2, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v[0-9]+}}, 1, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v[0-9]+}}, 4, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v[0-9]+}}, 8, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 -;CHECK-DAG: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 -;CHECK-DAG: image_load_mip {{v[0-9]+}}, 8, 0, 0, -1 - -define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) { - %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 - %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 - %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 - %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 - %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 - %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 - %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 - %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 - %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 - %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 - %res1 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v1, - <32 x i8> undef, i32 1) - %res2 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v2, - <32 x i8> undef, i32 2) - %res3 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v3, - <32 x i8> undef, i32 3) - %res4 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v4, - <32 x i8> undef, i32 4) - %res5 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v5, - <32 x i8> undef, i32 5) - %res6 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v6, - <32 x i8> undef, i32 6) - %res10 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v10, - <32 x i8> undef, i32 10) - %res11 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v11, - <32 x i8> undef, i32 11) - %res15 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v15, - <32 x i8> undef, i32 15) - %res16 = call <4 x i32> @llvm.SI.imageload.(<4 x i32> %v16, - <32 x i8> undef, i32 16) - %e1 = extractelement <4 x i32> %res1, i32 0 - %e2 = extractelement <4 x i32> %res2, i32 1 - %e3 = extractelement <4 x i32> %res3, i32 2 - %e4 = extractelement <4 x i32> %res4, i32 3 - %t0 = extractelement <4 x i32> %res5, i32 0 - %t1 = extractelement <4 x i32> %res5, i32 1 - %e5 = add i32 %t0, %t1 - %t2 = extractelement <4 x i32> %res6, i32 0 - %t3 = extractelement <4 x i32> %res6, i32 2 - %e6 = add i32 %t2, %t3 - %t10 = extractelement <4 x i32> %res10, i32 2 - %t11 = extractelement <4 x i32> %res10, i32 3 - %e10 = add i32 %t10, %t11 - %t12 = extractelement <4 x i32> %res11, i32 0 - %t13 = extractelement <4 x i32> %res11, i32 1 - %t14 = extractelement <4 x i32> %res11, i32 2 - %t15 = add i32 %t12, %t13 - %e11 = add i32 %t14, %t15 - %t28 = extractelement <4 x i32> %res15, i32 0 - %t29 = extractelement <4 x i32> %res15, i32 1 - %t30 = extractelement <4 x i32> %res15, i32 2 - %t31 = extractelement <4 x i32> %res15, i32 3 - %t32 = add i32 %t28, %t29 - %t33 = add i32 %t30, %t31 - %e15 = add i32 %t32, %t33 - %e16 = extractelement <4 x i32> %res16, i32 3 - %s1 = add i32 %e1, %e2 - %s2 = add i32 %s1, %e3 - %s3 = add i32 %s2, %e4 - %s4 = add i32 %s3, %e5 - %s5 = add i32 %s4, %e6 - %s9 = add i32 %s5, %e10 - %s10 = add i32 %s9, %e11 - %s14 = add i32 %s10, %e15 - %s15 = add i32 %s14, %e16 - %s16 = bitcast i32 %s15 to float - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s16, float %s16, float %s16, float %s16) - ret void -} - -; Test that ccordinates are stored in vgprs and not sgprs -; CHECK: vgpr_coords -; CHECK: image_load_mip {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, 0, 0, 0, 0, 0, {{v\[[0-9]+:[0-9]+\]}} -define void @vgpr_coords(float addrspace(2)* addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { -main_body: - %20 = getelementptr float addrspace(2)*, float addrspace(2)* addrspace(2)* %0, i32 0 - %21 = load float addrspace(2)*, float addrspace(2)* addrspace(2)* %20, !tbaa !2 - %22 = getelementptr float, float addrspace(2)* %21, i32 0 - %23 = load float, float addrspace(2)* %22, !tbaa !2, !invariant.load !1 - %24 = getelementptr float, float addrspace(2)* %21, i32 1 - %25 = load float, float addrspace(2)* %24, !tbaa !2, !invariant.load !1 - %26 = getelementptr float, float addrspace(2)* %21, i32 4 - %27 = load float, float addrspace(2)* %26, !tbaa !2, !invariant.load !1 - %28 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0 - %29 = load <32 x i8>, <32 x i8> addrspace(2)* %28, !tbaa !2 - %30 = bitcast float %27 to i32 - %31 = bitcast float %23 to i32 - %32 = bitcast float %25 to i32 - %33 = insertelement <4 x i32> undef, i32 %31, i32 0 - %34 = insertelement <4 x i32> %33, i32 %32, i32 1 - %35 = insertelement <4 x i32> %34, i32 %30, i32 2 - %36 = insertelement <4 x i32> %35, i32 undef, i32 3 - %37 = call <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32> %36, <32 x i8> %29, i32 2) - %38 = extractelement <4 x i32> %37, i32 0 - %39 = extractelement <4 x i32> %37, i32 1 - %40 = extractelement <4 x i32> %37, i32 2 - %41 = extractelement <4 x i32> %37, i32 3 - %42 = bitcast i32 %38 to float - %43 = bitcast i32 %39 to float - %44 = bitcast i32 %40 to float - %45 = bitcast i32 %41 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %42, float %43, float %44, float %45) - ret void -} - -declare <4 x i32> @llvm.SI.imageload.(<4 x i32>, <32 x i8>, i32) readnone -; Function Attrs: nounwind readnone -declare <4 x i32> @llvm.SI.imageload.v4i32(<4 x i32>, <32 x i8>, i32) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } - -!0 = !{!"const", null} -!1 = !{} -!2 = !{!0, !0, i64 0, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll b/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll index f6c258539d5b..d0cc00d81b4e 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.load.dword.ll @@ -7,14 +7,14 @@ ; FIXME: Out of bounds immediate offset crashes ; CHECK-LABEL: {{^}}main: -; CHECK: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc +; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc ; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc -define void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <16 x i8>] addrspace(2)* byval %arg3, [17 x <16 x i8>] addrspace(2)* inreg %arg4, [17 x <16 x i8>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) #0 { +define amdgpu_vs void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <16 x i8>] addrspace(2)* byval %arg3, [17 x <16 x i8>] addrspace(2)* inreg %arg4, [17 x <16 x i8>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) { main_body: %tmp = getelementptr [2 x <16 x i8>], [2 x <16 x i8>] addrspace(2)* %arg3, i64 0, i32 1 %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 @@ -40,14 +40,13 @@ main_body: } ; Function Attrs: nounwind readonly -declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #0 ; Function Attrs: nounwind readonly -declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #1 +declare i32 @llvm.SI.buffer.load.dword.i32.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="1" } -attributes #1 = { nounwind readonly } +attributes #0 = { nounwind readonly } !0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.SI.packf16.ll b/test/CodeGen/AMDGPU/llvm.SI.packf16.ll index 0155757632d4..6984b4cf488a 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.packf16.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.packf16.ll @@ -6,7 +6,7 @@ ; GCN: v_cvt_pkrtz_f16_f32 ; GCN-NOT: v_cvt_pkrtz_f16_f32 -define void @main(float %src) #0 { +define amdgpu_ps void @main(float %src) { main_body: %p1 = call i32 @llvm.SI.packf16(float undef, float %src) %p2 = call i32 @llvm.SI.packf16(float %src, float undef) @@ -21,9 +21,8 @@ main_body: } ; Function Attrs: nounwind readnone -declare i32 @llvm.SI.packf16(float, float) #1 +declare i32 @llvm.SI.packf16(float, float) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.SI.resinfo.ll b/test/CodeGen/AMDGPU/llvm.SI.resinfo.ll deleted file mode 100644 index ac95fd0b83a2..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.resinfo.ll +++ /dev/null @@ -1,111 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s - -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 2, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 1, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 4, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 8, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0 -; CHECK-DAG: image_get_resinfo {{v[0-9]+}}, 8, 0, 0, -1 - -define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8, - i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) { - %res1 = call <4 x i32> @llvm.SI.resinfo(i32 %a1, <32 x i8> undef, i32 1) - %res2 = call <4 x i32> @llvm.SI.resinfo(i32 %a2, <32 x i8> undef, i32 2) - %res3 = call <4 x i32> @llvm.SI.resinfo(i32 %a3, <32 x i8> undef, i32 3) - %res4 = call <4 x i32> @llvm.SI.resinfo(i32 %a4, <32 x i8> undef, i32 4) - %res5 = call <4 x i32> @llvm.SI.resinfo(i32 %a5, <32 x i8> undef, i32 5) - %res6 = call <4 x i32> @llvm.SI.resinfo(i32 %a6, <32 x i8> undef, i32 6) - %res7 = call <4 x i32> @llvm.SI.resinfo(i32 %a7, <32 x i8> undef, i32 7) - %res8 = call <4 x i32> @llvm.SI.resinfo(i32 %a8, <32 x i8> undef, i32 8) - %res9 = call <4 x i32> @llvm.SI.resinfo(i32 %a9, <32 x i8> undef, i32 9) - %res10 = call <4 x i32> @llvm.SI.resinfo(i32 %a10, <32 x i8> undef, i32 10) - %res11 = call <4 x i32> @llvm.SI.resinfo(i32 %a11, <32 x i8> undef, i32 11) - %res12 = call <4 x i32> @llvm.SI.resinfo(i32 %a12, <32 x i8> undef, i32 12) - %res13 = call <4 x i32> @llvm.SI.resinfo(i32 %a13, <32 x i8> undef, i32 13) - %res14 = call <4 x i32> @llvm.SI.resinfo(i32 %a14, <32 x i8> undef, i32 14) - %res15 = call <4 x i32> @llvm.SI.resinfo(i32 %a15, <32 x i8> undef, i32 15) - %res16 = call <4 x i32> @llvm.SI.resinfo(i32 %a16, <32 x i8> undef, i32 16) - %e1 = extractelement <4 x i32> %res1, i32 0 - %e2 = extractelement <4 x i32> %res2, i32 1 - %e3 = extractelement <4 x i32> %res3, i32 2 - %e4 = extractelement <4 x i32> %res4, i32 3 - %t0 = extractelement <4 x i32> %res5, i32 0 - %t1 = extractelement <4 x i32> %res5, i32 1 - %e5 = add i32 %t0, %t1 - %t2 = extractelement <4 x i32> %res6, i32 0 - %t3 = extractelement <4 x i32> %res6, i32 2 - %e6 = add i32 %t2, %t3 - %t4 = extractelement <4 x i32> %res7, i32 0 - %t5 = extractelement <4 x i32> %res7, i32 3 - %e7 = add i32 %t4, %t5 - %t6 = extractelement <4 x i32> %res8, i32 1 - %t7 = extractelement <4 x i32> %res8, i32 2 - %e8 = add i32 %t6, %t7 - %t8 = extractelement <4 x i32> %res9, i32 1 - %t9 = extractelement <4 x i32> %res9, i32 3 - %e9 = add i32 %t8, %t9 - %t10 = extractelement <4 x i32> %res10, i32 2 - %t11 = extractelement <4 x i32> %res10, i32 3 - %e10 = add i32 %t10, %t11 - %t12 = extractelement <4 x i32> %res11, i32 0 - %t13 = extractelement <4 x i32> %res11, i32 1 - %t14 = extractelement <4 x i32> %res11, i32 2 - %t15 = add i32 %t12, %t13 - %e11 = add i32 %t14, %t15 - %t16 = extractelement <4 x i32> %res12, i32 0 - %t17 = extractelement <4 x i32> %res12, i32 1 - %t18 = extractelement <4 x i32> %res12, i32 3 - %t19 = add i32 %t16, %t17 - %e12 = add i32 %t18, %t19 - %t20 = extractelement <4 x i32> %res13, i32 0 - %t21 = extractelement <4 x i32> %res13, i32 2 - %t22 = extractelement <4 x i32> %res13, i32 3 - %t23 = add i32 %t20, %t21 - %e13 = add i32 %t22, %t23 - %t24 = extractelement <4 x i32> %res14, i32 1 - %t25 = extractelement <4 x i32> %res14, i32 2 - %t26 = extractelement <4 x i32> %res14, i32 3 - %t27 = add i32 %t24, %t25 - %e14 = add i32 %t26, %t27 - %t28 = extractelement <4 x i32> %res15, i32 0 - %t29 = extractelement <4 x i32> %res15, i32 1 - %t30 = extractelement <4 x i32> %res15, i32 2 - %t31 = extractelement <4 x i32> %res15, i32 3 - %t32 = add i32 %t28, %t29 - %t33 = add i32 %t30, %t31 - %e15 = add i32 %t32, %t33 - %e16 = extractelement <4 x i32> %res16, i32 3 - %s1 = add i32 %e1, %e2 - %s2 = add i32 %s1, %e3 - %s3 = add i32 %s2, %e4 - %s4 = add i32 %s3, %e5 - %s5 = add i32 %s4, %e6 - %s6 = add i32 %s5, %e7 - %s7 = add i32 %s6, %e8 - %s8 = add i32 %s7, %e9 - %s9 = add i32 %s8, %e10 - %s10 = add i32 %s9, %e11 - %s11 = add i32 %s10, %e12 - %s12 = add i32 %s11, %e13 - %s13 = add i32 %s12, %e14 - %s14 = add i32 %s13, %e15 - %s15 = add i32 %s14, %e16 - %s16 = bitcast i32 %s15 to float - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s16, float %s16, float %s16, float %s16) - ret void -} - -declare <4 x i32> @llvm.SI.resinfo(i32, <32 x i8>, i32) readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/AMDGPU/llvm.SI.sample-masked.ll b/test/CodeGen/AMDGPU/llvm.SI.sample-masked.ll deleted file mode 100644 index ce9558cbf81d..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.sample-masked.ll +++ /dev/null @@ -1,96 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s - -; CHECK-LABEL: {{^}}v1: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 13 -define void @v1(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 0 - %3 = extractelement <4 x float> %1, i32 2 - %4 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) - ret void -} - -; CHECK-LABEL: {{^}}v2: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 11 -define void @v2(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 0 - %3 = extractelement <4 x float> %1, i32 1 - %4 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) - ret void -} - -; CHECK-LABEL: {{^}}v3: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14 -define void @v3(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 1 - %3 = extractelement <4 x float> %1, i32 2 - %4 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) - ret void -} - -; CHECK-LABEL: {{^}}v4: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 7 -define void @v4(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 0 - %3 = extractelement <4 x float> %1, i32 1 - %4 = extractelement <4 x float> %1, i32 2 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %4) - ret void -} - -; CHECK-LABEL: {{^}}v5: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10 -define void @v5(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 1 - %3 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) - ret void -} - -; CHECK-LABEL: {{^}}v6: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 6 -define void @v6(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 1 - %3 = extractelement <4 x float> %1, i32 2 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) - ret void -} - -; CHECK-LABEL: {{^}}v7: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 9 -define void @v7(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 0 - %3 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %3, float %3) - ret void -} - -declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/llvm.SI.sample.ll b/test/CodeGen/AMDGPU/llvm.SI.sample.ll deleted file mode 100644 index 509c45f588b8..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.sample.ll +++ /dev/null @@ -1,160 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s - -;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15 -;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 3 -;CHECK-DAG: image_sample {{v[0-9]+}}, 2 -;CHECK-DAG: image_sample {{v[0-9]+}}, 1 -;CHECK-DAG: image_sample {{v[0-9]+}}, 4 -;CHECK-DAG: image_sample {{v[0-9]+}}, 8 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 5 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 9 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 6 -;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 10 -;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 12 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 7 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 11 -;CHECK-DAG: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, 13 -;CHECK-DAG: image_sample {{v\[[0-9]+:[0-9]+\]}}, 14 -;CHECK-DAG: image_sample {{v[0-9]+}}, 8 - -define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 { - %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 - %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 - %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 - %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 - %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 - %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 - %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2 - %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3 - %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0 - %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 - %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 - %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3 - %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0 - %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 - %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 - %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 - %res1 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v1, - <32 x i8> undef, <16 x i8> undef, i32 1) - %res2 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v2, - <32 x i8> undef, <16 x i8> undef, i32 2) - %res3 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v3, - <32 x i8> undef, <16 x i8> undef, i32 3) - %res4 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v4, - <32 x i8> undef, <16 x i8> undef, i32 4) - %res5 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v5, - <32 x i8> undef, <16 x i8> undef, i32 5) - %res6 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v6, - <32 x i8> undef, <16 x i8> undef, i32 6) - %res7 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v7, - <32 x i8> undef, <16 x i8> undef, i32 7) - %res8 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v8, - <32 x i8> undef, <16 x i8> undef, i32 8) - %res9 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v9, - <32 x i8> undef, <16 x i8> undef, i32 9) - %res10 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v10, - <32 x i8> undef, <16 x i8> undef, i32 10) - %res11 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v11, - <32 x i8> undef, <16 x i8> undef, i32 11) - %res12 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v12, - <32 x i8> undef, <16 x i8> undef, i32 12) - %res13 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v13, - <32 x i8> undef, <16 x i8> undef, i32 13) - %res14 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v14, - <32 x i8> undef, <16 x i8> undef, i32 14) - %res15 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v15, - <32 x i8> undef, <16 x i8> undef, i32 15) - %res16 = call <4 x float> @llvm.SI.sample.(<4 x i32> %v16, - <32 x i8> undef, <16 x i8> undef, i32 16) - %e1 = extractelement <4 x float> %res1, i32 0 - %e2 = extractelement <4 x float> %res2, i32 1 - %e3 = extractelement <4 x float> %res3, i32 2 - %e4 = extractelement <4 x float> %res4, i32 3 - %t0 = extractelement <4 x float> %res5, i32 0 - %t1 = extractelement <4 x float> %res5, i32 1 - %e5 = fadd float %t0, %t1 - %t2 = extractelement <4 x float> %res6, i32 0 - %t3 = extractelement <4 x float> %res6, i32 2 - %e6 = fadd float %t2, %t3 - %t4 = extractelement <4 x float> %res7, i32 0 - %t5 = extractelement <4 x float> %res7, i32 3 - %e7 = fadd float %t4, %t5 - %t6 = extractelement <4 x float> %res8, i32 1 - %t7 = extractelement <4 x float> %res8, i32 2 - %e8 = fadd float %t6, %t7 - %t8 = extractelement <4 x float> %res9, i32 1 - %t9 = extractelement <4 x float> %res9, i32 3 - %e9 = fadd float %t8, %t9 - %t10 = extractelement <4 x float> %res10, i32 2 - %t11 = extractelement <4 x float> %res10, i32 3 - %e10 = fadd float %t10, %t11 - %t12 = extractelement <4 x float> %res11, i32 0 - %t13 = extractelement <4 x float> %res11, i32 1 - %t14 = extractelement <4 x float> %res11, i32 2 - %t15 = fadd float %t12, %t13 - %e11 = fadd float %t14, %t15 - %t16 = extractelement <4 x float> %res12, i32 0 - %t17 = extractelement <4 x float> %res12, i32 1 - %t18 = extractelement <4 x float> %res12, i32 3 - %t19 = fadd float %t16, %t17 - %e12 = fadd float %t18, %t19 - %t20 = extractelement <4 x float> %res13, i32 0 - %t21 = extractelement <4 x float> %res13, i32 2 - %t22 = extractelement <4 x float> %res13, i32 3 - %t23 = fadd float %t20, %t21 - %e13 = fadd float %t22, %t23 - %t24 = extractelement <4 x float> %res14, i32 1 - %t25 = extractelement <4 x float> %res14, i32 2 - %t26 = extractelement <4 x float> %res14, i32 3 - %t27 = fadd float %t24, %t25 - %e14 = fadd float %t26, %t27 - %t28 = extractelement <4 x float> %res15, i32 0 - %t29 = extractelement <4 x float> %res15, i32 1 - %t30 = extractelement <4 x float> %res15, i32 2 - %t31 = extractelement <4 x float> %res15, i32 3 - %t32 = fadd float %t28, %t29 - %t33 = fadd float %t30, %t31 - %e15 = fadd float %t32, %t33 - %e16 = extractelement <4 x float> %res16, i32 3 - %s1 = fadd float %e1, %e2 - %s2 = fadd float %s1, %e3 - %s3 = fadd float %s2, %e4 - %s4 = fadd float %s3, %e5 - %s5 = fadd float %s4, %e6 - %s6 = fadd float %s5, %e7 - %s7 = fadd float %s6, %e8 - %s8 = fadd float %s7, %e9 - %s9 = fadd float %s8, %e10 - %s10 = fadd float %s9, %e11 - %s11 = fadd float %s10, %e12 - %s12 = fadd float %s11, %e13 - %s13 = fadd float %s12, %e14 - %s14 = fadd float %s13, %e15 - %s15 = fadd float %s14, %e16 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15) - ret void -} - -; CHECK: {{^}}v1: -; CHECK: image_sample {{v\[[0-9]+:[0-9]+\]}}, 15 -define void @v1(i32 %a1) #0 { -entry: - %0 = insertelement <1 x i32> undef, i32 %a1, i32 0 - %1 = call <4 x float> @llvm.SI.sample.v1i32(<1 x i32> %0, <32 x i8> undef, <16 x i8> undef, i32 0) - %2 = extractelement <4 x float> %1, i32 0 - %3 = extractelement <4 x float> %1, i32 1 - %4 = extractelement <4 x float> %1, i32 2 - %5 = extractelement <4 x float> %1, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %2, float %3, float %4, float %5) - ret void -} - - -declare <4 x float> @llvm.SI.sample.v1i32(<1 x i32>, <32 x i8>, <16 x i8>, i32) readnone - -declare <4 x float> @llvm.SI.sample.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/llvm.SI.sampled.ll b/test/CodeGen/AMDGPU/llvm.SI.sampled.ll deleted file mode 100644 index f2badff2a99c..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.sampled.ll +++ /dev/null @@ -1,143 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s - -;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 15 -;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 3 -;CHECK-DAG: image_sample_d {{v[0-9]+}}, 2 -;CHECK-DAG: image_sample_d {{v[0-9]+}}, 1 -;CHECK-DAG: image_sample_d {{v[0-9]+}}, 4 -;CHECK-DAG: image_sample_d {{v[0-9]+}}, 8 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 5 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 9 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 6 -;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 10 -;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 12 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 7 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 11 -;CHECK-DAG: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, 13 -;CHECK-DAG: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, 14 -;CHECK-DAG: image_sample_d {{v[0-9]+}}, 8 - -define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4) #0 { - %v1 = insertelement <4 x i32> undef, i32 %a1, i32 0 - %v2 = insertelement <4 x i32> undef, i32 %a1, i32 1 - %v3 = insertelement <4 x i32> undef, i32 %a1, i32 2 - %v4 = insertelement <4 x i32> undef, i32 %a1, i32 3 - %v5 = insertelement <4 x i32> undef, i32 %a2, i32 0 - %v6 = insertelement <4 x i32> undef, i32 %a2, i32 1 - %v7 = insertelement <4 x i32> undef, i32 %a2, i32 2 - %v8 = insertelement <4 x i32> undef, i32 %a2, i32 3 - %v9 = insertelement <4 x i32> undef, i32 %a3, i32 0 - %v10 = insertelement <4 x i32> undef, i32 %a3, i32 1 - %v11 = insertelement <4 x i32> undef, i32 %a3, i32 2 - %v12 = insertelement <4 x i32> undef, i32 %a3, i32 3 - %v13 = insertelement <4 x i32> undef, i32 %a4, i32 0 - %v14 = insertelement <4 x i32> undef, i32 %a4, i32 1 - %v15 = insertelement <4 x i32> undef, i32 %a4, i32 2 - %v16 = insertelement <4 x i32> undef, i32 %a4, i32 3 - %res1 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v1, - <32 x i8> undef, <16 x i8> undef, i32 1) - %res2 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v2, - <32 x i8> undef, <16 x i8> undef, i32 2) - %res3 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v3, - <32 x i8> undef, <16 x i8> undef, i32 3) - %res4 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v4, - <32 x i8> undef, <16 x i8> undef, i32 4) - %res5 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v5, - <32 x i8> undef, <16 x i8> undef, i32 5) - %res6 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v6, - <32 x i8> undef, <16 x i8> undef, i32 6) - %res7 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v7, - <32 x i8> undef, <16 x i8> undef, i32 7) - %res8 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v8, - <32 x i8> undef, <16 x i8> undef, i32 8) - %res9 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v9, - <32 x i8> undef, <16 x i8> undef, i32 9) - %res10 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v10, - <32 x i8> undef, <16 x i8> undef, i32 10) - %res11 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v11, - <32 x i8> undef, <16 x i8> undef, i32 11) - %res12 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v12, - <32 x i8> undef, <16 x i8> undef, i32 12) - %res13 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v13, - <32 x i8> undef, <16 x i8> undef, i32 13) - %res14 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v14, - <32 x i8> undef, <16 x i8> undef, i32 14) - %res15 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v15, - <32 x i8> undef, <16 x i8> undef, i32 15) - %res16 = call <4 x float> @llvm.SI.sampled.(<4 x i32> %v16, - <32 x i8> undef, <16 x i8> undef, i32 16) - %e1 = extractelement <4 x float> %res1, i32 0 - %e2 = extractelement <4 x float> %res2, i32 1 - %e3 = extractelement <4 x float> %res3, i32 2 - %e4 = extractelement <4 x float> %res4, i32 3 - %t0 = extractelement <4 x float> %res5, i32 0 - %t1 = extractelement <4 x float> %res5, i32 1 - %e5 = fadd float %t0, %t1 - %t2 = extractelement <4 x float> %res6, i32 0 - %t3 = extractelement <4 x float> %res6, i32 2 - %e6 = fadd float %t2, %t3 - %t4 = extractelement <4 x float> %res7, i32 0 - %t5 = extractelement <4 x float> %res7, i32 3 - %e7 = fadd float %t4, %t5 - %t6 = extractelement <4 x float> %res8, i32 1 - %t7 = extractelement <4 x float> %res8, i32 2 - %e8 = fadd float %t6, %t7 - %t8 = extractelement <4 x float> %res9, i32 1 - %t9 = extractelement <4 x float> %res9, i32 3 - %e9 = fadd float %t8, %t9 - %t10 = extractelement <4 x float> %res10, i32 2 - %t11 = extractelement <4 x float> %res10, i32 3 - %e10 = fadd float %t10, %t11 - %t12 = extractelement <4 x float> %res11, i32 0 - %t13 = extractelement <4 x float> %res11, i32 1 - %t14 = extractelement <4 x float> %res11, i32 2 - %t15 = fadd float %t12, %t13 - %e11 = fadd float %t14, %t15 - %t16 = extractelement <4 x float> %res12, i32 0 - %t17 = extractelement <4 x float> %res12, i32 1 - %t18 = extractelement <4 x float> %res12, i32 3 - %t19 = fadd float %t16, %t17 - %e12 = fadd float %t18, %t19 - %t20 = extractelement <4 x float> %res13, i32 0 - %t21 = extractelement <4 x float> %res13, i32 2 - %t22 = extractelement <4 x float> %res13, i32 3 - %t23 = fadd float %t20, %t21 - %e13 = fadd float %t22, %t23 - %t24 = extractelement <4 x float> %res14, i32 1 - %t25 = extractelement <4 x float> %res14, i32 2 - %t26 = extractelement <4 x float> %res14, i32 3 - %t27 = fadd float %t24, %t25 - %e14 = fadd float %t26, %t27 - %t28 = extractelement <4 x float> %res15, i32 0 - %t29 = extractelement <4 x float> %res15, i32 1 - %t30 = extractelement <4 x float> %res15, i32 2 - %t31 = extractelement <4 x float> %res15, i32 3 - %t32 = fadd float %t28, %t29 - %t33 = fadd float %t30, %t31 - %e15 = fadd float %t32, %t33 - %e16 = extractelement <4 x float> %res16, i32 3 - %s1 = fadd float %e1, %e2 - %s2 = fadd float %s1, %e3 - %s3 = fadd float %s2, %e4 - %s4 = fadd float %s3, %e5 - %s5 = fadd float %s4, %e6 - %s6 = fadd float %s5, %e7 - %s7 = fadd float %s6, %e8 - %s8 = fadd float %s7, %e9 - %s9 = fadd float %s8, %e10 - %s10 = fadd float %s9, %e11 - %s11 = fadd float %s10, %e12 - %s12 = fadd float %s11, %e13 - %s13 = fadd float %s12, %e14 - %s14 = fadd float %s13, %e15 - %s15 = fadd float %s14, %e16 - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %s15, float %s15, float %s15, float %s15) - ret void -} - -declare <4 x float> @llvm.SI.sampled.(<4 x i32>, <32 x i8>, <16 x i8>, i32) readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll b/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll index 2198590f2dfe..2d4987643a2b 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.sendmsg-m0.ll @@ -1,20 +1,17 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=BOTH %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=BOTH %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s -; BOTH-LABEL: {{^}}main: -; BOTH: s_mov_b32 m0, s0 +; GCN-LABEL: {{^}}main: +; GCN: s_mov_b32 m0, s0 ; VI-NEXT: s_nop 0 -; BOTH-NEXT: s_sendmsg Gs_done(nop) -; BOTH-NEXT: s_endpgm +; GCN-NEXT: sendmsg(MSG_GS_DONE, GS_OP_NOP) +; GCN-NEXT: s_endpgm -define void @main(i32 inreg %a) #0 { -main_body: +define amdgpu_gs void @main(i32 inreg %a) #0 { call void @llvm.SI.sendmsg(i32 3, i32 %a) ret void } -; Function Attrs: nounwind -declare void @llvm.SI.sendmsg(i32, i32) #1 +declare void @llvm.SI.sendmsg(i32, i32) #0 -attributes #0 = { "ShaderType"="2" "unsafe-fp-math"="true" } -attributes #1 = { nounwind } +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll b/test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll index 09675d503355..c4bb27676e7d 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.sendmsg.ll @@ -4,10 +4,10 @@ ; CHECK-LABEL: {{^}}main: ; CHECK: s_mov_b32 m0, 0 ; CHECK-NOT: s_mov_b32 m0 -; CHECK: s_sendmsg Gs(emit stream 0) -; CHECK: s_sendmsg Gs(cut stream 1) -; CHECK: s_sendmsg Gs(emit-cut stream 2) -; CHECK: s_sendmsg Gs_done(nop) +; CHECK: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT, 0) +; CHECK: s_sendmsg sendmsg(MSG_GS, GS_OP_CUT, 1) +; CHECK: s_sendmsg sendmsg(MSG_GS, GS_OP_EMIT_CUT, 2) +; CHECK: s_sendmsg sendmsg(MSG_GS_DONE, GS_OP_NOP) define void @main() { main_body: diff --git a/test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll b/test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll index 71f51548a5f8..645c6a6b8d7e 100644 --- a/test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll +++ b/test/CodeGen/AMDGPU/llvm.SI.tbuffer.store.ll @@ -3,7 +3,7 @@ ;CHECK-LABEL: {{^}}test1: ;CHECK: tbuffer_store_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, 0x20, -1, 0, -1, 0, 14, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 -define void @test1(i32 %a1, i32 %vaddr) #0 { +define amdgpu_vs void @test1(i32 %a1, i32 %vaddr) { %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, i32 4, i32 %vaddr, i32 0, i32 32, i32 14, i32 4, i32 1, i32 0, i32 1, @@ -13,7 +13,7 @@ define void @test1(i32 %a1, i32 %vaddr) #0 { ;CHECK-LABEL: {{^}}test2: ;CHECK: tbuffer_store_format_xyz {{v\[[0-9]+:[0-9]+\]}}, 0x18, -1, 0, -1, 0, 13, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 -define void @test2(i32 %a1, i32 %vaddr) #0 { +define amdgpu_vs void @test2(i32 %a1, i32 %vaddr) { %vdata = insertelement <4 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v4i32(<16 x i8> undef, <4 x i32> %vdata, i32 3, i32 %vaddr, i32 0, i32 24, i32 13, i32 4, i32 1, i32 0, i32 1, @@ -23,7 +23,7 @@ define void @test2(i32 %a1, i32 %vaddr) #0 { ;CHECK-LABEL: {{^}}test3: ;CHECK: tbuffer_store_format_xy {{v\[[0-9]+:[0-9]+\]}}, 0x10, -1, 0, -1, 0, 11, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 -define void @test3(i32 %a1, i32 %vaddr) #0 { +define amdgpu_vs void @test3(i32 %a1, i32 %vaddr) { %vdata = insertelement <2 x i32> undef, i32 %a1, i32 0 call void @llvm.SI.tbuffer.store.v2i32(<16 x i8> undef, <2 x i32> %vdata, i32 2, i32 %vaddr, i32 0, i32 16, i32 11, i32 4, i32 1, i32 0, i32 1, @@ -33,7 +33,7 @@ define void @test3(i32 %a1, i32 %vaddr) #0 { ;CHECK-LABEL: {{^}}test4: ;CHECK: tbuffer_store_format_x {{v[0-9]+}}, 0x8, -1, 0, -1, 0, 4, 4, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, -1, 0, 0 -define void @test4(i32 %vdata, i32 %vaddr) #0 { +define amdgpu_vs void @test4(i32 %vdata, i32 %vaddr) { call void @llvm.SI.tbuffer.store.i32(<16 x i8> undef, i32 %vdata, i32 1, i32 %vaddr, i32 0, i32 8, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) @@ -43,5 +43,3 @@ define void @test4(i32 %vdata, i32 %vaddr) #0 { declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.v2i32(<16 x i8>, <2 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) - -attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/AMDGPU/llvm.SI.tid.ll b/test/CodeGen/AMDGPU/llvm.SI.tid.ll deleted file mode 100644 index f6e6d7050ba7..000000000000 --- a/test/CodeGen/AMDGPU/llvm.SI.tid.ll +++ /dev/null @@ -1,18 +0,0 @@ -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=GCN %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI --check-prefix=GCN %s - -;GCN: v_mbcnt_lo_u32_b32_e64 -;SI: v_mbcnt_hi_u32_b32_e32 -;VI: v_mbcnt_hi_u32_b32_e64 - -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { -main_body: - %4 = call i32 @llvm.SI.tid() - %5 = bitcast i32 %4 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %5, float %5, float %5) - ret void -} - -declare i32 @llvm.SI.tid() readnone - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll new file mode 100644 index 000000000000..93911d4a91f1 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll @@ -0,0 +1,387 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32) #2 +declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32) #2 +declare i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* nocapture, i32) #2 + +declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64) #2 +declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64) #2 +declare i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* nocapture, i64) #2 + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +; GCN-LABEL: {{^}}lds_atomic_dec_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] +define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_dec_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] offset:16 +define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32: +; GCN: s_load_dword [[SPTR:s[0-9]+]], +; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; GCN: ds_dec_u32 [[VPTR]], [[DATA]] +define void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_dec_u32 v{{[0-9]+}}, [[K]] offset:16 +define void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} +define void @global_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 glc{{$}} +define void @global_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_dec_noret_i32: +; GCN: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @global_atomic_dec_noret_i32(i32 addrspace(1)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_dec_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_dec [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +define void @global_atomic_dec_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; CI: buffer_atomic_dec [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20 glc{{$}} +; VI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @global_atomic_dec_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id + %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_noret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; CI: buffer_atomic_dec [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}} +; VI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id + %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_dec_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42) + store i32 %result, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_dec_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + store i32 %result, i32 addrspace(4)* %out + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32: +; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_dec_noret_i32(i32 addrspace(4)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_dec_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_dec_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id + %out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id + %gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + store i32 %result, i32 addrspace(4)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_dec_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id + %gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_dec_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42) + store i64 %result, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_dec_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + store i64 %result, i64 addrspace(4)* %out + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_dec_noret_i64(i64 addrspace(4)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_dec_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_dec_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_dec_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id + %out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id + %gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + store i64 %result, i64 addrspace(4)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_dec_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id + %gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + ret void +} + +@lds0 = addrspace(3) global [512 x i32] undef + +; SI-LABEL: {{^}}atomic_dec_shl_base_lds_0: +; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; SI: ds_dec_rtn_u32 {{v[0-9]+}}, [[PTR]] offset:8 +define void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 2 + %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds0, i32 0, i32 %idx.0 + %val0 = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %arrayidx0, i32 9) + store i32 %idx.0, i32 addrspace(1)* %add_use + store i32 %val0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_dec_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 +define void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_dec_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} +define void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} +define void @global_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}} +define void @global_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_dec_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @global_atomic_dec_noret_i64(i64 addrspace(1)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_dec_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}} +define void @global_atomic_dec_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_ret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}} +; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @global_atomic_dec_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id + %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}global_atomic_dec_noret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; CI: buffer_atomic_dec_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}} +; VI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @global_atomic_dec_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id + %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + ret void +} + +@lds1 = addrspace(3) global [512 x i64] undef, align 8 + +; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0_i64: +; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}} +; GCN: ds_dec_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16 +define void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 2 + %arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0 + %val0 = call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9) + store i32 %idx.0, i32 addrspace(1)* %add_use + store i64 %val0, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind argmemonly } + + + + + + + + + diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll new file mode 100644 index 000000000000..181d68c8ea75 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll @@ -0,0 +1,383 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32) #2 +declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32) #2 +declare i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* nocapture, i32) #2 + +declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64) #2 +declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64) #2 +declare i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* nocapture, i64) #2 + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] +define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] offset:16 +define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32: +; GCN: s_load_dword [[SPTR:s[0-9]+]], +; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 +; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] +; GCN: ds_inc_u32 [[VPTR]], [[DATA]] +define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: ds_inc_u32 v{{[0-9]+}}, [[K]] offset:16 +define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} +define void @global_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 glc{{$}} +define void @global_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_inc_noret_i32: +; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @global_atomic_inc_noret_i32(i32 addrspace(1)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_inc_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: buffer_atomic_inc [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +define void @global_atomic_inc_noret_i32_offset(i32 addrspace(1)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20 glc{{$}} +; VI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @global_atomic_inc_ret_i32_offset_addr64(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id + %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + store i32 %result, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_noret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; CI: buffer_atomic_inc [[K]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:20{{$}} +; VI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @global_atomic_inc_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(1)* %ptr, i32 %id + %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %gep, i32 42) + ret void +} + +@lds0 = addrspace(3) global [512 x i32] undef, align 4 + +; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i32: +; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}} +; GCN: ds_inc_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 +define void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 2 + %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds0, i32 0, i32 %idx.0 + %val0 = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %arrayidx0, i32 9) + store i32 %idx.0, i32 addrspace(1)* %add_use + store i32 %val0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lds_atomic_inc_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 +define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: ds_inc_u64 v{{[0-9]+}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} +define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 glc{{$}} +define void @global_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32 glc{{$}} +define void @global_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_inc_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +define void @global_atomic_inc_noret_i64(i64 addrspace(1)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}global_atomic_inc_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:32{{$}} +define void @global_atomic_inc_noret_i64_offset(i64 addrspace(1)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(1)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_ret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40 glc{{$}} +; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @global_atomic_inc_ret_i64_offset_addr64(i64 addrspace(1)* %out, i64 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id + %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + store i64 %result, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}global_atomic_inc_noret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; CI: buffer_atomic_inc_x2 v{{\[}}[[KLO]]:[[KHI]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:40{{$}} +; VI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}}{{$}} +define void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(1)* %ptr, i32 %id + %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_inc_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42) + store i32 %result, i32 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_inc_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + store i32 %result, i32 addrspace(4)* %out + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32: +; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_inc_noret_i32(i32 addrspace(4)* %ptr) nounwind { + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42) + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i32_offset: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_inc_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { + %gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} +define void @flat_atomic_inc_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id + %out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id + %gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + store i32 %result, i32 addrspace(4)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 +; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} +define void @flat_atomic_inc_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id + %gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 + %result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42) + ret void +} + +@lds1 = addrspace(3) global [512 x i64] undef, align 8 + +; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64: +; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}} +; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16 +define void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 2 + %arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0 + %val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9) + store i32 %idx.0, i32 addrspace(1)* %add_use + store i64 %val0, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind argmemonly } + + + + + + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_inc_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42) + store i64 %result, i64 addrspace(4)* %out + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_inc_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + store i64 %result, i64 addrspace(4)* %out + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_inc_noret_i64(i64 addrspace(4)* %ptr) nounwind { + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42) + ret void +} + +; FUNC-LABEL: {{^}}flat_atomic_inc_noret_i64_offset: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_inc_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { + %gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} +define void @flat_atomic_inc_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id + %out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id + %gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + store i64 %result, i64 addrspace(4)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64: +; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 +; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} +; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} +define void @flat_atomic_inc_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id + %gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 + %result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42) + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll new file mode 100644 index 000000000000..98f7058b5ef8 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.atomic.ll @@ -0,0 +1,126 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI + +;CHECK-LABEL: {{^}}test1: +;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc +;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1fff +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc +;CHECK-DAG: s_waitcnt vmcnt(0) +;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc +;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:1 glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}} +define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) { +main_body: + %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0) + %o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) + %o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) + %ofs.5 = add i32 %voffset, 42 + %o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) + %o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) + %unused = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0) + %out = bitcast i32 %o6 to float + ret float %out +} + +;CHECK-LABEL: {{^}}test2: +;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc +define amdgpu_ps float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) { +main_body: + %t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t2 = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t3 = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t4 = call i32 @llvm.amdgcn.buffer.atomic.umin(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t5 = call i32 @llvm.amdgcn.buffer.atomic.smax(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t6 = call i32 @llvm.amdgcn.buffer.atomic.umax(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t7 = call i32 @llvm.amdgcn.buffer.atomic.and(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t8 = call i32 @llvm.amdgcn.buffer.atomic.or(i32 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %t9 = call i32 @llvm.amdgcn.buffer.atomic.xor(i32 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %out = bitcast i32 %t9 to float + ret float %out +} + +; Ideally, we would teach tablegen & friends that cmpswap only modifies the +; first vgpr. Since we don't do that yet, the register allocator will have to +; create copies which we don't bother to track here. +; +;CHECK-LABEL: {{^}}test3: +;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc +;CHECK: s_waitcnt vmcnt(0) +;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1fff +;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 idxen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:42 glc +;CHECK-DAG: s_waitcnt vmcnt(0) +;SICI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen glc +;VI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:1 glc +define amdgpu_ps float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) { +main_body: + %o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0) + %o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) + %o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) + %o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) + %ofs.5 = add i32 %voffset, 42 + %o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) + %o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) + +; Detecting the no-return variant doesn't work right now because of how the +; intrinsic is replaced by an instruction that feeds into an EXTRACT_SUBREG. +; Since there probably isn't a reasonable use-case of cmpswap that discards +; the return value, that seems okay. +; +; %unused = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0) + %out = bitcast i32 %o6 to float + ret float %out +} + +;CHECK-LABEL: {{^}}test4: +;CHECK: buffer_atomic_add v0, +define amdgpu_ps float @test4() { +main_body: + %v = call i32 @llvm.amdgcn.buffer.atomic.add(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false) + %v.float = bitcast i32 %v to float + ret float %v.float +} + +declare i32 @llvm.amdgcn.buffer.atomic.swap(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.add(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.smin(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.umin(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.smax(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.umax(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.and(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.or(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.xor(i32, <4 x i32>, i32, i32, i1) #0 +declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll new file mode 100644 index 000000000000..67c7baba3e14 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.format.ll @@ -0,0 +1,133 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI + +;CHECK-LABEL: {{^}}buffer_load: +;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 +;CHECK: buffer_load_format_xyzw v[4:7], off, s[0:3], 0 glc +;CHECK: buffer_load_format_xyzw v[8:11], off, s[0:3], 0 slc +;CHECK: s_waitcnt +define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) + %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) + %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) + %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 + %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 + %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 + ret {<4 x float>, <4 x float>, <4 x float>} %r2 +} + +;CHECK-LABEL: {{^}}buffer_load_immoffs: +;CHECK: buffer_load_format_xyzw v[0:3], off, s[0:3], 0 offset:42 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_immoffs_large: +;SICI: v_mov_b32_e32 [[VOFS:v[0-9]+]], 0x103c +;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, [[VOFS]], s[0:3], 0 offen +;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen +;VI-DAG: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 61 offset:4095 +;VI-DAG: s_movk_i32 [[OFS1:s[0-9]+]], 0x7fff +;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS1]] offset:4093 +;SICI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen +;VI: s_mov_b32 [[OFS2:s[0-9]+]], 0x8fff +;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS2]] offset:1 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { +main_body: + %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4156, i1 0, i1 0) + %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36860, i1 0, i1 0) + %d.2 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 36864, i1 0, i1 0) + %d.3 = fadd <4 x float> %d.0, %d.1 + %data = fadd <4 x float> %d.2, %d.3 + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_immoffs_reuse: +;VI: s_movk_i32 [[OFS:s[0-9]+]], 0xfff +;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS]] offset:65 +;VI-NOT: s_mov +;VI: buffer_load_format_xyzw {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[OFS]] offset:81 +;VI: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_immoffs_reuse(<4 x i32> inreg) { +main_body: + %d.0 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4160, i1 0, i1 0) + %d.1 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 4176, i1 0, i1 0) + %data = fadd <4 x float> %d.0, %d.1 + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_idx: +;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_ofs: +;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_ofs_imm: +;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen offset:58 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { +main_body: + %ofs = add i32 %1, 58 + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_both: +;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_both_reversed: +;CHECK: v_mov_b32_e32 v2, v0 +;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_x: +;CHECK: buffer_load_format_x v0, off, s[0:3], 0 +;CHECK: s_waitcnt +define amdgpu_ps float @buffer_load_x(<4 x i32> inreg %rsrc) { +main_body: + %data = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) + ret float %data +} + +;CHECK-LABEL: {{^}}buffer_load_xy: +;CHECK: buffer_load_format_xy v[0:1], off, s[0:3], 0 +;CHECK: s_waitcnt +define amdgpu_ps <2 x float> @buffer_load_xy(<4 x i32> inreg %rsrc) { +main_body: + %data = call <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32> %rsrc, i32 0, i32 0, i1 0, i1 0) + ret <2 x float> %data +} + +declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) #0 +declare <2 x float> @llvm.amdgcn.buffer.load.format.v2f32(<4 x i32>, i32, i32, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #0 + +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll new file mode 100644 index 000000000000..010ad276da10 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll @@ -0,0 +1,119 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI + +;CHECK-LABEL: {{^}}buffer_load: +;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 +;CHECK: buffer_load_dwordx4 v[4:7], off, s[0:3], 0 glc +;CHECK: buffer_load_dwordx4 v[8:11], off, s[0:3], 0 slc +;CHECK: s_waitcnt +define amdgpu_ps {<4 x float>, <4 x float>, <4 x float>} @buffer_load(<4 x i32> inreg) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0) + %data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0) + %data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1) + %r0 = insertvalue {<4 x float>, <4 x float>, <4 x float>} undef, <4 x float> %data, 0 + %r1 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r0, <4 x float> %data_glc, 1 + %r2 = insertvalue {<4 x float>, <4 x float>, <4 x float>} %r1, <4 x float> %data_slc, 2 + ret {<4 x float>, <4 x float>, <4 x float>} %r2 +} + +;CHECK-LABEL: {{^}}buffer_load_immoffs: +;CHECK: buffer_load_dwordx4 v[0:3], off, s[0:3], 0 offset:42 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_immoffs(<4 x i32> inreg) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 42, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_immoffs_large: +;SICI: buffer_load_dwordx4 v[0:3], {{v[0-9]+}}, s[0:3], 0 offen +;VI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x1fff +;VI: buffer_load_dwordx4 v[0:3], off, s[0:3], [[OFFSET]] offset:1 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_immoffs_large(<4 x i32> inreg) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_idx: +;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_idx(<4 x i32> inreg, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_ofs: +;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_ofs(<4 x i32> inreg, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_ofs_imm: +;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 offen offset:58 +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_ofs_imm(<4 x i32> inreg, i32) { +main_body: + %ofs = add i32 %1, 58 + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_both: +;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_both(<4 x i32> inreg, i32, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 %2, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_both_reversed: +;CHECK: v_mov_b32_e32 v2, v0 +;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps <4 x float> @buffer_load_both_reversed(<4 x i32> inreg, i32, i32) { +main_body: + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %2, i32 %1, i1 0, i1 0) + ret <4 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_x1: +;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps float @buffer_load_x1(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { +main_body: + %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) + ret float %data +} + +;CHECK-LABEL: {{^}}buffer_load_x2: +;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen +;CHECK: s_waitcnt +define amdgpu_ps <2 x float> @buffer_load_x2(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) { +main_body: + %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 0, i1 0) + ret <2 x float> %data +} + +;CHECK-LABEL: {{^}}buffer_load_negative_offset: +;CHECK: v_add_i32_e32 [[VOFS:v[0-9]+]], vcc, -16, v0 +;CHECK: buffer_load_dwordx4 v[0:3], [[VOFS]], s[0:3], 0 offen +define amdgpu_ps <4 x float> @buffer_load_negative_offset(<4 x i32> inreg, i32 %ofs) { +main_body: + %ofs.1 = add i32 %ofs, -16 + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs.1, i1 0, i1 0) + ret <4 x float> %data +} + +declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 +declare <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32>, i32, i32, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #0 + +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll new file mode 100644 index 000000000000..555a1d23ebe9 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.format.ll @@ -0,0 +1,95 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s + +;CHECK-LABEL: {{^}}buffer_store: +;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 +;CHECK: buffer_store_format_xyzw v[4:7], off, s[0:3], 0 glc +;CHECK: buffer_store_format_xyzw v[8:11], off, s[0:3], 0 slc +define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_immoffs: +;CHECK: buffer_store_format_xyzw v[0:3], off, s[0:3], 0 offset:42 +define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_idx: +;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_ofs: +;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 offen +define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_both: +;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen +define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_both_reversed: +;CHECK: v_mov_b32_e32 v6, v4 +;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen +define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) + ret void +} + +; Ideally, the register allocator would avoid the wait here +; +;CHECK-LABEL: {{^}}buffer_store_wait: +;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen +;CHECK: s_waitcnt vmcnt(0) expcnt(0) +;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) + %data = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) + call void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_x1: +;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) { +main_body: + call void @llvm.amdgcn.buffer.store.format.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_x2: +;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) { +main_body: + call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) + ret void +} + +declare void @llvm.amdgcn.buffer.store.format.f32(float, <4 x i32>, i32, i32, i1, i1) #0 +declare void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0 +declare void @llvm.amdgcn.buffer.store.format.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll new file mode 100644 index 000000000000..5ae255c7a26c --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.ll @@ -0,0 +1,95 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s + +;CHECK-LABEL: {{^}}buffer_store: +;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 +;CHECK: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 glc +;CHECK: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 slc +define amdgpu_ps void @buffer_store(<4 x i32> inreg, <4 x float>, <4 x float>, <4 x float>) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0) + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0) + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_immoffs: +;CHECK: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:42 +define amdgpu_ps void @buffer_store_immoffs(<4 x i32> inreg, <4 x float>) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_idx: +;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_idx(<4 x i32> inreg, <4 x float>, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_ofs: +;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 offen +define amdgpu_ps void @buffer_store_ofs(<4 x i32> inreg, <4 x float>, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_both: +;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen +define amdgpu_ps void @buffer_store_both(<4 x i32> inreg, <4 x float>, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_both_reversed: +;CHECK: v_mov_b32_e32 v6, v4 +;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen +define amdgpu_ps void @buffer_store_both_reversed(<4 x i32> inreg, <4 x float>, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0) + ret void +} + +; Ideally, the register allocator would avoid the wait here +; +;CHECK-LABEL: {{^}}buffer_store_wait: +;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen +;CHECK: s_waitcnt vmcnt(0) expcnt(0) +;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen +;CHECK: s_waitcnt vmcnt(0) +;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_wait(<4 x i32> inreg, <4 x float>, i32, i32, i32) { +main_body: + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0) + %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %3, i32 0, i1 0, i1 0) + call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %data, <4 x i32> %0, i32 %4, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_x1: +;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_x1(<4 x i32> inreg %rsrc, float %data, i32 %index) { +main_body: + call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}buffer_store_x2: +;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen +define amdgpu_ps void @buffer_store_x2(<4 x i32> inreg %rsrc, <2 x float> %data, i32 %index) #0 { +main_body: + call void @llvm.amdgcn.buffer.store.v2f32(<2 x float> %data, <4 x i32> %rsrc, i32 %index, i32 0, i1 0, i1 0) + ret void +} + +declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #0 +declare void @llvm.amdgcn.buffer.store.v2f32(<2 x float>, <4 x i32>, i32, i32, i1, i1) #0 +declare void @llvm.amdgcn.buffer.store.v4f32(<4 x float>, <4 x i32>, i32, i32, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32>, i32, i32, i1, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll new file mode 100644 index 000000000000..668c669e41e8 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.class.ll @@ -0,0 +1,511 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare i1 @llvm.amdgcn.class.f32(float, i32) #1 +declare i1 @llvm.amdgcn.class.f64(double, i32) #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 +declare float @llvm.fabs.f32(float) #1 +declare double @llvm.fabs.f64(double) #1 + +; SI-LABEL: {{^}}test_class_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fabs_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { + %a.fabs = call float @llvm.fabs.f32(float %a) #1 + %result = call i1 @llvm.amdgcn.class.f32(float %a.fabs, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fneg_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fneg_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { + %a.fneg = fsub float -0.0, %a + %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fneg_fabs_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fneg_fabs_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { + %a.fabs = call float @llvm.fabs.f32(float %a) #1 + %a.fneg.fabs = fsub float -0.0, %a.fabs + %result = call i1 @llvm.amdgcn.class.f32(float %a.fneg.fabs, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_1_f32: +; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 1{{$}} +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_1_f32(i32 addrspace(1)* %out, float %a) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_64_f32: +; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: v_cmp_class_f32_e64 [[COND:s\[[0-9]+:[0-9]+\]]], [[SA]], 64{{$}} +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[COND]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_64_f32(i32 addrspace(1)* %out, float %a) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; Set all 10 bits of mask +; SI-LABEL: {{^}}test_class_full_mask_f32: +; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}} +; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_full_mask_f32(i32 addrspace(1)* %out, float %a) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 1023) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_9bit_mask_f32: +; SI: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} +; SI: v_cmp_class_f32_e32 vcc, [[SA]], [[MASK]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_9bit_mask_f32(i32 addrspace(1)* %out, float %a) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}v_test_class_full_mask_f32: +; SI-DAG: buffer_load_dword [[VA:v[0-9]+]] +; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} +; SI: v_cmp_class_f32_e32 vcc, [[VA]], [[MASK]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @v_test_class_full_mask_f32(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 511) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f32: +; SI-DAG: buffer_load_dword [[VB:v[0-9]+]] +; SI: v_cmp_class_f32_e32 vcc, 1.0, [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_inline_imm_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %b = load i32, i32 addrspace(1)* %gep.in + + %result = call i1 @llvm.amdgcn.class.f32(float 1.0, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; FIXME: Why isn't this using a literal constant operand? +; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f32: +; SI-DAG: buffer_load_dword [[VB:v[0-9]+]] +; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000 +; SI: v_cmp_class_f32_e32 vcc, [[VK]], [[VB]] +; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_lit_constant_dynamic_mask_f32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %b = load i32, i32 addrspace(1)* %gep.in + + %result = call i1 @llvm.amdgcn.class.f32(float 1024.0, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_f64: +; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[VB]] +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fabs_f64: +; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], |[[SA]]|, [[VB]] +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { + %a.fabs = call double @llvm.fabs.f64(double %a) #1 + %result = call i1 @llvm.amdgcn.class.f64(double %a.fabs, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fneg_f64: +; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -[[SA]], [[VB]] +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fneg_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { + %a.fneg = fsub double -0.0, %a + %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_fneg_fabs_f64: +; SI-DAG: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_cmp_class_f64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], -|[[SA]]|, [[VB]] +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, [[CMP]] +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_fneg_fabs_f64(i32 addrspace(1)* %out, double %a, i32 %b) #0 { + %a.fabs = call double @llvm.fabs.f64(double %a) #1 + %a.fneg.fabs = fsub double -0.0, %a.fabs + %result = call i1 @llvm.amdgcn.class.f64(double %a.fneg.fabs, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_1_f64: +; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 1{{$}} +; SI: s_endpgm +define void @test_class_1_f64(i32 addrspace(1)* %out, double %a) #0 { + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 1) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_64_f64: +; SI: v_cmp_class_f64_e64 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 64{{$}} +; SI: s_endpgm +define void @test_class_64_f64(i32 addrspace(1)* %out, double %a) #0 { + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 64) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; Set all 9 bits of mask +; SI-LABEL: {{^}}test_class_full_mask_f64: +; SI: s_load_dwordx2 [[SA:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} +; SI: v_cmp_class_f64_e32 vcc, [[SA]], [[MASK]] +; SI-NOT: vcc +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI-NEXT: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_full_mask_f64(i32 addrspace(1)* %out, double %a) #0 { + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}v_test_class_full_mask_f64: +; SI-DAG: buffer_load_dwordx2 [[VA:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x1ff{{$}} +; SI: v_cmp_class_f64_e32 vcc, [[VA]], [[MASK]] +; SI-NOT: vcc +; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1, vcc +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @v_test_class_full_mask_f64(i32 addrspace(1)* %out, double addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr double, double addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load double, double addrspace(1)* %in + + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 511) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_inline_imm_constant_dynamic_mask_f64: +; XSI: v_cmp_class_f64_e32 vcc, 1.0, +; SI: v_cmp_class_f64_e32 vcc, +; SI: s_endpgm +define void @test_class_inline_imm_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %b = load i32, i32 addrspace(1)* %gep.in + + %result = call i1 @llvm.amdgcn.class.f64(double 1.0, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_lit_constant_dynamic_mask_f64: +; SI: v_cmp_class_f64_e32 vcc, s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} +; SI: s_endpgm +define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %b = load i32, i32 addrspace(1)* %gep.in + + %result = call i1 @llvm.amdgcn.class.f64(double 1024.0, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %gep.out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_fold_or_class_f32_0: +; SI-NOT: v_cmp_class +; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 3{{$}} +; SI-NOT: v_cmp_class +; SI: s_endpgm +define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 3) #1 + %or = or i1 %class0, %class1 + + %sext = sext i1 %or to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_fold_or3_class_f32_0: +; SI-NOT: v_cmp_class +; SI: v_cmp_class_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}} +; SI-NOT: v_cmp_class +; SI: s_endpgm +define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1 + %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1 + %or.0 = or i1 %class0, %class1 + %or.1 = or i1 %or.0, %class2 + + %sext = sext i1 %or.1 to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_fold_or_all_tests_class_f32_0: +; SI-NOT: v_cmp_class +; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}} +; SI: v_cmp_class_f32_e32 vcc, v{{[0-9]+}}, [[MASK]]{{$}} +; SI-NOT: v_cmp_class +; SI: s_endpgm +define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 1) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 2) #1 + %class2 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1 + %class3 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1 + %class4 = call i1 @llvm.amdgcn.class.f32(float %a, i32 16) #1 + %class5 = call i1 @llvm.amdgcn.class.f32(float %a, i32 32) #1 + %class6 = call i1 @llvm.amdgcn.class.f32(float %a, i32 64) #1 + %class7 = call i1 @llvm.amdgcn.class.f32(float %a, i32 128) #1 + %class8 = call i1 @llvm.amdgcn.class.f32(float %a, i32 256) #1 + %class9 = call i1 @llvm.amdgcn.class.f32(float %a, i32 512) #1 + %or.0 = or i1 %class0, %class1 + %or.1 = or i1 %or.0, %class2 + %or.2 = or i1 %or.1, %class3 + %or.3 = or i1 %or.2, %class4 + %or.4 = or i1 %or.3, %class5 + %or.5 = or i1 %or.4, %class6 + %or.6 = or i1 %or.5, %class7 + %or.7 = or i1 %or.6, %class8 + %or.8 = or i1 %or.7, %class9 + %sext = sext i1 %or.8 to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_fold_or_class_f32_1: +; SI-NOT: v_cmp_class +; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 12{{$}} +; SI-NOT: v_cmp_class +; SI: s_endpgm +define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 8) #1 + %or = or i1 %class0, %class1 + + %sext = sext i1 %or to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_fold_or_class_f32_2: +; SI-NOT: v_cmp_class +; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}} +; SI-NOT: v_cmp_class +; SI: s_endpgm +define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %a, i32 7) #1 + %or = or i1 %class0, %class1 + + %sext = sext i1 %or to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_no_fold_or_class_f32_0: +; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 4{{$}} +; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 8{{$}} +; SI: s_or_b64 +; SI: s_endpgm +define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 { + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %gep.in = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load float, float addrspace(1)* %gep.in + + %class0 = call i1 @llvm.amdgcn.class.f32(float %a, i32 4) #1 + %class1 = call i1 @llvm.amdgcn.class.f32(float %b, i32 8) #1 + %or = or i1 %class0, %class1 + + %sext = sext i1 %or to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_0_f32: +; SI-NOT: v_cmp_class +; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float %a, i32 0) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_class_0_f64: +; SI-NOT: v_cmp_class +; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}} +; SI: buffer_store_dword [[RESULT]] +; SI: s_endpgm +define void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 { + %result = call i1 @llvm.amdgcn.class.f64(double %a, i32 0) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +; FIXME: Why is the extension still here? +; SI-LABEL: {{^}}test_class_undef_f32: +; SI-NOT: v_cmp_class +; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, -1, +; SI: buffer_store_dword +define void @test_class_undef_f32(i32 addrspace(1)* %out, float %a, i32 %b) #0 { + %result = call i1 @llvm.amdgcn.class.f32(float undef, i32 %b) #1 + %sext = sext i1 %result to i32 + store i32 %sext, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll new file mode 100644 index 000000000000..f6495d8155f7 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cos.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s + +declare float @llvm.amdgcn.cos.f32(float) #0 + +; GCN-LABEL: {{^}}v_cos_f32: +; GCN: v_cos_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @v_cos_f32(float addrspace(1)* %out, float %src) #1 { + %cos = call float @llvm.amdgcn.cos.f32(float %src) #0 + store float %cos, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll new file mode 100644 index 000000000000..22bed45ee30f --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cubeid.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare float @llvm.amdgcn.cubeid(float, float, float) #0 + +; GCN-LABEL: {{^}}test_cubeid: +; GCN: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @test_cubeid(float addrspace(1)* %out, float %a, float %b, float %c) #1 { + %result = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c) + store float %result, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll new file mode 100644 index 000000000000..565f22c5d5b6 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cubema.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare float @llvm.amdgcn.cubema(float, float, float) #0 + +; GCN-LABEL: {{^}}test_cubema: +; GCN: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @test_cubema(float addrspace(1)* %out, float %a, float %b, float %c) #1 { + %result = call float @llvm.amdgcn.cubema(float %a, float %b, float %c) + store float %result, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll new file mode 100644 index 000000000000..a3ba32745814 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cubesc.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare float @llvm.amdgcn.cubesc(float, float, float) #0 + +; GCN-LABEL: {{^}}test_cubesc: +; GCN: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @test_cubesc(float addrspace(1)* %out, float %a, float %b, float %c) #1 { + %result = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c) + store float %result, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll new file mode 100644 index 000000000000..d3c0f2851ead --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.cubetc.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +declare float @llvm.amdgcn.cubetc(float, float, float) #0 + +; GCN-LABEL: {{^}}test_cubetc: +; GCN: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @test_cubetc(float addrspace(1)* %out, float %a, float %b, float %c) #1 { + %result = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c) + store float %result, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll index d96ea743f6ed..2e8625256f13 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s -; ERROR: error: unsupported hsa intrinsic without hsa target in test +; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; GCN-LABEL: {{^}}test: ; GCN: enable_sgpr_dispatch_ptr = 1 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll new file mode 100644 index 000000000000..f9b390eca0c2 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fixup.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s + +declare float @llvm.amdgcn.div.fixup.f32(float, float, float) nounwind readnone +declare double @llvm.amdgcn.div.fixup.f64(double, double, double) nounwind readnone + +; GCN-LABEL: {{^}}test_div_fixup_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 +; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] +; GCN: buffer_store_dword [[RESULT]], +; GCN: s_endpgm +define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { + %result = call float @llvm.amdgcn.div.fixup.f32(float %a, float %b, float %c) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fixup_f64: +; GCN: v_div_fixup_f64 +define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { + %result = call double @llvm.amdgcn.div.fixup.f64(double %a, double %b, double %c) nounwind readnone + store double %result, double addrspace(1)* %out, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll new file mode 100644 index 000000000000..efea3eb707a1 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll @@ -0,0 +1,178 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s +; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s + +; FIXME: Enable for VI. + +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone +declare float @llvm.amdgcn.div.fmas.f32(float, float, float, i1) nounwind readnone +declare double @llvm.amdgcn.div.fmas.f64(double, double, double, i1) nounwind readnone + +; GCN-LABEL: {{^}}test_div_fmas_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34 +; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] +; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]] +; GCN: buffer_store_dword [[RESULT]], +; GCN: s_endpgm +define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0: +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm +define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] +; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], 1.0, [[VC]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm +define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]] +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0 +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm +define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f64: +; GCN: v_div_fmas_f64 +define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind { + %result = call double @llvm.amdgcn.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone + store double %result, double addrspace(1)* %out, align 8 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc: +; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} +; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind { + %cmp = icmp eq i32 %i, 0 + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc: +; SI: s_mov_b64 vcc, 0 +; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc: +; SI: s_mov_b64 vcc, -1 +; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} + +; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} +; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} +; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] +; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] +; SI: s_endpgm +define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 + %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 + %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 + + %a = load volatile float, float addrspace(1)* %gep.a + %b = load volatile float, float addrspace(1)* %gep.b + %c = load volatile float, float addrspace(1)* %gep.c + + %cmp0 = icmp eq i32 %tid, 0 + %cmp1 = icmp ne i32 %d, 0 + %and = and i1 %cmp0, %cmp1 + + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone + store float %result, float addrspace(1)* %gep.out, align 4 + ret void +} + +; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc: +; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}} +; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc +; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]] + +; SI: buffer_load_dword [[LOAD:v[0-9]+]] +; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]] +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc + + +; SI: BB9_2: +; SI: s_or_b64 exec, exec, [[SAVE]] +; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}} +; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} +; SI: buffer_store_dword +; SI: s_endpgm +define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.out = getelementptr float, float addrspace(1)* %out, i32 2 + %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 + %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 + + %a = load float, float addrspace(1)* %gep.a + %b = load float, float addrspace(1)* %gep.b + %c = load float, float addrspace(1)* %gep.c + + %cmp0 = icmp eq i32 %tid, 0 + br i1 %cmp0, label %bb, label %exit + +bb: + %val = load i32, i32 addrspace(1)* %dummy + %cmp1 = icmp ne i32 %val, 0 + br label %exit + +exit: + %cond = phi i1 [false, %entry], [%cmp1, %bb] + %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone + store float %result, float addrspace(1)* %gep.out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll new file mode 100644 index 000000000000..38e4b8440d32 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.div.scale.ll @@ -0,0 +1,364 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone +declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) nounwind readnone +declare { double, i1 } @llvm.amdgcn.div.scale.f64(double, double, i1) nounwind readnone +declare float @llvm.fabs.f32(float) nounwind readnone + +; SI-LABEL: {{^}}test_div_scale_f32_1: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 + + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_2: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 + + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_1: +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 + + %a = load volatile double, double addrspace(1)* %gep.0, align 8 + %b = load volatile double, double addrspace(1)* %gep.1, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_2: +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 + + %a = load volatile double, double addrspace(1)* %gep.0, align 8 + %b = load volatile double, double addrspace(1)* %gep.1, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_1: +; SI-DAG: buffer_load_dword [[B:v[0-9]+]] +; SI-DAG: s_load_dword [[A:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr float, float addrspace(1)* %in, i32 %tid + + %b = load float, float addrspace(1)* %gep, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_2: +; SI-DAG: buffer_load_dword [[B:v[0-9]+]] +; SI-DAG: s_load_dword [[A:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr float, float addrspace(1)* %in, i32 %tid + + %b = load float, float addrspace(1)* %gep, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_1: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]] +; SI-DAG: s_load_dword [[B:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr float, float addrspace(1)* %in, i32 %tid + + %a = load float, float addrspace(1)* %gep, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_2: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]] +; SI-DAG: s_load_dword [[B:s[0-9]+]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr float, float addrspace(1)* %in, i32 %tid + + %a = load float, float addrspace(1)* %gep, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_1: +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr double, double addrspace(1)* %in, i32 %tid + + %b = load double, double addrspace(1)* %gep, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_2: +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr double, double addrspace(1)* %in, i32 %tid + + %b = load double, double addrspace(1)* %gep, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_1: +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr double, double addrspace(1)* %in, i32 %tid + + %a = load double, double addrspace(1)* %gep, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_2: +; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep = getelementptr double, double addrspace(1)* %in, i32 %tid + + %a = load double, double addrspace(1)* %gep, align 8 + + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_1: +; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, float %a, float %b) nounwind { + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_2: +; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc +; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, float %a, float %b) nounwind { + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_1: +; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]] +; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}} +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, double %a, double %b) nounwind { + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_2: +; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]] +; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]] +; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]] +; SI: buffer_store_dwordx2 [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, double %a, double %b) nounwind { + %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone + %result0 = extractvalue { double, i1 } %result, 0 + store double %result0, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_num: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[A]], 1.0 +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %a = load float, float addrspace(1)* %gep.0, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_den: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], 2.0, 2.0, [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %a = load float, float addrspace(1)* %gep.0, align 4 + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_fabs_num: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], |[[A]]| +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 + + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 + + %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a.fabs, float %b, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_div_scale_f32_fabs_den: +; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 +; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], |[[B]]|, |[[B]]|, [[A]] +; SI: buffer_store_dword [[RESULT0]] +; SI: s_endpgm +define void @test_div_scale_f32_fabs_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind { + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid + %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 + + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 + + %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone + + %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b.fabs, i1 false) nounwind readnone + %result0 = extractvalue { float, i1 } %result, 0 + store float %result0, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll new file mode 100644 index 000000000000..92d3fc8b107e --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.amdgcn.ds.bpermute(i32, i32) #0 + +; FUNC-LABEL: {{^}}ds_bpermute: +; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; CHECK: s_waitcnt lgkmcnt +define void @ds_bpermute(i32 addrspace(1)* %out, i32 %index, i32 %src) nounwind { + %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %index, i32 %src) #0 + store i32 %bpermute, i32 addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: {{^}}ds_bpermute_imm_offset: +; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:4 +; CHECK: s_waitcnt lgkmcnt +define void @ds_bpermute_imm_offset(i32 addrspace(1)* %out, i32 %base_index, i32 %src) nounwind { + %index = add i32 %base_index, 4 + %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 %index, i32 %src) #0 + store i32 %bpermute, i32 addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: {{^}}ds_bpermute_imm_index: +; CHECK: ds_bpermute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:64 +; CHECK: s_waitcnt lgkmcnt +define void @ds_bpermute_imm_index(i32 addrspace(1)* %out, i32 %base_index, i32 %src) nounwind { + %bpermute = call i32 @llvm.amdgcn.ds.bpermute(i32 64, i32 %src) #0 + store i32 %bpermute, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone convergent } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll new file mode 100644 index 000000000000..6d9c94191535 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.permute.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.amdgcn.ds.permute(i32, i32) #0 + +; CHECK-LABEL: {{^}}ds_permute: +; CHECK: ds_permute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; CHECK: s_waitcnt lgkmcnt +define void @ds_permute(i32 addrspace(1)* %out, i32 %index, i32 %src) nounwind { + %bpermute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0 + store i32 %bpermute, i32 addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: {{^}}ds_permute_imm_offset: +; CHECK: ds_permute_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:4 +; CHECK: s_waitcnt lgkmcnt +define void @ds_permute_imm_offset(i32 addrspace(1)* %out, i32 %base_index, i32 %src) nounwind { + %index = add i32 %base_index, 4 + %bpermute = call i32 @llvm.amdgcn.ds.permute(i32 %index, i32 %src) #0 + store i32 %bpermute, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone convergent } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll new file mode 100644 index 000000000000..ef3cb00024bb --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ds.swizzle.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0 + +; FUNC-LABEL: {{^}}ds_swizzle: +; CHECK: ds_swizzle_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:100 +; CHECK: s_waitcnt lgkmcnt +define void @ds_swizzle(i32 addrspace(1)* %out, i32 %src) nounwind { + %swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0 + store i32 %swizzle, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone convergent } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll new file mode 100644 index 000000000000..1cca9eb6a77a --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.fract.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s + +declare float @llvm.amdgcn.fract.f32(float) #0 +declare double @llvm.amdgcn.fract.f64(double) #0 + +; GCN-LABEL: {{^}}v_fract_f32: +; GCN: v_fract_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @v_fract_f32(float addrspace(1)* %out, float %src) #1 { + %fract = call float @llvm.amdgcn.fract.f32(float %src) + store float %fract, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_fract_f64: +; GCN: v_fract_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +define void @v_fract_f64(double addrspace(1)* %out, double %src) #1 { + %fract = call double @llvm.amdgcn.fract.f64(double %src) + store double %fract, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_fract_undef_f32: +; GCN-NOT: v_fract_f32 +; GCN-NOT: v0 +; GCN: buffer_store_dword v0 +define void @v_fract_undef_f32(float addrspace(1)* %out) #1 { + %fract = call float @llvm.amdgcn.fract.f32(float undef) + store float %fract, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll new file mode 100644 index 000000000000..728a6b5cf26b --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.exp.ll @@ -0,0 +1,64 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare float @llvm.fabs.f32(float) #0 +declare double @llvm.fabs.f64(double) #0 +declare i32 @llvm.amdgcn.frexp.exp.f32(float) #0 +declare i32 @llvm.amdgcn.frexp.exp.f64(double) #0 + +; GCN-LABEL: {{^}}s_test_frexp_exp_f32: +; GCN: v_frexp_exp_i32_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @s_test_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 { + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f32(float %src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f32: +; GCN: v_frexp_exp_i32_f32_e64 {{v[0-9]+}}, |{{s[0-9]+}}| +define void @s_test_fabs_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 { + %fabs.src = call float @llvm.fabs.f32(float %src) + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f32(float %fabs.src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f32: +; GCN: v_frexp_exp_i32_f32_e64 {{v[0-9]+}}, -|{{s[0-9]+}}| +define void @s_test_fneg_fabs_frexp_exp_f32(i32 addrspace(1)* %out, float %src) #1 { + %fabs.src = call float @llvm.fabs.f32(float %src) + %fneg.fabs.src = fsub float -0.0, %fabs.src + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f32(float %fneg.fabs.src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_frexp_exp_f64: +; GCN: v_frexp_exp_i32_f64_e32 {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} +define void @s_test_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 { + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f64(double %src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fabs_frexp_exp_f64: +; GCN: v_frexp_exp_i32_f64_e64 {{v[0-9]+}}, |{{s\[[0-9]+:[0-9]+\]}}| +define void @s_test_fabs_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 { + %fabs.src = call double @llvm.fabs.f64(double %src) + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f64(double %fabs.src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_exp_f64: +; GCN: v_frexp_exp_i32_f64_e64 {{v[0-9]+}}, -|{{s\[[0-9]+:[0-9]+\]}}| +define void @s_test_fneg_fabs_frexp_exp_f64(i32 addrspace(1)* %out, double %src) #1 { + %fabs.src = call double @llvm.fabs.f64(double %src) + %fneg.fabs.src = fsub double -0.0, %fabs.src + %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f64(double %fneg.fabs.src) + store i32 %frexp.exp, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll new file mode 100644 index 000000000000..b8d63defffed --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.frexp.mant.ll @@ -0,0 +1,64 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare float @llvm.fabs.f32(float) #0 +declare double @llvm.fabs.f64(double) #0 +declare float @llvm.amdgcn.frexp.mant.f32(float) #0 +declare double @llvm.amdgcn.frexp.mant.f64(double) #0 + +; GCN-LABEL: {{^}}s_test_frexp_mant_f32: +; GCN: v_frexp_mant_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @s_test_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 { + %frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %src) + store float %frexp.mant, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fabs_frexp_mant_f32: +; GCN: v_frexp_mant_f32_e64 {{v[0-9]+}}, |{{s[0-9]+}}| +define void @s_test_fabs_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 { + %fabs.src = call float @llvm.fabs.f32(float %src) + %frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fabs.src) + store float %frexp.mant, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_mant_f32: +; GCN: v_frexp_mant_f32_e64 {{v[0-9]+}}, -|{{s[0-9]+}}| +define void @s_test_fneg_fabs_frexp_mant_f32(float addrspace(1)* %out, float %src) #1 { + %fabs.src = call float @llvm.fabs.f32(float %src) + %fneg.fabs.src = fsub float -0.0, %fabs.src + %frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fneg.fabs.src) + store float %frexp.mant, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_frexp_mant_f64: +; GCN: v_frexp_mant_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +define void @s_test_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 { + %frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %src) + store double %frexp.mant, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fabs_frexp_mant_f64: +; GCN: v_frexp_mant_f64_e64 {{v\[[0-9]+:[0-9]+\]}}, |{{s\[[0-9]+:[0-9]+\]}}| +define void @s_test_fabs_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 { + %fabs.src = call double @llvm.fabs.f64(double %src) + %frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fabs.src) + store double %frexp.mant, double addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}s_test_fneg_fabs_frexp_mant_f64: +; GCN: v_frexp_mant_f64_e64 {{v\[[0-9]+:[0-9]+\]}}, -|{{s\[[0-9]+:[0-9]+\]}}| +define void @s_test_fneg_fabs_frexp_mant_f64(double addrspace(1)* %out, double %src) #1 { + %fabs.src = call double @llvm.fabs.f64(double %src) + %fneg.fabs.src = fsub double -0.0, %fabs.src + %frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fneg.fabs.src) + store double %frexp.mant, double addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll new file mode 100644 index 000000000000..cf6d1ab237cd --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.groupstaticgroup.ll @@ -0,0 +1,56 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s + + +@lds0 = addrspace(3) global [512 x float] undef, align 4 +@lds1 = addrspace(3) global [256 x float] undef, align 4 + +; FUNC-LABEL: {{^}}groupstaticsize_test0: +; CHECK: s_movk_i32 s{{[0-9]+}}, 0x800 +define void @get_groupstaticsize_test0(float addrspace(1)* %out, i32 addrspace(1)* %lds_size) #0 { + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 64 + %static_lds_size = call i32 @llvm.amdgcn.groupstaticsize() #1 + store i32 %static_lds_size, i32 addrspace(1)* %lds_size, align 4 + %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 + %val0 = load float, float addrspace(3)* %arrayidx0, align 4 + store float %val0, float addrspace(1)* %out, align 4 + + ret void +} + + +; FUNC-LABEL: {{^}}groupstaticsize_test1: +; CHECK: s_movk_i32 s{{[0-9]+}}, 0xc00 +define void @groupstaticsize_test1(float addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %lds_size) { +entry: + %static_lds_size = call i32 @llvm.amdgcn.groupstaticsize() #1 + store i32 %static_lds_size, i32 addrspace(1)* %lds_size, align 4 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 + %idx.0 = add nsw i32 %tid.x, 64 + %tmp = icmp eq i32 %cond, 0 + br i1 %tmp, label %if, label %else + +if: ; preds = %entry + %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 + %val0 = load float, float addrspace(3)* %arrayidx0, align 4 + store float %val0, float addrspace(1)* %out, align 4 + br label %endif + +else: ; preds = %entry + %arrayidx1 = getelementptr inbounds [256 x float], [256 x float] addrspace(3)* @lds1, i32 0, i32 %idx.0 + %val1 = load float, float addrspace(3)* %arrayidx1, align 4 + store float %val1, float addrspace(1)* %out, align 4 + br label %endif + +endif: ; preds = %else, %if + ret void +} + + +declare i32 @llvm.amdgcn.groupstaticsize() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll new file mode 100644 index 000000000000..87d838727882 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.ll @@ -0,0 +1,123 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI +;RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI + +;CHECK-LABEL: {{^}}image_atomic_swap: +;SI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x04,0x00,0x00] +;VI: image_atomic_swap v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_swap(<8 x i32> inreg, <4 x i32>, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.swap.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_swap_v2i32: +;SI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x02,0x00,0x00] +;VI: image_atomic_swap v2, v[0:1], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x02,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_swap_v2i32(<8 x i32> inreg, <2 x i32>, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.swap.v2i32(i32 %2, <2 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_swap_i32: +;SI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x3c,0xf0,0x00,0x01,0x00,0x00] +;VI: image_atomic_swap v1, v0, s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x40,0xf0,0x00,0x01,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_swap_i32(<8 x i32> inreg, i32, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(i32 %2, i32 %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_cmpswap: +;SI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x40,0xf0,0x00,0x04,0x00,0x00] +;VI: image_atomic_cmpswap v[4:5], v[0:3], s[0:7] dmask:0x3 unorm glc ; encoding: [0x00,0x33,0x44,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: v_mov_b32_e32 v0, v4 +define amdgpu_ps float @image_atomic_cmpswap(<8 x i32> inreg, <4 x i32>, i32, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.cmpswap.v4i32(i32 %2, i32 %3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_add: +;SI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x44,0xf0,0x00,0x04,0x00,0x00] +;VI: image_atomic_add v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_add(<8 x i32> inreg, <4 x i32>, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.add.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_sub: +;SI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x48,0xf0,0x00,0x04,0x00,0x00] +;VI: image_atomic_sub v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x4c,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_sub(<8 x i32> inreg, <4 x i32>, i32) { +main_body: + %orig = call i32 @llvm.amdgcn.image.atomic.sub.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %orig.f = bitcast i32 %orig to float + ret float %orig.f +} + +;CHECK-LABEL: {{^}}image_atomic_unchanged: +;CHECK: image_atomic_smin v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x50,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_umin v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x54,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_smax v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x58,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_umax v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x5c,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_and v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x60,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_or v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x64,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_xor v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x68,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_inc v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x6c,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_atomic_dec v4, v[0:3], s[0:7] dmask:0x1 unorm glc ; encoding: [0x00,0x31,0x70,0xf0,0x00,0x04,0x00,0x00] +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_atomic_unchanged(<8 x i32> inreg, <4 x i32>, i32) { +main_body: + %t0 = call i32 @llvm.amdgcn.image.atomic.smin.v4i32(i32 %2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t1 = call i32 @llvm.amdgcn.image.atomic.umin.v4i32(i32 %t0, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t2 = call i32 @llvm.amdgcn.image.atomic.smax.v4i32(i32 %t1, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t3 = call i32 @llvm.amdgcn.image.atomic.umax.v4i32(i32 %t2, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t4 = call i32 @llvm.amdgcn.image.atomic.and.v4i32(i32 %t3, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t5 = call i32 @llvm.amdgcn.image.atomic.or.v4i32(i32 %t4, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t6 = call i32 @llvm.amdgcn.image.atomic.xor.v4i32(i32 %t5, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t7 = call i32 @llvm.amdgcn.image.atomic.inc.v4i32(i32 %t6, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %t8 = call i32 @llvm.amdgcn.image.atomic.dec.v4i32(i32 %t7, <4 x i32> %1, <8 x i32> %0, i1 0, i1 0, i1 0) + %out = bitcast i32 %t8 to float + ret float %out +} + +declare i32 @llvm.amdgcn.image.atomic.swap.i32(i32, i32, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.swap.v2i32(i32, <2 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.swap.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 + +declare i32 @llvm.amdgcn.image.atomic.cmpswap.v4i32(i32, i32, <4 x i32>, <8 x i32>,i1, i1, i1) #0 + +declare i32 @llvm.amdgcn.image.atomic.add.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.sub.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.smin.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.umin.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.smax.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.umax.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.and.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.or.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.xor.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.inc.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 +declare i32 @llvm.amdgcn.image.atomic.dec.v4i32(i32, <4 x i32>, <8 x i32>, i1, i1, i1) #0 + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll new file mode 100644 index 000000000000..f0d23b93119d --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.image.ll @@ -0,0 +1,110 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s + +;CHECK-LABEL: {{^}}image_load_v4i32: +;CHECK: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps <4 x float> @image_load_v4i32(<8 x i32> inreg %rsrc, <4 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret <4 x float> %tex +} + +;CHECK-LABEL: {{^}}image_load_v2i32: +;CHECK: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps <4 x float> @image_load_v2i32(<8 x i32> inreg %rsrc, <2 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret <4 x float> %tex +} + +;CHECK-LABEL: {{^}}image_load_i32: +;CHECK: image_load v[0:3], v0, s[0:7] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps <4 x float> @image_load_i32(<8 x i32> inreg %rsrc, i32 %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret <4 x float> %tex +} + +;CHECK-LABEL: {{^}}image_load_mip: +;CHECK: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps <4 x float> @image_load_mip(<8 x i32> inreg %rsrc, <4 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret <4 x float> %tex +} + +;CHECK-LABEL: {{^}}image_load_1: +;CHECK: image_load v0, v[0:3], s[0:7] dmask:0x1 unorm +;CHECK: s_waitcnt vmcnt(0) +define amdgpu_ps float @image_load_1(<8 x i32> inreg %rsrc, <4 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + %elt = extractelement <4 x float> %tex, i32 0 +; Only first component used, test that dmask etc. is changed accordingly + ret float %elt +} + +;CHECK-LABEL: {{^}}image_store_v4i32: +;CHECK: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm +define amdgpu_ps void @image_store_v4i32(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) { +main_body: + call void @llvm.amdgcn.image.store.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}image_store_v2i32: +;CHECK: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm +define amdgpu_ps void @image_store_v2i32(<8 x i32> inreg %rsrc, <4 x float> %data, <2 x i32> %coords) { +main_body: + call void @llvm.amdgcn.image.store.v2i32(<4 x float> %data, <2 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}image_store_i32: +;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm +define amdgpu_ps void @image_store_i32(<8 x i32> inreg %rsrc, <4 x float> %data, i32 %coords) { +main_body: + call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +;CHECK-LABEL: {{^}}image_store_mip: +;CHECK: image_store_mip v[0:3], v[4:7], s[0:7] dmask:0xf unorm +define amdgpu_ps void @image_store_mip(<8 x i32> inreg %rsrc, <4 x float> %data, <4 x i32> %coords) { +main_body: + call void @llvm.amdgcn.image.store.mip.v4i32(<4 x float> %data, <4 x i32> %coords, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +; Ideally, the register allocator would avoid the wait here +; +;CHECK-LABEL: {{^}}image_store_wait: +;CHECK: image_store v[0:3], v4, s[0:7] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) expcnt(0) +;CHECK: image_load v[0:3], v4, s[8:15] dmask:0xf unorm +;CHECK: s_waitcnt vmcnt(0) +;CHECK: image_store v[0:3], v4, s[16:23] dmask:0xf unorm +define amdgpu_ps void @image_store_wait(<8 x i32> inreg, <8 x i32> inreg, <8 x i32> inreg, <4 x float>, i32) { +main_body: + call void @llvm.amdgcn.image.store.i32(<4 x float> %3, i32 %4, <8 x i32> %0, i32 15, i1 0, i1 0, i1 0, i1 0) + %data = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %4, <8 x i32> %1, i32 15, i1 0, i1 0, i1 0, i1 0) + call void @llvm.amdgcn.image.store.i32(<4 x float> %data, i32 %4, <8 x i32> %2, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0 +declare void @llvm.amdgcn.image.store.v2i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 +declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 +declare void @llvm.amdgcn.image.store.mip.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.load.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare <4 x float> @llvm.amdgcn.image.load.v2i32(<2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll index a28e1b1eb241..911d7d9b74d9 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.interp.ll @@ -6,7 +6,7 @@ ;GCN: s_mov_b32 m0, s{{[0-9]+}} ;GCN: v_interp_p1_f32 ;GCN: v_interp_p2_f32 -define void @v_interp(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 { +define amdgpu_ps void @v_interp(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) { main_body: %i = extractelement <2 x i32> %4, i32 0 %j = extractelement <2 x i32> %4, i32 1 @@ -19,12 +19,11 @@ main_body: } ; Function Attrs: nounwind readnone -declare float @llvm.amdgcn.interp.p1(i32, i32, i32, i32) #1 +declare float @llvm.amdgcn.interp.p1(i32, i32, i32, i32) #0 ; Function Attrs: nounwind readnone -declare float @llvm.amdgcn.interp.p2(float, i32, i32, i32, i32) #1 +declare float @llvm.amdgcn.interp.p2(float, i32, i32, i32, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll new file mode 100644 index 000000000000..07650d990f3c --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll @@ -0,0 +1,34 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=HSA -check-prefix=ALL %s +; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=MESA -check-prefix=ALL %s + +; ALL-LABEL: {{^}}test: +; HSA: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: s_load_dword s{{[0-9]+}}, s[4:5], 0xa + +; MESA: s_load_dword s{{[0-9]+}}, s[0:1], 0xa +define void @test(i32 addrspace(1)* %out) #1 { + %kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() + %header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)* + %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10 + %value = load i32, i32 addrspace(2)* %gep + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}test_implicit: +; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15 +; MESA: s_load_dword s{{[0-9]+}}, s[0:1], 0x15 +define void @test_implicit(i32 addrspace(1)* %out) #1 { + %implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() + %header.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* + %gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10 + %value = load i32, i32 addrspace(2)* %gep + store i32 %value, i32 addrspace(1)* %out + ret void +} + +declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 +declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll new file mode 100644 index 000000000000..a23defd742a8 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ldexp.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare float @llvm.amdgcn.ldexp.f32(float, i32) nounwind readnone +declare double @llvm.amdgcn.ldexp.f64(double, i32) nounwind readnone + +; SI-LABEL: {{^}}test_ldexp_f32: +; SI: v_ldexp_f32 +; SI: s_endpgm +define void @test_ldexp_f32(float addrspace(1)* %out, float %a, i32 %b) nounwind { + %result = call float @llvm.amdgcn.ldexp.f32(float %a, i32 %b) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} + +; SI-LABEL: {{^}}test_ldexp_f64: +; SI: v_ldexp_f64 +; SI: s_endpgm +define void @test_ldexp_f64(double addrspace(1)* %out, double %a, i32 %b) nounwind { + %result = call double @llvm.amdgcn.ldexp.f64(double %a, i32 %b) nounwind readnone + store double %result, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_ldexp_undef_f32: +; SI-NOT: v_ldexp_f32 +define void @test_ldexp_undef_f32(float addrspace(1)* %out, i32 %b) nounwind { + %result = call float @llvm.amdgcn.ldexp.f32(float undef, i32 %b) nounwind readnone + store float %result, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll new file mode 100644 index 000000000000..014369b45015 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.lerp.ll @@ -0,0 +1,14 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.amdgcn.lerp(i32, i32, i32) #0 + +; GCN-LABEL: {{^}}v_lerp: +; GCN: v_lerp_u8 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @v_lerp(i32 addrspace(1)* %out, i32 %src) nounwind { + %result= call i32 @llvm.amdgcn.lerp(i32 %src, i32 100, i32 100) #0 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll new file mode 100644 index 000000000000..f78257f1d226 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.log.clamp.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: not llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERR %s + +; ERR: intrinsic not supported on subtarget + +declare float @llvm.amdgcn.log.clamp.f32(float) #0 + +; GCN-LABEL: {{^}}v_log_clamp_f32: +; GCN: v_log_clamp_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @v_log_clamp_f32(float addrspace(1)* %out, float %src) #1 { + %log.clamp = call float @llvm.amdgcn.log.clamp.f32(float %src) #0 + store float %log.clamp, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll index 02ee2039542a..4825c3a479c1 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.mbcnt.ll @@ -6,7 +6,7 @@ ;SI: v_mbcnt_hi_u32_b32_e32 {{v[0-9]+}}, -1, [[LO]] ;VI: v_mbcnt_hi_u32_b32_e64 {{v[0-9]+}}, -1, [[LO]] -define void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { +define amdgpu_ps void @mbcnt_intrinsics(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) { main_body: %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 %hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) #1 diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll new file mode 100644 index 000000000000..a85fc7e13fd8 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll @@ -0,0 +1,66 @@ +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s +; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s + +; FIXME: The register allocator / scheduler should be able to avoid these hazards. + +; VI-LABEL: {{^}}dpp_test: +; VI: v_mov_b32_e32 v0, s{{[0-9]+}} +; VI: s_nop 1 +; VI: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11] +define void @dpp_test(i32 addrspace(1)* %out, i32 %in) { + %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 + store i32 %tmp0, i32 addrspace(1)* %out + ret void +} + +; VI-LABEL: {{^}}dpp_wait_states: +; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}} +; VI: s_nop 1 +; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 +; VI: s_nop 1 +; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 +define void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) { + %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0 + %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 + store i32 %tmp1, i32 addrspace(1)* %out + ret void +} + +; VI-LABEL: {{^}}dpp_first_in_bb: +; VI: ; %endif +; VI-OPT: s_mov_b32 +; VI-OPT: s_mov_b32 +; VI-NOOPT: s_nop 1 +; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 +; VI: s_nop 1 +; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 +; VI: s_nop 1 +; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 +define void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) { + %cmp = fcmp oeq float %cond, 0.0 + br i1 %cmp, label %if, label %else + +if: + %out_val = load float, float addrspace(1)* %out + %if_val = fadd float %a, %out_val + br label %endif + +else: + %in_val = load float, float addrspace(1)* %in + %else_val = fadd float %b, %in_val + br label %endif + +endif: + %val = phi float [%if_val, %if], [%else_val, %else] + %val_i32 = bitcast float %val to i32 + %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %val_i32, i32 1, i32 1, i32 1, i1 1) #0 + %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0 + %tmp2 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp1, i32 1, i32 1, i32 1, i1 1) #0 + %tmp_float = bitcast i32 %tmp2 to float + store float %tmp_float, float addrspace(1)* %out + ret void +} + +declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32, i32, i32, i1) #0 + +attributes #0 = { nounwind readnone convergent } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll new file mode 100644 index 000000000000..fd1a463fd3e9 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll @@ -0,0 +1,59 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s + +; CHECK-LABEL: {{^}}test1: +; CHECK: v_cndmask_b32_e64 v0, 0, 1, exec +; +; Note: We could generate better code here if we recognized earlier that +; there is no WQM use and therefore llvm.amdgcn.ps.live is constant. However, +; the expectation is that the intrinsic will be used in non-trivial shaders, +; so such an optimization doesn't seem worth the effort. +define amdgpu_ps float @test1() { + %live = call i1 @llvm.amdgcn.ps.live() + %live.32 = zext i1 %live to i32 + %r = bitcast i32 %live.32 to float + ret float %r +} + +; CHECK-LABEL: {{^}}test2: +; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec +; CHECK-DAG: s_wqm_b64 exec, exec +; CHECK-DAG: v_cndmask_b32_e64 [[VAR:v[0-9]+]], 0, 1, [[LIVE]] +; CHECK: image_sample v0, [[VAR]], +define amdgpu_ps float @test2() { + %live = call i1 @llvm.amdgcn.ps.live() + %live.32 = zext i1 %live to i32 + + %t = call <4 x float> @llvm.SI.image.sample.i32(i32 %live.32, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + + %r = extractelement <4 x float> %t, i32 0 + ret float %r +} + +; CHECK-LABEL: {{^}}test3: +; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec +; CHECK-DAG: s_wqm_b64 exec, exec +; CHECK-DAG: s_xor_b64 [[HELPER:s\[[0-9]+:[0-9]+\]]], [[LIVE]], -1 +; CHECK_DAG: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[HELPER]] +; CHECK: ; %dead +define amdgpu_ps float @test3(i32 %in) { +entry: + %live = call i1 @llvm.amdgcn.ps.live() + br i1 %live, label %end, label %dead + +dead: + %tc.dead = mul i32 %in, 2 + br label %end + +end: + %tc = phi i32 [ %in, %entry ], [ %tc.dead, %dead ] + %t = call <4 x float> @llvm.SI.image.sample.i32(i32 %tc, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + + %r = extractelement <4 x float> %t, i32 0 + ret float %r +} + +declare i1 @llvm.amdgcn.ps.live() #0 + +declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll new file mode 100644 index 000000000000..6bf871543ca2 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll @@ -0,0 +1,19 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s + +; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target + +; GCN-LABEL: {{^}}test: +; GCN: enable_sgpr_queue_ptr = 1 +; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 +define void @test(i32 addrspace(1)* %out) { + %queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 + %header_ptr = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* + %value = load i32, i32 addrspace(2)* %header_ptr + store i32 %value, i32 addrspace(1)* %out + ret void +} + +declare noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll new file mode 100644 index 000000000000..825231bf8680 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll @@ -0,0 +1,128 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +declare float @llvm.amdgcn.rcp.f32(float) #0 +declare double @llvm.amdgcn.rcp.f64(double) #0 + +declare double @llvm.sqrt.f64(double) #0 +declare float @llvm.sqrt.f32(float) #0 + +; FUNC-LABEL: {{^}}rcp_undef_f32: +; SI-NOT: v_rcp_f32 +define void @rcp_undef_f32(float addrspace(1)* %out) #1 { + %rcp = call float @llvm.amdgcn.rcp.f32(float undef) + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}safe_no_fp32_denormals_rcp_f32: +; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dword [[RESULT]] +define void @safe_no_fp32_denormals_rcp_f32(float addrspace(1)* %out, float %src) #1 { + %rcp = fdiv float 1.0, %src + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}safe_f32_denormals_rcp_pat_f32: +; SI: v_rcp_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dword [[RESULT]] +define void @safe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #4 { + %rcp = fdiv float 1.0, %src + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}unsafe_f32_denormals_rcp_pat_f32: +; SI: v_div_scale_f32 +define void @unsafe_f32_denormals_rcp_pat_f32(float addrspace(1)* %out, float %src) #3 { + %rcp = fdiv float 1.0, %src + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f32: +; SI: v_sqrt_f32_e32 +; SI: v_rcp_f32_e32 +define void @safe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #1 { + %sqrt = call float @llvm.sqrt.f32(float %src) + %rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt) + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f32: +; SI: v_rsq_f32_e32 +define void @unsafe_rsq_rcp_pat_f32(float addrspace(1)* %out, float %src) #2 { + %sqrt = call float @llvm.sqrt.f32(float %src) + %rcp = call float @llvm.amdgcn.rcp.f32(float %sqrt) + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rcp_f64: +; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +define void @rcp_f64(double addrspace(1)* %out, double %src) #1 { + %rcp = call double @llvm.amdgcn.rcp.f64(double %src) + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}unsafe_rcp_f64: +; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +define void @unsafe_rcp_f64(double addrspace(1)* %out, double %src) #2 { + %rcp = call double @llvm.amdgcn.rcp.f64(double %src) + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}rcp_pat_f64: +; SI: v_div_scale_f64 +define void @rcp_pat_f64(double addrspace(1)* %out, double %src) #1 { + %rcp = fdiv double 1.0, %src + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}unsafe_rcp_pat_f64: +; SI: v_rcp_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +define void @unsafe_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 { + %rcp = fdiv double 1.0, %src + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}safe_rsq_rcp_pat_f64: +; SI-NOT: v_rsq_f64_e32 +; SI: v_sqrt_f64 +; SI: v_rcp_f64 +define void @safe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #1 { + %sqrt = call double @llvm.sqrt.f64(double %src) + %rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt) + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}unsafe_rsq_rcp_pat_f64: +; SI: v_rsq_f64_e32 [[RESULT:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}} +; SI-NOT: [[RESULT]] +; SI: buffer_store_dwordx2 [[RESULT]] +define void @unsafe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 { + %sqrt = call double @llvm.sqrt.f64(double %src) + %rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt) + store double %rcp, double addrspace(1)* %out, align 8 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "unsafe-fp-math"="false" "target-features"="-fp32-denormals" } +attributes #2 = { nounwind "unsafe-fp-math"="true" "target-features"="-fp32-denormals" } +attributes #3 = { nounwind "unsafe-fp-math"="false" "target-features"="+fp32-denormals" } +attributes #4 = { nounwind "unsafe-fp-math"="true" "target-features"="+fp32-denormals" } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll new file mode 100644 index 000000000000..76a5757e4c20 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.read.workdim.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA %s + +; GCN-LABEL: {{^}}read_workdim: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] +define void @read_workdim(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.amdgcn.read.workdim() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}read_workdim_known_bits: +; SI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; VI: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c +; GCN-NOT: 0xff +; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN: buffer_store_dword [[VVAL]] +define void @read_workdim_known_bits(i32 addrspace(1)* %out) { +entry: + %dim = call i32 @llvm.amdgcn.read.workdim() #0 + %shl = shl i32 %dim, 24 + %shr = lshr i32 %shl, 24 + store i32 %shr, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}legacy_read_workdim: +; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xb +; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2c +; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOHSA: buffer_store_dword [[VVAL]] +define void @legacy_read_workdim(i32 addrspace(1)* %out) { +entry: + %dim = call i32 @llvm.AMDGPU.read.workdim() #0 + store i32 %dim, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.amdgcn.read.workdim() #0 +declare i32 @llvm.AMDGPU.read.workdim() #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll new file mode 100644 index 000000000000..73a5c54e175e --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.clamp.ll @@ -0,0 +1,49 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=FUNC %s + +declare float @llvm.amdgcn.rsq.clamp.f32(float) #1 +declare double @llvm.amdgcn.rsq.clamp.f64(double) #1 + +; FUNC-LABEL: {{^}}rsq_clamp_f32: +; SI: v_rsq_clamp_f32_e32 + +; VI: s_load_dword [[SRC:s[0-9]+]] +; VI-DAG: v_rsq_f32_e32 [[RSQ:v[0-9]+]], [[SRC]] +; VI-DAG: v_min_f32_e32 [[MIN:v[0-9]+]], 0x7f7fffff, [[RSQ]] +; TODO: this constant should be folded: +; VI-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0xff7fffff +; VI: v_max_f32_e32 [[RESULT:v[0-9]+]], [[MIN]], [[K]] +; VI: buffer_store_dword [[RESULT]] +define void @rsq_clamp_f32(float addrspace(1)* %out, float %src) #0 { + %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float %src) + store float %rsq_clamp, float addrspace(1)* %out + ret void +} + + +; FUNC-LABEL: {{^}}rsq_clamp_f64: +; SI: v_rsq_clamp_f64_e32 + +; TODO: this constant should be folded: +; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], -1 +; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff +; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff +; VI-DAG: v_rsq_f64_e32 [[RSQ:v\[[0-9]+:[0-9]+\]]], s[{{[0-9]+:[0-9]+}} +; VI-DAG: v_min_f64 v[0:1], [[RSQ]], s{{\[}}[[LOW1]]:[[HIGH1]]] +; VI-DAG: v_max_f64 v[0:1], v[0:1], s{{\[}}[[LOW1]]:[[HIGH2]]] +define void @rsq_clamp_f64(double addrspace(1)* %out, double %src) #0 { + %rsq_clamp = call double @llvm.amdgcn.rsq.clamp.f64(double %src) + store double %rsq_clamp, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}rsq_clamp_undef_f32: +; SI-NOT: v_rsq_clamp_f32 +define void @rsq_clamp_undef_f32(float addrspace(1)* %out) #0 { + %rsq_clamp = call float @llvm.amdgcn.rsq.clamp.f32(float undef) + store float %rsq_clamp, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll new file mode 100644 index 000000000000..47bd0d82b834 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.legacy.ll @@ -0,0 +1,39 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +declare float @llvm.amdgcn.rsq.legacy(float) #0 + +; FUNC-LABEL: {{^}}rsq_legacy_f32: +; SI: v_rsq_legacy_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @rsq_legacy_f32(float addrspace(1)* %out, float %src) #1 { + %rsq = call float @llvm.amdgcn.rsq.legacy(float %src) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; TODO: Really these should be constant folded +; FUNC-LABEL: {{^}}rsq_legacy_f32_constant_4.0 +; SI: v_rsq_legacy_f32_e32 {{v[0-9]+}}, 4.0 +define void @rsq_legacy_f32_constant_4.0(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.legacy(float 4.0) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_legacy_f32_constant_100.0 +; SI: v_rsq_legacy_f32_e32 {{v[0-9]+}}, 0x42c80000 +define void @rsq_legacy_f32_constant_100.0(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.legacy(float 100.0) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_legacy_undef_f32: +; SI-NOT: v_rsq_legacy_f32 +define void @rsq_legacy_undef_f32(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.legacy(float undef) + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll new file mode 100644 index 000000000000..012f6cd82925 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.ll @@ -0,0 +1,68 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s + +declare float @llvm.amdgcn.rsq.f32(float) #0 +declare double @llvm.amdgcn.rsq.f64(double) #0 + +; FUNC-LABEL: {{^}}rsq_f32: +; SI: v_rsq_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @rsq_f32(float addrspace(1)* %out, float %src) #1 { + %rsq = call float @llvm.amdgcn.rsq.f32(float %src) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; TODO: Really these should be constant folded +; FUNC-LABEL: {{^}}rsq_f32_constant_4.0 +; SI: v_rsq_f32_e32 {{v[0-9]+}}, 4.0 +define void @rsq_f32_constant_4.0(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.f32(float 4.0) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_f32_constant_100.0 +; SI: v_rsq_f32_e32 {{v[0-9]+}}, 0x42c80000 +define void @rsq_f32_constant_100.0(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.f32(float 100.0) #0 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_f64: +; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +define void @rsq_f64(double addrspace(1)* %out, double %src) #1 { + %rsq = call double @llvm.amdgcn.rsq.f64(double %src) #0 + store double %rsq, double addrspace(1)* %out, align 4 + ret void +} + +; TODO: Really these should be constant folded +; FUNC-LABEL: {{^}}rsq_f64_constant_4.0 +; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, 4.0 +define void @rsq_f64_constant_4.0(double addrspace(1)* %out) #1 { + %rsq = call double @llvm.amdgcn.rsq.f64(double 4.0) #0 + store double %rsq, double addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_f64_constant_100.0 +; SI-DAG: s_mov_b32 s{{[0-9]+}}, 0x40590000 +; SI-DAG: s_mov_b32 s{{[0-9]+}}, 0{{$}} +; SI: v_rsq_f64_e32 {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} +define void @rsq_f64_constant_100.0(double addrspace(1)* %out) #1 { + %rsq = call double @llvm.amdgcn.rsq.f64(double 100.0) #0 + store double %rsq, double addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}rsq_undef_f32: +; SI-NOT: v_rsq_f32 +define void @rsq_undef_f32(float addrspace(1)* %out) #1 { + %rsq = call float @llvm.amdgcn.rsq.f32(float undef) + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll new file mode 100644 index 000000000000..132e476d5e29 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}test_barrier: +; GCN: buffer_store_dword +; GCN: s_waitcnt +; GCN: s_barrier +define void @test_barrier(i32 addrspace(1)* %out) #0 { +entry: + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp + store i32 %tmp, i32 addrspace(1)* %tmp1 + call void @llvm.amdgcn.s.barrier() + %tmp2 = call i32 @llvm.r600.read.local.size.x() + %tmp3 = sub i32 %tmp2, 1 + %tmp4 = sub i32 %tmp3, %tmp + %tmp5 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp4 + %tmp6 = load i32, i32 addrspace(1)* %tmp5 + store i32 %tmp6, i32 addrspace(1)* %tmp1 + ret void +} + +declare void @llvm.amdgcn.s.barrier() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #2 +declare i32 @llvm.r600.read.local.size.x() #2 + +attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } +attributes #2 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll index f8af67c17ec2..ecd4ac6824cc 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.ll @@ -2,6 +2,7 @@ ; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s declare void @llvm.amdgcn.s.dcache.inv() #0 +declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; GCN-LABEL: {{^}}test_s_dcache_inv: ; GCN-NEXT: ; BB#0: @@ -15,10 +16,11 @@ define void @test_s_dcache_inv() #0 { ; GCN-LABEL: {{^}}test_s_dcache_inv_insert_wait: ; GCN-NEXT: ; BB#0: -; GCN-NEXT: s_dcache_inv -; GCN-NEXT: s_waitcnt lgkmcnt(0) ; encoding +; GCN: s_dcache_inv +; GCN: s_waitcnt lgkmcnt(0) ; encoding define void @test_s_dcache_inv_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.inv() + call void @llvm.amdgcn.s.waitcnt(i32 0) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll index a8502a7c5033..097f35d42c4f 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.inv.vol.ll @@ -2,6 +2,7 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s declare void @llvm.amdgcn.s.dcache.inv.vol() #0 +declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; GCN-LABEL: {{^}}test_s_dcache_inv_vol: ; GCN-NEXT: ; BB#0: @@ -16,9 +17,10 @@ define void @test_s_dcache_inv_vol() #0 { ; GCN-LABEL: {{^}}test_s_dcache_inv_vol_insert_wait: ; GCN-NEXT: ; BB#0: ; GCN-NEXT: s_dcache_inv_vol -; GCN-NEXT: s_waitcnt lgkmcnt(0) ; encoding +; GCN: s_waitcnt lgkmcnt(0) ; encoding define void @test_s_dcache_inv_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.inv.vol() + call void @llvm.amdgcn.s.waitcnt(i32 0) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll index f9ae09b391aa..9ecce7463f6b 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll @@ -1,6 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s declare void @llvm.amdgcn.s.dcache.wb() #0 +declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; VI-LABEL: {{^}}test_s_dcache_wb: ; VI-NEXT: ; BB#0: @@ -14,9 +15,10 @@ define void @test_s_dcache_wb() #0 { ; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait: ; VI-NEXT: ; BB#0: ; VI-NEXT: s_dcache_wb -; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding +; VI: s_waitcnt lgkmcnt(0) ; encoding define void @test_s_dcache_wb_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb() + call void @llvm.amdgcn.s.waitcnt(i32 0) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll index d9145458a1f6..943f8c67a2e3 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.vol.ll @@ -1,6 +1,7 @@ ; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s declare void @llvm.amdgcn.s.dcache.wb.vol() #0 +declare void @llvm.amdgcn.s.waitcnt(i32) #0 ; VI-LABEL: {{^}}test_s_dcache_wb_vol: ; VI-NEXT: ; BB#0: @@ -14,9 +15,10 @@ define void @test_s_dcache_wb_vol() #0 { ; VI-LABEL: {{^}}test_s_dcache_wb_vol_insert_wait: ; VI-NEXT: ; BB#0: ; VI-NEXT: s_dcache_wb_vol -; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding +; VI: s_waitcnt lgkmcnt(0) ; encoding define void @test_s_dcache_wb_vol_insert_wait() #0 { call void @llvm.amdgcn.s.dcache.wb.vol() + call void @llvm.amdgcn.s.waitcnt(i32 0) br label %end end: diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll new file mode 100644 index 000000000000..251eec656edc --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.getreg.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck %s + +; FUNC-LABEL: {{^}}s_getreg_test: +; CHECK: s_getreg_b32 s{{[0-9]+}}, hwreg(HW_REG_LDS_ALLOC, 8, 23) +define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size. + %lds_size_64dwords = call i32 @llvm.amdgcn.s.getreg(i32 45574) #0 + %lds_size_bytes = shl i32 %lds_size_64dwords, 8 + store i32 %lds_size_bytes, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.amdgcn.s.getreg(i32) #0 + +attributes #0 = { nounwind readonly} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll new file mode 100644 index 000000000000..372cba6eb67b --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.memrealtime.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s + +declare i64 @llvm.amdgcn.s.memrealtime() #0 + +; GCN-LABEL: {{^}}test_s_memrealtime: +; GCN-DAG: s_memrealtime s{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: s_load_dwordx2 +; GCN: lgkmcnt +; GCN: buffer_store_dwordx2 +; GCN-NOT: lgkmcnt +; GCN: s_memrealtime s{{\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 +define void @test_s_memrealtime(i64 addrspace(1)* %out) #0 { + %cycle0 = call i64 @llvm.amdgcn.s.memrealtime() + store volatile i64 %cycle0, i64 addrspace(1)* %out + + %cycle1 = call i64 @llvm.amdgcn.s.memrealtime() + store volatile i64 %cycle1, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll new file mode 100644 index 000000000000..8ce2d48733c6 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.memtime.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s + +declare i64 @llvm.amdgcn.s.memtime() #0 + +; GCN-LABEL: {{^}}test_s_memtime: +; GCN-DAG: s_memtime s{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: s_load_dwordx2 +; GCN: lgkmcnt +; GCN: buffer_store_dwordx2 +; GCN-NOT: lgkmcnt +; GCN: s_memtime s{{\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 +define void @test_s_memtime(i64 addrspace(1)* %out) #0 { + %cycle0 = call i64 @llvm.amdgcn.s.memtime() + store volatile i64 %cycle0, i64 addrspace(1)* %out + + %cycle1 = call i64 @llvm.amdgcn.s.memtime() + store volatile i64 %cycle1, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll new file mode 100644 index 000000000000..870aa48a3417 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.ll @@ -0,0 +1,45 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare void @llvm.amdgcn.s.sleep(i32) #0 + +; GCN-LABEL: {{^}}test_s_sleep: +; GCN: s_sleep 0{{$}} +; GCN: s_sleep 1{{$}} +; GCN: s_sleep 2{{$}} +; GCN: s_sleep 3{{$}} +; GCN: s_sleep 4{{$}} +; GCN: s_sleep 5{{$}} +; GCN: s_sleep 6{{$}} +; GCN: s_sleep 7{{$}} +; GCN: s_sleep 8{{$}} +; GCN: s_sleep 9{{$}} +; GCN: s_sleep 10{{$}} +; GCN: s_sleep 11{{$}} +; GCN: s_sleep 12{{$}} +; GCN: s_sleep 13{{$}} +; GCN: s_sleep 14{{$}} +; GCN: s_sleep 15{{$}} +define void @test_s_sleep(i32 %x) #0 { + call void @llvm.amdgcn.s.sleep(i32 0) + call void @llvm.amdgcn.s.sleep(i32 1) + call void @llvm.amdgcn.s.sleep(i32 2) + call void @llvm.amdgcn.s.sleep(i32 3) + call void @llvm.amdgcn.s.sleep(i32 4) + call void @llvm.amdgcn.s.sleep(i32 5) + call void @llvm.amdgcn.s.sleep(i32 6) + call void @llvm.amdgcn.s.sleep(i32 7) + + ; Values that might only work on VI + call void @llvm.amdgcn.s.sleep(i32 8) + call void @llvm.amdgcn.s.sleep(i32 9) + call void @llvm.amdgcn.s.sleep(i32 10) + call void @llvm.amdgcn.s.sleep(i32 11) + call void @llvm.amdgcn.s.sleep(i32 12) + call void @llvm.amdgcn.s.sleep(i32 13) + call void @llvm.amdgcn.s.sleep(i32 14) + call void @llvm.amdgcn.s.sleep(i32 15) + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll new file mode 100644 index 000000000000..c2d48f99aac5 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.s.waitcnt.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK %s + +; CHECK-LABEL: {{^}}test1: +; CHECK: image_store +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0){{$}} +; CHECK-NEXT: image_store +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <4 x float> %d0, <4 x float> %d1, i32 %c0, i32 %c1) { + call void @llvm.amdgcn.image.store.i32(<4 x float> %d0, i32 %c0, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0) + call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 + call void @llvm.amdgcn.image.store.i32(<4 x float> %d1, i32 %c1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 1, i1 0) + ret void +} + +; Test that the intrinsic is merged with automatically generated waits and +; emitted as late as possible. +; +; CHECK-LABEL: {{^}}test2: +; CHECK: image_load +; CHECK-NOT: s_waitcnt vmcnt(0){{$}} +; CHECK: s_waitcnt +; CHECK-NEXT: image_store +define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, i32 %c) { + %t = call <4 x float> @llvm.amdgcn.image.load.i32(i32 %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + call void @llvm.amdgcn.s.waitcnt(i32 3840) ; 0xf00 + %c.1 = mul i32 %c, 2 + call void @llvm.amdgcn.image.store.i32(<4 x float> %t, i32 %c.1, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret void +} + +declare void @llvm.amdgcn.s.waitcnt(i32) #0 + +declare <4 x float> @llvm.amdgcn.image.load.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll new file mode 100644 index 000000000000..9dc4554b88a4 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.sin.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s + +declare float @llvm.amdgcn.sin.f32(float) #0 + +; GCN-LABEL: {{^}}v_sin_f32: +; GCN: v_sin_f32_e32 {{v[0-9]+}}, {{s[0-9]+}} +define void @v_sin_f32(float addrspace(1)* %out, float %src) #1 { + %sin = call float @llvm.amdgcn.sin.f32(float %src) #0 + store float %sin, float addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll new file mode 100644 index 000000000000..7757e411553b --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.trig.preop.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +declare double @llvm.amdgcn.trig.preop.f64(double, i32) nounwind readnone + +; SI-LABEL: {{^}}test_trig_preop_f64: +; SI-DAG: buffer_load_dword [[SEG:v[0-9]+]] +; SI-DAG: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], +; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], [[SEG]] +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm +define void @test_trig_preop_f64(double addrspace(1)* %out, double addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { + %a = load double, double addrspace(1)* %aptr, align 8 + %b = load i32, i32 addrspace(1)* %bptr, align 4 + %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) nounwind readnone + store double %result, double addrspace(1)* %out, align 8 + ret void +} + +; SI-LABEL: {{^}}test_trig_preop_f64_imm_segment: +; SI: buffer_load_dwordx2 [[SRC:v\[[0-9]+:[0-9]+\]]], +; SI: v_trig_preop_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[SRC]], 7 +; SI: buffer_store_dwordx2 [[RESULT]], +; SI: s_endpgm +define void @test_trig_preop_f64_imm_segment(double addrspace(1)* %out, double addrspace(1)* %aptr) nounwind { + %a = load double, double addrspace(1)* %aptr, align 8 + %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) nounwind readnone + store double %result, double addrspace(1)* %out, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll new file mode 100644 index 000000000000..c22eac7e271c --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll @@ -0,0 +1,107 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=CI-HSA %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=VI-HSA %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s + +declare i32 @llvm.amdgcn.workgroup.id.x() #0 +declare i32 @llvm.amdgcn.workgroup.id.y() #0 +declare i32 @llvm.amdgcn.workgroup.id.z() #0 + +; ALL-LABEL {{^}}test_workgroup_id_x: + +; HSA: .amd_kernel_code_t +; HSA: compute_pgm_rsrc2_user_sgpr = 6 +; HSA: compute_pgm_rsrc2_tgid_x_en = 1 +; HSA: compute_pgm_rsrc2_tgid_y_en = 0 +; HSA: compute_pgm_rsrc2_tgid_z_en = 0 +; HSA: compute_pgm_rsrc2_tg_size_en = 0 +; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; HSA: enable_sgpr_grid_workgroup_count_x = 0 +; HSA: enable_sgpr_grid_workgroup_count_y = 0 +; HSA: enable_sgpr_grid_workgroup_count_z = 0 +; HSA: .end_amd_kernel_code_t + +; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s2{{$}} +; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}} + +; ALL-NOT: [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] + +; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workgroup.id.x() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +; ALL-LABEL {{^}}test_workgroup_id_y: +; HSA: compute_pgm_rsrc2_user_sgpr = 6 +; HSA: compute_pgm_rsrc2_tgid_x_en = 1 +; HSA: compute_pgm_rsrc2_tgid_y_en = 1 +; HSA: compute_pgm_rsrc2_tgid_z_en = 0 +; HSA: compute_pgm_rsrc2_tg_size_en = 0 +; HSA: enable_sgpr_grid_workgroup_count_x = 0 +; HSA: enable_sgpr_grid_workgroup_count_y = 0 +; HSA: enable_sgpr_grid_workgroup_count_z = 0 + +; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}} +; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}} + +; ALL-NOT: [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] + +; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 +; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workgroup.id.y() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +; ALL-LABEL {{^}}test_workgroup_id_z: +; HSA: compute_pgm_rsrc2_user_sgpr = 6 +; HSA: compute_pgm_rsrc2_tgid_x_en = 1 +; HSA: compute_pgm_rsrc2_tgid_y_en = 0 +; HSA: compute_pgm_rsrc2_tgid_z_en = 1 +; HSA: compute_pgm_rsrc2_tg_size_en = 0 +; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_dispatch_ptr = 0 +; HSA: enable_sgpr_queue_ptr = 0 +; HSA: enable_sgpr_kernarg_segment_ptr = 1 +; HSA: enable_sgpr_dispatch_id = 0 +; HSA: enable_sgpr_flat_scratch_init = 0 +; HSA: enable_sgpr_private_segment_size = 0 +; HSA: enable_sgpr_grid_workgroup_count_x = 0 +; HSA: enable_sgpr_grid_workgroup_count_y = 0 +; HSA: enable_sgpr_grid_workgroup_count_z = 0 + +; MESA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}} +; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}} + +; ALL-NOT: [[VCOPY]] +; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]] + +; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 +; ALL-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +define void @test_workgroup_id_z(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workgroup.id.z() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll b/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll new file mode 100644 index 000000000000..28ef7b82ef84 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll @@ -0,0 +1,56 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=CI-HSA %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HSA -check-prefix=VI-HSA %s +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s + +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i32 @llvm.amdgcn.workitem.id.y() #0 +declare i32 @llvm.amdgcn.workitem.id.z() #0 + +; MESA: .section .AMDGPU.config +; MESA: .long 47180 +; MESA-NEXT: .long 132{{$}} + +; ALL-LABEL {{^}}test_workitem_id_x: +; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 + +; ALL-NOT: v0 +; ALL: {{buffer|flat}}_store_dword {{.*}}v0 +define void @test_workitem_id_x(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +; MESA: .section .AMDGPU.config +; MESA: .long 47180 +; MESA-NEXT: .long 2180{{$}} + +; ALL-LABEL {{^}}test_workitem_id_y: +; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1 + +; ALL-NOT: v1 +; ALL: {{buffer|flat}}_store_dword {{.*}}v1 +define void @test_workitem_id_y(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.y() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +; MESA: .section .AMDGPU.config +; MESA: .long 47180 +; MESA-NEXT: .long 4228{{$}} + +; ALL-LABEL {{^}}test_workitem_id_z: +; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2 + +; ALL-NOT: v2 +; ALL: {{buffer|flat}}_store_dword {{.*}}v2 +define void @test_workitem_id_z(i32 addrspace(1)* %out) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.z() + store i32 %id, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/llvm.amdgpu.dp4.ll b/test/CodeGen/AMDGPU/llvm.amdgpu.dp4.ll deleted file mode 100644 index 036cd2ca82a6..000000000000 --- a/test/CodeGen/AMDGPU/llvm.amdgpu.dp4.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s - -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) nounwind readnone - -define void @test_dp4(float addrspace(1)* %out, <4 x float> addrspace(1)* %a, <4 x float> addrspace(1)* %b) nounwind { - %src0 = load <4 x float>, <4 x float> addrspace(1)* %a, align 16 - %src1 = load <4 x float>, <4 x float> addrspace(1)* %b, align 16 - %dp4 = call float @llvm.AMDGPU.dp4(<4 x float> %src0, <4 x float> %src1) nounwind readnone - store float %dp4, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll b/test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll index 42df6db1ccfd..6b865d8076e6 100644 --- a/test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll +++ b/test/CodeGen/AMDGPU/llvm.amdgpu.kilp.ll @@ -3,7 +3,7 @@ ; SI-LABEL: {{^}}kilp_gs_const: ; SI: s_mov_b64 exec, 0 -define void @kilp_gs_const() #0 { +define amdgpu_gs void @kilp_gs_const() { main_body: %0 = icmp ule i32 0, 3 %1 = select i1 %0, float 1.000000e+00, float -1.000000e+00 @@ -16,6 +16,4 @@ main_body: declare void @llvm.AMDGPU.kilp(float) -attributes #0 = { "ShaderType"="2" } - !0 = !{!"const", null, i32 1} diff --git a/test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll b/test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll deleted file mode 100644 index 0c3e4ecaa1a0..000000000000 --- a/test/CodeGen/AMDGPU/llvm.amdgpu.lrp.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s - -declare float @llvm.AMDGPU.lrp(float, float, float) nounwind readnone - -; FUNC-LABEL: {{^}}test_lrp: -; SI: v_mad_f32 -; SI: v_mac_f32_e32 -define void @test_lrp(float addrspace(1)* %out, float %src0, float %src1, float %src2) nounwind { - %mad = call float @llvm.AMDGPU.lrp(float %src0, float %src1, float %src2) nounwind readnone - store float %mad, float addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/llvm.cos.ll b/test/CodeGen/AMDGPU/llvm.cos.ll index c65df8b3e8da..eb7dcbbf2346 100644 --- a/test/CodeGen/AMDGPU/llvm.cos.ll +++ b/test/CodeGen/AMDGPU/llvm.cos.ll @@ -1,6 +1,6 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC -;RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc < %s -march=amdgcn | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -mcpu=tonga | FileCheck %s -check-prefix=SI -check-prefix=FUNC +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC ;FUNC-LABEL: test ;EG: MULADD_IEEE * @@ -37,5 +37,3 @@ define void @testv(<4 x float> addrspace(1)* %out, <4 x float> inreg %vx) #1 { declare float @llvm.cos.f32(float) readnone declare <4 x float> @llvm.cos.v4f32(<4 x float>) readnone - -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/llvm.dbg.value.ll b/test/CodeGen/AMDGPU/llvm.dbg.value.ll index b01f8ab2bdf9..1a37ba311606 100644 --- a/test/CodeGen/AMDGPU/llvm.dbg.value.ll +++ b/test/CodeGen/AMDGPU/llvm.dbg.value.ll @@ -14,17 +14,16 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!11, !12} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (trunk 244715) (llvm/trunk 244718)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (trunk 244715) (llvm/trunk 244718)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !1 = !DIFile(filename: "/tmp/test_debug_value.cl", directory: "/Users/matt/src/llvm/build_debug") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "test_debug_value", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, variables: !9) +!4 = distinct !DISubprogram(name: "test_debug_value", scope: !1, file: !1, line: 1, type: !5, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !9) !5 = !DISubroutineType(types: !6) !6 = !{null, !7} !7 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64, align: 32) diff --git a/test/CodeGen/AMDGPU/llvm.memcpy.ll b/test/CodeGen/AMDGPU/llvm.memcpy.ll index d83ab562b718..8398309d7520 100644 --- a/test/CodeGen/AMDGPU/llvm.memcpy.ll +++ b/test/CodeGen/AMDGPU/llvm.memcpy.ll @@ -6,77 +6,77 @@ declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1: -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 - -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 - -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 - -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 + +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 + +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 + +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 +; SI-DAG: ds_read_u8 + +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 + +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 + +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 + +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 +; SI-DAG: ds_write_b8 ; SI: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align1(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { @@ -87,41 +87,41 @@ define void @test_small_memcpy_i64_lds_to_lds_align1(i64 addrspace(3)* noalias % } ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align2: -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 - -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 - -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 - -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 -; SI: ds_write_b16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 + +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 +; SI-DAG: ds_read_u16 + +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 + +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 +; SI-DAG: ds_write_b16 ; SI: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align2(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { @@ -153,15 +153,11 @@ define void @test_small_memcpy_i64_lds_to_lds_align4(i64 addrspace(3)* noalias % ; FIXME: Use 64-bit ops ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align8: -; SI: ds_read_b64 -; SI: ds_read_b64 -; SI: ds_read_b64 -; SI: ds_read_b64 +; SI: ds_read2_b64 +; SI: ds_read2_b64 -; SI: ds_write_b64 -; SI: ds_write_b64 -; SI: ds_write_b64 -; SI: ds_write_b64 +; SI: ds_write2_b64 +; SI: ds_write2_b64 ; SI-DAG: s_endpgm define void @test_small_memcpy_i64_lds_to_lds_align8(i64 addrspace(3)* noalias %out, i64 addrspace(3)* noalias %in) nounwind { diff --git a/test/CodeGen/AMDGPU/llvm.pow.ll b/test/CodeGen/AMDGPU/llvm.pow.ll index c4ae652619c2..3f203ddf93b8 100644 --- a/test/CodeGen/AMDGPU/llvm.pow.ll +++ b/test/CodeGen/AMDGPU/llvm.pow.ll @@ -5,12 +5,12 @@ ;CHECK-NEXT: MUL NON-IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, -define void @test1(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test1(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = call float @llvm.pow.f32( float %r0, float %r1) %vec = insertelement <4 x float> undef, float %r2, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } @@ -27,14 +27,12 @@ define void @test1(<4 x float> inreg %reg0) #0 { ;CHECK-NEXT: MUL NON-IEEE T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PS}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}, -define void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_ps void @test2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { %vec = call <4 x float> @llvm.pow.v4f32( <4 x float> %reg0, <4 x float> %reg1) - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } declare float @llvm.pow.f32(float ,float ) readonly declare <4 x float> @llvm.pow.v4f32(<4 x float> ,<4 x float> ) readonly -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/llvm.r600.dot4.ll b/test/CodeGen/AMDGPU/llvm.r600.dot4.ll new file mode 100644 index 000000000000..4db29c58385e --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.dot4.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s + +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) nounwind readnone + +define void @test_dp4(float addrspace(1)* %out, <4 x float> addrspace(1)* %a, <4 x float> addrspace(1)* %b) nounwind { + %src0 = load <4 x float>, <4 x float> addrspace(1)* %a, align 16 + %src1 = load <4 x float>, <4 x float> addrspace(1)* %b, align 16 + %dp4 = call float @llvm.r600.dot4(<4 x float> %src0, <4 x float> %src1) nounwind readnone + store float %dp4, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll b/test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll new file mode 100644 index 000000000000..e4e6dd8e1069 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.group.barrier.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s + +; EG-LABEL: {{^}}test_group_barrier: +; EG: GROUP_BARRIER +define void @test_group_barrier(i32 addrspace(1)* %out) #0 { +entry: + %tmp = call i32 @llvm.r600.read.tidig.x() + %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp + store i32 %tmp, i32 addrspace(1)* %tmp1 + call void @llvm.r600.group.barrier() + %tmp2 = call i32 @llvm.r600.read.local.size.x() + %tmp3 = sub i32 %tmp2, 1 + %tmp4 = sub i32 %tmp3, %tmp + %tmp5 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp4 + %tmp6 = load i32, i32 addrspace(1)* %tmp5 + store i32 %tmp6, i32 addrspace(1)* %tmp1 + ret void +} + +; Function Attrs: convergent nounwind +declare void @llvm.r600.group.barrier() #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.tidig.x() #2 + +; Function Attrs: nounwind readnone +declare i32 @llvm.r600.read.local.size.x() #2 + +attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } +attributes #2 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll b/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll new file mode 100644 index 000000000000..2f5947395c43 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.read.workdim.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s + +; EG-LABEL: {{^}}read_workdim: +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV * [[VAL]], KC0[2].Z +define void @read_workdim(i32 addrspace(1)* %out) { +entry: + %dim = call i32 @llvm.r600.read.workdim() #0 + store i32 %dim, i32 addrspace(1)* %out + ret void +} + +; EG-LABEL: {{^}}read_workdim_known_bits: +define void @read_workdim_known_bits(i32 addrspace(1)* %out) { +entry: + %dim = call i32 @llvm.r600.read.workdim() #0 + %shl = shl i32 %dim, 24 + %shr = lshr i32 %shl, 24 + store i32 %shr, i32 addrspace(1)* %out + ret void +} + +; EG-LABEL: {{^}}legacy_read_workdim: +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV * [[VAL]], KC0[2].Z +define void @legacy_read_workdim(i32 addrspace(1)* %out) { +entry: + %dim = call i32 @llvm.AMDGPU.read.workdim() #0 + store i32 %dim, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.r600.read.workdim() #0 +declare i32 @llvm.AMDGPU.read.workdim() #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll b/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll new file mode 100644 index 000000000000..1c6e7950e9b7 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.clamped.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s + +declare float @llvm.r600.recipsqrt.clamped.f32(float) nounwind readnone + +; EG-LABEL: {{^}}rsq_clamped_f32: +; EG: RECIPSQRT_CLAMPED +define void @rsq_clamped_f32(float addrspace(1)* %out, float %src) nounwind { + %rsq_clamped = call float @llvm.r600.recipsqrt.clamped.f32(float %src) + store float %rsq_clamped, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll b/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll new file mode 100644 index 000000000000..1d6bff01e662 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.recipsqrt.ieee.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s + +declare float @llvm.r600.recipsqrt.ieee.f32(float) nounwind readnone + +; EG-LABEL: {{^}}recipsqrt.ieee_f32: +; EG: RECIPSQRT_IEEE +define void @recipsqrt.ieee_f32(float addrspace(1)* %out, float %src) nounwind { + %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float %src) nounwind readnone + store float %recipsqrt.ieee, float addrspace(1)* %out, align 4 + ret void +} + +; TODO: Really these should be constant folded +; EG-LABEL: {{^}}recipsqrt.ieee_f32_constant_4.0 +; EG: RECIPSQRT_IEEE +define void @recipsqrt.ieee_f32_constant_4.0(float addrspace(1)* %out) nounwind { + %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float 4.0) nounwind readnone + store float %recipsqrt.ieee, float addrspace(1)* %out, align 4 + ret void +} + +; EG-LABEL: {{^}}recipsqrt.ieee_f32_constant_100.0 +; EG: RECIPSQRT_IEEE +define void @recipsqrt.ieee_f32_constant_100.0(float addrspace(1)* %out) nounwind { + %recipsqrt.ieee = call float @llvm.r600.recipsqrt.ieee.f32(float 100.0) nounwind readnone + store float %recipsqrt.ieee, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/llvm.r600.tex.ll b/test/CodeGen/AMDGPU/llvm.r600.tex.ll new file mode 100644 index 000000000000..409037f3e976 --- /dev/null +++ b/test/CodeGen/AMDGPU/llvm.r600.tex.ll @@ -0,0 +1,65 @@ +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s + +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZZ}} RID:0 SID:0 CT:UUNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYYW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYYZ}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN +;CHECK: TEX_SAMPLE_C T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNNN +;CHECK: TEX_SAMPLE T{{[0-9]+\.XYZW, T[0-9]+\.XYZW}} RID:0 SID:0 CT:NNUN + +define void @test(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { +bb: + %addr = load <4 x float>, <4 x float> addrspace(1)* %in + %tmp = shufflevector <4 x float> %addr, <4 x float> %addr, <4 x i32> + %tmp1 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> %tmp1, <4 x i32> + %tmp3 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp3, <4 x i32> + %tmp5 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp6 = shufflevector <4 x float> %tmp5, <4 x float> %tmp5, <4 x i32> + %tmp7 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1) + %tmp10 = shufflevector <4 x float> %tmp9, <4 x float> %tmp9, <4 x i32> + %tmp11 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp12 = shufflevector <4 x float> %tmp11, <4 x float> %tmp11, <4 x i32> + %tmp13 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp14 = shufflevector <4 x float> %tmp13, <4 x float> %tmp13, <4 x i32> + %tmp15 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1) + %tmp16 = shufflevector <4 x float> %tmp15, <4 x float> %tmp15, <4 x i32> + %tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1) + %tmp18 = shufflevector <4 x float> %tmp17, <4 x float> %tmp17, <4 x i32> + %tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1) + %tmp20 = shufflevector <4 x float> %tmp19, <4 x float> %tmp19, <4 x i32> + %tmp21 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1) + %tmp22 = shufflevector <4 x float> %tmp21, <4 x float> %tmp21, <4 x i32> + %tmp23 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1) + %tmp24 = shufflevector <4 x float> %tmp23, <4 x float> %tmp23, <4 x i32> + %tmp25 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp26 = shufflevector <4 x float> %tmp25, <4 x float> %tmp25, <4 x i32> + %tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp28 = shufflevector <4 x float> %tmp27, <4 x float> %tmp27, <4 x i32> + %tmp29 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp28, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp30 = shufflevector <4 x float> %tmp29, <4 x float> %tmp29, <4 x i32> + %tmp31 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp30, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1) + store <4 x float> %tmp31, <4 x float> addrspace(1)* %out + ret void +} + +; Function Attrs: readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +; Function Attrs: readnone +declare <4 x float> @llvm.r600.texc(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/llvm.rint.ll b/test/CodeGen/AMDGPU/llvm.rint.ll index 661db51ad032..cf7c0e4c6fb6 100644 --- a/test/CodeGen/AMDGPU/llvm.rint.ll +++ b/test/CodeGen/AMDGPU/llvm.rint.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; FUNC-LABEL: {{^}}rint_f32: ; R600: RNDNE @@ -43,18 +43,6 @@ entry: ret void } -; FUNC-LABEL: {{^}}legacy_amdil_round_nearest_f32: -; R600: RNDNE - -; SI: v_rndne_f32_e32 -define void @legacy_amdil_round_nearest_f32(float addrspace(1)* %out, float %in) { -entry: - %0 = call float @llvm.AMDIL.round.nearest.f32(float %in) #0 - store float %0, float addrspace(1)* %out - ret void -} - -declare float @llvm.AMDIL.round.nearest.f32(float) #0 declare float @llvm.rint.f32(float) #0 declare <2 x float> @llvm.rint.v2f32(<2 x float>) #0 declare <4 x float> @llvm.rint.v4f32(<4 x float>) #0 diff --git a/test/CodeGen/AMDGPU/llvm.round.f64.ll b/test/CodeGen/AMDGPU/llvm.round.f64.ll index 98afbeee93e6..a8024b713261 100644 --- a/test/CodeGen/AMDGPU/llvm.round.f64.ll +++ b/test/CodeGen/AMDGPU/llvm.round.f64.ll @@ -13,7 +13,7 @@ define void @round_f64(double addrspace(1)* %out, double %x) #0 { ; FUNC-LABEL: {{^}}v_round_f64: ; SI: buffer_load_dwordx2 -; SI: v_bfe_u32 [[EXP:v[0-9]+]], v{{[0-9]+}}, 20, 11 +; SI-DAG: v_bfe_u32 [[EXP:v[0-9]+]], v{{[0-9]+}}, 20, 11 ; SI-DAG: v_not_b32_e32 ; SI-DAG: v_not_b32_e32 @@ -27,7 +27,7 @@ define void @round_f64(double addrspace(1)* %out, double %x) #0 { ; SI: buffer_store_dwordx2 ; SI: s_endpgm define void @v_round_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %gep = getelementptr double, double addrspace(1)* %in, i32 %tid %out.gep = getelementptr double, double addrspace(1)* %out, i32 %tid %x = load double, double addrspace(1)* %gep @@ -60,7 +60,7 @@ define void @round_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %in) #0 { ret void } -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 declare double @llvm.round.f64(double) #1 declare <2 x double> @llvm.round.v2f64(<2 x double>) #1 diff --git a/test/CodeGen/AMDGPU/llvm.round.ll b/test/CodeGen/AMDGPU/llvm.round.ll index d0e49243ffa7..9b7bb00d3c38 100644 --- a/test/CodeGen/AMDGPU/llvm.round.ll +++ b/test/CodeGen/AMDGPU/llvm.round.ll @@ -5,9 +5,9 @@ ; FUNC-LABEL: {{^}}round_f32: ; SI-DAG: s_load_dword [[SX:s[0-9]+]] ; SI-DAG: s_mov_b32 [[K:s[0-9]+]], 0x7fffffff -; SI: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]] -; SI: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]] -; SI: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]] +; SI-DAG: v_trunc_f32_e32 [[TRUNC:v[0-9]+]], [[SX]] +; SI-DAG: v_sub_f32_e32 [[SUB:v[0-9]+]], [[SX]], [[TRUNC]] +; SI-DAG: v_mov_b32_e32 [[VX:v[0-9]+]], [[SX]] ; SI: v_bfi_b32 [[COPYSIGN:v[0-9]+]], [[K]], 1.0, [[VX]] ; SI: v_cmp_le_f32_e64 vcc, 0.5, |[[SUB]]| ; SI: v_cndmask_b32_e32 [[SEL:v[0-9]+]], 0, [[VX]] diff --git a/test/CodeGen/AMDGPU/llvm.sin.ll b/test/CodeGen/AMDGPU/llvm.sin.ll index 3bb245c2e249..04754396a0f7 100644 --- a/test/CodeGen/AMDGPU/llvm.sin.ll +++ b/test/CodeGen/AMDGPU/llvm.sin.ll @@ -1,8 +1,5 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=SI-SAFE -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI -check-prefix=SI-UNSAFE -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: sin_f32 ; EG: MULADD_IEEE * @@ -10,58 +7,91 @@ ; EG: ADD * ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN + ; SI: v_mul_f32 ; SI: v_fract_f32 ; SI: v_sin_f32 ; SI-NOT: v_sin_f32 - define void @sin_f32(float addrspace(1)* %out, float %x) #1 { %sin = call float @llvm.sin.f32(float %x) store float %sin, float addrspace(1)* %out ret void } -; FUNC-LABEL: {{^}}sin_3x_f32: -; SI-UNSAFE-NOT: v_add_f32 -; SI-UNSAFE: 0x3ef47644 -; SI-UNSAFE: v_mul_f32 -; SI-SAFE: v_mul_f32 -; SI-SAFE: v_mul_f32 +; FUNC-LABEL: {{^}}safe_sin_3x_f32: +; SI: v_mul_f32 +; SI: v_mul_f32 ; SI: v_fract_f32 ; SI: v_sin_f32 ; SI-NOT: v_sin_f32 -define void @sin_3x_f32(float addrspace(1)* %out, float %x) #1 { +define void @safe_sin_3x_f32(float addrspace(1)* %out, float %x) #1 { %y = fmul float 3.0, %x %sin = call float @llvm.sin.f32(float %y) store float %sin, float addrspace(1)* %out ret void } -; FUNC-LABEL: {{^}}sin_2x_f32: -; SI-UNSAFE-NOT: v_add_f32 -; SI-UNSAFE: 0x3ea2f983 -; SI-UNSAFE: v_mul_f32 -; SI-SAFE: v_add_f32 -; SI-SAFE: v_mul_f32 +; FUNC-LABEL: {{^}}unsafe_sin_3x_f32: +; SI-NOT: v_add_f32 +; SI: 0x3ef47644 +; SI: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 +define void @unsafe_sin_3x_f32(float addrspace(1)* %out, float %x) #2 { + %y = fmul float 3.0, %x + %sin = call float @llvm.sin.f32(float %y) + store float %sin, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}safe_sin_2x_f32: +; SI: v_add_f32 +; SI: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 +define void @safe_sin_2x_f32(float addrspace(1)* %out, float %x) #1 { + %y = fmul float 2.0, %x + %sin = call float @llvm.sin.f32(float %y) + store float %sin, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}unsafe_sin_2x_f32: +; SI-NOT: v_add_f32 +; SI: 0x3ea2f983 +; SI: v_mul_f32 ; SI: v_fract_f32 ; SI: v_sin_f32 ; SI-NOT: v_sin_f32 -define void @sin_2x_f32(float addrspace(1)* %out, float %x) #1 { +define void @unsafe_sin_2x_f32(float addrspace(1)* %out, float %x) #2 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) store float %sin, float addrspace(1)* %out ret void } -; FUNC-LABEL: {{^}}test_2sin_f32: -; SI-UNSAFE: 0x3ea2f983 -; SI-UNSAFE: v_mul_f32 -; SI-SAFE: v_add_f32 -; SI-SAFE: v_mul_f32 +; FUNC-LABEL: {{^}}test_safe_2sin_f32: +; SI: v_add_f32 +; SI: v_mul_f32 ; SI: v_fract_f32 ; SI: v_sin_f32 ; SI-NOT: v_sin_f32 -define void @test_2sin_f32(float addrspace(1)* %out, float %x) #1 { +define void @test_safe_2sin_f32(float addrspace(1)* %out, float %x) #1 { + %y = fmul float 2.0, %x + %sin = call float @llvm.sin.f32(float %y) + store float %sin, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}test_unsafe_2sin_f32: +; SI: 0x3ea2f983 +; SI: v_mul_f32 +; SI: v_fract_f32 +; SI: v_sin_f32 +; SI-NOT: v_sin_f32 +define void @test_unsafe_2sin_f32(float addrspace(1)* %out, float %x) #2 { %y = fmul float 2.0, %x %sin = call float @llvm.sin.f32(float %y) store float %sin, float addrspace(1)* %out @@ -74,19 +104,21 @@ define void @test_2sin_f32(float addrspace(1)* %out, float %x) #1 { ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}} ; EG-NOT: SIN + ; SI: v_sin_f32 ; SI: v_sin_f32 ; SI: v_sin_f32 ; SI: v_sin_f32 ; SI-NOT: v_sin_f32 - define void @sin_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 { %sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx) store <4 x float> %sin, <4 x float> addrspace(1)* %out ret void } -declare float @llvm.sin.f32(float) readnone -declare <4 x float> @llvm.sin.v4f32(<4 x float>) readnone +declare float @llvm.sin.f32(float) #0 +declare <4 x float> @llvm.sin.v4f32(<4 x float>) #0 -attributes #0 = { "ShaderType"="0" } +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "unsafe-fp-math"="false" } +attributes #2 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/llvm.sqrt.ll b/test/CodeGen/AMDGPU/llvm.sqrt.ll deleted file mode 100644 index c6da047f5392..000000000000 --- a/test/CodeGen/AMDGPU/llvm.sqrt.ll +++ /dev/null @@ -1,105 +0,0 @@ -; RUN: llc < %s -march=r600 --mcpu=redwood | FileCheck %s --check-prefix=R600 -; RUN: llc < %s -march=amdgcn --mcpu=SI -verify-machineinstrs| FileCheck %s --check-prefix=SI -; RUN: llc < %s -march=amdgcn --mcpu=tonga -verify-machineinstrs| FileCheck %s --check-prefix=SI - -; R600-LABEL: {{^}}sqrt_f32: -; R600: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].Z -; R600: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].Z, PS -; SI-LABEL: {{^}}sqrt_f32: -; SI: v_sqrt_f32_e32 -define void @sqrt_f32(float addrspace(1)* %out, float %in) { -entry: - %0 = call float @llvm.sqrt.f32(float %in) - store float %0, float addrspace(1)* %out - ret void -} - -; R600-LABEL: {{^}}sqrt_v2f32: -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[2].W -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[2].W, PS -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].X -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].X, PS -; SI-LABEL: {{^}}sqrt_v2f32: -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -define void @sqrt_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) { -entry: - %0 = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) - store <2 x float> %0, <2 x float> addrspace(1)* %out - ret void -} - -; R600-LABEL: {{^}}sqrt_v4f32: -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Y -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Y, PS -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].Z -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].Z, PS -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[3].W -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[3].W, PS -; R600-DAG: RECIPSQRT_CLAMPED * T{{[0-9]\.[XYZW]}}, KC0[4].X -; R600-DAG: MUL NON-IEEE T{{[0-9]\.[XYZW]}}, KC0[4].X, PS -; SI-LABEL: {{^}}sqrt_v4f32: -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -define void @sqrt_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) { -entry: - %0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) - store <4 x float> %0, <4 x float> addrspace(1)* %out - ret void -} - -; SI-LABEL: {{^}}elim_redun_check: -; SI: v_sqrt_f32_e32 -; SI-NOT: v_cndmask -define void @elim_redun_check(float addrspace(1)* %out, float %in) { -entry: - %sqrt = call float @llvm.sqrt.f32(float %in) - %cmp = fcmp olt float %in, -0.000000e+00 - %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt - store float %res, float addrspace(1)* %out - ret void -} - -; SI-LABEL: {{^}}elim_redun_check_ult: -; SI: v_sqrt_f32_e32 -; SI-NOT: v_cndmask -define void @elim_redun_check_ult(float addrspace(1)* %out, float %in) { -entry: - %sqrt = call float @llvm.sqrt.f32(float %in) - %cmp = fcmp ult float %in, -0.000000e+00 - %res = select i1 %cmp, float 0x7FF8000000000000, float %sqrt - store float %res, float addrspace(1)* %out - ret void -} - -; SI-LABEL: {{^}}elim_redun_check_v2: -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -; SI-NOT: v_cndmask -define void @elim_redun_check_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) { -entry: - %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) - %cmp = fcmp olt <2 x float> %in, - %res = select <2 x i1> %cmp, <2 x float> , <2 x float> %sqrt - store <2 x float> %res, <2 x float> addrspace(1)* %out - ret void -} - -; SI-LABEL: {{^}}elim_redun_check_v2_ult -; SI: v_sqrt_f32_e32 -; SI: v_sqrt_f32_e32 -; SI-NOT: v_cndmask -define void @elim_redun_check_v2_ult(<2 x float> addrspace(1)* %out, <2 x float> %in) { -entry: - %sqrt = call <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) - %cmp = fcmp ult <2 x float> %in, - %res = select <2 x i1> %cmp, <2 x float> , <2 x float> %sqrt - store <2 x float> %res, <2 x float> addrspace(1)* %out - ret void -} - -declare float @llvm.sqrt.f32(float %in) -declare <2 x float> @llvm.sqrt.v2f32(<2 x float> %in) -declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %in) diff --git a/test/CodeGen/AMDGPU/load-constant-f64.ll b/test/CodeGen/AMDGPU/load-constant-f64.ll new file mode 100644 index 000000000000..f94a3785a685 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-f64.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}constant_load_f64: +; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}] +; GCN-NOHSA: buffer_store_dwordx2 +; GCN-HSA: flat_store_dwordx2 +define void @constant_load_f64(double addrspace(1)* %out, double addrspace(2)* %in) #0 { + %ld = load double, double addrspace(2)* %in + store double %ld, double addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-constant-i1.ll b/test/CodeGen/AMDGPU/load-constant-i1.ll new file mode 100644 index 000000000000..f15e4f484ffa --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-i1.ll @@ -0,0 +1,371 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}constant_load_i1: +; GCN: buffer_load_ubyte +; GCN: v_and_b32_e32 v{{[0-9]+}}, 1 +; GCN: buffer_store_byte + +; EG: VTX_READ_8 +; EG: AND_INT +define void @constant_load_i1(i1 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { + %load = load i1, i1 addrspace(2)* %in + store i1 %load, i1 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v2i1: +define void @constant_load_v2i1(<2 x i1> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(2)* %in + store <2 x i1> %load, <2 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v3i1: +define void @constant_load_v3i1(<3 x i1> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(2)* %in + store <3 x i1> %load, <3 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v4i1: +define void @constant_load_v4i1(<4 x i1> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(2)* %in + store <4 x i1> %load, <4 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v8i1: +define void @constant_load_v8i1(<8 x i1> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(2)* %in + store <8 x i1> %load, <8 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v16i1: +define void @constant_load_v16i1(<16 x i1> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(2)* %in + store <16 x i1> %load, <16 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v32i1: +define void @constant_load_v32i1(<32 x i1> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(2)* %in + store <32 x i1> %load, <32 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v64i1: +define void @constant_load_v64i1(<64 x i1> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(2)* %in + store <64 x i1> %load, <64 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i1_to_i32: +; GCN: buffer_load_ubyte +; GCN: buffer_store_dword +define void @constant_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { + %a = load i1, i1 addrspace(2)* %in + %ext = zext i1 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i1_to_i32: +; GCN: buffer_load_ubyte +; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}} +; GCN: buffer_store_dword + +; EG: VTX_READ_8 +; EG: BFE_INT +define void @constant_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { + %a = load i1, i1 addrspace(2)* %in + %ext = sext i1 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i32: +define void @constant_zextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(2)* %in + %ext = zext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i32: +define void @constant_sextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(2)* %in + %ext = sext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i32: +define void @constant_zextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(2)* %in + %ext = zext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i32: +define void @constant_sextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(2)* %in + %ext = sext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i32: +define void @constant_zextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(2)* %in + %ext = zext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i32: +define void @constant_sextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(2)* %in + %ext = sext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i32: +define void @constant_zextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(2)* %in + %ext = zext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i32: +define void @constant_sextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(2)* %in + %ext = sext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i32: +define void @constant_zextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(2)* %in + %ext = zext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i32: +define void @constant_sextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(2)* %in + %ext = sext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i32: +define void @constant_zextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(2)* %in + %ext = zext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i32: +define void @constant_sextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(2)* %in + %ext = sext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i32: +define void @constant_zextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(2)* %in + %ext = zext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i32: +define void @constant_sextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(2)* %in + %ext = sext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i32: +define void @constant_zextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(2)* %in + %ext = zext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i32: +define void @constant_sextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(2)* %in + %ext = sext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i1_to_i64: +; GCN-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]], +; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}} +; GCN-DAG: v_and_b32_e32 {{v[0-9]+}}, 1, [[LOAD]] +; GCN: buffer_store_dwordx2 +define void @constant_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { + %a = load i1, i1 addrspace(2)* %in + %ext = zext i1 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i1_to_i64: +; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]], +; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}} +; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]] +; GCN: buffer_store_dwordx2 +define void @constant_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { + %a = load i1, i1 addrspace(2)* %in + %ext = sext i1 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i64: +define void @constant_zextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(2)* %in + %ext = zext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i64: +define void @constant_sextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(2)* %in + %ext = sext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i64: +define void @constant_zextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(2)* %in + %ext = zext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i64: +define void @constant_sextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(2)* %in + %ext = sext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i64: +define void @constant_zextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(2)* %in + %ext = zext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i64: +define void @constant_sextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(2)* %in + %ext = sext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i64: +define void @constant_zextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(2)* %in + %ext = zext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i64: +define void @constant_sextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(2)* %in + %ext = sext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i64: +define void @constant_zextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(2)* %in + %ext = zext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i64: +define void @constant_sextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(2)* %in + %ext = sext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i64: +define void @constant_zextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(2)* %in + %ext = zext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i64: +define void @constant_sextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(2)* %in + %ext = sext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i64: +define void @constant_zextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(2)* %in + %ext = zext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i64: +define void @constant_sextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(2)* %in + %ext = sext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i64: +define void @constant_zextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(2)* %in + %ext = zext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i64: +define void @constant_sextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(2)* %in + %ext = sext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-constant-i16.ll b/test/CodeGen/AMDGPU/load-constant-i16.ll new file mode 100644 index 000000000000..ef9791d8f7a1 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-i16.ll @@ -0,0 +1,441 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}constant_load_i16: +; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} +; GCN-HSA: flat_load_ushort + +; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @constant_load_i16(i16 addrspace(1)* %out, i16 addrspace(2)* %in) { +entry: + %ld = load i16, i16 addrspace(2)* %in + store i16 %ld, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v2i16: +; GCN: s_load_dword s + +; EG: VTX_READ_32 +define void @constant_load_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) { +entry: + %ld = load <2 x i16>, <2 x i16> addrspace(2)* %in + store <2 x i16> %ld, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v3i16: +; GCN: s_load_dwordx2 s + +; EG-DAG: VTX_READ_32 +; EG-DAG: VTX_READ_16 +define void @constant_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in + store <3 x i16> %ld, <3 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v4i16: +; GCN: s_load_dwordx2 + +; EG: VTX_READ_64 +define void @constant_load_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) { +entry: + %ld = load <4 x i16>, <4 x i16> addrspace(2)* %in + store <4 x i16> %ld, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v8i16: +; GCN: s_load_dwordx4 + +; EG: VTX_READ_128 +define void @constant_load_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) { +entry: + %ld = load <8 x i16>, <8 x i16> addrspace(2)* %in + store <8 x i16> %ld, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v16i16: +; GCN: s_load_dwordx8 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v16i16(<16 x i16> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) { +entry: + %ld = load <16 x i16>, <16 x i16> addrspace(2)* %in + store <16 x i16> %ld, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i16_to_i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-NOHSA: buffer_store_dword + +; GCN-HSA: flat_load_ushort +; GCN-HSA: flat_store_dword + +; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +define void @constant_zextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { + %a = load i16, i16 addrspace(2)* %in + %ext = zext i16 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i16_to_i32: +; GCN-NOHSA: buffer_load_sshort +; GCN-NOHSA: buffer_store_dword + +; GCN-HSA: flat_load_sshort +; GCN-HSA: flat_store_dword + +; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal +; EG: 16 +define void @constant_sextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { + %a = load i16, i16 addrspace(2)* %in + %ext = sext i16 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-HSA: flat_load_ushort +define void @constant_zextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(2)* %in + %ext = zext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i32: +; GCN-NOHSA: buffer_load_sshort +; GCN-HSA: flat_load_sshort +define void @constant_sextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(2)* %in + %ext = sext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i32: +; GCN: s_load_dword s +; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffff{{$}} +; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 +define void @constant_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(2)* %in + %ext = zext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i32: +; GCN: s_load_dword s +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i16 + +; EG-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: 16 +; EG-DAG: 16 +define void @constant_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(2)* %in + %ext = sext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_constant_zextload_v3i16_to_v3i32: +; GCN: s_load_dwordx2 +define void @constant_constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in + %ext = zext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_constant_sextload_v3i16_to_v3i32: +; GCN: s_load_dwordx2 +define void @constant_constant_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(2)* %in + %ext = sext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_constant_zextload_v4i16_to_v4i32: +; GCN: s_load_dwordx2 +; GCN-DAG: s_and_b32 +; GCN-DAG: s_lshr_b32 + +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +define void @constant_constant_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(2)* %in + %ext = zext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i32: +; GCN: s_load_dwordx2 +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i16 + +; EG-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; EG-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal +; EG-DAG: 16 +; EG-DAG: 16 +; EG-DAG: 16 +; EG-DAG: 16 +define void @constant_sextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(2)* %in + %ext = sext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i32: +; GCN: s_load_dwordx4 +; GCN-DAG: s_and_b32 +; GCN-DAG: s_lshr_b32 +define void @constant_zextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(2)* %in + %ext = zext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i32: +; GCN: s_load_dwordx4 +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i16 +define void @constant_sextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(2)* %in + %ext = sext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i32: +; GCN: s_load_dwordx8 +; GCN-DAG: s_and_b32 +; GCN-DAG: s_lshr_b32 +define void @constant_zextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(2)* %in + %ext = zext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i32: +; GCN: s_load_dwordx8 +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i16 +define void @constant_sextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(2)* %in + %ext = sext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i32: +; GCN-DAG: s_load_dwordx16 +; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} +; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[K]] +; GCN: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 +define void @constant_zextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(2)* %in + %ext = zext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i32: +; GCN: s_load_dwordx16 +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i16 +define void @constant_sextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(2)* %in + %ext = sext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i32: +; GCN: s_load_dwordx16 +; GCN: s_load_dwordx16 +define void @constant_zextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(2)* %in + %ext = zext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i32: +define void @constant_sextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(2)* %in + %ext = sext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i16_to_i64: +; GCN-NOHSA-DAG: buffer_load_ushort v[[LO:[0-9]+]], +; GCN-HSA-DAG: flat_load_ushort v[[LO:[0-9]+]], +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @constant_zextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { + %a = load i16, i16 addrspace(2)* %in + %ext = zext i16 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i16_to_i64: +; GCN-NOHSA-DAG: buffer_load_sshort v[[LO:[0-9]+]], +; GCN-HSA-DAG: flat_load_sshort v[[LO:[0-9]+]], +; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @constant_sextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { + %a = load i16, i16 addrspace(2)* %in + %ext = sext i16 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i64: +define void @constant_zextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(2)* %in + %ext = zext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i64: +define void @constant_sextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(2)* %in + %ext = sext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i64: +define void @constant_zextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(2)* %in + %ext = zext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i64: +define void @constant_sextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(2)* %in + %ext = sext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i64: +define void @constant_zextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(2)* %in + %ext = zext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i64: +define void @constant_sextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(2)* %in + %ext = sext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i64: +define void @constant_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(2)* %in + %ext = zext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i64: +define void @constant_sextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(2)* %in + %ext = sext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i64: +define void @constant_zextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(2)* %in + %ext = zext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i64: +define void @constant_sextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(2)* %in + %ext = sext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i64: +define void @constant_zextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(2)* %in + %ext = zext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i64: +define void @constant_sextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(2)* %in + %ext = sext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; ; XFUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i64: +; define void @constant_zextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in +; %ext = zext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; ; XFUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i64: +; define void @constant_sextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in +; %ext = sext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-constant-i32.ll b/test/CodeGen/AMDGPU/load-constant-i32.ll new file mode 100644 index 000000000000..40c29be60548 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-i32.ll @@ -0,0 +1,380 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}constant_load_i32: +; GCN: s_load_dword s{{[0-9]+}} + +; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @constant_load_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { +entry: + %ld = load i32, i32 addrspace(2)* %in + store i32 %ld, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v2i32: +; GCN: s_load_dwordx2 + +; EG: VTX_READ_64 +define void @constant_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { +entry: + %ld = load <2 x i32>, <2 x i32> addrspace(2)* %in + store <2 x i32> %ld, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v3i32: +; GCN: s_load_dwordx4 + +; EG: VTX_READ_128 +define void @constant_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(2)* %in) #0 { +entry: + %ld = load <3 x i32>, <3 x i32> addrspace(2)* %in + store <3 x i32> %ld, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v4i32: +; GCN: s_load_dwordx4 + +; EG: VTX_READ_128 +define void @constant_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { +entry: + %ld = load <4 x i32>, <4 x i32> addrspace(2)* %in + store <4 x i32> %ld, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v8i32: +; GCN: s_load_dwordx8 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { +entry: + %ld = load <8 x i32>, <8 x i32> addrspace(2)* %in + store <8 x i32> %ld, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v16i32: +; GCN: s_load_dwordx16 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { +entry: + %ld = load <16 x i32>, <16 x i32> addrspace(2)* %in + store <16 x i32> %ld, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i32_to_i64: +; GCN-DAG: s_load_dword s[[SLO:[0-9]+]], +; GCN-DAG: v_mov_b32_e32 v[[SHI:[0-9]+]], 0{{$}} +; GCN: store_dwordx2 + +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG: CF_END +; EG: VTX_READ_32 +define void @constant_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { + %ld = load i32, i32 addrspace(2)* %in + %ext = zext i32 %ld to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i32_to_i64: +; GCN: s_load_dword s[[SLO:[0-9]+]] +; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31 +; GCN: store_dwordx2 + +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG: CF_END +; EG: VTX_READ_32 +; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. +; EG: 31 +define void @constant_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { + %ld = load i32, i32 addrspace(2)* %in + %ext = sext i32 %ld to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i32_to_v1i64: +; GCN: s_load_dword +; GCN: store_dwordx2 +define void @constant_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(2)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(2)* %in + %ext = zext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i32_to_v1i64: +; GCN: s_load_dword s[[LO:[0-9]+]] +; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31 +; GCN: store_dwordx2 +define void @constant_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(2)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(2)* %in + %ext = sext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i32_to_v2i64: +; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} +; GCN: store_dwordx4 +define void @constant_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(2)* %in + %ext = zext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i32_to_v2i64: +; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} + +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_ashr_i32 + +; GCN: store_dwordx4 +define void @constant_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(2)* %in + %ext = sext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i32_to_v4i64: +; GCN: s_load_dwordx4 + +; GCN: store_dwordx4 +; GCN: store_dwordx4 +define void @constant_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(2)* %in + %ext = zext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i32_to_v4i64: +; GCN: s_load_dwordx4 + +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 + +; GCN: store_dwordx4 +; GCN: store_dwordx4 +define void @constant_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(2)* %in + %ext = sext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64: +; GCN: s_load_dwordx8 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-SA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @constant_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(2)* %in + %ext = zext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64: +; GCN: s_load_dwordx8 + +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 +; GCN: s_ashr_i32 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @constant_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(2)* %in + %ext = sext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64: +; GCN: s_load_dwordx16 + + +; GCN-DAG: s_ashr_i32 + +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +; GCN: store_dwordx4 +define void @constant_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(2)* %in + %ext = sext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i32_to_v16i64 +; GCN: s_load_dwordx16 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +define void @constant_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(2)* %in + %ext = zext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64: + +; GCN: s_load_dwordx16 +; GCN: s_load_dwordx16 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +define void @constant_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(2)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(2)* %in + %ext = sext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i32_to_v32i64: +; GCN: s_load_dwordx16 +; GCN: s_load_dwordx16 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @constant_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(2)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(2)* %in + %ext = zext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-constant-i64.ll b/test/CodeGen/AMDGPU/load-constant-i64.ll new file mode 100644 index 000000000000..e4656a2b2ac6 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-i64.ll @@ -0,0 +1,84 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=VI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}constant_load_i64: +; GCN: s_load_dwordx2 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} +; EG: VTX_READ_64 +define void @constant_load_i64(i64 addrspace(1)* %out, i64 addrspace(2)* %in) #0 { + %ld = load i64, i64 addrspace(2)* %in + store i64 %ld, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v2i64: +; GCN: s_load_dwordx4 + +; EG: VTX_READ_128 +define void @constant_load_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(2)* %in) #0 { +entry: + %ld = load <2 x i64>, <2 x i64> addrspace(2)* %in + store <2 x i64> %ld, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v3i64: +; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} + +; EG-DAG: VTX_READ_128 +; EG-DAG: VTX_READ_128 +define void @constant_load_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> addrspace(2)* %in) #0 { +entry: + %ld = load <3 x i64>, <3 x i64> addrspace(2)* %in + store <3 x i64> %ld, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v4i64 +; GCN: s_load_dwordx8 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(2)* %in) #0 { +entry: + %ld = load <4 x i64>, <4 x i64> addrspace(2)* %in + store <4 x i64> %ld, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v8i64: +; GCN: s_load_dwordx16 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v8i64(<8 x i64> addrspace(1)* %out, <8 x i64> addrspace(2)* %in) #0 { +entry: + %ld = load <8 x i64>, <8 x i64> addrspace(2)* %in + store <8 x i64> %ld, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v16i64: +; GCN: s_load_dwordx16 +; GCN: s_load_dwordx16 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @constant_load_v16i64(<16 x i64> addrspace(1)* %out, <16 x i64> addrspace(2)* %in) #0 { +entry: + %ld = load <16 x i64>, <16 x i64> addrspace(2)* %in + store <16 x i64> %ld, <16 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-constant-i8.ll b/test/CodeGen/AMDGPU/load-constant-i8.ll new file mode 100644 index 000000000000..87828982a987 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-constant-i8.ll @@ -0,0 +1,567 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}constant_load_i8: +; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}} +; GCN-HSA: flat_load_ubyte + +; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @constant_load_i8(i8 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { +entry: + %ld = load i8, i8 addrspace(2)* %in + store i8 %ld, i8 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v2i8: +; GCN-NOHSA: buffer_load_ushort v +; GCN-HSA: flat_load_ushort v + +; EG: VTX_READ_16 +define void @constant_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <2 x i8>, <2 x i8> addrspace(2)* %in + store <2 x i8> %ld, <2 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v3i8: +; GCN: s_load_dword s + +; EG-DAG: VTX_READ_32 +define void @constant_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(2)* %in + store <3 x i8> %ld, <3 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v4i8: +; GCN: s_load_dword s + +; EG: VTX_READ_32 +define void @constant_load_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <4 x i8>, <4 x i8> addrspace(2)* %in + store <4 x i8> %ld, <4 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v8i8: +; GCN: s_load_dwordx2 + +; EG: VTX_READ_64 +define void @constant_load_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <8 x i8>, <8 x i8> addrspace(2)* %in + store <8 x i8> %ld, <8 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_load_v16i8: +; GCN: s_load_dwordx4 + +; EG: VTX_READ_128 +define void @constant_load_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <16 x i8>, <16 x i8> addrspace(2)* %in + store <16 x i8> %ld, <16 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i8_to_i32: +; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, +; GCN-HSA: flat_load_ubyte + +; EG: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +define void @constant_zextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %a = load i8, i8 addrspace(2)* %in + %ext = zext i8 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i8_to_i32: +; GCN-NOHSA: buffer_load_sbyte +; GCN-HSA: flat_load_sbyte + +; EG: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal +; EG: 8 +define void @constant_sextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %ld = load i8, i8 addrspace(2)* %in + %ext = sext i8 %ld to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i32: +define void @constant_zextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = zext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i32: +define void @constant_sextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = sext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-HSA: flat_load_ushort +; EG: VTX_READ_8 +; EG: VTX_READ_8 +define void @constant_zextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = zext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i32: +; GCN-NOHSA: buffer_load_ushort + +; GCN-HSA: flat_load_ushort + +; GCN: v_bfe_i32 +; GCN: v_bfe_i32 + +; EG-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: 8 +; EG-DAG: 8 +define void @constant_sextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = sext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v3i8_to_v3i32: +; GCN: s_load_dword s + +; GCN-DAG: s_bfe_u32 +; GCN-DAG: s_bfe_u32 +; GCN-DAG: s_and_b32 +define void @constant_zextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(2)* %in + %ext = zext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v3i8_to_v3i32: +; GCN: s_load_dword s + +; GCN-DAG: s_bfe_i32 +; GCN-DAG: s_bfe_i32 +; GCN-DAG: s_bfe_i32 +define void @constant_sextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(2)* %in + %ext = sext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i32: +; GCN: s_load_dword s +; GCN-DAG: s_and_b32 +; GCN-DAG: s_lshr_b32 + +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +define void @constant_zextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = zext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i32: +; GCN: s_load_dword s +; GCN-DAG: s_sext_i32_i8 +; GCN-DAG: s_ashr_i32 + +; EG-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; EG-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal +; EG-DAG: 8 +; EG-DAG: 8 +; EG-DAG: 8 +; EG-DAG: 8 +define void @constant_sextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = sext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i32: +; GCN: s_load_dwordx2 +; GCN-DAG: s_and_b32 +; GCN-DAG: s_lshr_b32 +define void @constant_zextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = zext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i32: +; GCN: s_load_dwordx2 +; GCN-DAG: s_ashr_i32 +; GCN-DAG: s_sext_i32_i8 +define void @constant_sextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = sext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i32: +define void @constant_zextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = zext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i32: +define void @constant_sextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = sext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i32: +define void @constant_zextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = zext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i32: +define void @constant_sextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = sext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i32: +define void @constant_zextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(2)* %in + %ext = zext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i32: +define void @constant_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(2)* %in + %ext = sext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]], +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] + +; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]], +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] +define void @constant_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %a = load i8, i8 addrspace(2)* %in + %ext = zext i8 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64: +; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]], +; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]], +; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @constant_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %a = load i8, i8 addrspace(2)* %in + %ext = sext i8 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i64: +define void @constant_zextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = zext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i64: +define void @constant_sextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = sext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i64: +define void @constant_zextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = zext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i64: +define void @constant_sextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = sext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i64: +define void @constant_zextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = zext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i64: +define void @constant_sextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = sext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i64: +define void @constant_zextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = zext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i64: +define void @constant_sextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = sext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i64: +define void @constant_zextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = zext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i64: +define void @constant_sextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = sext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i64: +define void @constant_zextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = zext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i64: +define void @constant_sextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = sext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i64: +; define void @constant_zextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in +; %ext = zext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i64: +; define void @constant_sextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in +; %ext = sext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; FUNC-LABEL: {{^}}constant_zextload_i8_to_i16: +; GCN-NOHSA: buffer_load_ubyte v[[VAL:[0-9]+]], +; GCN-NOHSA: buffer_store_short v[[VAL]] + +; GCN-HSA: flat_load_ubyte v[[VAL:[0-9]+]], +; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] +define void @constant_zextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %a = load i8, i8 addrspace(2)* %in + %ext = zext i8 %a to i16 + store i16 %ext, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_i8_to_i16: +; GCN-NOHSA: buffer_load_sbyte v[[VAL:[0-9]+]], +; GCN-HSA: flat_load_sbyte v[[VAL:[0-9]+]], + +; GCN-NOHSA: buffer_store_short v[[VAL]] +; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] +define void @constant_sextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { + %a = load i8, i8 addrspace(2)* %in + %ext = sext i8 %a to i16 + store i16 %ext, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i16: +define void @constant_zextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = zext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i16: +define void @constant_sextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(2)* %in + %ext = sext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i16: +define void @constant_zextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = zext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i16: +define void @constant_sextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(2)* %in + %ext = sext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i16: +define void @constant_zextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = zext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i16: +define void @constant_sextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(2)* %in + %ext = sext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i16: +define void @constant_zextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = zext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i16: +define void @constant_sextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(2)* %in + %ext = sext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i16: +define void @constant_zextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = zext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i16: +define void @constant_sextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(2)* %in + %ext = sext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i16: +define void @constant_zextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = zext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i16: +define void @constant_sextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(2)* %in + %ext = sext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(1)* %out + ret void +} + +; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i16: +; define void @constant_zextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in +; %ext = zext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i16: +; define void @constant_sextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in +; %ext = sext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-f32.ll b/test/CodeGen/AMDGPU/load-global-f32.ll new file mode 100644 index 000000000000..23f4a6079e81 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-f32.ll @@ -0,0 +1,93 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s + +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}global_load_f32: +; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} +; GCN-HSA: flat_load_dword + +; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @global_load_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +entry: + %tmp0 = load float, float addrspace(1)* %in + store float %tmp0, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2f32: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 + +; R600: VTX_READ_64 +define void @global_load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) #0 { +entry: + %tmp0 = load <2 x float>, <2 x float> addrspace(1)* %in + store <2 x float> %tmp0, <2 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3f32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; R600: VTX_READ_128 +define void @global_load_v3f32(<3 x float> addrspace(1)* %out, <3 x float> addrspace(1)* %in) #0 { +entry: + %tmp0 = load <3 x float>, <3 x float> addrspace(1)* %in + store <3 x float> %tmp0, <3 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4f32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; R600: VTX_READ_128 +define void @global_load_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) #0 { +entry: + %tmp0 = load <4 x float>, <4 x float> addrspace(1)* %in + store <4 x float> %tmp0, <4 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8f32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; R600: VTX_READ_128 +; R600: VTX_READ_128 +define void @global_load_v8f32(<8 x float> addrspace(1)* %out, <8 x float> addrspace(1)* %in) #0 { +entry: + %tmp0 = load <8 x float>, <8 x float> addrspace(1)* %in + store <8 x float> %tmp0, <8 x float> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16f32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; R600: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 +; R600: VTX_READ_128 +define void @global_load_v16f32(<16 x float> addrspace(1)* %out, <16 x float> addrspace(1)* %in) #0 { +entry: + %tmp0 = load <16 x float>, <16 x float> addrspace(1)* %in + store <16 x float> %tmp0, <16 x float> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-f64.ll b/test/CodeGen/AMDGPU/load-global-f64.ll new file mode 100644 index 000000000000..a86cc5a6d3d4 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-f64.ll @@ -0,0 +1,94 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}global_load_f64: +; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-NOHSA: buffer_store_dwordx2 [[VAL]] + +; GCN-HSA: flat_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-HSA: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, [[VAL]] +define void @global_load_f64(double addrspace(1)* %out, double addrspace(1)* %in) #0 { + %ld = load double, double addrspace(1)* %in + store double %ld, double addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2f64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_load_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in) #0 { +entry: + %ld = load <2 x double>, <2 x double> addrspace(1)* %in + store <2 x double> %ld, <2 x double> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3f64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_load_v3f64(<3 x double> addrspace(1)* %out, <3 x double> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x double>, <3 x double> addrspace(1)* %in + store <3 x double> %ld, <3 x double> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4f64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_load_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in) #0 { +entry: + %ld = load <4 x double>, <4 x double> addrspace(1)* %in + store <4 x double> %ld, <4 x double> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8f64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_load_v8f64(<8 x double> addrspace(1)* %out, <8 x double> addrspace(1)* %in) #0 { +entry: + %ld = load <8 x double>, <8 x double> addrspace(1)* %in + store <8 x double> %ld, <8 x double> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16f64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_load_v16f64(<16 x double> addrspace(1)* %out, <16 x double> addrspace(1)* %in) #0 { +entry: + %ld = load <16 x double>, <16 x double> addrspace(1)* %in + store <16 x double> %ld, <16 x double> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-i1.ll b/test/CodeGen/AMDGPU/load-global-i1.ll new file mode 100644 index 000000000000..ebfec781087e --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-i1.ll @@ -0,0 +1,371 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}global_load_i1: +; GCN: buffer_load_ubyte +; GCN: v_and_b32_e32 v{{[0-9]+}}, 1 +; GCN: buffer_store_byte + +; EG: VTX_READ_8 +; EG: AND_INT +define void @global_load_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) #0 { + %load = load i1, i1 addrspace(1)* %in + store i1 %load, i1 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2i1: +define void @global_load_v2i1(<2 x i1> addrspace(1)* %out, <2 x i1> addrspace(1)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(1)* %in + store <2 x i1> %load, <2 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3i1: +define void @global_load_v3i1(<3 x i1> addrspace(1)* %out, <3 x i1> addrspace(1)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(1)* %in + store <3 x i1> %load, <3 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4i1: +define void @global_load_v4i1(<4 x i1> addrspace(1)* %out, <4 x i1> addrspace(1)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(1)* %in + store <4 x i1> %load, <4 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8i1: +define void @global_load_v8i1(<8 x i1> addrspace(1)* %out, <8 x i1> addrspace(1)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(1)* %in + store <8 x i1> %load, <8 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16i1: +define void @global_load_v16i1(<16 x i1> addrspace(1)* %out, <16 x i1> addrspace(1)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(1)* %in + store <16 x i1> %load, <16 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v32i1: +define void @global_load_v32i1(<32 x i1> addrspace(1)* %out, <32 x i1> addrspace(1)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(1)* %in + store <32 x i1> %load, <32 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v64i1: +define void @global_load_v64i1(<64 x i1> addrspace(1)* %out, <64 x i1> addrspace(1)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(1)* %in + store <64 x i1> %load, <64 x i1> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i1_to_i32: +; GCN: buffer_load_ubyte +; GCN: buffer_store_dword +define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) #0 { + %a = load i1, i1 addrspace(1)* %in + %ext = zext i1 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i1_to_i32: +; GCN: buffer_load_ubyte +; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}} +; GCN: buffer_store_dword + +; EG: VTX_READ_8 +; EG: BFE_INT +define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) #0 { + %a = load i1, i1 addrspace(1)* %in + %ext = sext i1 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i1_to_v1i32: +define void @global_zextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(1)* %in + %ext = zext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i1_to_v1i32: +define void @global_sextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(1)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(1)* %in + %ext = sext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i1_to_v2i32: +define void @global_zextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(1)* %in + %ext = zext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i1_to_v2i32: +define void @global_sextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(1)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(1)* %in + %ext = sext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v3i1_to_v3i32: +define void @global_zextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(1)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(1)* %in + %ext = zext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v3i1_to_v3i32: +define void @global_sextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(1)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(1)* %in + %ext = sext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i1_to_v4i32: +define void @global_zextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(1)* %in + %ext = zext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i1_to_v4i32: +define void @global_sextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(1)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(1)* %in + %ext = sext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i1_to_v8i32: +define void @global_zextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(1)* %in + %ext = zext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i1_to_v8i32: +define void @global_sextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(1)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(1)* %in + %ext = sext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i1_to_v16i32: +define void @global_zextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(1)* %in + %ext = zext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i1_to_v16i32: +define void @global_sextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(1)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(1)* %in + %ext = sext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i1_to_v32i32: +define void @global_zextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(1)* %in + %ext = zext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i1_to_v32i32: +define void @global_sextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(1)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(1)* %in + %ext = sext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v64i1_to_v64i32: +define void @global_zextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(1)* %in + %ext = zext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v64i1_to_v64i32: +define void @global_sextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(1)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(1)* %in + %ext = sext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i1_to_i64: +; GCN-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]], +; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}} +; GCN-DAG: v_and_b32_e32 {{v[0-9]+}}, 1, [[LOAD]]{{$}} +; GCN: buffer_store_dwordx2 +define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) #0 { + %a = load i1, i1 addrspace(1)* %in + %ext = zext i1 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i1_to_i64: +; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]], +; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}} +; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]] +; GCN: buffer_store_dwordx2 +define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) #0 { + %a = load i1, i1 addrspace(1)* %in + %ext = sext i1 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i1_to_v1i64: +define void @global_zextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(1)* %in + %ext = zext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i1_to_v1i64: +define void @global_sextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(1)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(1)* %in + %ext = sext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i1_to_v2i64: +define void @global_zextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(1)* %in + %ext = zext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i1_to_v2i64: +define void @global_sextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(1)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(1)* %in + %ext = sext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v3i1_to_v3i64: +define void @global_zextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(1)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(1)* %in + %ext = zext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v3i1_to_v3i64: +define void @global_sextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(1)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(1)* %in + %ext = sext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i1_to_v4i64: +define void @global_zextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(1)* %in + %ext = zext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i1_to_v4i64: +define void @global_sextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(1)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(1)* %in + %ext = sext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i1_to_v8i64: +define void @global_zextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(1)* %in + %ext = zext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i1_to_v8i64: +define void @global_sextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(1)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(1)* %in + %ext = sext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i1_to_v16i64: +define void @global_zextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(1)* %in + %ext = zext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i1_to_v16i64: +define void @global_sextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(1)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(1)* %in + %ext = sext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i1_to_v32i64: +define void @global_zextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(1)* %in + %ext = zext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i1_to_v32i64: +define void @global_sextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(1)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(1)* %in + %ext = sext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v64i1_to_v64i64: +define void @global_zextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(1)* %in + %ext = zext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v64i1_to_v64i64: +define void @global_sextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(1)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(1)* %in + %ext = sext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-i16.ll b/test/CodeGen/AMDGPU/load-global-i16.ll new file mode 100644 index 000000000000..11e6b10c38ff --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-i16.ll @@ -0,0 +1,476 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FIXME: r600 is broken because the bigger testcases spill and it's not implemented + +; FUNC-LABEL: {{^}}global_load_i16: +; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} +; GCN-HSA: flat_load_ushort + +; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @global_load_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { +entry: + %ld = load i16, i16 addrspace(1)* %in + store i16 %ld, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2i16: +; GCN-NOHSA: buffer_load_dword v +; GCN-HSA: flat_load_dword v + +; EG: VTX_READ_32 +define void @global_load_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { +entry: + %ld = load <2 x i16>, <2 x i16> addrspace(1)* %in + store <2 x i16> %ld, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3i16: +; GCN-NOHSA: buffer_load_dwordx2 v +; GCN-HSA: flat_load_dwordx2 v + +; EG-DAG: VTX_READ_32 +; EG-DAG: VTX_READ_16 +define void @global_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(1)* %in + store <3 x i16> %ld, <3 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4i16: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 + +; EG: VTX_READ_64 +define void @global_load_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { +entry: + %ld = load <4 x i16>, <4 x i16> addrspace(1)* %in + store <4 x i16> %ld, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8i16: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +define void @global_load_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) { +entry: + %ld = load <8 x i16>, <8 x i16> addrspace(1)* %in + store <8 x i16> %ld, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16i16: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v16i16(<16 x i16> addrspace(1)* %out, <16 x i16> addrspace(1)* %in) { +entry: + %ld = load <16 x i16>, <16 x i16> addrspace(1)* %in + store <16 x i16> %ld, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i16_to_i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-NOHSA: buffer_store_dword + +; GCN-HSA: flat_load_ushort +; GCN-HSA: flat_store_dword + +; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} +define void @global_zextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { + %a = load i16, i16 addrspace(1)* %in + %ext = zext i16 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i16_to_i32: +; GCN-NOHSA: buffer_load_sshort +; GCN-NOHSA: buffer_store_dword + +; GCN-HSA: flat_load_sshort +; GCN-HSA: flat_store_dword + +; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal +; EG: 16 +define void @global_sextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { + %a = load i16, i16 addrspace(1)* %in + %ext = sext i16 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i16_to_v1i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-HSA: flat_load_ushort +define void @global_zextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(1)* %in + %ext = zext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i16_to_v1i32: +; GCN-NOHSA: buffer_load_sshort +; GCN-HSA: flat_load_sshort +define void @global_sextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(1)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(1)* %in + %ext = sext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i16_to_v2i32: +; GCN-NOHSA: buffer_load_dword +; GCN-HSA: flat_load_dword +define void @global_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(1)* %in + %ext = zext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i16_to_v2i32: +; GCN-NOHSA: buffer_load_dword + +; GCN-HSA: flat_load_dword + +; EG-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: 16 +; EG-DAG: 16 +define void @global_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(1)* %in + %ext = sext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_global_zextload_v3i16_to_v3i32: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 +define void @global_global_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(1)* %in + %ext = zext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_global_sextload_v3i16_to_v3i32: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 +define void @global_global_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(1)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(1)* %in + %ext = sext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_global_zextload_v4i16_to_v4i32: +; GCN-NOHSA: buffer_load_dwordx2 + +; GCN-HSA: flat_load_dwordx2 + +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +; EG: VTX_READ_16 +define void @global_global_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(1)* %in + %ext = zext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i16_to_v4i32: +; GCN-NOHSA: buffer_load_dwordx2 + +; GCN-HSA: flat_load_dwordx2 + +; EG-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; EG-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal +; EG-DAG: 16 +; EG-DAG: 16 +; EG-DAG: 16 +; EG-DAG: 16 +define void @global_sextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(1)* %in + %ext = sext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i16_to_v8i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_zextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(1)* %in + %ext = zext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i16_to_v8i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_sextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(1)* %in + %ext = sext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i16_to_v16i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_zextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(1)* %in + %ext = zext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i16_to_v16i32: +define void @global_sextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(1)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(1)* %in + %ext = sext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i16_to_v32i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_zextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(1)* %in + %ext = zext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i16_to_v32i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_sextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(1)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(1)* %in + %ext = sext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v64i16_to_v64i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +define void @global_zextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(1)* %in + %ext = zext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v64i16_to_v64i32: +define void @global_sextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(1)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(1)* %in + %ext = sext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i16_to_i64: +; GCN-NOHSA-DAG: buffer_load_ushort v[[LO:[0-9]+]], +; GCN-HSA-DAG: flat_load_ushort v[[LO:[0-9]+]], +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @global_zextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { + %a = load i16, i16 addrspace(1)* %in + %ext = zext i16 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i16_to_i64: +; GCN-NOHSA-DAG: buffer_load_sshort v[[LO:[0-9]+]], +; GCN-HSA-DAG: flat_load_sshort v[[LO:[0-9]+]], +; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @global_sextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(1)* %in) #0 { + %a = load i16, i16 addrspace(1)* %in + %ext = sext i16 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i16_to_v1i64: +define void @global_zextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(1)* %in + %ext = zext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i16_to_v1i64: +define void @global_sextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(1)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(1)* %in + %ext = sext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i16_to_v2i64: +define void @global_zextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(1)* %in + %ext = zext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i16_to_v2i64: +define void @global_sextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(1)* %in + %ext = sext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i16_to_v4i64: +define void @global_zextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(1)* %in + %ext = zext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i16_to_v4i64: +define void @global_sextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(1)* %in + %ext = sext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i16_to_v8i64: +define void @global_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(1)* %in + %ext = zext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i16_to_v8i64: +define void @global_sextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(1)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(1)* %in + %ext = sext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i16_to_v16i64: +define void @global_zextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(1)* %in + %ext = zext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i16_to_v16i64: +define void @global_sextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(1)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(1)* %in + %ext = sext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i16_to_v32i64: +define void @global_zextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(1)* %in + %ext = zext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i16_to_v32i64: +define void @global_sextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(1)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(1)* %in + %ext = sext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; ; XFUNC-LABEL: {{^}}global_zextload_v64i16_to_v64i64: +; define void @global_zextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(1)* %in +; %ext = zext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; ; XFUNC-LABEL: {{^}}global_sextload_v64i16_to_v64i64: +; define void @global_sextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(1)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(1)* %in +; %ext = sext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-i32.ll b/test/CodeGen/AMDGPU/load-global-i32.ll new file mode 100644 index 000000000000..5e1171a69be5 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-i32.ll @@ -0,0 +1,521 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}global_load_i32: +; GCN-NOHSA: buffer_load_dword v{{[0-9]+}} +; GCN-HSA: flat_load_dword + +; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @global_load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { +entry: + %ld = load i32, i32 addrspace(1)* %in + store i32 %ld, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2i32: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 + +; EG: VTX_READ_64 +define void @global_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { +entry: + %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in + store <2 x i32> %ld, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +define void @global_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x i32>, <3 x i32> addrspace(1)* %in + store <3 x i32> %ld, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +define void @global_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { +entry: + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + store <4 x i32> %ld, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { +entry: + %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in + store <8 x i32> %ld, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16i32: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { +entry: + %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in + store <16 x i32> %ld, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i32_to_i64: +; GCN-NOHSA-DAG: buffer_load_dword v[[LO:[0-9]+]], +; GCN-HSA-DAG: flat_load_dword v[[LO:[0-9]+]], +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] + +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +define void @global_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %ld = load i32, i32 addrspace(1)* %in + %ext = zext i32 %ld to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i32_to_i64: +; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] +; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] +; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} + + +; EG: MEM_RAT +; EG: VTX_READ_32 +; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. +; EG: 31 +define void @global_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %ld = load i32, i32 addrspace(1)* %in + %ext = sext i32 %ld to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i32_to_v1i64: +; GCN-NOHSA: buffer_load_dword +; GCN-NOHSA: buffer_store_dwordx2 + +; GCN-HSA: flat_load_dword +; GCN-HSA: flat_store_dwordx2 +define void @global_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in + %ext = zext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i32_to_v1i64: +; GCN-NOHSA: buffer_load_dword v[[LO:[0-9]+]] +; GCN-HSA: flat_load_dword v[[LO:[0-9]+]] +; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @global_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(1)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(1)* %in + %ext = sext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i32_to_v2i64: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_load_dwordx2 +; GCN-HSA: flat_store_dwordx4 +define void @global_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in + %ext = zext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i32_to_v2i64: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in + %ext = sext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i32_to_v4i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +define void @global_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %ext = zext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i32_to_v4i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %ext = sext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i32_to_v8i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-SA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in + %ext = zext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i32_to_v8i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(1)* %in + %ext = sext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i32_to_v16i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in + %ext = sext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i32_to_v16i64 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +define void @global_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(1)* %in + %ext = zext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i32_to_v32i64: + +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 +; GCN-DAG: v_ashrrev_i32 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 +; GCN-NOHSA: buffer_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 +; GCN-HSA: flat_store_dwordx4 + +define void @global_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in + %ext = sext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i32_to_v32i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 +; GCN-NOHSA-DAG: buffer_store_dwordx4 + + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 + +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +; GCN-HSA-DAG: flat_store_dwordx4 +define void @global_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(1)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(1)* %in + %ext = zext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-i64.ll b/test/CodeGen/AMDGPU/load-global-i64.ll new file mode 100644 index 000000000000..305b954c78f9 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-i64.ll @@ -0,0 +1,122 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s + +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}global_load_i64: +; GCN-NOHSA: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-NOHSA: buffer_store_dwordx2 [[VAL]] + +; GCN-HSA: flat_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-HSA: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, [[VAL]] + +; EG: VTX_READ_64 +define void @global_load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #0 { + %ld = load i64, i64 addrspace(1)* %in + store i64 %ld, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +define void @global_load_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) #0 { +entry: + %ld = load <2 x i64>, <2 x i64> addrspace(1)* %in + store <2 x i64> %ld, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x i64>, <3 x i64> addrspace(1)* %in + store <3 x i64> %ld, <3 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 { +entry: + %ld = load <4 x i64>, <4 x i64> addrspace(1)* %in + store <4 x i64> %ld, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v8i64(<8 x i64> addrspace(1)* %out, <8 x i64> addrspace(1)* %in) #0 { +entry: + %ld = load <8 x i64>, <8 x i64> addrspace(1)* %in + store <8 x i64> %ld, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16i64: +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +; EG: VTX_READ_128 +define void @global_load_v16i64(<16 x i64> addrspace(1)* %out, <16 x i64> addrspace(1)* %in) #0 { +entry: + %ld = load <16 x i64>, <16 x i64> addrspace(1)* %in + store <16 x i64> %ld, <16 x i64> addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-global-i8.ll b/test/CodeGen/AMDGPU/load-global-i8.ll new file mode 100644 index 000000000000..b697967f1a23 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-global-i8.ll @@ -0,0 +1,564 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}global_load_i8: +; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}} +; GCN-HSA: flat_load_ubyte + +; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +define void @global_load_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { +entry: + %ld = load i8, i8 addrspace(1)* %in + store i8 %ld, i8 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v2i8: +; GCN-NOHSA: buffer_load_ushort v +; GCN-HSA: flat_load_ushort v + +; EG: VTX_READ_16 +define void @global_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <2 x i8>, <2 x i8> addrspace(1)* %in + store <2 x i8> %ld, <2 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v3i8: +; GCN-NOHSA: buffer_load_dword v +; GCN-HSA: flat_load_dword v + +; EG-DAG: VTX_READ_32 +define void @global_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(1)* %in + store <3 x i8> %ld, <3 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v4i8: +; GCN-NOHSA: buffer_load_dword v +; GCN-HSA: flat_load_dword v + +; EG: VTX_READ_32 +define void @global_load_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <4 x i8>, <4 x i8> addrspace(1)* %in + store <4 x i8> %ld, <4 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v8i8: +; GCN-NOHSA: buffer_load_dwordx2 +; GCN-HSA: flat_load_dwordx2 + +; EG: VTX_READ_64 +define void @global_load_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <8 x i8>, <8 x i8> addrspace(1)* %in + store <8 x i8> %ld, <8 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_load_v16i8: +; GCN-NOHSA: buffer_load_dwordx4 + +; GCN-HSA: flat_load_dwordx4 + +; EG: VTX_READ_128 +define void @global_load_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <16 x i8>, <16 x i8> addrspace(1)* %in + store <16 x i8> %ld, <16 x i8> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i8_to_i32: +; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, +; GCN-HSA: flat_load_ubyte + +; EG: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} +define void @global_zextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %a = load i8, i8 addrspace(1)* %in + %ext = zext i8 %a to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i8_to_i32: +; GCN-NOHSA: buffer_load_sbyte +; GCN-HSA: flat_load_sbyte + +; EG: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] +; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal +; EG: 8 +define void @global_sextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %ld = load i8, i8 addrspace(1)* %in + %ext = sext i8 %ld to i32 + store i32 %ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i8_to_v1i32: +define void @global_zextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = zext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i8_to_v1i32: +define void @global_sextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = sext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i8_to_v2i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-HSA: flat_load_ushort + +; EG: VTX_READ_8 +; EG: VTX_READ_8 +define void @global_zextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = zext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i8_to_v2i32: +; GCN-NOHSA: buffer_load_ushort +; GCN-HSA: flat_load_ushort + +; EG-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: 8 +; EG-DAG: 8 +define void @global_sextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = sext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v3i8_to_v3i32: +; GCN-NOHSA: buffer_load_dword v +; GCN-HSA: flat_load_dword v + +; GCN-DAG: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 8, 8 +; GCN-DAG: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 16, 8 +; GCN-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff, +define void @global_zextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(1)* %in + %ext = zext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v3i8_to_v3i32: +; GCN-NOHSA: buffer_load_dword v +; GCN-HSA: flat_load_dword v + +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 8, 8 +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 16, 8 +define void @global_sextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(1)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(1)* %in + %ext = sext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i8_to_v4i32: +; GCN-NOHSA: buffer_load_dword +; GCN-HSA: flat_load_dword + +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +; EG: VTX_READ_8 +define void @global_zextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = zext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i8_to_v4i32: +; GCN-NOHSA: buffer_load_dword +; GCN-HSA: flat_load_dword + +; EG-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] +; EG-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] +; EG-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] +; EG-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal +; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal +; EG-DAG: 8 +; EG-DAG: 8 +; EG-DAG: 8 +; EG-DAG: 8 +define void @global_sextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = sext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i8_to_v8i32: +define void @global_zextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = zext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i8_to_v8i32: +define void @global_sextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = sext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i8_to_v16i32: +define void @global_zextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = zext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i8_to_v16i32: +define void @global_sextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = sext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i8_to_v32i32: +define void @global_zextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = zext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i8_to_v32i32: +define void @global_sextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = sext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i32: +define void @global_zextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(1)* %in + %ext = zext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i32: +define void @global_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(1)* %in + %ext = sext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_i8_to_i64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]], +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] + +; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]], +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] +define void @global_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %a = load i8, i8 addrspace(1)* %in + %ext = zext i8 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i8_to_i64: +; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]], +; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]], +; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @global_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %a = load i8, i8 addrspace(1)* %in + %ext = sext i8 %a to i64 + store i64 %ext, i64 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i8_to_v1i64: +define void @global_zextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = zext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i8_to_v1i64: +define void @global_sextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = sext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i8_to_v2i64: +define void @global_zextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = zext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i8_to_v2i64: +define void @global_sextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = sext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i8_to_v4i64: +define void @global_zextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = zext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i8_to_v4i64: +define void @global_sextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = sext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i8_to_v8i64: +define void @global_zextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = zext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i8_to_v8i64: +define void @global_sextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = sext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i8_to_v16i64: +define void @global_zextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = zext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i8_to_v16i64: +define void @global_sextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = sext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i8_to_v32i64: +define void @global_zextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = zext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i8_to_v32i64: +define void @global_sextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = sext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(1)* %out + ret void +} + +; XFUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i64: +; define void @global_zextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in +; %ext = zext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i64: +; define void @global_sextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in +; %ext = sext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out +; ret void +; } + +; FUNC-LABEL: {{^}}global_zextload_i8_to_i16: +; GCN-NOHSA: buffer_load_ubyte v[[VAL:[0-9]+]], +; GCN-NOHSA: buffer_store_short v[[VAL]] + +; GCN-HSA: flat_load_ubyte v[[VAL:[0-9]+]], +; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] +define void @global_zextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %a = load i8, i8 addrspace(1)* %in + %ext = zext i8 %a to i16 + store i16 %ext, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_i8_to_i16: +; GCN-NOHSA: buffer_load_sbyte v[[VAL:[0-9]+]], +; GCN-HSA: flat_load_sbyte v[[VAL:[0-9]+]], + +; GCN-NOHSA: buffer_store_short v[[VAL]] +; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] +define void @global_sextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(1)* %in) #0 { + %a = load i8, i8 addrspace(1)* %in + %ext = sext i8 %a to i16 + store i16 %ext, i16 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v1i8_to_v1i16: +define void @global_zextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = zext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v1i8_to_v1i16: +define void @global_sextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(1)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(1)* %in + %ext = sext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v2i8_to_v2i16: +define void @global_zextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = zext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v2i8_to_v2i16: +define void @global_sextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(1)* %in + %ext = sext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v4i8_to_v4i16: +define void @global_zextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = zext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v4i8_to_v4i16: +define void @global_sextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(1)* %in + %ext = sext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v8i8_to_v8i16: +define void @global_zextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = zext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v8i8_to_v8i16: +define void @global_sextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(1)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(1)* %in + %ext = sext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v16i8_to_v16i16: +define void @global_zextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = zext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v16i8_to_v16i16: +define void @global_sextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(1)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(1)* %in + %ext = sext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_zextload_v32i8_to_v32i16: +define void @global_zextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = zext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}global_sextload_v32i8_to_v32i16: +define void @global_sextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(1)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(1)* %in + %ext = sext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(1)* %out + ret void +} + +; XFUNC-LABEL: {{^}}global_zextload_v64i8_to_v64i16: +; define void @global_zextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in +; %ext = zext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}global_sextload_v64i8_to_v64i16: +; define void @global_sextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(1)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(1)* %in +; %ext = sext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-i1.ll b/test/CodeGen/AMDGPU/load-i1.ll deleted file mode 100644 index 0ca49fde3e7b..000000000000 --- a/test/CodeGen/AMDGPU/load-i1.ll +++ /dev/null @@ -1,149 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - -; FUNC-LABEL: {{^}}global_copy_i1_to_i1: -; SI: buffer_load_ubyte -; SI: v_and_b32_e32 v{{[0-9]+}}, 1 -; SI: buffer_store_byte -; SI: s_endpgm - -; EG: VTX_READ_8 -; EG: AND_INT -define void @global_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %load = load i1, i1 addrspace(1)* %in - store i1 %load, i1 addrspace(1)* %out, align 1 - ret void -} - -; FUNC-LABEL: {{^}}local_copy_i1_to_i1: -; SI: ds_read_u8 -; SI: v_and_b32_e32 v{{[0-9]+}}, 1 -; SI: ds_write_b8 -; SI: s_endpgm - -; EG: LDS_UBYTE_READ_RET -; EG: AND_INT -; EG: LDS_BYTE_WRITE -define void @local_copy_i1_to_i1(i1 addrspace(3)* %out, i1 addrspace(3)* %in) nounwind { - %load = load i1, i1 addrspace(3)* %in - store i1 %load, i1 addrspace(3)* %out, align 1 - ret void -} - -; FUNC-LABEL: {{^}}constant_copy_i1_to_i1: -; SI: buffer_load_ubyte -; SI: v_and_b32_e32 v{{[0-9]+}}, 1 -; SI: buffer_store_byte -; SI: s_endpgm - -; EG: VTX_READ_8 -; EG: AND_INT -define void @constant_copy_i1_to_i1(i1 addrspace(1)* %out, i1 addrspace(2)* %in) nounwind { - %load = load i1, i1 addrspace(2)* %in - store i1 %load, i1 addrspace(1)* %out, align 1 - ret void -} - -; FUNC-LABEL: {{^}}global_sextload_i1_to_i32: -; SI: buffer_load_ubyte -; SI: v_bfe_i32 -; SI: buffer_store_dword -; SI: s_endpgm - -; EG: VTX_READ_8 -; EG: BFE_INT -define void @global_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %load = load i1, i1 addrspace(1)* %in - %ext = sext i1 %load to i32 - store i32 %ext, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}global_zextload_i1_to_i32: -; SI: buffer_load_ubyte -; SI: buffer_store_dword -; SI: s_endpgm - -define void @global_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %load = load i1, i1 addrspace(1)* %in - %ext = zext i1 %load to i32 - store i32 %ext, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}global_sextload_i1_to_i64: -; SI: buffer_load_ubyte -; SI: v_bfe_i32 -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @global_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %load = load i1, i1 addrspace(1)* %in - %ext = sext i1 %load to i64 - store i64 %ext, i64 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}global_zextload_i1_to_i64: -; SI: buffer_load_ubyte -; SI: v_mov_b32_e32 {{v[0-9]+}}, 0 -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @global_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { - %load = load i1, i1 addrspace(1)* %in - %ext = zext i1 %load to i64 - store i64 %ext, i64 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}i1_arg: -; SI: buffer_load_ubyte -; SI: v_and_b32_e32 -; SI: buffer_store_byte -; SI: s_endpgm -define void @i1_arg(i1 addrspace(1)* %out, i1 %x) nounwind { - store i1 %x, i1 addrspace(1)* %out, align 1 - ret void -} - -; FUNC-LABEL: {{^}}i1_arg_zext_i32: -; SI: buffer_load_ubyte -; SI: buffer_store_dword -; SI: s_endpgm -define void @i1_arg_zext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { - %ext = zext i1 %x to i32 - store i32 %ext, i32 addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}i1_arg_zext_i64: -; SI: buffer_load_ubyte -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @i1_arg_zext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { - %ext = zext i1 %x to i64 - store i64 %ext, i64 addrspace(1)* %out, align 8 - ret void -} - -; FUNC-LABEL: {{^}}i1_arg_sext_i32: -; SI: buffer_load_ubyte -; SI: buffer_store_dword -; SI: s_endpgm -define void @i1_arg_sext_i32(i32 addrspace(1)* %out, i1 %x) nounwind { - %ext = sext i1 %x to i32 - store i32 %ext, i32addrspace(1)* %out, align 4 - ret void -} - -; FUNC-LABEL: {{^}}i1_arg_sext_i64: -; SI: buffer_load_ubyte -; SI: v_bfe_i32 -; SI: v_ashrrev_i32 -; SI: buffer_store_dwordx2 -; SI: s_endpgm -define void @i1_arg_sext_i64(i64 addrspace(1)* %out, i1 %x) nounwind { - %ext = sext i1 %x to i64 - store i64 %ext, i64 addrspace(1)* %out, align 8 - ret void -} diff --git a/test/CodeGen/AMDGPU/load-input-fold.ll b/test/CodeGen/AMDGPU/load-input-fold.ll index 1daf0e6527b9..b1899a45bf56 100644 --- a/test/CodeGen/AMDGPU/load-input-fold.ll +++ b/test/CodeGen/AMDGPU/load-input-fold.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=cayman -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -88,14 +88,14 @@ main_body: %83 = insertelement <4 x float> %82, float %75, i32 1 %84 = insertelement <4 x float> %83, float %77, i32 2 %85 = insertelement <4 x float> %84, float 0.000000e+00, i32 3 - %86 = call float @llvm.AMDGPU.dp4(<4 x float> %81, <4 x float> %85) + %86 = call float @llvm.r600.dot4(<4 x float> %81, <4 x float> %85) %87 = insertelement <4 x float> undef, float %86, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %87, i32 2, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %87, i32 2, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly declare float @fabs(float) #2 @@ -104,14 +104,13 @@ declare float @fabs(float) #2 declare float @llvm.AMDGPU.rsq(float) #1 ; Function Attrs: readnone -declare float @llvm.AMDIL.clamp.(float, float, float) #1 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1 ; Function Attrs: nounwind readonly declare float @llvm.pow.f32(float, float) #3 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } attributes #2 = { readonly } attributes #3 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/load-local-f32.ll b/test/CodeGen/AMDGPU/load-local-f32.ll new file mode 100644 index 000000000000..77b5e3cf3aed --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-f32.ll @@ -0,0 +1,110 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}load_f32_local: +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; EG: LDS_READ_RET +define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) #0 { +entry: + %tmp0 = load float, float addrspace(3)* %in + store float %tmp0, float addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}load_v2f32_local: +; GCN: s_mov_b32 m0 +; GCN: ds_read_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) #0 { +entry: + %tmp0 = load <2 x float>, <2 x float> addrspace(3)* %in + store <2 x float> %tmp0, <2 x float> addrspace(1)* %out + ret void +} + +; FIXME: should this do a read2_b64? +; FUNC-LABEL: {{^}}local_load_v3f32: +; GCN-DAG: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8 +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}} +; GCN: s_waitcnt +; GCN-DAG: ds_write_b64 +; GCN-DAG: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:8{{$}} + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v3f32(<3 x float> addrspace(3)* %out, <3 x float> addrspace(3)* %in) #0 { +entry: + %tmp0 = load <3 x float>, <3 x float> addrspace(3)* %in + store <3 x float> %tmp0, <3 x float> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4f32: +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v4f32(<4 x float> addrspace(3)* %out, <4 x float> addrspace(3)* %in) #0 { +entry: + %tmp0 = load <4 x float>, <4 x float> addrspace(3)* %in + store <4 x float> %tmp0, <4 x float> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8f32: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v8f32(<8 x float> addrspace(3)* %out, <8 x float> addrspace(3)* %in) #0 { +entry: + %tmp0 = load <8 x float>, <8 x float> addrspace(3)* %in + store <8 x float> %tmp0, <8 x float> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16f32: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v16f32(<16 x float> addrspace(3)* %out, <16 x float> addrspace(3)* %in) #0 { +entry: + %tmp0 = load <16 x float>, <16 x float> addrspace(3)* %in + store <16 x float> %tmp0, <16 x float> addrspace(3)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-f64.ll b/test/CodeGen/AMDGPU/load-local-f64.ll new file mode 100644 index 000000000000..27d39b7e9d7d --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-f64.ll @@ -0,0 +1,154 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}local_load_f64: +; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} +; GCN: ds_write_b64 v{{[0-9]+}}, [[VAL]] + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_f64(double addrspace(3)* %out, double addrspace(3)* %in) #0 { + %ld = load double, double addrspace(3)* %in + store double %ld, double addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2f64: +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v2f64(<2 x double> addrspace(3)* %out, <2 x double> addrspace(3)* %in) #0 { +entry: + %ld = load <2 x double>, <2 x double> addrspace(3)* %in + store <2 x double> %ld, <2 x double> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3f64: +; GCN-DAG: ds_read2_b64 +; GCN-DAG: ds_read_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v3f64(<3 x double> addrspace(3)* %out, <3 x double> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x double>, <3 x double> addrspace(3)* %in + store <3 x double> %ld, <3 x double> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4f64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v4f64(<4 x double> addrspace(3)* %out, <4 x double> addrspace(3)* %in) #0 { +entry: + %ld = load <4 x double>, <4 x double> addrspace(3)* %in + store <4 x double> %ld, <4 x double> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8f64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v8f64(<8 x double> addrspace(3)* %out, <8 x double> addrspace(3)* %in) #0 { +entry: + %ld = load <8 x double>, <8 x double> addrspace(3)* %in + store <8 x double> %ld, <8 x double> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16f64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v16f64(<16 x double> addrspace(3)* %out, <16 x double> addrspace(3)* %in) #0 { +entry: + %ld = load <16 x double>, <16 x double> addrspace(3)* %in + store <16 x double> %ld, <16 x double> addrspace(3)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-i1.ll b/test/CodeGen/AMDGPU/load-local-i1.ll new file mode 100644 index 000000000000..2eed9917b5e5 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-i1.ll @@ -0,0 +1,371 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}local_load_i1: +; GCN: ds_read_u8 +; GCN: v_and_b32_e32 v{{[0-9]+}}, 1 +; GCN: ds_write_b8 + +; EG: LDS_UBYTE_READ_RET +; EG: AND_INT +; EG: LDS_BYTE_WRITE +define void @local_load_i1(i1 addrspace(3)* %out, i1 addrspace(3)* %in) #0 { + %load = load i1, i1 addrspace(3)* %in + store i1 %load, i1 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2i1: +define void @local_load_v2i1(<2 x i1> addrspace(3)* %out, <2 x i1> addrspace(3)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(3)* %in + store <2 x i1> %load, <2 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3i1: +define void @local_load_v3i1(<3 x i1> addrspace(3)* %out, <3 x i1> addrspace(3)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(3)* %in + store <3 x i1> %load, <3 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4i1: +define void @local_load_v4i1(<4 x i1> addrspace(3)* %out, <4 x i1> addrspace(3)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(3)* %in + store <4 x i1> %load, <4 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8i1: +define void @local_load_v8i1(<8 x i1> addrspace(3)* %out, <8 x i1> addrspace(3)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(3)* %in + store <8 x i1> %load, <8 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16i1: +define void @local_load_v16i1(<16 x i1> addrspace(3)* %out, <16 x i1> addrspace(3)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(3)* %in + store <16 x i1> %load, <16 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v32i1: +define void @local_load_v32i1(<32 x i1> addrspace(3)* %out, <32 x i1> addrspace(3)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(3)* %in + store <32 x i1> %load, <32 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v64i1: +define void @local_load_v64i1(<64 x i1> addrspace(3)* %out, <64 x i1> addrspace(3)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(3)* %in + store <64 x i1> %load, <64 x i1> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i1_to_i32: +; GCN: ds_read_u8 +; GCN: ds_write_b32 +define void @local_zextload_i1_to_i32(i32 addrspace(3)* %out, i1 addrspace(3)* %in) #0 { + %a = load i1, i1 addrspace(3)* %in + %ext = zext i1 %a to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i1_to_i32: +; GCN: ds_read_u8 +; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}} +; GCN: ds_write_b32 + +; EG: LDS_UBYTE_READ_RET +; EG: BFE_INT +define void @local_sextload_i1_to_i32(i32 addrspace(3)* %out, i1 addrspace(3)* %in) #0 { + %a = load i1, i1 addrspace(3)* %in + %ext = sext i1 %a to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i1_to_v1i32: +define void @local_zextload_v1i1_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i1> addrspace(3)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(3)* %in + %ext = zext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i1_to_v1i32: +define void @local_sextload_v1i1_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i1> addrspace(3)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(3)* %in + %ext = sext <1 x i1> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i1_to_v2i32: +define void @local_zextload_v2i1_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i1> addrspace(3)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(3)* %in + %ext = zext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i1_to_v2i32: +define void @local_sextload_v2i1_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i1> addrspace(3)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(3)* %in + %ext = sext <2 x i1> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v3i1_to_v3i32: +define void @local_zextload_v3i1_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i1> addrspace(3)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(3)* %in + %ext = zext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v3i1_to_v3i32: +define void @local_sextload_v3i1_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i1> addrspace(3)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(3)* %in + %ext = sext <3 x i1> %load to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i1_to_v4i32: +define void @local_zextload_v4i1_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i1> addrspace(3)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(3)* %in + %ext = zext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i1_to_v4i32: +define void @local_sextload_v4i1_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i1> addrspace(3)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(3)* %in + %ext = sext <4 x i1> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i1_to_v8i32: +define void @local_zextload_v8i1_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i1> addrspace(3)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(3)* %in + %ext = zext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i1_to_v8i32: +define void @local_sextload_v8i1_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i1> addrspace(3)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(3)* %in + %ext = sext <8 x i1> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i1_to_v16i32: +define void @local_zextload_v16i1_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i1> addrspace(3)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(3)* %in + %ext = zext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i1_to_v16i32: +define void @local_sextload_v16i1_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i1> addrspace(3)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(3)* %in + %ext = sext <16 x i1> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i1_to_v32i32: +define void @local_zextload_v32i1_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i1> addrspace(3)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(3)* %in + %ext = zext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i1_to_v32i32: +define void @local_sextload_v32i1_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i1> addrspace(3)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(3)* %in + %ext = sext <32 x i1> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v64i1_to_v64i32: +define void @local_zextload_v64i1_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i1> addrspace(3)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(3)* %in + %ext = zext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v64i1_to_v64i32: +define void @local_sextload_v64i1_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i1> addrspace(3)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(3)* %in + %ext = sext <64 x i1> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i1_to_i64: +; GCN-DAG: ds_read_u8 [[LOAD:v[0-9]+]], +; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}} +; GCN: ds_write_b64 +define void @local_zextload_i1_to_i64(i64 addrspace(3)* %out, i1 addrspace(3)* %in) #0 { + %a = load i1, i1 addrspace(3)* %in + %ext = zext i1 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i1_to_i64: +; GCN: ds_read_u8 [[LOAD:v[0-9]+]], +; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}} +; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]] +; GCN: ds_write_b64 +define void @local_sextload_i1_to_i64(i64 addrspace(3)* %out, i1 addrspace(3)* %in) #0 { + %a = load i1, i1 addrspace(3)* %in + %ext = sext i1 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i1_to_v1i64: +define void @local_zextload_v1i1_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i1> addrspace(3)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(3)* %in + %ext = zext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i1_to_v1i64: +define void @local_sextload_v1i1_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i1> addrspace(3)* %in) #0 { + %load = load <1 x i1>, <1 x i1> addrspace(3)* %in + %ext = sext <1 x i1> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i1_to_v2i64: +define void @local_zextload_v2i1_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i1> addrspace(3)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(3)* %in + %ext = zext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i1_to_v2i64: +define void @local_sextload_v2i1_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i1> addrspace(3)* %in) #0 { + %load = load <2 x i1>, <2 x i1> addrspace(3)* %in + %ext = sext <2 x i1> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v3i1_to_v3i64: +define void @local_zextload_v3i1_to_v3i64(<3 x i64> addrspace(3)* %out, <3 x i1> addrspace(3)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(3)* %in + %ext = zext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v3i1_to_v3i64: +define void @local_sextload_v3i1_to_v3i64(<3 x i64> addrspace(3)* %out, <3 x i1> addrspace(3)* %in) #0 { + %load = load <3 x i1>, <3 x i1> addrspace(3)* %in + %ext = sext <3 x i1> %load to <3 x i64> + store <3 x i64> %ext, <3 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i1_to_v4i64: +define void @local_zextload_v4i1_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i1> addrspace(3)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(3)* %in + %ext = zext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i1_to_v4i64: +define void @local_sextload_v4i1_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i1> addrspace(3)* %in) #0 { + %load = load <4 x i1>, <4 x i1> addrspace(3)* %in + %ext = sext <4 x i1> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i1_to_v8i64: +define void @local_zextload_v8i1_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i1> addrspace(3)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(3)* %in + %ext = zext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i1_to_v8i64: +define void @local_sextload_v8i1_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i1> addrspace(3)* %in) #0 { + %load = load <8 x i1>, <8 x i1> addrspace(3)* %in + %ext = sext <8 x i1> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i1_to_v16i64: +define void @local_zextload_v16i1_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i1> addrspace(3)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(3)* %in + %ext = zext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i1_to_v16i64: +define void @local_sextload_v16i1_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i1> addrspace(3)* %in) #0 { + %load = load <16 x i1>, <16 x i1> addrspace(3)* %in + %ext = sext <16 x i1> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i1_to_v32i64: +define void @local_zextload_v32i1_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i1> addrspace(3)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(3)* %in + %ext = zext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i1_to_v32i64: +define void @local_sextload_v32i1_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i1> addrspace(3)* %in) #0 { + %load = load <32 x i1>, <32 x i1> addrspace(3)* %in + %ext = sext <32 x i1> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v64i1_to_v64i64: +define void @local_zextload_v64i1_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i1> addrspace(3)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(3)* %in + %ext = zext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v64i1_to_v64i64: +define void @local_sextload_v64i1_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i1> addrspace(3)* %in) #0 { + %load = load <64 x i1>, <64 x i1> addrspace(3)* %in + %ext = sext <64 x i1> %load to <64 x i64> + store <64 x i64> %ext, <64 x i64> addrspace(3)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-i16.ll b/test/CodeGen/AMDGPU/load-local-i16.ll new file mode 100644 index 000000000000..d3c0af469dd2 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-i16.ll @@ -0,0 +1,454 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}local_load_i16: +; GCN: ds_read_u16 v{{[0-9]+}} + +; EG: LDS_USHORT_READ_RET +define void @local_load_i16(i16 addrspace(3)* %out, i16 addrspace(3)* %in) { +entry: + %ld = load i16, i16 addrspace(3)* %in + store i16 %ld, i16 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2i16: +; GCN: ds_read_b32 + +; EG: LDS_READ_RET +define void @local_load_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> addrspace(3)* %in) { +entry: + %ld = load <2 x i16>, <2 x i16> addrspace(3)* %in + store <2 x i16> %ld, <2 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3i16: +; GCN: ds_read_b64 +; GCN-DAG: ds_write_b32 +; GCN-DAG: ds_write_b16 + +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: LDS_READ_RET +define void @local_load_v3i16(<3 x i16> addrspace(3)* %out, <3 x i16> addrspace(3)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(3)* %in + store <3 x i16> %ld, <3 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4i16: +; GCN: ds_read_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v4i16(<4 x i16> addrspace(3)* %out, <4 x i16> addrspace(3)* %in) { +entry: + %ld = load <4 x i16>, <4 x i16> addrspace(3)* %in + store <4 x i16> %ld, <4 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8i16: +; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v8i16(<8 x i16> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) { +entry: + %ld = load <8 x i16>, <8 x i16> addrspace(3)* %in + store <8 x i16> %ld, <8 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16i16: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} + + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v16i16(<16 x i16> addrspace(3)* %out, <16 x i16> addrspace(3)* %in) { +entry: + %ld = load <16 x i16>, <16 x i16> addrspace(3)* %in + store <16 x i16> %ld, <16 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i16_to_i32: +; GCN: ds_read_u16 +; GCN: ds_write_b32 + +; EG: LDS_USHORT_READ_RET +define void @local_zextload_i16_to_i32(i32 addrspace(3)* %out, i16 addrspace(3)* %in) #0 { + %a = load i16, i16 addrspace(3)* %in + %ext = zext i16 %a to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i16_to_i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_i16 + +; EG: LDS_USHORT_READ_RET +; EG: BFE_INT +define void @local_sextload_i16_to_i32(i32 addrspace(3)* %out, i16 addrspace(3)* %in) #0 { + %a = load i16, i16 addrspace(3)* %in + %ext = sext i16 %a to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i16_to_v1i32: +; GCN: ds_read_u16 +define void @local_zextload_v1i16_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i16> addrspace(3)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(3)* %in + %ext = zext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i16_to_v1i32: +; GCN: ds_read_i16 +define void @local_sextload_v1i16_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i16> addrspace(3)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(3)* %in + %ext = sext <1 x i16> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i16_to_v2i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; EG: LDS_USHORT_READ_RET +; EG: LDS_USHORT_READ_RET +define void @local_zextload_v2i16_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i16> addrspace(3)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(3)* %in + %ext = zext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i16_to_v2i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +define void @local_sextload_v2i16_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i16> addrspace(3)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(3)* %in + %ext = sext <2 x i16> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_local_zextload_v3i16_to_v3i32: +; GCN: ds_read_b64 +; GCN-DAG: ds_write_b32 +; GCN-DAG: ds_write_b64 +define void @local_local_zextload_v3i16_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i16> addrspace(3)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(3)* %in + %ext = zext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_local_sextload_v3i16_to_v3i32: +; GCN: ds_read_b64 +; GCN-DAG: ds_write_b32 +; GCN-DAG: ds_write_b64 +define void @local_local_sextload_v3i16_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i16> addrspace(3)* %in) { +entry: + %ld = load <3 x i16>, <3 x i16> addrspace(3)* %in + %ext = sext <3 x i16> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_local_zextload_v4i16_to_v4i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b64 + +; EG: LDS_USHORT_READ_RET +; EG: LDS_USHORT_READ_RET +; EG: LDS_USHORT_READ_RET +; EG: LDS_USHORT_READ_RET +define void @local_local_zextload_v4i16_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i16> addrspace(3)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(3)* %in + %ext = zext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i16_to_v4i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b64 + +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: LDS_USHORT_READ_RET +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +define void @local_sextload_v4i16_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i16> addrspace(3)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(3)* %in + %ext = sext <4 x i16> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i16_to_v8i32: +; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}} +define void @local_zextload_v8i16_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(3)* %in + %ext = zext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i16_to_v8i32: +; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}} +define void @local_sextload_v8i16_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(3)* %in + %ext = sext <8 x i16> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FIXME: Should have 2 ds_read_b64 +; FUNC-LABEL: {{^}}local_zextload_v16i16_to_v16i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}} +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:24 + +; GCN: ds_write2_b64 +; GCN: ds_write2_b64 +; GCN: ds_write2_b64 +; GCN: ds_write2_b64 +define void @local_zextload_v16i16_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i16> addrspace(3)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(3)* %in + %ext = zext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i16_to_v16i32: +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:1{{$}} +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:16{{$}} +define void @local_sextload_v16i16_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i16> addrspace(3)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(3)* %in + %ext = sext <16 x i16> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i16_to_v32i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 +define void @local_zextload_v32i16_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i16> addrspace(3)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(3)* %in + %ext = zext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i16_to_v32i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 +define void @local_sextload_v32i16_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i16> addrspace(3)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(3)* %in + %ext = sext <32 x i16> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FIXME: Missed read2 +; FUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:11 offset1:15 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7 +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:64 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:9 offset1:10 +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:12 offset1:13 +; GCN-DAG: ds_read_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:112 +define void @local_zextload_v64i16_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i16> addrspace(3)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(3)* %in + %ext = zext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i32: +define void @local_sextload_v64i16_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i16> addrspace(3)* %in) #0 { + %load = load <64 x i16>, <64 x i16> addrspace(3)* %in + %ext = sext <64 x i16> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i16_to_i64: +; GCN-DAG: ds_read_u16 v[[LO:[0-9]+]], +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} + +; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] +define void @local_zextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* %in) #0 { + %a = load i16, i16 addrspace(3)* %in + %ext = zext i16 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i16_to_i64: +; GCN: ds_read_i16 v[[LO:[0-9]+]], +; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] +define void @local_sextload_i16_to_i64(i64 addrspace(3)* %out, i16 addrspace(3)* %in) #0 { + %a = load i16, i16 addrspace(3)* %in + %ext = sext i16 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i16_to_v1i64: +define void @local_zextload_v1i16_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i16> addrspace(3)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(3)* %in + %ext = zext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i16_to_v1i64: +define void @local_sextload_v1i16_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i16> addrspace(3)* %in) #0 { + %load = load <1 x i16>, <1 x i16> addrspace(3)* %in + %ext = sext <1 x i16> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i16_to_v2i64: +define void @local_zextload_v2i16_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i16> addrspace(3)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(3)* %in + %ext = zext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i16_to_v2i64: +define void @local_sextload_v2i16_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i16> addrspace(3)* %in) #0 { + %load = load <2 x i16>, <2 x i16> addrspace(3)* %in + %ext = sext <2 x i16> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i16_to_v4i64: +define void @local_zextload_v4i16_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i16> addrspace(3)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(3)* %in + %ext = zext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i16_to_v4i64: +define void @local_sextload_v4i16_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i16> addrspace(3)* %in) #0 { + %load = load <4 x i16>, <4 x i16> addrspace(3)* %in + %ext = sext <4 x i16> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i16_to_v8i64: +define void @local_zextload_v8i16_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(3)* %in + %ext = zext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i16_to_v8i64: +define void @local_sextload_v8i16_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i16> addrspace(3)* %in) #0 { + %load = load <8 x i16>, <8 x i16> addrspace(3)* %in + %ext = sext <8 x i16> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i16_to_v16i64: +define void @local_zextload_v16i16_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i16> addrspace(3)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(3)* %in + %ext = zext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i16_to_v16i64: +define void @local_sextload_v16i16_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i16> addrspace(3)* %in) #0 { + %load = load <16 x i16>, <16 x i16> addrspace(3)* %in + %ext = sext <16 x i16> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i16_to_v32i64: +define void @local_zextload_v32i16_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i16> addrspace(3)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(3)* %in + %ext = zext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i16_to_v32i64: +define void @local_sextload_v32i16_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i16> addrspace(3)* %in) #0 { + %load = load <32 x i16>, <32 x i16> addrspace(3)* %in + %ext = sext <32 x i16> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; ; XFUNC-LABEL: {{^}}local_zextload_v64i16_to_v64i64: +; define void @local_zextload_v64i16_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i16> addrspace(3)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(3)* %in +; %ext = zext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(3)* %out +; ret void +; } + +; ; XFUNC-LABEL: {{^}}local_sextload_v64i16_to_v64i64: +; define void @local_sextload_v64i16_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i16> addrspace(3)* %in) #0 { +; %load = load <64 x i16>, <64 x i16> addrspace(3)* %in +; %ext = sext <64 x i16> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(3)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-i32.ll b/test/CodeGen/AMDGPU/load-local-i32.ll new file mode 100644 index 000000000000..d68a8518e2ed --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-i32.ll @@ -0,0 +1,182 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}local_load_i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0, -1 +; GCN: ds_read_b32 + +; EG: LDS_READ_RET +define void @local_load_i32(i32 addrspace(3)* %out, i32 addrspace(3)* %in) #0 { +entry: + %ld = load i32, i32 addrspace(3)* %in + store i32 %ld, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2i32: +; GCN: ds_read_b64 +define void @local_load_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> addrspace(3)* %in) #0 { +entry: + %ld = load <2 x i32>, <2 x i32> addrspace(3)* %in + store <2 x i32> %ld, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3i32: +; GCN-DAG: ds_read_b64 +; GCN-DAG: ds_read_b32 +define void @local_load_v3i32(<3 x i32> addrspace(3)* %out, <3 x i32> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x i32>, <3 x i32> addrspace(3)* %in + store <3 x i32> %ld, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4i32: +; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} + +define void @local_load_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> addrspace(3)* %in) #0 { +entry: + %ld = load <4 x i32>, <4 x i32> addrspace(3)* %in + store <4 x i32> %ld, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1{{$}} +define void @local_load_v8i32(<8 x i32> addrspace(3)* %out, <8 x i32> addrspace(3)* %in) #0 { +entry: + %ld = load <8 x i32>, <8 x i32> addrspace(3)* %in + store <8 x i32> %ld, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16i32: +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:3 offset1:4{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:5 offset1:6{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7{{$}} +; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:1 offset1:2{{$}} +define void @local_load_v16i32(<16 x i32> addrspace(3)* %out, <16 x i32> addrspace(3)* %in) #0 { +entry: + %ld = load <16 x i32>, <16 x i32> addrspace(3)* %in + store <16 x i32> %ld, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i32_to_i64: +define void @local_zextload_i32_to_i64(i64 addrspace(3)* %out, i32 addrspace(3)* %in) #0 { + %ld = load i32, i32 addrspace(3)* %in + %ext = zext i32 %ld to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i32_to_i64: +define void @local_sextload_i32_to_i64(i64 addrspace(3)* %out, i32 addrspace(3)* %in) #0 { + %ld = load i32, i32 addrspace(3)* %in + %ext = sext i32 %ld to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i32_to_v1i64: +define void @local_zextload_v1i32_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i32> addrspace(3)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(3)* %in + %ext = zext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i32_to_v1i64: +define void @local_sextload_v1i32_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i32> addrspace(3)* %in) #0 { + %ld = load <1 x i32>, <1 x i32> addrspace(3)* %in + %ext = sext <1 x i32> %ld to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i32_to_v2i64: +define void @local_zextload_v2i32_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i32> addrspace(3)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(3)* %in + %ext = zext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i32_to_v2i64: +define void @local_sextload_v2i32_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i32> addrspace(3)* %in) #0 { + %ld = load <2 x i32>, <2 x i32> addrspace(3)* %in + %ext = sext <2 x i32> %ld to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i32_to_v4i64: +define void @local_zextload_v4i32_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i32> addrspace(3)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(3)* %in + %ext = zext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i32_to_v4i64: +define void @local_sextload_v4i32_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i32> addrspace(3)* %in) #0 { + %ld = load <4 x i32>, <4 x i32> addrspace(3)* %in + %ext = sext <4 x i32> %ld to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i32_to_v8i64: +define void @local_zextload_v8i32_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i32> addrspace(3)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(3)* %in + %ext = zext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i32_to_v8i64: +define void @local_sextload_v8i32_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i32> addrspace(3)* %in) #0 { + %ld = load <8 x i32>, <8 x i32> addrspace(3)* %in + %ext = sext <8 x i32> %ld to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i32_to_v16i64: +define void @local_sextload_v16i32_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i32> addrspace(3)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(3)* %in + %ext = sext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i32_to_v16i64 +define void @local_zextload_v16i32_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i32> addrspace(3)* %in) #0 { + %ld = load <16 x i32>, <16 x i32> addrspace(3)* %in + %ext = zext <16 x i32> %ld to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i32_to_v32i64: +define void @local_sextload_v32i32_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i32> addrspace(3)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(3)* %in + %ext = sext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i32_to_v32i64: +define void @local_zextload_v32i32_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i32> addrspace(3)* %in) #0 { + %ld = load <32 x i32>, <32 x i32> addrspace(3)* %in + %ext = zext <32 x i32> %ld to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-i64.ll b/test/CodeGen/AMDGPU/load-local-i64.ll new file mode 100644 index 000000000000..180807df7b9a --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-i64.ll @@ -0,0 +1,154 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}local_load_i64: +; GCN: ds_read_b64 [[VAL:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}} +; GCN: ds_write_b64 v{{[0-9]+}}, [[VAL]] + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_i64(i64 addrspace(3)* %out, i64 addrspace(3)* %in) #0 { + %ld = load i64, i64 addrspace(3)* %in + store i64 %ld, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2i64: +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v2i64(<2 x i64> addrspace(3)* %out, <2 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <2 x i64>, <2 x i64> addrspace(3)* %in + store <2 x i64> %ld, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3i64: +; GCN-DAG: ds_read2_b64 +; GCN-DAG: ds_read_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v3i64(<3 x i64> addrspace(3)* %out, <3 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x i64>, <3 x i64> addrspace(3)* %in + store <3 x i64> %ld, <3 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4i64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v4i64(<4 x i64> addrspace(3)* %out, <4 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <4 x i64>, <4 x i64> addrspace(3)* %in + store <4 x i64> %ld, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8i64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v8i64(<8 x i64> addrspace(3)* %out, <8 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <8 x i64>, <8 x i64> addrspace(3)* %in + store <8 x i64> %ld, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16i64: +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 +; GCN: ds_read2_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v16i64(<16 x i64> addrspace(3)* %out, <16 x i64> addrspace(3)* %in) #0 { +entry: + %ld = load <16 x i64>, <16 x i64> addrspace(3)* %in + store <16 x i64> %ld, <16 x i64> addrspace(3)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-local-i8.ll b/test/CodeGen/AMDGPU/load-local-i8.ll new file mode 100644 index 000000000000..be865b078d74 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-local-i8.ll @@ -0,0 +1,556 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + + +; FUNC-LABEL: {{^}}local_load_i8: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_u8 + +; EG: LDS_UBYTE_READ_RET +define void @local_load_i8(i8 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { +entry: + %ld = load i8, i8 addrspace(3)* %in + store i8 %ld, i8 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v2i8: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_u16 + +; EG: LDS_USHORT_READ_RET +define void @local_load_v2i8(<2 x i8> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <2 x i8>, <2 x i8> addrspace(3)* %in + store <2 x i8> %ld, <2 x i8> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v3i8: +; GCN: ds_read_b32 + +; EG: DS_READ_RET +define void @local_load_v3i8(<3 x i8> addrspace(3)* %out, <3 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(3)* %in + store <3 x i8> %ld, <3 x i8> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v4i8: +; GCN: ds_read_b32 + +; EG: LDS_READ_RET +define void @local_load_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <4 x i8>, <4 x i8> addrspace(3)* %in + store <4 x i8> %ld, <4 x i8> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v8i8: +; GCN: ds_read_b64 + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v8i8(<8 x i8> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <8 x i8>, <8 x i8> addrspace(3)* %in + store <8 x i8> %ld, <8 x i8> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_load_v16i8: +; GCN: ds_read2_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}} +; GCN: ds_write2_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:{{[0-9]+}}], v[{{[0-9]+}}:[[HI]]{{\]}} offset0:1{{$}} + +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +; EG: LDS_READ_RET +define void @local_load_v16i8(<16 x i8> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <16 x i8>, <16 x i8> addrspace(3)* %in + store <16 x i8> %ld, <16 x i8> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i8_to_i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_u8 + +; EG: LDS_UBYTE_READ_RET +define void @local_zextload_i8_to_i32(i32 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %a = load i8, i8 addrspace(3)* %in + %ext = zext i8 %a to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i8_to_i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_i8 + +; EG: LDS_UBYTE_READ_RET +; EG: BFE_INT +define void @local_sextload_i8_to_i32(i32 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %ld = load i8, i8 addrspace(3)* %in + %ext = sext i8 %ld to i32 + store i32 %ext, i32 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i8_to_v1i32: +define void @local_zextload_v1i8_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = zext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i8_to_v1i32: +define void @local_sextload_v1i8_to_v1i32(<1 x i32> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = sext <1 x i8> %load to <1 x i32> + store <1 x i32> %ext, <1 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i8_to_v2i32: +; GCN: ds_read_u16 + +; EG: LDS_UBYTE_READ_RET +; EG: LDS_UBYTE_READ_RET +define void @local_zextload_v2i8_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = zext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i8_to_v2i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_u16 +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 8, 8 +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 + +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +define void @local_sextload_v2i8_to_v2i32(<2 x i32> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = sext <2 x i8> %load to <2 x i32> + store <2 x i32> %ext, <2 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v3i8_to_v3i32: +; GCN: ds_read_b32 + +; GCN-DAG: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 8, 8 +; GCN-DAG: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, 16, 8 +; GCN-DAG: v_and_b32_e32 v{{[0-9]+}}, 0xff, +define void @local_zextload_v3i8_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(3)* %in + %ext = zext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v3i8_to_v3i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; GCN-DAG: v_bfe_i32 +; GCN-DAG: v_bfe_i32 +; GCN-DAG: v_bfe_i32 +; GCN-DAG: v_bfe_i32 + +; GCN-DAG: ds_write_b64 +; GCN-DAG: ds_write_b32 + +define void @local_sextload_v3i8_to_v3i32(<3 x i32> addrspace(3)* %out, <3 x i8> addrspace(3)* %in) #0 { +entry: + %ld = load <3 x i8>, <3 x i8> addrspace(3)* %in + %ext = sext <3 x i8> %ld to <3 x i32> + store <3 x i32> %ext, <3 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i8_to_v4i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; EG: LDS_UBYTE_READ_RET +; EG: LDS_UBYTE_READ_RET +; EG: LDS_UBYTE_READ_RET +; EG: LDS_UBYTE_READ_RET +define void @local_zextload_v4i8_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = zext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i8_to_v4i32: +; GCN-NOT: s_wqm_b64 +; GCN: s_mov_b32 m0 +; GCN: ds_read_b32 + +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: LDS_UBYTE_READ_RET +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +; EG-DAG: BFE_INT +define void @local_sextload_v4i8_to_v4i32(<4 x i32> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = sext <4 x i8> %load to <4 x i32> + store <4 x i32> %ext, <4 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i8_to_v8i32: +define void @local_zextload_v8i8_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = zext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i8_to_v8i32: +define void @local_sextload_v8i8_to_v8i32(<8 x i32> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = sext <8 x i8> %load to <8 x i32> + store <8 x i32> %ext, <8 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i8_to_v16i32: +define void @local_zextload_v16i8_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = zext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i8_to_v16i32: +define void @local_sextload_v16i8_to_v16i32(<16 x i32> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = sext <16 x i8> %load to <16 x i32> + store <16 x i32> %ext, <16 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i8_to_v32i32: +define void @local_zextload_v32i8_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = zext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i8_to_v32i32: +define void @local_sextload_v32i8_to_v32i32(<32 x i32> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = sext <32 x i8> %load to <32 x i32> + store <32 x i32> %ext, <32 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i32: +define void @local_zextload_v64i8_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(3)* %in + %ext = zext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i32: +define void @local_sextload_v64i8_to_v64i32(<64 x i32> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { + %load = load <64 x i8>, <64 x i8> addrspace(3)* %in + %ext = sext <64 x i8> %load to <64 x i32> + store <64 x i32> %ext, <64 x i32> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_i8_to_i64: +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN-DAG: ds_read_u8 v[[LO:[0-9]+]], +; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]] +define void @local_zextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %a = load i8, i8 addrspace(3)* %in + %ext = zext i8 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i8_to_i64: +; GCN: ds_read_i8 v[[LO:[0-9]+]], +; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] + +; GCN: ds_write_b64 v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @local_sextload_i8_to_i64(i64 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %a = load i8, i8 addrspace(3)* %in + %ext = sext i8 %a to i64 + store i64 %ext, i64 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i8_to_v1i64: +define void @local_zextload_v1i8_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = zext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i8_to_v1i64: +define void @local_sextload_v1i8_to_v1i64(<1 x i64> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = sext <1 x i8> %load to <1 x i64> + store <1 x i64> %ext, <1 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i8_to_v2i64: +define void @local_zextload_v2i8_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = zext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i8_to_v2i64: +define void @local_sextload_v2i8_to_v2i64(<2 x i64> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = sext <2 x i8> %load to <2 x i64> + store <2 x i64> %ext, <2 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i8_to_v4i64: +define void @local_zextload_v4i8_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = zext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i8_to_v4i64: +define void @local_sextload_v4i8_to_v4i64(<4 x i64> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = sext <4 x i8> %load to <4 x i64> + store <4 x i64> %ext, <4 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i8_to_v8i64: +define void @local_zextload_v8i8_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = zext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i8_to_v8i64: +define void @local_sextload_v8i8_to_v8i64(<8 x i64> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = sext <8 x i8> %load to <8 x i64> + store <8 x i64> %ext, <8 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i8_to_v16i64: +define void @local_zextload_v16i8_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = zext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i8_to_v16i64: +define void @local_sextload_v16i8_to_v16i64(<16 x i64> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = sext <16 x i8> %load to <16 x i64> + store <16 x i64> %ext, <16 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i8_to_v32i64: +define void @local_zextload_v32i8_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = zext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i8_to_v32i64: +define void @local_sextload_v32i8_to_v32i64(<32 x i64> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = sext <32 x i8> %load to <32 x i64> + store <32 x i64> %ext, <32 x i64> addrspace(3)* %out + ret void +} + +; XFUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i64: +; define void @local_zextload_v64i8_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(3)* %in +; %ext = zext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(3)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i64: +; define void @local_sextload_v64i8_to_v64i64(<64 x i64> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(3)* %in +; %ext = sext <64 x i8> %load to <64 x i64> +; store <64 x i64> %ext, <64 x i64> addrspace(3)* %out +; ret void +; } + +; FUNC-LABEL: {{^}}local_zextload_i8_to_i16: +; GCN: ds_read_u8 v[[VAL:[0-9]+]], +; GCN: ds_write_b16 v[[VAL:[0-9]+]] +define void @local_zextload_i8_to_i16(i16 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %a = load i8, i8 addrspace(3)* %in + %ext = zext i8 %a to i16 + store i16 %ext, i16 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_i8_to_i16: +; GCN: ds_read_i8 v[[VAL:[0-9]+]], +; GCN: ds_write_b16 v{{[0-9]+}}, v[[VAL]] +define void @local_sextload_i8_to_i16(i16 addrspace(3)* %out, i8 addrspace(3)* %in) #0 { + %a = load i8, i8 addrspace(3)* %in + %ext = sext i8 %a to i16 + store i16 %ext, i16 addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v1i8_to_v1i16: +define void @local_zextload_v1i8_to_v1i16(<1 x i16> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = zext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v1i8_to_v1i16: +define void @local_sextload_v1i8_to_v1i16(<1 x i16> addrspace(3)* %out, <1 x i8> addrspace(3)* %in) #0 { + %load = load <1 x i8>, <1 x i8> addrspace(3)* %in + %ext = sext <1 x i8> %load to <1 x i16> + store <1 x i16> %ext, <1 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v2i8_to_v2i16: +define void @local_zextload_v2i8_to_v2i16(<2 x i16> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = zext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v2i8_to_v2i16: +define void @local_sextload_v2i8_to_v2i16(<2 x i16> addrspace(3)* %out, <2 x i8> addrspace(3)* %in) #0 { + %load = load <2 x i8>, <2 x i8> addrspace(3)* %in + %ext = sext <2 x i8> %load to <2 x i16> + store <2 x i16> %ext, <2 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v4i8_to_v4i16: +define void @local_zextload_v4i8_to_v4i16(<4 x i16> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = zext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v4i8_to_v4i16: +define void @local_sextload_v4i8_to_v4i16(<4 x i16> addrspace(3)* %out, <4 x i8> addrspace(3)* %in) #0 { + %load = load <4 x i8>, <4 x i8> addrspace(3)* %in + %ext = sext <4 x i8> %load to <4 x i16> + store <4 x i16> %ext, <4 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v8i8_to_v8i16: +define void @local_zextload_v8i8_to_v8i16(<8 x i16> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = zext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v8i8_to_v8i16: +define void @local_sextload_v8i8_to_v8i16(<8 x i16> addrspace(3)* %out, <8 x i8> addrspace(3)* %in) #0 { + %load = load <8 x i8>, <8 x i8> addrspace(3)* %in + %ext = sext <8 x i8> %load to <8 x i16> + store <8 x i16> %ext, <8 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v16i8_to_v16i16: +define void @local_zextload_v16i8_to_v16i16(<16 x i16> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = zext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v16i8_to_v16i16: +define void @local_sextload_v16i8_to_v16i16(<16 x i16> addrspace(3)* %out, <16 x i8> addrspace(3)* %in) #0 { + %load = load <16 x i8>, <16 x i8> addrspace(3)* %in + %ext = sext <16 x i8> %load to <16 x i16> + store <16 x i16> %ext, <16 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_zextload_v32i8_to_v32i16: +define void @local_zextload_v32i8_to_v32i16(<32 x i16> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = zext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(3)* %out + ret void +} + +; FUNC-LABEL: {{^}}local_sextload_v32i8_to_v32i16: +define void @local_sextload_v32i8_to_v32i16(<32 x i16> addrspace(3)* %out, <32 x i8> addrspace(3)* %in) #0 { + %load = load <32 x i8>, <32 x i8> addrspace(3)* %in + %ext = sext <32 x i8> %load to <32 x i16> + store <32 x i16> %ext, <32 x i16> addrspace(3)* %out + ret void +} + +; XFUNC-LABEL: {{^}}local_zextload_v64i8_to_v64i16: +; define void @local_zextload_v64i8_to_v64i16(<64 x i16> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(3)* %in +; %ext = zext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(3)* %out +; ret void +; } + +; XFUNC-LABEL: {{^}}local_sextload_v64i8_to_v64i16: +; define void @local_sextload_v64i8_to_v64i16(<64 x i16> addrspace(3)* %out, <64 x i8> addrspace(3)* %in) #0 { +; %load = load <64 x i8>, <64 x i8> addrspace(3)* %in +; %ext = sext <64 x i8> %load to <64 x i16> +; store <64 x i16> %ext, <64 x i16> addrspace(3)* %out +; ret void +; } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load-weird-sizes.ll b/test/CodeGen/AMDGPU/load-weird-sizes.ll new file mode 100644 index 000000000000..b9f7018b8107 --- /dev/null +++ b/test/CodeGen/AMDGPU/load-weird-sizes.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=CI-HSA -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI-NOHSA -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=R600 -check-prefix=CM -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}load_i24: +; SI: {{flat|buffer}}_load_ubyte +; SI: {{flat|buffer}}_load_ushort +; SI: {{flat|buffer}}_store_dword +define void @load_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) #0 { + %1 = load i24, i24 addrspace(1)* %in + %2 = zext i24 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}load_i25: +; SI-NOHSA: buffer_load_dword [[VAL:v[0-9]+]] +; SI-NOHSA: buffer_store_dword [[VAL]] + +; CI-HSA: flat_load_dword [[VAL:v[0-9]+]] +; CI-HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[VAL]] +define void @load_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) #0 { + %1 = load i25, i25 addrspace(1)* %in + %2 = zext i25 %1 to i32 + store i32 %2, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/load.ll b/test/CodeGen/AMDGPU/load.ll deleted file mode 100644 index 6486c6ab2ffc..000000000000 --- a/test/CodeGen/AMDGPU/load.ll +++ /dev/null @@ -1,737 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=R600 --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI-NOHSA --check-prefix=FUNC %s -; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck --check-prefix=FUNC --check-prefix=CI-HSA --check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI-NOHSA --check-prefix=FUNC %s - -;===------------------------------------------------------------------------===; -; GLOBAL ADDRESS SPACE -;===------------------------------------------------------------------------===; - -; Load an i8 value from the global address space. -; FUNC-LABEL: {{^}}load_i8: -; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} - -; SI-NOHSA: buffer_load_ubyte v{{[0-9]+}}, -; CI-HSA: flat_load_ubyte -define void @load_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { - %1 = load i8, i8 addrspace(1)* %in - %2 = zext i8 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i8_sext: -; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal -; R600: 8 -; SI-NOHSA: buffer_load_sbyte -; CI-HSA: flat_load_sbyte -define void @load_i8_sext(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { -entry: - %0 = load i8, i8 addrspace(1)* %in - %1 = sext i8 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i8: -; R600: VTX_READ_8 -; R600: VTX_READ_8 -; SI-NOHSA: buffer_load_ubyte -; SI-NOHSA: buffer_load_ubyte -; CI-HSA: flat_load_ubyte -; CI-HSA: flat_load_ubyte -define void @load_v2i8(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { -entry: - %0 = load <2 x i8>, <2 x i8> addrspace(1)* %in - %1 = zext <2 x i8> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i8_sext: -; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal -; R600-DAG: 8 -; R600-DAG: 8 - -; SI-NOHSA: buffer_load_sbyte -; SI-NOHSA: buffer_load_sbyte -; CI-HSA: flat_load_sbyte -; CI-HSA: flat_load_sbyte -define void @load_v2i8_sext(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { -entry: - %0 = load <2 x i8>, <2 x i8> addrspace(1)* %in - %1 = sext <2 x i8> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i8: -; R600: VTX_READ_8 -; R600: VTX_READ_8 -; R600: VTX_READ_8 -; R600: VTX_READ_8 -; SI-NOHSA: buffer_load_ubyte -; SI-NOHSA: buffer_load_ubyte -; SI-NOHSA: buffer_load_ubyte -; SI-NOHSA: buffer_load_ubyte -; CI-HSA: flat_load_ubyte -; CI-HSA: flat_load_ubyte -; CI-HSA: flat_load_ubyte -; CI-HSA: flat_load_ubyte -define void @load_v4i8(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { -entry: - %0 = load <4 x i8>, <4 x i8> addrspace(1)* %in - %1 = zext <4 x i8> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i8_sext: -; R600-DAG: VTX_READ_8 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-DAG: VTX_READ_8 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-DAG: VTX_READ_8 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] -; R600-DAG: VTX_READ_8 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal -; R600-DAG: 8 -; R600-DAG: 8 -; R600-DAG: 8 -; R600-DAG: 8 -; SI-NOHSA: buffer_load_sbyte -; SI-NOHSA: buffer_load_sbyte -; SI-NOHSA: buffer_load_sbyte -; SI-NOHSA: buffer_load_sbyte -; CI-HSA: flat_load_sbyte -; CI-HSA: flat_load_sbyte -; CI-HSA: flat_load_sbyte -; CI-HSA: flat_load_sbyte -define void @load_v4i8_sext(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { -entry: - %0 = load <4 x i8>, <4 x i8> addrspace(1)* %in - %1 = sext <4 x i8> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; Load an i16 value from the global address space. -; FUNC-LABEL: {{^}}load_i16: -; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-NOHSA: buffer_load_ushort -; CI-HSA: flat_load_ushort -define void @load_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { -entry: - %0 = load i16 , i16 addrspace(1)* %in - %1 = zext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i16_sext: -; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal -; R600: 16 -; SI-NOHSA: buffer_load_sshort -; CI-HSA: flat_load_sshort -define void @load_i16_sext(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { -entry: - %0 = load i16, i16 addrspace(1)* %in - %1 = sext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i16: -; R600: VTX_READ_16 -; R600: VTX_READ_16 -; SI-NOHSA: buffer_load_ushort -; SI-NOHSA: buffer_load_ushort -; CI-HSA: flat_load_ushort -; CI-HSA: flat_load_ushort -define void @load_v2i16(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { -entry: - %0 = load <2 x i16>, <2 x i16> addrspace(1)* %in - %1 = zext <2 x i16> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i16_sext: -; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal -; R600-DAG: 16 -; R600-DAG: 16 -; SI-NOHSA: buffer_load_sshort -; SI-NOHSA: buffer_load_sshort -; CI-HSA: flat_load_sshort -; CI-HSA: flat_load_sshort -define void @load_v2i16_sext(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { -entry: - %0 = load <2 x i16>, <2 x i16> addrspace(1)* %in - %1 = sext <2 x i16> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i16: -; R600: VTX_READ_16 -; R600: VTX_READ_16 -; R600: VTX_READ_16 -; R600: VTX_READ_16 -; SI-NOHSA: buffer_load_ushort -; SI-NOHSA: buffer_load_ushort -; SI-NOHSA: buffer_load_ushort -; SI-NOHSA: buffer_load_ushort -; CI-HSA: flat_load_ushort -; CI-HSA: flat_load_ushort -; CI-HSA: flat_load_ushort -; CI-HSA: flat_load_ushort -define void @load_v4i16(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { -entry: - %0 = load <4 x i16>, <4 x i16> addrspace(1)* %in - %1 = zext <4 x i16> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i16_sext: -; R600-DAG: VTX_READ_16 [[DST_X:T[0-9]\.[XYZW]]], [[DST_X]] -; R600-DAG: VTX_READ_16 [[DST_Y:T[0-9]\.[XYZW]]], [[DST_Y]] -; R600-DAG: VTX_READ_16 [[DST_Z:T[0-9]\.[XYZW]]], [[DST_Z]] -; R600-DAG: VTX_READ_16 [[DST_W:T[0-9]\.[XYZW]]], [[DST_W]] -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_X]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Y]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_Z]], 0.0, literal -; R600-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST_W]], 0.0, literal -; R600-DAG: 16 -; R600-DAG: 16 -; R600-DAG: 16 -; R600-DAG: 16 -; SI-NOHSA: buffer_load_sshort -; SI-NOHSA: buffer_load_sshort -; SI-NOHSA: buffer_load_sshort -; SI-NOHSA: buffer_load_sshort -; CI-HSA: flat_load_sshort -; CI-HSA: flat_load_sshort -; CI-HSA: flat_load_sshort -; CI-HSA: flat_load_sshort -define void @load_v4i16_sext(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { -entry: - %0 = load <4 x i16>, <4 x i16> addrspace(1)* %in - %1 = sext <4 x i16> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; load an i32 value from the global address space. -; FUNC-LABEL: {{^}}load_i32: -; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 - -; SI-NOHSA: buffer_load_dword v{{[0-9]+}} -; CI-HSA: flat_load_dword -define void @load_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { -entry: - %0 = load i32, i32 addrspace(1)* %in - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; load a f32 value from the global address space. -; FUNC-LABEL: {{^}}load_f32: -; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 - -; SI-NOHSA: buffer_load_dword v{{[0-9]+}} -; CI-HSA: flat_load_dword -define void @load_f32(float addrspace(1)* %out, float addrspace(1)* %in) { -entry: - %0 = load float, float addrspace(1)* %in - store float %0, float addrspace(1)* %out - ret void -} - -; load a v2f32 value from the global address space -; FUNC-LABEL: {{^}}load_v2f32: -; R600: MEM_RAT -; R600: VTX_READ_64 -; SI-NOHSA: buffer_load_dwordx2 -; CI-HSA: flat_load_dwordx2 -define void @load_v2f32(<2 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) { -entry: - %0 = load <2 x float>, <2 x float> addrspace(1)* %in - store <2 x float> %0, <2 x float> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i64: -; R600: VTX_READ_64 -; SI-NOHSA: buffer_load_dwordx2 -; CI-HSA: flat_load_dwordx2 -define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { -entry: - %0 = load i64, i64 addrspace(1)* %in - store i64 %0, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i64_sext: -; R600: MEM_RAT -; R600: MEM_RAT -; R600: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x -; R600: 31 -; SI-NOHSA: buffer_load_dword -; CI-HSA: flat_load_dword - -define void @load_i64_sext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { -entry: - %0 = load i32, i32 addrspace(1)* %in - %1 = sext i32 %0 to i64 - store i64 %1, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i64_zext: -; R600: MEM_RAT -; R600: MEM_RAT -define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { -entry: - %0 = load i32, i32 addrspace(1)* %in - %1 = zext i32 %0 to i64 - store i64 %1, i64 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v8i32: -; R600: VTX_READ_128 -; R600: VTX_READ_128 - -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -define void @load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(1)* %in) { -entry: - %0 = load <8 x i32>, <8 x i32> addrspace(1)* %in - store <8 x i32> %0, <8 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v16i32: -; R600: VTX_READ_128 -; R600: VTX_READ_128 -; R600: VTX_READ_128 -; R600: VTX_READ_128 - -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; SI-NOHSA: buffer_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -; CI-HSA: flat_load_dwordx4 -define void @load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(1)* %in) { -entry: - %0 = load <16 x i32>, <16 x i32> addrspace(1)* %in - store <16 x i32> %0, <16 x i32> addrspace(1)* %out - ret void -} - -;===------------------------------------------------------------------------===; -; CONSTANT ADDRESS SPACE -;===------------------------------------------------------------------------===; - -; Load a sign-extended i8 value -; FUNC-LABEL: {{^}}load_const_i8_sext: -; R600: VTX_READ_8 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal -; R600: 8 -; SI-NOHSA: buffer_load_sbyte v{{[0-9]+}}, -; CI-HSA: flat_load_sbyte v{{[0-9]+}}, -define void @load_const_i8_sext(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { -entry: - %0 = load i8, i8 addrspace(2)* %in - %1 = sext i8 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; Load an aligned i8 value -; FUNC-LABEL: {{^}}load_const_i8_aligned: -; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-NOHSA: buffer_load_ubyte v{{[0-9]+}}, -; CI-HSA: flat_load_ubyte v{{[0-9]+}}, -define void @load_const_i8_aligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { -entry: - %0 = load i8, i8 addrspace(2)* %in - %1 = zext i8 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; Load an un-aligned i8 value -; FUNC-LABEL: {{^}}load_const_i8_unaligned: -; R600: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-NOHSA: buffer_load_ubyte v{{[0-9]+}}, -; CI-HSA: flat_load_ubyte v{{[0-9]+}}, -define void @load_const_i8_unaligned(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { -entry: - %0 = getelementptr i8, i8 addrspace(2)* %in, i32 1 - %1 = load i8, i8 addrspace(2)* %0 - %2 = zext i8 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} - -; Load a sign-extended i16 value -; FUNC-LABEL: {{^}}load_const_i16_sext: -; R600: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]] -; R600: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal -; R600: 16 -; SI-NOHSA: buffer_load_sshort -; CI-HSA: flat_load_sshort -define void @load_const_i16_sext(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { -entry: - %0 = load i16, i16 addrspace(2)* %in - %1 = sext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; Load an aligned i16 value -; FUNC-LABEL: {{^}}load_const_i16_aligned: -; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-NOHSA: buffer_load_ushort -; CI-HSA: flat_load_ushort -define void @load_const_i16_aligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { -entry: - %0 = load i16, i16 addrspace(2)* %in - %1 = zext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; Load an un-aligned i16 value -; FUNC-LABEL: {{^}}load_const_i16_unaligned: -; R600: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-NOHSA: buffer_load_ushort -; CI-HSA: flat_load_ushort -define void @load_const_i16_unaligned(i32 addrspace(1)* %out, i16 addrspace(2)* %in) { -entry: - %0 = getelementptr i16, i16 addrspace(2)* %in, i32 1 - %1 = load i16, i16 addrspace(2)* %0 - %2 = zext i16 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} - -; Load an i32 value from the constant address space. -; FUNC-LABEL: {{^}}load_const_addrspace_i32: -; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 - -; SI: s_load_dword s{{[0-9]+}} -define void @load_const_addrspace_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { -entry: - %0 = load i32, i32 addrspace(2)* %in - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; Load a f32 value from the constant address space. -; FUNC-LABEL: {{^}}load_const_addrspace_f32: -; R600: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 - -; SI: s_load_dword s{{[0-9]+}} -define void @load_const_addrspace_f32(float addrspace(1)* %out, float addrspace(2)* %in) { - %1 = load float, float addrspace(2)* %in - store float %1, float addrspace(1)* %out - ret void -} - -;===------------------------------------------------------------------------===; -; LOCAL ADDRESS SPACE -;===------------------------------------------------------------------------===; - -; Load an i8 value from the local address space. -; FUNC-LABEL: {{^}}load_i8_local: -; R600: LDS_UBYTE_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u8 -define void @load_i8_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { - %1 = load i8, i8 addrspace(3)* %in - %2 = zext i8 %1 to i32 - store i32 %2, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i8_sext_local: -; R600: LDS_UBYTE_READ_RET -; R600: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i8 -define void @load_i8_sext_local(i32 addrspace(1)* %out, i8 addrspace(3)* %in) { -entry: - %0 = load i8, i8 addrspace(3)* %in - %1 = sext i8 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i8_local: -; R600: LDS_UBYTE_READ_RET -; R600: LDS_UBYTE_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u8 -; SI: ds_read_u8 -define void @load_v2i8_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { -entry: - %0 = load <2 x i8>, <2 x i8> addrspace(3)* %in - %1 = zext <2 x i8> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i8_sext_local: -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i8 -; SI: ds_read_i8 -define void @load_v2i8_sext_local(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(3)* %in) { -entry: - %0 = load <2 x i8>, <2 x i8> addrspace(3)* %in - %1 = sext <2 x i8> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i8_local: -; R600: LDS_UBYTE_READ_RET -; R600: LDS_UBYTE_READ_RET -; R600: LDS_UBYTE_READ_RET -; R600: LDS_UBYTE_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -define void @load_v4i8_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { -entry: - %0 = load <4 x i8>, <4 x i8> addrspace(3)* %in - %1 = zext <4 x i8> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i8_sext_local: -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: LDS_UBYTE_READ_RET -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i8 -; SI: ds_read_i8 -; SI: ds_read_i8 -; SI: ds_read_i8 -define void @load_v4i8_sext_local(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(3)* %in) { -entry: - %0 = load <4 x i8>, <4 x i8> addrspace(3)* %in - %1 = sext <4 x i8> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; Load an i16 value from the local address space. -; FUNC-LABEL: {{^}}load_i16_local: -; R600: LDS_USHORT_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u16 -define void @load_i16_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { -entry: - %0 = load i16 , i16 addrspace(3)* %in - %1 = zext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_i16_sext_local: -; R600: LDS_USHORT_READ_RET -; R600: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i16 -define void @load_i16_sext_local(i32 addrspace(1)* %out, i16 addrspace(3)* %in) { -entry: - %0 = load i16, i16 addrspace(3)* %in - %1 = sext i16 %0 to i32 - store i32 %1, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i16_local: -; R600: LDS_USHORT_READ_RET -; R600: LDS_USHORT_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u16 -; SI: ds_read_u16 -define void @load_v2i16_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { -entry: - %0 = load <2 x i16>, <2 x i16> addrspace(3)* %in - %1 = zext <2 x i16> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v2i16_sext_local: -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i16 -; SI: ds_read_i16 -define void @load_v2i16_sext_local(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(3)* %in) { -entry: - %0 = load <2 x i16>, <2 x i16> addrspace(3)* %in - %1 = sext <2 x i16> %0 to <2 x i32> - store <2 x i32> %1, <2 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i16_local: -; R600: LDS_USHORT_READ_RET -; R600: LDS_USHORT_READ_RET -; R600: LDS_USHORT_READ_RET -; R600: LDS_USHORT_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -; SI: ds_read_u16 -define void @load_v4i16_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { -entry: - %0 = load <4 x i16>, <4 x i16> addrspace(3)* %in - %1 = zext <4 x i16> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}load_v4i16_sext_local: -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: LDS_USHORT_READ_RET -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; R600-DAG: BFE_INT -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_i16 -; SI: ds_read_i16 -; SI: ds_read_i16 -; SI: ds_read_i16 -define void @load_v4i16_sext_local(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(3)* %in) { -entry: - %0 = load <4 x i16>, <4 x i16> addrspace(3)* %in - %1 = sext <4 x i16> %0 to <4 x i32> - store <4 x i32> %1, <4 x i32> addrspace(1)* %out - ret void -} - -; load an i32 value from the local address space. -; FUNC-LABEL: {{^}}load_i32_local: -; R600: LDS_READ_RET -; SI-NOT: s_wqm_b64 -; SI: s_mov_b32 m0 -; SI: ds_read_b32 -define void @load_i32_local(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { -entry: - %0 = load i32, i32 addrspace(3)* %in - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; load a f32 value from the local address space. -; FUNC-LABEL: {{^}}load_f32_local: -; R600: LDS_READ_RET -; SI: s_mov_b32 m0 -; SI: ds_read_b32 -define void @load_f32_local(float addrspace(1)* %out, float addrspace(3)* %in) { -entry: - %0 = load float, float addrspace(3)* %in - store float %0, float addrspace(1)* %out - ret void -} - -; load a v2f32 value from the local address space -; FUNC-LABEL: {{^}}load_v2f32_local: -; R600: LDS_READ_RET -; R600: LDS_READ_RET -; SI: s_mov_b32 m0 -; SI: ds_read_b64 -define void @load_v2f32_local(<2 x float> addrspace(1)* %out, <2 x float> addrspace(3)* %in) { -entry: - %0 = load <2 x float>, <2 x float> addrspace(3)* %in - store <2 x float> %0, <2 x float> addrspace(1)* %out - ret void -} - -; Test loading a i32 and v2i32 value from the same base pointer. -; FUNC-LABEL: {{^}}load_i32_v2i32_local: -; R600: LDS_READ_RET -; R600: LDS_READ_RET -; R600: LDS_READ_RET -; SI-DAG: ds_read_b32 -; SI-DAG: ds_read2_b32 -define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) { - %scalar = load i32, i32 addrspace(3)* %in - %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)* - %vec_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(3)* %tmp0, i32 2 - %vec0 = load <2 x i32>, <2 x i32> addrspace(3)* %vec_ptr, align 4 - %vec1 = insertelement <2 x i32> , i32 %scalar, i32 0 - %vec = add <2 x i32> %vec0, %vec1 - store <2 x i32> %vec, <2 x i32> addrspace(1)* %out - ret void -} - - -@lds = addrspace(3) global [512 x i32] undef, align 4 - -; On SI we need to make sure that the base offset is a register and not -; an immediate. -; FUNC-LABEL: {{^}}load_i32_local_const_ptr: -; SI: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 -; SI: ds_read_b32 v0, v[[ZERO]] offset:4 -; R600: LDS_READ_RET -define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) { -entry: - %tmp0 = getelementptr [512 x i32], [512 x i32] addrspace(3)* @lds, i32 0, i32 1 - %tmp1 = load i32, i32 addrspace(3)* %tmp0 - %tmp2 = getelementptr i32, i32 addrspace(1)* %out, i32 1 - store i32 %tmp1, i32 addrspace(1)* %tmp2 - ret void -} diff --git a/test/CodeGen/AMDGPU/load.vec.ll b/test/CodeGen/AMDGPU/load.vec.ll deleted file mode 100644 index 02f883cd8e9c..000000000000 --- a/test/CodeGen/AMDGPU/load.vec.ll +++ /dev/null @@ -1,25 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s - -; load a v2i32 value from the global address space. -; EG: {{^}}load_v2i32: -; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 -; SI: {{^}}load_v2i32: -; SI: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] -define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { - %a = load <2 x i32>, <2 x i32> addrspace(1) * %in - store <2 x i32> %a, <2 x i32> addrspace(1)* %out - ret void -} - -; load a v4i32 value from the global address space. -; EG: {{^}}load_v4i32: -; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0 -; SI: {{^}}load_v4i32: -; SI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}] -define void @load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { - %a = load <4 x i32>, <4 x i32> addrspace(1) * %in - store <4 x i32> %a, <4 x i32> addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/load64.ll b/test/CodeGen/AMDGPU/load64.ll deleted file mode 100644 index 74beabdc0076..000000000000 --- a/test/CodeGen/AMDGPU/load64.ll +++ /dev/null @@ -1,31 +0,0 @@ -; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s - -; load a f64 value from the global address space. -; CHECK-LABEL: {{^}}load_f64: -; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] -; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] -define void @load_f64(double addrspace(1)* %out, double addrspace(1)* %in) { - %1 = load double, double addrspace(1)* %in - store double %1, double addrspace(1)* %out - ret void -} - -; CHECK-LABEL: {{^}}load_i64: -; CHECK: buffer_load_dwordx2 v[{{[0-9]+:[0-9]+}}] -; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] -define void @load_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { - %tmp = load i64, i64 addrspace(1)* %in - store i64 %tmp, i64 addrspace(1)* %out, align 8 - ret void -} - -; Load a f64 value from the constant address space. -; CHECK-LABEL: {{^}}load_const_addrspace_f64: -; CHECK: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}] -; CHECK: buffer_store_dwordx2 v[{{[0-9]+:[0-9]+}}] -define void @load_const_addrspace_f64(double addrspace(1)* %out, double addrspace(2)* %in) { - %1 = load double, double addrspace(2)* %in - store double %1, double addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/local-64.ll b/test/CodeGen/AMDGPU/local-64.ll index 33f3159d13eb..f63d6e08ef73 100644 --- a/test/CodeGen/AMDGPU/local-64.ll +++ b/test/CodeGen/AMDGPU/local-64.ll @@ -122,8 +122,7 @@ define void @local_f64_store_0_offset(double addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v2i64_store: ; BOTH-NOT: ADD -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:112 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:120 +; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:15 offset1:14 ; BOTH: s_endpgm define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind { %gep = getelementptr <2 x i64>, <2 x i64> addrspace(3)* %out, i32 7 @@ -133,8 +132,7 @@ define void @local_v2i64_store(<2 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v2i64_store_0_offset: ; BOTH-NOT: ADD -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 +; BOTH: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1 ; BOTH: s_endpgm define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind { store <2 x i64> , <2 x i64> addrspace(3)* %out, align 16 @@ -143,10 +141,8 @@ define void @local_v2i64_store_0_offset(<2 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v4i64_store: ; BOTH-NOT: ADD -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:224 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:232 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:240 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:248 +; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:31 offset1:30 +; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:29 offset1:28 ; BOTH: s_endpgm define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind { %gep = getelementptr <4 x i64>, <4 x i64> addrspace(3)* %out, i32 7 @@ -156,10 +152,8 @@ define void @local_v4i64_store(<4 x i64> addrspace(3)* %out) nounwind { ; BOTH-LABEL: {{^}}local_v4i64_store_0_offset: ; BOTH-NOT: ADD -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:8 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:16 -; BOTH-DAG: ds_write_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}} offset:24 +; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:3 offset1:2 +; BOTH-DAG: ds_write2_b64 v{{[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}} offset0:1 ; BOTH: s_endpgm define void @local_v4i64_store_0_offset(<4 x i64> addrspace(3)* %out) nounwind { store <4 x i64> , <4 x i64> addrspace(3)* %out, align 16 diff --git a/test/CodeGen/AMDGPU/local-atomics.ll b/test/CodeGen/AMDGPU/local-atomics.ll index 2aaf977ab903..ce82ff5475bc 100644 --- a/test/CodeGen/AMDGPU/local-atomics.ll +++ b/test/CodeGen/AMDGPU/local-atomics.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=CIVI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32: ; EG: LDS_WRXCHG_RET * -; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 ; GCN: s_load_dword [[SPTR:s[0-9]+]], +; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] ; GCN: buffer_store_dword [[RESULT]], @@ -31,8 +31,8 @@ define void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspac ; XXX - Is it really necessary to load 4 into VGPR? ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32: ; EG: LDS_ADD_RET * -; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 ; GCN: s_load_dword [[SPTR:s[0-9]+]], +; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]] ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]] ; GCN: buffer_store_dword [[RESULT]], @@ -68,35 +68,35 @@ define void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 ad ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32: +; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32: ; EG: LDS_ADD_RET * -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] ; GCN: s_endpgm -define void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_offset: +; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32_offset: ; EG: LDS_ADD_RET * -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16 ; GCN: s_endpgm -define void @lds_atomic_inc_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i32_bad_si_offset: +; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32_bad_si_offset: ; EG: LDS_ADD_RET * -; SI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} -; CIVI: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16 ; GCN: s_endpgm -define void @lds_atomic_inc_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { +define void @lds_atomic_add1_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add @@ -126,23 +126,23 @@ define void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32: +; FUNC-LABEL: {{^}}lds_atomic_sub1_ret_i32: ; EG: LDS_SUB_RET * -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] ; GCN: s_endpgm -define void @lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i32_offset: +; FUNC-LABEL: {{^}}lds_atomic_sub1_ret_i32_offset: ; EG: LDS_SUB_RET * -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_dec_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[NEGONE]] offset:16 +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16 ; GCN: s_endpgm -define void @lds_atomic_dec_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst store i32 %result, i32 addrspace(1)* %out, align 4 @@ -324,7 +324,6 @@ define void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { ret void } -; XXX - Is it really necessary to load 4 into VGPR? ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32: ; GCN: s_load_dword [[SPTR:s[0-9]+]], ; GCN: v_mov_b32_e32 [[DATA:v[0-9]+]], 4 @@ -357,30 +356,30 @@ define void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32: -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] +; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32: +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]] ; GCN: s_endpgm -define void @lds_atomic_inc_noret_i32(i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_offset: -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_inc_u32 v{{[0-9]+}}, [[NEGONE]] offset:16 +; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32_offset: +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]] offset:16 ; GCN: s_endpgm -define void @lds_atomic_inc_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i32_bad_si_offset: -; SI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} -; CIVI: ds_inc_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 +; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32_bad_si_offset: +; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} +; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16 ; GCN: s_endpgm -define void @lds_atomic_inc_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { +define void @lds_atomic_add1_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind { %sub = sub i32 %a, %b %add = add i32 %sub, 4 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add @@ -405,20 +404,20 @@ define void @lds_atomic_sub_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32: -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] +; FUNC-LABEL: {{^}}lds_atomic_sub1_noret_i32: +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] ; GCN: s_endpgm -define void @lds_atomic_dec_noret_i32(i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_noret_i32(i32 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i32_offset: -; GCN: v_mov_b32_e32 [[NEGONE:v[0-9]+]], -1 -; GCN: ds_dec_u32 v{{[0-9]+}}, [[NEGONE]] offset:16 +; FUNC-LABEL: {{^}}lds_atomic_sub1_noret_i32_offset: +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}} +; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] offset:16 ; GCN: s_endpgm -define void @lds_atomic_dec_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind { %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst ret void diff --git a/test/CodeGen/AMDGPU/local-atomics64.ll b/test/CodeGen/AMDGPU/local-atomics64.ll index 0ffa5e751b7d..34be6511a602 100644 --- a/test/CodeGen/AMDGPU/local-atomics64.ll +++ b/test/CodeGen/AMDGPU/local-atomics64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=VI -check-prefix=GCN %s -; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_xchg_ret_i64: ; GCN: ds_wrxchg_rtn_b64 ; GCN: s_endpgm define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -10,7 +10,7 @@ define void @lds_atomic_xchg_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % ret void } -; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_xchg_ret_i64_offset: ; GCN: ds_wrxchg_rtn_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_xchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -20,7 +20,7 @@ define void @lds_atomic_xchg_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac ret void } -; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_add_ret_i64: ; GCN: ds_add_rtn_u64 ; GCN: s_endpgm define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -29,11 +29,11 @@ define void @lds_atomic_add_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_add_ret_i64_offset: -; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9 -; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0 +; GCN-LABEL: {{^}}lds_atomic_add_ret_i64_offset: ; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9 +; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} offset:32 ; GCN: buffer_store_dwordx2 [[RESULT]], @@ -45,29 +45,29 @@ define void @lds_atomic_add_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64: -; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1 -; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1 -; GCN: ds_inc_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; GCN-LABEL: {{^}}lds_atomic_add1_ret_i64: +; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} +; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} +; GCN: ds_add_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: buffer_store_dwordx2 [[RESULT]], ; GCN: s_endpgm -define void @lds_atomic_inc_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_ret_i64_offset: -; GCN: ds_inc_rtn_u64 {{.*}} offset:32 +; GCN-LABEL: {{^}}lds_atomic_add1_ret_i64_offset: +; GCN: ds_add_rtn_u64 {{.*}} offset:32 ; GCN: s_endpgm -define void @lds_atomic_inc_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_sub_ret_i64: ; GCN: ds_sub_rtn_u64 ; GCN: s_endpgm define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -76,7 +76,7 @@ define void @lds_atomic_sub_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_sub_ret_i64_offset: ; GCN: ds_sub_rtn_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_sub_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -86,29 +86,29 @@ define void @lds_atomic_sub_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64: -; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1 -; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1 -; GCN: ds_dec_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; GCN-LABEL: {{^}}lds_atomic_sub1_ret_i64: +; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} +; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} +; GCN: ds_sub_rtn_u64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: buffer_store_dwordx2 [[RESULT]], ; GCN: s_endpgm -define void @lds_atomic_dec_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_ret_i64_offset: -; GCN: ds_dec_rtn_u64 {{.*}} offset:32 +; GCN-LABEL: {{^}}lds_atomic_sub1_ret_i64_offset: +; GCN: ds_sub_rtn_u64 {{.*}} offset:32 ; GCN: s_endpgm -define void @lds_atomic_dec_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst store i64 %result, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_and_ret_i64: ; GCN: ds_and_rtn_b64 ; GCN: s_endpgm define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -117,7 +117,7 @@ define void @lds_atomic_and_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_and_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_and_ret_i64_offset: ; GCN: ds_and_rtn_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_and_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -127,7 +127,7 @@ define void @lds_atomic_and_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_or_ret_i64: ; GCN: ds_or_rtn_b64 ; GCN: s_endpgm define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -136,7 +136,7 @@ define void @lds_atomic_or_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %pt ret void } -; FUNC-LABEL: {{^}}lds_atomic_or_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_or_ret_i64_offset: ; GCN: ds_or_rtn_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_or_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -146,7 +146,7 @@ define void @lds_atomic_or_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace( ret void } -; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_xor_ret_i64: ; GCN: ds_xor_rtn_b64 ; GCN: s_endpgm define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -155,7 +155,7 @@ define void @lds_atomic_xor_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_xor_ret_i64_offset: ; GCN: ds_xor_rtn_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -166,14 +166,14 @@ define void @lds_atomic_xor_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace } ; FIXME: There is no atomic nand instr -; XFUNC-LABEL: {{^}}lds_atomic_nand_ret_i64:uction, so we somehow need to expand this. +; XGCN-LABEL: {{^}}lds_atomic_nand_ret_i64:uction, so we somehow need to expand this. ; define void @lds_atomic_nand_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { ; %result = atomicrmw nand i64 addrspace(3)* %ptr, i32 4 seq_cst ; store i64 %result, i64 addrspace(1)* %out, align 8 ; ret void ; } -; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_min_ret_i64: ; GCN: ds_min_rtn_i64 ; GCN: s_endpgm define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -182,7 +182,7 @@ define void @lds_atomic_min_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_min_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_min_ret_i64_offset: ; GCN: ds_min_rtn_i64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_min_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -192,7 +192,7 @@ define void @lds_atomic_min_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_max_ret_i64: ; GCN: ds_max_rtn_i64 ; GCN: s_endpgm define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -201,7 +201,7 @@ define void @lds_atomic_max_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %p ret void } -; FUNC-LABEL: {{^}}lds_atomic_max_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_max_ret_i64_offset: ; GCN: ds_max_rtn_i64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_max_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -211,7 +211,7 @@ define void @lds_atomic_max_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace ret void } -; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_umin_ret_i64: ; GCN: ds_min_rtn_u64 ; GCN: s_endpgm define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -220,7 +220,7 @@ define void @lds_atomic_umin_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % ret void } -; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_umin_ret_i64_offset: ; GCN: ds_min_rtn_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_umin_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -230,7 +230,7 @@ define void @lds_atomic_umin_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac ret void } -; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64: +; GCN-LABEL: {{^}}lds_atomic_umax_ret_i64: ; GCN: ds_max_rtn_u64 ; GCN: s_endpgm define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -239,7 +239,7 @@ define void @lds_atomic_umax_ret_i64(i64 addrspace(1)* %out, i64 addrspace(3)* % ret void } -; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_umax_ret_i64_offset: ; GCN: ds_max_rtn_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_umax_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspace(3)* %ptr) nounwind { @@ -249,7 +249,7 @@ define void @lds_atomic_umax_ret_i64_offset(i64 addrspace(1)* %out, i64 addrspac ret void } -; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_xchg_noret_i64: ; GCN: ds_wrxchg_rtn_b64 ; GCN: s_endpgm define void @lds_atomic_xchg_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -257,7 +257,7 @@ define void @lds_atomic_xchg_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_xchg_noret_i64_offset: ; GCN: ds_wrxchg_rtn_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_xchg_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -266,7 +266,7 @@ define void @lds_atomic_xchg_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_add_noret_i64: ; GCN: ds_add_u64 ; GCN: s_endpgm define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -274,7 +274,7 @@ define void @lds_atomic_add_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_add_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_add_noret_i64_offset: ; SI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; VI: s_load_dword [[PTR:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x24 ; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 9 @@ -288,26 +288,26 @@ define void @lds_atomic_add_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64: -; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1 -; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1 -; GCN: ds_inc_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64: +; GCN-DAG: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} +; GCN-DAG: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} +; GCN: ds_add_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: s_endpgm -define void @lds_atomic_inc_noret_i64(i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw add i64 addrspace(3)* %ptr, i64 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_inc_noret_i64_offset: -; GCN: ds_inc_u64 {{.*}} offset:32 +; GCN-LABEL: {{^}}lds_atomic_add1_noret_i64_offset: +; GCN: ds_add_u64 {{.*}} offset:32 ; GCN: s_endpgm -define void @lds_atomic_inc_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_add1_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw add i64 addrspace(3)* %gep, i64 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_sub_noret_i64: ; GCN: ds_sub_u64 ; GCN: s_endpgm define void @lds_atomic_sub_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -315,7 +315,7 @@ define void @lds_atomic_sub_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_sub_noret_i64_offset: ; GCN: ds_sub_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_sub_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -324,26 +324,26 @@ define void @lds_atomic_sub_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64: -; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], -1 -; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], -1 -; GCN: ds_dec_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} +; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64: +; GCN: v_mov_b32_e32 v[[LOVDATA:[0-9]+]], 1{{$}} +; GCN: v_mov_b32_e32 v[[HIVDATA:[0-9]+]], 0{{$}} +; GCN: ds_sub_u64 [[VPTR]], v{{\[}}[[LOVDATA]]:[[HIVDATA]]{{\]}} ; GCN: s_endpgm -define void @lds_atomic_dec_noret_i64(i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_noret_i64(i64 addrspace(3)* %ptr) nounwind { %result = atomicrmw sub i64 addrspace(3)* %ptr, i64 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_dec_noret_i64_offset: -; GCN: ds_dec_u64 {{.*}} offset:32 +; GCN-LABEL: {{^}}lds_atomic_sub1_noret_i64_offset: +; GCN: ds_sub_u64 {{.*}} offset:32 ; GCN: s_endpgm -define void @lds_atomic_dec_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { +define void @lds_atomic_sub1_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { %gep = getelementptr i64, i64 addrspace(3)* %ptr, i32 4 %result = atomicrmw sub i64 addrspace(3)* %gep, i64 1 seq_cst ret void } -; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_and_noret_i64: ; GCN: ds_and_b64 ; GCN: s_endpgm define void @lds_atomic_and_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -351,7 +351,7 @@ define void @lds_atomic_and_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_and_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_and_noret_i64_offset: ; GCN: ds_and_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_and_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -360,7 +360,7 @@ define void @lds_atomic_and_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_or_noret_i64: ; GCN: ds_or_b64 ; GCN: s_endpgm define void @lds_atomic_or_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -368,7 +368,7 @@ define void @lds_atomic_or_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_or_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_or_noret_i64_offset: ; GCN: ds_or_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_or_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -377,7 +377,7 @@ define void @lds_atomic_or_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_xor_noret_i64: ; GCN: ds_xor_b64 ; GCN: s_endpgm define void @lds_atomic_xor_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -385,7 +385,7 @@ define void @lds_atomic_xor_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_xor_noret_i64_offset: ; GCN: ds_xor_b64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -395,13 +395,13 @@ define void @lds_atomic_xor_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { } ; FIXME: There is no atomic nand instr -; XFUNC-LABEL: {{^}}lds_atomic_nand_noret_i64:uction, so we somehow need to expand this. +; XGCN-LABEL: {{^}}lds_atomic_nand_noret_i64:uction, so we somehow need to expand this. ; define void @lds_atomic_nand_noret_i64(i64 addrspace(3)* %ptr) nounwind { ; %result = atomicrmw nand i64 addrspace(3)* %ptr, i32 4 seq_cst ; ret void ; } -; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_min_noret_i64: ; GCN: ds_min_i64 ; GCN: s_endpgm define void @lds_atomic_min_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -409,7 +409,7 @@ define void @lds_atomic_min_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_min_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_min_noret_i64_offset: ; GCN: ds_min_i64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_min_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -418,7 +418,7 @@ define void @lds_atomic_min_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_max_noret_i64: ; GCN: ds_max_i64 ; GCN: s_endpgm define void @lds_atomic_max_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -426,7 +426,7 @@ define void @lds_atomic_max_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_max_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_max_noret_i64_offset: ; GCN: ds_max_i64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_max_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -435,7 +435,7 @@ define void @lds_atomic_max_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_umin_noret_i64: ; GCN: ds_min_u64 ; GCN: s_endpgm define void @lds_atomic_umin_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -443,7 +443,7 @@ define void @lds_atomic_umin_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_umin_noret_i64_offset: ; GCN: ds_min_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_umin_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { @@ -452,7 +452,7 @@ define void @lds_atomic_umin_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64: +; GCN-LABEL: {{^}}lds_atomic_umax_noret_i64: ; GCN: ds_max_u64 ; GCN: s_endpgm define void @lds_atomic_umax_noret_i64(i64 addrspace(3)* %ptr) nounwind { @@ -460,7 +460,7 @@ define void @lds_atomic_umax_noret_i64(i64 addrspace(3)* %ptr) nounwind { ret void } -; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i64_offset: +; GCN-LABEL: {{^}}lds_atomic_umax_noret_i64_offset: ; GCN: ds_max_u64 {{.*}} offset:32 ; GCN: s_endpgm define void @lds_atomic_umax_noret_i64_offset(i64 addrspace(3)* %ptr) nounwind { diff --git a/test/CodeGen/AMDGPU/local-memory-two-objects.ll b/test/CodeGen/AMDGPU/local-memory-two-objects.ll deleted file mode 100644 index 6b52b80ba082..000000000000 --- a/test/CodeGen/AMDGPU/local-memory-two-objects.ll +++ /dev/null @@ -1,63 +0,0 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s -; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI %s -; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=CI %s - -@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 -@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 - - -; Check that the LDS size emitted correctly -; EG: .long 166120 -; EG-NEXT: .long 8 -; GCN: .long 47180 -; GCN-NEXT: .long 32900 - -; EG: {{^}}local_memory_two_objects: - -; We would like to check the lds writes are using different -; addresses, but due to variations in the scheduler, we can't do -; this consistently on evergreen GPUs. -; EG: LDS_WRITE -; EG: LDS_WRITE -; GCN: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]] -; GCN-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]] - -; GROUP_BARRIER must be the last instruction in a clause -; EG: GROUP_BARRIER -; EG-NEXT: ALU clause - -; Make sure the lds reads are using different addresses, at different -; constant offsets. -; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] -; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] -; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], vcc, 16, v{{[0-9]+}} -; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]] -; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16 -; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]] - -define void @local_memory_two_objects(i32 addrspace(1)* %out) { -entry: - %x.i = call i32 @llvm.r600.read.tidig.x() #0 - %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i - store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 - %mul = shl nsw i32 %x.i, 1 - %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i - store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 - %sub = sub nsw i32 3, %x.i - call void @llvm.AMDGPU.barrier.local() - %arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub - %0 = load i32, i32 addrspace(3)* %arrayidx2, align 4 - %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i - store i32 %0, i32 addrspace(1)* %arrayidx3, align 4 - %arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub - %1 = load i32, i32 addrspace(3)* %arrayidx4, align 4 - %add = add nsw i32 %x.i, 4 - %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add - store i32 %1, i32 addrspace(1)* %arrayidx5, align 4 - ret void -} - -declare i32 @llvm.r600.read.tidig.x() #0 -declare void @llvm.AMDGPU.barrier.local() - -attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/local-memory.amdgcn.ll b/test/CodeGen/AMDGPU/local-memory.amdgcn.ll new file mode 100644 index 000000000000..f6c0e3c62390 --- /dev/null +++ b/test/CodeGen/AMDGPU/local-memory.amdgcn.ll @@ -0,0 +1,92 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s + +@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 + +; Check that the LDS size emitted correctly +; SI: .long 47180 +; SI-NEXT: .long 65668 +; CI: .long 47180 +; CI-NEXT: .long 32900 + +; GCN-LABEL: {{^}}local_memory: + +; GCN-NOT: s_wqm_b64 +; GCN: ds_write_b32 + +; GCN: s_barrier + +; GCN: ds_read_b32 {{v[0-9]+}}, +define void @local_memory(i32 addrspace(1)* %out) #0 { +entry: + %y.i = call i32 @llvm.amdgcn.workitem.id.x() #1 + %arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i + store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4 + %add = add nsw i32 %y.i, 1 + %cmp = icmp eq i32 %add, 16 + %.add = select i1 %cmp, i32 0, i32 %add + call void @llvm.amdgcn.s.barrier() + %arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add + %tmp = load i32, i32 addrspace(3)* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i + store i32 %tmp, i32 addrspace(1)* %arrayidx2, align 4 + ret void +} + +@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 +@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 + +; Check that the LDS size emitted correctly +; EG: .long 166120 +; EG-NEXT: .long 8 +; GCN: .long 47180 +; GCN-NEXT: .long 32900 + +; GCN-LABEL: {{^}}local_memory_two_objects: +; GCN: v_lshlrev_b32_e32 [[ADDRW:v[0-9]+]], 2, v0 +; CI-DAG: ds_write_b32 [[ADDRW]], {{v[0-9]*}} offset:16 +; CI-DAG: ds_write_b32 [[ADDRW]], {{v[0-9]*$}} + +; SI: v_add_i32_e32 [[ADDRW_OFF:v[0-9]+]], vcc, 16, [[ADDRW]] + +; SI-DAG: ds_write_b32 [[ADDRW]], +; SI-DAG: ds_write_b32 [[ADDRW_OFF]], + +; GCN: s_barrier + +; SI-DAG: v_sub_i32_e32 [[SUB0:v[0-9]+]], vcc, 28, [[ADDRW]] +; SI-DAG: v_sub_i32_e32 [[SUB1:v[0-9]+]], vcc, 12, [[ADDRW]] + +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB0]] +; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB1]] + +; CI: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, 0, [[ADDRW]] +; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, [[SUB]] offset0:3 offset1:7 +define void @local_memory_two_objects(i32 addrspace(1)* %out) #0 { +entry: + %x.i = call i32 @llvm.amdgcn.workitem.id.x() + %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i + store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 + %mul = shl nsw i32 %x.i, 1 + %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i + store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 + %sub = sub nsw i32 3, %x.i + call void @llvm.amdgcn.s.barrier() + %arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub + %tmp = load i32, i32 addrspace(3)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i + store i32 %tmp, i32 addrspace(1)* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub + %tmp1 = load i32, i32 addrspace(3)* %arrayidx4, align 4 + %add = add nsw i32 %x.i, 4 + %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add + store i32 %tmp1, i32 addrspace(1)* %arrayidx5, align 4 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 +declare void @llvm.amdgcn.s.barrier() #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/local-memory.ll b/test/CodeGen/AMDGPU/local-memory.ll index 9ffb59e70920..1a11332f865d 100644 --- a/test/CodeGen/AMDGPU/local-memory.ll +++ b/test/CodeGen/AMDGPU/local-memory.ll @@ -1,49 +1,44 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s @local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 +@lds = addrspace(3) global [512 x i32] undef, align 4 -; Check that the LDS size emitted correctly -; EG: .long 166120 -; EG-NEXT: .long 128 -; SI: .long 47180 -; SI-NEXT: .long 65668 -; CI: .long 47180 -; CI-NEXT: .long 32900 +; On SI we need to make sure that the base offset is a register and +; not an immediate. -; FUNC-LABEL: {{^}}local_memory: +; FUNC-LABEL: {{^}}load_i32_local_const_ptr: +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0 +; GCN: ds_read_b32 v{{[0-9]+}}, v[[ZERO]] offset:4 -; EG: LDS_WRITE -; SI-NOT: s_wqm_b64 -; SI: ds_write_b32 - -; GROUP_BARRIER must be the last instruction in a clause -; EG: GROUP_BARRIER -; EG-NEXT: ALU clause -; SI: s_barrier - -; EG: LDS_READ_RET -; SI: ds_read_b32 {{v[0-9]+}}, - -define void @local_memory(i32 addrspace(1)* %out) { +; R600: LDS_READ_RET +define void @load_i32_local_const_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %in) #0 { entry: - %y.i = call i32 @llvm.r600.read.tidig.x() #0 - %arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i - store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4 - %add = add nsw i32 %y.i, 1 - %cmp = icmp eq i32 %add, 16 - %.add = select i1 %cmp, i32 0, i32 %add - call void @llvm.AMDGPU.barrier.local() - %arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add - %0 = load i32, i32 addrspace(3)* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i - store i32 %0, i32 addrspace(1)* %arrayidx2, align 4 + %tmp0 = getelementptr [512 x i32], [512 x i32] addrspace(3)* @lds, i32 0, i32 1 + %tmp1 = load i32, i32 addrspace(3)* %tmp0 + %tmp2 = getelementptr i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp1, i32 addrspace(1)* %tmp2 ret void } -declare i32 @llvm.r600.read.tidig.x() #0 -declare void @llvm.AMDGPU.barrier.local() +; Test loading a i32 and v2i32 value from the same base pointer. +; FUNC-LABEL: {{^}}load_i32_v2i32_local: +; R600: LDS_READ_RET +; R600: LDS_READ_RET +; R600: LDS_READ_RET +; GCN-DAG: ds_read_b32 +; GCN-DAG: ds_read2_b32 +define void @load_i32_v2i32_local(<2 x i32> addrspace(1)* %out, i32 addrspace(3)* %in) #0 { + %scalar = load i32, i32 addrspace(3)* %in + %tmp0 = bitcast i32 addrspace(3)* %in to <2 x i32> addrspace(3)* + %vec_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(3)* %tmp0, i32 2 + %vec0 = load <2 x i32>, <2 x i32> addrspace(3)* %vec_ptr, align 4 + %vec1 = insertelement <2 x i32> , i32 %scalar, i32 0 + %vec = add <2 x i32> %vec0, %vec1 + store <2 x i32> %vec, <2 x i32> addrspace(1)* %out + ret void +} -attributes #0 = { readnone } +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/local-memory.r600.ll b/test/CodeGen/AMDGPU/local-memory.r600.ll new file mode 100644 index 000000000000..9841b8882b39 --- /dev/null +++ b/test/CodeGen/AMDGPU/local-memory.r600.ll @@ -0,0 +1,87 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4 + +; Check that the LDS size emitted correctly +; EG: .long 166120 +; EG-NEXT: .long 128 + +; FUNC-LABEL: {{^}}local_memory: + +; EG: LDS_WRITE + +; GROUP_BARRIER must be the last instruction in a clause +; EG: GROUP_BARRIER +; EG-NEXT: ALU clause + +; EG: LDS_READ_RET +define void @local_memory(i32 addrspace(1)* %out) #0 { +entry: + %y.i = call i32 @llvm.r600.read.tidig.x() #1 + %arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i + store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4 + %add = add nsw i32 %y.i, 1 + %cmp = icmp eq i32 %add, 16 + %.add = select i1 %cmp, i32 0, i32 %add + call void @llvm.r600.group.barrier() + %arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add + %tmp = load i32, i32 addrspace(3)* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i + store i32 %tmp, i32 addrspace(1)* %arrayidx2, align 4 + ret void +} + +@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 +@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4 + +; Check that the LDS size emitted correctly +; EG: .long 166120 +; EG-NEXT: .long 8 +; GCN: .long 47180 +; GCN-NEXT: .long 32900 + +; FUNC-LABEL: {{^}}local_memory_two_objects: + +; We would like to check the lds writes are using different +; addresses, but due to variations in the scheduler, we can't do +; this consistently on evergreen GPUs. +; EG: LDS_WRITE +; EG: LDS_WRITE + +; GROUP_BARRIER must be the last instruction in a clause +; EG: GROUP_BARRIER +; EG-NEXT: ALU clause + +; Make sure the lds reads are using different addresses, at different +; constant offsets. +; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]] +; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]] + +define void @local_memory_two_objects(i32 addrspace(1)* %out) #0 { +entry: + %x.i = call i32 @llvm.r600.read.tidig.x() #1 + %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i + store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4 + %mul = shl nsw i32 %x.i, 1 + %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i + store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4 + %sub = sub nsw i32 3, %x.i + call void @llvm.r600.group.barrier() + %arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub + %tmp = load i32, i32 addrspace(3)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i + store i32 %tmp, i32 addrspace(1)* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub + %tmp1 = load i32, i32 addrspace(3)* %arrayidx4, align 4 + %add = add nsw i32 %x.i, 4 + %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add + store i32 %tmp1, i32 addrspace(1)* %arrayidx5, align 4 + ret void +} + +declare i32 @llvm.r600.read.tidig.x() #1 +declare void @llvm.r600.group.barrier() #2 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/local-stack-slot-bug.ll b/test/CodeGen/AMDGPU/local-stack-slot-bug.ll new file mode 100644 index 000000000000..6e6f289f5d6d --- /dev/null +++ b/test/CodeGen/AMDGPU/local-stack-slot-bug.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck %s + +; This used to fail due to a v_add_i32 instruction with an illegal immediate +; operand that was created during Local Stack Slot Allocation. Test case derived +; from https://bugs.freedesktop.org/show_bug.cgi?id=96602 +; +; CHECK-LABEL: {{^}}main: +; CHECK: v_lshlrev_b32_e32 [[BYTES:v[0-9]+]], 2, v0 +; CHECK: v_mov_b32_e32 [[HI_CONST:v[0-9]+]], 0x200 +; CHECK: v_mov_b32_e32 [[LO_CONST:v[0-9]+]], 0 +; CHECK: v_add_i32_e32 [[HI_OFF:v[0-9]+]], vcc, [[BYTES]], [[HI_CONST]] +; CHECK: v_add_i32_e32 [[LO_OFF:v[0-9]+]], vcc, [[BYTES]], [[LO_CONST]] +; CHECK: buffer_load_dword {{v[0-9]+}}, [[LO_OFF]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen +; CHECK: buffer_load_dword {{v[0-9]+}}, [[HI_OFF]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen +define amdgpu_ps float @main(i32 %idx) { +main_body: + %v1 = extractelement <81 x float> , i32 %idx + %v2 = extractelement <81 x float> , i32 %idx + %r = fadd float %v1, %v2 + ret float %r +} diff --git a/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll b/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll new file mode 100644 index 000000000000..e1fad13e0b51 --- /dev/null +++ b/test/CodeGen/AMDGPU/lower-range-metadata-intrinsic-call.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-unknown < %s | FileCheck %s + +; and can be eliminated +; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range: +; CHECK-NOT: v0 +; CHECK: {{flat|buffer}}_store_dword {{.*}}v0 +define void @test_workitem_id_x_known_max_range(i32 addrspace(1)* nocapture %out) #0 { +entry: + %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0 + %and = and i32 %id, 1023 + store i32 %and, i32 addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: {{^}}test_workitem_id_x_known_trunc_1_bit_range: +; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x1ff, v0 +; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]] +define void @test_workitem_id_x_known_trunc_1_bit_range(i32 addrspace(1)* nocapture %out) #0 { +entry: + %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0 + %and = and i32 %id, 511 + store i32 %and, i32 addrspace(1)* %out, align 4 + ret void +} + +; CHECK-LABEL: {{^}}test_workitem_id_x_known_max_range_m1: +; CHECK-NOT: v0 +; CHECK: v_and_b32_e32 [[MASKED:v[0-9]+]], 0xff, v0 +; CHECK: {{flat|buffer}}_store_dword {{.*}}[[MASKED]] +define void @test_workitem_id_x_known_max_range_m1(i32 addrspace(1)* nocapture %out) #0 { +entry: + %id = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !1 + %and = and i32 %id, 255 + store i32 %and, i32 addrspace(1)* %out, align 4 + ret void +} + + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { norecurse nounwind } +attributes #1 = { nounwind readnone } + +!0 = !{i32 0, i32 1024} +!1 = !{i32 0, i32 1023} diff --git a/test/CodeGen/AMDGPU/m0-spill.ll b/test/CodeGen/AMDGPU/m0-spill.ll index 1dddc85f775d..2427c8de34f8 100644 --- a/test/CodeGen/AMDGPU/m0-spill.ll +++ b/test/CodeGen/AMDGPU/m0-spill.ll @@ -5,7 +5,7 @@ ; CHECK-LABEL: {{^}}main: ; CHECK-NOT: v_readlane_b32 m0 -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" { +define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) { main_body: %4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3) %cmp = fcmp ueq float 0.0, %4 diff --git a/test/CodeGen/AMDGPU/mad-combine.ll b/test/CodeGen/AMDGPU/mad-combine.ll index c98f851f2b93..0e6281940c24 100644 --- a/test/CodeGen/AMDGPU/mad-combine.ll +++ b/test/CodeGen/AMDGPU/mad-combine.ll @@ -8,7 +8,7 @@ ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=SI-DENORM-SLOWFMAF -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 declare float @llvm.fabs.f32(float) #0 declare float @llvm.fma.f32(float, float, float) #0 declare float @llvm.fmuladd.f32(float, float, float) #0 @@ -32,15 +32,15 @@ declare float @llvm.fmuladd.f32(float, float, float) #0 ; SI-DENORM: buffer_store_dword [[RESULT]] ; SI-STD: buffer_store_dword [[C]] define void @combine_to_mad_f32_0(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %mul = fmul float %a, %b %fma = fadd float %mul, %c @@ -71,7 +71,7 @@ define void @combine_to_mad_f32_0(float addrspace(1)* noalias %out, float addrsp ; SI-STD-DAG: buffer_store_dword [[D]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI: s_endpgm define void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -79,17 +79,17 @@ define void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float a %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 - %d = load float, float addrspace(1)* %gep.3 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 + %d = load volatile float, float addrspace(1)* %gep.3 %mul = fmul float %a, %b %fma0 = fadd float %mul, %c %fma1 = fadd float %mul, %d - store float %fma0, float addrspace(1)* %gep.out.0 - store float %fma1, float addrspace(1)* %gep.out.1 + store volatile float %fma0, float addrspace(1)* %gep.out.0 + store volatile float %fma1, float addrspace(1)* %gep.out.1 ret void } @@ -108,15 +108,15 @@ define void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float a ; SI-DENORM: buffer_store_dword [[RESULT]] ; SI-STD: buffer_store_dword [[C]] define void @combine_to_mad_f32_1(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %mul = fmul float %a, %b %fma = fadd float %c, %mul @@ -138,15 +138,15 @@ define void @combine_to_mad_f32_1(float addrspace(1)* noalias %out, float addrsp ; SI: buffer_store_dword [[RESULT]] define void @combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %mul = fmul float %a, %b %fma = fsub float %mul, %c @@ -175,7 +175,7 @@ define void @combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float a ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI: s_endpgm define void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -183,16 +183,16 @@ define void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, fl %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 - %d = load float, float addrspace(1)* %gep.3 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 + %d = load volatile float, float addrspace(1)* %gep.3 %mul = fmul float %a, %b %fma0 = fsub float %mul, %c %fma1 = fsub float %mul, %d - store float %fma0, float addrspace(1)* %gep.out.0 - store float %fma1, float addrspace(1)* %gep.out.1 + store volatile float %fma0, float addrspace(1)* %gep.out.0 + store volatile float %fma1, float addrspace(1)* %gep.out.1 ret void } @@ -210,15 +210,15 @@ define void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, fl ; SI: buffer_store_dword [[RESULT]] define void @combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %mul = fmul float %a, %b %fma = fsub float %c, %mul @@ -246,7 +246,7 @@ define void @combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float a ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI: s_endpgm define void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -254,16 +254,16 @@ define void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, fl %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 - %d = load float, float addrspace(1)* %gep.3 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 + %d = load volatile float, float addrspace(1)* %gep.3 %mul = fmul float %a, %b %fma0 = fsub float %c, %mul %fma1 = fsub float %d, %mul - store float %fma0, float addrspace(1)* %gep.out.0 - store float %fma1, float addrspace(1)* %gep.out.1 + store volatile float %fma0, float addrspace(1)* %gep.out.0 + store volatile float %fma1, float addrspace(1)* %gep.out.1 ret void } @@ -282,15 +282,15 @@ define void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, fl ; SI: buffer_store_dword [[RESULT]] define void @combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %mul = fmul float %a, %b %mul.neg = fsub float -0.0, %mul @@ -320,7 +320,7 @@ define void @combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float a ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI: s_endpgm define void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -328,18 +328,18 @@ define void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %ou %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 - %d = load float, float addrspace(1)* %gep.3 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 + %d = load volatile float, float addrspace(1)* %gep.3 %mul = fmul float %a, %b %mul.neg = fsub float -0.0, %mul %fma0 = fsub float %mul.neg, %c %fma1 = fsub float %mul.neg, %d - store float %fma0, float addrspace(1)* %gep.out.0 - store float %fma1, float addrspace(1)* %gep.out.1 + store volatile float %fma0, float addrspace(1)* %gep.out.0 + store volatile float %fma1, float addrspace(1)* %gep.out.1 ret void } @@ -363,7 +363,7 @@ define void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %ou ; SI-DAG: buffer_store_dword [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI: s_endpgm define void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -371,18 +371,18 @@ define void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %ou %gep.out.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out.1 = getelementptr float, float addrspace(1)* %gep.out.0, i32 1 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 - %d = load float, float addrspace(1)* %gep.3 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 + %d = load volatile float, float addrspace(1)* %gep.3 %mul = fmul float %a, %b %mul.neg = fsub float -0.0, %mul %fma0 = fsub float %mul.neg, %c %fma1 = fsub float %mul, %d - store float %fma0, float addrspace(1)* %gep.out.0 - store float %fma1, float addrspace(1)* %gep.out.1 + store volatile float %fma0, float addrspace(1)* %gep.out.0 + store volatile float %fma1, float addrspace(1)* %gep.out.1 ret void } @@ -408,7 +408,7 @@ define void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %ou ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} define void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -416,11 +416,11 @@ define void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %o %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 - %z = load float, float addrspace(1)* %gep.2 - %u = load float, float addrspace(1)* %gep.3 - %v = load float, float addrspace(1)* %gep.4 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 + %z = load volatile float, float addrspace(1)* %gep.2 + %u = load volatile float, float addrspace(1)* %gep.3 + %v = load volatile float, float addrspace(1)* %gep.4 %tmp0 = fmul float %u, %v %tmp1 = call float @llvm.fma.f32(float %x, float %y, float %tmp0) #0 @@ -454,7 +454,7 @@ define void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %o ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: s_endpgm define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -462,11 +462,11 @@ define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %o %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 - %z = load float, float addrspace(1)* %gep.2 - %u = load float, float addrspace(1)* %gep.3 - %v = load float, float addrspace(1)* %gep.4 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 + %z = load volatile float, float addrspace(1)* %gep.2 + %u = load volatile float, float addrspace(1)* %gep.3 + %v = load volatile float, float addrspace(1)* %gep.4 %tmp0 = fmul float %u, %v %tmp1 = call float @llvm.fma.f32(float %y, float %z, float %tmp0) #0 @@ -491,8 +491,8 @@ define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %o ; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], [[D]], [[E]], -[[C]] ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[TMP]] -; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]] -; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]] +; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]] +; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[B]], [[A]] ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]] ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP2]] @@ -500,7 +500,7 @@ define void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %o ; SI-STD: buffer_store_dword [[TMP]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: s_endpgm define void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -508,11 +508,11 @@ define void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %o %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 - %z = load float, float addrspace(1)* %gep.2 - %u = load float, float addrspace(1)* %gep.3 - %v = load float, float addrspace(1)* %gep.4 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 + %z = load volatile float, float addrspace(1)* %gep.2 + %u = load volatile float, float addrspace(1)* %gep.3 + %v = load volatile float, float addrspace(1)* %gep.4 %tmp0 = fmul float %u, %v %tmp1 = call float @llvm.fmuladd.f32(float %x, float %y, float %tmp0) #0 @@ -538,15 +538,15 @@ define void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %o ; SI-DENORM: v_fma_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]] ; SI-DENORM: v_fma_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]] -; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]] -; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[C]], [[B]] +; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[E]], [[D]] +; SI-DENORM-SLOWFMAF-DAG: v_mul_f32_e32 [[TMP1:v[0-9]+]], [[C]], [[B]] ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[TMP2:v[0-9]+]], [[TMP0]], [[TMP1]] ; SI-DENORM-SLOWFMAF: v_subrev_f32_e32 [[RESULT:v[0-9]+]], [[TMP2]], [[A]] ; SI: buffer_store_dword [[RESULT]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI: s_endpgm define void @aggressive_combine_to_mad_fsub_3_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 @@ -554,11 +554,11 @@ define void @aggressive_combine_to_mad_fsub_3_f32(float addrspace(1)* noalias %o %gep.4 = getelementptr float, float addrspace(1)* %gep.0, i32 4 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %x = load float, float addrspace(1)* %gep.0 - %y = load float, float addrspace(1)* %gep.1 - %z = load float, float addrspace(1)* %gep.2 - %u = load float, float addrspace(1)* %gep.3 - %v = load float, float addrspace(1)* %gep.4 + %x = load volatile float, float addrspace(1)* %gep.0 + %y = load volatile float, float addrspace(1)* %gep.1 + %z = load volatile float, float addrspace(1)* %gep.2 + %u = load volatile float, float addrspace(1)* %gep.3 + %v = load volatile float, float addrspace(1)* %gep.4 %tmp0 = fmul float %u, %v %tmp1 = call float @llvm.fmuladd.f32(float %y, float %z, float %tmp0) #0 diff --git a/test/CodeGen/AMDGPU/mad-sub.ll b/test/CodeGen/AMDGPU/mad-sub.ll index 24ff23a4cfc1..7fcfe7f53f06 100644 --- a/test/CodeGen/AMDGPU/mad-sub.ll +++ b/test/CodeGen/AMDGPU/mad-sub.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 declare float @llvm.fabs.f32(float) #0 ; FUNC-LABEL: {{^}}mad_sub_f32: @@ -10,7 +10,7 @@ declare float @llvm.fabs.f32(float) #0 ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -[[REGC]] ; SI: buffer_store_dword [[RESULT]] define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -18,9 +18,9 @@ define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrs %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %mul = fmul float %a, %b %sub = fsub float %mul, %c store float %sub, float addrspace(1)* %outgep, align 4 @@ -34,7 +34,7 @@ define void @mad_sub_f32(float addrspace(1)* noalias nocapture %out, float addrs ; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], [[REGC]] ; SI: buffer_store_dword [[RESULT]] define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -42,9 +42,9 @@ define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float a %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %mul = fmul float %a, %b %sub = fsub float %c, %mul store float %sub, float addrspace(1)* %outgep, align 4 @@ -55,7 +55,7 @@ define void @mad_sub_inv_f32(float addrspace(1)* noalias nocapture %out, float a ; SI: v_mul_f64 ; SI: v_add_f64 define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr double, double addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -63,9 +63,9 @@ define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double add %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr double, double addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr double, double addrspace(1)* %out, i64 %tid.ext - %a = load double, double addrspace(1)* %gep0, align 8 - %b = load double, double addrspace(1)* %gep1, align 8 - %c = load double, double addrspace(1)* %gep2, align 8 + %a = load volatile double, double addrspace(1)* %gep0, align 8 + %b = load volatile double, double addrspace(1)* %gep1, align 8 + %c = load volatile double, double addrspace(1)* %gep2, align 8 %mul = fmul double %a, %b %sub = fsub double %mul, %c store double %sub, double addrspace(1)* %outgep, align 8 @@ -79,7 +79,7 @@ define void @mad_sub_f64(double addrspace(1)* noalias nocapture %out, double add ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], [[REGB]], -|[[REGC]]| ; SI: buffer_store_dword [[RESULT]] define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -87,9 +87,9 @@ define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %c.abs = call float @llvm.fabs.f32(float %c) #0 %mul = fmul float %a, %b %sub = fsub float %mul, %c.abs @@ -104,7 +104,7 @@ define void @mad_sub_fabs_f32(float addrspace(1)* noalias nocapture %out, float ; SI: v_mad_f32 [[RESULT:v[0-9]+]], -[[REGA]], [[REGB]], |[[REGC]]| ; SI: buffer_store_dword [[RESULT]] define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -112,9 +112,9 @@ define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, fl %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %c.abs = call float @llvm.fabs.f32(float %c) #0 %mul = fmul float %a, %b %sub = fsub float %c.abs, %mul @@ -125,7 +125,7 @@ define void @mad_sub_fabs_inv_f32(float addrspace(1)* noalias nocapture %out, fl ; FUNC-LABEL: {{^}}neg_neg_mad_f32: ; SI: v_mac_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -133,9 +133,9 @@ define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float a %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %nega = fsub float -0.000000e+00, %a %negb = fsub float -0.000000e+00, %b %mul = fmul float %nega, %negb @@ -151,7 +151,7 @@ define void @neg_neg_mad_f32(float addrspace(1)* noalias nocapture %out, float a ; SI: v_mad_f32 [[RESULT:v[0-9]+]], [[REGA]], |[[REGB]]|, -[[REGC]] ; SI: buffer_store_dword [[RESULT]] define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float addrspace(1)* noalias nocapture readonly %ptr) #1 { - %tid = tail call i32 @llvm.r600.read.tidig.x() #0 + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid.ext = sext i32 %tid to i64 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 %tid.ext %add1 = add i64 %tid.ext, 1 @@ -159,9 +159,9 @@ define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float %add2 = add i64 %tid.ext, 2 %gep2 = getelementptr float, float addrspace(1)* %ptr, i64 %add2 %outgep = getelementptr float, float addrspace(1)* %out, i64 %tid.ext - %a = load float, float addrspace(1)* %gep0, align 4 - %b = load float, float addrspace(1)* %gep1, align 4 - %c = load float, float addrspace(1)* %gep2, align 4 + %a = load volatile float, float addrspace(1)* %gep0, align 4 + %b = load volatile float, float addrspace(1)* %gep1, align 4 + %c = load volatile float, float addrspace(1)* %gep2, align 4 %b.abs = call float @llvm.fabs.f32(float %b) #0 %mul = fmul float %a, %b.abs %sub = fsub float %mul, %c @@ -175,13 +175,13 @@ define void @mad_fabs_sub_f32(float addrspace(1)* noalias nocapture %out, float ; SI: v_mac_f32_e32 [[R2]], -2.0, [[R1]] ; SI: buffer_store_dword [[R2]] define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %add = fadd float %r1, %r1 %r3 = fsub float %r2, %add @@ -196,13 +196,13 @@ define void @fsub_c_fadd_a_a(float addrspace(1)* %out, float addrspace(1)* %in) ; SI: v_mad_f32 [[RESULT:v[0-9]+]], 2.0, [[R1]], -[[R2]] ; SI: buffer_store_dword [[RESULT]] define void @fsub_fadd_a_a_c(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid - %r1 = load float, float addrspace(1)* %gep.0 - %r2 = load float, float addrspace(1)* %gep.1 + %r1 = load volatile float, float addrspace(1)* %gep.0 + %r2 = load volatile float, float addrspace(1)* %gep.1 %add = fadd float %r1, %r1 %r3 = fsub float %add, %r2 diff --git a/test/CodeGen/AMDGPU/mad24-get-global-id.ll b/test/CodeGen/AMDGPU/mad24-get-global-id.ll new file mode 100644 index 000000000000..9183ae0972dc --- /dev/null +++ b/test/CodeGen/AMDGPU/mad24-get-global-id.ll @@ -0,0 +1,36 @@ +; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; If the workgroup id range is restricted, we should be able to use +; mad24 for the usual indexing pattern. + +declare i32 @llvm.amdgcn.workgroup.id.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 + +; GCN-LABEL: {{^}}get_global_id_0: +; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff +; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]] +; GCN: v_mad_u32_u24 v{{[0-9]+}}, [[VWGSIZEX]], s8, v0 +define void @get_global_id_0(i32 addrspace(1)* %out) #1 { + %dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() + %cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* + %gep = getelementptr inbounds i32, i32 addrspace(2)* %cast.dispatch.ptr, i64 1 + %workgroup.size.xy = load i32, i32 addrspace(2)* %gep, align 4, !invariant.load !0 + %workgroup.size.x = and i32 %workgroup.size.xy, 65535 + + %workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1 + %workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2 + + %mul = mul i32 %workgroup.id.x, %workgroup.size.x + %add = add i32 %mul, %workitem.id.x + + store i32 %add, i32 addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + +!0 = !{} +!1 = !{i32 0, i32 1024} +!2 = !{i32 0, i32 16777216} diff --git a/test/CodeGen/AMDGPU/mad_int24.ll b/test/CodeGen/AMDGPU/mad_int24.ll index 86d75a63ca40..f177608a62fc 100644 --- a/test/CodeGen/AMDGPU/mad_int24.ll +++ b/test/CodeGen/AMDGPU/mad_int24.ll @@ -1,9 +1,7 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC - -declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone ; FUNC-LABEL: {{^}}i32_mad24: ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. @@ -24,12 +22,3 @@ entry: store i32 %3, i32 addrspace(1)* %out ret void } - -; FUNC-LABEL: @test_imul24 -; SI: v_mad_i32_i24 -define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind { - %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone - %add = add i32 %mul, %src2 - store i32 %add, i32 addrspace(1)* %out, align 4 - ret void -} diff --git a/test/CodeGen/AMDGPU/mad_uint24.ll b/test/CodeGen/AMDGPU/mad_uint24.ll index 95fe34119596..72c6b2b26173 100644 --- a/test/CodeGen/AMDGPU/mad_uint24.ll +++ b/test/CodeGen/AMDGPU/mad_uint24.ll @@ -1,7 +1,7 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; FUNC-LABEL: {{^}}u32_mad24: ; EG: MULADD_UINT24 diff --git a/test/CodeGen/AMDGPU/madak.ll b/test/CodeGen/AMDGPU/madak.ll index 2e90cf10a3b5..6ea1202ac500 100644 --- a/test/CodeGen/AMDGPU/madak.ll +++ b/test/CodeGen/AMDGPU/madak.ll @@ -3,7 +3,7 @@ ; FIXME: Enable VI -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare float @llvm.fabs.f32(float) nounwind readnone ; GCN-LABEL: {{^}}madak_f32: @@ -11,7 +11,7 @@ declare float @llvm.fabs.f32(float) nounwind readnone ; GCN: buffer_load_dword [[VB:v[0-9]+]] ; GCN: v_madak_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -38,7 +38,7 @@ define void @madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noa ; GCN-DAG: v_mac_f32_e32 [[VK]], [[VC]], [[VA]] ; GCN: s_endpgm define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 @@ -47,17 +47,17 @@ define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %a = load float, float addrspace(1)* %in.gep.0, align 4 - %b = load float, float addrspace(1)* %in.gep.1, align 4 - %c = load float, float addrspace(1)* %in.gep.2, align 4 + %a = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %b = load volatile float, float addrspace(1)* %in.gep.1, align 4 + %c = load volatile float, float addrspace(1)* %in.gep.2, align 4 %mul0 = fmul float %a, %b %mul1 = fmul float %a, %c %madak0 = fadd float %mul0, 10.0 %madak1 = fadd float %mul1, 10.0 - store float %madak0, float addrspace(1)* %out.gep.0, align 4 - store float %madak1, float addrspace(1)* %out.gep.1, align 4 + store volatile float %madak0, float addrspace(1)* %out.gep.0, align 4 + store volatile float %madak1, float addrspace(1)* %out.gep.1, align 4 ret void } @@ -65,7 +65,7 @@ define void @madak_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1 ; GCN: buffer_load_dword [[VA:v[0-9]+]] ; GCN: v_madak_f32_e32 {{v[0-9]+}}, 4.0, [[VA]], 0x41200000 define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -85,7 +85,7 @@ define void @madak_m_inline_imm_f32(float addrspace(1)* noalias %out, float addr ; GCN: buffer_load_dword [[VB:v[0-9]+]] ; GCN: v_mad_f32 {{v[0-9]+}}, [[VA]], [[VB]], 4.0 define void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -101,13 +101,13 @@ define void @madak_inline_imm_f32(float addrspace(1)* noalias %out, float addrsp ; We can't use an SGPR when forming madak ; GCN-LABEL: {{^}}s_v_madak_f32: -; GCN: s_load_dword [[SB:s[0-9]+]] +; GCN-DAG: s_load_dword [[SB:s[0-9]+]] ; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]] ; GCN-NOT: v_madak_f32 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]] define void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float %b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -126,7 +126,7 @@ define void @s_v_madak_f32(float addrspace(1)* noalias %out, float addrspace(1)* ; GCN-NOT: v_madak_f32 ; GCN: v_mac_f32_e32 [[VK]], [[SB]], [[VA]] define void @v_s_madak_f32(float addrspace(1)* noalias %out, float %a, float addrspace(1)* noalias %in.b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -154,7 +154,7 @@ define void @s_s_madak_f32(float addrspace(1)* %out, float %a, float %b) nounwin ; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}} ; GCN: s_endpgm define void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -176,7 +176,7 @@ define void @no_madak_src0_modifier_f32(float addrspace(1)* noalias %out, float ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, |{{v[0-9]+}}|, {{[sv][0-9]+}} ; GCN: s_endpgm define void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in.a, float addrspace(1)* noalias %in.b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.a.gep = getelementptr float, float addrspace(1)* %in.a, i32 %tid %in.b.gep = getelementptr float, float addrspace(1)* %in.b, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -191,3 +191,32 @@ define void @no_madak_src1_modifier_f32(float addrspace(1)* noalias %out, float store float %madak, float addrspace(1)* %out.gep, align 4 ret void } + +; SIFoldOperands should not fold the SGPR copy into the instruction +; because the implicit immediate already uses the constant bus. +; GCN-LABEL: {{^}}madak_constant_bus_violation: +; GCN: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, {{0xa|0x28}} +; GCN: v_mov_b32_e32 [[SGPR0_VCOPY:v[0-9]+]], [[SGPR0]] +; GCN: buffer_load_dword [[VGPR:v[0-9]+]] +; GCN: v_madak_f32_e32 [[MADAK:v[0-9]+]], 0.5, [[SGPR0_VCOPY]], 0x42280000 +; GCN: v_mul_f32_e32 [[MUL:v[0-9]+]], [[VGPR]], [[MADAK]] +; GCN: buffer_store_dword [[MUL]] +define void @madak_constant_bus_violation(i32 %arg1, float %sgpr0, float %sgpr1) #0 { +bb: + %tmp = icmp eq i32 %arg1, 0 + br i1 %tmp, label %bb3, label %bb4 + +bb3: + store volatile float 0.0, float addrspace(1)* undef + br label %bb4 + +bb4: + %vgpr = load volatile float, float addrspace(1)* undef + %tmp0 = fmul float %sgpr0, 0.5 + %tmp1 = fadd float %tmp0, 42.0 + %tmp2 = fmul float %tmp1, %vgpr + store volatile float %tmp2, float addrspace(1)* undef, align 4 + ret void +} + +attributes #0 = { nounwind} diff --git a/test/CodeGen/AMDGPU/madmk.ll b/test/CodeGen/AMDGPU/madmk.ll index f8e14e34af67..1adf82402b72 100644 --- a/test/CodeGen/AMDGPU/madmk.ll +++ b/test/CodeGen/AMDGPU/madmk.ll @@ -1,21 +1,25 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone + ; FIXME: None of these trigger madmk emission anymore. It is still + ; possible, but requires the correct registers to be used which is + ; hard to trigger. + +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare float @llvm.fabs.f32(float) nounwind readnone ; GCN-LABEL: {{^}}madmk_f32: ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 -; GCN: v_madmk_f32_e32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 +; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]] define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %mul = fmul float %a, 10.0 %madmk = fadd float %mul, %b @@ -32,7 +36,7 @@ define void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noa ; GCN-DAG: v_mac_f32_e32 [[VC]], [[VK]], [[VA]] ; GCN: s_endpgm define void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 @@ -41,9 +45,9 @@ define void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1 %out.gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 - %a = load float, float addrspace(1)* %in.gep.0, align 4 - %b = load float, float addrspace(1)* %in.gep.1, align 4 - %c = load float, float addrspace(1)* %in.gep.2, align 4 + %a = load volatile float, float addrspace(1)* %in.gep.0, align 4 + %b = load volatile float, float addrspace(1)* %in.gep.1, align 4 + %c = load volatile float, float addrspace(1)* %in.gep.2, align 4 %mul0 = fmul float %a, 10.0 %mul1 = fmul float %a, 10.0 @@ -61,13 +65,13 @@ define void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]] define void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %mul = fmul float %a, 4.0 %madmk = fadd float %mul, %b @@ -80,7 +84,7 @@ define void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrsp ; GCN: v_mac_f32_e32 ; GCN: s_endpgm define void @s_s_madmk_f32(float addrspace(1)* noalias %out, float %a, float %b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %mul = fmul float %a, 10.0 @@ -94,7 +98,7 @@ define void @s_s_madmk_f32(float addrspace(1)* noalias %out, float %a, float %b) ; GCN: v_mad_f32 ; GCN: s_endpgm define void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %b) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %a = load float, float addrspace(1)* %gep.0, align 4 @@ -110,7 +114,7 @@ define void @v_s_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* ; GCN: v_mac_f32_e32 ; GCN: s_endpgm define void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %b = load float, float addrspace(1)* %gep.0, align 4 @@ -126,13 +130,13 @@ define void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float add ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN: v_mad_f32 {{v[0-9]+}}, |{{v[0-9]+}}|, {{v[0-9]+}}, {{[sv][0-9]+}} define void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone @@ -147,13 +151,13 @@ define void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, |{{[sv][0-9]+}}| define void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid - %a = load float, float addrspace(1)* %gep.0, align 4 - %b = load float, float addrspace(1)* %gep.1, align 4 + %a = load volatile float, float addrspace(1)* %gep.0, align 4 + %b = load volatile float, float addrspace(1)* %gep.1, align 4 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone @@ -168,7 +172,7 @@ define void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float ; GCN: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GCN: v_mad_f32 {{v[0-9]+}}, [[VK]], [[A]], 2.0 define void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) nounwind { - %tid = tail call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid @@ -182,7 +186,7 @@ define void @madmk_add_inline_imm_f32(float addrspace(1)* noalias %out, float ad ; SI-LABEL: {{^}}kill_madmk_verifier_error: ; SI: s_xor_b64 -; SI: v_madmk_f32_e32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, 0x472aee8c +; SI: v_mac_f32_e32 {{v[0-9]+}}, 0x472aee8c, {{v[0-9]+}} ; SI: s_or_b64 define void @kill_madmk_verifier_error() nounwind { bb: @@ -193,7 +197,9 @@ bb1: ; preds = %bb2 bb2: ; preds = %bb6, %bb %tmp = phi float [ undef, %bb ], [ %tmp8, %bb6 ] - %tmp3 = fsub float undef, %tmp + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 + %f_tid = bitcast i32 %tid to float + %tmp3 = fsub float %f_tid, %tmp %tmp5 = fcmp oeq float %tmp3, 1.000000e+04 br i1 %tmp5, label %bb1, label %bb6 @@ -203,3 +209,7 @@ bb6: ; preds = %bb2 %tmp8 = fadd float %tmp7, undef br label %bb2 } + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 + +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/max-literals.ll b/test/CodeGen/AMDGPU/max-literals.ll index c357524b140f..3f80d5e41a3f 100644 --- a/test/CodeGen/AMDGPU/max-literals.ll +++ b/test/CodeGen/AMDGPU/max-literals.ll @@ -3,7 +3,7 @@ ; CHECK-LABEL: {{^}}main: ; CHECK: ADD * -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -23,16 +23,16 @@ main_body: %15 = insertelement <4 x float> %14, float %8, i32 3 %16 = insertelement <4 x float> %15, float %11, i32 3 - %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) + %17 = call float @llvm.r600.dot4(<4 x float> %15,<4 x float> %16) %18 = insertelement <4 x float> undef, float %17, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } ; CHECK-LABEL: {{^}}main2: ; CHECK-NOT: ADD * -define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -52,16 +52,15 @@ main_body: %15 = insertelement <4 x float> %14, float %8, i32 3 %16 = insertelement <4 x float> %15, float %11, i32 3 - %17 = call float @llvm.AMDGPU.dp4(<4 x float> %15,<4 x float> %16) + %17 = call float @llvm.r600.dot4(<4 x float> %15,<4 x float> %16) %18 = insertelement <4 x float> undef, float %17, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/max.ll b/test/CodeGen/AMDGPU/max.ll index eeb915c10a96..5fa307be0fd5 100644 --- a/test/CodeGen/AMDGPU/max.ll +++ b/test/CodeGen/AMDGPU/max.ll @@ -1,19 +1,17 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; FUNC-LABEL: {{^}}v_test_imax_sge_i32: ; SI: v_max_i32_e32 + +; EG: MAX_INT define void @v_test_imax_sge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp sge i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } @@ -22,21 +20,25 @@ define void @v_test_imax_sge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr ; SI: v_max_i32_e32 ; SI: v_max_i32_e32 ; SI: v_max_i32_e32 + +; These could be merged into one +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT define void @v_test_imax_sge_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %aptr, <4 x i32> addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %out, i32 %tid - %a = load <4 x i32>, <4 x i32> addrspace(1)* %gep0, align 4 - %b = load <4 x i32>, <4 x i32> addrspace(1)* %gep1, align 4 + %a = load <4 x i32>, <4 x i32> addrspace(1)* %aptr, align 4 + %b = load <4 x i32>, <4 x i32> addrspace(1)* %bptr, align 4 %cmp = icmp sge <4 x i32> %a, %b %val = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b - store <4 x i32> %val, <4 x i32> addrspace(1)* %outgep, align 4 + store <4 x i32> %val, <4 x i32> addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: @s_test_imax_sge_i32 ; SI: s_max_i32 + +; EG: MAX_INT define void @s_test_imax_sge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp sge i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -46,6 +48,8 @@ define void @s_test_imax_sge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; FUNC-LABEL: {{^}}s_test_imax_sge_imm_i32: ; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9 + +; EG: MAX_INT {{.*}}literal.{{[xyzw]}} define void @s_test_imax_sge_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { %cmp = icmp sge i32 %a, 9 %val = select i1 %cmp, i32 %a, i32 9 @@ -57,21 +61,21 @@ define void @s_test_imax_sge_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { ; SI: buffer_load_sbyte ; SI: buffer_load_sbyte ; SI: v_max_i32_e32 + +; EG: MAX_INT define void @v_test_imax_sge_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid - %a = load i8, i8 addrspace(1)* %gep0, align 1 - %b = load i8, i8 addrspace(1)* %gep1, align 1 + %a = load i8, i8 addrspace(1)* %aptr, align 1 + %b = load i8, i8 addrspace(1)* %bptr, align 1 %cmp = icmp sge i8 %a, %b %val = select i1 %cmp, i8 %a, i8 %b - store i8 %val, i8 addrspace(1)* %outgep, align 1 + store i8 %val, i8 addrspace(1)* %out, align 1 ret void } ; FUNC-LABEL: {{^}}s_test_imax_sgt_imm_i32: ; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9 + +; EG: MAX_INT {{.*}}literal.{{[xyzw]}} define void @s_test_imax_sgt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { %cmp = icmp sgt i32 %a, 9 %val = select i1 %cmp, i32 %a, i32 9 @@ -82,29 +86,33 @@ define void @s_test_imax_sgt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { ; FUNC-LABEL: {{^}}s_test_imax_sgt_imm_v2i32: ; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9 ; SI: s_max_i32 {{s[0-9]+}}, {{s[0-9]+}}, 9 + +; EG: MAX_INT {{.*}}literal.{{[xyzw]}} +; EG: MAX_INT {{.*}}literal.{{[xyzw]}} define void @s_test_imax_sgt_imm_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a) nounwind { %cmp = icmp sgt <2 x i32> %a, %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> store <2 x i32> %val, <2 x i32> addrspace(1)* %out, align 4 ret void } + ; FUNC-LABEL: @v_test_imax_sgt_i32 ; SI: v_max_i32_e32 + +; EG: MAX_INT define void @v_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp sgt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: @s_test_imax_sgt_i32 ; SI: s_max_i32 + +; EG: MAX_INT define void @s_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp sgt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -114,21 +122,21 @@ define void @s_test_imax_sgt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; FUNC-LABEL: @v_test_umax_uge_i32 ; SI: v_max_u32_e32 + +; EG: MAX_UINT define void @v_test_umax_uge_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp uge i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: @s_test_umax_uge_i32 ; SI: s_max_u32 + +; EG: MAX_UINT define void @s_test_umax_uge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp uge i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -142,6 +150,11 @@ define void @s_test_umax_uge_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; SI: s_max_u32 ; SI-NOT: s_max_u32 ; SI: s_endpgm + +; EG: MAX_UINT +; EG: MAX_UINT +; EG: MAX_UINT +; EG-NOT: MAX_UINT define void @s_test_umax_uge_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, <3 x i32> %b) nounwind { %cmp = icmp uge <3 x i32> %a, %b %val = select <3 x i1> %cmp, <3 x i32> %a, <3 x i32> %b @@ -153,36 +166,34 @@ define void @s_test_umax_uge_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> %a, < ; SI: buffer_load_ubyte ; SI: buffer_load_ubyte ; SI: v_max_u32_e32 + +; EG: MAX_UINT define void @v_test_umax_uge_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid - %a = load i8, i8 addrspace(1)* %gep0, align 1 - %b = load i8, i8 addrspace(1)* %gep1, align 1 + %a = load i8, i8 addrspace(1)* %aptr, align 1 + %b = load i8, i8 addrspace(1)* %bptr, align 1 %cmp = icmp uge i8 %a, %b %val = select i1 %cmp, i8 %a, i8 %b - store i8 %val, i8 addrspace(1)* %outgep, align 1 + store i8 %val, i8 addrspace(1)* %out, align 1 ret void } ; FUNC-LABEL: @v_test_umax_ugt_i32 ; SI: v_max_u32_e32 + +; EG: MAX_UINT define void @v_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp ugt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: {{^}}s_test_umax_ugt_i32: ; SI: s_max_u32 + +; EG: MAX_UINT define void @s_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp ugt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -191,8 +202,11 @@ define void @s_test_umax_ugt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin } ; FUNC-LABEL: {{^}}s_test_umax_ugt_imm_v2i32: -; SI: s_max_u32 {{s[0-9]+}}, {{s[0-9]+}}, 15 -; SI: s_max_u32 {{s[0-9]+}}, {{s[0-9]+}}, 23 +; SI-DAG: s_max_u32 {{s[0-9]+}}, {{s[0-9]+}}, 15 +; SI-DAG: s_max_u32 {{s[0-9]+}}, {{s[0-9]+}}, 23 + +; EG: MAX_UINT {{.*}}literal.{{[xyzw]}} +; EG: MAX_UINT {{.*}}literal.{{[xyzw]}} define void @s_test_umax_ugt_imm_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a) nounwind { %cmp = icmp ugt <2 x i32> %a, %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> @@ -205,8 +219,10 @@ define void @s_test_umax_ugt_imm_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_max_u32 [[MAX:s[0-9]+]], [[A]], [[B]] -; SI-NEXT: v_mov_b32_e32 [[VMAX:v[0-9]+]], [[MAX]] -; SI-NEXT: buffer_store_dword [[VMAX]] +; SI: v_mov_b32_e32 [[VMAX:v[0-9]+]], [[MAX]] +; SI: buffer_store_dword [[VMAX]] + +; EG: MAX_UINT define void @simplify_demanded_bits_test_umax_ugt_i16(i32 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) nounwind { %a.ext = zext i16 %a to i32 %b.ext = zext i16 %b to i32 @@ -223,8 +239,10 @@ define void @simplify_demanded_bits_test_umax_ugt_i16(i32 addrspace(1)* %out, i1 ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_max_i32 [[MAX:s[0-9]+]], [[A]], [[B]] -; SI-NEXT: v_mov_b32_e32 [[VMAX:v[0-9]+]], [[MAX]] -; SI-NEXT: buffer_store_dword [[VMAX]] +; SI: v_mov_b32_e32 [[VMAX:v[0-9]+]], [[MAX]] +; SI: buffer_store_dword [[VMAX]] + +; EG: MAX_INT define void @simplify_demanded_bits_test_max_slt_i16(i32 addrspace(1)* %out, i16 signext %a, i16 signext %b) nounwind { %a.ext = sext i16 %a to i32 %b.ext = sext i16 %b to i32 @@ -242,9 +260,60 @@ define void @simplify_demanded_bits_test_max_slt_i16(i32 addrspace(1)* %out, i16 ; SI: s_sext_i32_i16 ; SI: s_sext_i32_i16 ; SI: s_max_i32 + +; EG: MAX_INT define void @s_test_imax_sge_i16(i16 addrspace(1)* %out, i16 %a, i16 %b) nounwind { %cmp = icmp sge i16 %a, %b %val = select i1 %cmp, i16 %a, i16 %b store i16 %val, i16 addrspace(1)* %out ret void } + +; 64 bit +; FUNC-LABEL: {{^}}test_umax_ugt_i64 +; SI: s_endpgm + +; EG: MAX_UINT +; EG: MAX_UINT +define void @test_umax_ugt_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp ugt i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_umax_uge_i64 +; SI: s_endpgm + +; EG: MAX_UINT +; EG: MAX_UINT +define void @test_umax_uge_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp uge i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_imax_sgt_i64 +; SI: s_endpgm + +; EG-DAG: MAX_UINT +; EG-DAG: MAX_INT +define void @test_imax_sgt_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp sgt i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_imax_sge_i64 +; SI: s_endpgm + +; EG-DAG: MAX_UINT +; EG-DAG: MAX_INT +define void @test_imax_sge_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp sge i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/max3.ll b/test/CodeGen/AMDGPU/max3.ll index cfb94b272e51..a12dba2eb6e9 100644 --- a/test/CodeGen/AMDGPU/max3.ll +++ b/test/CodeGen/AMDGPU/max3.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; FUNC-LABEL: @v_test_imax3_sgt_i32 ; SI: v_max3_i32 define void @v_test_imax3_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid @@ -24,7 +24,7 @@ define void @v_test_imax3_sgt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt ; FUNC-LABEL: @v_test_umax3_ugt_i32 ; SI: v_max3_u32 define void @v_test_umax3_ugt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid diff --git a/test/CodeGen/AMDGPU/merge-stores.ll b/test/CodeGen/AMDGPU/merge-stores.ll index 65b454b5d8cb..17b4af818f8f 100644 --- a/test/CodeGen/AMDGPU/merge-stores.ll +++ b/test/CodeGen/AMDGPU/merge-stores.ll @@ -231,8 +231,8 @@ define void @merge_global_store_2_adjacent_loads_i32(i32 addrspace(1)* %out, i32 } ; GCN-LABEL: {{^}}merge_global_store_2_adjacent_loads_i32_nonzero_base: -; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 -; GCN: buffer_store_dwordx2 [[LOAD]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN: buffer_store_dwordx2 [[LOAD]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 define void @merge_global_store_2_adjacent_loads_i32_nonzero_base(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %in.gep.0 = getelementptr i32, i32 addrspace(1)* %in, i32 2 %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 3 @@ -334,8 +334,8 @@ define void @merge_global_store_4_adjacent_loads_f32(float addrspace(1)* %out, f } ; GCN-LABEL: {{^}}merge_global_store_4_adjacent_loads_i32_nonzero_base: -; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 -; GCN: buffer_store_dwordx4 [[LOAD]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 +; GCN: buffer_load_dwordx4 [[LOAD:v\[[0-9]+:[0-9]+\]]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 +; GCN: buffer_store_dwordx4 [[LOAD]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 define void @merge_global_store_4_adjacent_loads_i32_nonzero_base(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { %in.gep.0 = getelementptr i32, i32 addrspace(1)* %in, i32 11 %in.gep.1 = getelementptr i32, i32 addrspace(1)* %in, i32 12 @@ -376,7 +376,7 @@ define void @merge_global_store_4_adjacent_loads_inverse_i32(i32 addrspace(1)* % %w = load i32, i32 addrspace(1)* %in.gep.3 ; Make sure the barrier doesn't stop this - tail call void @llvm.AMDGPU.barrier.local() #1 + tail call void @llvm.amdgcn.s.barrier() #1 store i32 %w, i32 addrspace(1)* %out.gep.3 store i32 %z, i32 addrspace(1)* %out.gep.2 @@ -413,7 +413,7 @@ define void @merge_global_store_4_adjacent_loads_shuffle_i32(i32 addrspace(1)* % %w = load i32, i32 addrspace(1)* %in.gep.3 ; Make sure the barrier doesn't stop this - tail call void @llvm.AMDGPU.barrier.local() #1 + tail call void @llvm.amdgcn.s.barrier() #1 store i32 %w, i32 addrspace(1)* %out store i32 %z, i32 addrspace(1)* %out.gep.1 @@ -640,13 +640,13 @@ define void @merge_global_store_8_constants_i32(i32 addrspace(1)* %out) { ; GCN-LABEL: {{^}}copy_v3i32_align4: ; GCN-NOT: SCRATCH_RSRC_DWORD -; GCN-DAG: buffer_load_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 -; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN-NOT: offen ; GCN: s_waitcnt vmcnt ; GCN-NOT: offen -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; GCN: ScratchSize: 0{{$}} define void @copy_v3i32_align4(<3 x i32> addrspace(1)* noalias %out, <3 x i32> addrspace(1)* noalias %in) #0 { @@ -657,13 +657,13 @@ define void @copy_v3i32_align4(<3 x i32> addrspace(1)* noalias %out, <3 x i32> a ; GCN-LABEL: {{^}}copy_v3i64_align4: ; GCN-NOT: SCRATCH_RSRC_DWORD -; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} ; GCN-NOT: offen ; GCN: s_waitcnt vmcnt ; GCN-NOT: offen -; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} ; GCN: ScratchSize: 0{{$}} define void @copy_v3i64_align4(<3 x i64> addrspace(1)* noalias %out, <3 x i64> addrspace(1)* noalias %in) #0 { %vec = load <3 x i64>, <3 x i64> addrspace(1)* %in, align 4 @@ -673,13 +673,13 @@ define void @copy_v3i64_align4(<3 x i64> addrspace(1)* noalias %out, <3 x i64> a ; GCN-LABEL: {{^}}copy_v3f32_align4: ; GCN-NOT: SCRATCH_RSRC_DWORD -; GCN-DAG: buffer_load_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 -; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_load_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN-NOT: offen ; GCN: s_waitcnt vmcnt ; GCN-NOT: offen -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; GCN: ScratchSize: 0{{$}} define void @copy_v3f32_align4(<3 x float> addrspace(1)* noalias %out, <3 x float> addrspace(1)* noalias %in) #0 { %vec = load <3 x float>, <3 x float> addrspace(1)* %in, align 4 @@ -690,13 +690,13 @@ define void @copy_v3f32_align4(<3 x float> addrspace(1)* noalias %out, <3 x floa ; GCN-LABEL: {{^}}copy_v3f64_align4: ; GCN-NOT: SCRATCH_RSRC_DWORD -; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} ; GCN-NOT: offen ; GCN: s_waitcnt vmcnt ; GCN-NOT: offen -; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16{{$}} ; GCN: ScratchSize: 0{{$}} define void @copy_v3f64_align4(<3 x double> addrspace(1)* noalias %out, <3 x double> addrspace(1)* noalias %in) #0 { %vec = load <3 x double>, <3 x double> addrspace(1)* %in, align 4 @@ -705,7 +705,7 @@ define void @copy_v3f64_align4(<3 x double> addrspace(1)* noalias %out, <3 x dou ret void } -declare void @llvm.AMDGPU.barrier.local() #1 +declare void @llvm.amdgcn.s.barrier() #1 attributes #0 = { nounwind } attributes #1 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/min.ll b/test/CodeGen/AMDGPU/min.ll index 215dbeb4b2fd..5d64a152af3c 100644 --- a/test/CodeGen/AMDGPU/min.ll +++ b/test/CodeGen/AMDGPU/min.ll @@ -1,24 +1,25 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; FUNC-LABEL: {{^}}v_test_imin_sle_i32: ; SI: v_min_i32_e32 + +; EG: MIN_INT define void @v_test_imin_sle_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp sle i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: {{^}}s_test_imin_sle_i32: ; SI: s_min_i32 + +; EG: MIN_INT define void @s_test_imin_sle_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp sle i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -28,6 +29,8 @@ define void @s_test_imin_sle_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; FUNC-LABEL: {{^}}s_test_imin_sle_v1i32: ; SI: s_min_i32 + +; EG: MIN_INT define void @s_test_imin_sle_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind { %cmp = icmp sle <1 x i32> %a, %b %val = select <1 x i1> %cmp, <1 x i32> %a, <1 x i32> %b @@ -40,6 +43,11 @@ define void @s_test_imin_sle_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, < ; SI: s_min_i32 ; SI: s_min_i32 ; SI: s_min_i32 + +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT define void @s_test_imin_sle_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind { %cmp = icmp sle <4 x i32> %a, %b %val = select <4 x i1> %cmp, <4 x i32> %a, <4 x i32> %b @@ -79,6 +87,11 @@ define void @s_test_imin_sle_i8(i8 addrspace(1)* %out, i8 %a, i8 %b) nounwind { ; SI: v_min_i32 ; SI: s_endpgm + +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT define void @s_test_imin_sle_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x i8> %b) nounwind { %cmp = icmp sle <4 x i8> %a, %b %val = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b @@ -91,6 +104,11 @@ define void @s_test_imin_sle_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> %a, <4 x ; SI: v_min_i32 ; SI: v_min_i32 ; SI: v_min_i32 + +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT +; EG: MIN_INT define void @s_test_imin_sle_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b) nounwind { %cmp = icmp sle <4 x i16> %a, %b %val = select <4 x i1> %cmp, <4 x i16> %a, <4 x i16> %b @@ -100,21 +118,21 @@ define void @s_test_imin_sle_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, < ; FUNC-LABEL: @v_test_imin_slt_i32 ; SI: v_min_i32_e32 + +; EG: MIN_INT define void @v_test_imin_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp slt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } ; FUNC-LABEL: @s_test_imin_slt_i32 ; SI: s_min_i32 + +; EG: MIN_INT define void @s_test_imin_slt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp slt i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -125,6 +143,9 @@ define void @s_test_imin_slt_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; FUNC-LABEL: {{^}}s_test_imin_slt_v2i32: ; SI: s_min_i32 ; SI: s_min_i32 + +; EG: MIN_INT +; EG: MIN_INT define void @s_test_imin_slt_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind { %cmp = icmp slt <2 x i32> %a, %b %val = select <2 x i1> %cmp, <2 x i32> %a, <2 x i32> %b @@ -134,6 +155,8 @@ define void @s_test_imin_slt_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, < ; FUNC-LABEL: {{^}}s_test_imin_slt_imm_i32: ; SI: s_min_i32 {{s[0-9]+}}, {{s[0-9]+}}, 8 + +; EG: MIN_INT {{.*}}literal.{{[xyzw]}} define void @s_test_imin_slt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { %cmp = icmp slt i32 %a, 8 %val = select i1 %cmp, i32 %a, i32 8 @@ -143,6 +166,8 @@ define void @s_test_imin_slt_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { ; FUNC-LABEL: {{^}}s_test_imin_sle_imm_i32: ; SI: s_min_i32 {{s[0-9]+}}, {{s[0-9]+}}, 8 + +; EG: MIN_INT {{.*}}literal.{{[xyzw]}} define void @s_test_imin_sle_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { %cmp = icmp sle i32 %a, 8 %val = select i1 %cmp, i32 %a, i32 8 @@ -152,16 +177,14 @@ define void @s_test_imin_sle_imm_i32(i32 addrspace(1)* %out, i32 %a) nounwind { ; FUNC-LABEL: @v_test_umin_ule_i32 ; SI: v_min_u32_e32 + +; EG: MIN_UINT define void @v_test_umin_ule_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp ule i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } @@ -171,20 +194,22 @@ define void @v_test_umin_ule_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr ; SI: v_min_u32_e32 ; SI-NOT: v_min_u32_e32 ; SI: s_endpgm + +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT define void @v_test_umin_ule_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %aptr, <3 x i32> addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr <3 x i32>, <3 x i32> addrspace(1)* %out, i32 %tid - %a = load <3 x i32>, <3 x i32> addrspace(1)* %gep0 - %b = load <3 x i32>, <3 x i32> addrspace(1)* %gep1 + %a = load <3 x i32>, <3 x i32> addrspace(1)* %aptr + %b = load <3 x i32>, <3 x i32> addrspace(1)* %bptr %cmp = icmp ule <3 x i32> %a, %b %val = select <3 x i1> %cmp, <3 x i32> %a, <3 x i32> %b - store <3 x i32> %val, <3 x i32> addrspace(1)* %outgep + store <3 x i32> %val, <3 x i32> addrspace(1)* %out ret void } ; FUNC-LABEL: @s_test_umin_ule_i32 ; SI: s_min_u32 + +; EG: MIN_UINT define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp ule i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -194,16 +219,14 @@ define void @s_test_umin_ule_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; FUNC-LABEL: @v_test_umin_ult_i32 ; SI: v_min_u32_e32 + +; EG: MIN_UINT define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp ult i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep, align 4 + store i32 %val, i32 addrspace(1)* %out, align 4 ret void } @@ -211,21 +234,21 @@ define void @v_test_umin_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr ; SI: buffer_load_ubyte ; SI: buffer_load_ubyte ; SI: v_min_u32_e32 + +; EG: MIN_UINT define void @v_test_umin_ult_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %aptr, i8 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i8, i8 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i8, i8 addrspace(1)* %bptr, i32 %tid - %outgep = getelementptr i8, i8 addrspace(1)* %out, i32 %tid - %a = load i8, i8 addrspace(1)* %gep0, align 1 - %b = load i8, i8 addrspace(1)* %gep1, align 1 + %a = load i8, i8 addrspace(1)* %aptr, align 1 + %b = load i8, i8 addrspace(1)* %bptr, align 1 %cmp = icmp ult i8 %a, %b %val = select i1 %cmp, i8 %a, i8 %b - store i8 %val, i8 addrspace(1)* %outgep, align 1 + store i8 %val, i8 addrspace(1)* %out, align 1 ret void } ; FUNC-LABEL: @s_test_umin_ult_i32 ; SI: s_min_u32 + +; EG: MIN_UINT define void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp ult i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b @@ -239,24 +262,23 @@ define void @s_test_umin_ult_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwin ; SI-NEXT: v_cndmask_b32 ; SI-NOT: v_min ; SI: s_endpgm + +; EG-NOT: MIN_UINT define void @v_test_umin_ult_i32_multi_use(i32 addrspace(1)* %out0, i1 addrspace(1)* %out1, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone - %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid - %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid - %outgep0 = getelementptr i32, i32 addrspace(1)* %out0, i32 %tid - %outgep1 = getelementptr i1, i1 addrspace(1)* %out1, i32 %tid - %a = load i32, i32 addrspace(1)* %gep0, align 4 - %b = load i32, i32 addrspace(1)* %gep1, align 4 + %a = load i32, i32 addrspace(1)* %aptr, align 4 + %b = load i32, i32 addrspace(1)* %bptr, align 4 %cmp = icmp ult i32 %a, %b %val = select i1 %cmp, i32 %a, i32 %b - store i32 %val, i32 addrspace(1)* %outgep0, align 4 - store i1 %cmp, i1 addrspace(1)* %outgep1 + store i32 %val, i32 addrspace(1)* %out0, align 4 + store i1 %cmp, i1 addrspace(1)* %out1 ret void } ; FUNC-LABEL: @s_test_umin_ult_v1i32 ; SI: s_min_u32 + +; EG: MIN_UINT define void @s_test_umin_ult_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind { %cmp = icmp ult <1 x i32> %a, %b %val = select <1 x i1> %cmp, <1 x i32> %a, <1 x i32> %b @@ -273,6 +295,15 @@ define void @s_test_umin_ult_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, < ; SI: s_min_u32 ; SI: s_min_u32 ; SI: s_min_u32 + +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT define void @s_test_umin_ult_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) nounwind { %cmp = icmp ult <8 x i32> %a, %b %val = select <8 x i1> %cmp, <8 x i32> %a, <8 x i32> %b @@ -289,6 +320,15 @@ define void @s_test_umin_ult_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, < ; SI: v_min_u32 ; SI: v_min_u32 ; SI: v_min_u32 + +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT +; EG: MIN_UINT define void @s_test_umin_ult_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> %a, <8 x i16> %b) nounwind { %cmp = icmp ult <8 x i16> %a, %b %val = select <8 x i1> %cmp, <8 x i16> %a, <8 x i16> %b @@ -301,8 +341,10 @@ define void @s_test_umin_ult_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> %a, < ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_min_u32 [[MIN:s[0-9]+]], [[A]], [[B]] -; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]] -; SI-NEXT: buffer_store_dword [[VMIN]] +; SI: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]] +; SI: buffer_store_dword [[VMIN]] + +; EG: MIN_UINT define void @simplify_demanded_bits_test_umin_ult_i16(i32 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) nounwind { %a.ext = zext i16 %a to i32 %b.ext = zext i16 %b to i32 @@ -319,8 +361,10 @@ define void @simplify_demanded_bits_test_umin_ult_i16(i32 addrspace(1)* %out, i1 ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_min_i32 [[MIN:s[0-9]+]], [[A]], [[B]] -; SI-NEXT: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]] -; SI-NEXT: buffer_store_dword [[VMIN]] +; SI: v_mov_b32_e32 [[VMIN:v[0-9]+]], [[MIN]] +; SI: buffer_store_dword [[VMIN]] + +; EG: MIN_INT define void @simplify_demanded_bits_test_min_slt_i16(i32 addrspace(1)* %out, i16 signext %a, i16 signext %b) nounwind { %a.ext = sext i16 %a to i32 %b.ext = sext i16 %b to i32 @@ -334,9 +378,60 @@ define void @simplify_demanded_bits_test_min_slt_i16(i32 addrspace(1)* %out, i16 ; FUNC-LABEL: {{^}}s_test_imin_sle_i16: ; SI: s_min_i32 + +; EG: MIN_INT define void @s_test_imin_sle_i16(i16 addrspace(1)* %out, i16 %a, i16 %b) nounwind { %cmp = icmp sle i16 %a, %b %val = select i1 %cmp, i16 %a, i16 %b store i16 %val, i16 addrspace(1)* %out ret void } + +; 64 bit +; FUNC-LABEL: {{^}}test_umin_ult_i64 +; SI: s_endpgm + +; EG: MIN_UINT +; EG: MIN_UINT +define void @test_umin_ult_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp ult i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_umin_ule_i64 +; SI: s_endpgm + +; EG: MIN_UINT +; EG: MIN_UINT +define void @test_umin_ule_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp ule i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_imin_slt_i64 +; SI: s_endpgm + +; EG-DAG: MIN_UINT +; EG-DAG: MIN_INT +define void @test_imin_slt_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp slt i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}test_imin_sle_i64 +; SI: s_endpgm + +; EG-DAG: MIN_UINT +; EG-DAG: MIN_INT +define void @test_imin_sle_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { + %tmp = icmp sle i64 %a, %b + %val = select i1 %tmp, i64 %a, i64 %b + store i64 %val, i64 addrspace(1)* %out, align 8 + ret void +} diff --git a/test/CodeGen/AMDGPU/min3.ll b/test/CodeGen/AMDGPU/min3.ll index 38ef46d1bdd6..728479ad9f62 100644 --- a/test/CodeGen/AMDGPU/min3.ll +++ b/test/CodeGen/AMDGPU/min3.ll @@ -1,11 +1,11 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; FUNC-LABEL: @v_test_imin3_slt_i32 ; SI: v_min3_i32 define void @v_test_imin3_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid @@ -24,7 +24,7 @@ define void @v_test_imin3_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt ; FUNC-LABEL: @v_test_umin3_ult_i32 ; SI: v_min3_u32 define void @v_test_umin3_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid %gep2 = getelementptr i32, i32 addrspace(1)* %cptr, i32 %tid @@ -44,7 +44,7 @@ define void @v_test_umin3_ult_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %apt ; SI: v_min_i32 ; SI: v_min3_i32 define void @v_test_umin_umin_umin(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid2 = mul i32 %tid, 2 %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid @@ -78,7 +78,7 @@ define void @v_test_umin_umin_umin(i32 addrspace(1)* %out, i32 addrspace(1)* %ap ; FUNC-LABEL: @v_test_umin3_2_uses ; SI-NOT: v_min3 define void @v_test_umin3_2_uses(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr, i32 addrspace(1)* %cptr) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid2 = mul i32 %tid, 2 %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid %gep1 = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid diff --git a/test/CodeGen/AMDGPU/missing-store.ll b/test/CodeGen/AMDGPU/missing-store.ll index 4af9cdf1b960..3d6d7fae0fd6 100644 --- a/test/CodeGen/AMDGPU/missing-store.ll +++ b/test/CodeGen/AMDGPU/missing-store.ll @@ -7,8 +7,12 @@ ; FUNC-LABEL: {{^}}missing_store_reduced: ; SI: ds_read_b64 -; SI: buffer_store_dword -; SI: buffer_load_dword +; SI-DAG: buffer_store_dword +; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} +; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} +; SI: s_load_dword +; SI: s_nop 2 +; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} ; SI: buffer_store_dword ; SI: s_endpgm define void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { diff --git a/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll b/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll index e9f641b736d5..36f12573c173 100644 --- a/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll +++ b/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll @@ -6,12 +6,13 @@ ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32 ; GCN-LABEL: {{^}}clobber_vgpr_pair_pointer_add: -; GCN: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} -; GCN: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} +; GCN-DAG: s_load_dwordx2 s{{\[}}[[ARG1LO:[0-9]+]]:[[ARG1HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} +; GCN-DAG: buffer_load_dwordx2 v{{\[}}[[LDPTRLO:[0-9]+]]:[[LDPTRHI:[0-9]+]]{{\]}} +; GCN-NOT: v_mov_b32 +; GCN: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]] ; GCN-NOT: v_mov_b32 ; GCN: v_mov_b32_e32 v[[VARG1LO:[0-9]+]], s[[ARG1LO]] -; GCN-NEXT: v_mov_b32_e32 v[[VARG1HI:[0-9]+]], s[[ARG1HI]] ; GCN-NOT: v_mov_b32 ; GCN: v_add_i32_e32 v[[PTRLO:[0-9]+]], vcc, v[[LDPTRLO]], v[[VARG1LO]] diff --git a/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll b/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll index 8bca0575ecd2..1a0a39027853 100644 --- a/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll +++ b/test/CodeGen/AMDGPU/move-to-valu-atomicrmw.ll @@ -7,12 +7,12 @@ ; Check that moving the pointer out of the resource descriptor to ; vaddr works for atomics. -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; GCN-LABEL: {{^}}atomic_max_i32: ; GCN: buffer_atomic_smax v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:400 glc{{$}} define void @atomic_max_i32(i32 addrspace(1)* %out, i32 addrspace(1)* addrspace(1)* %in, i32 addrspace(1)* %x, i32 %y) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() + %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.gep = getelementptr i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %in, i32 %tid %ptr = load volatile i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %tid.gep %xor = xor i32 %tid, 1 @@ -32,7 +32,7 @@ exit: ; GCN-LABEL: {{^}}atomic_max_i32_noret: ; GCN: buffer_atomic_smax v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:400{{$}} define void @atomic_max_i32_noret(i32 addrspace(1)* %out, i32 addrspace(1)* addrspace(1)* %in, i32 addrspace(1)* %x, i32 %y) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() + %tid = call i32 @llvm.amdgcn.workitem.id.x() %tid.gep = getelementptr i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %in, i32 %tid %ptr = load volatile i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* %tid.gep %xor = xor i32 %tid, 1 diff --git a/test/CodeGen/AMDGPU/mubuf.ll b/test/CodeGen/AMDGPU/mubuf.ll index b19163f294e0..a574365da986 100644 --- a/test/CodeGen/AMDGPU/mubuf.ll +++ b/test/CodeGen/AMDGPU/mubuf.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s -declare i32 @llvm.r600.read.tidig.x() readnone +declare i32 @llvm.amdgcn.workitem.id.x() readnone ;;;==========================================================================;;; ;;; MUBUF LOAD TESTS @@ -8,7 +8,7 @@ declare i32 @llvm.r600.read.tidig.x() readnone ; MUBUF load with an immediate byte offset that fits into 12-bits ; CHECK-LABEL: {{^}}mubuf_load0: -; CHECK: buffer_load_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x30,0xe0 +; CHECK: buffer_load_dword v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 ; encoding: [0x04,0x00,0x30,0xe0 define void @mubuf_load0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = getelementptr i32, i32 addrspace(1)* %in, i64 1 @@ -19,7 +19,7 @@ entry: ; MUBUF load with the largest possible immediate offset ; CHECK-LABEL: {{^}}mubuf_load1: -; CHECK: buffer_load_ubyte v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0 +; CHECK: buffer_load_ubyte v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x20,0xe0 define void @mubuf_load1(i8 addrspace(1)* %out, i8 addrspace(1)* %in) { entry: %0 = getelementptr i8, i8 addrspace(1)* %in, i64 4095 @@ -31,7 +31,7 @@ entry: ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits ; CHECK-LABEL: {{^}}mubuf_load2: ; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000 -; CHECK: buffer_load_dword v{{[0-9]}}, s[{{[0-9]+:[0-9]+}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x30,0xe0 +; CHECK: buffer_load_dword v{{[0-9]}}, off, s[{{[0-9]+:[0-9]+}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x30,0xe0 define void @mubuf_load2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %0 = getelementptr i32, i32 addrspace(1)* %in, i64 1024 @@ -55,15 +55,14 @@ entry: ; CHECK-LABEL: {{^}}soffset_max_imm: ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc -define void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 { +define amdgpu_gs void @soffset_max_imm([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) { main_body: %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0 %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0 %tmp2 = shl i32 %6, 2 %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp4 = add i32 %6, 16 - %tmp5 = bitcast float 0.0 to i32 - call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) + call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp3, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) ret void } @@ -74,15 +73,14 @@ main_body: ; CHECK-LABEL: {{^}}soffset_no_fold: ; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41 ; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc -define void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) #1 { +define amdgpu_gs void @soffset_no_fold([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) { main_body: %tmp0 = getelementptr [6 x <16 x i8>], [6 x <16 x i8>] addrspace(2)* %0, i32 0, i32 0 %tmp1 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp0 %tmp2 = shl i32 %6, 2 %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp4 = add i32 %6, 16 - %tmp5 = bitcast float 0.0 to i32 - call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp5, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) + call void @llvm.SI.tbuffer.store.i32(<16 x i8> %tmp1, i32 %tmp3, i32 1, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0) ret void } @@ -92,7 +90,7 @@ main_body: ; MUBUF store with an immediate byte offset that fits into 12-bits ; CHECK-LABEL: {{^}}mubuf_store0: -; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x70,0xe0 +; CHECK: buffer_store_dword v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], 0 offset:4 ; encoding: [0x04,0x00,0x70,0xe0 define void @mubuf_store0(i32 addrspace(1)* %out) { entry: %0 = getelementptr i32, i32 addrspace(1)* %out, i64 1 @@ -102,7 +100,7 @@ entry: ; MUBUF store with the largest possible immediate offset ; CHECK-LABEL: {{^}}mubuf_store1: -; CHECK: buffer_store_byte v{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0 +; CHECK: buffer_store_byte v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], 0 offset:4095 ; encoding: [0xff,0x0f,0x60,0xe0 define void @mubuf_store1(i8 addrspace(1)* %out) { entry: @@ -114,7 +112,7 @@ entry: ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits ; CHECK-LABEL: {{^}}mubuf_store2: ; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x1000 -; CHECK: buffer_store_dword v{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x70,0xe0 +; CHECK: buffer_store_dword v{{[0-9]}}, off, s[{{[0-9]:[0-9]}}], [[SOFFSET]] ; encoding: [0x00,0x00,0x70,0xe0 define void @mubuf_store2(i32 addrspace(1)* %out) { entry: %0 = getelementptr i32, i32 addrspace(1)* %out, i64 1024 @@ -135,14 +133,14 @@ entry: } ; CHECK-LABEL: {{^}}store_sgpr_ptr: -; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 +; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 define void @store_sgpr_ptr(i32 addrspace(1)* %out) #0 { store i32 99, i32 addrspace(1)* %out, align 4 ret void } ; CHECK-LABEL: {{^}}store_sgpr_ptr_offset: -; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:40 +; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:40 define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 { %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 10 store i32 99, i32 addrspace(1)* %out.gep, align 4 @@ -151,7 +149,7 @@ define void @store_sgpr_ptr_offset(i32 addrspace(1)* %out) #0 { ; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset: ; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000 -; CHECK: buffer_store_dword v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]] +; CHECK: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]] define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 { %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768 store i32 99, i32 addrspace(1)* %out.gep, align 4 @@ -160,7 +158,7 @@ define void @store_sgpr_ptr_large_offset(i32 addrspace(1)* %out) #0 { ; CHECK-LABEL: {{^}}store_sgpr_ptr_large_offset_atomic: ; CHECK: s_mov_b32 [[SOFFSET:s[0-9]+]], 0x20000 -; CHECK: buffer_atomic_add v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]] +; CHECK: buffer_atomic_add v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, [[SOFFSET]] define void @store_sgpr_ptr_large_offset_atomic(i32 addrspace(1)* %out) #0 { %gep = getelementptr i32, i32 addrspace(1)* %out, i32 32768 %val = atomicrmw volatile add i32 addrspace(1)* %gep, i32 5 seq_cst @@ -170,14 +168,13 @@ define void @store_sgpr_ptr_large_offset_atomic(i32 addrspace(1)* %out) #0 { ; CHECK-LABEL: {{^}}store_vgpr_ptr: ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 define void @store_vgpr_ptr(i32 addrspace(1)* %out) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid store i32 99, i32 addrspace(1)* %out.gep, align 4 ret void } -declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #3 +declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #0 declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -attributes #1 = { "ShaderType"="2" "unsafe-fp-math"="true" } -attributes #3 = { nounwind readonly } +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/mul.ll b/test/CodeGen/AMDGPU/mul.ll index 94e0f96b323e..5ceef7fda826 100644 --- a/test/CodeGen/AMDGPU/mul.ll +++ b/test/CodeGen/AMDGPU/mul.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s -check-prefix=FUNC ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s -check-prefix=FUNC ; mul24 and mad24 are affected @@ -96,8 +96,8 @@ define void @v_mul64_sext_c(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}v_mul64_sext_inline_imm: -; SI-DAG: v_mul_lo_i32 v{{[0-9]+}}, 9, v{{[0-9]+}} -; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, 9, v{{[0-9]+}} +; SI-DAG: v_mul_lo_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9 +; SI-DAG: v_mul_hi_i32 v{{[0-9]+}}, v{{[0-9]+}}, 9 ; SI: s_endpgm define void @v_mul64_sext_inline_imm(i64 addrspace(1)* %out, i32 addrspace(1)* %in) { %val = load i32, i32 addrspace(1)* %in, align 4 diff --git a/test/CodeGen/AMDGPU/mul_int24.ll b/test/CodeGen/AMDGPU/mul_int24.ll index 7609dcc87afa..1a323fbaa1a3 100644 --- a/test/CodeGen/AMDGPU/mul_int24.ll +++ b/test/CodeGen/AMDGPU/mul_int24.ll @@ -1,7 +1,7 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; FUNC-LABEL: {{^}}i32_mul24: ; Signed 24-bit multiply is not supported on pre-Cayman GPUs. diff --git a/test/CodeGen/AMDGPU/mul_uint24.ll b/test/CodeGen/AMDGPU/mul_uint24.ll index 8a0e71d739be..fdd348403edf 100644 --- a/test/CodeGen/AMDGPU/mul_uint24.ll +++ b/test/CodeGen/AMDGPU/mul_uint24.ll @@ -1,7 +1,7 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC -; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC ; FUNC-LABEL: {{^}}u32_mul24: ; EG: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W diff --git a/test/CodeGen/AMDGPU/multilevel-break.ll b/test/CodeGen/AMDGPU/multilevel-break.ll new file mode 100644 index 000000000000..e1130c9125e5 --- /dev/null +++ b/test/CodeGen/AMDGPU/multilevel-break.ll @@ -0,0 +1,41 @@ +; RUN: opt -S -mtriple=amdgcn-- -structurizecfg -si-annotate-control-flow < %s | FileCheck %s + +; CHECK-LABEL: {{^}}define amdgpu_vs void @main +; CHECK: main_body: +; CHECK: LOOP.outer: +; CHECK: LOOP: +; CHECK: [[if:%[0-9]+]] = call { i1, i64 } @llvm.amdgcn.if( +; CHECK: [[if_exec:%[0-9]+]] = extractvalue { i1, i64 } [[if]], 1 +; +; CHECK: Flow: +; +; Ensure two else.break calls, for both the inner and outer loops +; +; CHECK: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]], +; CHECK-NEXT: call i64 @llvm.amdgcn.else.break(i64 [[if_exec]], +; CHECK-NEXT: call void @llvm.amdgcn.end.cf +; +; CHECK: Flow1: +define amdgpu_vs void @main(<4 x float> %vec, i32 %ub, i32 %cont) { +main_body: + br label %LOOP.outer + +LOOP.outer: ; preds = %ENDIF, %main_body + %tmp43 = phi i32 [ 0, %main_body ], [ %tmp47, %ENDIF ] + br label %LOOP + +LOOP: ; preds = %ENDIF, %LOOP.outer + %tmp45 = phi i32 [ %tmp43, %LOOP.outer ], [ %tmp47, %ENDIF ] + %tmp47 = add i32 %tmp45, 1 + %tmp48 = icmp slt i32 %tmp45, %ub + br i1 %tmp48, label %ENDIF, label %IF + +IF: ; preds = %LOOP + ret void + +ENDIF: ; preds = %LOOP + %tmp51 = icmp eq i32 %tmp47, %cont + br i1 %tmp51, label %LOOP, label %LOOP.outer +} + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll b/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll index 73a146710a9f..d1fe794b93fb 100644 --- a/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll +++ b/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll @@ -1,18 +1,16 @@ ; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s 2>&1 | FileCheck %s -; CHECK: error: unsupported non-compute shaders with HSA in pixel_shader -define void @pixel_shader() #0 { +; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA +define amdgpu_ps void @pixel_shader() #0 { ret void } -define void @vertex_shader() #1 { +; CHECK: in function vertex_s{{.*}}: unsupported non-compute shaders with HSA +define amdgpu_vs void @vertex_shader() #0 { ret void } -define void @geometry_shader() #2 { +; CHECK: in function geometry_s{{.*}}: unsupported non-compute shaders with HSA +define amdgpu_gs void @geometry_shader() #0 { ret void } - -attributes #0 = { nounwind "ShaderType"="0" } -attributes #1 = { nounwind "ShaderType"="1" } -attributes #2 = { nounwind "ShaderType"="2" } diff --git a/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll b/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll index 9a814b579deb..9dd99efd997c 100644 --- a/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll +++ b/test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll @@ -1,19 +1,24 @@ -; RUN: llc -march=amdgcn -mcpu=SI -o /dev/null %s -; RUN: llc -march=amdgcn -mcpu=tonga -o /dev/null %s -; RUN: llc -march=r600 -mcpu=cypress -o /dev/null %s +; RUN: llc -march=amdgcn -mcpu=SI -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN +; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN +; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG +; GCN: R_AMDGPU_REL32 extern_const_addrspace +; EG: R_AMDGPU_ABS32 extern_const_addrspace + +; CHECK-DAG: Name: extern_const_addrspace @extern_const_addrspace = external unnamed_addr addrspace(2) constant [5 x i32], align 4 -; FUNC-LABEL: {{^}}load_extern_const_init: +; CHECK-DAG: Name: load_extern_const_init define void @load_extern_const_init(i32 addrspace(1)* %out) nounwind { %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @extern_const_addrspace, i64 0, i64 3), align 4 store i32 %val, i32 addrspace(1)* %out, align 4 ret void } +; CHECK-DAG: Name: undef_const_addrspace @undef_const_addrspace = unnamed_addr addrspace(2) constant [5 x i32] undef, align 4 -; FUNC-LABEL: {{^}}load_undef_const_init: +; CHECK-DAG: Name: undef_const_addrspace define void @load_undef_const_init(i32 addrspace(1)* %out) nounwind { %val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @undef_const_addrspace, i64 0, i64 3), align 4 store i32 %val, i32 addrspace(1)* %out, align 4 diff --git a/test/CodeGen/AMDGPU/no-shrink-extloads.ll b/test/CodeGen/AMDGPU/no-shrink-extloads.ll index f81911aafe22..fd66b0b5d1f6 100644 --- a/test/CodeGen/AMDGPU/no-shrink-extloads.ll +++ b/test/CodeGen/AMDGPU/no-shrink-extloads.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; Make sure we don't turn the 32-bit argument load into a 16-bit ; load. There aren't extending scalar lods, so that would require @@ -22,7 +22,7 @@ define void @truncate_kernarg_i32_to_i16(i16 addrspace(1)* %out, i32 %arg) nounw ; SI: buffer_load_dword v ; SI: buffer_store_short v define void @truncate_buffer_load_i32_to_i16(i16 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i16, i16 addrspace(1)* %out, i32 %tid %load = load i32, i32 addrspace(1)* %gep.in @@ -44,7 +44,7 @@ define void @truncate_kernarg_i32_to_i8(i8 addrspace(1)* %out, i32 %arg) nounwin ; SI: buffer_load_dword v ; SI: buffer_store_byte v define void @truncate_buffer_load_i32_to_i8(i8 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid %load = load i32, i32 addrspace(1)* %gep.in @@ -66,7 +66,7 @@ define void @truncate_kernarg_i32_to_i1(i1 addrspace(1)* %out, i32 %arg) nounwin ; SI: buffer_load_dword v ; SI: buffer_store_byte v define void @truncate_buffer_load_i32_to_i1(i1 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i1, i1 addrspace(1)* %out, i32 %tid %load = load i32, i32 addrspace(1)* %gep.in @@ -88,7 +88,7 @@ define void @truncate_kernarg_i64_to_i32(i32 addrspace(1)* %out, i64 %arg) nounw ; SI: buffer_load_dword v ; SI: buffer_store_dword v define void @truncate_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %load = load i64, i64 addrspace(1)* %gep.in @@ -111,7 +111,7 @@ define void @srl_kernarg_i64_to_i32(i32 addrspace(1)* %out, i64 %arg) nounwind { ; SI: buffer_load_dword v ; SI: buffer_store_dword v define void @srl_buffer_load_i64_to_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid %load = load i64, i64 addrspace(1)* %gep.in @@ -135,7 +135,7 @@ define void @truncate_kernarg_i16_to_i8(i8 addrspace(1)* %out, i16 %arg) nounwin ; SI: buffer_load_ubyte v ; SI: buffer_store_byte v define void @truncate_buffer_load_i16_to_i8(i8 addrspace(1)* %out, i16 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i16, i16 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid %load = load i16, i16 addrspace(1)* %gep.in @@ -158,7 +158,7 @@ define void @srl_kernarg_i64_to_i8(i8 addrspace(1)* %out, i64 %arg) nounwind { ; SI: buffer_load_dword v ; SI: buffer_store_byte v define void @srl_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid %load = load i64, i64 addrspace(1)* %gep.in @@ -181,7 +181,7 @@ define void @truncate_kernarg_i64_to_i8(i8 addrspace(1)* %out, i64 %arg) nounwin ; SI: buffer_load_dword v ; SI: buffer_store_byte v define void @truncate_buffer_load_i64_to_i8(i8 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %gep.out = getelementptr i8, i8 addrspace(1)* %out, i32 %tid %load = load i64, i64 addrspace(1)* %gep.in @@ -201,3 +201,15 @@ entry: store i32 %mask, i32 addrspace(1)* %out ret void } + +; FUNC-LABEL: {{^}}extract_hi_i64_bitcast_v2i32: +; SI: buffer_load_dword v +; SI: buffer_store_dword v +define void @extract_hi_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind { + %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in + %bc = bitcast <2 x i32> %ld to i64 + %hi = lshr i64 %bc, 32 + %trunc = trunc i64 %hi to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/opencl-image-metadata.ll b/test/CodeGen/AMDGPU/opencl-image-metadata.ll index bc467e47dc31..0242f6d6145a 100644 --- a/test/CodeGen/AMDGPU/opencl-image-metadata.ll +++ b/test/CodeGen/AMDGPU/opencl-image-metadata.ll @@ -1,5 +1,5 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; Make sure the OpenCL Image lowering pass doesn't crash when argument metadata ; is not in expected order. diff --git a/test/CodeGen/AMDGPU/operand-folding.ll b/test/CodeGen/AMDGPU/operand-folding.ll index 9e514ef9970a..d6fc65fa7e83 100644 --- a/test/CodeGen/AMDGPU/operand-folding.ll +++ b/test/CodeGen/AMDGPU/operand-folding.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; CHECK-LABEL: {{^}}fold_sgpr: ; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s @@ -8,7 +8,7 @@ entry: br i1 %tmp0, label %if, label %endif if: - %id = call i32 @llvm.r600.read.tidig.x() + %id = call i32 @llvm.amdgcn.workitem.id.x() %offset = add i32 %fold, %id %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %offset store i32 0, i32 addrspace(1)* %tmp1 @@ -27,7 +27,7 @@ entry: br i1 %tmp0, label %if, label %endif if: - %id = call i32 @llvm.r600.read.tidig.x() + %id = call i32 @llvm.amdgcn.workitem.id.x() %val = or i32 %id, %fold store i32 %val, i32 addrspace(1)* %out br label %endif @@ -63,7 +63,7 @@ entry: define void @vector_inline(<4 x i32> addrspace(1)* %out) { entry: - %tmp0 = call i32 @llvm.r600.read.tidig.x() + %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp0, 1 %tmp2 = add i32 %tmp0, 2 %tmp3 = add i32 %tmp0, 3 @@ -82,7 +82,7 @@ entry: define void @imm_one_use(i32 addrspace(1)* %out) { entry: - %tmp0 = call i32 @llvm.r600.read.tidig.x() + %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = xor i32 %tmp0, 100 store i32 %tmp1, i32 addrspace(1)* %out ret void @@ -96,7 +96,7 @@ entry: define void @vector_imm(<4 x i32> addrspace(1)* %out) { entry: - %tmp0 = call i32 @llvm.r600.read.tidig.x() + %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp0, 1 %tmp2 = add i32 %tmp0, 2 %tmp3 = add i32 %tmp0, 3 @@ -109,5 +109,6 @@ entry: ret void } -declare i32 @llvm.r600.read.tidig.x() #0 -attributes #0 = { readnone } +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/or.ll b/test/CodeGen/AMDGPU/or.ll index e40f18f040b7..9b90ff798ca7 100644 --- a/test/CodeGen/AMDGPU/or.ll +++ b/test/CodeGen/AMDGPU/or.ll @@ -96,7 +96,7 @@ define void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { ; SI: v_or_b32_e32 v{{[0-9]}} define void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) { %loada = load i64, i64 addrspace(1)* %a, align 8 - %loadb = load i64, i64 addrspace(1)* %a, align 8 + %loadb = load i64, i64 addrspace(1)* %b, align 8 %or = or i64 %loada, %loadb store i64 %or, i64 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/over-max-lds-size.ll b/test/CodeGen/AMDGPU/over-max-lds-size.ll new file mode 100644 index 000000000000..32ad9aba04ed --- /dev/null +++ b/test/CodeGen/AMDGPU/over-max-lds-size.ll @@ -0,0 +1,14 @@ +; RUN: not llc -march=amdgcn -mcpu=tahiti < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -march=amdgcn -mcpu=hawaii < %s 2>&1 | FileCheck -check-prefix=ERROR %s +; RUN: not llc -march=amdgcn -mcpu=fiji < %s 2>&1 | FileCheck -check-prefix=ERROR %s + +; ERROR: error: local memory limit exceeded (400000) in use_huge_lds + +@huge = internal unnamed_addr addrspace(3) global [100000 x i32] undef, align 4 + +define void @use_huge_lds() { +entry: + %v0 = getelementptr inbounds [100000 x i32], [100000 x i32] addrspace(3)* @huge, i32 0, i32 0 + store i32 0, i32 addrspace(3)* %v0 + ret void +} diff --git a/test/CodeGen/AMDGPU/parallelandifcollapse.ll b/test/CodeGen/AMDGPU/parallelandifcollapse.ll index f32b044198ab..ea943a533c81 100644 --- a/test/CodeGen/AMDGPU/parallelandifcollapse.ll +++ b/test/CodeGen/AMDGPU/parallelandifcollapse.ll @@ -1,5 +1,4 @@ -; Function Attrs: nounwind -; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca < %s | FileCheck %s +; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck %s ; ; CFG flattening should use parallel-and mode to generate branch conditions and ; then merge if-regions with the same bodies. diff --git a/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll b/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll index 51985af42a29..3e0d36978ad4 100644 --- a/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll +++ b/test/CodeGen/AMDGPU/partially-dead-super-register-immediate.ll @@ -8,10 +8,10 @@ ; During live interval construction, the first sub register def is ; incorrectly marked as dead. -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 define void @dead_def_subregister(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %val = load i64, i64 addrspace(1)* %in.gep diff --git a/test/CodeGen/AMDGPU/predicate-dp4.ll b/test/CodeGen/AMDGPU/predicate-dp4.ll index 6bc187594359..7ac2bb7b0c7f 100644 --- a/test/CodeGen/AMDGPU/predicate-dp4.ll +++ b/test/CodeGen/AMDGPU/predicate-dp4.ll @@ -3,7 +3,7 @@ ; CHECK-LABEL: {{^}}main: ; CHECK: PRED_SETE_INT * Pred, ; CHECK: DOT4 T{{[0-9]+}}.X, T0.X, T0.X, Pred_sel_one -define void @main(<4 x float> inreg) #0 { +define amdgpu_ps void @main(<4 x float> inreg) { main_body: %1 = extractelement <4 x float> %0, i32 0 %2 = bitcast float %1 to i32 @@ -11,17 +11,16 @@ main_body: br i1 %3, label %IF, label %ENDIF IF: ; preds = %main_body - %4 = call float @llvm.AMDGPU.dp4(<4 x float> %0, <4 x float> %0) + %4 = call float @llvm.r600.dot4(<4 x float> %0, <4 x float> %0) br label %ENDIF ENDIF: ; preds = %IF, %main_body %5 = phi float [%4, %IF], [0.000000e+00, %main_body] %6 = insertelement <4 x float> undef, float %5, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %6, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %6, i32 0, i32 0) ret void } -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) attributes #1 = { readnone } -attributes #0 = { "ShaderType"="0" } diff --git a/test/CodeGen/AMDGPU/predicates.ll b/test/CodeGen/AMDGPU/predicates.ll index 0ce74d97ba8e..c1af815c7b1e 100644 --- a/test/CodeGen/AMDGPU/predicates.ll +++ b/test/CodeGen/AMDGPU/predicates.ll @@ -1,27 +1,27 @@ -; RUN: llc < %s -march=r600 -mattr=disable-irstructurizer -mcpu=redwood | FileCheck %s +; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s ; These tests make sure the compiler is optimizing branches using predicates ; when it is legal to do so. -; CHECK: {{^}}simple_if: +; CHECK-LABEL: {{^}}simple_if: ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, ; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel define void @simple_if(i32 addrspace(1)* %out, i32 %in) { entry: - %0 = icmp sgt i32 %in, 0 - br i1 %0, label %IF, label %ENDIF + %cmp0 = icmp sgt i32 %in, 0 + br i1 %cmp0, label %IF, label %ENDIF IF: - %1 = shl i32 %in, 1 + %tmp1 = shl i32 %in, 1 br label %ENDIF ENDIF: - %2 = phi i32 [ %in, %entry ], [ %1, %IF ] - store i32 %2, i32 addrspace(1)* %out + %tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ] + store i32 %tmp2, i32 addrspace(1)* %out ret void } -; CHECK: {{^}}simple_if_else: +; CHECK-LABEL: {{^}}simple_if_else: ; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred, ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel ; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel @@ -44,7 +44,7 @@ ENDIF: ret void } -; CHECK: {{^}}nested_if: +; CHECK-LABEL: {{^}}nested_if: ; CHECK: ALU_PUSH_BEFORE ; CHECK: JUMP ; CHECK: POP @@ -71,7 +71,7 @@ ENDIF: ret void } -; CHECK: {{^}}nested_if_else: +; CHECK-LABEL: {{^}}nested_if_else: ; CHECK: ALU_PUSH_BEFORE ; CHECK: JUMP ; CHECK: POP diff --git a/test/CodeGen/AMDGPU/private-element-size.ll b/test/CodeGen/AMDGPU/private-element-size.ll new file mode 100644 index 000000000000..cd8fb22e620a --- /dev/null +++ b/test/CodeGen/AMDGPU/private-element-size.ll @@ -0,0 +1,252 @@ +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT16 -check-prefix=HSA -check-prefix=HSA-ELT16 -check-prefix=ALL -check-prefix=HSA_ELTGE8 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT8 -check-prefix=HSA -check-prefix=HSA-ELT8 -check-prefix=ALL -check-prefix=HSA-ELTGE8 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=ELT4 -check-prefix=HSA -check-prefix=HSA-ELT4 -check-prefix=ALL %s + + +; ALL-LABEL: {{^}}private_elt_size_v4i32: + +; HSA-ELT16: private_element_size = 3 +; HSA-ELT8: private_element_size = 2 +; HSA-ELT4: private_element_size = 1 + + +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} + +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24 + +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen + + +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:20{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}} + +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +define void @private_elt_size_v4i32(<4 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %idxprom = sext i32 %tid to i64 + %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom + %index.load = load i32, i32 addrspace(1)* %gep.index + %index = and i32 %index.load, 2 + %alloca = alloca [2 x <4 x i32>], align 16 + %gep0 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 1 + store <4 x i32> zeroinitializer, <4 x i32>* %gep0 + store <4 x i32> , <4 x i32>* %gep1 + %gep2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 %index + %load = load <4 x i32>, <4 x i32>* %gep2 + store <4 x i32> %load, <4 x i32> addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}private_elt_size_v8i32: +; HSA-ELT16: private_element_size = 3 +; HSA-ELT8: private_element_size = 2 +; HSA-ELT4: private_element_size = 1 + +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:32 +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:48 + +; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} + + +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:32 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:40 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:48 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:56 + +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen + + +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:20{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:32{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:36{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:40{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:44{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:48{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:52{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:56{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:60{{$}} + +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:20{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24{{$}} +; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}} +define void @private_elt_size_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %idxprom = sext i32 %tid to i64 + %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom + %index.load = load i32, i32 addrspace(1)* %gep.index + %index = and i32 %index.load, 2 + %alloca = alloca [2 x <8 x i32>], align 16 + %gep0 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 1 + store <8 x i32> zeroinitializer, <8 x i32>* %gep0 + store <8 x i32> , <8 x i32>* %gep1 + %gep2 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 %index + %load = load <8 x i32>, <8 x i32>* %gep2 + store <8 x i32> %load, <8 x i32> addrspace(1)* %out + ret void +} + + +; ALL-LABEL: {{^}}private_elt_size_i64: +; HSA-ELT16: private_element_size = 3 +; HSA-ELT8: private_element_size = 2 +; HSA-ELT4: private_element_size = 1 + +; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8 + +; HSA-ELTGE8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen + + +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} + +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +define void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %idxprom = sext i32 %tid to i64 + %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom + %index.load = load i32, i32 addrspace(1)* %gep.index + %index = and i32 %index.load, 2 + %alloca = alloca [2 x i64], align 16 + %gep0 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 1 + store i64 0, i64* %gep0 + store i64 34359738602, i64* %gep1 + %gep2 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 %index + %load = load i64, i64* %gep2 + store i64 %load, i64 addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}private_elt_size_f64: +; HSA-ELT16: private_element_size = 3 +; HSA-ELT8: private_element_size = 2 +; HSA-ELT4: private_element_size = 1 + +; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELTGE8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8 + +; HSA-ELTGE8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen + + +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} + +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +define void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %idxprom = sext i32 %tid to i64 + %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom + %index.load = load i32, i32 addrspace(1)* %gep.index + %index = and i32 %index.load, 2 + %alloca = alloca [2 x double], align 16 + %gep0 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 1 + store double 0.0, double* %gep0 + store double 4.0, double* %gep1 + %gep2 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 %index + %load = load double, double* %gep2 + store double %load, double addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}private_elt_size_v2i64: +; HSA-ELT16: private_element_size = 3 +; HSA-ELT8: private_element_size = 2 +; HSA-ELT4: private_element_size = 1 + +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} + +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16 +; HSA-ELT8-DAG: buffer_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24 + +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen +; HSA-ELT8: buffer_load_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen + + +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:16{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:20{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:24{{$}} +; HSA-ELT4-DAG: buffer_store_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}} + +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:8{{$}} +; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} +define void @private_elt_size_v2i64(<2 x i64> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %idxprom = sext i32 %tid to i64 + %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom + %index.load = load i32, i32 addrspace(1)* %gep.index + %index = and i32 %index.load, 2 + %alloca = alloca [2 x <2 x i64>], align 16 + %gep0 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 1 + store <2 x i64> zeroinitializer, <2 x i64>* %gep0 + store <2 x i64> , <2 x i64>* %gep1 + %gep2 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 %index + %load = load <2 x i64>, <2 x i64>* %gep2 + store <2 x i64> %load, <2 x i64> addrspace(1)* %out + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/private-memory-atomics.ll b/test/CodeGen/AMDGPU/private-memory-atomics.ll index a008ac98a43b..eea10c862238 100644 --- a/test/CodeGen/AMDGPU/private-memory-atomics.ll +++ b/test/CodeGen/AMDGPU/private-memory-atomics.ll @@ -7,11 +7,11 @@ define void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind { entry: %tmp = alloca [2 x i32] - %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 - %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 + %tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 + %tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 store i32 0, i32* %tmp1 store i32 1, i32* %tmp2 - %tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in + %tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel store i32 %tmp4, i32 addrspace(1)* %out ret void @@ -20,11 +20,11 @@ entry: define void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind { entry: %tmp = alloca [2 x i32] - %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 - %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 + %tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 + %tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 store i32 0, i32* %tmp1 store i32 1, i32* %tmp2 - %tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in + %tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic %val = extractvalue { i32, i1 } %tmp4, 0 store i32 %val, i32 addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/private-memory-broken.ll b/test/CodeGen/AMDGPU/private-memory-broken.ll index 6b18a19f1956..8ba0b70dbdbb 100644 --- a/test/CodeGen/AMDGPU/private-memory-broken.ll +++ b/test/CodeGen/AMDGPU/private-memory-broken.ll @@ -1,4 +1,4 @@ -; RUN: not llc -verify-machineinstrs -march=amdgcn -mcpu=SI %s -o /dev/null 2>&1 | FileCheck %s +; RUN: not llc -verify-machineinstrs -march=amdgcn %s -o /dev/null 2>&1 | FileCheck %s ; RUN: not llc -verify-machineinstrs -march=amdgcn -mcpu=tonga %s -o /dev/null 2>&1 | FileCheck %s ; Make sure promote alloca pass doesn't crash diff --git a/test/CodeGen/AMDGPU/private-memory-r600.ll b/test/CodeGen/AMDGPU/private-memory-r600.ll new file mode 100644 index 000000000000..883bdc1ce265 --- /dev/null +++ b/test/CodeGen/AMDGPU/private-memory-r600.ll @@ -0,0 +1,300 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC +; RUN: opt -S -mtriple=r600-unknown-unknown -mcpu=redwood -amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s + +declare i32 @llvm.r600.read.tidig.x() nounwind readnone + +; FUNC-LABEL: {{^}}mova_same_clause: + +; R600: LDS_WRITE +; R600: LDS_WRITE +; R600: LDS_READ +; R600: LDS_READ + +; OPT: call i32 @llvm.r600.read.local.size.y(), !range !0 +; OPT: call i32 @llvm.r600.read.local.size.z(), !range !0 +; OPT: call i32 @llvm.r600.read.tidig.x(), !range !0 +; OPT: call i32 @llvm.r600.read.tidig.y(), !range !0 +; OPT: call i32 @llvm.r600.read.tidig.z(), !range !0 + +define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %2 = load i32, i32* %arrayidx10, align 4 + store i32 %2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; This test checks that the stack offset is calculated correctly for structs. +; All register loads/stores should be optimized away, so there shouldn't be +; any MOVA instructions. +; +; XXX: This generated code has unnecessary MOVs, we should be able to optimize +; this. + +; FUNC-LABEL: {{^}}multiple_structs: +; R600-NOT: MOVA_INT +%struct.point = type { i32, i32 } + +define void @multiple_structs(i32 addrspace(1)* %out) #0 { +entry: + %a = alloca %struct.point + %b = alloca %struct.point + %a.x.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 0 + %a.y.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 1 + %b.x.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 0 + %b.y.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 1 + store i32 0, i32* %a.x.ptr + store i32 1, i32* %a.y.ptr + store i32 2, i32* %b.x.ptr + store i32 3, i32* %b.y.ptr + %a.indirect.ptr = getelementptr inbounds %struct.point, %struct.point* %a, i32 0, i32 0 + %b.indirect.ptr = getelementptr inbounds %struct.point, %struct.point* %b, i32 0, i32 0 + %a.indirect = load i32, i32* %a.indirect.ptr + %b.indirect = load i32, i32* %b.indirect.ptr + %0 = add i32 %a.indirect, %b.indirect + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; Test direct access of a private array inside a loop. The private array +; loads and stores should be lowered to copies, so there shouldn't be any +; MOVA instructions. + +; FUNC-LABEL: {{^}}direct_loop: +; R600-NOT: MOVA_INT + +define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { +entry: + %prv_array_const = alloca [2 x i32] + %prv_array = alloca [2 x i32] + %a = load i32, i32 addrspace(1)* %in + %b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %b = load i32, i32 addrspace(1)* %b_src_ptr + %a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 + store i32 %a, i32* %a_dst_ptr + %b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1 + store i32 %b, i32* %b_dst_ptr + br label %for.body + +for.body: + %inc = phi i32 [0, %entry], [%count, %for.body] + %x_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 + %x = load i32, i32* %x_ptr + %y_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 + %y = load i32, i32* %y_ptr + %xy = add i32 %x, %y + store i32 %xy, i32* %y_ptr + %count = add i32 %inc, 1 + %done = icmp eq i32 %count, 4095 + br i1 %done, label %for.end, label %for.body + +for.end: + %value_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 + %value = load i32, i32* %value_ptr + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}short_array: + +; R600: MOVA_INT +define void @short_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %0 = alloca [2 x i16] + %1 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 0 + %2 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 1 + store i16 0, i16* %1 + store i16 1, i16* %2 + %3 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 %index + %4 = load i16, i16* %3 + %5 = sext i16 %4 to i32 + store i32 %5, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}char_array: + +; R600: MOVA_INT +define void @char_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %0 = alloca [2 x i8] + %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0 + %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1 + store i8 0, i8* %1 + store i8 1, i8* %2 + %3 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 %index + %4 = load i8, i8* %3 + %5 = sext i8 %4 to i32 + store i32 %5, i32 addrspace(1)* %out + ret void + +} + +; Make sure we don't overwrite workitem information with private memory + +; FUNC-LABEL: {{^}}work_item_info: +; R600-NOT: MOV T0.X +; Additional check in case the move ends up in the last slot +; R600-NOT: MOV * TO.X +define void @work_item_info(i32 addrspace(1)* %out, i32 %in) #0 { +entry: + %0 = alloca [2 x i32] + %1 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 0 + %2 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 1 + store i32 0, i32* %1 + store i32 1, i32* %2 + %3 = getelementptr inbounds [2 x i32], [2 x i32]* %0, i32 0, i32 %in + %4 = load i32, i32* %3 + %5 = call i32 @llvm.r600.read.tidig.x() + %6 = add i32 %4, %5 + store i32 %6, i32 addrspace(1)* %out + ret void +} + +; Test that two stack objects are not stored in the same register +; The second stack object should be in T3.X +; FUNC-LABEL: {{^}}no_overlap: +; R600_CHECK: MOV +; R600_CHECK: [[CHAN:[XYZW]]]+ +; R600-NOT: [[CHAN]]+ +define void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 { +entry: + %0 = alloca [3 x i8], align 1 + %1 = alloca [2 x i8], align 1 + %2 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 0 + %3 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 1 + %4 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 2 + %5 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 0 + %6 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 1 + store i8 0, i8* %2 + store i8 1, i8* %3 + store i8 2, i8* %4 + store i8 1, i8* %5 + store i8 0, i8* %6 + %7 = getelementptr inbounds [3 x i8], [3 x i8]* %0, i32 0, i32 %in + %8 = getelementptr inbounds [2 x i8], [2 x i8]* %1, i32 0, i32 %in + %9 = load i8, i8* %7 + %10 = load i8, i8* %8 + %11 = add i8 %9, %10 + %12 = sext i8 %11 to i32 + store i32 %12, i32 addrspace(1)* %out + ret void +} + +define void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i8]] + %gep0 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1 + store i8 0, i8* %gep0 + store i8 1, i8* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index + %load = load i8, i8* %gep2 + %sext = sext i8 %load to i32 + store i32 %sext, i32 addrspace(1)* %out + ret void +} + +define void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i64]] + %gep0 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1 + store i64 0, i64* %gep0 + store i64 1, i64* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index + %load = load i64, i64* %gep2 + store i64 %load, i64 addrspace(1)* %out + ret void +} + +%struct.pair32 = type { i32, i32 } + +define void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x %struct.pair32]] + %gep0 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1 + %gep1 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0 + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x %struct.pair32] + %gep0 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1 + %gep1 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0 + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +define void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind { +entry: + %tmp = alloca [2 x i32] + %tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 + %tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 + store i32 0, i32* %tmp1 + store i32 1, i32* %tmp2 + %cmp = icmp eq i32 %in, 0 + %sel = select i1 %cmp, i32* %tmp1, i32* %tmp2 + %load = load i32, i32* %sel + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it +; finds one, it should stop trying to promote. + +; FUNC-LABEL: ptrtoint: +; SI-NOT: ds_write +; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen +; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; +define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32] + %tmp0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + store i32 5, i32* %tmp0 + %tmp1 = ptrtoint [16 x i32]* %alloca to i32 + %tmp2 = add i32 %tmp1, 5 + %tmp3 = inttoptr i32 %tmp2 to i32* + %tmp4 = getelementptr inbounds i32, i32* %tmp3, i32 %b + %tmp5 = load i32, i32* %tmp4 + store i32 %tmp5, i32 addrspace(1)* %out + ret void +} + +; OPT: !0 = !{i32 0, i32 2048} + +attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="2" } diff --git a/test/CodeGen/AMDGPU/private-memory.ll b/test/CodeGen/AMDGPU/private-memory.ll deleted file mode 100644 index 79778eebd802..000000000000 --- a/test/CodeGen/AMDGPU/private-memory.ll +++ /dev/null @@ -1,325 +0,0 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC -; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE -; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA -; RUN: llc -show-mc-encoding -mattr=+promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -; RUN: llc -show-mc-encoding -mattr=-promote-alloca -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC - -declare i32 @llvm.r600.read.tidig.x() nounwind readnone - -; FUNC-LABEL: {{^}}mova_same_clause: - -; R600: LDS_WRITE -; R600: LDS_WRITE -; R600: LDS_READ -; R600: LDS_READ - -; HSA-PROMOTE: .amd_kernel_code_t -; HSA-PROMOTE: workgroup_group_segment_byte_size = 5120 -; HSA-PROMOTE: .end_amd_kernel_code_t - -; SI-PROMOTE: ds_write_b32 -; SI-PROMOTE: ds_write_b32 -; SI-PROMOTE: ds_read_b32 -; SI-PROMOTE: ds_read_b32 - -; HSA-ALLOCA: .amd_kernel_code_t -; FIXME: Creating the emergency stack slots causes us to over-estimate scratch -; by 4 bytes. -; HSA-ALLOCA: workitem_private_segment_byte_size = 24 -; HSA-ALLOCA: .end_amd_kernel_code_t - -; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 -; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 -define void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { -entry: - %stack = alloca [5 x i32], align 4 - %0 = load i32, i32 addrspace(1)* %in, align 4 - %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 - store i32 4, i32* %arrayidx1, align 4 - %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 - %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 - %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 - store i32 5, i32* %arrayidx3, align 4 - %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 - %2 = load i32, i32* %arrayidx10, align 4 - store i32 %2, i32 addrspace(1)* %out, align 4 - %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 - %3 = load i32, i32* %arrayidx12 - %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 - store i32 %3, i32 addrspace(1)* %arrayidx13 - ret void -} - -; This test checks that the stack offset is calculated correctly for structs. -; All register loads/stores should be optimized away, so there shouldn't be -; any MOVA instructions. -; -; XXX: This generated code has unnecessary MOVs, we should be able to optimize -; this. - -; FUNC-LABEL: {{^}}multiple_structs: -; R600-NOT: MOVA_INT -; SI-NOT: v_movrel -; SI-NOT: v_movrel -%struct.point = type { i32, i32 } - -define void @multiple_structs(i32 addrspace(1)* %out) { -entry: - %a = alloca %struct.point - %b = alloca %struct.point - %a.x.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 - %a.y.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 1 - %b.x.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 - %b.y.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 1 - store i32 0, i32* %a.x.ptr - store i32 1, i32* %a.y.ptr - store i32 2, i32* %b.x.ptr - store i32 3, i32* %b.y.ptr - %a.indirect.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 - %b.indirect.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 - %a.indirect = load i32, i32* %a.indirect.ptr - %b.indirect = load i32, i32* %b.indirect.ptr - %0 = add i32 %a.indirect, %b.indirect - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; Test direct access of a private array inside a loop. The private array -; loads and stores should be lowered to copies, so there shouldn't be any -; MOVA instructions. - -; FUNC-LABEL: {{^}}direct_loop: -; R600-NOT: MOVA_INT -; SI-NOT: v_movrel - -define void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { -entry: - %prv_array_const = alloca [2 x i32] - %prv_array = alloca [2 x i32] - %a = load i32, i32 addrspace(1)* %in - %b_src_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 - %b = load i32, i32 addrspace(1)* %b_src_ptr - %a_dst_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 - store i32 %a, i32* %a_dst_ptr - %b_dst_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1 - store i32 %b, i32* %b_dst_ptr - br label %for.body - -for.body: - %inc = phi i32 [0, %entry], [%count, %for.body] - %x_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 - %x = load i32, i32* %x_ptr - %y_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 - %y = load i32, i32* %y_ptr - %xy = add i32 %x, %y - store i32 %xy, i32* %y_ptr - %count = add i32 %inc, 1 - %done = icmp eq i32 %count, 4095 - br i1 %done, label %for.end, label %for.body - -for.end: - %value_ptr = getelementptr [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 - %value = load i32, i32* %value_ptr - store i32 %value, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}short_array: - -; R600: MOVA_INT - -; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x68,0xe0 -; SI-PROMOTE-DAG: buffer_store_short v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:2 ; encoding: [0x02,0x10,0x68,0xe0 -; SI-PROMOTE: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} -define void @short_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %0 = alloca [2 x i16] - %1 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 0 - %2 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 1 - store i16 0, i16* %1 - store i16 1, i16* %2 - %3 = getelementptr [2 x i16], [2 x i16]* %0, i32 0, i32 %index - %4 = load i16, i16* %3 - %5 = sext i16 %4 to i32 - store i32 %5, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}char_array: - -; R600: MOVA_INT - -; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x60,0xe0 -; SI-DAG: buffer_store_byte v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:1 ; encoding: [0x01,0x10,0x60,0xe0 -define void @char_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %0 = alloca [2 x i8] - %1 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 0 - %2 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 1 - store i8 0, i8* %1 - store i8 1, i8* %2 - %3 = getelementptr [2 x i8], [2 x i8]* %0, i32 0, i32 %index - %4 = load i8, i8* %3 - %5 = sext i8 %4 to i32 - store i32 %5, i32 addrspace(1)* %out - ret void - -} - -; Make sure we don't overwrite workitem information with private memory - -; FUNC-LABEL: {{^}}work_item_info: -; R600-NOT: MOV T0.X -; Additional check in case the move ends up in the last slot -; R600-NOT: MOV * TO.X - -; SI-NOT: v_mov_b32_e{{(32|64)}} v0 -define void @work_item_info(i32 addrspace(1)* %out, i32 %in) { -entry: - %0 = alloca [2 x i32] - %1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 - %2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 - store i32 0, i32* %1 - store i32 1, i32* %2 - %3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in - %4 = load i32, i32* %3 - %5 = call i32 @llvm.r600.read.tidig.x() - %6 = add i32 %4, %5 - store i32 %6, i32 addrspace(1)* %out - ret void -} - -; Test that two stack objects are not stored in the same register -; The second stack object should be in T3.X -; FUNC-LABEL: {{^}}no_overlap: -; R600_CHECK: MOV -; R600_CHECK: [[CHAN:[XYZW]]]+ -; R600-NOT: [[CHAN]]+ -; SI: v_mov_b32_e32 v3 -define void @no_overlap(i32 addrspace(1)* %out, i32 %in) { -entry: - %0 = alloca [3 x i8], align 1 - %1 = alloca [2 x i8], align 1 - %2 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 0 - %3 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 1 - %4 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 2 - %5 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 0 - %6 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 1 - store i8 0, i8* %2 - store i8 1, i8* %3 - store i8 2, i8* %4 - store i8 1, i8* %5 - store i8 0, i8* %6 - %7 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 %in - %8 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 %in - %9 = load i8, i8* %7 - %10 = load i8, i8* %8 - %11 = add i8 %9, %10 - %12 = sext i8 %11 to i32 - store i32 %12, i32 addrspace(1)* %out - ret void -} - -define void @char_array_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %alloca = alloca [2 x [2 x i8]] - %gep0 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0 - %gep1 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1 - store i8 0, i8* %gep0 - store i8 1, i8* %gep1 - %gep2 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index - %load = load i8, i8* %gep2 - %sext = sext i8 %load to i32 - store i32 %sext, i32 addrspace(1)* %out - ret void -} - -define void @i32_array_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %alloca = alloca [2 x [2 x i32]] - %gep0 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 - %gep1 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 - store i32 0, i32* %gep0 - store i32 1, i32* %gep1 - %gep2 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index - %load = load i32, i32* %gep2 - store i32 %load, i32 addrspace(1)* %out - ret void -} - -define void @i64_array_array(i64 addrspace(1)* %out, i32 %index) { -entry: - %alloca = alloca [2 x [2 x i64]] - %gep0 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0 - %gep1 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1 - store i64 0, i64* %gep0 - store i64 1, i64* %gep1 - %gep2 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index - %load = load i64, i64* %gep2 - store i64 %load, i64 addrspace(1)* %out - ret void -} - -%struct.pair32 = type { i32, i32 } - -define void @struct_array_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %alloca = alloca [2 x [2 x %struct.pair32]] - %gep0 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1 - %gep1 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1 - store i32 0, i32* %gep0 - store i32 1, i32* %gep1 - %gep2 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0 - %load = load i32, i32* %gep2 - store i32 %load, i32 addrspace(1)* %out - ret void -} - -define void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) { -entry: - %alloca = alloca [2 x %struct.pair32] - %gep0 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1 - %gep1 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0 - store i32 0, i32* %gep0 - store i32 1, i32* %gep1 - %gep2 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0 - %load = load i32, i32* %gep2 - store i32 %load, i32 addrspace(1)* %out - ret void -} - -define void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind { -entry: - %tmp = alloca [2 x i32] - %tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 - %tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 - store i32 0, i32* %tmp1 - store i32 1, i32* %tmp2 - %cmp = icmp eq i32 %in, 0 - %sel = select i1 %cmp, i32* %tmp1, i32* %tmp2 - %load = load i32, i32* %sel - store i32 %load, i32 addrspace(1)* %out - ret void -} - -; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it -; finds one, it should stop trying to promote. - -; FUNC-LABEL: ptrtoint: -; SI-NOT: ds_write -; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen -; SI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; -define void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) { - %alloca = alloca [16 x i32] - %tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a - store i32 5, i32* %tmp0 - %tmp1 = ptrtoint [16 x i32]* %alloca to i32 - %tmp2 = add i32 %tmp1, 5 - %tmp3 = inttoptr i32 %tmp2 to i32* - %tmp4 = getelementptr i32, i32* %tmp3, i32 %b - %tmp5 = load i32, i32* %tmp4 - store i32 %tmp5, i32 addrspace(1)* %out - ret void -} diff --git a/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll b/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll new file mode 100644 index 000000000000..3bd0aecf7aa9 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-array-allocation.ll @@ -0,0 +1,50 @@ +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s + +; Make sure this allocates the correct size if the alloca has a non-0 +; number of elements. + +; CHECK-LABEL: @array_alloca( +; CHECK: %stack = alloca i32, i32 5, align 4 +define void @array_alloca(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { +entry: + %stack = alloca i32, i32 5, align 4 + %ld0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %stack, i32 %ld0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds i32, i32* %stack, i32 0 + %ld2 = load i32, i32* %arrayidx10, align 4 + store i32 %ld2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds i32, i32* %stack, i32 1 + %ld3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %ld3, i32 addrspace(1)* %arrayidx13 + ret void +} + +; CHECK-LABEL: @array_alloca_dynamic( +; CHECK: %stack = alloca i32, i32 %size, align 4 +define void @array_alloca_dynamic(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %size) #0 { +entry: + %stack = alloca i32, i32 %size, align 4 + %ld0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds i32, i32* %stack, i32 %ld0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %ld1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds i32, i32* %stack, i32 %ld1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds i32, i32* %stack, i32 0 + %ld2 = load i32, i32* %arrayidx10, align 4 + store i32 %ld2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds i32, i32* %stack, i32 1 + %ld3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %ld3, i32 addrspace(1)* %arrayidx13 + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll b/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll index 10739df08379..82030f377d9f 100644 --- a/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll +++ b/test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll @@ -6,13 +6,14 @@ declare void @foo(float*) #0 declare void @foo.varargs(...) #0 -; CHECK: error: unsupported call to function foo in crash_call_constexpr_cast +; CHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo define void @crash_call_constexpr_cast() #0 { %alloca = alloca i32 call void bitcast (void (float*)* @foo to void (i32*)*)(i32* %alloca) #0 ret void } +; CHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo.varargs define void @crash_call_constexpr_cast_varargs() #0 { %alloca = alloca i32 call void bitcast (void (...)* @foo.varargs to void (i32*)*)(i32* %alloca) #0 diff --git a/test/CodeGen/AMDGPU/promote-alloca-globals.ll b/test/CodeGen/AMDGPU/promote-alloca-globals.ll new file mode 100644 index 000000000000..eb0d0cc62697 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-globals.ll @@ -0,0 +1,35 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s +; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s + + +@global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4 +@global_array1 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4 + +; IR-LABEL: define void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +; IR: alloca [10 x i32] +; ASM-LABEL: {{^}}promote_alloca_size_256: +; ASM: ; LDSByteSize: 60000 bytes/workgroup (compile time only) + +define void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +entry: + %stack = alloca [10 x i32], align 4 + %tmp = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 0 + %tmp2 = load i32, i32* %arrayidx10, align 4 + store i32 %tmp2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 1 + %tmp3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp3, i32 addrspace(1)* %arrayidx13 + %v0 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array0, i32 0, i32 0, i32 0 + store i32 %tmp3, i32 addrspace(3)* %v0 + %v1 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array1, i32 0, i32 0, i32 0 + store i32 %tmp3, i32 addrspace(3)* %v1 + ret void +} diff --git a/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll b/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll new file mode 100644 index 000000000000..6a9ec31696d2 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-invariant-markers.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=amdgcn -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare {}* @llvm.invariant.start(i64, i8* nocapture) #0 +declare void @llvm.invariant.end({}*, i64, i8* nocapture) #0 +declare i8* @llvm.invariant.group.barrier(i8*) #1 + +; GCN-LABEL: {{^}}use_invariant_promotable_lds: +; GCN: buffer_load_dword +; GCN: ds_write_b32 +define void @use_invariant_promotable_lds(i32 addrspace(1)* %arg) #2 { +bb: + %tmp = alloca i32, align 4 + %tmp1 = bitcast i32* %tmp to i8* + %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 + %tmp3 = load i32, i32 addrspace(1)* %tmp2 + store i32 %tmp3, i32* %tmp + %tmp4 = call {}* @llvm.invariant.start(i64 4, i8* %tmp1) #0 + call void @llvm.invariant.end({}* %tmp4, i64 4, i8* %tmp1) #0 + %tmp5 = call i8* @llvm.invariant.group.barrier(i8* %tmp1) #1 + ret void +} + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll b/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll new file mode 100644 index 000000000000..eeda19fa27ac --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-lifetime.ll @@ -0,0 +1,24 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca %s | FileCheck -check-prefix=OPT %s + +declare void @llvm.lifetime.start(i64, i8* nocapture) #0 +declare void @llvm.lifetime.end(i64, i8* nocapture) #0 + +; OPT-LABEL: @use_lifetime_promotable_lds( +; OPT-NOT: alloca i32 +; OPT-NOT: llvm.lifetime +; OPT: store i32 %tmp3, i32 addrspace(3)* +define void @use_lifetime_promotable_lds(i32 addrspace(1)* %arg) #2 { +bb: + %tmp = alloca i32, align 4 + %tmp1 = bitcast i32* %tmp to i8* + call void @llvm.lifetime.start(i64 4, i8* %tmp1) + %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 + %tmp3 = load i32, i32 addrspace(1)* %tmp2 + store i32 %tmp3, i32* %tmp + call void @llvm.lifetime.end(i64 4, i8* %tmp1) + ret void +} + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll b/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll new file mode 100644 index 000000000000..01ecb638b033 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-mem-intrinsics.ll @@ -0,0 +1,65 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s + +declare void @llvm.memcpy.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0 +declare void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0 + +declare void @llvm.memmove.p0i8.p1i8.i32(i8* nocapture, i8 addrspace(1)* nocapture, i32, i32, i1) #0 +declare void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* nocapture, i8* nocapture, i32, i32, i1) #0 + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 + +declare i32 @llvm.objectsize.i32.p0i8(i8*, i1) #1 + +; CHECK-LABEL: @promote_with_memcpy( +; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memcpy.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: call void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) +; CHECK: call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false) +define void @promote_with_memcpy(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %alloca = alloca [17 x i32], align 4 + %alloca.bc = bitcast [17 x i32]* %alloca to i8* + %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* + %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* + call void @llvm.memcpy.p0i8.p1i8.i32(i8* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) + call void @llvm.memcpy.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8* %alloca.bc, i32 68, i32 4, i1 false) + ret void +} + +; CHECK-LABEL: @promote_with_memmove( +; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memmove.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: call void @llvm.memmove.p3i8.p1i8.i32(i8 addrspace(3)* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) +; CHECK: call void @llvm.memmove.p1i8.p3i8.i32(i8 addrspace(1)* %out.bc, i8 addrspace(3)* %alloca.bc, i32 68, i32 4, i1 false) +define void @promote_with_memmove(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %alloca = alloca [17 x i32], align 4 + %alloca.bc = bitcast [17 x i32]* %alloca to i8* + %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* + %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* + call void @llvm.memmove.p0i8.p1i8.i32(i8* %alloca.bc, i8 addrspace(1)* %in.bc, i32 68, i32 4, i1 false) + call void @llvm.memmove.p1i8.p0i8.i32(i8 addrspace(1)* %out.bc, i8* %alloca.bc, i32 68, i32 4, i1 false) + ret void +} + +; CHECK-LABEL: @promote_with_memset( +; CHECK: getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_memset.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: call void @llvm.memset.p3i8.i32(i8 addrspace(3)* %alloca.bc, i8 7, i32 68, i32 4, i1 false) +define void @promote_with_memset(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { + %alloca = alloca [17 x i32], align 4 + %alloca.bc = bitcast [17 x i32]* %alloca to i8* + %in.bc = bitcast i32 addrspace(1)* %in to i8 addrspace(1)* + %out.bc = bitcast i32 addrspace(1)* %out to i8 addrspace(1)* + call void @llvm.memset.p0i8.i32(i8* %alloca.bc, i8 7, i32 68, i32 4, i1 false) + ret void +} + +; CHECK-LABEL: @promote_with_objectsize( +; CHECK: [[PTR:%[0-9]+]] = getelementptr inbounds [64 x [17 x i32]], [64 x [17 x i32]] addrspace(3)* @promote_with_objectsize.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %alloca.bc, i1 false) +define void @promote_with_objectsize(i32 addrspace(1)* %out) #0 { + %alloca = alloca [17 x i32], align 4 + %alloca.bc = bitcast [17 x i32]* %alloca to i8* + %size = call i32 @llvm.objectsize.i32.p0i8(i8* %alloca.bc, i1 false) + store i32 %size, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" "amdgpu-max-waves-per-eu"="3" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll b/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll new file mode 100644 index 000000000000..7c5a5182bc8e --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll @@ -0,0 +1,38 @@ +; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s +; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s + +; ALL-LABEL: {{^}}promote_alloca_i32_array_array: +; NOOPTS: workgroup_group_segment_byte_size = 0{{$}} +; NOOPTS-NOT ds_write +; OPTS: ds_write +define void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array: +; ALL: workgroup_group_segment_byte_size = 0{{$}} +; ALL-NOT ds_write +define void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 { +entry: + %alloca = alloca [2 x [2 x i32]] + %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 + %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 + store i32 0, i32* %gep0 + store i32 1, i32* %gep1 + %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index + %load = load i32, i32* %gep2 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" } +attributes #1 = { nounwind optnone noinline "amdgpu-max-work-group-size"="64" } diff --git a/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll b/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll new file mode 100644 index 000000000000..46fe307a17fe --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll @@ -0,0 +1,130 @@ +; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=GCN %s + +; This shows that the amount of LDS estimate is sensitive to the order +; of the LDS globals. + +; Both of these functions use the same amount of LDS, but the total +; changes depending on the visit order of first use. + +; The one with the suboptimal order resulting in extra padding exceeds +; the desired limit + +; The padding estimate heuristic used by the promote alloca pass +; is mostly determined by the order of the globals, + +; Raw usage = 1060 bytes +; Rounded usage: +; 292 + (4 pad) + 256 + (8 pad) + 512 = 1072 +; 512 + (0 pad) + 256 + (0 pad) + 292 = 1060 + +; At default occupancy guess of 7, 2340 bytes available total. + +; 1280 need to be left to promote alloca +; optimally packed, this requires + + +@lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] undef, align 16 +@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8 +@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4 + + +; GCN-LABEL: {{^}}promote_alloca_size_order_0: +; GCN: workgroup_group_segment_byte_size = 2340 +define void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %tmp2 = load i32, i32* %arrayidx10, align 4 + store i32 %tmp2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %tmp3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp3, i32 addrspace(1)* %arrayidx13 + + %gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx + store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4 + + %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx + store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8 + + %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx + store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16 + + ret void +} + +; GCN-LABEL: {{^}}promote_alloca_size_order_1: +; GCN: workgroup_group_segment_byte_size = 2352 +define void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %tmp2 = load i32, i32* %arrayidx10, align 4 + store i32 %tmp2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %tmp3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp3, i32 addrspace(1)* %arrayidx13 + + %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx + store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16 + + %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx + store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8 + + %gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx + store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4 + + ret void +} + +@lds3 = internal unnamed_addr addrspace(3) global [13 x i32] undef, align 4 +@lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] undef, align 16 + +; The guess from the alignment padding pushes this over the determined +; size limit, so it isn't promoted + +; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit: +; GCN: workgroup_group_segment_byte_size = 1060 +define void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %tmp2 = load i32, i32* %arrayidx10, align 4 + store i32 %tmp2, i32 addrspace(1)* %out, align 4 + %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %tmp3 = load i32, i32* %arrayidx12 + %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp3, i32 addrspace(1)* %arrayidx13 + + %gep.lds3 = getelementptr inbounds [13 x i32], [13 x i32] addrspace(3)* @lds3, i32 0, i32 %idx + store volatile i32 0, i32 addrspace(3)* %gep.lds3, align 4 + + %gep.lds4 = getelementptr inbounds [63 x <4 x i32>], [63 x <4 x i32>] addrspace(3)* @lds4, i32 0, i32 %idx + store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds4, align 16 + + ret void +} + +attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" } diff --git a/test/CodeGen/AMDGPU/promote-alloca-shaders.ll b/test/CodeGen/AMDGPU/promote-alloca-shaders.ll new file mode 100644 index 000000000000..d40fca9f4fd5 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-shaders.ll @@ -0,0 +1,29 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s +; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s + +; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { +; IR: alloca [5 x i32] +; ASM-LABEL: {{^}}promote_alloca_shaders: +; ASM: ; LDSByteSize: 0 bytes/workgroup (compile time only) + +define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp0 = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 + store i32 4, i32* %arrayidx1, align 4 + %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 + %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 + %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 + store i32 5, i32* %arrayidx3, align 4 + %arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 + %tmp2 = load i32, i32* %arrayidx4, align 4 + store i32 %tmp2, i32 addrspace(1)* %out, align 4 + %arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 + %tmp3 = load i32, i32* %arrayidx5 + %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 + store i32 %tmp3, i32 addrspace(1)* %arrayidx6 + ret void +} + +attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" } diff --git a/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll b/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll index 2ee98cc3d2d2..307eca712cc8 100644 --- a/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll +++ b/test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; Pointer value is stored in a candidate for LDS usage. @@ -11,6 +12,18 @@ define void @stored_lds_pointer_value(float* addrspace(1)* %ptr) #0 { ret void } +; GCN-LABEL: {{^}}stored_lds_pointer_value_offset: +; GCN: buffer_store_dword v +define void @stored_lds_pointer_value_offset(float* addrspace(1)* %ptr) #0 { + %tmp0 = alloca float + %tmp1 = alloca float + store float 0.0, float *%tmp0 + store float 0.0, float *%tmp1 + store volatile float* %tmp0, float* addrspace(1)* %ptr + store volatile float* %tmp1, float* addrspace(1)* %ptr + ret void +} + ; GCN-LABEL: {{^}}stored_lds_pointer_value_gep: ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 @@ -36,17 +49,27 @@ bb: define void @stored_vector_pointer_value(i32* addrspace(1)* %out, i32 %index) { entry: %tmp0 = alloca [4 x i32] - %x = getelementptr [4 x i32], [4 x i32]* %tmp0, i32 0, i32 0 - %y = getelementptr [4 x i32], [4 x i32]* %tmp0, i32 0, i32 1 - %z = getelementptr [4 x i32], [4 x i32]* %tmp0, i32 0, i32 2 - %w = getelementptr [4 x i32], [4 x i32]* %tmp0, i32 0, i32 3 + %x = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 0 + %y = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 1 + %z = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 2 + %w = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 3 store i32 0, i32* %x store i32 1, i32* %y store i32 2, i32* %z store i32 3, i32* %w - %tmp1 = getelementptr [4 x i32], [4 x i32]* %tmp0, i32 0, i32 %index + %tmp1 = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 %index store i32* %tmp1, i32* addrspace(1)* %out ret void } +; GCN-LABEL: {{^}}stored_fi_to_self: +; GCN-NOT: ds_ +define void @stored_fi_to_self() #0 { + %tmp = alloca i32* + store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp + %bitcast = bitcast i32** %tmp to i32* + store volatile i32* %bitcast, i32** %tmp + ret void +} + attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll b/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll new file mode 100644 index 000000000000..857e547aa03b --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-to-lds-icmp.ll @@ -0,0 +1,64 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s + +; This normally would be fixed by instcombine to be compare to the GEP +; indices + +; CHECK-LABEL: @lds_promoted_alloca_icmp_same_derived_pointer( +; CHECK: [[ARRAYGEP:%[0-9]+]] = getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promoted_alloca_icmp_same_derived_pointer.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a +; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %b +; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, %ptr1 +define void @lds_promoted_alloca_icmp_same_derived_pointer(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %b + %cmp = icmp eq i32* %ptr0, %ptr1 + %zext = zext i1 %cmp to i32 + store volatile i32 %zext, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @lds_promoted_alloca_icmp_null_rhs( +; CHECK: [[ARRAYGEP:%[0-9]+]] = getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promoted_alloca_icmp_null_rhs.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a +; CHECK: %cmp = icmp eq i32 addrspace(3)* %ptr0, null +define void @lds_promoted_alloca_icmp_null_rhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %cmp = icmp eq i32* %ptr0, null + %zext = zext i1 %cmp to i32 + store volatile i32 %zext, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @lds_promoted_alloca_icmp_null_lhs( +; CHECK: [[ARRAYGEP:%[0-9]+]] = getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promoted_alloca_icmp_null_lhs.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a +; CHECK: %cmp = icmp eq i32 addrspace(3)* null, %ptr0 +define void @lds_promoted_alloca_icmp_null_lhs(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %cmp = icmp eq i32* null, %ptr0 + %zext = zext i1 %cmp to i32 + store volatile i32 %zext, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @lds_promoted_alloca_icmp_unknown_ptr( +; CHECK: %alloca = alloca [16 x i32], align 4 +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a +; CHECK: %ptr1 = call i32* @get_unknown_pointer() +; CHECK: %cmp = icmp eq i32* %ptr0, %ptr1 +define void @lds_promoted_alloca_icmp_unknown_ptr(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %ptr1 = call i32* @get_unknown_pointer() + %cmp = icmp eq i32* %ptr0, %ptr1 + %zext = zext i1 %cmp to i32 + store volatile i32 %zext, i32 addrspace(1)* %out + ret void +} + +declare i32* @get_unknown_pointer() #0 + +attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="1" } diff --git a/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll b/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll new file mode 100644 index 000000000000..a0ad564a6c8f --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-to-lds-phi.ll @@ -0,0 +1,204 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s + + +; CHECK-LABEL: @branch_ptr_var_same_alloca( +; CHECK: getelementptr inbounds [256 x [64 x i32]], [256 x [64 x i32]] addrspace(3)* @branch_ptr_var_same_alloca.alloca, i32 0, i32 %{{[0-9]+}} + +; CHECK: if: +; CHECK: %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(3)* %{{[0-9]+}}, i32 0, i32 %a + +; CHECK: else: +; CHECK: %arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(3)* %15, i32 0, i32 %b + +; CHECK: endif: +; CHECK: %phi.ptr = phi i32 addrspace(3)* [ %arrayidx0, %if ], [ %arrayidx1, %else ] +; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4 +define void @branch_ptr_var_same_alloca(i32 %a, i32 %b) #0 { +entry: + %alloca = alloca [64 x i32], align 4 + br i1 undef, label %if, label %else + +if: + %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + br label %endif + +else: + %arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %b + br label %endif + +endif: + %phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] + store i32 0, i32* %phi.ptr, align 4 + ret void +} + +; CHECK-LABEL: @branch_ptr_phi_alloca_null_0( +; CHECK: %phi.ptr = phi i32 addrspace(3)* [ %arrayidx0, %if ], [ null, %entry ] +define void @branch_ptr_phi_alloca_null_0(i32 %a, i32 %b) #0 { +entry: + %alloca = alloca [64 x i32], align 4 + br i1 undef, label %if, label %endif + +if: + %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + br label %endif + +endif: + %phi.ptr = phi i32* [ %arrayidx0, %if ], [ null, %entry ] + store i32 0, i32* %phi.ptr, align 4 + ret void +} + +; CHECK-LABEL: @branch_ptr_phi_alloca_null_1( +; CHECK: %phi.ptr = phi i32 addrspace(3)* [ null, %entry ], [ %arrayidx0, %if ] +define void @branch_ptr_phi_alloca_null_1(i32 %a, i32 %b) #0 { +entry: + %alloca = alloca [64 x i32], align 4 + br i1 undef, label %if, label %endif + +if: + %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + br label %endif + +endif: + %phi.ptr = phi i32* [ null, %entry ], [ %arrayidx0, %if ] + store i32 0, i32* %phi.ptr, align 4 + ret void +} + +; CHECK-LABEL: @one_phi_value( +; CHECK: getelementptr inbounds [256 x [64 x i32]], [256 x [64 x i32]] addrspace(3)* @one_phi_value.alloca, i32 0, i32 %14 +; CHECK: %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(3)* %{{[0-9]+}}, i32 0, i32 %a + +; CHECK: br label %exit +; CHECK: %phi.ptr = phi i32 addrspace(3)* [ %arrayidx0, %entry ] +; CHECK: store i32 0, i32 addrspace(3)* %phi.ptr, align 4 +define void @one_phi_value(i32 %a) #0 { +entry: + %alloca = alloca [64 x i32], align 4 + %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + br label %exit + +exit: + %phi.ptr = phi i32* [ %arrayidx0, %entry ] + store i32 0, i32* %phi.ptr, align 4 + ret void +} + +; CHECK-LABEL: @branch_ptr_alloca_unknown_obj( +; CHECK: %alloca = alloca [64 x i32], align 4 + +; CHECK: if: +; CHECK: %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + +; CHECK: else: +; CHECK: %arrayidx1 = call i32* @get_unknown_pointer() + +; CHECK: endif: +; CHECK: %phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] +; CHECK: store i32 0, i32* %phi.ptr, align 4 +define void @branch_ptr_alloca_unknown_obj(i32 %a, i32 %b) #0 { +entry: + %alloca = alloca [64 x i32], align 4 + br i1 undef, label %if, label %else + +if: + %arrayidx0 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 %a + br label %endif + +else: + %arrayidx1 = call i32* @get_unknown_pointer() + br label %endif + +endif: + %phi.ptr = phi i32* [ %arrayidx0, %if ], [ %arrayidx1, %else ] + store i32 0, i32* %phi.ptr, align 4 + ret void +} + +; kernel void ptr_induction_var_same_alloca(void) +; { +; int alloca[64]; +; int i = 0; + +; #pragma nounroll +; for (int* p = &alloca[2], *e = &alloca[48]; p != e; ++p, ++i) +; { +; *p = i; +; } +; } + +; FIXME: This should be promotable. We need to use +; GetUnderlyingObjects when looking at the icmp user. + +; CHECK-LABEL: @ptr_induction_var_same_alloca( +; CHECK: %alloca = alloca [64 x i32], align 4 +; CHECK: phi i32* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ] +define void @ptr_induction_var_same_alloca() #0 { +entry: + %alloca = alloca [64 x i32], align 4 + %arrayidx = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 2 + %arrayidx1 = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 48 + br label %for.body + +for.cond.cleanup: ; preds = %for.body + ret void + +for.body: ; preds = %for.body, %entry + %i.09 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + %p.08 = phi i32* [ %arrayidx, %entry ], [ %incdec.ptr, %for.body ] + store i32 %i.09, i32* %p.08, align 4 + %incdec.ptr = getelementptr inbounds i32, i32* %p.08, i32 1 + %inc = add nuw nsw i32 %i.09, 1 + %cmp = icmp eq i32* %incdec.ptr, %arrayidx1 + br i1 %cmp, label %for.cond.cleanup, label %for.body +} + + +; extern int* get_unknown_pointer(void); + +; kernel void ptr_induction_var_alloca_unknown(void) +; { +; int alloca[64]; +; int i = 0; +; +; for (int* p = &alloca[2], *e = get_unknown_pointer(); p != e; ++p, ++i) +; { +; *p = i; +; } +; } + +; CHECK-LABEL: @ptr_induction_var_alloca_unknown( +; CHECK: %alloca = alloca [64 x i32], align 4 +; CHECK: %p.08 = phi i32* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ] +; CHECK: %cmp = icmp eq i32* %incdec.ptr, %call +define void @ptr_induction_var_alloca_unknown() #0 { +entry: + %alloca = alloca [64 x i32], align 4 + %arrayidx = getelementptr inbounds [64 x i32], [64 x i32]* %alloca, i32 0, i32 2 + %call = tail call i32* @get_unknown_pointer() #2 + %cmp.7 = icmp eq i32* %arrayidx, %call + br i1 %cmp.7, label %for.cond.cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + ret void + +for.body: ; preds = %for.body, %for.body.preheader + %i.09 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %p.08 = phi i32* [ %incdec.ptr, %for.body ], [ %arrayidx, %for.body.preheader ] + store i32 %i.09, i32* %p.08, align 4 + %incdec.ptr = getelementptr inbounds i32, i32* %p.08, i32 1 + %inc = add nuw nsw i32 %i.09, 1 + %cmp = icmp eq i32* %incdec.ptr, %call + br i1 %cmp, label %for.cond.cleanup.loopexit, label %for.body +} + +declare i32* @get_unknown_pointer() #0 + +attributes #0 = { nounwind "amdgpu-max-waves-per-eu"="1" } diff --git a/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll new file mode 100644 index 000000000000..bb13adb19852 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-to-lds-select.ll @@ -0,0 +1,133 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck %s + +; CHECK-LABEL: @lds_promoted_alloca_select_invalid_pointer_operand( +; CHECK: %alloca = alloca i32 +; CHECK: select i1 undef, i32* undef, i32* %alloca +define void @lds_promoted_alloca_select_invalid_pointer_operand() #0 { + %alloca = alloca i32, align 4 + %select = select i1 undef, i32* undef, i32* %alloca + store i32 0, i32* %select, align 4 + ret void +} + +; CHECK-LABEL: @lds_promote_alloca_select_two_derived_pointers( +; CHECK: [[ARRAYGEP:%[0-9]+]] = getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promote_alloca_select_two_derived_pointers.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %a +; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 %b +; CHECK: %select = select i1 undef, i32 addrspace(3)* %ptr0, i32 addrspace(3)* %ptr1 +; CHECK: store i32 0, i32 addrspace(3)* %select, align 4 +define void @lds_promote_alloca_select_two_derived_pointers(i32 %a, i32 %b) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %b + %select = select i1 undef, i32* %ptr0, i32* %ptr1 + store i32 0, i32* %select, align 4 + ret void +} + +; FIXME: This should be promotable but requires knowing that both will be promoted first. + +; CHECK-LABEL: @lds_promote_alloca_select_two_allocas( +; CHECK: %alloca0 = alloca i32, i32 16, align 4 +; CHECK: %alloca1 = alloca i32, i32 16, align 4 +; CHECK: %ptr0 = getelementptr inbounds i32, i32* %alloca0, i32 %a +; CHECK: %ptr1 = getelementptr inbounds i32, i32* %alloca1, i32 %b +; CHECK: %select = select i1 undef, i32* %ptr0, i32* %ptr1 +define void @lds_promote_alloca_select_two_allocas(i32 %a, i32 %b) #0 { + %alloca0 = alloca i32, i32 16, align 4 + %alloca1 = alloca i32, i32 16, align 4 + %ptr0 = getelementptr inbounds i32, i32* %alloca0, i32 %a + %ptr1 = getelementptr inbounds i32, i32* %alloca1, i32 %b + %select = select i1 undef, i32* %ptr0, i32* %ptr1 + store i32 0, i32* %select, align 4 + ret void +} + +; TODO: Maybe this should be canonicalized to select on the constant and GEP after. +; CHECK-LABEL: @lds_promote_alloca_select_two_derived_constant_pointers( +; CHECK: [[ARRAYGEP:%[0-9]+]] = getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promote_alloca_select_two_derived_constant_pointers.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 1 +; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* [[ARRAYGEP]], i32 0, i32 3 +; CHECK: %select = select i1 undef, i32 addrspace(3)* %ptr0, i32 addrspace(3)* %ptr1 +; CHECK: store i32 0, i32 addrspace(3)* %select, align 4 +define void @lds_promote_alloca_select_two_derived_constant_pointers() #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 1 + %ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 3 + %select = select i1 undef, i32* %ptr0, i32* %ptr1 + store i32 0, i32* %select, align 4 + ret void +} + +; CHECK-LABEL: @lds_promoted_alloca_select_input_select( +; CHECK: getelementptr inbounds [256 x [16 x i32]], [256 x [16 x i32]] addrspace(3)* @lds_promoted_alloca_select_input_select.alloca, i32 0, i32 %{{[0-9]+}} +; CHECK: %ptr0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %{{[0-9]+}}, i32 0, i32 %a +; CHECK: %ptr1 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %{{[0-9]+}}, i32 0, i32 %b +; CHECK: %ptr2 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(3)* %{{[0-9]+}}, i32 0, i32 %c +; CHECK: %select0 = select i1 undef, i32 addrspace(3)* %ptr0, i32 addrspace(3)* %ptr1 +; CHECK: %select1 = select i1 undef, i32 addrspace(3)* %select0, i32 addrspace(3)* %ptr2 +; CHECK: store i32 0, i32 addrspace(3)* %select1, align 4 +define void @lds_promoted_alloca_select_input_select(i32 %a, i32 %b, i32 %c) #0 { + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %b + %ptr2 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %c + %select0 = select i1 undef, i32* %ptr0, i32* %ptr1 + %select1 = select i1 undef, i32* %select0, i32* %ptr2 + store i32 0, i32* %select1, align 4 + ret void +} + +define void @lds_promoted_alloca_select_input_phi(i32 %a, i32 %b, i32 %c) #0 { +entry: + %alloca = alloca [16 x i32], align 4 + %ptr0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a + %ptr1 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %b + store i32 0, i32* %ptr0 + br i1 undef, label %bb1, label %bb2 + +bb1: + %ptr2 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %c + %select0 = select i1 undef, i32* undef, i32* %ptr2 + store i32 0, i32* %ptr1 + br label %bb2 + +bb2: + %phi.ptr = phi i32* [ %ptr0, %entry ], [ %select0, %bb1 ] + %select1 = select i1 undef, i32* %phi.ptr, i32* %ptr1 + store i32 0, i32* %select1, align 4 + ret void +} + +; CHECK-LABEL: @select_null_rhs( +; CHECK-NOT: alloca +; CHECK: select i1 %tmp2, double addrspace(3)* %{{[0-9]+}}, double addrspace(3)* null +define void @select_null_rhs(double addrspace(1)* nocapture %arg, i32 %arg1) #1 { +bb: + %tmp = alloca double, align 8 + store double 0.000000e+00, double* %tmp, align 8 + %tmp2 = icmp eq i32 %arg1, 0 + %tmp3 = select i1 %tmp2, double* %tmp, double* null + store double 1.000000e+00, double* %tmp3, align 8 + %tmp4 = load double, double* %tmp, align 8 + store double %tmp4, double addrspace(1)* %arg + ret void +} + +; CHECK-LABEL: @select_null_lhs( +; CHECK-NOT: alloca +; CHECK: select i1 %tmp2, double addrspace(3)* null, double addrspace(3)* %{{[0-9]+}} +define void @select_null_lhs(double addrspace(1)* nocapture %arg, i32 %arg1) #1 { +bb: + %tmp = alloca double, align 8 + store double 0.000000e+00, double* %tmp, align 8 + %tmp2 = icmp eq i32 %arg1, 0 + %tmp3 = select i1 %tmp2, double* null, double* %tmp + store double 1.000000e+00, double* %tmp3, align 8 + %tmp4 = load double, double* %tmp, align 8 + store double %tmp4, double addrspace(1)* %arg + ret void +} + +attributes #0 = { norecurse nounwind "amdgpu-max-waves-per-eu"="1" } +attributes #1 = { norecurse nounwind } \ No newline at end of file diff --git a/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll b/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll new file mode 100644 index 000000000000..e331731f90f6 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-unhandled-intrinsic.ll @@ -0,0 +1,24 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s + +; This is just an arbitrary intrinisic that shouldn't ever need to be +; handled to ensure it doesn't crash. + +declare void @llvm.stackrestore(i8*) #2 + +; CHECK-LABEL: @try_promote_unhandled_intrinsic( +; CHECK: alloca +; CHECK: call void @llvm.stackrestore(i8* %tmp1) +define void @try_promote_unhandled_intrinsic(i32 addrspace(1)* %arg) #2 { +bb: + %tmp = alloca i32, align 4 + %tmp1 = bitcast i32* %tmp to i8* + %tmp2 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1 + %tmp3 = load i32, i32 addrspace(1)* %tmp2 + store i32 %tmp3, i32* %tmp + call void @llvm.stackrestore(i8* %tmp1) + ret void +} + +attributes #0 = { argmemonly nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AMDGPU/promote-alloca-volatile.ll b/test/CodeGen/AMDGPU/promote-alloca-volatile.ll new file mode 100644 index 000000000000..f9de38839bc5 --- /dev/null +++ b/test/CodeGen/AMDGPU/promote-alloca-volatile.ll @@ -0,0 +1,45 @@ +; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-promote-alloca < %s | FileCheck %s + +; CHECK-LABEL: @volatile_load( +; CHECK: alloca [5 x i32] +; CHECK load volatile i32, i32* +define void @volatile_load(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +entry: + %stack = alloca [5 x i32], align 4 + %tmp = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp + %load = load volatile i32, i32* %arrayidx1 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: @volatile_store( +; CHECK: alloca [5 x i32] +; CHECK store volatile i32 %tmp, i32* +define void @volatile_store(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { +entry: + %stack = alloca [5 x i32], align 4 + %tmp = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp + store volatile i32 %tmp, i32* %arrayidx1 + ret void +} + +; Has on OK non-volatile user but also a volatile user +; CHECK-LABEL: @volatile_and_non_volatile_load( +; CHECK: alloca double +; CHECK: load double +; CHECK: load volatile double +define void @volatile_and_non_volatile_load(double addrspace(1)* nocapture %arg, i32 %arg1) #0 { +bb: + %tmp = alloca double, align 8 + store double 0.000000e+00, double* %tmp, align 8 + + %tmp4 = load double, double* %tmp, align 8 + %tmp5 = load volatile double, double* %tmp, align 8 + + store double %tmp4, double addrspace(1)* %arg + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/pv-packing.ll b/test/CodeGen/AMDGPU/pv-packing.ll index abeae563ff3f..b01c00daede3 100644 --- a/test/CodeGen/AMDGPU/pv-packing.ll +++ b/test/CodeGen/AMDGPU/pv-packing.ll @@ -3,7 +3,7 @@ ;CHECK: DOT4 T{{[0-9]\.X}} ;CHECK: MULADD_IEEE * T{{[0-9]\.W}} -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -16,7 +16,7 @@ main_body: %8 = extractelement <4 x float> %reg3, i32 2 %9 = load <4 x float>, <4 x float> addrspace(8)* null %10 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 1) - %11 = call float @llvm.AMDGPU.dp4(<4 x float> %9, <4 x float> %9) + %11 = call float @llvm.r600.dot4(<4 x float> %9, <4 x float> %9) %12 = fmul float %0, %3 %13 = fadd float %12, %6 %14 = fmul float %1, %4 @@ -29,17 +29,16 @@ main_body: %21 = insertelement <4 x float> %20, float %15, i32 1 %22 = insertelement <4 x float> %21, float %17, i32 2 %23 = insertelement <4 x float> %22, float %19, i32 3 - %24 = call float @llvm.AMDGPU.dp4(<4 x float> %23, <4 x float> %10) + %24 = call float @llvm.r600.dot4(<4 x float> %23, <4 x float> %10) %25 = insertelement <4 x float> undef, float %24, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %25, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %25, i32 0, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/pv.ll b/test/CodeGen/AMDGPU/pv.ll index 9a57dd19765a..d5f9833d6ad0 100644 --- a/test/CodeGen/AMDGPU/pv.ll +++ b/test/CodeGen/AMDGPU/pv.ll @@ -3,7 +3,7 @@ ; CHECK: DOT4 * T{{[0-9]\.W}} (MASKED) ; CHECK: MAX T{{[0-9].[XYZW]}}, 0.0, PV.X -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg %reg6, <4 x float> inreg %reg7) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -101,9 +101,9 @@ main_body: %93 = insertelement <4 x float> %92, float %5, i32 1 %94 = insertelement <4 x float> %93, float %6, i32 2 %95 = insertelement <4 x float> %94, float 0.000000e+00, i32 3 - %96 = call float @llvm.AMDGPU.dp4(<4 x float> %91, <4 x float> %95) - %97 = call float @fabs(float %96) - %98 = call float @llvm.AMDGPU.rsq.f32(float %97) + %96 = call float @llvm.r600.dot4(<4 x float> %91, <4 x float> %95) + %97 = call float @llvm.fabs.f32(float %96) + %98 = call float @llvm.r600.recipsqrt.clamped.f32(float %97) %99 = fmul float %4, %98 %100 = fmul float %5, %98 %101 = fmul float %6, %98 @@ -119,10 +119,10 @@ main_body: %111 = extractelement <4 x float> %110, i32 2 %112 = fmul float %111, %10 %113 = fadd float %112, %22 - %114 = call float @llvm.AMDIL.clamp.(float %105, float 0.000000e+00, float 1.000000e+00) - %115 = call float @llvm.AMDIL.clamp.(float %109, float 0.000000e+00, float 1.000000e+00) - %116 = call float @llvm.AMDIL.clamp.(float %113, float 0.000000e+00, float 1.000000e+00) - %117 = call float @llvm.AMDIL.clamp.(float %15, float 0.000000e+00, float 1.000000e+00) + %114 = call float @llvm.AMDGPU.clamp.f32(float %105, float 0.000000e+00, float 1.000000e+00) + %115 = call float @llvm.AMDGPU.clamp.f32(float %109, float 0.000000e+00, float 1.000000e+00) + %116 = call float @llvm.AMDGPU.clamp.f32(float %113, float 0.000000e+00, float 1.000000e+00) + %117 = call float @llvm.AMDGPU.clamp.f32(float %15, float 0.000000e+00, float 1.000000e+00) %118 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) %119 = extractelement <4 x float> %118, i32 0 %120 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 5) @@ -137,7 +137,7 @@ main_body: %129 = insertelement <4 x float> %128, float %121, i32 1 %130 = insertelement <4 x float> %129, float %123, i32 2 %131 = insertelement <4 x float> %130, float 0.000000e+00, i32 3 - %132 = call float @llvm.AMDGPU.dp4(<4 x float> %127, <4 x float> %131) + %132 = call float @llvm.r600.dot4(<4 x float> %127, <4 x float> %131) %133 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) %134 = extractelement <4 x float> %133, i32 0 %135 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 7) @@ -152,7 +152,7 @@ main_body: %144 = insertelement <4 x float> %143, float %136, i32 1 %145 = insertelement <4 x float> %144, float %138, i32 2 %146 = insertelement <4 x float> %145, float 0.000000e+00, i32 3 - %147 = call float @llvm.AMDGPU.dp4(<4 x float> %142, <4 x float> %146) + %147 = call float @llvm.r600.dot4(<4 x float> %142, <4 x float> %146) %148 = load <4 x float>, <4 x float> addrspace(8)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(8)* null, i64 0, i32 8) %149 = extractelement <4 x float> %148, i32 0 %150 = fmul float %149, %8 @@ -202,40 +202,39 @@ main_body: %194 = fadd float %193, %188 %195 = fmul float %181, %174 %196 = fadd float %195, %190 - %197 = call float @llvm.AMDIL.clamp.(float %192, float 0.000000e+00, float 1.000000e+00) - %198 = call float @llvm.AMDIL.clamp.(float %194, float 0.000000e+00, float 1.000000e+00) - %199 = call float @llvm.AMDIL.clamp.(float %196, float 0.000000e+00, float 1.000000e+00) + %197 = call float @llvm.AMDGPU.clamp.f32(float %192, float 0.000000e+00, float 1.000000e+00) + %198 = call float @llvm.AMDGPU.clamp.f32(float %194, float 0.000000e+00, float 1.000000e+00) + %199 = call float @llvm.AMDGPU.clamp.f32(float %196, float 0.000000e+00, float 1.000000e+00) %200 = insertelement <4 x float> undef, float %75, i32 0 %201 = insertelement <4 x float> %200, float %79, i32 1 %202 = insertelement <4 x float> %201, float %83, i32 2 %203 = insertelement <4 x float> %202, float %87, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %203, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %203, i32 60, i32 1) %204 = insertelement <4 x float> undef, float %197, i32 0 %205 = insertelement <4 x float> %204, float %198, i32 1 %206 = insertelement <4 x float> %205, float %199, i32 2 %207 = insertelement <4 x float> %206, float %117, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %207, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %207, i32 0, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 ; Function Attrs: readonly -declare float @fabs(float) #2 +declare float @llvm.fabs.f32(float) #1 ; Function Attrs: readnone -declare float @llvm.AMDGPU.rsq.f32(float) #1 +declare float @llvm.r600.recipsqrt.clamped.f32(float) #1 ; Function Attrs: readnone -declare float @llvm.AMDIL.clamp.(float, float, float) #1 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1 ; Function Attrs: nounwind readonly -declare float @llvm.pow.f32(float, float) #3 +declare float @llvm.pow.f32(float, float) #2 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) #3 -attributes #0 = { "ShaderType"="1" } -attributes #1 = { readnone } -attributes #2 = { readonly } -attributes #3 = { nounwind readonly } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind readonly } +attributes #3 = { nounwind } diff --git a/test/CodeGen/AMDGPU/r600-encoding.ll b/test/CodeGen/AMDGPU/r600-encoding.ll index 3a82ee30a328..e14b30680ba1 100644 --- a/test/CodeGen/AMDGPU/r600-encoding.ll +++ b/test/CodeGen/AMDGPU/r600-encoding.ll @@ -10,16 +10,14 @@ ; R600: {{^}}test: ; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}] -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { entry: %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = extractelement <4 x float> %reg0, i32 1 %r2 = fmul float %r0, %r1 %vec = insertelement <4 x float> undef, float %r2, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/r600-export-fix.ll b/test/CodeGen/AMDGPU/r600-export-fix.ll index 7cb80195b368..7d86f9e3b3f1 100644 --- a/test/CodeGen/AMDGPU/r600-export-fix.ll +++ b/test/CodeGen/AMDGPU/r600-export-fix.ll @@ -10,7 +10,7 @@ ;CHECK: EXPORT T{{[0-9]}}.0000 -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -98,45 +98,43 @@ main_body: %83 = insertelement <4 x float> %82, float %55, i32 1 %84 = insertelement <4 x float> %83, float %59, i32 2 %85 = insertelement <4 x float> %84, float %63, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %85, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %85, i32 60, i32 1) %86 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %87 = insertelement <4 x float> %86, float 0.000000e+00, i32 1 %88 = insertelement <4 x float> %87, float 0.000000e+00, i32 2 %89 = insertelement <4 x float> %88, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %89, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %89, i32 0, i32 2) %90 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %91 = insertelement <4 x float> %90, float 0.000000e+00, i32 1 %92 = insertelement <4 x float> %91, float 0.000000e+00, i32 2 %93 = insertelement <4 x float> %92, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %93, i32 1, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %93, i32 1, i32 2) %94 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %95 = insertelement <4 x float> %94, float %65, i32 1 %96 = insertelement <4 x float> %95, float %67, i32 2 %97 = insertelement <4 x float> %96, float %69, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %97, i32 2, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %97, i32 2, i32 2) %98 = insertelement <4 x float> undef, float %77, i32 0 %99 = insertelement <4 x float> %98, float %79, i32 1 %100 = insertelement <4 x float> %99, float %81, i32 2 %101 = insertelement <4 x float> %100, float %71, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %101, i32 3, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %101, i32 3, i32 2) %102 = insertelement <4 x float> undef, float %73, i32 0 %103 = insertelement <4 x float> %102, float %75, i32 1 %104 = insertelement <4 x float> %103, float 0.000000e+00, i32 2 %105 = insertelement <4 x float> %104, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %105, i32 4, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %105, i32 4, i32 2) %106 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %107 = insertelement <4 x float> %106, float 0.000000e+00, i32 1 %108 = insertelement <4 x float> %107, float 0.000000e+00, i32 2 %109 = insertelement <4 x float> %108, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %109, i32 5, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %109, i32 5, i32 2) %110 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %111 = insertelement <4 x float> %110, float 0.000000e+00, i32 1 %112 = insertelement <4 x float> %111, float 0.000000e+00, i32 2 %113 = insertelement <4 x float> %112, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %113, i32 6, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %113, i32 6, i32 2) ret void } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll b/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll index f388f8ffe293..461caf5b5d20 100644 --- a/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll +++ b/test/CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll @@ -1,58 +1,58 @@ -;RUN: llc < %s -march=r600 -mcpu=cayman +; RUN: llc -march=r600 -mcpu=cayman < %s -define void @main(<4 x float> inreg, <4 x float> inreg) #0 { +define amdgpu_ps void @main(<4 x float> inreg %arg, <4 x float> inreg %arg1) { main_body: - %2 = extractelement <4 x float> %0, i32 0 - %3 = extractelement <4 x float> %0, i32 1 - %4 = extractelement <4 x float> %0, i32 2 - %5 = extractelement <4 x float> %0, i32 3 - %6 = insertelement <4 x float> undef, float %2, i32 0 - %7 = insertelement <4 x float> %6, float %3, i32 1 - %8 = insertelement <4 x float> %7, float %4, i32 2 - %9 = insertelement <4 x float> %8, float %5, i32 3 - %10 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %9) - %11 = extractelement <4 x float> %10, i32 0 - %12 = extractelement <4 x float> %10, i32 1 - %13 = extractelement <4 x float> %10, i32 2 - %14 = extractelement <4 x float> %10, i32 3 - %15 = call float @fabs(float %13) - %16 = fdiv float 1.000000e+00, %15 - %17 = fmul float %11, %16 - %18 = fadd float %17, 1.500000e+00 - %19 = fmul float %12, %16 - %20 = fadd float %19, 1.500000e+00 - %21 = insertelement <4 x float> undef, float %20, i32 0 - %22 = insertelement <4 x float> %21, float %18, i32 1 - %23 = insertelement <4 x float> %22, float %14, i32 2 - %24 = insertelement <4 x float> %23, float %5, i32 3 - %25 = extractelement <4 x float> %24, i32 0 - %26 = extractelement <4 x float> %24, i32 1 - %27 = extractelement <4 x float> %24, i32 2 - %28 = extractelement <4 x float> %24, i32 3 - %29 = insertelement <4 x float> undef, float %25, i32 0 - %30 = insertelement <4 x float> %29, float %26, i32 1 - %31 = insertelement <4 x float> %30, float %27, i32 2 - %32 = insertelement <4 x float> %31, float %28, i32 3 - %33 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %32, i32 16, i32 0, i32 13) - %34 = extractelement <4 x float> %33, i32 0 - %35 = insertelement <4 x float> undef, float %34, i32 0 - %36 = insertelement <4 x float> %35, float %34, i32 1 - %37 = insertelement <4 x float> %36, float %34, i32 2 - %38 = insertelement <4 x float> %37, float 1.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %38, i32 0, i32 0) + %tmp = extractelement <4 x float> %arg, i32 0 + %tmp2 = extractelement <4 x float> %arg, i32 1 + %tmp3 = extractelement <4 x float> %arg, i32 2 + %tmp4 = extractelement <4 x float> %arg, i32 3 + %tmp5 = insertelement <4 x float> undef, float %tmp, i32 0 + %tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 1 + %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 2 + %tmp8 = insertelement <4 x float> %tmp7, float %tmp4, i32 3 + %tmp9 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp8) + %tmp10 = extractelement <4 x float> %tmp9, i32 0 + %tmp11 = extractelement <4 x float> %tmp9, i32 1 + %tmp12 = extractelement <4 x float> %tmp9, i32 2 + %tmp13 = extractelement <4 x float> %tmp9, i32 3 + %tmp14 = call float @fabs(float %tmp12) + %tmp15 = fdiv float 1.000000e+00, %tmp14 + %tmp16 = fmul float %tmp10, %tmp15 + %tmp17 = fadd float %tmp16, 1.500000e+00 + %tmp18 = fmul float %tmp11, %tmp15 + %tmp19 = fadd float %tmp18, 1.500000e+00 + %tmp20 = insertelement <4 x float> undef, float %tmp19, i32 0 + %tmp21 = insertelement <4 x float> %tmp20, float %tmp17, i32 1 + %tmp22 = insertelement <4 x float> %tmp21, float %tmp13, i32 2 + %tmp23 = insertelement <4 x float> %tmp22, float %tmp4, i32 3 + %tmp24 = extractelement <4 x float> %tmp23, i32 0 + %tmp25 = extractelement <4 x float> %tmp23, i32 1 + %tmp26 = extractelement <4 x float> %tmp23, i32 2 + %tmp27 = extractelement <4 x float> %tmp23, i32 3 + %tmp28 = insertelement <4 x float> undef, float %tmp24, i32 0 + %tmp29 = insertelement <4 x float> %tmp28, float %tmp25, i32 1 + %tmp30 = insertelement <4 x float> %tmp29, float %tmp26, i32 2 + %tmp31 = insertelement <4 x float> %tmp30, float %tmp27, i32 3 + %tmp32 = shufflevector <4 x float> %tmp31, <4 x float> %tmp31, <4 x i32> + %tmp33 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp32, i32 0, i32 0, i32 0, i32 16, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp34 = extractelement <4 x float> %tmp33, i32 0 + %tmp35 = insertelement <4 x float> undef, float %tmp34, i32 0 + %tmp36 = insertelement <4 x float> %tmp35, float %tmp34, i32 1 + %tmp37 = insertelement <4 x float> %tmp36, float %tmp34, i32 2 + %tmp38 = insertelement <4 x float> %tmp37, float 1.000000e+00, i32 3 + call void @llvm.r600.store.swizzle(<4 x float> %tmp38, i32 0, i32 0) ret void } ; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1 +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #0 ; Function Attrs: readnone -declare float @fabs(float) #1 +declare float @fabs(float) #0 -; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) #1 +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +; Function Attrs: readnone +declare <4 x float> @llvm.r600.texc(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 -attributes #0 = { "ShaderType"="0" } -attributes #1 = { readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/r600.private-memory.ll b/test/CodeGen/AMDGPU/r600.private-memory.ll new file mode 100644 index 000000000000..f406c160cbbe --- /dev/null +++ b/test/CodeGen/AMDGPU/r600.private-memory.ll @@ -0,0 +1,26 @@ +; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC + +declare i32 @llvm.r600.read.tidig.x() nounwind readnone + + +; Make sure we don't overwrite workitem information with private memory + +; FUNC-LABEL: {{^}}work_item_info: +; R600-NOT: MOV T0.X +; Additional check in case the move ends up in the last slot +; R600-NOT: MOV * TO.X + +define void @work_item_info(i32 addrspace(1)* %out, i32 %in) { +entry: + %0 = alloca [2 x i32] + %1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 + %2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 + store i32 0, i32* %1 + store i32 1, i32* %2 + %3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in + %4 = load i32, i32* %3 + %5 = call i32 @llvm.r600.read.tidig.x() + %6 = add i32 %4, %5 + store i32 %6, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll b/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll new file mode 100644 index 000000000000..ff248a89cedc --- /dev/null +++ b/test/CodeGen/AMDGPU/r600.work-item-intrinsics.ll @@ -0,0 +1,107 @@ +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FUNC-LABEL: {{^}}tgid_x: +; EG: MEM_RAT_CACHELESS STORE_RAW T1.X +define void @tgid_x(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tgid_y: +; EG: MEM_RAT_CACHELESS STORE_RAW T1.Y +define void @tgid_y(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tgid_z: +; EG: MEM_RAT_CACHELESS STORE_RAW T1.Z +define void @tgid_z(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tgid.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tidig_x: +; EG: MEM_RAT_CACHELESS STORE_RAW T0.X +define void @tidig_x(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.x() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tidig_y: +; EG: MEM_RAT_CACHELESS STORE_RAW T0.Y +define void @tidig_y(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.y() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}tidig_z: +; EG: MEM_RAT_CACHELESS STORE_RAW T0.Z +define void @tidig_z(i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.tidig.z() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}test_implicit: +; 36 prepended implicit bytes + 4(out pointer) + 4*4 = 56 +; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 56 +define void @test_implicit(i32 addrspace(1)* %out) #1 { + %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr() + %header.ptr = bitcast i8 addrspace(7)* %implicitarg.ptr to i32 addrspace(7)* + %gep = getelementptr i32, i32 addrspace(7)* %header.ptr, i32 4 + %value = load i32, i32 addrspace(7)* %gep + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}test_implicit_dyn: +; 36 prepended implicit bytes + 8(out pointer + in) = 44 +; EG: VTX_READ_32 {{T[0-9]+\.[XYZW]}}, {{T[0-9]+\.[XYZW]}}, 44 +define void @test_implicit_dyn(i32 addrspace(1)* %out, i32 %in) #1 { + %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr() + %header.ptr = bitcast i8 addrspace(7)* %implicitarg.ptr to i32 addrspace(7)* + %gep = getelementptr i32, i32 addrspace(7)* %header.ptr, i32 %in + %value = load i32, i32 addrspace(7)* %gep + store i32 %value, i32 addrspace(1)* %out + ret void +} + + + +; DEPRECATED but R600 only + +; FUNC-LABEL: {{^}}workdim: +; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] +; EG: MOV {{\*? *}}[[VAL]], KC0[2].Z +define void @workdim (i32 addrspace(1)* %out) { +entry: + %0 = call i32 @llvm.r600.read.workdim() #0 + store i32 %0, i32 addrspace(1)* %out + ret void +} + +declare i32 @llvm.r600.read.workdim() #0 + +declare i8 addrspace(7)* @llvm.r600.implicitarg.ptr() #0 + +declare i32 @llvm.r600.read.tgid.x() #0 +declare i32 @llvm.r600.read.tgid.y() #0 +declare i32 @llvm.r600.read.tgid.z() #0 + +declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.r600.read.tidig.y() #0 +declare i32 @llvm.r600.read.tidig.z() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/r600cfg.ll b/test/CodeGen/AMDGPU/r600cfg.ll index c7b9d65220f3..2996a1053da5 100644 --- a/test/CodeGen/AMDGPU/r600cfg.ll +++ b/test/CodeGen/AMDGPU/r600cfg.ll @@ -1,6 +1,6 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -32,27 +32,27 @@ IF41: ; preds = %LOOP %17 = insertelement <4 x float> %16, float %temp8.0, i32 1 %18 = insertelement <4 x float> %17, float %temp12.0, i32 2 %19 = insertelement <4 x float> %18, float 0.000000e+00, i32 3 - call void @llvm.R600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1) + call void @llvm.r600.store.stream.output(<4 x float> %19, i32 0, i32 0, i32 1) %20 = insertelement <4 x float> undef, float %0, i32 0 %21 = insertelement <4 x float> %20, float %temp8.0, i32 1 %22 = insertelement <4 x float> %21, float %temp12.0, i32 2 %23 = insertelement <4 x float> %22, float 0.000000e+00, i32 3 - call void @llvm.R600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2) + call void @llvm.r600.store.stream.output(<4 x float> %23, i32 0, i32 0, i32 2) %24 = insertelement <4 x float> undef, float %0, i32 0 %25 = insertelement <4 x float> %24, float %temp8.0, i32 1 %26 = insertelement <4 x float> %25, float %temp12.0, i32 2 %27 = insertelement <4 x float> %26, float 0.000000e+00, i32 3 - call void @llvm.R600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4) + call void @llvm.r600.store.stream.output(<4 x float> %27, i32 0, i32 0, i32 4) %28 = insertelement <4 x float> undef, float 0.000000e+00, i32 0 %29 = insertelement <4 x float> %28, float 0.000000e+00, i32 1 %30 = insertelement <4 x float> %29, float 0.000000e+00, i32 2 %31 = insertelement <4 x float> %30, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %31, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %31, i32 60, i32 1) %32 = insertelement <4 x float> undef, float %0, i32 0 %33 = insertelement <4 x float> %32, float %temp8.0, i32 1 %34 = insertelement <4 x float> %33, float %temp12.0, i32 2 %35 = insertelement <4 x float> %34, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %35, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %35, i32 0, i32 2) ret void ENDIF40: ; preds = %LOOP @@ -112,8 +112,6 @@ ENDIF48: ; preds = %LOOP47 br label %LOOP47 } -declare void @llvm.R600.store.stream.output(<4 x float>, i32, i32, i32) +declare void @llvm.r600.store.stream.output(<4 x float>, i32, i32, i32) -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/rcp-pattern.ll b/test/CodeGen/AMDGPU/rcp-pattern.ll new file mode 100644 index 000000000000..b1d422062543 --- /dev/null +++ b/test/CodeGen/AMDGPU/rcp-pattern.ll @@ -0,0 +1,11 @@ +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG-SAFE -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s + +; FIXME: Evergreen only ever does unsafe fp math. +; FUNC-LABEL: {{^}}rcp_pat_f32: +; EG: RECIP_IEEE +define void @rcp_pat_f32(float addrspace(1)* %out, float %src) nounwind { + %rcp = fdiv float 1.0, %src + store float %rcp, float addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll b/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll new file mode 100644 index 000000000000..a5581d73cb25 --- /dev/null +++ b/test/CodeGen/AMDGPU/read-register-invalid-subtarget.ll @@ -0,0 +1,14 @@ +; RUN: not llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck %s + +; CHECK: invalid register "flat_scratch_lo" for subtarget. + +declare i32 @llvm.read_register.i32(metadata) #0 + +define void @test_invalid_read_flat_scratch_lo(i32 addrspace(1)* %out) nounwind { + store volatile i32 0, i32 addrspace(3)* undef + %m0 = call i32 @llvm.read_register.i32(metadata !0) + store i32 %m0, i32 addrspace(1)* %out + ret void +} + +!0 = !{!"flat_scratch_lo"} diff --git a/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll b/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll new file mode 100644 index 000000000000..2617ad7402ff --- /dev/null +++ b/test/CodeGen/AMDGPU/read-register-invalid-type-i32.ll @@ -0,0 +1,14 @@ +; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s + +; CHECK: invalid type for register "exec". + +declare i32 @llvm.read_register.i32(metadata) #0 + +define void @test_invalid_read_exec(i32 addrspace(1)* %out) nounwind { + store volatile i32 0, i32 addrspace(3)* undef + %m0 = call i32 @llvm.read_register.i32(metadata !0) + store i32 %m0, i32 addrspace(1)* %out + ret void +} + +!0 = !{!"exec"} diff --git a/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll b/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll new file mode 100644 index 000000000000..dcde8a1894fc --- /dev/null +++ b/test/CodeGen/AMDGPU/read-register-invalid-type-i64.ll @@ -0,0 +1,13 @@ +; RUN: not llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck %s + +; CHECK: invalid type for register "m0". + +declare i64 @llvm.read_register.i64(metadata) #0 + +define void @test_invalid_read_m0(i64 addrspace(1)* %out) #0 { + %exec = call i64 @llvm.read_register.i64(metadata !0) + store i64 %exec, i64 addrspace(1)* %out + ret void +} + +!0 = !{!"m0"} diff --git a/test/CodeGen/AMDGPU/read_register.ll b/test/CodeGen/AMDGPU/read_register.ll new file mode 100644 index 000000000000..58a9e34b77f2 --- /dev/null +++ b/test/CodeGen/AMDGPU/read_register.ll @@ -0,0 +1,81 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s + +declare i32 @llvm.read_register.i32(metadata) #0 +declare i64 @llvm.read_register.i64(metadata) #0 + +; CHECK-LABEL: {{^}}test_read_m0: +; CHECK: s_mov_b32 m0, -1 +; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], m0 +; CHECK: buffer_store_dword [[COPY]] +define void @test_read_m0(i32 addrspace(1)* %out) #0 { + store volatile i32 0, i32 addrspace(3)* undef + %m0 = call i32 @llvm.read_register.i32(metadata !0) + store i32 %m0, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_exec: +; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], exec_lo +; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], exec_hi +; CHECK: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_read_exec(i64 addrspace(1)* %out) #0 { + %exec = call i64 @llvm.read_register.i64(metadata !1) + store i64 %exec, i64 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_flat_scratch: +; CHECK: v_mov_b32_e32 v[[LO:[0-9]+]], flat_scratch_lo +; CHECK: v_mov_b32_e32 v[[HI:[0-9]+]], flat_scratch_hi +; CHECK: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @test_read_flat_scratch(i64 addrspace(1)* %out) #0 { + %flat_scratch = call i64 @llvm.read_register.i64(metadata !2) + store i64 %flat_scratch, i64 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_flat_scratch_lo: +; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_lo +; CHECK: buffer_store_dword [[COPY]] +define void @test_read_flat_scratch_lo(i32 addrspace(1)* %out) #0 { + %flat_scratch_lo = call i32 @llvm.read_register.i32(metadata !3) + store i32 %flat_scratch_lo, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_flat_scratch_hi: +; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], flat_scratch_hi +; CHECK: buffer_store_dword [[COPY]] +define void @test_read_flat_scratch_hi(i32 addrspace(1)* %out) #0 { + %flat_scratch_hi = call i32 @llvm.read_register.i32(metadata !4) + store i32 %flat_scratch_hi, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_exec_lo: +; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_lo +; CHECK: buffer_store_dword [[COPY]] +define void @test_read_exec_lo(i32 addrspace(1)* %out) #0 { + %exec_lo = call i32 @llvm.read_register.i32(metadata !5) + store i32 %exec_lo, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}test_read_exec_hi: +; CHECK: v_mov_b32_e32 [[COPY:v[0-9]+]], exec_hi +; CHECK: buffer_store_dword [[COPY]] +define void @test_read_exec_hi(i32 addrspace(1)* %out) #0 { + %exec_hi = call i32 @llvm.read_register.i32(metadata !6) + store i32 %exec_hi, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } + +!0 = !{!"m0"} +!1 = !{!"exec"} +!2 = !{!"flat_scratch"} +!3 = !{!"flat_scratch_lo"} +!4 = !{!"flat_scratch_hi"} +!5 = !{!"exec_lo"} +!6 = !{!"exec_hi"} diff --git a/test/CodeGen/AMDGPU/readcyclecounter.ll b/test/CodeGen/AMDGPU/readcyclecounter.ll new file mode 100644 index 000000000000..e6d0efd0ff94 --- /dev/null +++ b/test/CodeGen/AMDGPU/readcyclecounter.ll @@ -0,0 +1,25 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s + +declare i64 @llvm.readcyclecounter() #0 + +; GCN-LABEL: {{^}}test_readcyclecounter: +; SI-DAG: s_memtime s{{\[[0-9]+:[0-9]+\]}} +; VI-DAG: s_memrealtime s{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: s_load_dwordx2 +; GCN: lgkmcnt +; GCN: buffer_store_dwordx2 +; GCN-NOT: lgkmcnt +; SI: s_memtime s{{\[[0-9]+:[0-9]+\]}} +; VI: s_memrealtime s{{\[[0-9]+:[0-9]+\]}} +; GCN: buffer_store_dwordx2 +define void @test_readcyclecounter(i64 addrspace(1)* %out) #0 { + %cycle0 = call i64 @llvm.readcyclecounter() + store volatile i64 %cycle0, i64 addrspace(1)* %out + + %cycle1 = call i64 @llvm.readcyclecounter() + store volatile i64 %cycle1, i64 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/reciprocal.ll b/test/CodeGen/AMDGPU/reciprocal.ll index b4ac47afced7..f9292a788521 100644 --- a/test/CodeGen/AMDGPU/reciprocal.ll +++ b/test/CodeGen/AMDGPU/reciprocal.ll @@ -2,14 +2,12 @@ ;CHECK: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_ps void @test(<4 x float> inreg %reg0) { %r0 = extractelement <4 x float> %reg0, i32 0 %r1 = fdiv float 1.0, %r0 %vec = insertelement <4 x float> undef, float %r1, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0) ret void } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="0" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll b/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll new file mode 100644 index 000000000000..c902cb9e1dfb --- /dev/null +++ b/test/CodeGen/AMDGPU/reduce-load-width-alignment.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s + +; GCN-LABEL: {{^}}reduce_i64_load_align_4_width_to_i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, [[VAL]] +; GCN: buffer_store_dwordx2 +define void @reduce_i64_load_align_4_width_to_i32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #0 { + %a = load i64, i64 addrspace(1)* %in, align 4 + %and = and i64 %a, 1234567 + store i64 %and, i64 addrspace(1)* %out, align 8 + ret void +} + +; GCN-LABEL: {{^}}reduce_i64_align_4_bitcast_v2i32_elt0: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: buffer_store_dword [[VAL]] +define void @reduce_i64_align_4_bitcast_v2i32_elt0(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #0 { + %a = load i64, i64 addrspace(1)* %in, align 4 + %vec = bitcast i64 %a to <2 x i32> + %elt0 = extractelement <2 x i32> %vec, i32 0 + store i32 %elt0, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}reduce_i64_align_4_bitcast_v2i32_elt1: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 +; GCN: buffer_store_dword [[VAL]] +define void @reduce_i64_align_4_bitcast_v2i32_elt1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #0 { + %a = load i64, i64 addrspace(1)* %in, align 4 + %vec = bitcast i64 %a to <2 x i32> + %elt0 = extractelement <2 x i32> %vec, i32 1 + store i32 %elt0, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll b/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll new file mode 100644 index 000000000000..281e49f804c6 --- /dev/null +++ b/test/CodeGen/AMDGPU/reduce-store-width-alignment.ll @@ -0,0 +1,53 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}store_v2i32_as_v4i16_align_4: +; GCN: s_load_dwordx2 +; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} +define void @store_v2i32_as_v4i16_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 { + %x.bc = bitcast <2 x i32> %x to <4 x i16> + store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}store_v4i32_as_v8i16_align_4: +; GCN: s_load_dwordx4 +; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 +; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} +define void @store_v4i32_as_v8i16_align_4(<8 x i16> addrspace(3)* align 4 %out, <4 x i32> %x) #0 { + %x.bc = bitcast <4 x i32> %x to <8 x i16> + store <8 x i16> %x.bc, <8 x i16> addrspace(3)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}store_v2i32_as_i64_align_4: +; GCN: s_load_dwordx2 +; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} +define void @store_v2i32_as_i64_align_4(<4 x i16> addrspace(3)* align 4 %out, <2 x i32> %x) #0 { + %x.bc = bitcast <2 x i32> %x to <4 x i16> + store <4 x i16> %x.bc, <4 x i16> addrspace(3)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}store_v4i32_as_v2i64_align_4: +; GCN: s_load_dwordx4 +; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3 +; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} +define void @store_v4i32_as_v2i64_align_4(<2 x i64> addrspace(3)* align 4 %out, <4 x i32> %x) #0 { + %x.bc = bitcast <4 x i32> %x to <2 x i64> + store <2 x i64> %x.bc, <2 x i64> addrspace(3)* %out, align 4 + ret void +} + +; GCN-LABEL: {{^}}store_v4i16_as_v2i32_align_4: +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: buffer_load_ushort +; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}} +define void @store_v4i16_as_v2i32_align_4(<2 x i32> addrspace(3)* align 4 %out, <4 x i16> %x) #0 { + %x.bc = bitcast <4 x i16> %x to <2 x i32> + store <2 x i32> %x.bc, <2 x i32> addrspace(3)* %out, align 4 + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll b/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll new file mode 100644 index 000000000000..6e95f4c7521f --- /dev/null +++ b/test/CodeGen/AMDGPU/reg-coalescer-sched-crash.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs -o /dev/null < %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -o /dev/null < %s + +; The register coalescer introduces a verifier error which later +; results in a crash during scheduling. + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +define void @reg_coalescer_breaks_dead(<2 x i32> addrspace(1)* nocapture readonly %arg, i32 %arg1, i32 %arg2, i32 %arg3) #1 { +bb: + %id.x = call i32 @llvm.amdgcn.workitem.id.x() + %cmp0 = icmp eq i32 %id.x, 0 + br i1 %cmp0, label %bb3, label %bb4 + +bb3: ; preds = %bb + %tmp = ashr exact i32 undef, 8 + br label %bb6 + +bb4: ; preds = %bb6, %bb + %tmp5 = phi <2 x i32> [ zeroinitializer, %bb ], [ %tmp13, %bb6 ] + br i1 undef, label %bb15, label %bb16 + +bb6: ; preds = %bb6, %bb3 + %tmp7 = phi <2 x i32> [ zeroinitializer, %bb3 ], [ %tmp13, %bb6 ] + %tmp8 = add nsw i32 0, %arg1 + %tmp9 = add nsw i32 %tmp8, 0 + %tmp10 = sext i32 %tmp9 to i64 + %tmp11 = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %arg, i64 %tmp10 + %tmp12 = load <2 x i32>, <2 x i32> addrspace(1)* %tmp11, align 8 + %tmp13 = add <2 x i32> %tmp12, %tmp7 + %tmp14 = icmp slt i32 undef, %arg2 + br i1 %tmp14, label %bb6, label %bb4 + +bb15: ; preds = %bb4 + store <2 x i32> %tmp5, <2 x i32> addrspace(3)* undef, align 8 + br label %bb16 + +bb16: ; preds = %bb15, %bb4 + unreachable +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/register-count-comments.ll b/test/CodeGen/AMDGPU/register-count-comments.ll index 4bb315049be4..bff3a9f5d2b0 100644 --- a/test/CodeGen/AMDGPU/register-count-comments.ll +++ b/test/CodeGen/AMDGPU/register-count-comments.ll @@ -1,7 +1,8 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs -asm-verbose < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -verify-machineinstrs -asm-verbose -mattr=-flat-for-global < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.SI.tid() nounwind readnone +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 ; SI-LABEL: {{^}}foo: ; SI: .section .AMDGPU.csdata @@ -9,7 +10,8 @@ declare i32 @llvm.SI.tid() nounwind readnone ; SI: ; NumSgprs: {{[0-9]+}} ; SI: ; NumVgprs: {{[0-9]+}} define void @foo(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %abase, i32 addrspace(1)* %bbase) nounwind { - %tid = call i32 @llvm.SI.tid() nounwind readnone + %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); + %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) %aptr = getelementptr i32, i32 addrspace(1)* %abase, i32 %tid %bptr = getelementptr i32, i32 addrspace(1)* %bbase, i32 %tid %outptr = getelementptr i32, i32 addrspace(1)* %out, i32 %tid diff --git a/test/CodeGen/AMDGPU/rename-disconnected-bug.ll b/test/CodeGen/AMDGPU/rename-disconnected-bug.ll new file mode 100644 index 000000000000..47bdfba96530 --- /dev/null +++ b/test/CodeGen/AMDGPU/rename-disconnected-bug.ll @@ -0,0 +1,33 @@ +; RUN: llc -verify-machineinstrs -o /dev/null %s +; Check that renameDisconnectedComponents() does not create vregs without a +; definition on every path (there should at least be IMPLICIT_DEF instructions). +target triple = "amdgcn--" + +define void @func() { +B0: + br i1 undef, label %B1, label %B2 + +B1: + br label %B2 + +B2: + %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ , %B0 ] + br i1 undef, label %B20.1, label %B20.2 + +B20.1: + br label %B20.2 + +B20.2: + %v2 = phi <4 x float> [ zeroinitializer, %B20.1 ], [ %v0, %B2 ] + br i1 undef, label %B30.1, label %B30.2 + +B30.1: + %sub = fsub <4 x float> %v2, undef + br label %B30.2 + +B30.2: + %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v2, %B20.2 ] + %ve0 = extractelement <4 x float> %v3, i32 0 + store float %ve0, float addrspace(3)* undef, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/test/CodeGen/AMDGPU/rename-independent-subregs.mir new file mode 100644 index 000000000000..2dd21ca51e46 --- /dev/null +++ b/test/CodeGen/AMDGPU/rename-independent-subregs.mir @@ -0,0 +1,30 @@ +# RUN: llc -march=amdgcn -run-pass rename-independent-subregs -o - %s | FileCheck %s +--- | + define void @test0() { ret void } +... +--- +# In the test below we have two independent def+use pairs of subregister1 which +# can be moved to a new virtual register. The third def of sub1 however is used +# in combination with sub0 and needs to stay with the original vreg. +# CHECK-LABEL: name: test0 +# CHECK: S_NOP 0, implicit-def undef %0:sub0 +# CHECK: S_NOP 0, implicit-def undef %2:sub1 +# CHECK: S_NOP 0, implicit %2:sub1 +# CHECK: S_NOP 0, implicit-def undef %1:sub1 +# CHECK: S_NOP 0, implicit %1:sub1 +# CHECK: S_NOP 0, implicit-def %0:sub1 +# CHECK: S_NOP 0, implicit %0 +name: test0 +isSSA: true +registers: + - { id: 0, class: sreg_128 } +body: | + bb.0: + S_NOP 0, implicit-def undef %0:sub0 + S_NOP 0, implicit-def %0:sub1 + S_NOP 0, implicit %0:sub1 + S_NOP 0, implicit-def %0:sub1 + S_NOP 0, implicit %0:sub1 + S_NOP 0, implicit-def %0:sub1 + S_NOP 0, implicit %0 +... diff --git a/test/CodeGen/AMDGPU/reorder-stores.ll b/test/CodeGen/AMDGPU/reorder-stores.ll index d5e10d0be883..ad8d00c36393 100644 --- a/test/CodeGen/AMDGPU/reorder-stores.ll +++ b/test/CodeGen/AMDGPU/reorder-stores.ll @@ -16,10 +16,8 @@ define void @no_reorder_v2f64_global_load_store(<2 x double> addrspace(1)* nocap } ; SI-LABEL: {{^}}no_reorder_scalarized_v2f64_local_load_store: -; SI: ds_read_b64 -; SI: ds_read_b64 -; SI: ds_write_b64 -; SI: ds_write_b64 +; SI: ds_read2_b64 +; SI: ds_write2_b64 ; SI: s_endpgm define void @no_reorder_scalarized_v2f64_local_load_store(<2 x double> addrspace(3)* nocapture %x, <2 x double> addrspace(3)* nocapture %y) nounwind { %tmp1 = load <2 x double>, <2 x double> addrspace(3)* %x, align 16 diff --git a/test/CodeGen/AMDGPU/ret.ll b/test/CodeGen/AMDGPU/ret.ll index 2bd9fd6858fe..915c4383ff49 100644 --- a/test/CodeGen/AMDGPU/ret.ll +++ b/test/CodeGen/AMDGPU/ret.ll @@ -1,8 +1,6 @@ ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s -attributes #0 = { "ShaderType"="1" } - declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) ; GCN-LABEL: {{^}}vgpr: @@ -11,7 +9,7 @@ declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float ; GCN-DAG: exp 15, 0, 1, 1, 1, v1, v1, v1, v1 ; GCN: s_waitcnt expcnt(0) ; GCN-NOT: s_endpgm -define {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) %x = fadd float %3, 1.0 %a = insertvalue {float, float} undef, float %x, 0 @@ -20,15 +18,14 @@ define {float, float} @vgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 } ; GCN-LABEL: {{^}}vgpr_literal: -; GCN: v_mov_b32_e32 v4, v0 +; GCN: exp 15, 0, 1, 1, 1, v0, v0, v0, v0 +; GCN: s_waitcnt expcnt(0) ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v3, -1.0 -; GCN: exp 15, 0, 1, 1, 1, v4, v4, v4, v4 -; GCN: s_waitcnt expcnt(0) ; GCN-NOT: s_endpgm -define {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) ret {float, float, float, float} {float 1.0, float 2.0, float 4.0, float -1.0} } @@ -45,8 +42,8 @@ define {float, float, float, float} @vgpr_literal([9 x <16 x i8>] addrspace(2)* ; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v4, v6 ; GCN-NOT: s_endpgm -attributes #1 = { "ShaderType"="0" "InitialPSInputAddr"="0" } -define {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { +attributes #0 = { "InitialPSInputAddr"="0" } +define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { %i0 = extractelement <2 x i32> %4, i32 0 %i1 = extractelement <2 x i32> %4, i32 1 %i2 = extractelement <2 x i32> %7, i32 0 @@ -71,7 +68,7 @@ define {float, float, float, float, float} @vgpr_ps_addr0([9 x <16 x i8>] addrsp ; GCN-LABEL: {{^}}ps_input_ena_no_inputs: ; GCN: v_mov_b32_e32 v0, 1.0 ; GCN-NOT: s_endpgm -define float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { +define amdgpu_ps float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { ret float 1.0 } @@ -85,7 +82,7 @@ define float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval, i32 in ; GCN-DAG: v_mov_b32_e32 v1, v2 ; GCN: v_mov_b32_e32 v2, v3 ; GCN-NOT: s_endpgm -define {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { +define amdgpu_ps {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { %f = bitcast <2 x i32> %8 to <2 x float> %s = insertvalue {float, <2 x float>} undef, float %14, 0 %s1 = insertvalue {float, <2 x float>} %s, <2 x float> %f, 1 @@ -104,8 +101,8 @@ define {float, <2 x float>} @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* by ; GCN-DAG: v_mov_b32_e32 v3, v6 ; GCN-DAG: v_mov_b32_e32 v4, v8 ; GCN-NOT: s_endpgm -attributes #2 = { "ShaderType"="0" "InitialPSInputAddr"="1" } -define {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 { +attributes #1 = { "InitialPSInputAddr"="1" } +define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #1 { %i0 = extractelement <2 x i32> %4, i32 0 %i1 = extractelement <2 x i32> %4, i32 1 %i2 = extractelement <2 x i32> %7, i32 0 @@ -134,8 +131,8 @@ define {float, float, float, float, float} @vgpr_ps_addr1([9 x <16 x i8>] addrsp ; GCN: v_mov_b32_e32 v3, v8 ; GCN: v_mov_b32_e32 v4, v12 ; GCN-NOT: s_endpgm -attributes #3 = { "ShaderType"="0" "InitialPSInputAddr"="119" } -define {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 { +attributes #2 = { "InitialPSInputAddr"="119" } +define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #2 { %i0 = extractelement <2 x i32> %4, i32 0 %i1 = extractelement <2 x i32> %4, i32 1 %i2 = extractelement <2 x i32> %7, i32 0 @@ -164,8 +161,8 @@ define {float, float, float, float, float} @vgpr_ps_addr119([9 x <16 x i8>] addr ; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v4, v8 ; GCN-NOT: s_endpgm -attributes #4 = { "ShaderType"="0" "InitialPSInputAddr"="418" } -define {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #4 { +attributes #3 = { "InitialPSInputAddr"="418" } +define amdgpu_ps {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #3 { %i0 = extractelement <2 x i32> %4, i32 0 %i1 = extractelement <2 x i32> %4, i32 1 %i2 = extractelement <2 x i32> %7, i32 0 @@ -187,7 +184,7 @@ define {float, float, float, float, float} @vgpr_ps_addr418([9 x <16 x i8>] addr ; GCN: s_add_i32 s0, s3, 2 ; GCN: s_mov_b32 s2, s3 ; GCN-NOT: s_endpgm -define {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { %x = add i32 %2, 2 %a = insertvalue {i32, i32, i32} undef, i32 %x, 0 %b = insertvalue {i32, i32, i32} %a, i32 %1, 1 @@ -203,7 +200,7 @@ define {i32, i32, i32} @sgpr([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 ; GCN-DAG: s_mov_b32 s2, 7 ; GCN-DAG: s_mov_b32 s3, 8 ; GCN-NOT: s_endpgm -define {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { %x = add i32 %2, 2 ret {i32, i32, i32, i32} {i32 5, i32 6, i32 7, i32 8} } @@ -218,7 +215,7 @@ define {i32, i32, i32, i32} @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval, i ; GCN: s_mov_b32 s2, s3 ; GCN: s_waitcnt expcnt(0) ; GCN-NOT: s_endpgm -define {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) %v = fadd float %3, 1.0 %s = add i32 %2, 2 @@ -232,14 +229,14 @@ define {float, i32, float, i32, i32} @both([9 x <16 x i8>] addrspace(2)* byval, ; GCN-LABEL: {{^}}structure_literal: -; GCN: v_mov_b32_e32 v3, v0 +; GCN: exp 15, 0, 1, 1, 1, v0, v0, v0, v0 +; GCN: s_waitcnt expcnt(0) ; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: s_mov_b32 s0, 2 ; GCN-DAG: s_mov_b32 s1, 3 ; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0 -; GCN-DAG: exp 15, 0, 1, 1, 1, v3, v3, v3, v3 -define {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) #0 { +define amdgpu_vs {{float, i32}, {i32, <2 x float>}} @structure_literal([9 x <16 x i8>] addrspace(2)* byval, i32 inreg, i32 inreg, float) { call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %3, float %3, float %3, float %3) ret {{float, i32}, {i32, <2 x float>}} {{float, i32} {float 1.0, i32 2}, {i32, <2 x float>} {i32 3, <2 x float> }} } diff --git a/test/CodeGen/AMDGPU/ret_jump.ll b/test/CodeGen/AMDGPU/ret_jump.ll new file mode 100644 index 000000000000..f7380cd96921 --- /dev/null +++ b/test/CodeGen/AMDGPU/ret_jump.ll @@ -0,0 +1,63 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; This should end with an no-op sequence of exec mask manipulations +; Mask should be in original state after executed unreachable block + +; GCN-LABEL: {{^}}main: +; GCN: s_cbranch_vccnz [[RET_BB:BB[0-9]+_[0-9]+]] + +; GCN: s_and_saveexec_b64 [[SAVE_EXEC:s\[[0-9]+:[0-9]+\]]], vcc +; GCN-NEXT: s_xor_b64 [[XOR_EXEC:s\[[0-9]+:[0-9]+\]]], exec, [[SAVE_EXEC]] +; GCN-NEXT: ; mask branch [[UNREACHABLE_BB:BB[0-9]+_[0-9]+]] + +; GCN: [[RET_BB]]: +; GCN-NEXT: s_branch [[FINAL_BB:BB[0-9]+_[0-9]+]] + +; GCN-NEXT: [[UNREACHABLE_BB]]: +; GCN-NEXT: s_or_b64 exec, exec, [[XOR_EXEC]] +; GCN-NEXT: [[FINAL_BB]]: +; GCN-NEXT: .Lfunc_end0 +define amdgpu_ps <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @main([9 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <8 x i32>] addrspace(2)* byval, i32 addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #0 { +main_body: + %p83 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7) + %p87 = fmul float undef, %p83 + %p88 = fadd float %p87, undef + %p93 = fadd float %p88, undef + %p97 = fmul float %p93, undef + %p102 = fsub float %p97, undef + %p104 = fmul float %p102, undef + %p106 = fadd float 0.000000e+00, %p104 + %p108 = fadd float undef, %p106 + br i1 undef, label %ENDIF69, label %ELSE + +ELSE: ; preds = %main_body + %p124 = fmul float %p108, %p108 + %p125 = fsub float %p124, undef + %p126 = fcmp olt float %p125, 0.000000e+00 + br i1 %p126, label %ENDIF69, label %ELSE41 + +ELSE41: ; preds = %ELSE + unreachable + +ENDIF69: ; preds = %ELSE, %main_body + ret <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.fabs.f32(float) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.sqrt.f32(float) #1 + +; Function Attrs: nounwind readnone +declare float @llvm.floor.f32(float) #1 + +attributes #0 = { "InitialPSInputAddr"="36983" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/rotl.ll b/test/CodeGen/AMDGPU/rotl.ll index 6c144cd56ea7..7d2b5538ca33 100644 --- a/test/CodeGen/AMDGPU/rotl.ll +++ b/test/CodeGen/AMDGPU/rotl.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}rotl_i32: ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x diff --git a/test/CodeGen/AMDGPU/rsq.ll b/test/CodeGen/AMDGPU/rsq.ll index b67b800c7374..8192b861b602 100644 --- a/test/CodeGen/AMDGPU/rsq.ll +++ b/test/CodeGen/AMDGPU/rsq.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=SI -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s +; RUN: llc -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=SI-UNSAFE -check-prefix=SI %s +; RUN: llc -march=amdgcn -mattr=-fp32-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=SI-SAFE -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare float @llvm.sqrt.f32(float) nounwind readnone declare double @llvm.sqrt.f64(double) nounwind readnone @@ -56,15 +56,15 @@ define void @rsq_f32_sgpr(float addrspace(1)* noalias %out, float %val) nounwind ; SI: s_endpgm define void @rsqrt_fmul(float addrspace(1)* %out, float addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.2 = getelementptr float, float addrspace(1)* %gep.0, i32 2 - %a = load float, float addrspace(1)* %gep.0 - %b = load float, float addrspace(1)* %gep.1 - %c = load float, float addrspace(1)* %gep.2 + %a = load volatile float, float addrspace(1)* %gep.0 + %b = load volatile float, float addrspace(1)* %gep.1 + %c = load volatile float, float addrspace(1)* %gep.2 %x = call float @llvm.sqrt.f32(float %a) %y = fmul float %x, %b diff --git a/test/CodeGen/AMDGPU/runtime-metadata.ll b/test/CodeGen/AMDGPU/runtime-metadata.ll new file mode 100644 index 000000000000..052ad5b9c15b --- /dev/null +++ b/test/CodeGen/AMDGPU/runtime-metadata.ll @@ -0,0 +1,848 @@ +; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck %s + +%struct.A = type { i8, float } +%opencl.image1d_t = type opaque +%opencl.image2d_t = type opaque +%opencl.image3d_t = type opaque +%opencl.queue_t = type opaque +%opencl.pipe_t = type opaque +%struct.B = type { i32 addrspace(1)*} +%opencl.clk_event_t = type opaque + +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .short 256 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .short 200 + +; CHECK-LABEL:{{^}}test_char: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "test_char" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 1 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 1 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .ascii "char" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 1 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_char(i8 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !9 !kernel_arg_base_type !9 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_ushort2: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 12 +; CHECK-NEXT: .ascii "test_ushort2" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 7 +; CHECK-NEXT: .ascii "ushort2" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 4 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_ushort2(<2 x i16> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_int3: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "test_int3" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .ascii "int3" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_int3(<3 x i32> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !11 !kernel_arg_base_type !11 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_ulong4: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 11 +; CHECK-NEXT: .ascii "test_ulong4" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 32 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 32 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 6 +; CHECK-NEXT: .ascii "ulong4" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 10 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_ulong4(<4 x i64> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !12 !kernel_arg_base_type !12 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_half8: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 10 +; CHECK-NEXT: .ascii "test_half8" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "half8" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 5 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_half8(<8 x half> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !13 !kernel_arg_base_type !13 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_float16: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 12 +; CHECK-NEXT: .ascii "test_float16" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 64 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 64 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 7 +; CHECK-NEXT: .ascii "float16" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 8 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_float16(<16 x float> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_double16: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 13 +; CHECK-NEXT: .ascii "test_double16" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 128 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 128 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .ascii "double16" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 11 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_double16(<16 x double> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !15 !kernel_arg_base_type !15 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_pointer: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 12 +; CHECK-NEXT: .ascii "test_pointer" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_pointer(i32 addrspace(1)* %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !16 !kernel_arg_base_type !16 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_image: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 10 +; CHECK-NEXT: .ascii "test_image" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "image2d_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_image(%opencl.image2d_t addrspace(1)* %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !17 !kernel_arg_base_type !17 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_sampler: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 12 +; CHECK-NEXT: .ascii "test_sampler" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "sampler_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_sampler(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !18 !kernel_arg_base_type !18 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_queue: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 10 +; CHECK-NEXT: .ascii "test_queue" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 7 +; CHECK-NEXT: .ascii "queue_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_queue(%opencl.queue_t addrspace(1)* %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !19 !kernel_arg_base_type !19 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_struct: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 11 +; CHECK-NEXT: .ascii "test_struct" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .ascii "struct A" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_struct(%struct.A* byval %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !20 !kernel_arg_base_type !20 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_i128: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "test_i128" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .ascii "i128" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_i128(i128 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !21 !kernel_arg_base_type !21 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_multi_arg: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 14 +; CHECK-NEXT: .ascii "test_multi_arg" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 3 +; CHECK-NEXT: .ascii "int" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 6 +; CHECK-NEXT: .ascii "short2" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 3 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "char3" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 1 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_multi_arg(i32 %a, <2 x i16> %b, <3 x i8> %c) !kernel_arg_addr_space !22 !kernel_arg_access_qual !23 !kernel_arg_type !24 !kernel_arg_base_type !24 !kernel_arg_type_qual !25 { + ret void +} + +; CHECK-LABEL:{{^}}test_addr_space: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 15 +; CHECK-NEXT: .ascii "test_addr_space" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_addr_space(i32 addrspace(1)* %g, i32 addrspace(2)* %c, i32 addrspace(3)* %l) !kernel_arg_addr_space !50 !kernel_arg_access_qual !23 !kernel_arg_type !51 !kernel_arg_base_type !51 !kernel_arg_type_qual !25 { + ret void +} + +; CHECK-LABEL:{{^}}test_type_qual: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 14 +; CHECK-NEXT: .ascii "test_type_qual" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 19 +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 17 +; CHECK-NEXT: .byte 18 +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "int *" +; CHECK-NEXT: .byte 20 +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_type_qual(i32 addrspace(1)* %a, i32 addrspace(1)* %b, %opencl.pipe_t addrspace(1)* %c) !kernel_arg_addr_space !22 !kernel_arg_access_qual !23 !kernel_arg_type !51 !kernel_arg_base_type !51 !kernel_arg_type_qual !70 { + ret void +} + +; CHECK-LABEL:{{^}}test_access_qual: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .ascii "test_access_qual" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "image1d_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "image2d_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 9 +; CHECK-NEXT: .ascii "image3d_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_access_qual(%opencl.image1d_t addrspace(1)* %ro, %opencl.image2d_t addrspace(1)* %wo, %opencl.image3d_t addrspace(1)* %rw) !kernel_arg_addr_space !60 !kernel_arg_access_qual !61 !kernel_arg_type !62 !kernel_arg_base_type !62 !kernel_arg_type_qual !25 { + ret void +} + +; CHECK-LABEL:{{^}}test_reqd_wgs_vec_type_hint: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 27 +; CHECK-NEXT: .ascii "test_reqd_wgs_vec_type_hint" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 3 +; CHECK-NEXT: .ascii "int" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 21 +; CHECK-NEXT: .long 1 +; CHECK-NEXT: .long 2 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 23 +; CHECK-NEXT: .long 3 +; CHECK-NEXT: .ascii "int" +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_reqd_wgs_vec_type_hint(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !5 !reqd_work_group_size !6 { + ret void +} + +; CHECK-LABEL:{{^}}test_wgs_hint_vec_type_hint: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 27 +; CHECK-NEXT: .ascii "test_wgs_hint_vec_type_hint" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 3 +; CHECK-NEXT: .ascii "int" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 22 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .long 32 +; CHECK-NEXT: .byte 23 +; CHECK-NEXT: .long 5 +; CHECK-NEXT: .ascii "uint4" +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_wgs_hint_vec_type_hint(i32 %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !3 !kernel_arg_base_type !3 !kernel_arg_type_qual !4 !vec_type_hint !7 !work_group_size_hint !8 { + ret void +} + +; CHECK-LABEL:{{^}}test_arg_ptr_to_ptr: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 19 +; CHECK-NEXT: .ascii "test_arg_ptr_to_ptr" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 6 +; CHECK-NEXT: .ascii "int **" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_arg_ptr_to_ptr(i32 * addrspace(1)* %a) !kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !80 !kernel_arg_base_type !80 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_arg_struct_contains_ptr: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 28 +; CHECK-NEXT: .ascii "test_arg_struct_contains_ptr" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 4 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .ascii "struct B" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_arg_struct_contains_ptr(%struct.B * byval %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !82 !kernel_arg_base_type !82 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_arg_vector_of_ptr: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 22 +; CHECK-NEXT: .ascii "test_arg_vector_of_ptr" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 16 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 47 +; CHECK-NEXT: .ascii "global int* __attribute__((ext_vector_type(2)))" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 6 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_arg_vector_of_ptr(<2 x i32 addrspace(1)*> %a) !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !83 !kernel_arg_base_type !83 !kernel_arg_type_qual !4 { + ret void +} + +; CHECK-LABEL:{{^}}test_arg_unknown_builtin_type: +; CHECK: .section .AMDGPU.runtime_metadata +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 6 +; CHECK-NEXT: .long 29 +; CHECK-NEXT: .ascii "test_arg_unknown_builtin_type" +; CHECK-NEXT: .byte 7 +; CHECK-NEXT: .byte 9 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 10 +; CHECK-NEXT: .long 8 +; CHECK-NEXT: .byte 11 +; CHECK-NEXT: .long 11 +; CHECK-NEXT: .ascii "clk_event_t" +; CHECK-NEXT: .byte 13 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 14 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .byte 15 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .byte 5 + +define amdgpu_kernel void @test_arg_unknown_builtin_type(%opencl.clk_event_t addrspace(1)* %a) !kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !84 !kernel_arg_base_type !84 !kernel_arg_type_qual !4 { + ret void +} + +!1 = !{i32 0} +!2 = !{!"none"} +!3 = !{!"int"} +!4 = !{!""} +!5 = !{i32 undef, i32 1} +!6 = !{i32 1, i32 2, i32 4} +!7 = !{<4 x i32> undef, i32 0} +!8 = !{i32 8, i32 16, i32 32} +!9 = !{!"char"} +!10 = !{!"ushort2"} +!11 = !{!"int3"} +!12 = !{!"ulong4"} +!13 = !{!"half8"} +!14 = !{!"float16"} +!15 = !{!"double16"} +!16 = !{!"int *"} +!17 = !{!"image2d_t"} +!18 = !{!"sampler_t"} +!19 = !{!"queue_t"} +!20 = !{!"struct A"} +!21 = !{!"i128"} +!22 = !{i32 0, i32 0, i32 0} +!23 = !{!"none", !"none", !"none"} +!24 = !{!"int", !"short2", !"char3"} +!25 = !{!"", !"", !""} +!50 = !{i32 1, i32 2, i32 3} +!51 = !{!"int *", !"int *", !"int *"} +!60 = !{i32 1, i32 1, i32 1} +!61 = !{!"read_only", !"write_only", !"read_write"} +!62 = !{!"image1d_t", !"image2d_t", !"image3d_t"} +!70 = !{!"volatile", !"const restrict", !"pipe"} +!80 = !{!"int **"} +!81 = !{i32 1} +!82 = !{!"struct B"} +!83 = !{!"global int* __attribute__((ext_vector_type(2)))"} +!84 = !{!"clk_event_t"} +!opencl.ocl.version = !{!90} +!90 = !{i32 2, i32 0} diff --git a/test/CodeGen/AMDGPU/rv7x0_count3.ll b/test/CodeGen/AMDGPU/rv7x0_count3.ll index c3fd923e4593..50df64bf5471 100644 --- a/test/CodeGen/AMDGPU/rv7x0_count3.ll +++ b/test/CodeGen/AMDGPU/rv7x0_count3.ll @@ -1,41 +1,52 @@ ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s ; CHECK: TEX 9 @6 ; encoding: [0x06,0x00,0x00,0x00,0x00,0x04,0x88,0x80] - -define void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { - %1 = extractelement <4 x float> %reg1, i32 0 - %2 = extractelement <4 x float> %reg1, i32 1 - %3 = extractelement <4 x float> %reg1, i32 2 - %4 = extractelement <4 x float> %reg1, i32 3 - %5 = insertelement <4 x float> undef, float %1, i32 0 - %6 = insertelement <4 x float> %5, float %2, i32 1 - %7 = insertelement <4 x float> %6, float %3, i32 2 - %8 = insertelement <4 x float> %7, float %4, i32 3 - %9 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 0, i32 0, i32 1) - %10 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 1, i32 0, i32 1) - %11 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 2, i32 0, i32 1) - %12 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 3, i32 0, i32 1) - %13 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 4, i32 0, i32 1) - %14 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 5, i32 0, i32 1) - %15 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 6, i32 0, i32 1) - %16 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 7, i32 0, i32 1) - %17 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 8, i32 0, i32 1) - %18 = call <4 x float> @llvm.AMDGPU.tex(<4 x float> %8, i32 9, i32 0, i32 1) - %19 = fadd <4 x float> %9, %10 - %20 = fadd <4 x float> %19, %11 - %21 = fadd <4 x float> %20, %12 - %22 = fadd <4 x float> %21, %13 - %23 = fadd <4 x float> %22, %14 - %24 = fadd <4 x float> %23, %15 - %25 = fadd <4 x float> %24, %16 - %26 = fadd <4 x float> %25, %17 - %27 = fadd <4 x float> %26, %18 - call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2) - ret void +define amdgpu_vs void @test(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { +bb: + %tmp = extractelement <4 x float> %reg1, i32 0 + %tmp1 = extractelement <4 x float> %reg1, i32 1 + %tmp2 = extractelement <4 x float> %reg1, i32 2 + %tmp3 = extractelement <4 x float> %reg1, i32 3 + %tmp4 = insertelement <4 x float> undef, float %tmp, i32 0 + %tmp5 = insertelement <4 x float> %tmp4, float %tmp1, i32 1 + %tmp6 = insertelement <4 x float> %tmp5, float %tmp2, i32 2 + %tmp7 = insertelement <4 x float> %tmp6, float %tmp3, i32 3 + %tmp8 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp10 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp12 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp14 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp16 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp18 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp20 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp22 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp24 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp26 = shufflevector <4 x float> %tmp7, <4 x float> %tmp7, <4 x i32> + %tmp27 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp26, i32 0, i32 0, i32 0, i32 9, i32 0, i32 1, i32 1, i32 1, i32 1) + %tmp28 = fadd <4 x float> %tmp9, %tmp11 + %tmp29 = fadd <4 x float> %tmp28, %tmp13 + %tmp30 = fadd <4 x float> %tmp29, %tmp15 + %tmp31 = fadd <4 x float> %tmp30, %tmp17 + %tmp32 = fadd <4 x float> %tmp31, %tmp19 + %tmp33 = fadd <4 x float> %tmp32, %tmp21 + %tmp34 = fadd <4 x float> %tmp33, %tmp23 + %tmp35 = fadd <4 x float> %tmp34, %tmp25 + %tmp36 = fadd <4 x float> %tmp35, %tmp27 + call void @llvm.r600.store.swizzle(<4 x float> %tmp36, i32 0, i32 2) + ret void } -declare <4 x float> @llvm.AMDGPU.tex(<4 x float>, i32, i32, i32) readnone +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) #0 -attributes #0 = { "ShaderType"="1" } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/s_addk_i32.ll b/test/CodeGen/AMDGPU/s_addk_i32.ll new file mode 100644 index 000000000000..987056010e69 --- /dev/null +++ b/test/CodeGen/AMDGPU/s_addk_i32.ll @@ -0,0 +1,93 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +; SI-LABEL: {{^}}s_addk_i32_k0: +; SI: s_load_dword [[VAL:s[0-9]+]] +; SI: s_addk_i32 [[VAL]], 0x41 +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VRESULT]] +; SI: s_endpgm +define void @s_addk_i32_k0(i32 addrspace(1)* %out, i32 %b) { + %add = add i32 %b, 65 + store i32 %add, i32 addrspace(1)* %out + ret void +} + +; FIXME: This should be folded with any number of uses. +; SI-LABEL: {{^}}s_addk_i32_k0_x2: +; SI: s_movk_i32 [[K:s[0-9]+]], 0x41 +; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] +; SI-DAG: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, [[K]] +; SI: s_endpgm +define void @s_addk_i32_k0_x2(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %a, i32 %b) { + %add0 = add i32 %a, 65 + %add1 = add i32 %b, 65 + store i32 %add0, i32 addrspace(1)* %out0 + store i32 %add1, i32 addrspace(1)* %out1 + ret void +} + +; SI-LABEL: {{^}}s_addk_i32_k1: +; SI: s_addk_i32 {{s[0-9]+}}, 0x7fff{{$}} +; SI: s_endpgm +define void @s_addk_i32_k1(i32 addrspace(1)* %out, i32 %b) { + %add = add i32 %b, 32767 ; (1 << 15) - 1 + store i32 %add, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_addk_i32_k2: +; SI: s_addk_i32 {{s[0-9]+}}, 0xffef{{$}} +; SI: s_endpgm +define void @s_addk_i32_k2(i32 addrspace(1)* %out, i32 %b) { + %add = add i32 %b, -17 + store i32 %add, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_addk_v2i32_k0: +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42 +; SI: s_endpgm +define void @s_addk_v2i32_k0(<2 x i32> addrspace(1)* %out, <2 x i32> %b) { + %add = add <2 x i32> %b, + store <2 x i32> %add, <2 x i32> addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_addk_v4i32_k0: +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x43 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x44 +; SI: s_endpgm +define void @s_addk_v4i32_k0(<4 x i32> addrspace(1)* %out, <4 x i32> %b) { + %add = add <4 x i32> %b, + store <4 x i32> %add, <4 x i32> addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_addk_v8i32_k0: +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x41 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x42 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x43 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x44 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x45 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x46 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x47 +; SI-DAG: s_addk_i32 {{s[0-9]+}}, 0x48 +; SI: s_endpgm +define void @s_addk_v8i32_k0(<8 x i32> addrspace(1)* %out, <8 x i32> %b) { + %add = add <8 x i32> %b, + store <8 x i32> %add, <8 x i32> addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}no_s_addk_i32_k0: +; SI: s_add_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8000{{$}} +; SI: s_endpgm +define void @no_s_addk_i32_k0(i32 addrspace(1)* %out, i32 %b) { + %add = add i32 %b, 32768 ; 1 << 15 + store i32 %add, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/s_mulk_i32.ll b/test/CodeGen/AMDGPU/s_mulk_i32.ll new file mode 100644 index 000000000000..33d7eeacdb83 --- /dev/null +++ b/test/CodeGen/AMDGPU/s_mulk_i32.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s + +; SI-LABEL: {{^}}s_mulk_i32_k0: +; SI: s_load_dword [[VAL:s[0-9]+]] +; SI: s_mulk_i32 [[VAL]], 0x41 +; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]] +; SI: buffer_store_dword [[VRESULT]] +; SI: s_endpgm +define void @s_mulk_i32_k0(i32 addrspace(1)* %out, i32 %b) { + %mul = mul i32 %b, 65 + store i32 %mul, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_mulk_i32_k1: +; SI: s_mulk_i32 {{s[0-9]+}}, 0x7fff{{$}} +; SI: s_endpgm +define void @s_mulk_i32_k1(i32 addrspace(1)* %out, i32 %b) { + %mul = mul i32 %b, 32767 ; (1 << 15) - 1 + store i32 %mul, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}s_mulk_i32_k2: +; SI: s_mulk_i32 {{s[0-9]+}}, 0xffef{{$}} +; SI: s_endpgm +define void @s_mulk_i32_k2(i32 addrspace(1)* %out, i32 %b) { + %mul = mul i32 %b, -17 + store i32 %mul, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}no_s_mulk_i32_k0: +; SI: s_mul_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x8001{{$}} +; SI: s_endpgm +define void @no_s_mulk_i32_k0(i32 addrspace(1)* %out, i32 %b) { + %mul = mul i32 %b, 32769 ; 1 << 15 + 1 + store i32 %mul, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/salu-to-valu.ll b/test/CodeGen/AMDGPU/salu-to-valu.ll index 551f34339a12..52f3cceac2a0 100644 --- a/test/CodeGen/AMDGPU/salu-to-valu.ll +++ b/test/CodeGen/AMDGPU/salu-to-valu.ll @@ -2,8 +2,8 @@ ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s -declare i32 @llvm.r600.read.tidig.x() #0 -declare i32 @llvm.r600.read.tidig.y() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 +declare i32 @llvm.amdgcn.workitem.id.y() #0 ; In this test both the pointer and the offset operands to the ; BUFFER_LOAD instructions end up being stored in vgprs. This @@ -26,8 +26,8 @@ declare i32 @llvm.r600.read.tidig.y() #0 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() - %tmp1 = call i32 @llvm.r600.read.tidig.y() + %tmp = call i32 @llvm.amdgcn.workitem.id.x() + %tmp1 = call i32 @llvm.amdgcn.workitem.id.y() %tmp2 = sext i32 %tmp to i64 %tmp3 = sext i32 %tmp1 to i64 br label %loop @@ -51,12 +51,20 @@ done: ; preds = %loop } ; Test moving an SMRD instruction to the VALU +; FIXME: movs can be moved before nop to reduce count ; GCN-LABEL: {{^}}smrd_valu: -; FIXME: We should be using flat load for HSA. -; GCN: buffer_load_dword [[OUT:v[0-9]+]] -; GCN-NOHSA: buffer_store_dword [[OUT]] -; GCN-HSA: flat_store_dword [[OUT]] +; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0 +; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} +; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} +; SI: s_nop 3 +; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]] +; SI: s_mov_b32 + +; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8 +; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]] +; GCN-NOHSA: buffer_store_dword [[V_OUT]] +; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]] define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 { entry: %tmp = icmp ne i32 %a, 0 @@ -87,7 +95,7 @@ endif: ; preds = %else, %if ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp, 4 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4 %tmp3 = load i32, i32 addrspace(2)* %tmp2 @@ -104,10 +112,10 @@ entry: ; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: buffer_store_dword ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] -; GCN-HSA: flat_store_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] +; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} define void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %c) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = getelementptr i32, i32 addrspace(2)* %in, i32 %tmp %tmp3 = getelementptr i32, i32 addrspace(2)* %tmp2, i32 5000 %tmp4 = load i32, i32 addrspace(2)* %tmp3 @@ -127,7 +135,7 @@ entry: ; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] define void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(2)* %in, i64 %c) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = getelementptr i64, i64 addrspace(2)* %in, i32 %tmp %tmp3 = getelementptr i64, i64 addrspace(2)* %tmp2, i32 5000 %tmp4 = load i64, i64 addrspace(2)* %tmp3 @@ -149,7 +157,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] define void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in, <4 x i32> %c) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %in, i32 %tmp %tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %tmp2, i32 1234 %tmp4 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp3 @@ -185,7 +193,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 define void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in, <8 x i32> %c) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %in, i32 %tmp %tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %tmp2, i32 1234 %tmp4 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp3 @@ -196,22 +204,14 @@ entry: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16: -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}} -; GCN-NOHSA-NOT: v_add -; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}} +; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}} +; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}} +; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}} +; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}} +; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}} +; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}} +; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}} +; GCN-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} @@ -234,7 +234,7 @@ entry: ; GCN: s_endpgm define void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in, <16 x i32> %c) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %in, i32 %tmp %tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %tmp2, i32 1234 %tmp4 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp3 @@ -248,10 +248,10 @@ entry: ; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}] ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]] ; GCN-NOHSA: buffer_store_dword [[ADD]] -; GCN-HSA: flat_store_dword [[ADD]] +; GCN-HSA: flat_store_dword {{.*}}, [[ADD]] define void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in, i32 %a) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp, 4 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4 %tmp3 = load i32, i32 addrspace(2)* %tmp2 @@ -265,7 +265,7 @@ entry: ; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}} define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp, 4 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255 %tmp3 = load i32, i32 addrspace(2)* %tmp2 @@ -279,7 +279,7 @@ entry: ; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}] define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() #0 + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = add i32 %tmp, 4 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256 %tmp3 = load i32, i32 addrspace(2)* %tmp2 @@ -294,7 +294,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { entry: - %tmp0 = tail call i32 @llvm.r600.read.tidig.x() + %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)* %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4 @@ -317,7 +317,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 define void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { entry: - %tmp0 = tail call i32 @llvm.r600.read.tidig.x() + %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)* %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4 @@ -354,7 +354,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { entry: - %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1 + %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)* %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4 @@ -389,7 +389,7 @@ entry: ; GCN-HSA: flat_load_dwordx4 define void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { entry: - %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1 + %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)* %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4 @@ -431,5 +431,33 @@ entry: ret void } +; Make sure we legalize vopc operands after moving an sopc to the value. + +; {{^}}sopc_vopc_legalize_bug: +; GCN: s_load_dword [[SGPR:s[0-9]+]] +; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}} +; GCN: s_and_b64 vcc, exec, vcc +; GCN: s_cbranch_vccnz [[EXIT:[A-Z0-9_]+]] +; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; GCN-NOHSA: buffer_store_dword [[ONE]] +; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]] +; GCN; {{^}}[[EXIT]]: +; GCN: s_endpgm +define void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +bb3: ; preds = %bb2 + %tmp0 = bitcast i32 %cond to float + %tmp1 = fadd float %tmp0, 2.500000e-01 + %tmp2 = bitcast float %tmp1 to i32 + %tmp3 = icmp ult i32 %tmp2, %cond + br i1 %tmp3, label %bb6, label %bb7 + +bb6: + store i32 1, i32 addrspace(1)* %out + br label %bb7 + +bb7: ; preds = %bb3 + ret void +} + attributes #0 = { nounwind readnone } attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/scalar_to_vector.ll b/test/CodeGen/AMDGPU/scalar_to_vector.ll index 0970e5d30630..55b392a32729 100644 --- a/test/CodeGen/AMDGPU/scalar_to_vector.ll +++ b/test/CodeGen/AMDGPU/scalar_to_vector.ll @@ -1,15 +1,14 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s - +; XXX - Why the packing? ; FUNC-LABEL: {{^}}scalar_to_vector_v2i32: ; SI: buffer_load_dword [[VAL:v[0-9]+]], -; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: s_endpgm +; SI: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]] +; SI: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]] +; SI: v_or_b32_e32 v[[OR:[0-9]+]], [[SHL]], [[SHR]] +; SI: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]] +; SI: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}} define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %tmp1 = load i32, i32 addrspace(1)* %in, align 4 %bc = bitcast i32 %tmp1 to <2 x i16> @@ -21,11 +20,7 @@ define void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace( ; FUNC-LABEL: {{^}}scalar_to_vector_v2f32: ; SI: buffer_load_dword [[VAL:v[0-9]+]], ; SI: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: buffer_store_short [[RESULT]] -; SI: s_endpgm +; SI: buffer_store_dwordx2 define void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { %tmp1 = load float, float addrspace(1)* %in, align 4 %bc = bitcast float %tmp1 to <2 x i16> diff --git a/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll b/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll index 11e8f5176f44..e040639a2d94 100644 --- a/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll +++ b/test/CodeGen/AMDGPU/schedule-fs-loop-nested-if.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs ;REQUIRES: asserts -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #1 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -44,15 +44,15 @@ ENDIF: ; preds = %ELSE17, %ELSE, %IF %temp1.0 = phi float [ %., %IF ], [ %48, %ELSE17 ], [ 0.000000e+00, %ELSE ] %temp2.0 = phi float [ 0.000000e+00, %IF ], [ %49, %ELSE17 ], [ 1.000000e+00, %ELSE ] %temp.0 = phi float [ %.18, %IF ], [ %47, %ELSE17 ], [ 0.000000e+00, %ELSE ] - %27 = call float @llvm.AMDIL.clamp.(float %temp.0, float 0.000000e+00, float 1.000000e+00) - %28 = call float @llvm.AMDIL.clamp.(float %temp1.0, float 0.000000e+00, float 1.000000e+00) - %29 = call float @llvm.AMDIL.clamp.(float %temp2.0, float 0.000000e+00, float 1.000000e+00) - %30 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) + %27 = call float @llvm.AMDGPU.clamp.f32(float %temp.0, float 0.000000e+00, float 1.000000e+00) + %28 = call float @llvm.AMDGPU.clamp.f32(float %temp1.0, float 0.000000e+00, float 1.000000e+00) + %29 = call float @llvm.AMDGPU.clamp.f32(float %temp2.0, float 0.000000e+00, float 1.000000e+00) + %30 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %31 = insertelement <4 x float> undef, float %27, i32 0 %32 = insertelement <4 x float> %31, float %28, i32 1 %33 = insertelement <4 x float> %32, float %29, i32 2 %34 = insertelement <4 x float> %33, float %30, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %34, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %34, i32 0, i32 0) ret void ELSE17: ; preds = %ELSE @@ -74,9 +74,8 @@ ELSE17: ; preds = %ELSE br label %ENDIF } -declare float @llvm.AMDIL.clamp.(float, float, float) #0 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { readnone } -attributes #1 = { "ShaderType"="1" } diff --git a/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll b/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll index 759197ca61f7..f907e154f962 100644 --- a/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll +++ b/test/CodeGen/AMDGPU/schedule-fs-loop-nested.ll @@ -43,15 +43,15 @@ LOOP: ; preds = %IF31, %main_body br i1 %29, label %IF, label %LOOP29 IF: ; preds = %LOOP - %30 = call float @llvm.AMDIL.clamp.(float %temp4.0, float 0.000000e+00, float 1.000000e+00) - %31 = call float @llvm.AMDIL.clamp.(float %temp5.0, float 0.000000e+00, float 1.000000e+00) - %32 = call float @llvm.AMDIL.clamp.(float %temp6.0, float 0.000000e+00, float 1.000000e+00) - %33 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) + %30 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00) + %31 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00) + %32 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00) + %33 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %34 = insertelement <4 x float> undef, float %30, i32 0 %35 = insertelement <4 x float> %34, float %31, i32 1 %36 = insertelement <4 x float> %35, float %32, i32 2 %37 = insertelement <4 x float> %36, float %33, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %37, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %37, i32 0, i32 0) ret void LOOP29: ; preds = %LOOP, %ENDIF30 @@ -81,8 +81,8 @@ ENDIF30: ; preds = %LOOP29 br label %LOOP29 } -declare float @llvm.AMDIL.clamp.(float, float, float) #0 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/schedule-fs-loop.ll b/test/CodeGen/AMDGPU/schedule-fs-loop.ll index 28cc08abc022..5839785f00d5 100644 --- a/test/CodeGen/AMDGPU/schedule-fs-loop.ll +++ b/test/CodeGen/AMDGPU/schedule-fs-loop.ll @@ -30,15 +30,15 @@ LOOP: ; preds = %ENDIF, %main_body br i1 %16, label %IF, label %ENDIF IF: ; preds = %LOOP - %17 = call float @llvm.AMDIL.clamp.(float %temp4.0, float 0.000000e+00, float 1.000000e+00) - %18 = call float @llvm.AMDIL.clamp.(float %temp5.0, float 0.000000e+00, float 1.000000e+00) - %19 = call float @llvm.AMDIL.clamp.(float %temp6.0, float 0.000000e+00, float 1.000000e+00) - %20 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) + %17 = call float @llvm.AMDGPU.clamp.f32(float %temp4.0, float 0.000000e+00, float 1.000000e+00) + %18 = call float @llvm.AMDGPU.clamp.f32(float %temp5.0, float 0.000000e+00, float 1.000000e+00) + %19 = call float @llvm.AMDGPU.clamp.f32(float %temp6.0, float 0.000000e+00, float 1.000000e+00) + %20 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) %21 = insertelement <4 x float> undef, float %17, i32 0 %22 = insertelement <4 x float> %21, float %18, i32 1 %23 = insertelement <4 x float> %22, float %19, i32 2 %24 = insertelement <4 x float> %23, float %20, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %24, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %24, i32 0, i32 0) ret void ENDIF: ; preds = %LOOP @@ -48,8 +48,8 @@ ENDIF: ; preds = %LOOP br label %LOOP } -declare float @llvm.AMDIL.clamp.(float, float, float) #0 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #0 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/schedule-global-loads.ll b/test/CodeGen/AMDGPU/schedule-global-loads.ll index 3f728fd873b3..1bf109dec032 100644 --- a/test/CodeGen/AMDGPU/schedule-global-loads.ll +++ b/test/CodeGen/AMDGPU/schedule-global-loads.ll @@ -1,21 +1,19 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() #1 - ; FIXME: This currently doesn't do a great job of clustering the ; loads, which end up with extra moves between them. Right now, it ; seems the only things areLoadsFromSameBasePtr is accomplishing is ; ordering the loads so that the lower address loads come first. ; FUNC-LABEL: {{^}}cluster_global_arg_loads: -; SI-DAG: buffer_load_dword [[REG0:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; SI-DAG: buffer_load_dword [[REG1:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 +; SI-DAG: buffer_load_dword [[REG0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; SI-DAG: buffer_load_dword [[REG1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:8 ; SI: buffer_store_dword [[REG0]] ; SI: buffer_store_dword [[REG1]] define void @cluster_global_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr) #0 { %load0 = load i32, i32 addrspace(1)* %ptr, align 4 - %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 1 + %gep = getelementptr i32, i32 addrspace(1)* %ptr, i32 2 %load1 = load i32, i32 addrspace(1)* %gep, align 4 store i32 %load0, i32 addrspace(1)* %out0, align 4 store i32 %load1, i32 addrspace(1)* %out1, align 4 diff --git a/test/CodeGen/AMDGPU/schedule-if-2.ll b/test/CodeGen/AMDGPU/schedule-if-2.ll index 549465096833..aa67b2e0f7db 100644 --- a/test/CodeGen/AMDGPU/schedule-if-2.ll +++ b/test/CodeGen/AMDGPU/schedule-if-2.ll @@ -66,7 +66,7 @@ ENDIF: ; preds = %IF23, %ELSE, %IF %45 = insertelement <4 x float> %44, float %temp5.0, i32 1 %46 = insertelement <4 x float> %45, float %temp6.0, i32 2 %47 = insertelement <4 x float> %46, float %temp7.0, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %47, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %47, i32 0, i32 0) ret void IF23: ; preds = %ELSE @@ -89,6 +89,6 @@ IF23: ; preds = %ELSE declare float @fabs(float) #0 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) attributes #0 = { readonly } diff --git a/test/CodeGen/AMDGPU/schedule-if.ll b/test/CodeGen/AMDGPU/schedule-if.ll index 94c653c8f25b..6637b3897717 100644 --- a/test/CodeGen/AMDGPU/schedule-if.ll +++ b/test/CodeGen/AMDGPU/schedule-if.ll @@ -32,7 +32,7 @@ ENDIF: ; preds = %IF13, %ELSE, %main_ %17 = insertelement <4 x float> %16, float %temp1.0, i32 1 %18 = insertelement <4 x float> %17, float 0.000000e+00, i32 2 %19 = insertelement <4 x float> %18, float %temp3.0, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %19, i32 0, i32 0) ret void IF13: ; preds = %ELSE @@ -43,4 +43,4 @@ IF13: ; preds = %ELSE br label %ENDIF } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll b/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll index 6b3e0814c380..886d4a1dcb5c 100644 --- a/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll +++ b/test/CodeGen/AMDGPU/schedule-kernel-arg-loads.ll @@ -1,18 +1,17 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI --check-prefix=GCN %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI --check-prefix=GCN %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=VI -check-prefix=GCN %s ; FUNC-LABEL: {{^}}cluster_arg_loads: +; FIXME: Due to changes in the load clustering heuristics. We no longer +; cluster all argument loads together on SI. +; SI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; SI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9 ; SI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; SI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xe +; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 ; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24 -; VI-NEXT: s_nop 0 -; VI-NEXT: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI-NEXT: s_nop 0 -; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34 -; VI-NEXT: s_nop 0 -; VI-NEXT: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38 +; VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI: s_load_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0x38 define void @cluster_arg_loads(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) nounwind { store i32 %x, i32 addrspace(1)* %out0, align 4 store i32 %y, i32 addrspace(1)* %out1, align 4 diff --git a/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll b/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll index e4b16c0a165f..9b490bb3a731 100644 --- a/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll +++ b/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop-failure.ll @@ -1,13 +1,10 @@ -; XFAIL: * -; REQUIRES: asserts -; RUN: llc -O0 -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI -; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck %s -check-prefix=SI +; RUN: llc -O0 -march=amdgcn -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -O0 -march=amdgcn -mcpu=tonga -verify-machineinstrs -mattr=+vgpr-spilling < %s | FileCheck -check-prefix=GCN %s -declare void @llvm.AMDGPU.barrier.local() nounwind convergent +declare void @llvm.amdgcn.s.barrier() nounwind convergent - -; SI-LABEL: {{^}}main( -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +; GCN-LABEL: {{^}}main: +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 2 @@ -39,63 +36,63 @@ ENDIF: ; preds = %main_body, %Flow2 %temp3.0 = phi float [ 0.000000e+00, %main_body ], [ %101, %Flow2 ] %15 = extractelement <4 x float> %reg1, i32 1 %16 = extractelement <4 x float> %reg1, i32 3 - %17 = load <4 x float>, <4 x float> addrspace(9)* null + %17 = load <4 x float>, <4 x float> addrspace(2)* null %18 = extractelement <4 x float> %17, i32 0 %19 = fmul float %18, %0 - %20 = load <4 x float>, <4 x float> addrspace(9)* null + %20 = load <4 x float>, <4 x float> addrspace(2)* null %21 = extractelement <4 x float> %20, i32 1 %22 = fmul float %21, %0 - %23 = load <4 x float>, <4 x float> addrspace(9)* null + %23 = load <4 x float>, <4 x float> addrspace(2)* null %24 = extractelement <4 x float> %23, i32 2 %25 = fmul float %24, %0 - %26 = load <4 x float>, <4 x float> addrspace(9)* null + %26 = load <4 x float>, <4 x float> addrspace(2)* null %27 = extractelement <4 x float> %26, i32 3 %28 = fmul float %27, %0 - %29 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1) + %29 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 1) %30 = extractelement <4 x float> %29, i32 0 %31 = fmul float %30, %15 %32 = fadd float %31, %19 - %33 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1) + %33 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 1) %34 = extractelement <4 x float> %33, i32 1 %35 = fmul float %34, %15 %36 = fadd float %35, %22 - %37 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1) + %37 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 1) %38 = extractelement <4 x float> %37, i32 2 %39 = fmul float %38, %15 %40 = fadd float %39, %25 - %41 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 1) + %41 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 1) %42 = extractelement <4 x float> %41, i32 3 %43 = fmul float %42, %15 %44 = fadd float %43, %28 - %45 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2) + %45 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 2) %46 = extractelement <4 x float> %45, i32 0 %47 = fmul float %46, %1 %48 = fadd float %47, %32 - %49 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2) + %49 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 2) %50 = extractelement <4 x float> %49, i32 1 %51 = fmul float %50, %1 %52 = fadd float %51, %36 - %53 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2) + %53 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 2) %54 = extractelement <4 x float> %53, i32 2 %55 = fmul float %54, %1 %56 = fadd float %55, %40 - %57 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 2) + %57 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 2) %58 = extractelement <4 x float> %57, i32 3 %59 = fmul float %58, %1 %60 = fadd float %59, %44 - %61 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3) + %61 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 3) %62 = extractelement <4 x float> %61, i32 0 %63 = fmul float %62, %16 %64 = fadd float %63, %48 - %65 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3) + %65 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 3) %66 = extractelement <4 x float> %65, i32 1 %67 = fmul float %66, %16 %68 = fadd float %67, %52 - %69 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3) + %69 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 3) %70 = extractelement <4 x float> %69, i32 2 %71 = fmul float %70, %16 %72 = fadd float %71, %56 - %73 = load <4 x float>, <4 x float> addrspace(9)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(9)* null, i64 0, i32 3) + %73 = load <4 x float>, <4 x float> addrspace(2)* getelementptr ([1024 x <4 x float>], [1024 x <4 x float>] addrspace(2)* null, i64 0, i32 3) %74 = extractelement <4 x float> %73, i32 3 %75 = fmul float %74, %16 %76 = fadd float %75, %60 @@ -103,12 +100,12 @@ ENDIF: ; preds = %main_body, %Flow2 %78 = insertelement <4 x float> %77, float %68, i32 1 %79 = insertelement <4 x float> %78, float %72, i32 2 %80 = insertelement <4 x float> %79, float %76, i32 3 - call void @llvm.AMDGPU.barrier.local() + call void @llvm.amdgcn.s.barrier() %81 = insertelement <4 x float> undef, float %temp.0, i32 0 %82 = insertelement <4 x float> %81, float %temp1.0, i32 1 %83 = insertelement <4 x float> %82, float %temp2.0, i32 2 %84 = insertelement <4 x float> %83, float %temp3.0, i32 3 - call void @llvm.AMDGPU.barrier.local() + call void @llvm.amdgcn.s.barrier() ret void LOOP: ; preds = %main_body, %Flow @@ -159,5 +156,3 @@ ENDIF19: ; preds = %ENDIF16 %115 = fadd float %temp4.0, 1.000000e+00 br label %Flow1 } - -attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll b/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll index 8d980dbf8995..00d4ba66913d 100644 --- a/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll +++ b/test/CodeGen/AMDGPU/schedule-vs-if-nested-loop.ll @@ -1,7 +1,7 @@ ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched ;REQUIRES: asserts -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -85,12 +85,12 @@ ENDIF: ; preds = %ENDIF16, %LOOP, %ma %72 = insertelement <4 x float> %71, float %62, i32 1 %73 = insertelement <4 x float> %72, float %66, i32 2 %74 = insertelement <4 x float> %73, float %70, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %74, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %74, i32 60, i32 1) %75 = insertelement <4 x float> undef, float %temp.0, i32 0 %76 = insertelement <4 x float> %75, float %temp1.0, i32 1 %77 = insertelement <4 x float> %76, float %temp2.0, i32 2 %78 = insertelement <4 x float> %77, float %temp3.0, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %78, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %78, i32 0, i32 2) ret void LOOP: ; preds = %main_body, %ENDIF19 @@ -127,6 +127,4 @@ ENDIF19: ; preds = %ENDIF16 br label %LOOP } -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/scratch-buffer.ll b/test/CodeGen/AMDGPU/scratch-buffer.ll index d43de4766057..a66f074123c1 100644 --- a/test/CodeGen/AMDGPU/scratch-buffer.ll +++ b/test/CodeGen/AMDGPU/scratch-buffer.ll @@ -1,7 +1,5 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck --check-prefix=GCN --check-prefix=DEFAULT-SCRATCH %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=GCN --check-prefix=DEFAULT-SCRATCH %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+huge-scratch-buffer -mcpu=SI < %s | FileCheck --check-prefix=GCN --check-prefix=HUGE-SCRATCH %s -; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+huge-scratch-buffer -mcpu=tonga < %s | FileCheck --check-prefix=GCN --check-prefix=HUGE-SCRATCH %s +; RUN: llc -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GCN %s ; When a frame index offset is more than 12-bits, make sure we don't store ; it in mubuf's offset field. @@ -49,8 +47,8 @@ done: } -; GCN-LABEL: {{^}}legal_offset_fi_offset -; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen +; GCN-LABEL: {{^}}legal_offset_fi_offset: +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN: v_add_i32_e32 [[OFFSET:v[0-9]+]], vcc, 0x8000 ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} @@ -87,11 +85,8 @@ done: ret void } -; GCN-LABEL: @neg_vaddr_offset -; We can't prove %offset is positive, so we must do the computation with the -; immediate in an add instruction instead of folding offset and the immediate into -; the store instruction. -; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} +; GCN-LABEL: {{^}}neg_vaddr_offset: +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16{{$}} define void @neg_vaddr_offset(i32 %offset) { entry: %array = alloca [8192 x i32] @@ -101,9 +96,8 @@ entry: ret void } -; GCN-LABEL: @pos_vaddr_offse -; DEFAULT-SCRATCH: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16 -; HUGE-SCRATCH: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} +; GCN-LABEL: {{^}}pos_vaddr_offset: +; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:16 define void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) { entry: %array = alloca [8192 x i32] diff --git a/test/CodeGen/AMDGPU/sdiv.ll b/test/CodeGen/AMDGPU/sdiv.ll index de645353a401..29d893414c07 100644 --- a/test/CodeGen/AMDGPU/sdiv.ll +++ b/test/CodeGen/AMDGPU/sdiv.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s @@ -34,8 +34,8 @@ define void @sdiv_i32_4(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ; working. ; FUNC-LABEL: {{^}}slow_sdiv_i32_3435: -; SI: buffer_load_dword [[VAL:v[0-9]+]], -; SI: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]], +; SI-DAG: v_mov_b32_e32 [[MAGIC:v[0-9]+]], 0x98a1930b ; SI: v_mul_hi_i32 [[TMP:v[0-9]+]], [[MAGIC]], [[VAL]] ; SI: v_add_i32 ; SI: v_lshrrev_b32 @@ -82,6 +82,60 @@ define void @sdiv_v4i32_4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* ret void } +; FUNC-LABEL: {{^}}v_sdiv_i8: +; SI: v_rcp_f32 +; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 8 +; SI: buffer_store_dword [[BFE]] +define void @v_sdiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { + %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 + %num = load i8, i8 addrspace(1) * %in + %den = load i8, i8 addrspace(1) * %den_ptr + %result = sdiv i8 %num, %den + %result.ext = sext i8 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_sdiv_i23: +; SI: v_rcp_f32 +; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 23 +; SI: buffer_store_dword [[BFE]] +define void @v_sdiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) { + %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1 + %num = load i23, i23 addrspace(1) * %in + %den = load i23, i23 addrspace(1) * %den_ptr + %result = sdiv i23 %num, %den + %result.ext = sext i23 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_sdiv_i24: +; SI: v_rcp_f32 +; SI: v_bfe_i32 [[BFE:v[0-9]+]], v{{[0-9]+}}, 0, 24 +; SI: buffer_store_dword [[BFE]] +define void @v_sdiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { + %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1 + %num = load i24, i24 addrspace(1) * %in + %den = load i24, i24 addrspace(1) * %den_ptr + %result = sdiv i24 %num, %den + %result.ext = sext i24 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_sdiv_i25: +; SI-NOT: v_rcp_f32 +define void @v_sdiv_i25(i32 addrspace(1)* %out, i25 addrspace(1)* %in) { + %den_ptr = getelementptr i25, i25 addrspace(1)* %in, i25 1 + %num = load i25, i25 addrspace(1) * %in + %den = load i25, i25 addrspace(1) * %den_ptr + %result = sdiv i25 %num, %den + %result.ext = sext i25 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + ; Tests for 64-bit divide bypass. ; define void @test_get_quotient(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { ; %result = sdiv i64 %a, %b diff --git a/test/CodeGen/AMDGPU/sdivrem24.ll b/test/CodeGen/AMDGPU/sdivrem24.ll index ad5df39f5505..ccabd3c2a969 100644 --- a/test/CodeGen/AMDGPU/sdivrem24.ll +++ b/test/CodeGen/AMDGPU/sdivrem24.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s @@ -181,13 +181,13 @@ define void @srem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ret void } -; FUNC-LABEL: {{^}}srem25_i32: +; FUNC-LABEL: {{^}}no_srem25_i32: ; SI-NOT: v_cvt_f32_i32 ; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE -define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +define void @no_srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 %den = load i32, i32 addrspace(1) * %den_ptr, align 4 @@ -200,40 +200,138 @@ define void @srem25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ret void } -; FUNC-LABEL: {{^}}test_no_srem24_i32_1: +; FUNC-LABEL: {{^}}no_sdiv25_i24_i25_i32: ; SI-NOT: v_cvt_f32_i32 ; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE -define void @test_no_srem24_i32_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +define void @no_sdiv25_i24_i25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 %den = load i32, i32 addrspace(1) * %den_ptr, align 4 %num.i24.0 = shl i32 %num, 8 - %den.i24.0 = shl i32 %den, 7 + %den.i25.0 = shl i32 %den, 7 %num.i24 = ashr i32 %num.i24.0, 8 - %den.i24 = ashr i32 %den.i24.0, 7 - %result = srem i32 %num.i24, %den.i24 + %den.i25 = ashr i32 %den.i25.0, 7 + %result = sdiv i32 %num.i24, %den.i25 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } -; FUNC-LABEL: {{^}}test_no_srem24_i32_2: +; FUNC-LABEL: {{^}}no_sdiv25_i25_i24_i32: ; SI-NOT: v_cvt_f32_i32 ; SI-NOT: v_rcp_f32 ; EG-NOT: INT_TO_FLT ; EG-NOT: RECIP_IEEE -define void @test_no_srem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { +define void @no_sdiv25_i25_i24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 %den = load i32, i32 addrspace(1) * %den_ptr, align 4 - %num.i24.0 = shl i32 %num, 7 + %num.i25.0 = shl i32 %num, 7 %den.i24.0 = shl i32 %den, 8 - %num.i24 = ashr i32 %num.i24.0, 7 + %num.i25 = ashr i32 %num.i25.0, 7 %den.i24 = ashr i32 %den.i24.0, 8 - %result = srem i32 %num.i24, %den.i24 + %result = sdiv i32 %num.i25, %den.i24 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}no_srem25_i24_i25_i32: +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 + +; EG-NOT: INT_TO_FLT +; EG-NOT: RECIP_IEEE +define void @no_srem25_i24_i25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i24.0 = shl i32 %num, 8 + %den.i25.0 = shl i32 %den, 7 + %num.i24 = ashr i32 %num.i24.0, 8 + %den.i25 = ashr i32 %den.i25.0, 7 + %result = srem i32 %num.i24, %den.i25 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}no_srem25_i25_i24_i32: +; SI-NOT: v_cvt_f32_i32 +; SI-NOT: v_rcp_f32 + +; EG-NOT: INT_TO_FLT +; EG-NOT: RECIP_IEEE +define void @no_srem25_i25_i24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i25.0 = shl i32 %num, 7 + %den.i24.0 = shl i32 %den, 8 + %num.i25 = ashr i32 %num.i25.0, 7 + %den.i24 = ashr i32 %den.i24.0, 8 + %result = srem i32 %num.i25, %den.i24 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}srem25_i24_i11_i32: +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 24 + +; EG: INT_TO_FLT +; EG: RECIP_IEEE +define void @srem25_i24_i11_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i24.0 = shl i32 %num, 8 + %den.i11.0 = shl i32 %den, 21 + %num.i24 = ashr i32 %num.i24.0, 8 + %den.i11 = ashr i32 %den.i11.0, 21 + %result = srem i32 %num.i24, %den.i11 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}srem25_i11_i24_i32: +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 24 + +; EG: INT_TO_FLT +; EG: RECIP_IEEE +define void @srem25_i11_i24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i11.0 = shl i32 %num, 21 + %den.i24.0 = shl i32 %den, 8 + %num.i11 = ashr i32 %num.i11.0, 21 + %den.i24 = ashr i32 %den.i24.0, 8 + %result = srem i32 %num.i11, %den.i24 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}srem25_i17_i12_i32: +; SI: v_cvt_f32_i32 +; SI: v_rcp_f32 +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 17 + +; EG: INT_TO_FLT +; EG: RECIP_IEEE +define void @srem25_i17_i12_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i17.0 = shl i32 %num, 15 + %den.i12.0 = shl i32 %den, 20 + %num.i17 = ashr i32 %num.i17.0, 15 + %den.i12 = ashr i32 %den.i12.0, 20 + %result = sdiv i32 %num.i17, %den.i12 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } diff --git a/test/CodeGen/AMDGPU/sdivrem64.ll b/test/CodeGen/AMDGPU/sdivrem64.ll index a9b2b7f9df55..a7ce948acd4f 100644 --- a/test/CodeGen/AMDGPU/sdivrem64.ll +++ b/test/CodeGen/AMDGPU/sdivrem64.ll @@ -1,8 +1,8 @@ -;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s +;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s -;FUNC-LABEL: {{^}}test_sdiv: +;FUNC-LABEL: {{^}}s_test_sdiv: ;EG: RECIP_UINT ;EG: LSHL {{.*}}, 1, ;EG: BFE_UINT @@ -36,47 +36,47 @@ ;EG: BFE_UINT ;EG: BFE_UINT -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN: v_bfe_u32 -;GCN-NOT: v_mad_f32 -;SI-NOT: v_lshr_b64 -;VI-NOT: v_lshrrev_b64 -;GCN: s_endpgm -define void @test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN: s_bfe_u32 +; GCN-NOT: v_mad_f32 +; SI-NOT: v_lshr_b64 +; VI-NOT: v_lshrrev_b64 +; GCN: s_endpgm +define void @s_test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { %result = sdiv i64 %x, %y store i64 %result, i64 addrspace(1)* %out ret void } -;FUNC-LABEL: {{^}}test_srem: +;FUNC-LABEL: {{^}}s_test_srem: ;EG: RECIP_UINT ;EG: BFE_UINT ;EG: BFE_UINT @@ -144,7 +144,7 @@ define void @test_sdiv(i64 addrspace(1)* %out, i64 %x, i64 %y) { ;SI-NOT: v_lshr_b64 ;VI-NOT: v_lshrrev_b64 ;GCN: s_endpgm -define void @test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { +define void @s_test_srem(i64 addrspace(1)* %out, i64 %x, i64 %y) { %result = urem i64 %x, %y store i64 %result, i64 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/select-i1.ll b/test/CodeGen/AMDGPU/select-i1.ll index 6735394e93a9..2406831b94c5 100644 --- a/test/CodeGen/AMDGPU/select-i1.ll +++ b/test/CodeGen/AMDGPU/select-i1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FIXME: This should go in existing select.ll test, except the current testcase there is broken on SI @@ -13,3 +13,15 @@ define void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind ret void } +; FUNC-LABEL: {{^}}s_minmax_i1: +; SI-DAG: buffer_load_ubyte [[COND:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:44 +; SI-DAG: buffer_load_ubyte [[A:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:45 +; SI-DAG: buffer_load_ubyte [[B:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:46 +; SI: v_cmp_eq_i32_e32 vcc, 1, [[COND]] +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, [[B]], [[A]] +define void @s_minmax_i1(i1 addrspace(1)* %out, i1 zeroext %cond, i1 zeroext %a, i1 zeroext %b) nounwind { + %cmp = icmp slt i1 %cond, false + %sel = select i1 %cmp, i1 %a, i1 %b + store i1 %sel, i1 addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/select-vectors.ll b/test/CodeGen/AMDGPU/select-vectors.ll index 94758ad84c18..faf8d8a12c25 100644 --- a/test/CodeGen/AMDGPU/select-vectors.ll +++ b/test/CodeGen/AMDGPU/select-vectors.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -verify-machineinstrs -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; Test expansion of scalar selects on vectors. @@ -29,30 +29,50 @@ define void @select_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> ret void } -; FUNC-LABEL: {{^}}select_v2i32: +; FIXME: Expansion with bitwise operations may be better if doing a +; vector select with SGPR inputs. + +; FUNC-LABEL: {{^}}s_select_v2i32: ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 ; SI: buffer_store_dwordx2 -define void @select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind { +define void @s_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x i32> %a, <2 x i32> %b store <2 x i32> %select, <2 x i32> addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: {{^}}select_v4i32: +; FUNC-LABEL: {{^}}s_select_v4i32: ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 ; SI: buffer_store_dwordx4 -define void @select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind { +define void @s_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x i32> %a, <4 x i32> %b store <4 x i32> %select, <4 x i32> addrspace(1)* %out, align 16 ret void } +; FUNC-LABEL: {{^}}v_select_v4i32: +; SI: buffer_load_dwordx4 +; SI: v_cmp_gt_u32_e64 vcc, 32, s{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: buffer_store_dwordx4 +define void @v_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %cond) #0 { +bb: + %tmp2 = icmp ult i32 %cond, 32 + %val = load <4 x i32>, <4 x i32> addrspace(1)* %in + %tmp3 = select i1 %tmp2, <4 x i32> %val, <4 x i32> zeroinitializer + store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %out, align 16 + ret void +} + ; FUNC-LABEL: {{^}}select_v8i32: ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 @@ -69,24 +89,61 @@ define void @select_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> ret void } -; FUNC-LABEL: {{^}}select_v2f32: +; FUNC-LABEL: {{^}}s_select_v2f32: +; SI-DAG: s_load_dwordx2 s{{\[}}[[ALO:[0-9]+]]:[[AHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} +; SI-DAG: s_load_dwordx2 s{{\[}}[[BLO:[0-9]+]]:[[BHI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xd|0x34}} + +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[ALO]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[AHI]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BLO]] +; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[BHI]] +; SI-DAG: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} + +; SI: v_cndmask_b32_e32 +; SI: v_cndmask_b32_e32 ; SI: buffer_store_dwordx2 -define void @select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind { +define void @s_select_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <2 x float> %a, <2 x float> %b store <2 x float> %select, <2 x float> addrspace(1)* %out, align 16 ret void } -; FUNC-LABEL: {{^}}select_v4f32: +; FUNC-LABEL: {{^}}s_select_v4f32: +; SI: s_load_dwordx4 +; SI: s_load_dwordx4 +; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}} + +; SI: v_cndmask_b32_e32 +; SI: v_cndmask_b32_e32 +; SI: v_cndmask_b32_e32 +; SI: v_cndmask_b32_e32 + ; SI: buffer_store_dwordx4 -define void @select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind { +define void @s_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b, i32 %c) nounwind { %cmp = icmp eq i32 %c, 0 %select = select i1 %cmp, <4 x float> %a, <4 x float> %b store <4 x float> %select, <4 x float> addrspace(1)* %out, align 16 ret void } +; FUNC-LABEL: {{^}}v_select_v4f32: +; SI: buffer_load_dwordx4 +; SI: v_cmp_gt_u32_e64 vcc, 32, s{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} +; SI: buffer_store_dwordx4 +define void @v_select_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in, i32 %cond) #0 { +bb: + %tmp2 = icmp ult i32 %cond, 32 + %val = load <4 x float>, <4 x float> addrspace(1)* %in + %tmp3 = select i1 %tmp2, <4 x float> %val, <4 x float> zeroinitializer + store <4 x float> %tmp3, <4 x float> addrspace(1)* %out, align 16 + ret void +} + ; FUNC-LABEL: {{^}}select_v8f32: ; SI: v_cndmask_b32_e32 ; SI: v_cndmask_b32_e32 @@ -154,3 +211,9 @@ define void @select_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, <8 x store <8 x double> %select, <8 x double> addrspace(1)* %out, align 16 ret void } + +; Function Attrs: nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/selected-stack-object.ll b/test/CodeGen/AMDGPU/selected-stack-object.ll new file mode 100644 index 000000000000..37f2747d9815 --- /dev/null +++ b/test/CodeGen/AMDGPU/selected-stack-object.ll @@ -0,0 +1,15 @@ +; "Assertion failure" should be caught with both XFAIL:* and +Asserts. +; XFAIL: * +; REQUIRES: asserts + +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s + +; See also local-stack-slot-bug.ll +; This fails because a stack object is created during instruction selection. + +; CHECK-LABEL: {{^}}main: +define amdgpu_ps float @main(i32 %idx) { +main_body: + %v1 = extractelement <81 x float> , i32 %idx + ret float %v1 +} diff --git a/test/CodeGen/AMDGPU/setcc-opt.ll b/test/CodeGen/AMDGPU/setcc-opt.ll index 63d74820f961..d2c57a810c2c 100644 --- a/test/CodeGen/AMDGPU/setcc-opt.ll +++ b/test/CodeGen/AMDGPU/setcc-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s @@ -36,34 +36,30 @@ define void @sext_bool_icmp_ne_0(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind ret void } -; This really folds away to false -; FUNC-LABEL: {{^}}sext_bool_icmp_eq_1: +; FUNC-LABEL: {{^}}sext_bool_icmp_eq_neg1: +; GCN-NOT: v_cmp ; GCN: v_cmp_eq_i32_e32 vcc, -; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc -; GCN-NEXT: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}} -; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1, -; GCN-NEXT: buffer_store_byte [[TMP]] +; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc +; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: s_endpgm -define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { +define void @sext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %icmp0 = icmp eq i32 %a, %b %ext = sext i1 %icmp0 to i32 - %icmp1 = icmp eq i32 %ext, 1 + %icmp1 = icmp eq i32 %ext, -1 store i1 %icmp1, i1 addrspace(1)* %out ret void } -; This really folds away to true -; FUNC-LABEL: {{^}}sext_bool_icmp_ne_1: -; GCN: v_cmp_ne_i32_e32 vcc, -; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, -1, vcc -; GCN-NEXT: v_cmp_ne_i32_e32 vcc, 1, [[TMP]]{{$}} -; GCN-NEXT: v_cndmask_b32_e64 [[TMP:v[0-9]+]], 0, 1, -; GCN-NEXT: buffer_store_byte [[TMP]] +; FUNC-LABEL: {{^}}sext_bool_icmp_ne_neg1: +; GCN-NOT: v_cmp +; GCN: v_cmp_eq_i32_e32 vcc, +; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc +; GCN-NEXT: buffer_store_byte [[RESULT]] ; GCN-NEXT: s_endpgm -define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { +define void @sext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %icmp0 = icmp ne i32 %a, %b %ext = sext i1 %icmp0 to i32 - %icmp1 = icmp ne i32 %ext, 1 + %icmp1 = icmp ne i32 %ext, -1 store i1 %icmp1, i1 addrspace(1)* %out ret void } @@ -123,20 +119,28 @@ define void @zext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind ret void } -; FUNC-LABEL: {{^}}sext_bool_icmp_ne_k: -; SI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI-DAG: s_load_dword [[A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI-DAG: s_load_dword [[B:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 -; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]] -; GCN: v_cmp_ne_i32_e32 vcc, 2, [[VB]]{{$}} -; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc -; GCN: buffer_store_byte -; GCN: s_endpgm -define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { +; Reduces to false: +; FUNC-LABEL: {{^}}zext_bool_icmp_eq_neg1: +; GCN: v_mov_b32_e32 [[TMP:v[0-9]+]], 0{{$}} +; GCN: buffer_store_byte [[TMP]] +; GCN-NEXT: s_endpgm +define void @zext_bool_icmp_eq_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { + %icmp0 = icmp eq i32 %a, %b + %ext = zext i1 %icmp0 to i32 + %icmp1 = icmp eq i32 %ext, -1 + store i1 %icmp1, i1 addrspace(1)* %out + ret void +} + +; Reduces to true: +; FUNC-LABEL: {{^}}zext_bool_icmp_ne_neg1: +; GCN: v_mov_b32_e32 [[TMP:v[0-9]+]], 1{{$}} +; GCN: buffer_store_byte [[TMP]] +; GCN-NEXT: s_endpgm +define void @zext_bool_icmp_ne_neg1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %icmp0 = icmp ne i32 %a, %b - %ext = sext i1 %icmp0 to i32 - %icmp1 = icmp ne i32 %ext, 2 + %ext = zext i1 %icmp0 to i32 + %icmp1 = icmp ne i32 %ext, -1 store i1 %icmp1, i1 addrspace(1)* %out ret void } @@ -145,10 +149,10 @@ define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind ; SI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; VI: s_load_dword [[VALUE:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GCN: s_movk_i32 [[K255:s[0-9]+]], 0xff -; GCN: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]] -; GCN: v_mov_b32_e32 [[VK255:v[0-9]+]], [[K255]] +; GCN-DAG: s_and_b32 [[B:s[0-9]+]], [[VALUE]], [[K255]] +; GCN-DAG: v_mov_b32_e32 [[VK255:v[0-9]+]], [[K255]] ; GCN: v_cmp_ne_i32_e32 vcc, [[B]], [[VK255]] -; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc +; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: buffer_store_byte [[RESULT]] ; GCN: s_endpgm define void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind { @@ -162,7 +166,7 @@ define void @cmp_zext_k_i8max(i1 addrspace(1)* %out, i8 %b) nounwind { ; GCN: buffer_load_sbyte [[B:v[0-9]+]] ; GCN: v_cmp_ne_i32_e32 vcc, -1, [[B]]{{$}} ; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc -; GCN-NEXT: buffer_store_byte [[RESULT]] +; GCN: buffer_store_byte [[RESULT]] ; GCN: s_endpgm define void @cmp_sext_k_neg1(i1 addrspace(1)* %out, i8 addrspace(1)* %b.ptr) nounwind { %b = load i8, i8 addrspace(1)* %b.ptr @@ -193,10 +197,10 @@ define void @cmp_sext_k_neg1_i8_sext_arg(i1 addrspace(1)* %out, i8 signext %b) n ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; VI: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c ; GCN: s_movk_i32 [[K:s[0-9]+]], 0xff -; GCN: s_and_b32 [[B:s[0-9]+]], [[VAL]], [[K]] -; GCN: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]] +; GCN-DAG: s_and_b32 [[B:s[0-9]+]], [[VAL]], [[K]] +; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]] ; GCN: v_cmp_ne_i32_e32 vcc, [[B]], [[VK]]{{$}} -; GCN-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc +; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc ; GCN: buffer_store_byte [[RESULT]] ; GCN: s_endpgm define void @cmp_sext_k_neg1_i8_arg(i1 addrspace(1)* %out, i8 %b) nounwind { @@ -240,3 +244,40 @@ define void @zext_bool_icmp_eq_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind store i1 %icmp1, i1 addrspace(1)* %out ret void } + +; FIXME: These cases should really be able fold to true/false in +; DAGCombiner + +; This really folds away to false +; FUNC-LABEL: {{^}}sext_bool_icmp_eq_1: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0{{$}} +; GCN: buffer_store_byte [[K]] +define void @sext_bool_icmp_eq_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { + %icmp0 = icmp eq i32 %a, %b + %ext = sext i1 %icmp0 to i32 + %icmp1 = icmp eq i32 %ext, 1 + store i1 %icmp1, i1 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}sext_bool_icmp_ne_1: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 1{{$}} +; GCN: buffer_store_byte [[K]] +define void @sext_bool_icmp_ne_1(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { + %icmp0 = icmp ne i32 %a, %b + %ext = sext i1 %icmp0 to i32 + %icmp1 = icmp ne i32 %ext, 1 + store i1 %icmp1, i1 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}sext_bool_icmp_ne_k: +; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 1{{$}} +; GCN: buffer_store_byte [[K]] +define void @sext_bool_icmp_ne_k(i1 addrspace(1)* %out, i32 %a, i32 %b) nounwind { + %icmp0 = icmp ne i32 %a, %b + %ext = sext i1 %icmp0 to i32 + %icmp1 = icmp ne i32 %ext, 2 + store i1 %icmp1, i1 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/setcc.ll b/test/CodeGen/AMDGPU/setcc.ll index f33a82df5ffb..c89e712e4cb0 100644 --- a/test/CodeGen/AMDGPU/setcc.ll +++ b/test/CodeGen/AMDGPU/setcc.ll @@ -1,5 +1,5 @@ +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600 --check-prefix=FUNC %s -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck -check-prefix=SI -check-prefix=FUNC %s declare i32 @llvm.r600.read.tidig.x() nounwind readnone @@ -375,3 +375,37 @@ define void @v3i8_eq(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(1)* %ptra, store <3 x i8> %ext, <3 x i8> addrspace(1)* %gep.out ret void } + +; Make sure we don't try to emit i1 setcc ops +; FUNC-LABEL: setcc-i1 +; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 1 +; SI: s_cmp_eq_i32 [[AND]], 0 +define void @setcc-i1(i32 %in) { + %and = and i32 %in, 1 + %cmp = icmp eq i32 %and, 0 + br i1 %cmp, label %endif, label %if +if: + unreachable +endif: + ret void +} + +; FUNC-LABEL: setcc-i1-and-xor +; SI-DAG: v_cmp_le_f32_e64 [[A:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} +; SI-DAG: v_cmp_ge_f32_e64 [[B:s\[[0-9]+:[0-9]+\]]], 1.0, s{{[0-9]+}} +; SI: s_and_b64 s[2:3], [[A]], [[B]] +define void @setcc-i1-and-xor(i32 addrspace(1)* %out, float %cond) #0 { +bb0: + %tmp5 = fcmp oge float %cond, 0.000000e+00 + %tmp7 = fcmp ole float %cond, 1.000000e+00 + %tmp9 = and i1 %tmp5, %tmp7 + %tmp11 = xor i1 %tmp9, 1 + br i1 %tmp11, label %bb2, label %bb1 + +bb1: + store i32 0, i32 addrspace(1)* %out + br label %bb2 + +bb2: + ret void +} diff --git a/test/CodeGen/AMDGPU/setcc64.ll b/test/CodeGen/AMDGPU/setcc64.ll index 231be7aa3da7..15db03cf906e 100644 --- a/test/CodeGen/AMDGPU/setcc64.ll +++ b/test/CodeGen/AMDGPU/setcc64.ll @@ -59,7 +59,7 @@ entry: ; FUNC-LABEL: {{^}}f64_one: ; SI: v_cmp_lg_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_one(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp one double %a, %b @@ -80,7 +80,7 @@ entry: ; FUNC-LABEL: {{^}}f64_ueq: ; SI: v_cmp_nlg_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_ueq(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ueq double %a, %b @@ -92,7 +92,7 @@ entry: ; FUNC-LABEL: {{^}}f64_ugt: ; SI: v_cmp_nle_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_ugt(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ugt double %a, %b @@ -103,7 +103,7 @@ entry: ; FUNC-LABEL: {{^}}f64_uge: ; SI: v_cmp_nlt_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_uge(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp uge double %a, %b @@ -114,7 +114,7 @@ entry: ; FUNC-LABEL: {{^}}f64_ult: ; SI: v_cmp_nge_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_ult(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ult double %a, %b @@ -125,7 +125,7 @@ entry: ; FUNC-LABEL: {{^}}f64_ule: ; SI: v_cmp_ngt_f64_e32 vcc -; SI-NEXT: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc +; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc define void @f64_ule(i32 addrspace(1)* %out, double %a, double %b) { entry: %0 = fcmp ule double %a, %b diff --git a/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll b/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll new file mode 100644 index 000000000000..08bdc3aba555 --- /dev/null +++ b/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll @@ -0,0 +1,22 @@ +; XFAIL: * +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s +; XUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s +; +; EG-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: +; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] +; EG-NOT: BFE +; EG: ADD_INT +; EG: LSHL +; EG: ASHR [[RES]] +; EG: LSHL +; EG: ASHR [[RES]] +; EG: LSHR {{\*?}} [[ADDR]] + +; Works with the align 2 removed +define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind { + %c = add <2 x i32> %a, %b + %x = shl <2 x i32> %c, + %y = ashr <2 x i32> %x, + store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2 + ret void +} diff --git a/test/CodeGen/AMDGPU/sext-in-reg.ll b/test/CodeGen/AMDGPU/sext-in-reg.ll index 23ae3b967971..a6c72a5165d6 100644 --- a/test/CodeGen/AMDGPU/sext-in-reg.ll +++ b/test/CodeGen/AMDGPU/sext-in-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone @@ -95,17 +95,6 @@ define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw ; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} - -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] -; EG: LSHL -; EG: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal -; EG: ASHR [[RES_HI]] -; EG-NOT: BFE_INT -; EG: LSHR -; EG: LSHR -;; TODO Check address computation, using | with variables in {{}} does not work, -;; also the _LO/_HI order might be different define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %c = shl i64 %a, %b %shl = shl i64 %c, 56 @@ -121,16 +110,6 @@ define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] -; EG: LSHL -; EG: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal -; EG: ASHR [[RES_HI]] -; EG-NOT: BFE_INT -; EG: LSHR -; EG: LSHR -;; TODO Check address computation, using | with variables in {{}} does not work, -;; also the _LO/_HI order might be different define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %c = shl i64 %a, %b %shl = shl i64 %c, 48 @@ -145,17 +124,6 @@ define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun ; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} - -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] -; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] -; EG-NOT: BFE_INT - -; EG: ASHR [[RES_HI]] - -; EG: LSHR -; EG: LSHR -;; TODO Check address computation, using | with variables in {{}} does not work, -;; also the _LO/_HI order might be different define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { %c = shl i64 %a, %b %shl = shl i64 %c, 32 @@ -300,7 +268,7 @@ define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out %c = add <2 x i32> %a, %b %x = shl <2 x i32> %c, %y = ashr <2 x i32> %x, - store <2 x i32> %y, <2 x i32> addrspace(1)* %out, align 2 + store <2 x i32> %y, <2 x i32> addrspace(1)* %out ret void } @@ -458,7 +426,8 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8, i8 addrspace(1)* %src, align 1 %tmp2 = sext i8 %tmp5 to i32 - %tmp3 = tail call i32 @llvm.AMDGPU.imax(i32 %tmp2, i32 0) nounwind readnone + %tmp2.5 = icmp sgt i32 %tmp2, 0 + %tmp3 = select i1 %tmp2.5, i32 %tmp2, i32 0 %tmp4 = trunc i32 %tmp3 to i8 %tmp6 = sext i8 %tmp4 to i16 store i16 %tmp6, i16 addrspace(1)* %out, align 2 diff --git a/test/CodeGen/AMDGPU/sgpr-control-flow.ll b/test/CodeGen/AMDGPU/sgpr-control-flow.ll index 38289ced632a..f1b8e8eec85d 100644 --- a/test/CodeGen/AMDGPU/sgpr-control-flow.ll +++ b/test/CodeGen/AMDGPU/sgpr-control-flow.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s ; ; ; Most SALU instructions ignore control flow, so we need to make sure @@ -40,7 +40,7 @@ endif: define void @sgpr_if_else_valu_br(i32 addrspace(1)* %out, float %a, i32 %b, i32 %c, i32 %d, i32 %e) { entry: - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tid_f = uitofp i32 %tid to float %tmp1 = fcmp ueq float %tid_f, 0.0 br i1 %tmp1, label %if, label %else @@ -67,7 +67,7 @@ endif: ; SI: v_cmp_gt_i32_e32 [[CMP_IF:vcc]], 0, [[AVAL]] ; SI: v_cndmask_b32_e64 [[V_CMP:v[0-9]+]], 0, -1, [[CMP_IF]] -; SI: BB2_1: +; SI: BB2_2: ; SI: buffer_load_dword [[AVAL:v[0-9]+]] ; SI: v_cmp_eq_i32_e32 [[CMP_ELSE:vcc]], 0, [[AVAL]] ; SI: v_cndmask_b32_e64 [[V_CMP]], 0, -1, [[CMP_ELSE]] @@ -77,7 +77,7 @@ endif: ; SI: buffer_store_dword [[RESULT]] define void @sgpr_if_else_valu_cmp_phi_br(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) { entry: - %tid = call i32 @llvm.r600.read.tidig.x() #0 + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp1 = icmp eq i32 %tid, 0 br i1 %tmp1, label %if, label %else @@ -100,6 +100,6 @@ endif: ret void } -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/sgpr-copy.ll b/test/CodeGen/AMDGPU/sgpr-copy.ll index b849c4038bc7..da270c533ece 100644 --- a/test/CodeGen/AMDGPU/sgpr-copy.ll +++ b/test/CodeGen/AMDGPU/sgpr-copy.ll @@ -3,189 +3,193 @@ ; This test checks that no VGPR to SGPR copies are created by the register ; allocator. + + +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + + ; CHECK-LABEL: {{^}}phi1: ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] - -define void @phi1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @phi1(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { main_body: - %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 - %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1 - %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0) - %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) - %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32) - %25 = fptosi float %23 to i32 - %26 = icmp ne i32 %25, 0 - br i1 %26, label %ENDIF, label %ELSE + %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 + %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) + %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) + %tmp24 = fptosi float %tmp22 to i32 + %tmp25 = icmp ne i32 %tmp24, 0 + br i1 %tmp25, label %ENDIF, label %ELSE ELSE: ; preds = %main_body - %27 = fsub float -0.000000e+00, %22 + %tmp26 = fsub float -0.000000e+00, %tmp21 br label %ENDIF -ENDIF: ; preds = %main_body, %ELSE - %temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ] - %28 = fadd float %temp.0, %24 - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00) +ENDIF: ; preds = %ELSE, %main_body + %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] + %tmp27 = fadd float %temp.0, %tmp23 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00) ret void } ; Make sure this program doesn't crash ; CHECK-LABEL: {{^}}phi2: -define void @phi2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @phi2(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { main_body: - %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 - %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1 - %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) - %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32) - %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 36) - %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 40) - %26 = call float @llvm.SI.load.const(<16 x i8> %21, i32 48) - %27 = call float @llvm.SI.load.const(<16 x i8> %21, i32 52) - %28 = call float @llvm.SI.load.const(<16 x i8> %21, i32 56) - %29 = call float @llvm.SI.load.const(<16 x i8> %21, i32 64) - %30 = call float @llvm.SI.load.const(<16 x i8> %21, i32 68) - %31 = call float @llvm.SI.load.const(<16 x i8> %21, i32 72) - %32 = call float @llvm.SI.load.const(<16 x i8> %21, i32 76) - %33 = call float @llvm.SI.load.const(<16 x i8> %21, i32 80) - %34 = call float @llvm.SI.load.const(<16 x i8> %21, i32 84) - %35 = call float @llvm.SI.load.const(<16 x i8> %21, i32 88) - %36 = call float @llvm.SI.load.const(<16 x i8> %21, i32 92) - %37 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0 - %38 = load <32 x i8>, <32 x i8> addrspace(2)* %37, !tbaa !1 - %39 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0 - %40 = load <16 x i8>, <16 x i8> addrspace(2)* %39, !tbaa !1 - %41 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5) - %42 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5) - %43 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %3, <2 x i32> %5) - %44 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %3, <2 x i32> %5) - %45 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %3, <2 x i32> %5) - %46 = bitcast float %41 to i32 - %47 = bitcast float %42 to i32 - %48 = insertelement <2 x i32> undef, i32 %46, i32 0 - %49 = insertelement <2 x i32> %48, i32 %47, i32 1 - %50 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %49, <32 x i8> %38, <16 x i8> %40, i32 2) - %51 = extractelement <4 x float> %50, i32 2 - %52 = call float @fabs(float %51) - %53 = fmul float %43, %43 - %54 = fmul float %44, %44 - %55 = fadd float %54, %53 - %56 = fmul float %45, %45 - %57 = fadd float %55, %56 - %58 = call float @llvm.AMDGPU.rsq.f32(float %57) - %59 = fmul float %43, %58 - %60 = fmul float %44, %58 - %61 = fmul float %45, %58 - %62 = fmul float %59, %23 - %63 = fmul float %60, %24 - %64 = fadd float %63, %62 - %65 = fmul float %61, %25 - %66 = fadd float %64, %65 - %67 = fsub float -0.000000e+00, %26 - %68 = fmul float %66, %52 - %69 = fadd float %68, %67 - %70 = fmul float %27, %69 - %71 = fmul float %28, %69 - %72 = call float @fabs(float %70) - %73 = fcmp olt float 0x3EE4F8B580000000, %72 - %74 = sext i1 %73 to i32 - %75 = bitcast i32 %74 to float - %76 = bitcast float %75 to i32 - %77 = icmp ne i32 %76, 0 - br i1 %77, label %IF, label %ENDIF + %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 + %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 32) + %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 36) + %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 40) + %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 48) + %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 52) + %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 56) + %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 64) + %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 68) + %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 72) + %tmp31 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 76) + %tmp32 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 80) + %tmp33 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 84) + %tmp34 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 88) + %tmp35 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 92) + %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 + %tmp37 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp36, !tbaa !0 + %tmp38 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0 + %tmp39 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp38, !tbaa !0 + %tmp40 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5) + %tmp41 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5) + %tmp42 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg3, <2 x i32> %arg5) + %tmp43 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg3, <2 x i32> %arg5) + %tmp44 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg3, <2 x i32> %arg5) + %tmp45 = bitcast float %tmp40 to i32 + %tmp46 = bitcast float %tmp41 to i32 + %tmp47 = insertelement <2 x i32> undef, i32 %tmp45, i32 0 + %tmp48 = insertelement <2 x i32> %tmp47, i32 %tmp46, i32 1 + %tmp39.bc = bitcast <16 x i8> %tmp39 to <4 x i32> + %tmp49 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp48, <8 x i32> %tmp37, <4 x i32> %tmp39.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp50 = extractelement <4 x float> %tmp49, i32 2 + %tmp51 = call float @fabs(float %tmp50) + %tmp52 = fmul float %tmp42, %tmp42 + %tmp53 = fmul float %tmp43, %tmp43 + %tmp54 = fadd float %tmp53, %tmp52 + %tmp55 = fmul float %tmp44, %tmp44 + %tmp56 = fadd float %tmp54, %tmp55 + %tmp57 = call float @llvm.amdgcn.rsq.f32(float %tmp56) + %tmp58 = fmul float %tmp42, %tmp57 + %tmp59 = fmul float %tmp43, %tmp57 + %tmp60 = fmul float %tmp44, %tmp57 + %tmp61 = fmul float %tmp58, %tmp22 + %tmp62 = fmul float %tmp59, %tmp23 + %tmp63 = fadd float %tmp62, %tmp61 + %tmp64 = fmul float %tmp60, %tmp24 + %tmp65 = fadd float %tmp63, %tmp64 + %tmp66 = fsub float -0.000000e+00, %tmp25 + %tmp67 = fmul float %tmp65, %tmp51 + %tmp68 = fadd float %tmp67, %tmp66 + %tmp69 = fmul float %tmp26, %tmp68 + %tmp70 = fmul float %tmp27, %tmp68 + %tmp71 = call float @fabs(float %tmp69) + %tmp72 = fcmp olt float 0x3EE4F8B580000000, %tmp71 + %tmp73 = sext i1 %tmp72 to i32 + %tmp74 = bitcast i32 %tmp73 to float + %tmp75 = bitcast float %tmp74 to i32 + %tmp76 = icmp ne i32 %tmp75, 0 + br i1 %tmp76, label %IF, label %ENDIF IF: ; preds = %main_body - %78 = fsub float -0.000000e+00, %70 - %79 = call float @llvm.AMDIL.exp.(float %78) - %80 = fsub float -0.000000e+00, %79 - %81 = fadd float 1.000000e+00, %80 - %82 = fdiv float 1.000000e+00, %70 - %83 = fmul float %81, %82 - %84 = fmul float %32, %83 + %tmp77 = fsub float -0.000000e+00, %tmp69 + %tmp78 = call float @llvm.exp2.f32(float %tmp77) + %tmp79 = fsub float -0.000000e+00, %tmp78 + %tmp80 = fadd float 1.000000e+00, %tmp79 + %tmp81 = fdiv float 1.000000e+00, %tmp69 + %tmp82 = fmul float %tmp80, %tmp81 + %tmp83 = fmul float %tmp31, %tmp82 br label %ENDIF -ENDIF: ; preds = %main_body, %IF - %temp4.0 = phi float [ %84, %IF ], [ %32, %main_body ] - %85 = call float @fabs(float %71) - %86 = fcmp olt float 0x3EE4F8B580000000, %85 - %87 = sext i1 %86 to i32 - %88 = bitcast i32 %87 to float - %89 = bitcast float %88 to i32 - %90 = icmp ne i32 %89, 0 - br i1 %90, label %IF25, label %ENDIF24 +ENDIF: ; preds = %IF, %main_body + %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ] + %tmp84 = call float @fabs(float %tmp70) + %tmp85 = fcmp olt float 0x3EE4F8B580000000, %tmp84 + %tmp86 = sext i1 %tmp85 to i32 + %tmp87 = bitcast i32 %tmp86 to float + %tmp88 = bitcast float %tmp87 to i32 + %tmp89 = icmp ne i32 %tmp88, 0 + br i1 %tmp89, label %IF25, label %ENDIF24 IF25: ; preds = %ENDIF - %91 = fsub float -0.000000e+00, %71 - %92 = call float @llvm.AMDIL.exp.(float %91) - %93 = fsub float -0.000000e+00, %92 - %94 = fadd float 1.000000e+00, %93 - %95 = fdiv float 1.000000e+00, %71 - %96 = fmul float %94, %95 - %97 = fmul float %36, %96 + %tmp90 = fsub float -0.000000e+00, %tmp70 + %tmp91 = call float @llvm.exp2.f32(float %tmp90) + %tmp92 = fsub float -0.000000e+00, %tmp91 + %tmp93 = fadd float 1.000000e+00, %tmp92 + %tmp94 = fdiv float 1.000000e+00, %tmp70 + %tmp95 = fmul float %tmp93, %tmp94 + %tmp96 = fmul float %tmp35, %tmp95 br label %ENDIF24 -ENDIF24: ; preds = %ENDIF, %IF25 - %temp8.0 = phi float [ %97, %IF25 ], [ %36, %ENDIF ] - %98 = fmul float %29, %temp4.0 - %99 = fmul float %30, %temp4.0 - %100 = fmul float %31, %temp4.0 - %101 = fmul float %33, %temp8.0 - %102 = fadd float %101, %98 - %103 = fmul float %34, %temp8.0 - %104 = fadd float %103, %99 - %105 = fmul float %35, %temp8.0 - %106 = fadd float %105, %100 - %107 = call float @llvm.pow.f32(float %52, float %22) - %108 = fsub float -0.000000e+00, %102 - %109 = fmul float %108, %107 - %110 = fsub float -0.000000e+00, %104 - %111 = fmul float %110, %107 - %112 = fsub float -0.000000e+00, %106 - %113 = fmul float %112, %107 - %114 = call i32 @llvm.SI.packf16(float %109, float %111) - %115 = bitcast i32 %114 to float - %116 = call i32 @llvm.SI.packf16(float %113, float 1.000000e+00) - %117 = bitcast i32 %116 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %115, float %117, float %115, float %117) +ENDIF24: ; preds = %IF25, %ENDIF + %temp8.0 = phi float [ %tmp96, %IF25 ], [ %tmp35, %ENDIF ] + %tmp97 = fmul float %tmp28, %temp4.0 + %tmp98 = fmul float %tmp29, %temp4.0 + %tmp99 = fmul float %tmp30, %temp4.0 + %tmp100 = fmul float %tmp32, %temp8.0 + %tmp101 = fadd float %tmp100, %tmp97 + %tmp102 = fmul float %tmp33, %temp8.0 + %tmp103 = fadd float %tmp102, %tmp98 + %tmp104 = fmul float %tmp34, %temp8.0 + %tmp105 = fadd float %tmp104, %tmp99 + %tmp106 = call float @llvm.pow.f32(float %tmp51, float %tmp21) + %tmp107 = fsub float -0.000000e+00, %tmp101 + %tmp108 = fmul float %tmp107, %tmp106 + %tmp109 = fsub float -0.000000e+00, %tmp103 + %tmp110 = fmul float %tmp109, %tmp106 + %tmp111 = fsub float -0.000000e+00, %tmp105 + %tmp112 = fmul float %tmp111, %tmp106 + %tmp113 = call i32 @llvm.SI.packf16(float %tmp108, float %tmp110) + %tmp114 = bitcast i32 %tmp113 to float + %tmp115 = call i32 @llvm.SI.packf16(float %tmp112, float 1.000000e+00) + %tmp116 = bitcast i32 %tmp115 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp114, float %tmp116, float %tmp114, float %tmp116) ret void } ; We just want ot make sure the program doesn't crash ; CHECK-LABEL: {{^}}loop: - -define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @loop(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { main_body: - %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 - %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1 - %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0) - %23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4) - %24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8) - %25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12) - %26 = fptosi float %25 to i32 - %27 = bitcast i32 %26 to float - %28 = bitcast float %27 to i32 + %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 + %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 0) + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 4) + %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 8) + %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 12) + %tmp25 = fptosi float %tmp24 to i32 + %tmp26 = bitcast i32 %tmp25 to float + %tmp27 = bitcast float %tmp26 to i32 br label %LOOP LOOP: ; preds = %ENDIF, %main_body - %temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ] - %temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ] - %temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ] - %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ] - %29 = bitcast float %temp8.0 to i32 - %30 = icmp sge i32 %29, %28 - %31 = sext i1 %30 to i32 - %32 = bitcast i32 %31 to float - %33 = bitcast float %32 to i32 - %34 = icmp ne i32 %33, 0 - br i1 %34, label %IF, label %ENDIF + %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ] + %temp5.0 = phi float [ %tmp22, %main_body ], [ %temp6.0, %ENDIF ] + %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ] + %temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %tmp36, %ENDIF ] + %tmp28 = bitcast float %temp8.0 to i32 + %tmp29 = icmp sge i32 %tmp28, %tmp27 + %tmp30 = sext i1 %tmp29 to i32 + %tmp31 = bitcast i32 %tmp30 to float + %tmp32 = bitcast float %tmp31 to i32 + %tmp33 = icmp ne i32 %tmp32, 0 + br i1 %tmp33, label %IF, label %ENDIF IF: ; preds = %LOOP call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00) ret void ENDIF: ; preds = %LOOP - %35 = bitcast float %temp8.0 to i32 - %36 = add i32 %35, 1 - %37 = bitcast i32 %36 to float + %tmp34 = bitcast float %temp8.0 to i32 + %tmp35 = add i32 %tmp34, 1 + %tmp36 = bitcast i32 %tmp35 to float br label %LOOP } @@ -197,29 +201,19 @@ declare float @fabs(float) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } -attributes #2 = { readonly } -attributes #3 = { readnone } -attributes #4 = { nounwind readonly } - -!0 = !{!"const", null} -!1 = !{!0, !0, i64 0, i32 1} - ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <8 x i32>, <16 x i8>, i32) #1 ; Function Attrs: readnone -declare float @llvm.AMDGPU.rsq.f32(float) #3 +declare float @llvm.amdgcn.rsq.f32(float) #1 -; Function Attrs: readnone -declare float @llvm.AMDIL.exp.(float) #3 +declare float @llvm.exp2.f32(float) #1 -; Function Attrs: nounwind readonly -declare float @llvm.pow.f32(float, float) #4 +; Function Attrs: nounwind readnone +declare float @llvm.pow.f32(float, float) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 @@ -233,114 +227,109 @@ declare i32 @llvm.SI.packf16(float, float) #1 ; CHECK: image_sample ; CHECK: exp ; CHECK: s_endpgm -define void @sample_v3([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { - +define amdgpu_ps void @sample_v3([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { entry: - %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 - %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !2 - %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 16) - %24 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 - %25 = load <32 x i8>, <32 x i8> addrspace(2)* %24, !tbaa !2 - %26 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 - %27 = load <16 x i8>, <16 x i8> addrspace(2)* %26, !tbaa !2 - %28 = fcmp oeq float %23, 0.0 - br i1 %28, label %if, label %else - -if: - %val.if = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> , <32 x i8> %25, <16 x i8> %27, i32 2) + %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 + %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 16) + %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 + %tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0 + %tmp25 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0 + %tmp26 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp25, !tbaa !0 + %tmp27 = fcmp oeq float %tmp22, 0.000000e+00 + %tmp26.bc = bitcast <16 x i8> %tmp26 to <4 x i32> + br i1 %tmp27, label %if, label %else + +if: ; preds = %entry + %val.if = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> zeroinitializer, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %val.if.0 = extractelement <4 x float> %val.if, i32 0 %val.if.1 = extractelement <4 x float> %val.if, i32 1 %val.if.2 = extractelement <4 x float> %val.if, i32 2 br label %endif -else: - %val.else = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> , <32 x i8> %25, <16 x i8> %27, i32 2) +else: ; preds = %entry + %val.else = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %val.else.0 = extractelement <4 x float> %val.else, i32 0 %val.else.1 = extractelement <4 x float> %val.else, i32 1 %val.else.2 = extractelement <4 x float> %val.else, i32 2 br label %endif -endif: - %val.0 = phi float [%val.if.0, %if], [%val.else.0, %else] - %val.1 = phi float [%val.if.1, %if], [%val.else.1, %else] - %val.2 = phi float [%val.if.2, %if], [%val.else.2, %else] - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.0) +endif: ; preds = %else, %if + %val.0 = phi float [ %val.if.0, %if ], [ %val.else.0, %else ] + %val.1 = phi float [ %val.if.1, %if ], [ %val.else.1, %else ] + %val.2 = phi float [ %val.if.2, %if ], [ %val.else.2, %else ] + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %val.0, float %val.1, float %val.2, float 0.000000e+00) ret void } -!2 = !{!"const", null, i32 1} - ; CHECK-LABEL: {{^}}copy1: ; CHECK: buffer_load_dword ; CHECK: v_add ; CHECK: s_endpgm define void @copy1(float addrspace(1)* %out, float addrspace(1)* %in0) { entry: - %0 = load float, float addrspace(1)* %in0 - %1 = fcmp oeq float %0, 0.0 - br i1 %1, label %if0, label %endif + %tmp = load float, float addrspace(1)* %in0 + %tmp1 = fcmp oeq float %tmp, 0.000000e+00 + br i1 %tmp1, label %if0, label %endif -if0: - %2 = bitcast float %0 to i32 - %3 = fcmp olt float %0, 0.0 - br i1 %3, label %if1, label %endif +if0: ; preds = %entry + %tmp2 = bitcast float %tmp to i32 + %tmp3 = fcmp olt float %tmp, 0.000000e+00 + br i1 %tmp3, label %if1, label %endif -if1: - %4 = add i32 %2, 1 +if1: ; preds = %if0 + %tmp4 = add i32 %tmp2, 1 br label %endif -endif: - %5 = phi i32 [ 0, %entry ], [ %2, %if0 ], [ %4, %if1 ] - %6 = bitcast i32 %5 to float - store float %6, float addrspace(1)* %out +endif: ; preds = %if1, %if0, %entry + %tmp5 = phi i32 [ 0, %entry ], [ %tmp2, %if0 ], [ %tmp4, %if1 ] + %tmp6 = bitcast i32 %tmp5 to float + store float %tmp6, float addrspace(1)* %out ret void } ; This test is just checking that we don't crash / assertion fail. ; CHECK-LABEL: {{^}}copy2: ; CHECK: s_endpgm - -define void @copy2([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @copy2([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { entry: br label %LOOP68 -LOOP68: +LOOP68: ; preds = %ENDIF69, %entry %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] %g = icmp eq i32 0, %t %l = bitcast float %temp4.7 to i32 br i1 %g, label %IF70, label %ENDIF69 -IF70: +IF70: ; preds = %LOOP68 %q = icmp ne i32 %l, 13 %temp.8 = select i1 %q, float 1.000000e+00, float 0.000000e+00 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp.8, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) ret void -ENDIF69: +ENDIF69: ; preds = %LOOP68 %u = add i32 %l, %t %v = bitcast i32 %u to float %x = add i32 %t, -1 br label %LOOP68 } -attributes #0 = { "ShaderType"="0" } - ; This test checks that image_sample resource descriptors aren't loaded into ; vgprs. The verifier will fail if this happens. ; CHECK-LABEL:{{^}}sample_rsrc: ; CHECK: image_sample ; CHECK: image_sample ; CHECK: s_endpgm -define void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { +define amdgpu_ps void @sample_rsrc([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { bb: %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i32 0, i32 0 - %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp22 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !2 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp22, i32 16) %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0 - %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !0 + %tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !2 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0 - %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !0 + %tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !2 %tmp29 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg7) %tmp30 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg7) %tmp31 = bitcast float %tmp23 to i32 @@ -352,9 +341,8 @@ bb38: ; preds = %bb %tmp53 = bitcast float %tmp30 to i32 %tmp54 = insertelement <2 x i32> undef, i32 %tmp52, i32 0 %tmp55 = insertelement <2 x i32> %tmp54, i32 %tmp53, i32 1 - %tmp56 = bitcast <8 x i32> %tmp26 to <32 x i8> - %tmp57 = bitcast <4 x i32> %tmp28 to <16 x i8> - %tmp58 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %tmp55, <32 x i8> %tmp56, <16 x i8> %tmp57, i32 2) + %tmp56 = bitcast <8 x i32> %tmp26 to <8 x i32> + %tmp58 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp55, <8 x i32> %tmp56, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) br label %bb71 bb80: ; preds = %bb @@ -363,9 +351,8 @@ bb80: ; preds = %bb %tmp82.2 = add i32 %tmp82, 1 %tmp83 = insertelement <2 x i32> undef, i32 %tmp81, i32 0 %tmp84 = insertelement <2 x i32> %tmp83, i32 %tmp82.2, i32 1 - %tmp85 = bitcast <8 x i32> %tmp26 to <32 x i8> - %tmp86 = bitcast <4 x i32> %tmp28 to <16 x i8> - %tmp87 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %tmp84, <32 x i8> %tmp85, <16 x i8> %tmp86, i32 2) + %tmp85 = bitcast <8 x i32> %tmp26 to <8 x i32> + %tmp87 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp84, <8 x i32> %tmp85, <4 x i32> %tmp28, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) br label %bb71 bb71: ; preds = %bb80, %bb38 @@ -375,5 +362,42 @@ bb71: ; preds = %bb80, %bb38 ret void } -attributes #0 = { "ShaderType"="0" "unsafe-fp-math"="true" } +; Check the the resource descriptor is stored in an sgpr. +; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: +; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 +define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid + %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 + %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp10 = extractelement <4 x float> %tmp9, i32 0 + %tmp12 = call i32 @llvm.SI.packf16(float undef, float %tmp10) + %tmp13 = bitcast i32 %tmp12 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) + ret void +} + +; Check the the sampler is stored in an sgpr. +; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: +; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 +define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 { + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid + %tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0 + %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> undef, <4 x i32> %tmp8, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp10 = extractelement <4 x float> %tmp9, i32 0 + %tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef) + %tmp13 = bitcast i32 %tmp12 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp13, float undef, float undef, float undef) + ret void +} + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 + +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } +attributes #2 = { nounwind readonly } + +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} +!2 = !{!1, !1, i64 0} diff --git a/test/CodeGen/AMDGPU/shared-op-cycle.ll b/test/CodeGen/AMDGPU/shared-op-cycle.ll index f52a9baf4d18..f9a72b47cc99 100644 --- a/test/CodeGen/AMDGPU/shared-op-cycle.ll +++ b/test/CodeGen/AMDGPU/shared-op-cycle.ll @@ -4,7 +4,7 @@ ; CHECK: MULADD_IEEE * ; CHECK-NOT: MULADD_IEEE * -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) { %w0 = extractelement <4 x float> %reg0, i32 3 %w1 = extractelement <4 x float> %reg1, i32 3 %w2 = extractelement <4 x float> %reg2, i32 3 @@ -17,16 +17,15 @@ define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> %v0 = insertelement <4 x float> undef, float %r0, i32 0 %v1 = insertelement <4 x float> %v0, float %r1, i32 1 %v2 = insertelement <4 x float> %v1, float %r2, i32 2 - %res = call float @llvm.AMDGPU.dp4(<4 x float> %v2, <4 x float> %v2) + %res = call float @llvm.r600.dot4(<4 x float> %v2, <4 x float> %v2) %vecres = insertelement <4 x float> undef, float %res, i32 0 - call void @llvm.R600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %vecres, i32 0, i32 2) ret void } ; Function Attrs: readnone -declare float @llvm.AMDGPU.dp4(<4 x float>, <4 x float>) #1 +declare float @llvm.r600.dot4(<4 x float>, <4 x float>) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } -attributes #1 = { readnone } \ No newline at end of file +attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll b/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll new file mode 100644 index 000000000000..a6555a197388 --- /dev/null +++ b/test/CodeGen/AMDGPU/shift-and-i128-ubfe.ll @@ -0,0 +1,118 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Extract the high bit of the 1st quarter +; GCN-LABEL: {{^}}v_uextract_bit_31_i128: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} + +; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] + +; GCN: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: s_endpgm +define void @v_uextract_bit_31_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x + %ld.64 = load i128, i128 addrspace(1)* %in.gep + %srl = lshr i128 %ld.64, 31 + %bit = and i128 %srl, 1 + store i128 %bit, i128 addrspace(1)* %out.gep + ret void +} + +; Extract the high bit of the 2nd quarter +; GCN-LABEL: {{^}}v_uextract_bit_63_i128: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} + +; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} +; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] + +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: s_endpgm +define void @v_uextract_bit_63_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x + %ld.64 = load i128, i128 addrspace(1)* %in.gep + %srl = lshr i128 %ld.64, 63 + %bit = and i128 %srl, 1 + store i128 %bit, i128 addrspace(1)* %out.gep + ret void +} + +; Extract the high bit of the 3rd quarter +; GCN-LABEL: {{^}}v_uextract_bit_95_i128: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} + +; GCN-DAG: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] + +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: s_endpgm +define void @v_uextract_bit_95_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x + %ld.64 = load i128, i128 addrspace(1)* %in.gep + %srl = lshr i128 %ld.64, 95 + %bit = and i128 %srl, 1 + store i128 %bit, i128 addrspace(1)* %out.gep + ret void +} + +; Extract the high bit of the 4th quarter +; GCN-LABEL: {{^}}v_uextract_bit_127_i128: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} + +; GCN: v_mov_b32_e32 v[[ZERO0:[0-9]+]], 0{{$}} +; GCN: v_mov_b32_e32 v[[ZERO1:[0-9]+]], v[[ZERO0]]{{$}} +; GCN: v_mov_b32_e32 v[[ZERO2:[0-9]+]], v[[ZERO0]]{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] + +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[SHIFT]]:[[ZERO2]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: s_endpgm +define void @v_uextract_bit_127_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x + %ld.64 = load i128, i128 addrspace(1)* %in.gep + %srl = lshr i128 %ld.64, 127 + %bit = and i128 %srl, 1 + store i128 %bit, i128 addrspace(1)* %out.gep + ret void +} + +; Spans more than 2 dword boundaries +; GCN-LABEL: {{^}}v_uextract_bit_34_100_i128: +; GCN: buffer_load_dwordx4 v{{\[}}[[VAL0:[0-9]+]]:[[VAL3:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} + +; GCN-DAG: v_lshl_b64 v{{\[}}[[SHLLO:[0-9]+]]:[[SHLHI:[0-9]+]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, 30 +; GCN-DAG: v_lshrrev_b32_e32 v[[ELT1PART:[0-9]+]], 2, v{{[[0-9]+}} +; GCN-DAG: v_bfe_u32 v[[ELT2PART:[0-9]+]], v[[VAL3]], 2, 2{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN-DAG: v_or_b32_e32 v[[OR0:[0-9]+]], v[[SHLLO]], v[[ELT1PART]] +; GCN-DAG: v_or_b32_e32 v[[OR1:[0-9]+]], 0, v[[SHLHI]]{{$}} + +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[OR0]]:[[ZERO]]{{\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: s_endpgm +define void @v_uextract_bit_34_100_i128(i128 addrspace(1)* %out, i128 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i128, i128 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i128, i128 addrspace(1)* %out, i32 %id.x + %ld.64 = load i128, i128 addrspace(1)* %in.gep + %srl = lshr i128 %ld.64, 34 + %bit = and i128 %srl, 73786976294838206463 + store i128 %bit, i128 addrspace(1)* %out.gep + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll b/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll new file mode 100644 index 000000000000..c5dbfd9589a6 --- /dev/null +++ b/test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll @@ -0,0 +1,386 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Make sure 64-bit BFE pattern does a 32-bit BFE on the relevant half. + +; Extract the high bit of the low half +; GCN-LABEL: {{^}}v_uextract_bit_31_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 31 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; Extract the high bit of the high half +; GCN-LABEL: {{^}}v_uextract_bit_63_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 63 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_1_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 1 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_20_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 1 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_20_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 20 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_32_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 1, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 32 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_33_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 1{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 33 + %bit = and i64 %srl, 1 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_20_21_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 20, 2 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_20_21_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 20 + %bit = and i64 %srl, 3 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_1_30_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_1_30_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 1 + %bit = and i64 %srl, 1073741823 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_1_31_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 1, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_1_31_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 1 + %bit = and i64 %srl, 2147483647 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; Spans the dword boundary, so requires full shift +; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 31 +; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]]{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_31_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 31 + %bit = and i64 %srl, 3 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_32_33_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 2 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_32_33_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 33 + %bit = and i64 %srl, 3 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_30_60_i64: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 30 +; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 0x3fffffff, v[[SHRLO]]{{$}} +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_30_60_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 30 + %bit = and i64 %srl, 1073741823 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_33_63_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 30 +; GCN-DAG: v_mov_b32_e32 v[[BFE:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHIFT]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_33_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 33 + %bit = and i64 %srl, 1073741823 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_31_63_i64: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 31 +; GCN-NEXT: v_mov_b32_e32 v[[SHRHI]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} +define void @v_uextract_bit_31_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 31 + %and = and i64 %srl, 4294967295 + store i64 %and, i64 addrspace(1)* %out + ret void +} + +; trunc applied before and mask +; GCN-LABEL: {{^}}v_uextract_bit_31_i64_trunc_i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHIFT:[0-9]+]], 31, [[VAL]] +; GCN: buffer_store_dword v[[SHIFT]] +define void @v_uextract_bit_31_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 31 + %trunc = trunc i64 %srl to i32 + %bit = and i32 %trunc, 1 + store i32 %bit, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_3_i64_trunc_i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} +; GCN: v_bfe_u32 [[BFE:v[0-9]+]], [[VAL]], 3, 1{{$}} +; GCN: buffer_store_dword [[BFE]] +define void @v_uextract_bit_3_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 3 + %trunc = trunc i64 %srl to i32 + %bit = and i32 %trunc, 1 + store i32 %bit, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_33_i64_trunc_i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN: v_bfe_u32 [[BFE:v[0-9]+]], [[VAL]], 1, 1{{$}} +; GCN: buffer_store_dword [[BFE]] +define void @v_uextract_bit_33_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 33 + %trunc = trunc i64 %srl to i32 + %bit = and i32 %trunc, 1 + store i32 %bit, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_31_32_i64_trunc_i32: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 31 +; GCN-NEXT: v_and_b32_e32 v[[SHRLO]], 3, v[[SHRLO]] +; GCN-NOT: v[[SHRLO]] +; GCN: buffer_store_dword v[[SHRLO]] +define void @v_uextract_bit_31_32_i64_trunc_i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 31 + %trunc = trunc i64 %srl to i32 + %bit = and i32 %trunc, 3 + store i32 %bit, i32 addrspace(1)* %out.gep + ret void +} + +; GCN-LABEL: {{^}}and_not_mask_i64: +; GCN: buffer_load_dwordx2 v{{\[}}[[VALLO:[0-9]+]]:[[VALHI:[0-9]+]]{{\]}} +; GCN: v_mov_b32_e32 v[[SHRHI]], 0{{$}} +; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 20, v[[VALLO]] +; GCN-DAG: v_and_b32_e32 v[[SHRLO]], 4, [[SHR]] +; GCN-NOT: v[[SHRLO]] +; GCN-NOT: v[[SHRHI]] +; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} +define void @and_not_mask_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 20 + %bit = and i64 %srl, 4 + store i64 %bit, i64 addrspace(1)* %out.gep + ret void +} + +; The instruction count is the same with/without hasOneUse, but +; keeping the 32-bit and has a smaller encoding size than the bfe. + +; GCN-LABEL: {{^}}v_uextract_bit_27_29_multi_use_shift_i64: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN-DAG: v_lshr_b64 v{{\[}}[[SHRLO:[0-9]+]]:[[SHRHI:[0-9]+]]{{\]}}, [[VAL]], 27 +; GCN-DAG: v_and_b32_e32 v[[AND:[0-9]+]], 3, v[[SHRLO]] +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[SHRLO]]:[[SHRHI]]{{\]}} +; GCN: buffer_store_dwordx2 v{{\[}}[[AND]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_27_29_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 27 + %bit = and i64 %srl, 3 + store volatile i64 %srl, i64 addrspace(1)* %out + store volatile i64 %bit, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_34_37_multi_use_shift_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 2, [[VAL]] +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 2, 3 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[SHR]]:[[ZERO]]{{\]}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @v_uextract_bit_34_37_multi_use_shift_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out.gep = getelementptr i64, i64 addrspace(1)* %out, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 34 + %bit = and i64 %srl, 7 + store volatile i64 %srl, i64 addrspace(1)* %out + store volatile i64 %bit, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_uextract_bit_33_36_use_upper_half_shift_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} +; GCN-DAG: v_bfe_u32 v[[BFE:[0-9]+]], [[VAL]], 1, 3 +; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +; GCN: buffer_store_dword v[[ZERO]] +define void @v_uextract_bit_33_36_use_upper_half_shift_i64(i64 addrspace(1)* %out0, i32 addrspace(1)* %out1, i64 addrspace(1)* %in) #1 { + %id.x = tail call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %id.x + %out0.gep = getelementptr i64, i64 addrspace(1)* %out0, i32 %id.x + %out1.gep = getelementptr i32, i32 addrspace(1)* %out1, i32 %id.x + %ld.64 = load i64, i64 addrspace(1)* %in.gep + %srl = lshr i64 %ld.64, 33 + %bit = and i64 %srl, 7 + store volatile i64 %bit, i64 addrspace(1)* %out0.gep + + %srl.srl32 = lshr i64 %srl, 32 + %srl.hi = trunc i64 %srl.srl32 to i32 + store volatile i32 %srl.hi, i32 addrspace(1)* %out1.gep + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/test/CodeGen/AMDGPU/shift-i64-opts.ll b/test/CodeGen/AMDGPU/shift-i64-opts.ll new file mode 100644 index 000000000000..28a7b924904d --- /dev/null +++ b/test/CodeGen/AMDGPU/shift-i64-opts.ll @@ -0,0 +1,245 @@ +; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=FAST64 -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=SLOW64 -check-prefix=GCN %s + + +; lshr (i64 x), c: c > 32 => reg_sequence lshr (i32 hi_32(x)), (c - 32), 0 +; GCN-LABEL: {{^}}lshr_i64_35: +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 3, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @lshr_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = lshr i64 %val, 35 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lshr_i64_63: +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 31, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @lshr_i64_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = lshr i64 %val, 63 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lshr_i64_33: +; GCN-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_lshrrev_b32_e32 v[[LO:[0-9]+]], 1, [[VAL]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @lshr_i64_33(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = lshr i64 %val, 33 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}lshr_i64_32: +; GCN-DAG: buffer_load_dword v[[LO:[0-9]+]] +; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @lshr_i64_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = lshr i64 %val, 32 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; Make sure the and of the constant doesn't prevent bfe from forming +; after 64-bit shift is split. + +; GCN-LABEL: {{^}}lshr_and_i64_35: +; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; GCN: v_bfe_u32 v[[BFE:[0-9]+]], v[[HI]], 8, 23 +; GCN: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[BFE]]:[[ZERO]]{{\]}} +define void @lshr_and_i64_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %and = and i64 %val, 9223372036854775807 ; 0x7fffffffffffffff + %shl = lshr i64 %and, 40 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; lshl (i64 x), c: c > 32 => reg_sequence lshl 0, (i32 lo_32(x)), (c - 32) + +; GCN-LABEL: {{^}}shl_i64_const_35: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 3, [[VAL]] +; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @shl_i64_const_35(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 35 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}shl_i64_const_32: +; GCN-DAG: buffer_load_dword v[[HI:[0-9]+]] +; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @shl_i64_const_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 32 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}shl_i64_const_63: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 v[[HI:[0-9]+]], 31, [[VAL]] +; GCN: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @shl_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 63 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; ashr (i64 x), 63 => (ashr lo(x), 31), lo(x) + +; GCN-LABEL: {{^}}ashr_i64_const_32: +define void @ashr_i64_const_32(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = ashr i64 %val, 32 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}ashr_i64_const_63: +define void @ashr_i64_const_63(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = ashr i64 %val, 63 + store i64 %shl, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_31_i32_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 31, [[VAL]] +; GCN: buffer_store_dword [[SHL]] +define void @trunc_shl_31_i32_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 31 + %trunc = trunc i64 %shl to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_15_i16_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]] +; GCN: buffer_store_short [[SHL]] +define void @trunc_shl_15_i16_i64(i16 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 15 + %trunc = trunc i64 %shl to i16 + store i16 %trunc, i16 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_15_i16_i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 15, [[VAL]] +; GCN: buffer_store_short [[SHL]] +define void @trunc_shl_15_i16_i32(i16 addrspace(1)* %out, i32 addrspace(1)* %in) { + %val = load i32, i32 addrspace(1)* %in + %shl = shl i32 %val, 15 + %trunc = trunc i32 %shl to i16 + store i16 %trunc, i16 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_7_i8_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 7, [[VAL]] +; GCN: buffer_store_byte [[SHL]] +define void @trunc_shl_7_i8_i64(i8 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 7 + %trunc = trunc i64 %shl to i8 + store i8 %trunc, i8 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_1_i2_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]] +; GCN: v_and_b32_e32 [[AND:v[0-9]+]], 2, [[SHL]] +; GCN: buffer_store_byte [[AND]] +define void @trunc_shl_1_i2_i64(i2 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 1 + %trunc = trunc i64 %shl to i2 + store i2 %trunc, i2 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_1_i32_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 1, [[VAL]] +; GCN: buffer_store_dword [[SHL]] +define void @trunc_shl_1_i32_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 1 + %trunc = trunc i64 %shl to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_16_i32_i64: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[VAL]] +; GCN: buffer_store_dword [[SHL]] +define void @trunc_shl_16_i32_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 16 + %trunc = trunc i64 %shl to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_33_i32_i64: +; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0{{$}} +; GCN: buffer_store_dword [[ZERO]] +define void @trunc_shl_33_i32_i64(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 33 + %trunc = trunc i64 %shl to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_16_v2i32_v2i64: +; GCN: buffer_load_dwordx4 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; GCN-DAG: v_lshlrev_b32_e32 v[[RESHI:[0-9]+]], 16, v{{[0-9]+}} +; GCN-DAG: v_lshlrev_b32_e32 v[[RESLO:[0-9]+]], 16, v[[LO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} +define void @trunc_shl_16_v2i32_v2i64(<2 x i32> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { + %val = load <2 x i64>, <2 x i64> addrspace(1)* %in + %shl = shl <2 x i64> %val, + %trunc = trunc <2 x i64> %shl to <2 x i32> + store <2 x i32> %trunc, <2 x i32> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}trunc_shl_31_i32_i64_multi_use: +; GCN: buffer_load_dwordx2 [[VAL:v\[[0-9]+:[0-9]+\]]] +; GCN: v_lshl_b64 v{{\[}}[[RESLO:[0-9]+]]:[[RESHI:[0-9]+]]{{\]}}, [[VAL]], 31 +; GCN: buffer_store_dword v[[RESLO]] +; GCN: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]{{\]}} +define void @trunc_shl_31_i32_i64_multi_use(i32 addrspace(1)* %out, i64 addrspace(1)* %in) { + %val = load i64, i64 addrspace(1)* %in + %shl = shl i64 %val, 31 + %trunc = trunc i64 %shl to i32 + store volatile i32 %trunc, i32 addrspace(1)* %out + store volatile i64 %shl, i64 addrspace(1)* %in + ret void +} diff --git a/test/CodeGen/AMDGPU/shl.ll b/test/CodeGen/AMDGPU/shl.ll index 55db80731c90..5a2b03bff990 100644 --- a/test/CodeGen/AMDGPU/shl.ll +++ b/test/CodeGen/AMDGPU/shl.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=SI %s ; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s declare i32 @llvm.r600.read.tidig.x() #0 @@ -208,4 +208,173 @@ define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { ret void } +; FUNC-LABEL: {{^}}s_shl_constant_i64 +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} +define void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) { + %shl = shl i64 281474976710655, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_shl_constant_i64: +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207 +; SI-DAG: s_movk_i32 s[[KHI:[0-9]+]], 0x11e{{$}} +; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] +; SI: buffer_store_dwordx2 +define void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { + %a = load i64, i64 addrspace(1)* %aptr, align 8 + %shl = shl i64 1231231234567, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_shl_i64_32_bit_constant: +; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]] +; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}} +; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}} +; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]] +define void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { + %a = load i64, i64 addrspace(1)* %aptr, align 8 + %shl = shl i64 1234567, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_shl_inline_imm_64_i64: +; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}} +define void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) { + %a = load i64, i64 addrspace(1)* %aptr, align 8 + %shl = shl i64 64, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_64_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}} +define void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 64, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_1_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}} +define void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 1, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_1.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}} +define void @s_shl_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 4607182418800017408, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_1.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}} +define void @s_shl_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 13830554455654793216, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_0.5_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}} +define void @s_shl_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 4602678819172646912, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_0.5_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}} +define void @s_shl_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 13826050856027422720, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_2.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}} +define void @s_shl_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 4611686018427387904, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_2.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}} +define void @s_shl_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 13835058055282163712, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_4.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}} +define void @s_shl_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 4616189618054758400, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_4.0_i64: +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -4.0, s{{[0-9]+}} +define void @s_shl_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 13839561654909534208, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + + +; Test with the 64-bit integer bitpattern for a 32-bit float in the +; low 32-bits, which is not a valid 64-bit inline immmediate. + +; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_4.0_i64: +; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0 +; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}} +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} +define void @s_shl_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 1082130432, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FIXME: Copy of -1 register +; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_neg_4.0_i64: +; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0 +; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}} +; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]] +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}, s{{[0-9]+}} +define void @s_shl_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 -1065353216, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; Shift into upper 32-bits +; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_4.0_i64: +; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0 +; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} +define void @s_shl_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 4647714815446351872, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + +; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_neg_4.0_i64: +; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0 +; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}} +; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}} +define void @s_shl_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) { + %shl = shl i64 13871086852301127680, %a + store i64 %shl, i64 addrspace(1)* %out, align 8 + ret void +} + attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/shl_add_constant.ll b/test/CodeGen/AMDGPU/shl_add_constant.ll index dfb2bf3383fc..13254d0bcf74 100644 --- a/test/CodeGen/AMDGPU/shl_add_constant.ll +++ b/test/CodeGen/AMDGPU/shl_add_constant.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Test with inline immediate @@ -10,7 +10,7 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x %val = load i32, i32 addrspace(1)* %ptr, align 4 %add = add i32 %val, 9 @@ -26,7 +26,7 @@ define void @shl_2_add_9_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { ; SI-DAG: buffer_store_dword [[SHLREG]] ; SI: s_endpgm define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %in) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x %val = load i32, i32 addrspace(1)* %ptr, align 4 %add = add i32 %val, 9 @@ -44,7 +44,7 @@ define void @shl_2_add_9_i32_2_add_uses(i32 addrspace(1)* %out0, i32 addrspace(1 ; SI: buffer_store_dword [[RESULT]] ; SI: s_endpgm define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %ptr = getelementptr i32, i32 addrspace(1)* %in, i32 %tid.x %val = load i32, i32 addrspace(1)* %ptr, align 4 %shl = add i32 %val, 999 @@ -57,8 +57,8 @@ define void @shl_2_add_999_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 ; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3 -; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] -; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 +; SI: s_add_i32 [[RESULT:s[0-9]+]], [[SHL3]], [[Y]] +; SI: s_addk_i32 [[RESULT]], 0x3d8 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] ; SI: buffer_store_dword [[VRESULT]] define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) #0 { @@ -73,7 +73,7 @@ define void @test_add_shl_add_constant(i32 addrspace(1)* %out, i32 %x, i32 %y) # ; SI-DAG: s_load_dword [[X:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb ; SI-DAG: s_load_dword [[Y:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc ; SI: s_lshl_b32 [[SHL3:s[0-9]+]], [[X]], 3 -; SI: s_add_i32 [[TMP:s[0-9]+]], [[SHL3]], [[Y]] +; SI: s_add_i32 [[TMP:s[0-9]+]], [[Y]], [[SHL3]] ; SI: s_add_i32 [[RESULT:s[0-9]+]], [[TMP]], 0x3d8 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[RESULT]] ; SI: buffer_store_dword [[VRESULT]] diff --git a/test/CodeGen/AMDGPU/shl_add_ptr.ll b/test/CodeGen/AMDGPU/shl_add_ptr.ll index ac94824bd61f..a6be2eda33b3 100644 --- a/test/CodeGen/AMDGPU/shl_add_ptr.ll +++ b/test/CodeGen/AMDGPU/shl_add_ptr.ll @@ -7,7 +7,7 @@ ; LDS globals. -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 @lds0 = addrspace(3) global [512 x float] undef, align 4 @lds1 = addrspace(3) global [512 x float] undef, align 4 @@ -20,7 +20,7 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; SI: ds_read_b32 {{v[0-9]+}}, [[PTR]] offset:8 ; SI: s_endpgm define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -40,7 +40,7 @@ define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %ad ; SI-DAG: buffer_store_dword [[ADDUSE]] ; SI: s_endpgm define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -56,7 +56,7 @@ define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %ad ; SI: ds_read_u8 v{{[0-9]+}}, v{{[0-9]+}} offset:65535 ; SI: s_endpgm define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 65535 %arrayidx0 = getelementptr inbounds [65536 x i8], [65536 x i8] addrspace(3)* @maxlds, i32 0, i32 %idx.0 %val0 = load i8, i8 addrspace(3)* %arrayidx0 @@ -74,7 +74,7 @@ define void @load_shl_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3) ; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 ; SI: s_endpgm define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 64 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 %val0 = load float, float addrspace(3)* %arrayidx0, align 4 @@ -90,7 +90,7 @@ define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 { ; SI: ds_write_b32 [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds0, i32 0, i32 %idx.0 store float 1.0, float addrspace(3)* %arrayidx0, align 4 @@ -105,7 +105,7 @@ define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %a @lds2 = addrspace(3) global [512 x i32] undef, align 4 ; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { -; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 +; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 ; %idx.0 = add nsw i32 %tid.x, 2 ; %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 ; %val = load atomic i32, i32 addrspace(3)* %arrayidx0 seq_cst, align 4 @@ -120,7 +120,7 @@ define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %a ; SI: ds_cmpst_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}}, {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use, i32 %swap) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %pair = cmpxchg i32 addrspace(3)* %arrayidx0, i32 7, i32 %swap seq_cst monotonic @@ -135,7 +135,7 @@ define void @atomic_cmpxchg_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace ; SI: ds_wrxchg_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw xchg i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -149,7 +149,7 @@ define void @atomic_swap_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1) ; SI: ds_add_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw add i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -163,7 +163,7 @@ define void @atomic_add_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_sub_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw sub i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -177,7 +177,7 @@ define void @atomic_sub_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_and_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw and i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -191,7 +191,7 @@ define void @atomic_and_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_or_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw or i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -205,7 +205,7 @@ define void @atomic_or_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_xor_rtn_b32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw xor i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -215,7 +215,7 @@ define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* } ; define void @atomic_nand_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { -; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 +; %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 ; %idx.0 = add nsw i32 %tid.x, 2 ; %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 ; %val = atomicrmw nand i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -229,7 +229,7 @@ define void @atomic_xor_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_min_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw min i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -243,7 +243,7 @@ define void @atomic_min_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_max_rtn_i32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw max i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -257,7 +257,7 @@ define void @atomic_max_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* ; SI: ds_min_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw umin i32 addrspace(3)* %arrayidx0, i32 3 seq_cst @@ -271,7 +271,7 @@ define void @atomic_umin_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1) ; SI: ds_max_rtn_u32 {{v[0-9]+}}, [[PTR]], {{v[0-9]+}} offset:8 ; SI: s_endpgm define void @atomic_umax_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { - %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1 + %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %idx.0 = add nsw i32 %tid.x, 2 %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(3)* @lds2, i32 0, i32 %idx.0 %val = atomicrmw umax i32 addrspace(3)* %arrayidx0, i32 3 seq_cst diff --git a/test/CodeGen/AMDGPU/si-annotate-cf-assertion.ll b/test/CodeGen/AMDGPU/si-annotate-cf-assertion.ll deleted file mode 100644 index 69d719385acd..000000000000 --- a/test/CodeGen/AMDGPU/si-annotate-cf-assertion.ll +++ /dev/null @@ -1,25 +0,0 @@ -; REQUIRES: asserts -; XFAIL: * -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs-asm-verbose=false < %s | FileCheck %s - - -define void @test(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind { -; CHECK-LABEL: {{^}}test: - -entry: - switch i32 %x, label %sw.default [ - i32 0, label %sw.bb - i32 60, label %sw.bb - ] - -sw.bb: - unreachable - -sw.default: - unreachable - -sw.epilog: - ret void -} - diff --git a/test/CodeGen/AMDGPU/si-annotate-cf.ll b/test/CodeGen/AMDGPU/si-annotate-cf.ll index bbcb861f37dc..133fd480e599 100644 --- a/test/CodeGen/AMDGPU/si-annotate-cf.ll +++ b/test/CodeGen/AMDGPU/si-annotate-cf.ll @@ -10,9 +10,10 @@ ; SI: s_andn2_b64 ; s_cbranch_execnz [[LOOP_LABEL]] ; SI: s_endpgm -define void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a, i32 %b) { +define void @break_inserted_outside_of_loop(i32 addrspace(1)* %out, i32 %a) { main_body: - %0 = and i32 %a, %b + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %0 = and i32 %a, %tid %1 = trunc i32 %0 to i1 br label %ENDIF @@ -39,9 +40,10 @@ ENDIF: ; SI: s_cbranch_execnz [[LOOP_LABEL]] ; SI: s_endpgm -define void @phi_cond_outside_loop(i32 %a, i32 %b) { +define void @phi_cond_outside_loop(i32 %b) { entry: - %0 = icmp eq i32 %a , 0 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %0 = icmp eq i32 %tid , 0 br i1 %0, label %if, label %else if: @@ -61,3 +63,88 @@ loop: exit: ret void } + +; FIXME: should emit s_endpgm +; CHECK-LABEL: {{^}}switch_unreachable: +; CHECK-NOT: s_endpgm +; CHECK: .Lfunc_end2 +define void @switch_unreachable(i32 addrspace(1)* %g, i8 addrspace(3)* %l, i32 %x) nounwind { +centry: + switch i32 %x, label %sw.default [ + i32 0, label %sw.bb + i32 60, label %sw.bb + ] + +sw.bb: + unreachable + +sw.default: + unreachable + +sw.epilog: + ret void +} + +declare float @llvm.fabs.f32(float) nounwind readnone + +; This broke the old AMDIL cfg structurizer +; FUNC-LABEL: {{^}}loop_land_info_assert: +; SI: s_cmp_gt_i32 +; SI-NEXT: s_cbranch_scc0 [[ENDPGM:BB[0-9]+_[0-9]+]] + +; SI: s_cmp_gt_i32 +; SI-NEXT: s_cbranch_scc1 [[ENDPGM]] + +; SI: [[INFLOOP:BB[0-9]+_[0-9]+]] +; SI: s_branch [[INFLOOP]] + +; SI: [[ENDPGM]]: +; SI: s_endpgm +define void @loop_land_info_assert(i32 %c0, i32 %c1, i32 %c2, i32 %c3, i32 %x, i32 %y, i1 %arg) nounwind { +entry: + %cmp = icmp sgt i32 %c0, 0 + br label %while.cond.outer + +while.cond.outer: + %tmp = load float, float addrspace(1)* undef + br label %while.cond + +while.cond: + %cmp1 = icmp slt i32 %c1, 4 + br i1 %cmp1, label %convex.exit, label %for.cond + +convex.exit: + %or = or i1 %cmp, %cmp1 + br i1 %or, label %return, label %if.end + +if.end: + %tmp3 = call float @llvm.fabs.f32(float %tmp) nounwind readnone + %cmp2 = fcmp olt float %tmp3, 0x3E80000000000000 + br i1 %cmp2, label %if.else, label %while.cond.outer + +if.else: + store volatile i32 3, i32 addrspace(1)* undef, align 4 + br label %while.cond + +for.cond: + %cmp3 = icmp slt i32 %c3, 1000 + br i1 %cmp3, label %for.body, label %return + +for.body: + br i1 %cmp3, label %self.loop, label %if.end.2 + +if.end.2: + %or.cond2 = or i1 %cmp3, %arg + br i1 %or.cond2, label %return, label %for.cond + +self.loop: + br label %self.loop + +return: + ret void +} + + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll b/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll new file mode 100644 index 000000000000..025a3d8fca2e --- /dev/null +++ b/test/CodeGen/AMDGPU/si-annotate-cfg-loop-assert.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: {{^}}test: +; CHECK s_and_saveexec_b64 +; CHECK s_xor_b64 +; CHECK s_or_b64 exec, exec +; CHECK s_andn2_b64 exec, exec +; CHECK s_cbranch_execnz +define void @test(i32 %arg, i32 %arg1) { +bb: + %tmp = icmp ne i32 %arg, 0 + %tmp7 = icmp ne i32 %arg1, 0 + %tmp8 = and i1 %tmp, %tmp7 + br i1 %tmp8, label %bb9, label %bb11 + +bb9: ; preds = %bb + br label %bb10 + +bb10: ; preds = %bb10, %bb9 + br label %bb10 + +bb11: ; preds = %bb + ret void +} diff --git a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll index 27a8e70aae13..98d1bb7cf9a2 100644 --- a/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll +++ b/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll @@ -1,15 +1,15 @@ -; RUN: llc -o /dev/null %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos 2>&1 | FileCheck %s +; RUN: llc -o - %s -march=amdgcn -mcpu=verde -verify-machineinstrs -stop-after expand-isel-pseudos | FileCheck %s ; This test verifies that the instruction selection will add the implicit ; register operands in the correct order when modifying the opcode of an ; instruction to V_ADD_I32_e32. -; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit-def %vcc, implicit %exec +; CHECK: %{{[0-9]+}} = V_ADD_I32_e32 killed %{{[0-9]+}}, killed %{{[0-9]+}}, implicit-def %vcc, implicit %exec define void @test(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { entry: %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 - %a = load i32, i32 addrspace(1)* %in - %b = load i32, i32 addrspace(1)* %b_ptr + %a = load volatile i32, i32 addrspace(1)* %in + %b = load volatile i32, i32 addrspace(1)* %b_ptr %result = add i32 %a, %b store i32 %result, i32 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/si-literal-folding.ll b/test/CodeGen/AMDGPU/si-literal-folding.ll index 901b3c3453fc..d5030adc89be 100644 --- a/test/CodeGen/AMDGPU/si-literal-folding.ll +++ b/test/CodeGen/AMDGPU/si-literal-folding.ll @@ -4,7 +4,7 @@ ; CHECK-LABEL: {{^}}main: ; CHECK-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0xbf4353f8 -define void @main(float) #0 { +define amdgpu_vs void @main(float) { main_body: %1 = fmul float %0, 0x3FE86A7F00000000 %2 = fmul float %0, 0xBFE86A7F00000000 @@ -13,5 +13,3 @@ main_body: } declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="1" } diff --git a/test/CodeGen/AMDGPU/si-lod-bias.ll b/test/CodeGen/AMDGPU/si-lod-bias.ll index 944499a11461..8df0a64a2b7c 100644 --- a/test/CodeGen/AMDGPU/si-lod-bias.ll +++ b/test/CodeGen/AMDGPU/si-lod-bias.ll @@ -5,32 +5,32 @@ ; the wrong register class is used for the REG_SEQUENCE instructions. ; CHECK: {{^}}main: -; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, 15, 0, 0, 0, 0, 0, 0, 0, v{{\[[0-9]:[0-9]\]}} - -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +; CHECK: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf +define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) { main_body: - %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 - %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20, !tbaa !1 - %22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16) - %23 = getelementptr <32 x i8>, <32 x i8> addrspace(2)* %2, i32 0 - %24 = load <32 x i8>, <32 x i8> addrspace(2)* %23, !tbaa !1 - %25 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %1, i32 0 - %26 = load <16 x i8>, <16 x i8> addrspace(2)* %25, !tbaa !1 - %27 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %5) - %28 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %5) - %29 = bitcast float %22 to i32 - %30 = bitcast float %27 to i32 - %31 = bitcast float %28 to i32 - %32 = insertelement <4 x i32> undef, i32 %29, i32 0 - %33 = insertelement <4 x i32> %32, i32 %30, i32 1 - %34 = insertelement <4 x i32> %33, i32 %31, i32 2 - %35 = insertelement <4 x i32> %34, i32 undef, i32 3 - %36 = call <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32> %35, <32 x i8> %24, <16 x i8> %26, i32 2) - %37 = extractelement <4 x float> %36, i32 0 - %38 = extractelement <4 x float> %36, i32 1 - %39 = extractelement <4 x float> %36, i32 2 - %40 = extractelement <4 x float> %36, i32 3 - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %37, float %38, float %39, float %40) + %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg, i32 0 + %tmp20 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp21 = call float @llvm.SI.load.const(<16 x i8> %tmp20, i32 16) + %tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 + %tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0 + %tmp24 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg1, i32 0 + %tmp25 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp24, !tbaa !0 + %tmp26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg3, <2 x i32> %arg5) + %tmp27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg3, <2 x i32> %arg5) + %tmp28 = bitcast float %tmp21 to i32 + %tmp29 = bitcast float %tmp26 to i32 + %tmp30 = bitcast float %tmp27 to i32 + %tmp31 = insertelement <4 x i32> undef, i32 %tmp28, i32 0 + %tmp32 = insertelement <4 x i32> %tmp31, i32 %tmp29, i32 1 + %tmp33 = insertelement <4 x i32> %tmp32, i32 %tmp30, i32 2 + %tmp34 = insertelement <4 x i32> %tmp33, i32 undef, i32 3 + %tmp25.bc = bitcast <16 x i8> %tmp25 to <4 x i32> + %tmp35 = call <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32> %tmp34, <8 x i32> %tmp23, <4 x i32> %tmp25.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp36 = extractelement <4 x float> %tmp35, i32 0 + %tmp37 = extractelement <4 x float> %tmp35, i32 1 + %tmp38 = extractelement <4 x float> %tmp35, i32 2 + %tmp39 = extractelement <4 x float> %tmp35, i32 3 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %tmp36, float %tmp37, float %tmp38, float %tmp39) ret void } @@ -40,13 +40,13 @@ declare float @llvm.SI.load.const(<16 x i8>, i32) #1 ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 -; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sampleb.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.image.sample.b.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } + attributes #1 = { nounwind readnone } -!0 = !{!"const", null} -!1 = !{!0, !0, i64 0, i32 1} +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} diff --git a/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll new file mode 100644 index 000000000000..ea506e6b3b3f --- /dev/null +++ b/test/CodeGen/AMDGPU/si-lower-control-flow-unreachable-block.ll @@ -0,0 +1,56 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator: +; GCN: v_cmp_eq_i32 +; GCN: s_and_saveexec_b64 +; GCN: s_xor_b64 +; GCN: s_branch BB0_1 + +; GCN: s_or_b64 exec, exec +; GCN: s_endpgm + +; GCN: ds_write_b32 +; GCN: s_waitcnt +define void @lower_control_flow_unreachable_terminator() #0 { +bb: + %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y() + %tmp63 = icmp eq i32 %tmp15, 32 + br i1 %tmp63, label %bb64, label %bb68 + +bb64: + store volatile i32 0, i32 addrspace(3)* undef, align 4 + unreachable + +bb68: + ret void +} + +; GCN-LABEL: {{^}}lower_control_flow_unreachable_terminator_swap_block_order: +; GCN: v_cmp_eq_i32 +; GCN: s_and_saveexec_b64 +; GCN: s_xor_b64 +; GCN: s_endpgm + +; GCN: s_or_b64 exec, exec +; GCN: ds_write_b32 +; GCN: s_waitcnt +define void @lower_control_flow_unreachable_terminator_swap_block_order() #0 { +bb: + %tmp15 = tail call i32 @llvm.amdgcn.workitem.id.y() + %tmp63 = icmp eq i32 %tmp15, 32 + br i1 %tmp63, label %bb68, label %bb64 + +bb68: + ret void + +bb64: + store volatile i32 0, i32 addrspace(3)* undef, align 4 + unreachable +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.y() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/AMDGPU/si-scheduler.ll b/test/CodeGen/AMDGPU/si-scheduler.ll index 66a9571d75bf..5520fe61d867 100644 --- a/test/CodeGen/AMDGPU/si-scheduler.ll +++ b/test/CodeGen/AMDGPU/si-scheduler.ll @@ -1,4 +1,9 @@ -; RUN: llc -march=amdgcn -mcpu=SI --misched=si < %s | FileCheck %s +; FIXME: The si scheduler crashes if when lane mask tracking is enabled, so +; we need to disable this when the si scheduler is being used. +; The only way the subtarget knows that the si machine scheduler is being used +; is to specify -mattr=si-scheduler. If we just pass --misched=si, the backend +; won't know what scheduler we are using. +; RUN: llc -march=amdgcn -mcpu=SI --misched=si -mattr=si-scheduler < %s | FileCheck %s ; The test checks the "si" machine scheduler pass works correctly. @@ -11,45 +16,45 @@ ; CHECK: s_waitcnt vmcnt(0) ; CHECK: exp ; CHECK: s_endpgm - -define void @main([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, -<2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 { +define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { main_body: - %22 = bitcast [34 x <8 x i32>] addrspace(2)* %3 to <32 x i8> addrspace(2)* - %23 = load <32 x i8>, <32 x i8> addrspace(2)* %22, align 32, !tbaa !0 - %24 = bitcast [17 x <4 x i32>] addrspace(2)* %2 to <16 x i8> addrspace(2)* - %25 = load <16 x i8>, <16 x i8> addrspace(2)* %24, align 16, !tbaa !0 - %26 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %11) - %27 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %11) - %28 = bitcast float %26 to i32 - %29 = bitcast float %27 to i32 - %30 = insertelement <2 x i32> undef, i32 %28, i32 0 - %31 = insertelement <2 x i32> %30, i32 %29, i32 1 - %32 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %31, <32 x i8> %23, <16 x i8> %25, i32 2) - %33 = extractelement <4 x float> %32, i32 0 - %34 = extractelement <4 x float> %32, i32 1 - %35 = extractelement <4 x float> %32, i32 2 - %36 = extractelement <4 x float> %32, i32 3 - %37 = call i32 @llvm.SI.packf16(float %33, float %34) - %38 = bitcast i32 %37 to float - %39 = call i32 @llvm.SI.packf16(float %35, float %36) - %40 = bitcast i32 %39 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %38, float %40, float %38, float %40) + %tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)* + %tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0 + %tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)* + %tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0 + %tmp25 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg5, <2 x i32> %arg11) + %tmp26 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg5, <2 x i32> %arg11) + %tmp27 = bitcast float %tmp25 to i32 + %tmp28 = bitcast float %tmp26 to i32 + %tmp29 = insertelement <2 x i32> undef, i32 %tmp27, i32 0 + %tmp30 = insertelement <2 x i32> %tmp29, i32 %tmp28, i32 1 + %tmp22.bc = bitcast <32 x i8> %tmp22 to <8 x i32> + %tmp24.bc = bitcast <16 x i8> %tmp24 to <4 x i32> + %tmp31 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp30, <8 x i32> %tmp22.bc, <4 x i32> %tmp24.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp32 = extractelement <4 x float> %tmp31, i32 0 + %tmp33 = extractelement <4 x float> %tmp31, i32 1 + %tmp34 = extractelement <4 x float> %tmp31, i32 2 + %tmp35 = extractelement <4 x float> %tmp31, i32 3 + %tmp36 = call i32 @llvm.SI.packf16(float %tmp32, float %tmp33) + %tmp37 = bitcast i32 %tmp36 to float + %tmp38 = call i32 @llvm.SI.packf16(float %tmp34, float %tmp35) + %tmp39 = bitcast i32 %tmp38 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp37, float %tmp39, float %tmp37, float %tmp39) ret void } ; Function Attrs: nounwind readnone declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 -; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } attributes #1 = { nounwind readnone } -!0 = !{!"const", null, i32 1} +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} diff --git a/test/CodeGen/AMDGPU/si-sgpr-spill.ll b/test/CodeGen/AMDGPU/si-sgpr-spill.ll index d7b35fc631eb..63b1b71a8cb7 100644 --- a/test/CodeGen/AMDGPU/si-sgpr-spill.ll +++ b/test/CodeGen/AMDGPU/si-sgpr-spill.ll @@ -1,9 +1,12 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s ; These tests check that the compiler won't crash when it needs to spill ; SGPRs. + +@ddxy_lds = external addrspace(3) global [64 x i32] + ; CHECK-LABEL: {{^}}main: ; CHECK: s_wqm @@ -19,1560 +22,1601 @@ ; Writing to M0 from an SMRD instruction will hang the GPU. ; CHECK-NOT: s_buffer_load_dword m0 ; CHECK: s_endpgm -@ddxy_lds = external addrspace(3) global [64 x i32] - -define void @main([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @main([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { main_body: - %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 - %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !0 - %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 96) - %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 100) - %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 104) - %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 112) - %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 116) - %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 120) - %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128) - %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132) - %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 140) - %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144) - %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160) - %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176) - %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180) - %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184) - %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192) - %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196) - %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200) - %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208) - %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212) - %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216) - %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 224) - %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 240) - %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 244) - %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 248) - %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 256) - %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 272) - %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 276) - %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 280) - %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 288) - %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 292) - %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 296) - %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 304) - %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 308) - %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 312) - %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 368) - %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 372) - %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 376) - %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 384) - %61 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 - %62 = load <32 x i8>, <32 x i8> addrspace(2)* %61, !tbaa !0 - %63 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 - %64 = load <16 x i8>, <16 x i8> addrspace(2)* %63, !tbaa !0 - %65 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 - %66 = load <32 x i8>, <32 x i8> addrspace(2)* %65, !tbaa !0 - %67 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 - %68 = load <16 x i8>, <16 x i8> addrspace(2)* %67, !tbaa !0 - %69 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 - %70 = load <32 x i8>, <32 x i8> addrspace(2)* %69, !tbaa !0 - %71 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 - %72 = load <16 x i8>, <16 x i8> addrspace(2)* %71, !tbaa !0 - %73 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 - %74 = load <32 x i8>, <32 x i8> addrspace(2)* %73, !tbaa !0 - %75 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 - %76 = load <16 x i8>, <16 x i8> addrspace(2)* %75, !tbaa !0 - %77 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 - %78 = load <32 x i8>, <32 x i8> addrspace(2)* %77, !tbaa !0 - %79 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 - %80 = load <16 x i8>, <16 x i8> addrspace(2)* %79, !tbaa !0 - %81 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 - %82 = load <32 x i8>, <32 x i8> addrspace(2)* %81, !tbaa !0 - %83 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 - %84 = load <16 x i8>, <16 x i8> addrspace(2)* %83, !tbaa !0 - %85 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 - %86 = load <32 x i8>, <32 x i8> addrspace(2)* %85, !tbaa !0 - %87 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 - %88 = load <16 x i8>, <16 x i8> addrspace(2)* %87, !tbaa !0 - %89 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 - %90 = load <32 x i8>, <32 x i8> addrspace(2)* %89, !tbaa !0 - %91 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 - %92 = load <16 x i8>, <16 x i8> addrspace(2)* %91, !tbaa !0 - %93 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) - %94 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) - %95 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) - %96 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) - %97 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6) - %98 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6) - %99 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6) - %100 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6) - %101 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6) - %102 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6) - %103 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %4, <2 x i32> %6) - %104 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6) - %105 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6) - %106 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6) - %107 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6) - %108 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6) - %109 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6) - %110 = call i32 @llvm.SI.tid() - %111 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %110 - %112 = bitcast float %93 to i32 - store i32 %112, i32 addrspace(3)* %111 - %113 = bitcast float %94 to i32 - store i32 %113, i32 addrspace(3)* %111 - %114 = call i32 @llvm.SI.tid() - %115 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %114 - %116 = and i32 %114, -4 - %117 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %116 - %118 = add i32 %116, 1 - %119 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %118 - %120 = bitcast float %93 to i32 - store i32 %120, i32 addrspace(3)* %115 - %121 = load i32, i32 addrspace(3)* %117 - %122 = bitcast i32 %121 to float - %123 = load i32, i32 addrspace(3)* %119 - %124 = bitcast i32 %123 to float - %125 = fsub float %124, %122 - %126 = bitcast float %94 to i32 - store i32 %126, i32 addrspace(3)* %115 - %127 = load i32, i32 addrspace(3)* %117 - %128 = bitcast i32 %127 to float - %129 = load i32, i32 addrspace(3)* %119 - %130 = bitcast i32 %129 to float - %131 = fsub float %130, %128 - %132 = insertelement <4 x float> undef, float %125, i32 0 - %133 = insertelement <4 x float> %132, float %131, i32 1 - %134 = insertelement <4 x float> %133, float %131, i32 2 - %135 = insertelement <4 x float> %134, float %131, i32 3 - %136 = extractelement <4 x float> %135, i32 0 - %137 = extractelement <4 x float> %135, i32 1 - %138 = fmul float %60, %93 - %139 = fmul float %60, %94 - %140 = fmul float %60, %94 - %141 = fmul float %60, %94 - %142 = call i32 @llvm.SI.tid() - %143 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %142 - %144 = bitcast float %138 to i32 - store i32 %144, i32 addrspace(3)* %143 - %145 = bitcast float %139 to i32 - store i32 %145, i32 addrspace(3)* %143 - %146 = bitcast float %140 to i32 - store i32 %146, i32 addrspace(3)* %143 - %147 = bitcast float %141 to i32 - store i32 %147, i32 addrspace(3)* %143 - %148 = call i32 @llvm.SI.tid() - %149 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %148 - %150 = and i32 %148, -4 - %151 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %150 - %152 = add i32 %150, 2 - %153 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %152 - %154 = bitcast float %138 to i32 - store i32 %154, i32 addrspace(3)* %149 - %155 = load i32, i32 addrspace(3)* %151 - %156 = bitcast i32 %155 to float - %157 = load i32, i32 addrspace(3)* %153 - %158 = bitcast i32 %157 to float - %159 = fsub float %158, %156 - %160 = bitcast float %139 to i32 - store i32 %160, i32 addrspace(3)* %149 - %161 = load i32, i32 addrspace(3)* %151 - %162 = bitcast i32 %161 to float - %163 = load i32, i32 addrspace(3)* %153 - %164 = bitcast i32 %163 to float - %165 = fsub float %164, %162 - %166 = bitcast float %140 to i32 - store i32 %166, i32 addrspace(3)* %149 - %167 = load i32, i32 addrspace(3)* %151 - %168 = bitcast i32 %167 to float - %169 = load i32, i32 addrspace(3)* %153 - %170 = bitcast i32 %169 to float - %171 = fsub float %170, %168 - %172 = bitcast float %141 to i32 - store i32 %172, i32 addrspace(3)* %149 - %173 = load i32, i32 addrspace(3)* %151 - %174 = bitcast i32 %173 to float - %175 = load i32, i32 addrspace(3)* %153 - %176 = bitcast i32 %175 to float - %177 = fsub float %176, %174 - %178 = insertelement <4 x float> undef, float %159, i32 0 - %179 = insertelement <4 x float> %178, float %165, i32 1 - %180 = insertelement <4 x float> %179, float %171, i32 2 - %181 = insertelement <4 x float> %180, float %177, i32 3 - %182 = extractelement <4 x float> %181, i32 0 - %183 = extractelement <4 x float> %181, i32 1 - %184 = fdiv float 1.000000e+00, %97 - %185 = fmul float %33, %184 - %186 = fcmp uge float 1.000000e+00, %185 - %187 = select i1 %186, float %185, float 1.000000e+00 - %188 = fmul float %187, %30 - %189 = call float @ceil(float %188) - %190 = fcmp uge float 3.000000e+00, %189 - %191 = select i1 %190, float 3.000000e+00, float %189 - %192 = fdiv float 1.000000e+00, %191 - %193 = fdiv float 1.000000e+00, %30 - %194 = fmul float %191, %193 - %195 = fmul float %31, %194 - %196 = fmul float %95, %95 - %197 = fmul float %96, %96 - %198 = fadd float %197, %196 - %199 = fmul float %97, %97 - %200 = fadd float %198, %199 - %201 = call float @llvm.AMDGPU.rsq.f32(float %200) - %202 = fmul float %95, %201 - %203 = fmul float %96, %201 - %204 = fmul float %202, %29 - %205 = fmul float %203, %29 - %206 = fmul float %204, -1.000000e+00 - %207 = fmul float %205, 1.000000e+00 - %208 = fmul float %206, %32 - %209 = fmul float %207, %32 - %210 = fsub float -0.000000e+00, %208 - %211 = fadd float %93, %210 - %212 = fsub float -0.000000e+00, %209 - %213 = fadd float %94, %212 - %214 = fmul float %206, %192 - %215 = fmul float %207, %192 - %216 = fmul float -1.000000e+00, %192 - %217 = bitcast float %136 to i32 - %218 = bitcast float %182 to i32 - %219 = bitcast float %137 to i32 - %220 = bitcast float %183 to i32 - %221 = insertelement <8 x i32> undef, i32 %217, i32 0 - %222 = insertelement <8 x i32> %221, i32 %218, i32 1 - %223 = insertelement <8 x i32> %222, i32 %219, i32 2 - %224 = insertelement <8 x i32> %223, i32 %220, i32 3 + %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 + %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 96) + %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 100) + %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 104) + %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 112) + %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 116) + %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 120) + %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 128) + %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 132) + %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 140) + %tmp31 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 144) + %tmp32 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 160) + %tmp33 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 176) + %tmp34 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 180) + %tmp35 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 184) + %tmp36 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 192) + %tmp37 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 196) + %tmp38 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 200) + %tmp39 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 208) + %tmp40 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 212) + %tmp41 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 216) + %tmp42 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 224) + %tmp43 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 240) + %tmp44 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 244) + %tmp45 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 248) + %tmp46 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 256) + %tmp47 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 272) + %tmp48 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 276) + %tmp49 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 280) + %tmp50 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 288) + %tmp51 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 292) + %tmp52 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 296) + %tmp53 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 304) + %tmp54 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 308) + %tmp55 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 312) + %tmp56 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 368) + %tmp57 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 372) + %tmp58 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 376) + %tmp59 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 384) + %tmp60 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 + %tmp61 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp60, !tbaa !0 + %tmp62 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0 + %tmp63 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp62, !tbaa !0 + %tmp63.bc = bitcast <16 x i8> %tmp63 to <4 x i32> + %tmp64 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 1 + %tmp65 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp64, !tbaa !0 + %tmp66 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 1 + %tmp67 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp66, !tbaa !0 + %tmp68 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 2 + %tmp69 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp68, !tbaa !0 + %tmp70 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 2 + %tmp71 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp70, !tbaa !0 + %tmp72 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 3 + %tmp73 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp72, !tbaa !0 + %tmp74 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 3 + %tmp75 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp74, !tbaa !0 + %tmp76 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 4 + %tmp77 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp76, !tbaa !0 + %tmp78 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 4 + %tmp79 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp78, !tbaa !0 + %tmp80 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 5 + %tmp81 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp80, !tbaa !0 + %tmp82 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 5 + %tmp83 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp82, !tbaa !0 + %tmp84 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 6 + %tmp85 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp84, !tbaa !0 + %tmp86 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 6 + %tmp87 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp86, !tbaa !0 + %tmp88 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 7 + %tmp89 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp88, !tbaa !0 + %tmp90 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 7 + %tmp91 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp90, !tbaa !0 + %tmp92 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp93 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp94 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp95 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp96 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp97 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp98 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp99 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp100 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp101 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp102 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp103 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp104 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp105 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp106 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp107 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp108 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %arg4, <2 x i32> %arg6) + %mbcnt.lo.0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tmp109 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.0) + %tmp110 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp109 + %tmp111 = bitcast float %tmp92 to i32 + store i32 %tmp111, i32 addrspace(3)* %tmp110 + %tmp112 = bitcast float %tmp93 to i32 + store i32 %tmp112, i32 addrspace(3)* %tmp110 + %mbcnt.lo.1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tmp113 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.1) + %tmp114 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp113 + %tmp115 = and i32 %tmp113, -4 + %tmp116 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp115 + %tmp117 = add i32 %tmp115, 1 + %tmp118 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp117 + %tmp119 = bitcast float %tmp92 to i32 + store i32 %tmp119, i32 addrspace(3)* %tmp114 + %tmp120 = load i32, i32 addrspace(3)* %tmp116 + %tmp121 = bitcast i32 %tmp120 to float + %tmp122 = load i32, i32 addrspace(3)* %tmp118 + %tmp123 = bitcast i32 %tmp122 to float + %tmp124 = fsub float %tmp123, %tmp121 + %tmp125 = bitcast float %tmp93 to i32 + store i32 %tmp125, i32 addrspace(3)* %tmp114 + %tmp126 = load i32, i32 addrspace(3)* %tmp116 + %tmp127 = bitcast i32 %tmp126 to float + %tmp128 = load i32, i32 addrspace(3)* %tmp118 + %tmp129 = bitcast i32 %tmp128 to float + %tmp130 = fsub float %tmp129, %tmp127 + %tmp131 = insertelement <4 x float> undef, float %tmp124, i32 0 + %tmp132 = insertelement <4 x float> %tmp131, float %tmp130, i32 1 + %tmp133 = insertelement <4 x float> %tmp132, float %tmp130, i32 2 + %tmp134 = insertelement <4 x float> %tmp133, float %tmp130, i32 3 + %tmp135 = extractelement <4 x float> %tmp134, i32 0 + %tmp136 = extractelement <4 x float> %tmp134, i32 1 + %tmp137 = fmul float %tmp59, %tmp92 + %tmp138 = fmul float %tmp59, %tmp93 + %tmp139 = fmul float %tmp59, %tmp93 + %tmp140 = fmul float %tmp59, %tmp93 + %mbcnt.lo.2 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tmp141 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.2) + %tmp142 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp141 + %tmp143 = bitcast float %tmp137 to i32 + store i32 %tmp143, i32 addrspace(3)* %tmp142 + %tmp144 = bitcast float %tmp138 to i32 + store i32 %tmp144, i32 addrspace(3)* %tmp142 + %tmp145 = bitcast float %tmp139 to i32 + store i32 %tmp145, i32 addrspace(3)* %tmp142 + %tmp146 = bitcast float %tmp140 to i32 + store i32 %tmp146, i32 addrspace(3)* %tmp142 + %mbcnt.lo.3 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tmp147 = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo.3) + %tmp148 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp147 + %tmp149 = and i32 %tmp147, -4 + %tmp150 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp149 + %tmp151 = add i32 %tmp149, 2 + %tmp152 = getelementptr [64 x i32], [64 x i32] addrspace(3)* @ddxy_lds, i32 0, i32 %tmp151 + %tmp153 = bitcast float %tmp137 to i32 + store i32 %tmp153, i32 addrspace(3)* %tmp148 + %tmp154 = load i32, i32 addrspace(3)* %tmp150 + %tmp155 = bitcast i32 %tmp154 to float + %tmp156 = load i32, i32 addrspace(3)* %tmp152 + %tmp157 = bitcast i32 %tmp156 to float + %tmp158 = fsub float %tmp157, %tmp155 + %tmp159 = bitcast float %tmp138 to i32 + store i32 %tmp159, i32 addrspace(3)* %tmp148 + %tmp160 = load i32, i32 addrspace(3)* %tmp150 + %tmp161 = bitcast i32 %tmp160 to float + %tmp162 = load i32, i32 addrspace(3)* %tmp152 + %tmp163 = bitcast i32 %tmp162 to float + %tmp164 = fsub float %tmp163, %tmp161 + %tmp165 = bitcast float %tmp139 to i32 + store i32 %tmp165, i32 addrspace(3)* %tmp148 + %tmp166 = load i32, i32 addrspace(3)* %tmp150 + %tmp167 = bitcast i32 %tmp166 to float + %tmp168 = load i32, i32 addrspace(3)* %tmp152 + %tmp169 = bitcast i32 %tmp168 to float + %tmp170 = fsub float %tmp169, %tmp167 + %tmp171 = bitcast float %tmp140 to i32 + store i32 %tmp171, i32 addrspace(3)* %tmp148 + %tmp172 = load i32, i32 addrspace(3)* %tmp150 + %tmp173 = bitcast i32 %tmp172 to float + %tmp174 = load i32, i32 addrspace(3)* %tmp152 + %tmp175 = bitcast i32 %tmp174 to float + %tmp176 = fsub float %tmp175, %tmp173 + %tmp177 = insertelement <4 x float> undef, float %tmp158, i32 0 + %tmp178 = insertelement <4 x float> %tmp177, float %tmp164, i32 1 + %tmp179 = insertelement <4 x float> %tmp178, float %tmp170, i32 2 + %tmp180 = insertelement <4 x float> %tmp179, float %tmp176, i32 3 + %tmp181 = extractelement <4 x float> %tmp180, i32 0 + %tmp182 = extractelement <4 x float> %tmp180, i32 1 + %tmp183 = fdiv float 1.000000e+00, %tmp96 + %tmp184 = fmul float %tmp32, %tmp183 + %tmp185 = fcmp uge float 1.000000e+00, %tmp184 + %tmp186 = select i1 %tmp185, float %tmp184, float 1.000000e+00 + %tmp187 = fmul float %tmp186, %tmp29 + %tmp188 = call float @ceil(float %tmp187) + %tmp189 = fcmp uge float 3.000000e+00, %tmp188 + %tmp190 = select i1 %tmp189, float 3.000000e+00, float %tmp188 + %tmp191 = fdiv float 1.000000e+00, %tmp190 + %tmp192 = fdiv float 1.000000e+00, %tmp29 + %tmp193 = fmul float %tmp190, %tmp192 + %tmp194 = fmul float %tmp30, %tmp193 + %tmp195 = fmul float %tmp94, %tmp94 + %tmp196 = fmul float %tmp95, %tmp95 + %tmp197 = fadd float %tmp196, %tmp195 + %tmp198 = fmul float %tmp96, %tmp96 + %tmp199 = fadd float %tmp197, %tmp198 + %tmp200 = call float @llvm.amdgcn.rsq.f32(float %tmp199) + %tmp201 = fmul float %tmp94, %tmp200 + %tmp202 = fmul float %tmp95, %tmp200 + %tmp203 = fmul float %tmp201, %tmp28 + %tmp204 = fmul float %tmp202, %tmp28 + %tmp205 = fmul float %tmp203, -1.000000e+00 + %tmp206 = fmul float %tmp204, 1.000000e+00 + %tmp207 = fmul float %tmp205, %tmp31 + %tmp208 = fmul float %tmp206, %tmp31 + %tmp209 = fsub float -0.000000e+00, %tmp207 + %tmp210 = fadd float %tmp92, %tmp209 + %tmp211 = fsub float -0.000000e+00, %tmp208 + %tmp212 = fadd float %tmp93, %tmp211 + %tmp213 = fmul float %tmp205, %tmp191 + %tmp214 = fmul float %tmp206, %tmp191 + %tmp215 = fmul float -1.000000e+00, %tmp191 + %tmp216 = bitcast float %tmp135 to i32 + %tmp217 = bitcast float %tmp181 to i32 + %tmp218 = bitcast float %tmp136 to i32 + %tmp219 = bitcast float %tmp182 to i32 + %tmp220 = insertelement <8 x i32> undef, i32 %tmp216, i32 0 + %tmp221 = insertelement <8 x i32> %tmp220, i32 %tmp217, i32 1 + %tmp222 = insertelement <8 x i32> %tmp221, i32 %tmp218, i32 2 + %tmp223 = insertelement <8 x i32> %tmp222, i32 %tmp219, i32 3 br label %LOOP LOOP: ; preds = %ENDIF, %main_body - %temp24.0 = phi float [ 1.000000e+00, %main_body ], [ %258, %ENDIF ] - %temp28.0 = phi float [ %211, %main_body ], [ %253, %ENDIF ] - %temp29.0 = phi float [ %213, %main_body ], [ %255, %ENDIF ] - %temp30.0 = phi float [ 1.000000e+00, %main_body ], [ %257, %ENDIF ] - %225 = fcmp oge float %temp24.0, %191 - %226 = sext i1 %225 to i32 - %227 = bitcast i32 %226 to float - %228 = bitcast float %227 to i32 - %229 = icmp ne i32 %228, 0 - br i1 %229, label %IF, label %ENDIF + %temp24.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp257, %ENDIF ] + %temp28.0 = phi float [ %tmp210, %main_body ], [ %tmp252, %ENDIF ] + %temp29.0 = phi float [ %tmp212, %main_body ], [ %tmp254, %ENDIF ] + %temp30.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp256, %ENDIF ] + %tmp224 = fcmp oge float %temp24.0, %tmp190 + %tmp225 = sext i1 %tmp224 to i32 + %tmp226 = bitcast i32 %tmp225 to float + %tmp227 = bitcast float %tmp226 to i32 + %tmp228 = icmp ne i32 %tmp227, 0 + br i1 %tmp228, label %IF, label %ENDIF IF: ; preds = %LOOP - %230 = bitcast float %136 to i32 - %231 = bitcast float %182 to i32 - %232 = bitcast float %137 to i32 - %233 = bitcast float %183 to i32 - %234 = insertelement <8 x i32> undef, i32 %230, i32 0 - %235 = insertelement <8 x i32> %234, i32 %231, i32 1 - %236 = insertelement <8 x i32> %235, i32 %232, i32 2 - %237 = insertelement <8 x i32> %236, i32 %233, i32 3 + %tmp229 = bitcast float %tmp135 to i32 + %tmp230 = bitcast float %tmp181 to i32 + %tmp231 = bitcast float %tmp136 to i32 + %tmp232 = bitcast float %tmp182 to i32 + %tmp233 = insertelement <8 x i32> undef, i32 %tmp229, i32 0 + %tmp234 = insertelement <8 x i32> %tmp233, i32 %tmp230, i32 1 + %tmp235 = insertelement <8 x i32> %tmp234, i32 %tmp231, i32 2 + %tmp236 = insertelement <8 x i32> %tmp235, i32 %tmp232, i32 3 br label %LOOP65 ENDIF: ; preds = %LOOP - %238 = bitcast float %temp28.0 to i32 - %239 = bitcast float %temp29.0 to i32 - %240 = insertelement <8 x i32> %224, i32 %238, i32 4 - %241 = insertelement <8 x i32> %240, i32 %239, i32 5 - %242 = insertelement <8 x i32> %241, i32 undef, i32 6 - %243 = insertelement <8 x i32> %242, i32 undef, i32 7 - %244 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %243, <32 x i8> %62, <16 x i8> %64, i32 2) - %245 = extractelement <4 x float> %244, i32 3 - %246 = fcmp oge float %temp30.0, %245 - %247 = sext i1 %246 to i32 - %248 = bitcast i32 %247 to float - %249 = bitcast float %248 to i32 - %250 = and i32 %249, 1065353216 - %251 = bitcast i32 %250 to float - %252 = fmul float %214, %251 - %253 = fadd float %252, %temp28.0 - %254 = fmul float %215, %251 - %255 = fadd float %254, %temp29.0 - %256 = fmul float %216, %251 - %257 = fadd float %256, %temp30.0 - %258 = fadd float %temp24.0, 1.000000e+00 + %tmp237 = bitcast float %temp28.0 to i32 + %tmp238 = bitcast float %temp29.0 to i32 + %tmp239 = insertelement <8 x i32> %tmp223, i32 %tmp237, i32 4 + %tmp240 = insertelement <8 x i32> %tmp239, i32 %tmp238, i32 5 + %tmp241 = insertelement <8 x i32> %tmp240, i32 undef, i32 6 + %tmp242 = insertelement <8 x i32> %tmp241, i32 undef, i32 7 + %tmp243 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp242, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp244 = extractelement <4 x float> %tmp243, i32 3 + %tmp245 = fcmp oge float %temp30.0, %tmp244 + %tmp246 = sext i1 %tmp245 to i32 + %tmp247 = bitcast i32 %tmp246 to float + %tmp248 = bitcast float %tmp247 to i32 + %tmp249 = and i32 %tmp248, 1065353216 + %tmp250 = bitcast i32 %tmp249 to float + %tmp251 = fmul float %tmp213, %tmp250 + %tmp252 = fadd float %tmp251, %temp28.0 + %tmp253 = fmul float %tmp214, %tmp250 + %tmp254 = fadd float %tmp253, %temp29.0 + %tmp255 = fmul float %tmp215, %tmp250 + %tmp256 = fadd float %tmp255, %temp30.0 + %tmp257 = fadd float %temp24.0, 1.000000e+00 br label %LOOP LOOP65: ; preds = %ENDIF66, %IF - %temp24.1 = phi float [ 0.000000e+00, %IF ], [ %610, %ENDIF66 ] - %temp28.1 = phi float [ %temp28.0, %IF ], [ %605, %ENDIF66 ] - %temp29.1 = phi float [ %temp29.0, %IF ], [ %607, %ENDIF66 ] - %temp30.1 = phi float [ %temp30.0, %IF ], [ %609, %ENDIF66 ] - %temp32.0 = phi float [ 1.000000e+00, %IF ], [ %611, %ENDIF66 ] - %259 = fcmp oge float %temp24.1, %195 - %260 = sext i1 %259 to i32 - %261 = bitcast i32 %260 to float - %262 = bitcast float %261 to i32 - %263 = icmp ne i32 %262, 0 - br i1 %263, label %IF67, label %ENDIF66 + %temp24.1 = phi float [ 0.000000e+00, %IF ], [ %tmp609, %ENDIF66 ] + %temp28.1 = phi float [ %temp28.0, %IF ], [ %tmp604, %ENDIF66 ] + %temp29.1 = phi float [ %temp29.0, %IF ], [ %tmp606, %ENDIF66 ] + %temp30.1 = phi float [ %temp30.0, %IF ], [ %tmp608, %ENDIF66 ] + %temp32.0 = phi float [ 1.000000e+00, %IF ], [ %tmp610, %ENDIF66 ] + %tmp258 = fcmp oge float %temp24.1, %tmp194 + %tmp259 = sext i1 %tmp258 to i32 + %tmp260 = bitcast i32 %tmp259 to float + %tmp261 = bitcast float %tmp260 to i32 + %tmp262 = icmp ne i32 %tmp261, 0 + br i1 %tmp262, label %IF67, label %ENDIF66 IF67: ; preds = %LOOP65 - %264 = bitcast float %136 to i32 - %265 = bitcast float %182 to i32 - %266 = bitcast float %137 to i32 - %267 = bitcast float %183 to i32 - %268 = bitcast float %temp28.1 to i32 - %269 = bitcast float %temp29.1 to i32 - %270 = insertelement <8 x i32> undef, i32 %264, i32 0 - %271 = insertelement <8 x i32> %270, i32 %265, i32 1 - %272 = insertelement <8 x i32> %271, i32 %266, i32 2 - %273 = insertelement <8 x i32> %272, i32 %267, i32 3 - %274 = insertelement <8 x i32> %273, i32 %268, i32 4 - %275 = insertelement <8 x i32> %274, i32 %269, i32 5 - %276 = insertelement <8 x i32> %275, i32 undef, i32 6 - %277 = insertelement <8 x i32> %276, i32 undef, i32 7 - %278 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %277, <32 x i8> %66, <16 x i8> %68, i32 2) - %279 = extractelement <4 x float> %278, i32 0 - %280 = extractelement <4 x float> %278, i32 1 - %281 = extractelement <4 x float> %278, i32 2 - %282 = extractelement <4 x float> %278, i32 3 - %283 = fmul float %282, %47 - %284 = bitcast float %136 to i32 - %285 = bitcast float %182 to i32 - %286 = bitcast float %137 to i32 - %287 = bitcast float %183 to i32 - %288 = bitcast float %temp28.1 to i32 - %289 = bitcast float %temp29.1 to i32 - %290 = insertelement <8 x i32> undef, i32 %284, i32 0 - %291 = insertelement <8 x i32> %290, i32 %285, i32 1 - %292 = insertelement <8 x i32> %291, i32 %286, i32 2 - %293 = insertelement <8 x i32> %292, i32 %287, i32 3 - %294 = insertelement <8 x i32> %293, i32 %288, i32 4 - %295 = insertelement <8 x i32> %294, i32 %289, i32 5 - %296 = insertelement <8 x i32> %295, i32 undef, i32 6 - %297 = insertelement <8 x i32> %296, i32 undef, i32 7 - %298 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %297, <32 x i8> %82, <16 x i8> %84, i32 2) - %299 = extractelement <4 x float> %298, i32 0 - %300 = extractelement <4 x float> %298, i32 1 - %301 = extractelement <4 x float> %298, i32 2 - %302 = bitcast float %136 to i32 - %303 = bitcast float %182 to i32 - %304 = bitcast float %137 to i32 - %305 = bitcast float %183 to i32 - %306 = bitcast float %temp28.1 to i32 - %307 = bitcast float %temp29.1 to i32 - %308 = insertelement <8 x i32> undef, i32 %302, i32 0 - %309 = insertelement <8 x i32> %308, i32 %303, i32 1 - %310 = insertelement <8 x i32> %309, i32 %304, i32 2 - %311 = insertelement <8 x i32> %310, i32 %305, i32 3 - %312 = insertelement <8 x i32> %311, i32 %306, i32 4 - %313 = insertelement <8 x i32> %312, i32 %307, i32 5 - %314 = insertelement <8 x i32> %313, i32 undef, i32 6 - %315 = insertelement <8 x i32> %314, i32 undef, i32 7 - %316 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %315, <32 x i8> %78, <16 x i8> %80, i32 2) - %317 = extractelement <4 x float> %316, i32 0 - %318 = extractelement <4 x float> %316, i32 1 - %319 = extractelement <4 x float> %316, i32 2 - %320 = fmul float %317, %23 - %321 = fmul float %318, %24 - %322 = fmul float %319, %25 - %323 = fmul float %299, %26 - %324 = fadd float %323, %320 - %325 = fmul float %300, %27 - %326 = fadd float %325, %321 - %327 = fmul float %301, %28 - %328 = fadd float %327, %322 - %329 = fadd float %279, %324 - %330 = fadd float %280, %326 - %331 = fadd float %281, %328 - %332 = bitcast float %136 to i32 - %333 = bitcast float %182 to i32 - %334 = bitcast float %137 to i32 - %335 = bitcast float %183 to i32 - %336 = bitcast float %temp28.1 to i32 - %337 = bitcast float %temp29.1 to i32 - %338 = insertelement <8 x i32> undef, i32 %332, i32 0 - %339 = insertelement <8 x i32> %338, i32 %333, i32 1 - %340 = insertelement <8 x i32> %339, i32 %334, i32 2 - %341 = insertelement <8 x i32> %340, i32 %335, i32 3 - %342 = insertelement <8 x i32> %341, i32 %336, i32 4 - %343 = insertelement <8 x i32> %342, i32 %337, i32 5 - %344 = insertelement <8 x i32> %343, i32 undef, i32 6 - %345 = insertelement <8 x i32> %344, i32 undef, i32 7 - %346 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %345, <32 x i8> %62, <16 x i8> %64, i32 2) - %347 = extractelement <4 x float> %346, i32 0 - %348 = extractelement <4 x float> %346, i32 1 - %349 = extractelement <4 x float> %346, i32 2 - %350 = fadd float %347, -5.000000e-01 - %351 = fadd float %348, -5.000000e-01 - %352 = fadd float %349, -5.000000e-01 - %353 = fmul float %350, %350 - %354 = fmul float %351, %351 - %355 = fadd float %354, %353 - %356 = fmul float %352, %352 - %357 = fadd float %355, %356 - %358 = call float @llvm.AMDGPU.rsq.f32(float %357) - %359 = fmul float %350, %358 - %360 = fmul float %351, %358 - %361 = fmul float %352, %358 - %362 = bitcast float %136 to i32 - %363 = bitcast float %182 to i32 - %364 = bitcast float %137 to i32 - %365 = bitcast float %183 to i32 - %366 = bitcast float %temp28.1 to i32 - %367 = bitcast float %temp29.1 to i32 - %368 = insertelement <8 x i32> undef, i32 %362, i32 0 - %369 = insertelement <8 x i32> %368, i32 %363, i32 1 - %370 = insertelement <8 x i32> %369, i32 %364, i32 2 - %371 = insertelement <8 x i32> %370, i32 %365, i32 3 - %372 = insertelement <8 x i32> %371, i32 %366, i32 4 - %373 = insertelement <8 x i32> %372, i32 %367, i32 5 - %374 = insertelement <8 x i32> %373, i32 undef, i32 6 - %375 = insertelement <8 x i32> %374, i32 undef, i32 7 - %376 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %375, <32 x i8> %70, <16 x i8> %72, i32 2) - %377 = extractelement <4 x float> %376, i32 0 - %378 = extractelement <4 x float> %376, i32 1 - %379 = extractelement <4 x float> %376, i32 2 - %380 = extractelement <4 x float> %376, i32 3 - %381 = fsub float -0.000000e+00, %95 - %382 = fsub float -0.000000e+00, %96 - %383 = fsub float -0.000000e+00, %97 - %384 = fmul float %359, %381 - %385 = fmul float %360, %382 - %386 = fadd float %385, %384 - %387 = fmul float %361, %383 - %388 = fadd float %386, %387 - %389 = fmul float %388, %359 - %390 = fmul float %388, %360 - %391 = fmul float %388, %361 - %392 = fmul float 2.000000e+00, %389 - %393 = fmul float 2.000000e+00, %390 - %394 = fmul float 2.000000e+00, %391 - %395 = fsub float -0.000000e+00, %392 - %396 = fadd float %381, %395 - %397 = fsub float -0.000000e+00, %393 - %398 = fadd float %382, %397 - %399 = fsub float -0.000000e+00, %394 - %400 = fadd float %383, %399 - %401 = fmul float %396, %98 - %402 = fmul float %396, %99 - %403 = fmul float %396, %100 - %404 = fmul float %398, %101 - %405 = fadd float %404, %401 - %406 = fmul float %398, %102 - %407 = fadd float %406, %402 - %408 = fmul float %398, %103 - %409 = fadd float %408, %403 - %410 = fmul float %400, %104 - %411 = fadd float %410, %405 - %412 = fmul float %400, %105 - %413 = fadd float %412, %407 - %414 = fmul float %400, %106 - %415 = fadd float %414, %409 - %416 = bitcast float %136 to i32 - %417 = bitcast float %182 to i32 - %418 = bitcast float %137 to i32 - %419 = bitcast float %183 to i32 - %420 = bitcast float %temp28.1 to i32 - %421 = bitcast float %temp29.1 to i32 - %422 = insertelement <8 x i32> undef, i32 %416, i32 0 - %423 = insertelement <8 x i32> %422, i32 %417, i32 1 - %424 = insertelement <8 x i32> %423, i32 %418, i32 2 - %425 = insertelement <8 x i32> %424, i32 %419, i32 3 - %426 = insertelement <8 x i32> %425, i32 %420, i32 4 - %427 = insertelement <8 x i32> %426, i32 %421, i32 5 - %428 = insertelement <8 x i32> %427, i32 undef, i32 6 - %429 = insertelement <8 x i32> %428, i32 undef, i32 7 - %430 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %429, <32 x i8> %86, <16 x i8> %88, i32 2) - %431 = extractelement <4 x float> %430, i32 0 - %432 = extractelement <4 x float> %430, i32 1 - %433 = extractelement <4 x float> %430, i32 2 - %434 = fmul float %48, %411 - %435 = fmul float %49, %411 - %436 = fmul float %50, %411 - %437 = fmul float %51, %413 - %438 = fadd float %437, %434 - %439 = fmul float %52, %413 - %440 = fadd float %439, %435 - %441 = fmul float %53, %413 - %442 = fadd float %441, %436 - %443 = fmul float %54, %415 - %444 = fadd float %443, %438 - %445 = fmul float %55, %415 - %446 = fadd float %445, %440 - %447 = fmul float %56, %415 - %448 = fadd float %447, %442 - %449 = insertelement <4 x float> undef, float %444, i32 0 - %450 = insertelement <4 x float> %449, float %446, i32 1 - %451 = insertelement <4 x float> %450, float %448, i32 2 - %452 = insertelement <4 x float> %451, float %195, i32 3 - %453 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %452) - %454 = extractelement <4 x float> %453, i32 0 - %455 = extractelement <4 x float> %453, i32 1 - %456 = extractelement <4 x float> %453, i32 2 - %457 = extractelement <4 x float> %453, i32 3 - %458 = call float @fabs(float %456) - %459 = fdiv float 1.000000e+00, %458 - %460 = fmul float %454, %459 - %461 = fadd float %460, 1.500000e+00 - %462 = fmul float %455, %459 - %463 = fadd float %462, 1.500000e+00 - %464 = bitcast float %463 to i32 - %465 = bitcast float %461 to i32 - %466 = bitcast float %457 to i32 - %467 = insertelement <4 x i32> undef, i32 %464, i32 0 - %468 = insertelement <4 x i32> %467, i32 %465, i32 1 - %469 = insertelement <4 x i32> %468, i32 %466, i32 2 - %470 = insertelement <4 x i32> %469, i32 undef, i32 3 - %471 = call <4 x float> @llvm.SI.sample.v4i32(<4 x i32> %470, <32 x i8> %90, <16 x i8> %92, i32 4) - %472 = extractelement <4 x float> %471, i32 0 - %473 = extractelement <4 x float> %471, i32 1 - %474 = extractelement <4 x float> %471, i32 2 - %475 = fmul float %431, %472 - %476 = fadd float %475, %329 - %477 = fmul float %432, %473 - %478 = fadd float %477, %330 - %479 = fmul float %433, %474 - %480 = fadd float %479, %331 - %481 = fmul float %107, %107 - %482 = fmul float %108, %108 - %483 = fadd float %482, %481 - %484 = fmul float %109, %109 - %485 = fadd float %483, %484 - %486 = call float @llvm.AMDGPU.rsq.f32(float %485) - %487 = fmul float %107, %486 - %488 = fmul float %108, %486 - %489 = fmul float %109, %486 - %490 = fmul float %377, %40 - %491 = fmul float %378, %41 - %492 = fmul float %379, %42 - %493 = fmul float %359, %487 - %494 = fmul float %360, %488 - %495 = fadd float %494, %493 - %496 = fmul float %361, %489 - %497 = fadd float %495, %496 - %498 = fmul float %497, %359 - %499 = fmul float %497, %360 - %500 = fmul float %497, %361 - %501 = fmul float 2.000000e+00, %498 - %502 = fmul float 2.000000e+00, %499 - %503 = fmul float 2.000000e+00, %500 - %504 = fsub float -0.000000e+00, %501 - %505 = fadd float %487, %504 - %506 = fsub float -0.000000e+00, %502 - %507 = fadd float %488, %506 - %508 = fsub float -0.000000e+00, %503 - %509 = fadd float %489, %508 - %510 = fmul float %95, %95 - %511 = fmul float %96, %96 - %512 = fadd float %511, %510 - %513 = fmul float %97, %97 - %514 = fadd float %512, %513 - %515 = call float @llvm.AMDGPU.rsq.f32(float %514) - %516 = fmul float %95, %515 - %517 = fmul float %96, %515 - %518 = fmul float %97, %515 - %519 = fmul float %505, %516 - %520 = fmul float %507, %517 - %521 = fadd float %520, %519 - %522 = fmul float %509, %518 - %523 = fadd float %521, %522 - %524 = fsub float -0.000000e+00, %523 - %525 = fcmp uge float %524, 0.000000e+00 - %526 = select i1 %525, float %524, float 0.000000e+00 - %527 = fmul float %43, %380 - %528 = fadd float %527, 1.000000e+00 - %529 = call float @llvm.pow.f32(float %526, float %528) - %530 = fmul float %476, %37 - %531 = fmul float %478, %38 - %532 = fmul float %480, %39 - %533 = fmul float %359, %487 - %534 = fmul float %360, %488 - %535 = fadd float %534, %533 - %536 = fmul float %361, %489 - %537 = fadd float %535, %536 - %538 = fcmp uge float %537, 0.000000e+00 - %539 = select i1 %538, float %537, float 0.000000e+00 - %540 = fmul float %530, %539 - %541 = fmul float %531, %539 - %542 = fmul float %532, %539 - %543 = fmul float %490, %529 - %544 = fadd float %543, %540 - %545 = fmul float %491, %529 - %546 = fadd float %545, %541 - %547 = fmul float %492, %529 - %548 = fadd float %547, %542 - %549 = fmul float %476, %34 - %550 = fmul float %478, %35 - %551 = fmul float %480, %36 - %552 = fmul float %544, %57 - %553 = fadd float %552, %549 - %554 = fmul float %546, %58 - %555 = fadd float %554, %550 - %556 = fmul float %548, %59 - %557 = fadd float %556, %551 - %558 = bitcast float %136 to i32 - %559 = bitcast float %182 to i32 - %560 = bitcast float %137 to i32 - %561 = bitcast float %183 to i32 - %562 = bitcast float %temp28.1 to i32 - %563 = bitcast float %temp29.1 to i32 - %564 = insertelement <8 x i32> undef, i32 %558, i32 0 - %565 = insertelement <8 x i32> %564, i32 %559, i32 1 - %566 = insertelement <8 x i32> %565, i32 %560, i32 2 - %567 = insertelement <8 x i32> %566, i32 %561, i32 3 - %568 = insertelement <8 x i32> %567, i32 %562, i32 4 - %569 = insertelement <8 x i32> %568, i32 %563, i32 5 - %570 = insertelement <8 x i32> %569, i32 undef, i32 6 - %571 = insertelement <8 x i32> %570, i32 undef, i32 7 - %572 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %571, <32 x i8> %74, <16 x i8> %76, i32 2) - %573 = extractelement <4 x float> %572, i32 0 - %574 = extractelement <4 x float> %572, i32 1 - %575 = extractelement <4 x float> %572, i32 2 - %576 = fmul float %573, %44 - %577 = fadd float %576, %553 - %578 = fmul float %574, %45 - %579 = fadd float %578, %555 - %580 = fmul float %575, %46 - %581 = fadd float %580, %557 - %582 = call i32 @llvm.SI.packf16(float %577, float %579) - %583 = bitcast i32 %582 to float - %584 = call i32 @llvm.SI.packf16(float %581, float %283) - %585 = bitcast i32 %584 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %583, float %585, float %583, float %585) + %tmp263 = bitcast float %tmp135 to i32 + %tmp264 = bitcast float %tmp181 to i32 + %tmp265 = bitcast float %tmp136 to i32 + %tmp266 = bitcast float %tmp182 to i32 + %tmp267 = bitcast float %temp28.1 to i32 + %tmp268 = bitcast float %temp29.1 to i32 + %tmp269 = insertelement <8 x i32> undef, i32 %tmp263, i32 0 + %tmp270 = insertelement <8 x i32> %tmp269, i32 %tmp264, i32 1 + %tmp271 = insertelement <8 x i32> %tmp270, i32 %tmp265, i32 2 + %tmp272 = insertelement <8 x i32> %tmp271, i32 %tmp266, i32 3 + %tmp273 = insertelement <8 x i32> %tmp272, i32 %tmp267, i32 4 + %tmp274 = insertelement <8 x i32> %tmp273, i32 %tmp268, i32 5 + %tmp275 = insertelement <8 x i32> %tmp274, i32 undef, i32 6 + %tmp276 = insertelement <8 x i32> %tmp275, i32 undef, i32 7 + %tmp67.bc = bitcast <16 x i8> %tmp67 to <4 x i32> + %tmp277 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp276, <8 x i32> %tmp65, <4 x i32> %tmp67.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp278 = extractelement <4 x float> %tmp277, i32 0 + %tmp279 = extractelement <4 x float> %tmp277, i32 1 + %tmp280 = extractelement <4 x float> %tmp277, i32 2 + %tmp281 = extractelement <4 x float> %tmp277, i32 3 + %tmp282 = fmul float %tmp281, %tmp46 + %tmp283 = bitcast float %tmp135 to i32 + %tmp284 = bitcast float %tmp181 to i32 + %tmp285 = bitcast float %tmp136 to i32 + %tmp286 = bitcast float %tmp182 to i32 + %tmp287 = bitcast float %temp28.1 to i32 + %tmp288 = bitcast float %temp29.1 to i32 + %tmp289 = insertelement <8 x i32> undef, i32 %tmp283, i32 0 + %tmp290 = insertelement <8 x i32> %tmp289, i32 %tmp284, i32 1 + %tmp291 = insertelement <8 x i32> %tmp290, i32 %tmp285, i32 2 + %tmp292 = insertelement <8 x i32> %tmp291, i32 %tmp286, i32 3 + %tmp293 = insertelement <8 x i32> %tmp292, i32 %tmp287, i32 4 + %tmp294 = insertelement <8 x i32> %tmp293, i32 %tmp288, i32 5 + %tmp295 = insertelement <8 x i32> %tmp294, i32 undef, i32 6 + %tmp296 = insertelement <8 x i32> %tmp295, i32 undef, i32 7 + %tmp83.bc = bitcast <16 x i8> %tmp83 to <4 x i32> + %tmp297 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp296, <8 x i32> %tmp81, <4 x i32> %tmp83.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp298 = extractelement <4 x float> %tmp297, i32 0 + %tmp299 = extractelement <4 x float> %tmp297, i32 1 + %tmp300 = extractelement <4 x float> %tmp297, i32 2 + %tmp301 = bitcast float %tmp135 to i32 + %tmp302 = bitcast float %tmp181 to i32 + %tmp303 = bitcast float %tmp136 to i32 + %tmp304 = bitcast float %tmp182 to i32 + %tmp305 = bitcast float %temp28.1 to i32 + %tmp306 = bitcast float %temp29.1 to i32 + %tmp307 = insertelement <8 x i32> undef, i32 %tmp301, i32 0 + %tmp308 = insertelement <8 x i32> %tmp307, i32 %tmp302, i32 1 + %tmp309 = insertelement <8 x i32> %tmp308, i32 %tmp303, i32 2 + %tmp310 = insertelement <8 x i32> %tmp309, i32 %tmp304, i32 3 + %tmp311 = insertelement <8 x i32> %tmp310, i32 %tmp305, i32 4 + %tmp312 = insertelement <8 x i32> %tmp311, i32 %tmp306, i32 5 + %tmp313 = insertelement <8 x i32> %tmp312, i32 undef, i32 6 + %tmp314 = insertelement <8 x i32> %tmp313, i32 undef, i32 7 + %tmp79.bc = bitcast <16 x i8> %tmp79 to <4 x i32> + %tmp315 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp314, <8 x i32> %tmp77, <4 x i32> %tmp79.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp316 = extractelement <4 x float> %tmp315, i32 0 + %tmp317 = extractelement <4 x float> %tmp315, i32 1 + %tmp318 = extractelement <4 x float> %tmp315, i32 2 + %tmp319 = fmul float %tmp316, %tmp22 + %tmp320 = fmul float %tmp317, %tmp23 + %tmp321 = fmul float %tmp318, %tmp24 + %tmp322 = fmul float %tmp298, %tmp25 + %tmp323 = fadd float %tmp322, %tmp319 + %tmp324 = fmul float %tmp299, %tmp26 + %tmp325 = fadd float %tmp324, %tmp320 + %tmp326 = fmul float %tmp300, %tmp27 + %tmp327 = fadd float %tmp326, %tmp321 + %tmp328 = fadd float %tmp278, %tmp323 + %tmp329 = fadd float %tmp279, %tmp325 + %tmp330 = fadd float %tmp280, %tmp327 + %tmp331 = bitcast float %tmp135 to i32 + %tmp332 = bitcast float %tmp181 to i32 + %tmp333 = bitcast float %tmp136 to i32 + %tmp334 = bitcast float %tmp182 to i32 + %tmp335 = bitcast float %temp28.1 to i32 + %tmp336 = bitcast float %temp29.1 to i32 + %tmp337 = insertelement <8 x i32> undef, i32 %tmp331, i32 0 + %tmp338 = insertelement <8 x i32> %tmp337, i32 %tmp332, i32 1 + %tmp339 = insertelement <8 x i32> %tmp338, i32 %tmp333, i32 2 + %tmp340 = insertelement <8 x i32> %tmp339, i32 %tmp334, i32 3 + %tmp341 = insertelement <8 x i32> %tmp340, i32 %tmp335, i32 4 + %tmp342 = insertelement <8 x i32> %tmp341, i32 %tmp336, i32 5 + %tmp343 = insertelement <8 x i32> %tmp342, i32 undef, i32 6 + %tmp344 = insertelement <8 x i32> %tmp343, i32 undef, i32 7 + %tmp345 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp344, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp346 = extractelement <4 x float> %tmp345, i32 0 + %tmp347 = extractelement <4 x float> %tmp345, i32 1 + %tmp348 = extractelement <4 x float> %tmp345, i32 2 + %tmp349 = fadd float %tmp346, -5.000000e-01 + %tmp350 = fadd float %tmp347, -5.000000e-01 + %tmp351 = fadd float %tmp348, -5.000000e-01 + %tmp352 = fmul float %tmp349, %tmp349 + %tmp353 = fmul float %tmp350, %tmp350 + %tmp354 = fadd float %tmp353, %tmp352 + %tmp355 = fmul float %tmp351, %tmp351 + %tmp356 = fadd float %tmp354, %tmp355 + %tmp357 = call float @llvm.amdgcn.rsq.f32(float %tmp356) + %tmp358 = fmul float %tmp349, %tmp357 + %tmp359 = fmul float %tmp350, %tmp357 + %tmp360 = fmul float %tmp351, %tmp357 + %tmp361 = bitcast float %tmp135 to i32 + %tmp362 = bitcast float %tmp181 to i32 + %tmp363 = bitcast float %tmp136 to i32 + %tmp364 = bitcast float %tmp182 to i32 + %tmp365 = bitcast float %temp28.1 to i32 + %tmp366 = bitcast float %temp29.1 to i32 + %tmp367 = insertelement <8 x i32> undef, i32 %tmp361, i32 0 + %tmp368 = insertelement <8 x i32> %tmp367, i32 %tmp362, i32 1 + %tmp369 = insertelement <8 x i32> %tmp368, i32 %tmp363, i32 2 + %tmp370 = insertelement <8 x i32> %tmp369, i32 %tmp364, i32 3 + %tmp371 = insertelement <8 x i32> %tmp370, i32 %tmp365, i32 4 + %tmp372 = insertelement <8 x i32> %tmp371, i32 %tmp366, i32 5 + %tmp373 = insertelement <8 x i32> %tmp372, i32 undef, i32 6 + %tmp374 = insertelement <8 x i32> %tmp373, i32 undef, i32 7 + %tmp71.bc = bitcast <16 x i8> %tmp71 to <4 x i32> + %tmp375 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp374, <8 x i32> %tmp69, <4 x i32> %tmp71.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp376 = extractelement <4 x float> %tmp375, i32 0 + %tmp377 = extractelement <4 x float> %tmp375, i32 1 + %tmp378 = extractelement <4 x float> %tmp375, i32 2 + %tmp379 = extractelement <4 x float> %tmp375, i32 3 + %tmp380 = fsub float -0.000000e+00, %tmp94 + %tmp381 = fsub float -0.000000e+00, %tmp95 + %tmp382 = fsub float -0.000000e+00, %tmp96 + %tmp383 = fmul float %tmp358, %tmp380 + %tmp384 = fmul float %tmp359, %tmp381 + %tmp385 = fadd float %tmp384, %tmp383 + %tmp386 = fmul float %tmp360, %tmp382 + %tmp387 = fadd float %tmp385, %tmp386 + %tmp388 = fmul float %tmp387, %tmp358 + %tmp389 = fmul float %tmp387, %tmp359 + %tmp390 = fmul float %tmp387, %tmp360 + %tmp391 = fmul float 2.000000e+00, %tmp388 + %tmp392 = fmul float 2.000000e+00, %tmp389 + %tmp393 = fmul float 2.000000e+00, %tmp390 + %tmp394 = fsub float -0.000000e+00, %tmp391 + %tmp395 = fadd float %tmp380, %tmp394 + %tmp396 = fsub float -0.000000e+00, %tmp392 + %tmp397 = fadd float %tmp381, %tmp396 + %tmp398 = fsub float -0.000000e+00, %tmp393 + %tmp399 = fadd float %tmp382, %tmp398 + %tmp400 = fmul float %tmp395, %tmp97 + %tmp401 = fmul float %tmp395, %tmp98 + %tmp402 = fmul float %tmp395, %tmp99 + %tmp403 = fmul float %tmp397, %tmp100 + %tmp404 = fadd float %tmp403, %tmp400 + %tmp405 = fmul float %tmp397, %tmp101 + %tmp406 = fadd float %tmp405, %tmp401 + %tmp407 = fmul float %tmp397, %tmp102 + %tmp408 = fadd float %tmp407, %tmp402 + %tmp409 = fmul float %tmp399, %tmp103 + %tmp410 = fadd float %tmp409, %tmp404 + %tmp411 = fmul float %tmp399, %tmp104 + %tmp412 = fadd float %tmp411, %tmp406 + %tmp413 = fmul float %tmp399, %tmp105 + %tmp414 = fadd float %tmp413, %tmp408 + %tmp415 = bitcast float %tmp135 to i32 + %tmp416 = bitcast float %tmp181 to i32 + %tmp417 = bitcast float %tmp136 to i32 + %tmp418 = bitcast float %tmp182 to i32 + %tmp419 = bitcast float %temp28.1 to i32 + %tmp420 = bitcast float %temp29.1 to i32 + %tmp421 = insertelement <8 x i32> undef, i32 %tmp415, i32 0 + %tmp422 = insertelement <8 x i32> %tmp421, i32 %tmp416, i32 1 + %tmp423 = insertelement <8 x i32> %tmp422, i32 %tmp417, i32 2 + %tmp424 = insertelement <8 x i32> %tmp423, i32 %tmp418, i32 3 + %tmp425 = insertelement <8 x i32> %tmp424, i32 %tmp419, i32 4 + %tmp426 = insertelement <8 x i32> %tmp425, i32 %tmp420, i32 5 + %tmp427 = insertelement <8 x i32> %tmp426, i32 undef, i32 6 + %tmp428 = insertelement <8 x i32> %tmp427, i32 undef, i32 7 + %tmp87.bc = bitcast <16 x i8> %tmp87 to <4 x i32> + %tmp429 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp428, <8 x i32> %tmp85, <4 x i32> %tmp87.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp430 = extractelement <4 x float> %tmp429, i32 0 + %tmp431 = extractelement <4 x float> %tmp429, i32 1 + %tmp432 = extractelement <4 x float> %tmp429, i32 2 + %tmp433 = fmul float %tmp47, %tmp410 + %tmp434 = fmul float %tmp48, %tmp410 + %tmp435 = fmul float %tmp49, %tmp410 + %tmp436 = fmul float %tmp50, %tmp412 + %tmp437 = fadd float %tmp436, %tmp433 + %tmp438 = fmul float %tmp51, %tmp412 + %tmp439 = fadd float %tmp438, %tmp434 + %tmp440 = fmul float %tmp52, %tmp412 + %tmp441 = fadd float %tmp440, %tmp435 + %tmp442 = fmul float %tmp53, %tmp414 + %tmp443 = fadd float %tmp442, %tmp437 + %tmp444 = fmul float %tmp54, %tmp414 + %tmp445 = fadd float %tmp444, %tmp439 + %tmp446 = fmul float %tmp55, %tmp414 + %tmp447 = fadd float %tmp446, %tmp441 + %tmp448 = insertelement <4 x float> undef, float %tmp443, i32 0 + %tmp449 = insertelement <4 x float> %tmp448, float %tmp445, i32 1 + %tmp450 = insertelement <4 x float> %tmp449, float %tmp447, i32 2 + %tmp451 = insertelement <4 x float> %tmp450, float %tmp194, i32 3 + %tmp452 = call <4 x float> @llvm.AMDGPU.cube(<4 x float> %tmp451) + %tmp453 = extractelement <4 x float> %tmp452, i32 0 + %tmp454 = extractelement <4 x float> %tmp452, i32 1 + %tmp455 = extractelement <4 x float> %tmp452, i32 2 + %tmp456 = extractelement <4 x float> %tmp452, i32 3 + %tmp457 = call float @fabs(float %tmp455) + %tmp458 = fdiv float 1.000000e+00, %tmp457 + %tmp459 = fmul float %tmp453, %tmp458 + %tmp460 = fadd float %tmp459, 1.500000e+00 + %tmp461 = fmul float %tmp454, %tmp458 + %tmp462 = fadd float %tmp461, 1.500000e+00 + %tmp463 = bitcast float %tmp462 to i32 + %tmp464 = bitcast float %tmp460 to i32 + %tmp465 = bitcast float %tmp456 to i32 + %tmp466 = insertelement <4 x i32> undef, i32 %tmp463, i32 0 + %tmp467 = insertelement <4 x i32> %tmp466, i32 %tmp464, i32 1 + %tmp468 = insertelement <4 x i32> %tmp467, i32 %tmp465, i32 2 + %tmp469 = insertelement <4 x i32> %tmp468, i32 undef, i32 3 + %tmp91.bc = bitcast <16 x i8> %tmp91 to <4 x i32> + %tmp470 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tmp469, <8 x i32> %tmp89, <4 x i32> %tmp91.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp471 = extractelement <4 x float> %tmp470, i32 0 + %tmp472 = extractelement <4 x float> %tmp470, i32 1 + %tmp473 = extractelement <4 x float> %tmp470, i32 2 + %tmp474 = fmul float %tmp430, %tmp471 + %tmp475 = fadd float %tmp474, %tmp328 + %tmp476 = fmul float %tmp431, %tmp472 + %tmp477 = fadd float %tmp476, %tmp329 + %tmp478 = fmul float %tmp432, %tmp473 + %tmp479 = fadd float %tmp478, %tmp330 + %tmp480 = fmul float %tmp106, %tmp106 + %tmp481 = fmul float %tmp107, %tmp107 + %tmp482 = fadd float %tmp481, %tmp480 + %tmp483 = fmul float %tmp108, %tmp108 + %tmp484 = fadd float %tmp482, %tmp483 + %tmp485 = call float @llvm.amdgcn.rsq.f32(float %tmp484) + %tmp486 = fmul float %tmp106, %tmp485 + %tmp487 = fmul float %tmp107, %tmp485 + %tmp488 = fmul float %tmp108, %tmp485 + %tmp489 = fmul float %tmp376, %tmp39 + %tmp490 = fmul float %tmp377, %tmp40 + %tmp491 = fmul float %tmp378, %tmp41 + %tmp492 = fmul float %tmp358, %tmp486 + %tmp493 = fmul float %tmp359, %tmp487 + %tmp494 = fadd float %tmp493, %tmp492 + %tmp495 = fmul float %tmp360, %tmp488 + %tmp496 = fadd float %tmp494, %tmp495 + %tmp497 = fmul float %tmp496, %tmp358 + %tmp498 = fmul float %tmp496, %tmp359 + %tmp499 = fmul float %tmp496, %tmp360 + %tmp500 = fmul float 2.000000e+00, %tmp497 + %tmp501 = fmul float 2.000000e+00, %tmp498 + %tmp502 = fmul float 2.000000e+00, %tmp499 + %tmp503 = fsub float -0.000000e+00, %tmp500 + %tmp504 = fadd float %tmp486, %tmp503 + %tmp505 = fsub float -0.000000e+00, %tmp501 + %tmp506 = fadd float %tmp487, %tmp505 + %tmp507 = fsub float -0.000000e+00, %tmp502 + %tmp508 = fadd float %tmp488, %tmp507 + %tmp509 = fmul float %tmp94, %tmp94 + %tmp510 = fmul float %tmp95, %tmp95 + %tmp511 = fadd float %tmp510, %tmp509 + %tmp512 = fmul float %tmp96, %tmp96 + %tmp513 = fadd float %tmp511, %tmp512 + %tmp514 = call float @llvm.amdgcn.rsq.f32(float %tmp513) + %tmp515 = fmul float %tmp94, %tmp514 + %tmp516 = fmul float %tmp95, %tmp514 + %tmp517 = fmul float %tmp96, %tmp514 + %tmp518 = fmul float %tmp504, %tmp515 + %tmp519 = fmul float %tmp506, %tmp516 + %tmp520 = fadd float %tmp519, %tmp518 + %tmp521 = fmul float %tmp508, %tmp517 + %tmp522 = fadd float %tmp520, %tmp521 + %tmp523 = fsub float -0.000000e+00, %tmp522 + %tmp524 = fcmp uge float %tmp523, 0.000000e+00 + %tmp525 = select i1 %tmp524, float %tmp523, float 0.000000e+00 + %tmp526 = fmul float %tmp42, %tmp379 + %tmp527 = fadd float %tmp526, 1.000000e+00 + %tmp528 = call float @llvm.pow.f32(float %tmp525, float %tmp527) + %tmp529 = fmul float %tmp475, %tmp36 + %tmp530 = fmul float %tmp477, %tmp37 + %tmp531 = fmul float %tmp479, %tmp38 + %tmp532 = fmul float %tmp358, %tmp486 + %tmp533 = fmul float %tmp359, %tmp487 + %tmp534 = fadd float %tmp533, %tmp532 + %tmp535 = fmul float %tmp360, %tmp488 + %tmp536 = fadd float %tmp534, %tmp535 + %tmp537 = fcmp uge float %tmp536, 0.000000e+00 + %tmp538 = select i1 %tmp537, float %tmp536, float 0.000000e+00 + %tmp539 = fmul float %tmp529, %tmp538 + %tmp540 = fmul float %tmp530, %tmp538 + %tmp541 = fmul float %tmp531, %tmp538 + %tmp542 = fmul float %tmp489, %tmp528 + %tmp543 = fadd float %tmp542, %tmp539 + %tmp544 = fmul float %tmp490, %tmp528 + %tmp545 = fadd float %tmp544, %tmp540 + %tmp546 = fmul float %tmp491, %tmp528 + %tmp547 = fadd float %tmp546, %tmp541 + %tmp548 = fmul float %tmp475, %tmp33 + %tmp549 = fmul float %tmp477, %tmp34 + %tmp550 = fmul float %tmp479, %tmp35 + %tmp551 = fmul float %tmp543, %tmp56 + %tmp552 = fadd float %tmp551, %tmp548 + %tmp553 = fmul float %tmp545, %tmp57 + %tmp554 = fadd float %tmp553, %tmp549 + %tmp555 = fmul float %tmp547, %tmp58 + %tmp556 = fadd float %tmp555, %tmp550 + %tmp557 = bitcast float %tmp135 to i32 + %tmp558 = bitcast float %tmp181 to i32 + %tmp559 = bitcast float %tmp136 to i32 + %tmp560 = bitcast float %tmp182 to i32 + %tmp561 = bitcast float %temp28.1 to i32 + %tmp562 = bitcast float %temp29.1 to i32 + %tmp563 = insertelement <8 x i32> undef, i32 %tmp557, i32 0 + %tmp564 = insertelement <8 x i32> %tmp563, i32 %tmp558, i32 1 + %tmp565 = insertelement <8 x i32> %tmp564, i32 %tmp559, i32 2 + %tmp566 = insertelement <8 x i32> %tmp565, i32 %tmp560, i32 3 + %tmp567 = insertelement <8 x i32> %tmp566, i32 %tmp561, i32 4 + %tmp568 = insertelement <8 x i32> %tmp567, i32 %tmp562, i32 5 + %tmp569 = insertelement <8 x i32> %tmp568, i32 undef, i32 6 + %tmp570 = insertelement <8 x i32> %tmp569, i32 undef, i32 7 + %tmp75.bc = bitcast <16 x i8> %tmp75 to <4 x i32> + %tmp571 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp570, <8 x i32> %tmp73, <4 x i32> %tmp75.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp572 = extractelement <4 x float> %tmp571, i32 0 + %tmp573 = extractelement <4 x float> %tmp571, i32 1 + %tmp574 = extractelement <4 x float> %tmp571, i32 2 + %tmp575 = fmul float %tmp572, %tmp43 + %tmp576 = fadd float %tmp575, %tmp552 + %tmp577 = fmul float %tmp573, %tmp44 + %tmp578 = fadd float %tmp577, %tmp554 + %tmp579 = fmul float %tmp574, %tmp45 + %tmp580 = fadd float %tmp579, %tmp556 + %tmp581 = call i32 @llvm.SI.packf16(float %tmp576, float %tmp578) + %tmp582 = bitcast i32 %tmp581 to float + %tmp583 = call i32 @llvm.SI.packf16(float %tmp580, float %tmp282) + %tmp584 = bitcast i32 %tmp583 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp582, float %tmp584, float %tmp582, float %tmp584) ret void ENDIF66: ; preds = %LOOP65 - %586 = bitcast float %temp28.1 to i32 - %587 = bitcast float %temp29.1 to i32 - %588 = insertelement <8 x i32> %237, i32 %586, i32 4 - %589 = insertelement <8 x i32> %588, i32 %587, i32 5 - %590 = insertelement <8 x i32> %589, i32 undef, i32 6 - %591 = insertelement <8 x i32> %590, i32 undef, i32 7 - %592 = call <4 x float> @llvm.SI.sampled.v8i32(<8 x i32> %591, <32 x i8> %62, <16 x i8> %64, i32 2) - %593 = extractelement <4 x float> %592, i32 3 - %594 = fcmp oge float %temp30.1, %593 - %595 = sext i1 %594 to i32 - %596 = bitcast i32 %595 to float - %597 = bitcast float %596 to i32 - %598 = and i32 %597, 1065353216 - %599 = bitcast i32 %598 to float - %600 = fmul float 5.000000e-01, %temp32.0 - %601 = fsub float -0.000000e+00, %600 - %602 = fmul float %599, %temp32.0 - %603 = fadd float %602, %601 - %604 = fmul float %214, %603 - %605 = fadd float %604, %temp28.1 - %606 = fmul float %215, %603 - %607 = fadd float %606, %temp29.1 - %608 = fmul float %216, %603 - %609 = fadd float %608, %temp30.1 - %610 = fadd float %temp24.1, 1.000000e+00 - %611 = fmul float %temp32.0, 5.000000e-01 + %tmp585 = bitcast float %temp28.1 to i32 + %tmp586 = bitcast float %temp29.1 to i32 + %tmp587 = insertelement <8 x i32> %tmp236, i32 %tmp585, i32 4 + %tmp588 = insertelement <8 x i32> %tmp587, i32 %tmp586, i32 5 + %tmp589 = insertelement <8 x i32> %tmp588, i32 undef, i32 6 + %tmp590 = insertelement <8 x i32> %tmp589, i32 undef, i32 7 + %tmp591 = call <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32> %tmp590, <8 x i32> %tmp61, <4 x i32> %tmp63.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp592 = extractelement <4 x float> %tmp591, i32 3 + %tmp593 = fcmp oge float %temp30.1, %tmp592 + %tmp594 = sext i1 %tmp593 to i32 + %tmp595 = bitcast i32 %tmp594 to float + %tmp596 = bitcast float %tmp595 to i32 + %tmp597 = and i32 %tmp596, 1065353216 + %tmp598 = bitcast i32 %tmp597 to float + %tmp599 = fmul float 5.000000e-01, %temp32.0 + %tmp600 = fsub float -0.000000e+00, %tmp599 + %tmp601 = fmul float %tmp598, %temp32.0 + %tmp602 = fadd float %tmp601, %tmp600 + %tmp603 = fmul float %tmp213, %tmp602 + %tmp604 = fadd float %tmp603, %temp28.1 + %tmp605 = fmul float %tmp214, %tmp602 + %tmp606 = fadd float %tmp605, %temp29.1 + %tmp607 = fmul float %tmp215, %tmp602 + %tmp608 = fadd float %tmp607, %temp30.1 + %tmp609 = fadd float %temp24.1, 1.000000e+00 + %tmp610 = fmul float %temp32.0, 5.000000e-01 br label %LOOP65 } -; Function Attrs: nounwind readnone -declare float @llvm.SI.load.const(<16 x i8>, i32) #1 - -; Function Attrs: nounwind readnone -declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1 - -; Function Attrs: readnone -declare i32 @llvm.SI.tid() #2 - -; Function Attrs: readonly -declare float @ceil(float) #3 - -; Function Attrs: readnone -declare float @llvm.AMDGPU.rsq.f32(float) #2 - -; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sampled.v8i32(<8 x i32>, <32 x i8>, <16 x i8>, i32) #1 - -; Function Attrs: readnone -declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #2 - -; Function Attrs: readnone -declare float @fabs(float) #2 - -; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 - -; Function Attrs: nounwind readonly -declare float @llvm.pow.f32(float, float) #4 - -; Function Attrs: nounwind readnone -declare i32 @llvm.SI.packf16(float, float) #1 - -declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) - -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } -attributes #2 = { readnone } -attributes #3 = { readonly } -attributes #4 = { nounwind readonly } - -!0 = !{!"const", null, i32 1} - ; CHECK-LABEL: {{^}}main1: ; CHECK: s_endpgm -define void @main1([17 x <16 x i8>] addrspace(2)* byval, [32 x <16 x i8>] addrspace(2)* byval, [16 x <32 x i8>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @main1([17 x <16 x i8>] addrspace(2)* byval %arg, [32 x <16 x i8>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { main_body: - %21 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i32 0 - %22 = load <16 x i8>, <16 x i8> addrspace(2)* %21, !tbaa !0 - %23 = call float @llvm.SI.load.const(<16 x i8> %22, i32 0) - %24 = call float @llvm.SI.load.const(<16 x i8> %22, i32 4) - %25 = call float @llvm.SI.load.const(<16 x i8> %22, i32 8) - %26 = call float @llvm.SI.load.const(<16 x i8> %22, i32 12) - %27 = call float @llvm.SI.load.const(<16 x i8> %22, i32 28) - %28 = call float @llvm.SI.load.const(<16 x i8> %22, i32 48) - %29 = call float @llvm.SI.load.const(<16 x i8> %22, i32 52) - %30 = call float @llvm.SI.load.const(<16 x i8> %22, i32 56) - %31 = call float @llvm.SI.load.const(<16 x i8> %22, i32 64) - %32 = call float @llvm.SI.load.const(<16 x i8> %22, i32 68) - %33 = call float @llvm.SI.load.const(<16 x i8> %22, i32 72) - %34 = call float @llvm.SI.load.const(<16 x i8> %22, i32 76) - %35 = call float @llvm.SI.load.const(<16 x i8> %22, i32 128) - %36 = call float @llvm.SI.load.const(<16 x i8> %22, i32 132) - %37 = call float @llvm.SI.load.const(<16 x i8> %22, i32 144) - %38 = call float @llvm.SI.load.const(<16 x i8> %22, i32 148) - %39 = call float @llvm.SI.load.const(<16 x i8> %22, i32 152) - %40 = call float @llvm.SI.load.const(<16 x i8> %22, i32 160) - %41 = call float @llvm.SI.load.const(<16 x i8> %22, i32 164) - %42 = call float @llvm.SI.load.const(<16 x i8> %22, i32 168) - %43 = call float @llvm.SI.load.const(<16 x i8> %22, i32 172) - %44 = call float @llvm.SI.load.const(<16 x i8> %22, i32 176) - %45 = call float @llvm.SI.load.const(<16 x i8> %22, i32 180) - %46 = call float @llvm.SI.load.const(<16 x i8> %22, i32 184) - %47 = call float @llvm.SI.load.const(<16 x i8> %22, i32 192) - %48 = call float @llvm.SI.load.const(<16 x i8> %22, i32 196) - %49 = call float @llvm.SI.load.const(<16 x i8> %22, i32 200) - %50 = call float @llvm.SI.load.const(<16 x i8> %22, i32 208) - %51 = call float @llvm.SI.load.const(<16 x i8> %22, i32 212) - %52 = call float @llvm.SI.load.const(<16 x i8> %22, i32 216) - %53 = call float @llvm.SI.load.const(<16 x i8> %22, i32 220) - %54 = call float @llvm.SI.load.const(<16 x i8> %22, i32 236) - %55 = call float @llvm.SI.load.const(<16 x i8> %22, i32 240) - %56 = call float @llvm.SI.load.const(<16 x i8> %22, i32 244) - %57 = call float @llvm.SI.load.const(<16 x i8> %22, i32 248) - %58 = call float @llvm.SI.load.const(<16 x i8> %22, i32 252) - %59 = call float @llvm.SI.load.const(<16 x i8> %22, i32 256) - %60 = call float @llvm.SI.load.const(<16 x i8> %22, i32 260) - %61 = call float @llvm.SI.load.const(<16 x i8> %22, i32 264) - %62 = call float @llvm.SI.load.const(<16 x i8> %22, i32 268) - %63 = call float @llvm.SI.load.const(<16 x i8> %22, i32 272) - %64 = call float @llvm.SI.load.const(<16 x i8> %22, i32 276) - %65 = call float @llvm.SI.load.const(<16 x i8> %22, i32 280) - %66 = call float @llvm.SI.load.const(<16 x i8> %22, i32 284) - %67 = call float @llvm.SI.load.const(<16 x i8> %22, i32 288) - %68 = call float @llvm.SI.load.const(<16 x i8> %22, i32 292) - %69 = call float @llvm.SI.load.const(<16 x i8> %22, i32 464) - %70 = call float @llvm.SI.load.const(<16 x i8> %22, i32 468) - %71 = call float @llvm.SI.load.const(<16 x i8> %22, i32 472) - %72 = call float @llvm.SI.load.const(<16 x i8> %22, i32 496) - %73 = call float @llvm.SI.load.const(<16 x i8> %22, i32 500) - %74 = call float @llvm.SI.load.const(<16 x i8> %22, i32 504) - %75 = call float @llvm.SI.load.const(<16 x i8> %22, i32 512) - %76 = call float @llvm.SI.load.const(<16 x i8> %22, i32 516) - %77 = call float @llvm.SI.load.const(<16 x i8> %22, i32 524) - %78 = call float @llvm.SI.load.const(<16 x i8> %22, i32 532) - %79 = call float @llvm.SI.load.const(<16 x i8> %22, i32 536) - %80 = call float @llvm.SI.load.const(<16 x i8> %22, i32 540) - %81 = call float @llvm.SI.load.const(<16 x i8> %22, i32 544) - %82 = call float @llvm.SI.load.const(<16 x i8> %22, i32 548) - %83 = call float @llvm.SI.load.const(<16 x i8> %22, i32 552) - %84 = call float @llvm.SI.load.const(<16 x i8> %22, i32 556) - %85 = call float @llvm.SI.load.const(<16 x i8> %22, i32 560) - %86 = call float @llvm.SI.load.const(<16 x i8> %22, i32 564) - %87 = call float @llvm.SI.load.const(<16 x i8> %22, i32 568) - %88 = call float @llvm.SI.load.const(<16 x i8> %22, i32 572) - %89 = call float @llvm.SI.load.const(<16 x i8> %22, i32 576) - %90 = call float @llvm.SI.load.const(<16 x i8> %22, i32 580) - %91 = call float @llvm.SI.load.const(<16 x i8> %22, i32 584) - %92 = call float @llvm.SI.load.const(<16 x i8> %22, i32 588) - %93 = call float @llvm.SI.load.const(<16 x i8> %22, i32 592) - %94 = call float @llvm.SI.load.const(<16 x i8> %22, i32 596) - %95 = call float @llvm.SI.load.const(<16 x i8> %22, i32 600) - %96 = call float @llvm.SI.load.const(<16 x i8> %22, i32 604) - %97 = call float @llvm.SI.load.const(<16 x i8> %22, i32 608) - %98 = call float @llvm.SI.load.const(<16 x i8> %22, i32 612) - %99 = call float @llvm.SI.load.const(<16 x i8> %22, i32 616) - %100 = call float @llvm.SI.load.const(<16 x i8> %22, i32 624) - %101 = call float @llvm.SI.load.const(<16 x i8> %22, i32 628) - %102 = call float @llvm.SI.load.const(<16 x i8> %22, i32 632) - %103 = call float @llvm.SI.load.const(<16 x i8> %22, i32 636) - %104 = call float @llvm.SI.load.const(<16 x i8> %22, i32 640) - %105 = call float @llvm.SI.load.const(<16 x i8> %22, i32 644) - %106 = call float @llvm.SI.load.const(<16 x i8> %22, i32 648) - %107 = call float @llvm.SI.load.const(<16 x i8> %22, i32 652) - %108 = call float @llvm.SI.load.const(<16 x i8> %22, i32 656) - %109 = call float @llvm.SI.load.const(<16 x i8> %22, i32 660) - %110 = call float @llvm.SI.load.const(<16 x i8> %22, i32 664) - %111 = call float @llvm.SI.load.const(<16 x i8> %22, i32 668) - %112 = call float @llvm.SI.load.const(<16 x i8> %22, i32 672) - %113 = call float @llvm.SI.load.const(<16 x i8> %22, i32 676) - %114 = call float @llvm.SI.load.const(<16 x i8> %22, i32 680) - %115 = call float @llvm.SI.load.const(<16 x i8> %22, i32 684) - %116 = call float @llvm.SI.load.const(<16 x i8> %22, i32 688) - %117 = call float @llvm.SI.load.const(<16 x i8> %22, i32 692) - %118 = call float @llvm.SI.load.const(<16 x i8> %22, i32 696) - %119 = call float @llvm.SI.load.const(<16 x i8> %22, i32 700) - %120 = call float @llvm.SI.load.const(<16 x i8> %22, i32 704) - %121 = call float @llvm.SI.load.const(<16 x i8> %22, i32 708) - %122 = call float @llvm.SI.load.const(<16 x i8> %22, i32 712) - %123 = call float @llvm.SI.load.const(<16 x i8> %22, i32 716) - %124 = call float @llvm.SI.load.const(<16 x i8> %22, i32 864) - %125 = call float @llvm.SI.load.const(<16 x i8> %22, i32 868) - %126 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 0 - %127 = load <32 x i8>, <32 x i8> addrspace(2)* %126, !tbaa !0 - %128 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 0 - %129 = load <16 x i8>, <16 x i8> addrspace(2)* %128, !tbaa !0 - %130 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 1 - %131 = load <32 x i8>, <32 x i8> addrspace(2)* %130, !tbaa !0 - %132 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 1 - %133 = load <16 x i8>, <16 x i8> addrspace(2)* %132, !tbaa !0 - %134 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 2 - %135 = load <32 x i8>, <32 x i8> addrspace(2)* %134, !tbaa !0 - %136 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 2 - %137 = load <16 x i8>, <16 x i8> addrspace(2)* %136, !tbaa !0 - %138 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 3 - %139 = load <32 x i8>, <32 x i8> addrspace(2)* %138, !tbaa !0 - %140 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 3 - %141 = load <16 x i8>, <16 x i8> addrspace(2)* %140, !tbaa !0 - %142 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 4 - %143 = load <32 x i8>, <32 x i8> addrspace(2)* %142, !tbaa !0 - %144 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 4 - %145 = load <16 x i8>, <16 x i8> addrspace(2)* %144, !tbaa !0 - %146 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 5 - %147 = load <32 x i8>, <32 x i8> addrspace(2)* %146, !tbaa !0 - %148 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 5 - %149 = load <16 x i8>, <16 x i8> addrspace(2)* %148, !tbaa !0 - %150 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 6 - %151 = load <32 x i8>, <32 x i8> addrspace(2)* %150, !tbaa !0 - %152 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 6 - %153 = load <16 x i8>, <16 x i8> addrspace(2)* %152, !tbaa !0 - %154 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 7 - %155 = load <32 x i8>, <32 x i8> addrspace(2)* %154, !tbaa !0 - %156 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 7 - %157 = load <16 x i8>, <16 x i8> addrspace(2)* %156, !tbaa !0 - %158 = getelementptr [16 x <32 x i8>], [16 x <32 x i8>] addrspace(2)* %2, i64 0, i32 8 - %159 = load <32 x i8>, <32 x i8> addrspace(2)* %158, !tbaa !0 - %160 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %1, i64 0, i32 8 - %161 = load <16 x i8>, <16 x i8> addrspace(2)* %160, !tbaa !0 - %162 = fcmp ugt float %17, 0.000000e+00 - %163 = select i1 %162, float 1.000000e+00, float 0.000000e+00 - %164 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %4, <2 x i32> %6) - %165 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %4, <2 x i32> %6) - %166 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %4, <2 x i32> %6) - %167 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %4, <2 x i32> %6) - %168 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %4, <2 x i32> %6) - %169 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %4, <2 x i32> %6) - %170 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %4, <2 x i32> %6) - %171 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %4, <2 x i32> %6) - %172 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %4, <2 x i32> %6) - %173 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %4, <2 x i32> %6) - %174 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %4, <2 x i32> %6) - %175 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %4, <2 x i32> %6) - %176 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %4, <2 x i32> %6) - %177 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %4, <2 x i32> %6) - %178 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %4, <2 x i32> %6) - %179 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %4, <2 x i32> %6) - %180 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %4, <2 x i32> %6) - %181 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %4, <2 x i32> %6) - %182 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %4, <2 x i32> %6) - %183 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %4, <2 x i32> %6) - %184 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %4, <2 x i32> %6) - %185 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %4, <2 x i32> %6) - %186 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %4, <2 x i32> %6) - %187 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %4, <2 x i32> %6) - %188 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %4, <2 x i32> %6) - %189 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %4, <2 x i32> %6) - %190 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %4, <2 x i32> %6) - %191 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %4, <2 x i32> %6) - %192 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %4, <2 x i32> %6) - %193 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %4, <2 x i32> %6) - %194 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %4, <2 x i32> %6) - %195 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %4, <2 x i32> %6) - %196 = fmul float %14, %124 - %197 = fadd float %196, %125 - %198 = call float @llvm.AMDIL.clamp.(float %163, float 0.000000e+00, float 1.000000e+00) - %199 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) - %200 = call float @llvm.AMDIL.clamp.(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) - %201 = call float @llvm.AMDIL.clamp.(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) - %202 = bitcast float %198 to i32 - %203 = icmp ne i32 %202, 0 - %. = select i1 %203, float -1.000000e+00, float 1.000000e+00 - %204 = fsub float -0.000000e+00, %164 - %205 = fadd float %44, %204 - %206 = fsub float -0.000000e+00, %165 - %207 = fadd float %45, %206 - %208 = fsub float -0.000000e+00, %166 - %209 = fadd float %46, %208 - %210 = fmul float %205, %205 - %211 = fmul float %207, %207 - %212 = fadd float %211, %210 - %213 = fmul float %209, %209 - %214 = fadd float %212, %213 - %215 = call float @llvm.AMDGPU.rsq.f32(float %214) - %216 = fmul float %205, %215 - %217 = fmul float %207, %215 - %218 = fmul float %209, %215 - %219 = fmul float %., %54 - %220 = fmul float %13, %47 - %221 = fmul float %197, %48 - %222 = bitcast float %174 to i32 - %223 = bitcast float %175 to i32 - %224 = insertelement <2 x i32> undef, i32 %222, i32 0 - %225 = insertelement <2 x i32> %224, i32 %223, i32 1 - %226 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %225, <32 x i8> %131, <16 x i8> %133, i32 2) - %227 = extractelement <4 x float> %226, i32 0 - %228 = extractelement <4 x float> %226, i32 1 - %229 = extractelement <4 x float> %226, i32 2 - %230 = extractelement <4 x float> %226, i32 3 - %231 = fmul float %227, 0x4012611180000000 - %232 = fmul float %228, 0x4012611180000000 - %233 = fmul float %229, 0x4012611180000000 - %234 = call float @llvm.AMDGPU.lrp(float %27, float %231, float 1.000000e+00) - %235 = call float @llvm.AMDGPU.lrp(float %27, float %232, float 1.000000e+00) - %236 = call float @llvm.AMDGPU.lrp(float %27, float %233, float 1.000000e+00) - %237 = fmul float %216, %184 - %238 = fmul float %217, %185 - %239 = fadd float %238, %237 - %240 = fmul float %218, %186 - %241 = fadd float %239, %240 - %242 = fmul float %216, %187 - %243 = fmul float %217, %188 - %244 = fadd float %243, %242 - %245 = fmul float %218, %189 - %246 = fadd float %244, %245 - %247 = fmul float %216, %190 - %248 = fmul float %217, %191 - %249 = fadd float %248, %247 - %250 = fmul float %218, %192 - %251 = fadd float %249, %250 - %252 = call float @llvm.AMDIL.clamp.(float %251, float 0.000000e+00, float 1.000000e+00) - %253 = fmul float %214, 0x3F5A36E2E0000000 - %254 = call float @llvm.AMDIL.clamp.(float %253, float 0.000000e+00, float 1.000000e+00) - %255 = fsub float -0.000000e+00, %254 - %256 = fadd float 1.000000e+00, %255 - %257 = call float @llvm.pow.f32(float %252, float 2.500000e-01) - %258 = fmul float %39, %257 - %259 = fmul float %241, %258 - %260 = fmul float %246, %258 - %261 = fmul float %259, %230 - %262 = fmul float %260, %230 - %263 = fadd float %252, 0x3EE4F8B580000000 - %264 = fsub float -0.000000e+00, %252 - %265 = fadd float 1.000000e+00, %264 - %266 = fmul float 1.200000e+01, %265 - %267 = fadd float %266, 4.000000e+00 - %268 = fsub float -0.000000e+00, %267 - %269 = fmul float %268, %263 - %270 = fsub float -0.000000e+00, %267 - %271 = fmul float %270, %263 - %272 = fsub float -0.000000e+00, %267 - %273 = fmul float %272, %263 - %274 = fdiv float 1.000000e+00, %269 - %275 = fdiv float 1.000000e+00, %271 - %276 = fdiv float 1.000000e+00, %273 - %277 = fmul float %261, %274 - %278 = fmul float %262, %275 - %279 = fmul float %263, %276 + %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg, i64 0, i32 0 + %tmp21 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 0) + %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 4) + %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 8) + %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 12) + %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 28) + %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 48) + %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 52) + %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 56) + %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 64) + %tmp31 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 68) + %tmp32 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 72) + %tmp33 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 76) + %tmp34 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 128) + %tmp35 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 132) + %tmp36 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 144) + %tmp37 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 148) + %tmp38 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 152) + %tmp39 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 160) + %tmp40 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 164) + %tmp41 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 168) + %tmp42 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 172) + %tmp43 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 176) + %tmp44 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 180) + %tmp45 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 184) + %tmp46 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 192) + %tmp47 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 196) + %tmp48 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 200) + %tmp49 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 208) + %tmp50 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 212) + %tmp51 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 216) + %tmp52 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 220) + %tmp53 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 236) + %tmp54 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 240) + %tmp55 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 244) + %tmp56 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 248) + %tmp57 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 252) + %tmp58 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 256) + %tmp59 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 260) + %tmp60 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 264) + %tmp61 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 268) + %tmp62 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 272) + %tmp63 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 276) + %tmp64 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 280) + %tmp65 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 284) + %tmp66 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 288) + %tmp67 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 292) + %tmp68 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 464) + %tmp69 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 468) + %tmp70 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 472) + %tmp71 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 496) + %tmp72 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 500) + %tmp73 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 504) + %tmp74 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 512) + %tmp75 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 516) + %tmp76 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 524) + %tmp77 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 532) + %tmp78 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 536) + %tmp79 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 540) + %tmp80 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 544) + %tmp81 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 548) + %tmp82 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 552) + %tmp83 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 556) + %tmp84 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 560) + %tmp85 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 564) + %tmp86 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 568) + %tmp87 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 572) + %tmp88 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 576) + %tmp89 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 580) + %tmp90 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 584) + %tmp91 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 588) + %tmp92 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 592) + %tmp93 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 596) + %tmp94 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 600) + %tmp95 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 604) + %tmp96 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 608) + %tmp97 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 612) + %tmp98 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 616) + %tmp99 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 624) + %tmp100 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 628) + %tmp101 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 632) + %tmp102 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 636) + %tmp103 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 640) + %tmp104 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 644) + %tmp105 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 648) + %tmp106 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 652) + %tmp107 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 656) + %tmp108 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 660) + %tmp109 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 664) + %tmp110 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 668) + %tmp111 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 672) + %tmp112 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 676) + %tmp113 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 680) + %tmp114 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 684) + %tmp115 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 688) + %tmp116 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 692) + %tmp117 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 696) + %tmp118 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 700) + %tmp119 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 704) + %tmp120 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 708) + %tmp121 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 712) + %tmp122 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 716) + %tmp123 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 864) + %tmp124 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 868) + %tmp125 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 + %tmp126 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp125, !tbaa !0 + %tmp127 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 0 + %tmp128 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp127, !tbaa !0 + %tmp129 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 1 + %tmp130 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp129, !tbaa !0 + %tmp131 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 1 + %tmp132 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp131, !tbaa !0 + %tmp133 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 2 + %tmp134 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp133, !tbaa !0 + %tmp135 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 2 + %tmp136 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp135, !tbaa !0 + %tmp137 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 3 + %tmp138 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp137, !tbaa !0 + %tmp139 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 3 + %tmp140 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp139, !tbaa !0 + %tmp141 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 4 + %tmp142 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp141, !tbaa !0 + %tmp143 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 4 + %tmp144 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp143, !tbaa !0 + %tmp145 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 5 + %tmp146 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp145, !tbaa !0 + %tmp147 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 5 + %tmp148 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp147, !tbaa !0 + %tmp149 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 6 + %tmp150 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp149, !tbaa !0 + %tmp151 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 6 + %tmp152 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp151, !tbaa !0 + %tmp153 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 7 + %tmp154 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp153, !tbaa !0 + %tmp155 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 7 + %tmp156 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp155, !tbaa !0 + %tmp157 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 8 + %tmp158 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp157, !tbaa !0 + %tmp159 = getelementptr [32 x <16 x i8>], [32 x <16 x i8>] addrspace(2)* %arg1, i64 0, i32 8 + %tmp160 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp159, !tbaa !0 + %tmp161 = fcmp ugt float %arg17, 0.000000e+00 + %tmp162 = select i1 %tmp161, float 1.000000e+00, float 0.000000e+00 + %tmp163 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp164 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp165 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp166 = call float @llvm.SI.fs.interp(i32 3, i32 0, i32 %arg4, <2 x i32> %arg6) + %tmp167 = call float @llvm.SI.fs.interp(i32 0, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp168 = call float @llvm.SI.fs.interp(i32 1, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp169 = call float @llvm.SI.fs.interp(i32 2, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp170 = call float @llvm.SI.fs.interp(i32 3, i32 1, i32 %arg4, <2 x i32> %arg6) + %tmp171 = call float @llvm.SI.fs.interp(i32 0, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp172 = call float @llvm.SI.fs.interp(i32 1, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp173 = call float @llvm.SI.fs.interp(i32 2, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp174 = call float @llvm.SI.fs.interp(i32 3, i32 2, i32 %arg4, <2 x i32> %arg6) + %tmp175 = call float @llvm.SI.fs.interp(i32 0, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp176 = call float @llvm.SI.fs.interp(i32 1, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp177 = call float @llvm.SI.fs.interp(i32 2, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp178 = call float @llvm.SI.fs.interp(i32 3, i32 3, i32 %arg4, <2 x i32> %arg6) + %tmp179 = call float @llvm.SI.fs.interp(i32 0, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp180 = call float @llvm.SI.fs.interp(i32 1, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp181 = call float @llvm.SI.fs.interp(i32 2, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp182 = call float @llvm.SI.fs.interp(i32 3, i32 4, i32 %arg4, <2 x i32> %arg6) + %tmp183 = call float @llvm.SI.fs.interp(i32 0, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp184 = call float @llvm.SI.fs.interp(i32 1, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp185 = call float @llvm.SI.fs.interp(i32 2, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp186 = call float @llvm.SI.fs.interp(i32 3, i32 5, i32 %arg4, <2 x i32> %arg6) + %tmp187 = call float @llvm.SI.fs.interp(i32 0, i32 6, i32 %arg4, <2 x i32> %arg6) + %tmp188 = call float @llvm.SI.fs.interp(i32 1, i32 6, i32 %arg4, <2 x i32> %arg6) + %tmp189 = call float @llvm.SI.fs.interp(i32 2, i32 6, i32 %arg4, <2 x i32> %arg6) + %tmp190 = call float @llvm.SI.fs.interp(i32 3, i32 6, i32 %arg4, <2 x i32> %arg6) + %tmp191 = call float @llvm.SI.fs.interp(i32 0, i32 7, i32 %arg4, <2 x i32> %arg6) + %tmp192 = call float @llvm.SI.fs.interp(i32 1, i32 7, i32 %arg4, <2 x i32> %arg6) + %tmp193 = call float @llvm.SI.fs.interp(i32 2, i32 7, i32 %arg4, <2 x i32> %arg6) + %tmp194 = call float @llvm.SI.fs.interp(i32 3, i32 7, i32 %arg4, <2 x i32> %arg6) + %tmp195 = fmul float %arg14, %tmp123 + %tmp196 = fadd float %tmp195, %tmp124 + %tmp197 = call float @llvm.AMDGPU.clamp.f32(float %tmp162, float 0.000000e+00, float 1.000000e+00) + %tmp198 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) + %tmp199 = call float @llvm.AMDGPU.clamp.f32(float 0.000000e+00, float 0.000000e+00, float 1.000000e+00) + %tmp200 = call float @llvm.AMDGPU.clamp.f32(float 1.000000e+00, float 0.000000e+00, float 1.000000e+00) + %tmp201 = bitcast float %tmp197 to i32 + %tmp202 = icmp ne i32 %tmp201, 0 + %. = select i1 %tmp202, float -1.000000e+00, float 1.000000e+00 + %tmp203 = fsub float -0.000000e+00, %tmp163 + %tmp204 = fadd float %tmp43, %tmp203 + %tmp205 = fsub float -0.000000e+00, %tmp164 + %tmp206 = fadd float %tmp44, %tmp205 + %tmp207 = fsub float -0.000000e+00, %tmp165 + %tmp208 = fadd float %tmp45, %tmp207 + %tmp209 = fmul float %tmp204, %tmp204 + %tmp210 = fmul float %tmp206, %tmp206 + %tmp211 = fadd float %tmp210, %tmp209 + %tmp212 = fmul float %tmp208, %tmp208 + %tmp213 = fadd float %tmp211, %tmp212 + %tmp214 = call float @llvm.amdgcn.rsq.f32(float %tmp213) + %tmp215 = fmul float %tmp204, %tmp214 + %tmp216 = fmul float %tmp206, %tmp214 + %tmp217 = fmul float %tmp208, %tmp214 + %tmp218 = fmul float %., %tmp53 + %tmp219 = fmul float %arg13, %tmp46 + %tmp220 = fmul float %tmp196, %tmp47 + %tmp221 = bitcast float %tmp173 to i32 + %tmp222 = bitcast float %tmp174 to i32 + %tmp223 = insertelement <2 x i32> undef, i32 %tmp221, i32 0 + %tmp224 = insertelement <2 x i32> %tmp223, i32 %tmp222, i32 1 + %tmp132.bc = bitcast <16 x i8> %tmp132 to <4 x i32> + %tmp225 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp224, <8 x i32> %tmp130, <4 x i32> %tmp132.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp226 = extractelement <4 x float> %tmp225, i32 0 + %tmp227 = extractelement <4 x float> %tmp225, i32 1 + %tmp228 = extractelement <4 x float> %tmp225, i32 2 + %tmp229 = extractelement <4 x float> %tmp225, i32 3 + %tmp230 = fmul float %tmp226, 0x4012611180000000 + %tmp231 = fmul float %tmp227, 0x4012611180000000 + %tmp232 = fmul float %tmp228, 0x4012611180000000 + %one.sub.a.i = fsub float 1.000000e+00, %tmp26 + %result.i = fadd float %tmp230, %one.sub.a.i + %one.sub.a.i43 = fsub float 1.000000e+00, %tmp26 + %result.i44 = fadd float %tmp231, %one.sub.a.i43 + %one.sub.a.i41 = fsub float 1.000000e+00, %tmp26 + %result.i42 = fadd float %tmp232, %one.sub.a.i41 + %tmp233 = fmul float %tmp215, %tmp183 + %tmp234 = fmul float %tmp216, %tmp184 + %tmp235 = fadd float %tmp234, %tmp233 + %tmp236 = fmul float %tmp217, %tmp185 + %tmp237 = fadd float %tmp235, %tmp236 + %tmp238 = fmul float %tmp215, %tmp186 + %tmp239 = fmul float %tmp216, %tmp187 + %tmp240 = fadd float %tmp239, %tmp238 + %tmp241 = fmul float %tmp217, %tmp188 + %tmp242 = fadd float %tmp240, %tmp241 + %tmp243 = fmul float %tmp215, %tmp189 + %tmp244 = fmul float %tmp216, %tmp190 + %tmp245 = fadd float %tmp244, %tmp243 + %tmp246 = fmul float %tmp217, %tmp191 + %tmp247 = fadd float %tmp245, %tmp246 + %tmp248 = call float @llvm.AMDGPU.clamp.f32(float %tmp247, float 0.000000e+00, float 1.000000e+00) + %tmp249 = fmul float %tmp213, 0x3F5A36E2E0000000 + %tmp250 = call float @llvm.AMDGPU.clamp.f32(float %tmp249, float 0.000000e+00, float 1.000000e+00) + %tmp251 = fsub float -0.000000e+00, %tmp250 + %tmp252 = fadd float 1.000000e+00, %tmp251 + %tmp253 = call float @llvm.pow.f32(float %tmp248, float 2.500000e-01) + %tmp254 = fmul float %tmp38, %tmp253 + %tmp255 = fmul float %tmp237, %tmp254 + %tmp256 = fmul float %tmp242, %tmp254 + %tmp257 = fmul float %tmp255, %tmp229 + %tmp258 = fmul float %tmp256, %tmp229 + %tmp259 = fadd float %tmp248, 0x3EE4F8B580000000 + %tmp260 = fsub float -0.000000e+00, %tmp248 + %tmp261 = fadd float 1.000000e+00, %tmp260 + %tmp262 = fmul float 1.200000e+01, %tmp261 + %tmp263 = fadd float %tmp262, 4.000000e+00 + %tmp264 = fsub float -0.000000e+00, %tmp263 + %tmp265 = fmul float %tmp264, %tmp259 + %tmp266 = fsub float -0.000000e+00, %tmp263 + %tmp267 = fmul float %tmp266, %tmp259 + %tmp268 = fsub float -0.000000e+00, %tmp263 + %tmp269 = fmul float %tmp268, %tmp259 + %tmp270 = fdiv float 1.000000e+00, %tmp265 + %tmp271 = fdiv float 1.000000e+00, %tmp267 + %tmp272 = fdiv float 1.000000e+00, %tmp269 + %tmp273 = fmul float %tmp257, %tmp270 + %tmp274 = fmul float %tmp258, %tmp271 + %tmp275 = fmul float %tmp259, %tmp272 br label %LOOP LOOP: ; preds = %LOOP, %main_body - %temp144.0 = phi float [ 1.000000e+00, %main_body ], [ %292, %LOOP ] - %temp168.0 = phi float [ %176, %main_body ], [ %288, %LOOP ] - %temp169.0 = phi float [ %177, %main_body ], [ %289, %LOOP ] - %temp170.0 = phi float [ %256, %main_body ], [ %290, %LOOP ] - %280 = bitcast float %temp168.0 to i32 - %281 = bitcast float %temp169.0 to i32 - %282 = insertelement <4 x i32> undef, i32 %280, i32 0 - %283 = insertelement <4 x i32> %282, i32 %281, i32 1 - %284 = insertelement <4 x i32> %283, i32 0, i32 2 - %285 = insertelement <4 x i32> %284, i32 undef, i32 3 - %286 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %285, <32 x i8> %147, <16 x i8> %149, i32 2) - %287 = extractelement <4 x float> %286, i32 3 - %288 = fadd float %temp168.0, %277 - %289 = fadd float %temp169.0, %278 - %290 = fadd float %temp170.0, %279 - %291 = fsub float -0.000000e+00, %287 - %292 = fadd float %290, %291 - %293 = fcmp oge float 0.000000e+00, %292 - %294 = sext i1 %293 to i32 - %295 = bitcast i32 %294 to float - %296 = bitcast float %295 to i32 - %297 = icmp ne i32 %296, 0 - br i1 %297, label %IF189, label %LOOP + %temp144.0 = phi float [ 1.000000e+00, %main_body ], [ %tmp288, %LOOP ] + %temp168.0 = phi float [ %tmp175, %main_body ], [ %tmp284, %LOOP ] + %temp169.0 = phi float [ %tmp176, %main_body ], [ %tmp285, %LOOP ] + %temp170.0 = phi float [ %tmp252, %main_body ], [ %tmp286, %LOOP ] + %tmp276 = bitcast float %temp168.0 to i32 + %tmp277 = bitcast float %temp169.0 to i32 + %tmp278 = insertelement <4 x i32> undef, i32 %tmp276, i32 0 + %tmp279 = insertelement <4 x i32> %tmp278, i32 %tmp277, i32 1 + %tmp280 = insertelement <4 x i32> %tmp279, i32 0, i32 2 + %tmp281 = insertelement <4 x i32> %tmp280, i32 undef, i32 3 + %tmp148.bc = bitcast <16 x i8> %tmp148 to <4 x i32> + %tmp282 = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> %tmp281, <8 x i32> %tmp146, <4 x i32> %tmp148.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp283 = extractelement <4 x float> %tmp282, i32 3 + %tmp284 = fadd float %temp168.0, %tmp273 + %tmp285 = fadd float %temp169.0, %tmp274 + %tmp286 = fadd float %temp170.0, %tmp275 + %tmp287 = fsub float -0.000000e+00, %tmp283 + %tmp288 = fadd float %tmp286, %tmp287 + %tmp289 = fcmp oge float 0.000000e+00, %tmp288 + %tmp290 = sext i1 %tmp289 to i32 + %tmp291 = bitcast i32 %tmp290 to float + %tmp292 = bitcast float %tmp291 to i32 + %tmp293 = icmp ne i32 %tmp292, 0 + br i1 %tmp293, label %IF189, label %LOOP IF189: ; preds = %LOOP - %298 = extractelement <4 x float> %286, i32 0 - %299 = extractelement <4 x float> %286, i32 1 - %300 = extractelement <4 x float> %286, i32 2 - %301 = fsub float -0.000000e+00, %292 - %302 = fadd float %temp144.0, %301 - %303 = fdiv float 1.000000e+00, %302 - %304 = fmul float %292, %303 - %305 = fadd float %304, -1.000000e+00 - %306 = fmul float %305, %277 - %307 = fadd float %306, %288 - %308 = fmul float %305, %278 - %309 = fadd float %308, %289 - %310 = fsub float -0.000000e+00, %176 - %311 = fadd float %307, %310 - %312 = fsub float -0.000000e+00, %177 - %313 = fadd float %309, %312 - %314 = fadd float %176, %311 - %315 = fadd float %177, %313 - %316 = fmul float %311, %67 - %317 = fmul float %313, %68 - %318 = fmul float %316, %55 - %319 = fmul float %316, %56 - %320 = fmul float %317, %57 - %321 = fadd float %320, %318 - %322 = fmul float %317, %58 - %323 = fadd float %322, %319 - %324 = fadd float %178, %321 - %325 = fadd float %179, %323 - %326 = fmul float %316, %59 - %327 = fmul float %316, %60 - %328 = fmul float %316, %61 - %329 = fmul float %316, %62 - %330 = fmul float %317, %63 - %331 = fadd float %330, %326 - %332 = fmul float %317, %64 - %333 = fadd float %332, %327 - %334 = fmul float %317, %65 - %335 = fadd float %334, %328 - %336 = fmul float %317, %66 - %337 = fadd float %336, %329 - %338 = fadd float %168, %331 - %339 = fadd float %169, %333 - %340 = fadd float %170, %335 - %341 = fadd float %171, %337 - %342 = bitcast float %338 to i32 - %343 = bitcast float %339 to i32 - %344 = insertelement <2 x i32> undef, i32 %342, i32 0 - %345 = insertelement <2 x i32> %344, i32 %343, i32 1 - %346 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %345, <32 x i8> %135, <16 x i8> %137, i32 2) - %347 = extractelement <4 x float> %346, i32 0 - %348 = extractelement <4 x float> %346, i32 1 - %349 = extractelement <4 x float> %346, i32 2 - %350 = extractelement <4 x float> %346, i32 3 - %351 = fmul float %347, %23 - %352 = fmul float %348, %24 - %353 = fmul float %349, %25 - %354 = fmul float %350, %26 - %355 = fmul float %351, %180 - %356 = fmul float %352, %181 - %357 = fmul float %353, %182 - %358 = fmul float %354, %183 - %359 = fsub float -0.000000e+00, %350 - %360 = fadd float 1.000000e+00, %359 - %361 = fmul float %360, %49 - %362 = call float @llvm.AMDGPU.lrp(float %361, float %347, float %355) - %363 = call float @llvm.AMDGPU.lrp(float %361, float %348, float %356) - %364 = call float @llvm.AMDGPU.lrp(float %361, float %349, float %357) - %365 = bitcast float %340 to i32 - %366 = bitcast float %341 to i32 - %367 = insertelement <2 x i32> undef, i32 %365, i32 0 - %368 = insertelement <2 x i32> %367, i32 %366, i32 1 - %369 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %368, <32 x i8> %151, <16 x i8> %153, i32 2) - %370 = extractelement <4 x float> %369, i32 2 - %371 = fmul float %362, %234 - %372 = fmul float %363, %235 - %373 = fmul float %364, %236 - %374 = fmul float %358, %230 - %375 = bitcast float %314 to i32 - %376 = bitcast float %315 to i32 - %377 = insertelement <2 x i32> undef, i32 %375, i32 0 - %378 = insertelement <2 x i32> %377, i32 %376, i32 1 - %379 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %378, <32 x i8> %139, <16 x i8> %141, i32 2) - %380 = extractelement <4 x float> %379, i32 0 - %381 = extractelement <4 x float> %379, i32 1 - %382 = extractelement <4 x float> %379, i32 2 - %383 = extractelement <4 x float> %379, i32 3 - %384 = fcmp olt float 0.000000e+00, %382 - %385 = sext i1 %384 to i32 - %386 = bitcast i32 %385 to float - %387 = bitcast float %386 to i32 - %388 = icmp ne i32 %387, 0 - %.224 = select i1 %388, float %381, float %380 - %.225 = select i1 %388, float %383, float %381 - %389 = bitcast float %324 to i32 - %390 = bitcast float %325 to i32 - %391 = insertelement <2 x i32> undef, i32 %389, i32 0 - %392 = insertelement <2 x i32> %391, i32 %390, i32 1 - %393 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %392, <32 x i8> %143, <16 x i8> %145, i32 2) - %394 = extractelement <4 x float> %393, i32 0 - %395 = extractelement <4 x float> %393, i32 1 - %396 = extractelement <4 x float> %393, i32 2 - %397 = extractelement <4 x float> %393, i32 3 - %398 = fcmp olt float 0.000000e+00, %396 - %399 = sext i1 %398 to i32 - %400 = bitcast i32 %399 to float - %401 = bitcast float %400 to i32 - %402 = icmp ne i32 %401, 0 - %temp112.1 = select i1 %402, float %395, float %394 - %temp113.1 = select i1 %402, float %397, float %395 - %403 = fmul float %.224, 2.000000e+00 - %404 = fadd float %403, -1.000000e+00 - %405 = fmul float %.225, 2.000000e+00 - %406 = fadd float %405, -1.000000e+00 - %407 = fmul float %temp112.1, 2.000000e+00 - %408 = fadd float %407, -1.000000e+00 - %409 = fmul float %temp113.1, 2.000000e+00 - %410 = fadd float %409, -1.000000e+00 - %411 = fsub float -0.000000e+00, %404 - %412 = fmul float %411, %35 - %413 = fsub float -0.000000e+00, %406 - %414 = fmul float %413, %35 - %415 = fsub float -0.000000e+00, %408 - %416 = fmul float %415, %36 - %417 = fsub float -0.000000e+00, %410 - %418 = fmul float %417, %36 - %419 = fmul float %416, %370 - %420 = fmul float %418, %370 - %421 = call float @fabs(float %412) - %422 = call float @fabs(float %414) - %423 = fsub float -0.000000e+00, %421 - %424 = fadd float 1.000000e+00, %423 - %425 = fsub float -0.000000e+00, %422 - %426 = fadd float 1.000000e+00, %425 - %427 = fmul float %424, %419 - %428 = fadd float %427, %412 - %429 = fmul float %426, %420 - %430 = fadd float %429, %414 - %431 = fmul float %428, %428 - %432 = fmul float %430, %430 - %433 = fadd float %431, %432 - %434 = fsub float -0.000000e+00, %433 - %435 = fadd float 0x3FF00068E0000000, %434 - %436 = call float @llvm.AMDIL.clamp.(float %435, float 0.000000e+00, float 1.000000e+00) - %437 = call float @llvm.AMDGPU.rsq.f32(float %436) - %438 = fmul float %437, %436 - %439 = fsub float -0.000000e+00, %436 - %440 = call float @llvm.AMDGPU.cndlt(float %439, float %438, float 0.000000e+00) - %441 = fmul float %184, %428 - %442 = fmul float %185, %428 - %443 = fmul float %186, %428 - %444 = fmul float %187, %430 - %445 = fadd float %444, %441 - %446 = fmul float %188, %430 - %447 = fadd float %446, %442 - %448 = fmul float %189, %430 - %449 = fadd float %448, %443 - %450 = fmul float %190, %440 - %451 = fadd float %450, %445 - %452 = fmul float %191, %440 - %453 = fadd float %452, %447 - %454 = fmul float %192, %440 - %455 = fadd float %454, %449 - %456 = fmul float %451, %451 - %457 = fmul float %453, %453 - %458 = fadd float %457, %456 - %459 = fmul float %455, %455 - %460 = fadd float %458, %459 - %461 = call float @llvm.AMDGPU.rsq.f32(float %460) - %462 = fmul float %451, %461 - %463 = fmul float %453, %461 - %464 = fmul float %455, %461 - %465 = fcmp olt float 0.000000e+00, %219 - %466 = sext i1 %465 to i32 - %467 = bitcast i32 %466 to float - %468 = bitcast float %467 to i32 - %469 = icmp ne i32 %468, 0 - br i1 %469, label %IF198, label %ENDIF197 + %tmp294 = extractelement <4 x float> %tmp282, i32 0 + %tmp295 = extractelement <4 x float> %tmp282, i32 1 + %tmp296 = extractelement <4 x float> %tmp282, i32 2 + %tmp297 = fsub float -0.000000e+00, %tmp288 + %tmp298 = fadd float %temp144.0, %tmp297 + %tmp299 = fdiv float 1.000000e+00, %tmp298 + %tmp300 = fmul float %tmp288, %tmp299 + %tmp301 = fadd float %tmp300, -1.000000e+00 + %tmp302 = fmul float %tmp301, %tmp273 + %tmp303 = fadd float %tmp302, %tmp284 + %tmp304 = fmul float %tmp301, %tmp274 + %tmp305 = fadd float %tmp304, %tmp285 + %tmp306 = fsub float -0.000000e+00, %tmp175 + %tmp307 = fadd float %tmp303, %tmp306 + %tmp308 = fsub float -0.000000e+00, %tmp176 + %tmp309 = fadd float %tmp305, %tmp308 + %tmp310 = fadd float %tmp175, %tmp307 + %tmp311 = fadd float %tmp176, %tmp309 + %tmp312 = fmul float %tmp307, %tmp66 + %tmp313 = fmul float %tmp309, %tmp67 + %tmp314 = fmul float %tmp312, %tmp54 + %tmp315 = fmul float %tmp312, %tmp55 + %tmp316 = fmul float %tmp313, %tmp56 + %tmp317 = fadd float %tmp316, %tmp314 + %tmp318 = fmul float %tmp313, %tmp57 + %tmp319 = fadd float %tmp318, %tmp315 + %tmp320 = fadd float %tmp177, %tmp317 + %tmp321 = fadd float %tmp178, %tmp319 + %tmp322 = fmul float %tmp312, %tmp58 + %tmp323 = fmul float %tmp312, %tmp59 + %tmp324 = fmul float %tmp312, %tmp60 + %tmp325 = fmul float %tmp312, %tmp61 + %tmp326 = fmul float %tmp313, %tmp62 + %tmp327 = fadd float %tmp326, %tmp322 + %tmp328 = fmul float %tmp313, %tmp63 + %tmp329 = fadd float %tmp328, %tmp323 + %tmp330 = fmul float %tmp313, %tmp64 + %tmp331 = fadd float %tmp330, %tmp324 + %tmp332 = fmul float %tmp313, %tmp65 + %tmp333 = fadd float %tmp332, %tmp325 + %tmp334 = fadd float %tmp167, %tmp327 + %tmp335 = fadd float %tmp168, %tmp329 + %tmp336 = fadd float %tmp169, %tmp331 + %tmp337 = fadd float %tmp170, %tmp333 + %tmp338 = bitcast float %tmp334 to i32 + %tmp339 = bitcast float %tmp335 to i32 + %tmp340 = insertelement <2 x i32> undef, i32 %tmp338, i32 0 + %tmp341 = insertelement <2 x i32> %tmp340, i32 %tmp339, i32 1 + %tmp136.bc = bitcast <16 x i8> %tmp136 to <4 x i32> + %tmp342 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp341, <8 x i32> %tmp134, <4 x i32> %tmp136.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp343 = extractelement <4 x float> %tmp342, i32 0 + %tmp344 = extractelement <4 x float> %tmp342, i32 1 + %tmp345 = extractelement <4 x float> %tmp342, i32 2 + %tmp346 = extractelement <4 x float> %tmp342, i32 3 + %tmp347 = fmul float %tmp343, %tmp22 + %tmp348 = fmul float %tmp344, %tmp23 + %tmp349 = fmul float %tmp345, %tmp24 + %tmp350 = fmul float %tmp346, %tmp25 + %tmp351 = fmul float %tmp347, %tmp179 + %tmp352 = fmul float %tmp348, %tmp180 + %tmp353 = fmul float %tmp349, %tmp181 + %tmp354 = fmul float %tmp350, %tmp182 + %tmp355 = fsub float -0.000000e+00, %tmp346 + %tmp356 = fadd float 1.000000e+00, %tmp355 + %tmp357 = fmul float %tmp356, %tmp48 + %one.sub.a.i37 = fsub float 1.000000e+00, %tmp357 + %one.sub.ac.i38 = fmul float %one.sub.a.i37, %tmp351 + %mul.i39 = fmul float %tmp343, %tmp351 + %result.i40 = fadd float %mul.i39, %one.sub.ac.i38 + %one.sub.a.i33 = fsub float 1.000000e+00, %tmp357 + %one.sub.ac.i34 = fmul float %one.sub.a.i33, %tmp352 + %mul.i35 = fmul float %tmp344, %tmp352 + %result.i36 = fadd float %mul.i35, %one.sub.ac.i34 + %one.sub.a.i29 = fsub float 1.000000e+00, %tmp357 + %one.sub.ac.i30 = fmul float %one.sub.a.i29, %tmp353 + %mul.i31 = fmul float %tmp345, %tmp353 + %result.i32 = fadd float %mul.i31, %one.sub.ac.i30 + %tmp358 = bitcast float %tmp336 to i32 + %tmp359 = bitcast float %tmp337 to i32 + %tmp360 = insertelement <2 x i32> undef, i32 %tmp358, i32 0 + %tmp361 = insertelement <2 x i32> %tmp360, i32 %tmp359, i32 1 + %tmp152.bc = bitcast <16 x i8> %tmp152 to <4 x i32> + %tmp362 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp361, <8 x i32> %tmp150, <4 x i32> %tmp152.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp363 = extractelement <4 x float> %tmp362, i32 2 + %tmp364 = fmul float %result.i40, %result.i + %tmp365 = fmul float %result.i36, %result.i44 + %tmp366 = fmul float %result.i32, %result.i42 + %tmp367 = fmul float %tmp354, %tmp229 + %tmp368 = bitcast float %tmp310 to i32 + %tmp369 = bitcast float %tmp311 to i32 + %tmp370 = insertelement <2 x i32> undef, i32 %tmp368, i32 0 + %tmp371 = insertelement <2 x i32> %tmp370, i32 %tmp369, i32 1 + %tmp140.bc = bitcast <16 x i8> %tmp140 to <4 x i32> + %tmp372 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp371, <8 x i32> %tmp138, <4 x i32> %tmp140.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp373 = extractelement <4 x float> %tmp372, i32 0 + %tmp374 = extractelement <4 x float> %tmp372, i32 1 + %tmp375 = extractelement <4 x float> %tmp372, i32 2 + %tmp376 = extractelement <4 x float> %tmp372, i32 3 + %tmp377 = fcmp olt float 0.000000e+00, %tmp375 + %tmp378 = sext i1 %tmp377 to i32 + %tmp379 = bitcast i32 %tmp378 to float + %tmp380 = bitcast float %tmp379 to i32 + %tmp381 = icmp ne i32 %tmp380, 0 + %.224 = select i1 %tmp381, float %tmp374, float %tmp373 + %.225 = select i1 %tmp381, float %tmp376, float %tmp374 + %tmp382 = bitcast float %tmp320 to i32 + %tmp383 = bitcast float %tmp321 to i32 + %tmp384 = insertelement <2 x i32> undef, i32 %tmp382, i32 0 + %tmp385 = insertelement <2 x i32> %tmp384, i32 %tmp383, i32 1 + %tmp144.bc = bitcast <16 x i8> %tmp144 to <4 x i32> + %tmp386 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp385, <8 x i32> %tmp142, <4 x i32> %tmp144.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp387 = extractelement <4 x float> %tmp386, i32 0 + %tmp388 = extractelement <4 x float> %tmp386, i32 1 + %tmp389 = extractelement <4 x float> %tmp386, i32 2 + %tmp390 = extractelement <4 x float> %tmp386, i32 3 + %tmp391 = fcmp olt float 0.000000e+00, %tmp389 + %tmp392 = sext i1 %tmp391 to i32 + %tmp393 = bitcast i32 %tmp392 to float + %tmp394 = bitcast float %tmp393 to i32 + %tmp395 = icmp ne i32 %tmp394, 0 + %temp112.1 = select i1 %tmp395, float %tmp388, float %tmp387 + %temp113.1 = select i1 %tmp395, float %tmp390, float %tmp388 + %tmp396 = fmul float %.224, 2.000000e+00 + %tmp397 = fadd float %tmp396, -1.000000e+00 + %tmp398 = fmul float %.225, 2.000000e+00 + %tmp399 = fadd float %tmp398, -1.000000e+00 + %tmp400 = fmul float %temp112.1, 2.000000e+00 + %tmp401 = fadd float %tmp400, -1.000000e+00 + %tmp402 = fmul float %temp113.1, 2.000000e+00 + %tmp403 = fadd float %tmp402, -1.000000e+00 + %tmp404 = fsub float -0.000000e+00, %tmp397 + %tmp405 = fmul float %tmp404, %tmp34 + %tmp406 = fsub float -0.000000e+00, %tmp399 + %tmp407 = fmul float %tmp406, %tmp34 + %tmp408 = fsub float -0.000000e+00, %tmp401 + %tmp409 = fmul float %tmp408, %tmp35 + %tmp410 = fsub float -0.000000e+00, %tmp403 + %tmp411 = fmul float %tmp410, %tmp35 + %tmp412 = fmul float %tmp409, %tmp363 + %tmp413 = fmul float %tmp411, %tmp363 + %tmp414 = call float @fabs(float %tmp405) + %tmp415 = call float @fabs(float %tmp407) + %tmp416 = fsub float -0.000000e+00, %tmp414 + %tmp417 = fadd float 1.000000e+00, %tmp416 + %tmp418 = fsub float -0.000000e+00, %tmp415 + %tmp419 = fadd float 1.000000e+00, %tmp418 + %tmp420 = fmul float %tmp417, %tmp412 + %tmp421 = fadd float %tmp420, %tmp405 + %tmp422 = fmul float %tmp419, %tmp413 + %tmp423 = fadd float %tmp422, %tmp407 + %tmp424 = fmul float %tmp421, %tmp421 + %tmp425 = fmul float %tmp423, %tmp423 + %tmp426 = fadd float %tmp424, %tmp425 + %tmp427 = fsub float -0.000000e+00, %tmp426 + %tmp428 = fadd float 0x3FF00068E0000000, %tmp427 + %tmp429 = call float @llvm.AMDGPU.clamp.f32(float %tmp428, float 0.000000e+00, float 1.000000e+00) + %tmp430 = call float @llvm.amdgcn.rsq.f32(float %tmp429) + %tmp431 = fmul float %tmp430, %tmp429 + %tmp432 = fsub float -0.000000e+00, %tmp429 + %cmp = fcmp ogt float 0.000000e+00, %tmp432 + %tmp433 = select i1 %cmp, float %tmp431, float 0.000000e+00 + %tmp434 = fmul float %tmp183, %tmp421 + %tmp435 = fmul float %tmp184, %tmp421 + %tmp436 = fmul float %tmp185, %tmp421 + %tmp437 = fmul float %tmp186, %tmp423 + %tmp438 = fadd float %tmp437, %tmp434 + %tmp439 = fmul float %tmp187, %tmp423 + %tmp440 = fadd float %tmp439, %tmp435 + %tmp441 = fmul float %tmp188, %tmp423 + %tmp442 = fadd float %tmp441, %tmp436 + %tmp443 = fmul float %tmp189, %tmp433 + %tmp444 = fadd float %tmp443, %tmp438 + %tmp445 = fmul float %tmp190, %tmp433 + %tmp446 = fadd float %tmp445, %tmp440 + %tmp447 = fmul float %tmp191, %tmp433 + %tmp448 = fadd float %tmp447, %tmp442 + %tmp449 = fmul float %tmp444, %tmp444 + %tmp450 = fmul float %tmp446, %tmp446 + %tmp451 = fadd float %tmp450, %tmp449 + %tmp452 = fmul float %tmp448, %tmp448 + %tmp453 = fadd float %tmp451, %tmp452 + %tmp454 = call float @llvm.amdgcn.rsq.f32(float %tmp453) + %tmp455 = fmul float %tmp444, %tmp454 + %tmp456 = fmul float %tmp446, %tmp454 + %tmp457 = fmul float %tmp448, %tmp454 + %tmp458 = fcmp olt float 0.000000e+00, %tmp218 + %tmp459 = sext i1 %tmp458 to i32 + %tmp460 = bitcast i32 %tmp459 to float + %tmp461 = bitcast float %tmp460 to i32 + %tmp462 = icmp ne i32 %tmp461, 0 + br i1 %tmp462, label %IF198, label %ENDIF197 IF198: ; preds = %IF189 - %470 = fsub float -0.000000e+00, %462 - %471 = fsub float -0.000000e+00, %463 - %472 = fsub float -0.000000e+00, %464 + %tmp463 = fsub float -0.000000e+00, %tmp455 + %tmp464 = fsub float -0.000000e+00, %tmp456 + %tmp465 = fsub float -0.000000e+00, %tmp457 br label %ENDIF197 -ENDIF197: ; preds = %IF189, %IF198 - %temp14.0 = phi float [ %472, %IF198 ], [ %464, %IF189 ] - %temp13.0 = phi float [ %471, %IF198 ], [ %463, %IF189 ] - %temp12.0 = phi float [ %470, %IF198 ], [ %462, %IF189 ] - %473 = bitcast float %220 to i32 - %474 = bitcast float %221 to i32 - %475 = insertelement <2 x i32> undef, i32 %473, i32 0 - %476 = insertelement <2 x i32> %475, i32 %474, i32 1 - %477 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %476, <32 x i8> %159, <16 x i8> %161, i32 2) - %478 = extractelement <4 x float> %477, i32 0 - %479 = extractelement <4 x float> %477, i32 1 - %480 = extractelement <4 x float> %477, i32 2 - %481 = extractelement <4 x float> %477, i32 3 - %482 = fmul float %478, %40 - %483 = fadd float %482, %41 - %484 = fmul float %479, %40 - %485 = fadd float %484, %41 - %486 = fmul float %480, %40 - %487 = fadd float %486, %41 - %488 = fmul float %481, %42 - %489 = fadd float %488, %43 - %490 = bitcast float %172 to i32 - %491 = bitcast float %173 to i32 - %492 = insertelement <2 x i32> undef, i32 %490, i32 0 - %493 = insertelement <2 x i32> %492, i32 %491, i32 1 - %494 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> %493, <32 x i8> %155, <16 x i8> %157, i32 2) - %495 = extractelement <4 x float> %494, i32 0 - %496 = extractelement <4 x float> %494, i32 1 - %497 = extractelement <4 x float> %494, i32 2 - %498 = extractelement <4 x float> %494, i32 3 - %499 = fmul float %498, 3.200000e+01 - %500 = fadd float %499, -1.600000e+01 - %501 = call float @llvm.AMDIL.exp.(float %500) - %502 = fmul float %495, %501 - %503 = fmul float %496, %501 - %504 = fmul float %497, %501 - %505 = fmul float %28, %502 - %506 = fadd float %505, %193 - %507 = fmul float %29, %503 - %508 = fadd float %507, %194 - %509 = fmul float %30, %504 - %510 = fadd float %509, %195 - %511 = fmul float %506, %489 - %512 = fmul float %508, %489 - %513 = fmul float %510, %489 - %514 = fmul float %489, 5.000000e-01 - %515 = fadd float %514, 5.000000e-01 - %516 = fmul float %483, %515 - %517 = fadd float %516, %511 - %518 = fmul float %485, %515 - %519 = fadd float %518, %512 - %520 = fmul float %487, %515 - %521 = fadd float %520, %513 - %522 = fmul float %517, %371 - %523 = fmul float %519, %372 - %524 = fmul float %521, %373 - %525 = fmul float %428, 0x3FDB272440000000 - %526 = fmul float %430, 0xBFDB272440000000 - %527 = fadd float %526, %525 - %528 = fmul float %440, 0x3FE99999A0000000 - %529 = fadd float %527, %528 - %530 = fmul float %529, 5.000000e-01 - %531 = fadd float %530, 0x3FE3333340000000 - %532 = fmul float %531, %531 - %533 = fmul float %522, %532 - %534 = fmul float %523, %532 - %535 = fmul float %524, %532 - %536 = fsub float -0.000000e+00, %72 - %537 = fsub float -0.000000e+00, %73 - %538 = fsub float -0.000000e+00, %74 - %539 = fmul float %temp12.0, %536 - %540 = fmul float %temp13.0, %537 - %541 = fadd float %540, %539 - %542 = fmul float %temp14.0, %538 - %543 = fadd float %541, %542 - %544 = call float @llvm.AMDIL.clamp.(float %543, float 0.000000e+00, float 1.000000e+00) - %545 = fmul float %371, %544 - %546 = fmul float %372, %544 - %547 = fmul float %373, %544 - %548 = fmul float %545, %69 - %549 = fmul float %546, %70 - %550 = fmul float %547, %71 - %551 = fsub float -0.000000e+00, %164 - %552 = fadd float %97, %551 - %553 = fsub float -0.000000e+00, %165 - %554 = fadd float %98, %553 - %555 = fsub float -0.000000e+00, %166 - %556 = fadd float %99, %555 - %557 = fmul float %552, %552 - %558 = fmul float %554, %554 - %559 = fadd float %558, %557 - %560 = fmul float %556, %556 - %561 = fadd float %559, %560 - %562 = call float @llvm.AMDGPU.rsq.f32(float %561) - %563 = fmul float %562, %561 - %564 = fsub float -0.000000e+00, %561 - %565 = call float @llvm.AMDGPU.cndlt(float %564, float %563, float 0.000000e+00) - %566 = fsub float -0.000000e+00, %84 - %567 = fadd float %565, %566 - %568 = fsub float -0.000000e+00, %83 - %569 = fadd float %565, %568 - %570 = fsub float -0.000000e+00, %82 - %571 = fadd float %565, %570 - %572 = fsub float -0.000000e+00, %84 - %573 = fadd float %83, %572 - %574 = fsub float -0.000000e+00, %83 - %575 = fadd float %82, %574 - %576 = fsub float -0.000000e+00, %82 - %577 = fadd float %81, %576 - %578 = fdiv float 1.000000e+00, %573 - %579 = fdiv float 1.000000e+00, %575 - %580 = fdiv float 1.000000e+00, %577 - %581 = fmul float %567, %578 - %582 = fmul float %569, %579 - %583 = fmul float %571, %580 - %584 = fcmp olt float %565, %83 - %585 = sext i1 %584 to i32 - %586 = bitcast i32 %585 to float - %587 = bitcast float %586 to i32 - %588 = icmp ne i32 %587, 0 - br i1 %588, label %ENDIF200, label %ELSE202 +ENDIF197: ; preds = %IF198, %IF189 + %temp14.0 = phi float [ %tmp465, %IF198 ], [ %tmp457, %IF189 ] + %temp13.0 = phi float [ %tmp464, %IF198 ], [ %tmp456, %IF189 ] + %temp12.0 = phi float [ %tmp463, %IF198 ], [ %tmp455, %IF189 ] + %tmp466 = bitcast float %tmp219 to i32 + %tmp467 = bitcast float %tmp220 to i32 + %tmp468 = insertelement <2 x i32> undef, i32 %tmp466, i32 0 + %tmp469 = insertelement <2 x i32> %tmp468, i32 %tmp467, i32 1 + %tmp160.bc = bitcast <16 x i8> %tmp160 to <4 x i32> + %tmp470 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp469, <8 x i32> %tmp158, <4 x i32> %tmp160.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp471 = extractelement <4 x float> %tmp470, i32 0 + %tmp472 = extractelement <4 x float> %tmp470, i32 1 + %tmp473 = extractelement <4 x float> %tmp470, i32 2 + %tmp474 = extractelement <4 x float> %tmp470, i32 3 + %tmp475 = fmul float %tmp471, %tmp39 + %tmp476 = fadd float %tmp475, %tmp40 + %tmp477 = fmul float %tmp472, %tmp39 + %tmp478 = fadd float %tmp477, %tmp40 + %tmp479 = fmul float %tmp473, %tmp39 + %tmp480 = fadd float %tmp479, %tmp40 + %tmp481 = fmul float %tmp474, %tmp41 + %tmp482 = fadd float %tmp481, %tmp42 + %tmp483 = bitcast float %tmp171 to i32 + %tmp484 = bitcast float %tmp172 to i32 + %tmp485 = insertelement <2 x i32> undef, i32 %tmp483, i32 0 + %tmp486 = insertelement <2 x i32> %tmp485, i32 %tmp484, i32 1 + %tmp156.bc = bitcast <16 x i8> %tmp156 to <4 x i32> + %tmp487 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> %tmp486, <8 x i32> %tmp154, <4 x i32> %tmp156.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp488 = extractelement <4 x float> %tmp487, i32 0 + %tmp489 = extractelement <4 x float> %tmp487, i32 1 + %tmp490 = extractelement <4 x float> %tmp487, i32 2 + %tmp491 = extractelement <4 x float> %tmp487, i32 3 + %tmp492 = fmul float %tmp491, 3.200000e+01 + %tmp493 = fadd float %tmp492, -1.600000e+01 + %tmp494 = call float @llvm.exp2.f32(float %tmp493) + %tmp495 = fmul float %tmp488, %tmp494 + %tmp496 = fmul float %tmp489, %tmp494 + %tmp497 = fmul float %tmp490, %tmp494 + %tmp498 = fmul float %tmp27, %tmp495 + %tmp499 = fadd float %tmp498, %tmp192 + %tmp500 = fmul float %tmp28, %tmp496 + %tmp501 = fadd float %tmp500, %tmp193 + %tmp502 = fmul float %tmp29, %tmp497 + %tmp503 = fadd float %tmp502, %tmp194 + %tmp504 = fmul float %tmp499, %tmp482 + %tmp505 = fmul float %tmp501, %tmp482 + %tmp506 = fmul float %tmp503, %tmp482 + %tmp507 = fmul float %tmp482, 5.000000e-01 + %tmp508 = fadd float %tmp507, 5.000000e-01 + %tmp509 = fmul float %tmp476, %tmp508 + %tmp510 = fadd float %tmp509, %tmp504 + %tmp511 = fmul float %tmp478, %tmp508 + %tmp512 = fadd float %tmp511, %tmp505 + %tmp513 = fmul float %tmp480, %tmp508 + %tmp514 = fadd float %tmp513, %tmp506 + %tmp515 = fmul float %tmp510, %tmp364 + %tmp516 = fmul float %tmp512, %tmp365 + %tmp517 = fmul float %tmp514, %tmp366 + %tmp518 = fmul float %tmp421, 0x3FDB272440000000 + %tmp519 = fmul float %tmp423, 0xBFDB272440000000 + %tmp520 = fadd float %tmp519, %tmp518 + %tmp521 = fmul float %tmp433, 0x3FE99999A0000000 + %tmp522 = fadd float %tmp520, %tmp521 + %tmp523 = fmul float %tmp522, 5.000000e-01 + %tmp524 = fadd float %tmp523, 0x3FE3333340000000 + %tmp525 = fmul float %tmp524, %tmp524 + %tmp526 = fmul float %tmp515, %tmp525 + %tmp527 = fmul float %tmp516, %tmp525 + %tmp528 = fmul float %tmp517, %tmp525 + %tmp529 = fsub float -0.000000e+00, %tmp71 + %tmp530 = fsub float -0.000000e+00, %tmp72 + %tmp531 = fsub float -0.000000e+00, %tmp73 + %tmp532 = fmul float %temp12.0, %tmp529 + %tmp533 = fmul float %temp13.0, %tmp530 + %tmp534 = fadd float %tmp533, %tmp532 + %tmp535 = fmul float %temp14.0, %tmp531 + %tmp536 = fadd float %tmp534, %tmp535 + %tmp537 = call float @llvm.AMDGPU.clamp.f32(float %tmp536, float 0.000000e+00, float 1.000000e+00) + %tmp538 = fmul float %tmp364, %tmp537 + %tmp539 = fmul float %tmp365, %tmp537 + %tmp540 = fmul float %tmp366, %tmp537 + %tmp541 = fmul float %tmp538, %tmp68 + %tmp542 = fmul float %tmp539, %tmp69 + %tmp543 = fmul float %tmp540, %tmp70 + %tmp544 = fsub float -0.000000e+00, %tmp163 + %tmp545 = fadd float %tmp96, %tmp544 + %tmp546 = fsub float -0.000000e+00, %tmp164 + %tmp547 = fadd float %tmp97, %tmp546 + %tmp548 = fsub float -0.000000e+00, %tmp165 + %tmp549 = fadd float %tmp98, %tmp548 + %tmp550 = fmul float %tmp545, %tmp545 + %tmp551 = fmul float %tmp547, %tmp547 + %tmp552 = fadd float %tmp551, %tmp550 + %tmp553 = fmul float %tmp549, %tmp549 + %tmp554 = fadd float %tmp552, %tmp553 + %tmp555 = call float @llvm.amdgcn.rsq.f32(float %tmp554) + %tmp556 = fmul float %tmp555, %tmp554 + %tmp557 = fsub float -0.000000e+00, %tmp554 + %cmp1 = fcmp ogt float %tmp557, 0.000000e+00 + %tmp558 = select i1 %cmp1, float %tmp556, float 0.000000e+00 + %tmp559 = fsub float -0.000000e+00, %tmp83 + %tmp560 = fadd float %tmp558, %tmp559 + %tmp561 = fsub float -0.000000e+00, %tmp82 + %tmp562 = fadd float %tmp558, %tmp561 + %tmp563 = fsub float -0.000000e+00, %tmp81 + %tmp564 = fadd float %tmp558, %tmp563 + %tmp565 = fsub float -0.000000e+00, %tmp83 + %tmp566 = fadd float %tmp82, %tmp565 + %tmp567 = fsub float -0.000000e+00, %tmp82 + %tmp568 = fadd float %tmp81, %tmp567 + %tmp569 = fsub float -0.000000e+00, %tmp81 + %tmp570 = fadd float %tmp80, %tmp569 + %tmp571 = fdiv float 1.000000e+00, %tmp566 + %tmp572 = fdiv float 1.000000e+00, %tmp568 + %tmp573 = fdiv float 1.000000e+00, %tmp570 + %tmp574 = fmul float %tmp560, %tmp571 + %tmp575 = fmul float %tmp562, %tmp572 + %tmp576 = fmul float %tmp564, %tmp573 + %tmp577 = fcmp olt float %tmp558, %tmp82 + %tmp578 = sext i1 %tmp577 to i32 + %tmp579 = bitcast i32 %tmp578 to float + %tmp580 = bitcast float %tmp579 to i32 + %tmp581 = icmp ne i32 %tmp580, 0 + br i1 %tmp581, label %ENDIF200, label %ELSE202 ELSE202: ; preds = %ENDIF197 - %589 = fcmp olt float %565, %82 - %590 = sext i1 %589 to i32 - %591 = bitcast i32 %590 to float - %592 = bitcast float %591 to i32 - %593 = icmp ne i32 %592, 0 - br i1 %593, label %ENDIF200, label %ELSE205 + %tmp582 = fcmp olt float %tmp558, %tmp81 + %tmp583 = sext i1 %tmp582 to i32 + %tmp584 = bitcast i32 %tmp583 to float + %tmp585 = bitcast float %tmp584 to i32 + %tmp586 = icmp ne i32 %tmp585, 0 + br i1 %tmp586, label %ENDIF200, label %ELSE205 ENDIF200: ; preds = %ELSE205, %ELSE202, %ENDIF197 - %temp80.0 = phi float [ %581, %ENDIF197 ], [ %.226, %ELSE205 ], [ %582, %ELSE202 ] - %temp88.0 = phi float [ %122, %ENDIF197 ], [ %.227, %ELSE205 ], [ %120, %ELSE202 ] - %temp89.0 = phi float [ %123, %ENDIF197 ], [ %.228, %ELSE205 ], [ %121, %ELSE202 ] - %temp90.0 = phi float [ %120, %ENDIF197 ], [ %116, %ELSE205 ], [ %118, %ELSE202 ] - %temp91.0 = phi float [ %121, %ENDIF197 ], [ %117, %ELSE205 ], [ %119, %ELSE202 ] - %594 = fcmp olt float %565, %83 - %595 = sext i1 %594 to i32 - %596 = bitcast i32 %595 to float - %597 = bitcast float %596 to i32 - %598 = icmp ne i32 %597, 0 - br i1 %598, label %ENDIF209, label %ELSE211 + %temp80.0 = phi float [ %tmp574, %ENDIF197 ], [ %.226, %ELSE205 ], [ %tmp575, %ELSE202 ] + %temp88.0 = phi float [ %tmp121, %ENDIF197 ], [ %.227, %ELSE205 ], [ %tmp119, %ELSE202 ] + %temp89.0 = phi float [ %tmp122, %ENDIF197 ], [ %.228, %ELSE205 ], [ %tmp120, %ELSE202 ] + %temp90.0 = phi float [ %tmp119, %ENDIF197 ], [ %tmp115, %ELSE205 ], [ %tmp117, %ELSE202 ] + %temp91.0 = phi float [ %tmp120, %ENDIF197 ], [ %tmp116, %ELSE205 ], [ %tmp118, %ELSE202 ] + %tmp587 = fcmp olt float %tmp558, %tmp82 + %tmp588 = sext i1 %tmp587 to i32 + %tmp589 = bitcast i32 %tmp588 to float + %tmp590 = bitcast float %tmp589 to i32 + %tmp591 = icmp ne i32 %tmp590, 0 + br i1 %tmp591, label %ENDIF209, label %ELSE211 ELSE205: ; preds = %ELSE202 - %599 = fcmp olt float %565, %81 - %600 = sext i1 %599 to i32 - %601 = bitcast i32 %600 to float - %602 = bitcast float %601 to i32 - %603 = icmp ne i32 %602, 0 - %.226 = select i1 %603, float %583, float 1.000000e+00 - %.227 = select i1 %603, float %118, float %116 - %.228 = select i1 %603, float %119, float %117 + %tmp592 = fcmp olt float %tmp558, %tmp80 + %tmp593 = sext i1 %tmp592 to i32 + %tmp594 = bitcast i32 %tmp593 to float + %tmp595 = bitcast float %tmp594 to i32 + %tmp596 = icmp ne i32 %tmp595, 0 + %.226 = select i1 %tmp596, float %tmp576, float 1.000000e+00 + %.227 = select i1 %tmp596, float %tmp117, float %tmp115 + %.228 = select i1 %tmp596, float %tmp118, float %tmp116 br label %ENDIF200 ELSE211: ; preds = %ENDIF200 - %604 = fcmp olt float %565, %82 - %605 = sext i1 %604 to i32 - %606 = bitcast i32 %605 to float - %607 = bitcast float %606 to i32 - %608 = icmp ne i32 %607, 0 - br i1 %608, label %ENDIF209, label %ELSE214 + %tmp597 = fcmp olt float %tmp558, %tmp81 + %tmp598 = sext i1 %tmp597 to i32 + %tmp599 = bitcast i32 %tmp598 to float + %tmp600 = bitcast float %tmp599 to i32 + %tmp601 = icmp ne i32 %tmp600, 0 + br i1 %tmp601, label %ENDIF209, label %ELSE214 ENDIF209: ; preds = %ELSE214, %ELSE211, %ENDIF200 - %temp52.0 = phi float [ %108, %ENDIF200 ], [ %100, %ELSE214 ], [ %104, %ELSE211 ] - %temp53.0 = phi float [ %109, %ENDIF200 ], [ %101, %ELSE214 ], [ %105, %ELSE211 ] - %temp54.0 = phi float [ %110, %ENDIF200 ], [ %102, %ELSE214 ], [ %106, %ELSE211 ] - %temp55.0 = phi float [ %111, %ENDIF200 ], [ %103, %ELSE214 ], [ %107, %ELSE211 ] - %temp68.0 = phi float [ %112, %ENDIF200 ], [ %.230, %ELSE214 ], [ %108, %ELSE211 ] - %temp69.0 = phi float [ %113, %ENDIF200 ], [ %.231, %ELSE214 ], [ %109, %ELSE211 ] - %temp70.0 = phi float [ %114, %ENDIF200 ], [ %.232, %ELSE214 ], [ %110, %ELSE211 ] - %temp71.0 = phi float [ %115, %ENDIF200 ], [ %.233, %ELSE214 ], [ %111, %ELSE211 ] - %609 = fmul float %164, %85 - %610 = fmul float %165, %86 - %611 = fadd float %609, %610 - %612 = fmul float %166, %87 - %613 = fadd float %611, %612 - %614 = fmul float %167, %88 - %615 = fadd float %613, %614 - %616 = fmul float %164, %89 - %617 = fmul float %165, %90 - %618 = fadd float %616, %617 - %619 = fmul float %166, %91 - %620 = fadd float %618, %619 - %621 = fmul float %167, %92 - %622 = fadd float %620, %621 - %623 = fmul float %164, %93 - %624 = fmul float %165, %94 - %625 = fadd float %623, %624 - %626 = fmul float %166, %95 - %627 = fadd float %625, %626 - %628 = fmul float %167, %96 - %629 = fadd float %627, %628 - %630 = fsub float -0.000000e+00, %78 - %631 = fadd float 1.000000e+00, %630 - %632 = call float @fabs(float %615) - %633 = call float @fabs(float %622) - %634 = fcmp oge float %631, %632 - %635 = sext i1 %634 to i32 - %636 = bitcast i32 %635 to float - %637 = bitcast float %636 to i32 - %638 = and i32 %637, 1065353216 - %639 = bitcast i32 %638 to float - %640 = fcmp oge float %631, %633 - %641 = sext i1 %640 to i32 - %642 = bitcast i32 %641 to float - %643 = bitcast float %642 to i32 - %644 = and i32 %643, 1065353216 - %645 = bitcast i32 %644 to float - %646 = fmul float %639, %645 - %647 = fmul float %629, %646 - %648 = fmul float %615, %temp68.0 - %649 = fadd float %648, %temp70.0 - %650 = fmul float %622, %temp69.0 - %651 = fadd float %650, %temp71.0 - %652 = fmul float %615, %temp52.0 - %653 = fadd float %652, %temp54.0 - %654 = fmul float %622, %temp53.0 - %655 = fadd float %654, %temp55.0 - %656 = fadd float %temp80.0, -1.000000e+00 - %657 = fmul float %656, %77 - %658 = fadd float %657, 1.000000e+00 - %659 = call float @llvm.AMDIL.clamp.(float %658, float 0.000000e+00, float 1.000000e+00) - %660 = bitcast float %649 to i32 - %661 = bitcast float %651 to i32 - %662 = bitcast float 0.000000e+00 to i32 - %663 = insertelement <4 x i32> undef, i32 %660, i32 0 - %664 = insertelement <4 x i32> %663, i32 %661, i32 1 - %665 = insertelement <4 x i32> %664, i32 %662, i32 2 - %666 = insertelement <4 x i32> %665, i32 undef, i32 3 - %667 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %666, <32 x i8> %127, <16 x i8> %129, i32 2) - %668 = extractelement <4 x float> %667, i32 0 - %669 = extractelement <4 x float> %667, i32 1 - %670 = bitcast float %653 to i32 - %671 = bitcast float %655 to i32 - %672 = bitcast float 0.000000e+00 to i32 - %673 = insertelement <4 x i32> undef, i32 %670, i32 0 - %674 = insertelement <4 x i32> %673, i32 %671, i32 1 - %675 = insertelement <4 x i32> %674, i32 %672, i32 2 - %676 = insertelement <4 x i32> %675, i32 undef, i32 3 - %677 = call <4 x float> @llvm.SI.samplel.v4i32(<4 x i32> %676, <32 x i8> %127, <16 x i8> %129, i32 2) - %678 = extractelement <4 x float> %677, i32 0 - %679 = extractelement <4 x float> %677, i32 1 - %680 = fsub float -0.000000e+00, %669 - %681 = fadd float 1.000000e+00, %680 - %682 = fsub float -0.000000e+00, %679 - %683 = fadd float 1.000000e+00, %682 - %684 = fmul float %681, 2.500000e-01 - %685 = fmul float %683, 2.500000e-01 - %686 = fsub float -0.000000e+00, %684 - %687 = fadd float %668, %686 - %688 = fsub float -0.000000e+00, %685 - %689 = fadd float %678, %688 - %690 = fmul float %647, %temp88.0 - %691 = fadd float %690, %temp89.0 - %692 = fmul float %647, %temp90.0 - %693 = fadd float %692, %temp91.0 - %694 = call float @llvm.AMDIL.clamp.(float %691, float 0.000000e+00, float 1.000000e+00) - %695 = call float @llvm.AMDIL.clamp.(float %693, float 0.000000e+00, float 1.000000e+00) - %696 = fsub float -0.000000e+00, %694 - %697 = fadd float %668, %696 - %698 = fsub float -0.000000e+00, %695 - %699 = fadd float %678, %698 - %700 = fmul float %668, %668 - %701 = fmul float %678, %678 - %702 = fsub float -0.000000e+00, %700 - %703 = fadd float %687, %702 - %704 = fsub float -0.000000e+00, %701 - %705 = fadd float %689, %704 - %706 = fcmp uge float %703, %75 - %707 = select i1 %706, float %703, float %75 - %708 = fcmp uge float %705, %75 - %709 = select i1 %708, float %705, float %75 - %710 = fmul float %697, %697 - %711 = fadd float %710, %707 - %712 = fmul float %699, %699 - %713 = fadd float %712, %709 - %714 = fdiv float 1.000000e+00, %711 - %715 = fdiv float 1.000000e+00, %713 - %716 = fmul float %707, %714 - %717 = fmul float %709, %715 - %718 = fcmp oge float %697, 0.000000e+00 - %719 = sext i1 %718 to i32 - %720 = bitcast i32 %719 to float - %721 = bitcast float %720 to i32 - %722 = icmp ne i32 %721, 0 - %.229 = select i1 %722, float 1.000000e+00, float %716 - %723 = fcmp oge float %699, 0.000000e+00 - %724 = sext i1 %723 to i32 - %725 = bitcast i32 %724 to float - %726 = bitcast float %725 to i32 - %727 = icmp ne i32 %726, 0 - %temp28.0 = select i1 %727, float 1.000000e+00, float %717 - %728 = call float @llvm.AMDGPU.lrp(float %659, float %temp28.0, float %.229) - %729 = call float @llvm.pow.f32(float %728, float %76) - %730 = fmul float %729, %79 - %731 = fadd float %730, %80 - %732 = call float @llvm.AMDIL.clamp.(float %731, float 0.000000e+00, float 1.000000e+00) - %733 = fmul float %732, %732 - %734 = fmul float 2.000000e+00, %732 - %735 = fsub float -0.000000e+00, %734 - %736 = fadd float 3.000000e+00, %735 - %737 = fmul float %733, %736 - %738 = fmul float %548, %737 - %739 = fmul float %549, %737 - %740 = fmul float %550, %737 - %741 = fmul float %738, %515 - %742 = fadd float %741, %533 - %743 = fmul float %739, %515 - %744 = fadd float %743, %534 - %745 = fmul float %740, %515 - %746 = fadd float %745, %535 - %747 = call float @llvm.AMDGPU.lrp(float %230, float %287, float 1.000000e+00) - %748 = call float @llvm.AMDGPU.lrp(float %37, float %298, float 1.000000e+00) - %749 = call float @llvm.AMDGPU.lrp(float %37, float %299, float 1.000000e+00) - %750 = call float @llvm.AMDGPU.lrp(float %37, float %300, float 1.000000e+00) - %751 = call float @llvm.AMDGPU.lrp(float %38, float %747, float 1.000000e+00) - %752 = fmul float %748, %751 - %753 = fmul float %749, %751 - %754 = fmul float %750, %751 - %755 = fmul float %742, %752 - %756 = fmul float %744, %753 - %757 = fmul float %746, %754 - %758 = fmul float %temp12.0, %216 - %759 = fmul float %temp13.0, %217 - %760 = fadd float %759, %758 - %761 = fmul float %temp14.0, %218 - %762 = fadd float %760, %761 - %763 = call float @fabs(float %762) - %764 = fmul float %763, %763 - %765 = fmul float %764, %50 - %766 = fadd float %765, %51 - %767 = call float @llvm.AMDIL.clamp.(float %766, float 0.000000e+00, float 1.000000e+00) - %768 = fsub float -0.000000e+00, %767 - %769 = fadd float 1.000000e+00, %768 - %770 = fmul float %33, %769 - %771 = fmul float %33, %769 - %772 = fmul float %33, %769 - %773 = fmul float %34, %769 - %774 = call float @llvm.AMDGPU.lrp(float %770, float %31, float %755) - %775 = call float @llvm.AMDGPU.lrp(float %771, float %31, float %756) - %776 = call float @llvm.AMDGPU.lrp(float %772, float %31, float %757) - %777 = call float @llvm.AMDGPU.lrp(float %773, float %32, float %374) - %778 = fcmp uge float %774, 0x3E6FFFFE60000000 - %779 = select i1 %778, float %774, float 0x3E6FFFFE60000000 - %780 = fcmp uge float %775, 0x3E6FFFFE60000000 - %781 = select i1 %780, float %775, float 0x3E6FFFFE60000000 - %782 = fcmp uge float %776, 0x3E6FFFFE60000000 - %783 = select i1 %782, float %776, float 0x3E6FFFFE60000000 - %784 = fcmp uge float %779, 6.550400e+04 - %785 = select i1 %784, float 6.550400e+04, float %779 - %786 = fcmp uge float %781, 6.550400e+04 - %787 = select i1 %786, float 6.550400e+04, float %781 - %788 = fcmp uge float %783, 6.550400e+04 - %789 = select i1 %788, float 6.550400e+04, float %783 - %790 = fmul float %777, %52 - %791 = fadd float %790, %53 - %792 = call float @llvm.AMDIL.clamp.(float %791, float 0.000000e+00, float 1.000000e+00) - %793 = call i32 @llvm.SI.packf16(float %785, float %787) - %794 = bitcast i32 %793 to float - %795 = call i32 @llvm.SI.packf16(float %789, float %792) - %796 = bitcast i32 %795 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %794, float %796, float %794, float %796) + %temp52.0 = phi float [ %tmp107, %ENDIF200 ], [ %tmp99, %ELSE214 ], [ %tmp103, %ELSE211 ] + %temp53.0 = phi float [ %tmp108, %ENDIF200 ], [ %tmp100, %ELSE214 ], [ %tmp104, %ELSE211 ] + %temp54.0 = phi float [ %tmp109, %ENDIF200 ], [ %tmp101, %ELSE214 ], [ %tmp105, %ELSE211 ] + %temp55.0 = phi float [ %tmp110, %ENDIF200 ], [ %tmp102, %ELSE214 ], [ %tmp106, %ELSE211 ] + %temp68.0 = phi float [ %tmp111, %ENDIF200 ], [ %.230, %ELSE214 ], [ %tmp107, %ELSE211 ] + %temp69.0 = phi float [ %tmp112, %ENDIF200 ], [ %.231, %ELSE214 ], [ %tmp108, %ELSE211 ] + %temp70.0 = phi float [ %tmp113, %ENDIF200 ], [ %.232, %ELSE214 ], [ %tmp109, %ELSE211 ] + %temp71.0 = phi float [ %tmp114, %ENDIF200 ], [ %.233, %ELSE214 ], [ %tmp110, %ELSE211 ] + %tmp602 = fmul float %tmp163, %tmp84 + %tmp603 = fmul float %tmp164, %tmp85 + %tmp604 = fadd float %tmp602, %tmp603 + %tmp605 = fmul float %tmp165, %tmp86 + %tmp606 = fadd float %tmp604, %tmp605 + %tmp607 = fmul float %tmp166, %tmp87 + %tmp608 = fadd float %tmp606, %tmp607 + %tmp609 = fmul float %tmp163, %tmp88 + %tmp610 = fmul float %tmp164, %tmp89 + %tmp611 = fadd float %tmp609, %tmp610 + %tmp612 = fmul float %tmp165, %tmp90 + %tmp613 = fadd float %tmp611, %tmp612 + %tmp614 = fmul float %tmp166, %tmp91 + %tmp615 = fadd float %tmp613, %tmp614 + %tmp616 = fmul float %tmp163, %tmp92 + %tmp617 = fmul float %tmp164, %tmp93 + %tmp618 = fadd float %tmp616, %tmp617 + %tmp619 = fmul float %tmp165, %tmp94 + %tmp620 = fadd float %tmp618, %tmp619 + %tmp621 = fmul float %tmp166, %tmp95 + %tmp622 = fadd float %tmp620, %tmp621 + %tmp623 = fsub float -0.000000e+00, %tmp77 + %tmp624 = fadd float 1.000000e+00, %tmp623 + %tmp625 = call float @fabs(float %tmp608) + %tmp626 = call float @fabs(float %tmp615) + %tmp627 = fcmp oge float %tmp624, %tmp625 + %tmp628 = sext i1 %tmp627 to i32 + %tmp629 = bitcast i32 %tmp628 to float + %tmp630 = bitcast float %tmp629 to i32 + %tmp631 = and i32 %tmp630, 1065353216 + %tmp632 = bitcast i32 %tmp631 to float + %tmp633 = fcmp oge float %tmp624, %tmp626 + %tmp634 = sext i1 %tmp633 to i32 + %tmp635 = bitcast i32 %tmp634 to float + %tmp636 = bitcast float %tmp635 to i32 + %tmp637 = and i32 %tmp636, 1065353216 + %tmp638 = bitcast i32 %tmp637 to float + %tmp639 = fmul float %tmp632, %tmp638 + %tmp640 = fmul float %tmp622, %tmp639 + %tmp641 = fmul float %tmp608, %temp68.0 + %tmp642 = fadd float %tmp641, %temp70.0 + %tmp643 = fmul float %tmp615, %temp69.0 + %tmp644 = fadd float %tmp643, %temp71.0 + %tmp645 = fmul float %tmp608, %temp52.0 + %tmp646 = fadd float %tmp645, %temp54.0 + %tmp647 = fmul float %tmp615, %temp53.0 + %tmp648 = fadd float %tmp647, %temp55.0 + %tmp649 = fadd float %temp80.0, -1.000000e+00 + %tmp650 = fmul float %tmp649, %tmp76 + %tmp651 = fadd float %tmp650, 1.000000e+00 + %tmp652 = call float @llvm.AMDGPU.clamp.f32(float %tmp651, float 0.000000e+00, float 1.000000e+00) + %tmp653 = bitcast float %tmp642 to i32 + %tmp654 = bitcast float %tmp644 to i32 + %tmp655 = bitcast float 0.000000e+00 to i32 + %tmp656 = insertelement <4 x i32> undef, i32 %tmp653, i32 0 + %tmp657 = insertelement <4 x i32> %tmp656, i32 %tmp654, i32 1 + %tmp658 = insertelement <4 x i32> %tmp657, i32 %tmp655, i32 2 + %tmp659 = insertelement <4 x i32> %tmp658, i32 undef, i32 3 + %tmp128.bc = bitcast <16 x i8> %tmp128 to <4 x i32> + %tmp660 = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> %tmp659, <8 x i32> %tmp126, <4 x i32> %tmp128.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp661 = extractelement <4 x float> %tmp660, i32 0 + %tmp662 = extractelement <4 x float> %tmp660, i32 1 + %tmp663 = bitcast float %tmp646 to i32 + %tmp664 = bitcast float %tmp648 to i32 + %tmp665 = bitcast float 0.000000e+00 to i32 + %tmp666 = insertelement <4 x i32> undef, i32 %tmp663, i32 0 + %tmp667 = insertelement <4 x i32> %tmp666, i32 %tmp664, i32 1 + %tmp668 = insertelement <4 x i32> %tmp667, i32 %tmp665, i32 2 + %tmp669 = insertelement <4 x i32> %tmp668, i32 undef, i32 3 + %tmp670 = call <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32> %tmp669, <8 x i32> %tmp126, <4 x i32> %tmp128.bc, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp671 = extractelement <4 x float> %tmp670, i32 0 + %tmp672 = extractelement <4 x float> %tmp670, i32 1 + %tmp673 = fsub float -0.000000e+00, %tmp662 + %tmp674 = fadd float 1.000000e+00, %tmp673 + %tmp675 = fsub float -0.000000e+00, %tmp672 + %tmp676 = fadd float 1.000000e+00, %tmp675 + %tmp677 = fmul float %tmp674, 2.500000e-01 + %tmp678 = fmul float %tmp676, 2.500000e-01 + %tmp679 = fsub float -0.000000e+00, %tmp677 + %tmp680 = fadd float %tmp661, %tmp679 + %tmp681 = fsub float -0.000000e+00, %tmp678 + %tmp682 = fadd float %tmp671, %tmp681 + %tmp683 = fmul float %tmp640, %temp88.0 + %tmp684 = fadd float %tmp683, %temp89.0 + %tmp685 = fmul float %tmp640, %temp90.0 + %tmp686 = fadd float %tmp685, %temp91.0 + %tmp687 = call float @llvm.AMDGPU.clamp.f32(float %tmp684, float 0.000000e+00, float 1.000000e+00) + %tmp688 = call float @llvm.AMDGPU.clamp.f32(float %tmp686, float 0.000000e+00, float 1.000000e+00) + %tmp689 = fsub float -0.000000e+00, %tmp687 + %tmp690 = fadd float %tmp661, %tmp689 + %tmp691 = fsub float -0.000000e+00, %tmp688 + %tmp692 = fadd float %tmp671, %tmp691 + %tmp693 = fmul float %tmp661, %tmp661 + %tmp694 = fmul float %tmp671, %tmp671 + %tmp695 = fsub float -0.000000e+00, %tmp693 + %tmp696 = fadd float %tmp680, %tmp695 + %tmp697 = fsub float -0.000000e+00, %tmp694 + %tmp698 = fadd float %tmp682, %tmp697 + %tmp699 = fcmp uge float %tmp696, %tmp74 + %tmp700 = select i1 %tmp699, float %tmp696, float %tmp74 + %tmp701 = fcmp uge float %tmp698, %tmp74 + %tmp702 = select i1 %tmp701, float %tmp698, float %tmp74 + %tmp703 = fmul float %tmp690, %tmp690 + %tmp704 = fadd float %tmp703, %tmp700 + %tmp705 = fmul float %tmp692, %tmp692 + %tmp706 = fadd float %tmp705, %tmp702 + %tmp707 = fdiv float 1.000000e+00, %tmp704 + %tmp708 = fdiv float 1.000000e+00, %tmp706 + %tmp709 = fmul float %tmp700, %tmp707 + %tmp710 = fmul float %tmp702, %tmp708 + %tmp711 = fcmp oge float %tmp690, 0.000000e+00 + %tmp712 = sext i1 %tmp711 to i32 + %tmp713 = bitcast i32 %tmp712 to float + %tmp714 = bitcast float %tmp713 to i32 + %tmp715 = icmp ne i32 %tmp714, 0 + %.229 = select i1 %tmp715, float 1.000000e+00, float %tmp709 + %tmp716 = fcmp oge float %tmp692, 0.000000e+00 + %tmp717 = sext i1 %tmp716 to i32 + %tmp718 = bitcast i32 %tmp717 to float + %tmp719 = bitcast float %tmp718 to i32 + %tmp720 = icmp ne i32 %tmp719, 0 + %temp28.0 = select i1 %tmp720, float 1.000000e+00, float %tmp710 + %one.sub.a.i25 = fsub float 1.000000e+00, %tmp652 + %one.sub.ac.i26 = fmul float %one.sub.a.i25, %.229 + %mul.i27 = fmul float %temp28.0, %.229 + %result.i28 = fadd float %mul.i27, %one.sub.ac.i26 + %tmp721 = call float @llvm.pow.f32(float %result.i28, float %tmp75) + %tmp722 = fmul float %tmp721, %tmp78 + %tmp723 = fadd float %tmp722, %tmp79 + %tmp724 = call float @llvm.AMDGPU.clamp.f32(float %tmp723, float 0.000000e+00, float 1.000000e+00) + %tmp725 = fmul float %tmp724, %tmp724 + %tmp726 = fmul float 2.000000e+00, %tmp724 + %tmp727 = fsub float -0.000000e+00, %tmp726 + %tmp728 = fadd float 3.000000e+00, %tmp727 + %tmp729 = fmul float %tmp725, %tmp728 + %tmp730 = fmul float %tmp541, %tmp729 + %tmp731 = fmul float %tmp542, %tmp729 + %tmp732 = fmul float %tmp543, %tmp729 + %tmp733 = fmul float %tmp730, %tmp508 + %tmp734 = fadd float %tmp733, %tmp526 + %tmp735 = fmul float %tmp731, %tmp508 + %tmp736 = fadd float %tmp735, %tmp527 + %tmp737 = fmul float %tmp732, %tmp508 + %tmp738 = fadd float %tmp737, %tmp528 + %one.sub.a.i23 = fsub float 1.000000e+00, %tmp229 + %result.i24 = fadd float %tmp283, %one.sub.a.i23 + %one.sub.a.i21 = fsub float 1.000000e+00, %tmp36 + %result.i22 = fadd float %tmp294, %one.sub.a.i21 + %one.sub.a.i19 = fsub float 1.000000e+00, %tmp36 + %result.i20 = fadd float %tmp295, %one.sub.a.i19 + %one.sub.a.i17 = fsub float 1.000000e+00, %tmp36 + %result.i18 = fadd float %tmp296, %one.sub.a.i17 + %one.sub.a.i15 = fsub float 1.000000e+00, %tmp37 + %result.i16 = fadd float %result.i24, %one.sub.a.i15 + %tmp739 = fmul float %result.i22, %result.i16 + %tmp740 = fmul float %result.i20, %result.i16 + %tmp741 = fmul float %result.i18, %result.i16 + %tmp742 = fmul float %tmp734, %tmp739 + %tmp743 = fmul float %tmp736, %tmp740 + %tmp744 = fmul float %tmp738, %tmp741 + %tmp745 = fmul float %temp12.0, %tmp215 + %tmp746 = fmul float %temp13.0, %tmp216 + %tmp747 = fadd float %tmp746, %tmp745 + %tmp748 = fmul float %temp14.0, %tmp217 + %tmp749 = fadd float %tmp747, %tmp748 + %tmp750 = call float @fabs(float %tmp749) + %tmp751 = fmul float %tmp750, %tmp750 + %tmp752 = fmul float %tmp751, %tmp49 + %tmp753 = fadd float %tmp752, %tmp50 + %tmp754 = call float @llvm.AMDGPU.clamp.f32(float %tmp753, float 0.000000e+00, float 1.000000e+00) + %tmp755 = fsub float -0.000000e+00, %tmp754 + %tmp756 = fadd float 1.000000e+00, %tmp755 + %tmp757 = fmul float %tmp32, %tmp756 + %tmp758 = fmul float %tmp32, %tmp756 + %tmp759 = fmul float %tmp32, %tmp756 + %tmp760 = fmul float %tmp33, %tmp756 + %one.sub.a.i11 = fsub float 1.000000e+00, %tmp757 + %one.sub.ac.i12 = fmul float %one.sub.a.i11, %tmp742 + %mul.i13 = fmul float %tmp30, %tmp742 + %result.i14 = fadd float %mul.i13, %one.sub.ac.i12 + %one.sub.a.i7 = fsub float 1.000000e+00, %tmp758 + %one.sub.ac.i8 = fmul float %one.sub.a.i7, %tmp743 + %mul.i9 = fmul float %tmp30, %tmp743 + %result.i10 = fadd float %mul.i9, %one.sub.ac.i8 + %one.sub.a.i3 = fsub float 1.000000e+00, %tmp759 + %one.sub.ac.i4 = fmul float %one.sub.a.i3, %tmp744 + %mul.i5 = fmul float %tmp30, %tmp744 + %result.i6 = fadd float %mul.i5, %one.sub.ac.i4 + %one.sub.a.i1 = fsub float 1.000000e+00, %tmp760 + %one.sub.ac.i = fmul float %one.sub.a.i1, %tmp367 + %mul.i = fmul float %tmp31, %tmp367 + %result.i2 = fadd float %mul.i, %one.sub.ac.i + %tmp761 = fcmp uge float %result.i14, 0x3E6FFFFE60000000 + %tmp762 = select i1 %tmp761, float %result.i14, float 0x3E6FFFFE60000000 + %tmp763 = fcmp uge float %result.i10, 0x3E6FFFFE60000000 + %tmp764 = select i1 %tmp763, float %result.i10, float 0x3E6FFFFE60000000 + %tmp765 = fcmp uge float %result.i6, 0x3E6FFFFE60000000 + %tmp766 = select i1 %tmp765, float %result.i6, float 0x3E6FFFFE60000000 + %tmp767 = fcmp uge float %tmp762, 6.550400e+04 + %tmp768 = select i1 %tmp767, float 6.550400e+04, float %tmp762 + %tmp769 = fcmp uge float %tmp764, 6.550400e+04 + %tmp770 = select i1 %tmp769, float 6.550400e+04, float %tmp764 + %tmp771 = fcmp uge float %tmp766, 6.550400e+04 + %tmp772 = select i1 %tmp771, float 6.550400e+04, float %tmp766 + %tmp773 = fmul float %result.i2, %tmp51 + %tmp774 = fadd float %tmp773, %tmp52 + %tmp775 = call float @llvm.AMDGPU.clamp.f32(float %tmp774, float 0.000000e+00, float 1.000000e+00) + %tmp776 = call i32 @llvm.SI.packf16(float %tmp768, float %tmp770) + %tmp777 = bitcast i32 %tmp776 to float + %tmp778 = call i32 @llvm.SI.packf16(float %tmp772, float %tmp775) + %tmp779 = bitcast i32 %tmp778 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %tmp777, float %tmp779, float %tmp777, float %tmp779) ret void ELSE214: ; preds = %ELSE211 - %797 = fcmp olt float %565, %81 - %798 = sext i1 %797 to i32 - %799 = bitcast i32 %798 to float - %800 = bitcast float %799 to i32 - %801 = icmp ne i32 %800, 0 - %.230 = select i1 %801, float %104, float %100 - %.231 = select i1 %801, float %105, float %101 - %.232 = select i1 %801, float %106, float %102 - %.233 = select i1 %801, float %107, float %103 + %tmp780 = fcmp olt float %tmp558, %tmp80 + %tmp781 = sext i1 %tmp780 to i32 + %tmp782 = bitcast i32 %tmp781 to float + %tmp783 = bitcast float %tmp782 to i32 + %tmp784 = icmp ne i32 %tmp783, 0 + %.230 = select i1 %tmp784, float %tmp103, float %tmp99 + %.231 = select i1 %tmp784, float %tmp104, float %tmp100 + %.232 = select i1 %tmp784, float %tmp105, float %tmp101 + %.233 = select i1 %tmp784, float %tmp106, float %tmp102 br label %ENDIF209 } ; Function Attrs: readnone -declare float @llvm.AMDIL.clamp.(float, float, float) #2 +declare float @llvm.AMDGPU.clamp.f32(float, float, float) #1 ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2 -; Function Attrs: readnone -declare float @llvm.AMDGPU.lrp(float, float, float) #2 +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.image.sample.l.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2 + + +declare float @llvm.exp2.f32(float) #2 ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.samplel.v4i32(<4 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare float @llvm.SI.load.const(<16 x i8>, i32) #2 + +; Function Attrs: nounwind readnone +declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #2 + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 + +; Function Attrs: nounwind readonly +declare float @ceil(float) #3 + +; Function Attrs: nounwind readnone +declare float @llvm.amdgcn.rsq.f32(float) #2 + +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.image.sample.d.v8i32(<8 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2 ; Function Attrs: readnone -declare float @llvm.AMDGPU.cndlt(float, float, float) #2 +declare <4 x float> @llvm.AMDGPU.cube(<4 x float>) #1 ; Function Attrs: readnone -declare float @llvm.AMDIL.exp.(float) #2 +declare float @fabs(float) #1 -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } -attributes #2 = { readnone } +; Function Attrs: nounwind readnone +declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #2 + + +; Function Attrs: nounwind readnone +declare float @llvm.pow.f32(float, float) #2 + +; Function Attrs: nounwind readnone +declare i32 @llvm.SI.packf16(float, float) #2 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #1 = { readnone } +attributes #2 = { nounwind readnone } attributes #3 = { nounwind readonly } -attributes #4 = { readonly } + +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} diff --git a/test/CodeGen/AMDGPU/si-spill-cf.ll b/test/CodeGen/AMDGPU/si-spill-cf.ll index 4b2d8ec6bf0a..30aa2d550f65 100644 --- a/test/CodeGen/AMDGPU/si-spill-cf.ll +++ b/test/CodeGen/AMDGPU/si-spill-cf.ll @@ -3,10 +3,10 @@ ; If this occurs it is likely due to reordering and the restore was ; originally supposed to happen before SI_END_CF. + ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]] ; SI-NOT: v_readlane_b32 [[SAVED]] - -define void @main() #0 { +define amdgpu_ps void @main() #0 { main_body: %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16) %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32) @@ -80,184 +80,198 @@ main_body: LOOP: ; preds = %ENDIF2795, %main_body %temp894.0 = phi float [ 0.000000e+00, %main_body ], [ %temp894.1, %ENDIF2795 ] %temp18.0 = phi float [ undef, %main_body ], [ %temp18.1, %ENDIF2795 ] - %67 = icmp sgt i32 undef, 4 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %67 = icmp sgt i32 %tid, 4 br i1 %67, label %ENDLOOP, label %ENDIF ENDLOOP: ; preds = %ELSE2566, %LOOP - %68 = call float @llvm.AMDGPU.lrp(float %0, float undef, float undef) - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float undef, float %68, float undef, float 1.000000e+00) + %one.sub.a.i = fsub float 1.000000e+00, %0 + %one.sub.ac.i = fmul float %one.sub.a.i, undef + %result.i = fadd float fmul (float undef, float undef), %one.sub.ac.i + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float undef, float %result.i, float undef, float 1.000000e+00) ret void ENDIF: ; preds = %LOOP - %69 = fsub float %2, undef - %70 = fsub float %3, undef - %71 = fsub float %4, undef - %72 = fmul float %69, 0.000000e+00 + %68 = fsub float %2, undef + %69 = fsub float %3, undef + %70 = fsub float %4, undef + %71 = fmul float %68, 0.000000e+00 + %72 = fmul float %69, undef %73 = fmul float %70, undef - %74 = fmul float %71, undef - %75 = fsub float %6, undef - %76 = fsub float %7, undef - %77 = fmul float %75, undef - %78 = fmul float %76, 0.000000e+00 - %79 = call float @llvm.minnum.f32(float %74, float %78) - %80 = call float @llvm.maxnum.f32(float %72, float 0.000000e+00) - %81 = call float @llvm.maxnum.f32(float %73, float %77) - %82 = call float @llvm.maxnum.f32(float undef, float %79) - %83 = call float @llvm.minnum.f32(float %80, float %81) - %84 = call float @llvm.minnum.f32(float %83, float undef) - %85 = fsub float %14, undef - %86 = fsub float %15, undef - %87 = fsub float %16, undef + %74 = fsub float %6, undef + %75 = fsub float %7, undef + %76 = fmul float %74, undef + %77 = fmul float %75, 0.000000e+00 + %78 = call float @llvm.minnum.f32(float %73, float %77) + %79 = call float @llvm.maxnum.f32(float %71, float 0.000000e+00) + %80 = call float @llvm.maxnum.f32(float %72, float %76) + %81 = call float @llvm.maxnum.f32(float undef, float %78) + %82 = call float @llvm.minnum.f32(float %79, float %80) + %83 = call float @llvm.minnum.f32(float %82, float undef) + %84 = fsub float %14, undef + %85 = fsub float %15, undef + %86 = fsub float %16, undef + %87 = fmul float %84, undef %88 = fmul float %85, undef %89 = fmul float %86, undef - %90 = fmul float %87, undef - %91 = fsub float %17, undef - %92 = fsub float %18, undef - %93 = fsub float %19, undef - %94 = fmul float %91, 0.000000e+00 + %90 = fsub float %17, undef + %91 = fsub float %18, undef + %92 = fsub float %19, undef + %93 = fmul float %90, 0.000000e+00 + %94 = fmul float %91, undef %95 = fmul float %92, undef - %96 = fmul float %93, undef - %97 = call float @llvm.minnum.f32(float %89, float %95) - %98 = call float @llvm.maxnum.f32(float %88, float %94) - %99 = call float @llvm.maxnum.f32(float %90, float %96) - %100 = call float @llvm.maxnum.f32(float undef, float %97) - %101 = call float @llvm.maxnum.f32(float %100, float undef) - %102 = call float @llvm.minnum.f32(float %98, float undef) - %103 = call float @llvm.minnum.f32(float %102, float %99) - %104 = fsub float %30, undef - %105 = fsub float %31, undef + %96 = call float @llvm.minnum.f32(float %88, float %94) + %97 = call float @llvm.maxnum.f32(float %87, float %93) + %98 = call float @llvm.maxnum.f32(float %89, float %95) + %99 = call float @llvm.maxnum.f32(float undef, float %96) + %100 = call float @llvm.maxnum.f32(float %99, float undef) + %101 = call float @llvm.minnum.f32(float %97, float undef) + %102 = call float @llvm.minnum.f32(float %101, float %98) + %103 = fsub float %30, undef + %104 = fsub float %31, undef + %105 = fmul float %103, 0.000000e+00 %106 = fmul float %104, 0.000000e+00 - %107 = fmul float %105, 0.000000e+00 - %108 = call float @llvm.minnum.f32(float undef, float %106) + %107 = call float @llvm.minnum.f32(float undef, float %105) + %108 = call float @llvm.maxnum.f32(float undef, float %106) %109 = call float @llvm.maxnum.f32(float undef, float %107) - %110 = call float @llvm.maxnum.f32(float undef, float %108) - %111 = call float @llvm.maxnum.f32(float %110, float undef) - %112 = call float @llvm.minnum.f32(float undef, float %109) - %113 = fsub float %32, undef - %114 = fsub float %33, undef - %115 = fsub float %34, undef - %116 = fmul float %113, 0.000000e+00 + %110 = call float @llvm.maxnum.f32(float %109, float undef) + %111 = call float @llvm.minnum.f32(float undef, float %108) + %112 = fsub float %32, undef + %113 = fsub float %33, undef + %114 = fsub float %34, undef + %115 = fmul float %112, 0.000000e+00 + %116 = fmul float %113, undef %117 = fmul float %114, undef - %118 = fmul float %115, undef - %119 = fsub float %35, undef - %120 = fsub float %36, undef - %121 = fsub float %37, undef + %118 = fsub float %35, undef + %119 = fsub float %36, undef + %120 = fsub float %37, undef + %121 = fmul float %118, undef %122 = fmul float %119, undef %123 = fmul float %120, undef - %124 = fmul float %121, undef + %124 = call float @llvm.minnum.f32(float %115, float %121) %125 = call float @llvm.minnum.f32(float %116, float %122) %126 = call float @llvm.minnum.f32(float %117, float %123) - %127 = call float @llvm.minnum.f32(float %118, float %124) - %128 = call float @llvm.maxnum.f32(float %125, float %126) - %129 = call float @llvm.maxnum.f32(float %128, float %127) - %130 = fsub float %38, undef - %131 = fsub float %39, undef - %132 = fsub float %40, undef - %133 = fmul float %130, 0.000000e+00 + %127 = call float @llvm.maxnum.f32(float %124, float %125) + %128 = call float @llvm.maxnum.f32(float %127, float %126) + %129 = fsub float %38, undef + %130 = fsub float %39, undef + %131 = fsub float %40, undef + %132 = fmul float %129, 0.000000e+00 + %133 = fmul float %130, undef %134 = fmul float %131, undef - %135 = fmul float %132, undef - %136 = fsub float %41, undef - %137 = fsub float %42, undef - %138 = fsub float %43, undef + %135 = fsub float %41, undef + %136 = fsub float %42, undef + %137 = fsub float %43, undef + %138 = fmul float %135, undef %139 = fmul float %136, undef %140 = fmul float %137, undef - %141 = fmul float %138, undef + %141 = call float @llvm.minnum.f32(float %132, float %138) %142 = call float @llvm.minnum.f32(float %133, float %139) %143 = call float @llvm.minnum.f32(float %134, float %140) - %144 = call float @llvm.minnum.f32(float %135, float %141) - %145 = call float @llvm.maxnum.f32(float %142, float %143) - %146 = call float @llvm.maxnum.f32(float %145, float %144) - %147 = fsub float %44, undef - %148 = fsub float %45, undef - %149 = fsub float %46, undef + %144 = call float @llvm.maxnum.f32(float %141, float %142) + %145 = call float @llvm.maxnum.f32(float %144, float %143) + %146 = fsub float %44, undef + %147 = fsub float %45, undef + %148 = fsub float %46, undef + %149 = fmul float %146, 0.000000e+00 %150 = fmul float %147, 0.000000e+00 - %151 = fmul float %148, 0.000000e+00 - %152 = fmul float %149, undef - %153 = fsub float %47, undef - %154 = fsub float %48, undef - %155 = fsub float %49, undef - %156 = fmul float %153, undef - %157 = fmul float %154, 0.000000e+00 - %158 = fmul float %155, undef + %151 = fmul float %148, undef + %152 = fsub float %47, undef + %153 = fsub float %48, undef + %154 = fsub float %49, undef + %155 = fmul float %152, undef + %156 = fmul float %153, 0.000000e+00 + %157 = fmul float %154, undef + %158 = call float @llvm.minnum.f32(float %149, float %155) %159 = call float @llvm.minnum.f32(float %150, float %156) %160 = call float @llvm.minnum.f32(float %151, float %157) - %161 = call float @llvm.minnum.f32(float %152, float %158) - %162 = call float @llvm.maxnum.f32(float %159, float %160) - %163 = call float @llvm.maxnum.f32(float %162, float %161) - %164 = fsub float %50, undef - %165 = fsub float %51, undef - %166 = fsub float %52, undef - %167 = fmul float %164, undef + %161 = call float @llvm.maxnum.f32(float %158, float %159) + %162 = call float @llvm.maxnum.f32(float %161, float %160) + %163 = fsub float %50, undef + %164 = fsub float %51, undef + %165 = fsub float %52, undef + %166 = fmul float %163, undef + %167 = fmul float %164, 0.000000e+00 %168 = fmul float %165, 0.000000e+00 - %169 = fmul float %166, 0.000000e+00 - %170 = fsub float %53, undef - %171 = fsub float %54, undef - %172 = fsub float %55, undef - %173 = fdiv float 1.000000e+00, %temp18.0 + %169 = fsub float %53, undef + %170 = fsub float %54, undef + %171 = fsub float %55, undef + %172 = fdiv float 1.000000e+00, %temp18.0 + %173 = fmul float %169, undef %174 = fmul float %170, undef - %175 = fmul float %171, undef - %176 = fmul float %172, %173 + %175 = fmul float %171, %172 + %176 = call float @llvm.minnum.f32(float %166, float %173) %177 = call float @llvm.minnum.f32(float %167, float %174) %178 = call float @llvm.minnum.f32(float %168, float %175) - %179 = call float @llvm.minnum.f32(float %169, float %176) - %180 = call float @llvm.maxnum.f32(float %177, float %178) - %181 = call float @llvm.maxnum.f32(float %180, float %179) - %182 = fsub float %62, undef - %183 = fsub float %63, undef - %184 = fsub float %64, undef - %185 = fmul float %182, 0.000000e+00 + %179 = call float @llvm.maxnum.f32(float %176, float %177) + %180 = call float @llvm.maxnum.f32(float %179, float %178) + %181 = fsub float %62, undef + %182 = fsub float %63, undef + %183 = fsub float %64, undef + %184 = fmul float %181, 0.000000e+00 + %185 = fmul float %182, undef %186 = fmul float %183, undef - %187 = fmul float %184, undef - %188 = fsub float %65, undef - %189 = fsub float %66, undef + %187 = fsub float %65, undef + %188 = fsub float %66, undef + %189 = fmul float %187, undef %190 = fmul float %188, undef - %191 = fmul float %189, undef + %191 = call float @llvm.maxnum.f32(float %184, float %189) %192 = call float @llvm.maxnum.f32(float %185, float %190) - %193 = call float @llvm.maxnum.f32(float %186, float %191) - %194 = call float @llvm.maxnum.f32(float %187, float undef) - %195 = call float @llvm.minnum.f32(float %192, float %193) - %196 = call float @llvm.minnum.f32(float %195, float %194) - %.temp292.7 = select i1 undef, float %163, float undef - %temp292.9 = select i1 false, float %181, float %.temp292.7 + %193 = call float @llvm.maxnum.f32(float %186, float undef) + %194 = call float @llvm.minnum.f32(float %191, float %192) + %195 = call float @llvm.minnum.f32(float %194, float %193) + %.temp292.7 = select i1 undef, float %162, float undef + %temp292.9 = select i1 false, float %180, float %.temp292.7 %.temp292.9 = select i1 undef, float undef, float %temp292.9 - %197 = fcmp ogt float undef, 0.000000e+00 - %198 = fcmp olt float undef, %196 - %199 = and i1 %197, %198 - %200 = fcmp olt float undef, %.temp292.9 - %201 = and i1 %199, %200 - %temp292.11 = select i1 %201, float undef, float %.temp292.9 - br i1 undef, label %IF2565, label %ELSE2566 + %196 = fcmp ogt float undef, 0.000000e+00 + %197 = fcmp olt float undef, %195 + %198 = and i1 %196, %197 + %199 = fcmp olt float undef, %.temp292.9 + %200 = and i1 %198, %199 + %temp292.11 = select i1 %200, float undef, float %.temp292.9 + %tid0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 + %cmp0 = icmp eq i32 %tid0, 0 + br i1 %cmp0, label %IF2565, label %ELSE2566 IF2565: ; preds = %ENDIF - br i1 false, label %ENDIF2582, label %ELSE2584 + %tid1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 + %cmp1 = icmp eq i32 %tid1, 0 + br i1 %cmp1, label %ENDIF2582, label %ELSE2584 ELSE2566: ; preds = %ENDIF - %202 = fcmp oeq float %temp292.11, 1.000000e+04 - br i1 %202, label %ENDLOOP, label %ELSE2593 + %tid2 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 + %tidf = bitcast i32 %tid2 to float + %201 = fcmp oeq float %temp292.11, %tidf + br i1 %201, label %ENDLOOP, label %ELSE2593 ENDIF2564: ; preds = %ENDIF2594, %ENDIF2588 %temp894.1 = phi float [ undef, %ENDIF2588 ], [ %temp894.2, %ENDIF2594 ] - %temp18.1 = phi float [ %219, %ENDIF2588 ], [ undef, %ENDIF2594 ] - %203 = fsub float %5, undef - %204 = fmul float %203, undef - %205 = call float @llvm.maxnum.f32(float undef, float %204) + %temp18.1 = phi float [ %218, %ENDIF2588 ], [ undef, %ENDIF2594 ] + %202 = fsub float %5, undef + %203 = fmul float %202, undef + %204 = call float @llvm.maxnum.f32(float undef, float %203) + %205 = call float @llvm.minnum.f32(float %204, float undef) %206 = call float @llvm.minnum.f32(float %205, float undef) - %207 = call float @llvm.minnum.f32(float %206, float undef) - %208 = fcmp ogt float undef, 0.000000e+00 - %209 = fcmp olt float undef, 1.000000e+00 - %210 = and i1 %208, %209 - %211 = fcmp olt float undef, %207 - %212 = and i1 %210, %211 - br i1 %212, label %ENDIF2795, label %ELSE2797 + %207 = fcmp ogt float undef, 0.000000e+00 + %208 = fcmp olt float undef, 1.000000e+00 + %209 = and i1 %207, %208 + %tid3 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 + %tidf3 = bitcast i32 %tid3 to float + %210 = fcmp olt float %tidf3, %206 + %211 = and i1 %209, %210 + br i1 %211, label %ENDIF2795, label %ELSE2797 ELSE2584: ; preds = %IF2565 br label %ENDIF2582 ENDIF2582: ; preds = %ELSE2584, %IF2565 - %213 = fadd float %1, undef - %214 = fadd float 0.000000e+00, %213 - %215 = call float @llvm.AMDIL.fraction.(float %214) - br i1 undef, label %IF2589, label %ELSE2590 + %212 = fadd float %1, undef + %213 = fadd float 0.000000e+00, %212 + %floor = call float @llvm.floor.f32(float %213) + %214 = fsub float %213, %floor + %tid4 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 + %cmp4 = icmp eq i32 %tid4, 0 + br i1 %cmp4, label %IF2589, label %ELSE2590 IF2589: ; preds = %ENDIF2582 br label %ENDIF2588 @@ -266,61 +280,61 @@ ELSE2590: ; preds = %ENDIF2582 br label %ENDIF2588 ENDIF2588: ; preds = %ELSE2590, %IF2589 - %216 = fsub float 1.000000e+00, %215 - %217 = call float @llvm.sqrt.f32(float %216) - %218 = fmul float %217, undef - %219 = fadd float %218, undef + %215 = fsub float 1.000000e+00, %214 + %216 = call float @llvm.sqrt.f32(float %215) + %217 = fmul float %216, undef + %218 = fadd float %217, undef br label %ENDIF2564 ELSE2593: ; preds = %ELSE2566 - %220 = fcmp oeq float %temp292.11, %82 - %221 = fcmp olt float %82, %84 - %222 = and i1 %220, %221 - br i1 %222, label %ENDIF2594, label %ELSE2596 + %219 = fcmp oeq float %temp292.11, %81 + %220 = fcmp olt float %81, %83 + %221 = and i1 %219, %220 + br i1 %221, label %ENDIF2594, label %ELSE2596 ELSE2596: ; preds = %ELSE2593 - %223 = fcmp oeq float %temp292.11, %101 - %224 = fcmp olt float %101, %103 - %225 = and i1 %223, %224 - br i1 %225, label %ENDIF2594, label %ELSE2632 + %222 = fcmp oeq float %temp292.11, %100 + %223 = fcmp olt float %100, %102 + %224 = and i1 %222, %223 + br i1 %224, label %ENDIF2594, label %ELSE2632 ENDIF2594: ; preds = %ELSE2788, %ELSE2785, %ELSE2782, %ELSE2779, %IF2775, %ELSE2761, %ELSE2758, %IF2757, %ELSE2704, %ELSE2686, %ELSE2671, %ELSE2668, %IF2667, %ELSE2632, %ELSE2596, %ELSE2593 %temp894.2 = phi float [ 0.000000e+00, %IF2667 ], [ 0.000000e+00, %ELSE2671 ], [ 0.000000e+00, %IF2757 ], [ 0.000000e+00, %ELSE2761 ], [ %temp894.0, %ELSE2758 ], [ 0.000000e+00, %IF2775 ], [ 0.000000e+00, %ELSE2779 ], [ 0.000000e+00, %ELSE2782 ], [ %.2848, %ELSE2788 ], [ 0.000000e+00, %ELSE2785 ], [ 0.000000e+00, %ELSE2593 ], [ 0.000000e+00, %ELSE2632 ], [ 0.000000e+00, %ELSE2704 ], [ 0.000000e+00, %ELSE2686 ], [ 0.000000e+00, %ELSE2668 ], [ 0.000000e+00, %ELSE2596 ] - %226 = fmul float %temp894.2, undef + %225 = fmul float %temp894.2, undef br label %ENDIF2564 ELSE2632: ; preds = %ELSE2596 br i1 undef, label %ENDIF2594, label %ELSE2650 ELSE2650: ; preds = %ELSE2632 - %227 = fcmp oeq float %temp292.11, %111 - %228 = fcmp olt float %111, %112 - %229 = and i1 %227, %228 - br i1 %229, label %IF2667, label %ELSE2668 + %226 = fcmp oeq float %temp292.11, %110 + %227 = fcmp olt float %110, %111 + %228 = and i1 %226, %227 + br i1 %228, label %IF2667, label %ELSE2668 IF2667: ; preds = %ELSE2650 br i1 undef, label %ENDIF2594, label %ELSE2671 ELSE2668: ; preds = %ELSE2650 - %230 = fcmp oeq float %temp292.11, %129 - %231 = fcmp olt float %129, undef - %232 = and i1 %230, %231 - br i1 %232, label %ENDIF2594, label %ELSE2686 + %229 = fcmp oeq float %temp292.11, %128 + %230 = fcmp olt float %128, undef + %231 = and i1 %229, %230 + br i1 %231, label %ENDIF2594, label %ELSE2686 ELSE2671: ; preds = %IF2667 br label %ENDIF2594 ELSE2686: ; preds = %ELSE2668 - %233 = fcmp oeq float %temp292.11, %146 - %234 = fcmp olt float %146, undef - %235 = and i1 %233, %234 - br i1 %235, label %ENDIF2594, label %ELSE2704 + %232 = fcmp oeq float %temp292.11, %145 + %233 = fcmp olt float %145, undef + %234 = and i1 %232, %233 + br i1 %234, label %ENDIF2594, label %ELSE2704 ELSE2704: ; preds = %ELSE2686 - %236 = fcmp oeq float %temp292.11, %181 - %237 = fcmp olt float %181, undef - %238 = and i1 %236, %237 - br i1 %238, label %ENDIF2594, label %ELSE2740 + %235 = fcmp oeq float %temp292.11, %180 + %236 = fcmp olt float %180, undef + %237 = and i1 %235, %236 + br i1 %237, label %ENDIF2594, label %ELSE2740 ELSE2740: ; preds = %ELSE2704 br i1 undef, label %IF2757, label %ELSE2758 @@ -335,8 +349,8 @@ ELSE2761: ; preds = %IF2757 br label %ENDIF2594 IF2775: ; preds = %ELSE2758 - %239 = fcmp olt float undef, undef - br i1 %239, label %ENDIF2594, label %ELSE2779 + %238 = fcmp olt float undef, undef + br i1 %238, label %ENDIF2594, label %ELSE2779 ELSE2779: ; preds = %IF2775 br i1 undef, label %ENDIF2594, label %ELSE2782 @@ -345,39 +359,39 @@ ELSE2782: ; preds = %ELSE2779 br i1 undef, label %ENDIF2594, label %ELSE2785 ELSE2785: ; preds = %ELSE2782 - %240 = fcmp olt float undef, 0.000000e+00 - br i1 %240, label %ENDIF2594, label %ELSE2788 + %239 = fcmp olt float undef, 0.000000e+00 + br i1 %239, label %ENDIF2594, label %ELSE2788 ELSE2788: ; preds = %ELSE2785 - %241 = fcmp olt float 0.000000e+00, undef - %.2848 = select i1 %241, float -1.000000e+00, float 1.000000e+00 + %240 = fcmp olt float 0.000000e+00, undef + %.2848 = select i1 %240, float -1.000000e+00, float 1.000000e+00 br label %ENDIF2594 ELSE2797: ; preds = %ENDIF2564 - %242 = fsub float %8, undef - %243 = fsub float %9, undef - %244 = fsub float %10, undef + %241 = fsub float %8, undef + %242 = fsub float %9, undef + %243 = fsub float %10, undef + %244 = fmul float %241, undef %245 = fmul float %242, undef %246 = fmul float %243, undef - %247 = fmul float %244, undef - %248 = fsub float %11, undef - %249 = fsub float %12, undef - %250 = fsub float %13, undef + %247 = fsub float %11, undef + %248 = fsub float %12, undef + %249 = fsub float %13, undef + %250 = fmul float %247, undef %251 = fmul float %248, undef %252 = fmul float %249, undef - %253 = fmul float %250, undef + %253 = call float @llvm.minnum.f32(float %244, float %250) %254 = call float @llvm.minnum.f32(float %245, float %251) - %255 = call float @llvm.minnum.f32(float %246, float %252) - %256 = call float @llvm.maxnum.f32(float %247, float %253) - %257 = call float @llvm.maxnum.f32(float %254, float %255) - %258 = call float @llvm.maxnum.f32(float %257, float undef) - %259 = call float @llvm.minnum.f32(float undef, float %256) - %260 = fcmp ogt float %258, 0.000000e+00 - %261 = fcmp olt float %258, 1.000000e+00 - %262 = and i1 %260, %261 - %263 = fcmp olt float %258, %259 - %264 = and i1 %262, %263 - br i1 %264, label %ENDIF2795, label %ELSE2800 + %255 = call float @llvm.maxnum.f32(float %246, float %252) + %256 = call float @llvm.maxnum.f32(float %253, float %254) + %257 = call float @llvm.maxnum.f32(float %256, float undef) + %258 = call float @llvm.minnum.f32(float undef, float %255) + %259 = fcmp ogt float %257, 0.000000e+00 + %260 = fcmp olt float %257, 1.000000e+00 + %261 = and i1 %259, %260 + %262 = fcmp olt float %257, %258 + %263 = and i1 %261, %262 + br i1 %263, label %ENDIF2795, label %ELSE2800 ENDIF2795: ; preds = %ELSE2824, %ELSE2821, %ELSE2818, %ELSE2815, %ELSE2812, %ELSE2809, %ELSE2806, %ELSE2803, %ELSE2800, %ELSE2797, %ENDIF2564 br label %LOOP @@ -386,53 +400,53 @@ ELSE2800: ; preds = %ELSE2797 br i1 undef, label %ENDIF2795, label %ELSE2803 ELSE2803: ; preds = %ELSE2800 - %265 = fsub float %20, undef - %266 = fsub float %21, undef - %267 = fsub float %22, undef + %264 = fsub float %20, undef + %265 = fsub float %21, undef + %266 = fsub float %22, undef + %267 = fmul float %264, undef %268 = fmul float %265, undef - %269 = fmul float %266, undef - %270 = fmul float %267, 0.000000e+00 - %271 = fsub float %23, undef - %272 = fsub float %24, undef - %273 = fsub float %25, undef + %269 = fmul float %266, 0.000000e+00 + %270 = fsub float %23, undef + %271 = fsub float %24, undef + %272 = fsub float %25, undef + %273 = fmul float %270, undef %274 = fmul float %271, undef %275 = fmul float %272, undef - %276 = fmul float %273, undef - %277 = call float @llvm.minnum.f32(float %268, float %274) + %276 = call float @llvm.minnum.f32(float %267, float %273) + %277 = call float @llvm.maxnum.f32(float %268, float %274) %278 = call float @llvm.maxnum.f32(float %269, float %275) - %279 = call float @llvm.maxnum.f32(float %270, float %276) - %280 = call float @llvm.maxnum.f32(float %277, float undef) - %281 = call float @llvm.maxnum.f32(float %280, float undef) - %282 = call float @llvm.minnum.f32(float undef, float %278) - %283 = call float @llvm.minnum.f32(float %282, float %279) - %284 = fcmp ogt float %281, 0.000000e+00 - %285 = fcmp olt float %281, 1.000000e+00 - %286 = and i1 %284, %285 - %287 = fcmp olt float %281, %283 - %288 = and i1 %286, %287 - br i1 %288, label %ENDIF2795, label %ELSE2806 + %279 = call float @llvm.maxnum.f32(float %276, float undef) + %280 = call float @llvm.maxnum.f32(float %279, float undef) + %281 = call float @llvm.minnum.f32(float undef, float %277) + %282 = call float @llvm.minnum.f32(float %281, float %278) + %283 = fcmp ogt float %280, 0.000000e+00 + %284 = fcmp olt float %280, 1.000000e+00 + %285 = and i1 %283, %284 + %286 = fcmp olt float %280, %282 + %287 = and i1 %285, %286 + br i1 %287, label %ENDIF2795, label %ELSE2806 ELSE2806: ; preds = %ELSE2803 - %289 = fsub float %26, undef - %290 = fsub float %27, undef - %291 = fsub float %28, undef - %292 = fmul float %289, undef - %293 = fmul float %290, 0.000000e+00 - %294 = fmul float %291, undef - %295 = fsub float %29, undef - %296 = fmul float %295, undef - %297 = call float @llvm.minnum.f32(float %292, float %296) - %298 = call float @llvm.minnum.f32(float %293, float undef) - %299 = call float @llvm.maxnum.f32(float %294, float undef) - %300 = call float @llvm.maxnum.f32(float %297, float %298) - %301 = call float @llvm.maxnum.f32(float %300, float undef) - %302 = call float @llvm.minnum.f32(float undef, float %299) - %303 = fcmp ogt float %301, 0.000000e+00 - %304 = fcmp olt float %301, 1.000000e+00 - %305 = and i1 %303, %304 - %306 = fcmp olt float %301, %302 - %307 = and i1 %305, %306 - br i1 %307, label %ENDIF2795, label %ELSE2809 + %288 = fsub float %26, undef + %289 = fsub float %27, undef + %290 = fsub float %28, undef + %291 = fmul float %288, undef + %292 = fmul float %289, 0.000000e+00 + %293 = fmul float %290, undef + %294 = fsub float %29, undef + %295 = fmul float %294, undef + %296 = call float @llvm.minnum.f32(float %291, float %295) + %297 = call float @llvm.minnum.f32(float %292, float undef) + %298 = call float @llvm.maxnum.f32(float %293, float undef) + %299 = call float @llvm.maxnum.f32(float %296, float %297) + %300 = call float @llvm.maxnum.f32(float %299, float undef) + %301 = call float @llvm.minnum.f32(float undef, float %298) + %302 = fcmp ogt float %300, 0.000000e+00 + %303 = fcmp olt float %300, 1.000000e+00 + %304 = and i1 %302, %303 + %305 = fcmp olt float %300, %301 + %306 = and i1 %304, %305 + br i1 %306, label %ENDIF2795, label %ELSE2809 ELSE2809: ; preds = %ELSE2806 br i1 undef, label %ENDIF2795, label %ELSE2812 @@ -447,40 +461,42 @@ ELSE2818: ; preds = %ELSE2815 br i1 undef, label %ENDIF2795, label %ELSE2821 ELSE2821: ; preds = %ELSE2818 - %308 = fsub float %56, undef - %309 = fsub float %57, undef - %310 = fsub float %58, undef - %311 = fmul float %308, undef - %312 = fmul float %309, 0.000000e+00 - %313 = fmul float %310, undef - %314 = fsub float %59, undef - %315 = fsub float %60, undef - %316 = fsub float %61, undef + %307 = fsub float %56, undef + %308 = fsub float %57, undef + %309 = fsub float %58, undef + %310 = fmul float %307, undef + %311 = fmul float %308, 0.000000e+00 + %312 = fmul float %309, undef + %313 = fsub float %59, undef + %314 = fsub float %60, undef + %315 = fsub float %61, undef + %316 = fmul float %313, undef %317 = fmul float %314, undef %318 = fmul float %315, undef - %319 = fmul float %316, undef + %319 = call float @llvm.maxnum.f32(float %310, float %316) %320 = call float @llvm.maxnum.f32(float %311, float %317) %321 = call float @llvm.maxnum.f32(float %312, float %318) - %322 = call float @llvm.maxnum.f32(float %313, float %319) - %323 = call float @llvm.minnum.f32(float %320, float %321) - %324 = call float @llvm.minnum.f32(float %323, float %322) - %325 = fcmp ogt float undef, 0.000000e+00 - %326 = fcmp olt float undef, 1.000000e+00 - %327 = and i1 %325, %326 - %328 = fcmp olt float undef, %324 - %329 = and i1 %327, %328 - br i1 %329, label %ENDIF2795, label %ELSE2824 + %322 = call float @llvm.minnum.f32(float %319, float %320) + %323 = call float @llvm.minnum.f32(float %322, float %321) + %324 = fcmp ogt float undef, 0.000000e+00 + %325 = fcmp olt float undef, 1.000000e+00 + %326 = and i1 %324, %325 + %327 = fcmp olt float undef, %323 + %328 = and i1 %326, %327 + br i1 %328, label %ENDIF2795, label %ELSE2824 ELSE2824: ; preds = %ELSE2821 %.2849 = select i1 undef, float 0.000000e+00, float 1.000000e+00 br label %ENDIF2795 } +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 + ; Function Attrs: nounwind readnone declare float @llvm.SI.load.const(<16 x i8>, i32) #1 -; Function Attrs: readnone -declare float @llvm.AMDIL.fraction.(float) #2 +; Function Attrs: nounwind readnone +declare float @llvm.floor.f32(float) #1 ; Function Attrs: nounwind readnone declare float @llvm.sqrt.f32(float) #1 @@ -491,11 +507,7 @@ declare float @llvm.minnum.f32(float, float) #1 ; Function Attrs: nounwind readnone declare float @llvm.maxnum.f32(float, float) #1 -; Function Attrs: readnone -declare float @llvm.AMDGPU.lrp(float, float, float) #2 - declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -attributes #2 = { readnone } diff --git a/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll b/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll new file mode 100644 index 000000000000..5171406469ab --- /dev/null +++ b/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll @@ -0,0 +1,60 @@ +; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck %s + +; Make sure this doesn't crash. +; CHECK: {{^}}test: +; Make sure we are handling hazards correctly. +; CHECK: buffer_load_dword [[VHI:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:12 +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: v_readfirstlane_b32 s[[HI:[0-9]+]], [[VHI]] +; CHECK-NEXT: s_nop 4 +; CHECK-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0 +; CHECK: s_endpgm +define void @test(i32 addrspace(1)* %out, i32 %in) { + call void asm sideeffect "", "~{SGPR0_SGPR1_SGPR2_SGPR3_SGPR4_SGPR5_SGPR6_SGPR7}" () + call void asm sideeffect "", "~{SGPR8_SGPR9_SGPR10_SGPR11_SGPR12_SGPR13_SGPR14_SGPR15}" () + call void asm sideeffect "", "~{SGPR16_SGPR17_SGPR18_SGPR19_SGPR20_SGPR21_SGPR22_SGPR23}" () + call void asm sideeffect "", "~{SGPR24_SGPR25_SGPR26_SGPR27_SGPR28_SGPR29_SGPR30_SGPR31}" () + call void asm sideeffect "", "~{SGPR32_SGPR33_SGPR34_SGPR35_SGPR36_SGPR37_SGPR38_SGPR39}" () + call void asm sideeffect "", "~{SGPR40_SGPR41_SGPR42_SGPR43_SGPR44_SGPR45_SGPR46_SGPR47}" () + call void asm sideeffect "", "~{SGPR48_SGPR49_SGPR50_SGPR51_SGPR52_SGPR53_SGPR54_SGPR55}" () + call void asm sideeffect "", "~{SGPR56_SGPR57_SGPR58_SGPR59_SGPR60_SGPR61_SGPR62_SGPR63}" () + call void asm sideeffect "", "~{SGPR64_SGPR65_SGPR66_SGPR67_SGPR68_SGPR69_SGPR70_SGPR71}" () + call void asm sideeffect "", "~{SGPR72_SGPR73_SGPR74_SGPR75_SGPR76_SGPR77_SGPR78_SGPR79}" () + call void asm sideeffect "", "~{SGPR80_SGPR81_SGPR82_SGPR83_SGPR84_SGPR85_SGPR86_SGPR87}" () + call void asm sideeffect "", "~{SGPR88_SGPR89_SGPR90_SGPR91_SGPR92_SGPR93_SGPR94_SGPR95}" () + call void asm sideeffect "", "~{VGPR0_VGPR1_VGPR2_VGPR3_VGPR4_VGPR5_VGPR6_VGPR7}" () + call void asm sideeffect "", "~{VGPR8_VGPR9_VGPR10_VGPR11_VGPR12_VGPR13_VGPR14_VGPR15}" () + call void asm sideeffect "", "~{VGPR16_VGPR17_VGPR18_VGPR19_VGPR20_VGPR21_VGPR22_VGPR23}" () + call void asm sideeffect "", "~{VGPR24_VGPR25_VGPR26_VGPR27_VGPR28_VGPR29_VGPR30_VGPR31}" () + call void asm sideeffect "", "~{VGPR32_VGPR33_VGPR34_VGPR35_VGPR36_VGPR37_VGPR38_VGPR39}" () + call void asm sideeffect "", "~{VGPR40_VGPR41_VGPR42_VGPR43_VGPR44_VGPR45_VGPR46_VGPR47}" () + call void asm sideeffect "", "~{VGPR48_VGPR49_VGPR50_VGPR51_VGPR52_VGPR53_VGPR54_VGPR55}" () + call void asm sideeffect "", "~{VGPR56_VGPR57_VGPR58_VGPR59_VGPR60_VGPR61_VGPR62_VGPR63}" () + call void asm sideeffect "", "~{VGPR64_VGPR65_VGPR66_VGPR67_VGPR68_VGPR69_VGPR70_VGPR71}" () + call void asm sideeffect "", "~{VGPR72_VGPR73_VGPR74_VGPR75_VGPR76_VGPR77_VGPR78_VGPR79}" () + call void asm sideeffect "", "~{VGPR80_VGPR81_VGPR82_VGPR83_VGPR84_VGPR85_VGPR86_VGPR87}" () + call void asm sideeffect "", "~{VGPR88_VGPR89_VGPR90_VGPR91_VGPR92_VGPR93_VGPR94_VGPR95}" () + call void asm sideeffect "", "~{VGPR96_VGPR97_VGPR98_VGPR99_VGPR100_VGPR101_VGPR102_VGPR103}" () + call void asm sideeffect "", "~{VGPR104_VGPR105_VGPR106_VGPR107_VGPR108_VGPR109_VGPR110_VGPR111}" () + call void asm sideeffect "", "~{VGPR112_VGPR113_VGPR114_VGPR115_VGPR116_VGPR117_VGPR118_VGPR119}" () + call void asm sideeffect "", "~{VGPR120_VGPR121_VGPR122_VGPR123_VGPR124_VGPR125_VGPR126_VGPR127}" () + call void asm sideeffect "", "~{VGPR128_VGPR129_VGPR130_VGPR131_VGPR132_VGPR133_VGPR134_VGPR135}" () + call void asm sideeffect "", "~{VGPR136_VGPR137_VGPR138_VGPR139_VGPR140_VGPR141_VGPR142_VGPR143}" () + call void asm sideeffect "", "~{VGPR144_VGPR145_VGPR146_VGPR147_VGPR148_VGPR149_VGPR150_VGPR151}" () + call void asm sideeffect "", "~{VGPR152_VGPR153_VGPR154_VGPR155_VGPR156_VGPR157_VGPR158_VGPR159}" () + call void asm sideeffect "", "~{VGPR160_VGPR161_VGPR162_VGPR163_VGPR164_VGPR165_VGPR166_VGPR167}" () + call void asm sideeffect "", "~{VGPR168_VGPR169_VGPR170_VGPR171_VGPR172_VGPR173_VGPR174_VGPR175}" () + call void asm sideeffect "", "~{VGPR176_VGPR177_VGPR178_VGPR179_VGPR180_VGPR181_VGPR182_VGPR183}" () + call void asm sideeffect "", "~{VGPR184_VGPR185_VGPR186_VGPR187_VGPR188_VGPR189_VGPR190_VGPR191}" () + call void asm sideeffect "", "~{VGPR192_VGPR193_VGPR194_VGPR195_VGPR196_VGPR197_VGPR198_VGPR199}" () + call void asm sideeffect "", "~{VGPR200_VGPR201_VGPR202_VGPR203_VGPR204_VGPR205_VGPR206_VGPR207}" () + call void asm sideeffect "", "~{VGPR208_VGPR209_VGPR210_VGPR211_VGPR212_VGPR213_VGPR214_VGPR215}" () + call void asm sideeffect "", "~{VGPR216_VGPR217_VGPR218_VGPR219_VGPR220_VGPR221_VGPR222_VGPR223}" () + call void asm sideeffect "", "~{VGPR224_VGPR225_VGPR226_VGPR227_VGPR228_VGPR229_VGPR230_VGPR231}" () + call void asm sideeffect "", "~{VGPR232_VGPR233_VGPR234_VGPR235_VGPR236_VGPR237_VGPR238_VGPR239}" () + call void asm sideeffect "", "~{VGPR240_VGPR241_VGPR242_VGPR243_VGPR244_VGPR245_VGPR246_VGPR247}" () + call void asm sideeffect "", "~{VGPR248_VGPR249_VGPR250_VGPR251_VGPR252_VGPR253_VGPR254_VGPR255}" () + + store i32 %in, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll b/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll index bc766dbcac67..0e9618523e32 100644 --- a/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll +++ b/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll @@ -2,7 +2,7 @@ declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) declare void @llvm.SI.tbuffer.store.v4i32(<16 x i8>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) -declare void @llvm.AMDGPU.barrier.local() #2 +declare void @llvm.amdgcn.s.barrier() #1 @stored_lds_ptr = addrspace(3) global i32 addrspace(3)* undef, align 4 @@ -10,14 +10,13 @@ declare void @llvm.AMDGPU.barrier.local() #2 @stored_global_ptr = addrspace(3) global i32 addrspace(1)* undef, align 8 ; FUNC-LABEL: @reorder_local_load_global_store_local_load -; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4 -; CI-NEXT: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8 +; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3 ; CI: buffer_store_dword define void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4 %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3 %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4 @@ -32,12 +31,12 @@ define void @reorder_local_load_global_store_local_load(i32 addrspace(1)* %out, ; FUNC-LABEL: @no_reorder_local_load_volatile_global_store_local_load ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4 ; CI: buffer_store_dword -; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8 +; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12 define void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4 %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3 %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4 store volatile i32 99, i32 addrspace(1)* %gptr, align 4 @@ -51,17 +50,17 @@ define void @no_reorder_local_load_volatile_global_store_local_load(i32 addrspac ; FUNC-LABEL: @no_reorder_barrier_local_load_global_store_local_load ; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:4 -; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:8 +; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12 ; CI: buffer_store_dword define void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4 %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3 %tmp1 = load i32, i32 addrspace(3)* %ptr1, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4 - call void @llvm.AMDGPU.barrier.local() #2 + call void @llvm.amdgcn.s.barrier() #1 %tmp2 = load i32, i32 addrspace(3)* %ptr2, align 4 %add = add nsw i32 %tmp1, %tmp2 @@ -70,19 +69,18 @@ define void @no_reorder_barrier_local_load_global_store_local_load(i32 addrspace ret void } -; Technically we could reorder these, but just comparing the -; instruction type of the load is insufficient. - -; FUNC-LABEL: @no_reorder_constant_load_global_store_constant_load -; CI: buffer_load_dword -; CI: buffer_store_dword -; CI: buffer_load_dword +; FUNC-LABEL: @reorder_constant_load_global_store_constant_load +; CI-DAG: buffer_store_dword +; CI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} +; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} +; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 +; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; CI: buffer_store_dword -define void @no_reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { +define void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { %ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8 %ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3 %tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4 @@ -95,15 +93,17 @@ define void @no_reorder_constant_load_global_store_constant_load(i32 addrspace(1 } ; FUNC-LABEL: @reorder_constant_load_local_store_constant_load -; CI: buffer_load_dword -; CI: buffer_load_dword +; CI: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} +; CI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} +; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 +; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; CI: ds_write_b32 ; CI: buffer_store_dword define void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 { %ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8 %ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3 %tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4 store i32 99, i32 addrspace(3)* %lptr, align 4 @@ -142,7 +142,7 @@ define void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 ; CI: buffer_store_dword define void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr, i32 addrspace(1)* %ptr0) #0 { %ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 1 - %ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 2 + %ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i64 3 %tmp1 = load i32, i32 addrspace(1)* %ptr1, align 4 store i32 99, i32 addrspace(3)* %lptr, align 4 @@ -155,17 +155,15 @@ define void @reorder_global_load_local_store_global_load(i32 addrspace(1)* %out, } ; FUNC-LABEL: @reorder_local_offsets -; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:400 -; CI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:404 -; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:12 +; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:100 offset1:102 ; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:400 -; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:404 +; CI: ds_write_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:408 ; CI: buffer_store_dword ; CI: s_endpgm define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(3)* noalias nocapture %ptr0) #0 { %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 3 %ptr2 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 100 - %ptr3 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 101 + %ptr3 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 102 store i32 123, i32 addrspace(3)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(3)* %ptr2, align 4 @@ -181,18 +179,17 @@ define void @reorder_local_offsets(i32 addrspace(1)* nocapture %out, i32 addrspa } ; FUNC-LABEL: @reorder_global_offsets -; CI: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400 -; CI: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:404 -; CI: buffer_store_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12 -; CI: buffer_load_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12 -; CI: buffer_store_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400 -; CI: buffer_store_dword {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:404 -; CI: buffer_store_dword +; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400 +; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12 +; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408 +; CI: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:12 +; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:400 +; CI: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:408 ; CI: s_endpgm define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* noalias nocapture readnone %gptr, i32 addrspace(1)* noalias nocapture %ptr0) #0 { %ptr1 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 3 %ptr2 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 100 - %ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 101 + %ptr3 = getelementptr inbounds i32, i32 addrspace(1)* %ptr0, i32 102 store i32 123, i32 addrspace(1)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(1)* %ptr2, align 4 @@ -211,7 +208,7 @@ define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrsp ; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x4 ; XCI: TBUFFER_STORE_FORMAT ; XCI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}}, 0x8 -; define void @reorder_local_load_tbuffer_store_local_load(i32 addrspace(1)* %out, i32 %a1, i32 %vaddr) #1 { +; define amdgpu_vs void @reorder_local_load_tbuffer_store_local_load(i32 addrspace(1)* %out, i32 %a1, i32 %vaddr) #0 { ; %ptr0 = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(3)* @stored_lds_ptr, align 4 ; %ptr1 = getelementptr inbounds i32, i32 addrspace(3)* %ptr0, i32 1 @@ -232,6 +229,5 @@ define void @reorder_global_offsets(i32 addrspace(1)* nocapture %out, i32 addrsp ; ret void ; } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" } -attributes #1 = { "ShaderType"="1" nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" } -attributes #2 = { nounwind convergent } +attributes #0 = { nounwind } +attributes #1 = { nounwind convergent } diff --git a/test/CodeGen/AMDGPU/si-vector-hang.ll b/test/CodeGen/AMDGPU/si-vector-hang.ll index bd427dd3ed46..c7d85a0340cc 100644 --- a/test/CodeGen/AMDGPU/si-vector-hang.ll +++ b/test/CodeGen/AMDGPU/si-vector-hang.ll @@ -90,7 +90,7 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } !opencl.kernels = !{!0, !1, !2, !3, !4, !5, !6, !7, !8} diff --git a/test/CodeGen/AMDGPU/sign_extend.ll b/test/CodeGen/AMDGPU/sign_extend.ll index 06bee114c23a..30e6bd1e78f2 100644 --- a/test/CodeGen/AMDGPU/sign_extend.ll +++ b/test/CodeGen/AMDGPU/sign_extend.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; SI-LABEL: {{^}}s_sext_i1_to_i32: -; SI: v_cndmask_b32_e64 -; SI: s_endpgm +; GCN-LABEL: {{^}}s_sext_i1_to_i32: +; GCN: v_cndmask_b32_e64 +; GCN: s_endpgm define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %sext = sext i1 %cmp to i32 @@ -11,9 +11,9 @@ define void @s_sext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { ret void } -; SI-LABEL: {{^}}test_s_sext_i32_to_i64: -; SI: s_ashr_i32 -; SI: s_endpg +; GCN-LABEL: {{^}}test_s_sext_i32_to_i64: +; GCN: s_ashr_i32 +; GCN: s_endpg define void @test_s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) nounwind { entry: %mul = mul i32 %a, %b @@ -23,11 +23,11 @@ entry: ret void } -; SI-LABEL: {{^}}s_sext_i1_to_i64: -; SI: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc -; SI: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]] -; SI: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}} -; SI: s_endpgm +; GCN-LABEL: {{^}}s_sext_i1_to_i64: +; GCN: v_cndmask_b32_e64 v[[LOREG:[0-9]+]], 0, -1, vcc +; GCN: v_mov_b32_e32 v[[HIREG:[0-9]+]], v[[LOREG]] +; GCN: buffer_store_dwordx2 v{{\[}}[[LOREG]]:[[HIREG]]{{\]}} +; GCN: s_endpgm define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %cmp = icmp eq i32 %a, %b %sext = sext i1 %cmp to i64 @@ -35,18 +35,18 @@ define void @s_sext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) nounwind { ret void } -; SI-LABEL: {{^}}s_sext_i32_to_i64: -; SI: s_ashr_i32 -; SI: s_endpgm +; GCN-LABEL: {{^}}s_sext_i32_to_i64: +; GCN: s_ashr_i32 +; GCN: s_endpgm define void @s_sext_i32_to_i64(i64 addrspace(1)* %out, i32 %a) nounwind { %sext = sext i32 %a to i64 store i64 %sext, i64 addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}v_sext_i32_to_i64: -; SI: v_ashr -; SI: s_endpgm +; GCN-LABEL: {{^}}v_sext_i32_to_i64: +; GCN: v_ashr +; GCN: s_endpgm define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %val = load i32, i32 addrspace(1)* %in, align 4 %sext = sext i32 %val to i64 @@ -54,10 +54,112 @@ define void @v_sext_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %in) no ret void } -; SI-LABEL: {{^}}s_sext_i16_to_i64: -; SI: s_endpgm +; GCN-LABEL: {{^}}s_sext_i16_to_i64: +; GCN: s_endpgm define void @s_sext_i16_to_i64(i64 addrspace(1)* %out, i16 %a) nounwind { %sext = sext i16 %a to i64 store i64 %sext, i64 addrspace(1)* %out, align 8 ret void } + +; GCN-LABEL: {{^}}s_sext_v4i8_to_v4i32: +; GCN: s_load_dword [[VAL:s[0-9]+]] +; GCN-DAG: s_sext_i32_i8 [[EXT0:s[0-9]+]], [[VAL]] +; GCN-DAG: s_bfe_i32 [[EXT1:s[0-9]+]], [[VAL]], 0x80008 +; GCN-DAG: s_bfe_i32 [[EXT2:s[0-9]+]], [[VAL]], 0x80010 +; GCN-DAG: s_ashr_i32 [[EXT3:s[0-9]+]], [[VAL]], 24 + +; GCN-DAG: v_mov_b32_e32 [[VEXT0:v[0-9]+]], [[EXT0]] +; GCN-DAG: v_mov_b32_e32 [[VEXT1:v[0-9]+]], [[EXT1]] +; GCN-DAG: v_mov_b32_e32 [[VEXT2:v[0-9]+]], [[EXT2]] +; GCN-DAG: v_mov_b32_e32 [[VEXT3:v[0-9]+]], [[EXT3]] + +; GCN-DAG: buffer_store_dword [[VEXT0]] +; GCN-DAG: buffer_store_dword [[VEXT1]] +; GCN-DAG: buffer_store_dword [[VEXT2]] +; GCN-DAG: buffer_store_dword [[VEXT3]] + +; GCN: s_endpgm +define void @s_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 %a) nounwind { + %cast = bitcast i32 %a to <4 x i8> + %ext = sext <4 x i8> %cast to <4 x i32> + %elt0 = extractelement <4 x i32> %ext, i32 0 + %elt1 = extractelement <4 x i32> %ext, i32 1 + %elt2 = extractelement <4 x i32> %ext, i32 2 + %elt3 = extractelement <4 x i32> %ext, i32 3 + store volatile i32 %elt0, i32 addrspace(1)* %out + store volatile i32 %elt1, i32 addrspace(1)* %out + store volatile i32 %elt2, i32 addrspace(1)* %out + store volatile i32 %elt3, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_sext_v4i8_to_v4i32: +; GCN: buffer_load_dword [[VAL:v[0-9]+]] +; GCN-DAG: v_bfe_i32 [[EXT0:v[0-9]+]], [[VAL]], 0, 8 +; GCN-DAG: v_bfe_i32 [[EXT1:v[0-9]+]], [[VAL]], 8, 8 +; GCN-DAG: v_bfe_i32 [[EXT2:v[0-9]+]], [[VAL]], 16, 8 +; GCN-DAG: v_ashrrev_i32_e32 [[EXT3:v[0-9]+]], 24, [[VAL]] + +; GCN: buffer_store_dword [[EXT0]] +; GCN: buffer_store_dword [[EXT1]] +; GCN: buffer_store_dword [[EXT2]] +; GCN: buffer_store_dword [[EXT3]] +define void @v_sext_v4i8_to_v4i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { + %a = load i32, i32 addrspace(1)* %in + %cast = bitcast i32 %a to <4 x i8> + %ext = sext <4 x i8> %cast to <4 x i32> + %elt0 = extractelement <4 x i32> %ext, i32 0 + %elt1 = extractelement <4 x i32> %ext, i32 1 + %elt2 = extractelement <4 x i32> %ext, i32 2 + %elt3 = extractelement <4 x i32> %ext, i32 3 + store volatile i32 %elt0, i32 addrspace(1)* %out + store volatile i32 %elt1, i32 addrspace(1)* %out + store volatile i32 %elt2, i32 addrspace(1)* %out + store volatile i32 %elt3, i32 addrspace(1)* %out + ret void +} + +; FIXME: s_bfe_i64 +; GCN-LABEL: {{^}}s_sext_v4i16_to_v4i32: +; GCN-DAG: s_ashr_i64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 48 +; GCN-DAG: s_ashr_i32 s{{[0-9]+}}, s{{[0-9]+}}, 16 +; GCN-DAG: s_sext_i32_i16 +; GCN-DAG: s_sext_i32_i16 +; GCN: s_endpgm +define void @s_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 %a) nounwind { + %cast = bitcast i64 %a to <4 x i16> + %ext = sext <4 x i16> %cast to <4 x i32> + %elt0 = extractelement <4 x i32> %ext, i32 0 + %elt1 = extractelement <4 x i32> %ext, i32 1 + %elt2 = extractelement <4 x i32> %ext, i32 2 + %elt3 = extractelement <4 x i32> %ext, i32 3 + store volatile i32 %elt0, i32 addrspace(1)* %out + store volatile i32 %elt1, i32 addrspace(1)* %out + store volatile i32 %elt2, i32 addrspace(1)* %out + store volatile i32 %elt3, i32 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_sext_v4i16_to_v4i32: +; SI-DAG: v_ashr_i64 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, 48 +; VI-DAG: v_ashrrev_i64 v{{\[[0-9]+:[0-9]+\]}}, 48, v{{\[[0-9]+:[0-9]+\]}} +; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} +; GCN-DAG: v_ashrrev_i32_e32 v{{[0-9]+}}, 16, v{{[0-9]+}} +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 +; GCN-DAG: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 16 +; GCN: s_endpgm +define void @v_sext_v4i16_to_v4i32(i32 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind { + %a = load i64, i64 addrspace(1)* %in + %cast = bitcast i64 %a to <4 x i16> + %ext = sext <4 x i16> %cast to <4 x i32> + %elt0 = extractelement <4 x i32> %ext, i32 0 + %elt1 = extractelement <4 x i32> %ext, i32 1 + %elt2 = extractelement <4 x i32> %ext, i32 2 + %elt3 = extractelement <4 x i32> %ext, i32 3 + store volatile i32 %elt0, i32 addrspace(1)* %out + store volatile i32 %elt1, i32 addrspace(1)* %out + store volatile i32 %elt2, i32 addrspace(1)* %out + store volatile i32 %elt3, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/sint_to_fp.f64.ll b/test/CodeGen/AMDGPU/sint_to_fp.f64.ll index a94ccc32e61c..7c58f2d906d4 100644 --- a/test/CodeGen/AMDGPU/sint_to_fp.f64.ll +++ b/test/CodeGen/AMDGPU/sint_to_fp.f64.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; SI-LABEL: {{^}}sint_to_fp_i32_to_f64 ; SI: v_cvt_f64_i32_e32 @@ -10,14 +10,14 @@ define void @sint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) { ret void } -; FIXME: select on 0, 0 -; SI-LABEL: {{^}}sint_to_fp_i1_f64: -; SI: v_cmp_eq_i32_e64 vcc, ; We can't fold the SGPRs into v_cndmask_b32_e64, because it already ; uses an SGPR (implicit vcc). -; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} -; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc -; SI: buffer_store_dwordx2 + +; SI-LABEL: {{^}}sint_to_fp_i1_f64: +; SI-DAG: v_cmp_eq_i32_e64 vcc, +; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} +; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; SI: s_endpgm define void @sint_to_fp_i1_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 @@ -52,7 +52,7 @@ define void @s_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) { ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @v_sint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %val = load i64, i64 addrspace(1)* %gep, align 8 %result = sitofp i64 %val to double diff --git a/test/CodeGen/AMDGPU/sint_to_fp.i64.ll b/test/CodeGen/AMDGPU/sint_to_fp.i64.ll index 138b93b16d8d..16eae1899ec0 100644 --- a/test/CodeGen/AMDGPU/sint_to_fp.i64.ll +++ b/test/CodeGen/AMDGPU/sint_to_fp.i64.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s ; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600 @@ -13,8 +13,7 @@ define void @s_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) #0 { ; FUNC-LABEL: {{^}}v_sint_to_fp_i64_to_f32: ; GCN: {{buffer|flat}}_load_dwordx2 -; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, 63 -; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\]}}, 63, {{v\[[0-9]+:[0-9]+\]}} +; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}} ; GCN: v_xor_b32 ; GCN: v_ffbh_u32 @@ -26,10 +25,10 @@ define void @s_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) #0 { ; GCN-DAG: v_cmp_lt_u64 ; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}} -; GCN: v_cndmask_b32_e32 [[SIGN_SEL:v[0-9]+]], -; GCN: {{buffer|flat}}_store_dword [[SIGN_SEL]] +; GCN: v_cndmask_b32_e{{32|64}} [[SIGN_SEL:v[0-9]+]], +; GCN: {{buffer|flat}}_store_dword {{.*}}[[SIGN_SEL]] define void @v_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() + %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %val = load i64, i64 addrspace(1)* %in.gep @@ -47,7 +46,7 @@ define void @s_sint_to_fp_v2i64(<2 x float> addrspace(1)* %out, <2 x i64> %in) # ; FUNC-LABEL: {{^}}v_sint_to_fp_v4i64: define void @v_sint_to_fp_v4i64(<4 x float> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 { - %tid = call i32 @llvm.r600.read.tidig.x() + %tid = call i32 @llvm.amdgcn.workitem.id.x() %in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid %out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid %value = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep @@ -56,7 +55,7 @@ define void @v_sint_to_fp_v4i64(<4 x float> addrspace(1)* %out, <4 x i64> addrsp ret void } -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/sint_to_fp.ll b/test/CodeGen/AMDGPU/sint_to_fp.ll index 851085c9535d..75ffdd2cc85a 100644 --- a/test/CodeGen/AMDGPU/sint_to_fp.ll +++ b/test/CodeGen/AMDGPU/sint_to_fp.ll @@ -103,7 +103,7 @@ define void @s_sint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 %in) #0 { ; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} ; SI: v_cmp_eq_i32 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, -1.0 -; SI: {{buffer|flat}}_store_dword [[RESULT]], +; SI: {{buffer|flat}}_store_dword {{.*}}[[RESULT]] ; SI: s_endpgm define void @v_sint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() diff --git a/test/CodeGen/AMDGPU/skip-if-dead.ll b/test/CodeGen/AMDGPU/skip-if-dead.ll new file mode 100644 index 000000000000..10187f6125d6 --- /dev/null +++ b/test/CodeGen/AMDGPU/skip-if-dead.ll @@ -0,0 +1,390 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 { + call void @llvm.AMDGPU.kill(float 0.0) + ret void +} + +; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: s_mov_b64 exec, 0 +; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 { + call void @llvm.AMDGPU.kill(float -0.0) + ret void +} + +; FIXME: Ideally only one would be emitted +; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg_x2: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: s_mov_b64 exec, 0 +; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: s_mov_b64 exec, 0 +; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_0_imm_neg_x2() #0 { + call void @llvm.AMDGPU.kill(float -0.0) + call void @llvm.AMDGPU.kill(float -1.0) + ret void +} + +; CHECK-LABEL: {{^}}test_kill_depth_var: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_var(float %x) #0 { + call void @llvm.AMDGPU.kill(float %x) + ret void +} + +; FIXME: Ideally only one would be emitted +; CHECK-LABEL: {{^}}test_kill_depth_var_x2_same: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_var_x2_same(float %x) #0 { + call void @llvm.AMDGPU.kill(float %x) + call void @llvm.AMDGPU.kill(float %x) + ret void +} + +; CHECK-LABEL: {{^}}test_kill_depth_var_x2: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: ; BB#1: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v1 +; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_var_x2(float %x, float %y) #0 { + call void @llvm.AMDGPU.kill(float %x) + call void @llvm.AMDGPU.kill(float %y) + ret void +} + +; CHECK-LABEL: {{^}}test_kill_depth_var_x2_instructions: +; CHECK-NEXT: ; BB#0: +; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0 +; CHECK-NEXT: ; BB#1: +; CHECK: v_mov_b32_e64 v7, -1 +; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 +; CHECK-NEXT: ; BB#2: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_depth_var_x2_instructions(float %x) #0 { + call void @llvm.AMDGPU.kill(float %x) + %y = call float asm sideeffect "v_mov_b32_e64 v7, -1", "={VGPR7}"() + call void @llvm.AMDGPU.kill(float %y) + ret void +} + +; FIXME: why does the skip depend on the asm length in the same block? + +; CHECK-LABEL: {{^}}test_kill_control_flow: +; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] + +; CHECK-NEXT: ; BB#1: +; CHECK: v_mov_b32_e64 v7, -1 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 + +; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 +; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] +; CHECK-NEXT: ; BB#3: +; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0 +; CHECK-NEXT: s_endpgm + +; CHECK-NEXT: {{^}}[[SPLIT_BB]]: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_control_flow(i32 inreg %arg) #0 { +entry: + %cmp = icmp eq i32 %arg, 0 + br i1 %cmp, label %bb, label %exit + +bb: + %var = call float asm sideeffect " + v_mov_b32_e64 v7, -1 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64", "={VGPR7}"() + call void @llvm.AMDGPU.kill(float %var) + br label %exit + +exit: + ret void +} + +; CHECK-LABEL: {{^}}test_kill_control_flow_remainder: +; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]] + +; CHECK-NEXT: ; BB#1: ; %bb +; CHECK: v_mov_b32_e64 v7, -1 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: v_nop_e64 +; CHECK: ;;#ASMEND +; CHECK: v_mov_b32_e64 v8, -1 +; CHECK: ;;#ASMEND +; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 +; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]] + +; CHECK-NEXT: ; BB#4: +; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0 +; CHECK-NEXT: s_endpgm + +; CHECK-NEXT: {{^}}[[SPLIT_BB]]: +; CHECK: buffer_store_dword v8 +; CHECK: v_mov_b32_e64 v9, -2 + +; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}: +; CHECK: buffer_store_dword v9 +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 { +entry: + %cmp = icmp eq i32 %arg, 0 + br i1 %cmp, label %bb, label %exit + +bb: + %var = call float asm sideeffect " + v_mov_b32_e64 v7, -1 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64", "={VGPR7}"() + %live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={VGPR8}"() + call void @llvm.AMDGPU.kill(float %var) + store volatile float %live.across, float addrspace(1)* undef + %live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={VGPR9}"() + br label %exit + +exit: + %phi = phi float [ 0.0, %entry ], [ %live.out, %bb ] + store float %phi, float addrspace(1)* undef + ret void +} + +; CHECK-LABEL: {{^}}test_kill_divergent_loop: +; CHECK: v_cmp_eq_i32_e32 vcc, 0, v0 +; CHECK-NEXT: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], vcc +; CHECK-NEXT: s_xor_b64 [[SAVEEXEC]], exec, [[SAVEEXEC]] +; CHECK-NEXT: s_cbranch_execz [[EXIT:BB[0-9]+_[0-9]+]] +; CHECK-NEXT: ; mask branch [[EXIT]] + +; CHECK: [[LOOP_BB:BB[0-9]+_[0-9]+]]: + +; CHECK: v_mov_b32_e64 v7, -1 +; CHECK: v_nop_e64 +; CHECK: v_cmpx_le_f32_e32 vcc, 0, v7 + +; CHECK-NEXT: ; BB#3: +; CHECK: buffer_load_dword [[LOAD:v[0-9]+]] +; CHECK: v_cmp_eq_i32_e32 vcc, 0, [[LOAD]] +; CHECK-NEXT: s_and_b64 vcc, exec, vcc +; CHECK-NEXT: s_cbranch_vccnz [[LOOP_BB]] + +; CHECK-NEXT: {{^}}[[EXIT]]: +; CHECK: s_or_b64 exec, exec, [[SAVEEXEC]] +; CHECK: buffer_store_dword +; CHECK: s_endpgm +define amdgpu_ps void @test_kill_divergent_loop(i32 %arg) #0 { +entry: + %cmp = icmp eq i32 %arg, 0 + br i1 %cmp, label %bb, label %exit + +bb: + %var = call float asm sideeffect " + v_mov_b32_e64 v7, -1 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64 + v_nop_e64", "={VGPR7}"() + call void @llvm.AMDGPU.kill(float %var) + %vgpr = load volatile i32, i32 addrspace(1)* undef + %loop.cond = icmp eq i32 %vgpr, 0 + br i1 %loop.cond, label %bb, label %exit + +exit: + store volatile i32 8, i32 addrspace(1)* undef + ret void +} + +; bug 28550 +; CHECK-LABEL: {{^}}phi_use_def_before_kill: +; CHECK: v_cndmask_b32_e64 [[PHIREG:v[0-9]+]], 0, -1.0, +; CHECK: v_cmpx_le_f32_e32 vcc, 0, +; CHECK-NEXT: s_cbranch_execnz [[BB4:BB[0-9]+_[0-9]+]] + +; CHECK: exp +; CHECK-NEXT: s_endpgm + +; CHECK: [[KILLBB:BB[0-9]+_[0-9]+]]: +; CHECK: s_and_b64 vcc, exec, +; CHECK-NEXT: s_cbranch_vccz [[PHIBB:BB[0-9]+_[0-9]+]] + +; CHECK: [[PHIBB]]: +; CHECK: v_cmp_eq_f32_e32 vcc, 0, [[PHIREG]] +; CHECK: s_and_b64 vcc, exec, vcc +; CHECK: s_cbranch_vccz [[ENDBB:BB[0-9]+_[0-9]+]] + +; CHECK: ; BB#3: ; %bb10 +; CHECK: v_mov_b32_e32 v{{[0-9]+}}, 9 +; CHECK: buffer_store_dword + +; CHECK: [[ENDBB]]: +; CHECK-NEXT: s_endpgm +define amdgpu_ps void @phi_use_def_before_kill() #0 { +bb: + %tmp = fadd float undef, 1.000000e+00 + %tmp1 = fcmp olt float 0.000000e+00, %tmp + %tmp2 = select i1 %tmp1, float -1.000000e+00, float 0.000000e+00 + call void @llvm.AMDGPU.kill(float %tmp2) + br i1 undef, label %phibb, label %bb8 + +phibb: + %tmp5 = phi float [ %tmp2, %bb ], [ 4.0, %bb8 ] + %tmp6 = fcmp oeq float %tmp5, 0.000000e+00 + br i1 %tmp6, label %bb10, label %end + +bb8: + store volatile i32 8, i32 addrspace(1)* undef + br label %phibb + +bb10: + store volatile i32 9, i32 addrspace(1)* undef + br label %end + +end: + ret void +} + +; CHECK-LABEL: {{^}}no_skip_no_successors: +; CHECK: v_cmp_nle_f32 +; CHECK: s_and_b64 vcc, exec, +; CHECK: s_cbranch_vccz [[SKIPKILL:BB[0-9]+_[0-9]+]] + +; CHECK: ; BB#3: ; %bb6 +; CHECK: s_mov_b64 exec, 0 + +; CHECK: [[SKIPKILL]]: +; CHECK: v_cmp_nge_f32 +; CHECK: s_and_b64 vcc, exec, vcc +; CHECK: s_cbranch_vccz [[UNREACHABLE:BB[0-9]+_[0-9]+]] + +; CHECK: [[UNREACHABLE]]: +; CHECK-NEXT: .Lfunc_end{{[0-9]+}} +define amdgpu_ps void @no_skip_no_successors(float inreg %arg, float inreg %arg1) #0 { +bb: + %tmp = fcmp ult float %arg1, 0.000000e+00 + %tmp2 = fcmp ult float %arg, 0x3FCF5C2900000000 + br i1 %tmp, label %bb6, label %bb3 + +bb3: ; preds = %bb + br i1 %tmp2, label %bb5, label %bb4 + +bb4: ; preds = %bb3 + br i1 true, label %bb5, label %bb7 + +bb5: ; preds = %bb4, %bb3 + unreachable + +bb6: ; preds = %bb + call void @llvm.AMDGPU.kill(float -1.000000e+00) + unreachable + +bb7: ; preds = %bb4 + ret void +} + +; CHECK-LABEL: {{^}}if_after_kill_block: +; CHECK: ; BB#0: +; CHECK: s_and_saveexec_b64 +; CHECK: s_xor_b64 +; CHECK-NEXT: mask branch [[BB4:BB[0-9]+_[0-9]+]] + +; CHECK: v_cmpx_le_f32_e32 vcc, 0, +; CHECK: [[BB4]]: +; CHECK: s_or_b64 exec, exec +; CHECK: image_sample_c + +; CHECK: v_cmp_neq_f32_e32 vcc, 0, +; CHECK: s_and_b64 exec, exec, +; CHECK: s_and_saveexec_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc +; CHECK: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, exec +; CHECK: mask branch [[END:BB[0-9]+_[0-9]+]] +; CHECK-NOT: branch + +; CHECK: ; BB#3: ; %bb8 +; CHECK: buffer_store_dword + +; CHECK: [[END]]: +; CHECK: s_or_b64 exec, exec +; CHECK: s_endpgm +define amdgpu_ps void @if_after_kill_block(float %arg, float %arg1, <4 x i32> %arg2) #0 { +bb: + %tmp = fcmp ult float %arg1, 0.000000e+00 + br i1 %tmp, label %bb3, label %bb4 + +bb3: ; preds = %bb + call void @llvm.AMDGPU.kill(float %arg) + br label %bb4 + +bb4: ; preds = %bb3, %bb + %tmp5 = call <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32> %arg2, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp6 = extractelement <4 x float> %tmp5, i32 0 + %tmp7 = fcmp une float %tmp6, 0.000000e+00 + br i1 %tmp7, label %bb8, label %bb9 + +bb8: ; preds = %bb9, %bb4 + store volatile i32 9, i32 addrspace(1)* undef + ret void + +bb9: ; preds = %bb4 + ret void +} + +declare void @llvm.AMDGPU.kill(float) #0 +declare <4 x float> @llvm.SI.image.sample.c.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } \ No newline at end of file diff --git a/test/CodeGen/AMDGPU/smed3.ll b/test/CodeGen/AMDGPU/smed3.ll new file mode 100644 index 000000000000..9b977fc54630 --- /dev/null +++ b/test/CodeGen/AMDGPU/smed3.ll @@ -0,0 +1,449 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.r600.read.tidig.x() #0 + +; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i32: +; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +define void @v_test_smed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp slt i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_smed3_multi_use_r_i_i_i32: +; GCN: v_max_i32 +; GCN: v_min_i32 +define void @v_test_smed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp slt i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store volatile i32 %i0, i32 addrspace(1)* %outgep + store volatile i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_smed3_r_i_i_constant_order_i32: +; GCN: v_max_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}} +; GCN: v_min_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}} +define void @v_test_smed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i32 %a, 17 + %i0 = select i1 %icmp0, i32 %a, i32 17 + + %icmp1 = icmp slt i32 %i0, 12 + %i1 = select i1 %icmp1, i32 %i0, i32 12 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_smed3_r_i_i_sign_mismatch_i32: +; GCN: v_max_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}} +; GCN: v_min_i32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}} +define void @v_test_smed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp slt i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i64: +; GCN: v_cmp_lt_i64 +; GCN: v_cmp_gt_i64 +define void @v_test_smed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid + %a = load i64, i64 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i64 %a, 12 + %i0 = select i1 %icmp0, i64 %a, i64 12 + + %icmp1 = icmp slt i64 %i0, 17 + %i1 = select i1 %icmp1, i64 %i0, i64 17 + + store i64 %i1, i64 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_smed3_r_i_i_i16: +; GCN: v_med3_i32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +define void @v_test_smed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid + %a = load i16, i16 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i16 %a, 12 + %i0 = select i1 %icmp0, i16 %a, i16 12 + + %icmp1 = icmp slt i16 %i0, 17 + %i1 = select i1 %icmp1, i16 %i0, i16 17 + + store i16 %i1, i16 addrspace(1)* %outgep + ret void +} + + +define internal i32 @smin(i32 %x, i32 %y) #2 { + %cmp = icmp slt i32 %x, %y + %sel = select i1 %cmp, i32 %x, i32 %y + ret i32 %sel +} + +define internal i32 @smax(i32 %x, i32 %y) #2 { + %cmp = icmp sgt i32 %x, %y + %sel = select i1 %cmp, i32 %x, i32 %y + ret i32 %sel +} + +define internal i16 @smin16(i16 %x, i16 %y) #2 { + %cmp = icmp slt i16 %x, %y + %sel = select i1 %cmp, i16 %x, i16 %y + ret i16 %sel +} + +define internal i16 @smax16(i16 %x, i16 %y) #2 { + %cmp = icmp sgt i16 %x, %y + %sel = select i1 %cmp, i16 %x, i16 %y + ret i16 %sel +} + +define internal i8 @smin8(i8 %x, i8 %y) #2 { + %cmp = icmp slt i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %y + ret i8 %sel +} + +define internal i8 @smax8(i8 %x, i8 %y) #2 { + %cmp = icmp sgt i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %y + ret i8 %sel +} + +; 16 combinations + +; 0: max(min(x, y), min(max(x, y), z)) +; 1: max(min(x, y), min(max(y, x), z)) +; 2: max(min(x, y), min(z, max(x, y))) +; 3: max(min(x, y), min(z, max(y, x))) +; 4: max(min(y, x), min(max(x, y), z)) +; 5: max(min(y, x), min(max(y, x), z)) +; 6: max(min(y, x), min(z, max(x, y))) +; 7: max(min(y, x), min(z, max(y, x))) +; +; + commute outermost max + + +; FIXME: In these cases we probably should have used scalar operations +; instead. + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_1: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_2: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_3: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_3(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_4: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_4(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_5: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_5(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_6: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_6(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_7: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_7(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_8: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_8(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_9: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_9(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_10: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_10(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_11: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_11(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_12: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_12(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_13: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_13(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_14: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_14(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_15: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_15(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %y, i32 %x) + %tmp1 = call i32 @smax(i32 %y, i32 %x) + %tmp2 = call i32 @smin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0: +; GCN: s_sext_i32_i16 +; GCN: s_sext_i32_i16 +; GCN: s_sext_i32_i16 +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i16_pat_0(i16 addrspace(1)* %arg, i16 %x, i16 %y, i16 %z) #1 { +bb: + %tmp0 = call i16 @smin16(i16 %x, i16 %y) + %tmp1 = call i16 @smax16(i16 %x, i16 %y) + %tmp2 = call i16 @smin16(i16 %tmp1, i16 %z) + %tmp3 = call i16 @smax16(i16 %tmp0, i16 %tmp2) + store i16 %tmp3, i16 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i8_pat_0: +; GCN: s_sext_i32_i8 +; GCN: s_sext_i32_i8 +; GCN: s_sext_i32_i8 +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i8_pat_0(i8 addrspace(1)* %arg, i8 %x, i8 %y, i8 %z) #1 { +bb: + %tmp0 = call i8 @smin8(i8 %x, i8 %y) + %tmp1 = call i8 @smax8(i8 %x, i8 %y) + %tmp2 = call i8 @smin8(i8 %tmp1, i8 %z) + %tmp3 = call i8 @smax8(i8 %tmp0, i8 %tmp2) + store i8 %tmp3, i8 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_0: +; GCN-NOT: v_med3_i32 +define void @s_test_smed3_i32_pat_0_multi_use_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp0, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_1: +; GCN-NOT: v_med3_i32 +define void @s_test_smed3_i32_pat_0_multi_use_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp1, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_2: +; GCN-NOT: v_med3_i32 +define void @s_test_smed3_i32_pat_0_multi_use_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp2, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_smed3_i32_pat_0_multi_use_result: +; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_smed3_i32_pat_0_multi_use_result(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @smin(i32 %x, i32 %y) + %tmp1 = call i32 @smax(i32 %x, i32 %y) + %tmp2 = call i32 @smin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @smax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp3, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } +attributes #2 = { nounwind readnone alwaysinline } diff --git a/test/CodeGen/AMDGPU/sminmax.ll b/test/CodeGen/AMDGPU/sminmax.ll index e646605f7da1..560d5597baa9 100644 --- a/test/CodeGen/AMDGPU/sminmax.ll +++ b/test/CodeGen/AMDGPU/sminmax.ll @@ -1,9 +1,12 @@ ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}s_abs_i32: ; GCN: s_abs_i32 ; GCN: s_add_i32 + +; EG: MAX_INT define void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind { %neg = sub i32 0, %val %cond = icmp sgt i32 %val, %neg @@ -17,6 +20,8 @@ define void @s_abs_i32(i32 addrspace(1)* %out, i32 %val) nounwind { ; GCN: v_sub_i32_e32 [[NEG:v[0-9]+]], vcc, 0, [[SRC:v[0-9]+]] ; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG]], [[SRC]] ; GCN: v_add_i32 + +; EG: MAX_INT define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind { %val = load i32, i32 addrspace(1)* %src, align 4 %neg = sub i32 0, %val @@ -32,6 +37,9 @@ define void @v_abs_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %src) nounwind ; GCN: s_abs_i32 ; GCN: s_add_i32 ; GCN: s_add_i32 + +; EG: MAX_INT +; EG: MAX_INT define void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %val) nounwind { %z0 = insertelement <2 x i32> undef, i32 0, i32 0 %z1 = insertelement <2 x i32> %z0, i32 0, i32 1 @@ -46,14 +54,17 @@ define void @s_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> %val) nounwind } ; FUNC-LABEL: {{^}}v_abs_v2i32: -; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] -; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] ; GCN: v_add_i32 ; GCN: v_add_i32 + +; EG: MAX_INT +; EG: MAX_INT define void @v_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %src) nounwind { %z0 = insertelement <2 x i32> undef, i32 0, i32 0 %z1 = insertelement <2 x i32> %z0, i32 0, i32 1 @@ -79,6 +90,11 @@ define void @v_abs_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* % ; GCN: s_add_i32 ; GCN: s_add_i32 ; GCN: s_add_i32 + +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT define void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %val) nounwind { %z0 = insertelement <4 x i32> undef, i32 0, i32 0 %z1 = insertelement <4 x i32> %z0, i32 0, i32 1 @@ -97,20 +113,25 @@ define void @s_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %val) nounwind } ; FUNC-LABEL: {{^}}v_abs_v4i32: -; GCN: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] -; GCN: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] -; GCN: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] -; GCN: v_sub_i32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG0:v[0-9]+]], vcc, 0, [[SRC0:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG1:v[0-9]+]], vcc, 0, [[SRC1:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG2:v[0-9]+]], vcc, 0, [[SRC2:v[0-9]+]] +; GCN-DAG: v_sub_i32_e32 [[NEG3:v[0-9]+]], vcc, 0, [[SRC3:v[0-9]+]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]] -; GCN: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG0]], [[SRC0]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG1]], [[SRC1]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG2]], [[SRC2]] +; GCN-DAG: v_max_i32_e32 {{v[0-9]+}}, [[NEG3]], [[SRC3]] ; GCN: v_add_i32 ; GCN: v_add_i32 ; GCN: v_add_i32 ; GCN: v_add_i32 + +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT +; EG: MAX_INT define void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %src) nounwind { %z0 = insertelement <4 x i32> undef, i32 0, i32 0 %z1 = insertelement <4 x i32> %z0, i32 0, i32 1 @@ -128,3 +149,76 @@ define void @v_abs_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* % store <4 x i32> %res2, <4 x i32> addrspace(1)* %out, align 4 ret void } + +; FUNC-LABEL: {{^}}s_min_max_i32: +; GCN: s_load_dword [[VAL0:s[0-9]+]] +; GCN: s_load_dword [[VAL1:s[0-9]+]] + +; GCN-DAG: s_min_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]] +; GCN-DAG: s_max_i32 s{{[0-9]+}}, [[VAL0]], [[VAL1]] +define void @s_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %val0, i32 %val1) nounwind { + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}v_min_max_i32: +; GCN: buffer_load_dword [[VAL0:v[0-9]+]] +; GCN: buffer_load_dword [[VAL1:v[0-9]+]] + +; GCN-DAG: v_min_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]] +; GCN-DAG: v_max_i32_e32 v{{[0-9]+}}, [[VAL1]], [[VAL0]] +define void @v_min_max_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind { + %val0 = load volatile i32, i32 addrspace(1)* %ptr0 + %val1 = load volatile i32, i32 addrspace(1)* %ptr1 + + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}s_min_max_v4i32: +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_min_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +; GCN-DAG: s_max_i32 +define void @s_min_max_v4i32(<4 x i32> addrspace(1)* %out0, <4 x i32> addrspace(1)* %out1, <4 x i32> %val0, <4 x i32> %val1) nounwind { + %cond0 = icmp sgt <4 x i32> %val0, %val1 + %sel0 = select <4 x i1> %cond0, <4 x i32> %val0, <4 x i32> %val1 + %sel1 = select <4 x i1> %cond0, <4 x i32> %val1, <4 x i32> %val0 + + store volatile <4 x i32> %sel0, <4 x i32> addrspace(1)* %out0, align 4 + store volatile <4 x i32> %sel1, <4 x i32> addrspace(1)* %out1, align 4 + ret void +} + +; FUNC-LABEL: {{^}}v_min_max_i32_user: +; GCN: v_cmp_gt_i32_e32 +; GCN-DAG: v_cndmask_b32_e32 +; GCN-DAG: v_cndmask_b32_e32 +; GCN-DAG: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc +define void @v_min_max_i32_user(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(1)* %ptr0, i32 addrspace(1)* %ptr1) nounwind { + %val0 = load volatile i32, i32 addrspace(1)* %ptr0 + %val1 = load volatile i32, i32 addrspace(1)* %ptr1 + + %cond0 = icmp sgt i32 %val0, %val1 + %sel0 = select i1 %cond0, i32 %val0, i32 %val1 + %sel1 = select i1 %cond0, i32 %val1, i32 %val0 + + store volatile i32 %sel0, i32 addrspace(1)* %out0, align 4 + store volatile i32 %sel1, i32 addrspace(1)* %out1, align 4 + store volatile i1 %cond0, i1 addrspace(1)* undef + ret void +} diff --git a/test/CodeGen/AMDGPU/smrd-vccz-bug.ll b/test/CodeGen/AMDGPU/smrd-vccz-bug.ll new file mode 100644 index 000000000000..ddac8a006c86 --- /dev/null +++ b/test/CodeGen/AMDGPU/smrd-vccz-bug.ll @@ -0,0 +1,49 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s + +; GCN-FUNC: {{^}}vccz_workaround: +; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0 +; GCN: v_cmp_neq_f32_e64 [[MASK:s\[[0-9]+:[0-9]+\]]], 0 +; GCN: s_and_b64 vcc, exec, [[MASK]] +; GCN: s_waitcnt lgkmcnt(0) +; VCCZ-BUG: s_mov_b64 vcc, vcc +; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc +; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] +; GCN: buffer_store_dword +; GCN: [[EXIT]]: +; GCN: s_endpgm +define void @vccz_workaround(i32 addrspace(2)* %in, i32 addrspace(1)* %out, float %cond) { +entry: + %cnd = fcmp oeq float 0.0, %cond + %sgpr = load volatile i32, i32 addrspace(2)* %in + br i1 %cnd, label %if, label %endif + +if: + store i32 %sgpr, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + +; GCN-FUNC: {{^}}vccz_noworkaround: +; GCN: v_cmp_neq_f32_e32 vcc, 0, v{{[0-9]+}} +; GCN: s_and_b64 vcc, exec, vcc +; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] +; GCN: buffer_store_dword +; GCN: [[EXIT]]: +; GCN: s_endpgm +define void @vccz_noworkaround(float addrspace(1)* %in, float addrspace(1)* %out) { +entry: + %vgpr = load volatile float, float addrspace(1)* %in + %cnd = fcmp oeq float 0.0, %vgpr + br i1 %cnd, label %if, label %endif + +if: + store float %vgpr, float addrspace(1)* %out + br label %endif + +endif: + ret void +} diff --git a/test/CodeGen/AMDGPU/smrd.ll b/test/CodeGen/AMDGPU/smrd.ll index 1d6bb9ece8c6..476da9486dff 100644 --- a/test/CodeGen/AMDGPU/smrd.ll +++ b/test/CodeGen/AMDGPU/smrd.ll @@ -88,7 +88,7 @@ entry: ; GCN-LABEL: {{^}}smrd_load_const0: ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10 -define void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @smrd_load_const0(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) { main_body: %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 @@ -102,7 +102,7 @@ main_body: ; GCN-LABEL: {{^}}smrd_load_const1: ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc -define void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @smrd_load_const1(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) { main_body: %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 @@ -118,7 +118,7 @@ main_body: ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 -define void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @smrd_load_const2(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) { main_body: %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 @@ -133,7 +133,7 @@ main_body: ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff ; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc -define void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) { main_body: %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 @@ -148,7 +148,7 @@ main_body: ; SIVI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 ; GCN: s_endpgm -define void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 { +define amdgpu_ps void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) { main_body: %20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0 %21 = load <16 x i8>, <16 x i8> addrspace(2)* %20 @@ -158,9 +158,8 @@ main_body: } ; Function Attrs: nounwind readnone -declare float @llvm.SI.load.const(<16 x i8>, i32) #1 +declare float @llvm.SI.load.const(<16 x i8>, i32) #0 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { nounwind readnone } +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll b/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll index c91a44cf60e5..cc4b6bcbfb51 100644 --- a/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll +++ b/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll @@ -6,7 +6,8 @@ ; TONGA-LABEL: test define void @test(<256 x i32> addrspace(1)* %out, <256 x i32> addrspace(1)* %in) { entry: - %tid = call i32 @llvm.SI.tid() nounwind readnone + %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) %aptr = getelementptr <256 x i32>, <256 x i32> addrspace(1)* %in, i32 %tid %a = load <256 x i32>, <256 x i32> addrspace(1)* %aptr call void asm sideeffect "", "~{memory}" () @@ -21,4 +22,7 @@ entry: ret void } -declare i32 @llvm.SI.tid() nounwind readnone +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/spill-scavenge-offset.ll b/test/CodeGen/AMDGPU/spill-scavenge-offset.ll index 4a12ed545b81..9b3dfab2be6a 100644 --- a/test/CodeGen/AMDGPU/spill-scavenge-offset.ll +++ b/test/CodeGen/AMDGPU/spill-scavenge-offset.ll @@ -1,5 +1,9 @@ -; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=verde -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s +; RUN: llc -regalloc=basic -march=amdgcn -mcpu=tonga -enable-misched=0 -post-RA-scheduler=0 < %s | FileCheck %s + ; +; There is something about Tonga that causes this test to spend a lot of time +; in the default register allocator. + ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR ; is used to calculate the scratch load/store address. Make sure that this @@ -7,10 +11,10 @@ ; Just test that it compiles successfully. ; CHECK-LABEL: test -define void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in, - <96 x i32> addrspace(1)* %sdata_out, <96 x i32> %sdata_in) { +define void @test(<1280 x i32> addrspace(1)* %out, <1280 x i32> addrspace(1)* %in) { entry: - %tid = call i32 @llvm.SI.tid() nounwind readnone + %lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) + %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo) %aptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid %a = load <1280 x i32>, <1280 x i32> addrspace(1)* %aptr @@ -24,10 +28,13 @@ entry: call void asm sideeffect "", "~{VGPR164},~{VGPR168},~{VGPR172},~{VGPR176},~{VGPR180},~{VGPR184},~{VGPR188},~{VGPR192}" () call void asm sideeffect "", "~{VGPR196},~{VGPR200},~{VGPR204},~{VGPR208},~{VGPR212},~{VGPR216},~{VGPR220},~{VGPR224}" () - %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %in, i32 %tid + %outptr = getelementptr <1280 x i32>, <1280 x i32> addrspace(1)* %out, i32 %tid store <1280 x i32> %a, <1280 x i32> addrspace(1)* %outptr ret void } -declare i32 @llvm.SI.tid() nounwind readnone +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 +declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #1 + +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/split-scalar-i64-add.ll b/test/CodeGen/AMDGPU/split-scalar-i64-add.ll index 9e181bc14d9d..d4e2dc814050 100644 --- a/test/CodeGen/AMDGPU/split-scalar-i64-add.ll +++ b/test/CodeGen/AMDGPU/split-scalar-i64-add.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -declare i32 @llvm.r600.read.tidig.x() readnone +declare i32 @llvm.amdgcn.workitem.id.x() readnone ; This is broken because the low half of the 64-bit add remains on the ; SALU, but the upper half does not. The addc expects the carry bit @@ -62,7 +62,7 @@ define void @s_imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i6 ; SI: v_add_i32_e32 {{v[0-9]+}}, vcc, {{s[0-9]+}}, {{v[0-9]+}} ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc define void @imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) { - %tid = call i32 @llvm.r600.read.tidig.x() readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone %gep = getelementptr i32, i32 addrspace(1)* %in, i32 %tid %load = load i32, i32 addrspace(1)* %gep %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0 diff --git a/test/CodeGen/AMDGPU/split-smrd.ll b/test/CodeGen/AMDGPU/split-smrd.ll new file mode 100644 index 000000000000..237a62c1360a --- /dev/null +++ b/test/CodeGen/AMDGPU/split-smrd.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. +; Make sure that when we split an smrd instruction in order to move it to +; the VALU, we are also moving its users to the VALU. +; CHECK-LABEL: {{^}}split_smrd_add_worklist: +; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 + +define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { +bb: + %tmp = call float @llvm.SI.load.const(<16 x i8> undef, i32 96) + %tmp1 = bitcast float %tmp to i32 + br i1 undef, label %bb2, label %bb3 + +bb2: ; preds = %bb + unreachable + +bb3: ; preds = %bb + %tmp4 = bitcast float %tmp to i32 + %tmp5 = add i32 %tmp4, 4 + %tmp6 = sext i32 %tmp5 to i64 + %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i64 0, i64 %tmp6 + %tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 + %tmp9 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> , <8 x i32> %tmp8, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp10 = extractelement <4 x float> %tmp9, i32 0 + %tmp12 = call i32 @llvm.SI.packf16(float %tmp10, float undef) + %tmp13 = bitcast i32 %tmp12 to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %tmp13, float undef, float undef) + ret void +} + +; Function Attrs: nounwind readnone +declare float @llvm.SI.load.const(<16 x i8>, i32) #1 + +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + +declare i32 @llvm.SI.packf16(float, float) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!0 = !{!1, !1, i64 0, i32 1} +!1 = !{!"const", null} +!2 = !{!1, !1, i64 0} diff --git a/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll b/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll index 4c82ed6affc2..484150bc25fd 100644 --- a/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll +++ b/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll @@ -1,4 +1,5 @@ ; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s +; XFAIL: * @sPrivateStorage = external addrspace(3) global [256 x [8 x <4 x i64>]] @@ -34,14 +35,14 @@ define void @ds_reorder_vector_split(<4 x i64> addrspace(1)* nocapture readonly entry: %tmp = tail call i32 @llvm.r600.read.local.size.y() %tmp1 = tail call i32 @llvm.r600.read.local.size.z() - %tmp2 = tail call i32 @llvm.r600.read.tidig.x() - %tmp3 = tail call i32 @llvm.r600.read.tidig.y() - %tmp4 = tail call i32 @llvm.r600.read.tidig.z() + %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x() + %tmp3 = tail call i32 @llvm.amdgcn.workitem.id.y() + %tmp4 = tail call i32 @llvm.amdgcn.workitem.id.z() %tmp6 = mul i32 %tmp2, %tmp %tmp10 = add i32 %tmp3, %tmp6 %tmp11 = mul i32 %tmp10, %tmp1 %tmp9 = add i32 %tmp11, %tmp4 - %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1 + %x.i.i = tail call i32 @llvm.amdgcn.workgroup.id.x() #1 %x.i.12.i = tail call i32 @llvm.r600.read.local.size.x() #1 %mul.26.i = mul i32 %x.i.12.i, %x.i.i %add.i = add i32 %tmp2, %mul.26.i @@ -80,13 +81,13 @@ entry: } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tgid.x() #1 +declare i32 @llvm.amdgcn.workgroup.id.x() #1 ; Function Attrs: nounwind readnone declare i32 @llvm.r600.read.local.size.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; Function Attrs: nounwind readnone declare i32 @llvm.r600.read.local.size.y() #1 @@ -95,10 +96,10 @@ declare i32 @llvm.r600.read.local.size.y() #1 declare i32 @llvm.r600.read.local.size.z() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.y() #1 +declare i32 @llvm.amdgcn.workitem.id.y() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.z() #1 +declare i32 @llvm.amdgcn.workitem.id.z() #1 attributes #0 = { norecurse nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/sra.ll b/test/CodeGen/AMDGPU/sra.ll index 3b59bbfb18c0..dddfbfd3ed10 100644 --- a/test/CodeGen/AMDGPU/sra.ll +++ b/test/CodeGen/AMDGPU/sra.ll @@ -1,213 +1,258 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s -;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s -;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=VI %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s -;EG-LABEL: {{^}}ashr_v2i32: -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +declare i32 @llvm.r600.read.tidig.x() #0 -;SI-LABEL: {{^}}ashr_v2i32: -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; FUNC-LABEL: {{^}}ashr_v2i32: +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI-LABEL: {{^}}ashr_v2i32: -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1 - %a = load <2 x i32>, <2 x i32> addrspace(1) * %in - %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr + %a = load <2 x i32>, <2 x i32> addrspace(1)* %in + %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr %result = ashr <2 x i32> %a, %b store <2 x i32> %result, <2 x i32> addrspace(1)* %out ret void } -;EG-LABEL: {{^}}ashr_v4i32: -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; FUNC-LABEL: {{^}}ashr_v4i32: +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-LABEL: {{^}}ashr_v4i32: -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} - -;VI-LABEL: {{^}}ashr_v4i32: -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1 - %a = load <4 x i32>, <4 x i32> addrspace(1) * %in - %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr + %a = load <4 x i32>, <4 x i32> addrspace(1)* %in + %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr %result = ashr <4 x i32> %a, %b store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } -;EG-LABEL: {{^}}ashr_i64: -;EG: ASHR - -;SI-LABEL: {{^}}ashr_i64: -;SI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 - -;VI-LABEL: {{^}}ashr_i64: -;VI: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 +; FUNC-LABEL: {{^}}s_ashr_i64: +; GCN: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8 -define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { +; EG: ASHR +define void @s_ashr_i64(i64 addrspace(1)* %out, i32 %in) { entry: - %0 = sext i32 %in to i64 - %1 = ashr i64 %0, 8 - store i64 %1, i64 addrspace(1)* %out + %in.ext = sext i32 %in to i64 + %ashr = ashr i64 %in.ext, 8 + store i64 %ashr, i64 addrspace(1)* %out ret void } -;EG-LABEL: {{^}}ashr_i64_2: -;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] -;EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} -;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 -;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] -;EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} -;EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}} -;EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal -;EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal -;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal -;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} -;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} - -;SI-LABEL: {{^}}ashr_i64_2: -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-LABEL: {{^}}ashr_i64_2: -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; FUNC-LABEL: {{^}}ashr_i64_2: +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} + +; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]] +; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}} +; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal +; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1 +; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] +; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XYZW]}} +; EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}} +; EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal +; EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal +; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal +; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} +; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}} define void @ashr_i64_2(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { entry: %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1 - %a = load i64, i64 addrspace(1) * %in - %b = load i64, i64 addrspace(1) * %b_ptr + %a = load i64, i64 addrspace(1)* %in + %b = load i64, i64 addrspace(1)* %b_ptr %result = ashr i64 %a, %b store i64 %result, i64 addrspace(1)* %out ret void } -;EG-LABEL: {{^}}ashr_v2i64: -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHA]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHB]] -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: ASHR {{.*}}, [[SHA]] -;EG-DAG: ASHR {{.*}}, [[SHB]] -;EG-DAG: LSHR {{.*}}, [[SHA]] -;EG-DAG: LSHR {{.*}}, [[SHB]] -;EG-DAG: OR_INT -;EG-DAG: OR_INT -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ASHR -;EG-DAG: ASHR -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT - -;SI-LABEL: {{^}}ashr_v2i64: -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-LABEL: {{^}}ashr_v2i64: -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; FUNC-LABEL: {{^}}ashr_v2i64: +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: ASHR {{.*}}, [[SHA]] +; EG-DAG: ASHR {{.*}}, [[SHB]] +; EG-DAG: LSHR {{.*}}, [[SHA]] +; EG-DAG: LSHR {{.*}}, [[SHB]] +; EG-DAG: OR_INT +; EG-DAG: OR_INT +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ASHR +; EG-DAG: ASHR +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT define void @ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1 - %a = load <2 x i64>, <2 x i64> addrspace(1) * %in - %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr + %a = load <2 x i64>, <2 x i64> addrspace(1)* %in + %b = load <2 x i64>, <2 x i64> addrspace(1)* %b_ptr %result = ashr <2 x i64> %a, %b store <2 x i64> %result, <2 x i64> addrspace(1)* %out ret void } -;EG-LABEL: {{^}}ashr_v4i64: -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] -;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHA]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHB]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHC]] -;EG-DAG: LSHL {{\*? *}}[[COMPSHD]] -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: LSHL {{.*}}, 1 -;EG-DAG: ASHR {{.*}}, [[SHA]] -;EG-DAG: ASHR {{.*}}, [[SHB]] -;EG-DAG: ASHR {{.*}}, [[SHC]] -;EG-DAG: ASHR {{.*}}, [[SHD]] -;EG-DAG: LSHR {{.*}}, [[SHA]] -;EG-DAG: LSHR {{.*}}, [[SHB]] -;EG-DAG: LSHR {{.*}}, [[SHA]] -;EG-DAG: LSHR {{.*}}, [[SHB]] -;EG-DAG: OR_INT -;EG-DAG: OR_INT -;EG-DAG: OR_INT -;EG-DAG: OR_INT -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal -;EG-DAG: ASHR -;EG-DAG: ASHR -;EG-DAG: ASHR -;EG-DAG: ASHR -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: ASHR {{.*}}, literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal -;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT -;EG-DAG: CNDE_INT - -;SI-LABEL: {{^}}ashr_v4i64: -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} -;SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} - -;VI-LABEL: {{^}}ashr_v4i64: -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} -;VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; FIXME: Broken on r600 +; XFUNC-LABEL: {{^}}s_ashr_v2i64: +; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}} +; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}} +; define void @s_ashr_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in, <2 x i64> %a, <2 x i64> %b) { +; %result = ashr <2 x i64> %a, %b +; store <2 x i64> %result, <2 x i64> addrspace(1)* %out +; ret void +; } + +; FUNC-LABEL: {{^}}ashr_v4i64: +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} +; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}} + +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]] +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]] +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]] +; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHA]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHB]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHC]] +; EG-DAG: LSHL {{\*? *}}[[COMPSHD]] +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: LSHL {{.*}}, 1 +; EG-DAG: ASHR {{.*}}, [[SHA]] +; EG-DAG: ASHR {{.*}}, [[SHB]] +; EG-DAG: ASHR {{.*}}, [[SHC]] +; EG-DAG: ASHR {{.*}}, [[SHD]] +; EG-DAG: LSHR {{.*}}, [[SHA]] +; EG-DAG: LSHR {{.*}}, [[SHB]] +; EG-DAG: LSHR {{.*}}, [[SHA]] +; EG-DAG: LSHR {{.*}}, [[SHB]] +; EG-DAG: OR_INT +; EG-DAG: OR_INT +; EG-DAG: OR_INT +; EG-DAG: OR_INT +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal +; EG-DAG: ASHR +; EG-DAG: ASHR +; EG-DAG: ASHR +; EG-DAG: ASHR +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: ASHR {{.*}}, literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal +; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT +; EG-DAG: CNDE_INT define void @ashr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1 - %a = load <4 x i64>, <4 x i64> addrspace(1) * %in - %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr + %a = load <4 x i64>, <4 x i64> addrspace(1)* %in + %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr %result = ashr <4 x i64> %a, %b store <4 x i64> %result, <4 x i64> addrspace(1)* %out ret void } +; GCN-LABEL: {{^}}s_ashr_32_i64: +; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}} +; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31 +; GCN: s_add_u32 s{{[0-9]+}}, s[[HI]], s{{[0-9]+}} +; GCN: s_addc_u32 s{{[0-9]+}}, s[[SHIFT]], s{{[0-9]+}} +define void @s_ashr_32_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { + %result = ashr i64 %a, 32 + %add = add i64 %result, %b + store i64 %add, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_ashr_32_i64: +; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; VI: flat_load_dword v[[HI:[0-9]+]] +; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]] +; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[HI]]:[[SHIFT]]{{\]}} +define void @v_ashr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %tid = call i32 @llvm.r600.read.tidig.x() #0 + %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid + %a = load i64, i64 addrspace(1)* %gep.in + %result = ashr i64 %a, 32 + store i64 %result, i64 addrspace(1)* %gep.out + ret void +} + +; GCN-LABEL: {{^}}s_ashr_63_i64: +; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}} +; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31 +; GCN: s_add_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}} +; GCN: s_addc_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}} +define void @s_ashr_63_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) { + %result = ashr i64 %a, 63 + %add = add i64 %result, %b + store i64 %add, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}v_ashr_63_i64: +; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 +; VI: flat_load_dword v[[HI:[0-9]+]] +; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]] +; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[SHIFT]] +; GCN: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[SHIFT]]:[[COPY]]{{\]}} +define void @v_ashr_63_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) { + %tid = call i32 @llvm.r600.read.tidig.x() #0 + %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid + %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid + %a = load i64, i64 addrspace(1)* %gep.in + %result = ashr i64 %a, 63 + store i64 %result, i64 addrspace(1)* %gep.out + ret void +} + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/store-barrier.ll b/test/CodeGen/AMDGPU/store-barrier.ll index ba4049f28a6e..57a93ccd2505 100644 --- a/test/CodeGen/AMDGPU/store-barrier.ll +++ b/test/CodeGen/AMDGPU/store-barrier.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck --check-prefix=CHECK %s -; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -march=amdgcn -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt -enable-misched < %s | FileCheck %s ; This test is for a bug in the machine scheduler where stores without ; an underlying object would be moved across the barrier. In this @@ -12,16 +12,16 @@ ; CHECK: s_barrier ; CHECK: s_endpgm ; Function Attrs: nounwind -define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) { +define void @test(<2 x i8> addrspace(3)* nocapture %arg, <2 x i8> addrspace(1)* nocapture readonly %arg1, i32 addrspace(1)* nocapture readonly %arg2, <2 x i8> addrspace(1)* nocapture %arg3, i32 %arg4, i64 %tmp9) #0 { bb: %tmp10 = getelementptr inbounds i32, i32 addrspace(1)* %arg2, i64 %tmp9 %tmp13 = load i32, i32 addrspace(1)* %tmp10, align 2 %tmp14 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp13 - %tmp15 = load <2 x i8>, <2 x i8> addrspace(3)* %tmp14, align 2 + %tmp15 = load <2 x i8>, <2 x i8> addrspace(3)* %tmp14, align 1 %tmp16 = add i32 %tmp13, 1 %tmp17 = getelementptr inbounds <2 x i8>, <2 x i8> addrspace(3)* %arg, i32 %tmp16 - store <2 x i8> %tmp15, <2 x i8> addrspace(3)* %tmp17, align 2 - tail call void @llvm.AMDGPU.barrier.local() #2 + store <2 x i8> %tmp15, <2 x i8> addrspace(3)* %tmp17, align 1 + tail call void @llvm.amdgcn.s.barrier() %tmp25 = load i32, i32 addrspace(1)* %tmp10, align 4 %tmp26 = sext i32 %tmp25 to i64 %tmp27 = sext i32 %arg4 to i64 @@ -37,6 +37,7 @@ bb: } ; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.local() #2 +declare void @llvm.amdgcn.s.barrier() #1 -attributes #2 = { convergent nounwind } +attributes #0 = { nounwind } +attributes #1 = { convergent nounwind } diff --git a/test/CodeGen/AMDGPU/store-v3i64.ll b/test/CodeGen/AMDGPU/store-v3i64.ll index e0c554ad2c17..b4d7505e0a8a 100644 --- a/test/CodeGen/AMDGPU/store-v3i64.ll +++ b/test/CodeGen/AMDGPU/store-v3i64.ll @@ -1,29 +1,128 @@ -; XFAIL: * -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; SI-LABEL: {{^}}global_store_v3i64: -; SI: buffer_store_dwordx4 -; SI: buffer_store_dwordx4 +; GCN-LABEL: {{^}}global_store_v3i64: +; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 +; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} define void @global_store_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> %x) { store <3 x i64> %x, <3 x i64> addrspace(1)* %out, align 32 ret void } -; SI-LABEL: {{^}}global_store_v3i64_unaligned: +; GCN-LABEL: {{^}}global_store_v3i64_unaligned: +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte + +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte +; GCN: buffer_store_byte define void @global_store_v3i64_unaligned(<3 x i64> addrspace(1)* %out, <3 x i64> %x) { store <3 x i64> %x, <3 x i64> addrspace(1)* %out, align 1 ret void } -; SI-LABEL: {{^}}local_store_v3i64: +; GCN-LABEL: {{^}}local_store_v3i64: +; GCN: ds_write_b64 +; GCN: ds_write_b64 +; GCN: ds_write_b64 define void @local_store_v3i64(<3 x i64> addrspace(3)* %out, <3 x i64> %x) { store <3 x i64> %x, <3 x i64> addrspace(3)* %out, align 32 ret void } -; SI-LABEL: {{^}}local_store_v3i64_unaligned: -define void @local_store_v3i64_unaligned(<3 x i64> addrspace(1)* %out, <3 x i64> %x) { - store <3 x i64> %x, <3 x i64> addrspace(1)* %out, align 1 +; GCN-LABEL: {{^}}local_store_v3i64_unaligned: +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +define void @local_store_v3i64_unaligned(<3 x i64> addrspace(3)* %out, <3 x i64> %x) { + store <3 x i64> %x, <3 x i64> addrspace(3)* %out, align 1 + ret void +} + +; GCN-LABEL: {{^}}global_truncstore_v3i64_to_v3i32: +; GCN-DAG: buffer_store_dwordx2 +; GCN-DAG: buffer_store_dword v +define void @global_truncstore_v3i64_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i64> %x) { + %trunc = trunc <3 x i64> %x to <3 x i32> + store <3 x i32> %trunc, <3 x i32> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_truncstore_v3i64_to_v3i16: +; GCN-DAG: buffer_store_short +; GCN-DAG: buffer_store_dword v +define void @global_truncstore_v3i64_to_v3i16(<3 x i16> addrspace(1)* %out, <3 x i64> %x) { + %trunc = trunc <3 x i64> %x to <3 x i16> + store <3 x i16> %trunc, <3 x i16> addrspace(1)* %out + ret void +} + + +; GCN-LABEL: {{^}}global_truncstore_v3i64_to_v3i8: +; GCN-DAG: buffer_store_short +; GCN-DAG: buffer_store_byte v +define void @global_truncstore_v3i64_to_v3i8(<3 x i8> addrspace(1)* %out, <3 x i64> %x) { + %trunc = trunc <3 x i64> %x to <3 x i8> + store <3 x i8> %trunc, <3 x i8> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}global_truncstore_v3i64_to_v3i1: +; GCN-DAG: buffer_store_byte v +; GCN-DAG: buffer_store_byte v +; GCN-DAG: buffer_store_byte v +define void @global_truncstore_v3i64_to_v3i1(<3 x i1> addrspace(1)* %out, <3 x i64> %x) { + %trunc = trunc <3 x i64> %x to <3 x i1> + store <3 x i1> %trunc, <3 x i1> addrspace(1)* %out ret void } diff --git a/test/CodeGen/AMDGPU/store.ll b/test/CodeGen/AMDGPU/store.ll index d22f43fa05ef..68c659fdd2ff 100644 --- a/test/CodeGen/AMDGPU/store.ll +++ b/test/CodeGen/AMDGPU/store.ll @@ -77,12 +77,31 @@ entry: ret void } +; FUNC-LABEL: {{^}}store_i24: +; SI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 +; SI-DAG: buffer_store_byte +; SI-DAG: buffer_store_short +define void @store_i24(i24 addrspace(1)* %out, i24 %in) { +entry: + store i24 %in, i24 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}store_i25: +; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}} +; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]] +; SI: buffer_store_dword [[VAND]] +define void @store_i25(i25 addrspace(1)* %out, i25 %in) { +entry: + store i25 %in, i25 addrspace(1)* %out + ret void +} + ; FUNC-LABEL: {{^}}store_v2i8: ; EG: MEM_RAT MSKOR ; EG-NOT: MEM_RAT MSKOR -; SI: buffer_store_byte -; SI: buffer_store_byte +; SI: buffer_store_short define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i8> @@ -96,8 +115,7 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD -; SI: buffer_store_short -; SI: buffer_store_short +; SI: buffer_store_dword define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -110,10 +128,7 @@ entry: ; CM: MEM_RAT_CACHELESS STORE_DWORD -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte +; SI: buffer_store_dword define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i8> @@ -135,17 +150,9 @@ define void @store_f32(float addrspace(1)* %out, float %in) { } ; FUNC-LABEL: {{^}}store_v4i16: -; EG: MEM_RAT MSKOR -; EG: MEM_RAT MSKOR -; EG: MEM_RAT MSKOR -; EG: MEM_RAT MSKOR -; EG-NOT: MEM_RAT MSKOR +; MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW -; SI: buffer_store_short -; SI: buffer_store_short -; SI: buffer_store_short -; SI: buffer_store_short -; SI-NOT: buffer_store_byte +; SI: buffer_store_dwordx2 define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i16> @@ -239,8 +246,7 @@ define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { ; CM: LDS_WRITE -; SI: ds_write_b16 -; SI: ds_write_b16 +; SI: ds_write_b32 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(3)* %out @@ -252,10 +258,7 @@ entry: ; CM: LDS_WRITE -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 +; SI: ds_write_b32 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(3)* %out @@ -287,8 +290,7 @@ entry: ; CM: LDS_WRITE ; CM: LDS_WRITE -; SI: ds_write_b64 -; SI: ds_write_b64 +; SI: ds_write2_b64 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(3)* %out @@ -358,20 +360,13 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } - ; When i128 was a legal type this program generated cannot select errors: ; FUNC-LABEL: {{^}}"i128-const-store": -; FIXME: We should be able to to this with one store instruction -; EG: STORE_RAW -; EG: STORE_RAW -; EG: STORE_RAW -; EG: STORE_RAW -; CM: STORE_DWORD -; CM: STORE_DWORD -; CM: STORE_DWORD -; CM: STORE_DWORD +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 1 + +; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+}}, T{{[0-9]+}}.X + ; SI: buffer_store_dwordx4 define void @i128-const-store(i32 addrspace(1)* %out) { entry: @@ -384,3 +379,5 @@ entry: store i32 2, i32 addrspace(1)* %arrayidx6, align 4 ret void } + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/structurize.ll b/test/CodeGen/AMDGPU/structurize.ll index 02e592e9a559..174e64e2cf8b 100644 --- a/test/CodeGen/AMDGPU/structurize.ll +++ b/test/CodeGen/AMDGPU/structurize.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood -mattr=disable-irstructurizer | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood -r600-ir-structurize=0 | FileCheck %s ; Test case for a crash in the AMDILCFGStructurizer from a CFG like this: ; ; entry diff --git a/test/CodeGen/AMDGPU/structurize1.ll b/test/CodeGen/AMDGPU/structurize1.ll index 77432c1f9d2b..db0f50247e38 100644 --- a/test/CodeGen/AMDGPU/structurize1.ll +++ b/test/CodeGen/AMDGPU/structurize1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=r600 -mattr=disable-ifcvt -mcpu=redwood | FileCheck %s +; RUN: llc -march=r600 -mcpu=redwood -r600-if-convert=0 < %s | FileCheck %s ; This tests for abug where the AMDILCFGStructurizer was crashing on loops ; like this: diff --git a/test/CodeGen/AMDGPU/sub.ll b/test/CodeGen/AMDGPU/sub.ll index 9f9446a4e608..5a026cdf2990 100644 --- a/test/CodeGen/AMDGPU/sub.ll +++ b/test/CodeGen/AMDGPU/sub.ll @@ -58,13 +58,11 @@ define void @test_sub_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1) ; SI: s_sub_u32 ; SI: s_subb_u32 -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] -; EG-DAG: SUB_INT {{[* ]*}}[[LO]] +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG-DAG: SUB_INT {{[* ]*}} ; EG-DAG: SUBB_UINT ; EG-DAG: SUB_INT -; EG-DAG: SUB_INT {{[* ]*}}[[HI]] -; EG-NOT: SUB +; EG-DAG: SUB_INT {{[* ]*}} define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind { %result = sub i64 %a, %b store i64 %result, i64 addrspace(1)* %out, align 8 @@ -75,13 +73,11 @@ define void @s_sub_i64(i64 addrspace(1)* noalias %out, i64 %a, i64 %b) nounwind ; SI: v_sub_i32_e32 ; SI: v_subb_u32_e32 -; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.[XYZW]]] -; EG: MEM_RAT_CACHELESS STORE_RAW [[HI:T[0-9]+\.[XYZW]]] -; EG-DAG: SUB_INT {{[* ]*}}[[LO]] +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY +; EG-DAG: SUB_INT {{[* ]*}} ; EG-DAG: SUBB_UINT ; EG-DAG: SUB_INT -; EG-DAG: SUB_INT {{[* ]*}}[[HI]] -; EG-NOT: SUB +; EG-DAG: SUB_INT {{[* ]*}} define void @v_sub_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %inA, i64 addrspace(1)* noalias %inB) nounwind { %tid = call i32 @llvm.r600.read.tidig.x() readnone %a_ptr = getelementptr i64, i64 addrspace(1)* %inA, i32 %tid @@ -110,13 +106,13 @@ define void @v_test_sub_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace( } ; FUNC-LABEL: {{^}}v_test_sub_v4i64: -; SI: v_sub_i32_e32 +; SI: v_subrev_i32_e32 ; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 +; SI: v_subrev_i32_e32 ; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 +; SI: v_subrev_i32_e32 ; SI: v_subb_u32_e32 -; SI: v_sub_i32_e32 +; SI: v_subrev_i32_e32 ; SI: v_subb_u32_e32 define void @v_test_sub_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* noalias %inA, <4 x i64> addrspace(1)* noalias %inB) { %tid = call i32 @llvm.r600.read.tidig.x() readnone diff --git a/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll b/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll index c4dae4736cfa..ec2ed78b4954 100644 --- a/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll +++ b/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll @@ -44,7 +44,7 @@ for.inc.1: ; preds = %do.body.1562.prehea ; SI-LABEL: {{^}}foo: ; SI: s_endpgm -define void @foo() #0 { +define amdgpu_ps void @foo() #0 { bb: br i1 undef, label %bb2, label %bb1 @@ -67,7 +67,7 @@ bb7: ; preds = %bb6 br label %bb4 bb9: ; preds = %bb2 - %tmp10 = call <4 x float> @llvm.SI.sample.v2i32(<2 x i32> undef, <32 x i8> undef, <16 x i8> undef, i32 2) + %tmp10 = call <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %tmp11 = extractelement <4 x float> %tmp10, i32 1 %tmp12 = extractelement <4 x float> %tmp10, i32 3 br label %bb14 @@ -98,12 +98,12 @@ bb27: ; preds = %bb24 } ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.sample.v2i32(<2 x i32>, <32 x i8>, <16 x i8>, i32) #1 +declare <4 x float> @llvm.SI.image.sample.v2i32(<2 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 ; Function Attrs: nounwind readnone declare i32 @llvm.SI.packf16(float, float) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" "enable-no-nans-fp-math"="true" "unsafe-fp-math"="true" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll b/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll index ac9bedb2f8b5..4b6f65a77b9a 100644 --- a/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll +++ b/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll @@ -7,23 +7,25 @@ target triple="amdgcn--" ; CHECK: s_load_dword s2, s[0:1], 0x9 ; CHECK-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xb ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: v_mov_b32_e32 v0, s2 -; CHECK-NEXT: s_and_saveexec_b64 s[2:3], s[0:1] +; CHECK: v_mbcnt_lo_u32_b32_e64 +; CHECK-NEXT: v_cmp_eq_i32_e32 vcc, 0, v0 +; CHECK-NEXT: s_and_saveexec_b64 s[2:3], vcc ; CHECK-NEXT: s_xor_b64 s[2:3], exec, s[2:3] ; BB0_1: -; CHECK: s_load_dword s6, s[0:1], 0xa +; CHECK: s_load_dword s0, s[0:1], 0xa ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: v_mov_b32_e32 v0, s6 ; BB0_2: ; CHECK: s_or_b64 exec, exec, s[2:3] ; CHECK-NEXT: s_mov_b32 s7, 0xf000 ; CHECK-NEXT: s_mov_b32 s6, -1 -; CHECK-NEXT: buffer_store_dword v1, s[4:7], 0 +; CHECK-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; CHECK-NEXT: s_endpgm define void @foobar(float %a0, float %a1, float addrspace(1)* %out) nounwind { entry: %v0 = insertelement <4 x float> undef, float %a0, i32 0 - br i1 undef, label %ift, label %ife + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 + %cnd = icmp eq i32 %tid, 0 + br i1 %cnd, label %ift, label %ife ift: %v1 = insertelement <4 x float> undef, float %a1, i32 0 @@ -35,3 +37,7 @@ ife: store float %v2, float addrspace(1)* %out, align 4 ret void } + +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 + +attributes #0 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/swizzle-export.ll b/test/CodeGen/AMDGPU/swizzle-export.ll index 000ee2faa478..7cf380520d42 100644 --- a/test/CodeGen/AMDGPU/swizzle-export.ll +++ b/test/CodeGen/AMDGPU/swizzle-export.ll @@ -6,7 +6,7 @@ ;EG: EXPORT T{{[0-9]+}}.XXWX ;EG: EXPORT T{{[0-9]+}}.XXXW -define void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -68,27 +68,27 @@ main_body: %57 = insertelement <4 x float> %56, float %1, i32 1 %58 = insertelement <4 x float> %57, float %2, i32 2 %59 = insertelement <4 x float> %58, float %3, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %59, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %59, i32 60, i32 1) %60 = insertelement <4 x float> undef, float %10, i32 0 %61 = insertelement <4 x float> %60, float %13, i32 1 %62 = insertelement <4 x float> %61, float %16, i32 2 %63 = insertelement <4 x float> %62, float %19, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %63, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %63, i32 0, i32 2) %64 = insertelement <4 x float> undef, float %22, i32 0 %65 = insertelement <4 x float> %64, float %25, i32 1 %66 = insertelement <4 x float> %65, float %28, i32 2 %67 = insertelement <4 x float> %66, float %31, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %67, i32 1, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %67, i32 1, i32 2) %68 = insertelement <4 x float> undef, float %34, i32 0 %69 = insertelement <4 x float> %68, float %37, i32 1 %70 = insertelement <4 x float> %69, float %40, i32 2 %71 = insertelement <4 x float> %70, float %43, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %71, i32 2, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %71, i32 2, i32 2) %72 = insertelement <4 x float> undef, float %46, i32 0 %73 = insertelement <4 x float> %72, float %49, i32 1 %74 = insertelement <4 x float> %73, float %52, i32 2 %75 = insertelement <4 x float> %74, float %55, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %75, i32 3, i32 2) ret void } @@ -96,7 +96,7 @@ main_body: ; EG: T{{[0-9]+}}.XY__ ; EG: T{{[0-9]+}}.ZXY0 -define void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) #0 { +define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1) { main_body: %0 = extractelement <4 x float> %reg1, i32 0 %1 = extractelement <4 x float> %reg1, i32 1 @@ -111,19 +111,18 @@ main_body: %10 = extractelement <4 x float> %9, i32 1 %11 = insertelement <4 x float> undef, float %2, i32 0 %12 = insertelement <4 x float> %11, float %3, i32 1 - call void @llvm.R600.store.swizzle(<4 x float> %12, i32 60, i32 1) + call void @llvm.r600.store.swizzle(<4 x float> %12, i32 60, i32 1) %13 = insertelement <4 x float> undef, float %6, i32 0 %14 = insertelement <4 x float> %13, float %8, i32 1 %15 = insertelement <4 x float> %14, float %10, i32 2 %16 = insertelement <4 x float> %15, float 0.000000e+00, i32 3 - call void @llvm.R600.store.swizzle(<4 x float> %16, i32 0, i32 2) + call void @llvm.r600.store.swizzle(<4 x float> %16, i32 0, i32 2) ret void } ; Function Attrs: nounwind readonly declare float @llvm.cos.f32(float) #1 -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) -attributes #0 = { "ShaderType"="1" } attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/target-cpu.ll b/test/CodeGen/AMDGPU/target-cpu.ll new file mode 100644 index 000000000000..c1662acbf2a0 --- /dev/null +++ b/test/CodeGen/AMDGPU/target-cpu.ll @@ -0,0 +1,112 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s + +declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #1 + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +; CI+ intrinsic +declare void @llvm.amdgcn.s.dcache.inv.vol() #0 + +; VI+ intrinsic +declare void @llvm.amdgcn.s.dcache.wb() #0 + +; CHECK-LABEL: {{^}}target_none: +; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 +; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] +; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 +define void @target_none() #0 { + %kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() + %kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 + %kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* + %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext + store i32 0, i32 addrspace(1)* %gep + ret void +} + +; CHECK-LABEL: {{^}}target_tahiti: +; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 +; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] +; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 +define void @target_tahiti() #1 { + %kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() + %kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 + %kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* + %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext + store i32 0, i32 addrspace(1)* %gep + ret void +} + +; CHECK-LABEL: {{^}}target_bonaire: +; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100 +; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 +; CHECK: s_dcache_inv_vol +define void @target_bonaire() #3 { + %kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() + %kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 + %kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* + %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext + store i32 0, i32 addrspace(1)* %gep + call void @llvm.amdgcn.s.dcache.inv.vol() + ret void +} + +; CHECK-LABEL: {{^}}target_fiji: +; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x400 +; CHECK: flat_store_dword +; CHECK: s_dcache_wb{{$}} +define void @target_fiji() #4 { + %kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() + %kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 + %kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* + %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext + store i32 0, i32 addrspace(1)* %gep + call void @llvm.amdgcn.s.dcache.wb() + ret void +} + +; CHECK-LABEL: {{^}}promote_alloca_enabled: +; CHECK: ds_read_b32 +; CHECK: ; LDSByteSize: 5120 +define void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp + %load = load i32, i32* %arrayidx1 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}promote_alloca_disabled: +; CHECK: SCRATCH_RSRC_DWORD0 +; CHECK: SCRATCH_RSRC_DWORD1 +; CHECK: ScratchSize: 24 +define void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 { +entry: + %stack = alloca [5 x i32], align 4 + %tmp = load i32, i32 addrspace(1)* %in, align 4 + %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp + %load = load i32, i32* %arrayidx1 + store i32 %load, i32 addrspace(1)* %out + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind "target-cpu"="tahiti" } +attributes #3 = { nounwind "target-cpu"="bonaire" } +attributes #4 = { nounwind "target-cpu"="fiji" } +attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-max-waves-per-eu"="3" } +attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-max-waves-per-eu"="3" } diff --git a/test/CodeGen/AMDGPU/tex-clause-antidep.ll b/test/CodeGen/AMDGPU/tex-clause-antidep.ll index cbb9c50974a4..2420286f766e 100644 --- a/test/CodeGen/AMDGPU/tex-clause-antidep.ll +++ b/test/CodeGen/AMDGPU/tex-clause-antidep.ll @@ -3,7 +3,7 @@ ;CHECK: TEX ;CHECK-NEXT: ALU -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_vs void @test(<4 x float> inreg %reg0) { %1 = extractelement <4 x float> %reg0, i32 0 %2 = extractelement <4 x float> %reg0, i32 1 %3 = extractelement <4 x float> %reg0, i32 2 @@ -12,14 +12,12 @@ define void @test(<4 x float> inreg %reg0) #0 { %6 = insertelement <4 x float> %5, float %2, i32 1 %7 = insertelement <4 x float> %6, float %3, i32 2 %8 = insertelement <4 x float> %7, float %4, i32 3 - %9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %11 = fadd <4 x float> %9, %10 - call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0) ret void } -declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } \ No newline at end of file +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/texture-input-merge.ll b/test/CodeGen/AMDGPU/texture-input-merge.ll index 789538af5821..a56a5ca39dcc 100644 --- a/test/CodeGen/AMDGPU/texture-input-merge.ll +++ b/test/CodeGen/AMDGPU/texture-input-merge.ll @@ -2,7 +2,7 @@ ;CHECK-NOT: MOV -define void @test(<4 x float> inreg %reg0) #0 { +define amdgpu_vs void @test(<4 x float> inreg %reg0) { %1 = extractelement <4 x float> %reg0, i32 0 %2 = extractelement <4 x float> %reg0, i32 1 %3 = extractelement <4 x float> %reg0, i32 2 @@ -16,16 +16,14 @@ define void @test(<4 x float> inreg %reg0) #0 { %11 = insertelement <4 x float> undef, float %7, i32 0 %12 = insertelement <4 x float> %11, float %5, i32 1 %13 = insertelement <4 x float> undef, float %8, i32 0 - %14 = call <4 x float> @llvm.R600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %15 = call <4 x float> @llvm.R600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) - %16 = call <4 x float> @llvm.R600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) %17 = fadd <4 x float> %14, %15 %18 = fadd <4 x float> %17, %16 - call void @llvm.R600.store.swizzle(<4 x float> %18, i32 0, i32 0) + call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 0) ret void } -declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone -declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32) - -attributes #0 = { "ShaderType"="1" } \ No newline at end of file +declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone +declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32) diff --git a/test/CodeGen/AMDGPU/trap.ll b/test/CodeGen/AMDGPU/trap.ll new file mode 100644 index 000000000000..1555cfe39b1e --- /dev/null +++ b/test/CodeGen/AMDGPU/trap.ll @@ -0,0 +1,15 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN %s + +; GCN: warning: :0:0: in function trap void (): trap handler not supported + +declare void @llvm.trap() #0 + +; GCN-LABEL: {{^}}trap: +; GCN: s_endpgm +; GCN-NEXT: s_endpgm +define void @trap() { + call void @llvm.trap() + ret void +} + +attributes #0 = { nounwind noreturn } diff --git a/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll b/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll new file mode 100644 index 000000000000..9e2373c55e35 --- /dev/null +++ b/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll @@ -0,0 +1,92 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s + +; CHECK-LABEL: {{^}}trunc_i64_bitcast_v2i32: +; CHECK: buffer_load_dword v +; CHECK: buffer_store_dword v +define void @trunc_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { + %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in + %bc = bitcast <2 x i32> %ld to i64 + %trunc = trunc i64 %bc to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}trunc_i96_bitcast_v3i32: +; CHECK: buffer_load_dword v +; CHECK: buffer_store_dword v +define void @trunc_i96_bitcast_v3i32(i32 addrspace(1)* %out, <3 x i32> addrspace(1)* %in) { + %ld = load <3 x i32>, <3 x i32> addrspace(1)* %in + %bc = bitcast <3 x i32> %ld to i96 + %trunc = trunc i96 %bc to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}trunc_i128_bitcast_v4i32: +; CHECK: buffer_load_dword v +; CHECK: buffer_store_dword v +define void @trunc_i128_bitcast_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { + %ld = load <4 x i32>, <4 x i32> addrspace(1)* %in + %bc = bitcast <4 x i32> %ld to i128 + %trunc = trunc i128 %bc to i32 + store i32 %trunc, i32 addrspace(1)* %out + ret void +} + +; Don't want load width reduced in this case. +; CHECK-LABEL: {{^}}trunc_i16_bitcast_v2i16: +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: buffer_store_short [[VAL]] +define void @trunc_i16_bitcast_v2i16(i16 addrspace(1)* %out, <2 x i16> addrspace(1)* %in) { + %ld = load <2 x i16>, <2 x i16> addrspace(1)* %in + %bc = bitcast <2 x i16> %ld to i32 + %trunc = trunc i32 %bc to i16 + store i16 %trunc, i16 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}trunc_i16_bitcast_v4i16: +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: buffer_store_short [[VAL]] +define void @trunc_i16_bitcast_v4i16(i16 addrspace(1)* %out, <4 x i16> addrspace(1)* %in) { + %ld = load <4 x i16>, <4 x i16> addrspace(1)* %in + %bc = bitcast <4 x i16> %ld to i64 + %trunc = trunc i64 %bc to i16 + store i16 %trunc, i16 addrspace(1)* %out + ret void +} + +; FIXME: Don't want load width reduced in this case. +; CHECK-LABEL: {{^}}trunc_i8_bitcast_v2i8: +; CHECK: buffer_load_ubyte [[VAL:v[0-9]+]] +; CHECK: buffer_store_byte [[VAL]] +define void @trunc_i8_bitcast_v2i8(i8 addrspace(1)* %out, <2 x i8> addrspace(1)* %in) { + %ld = load <2 x i8>, <2 x i8> addrspace(1)* %in + %bc = bitcast <2 x i8> %ld to i16 + %trunc = trunc i16 %bc to i8 + store i8 %trunc, i8 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}trunc_i32_bitcast_v4i8: +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: buffer_store_byte [[VAL]] +define void @trunc_i32_bitcast_v4i8(i8 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) { + %ld = load <4 x i8>, <4 x i8> addrspace(1)* %in + %bc = bitcast <4 x i8> %ld to i32 + %trunc = trunc i32 %bc to i8 + store i8 %trunc, i8 addrspace(1)* %out + ret void +} + +; CHECK-LABEL: {{^}}trunc_i24_bitcast_v3i8: +; CHECK: buffer_load_dword [[VAL:v[0-9]+]] +; CHECK: buffer_store_byte [[VAL]] +define void @trunc_i24_bitcast_v3i8(i8 addrspace(1)* %out, <3 x i8> addrspace(1)* %in) { + %ld = load <3 x i8>, <3 x i8> addrspace(1)* %in + %bc = bitcast <3 x i8> %ld to i24 + %trunc = trunc i24 %bc to i8 + store i8 %trunc, i8 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/trunc-cmp-constant.ll b/test/CodeGen/AMDGPU/trunc-cmp-constant.ll index dac74728b3ce..6d820dbd2692 100644 --- a/test/CodeGen/AMDGPU/trunc-cmp-constant.ll +++ b/test/CodeGen/AMDGPU/trunc-cmp-constant.ll @@ -4,8 +4,7 @@ ; FUNC-LABEL {{^}}sextload_i1_to_i32_trunc_cmp_eq_0: ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]] ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]] -; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}} -; SI: s_xor_b64 s{{\[[0-9]+:[0-9]+\]}}, vcc, -1{{$}} +; SI: v_cmp_eq_i32_e32 vcc, 0, [[TMP]]{{$}} ; SI: v_cndmask_b32_e64 ; SI: buffer_store_byte define void @sextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { @@ -23,7 +22,7 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspa ; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}} ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @zextload_i1_to_i32_trunc_cmp_eq_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = zext i1 %load to i32 @@ -46,7 +45,7 @@ define void @sextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspa ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_eq_1: ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]] ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @zextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = zext i1 %load to i32 @@ -58,7 +57,7 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_1(i1 addrspace(1)* %out, i1 addrspa ; FUNC-LABEL: {{^}}sextload_i1_to_i32_trunc_cmp_eq_neg1: ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]] ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @sextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = sext i1 %load to i32 @@ -82,7 +81,7 @@ define void @zextload_i1_to_i32_trunc_cmp_eq_neg1(i1 addrspace(1)* %out, i1 addr ; FUNC-LABEL {{^}}sextload_i1_to_i32_trunc_cmp_ne_0: ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]] ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @sextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = sext i1 %load to i32 @@ -94,7 +93,7 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspa ; FUNC-LABEL: {{^}}zextload_i1_to_i32_trunc_cmp_ne_0: ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]] ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @zextload_i1_to_i32_trunc_cmp_ne_0(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = zext i1 %load to i32 @@ -120,7 +119,7 @@ define void @sextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspa ; SI: v_cmp_eq_i32_e32 vcc, 1, [[TMP]]{{$}} ; SI-NEXT: s_xor_b64 [[NEG:s\[[0-9]+:[0-9]+\]]], vcc, -1 ; SI-NEXT: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, [[NEG]] -; SI-NEXT: buffer_store_byte [[RESULT]] +; SI: buffer_store_byte [[RESULT]] define void @zextload_i1_to_i32_trunc_cmp_ne_1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) nounwind { %load = load i1, i1 addrspace(1)* %in %ext = zext i1 %load to i32 @@ -159,7 +158,7 @@ define void @zextload_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i1 addr ; SI: buffer_load_sbyte [[LOAD:v[0-9]+]] ; SI: v_cmp_ne_i32_e32 vcc, -1, [[LOAD]]{{$}} ; SI-NEXT: v_cndmask_b32_e64 -; SI-NEXT: buffer_store_byte +; SI: buffer_store_byte define void @masked_load_i1_to_i32_trunc_cmp_ne_neg1(i1 addrspace(1)* %out, i8 addrspace(1)* %in) nounwind { %load = load i8, i8 addrspace(1)* %in %masked = and i8 %load, 255 diff --git a/test/CodeGen/AMDGPU/trunc-store.ll b/test/CodeGen/AMDGPU/trunc-store.ll index 4ba815f26690..cf5c00e65b7d 100644 --- a/test/CodeGen/AMDGPU/trunc-store.ll +++ b/test/CodeGen/AMDGPU/trunc-store.ll @@ -2,22 +2,7 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}truncstore_arg_v16i32_to_v16i8: -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte +; SI: buffer_store_dwordx4 define void @truncstore_arg_v16i32_to_v16i8(<16 x i8> addrspace(1)* %out, <16 x i32> %in) { %trunc = trunc <16 x i32> %in to <16 x i8> store <16 x i8> %trunc, <16 x i8> addrspace(1)* %out @@ -25,22 +10,7 @@ define void @truncstore_arg_v16i32_to_v16i8(<16 x i8> addrspace(1)* %out, <16 x } ; FUNC-LABEL: {{^}}truncstore_arg_v16i64_to_v16i8: -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte +; SI: buffer_store_dwordx4 define void @truncstore_arg_v16i64_to_v16i8(<16 x i8> addrspace(1)* %out, <16 x i64> %in) { %trunc = trunc <16 x i64> %in to <16 x i8> store <16 x i8> %trunc, <16 x i8> addrspace(1)* %out diff --git a/test/CodeGen/AMDGPU/trunc.ll b/test/CodeGen/AMDGPU/trunc.ll index ad52d0f2e238..dbd07fee6bbe 100644 --- a/test/CodeGen/AMDGPU/trunc.ll +++ b/test/CodeGen/AMDGPU/trunc.ll @@ -37,8 +37,8 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) { ; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]], ; SI: s_addc_u32 ; SI: v_mov_b32_e32 -; SI: v_mov_b32_e32 ; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]] +; SI: v_mov_b32_e32 ; SI: buffer_store_dword v[[LO_VREG]], define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) { %aa = add i64 %a, 234 ; Prevent shrinking store. diff --git a/test/CodeGen/AMDGPU/udiv.ll b/test/CodeGen/AMDGPU/udiv.ll index 2a09e0b20498..f72c22095e4a 100644 --- a/test/CodeGen/AMDGPU/udiv.ll +++ b/test/CodeGen/AMDGPU/udiv.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}udiv_i32: ; EG-NOT: SETGE_INT @@ -91,3 +91,57 @@ define void @udiv_i32_div_k_odd(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { store i32 %result, i32 addrspace(1)* %out ret void } + +; FUNC-LABEL: {{^}}v_udiv_i8: +; SI: v_rcp_f32 +; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xff, v{{[0-9]+}} +; SI: buffer_store_dword [[TRUNC]] +define void @v_udiv_i8(i32 addrspace(1)* %out, i8 addrspace(1)* %in) { + %den_ptr = getelementptr i8, i8 addrspace(1)* %in, i8 1 + %num = load i8, i8 addrspace(1) * %in + %den = load i8, i8 addrspace(1) * %den_ptr + %result = udiv i8 %num, %den + %result.ext = zext i8 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_udiv_i16: +; SI: v_rcp_f32 +; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0xffff, v{{[0-9]+}} +; SI: buffer_store_dword [[TRUNC]] +define void @v_udiv_i16(i32 addrspace(1)* %out, i16 addrspace(1)* %in) { + %den_ptr = getelementptr i16, i16 addrspace(1)* %in, i16 1 + %num = load i16, i16 addrspace(1) * %in + %den = load i16, i16 addrspace(1) * %den_ptr + %result = udiv i16 %num, %den + %result.ext = zext i16 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_udiv_i23: +; SI: v_rcp_f32 +; SI: v_and_b32_e32 [[TRUNC:v[0-9]+]], 0x7fffff, v{{[0-9]+}} +; SI: buffer_store_dword [[TRUNC]] +define void @v_udiv_i23(i32 addrspace(1)* %out, i23 addrspace(1)* %in) { + %den_ptr = getelementptr i23, i23 addrspace(1)* %in, i23 1 + %num = load i23, i23 addrspace(1) * %in + %den = load i23, i23 addrspace(1) * %den_ptr + %result = udiv i23 %num, %den + %result.ext = zext i23 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} + +; FUNC-LABEL: {{^}}v_udiv_i24: +; SI-NOT: v_rcp_f32 +define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) { + %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1 + %num = load i24, i24 addrspace(1) * %in + %den = load i24, i24 addrspace(1) * %den_ptr + %result = udiv i24 %num, %den + %result.ext = zext i24 %result to i32 + store i32 %result.ext, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/udivrem.ll b/test/CodeGen/AMDGPU/udivrem.ll index f692b7dfdc27..268f3c764d6e 100644 --- a/test/CodeGen/AMDGPU/udivrem.ll +++ b/test/CodeGen/AMDGPU/udivrem.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s @@ -51,11 +51,11 @@ ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 ; SI: s_endpgm -define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) { +define void @test_udivrem(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 %x, i32 %y) { %result0 = udiv i32 %x, %y - store i32 %result0, i32 addrspace(1)* %out + store i32 %result0, i32 addrspace(1)* %out0 %result1 = urem i32 %x, %y - store i32 %result1, i32 addrspace(1)* %out + store i32 %result1, i32 addrspace(1)* %out1 ret void } @@ -107,50 +107,54 @@ define void @test_udivrem(i32 addrspace(1)* %out, i32 %x, i32 %y) { ; EG-DAG: CNDE_INT ; EG-DAG: CNDE_INT -; SI-DAG: v_rcp_iflag_f32_e32 [[FIRST_RCP:v[0-9]+]] -; SI-DAG: v_mul_hi_u32 [[FIRST_RCP_HI:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: v_mul_lo_i32 [[FIRST_RCP_LO:v[0-9]+]], [[FIRST_RCP]] -; SI-DAG: v_sub_i32_e32 [[FIRST_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[FIRST_RCP_LO]] +; For SI, we used to have checks for the input and output registers +; of the instructions, but these are way too fragile. The division for +; the two vector elements can be intermixed which makes it impossible to +; accurately check all the operands. +; SI-DAG: v_rcp_iflag_f32_e32 +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_mul_lo_i32 +; SI-DAG: v_sub_i32_e32 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_mul_hi_u32 [[FIRST_E:v[0-9]+]], {{v[0-9]+}}, [[FIRST_RCP]] -; SI-DAG: v_add_i32_e32 [[FIRST_RCP_A_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]] -; SI-DAG: v_subrev_i32_e32 [[FIRST_RCP_S_E:v[0-9]+]], vcc, [[FIRST_E]], [[FIRST_RCP]] +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_mul_hi_u32 [[FIRST_Quotient:v[0-9]+]] -; SI-DAG: v_mul_lo_i32 [[FIRST_Num_S_Remainder:v[0-9]+]] -; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder:v[0-9]+]], vcc, [[FIRST_Num_S_Remainder]], v{{[0-9]+}} +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_mul_lo_i32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_and_b32_e32 [[FIRST_Tmp1:v[0-9]+]] -; SI-DAG: v_add_i32_e32 [[FIRST_Quotient_A_One:v[0-9]+]], {{.*}}, [[FIRST_Quotient]] -; SI-DAG: v_subrev_i32_e32 [[FIRST_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_and_b32_e32 +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_add_i32_e32 [[FIRST_Remainder_A_Den:v[0-9]+]], -; SI-DAG: v_subrev_i32_e32 [[FIRST_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_rcp_iflag_f32_e32 [[SECOND_RCP:v[0-9]+]] -; SI-DAG: v_mul_hi_u32 [[SECOND_RCP_HI:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: v_mul_lo_i32 [[SECOND_RCP_LO:v[0-9]+]], [[SECOND_RCP]] -; SI-DAG: v_sub_i32_e32 [[SECOND_NEG_RCP_LO:v[0-9]+]], vcc, 0, [[SECOND_RCP_LO]] +; SI-DAG: v_rcp_iflag_f32_e32 +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_mul_lo_i32 +; SI-DAG: v_sub_i32_e32 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_mul_hi_u32 [[SECOND_E:v[0-9]+]], {{v[0-9]+}}, [[SECOND_RCP]] -; SI-DAG: v_add_i32_e32 [[SECOND_RCP_A_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]] -; SI-DAG: v_subrev_i32_e32 [[SECOND_RCP_S_E:v[0-9]+]], vcc, [[SECOND_E]], [[SECOND_RCP]] +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_mul_hi_u32 [[SECOND_Quotient:v[0-9]+]] -; SI-DAG: v_mul_lo_i32 [[SECOND_Num_S_Remainder:v[0-9]+]] -; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder:v[0-9]+]], vcc, [[SECOND_Num_S_Remainder]], v{{[0-9]+}} +; SI-DAG: v_mul_hi_u32 +; SI-DAG: v_mul_lo_i32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_and_b32_e32 [[SECOND_Tmp1:v[0-9]+]] -; SI-DAG: v_add_i32_e32 [[SECOND_Quotient_A_One:v[0-9]+]], {{.*}}, [[SECOND_Quotient]] -; SI-DAG: v_subrev_i32_e32 [[SECOND_Quotient_S_One:v[0-9]+]], +; SI-DAG: v_and_b32_e32 +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 -; SI-DAG: v_add_i32_e32 [[SECOND_Remainder_A_Den:v[0-9]+]], -; SI-DAG: v_subrev_i32_e32 [[SECOND_Remainder_S_Den:v[0-9]+]], +; SI-DAG: v_add_i32_e32 +; SI-DAG: v_subrev_i32_e32 ; SI-DAG: v_cndmask_b32_e64 ; SI-DAG: v_cndmask_b32_e64 ; SI: s_endpgm diff --git a/test/CodeGen/AMDGPU/udivrem24.ll b/test/CodeGen/AMDGPU/udivrem24.ll index 4de881b66f10..147b95560935 100644 --- a/test/CodeGen/AMDGPU/udivrem24.ll +++ b/test/CodeGen/AMDGPU/udivrem24.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}udiv24_i8: @@ -40,7 +40,7 @@ define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { ret void } -; FUNC-LABEL: {{^}}udiv24_i32: +; FUNC-LABEL: {{^}}udiv23_i32: ; SI: v_cvt_f32_u32 ; SI-DAG: v_cvt_f32_u32 ; SI-DAG: v_rcp_f32 @@ -50,6 +50,23 @@ define void @udiv24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { ; EG-DAG: UINT_TO_FLT ; EG-DAG: RECIP_IEEE ; EG: FLT_TO_UINT +define void @udiv23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i23.0 = shl i32 %num, 9 + %den.i23.0 = shl i32 %den, 9 + %num.i23 = lshr i32 %num.i23.0, 9 + %den.i23 = lshr i32 %den.i23.0, 9 + %result = udiv i32 %num.i23, %den.i23 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}udiv24_i32: +; SI: v_rcp_iflag +; SI-NOT v_rcp_f32 +; EG-NOT: RECIP_IEEE define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 @@ -63,6 +80,40 @@ define void @udiv24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ret void } +; FUNC-LABEL: {{^}}no_udiv24_u23_u24_i32: +; SI: v_rcp_iflag +; SI-NOT v_rcp_f32 +; EG-NOT: RECIP_IEEE +define void @no_udiv24_u23_u24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i23.0 = shl i32 %num, 9 + %den.i24.0 = shl i32 %den, 8 + %num.i23 = lshr i32 %num.i23.0, 9 + %den.i24 = lshr i32 %den.i24.0, 8 + %result = udiv i32 %num.i23, %den.i24 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}no_udiv24_u24_u23_i32: +; SI: v_rcp_iflag +; SI-NOT v_rcp_f32 +; EG-NOT: RECIP_IEEE +define void @no_udiv24_u24_u23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i24.0 = shl i32 %num, 8 + %den.i23.0 = shl i32 %den, 9 + %num.i24 = lshr i32 %num.i24.0, 8 + %den.i23 = lshr i32 %den.i23.0, 9 + %result = udiv i32 %num.i24, %den.i23 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + ; FUNC-LABEL: {{^}}udiv25_i32: ; RCP_IFLAG is for URECIP in the full 32b alg ; SI: v_rcp_iflag @@ -74,11 +125,11 @@ define void @udiv25_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 %den = load i32, i32 addrspace(1) * %den_ptr, align 4 - %num.i24.0 = shl i32 %num, 7 - %den.i24.0 = shl i32 %den, 7 - %num.i24 = lshr i32 %num.i24.0, 7 - %den.i24 = lshr i32 %den.i24.0, 7 - %result = udiv i32 %num.i24, %den.i24 + %num.i25.0 = shl i32 %num, 7 + %den.i25.0 = shl i32 %den, 7 + %num.i25 = lshr i32 %num.i25.0, 7 + %den.i25 = lshr i32 %den.i25.0, 7 + %result = udiv i32 %num.i25, %den.i25 store i32 %result, i32 addrspace(1)* %out, align 4 ret void } @@ -162,15 +213,8 @@ define void @urem24_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %in) { } ; FUNC-LABEL: {{^}}urem24_i32: -; SI: v_cvt_f32_u32 -; SI: v_cvt_f32_u32 -; SI: v_rcp_f32 -; SI: v_cvt_u32_f32 - -; EG: UINT_TO_FLT -; EG-DAG: UINT_TO_FLT -; EG-DAG: RECIP_IEEE -; EG: FLT_TO_UINT +; SI-NOT: v_rcp_f32 +; EG-NOT: RECIP_IEEE define void @urem24_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 %num = load i32, i32 addrspace(1) * %in, align 4 @@ -243,3 +287,41 @@ define void @test_no_urem24_i32_2(i32 addrspace(1)* %out, i32 addrspace(1)* %in) store i32 %result, i32 addrspace(1)* %out, align 4 ret void } + +; FUNC-LABEL: {{^}}test_udiv24_u16_u23_i32: +; SI-DAG: v_rcp_f32 +; SI-DAG: s_mov_b32 [[MASK:s[0-9]+]], 0x7fffff{{$}} +; SI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], + +; EG: RECIP_IEEE +define void @test_udiv24_u16_u23_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i16.0 = shl i32 %num, 16 + %den.i23.0 = shl i32 %den, 9 + %num.i16 = lshr i32 %num.i16.0, 16 + %den.i23 = lshr i32 %den.i23.0, 9 + %result = udiv i32 %num.i16, %den.i23 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} + +; FUNC-LABEL: {{^}}test_udiv24_u23_u16_i32: +; SI-DAG: v_rcp_f32 +; SI-DAG: s_mov_b32 [[MASK:s[0-9]+]], 0x7fffff{{$}} +; SI: v_and_b32_e32 v{{[0-9]+}}, [[MASK]], + +; EG: RECIP_IEEE +define void @test_udiv24_u23_u16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { + %den_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1 + %num = load i32, i32 addrspace(1) * %in, align 4 + %den = load i32, i32 addrspace(1) * %den_ptr, align 4 + %num.i23.0 = shl i32 %num, 9 + %den.i16.0 = shl i32 %den, 16 + %num.i23 = lshr i32 %num.i23.0, 9 + %den.i16 = lshr i32 %den.i16.0, 16 + %result = udiv i32 %num.i23, %den.i16 + store i32 %result, i32 addrspace(1)* %out, align 4 + ret void +} diff --git a/test/CodeGen/AMDGPU/udivrem64.ll b/test/CodeGen/AMDGPU/udivrem64.ll index 9f3069bdf80c..72e6af9a6eea 100644 --- a/test/CodeGen/AMDGPU/udivrem64.ll +++ b/test/CodeGen/AMDGPU/udivrem64.ll @@ -1,4 +1,4 @@ -;RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s +;RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=FUNC %s ;RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG --check-prefix=FUNC %s @@ -184,7 +184,7 @@ define void @test_urem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) { ret void } -;FUNC-LABEL: {{^}}test_udiv2464: +;FUNC-LABEL: {{^}}test_udiv2364: ;EG: UINT_TO_FLT ;EG: UINT_TO_FLT ;EG: FLT_TO_UINT @@ -195,15 +195,15 @@ define void @test_urem3264(i64 addrspace(1)* %out, i64 %x, i64 %y) { ;VI-NOT: v_lshrrev_b64 ;GCN: v_mad_f32 ;GCN: s_endpgm -define void @test_udiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) { - %1 = lshr i64 %x, 40 - %2 = lshr i64 %y, 40 +define void @test_udiv2364(i64 addrspace(1)* %out, i64 %x, i64 %y) { + %1 = lshr i64 %x, 41 + %2 = lshr i64 %y, 41 %result = udiv i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void } -;FUNC-LABEL: {{^}}test_urem2464: +;FUNC-LABEL: {{^}}test_urem2364: ;EG: UINT_TO_FLT ;EG: UINT_TO_FLT ;EG: FLT_TO_UINT @@ -214,9 +214,9 @@ define void @test_udiv2464(i64 addrspace(1)* %out, i64 %x, i64 %y) { ;VI-NOT: v_lshrrev_b64 ;GCN: v_mad_f32 ;GCN: s_endpgm -define void @test_urem2464(i64 addrspace(1)* %out, i64 %x, i64 %y) { - %1 = lshr i64 %x, 40 - %2 = lshr i64 %y, 40 +define void @test_urem2364(i64 addrspace(1)* %out, i64 %x, i64 %y) { + %1 = lshr i64 %x, 41 + %2 = lshr i64 %y, 41 %result = urem i64 %1, %2 store i64 %result, i64 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/uint_to_fp.f64.ll b/test/CodeGen/AMDGPU/uint_to_fp.f64.ll index 65fe580792a5..b36ce6b8d6ca 100644 --- a/test/CodeGen/AMDGPU/uint_to_fp.f64.ll +++ b/test/CodeGen/AMDGPU/uint_to_fp.f64.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64 ; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} @@ -10,7 +10,7 @@ declare i32 @llvm.r600.read.tidig.x() nounwind readnone ; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]] ; SI: buffer_store_dwordx2 [[RESULT]] define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid %val = load i64, i64 addrspace(1)* %gep, align 8 %result = uitofp i64 %val to double @@ -70,14 +70,14 @@ define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i ret void } -; FIXME: select on 0, 0 -; SI-LABEL: {{^}}uint_to_fp_i1_to_f64: -; SI: v_cmp_eq_i32_e64 vcc ; We can't fold the SGPRs into v_cndmask_b32_e32, because it already ; uses an SGPR (implicit vcc). -; SI: v_cndmask_b32_e32 v{{[0-9]+}}, 0, v{{[0-9]+}} -; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 0, vcc -; SI: buffer_store_dwordx2 + +; SI-LABEL: {{^}}uint_to_fp_i1_to_f64: +; SI-DAG: v_cmp_eq_i32_e64 vcc +; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}} +; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}} +; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}} ; SI: s_endpgm define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) { %cmp = icmp eq i32 %in, 0 diff --git a/test/CodeGen/AMDGPU/uint_to_fp.i64.ll b/test/CodeGen/AMDGPU/uint_to_fp.i64.ll index 3ab11442d5cc..27c41e41a0e7 100644 --- a/test/CodeGen/AMDGPU/uint_to_fp.i64.ll +++ b/test/CodeGen/AMDGPU/uint_to_fp.i64.ll @@ -22,7 +22,7 @@ define void @s_uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) #0 { ; GCN-DAG: v_cmp_lt_u64 ; GCN: v_add_i32_e32 [[VR:v[0-9]+]] -; GCN: {{buffer|flat}}_store_dword [[VR]] +; GCN: {{buffer|flat}}_store_dword {{.*}}[[VR]] define void @v_uint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() %in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid diff --git a/test/CodeGen/AMDGPU/uint_to_fp.ll b/test/CodeGen/AMDGPU/uint_to_fp.ll index a3343d1e2d9c..0c3d54cf0d09 100644 --- a/test/CodeGen/AMDGPU/uint_to_fp.ll +++ b/test/CodeGen/AMDGPU/uint_to_fp.ll @@ -103,7 +103,7 @@ define void @s_uint_to_fp_i1_to_f32_load(float addrspace(1)* %out, i1 %in) #0 { ; SI: v_and_b32_e32 {{v[0-9]+}}, 1, {{v[0-9]+}} ; SI: v_cmp_eq_i32 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1.0 -; SI: {{buffer|flat}}_store_dword [[RESULT]], +; SI: {{buffer|flat}}_store_dword {{.*}}[[RESULT]] ; SI: s_endpgm define void @v_uint_to_fp_i1_f32_load(float addrspace(1)* %out, i1 addrspace(1)* %in) #0 { %tid = call i32 @llvm.r600.read.tidig.x() diff --git a/test/CodeGen/AMDGPU/umed3.ll b/test/CodeGen/AMDGPU/umed3.ll new file mode 100644 index 000000000000..a26eb8f9ada9 --- /dev/null +++ b/test/CodeGen/AMDGPU/umed3.ll @@ -0,0 +1,484 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +declare i32 @llvm.r600.read.tidig.x() #0 + +; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i32: +; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +define void @v_test_umed3_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp ult i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_umed3_multi_use_r_i_i_i32: +; GCN: v_max_u32 +; GCN: v_min_u32 +define void @v_test_umed3_multi_use_r_i_i_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp ult i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store volatile i32 %i0, i32 addrspace(1)* %outgep + store volatile i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_umed3_r_i_i_constant_order_i32: +; GCN: v_max_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}} +; GCN: v_min_u32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}} +define void @v_test_umed3_r_i_i_constant_order_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i32 %a, 17 + %i0 = select i1 %icmp0, i32 %a, i32 17 + + %icmp1 = icmp ult i32 %i0, 12 + %i1 = select i1 %icmp1, i32 %i0, i32 12 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_umed3_r_i_i_sign_mismatch_i32: +; GCN: v_max_i32_e32 v{{[0-9]+}}, 12, v{{[0-9]+}} +; GCN: v_min_u32_e32 v{{[0-9]+}}, 17, v{{[0-9]+}} +define void @v_test_umed3_r_i_i_sign_mismatch_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid + %a = load i32, i32 addrspace(1)* %gep0 + + %icmp0 = icmp sgt i32 %a, 12 + %i0 = select i1 %icmp0, i32 %a, i32 12 + + %icmp1 = icmp ult i32 %i0, 17 + %i1 = select i1 %icmp1, i32 %i0, i32 17 + + store i32 %i1, i32 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i64: +; GCN: v_cmp_lt_u64 +; GCN: v_cmp_gt_u64 +define void @v_test_umed3_r_i_i_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i64, i64 addrspace(1)* %out, i32 %tid + %a = load i64, i64 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i64 %a, 12 + %i0 = select i1 %icmp0, i64 %a, i64 12 + + %icmp1 = icmp ult i64 %i0, 17 + %i1 = select i1 %icmp1, i64 %i0, i64 17 + + store i64 %i1, i64 addrspace(1)* %outgep + ret void +} + +; GCN-LABEL: {{^}}v_test_umed3_r_i_i_i16: +; GCN: v_med3_u32 v{{[0-9]+}}, v{{[0-9]+}}, 12, 17 +define void @v_test_umed3_r_i_i_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr) #1 { + %tid = call i32 @llvm.r600.read.tidig.x() + %gep0 = getelementptr i16, i16 addrspace(1)* %aptr, i32 %tid + %outgep = getelementptr i16, i16 addrspace(1)* %out, i32 %tid + %a = load i16, i16 addrspace(1)* %gep0 + + %icmp0 = icmp ugt i16 %a, 12 + %i0 = select i1 %icmp0, i16 %a, i16 12 + + %icmp1 = icmp ult i16 %i0, 17 + %i1 = select i1 %icmp1, i16 %i0, i16 17 + + store i16 %i1, i16 addrspace(1)* %outgep + ret void +} + +define internal i32 @umin(i32 %x, i32 %y) #2 { + %cmp = icmp ult i32 %x, %y + %sel = select i1 %cmp, i32 %x, i32 %y + ret i32 %sel +} + +define internal i32 @umax(i32 %x, i32 %y) #2 { + %cmp = icmp ugt i32 %x, %y + %sel = select i1 %cmp, i32 %x, i32 %y + ret i32 %sel +} + +define internal i16 @umin16(i16 %x, i16 %y) #2 { + %cmp = icmp ult i16 %x, %y + %sel = select i1 %cmp, i16 %x, i16 %y + ret i16 %sel +} + +define internal i16 @umax16(i16 %x, i16 %y) #2 { + %cmp = icmp ugt i16 %x, %y + %sel = select i1 %cmp, i16 %x, i16 %y + ret i16 %sel +} + +define internal i8 @umin8(i8 %x, i8 %y) #2 { + %cmp = icmp ult i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %y + ret i8 %sel +} + +define internal i8 @umax8(i8 %x, i8 %y) #2 { + %cmp = icmp ugt i8 %x, %y + %sel = select i1 %cmp, i8 %x, i8 %y + ret i8 %sel +} + +; 16 combinations + +; 0: max(min(x, y), min(max(x, y), z)) +; 1: max(min(x, y), min(max(y, x), z)) +; 2: max(min(x, y), min(z, max(x, y))) +; 3: max(min(x, y), min(z, max(y, x))) +; 4: max(min(y, x), min(max(x, y), z)) +; 5: max(min(y, x), min(max(y, x), z)) +; 6: max(min(y, x), min(z, max(x, y))) +; 7: max(min(y, x), min(z, max(y, x))) +; +; + commute outermost max + + +; FIXME: In these cases we probably should have used scalar operations +; instead. + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_1: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_2: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_3: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_3(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_4: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_4(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_5: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_5(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_6: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_6(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_7: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_7(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_8: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_8(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_9: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_9(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_10: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_10(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_11: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_11(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_12: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_12(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_13: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_13(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_14: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_14(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_15: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_15(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %y, i32 %x) + %tmp1 = call i32 @umax(i32 %y, i32 %x) + %tmp2 = call i32 @umin(i32 %z, i32 %tmp1) + %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i16_pat_0: +; GCN: s_and_b32 +; GCN: s_and_b32 +; GCN: s_and_b32 +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i16_pat_0(i16 addrspace(1)* %arg, i16 %x, i16 %y, i16 %z) #1 { +bb: + %tmp0 = call i16 @umin16(i16 %x, i16 %y) + %tmp1 = call i16 @umax16(i16 %x, i16 %y) + %tmp2 = call i16 @umin16(i16 %tmp1, i16 %z) + %tmp3 = call i16 @umax16(i16 %tmp0, i16 %tmp2) + store i16 %tmp3, i16 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i8_pat_0: +; GCN: s_and_b32 +; GCN: s_and_b32 +; GCN: s_and_b32 +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i8_pat_0(i8 addrspace(1)* %arg, i8 %x, i8 %y, i8 %z) #1 { +bb: + %tmp0 = call i8 @umin8(i8 %x, i8 %y) + %tmp1 = call i8 @umax8(i8 %x, i8 %y) + %tmp2 = call i8 @umin8(i8 %tmp1, i8 %z) + %tmp3 = call i8 @umax8(i8 %tmp0, i8 %tmp2) + store i8 %tmp3, i8 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_0: +; GCN-NOT: v_med3_u32 +define void @s_test_umed3_i32_pat_0_multi_use_0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp0, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_1: +; GCN-NOT: v_med3_u32 +define void @s_test_umed3_i32_pat_0_multi_use_1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp1, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_2: +; GCN-NOT: v_med3_u32 +define void @s_test_umed3_i32_pat_0_multi_use_2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp2, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_multi_use_result: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_0_multi_use_result(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store volatile i32 %tmp3, i32 addrspace(1)* %arg + store volatile i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_imm_src0: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, 1, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_0_imm_src0(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 1, i32 %y) + %tmp1 = call i32 @umax(i32 1, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_imm_src1: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, 2, v{{[0-9]+}} +define void @s_test_umed3_i32_pat_0_imm_src1(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 2) + %tmp1 = call i32 @umax(i32 %x, i32 2) + %tmp2 = call i32 @umin(i32 %tmp1, i32 %z) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +; GCN-LABEL: {{^}}s_test_umed3_i32_pat_0_imm_src2: +; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, 9 +define void @s_test_umed3_i32_pat_0_imm_src2(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 { +bb: + %tmp0 = call i32 @umin(i32 %x, i32 %y) + %tmp1 = call i32 @umax(i32 %x, i32 %y) + %tmp2 = call i32 @umin(i32 %tmp1, i32 9) + %tmp3 = call i32 @umax(i32 %tmp0, i32 %tmp2) + store i32 %tmp3, i32 addrspace(1)* %arg + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } +attributes #2 = { nounwind readnone alwaysinline } diff --git a/test/CodeGen/AMDGPU/unaligned-load-store.ll b/test/CodeGen/AMDGPU/unaligned-load-store.ll index 82d88ebd3ae7..129748afd938 100644 --- a/test/CodeGen/AMDGPU/unaligned-load-store.ll +++ b/test/CodeGen/AMDGPU/unaligned-load-store.ll @@ -1,62 +1,97 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s +; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=+unaligned-buffer-access -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=UNALIGNED %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=ALIGNED %s -; SI-LABEL: {{^}}unaligned_load_store_i16_local: +; SI-LABEL: {{^}}local_unaligned_load_store_i16: ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_write_b8 ; SI: ds_write_b8 ; SI: s_endpgm -define void @unaligned_load_store_i16_local(i16 addrspace(3)* %p, i16 addrspace(3)* %r) nounwind { +define void @local_unaligned_load_store_i16(i16 addrspace(3)* %p, i16 addrspace(3)* %r) #0 { %v = load i16, i16 addrspace(3)* %p, align 1 store i16 %v, i16 addrspace(3)* %r, align 1 ret void } -; SI-LABEL: {{^}}unaligned_load_store_i16_global: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_store_byte -; SI: buffer_store_byte +; SI-LABEL: {{^}}global_unaligned_load_store_i16: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte + +; UNALIGNED: buffer_load_ushort +; UNALIGNED: buffer_store_short ; SI: s_endpgm -define void @unaligned_load_store_i16_global(i16 addrspace(1)* %p, i16 addrspace(1)* %r) nounwind { +define void @global_unaligned_load_store_i16(i16 addrspace(1)* %p, i16 addrspace(1)* %r) #0 { %v = load i16, i16 addrspace(1)* %p, align 1 store i16 %v, i16 addrspace(1)* %r, align 1 ret void } -; SI-LABEL: {{^}}unaligned_load_store_i32_local: +; FUNC-LABEL: {{^}}local_unaligned_load_store_i32: + ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 +; SI-NOT: v_or +; SI-NOT: v_lshl ; SI: ds_write_b8 ; SI: ds_write_b8 ; SI: ds_write_b8 ; SI: ds_write_b8 ; SI: s_endpgm -define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind { +define void @local_unaligned_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) #0 { %v = load i32, i32 addrspace(3)* %p, align 1 store i32 %v, i32 addrspace(3)* %r, align 1 ret void } -; SI-LABEL: {{^}}unaligned_load_store_i32_global: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace(1)* %r) nounwind { +; SI-LABEL: {{^}}global_unaligned_load_store_i32: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte + +; UNALIGNED: buffer_load_dword +; UNALIGNED: buffer_store_dword +define void @global_unaligned_load_store_i32(i32 addrspace(1)* %p, i32 addrspace(1)* %r) #0 { %v = load i32, i32 addrspace(1)* %p, align 1 store i32 %v, i32 addrspace(1)* %r, align 1 ret void } -; SI-LABEL: {{^}}unaligned_load_store_i64_local: +; SI-LABEL: {{^}}global_align2_load_store_i32: +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_store_short +; ALIGNED: buffer_store_short + +; UNALIGNED: buffer_load_dword +; UNALIGNED: buffer_store_dword +define void @global_align2_load_store_i32(i32 addrspace(1)* %p, i32 addrspace(1)* %r) #0 { + %v = load i32, i32 addrspace(1)* %p, align 2 + store i32 %v, i32 addrspace(1)* %r, align 2 + ret void +} + +; FUNC-LABEL: {{^}}local_align2_load_store_i32: +; GCN: ds_read_u16 +; GCN: ds_read_u16 +; GCN: ds_write_b16 +; GCN: ds_write_b16 +define void @local_align2_load_store_i32(i32 addrspace(3)* %p, i32 addrspace(3)* %r) #0 { + %v = load i32, i32 addrspace(3)* %p, align 2 + store i32 %v, i32 addrspace(3)* %r, align 2 + ret void +} + +; FUNC-LABEL: {{^}}local_unaligned_load_store_i64: ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 @@ -65,139 +100,263 @@ define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 + +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 ; SI: s_endpgm -define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(3)* %r) { +define void @local_unaligned_load_store_i64(i64 addrspace(3)* %p, i64 addrspace(3)* %r) #0 { %v = load i64, i64 addrspace(3)* %p, align 1 store i64 %v, i64 addrspace(3)* %r, align 1 ret void } -; SI-LABEL: {{^}}unaligned_load_store_i64_global: -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_load_ubyte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -; SI: buffer_store_byte -define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace(1)* %r) { - %v = load i64, i64 addrspace(1)* %p, align 1 - store i64 %v, i64 addrspace(1)* %r, align 1 - ret void -} - -; SI-LABEL: {{^}}unaligned_load_store_v4i32_local: -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - +; SI-LABEL: {{^}}local_unaligned_load_store_v2i32: ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 - ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 ; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 - -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 -; SI: ds_write_b8 -; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl + ; SI: ds_write_b8 +; SI-NOT: v_or_b32 +; SI-NOT: v_lshl ; SI: ds_write_b8 ; SI: s_endpgm -define void @unaligned_load_store_v4i32_local(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind { +define void @local_unaligned_load_store_v2i32(<2 x i32> addrspace(3)* %p, <2 x i32> addrspace(3)* %r) #0 { + %v = load <2 x i32>, <2 x i32> addrspace(3)* %p, align 1 + store <2 x i32> %v, <2 x i32> addrspace(3)* %r, align 1 + ret void +} + +; SI-LABEL: {{^}}global_align2_load_store_i64: +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort + +; ALIGNED-NOT: v_or_ +; ALIGNED-NOT: v_lshl + +; ALIGNED: buffer_load_ushort + +; ALIGNED-NOT: v_or_ +; ALIGNED-NOT: v_lshl + +; ALIGNED: buffer_load_ushort + +; ALIGNED-NOT: v_or_ +; ALIGNED-NOT: v_lshl + +; ALIGNED: buffer_store_short +; ALIGNED: buffer_store_short +; ALIGNED: buffer_store_short +; ALIGNED: buffer_store_short + +; UNALIGNED: buffer_load_dwordx2 +; UNALIGNED: buffer_store_dwordx2 +define void @global_align2_load_store_i64(i64 addrspace(1)* %p, i64 addrspace(1)* %r) #0 { + %v = load i64, i64 addrspace(1)* %p, align 2 + store i64 %v, i64 addrspace(1)* %r, align 2 + ret void +} + +; SI-LABEL: {{^}}unaligned_load_store_i64_global: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED-NOT: v_or_ +; ALIGNED-NOT: v_lshl + +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte + +; UNALIGNED: buffer_load_dwordx2 +; UNALIGNED: buffer_store_dwordx2 +define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace(1)* %r) #0 { + %v = load i64, i64 addrspace(1)* %p, align 1 + store i64 %v, i64 addrspace(1)* %r, align 1 + ret void +} + +; FUNC-LABEL: {{^}}local_unaligned_load_store_v4i32: +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 + +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 + +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 + +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 + +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: ds_write_b8 +; GCN: s_endpgm +define void @local_unaligned_load_store_v4i32(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) #0 { %v = load <4 x i32>, <4 x i32> addrspace(3)* %p, align 1 store <4 x i32> %v, <4 x i32> addrspace(3)* %r, align 1 ret void } -; FIXME: We mark v4i32 as custom, so misaligned loads are never expanded. -; FIXME-SI-LABEL: {{^}}unaligned_load_store_v4i32_global -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -; FIXME-SI: buffer_load_ubyte -define void @unaligned_load_store_v4i32_global(<4 x i32> addrspace(1)* %p, <4 x i32> addrspace(1)* %r) nounwind { +; SI-LABEL: {{^}}global_unaligned_load_store_v4i32 +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte +; ALIGNED: buffer_store_byte + +; UNALIGNED: buffer_load_dwordx4 +; UNALIGNED: buffer_store_dwordx4 +define void @global_unaligned_load_store_v4i32(<4 x i32> addrspace(1)* %p, <4 x i32> addrspace(1)* %r) #0 { %v = load <4 x i32>, <4 x i32> addrspace(1)* %p, align 1 store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 1 ret void } -; SI-LABEL: {{^}}load_lds_i64_align_4: -; SI: ds_read2_b32 -; SI: s_endpgm -define void @load_lds_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { +; FUNC-LABEL: {{^}}local_load_i64_align_4: +; GCN: ds_read2_b32 +define void @local_load_i64_align_4(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %val = load i64, i64 addrspace(3)* %in, align 4 store i64 %val, i64 addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}load_lds_i64_align_4_with_offset -; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9 -; SI: s_endpgm -define void @load_lds_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { +; FUNC-LABEL: {{^}}local_load_i64_align_4_with_offset +; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset0:8 offset1:9 +define void @local_load_i64_align_4_with_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %ptr = getelementptr i64, i64 addrspace(3)* %in, i32 4 %val = load i64, i64 addrspace(3)* %ptr, align 4 store i64 %val, i64 addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}load_lds_i64_align_4_with_split_offset: +; FUNC-LABEL: {{^}}local_load_i64_align_4_with_split_offset: ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits -; SI: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1 -; SI: s_endpgm -define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { +; GCN: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]}} offset1:1 +; GCN: s_endpgm +define void @local_load_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %ptr = bitcast i64 addrspace(3)* %in to i32 addrspace(3)* %ptr255 = getelementptr i32, i32 addrspace(3)* %ptr, i32 255 %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)* @@ -206,49 +365,191 @@ define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture ret void } -; SI-LABEL: {{^}}load_lds_i64_align_1: -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: ds_read_u8 -; SI: buffer_store_dwordx2 -; SI: s_endpgm - -define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { +; FUNC-LABEL: {{^}}local_load_i64_align_1: +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: ds_read_u8 +; GCN: store_dwordx2 +define void @local_load_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 { %val = load i64, i64 addrspace(3)* %in, align 1 store i64 %val, i64 addrspace(1)* %out, align 8 ret void } -; SI-LABEL: {{^}}store_lds_i64_align_4: -; SI: ds_write2_b32 -; SI: s_endpgm -define void @store_lds_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 { +; FUNC-LABEL: {{^}}local_store_i64_align_4: +; GCN: ds_write2_b32 +define void @local_store_i64_align_4(i64 addrspace(3)* %out, i64 %val) #0 { store i64 %val, i64 addrspace(3)* %out, align 4 ret void } -; SI-LABEL: {{^}}store_lds_i64_align_4_with_offset -; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9 -; SI: s_endpgm -define void @store_lds_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { +; FUNC-LABEL: {{^}}local_store_i64_align_4_with_offset +; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:8 offset1:9 +; GCN: s_endpgm +define void @local_store_i64_align_4_with_offset(i64 addrspace(3)* %out) #0 { %ptr = getelementptr i64, i64 addrspace(3)* %out, i32 4 store i64 0, i64 addrspace(3)* %ptr, align 4 ret void } -; SI-LABEL: {{^}}store_lds_i64_align_4_with_split_offset: +; FUNC-LABEL: {{^}}local_store_i64_align_4_with_split_offset: ; The tests for the case where the lo offset is 8-bits, but the hi offset is 9-bits -; SI: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1 -; SI: s_endpgm -define void @store_lds_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 { +; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1 +; GCN: s_endpgm +define void @local_store_i64_align_4_with_split_offset(i64 addrspace(3)* %out) #0 { %ptr = bitcast i64 addrspace(3)* %out to i32 addrspace(3)* %ptr255 = getelementptr i32, i32 addrspace(3)* %ptr, i32 255 %ptri64 = bitcast i32 addrspace(3)* %ptr255 to i64 addrspace(3)* store i64 0, i64 addrspace(3)* %out, align 4 ret void } + +; SI-LABEL: {{^}}constant_unaligned_load_i32: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; UNALIGNED: s_load_dword + +; SI: buffer_store_dword +define void @constant_unaligned_load_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { + %v = load i32, i32 addrspace(2)* %p, align 1 + store i32 %v, i32 addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align2_load_i32: +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort + +; UNALIGNED: s_load_dword +; UNALIGNED: buffer_store_dword +define void @constant_align2_load_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { + %v = load i32, i32 addrspace(2)* %p, align 2 + store i32 %v, i32 addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align2_load_i64: +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort +; ALIGNED: buffer_load_ushort + +; UNALIGNED: s_load_dwordx2 +; UNALIGNED: buffer_store_dwordx2 +define void @constant_align2_load_i64(i64 addrspace(2)* %p, i64 addrspace(1)* %r) #0 { + %v = load i64, i64 addrspace(2)* %p, align 2 + store i64 %v, i64 addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align4_load_i64: +; SI: s_load_dwordx2 +; SI: buffer_store_dwordx2 +define void @constant_align4_load_i64(i64 addrspace(2)* %p, i64 addrspace(1)* %r) #0 { + %v = load i64, i64 addrspace(2)* %p, align 4 + store i64 %v, i64 addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align4_load_v4i32: +; SI: s_load_dwordx4 +; SI: buffer_store_dwordx4 +define void @constant_align4_load_v4i32(<4 x i32> addrspace(2)* %p, <4 x i32> addrspace(1)* %r) #0 { + %v = load <4 x i32>, <4 x i32> addrspace(2)* %p, align 4 + store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_unaligned_load_v2i32: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; UNALIGNED: buffer_load_dwordx2 + +; SI: buffer_store_dwordx2 +define void @constant_unaligned_load_v2i32(<2 x i32> addrspace(2)* %p, <2 x i32> addrspace(1)* %r) #0 { + %v = load <2 x i32>, <2 x i32> addrspace(2)* %p, align 1 + store <2 x i32> %v, <2 x i32> addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_unaligned_load_v4i32: +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte +; ALIGNED: buffer_load_ubyte + +; UNALIGNED: buffer_load_dwordx4 + +; SI: buffer_store_dwordx4 +define void @constant_unaligned_load_v4i32(<4 x i32> addrspace(2)* %p, <4 x i32> addrspace(1)* %r) #0 { + %v = load <4 x i32>, <4 x i32> addrspace(2)* %p, align 1 + store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align4_load_i8: +; SI: buffer_load_ubyte +; SI: buffer_store_byte +define void @constant_align4_load_i8(i8 addrspace(2)* %p, i8 addrspace(1)* %r) #0 { + %v = load i8, i8 addrspace(2)* %p, align 4 + store i8 %v, i8 addrspace(1)* %r, align 4 + ret void +} + +; SI-LABEL: {{^}}constant_align2_load_i8: +; SI: buffer_load_ubyte +; SI: buffer_store_byte +define void @constant_align2_load_i8(i8 addrspace(2)* %p, i8 addrspace(1)* %r) #0 { + %v = load i8, i8 addrspace(2)* %p, align 2 + store i8 %v, i8 addrspace(1)* %r, align 2 + ret void +} + +; SI-LABEL: {{^}}constant_align4_merge_load_2_i32: +; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} +; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]] +; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]] +; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} +define void @constant_align4_merge_load_2_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { + %gep0 = getelementptr i32, i32 addrspace(2)* %p, i64 1 + %v0 = load i32, i32 addrspace(2)* %p, align 4 + %v1 = load i32, i32 addrspace(2)* %gep0, align 4 + + %gep1 = getelementptr i32, i32 addrspace(1)* %r, i64 1 + store i32 %v0, i32 addrspace(1)* %r, align 4 + store i32 %v1, i32 addrspace(1)* %gep1, align 4 + ret void +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll b/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll new file mode 100644 index 000000000000..4902e9a3cafb --- /dev/null +++ b/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll @@ -0,0 +1,90 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s +; We may have subregister live ranges that are undefined on some paths. The +; verifier should not complain about this. + + +; CHECK-LABEL: {{^}}func: +define void @func() #0 { +B0: + br i1 undef, label %B1, label %B2 + +B1: + br label %B2 + +B2: + %v0 = phi <4 x float> [ zeroinitializer, %B1 ], [ , %B0 ] + br i1 undef, label %B30.1, label %B30.2 + +B30.1: + %sub = fsub <4 x float> %v0, undef + br label %B30.2 + +B30.2: + %v3 = phi <4 x float> [ %sub, %B30.1 ], [ %v0, %B2 ] + %ve0 = extractelement <4 x float> %v3, i32 0 + store float %ve0, float addrspace(3)* undef, align 4 + ret void +} + +; FIXME: Extra undef subregister copy should be removed before +; overwritten with defined copy +; CHECK-LABEL: {{^}}valley_partially_undef_copy: +define amdgpu_ps float @valley_partially_undef_copy() #0 { +bb: + %tmp = load volatile i32, i32 addrspace(1)* undef, align 4 + %tmp1 = load volatile i32, i32 addrspace(1)* undef, align 4 + %tmp2 = insertelement <4 x i32> undef, i32 %tmp1, i32 0 + %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 + %tmp4 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %tmp3, <8 x i32> undef, <4 x i32> undef, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tmp5 = extractelement <4 x float> %tmp4, i32 0 + %tmp6 = fmul float %tmp5, undef + %tmp7 = fadd float %tmp6, %tmp6 + %tmp8 = insertelement <4 x i32> %tmp2, i32 %tmp, i32 1 + store <4 x i32> %tmp8, <4 x i32> addrspace(1)* undef, align 16 + store float %tmp7, float addrspace(1)* undef, align 4 + br label %bb9 + +bb9: ; preds = %bb9, %bb + %tmp10 = icmp eq i32 %tmp, 0 + br i1 %tmp10, label %bb9, label %bb11 + +bb11: ; preds = %bb9 + store <4 x i32> %tmp2, <4 x i32> addrspace(1)* undef, align 16 + ret float undef +} + +; FIXME: Should be able to remove the undef copies + +; CHECK-LABEL: {{^}}partially_undef_copy: +; CHECK: v_mov_b32_e32 v5, 5 +; CHECK: v_mov_b32_e32 v6, 6 + +; CHECK: v_mov_b32_e32 v[[OUTPUT_LO:[0-9]+]], v5 + +; Undef copy +; CHECK: v_mov_b32_e32 v1, v6 + +; undef copy +; CHECK: v_mov_b32_e32 v2, v7 + +; CHECK: v_mov_b32_e32 v[[OUTPUT_HI:[0-9]+]], v8 +; CHECK: v_mov_b32_e32 v[[OUTPUT_LO]], v6 + +; CHECK: buffer_store_dwordx4 v{{\[}}[[OUTPUT_LO]]:[[OUTPUT_HI]]{{\]}} +define void @partially_undef_copy() #0 { + %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={VGPR5}"() + %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={VGPR6}"() + + %partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0 + %partially.undef.1 = insertelement <4 x i32> %partially.undef.0, i32 %tmp1, i32 0 + + store volatile <4 x i32> %partially.undef.1, <4 x i32> addrspace(1)* undef, align 16 + tail call void asm sideeffect "v_nop", "v={VGPR5_VGPR6_VGPR7_VGPR8}"(<4 x i32> %partially.undef.0) + ret void +} + +declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 +declare float @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll b/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll index 036a7e91b47f..f09f73c38b4c 100644 --- a/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll +++ b/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll @@ -1,8 +1,6 @@ -; REQUIRES: asserts -; XFAIL: * -; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=SI < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s +; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s ; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=SI -check-prefix=COMMON %s -; RUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s +; XUN: llc -O0 -verify-machineinstrs -asm-verbose=0 -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=COMMON %s ; SI hits an assertion at -O0, evergreen hits a not implemented unreachable. @@ -41,8 +39,9 @@ for.end: ; preds = %for.body, %entry } ; COMMON-LABEL: {{^}}branch_false: -; SI: .text -; SI-NEXT: s_endpgm +; SI: s_cbranch_vccnz +; SI: s_cbranch_vccnz +; SI: s_endpgm define void @branch_false(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 { entry: br i1 false, label %for.end, label %for.body.lr.ph @@ -77,8 +76,9 @@ for.end: ; preds = %for.body, %entry } ; COMMON-LABEL: {{^}}branch_undef: -; SI: .text -; SI-NEXT: s_endpgm +; SI: s_cbranch_vccnz +; SI: s_cbranch_vccnz +; SI: s_endpgm define void @branch_undef(i8 addrspace(1)* nocapture %main, i32 %main_stride) #0 { entry: br i1 undef, label %for.end, label %for.body.lr.ph diff --git a/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll b/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll new file mode 100644 index 000000000000..93a2c6998be4 --- /dev/null +++ b/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck %s + +; This used to raise an assertion due to how the choice between uniform and +; non-uniform branches was determined. +; +; CHECK-LABEL: {{^}}main: +; CHECK: s_cbranch_vccnz +define amdgpu_ps float @main(<4 x i32> inreg %rsrc) { +main_body: + %v = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 0, i32 0, i1 true, i1 false) + %cc = fcmp une float %v, 1.000000e+00 + br i1 %cc, label %if, label %else + +if: + %u = fadd float %v, %v + br label %else + +else: + %r = phi float [ %v, %main_body ], [ %u, %if ] + ret float %r +} + +; Function Attrs: nounwind readonly +declare float @llvm.amdgcn.buffer.load.f32(<4 x i32>, i32, i32, i1, i1) #0 + +attributes #0 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/uniform-cfg.ll b/test/CodeGen/AMDGPU/uniform-cfg.ll new file mode 100644 index 000000000000..ac9e2b5f8432 --- /dev/null +++ b/test/CodeGen/AMDGPU/uniform-cfg.ll @@ -0,0 +1,439 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI %s + +; SI-LABEL: {{^}}uniform_if_scc: +; SI-DAG: s_cmp_eq_i32 s{{[0-9]+}}, 0 +; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] + +; Fall-through to the else +; SI: v_mov_b32_e32 [[STORE_VAL]], 1 + +; SI: [[IF_LABEL]]: +; SI: buffer_store_dword [[STORE_VAL]] +define void @uniform_if_scc(i32 %cond, i32 addrspace(1)* %out) { +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %if, label %else + +if: + br label %done + +else: + br label %done + +done: + %value = phi i32 [0, %if], [1, %else] + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}uniform_if_vcc: +; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and +; also scheduled the write first. +; SI-DAG: v_cmp_eq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} +; SI-DAG: s_and_b64 vcc, exec, [[COND]] +; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] + +; Fall-through to the else +; SI: v_mov_b32_e32 [[STORE_VAL]], 1 + +; SI: [[IF_LABEL]]: +; SI: buffer_store_dword [[STORE_VAL]] +define void @uniform_if_vcc(float %cond, i32 addrspace(1)* %out) { +entry: + %cmp0 = fcmp oeq float %cond, 0.0 + br i1 %cmp0, label %if, label %else + +if: + br label %done + +else: + br label %done + +done: + %value = phi i32 [0, %if], [1, %else] + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}uniform_if_swap_br_targets_scc: +; SI-DAG: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; SI: s_cbranch_scc1 [[IF_LABEL:[0-9_A-Za-z]+]] + +; Fall-through to the else +; SI: v_mov_b32_e32 [[STORE_VAL]], 1 + +; SI: [[IF_LABEL]]: +; SI: buffer_store_dword [[STORE_VAL]] +define void @uniform_if_swap_br_targets_scc(i32 %cond, i32 addrspace(1)* %out) { +entry: + %cmp0 = icmp eq i32 %cond, 0 + br i1 %cmp0, label %else, label %if + +if: + br label %done + +else: + br label %done + +done: + %value = phi i32 [0, %if], [1, %else] + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}uniform_if_swap_br_targets_vcc: +; FIXME: We could use _e32 here if we re-used the 0 from [[STORE_VAL]], and +; also scheduled the write first. +; SI-DAG: v_cmp_neq_f32_e64 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}} +; SI-DAG: s_and_b64 vcc, exec, [[COND]] +; SI-DAG: v_mov_b32_e32 [[STORE_VAL:v[0-9]+]], 0 +; SI: s_cbranch_vccnz [[IF_LABEL:[0-9_A-Za-z]+]] + +; Fall-through to the else +; SI: v_mov_b32_e32 [[STORE_VAL]], 1 + +; SI: [[IF_LABEL]]: +; SI: buffer_store_dword [[STORE_VAL]] +define void @uniform_if_swap_br_targets_vcc(float %cond, i32 addrspace(1)* %out) { +entry: + %cmp0 = fcmp oeq float %cond, 0.0 + br i1 %cmp0, label %else, label %if + +if: + br label %done + +else: + br label %done + +done: + %value = phi i32 [0, %if], [1, %else] + store i32 %value, i32 addrspace(1)* %out + ret void +} + +; SI-LABEL: {{^}}uniform_if_move_valu: +; SI: v_add_f32_e32 [[CMP:v[0-9]+]] +; Using a floating-point value in an integer compare will cause the compare to +; be selected for the SALU and then later moved to the VALU. +; SI: v_cmp_ne_i32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 5, [[CMP]] +; SI: s_and_b64 vcc, exec, [[COND]] +; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] +; SI: buffer_store_dword +; SI: [[ENDIF_LABEL]]: +; SI: s_endpgm +define void @uniform_if_move_valu(i32 addrspace(1)* %out, float %a) { +entry: + %a.0 = fadd float %a, 10.0 + %cond = bitcast float %a.0 to i32 + %cmp = icmp eq i32 %cond, 5 + br i1 %cmp, label %if, label %endif + +if: + store i32 0, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + +; SI-LABEL: {{^}}uniform_if_move_valu_commute: +; SI: v_add_f32_e32 [[CMP:v[0-9]+]] +; Using a floating-point value in an integer compare will cause the compare to +; be selected for the SALU and then later moved to the VALU. +; SI: v_cmp_gt_u32_e32 [[COND:vcc|s\[[0-9]+:[0-9]+\]]], 6, [[CMP]] +; SI: s_and_b64 vcc, exec, [[COND]] +; SI: s_cbranch_vccnz [[ENDIF_LABEL:[0-9_A-Za-z]+]] +; SI: buffer_store_dword +; SI: [[ENDIF_LABEL]]: +; SI: s_endpgm +define void @uniform_if_move_valu_commute(i32 addrspace(1)* %out, float %a) { +entry: + %a.0 = fadd float %a, 10.0 + %cond = bitcast float %a.0 to i32 + %cmp = icmp ugt i32 %cond, 5 + br i1 %cmp, label %if, label %endif + +if: + store i32 0, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + + +; SI-LABEL: {{^}}uniform_if_else_ret: +; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] + +; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 +; SI: buffer_store_dword [[TWO]] +; SI: s_endpgm + +; SI: {{^}}[[IF_LABEL]]: +; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; SI: buffer_store_dword [[ONE]] +; SI: s_endpgm +define void @uniform_if_else_ret(i32 addrspace(1)* nocapture %out, i32 %a) { +entry: + %cmp = icmp eq i32 %a, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + store i32 1, i32 addrspace(1)* %out + br label %if.end + +if.else: ; preds = %entry + store i32 2, i32 addrspace(1)* %out + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +; SI-LABEL: {{^}}uniform_if_else: +; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; SI-NEXT: s_cbranch_scc0 [[IF_LABEL:[0-9_A-Za-z]+]] + +; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 +; SI: buffer_store_dword [[TWO]] +; SI: s_branch [[ENDIF_LABEL:[0-9_A-Za-z]+]] + +; SI: [[IF_LABEL]]: +; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; SI: buffer_store_dword [[ONE]] + +; SI: [[ENDIF_LABEL]]: +; SI: v_mov_b32_e32 [[THREE:v[0-9]+]], 3 +; SI: buffer_store_dword [[THREE]] +; SI: s_endpgm +define void @uniform_if_else(i32 addrspace(1)* nocapture %out0, i32 addrspace(1)* nocapture %out1, i32 %a) { +entry: + %cmp = icmp eq i32 %a, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + store i32 1, i32 addrspace(1)* %out0 + br label %if.end + +if.else: ; preds = %entry + store i32 2, i32 addrspace(1)* %out0 + br label %if.end + +if.end: ; preds = %if.else, %if.then + store i32 3, i32 addrspace(1)* %out1 + ret void +} + +; SI-LABEL: {{^}}icmp_2_users: +; SI: s_cmp_lt_i32 s{{[0-9]+}}, 1 +; SI: s_cbranch_scc1 [[LABEL:[a-zA-Z0-9_]+]] +; SI: buffer_store_dword +; SI: [[LABEL]]: +; SI: s_endpgm +define void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { +main_body: + %0 = icmp sgt i32 %cond, 0 + %1 = sext i1 %0 to i32 + br i1 %0, label %IF, label %ENDIF + +IF: + store i32 %1, i32 addrspace(1)* %out + br label %ENDIF + +ENDIF: ; preds = %IF, %main_body + ret void +} + +; SI-LABEL: {{^}}icmp_users_different_blocks: +; SI: s_load_dword [[COND:s[0-9]+]] +; SI: s_cmp_lt_i32 [[COND]], 1 +; SI: s_cbranch_scc1 [[EXIT:[A-Za-z0-9_]+]] +; SI: v_cmp_lt_i32_e64 [[MASK:s\[[0-9]+:[0-9]+\]]], 0, [[COND]] +; SI: s_and_b64 vcc, exec, [[MASK]] +; SI: s_cbranch_vccnz [[EXIT]] +; SI: buffer_store +; SI: {{^}}[[EXIT]]: +; SI: s_endpgm +define void @icmp_users_different_blocks(i32 %cond0, i32 %cond1, i32 addrspace(1)* %out) { +bb: + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 + %cmp0 = icmp sgt i32 %cond0, 0 + %cmp1 = icmp sgt i32 %cond1, 0 + br i1 %cmp0, label %bb2, label %bb9 + +bb2: ; preds = %bb + %tmp2 = sext i1 %cmp1 to i32 + %tmp3 = add i32 %tmp2, %tmp + br i1 %cmp1, label %bb9, label %bb7 + +bb7: ; preds = %bb5 + store i32 %tmp3, i32 addrspace(1)* %out + br label %bb9 + +bb9: ; preds = %bb8, %bb4 + ret void +} + +; SI-LABEL: {{^}}uniform_loop: +; SI: {{^}}[[LOOP_LABEL:[A-Z0-9_a-z]+]]: +; FIXME: We need to teach SIFixSGPRCopies about uniform branches so we +; get s_add_i32 here. +; SI: v_add_i32_e32 [[I:v[0-9]+]], vcc, -1, v{{[0-9]+}} +; SI: v_cmp_ne_i32_e32 vcc, 0, [[I]] +; SI: s_and_b64 vcc, exec, vcc +; SI: s_cbranch_vccnz [[LOOP_LABEL]] +; SI: s_endpgm +define void @uniform_loop(i32 addrspace(1)* %out, i32 %a) { +entry: + br label %loop + +loop: + %i = phi i32 [0, %entry], [%i.i, %loop] + %i.i = add i32 %i, 1 + %cmp = icmp eq i32 %a, %i.i + br i1 %cmp, label %done, label %loop + +done: + ret void +} + +; Test uniform and divergent. + +; SI-LABEL: {{^}}uniform_inside_divergent: +; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} +; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc +; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]] +; SI: s_cbranch_execz [[ENDIF_LABEL:[0-9_A-Za-z]+]] +; SI: s_cmp_lg_i32 {{s[0-9]+}}, 0 +; SI: s_cbranch_scc1 [[ENDIF_LABEL]] +; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; SI: buffer_store_dword [[ONE]] +define void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 + %d_cmp = icmp ult i32 %tid, 16 + br i1 %d_cmp, label %if, label %endif + +if: + store i32 0, i32 addrspace(1)* %out + %u_cmp = icmp eq i32 %cond, 0 + br i1 %u_cmp, label %if_uniform, label %endif + +if_uniform: + store i32 1, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + +; SI-LABEL: {{^}}divergent_inside_uniform: +; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; SI: s_cbranch_scc1 [[ENDIF_LABEL:[0-9_A-Za-z]+]] +; SI: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}} +; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc +; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]] +; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; SI: buffer_store_dword [[ONE]] +; SI: [[ENDIF_LABEL]]: +; SI: s_endpgm +define void @divergent_inside_uniform(i32 addrspace(1)* %out, i32 %cond) { +entry: + %u_cmp = icmp eq i32 %cond, 0 + br i1 %u_cmp, label %if, label %endif + +if: + store i32 0, i32 addrspace(1)* %out + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 + %d_cmp = icmp ult i32 %tid, 16 + br i1 %d_cmp, label %if_uniform, label %endif + +if_uniform: + store i32 1, i32 addrspace(1)* %out + br label %endif + +endif: + ret void +} + +; SI-LABEL: {{^}}divergent_if_uniform_if: +; SI: v_cmp_eq_i32_e32 vcc, 0, v0 +; SI: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc +; SI: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]] +; SI: v_mov_b32_e32 [[ONE:v[0-9]+]], 1 +; SI: buffer_store_dword [[ONE]] +; SI: s_or_b64 exec, exec, [[MASK]] +; SI: s_cmp_lg_i32 s{{[0-9]+}}, 0 +; SI: s_cbranch_scc1 [[EXIT:[A-Z0-9_]+]] +; SI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2 +; SI: buffer_store_dword [[TWO]] +; SI: [[EXIT]]: +; SI: s_endpgm +define void @divergent_if_uniform_if(i32 addrspace(1)* %out, i32 %cond) { +entry: + %tid = call i32 @llvm.amdgcn.workitem.id.x() #0 + %d_cmp = icmp eq i32 %tid, 0 + br i1 %d_cmp, label %if, label %endif + +if: + store i32 1, i32 addrspace(1)* %out + br label %endif + +endif: + %u_cmp = icmp eq i32 %cond, 0 + br i1 %u_cmp, label %if_uniform, label %exit + +if_uniform: + store i32 2, i32 addrspace(1)* %out + br label %exit + +exit: + ret void +} + +; The condition of the branches in the two blocks are +; uniform. MachineCSE replaces the 2nd condition with the inverse of +; the first, leaving an scc use in a different block than it was +; defed. + +; SI-LABEL: {{^}}cse_uniform_condition_different_blocks: +; SI: s_load_dword [[COND:s[0-9]+]] +; SI: s_cmp_lt_i32 [[COND]], 1 +; SI: s_cbranch_scc1 BB[[FNNUM:[0-9]+]]_3 + +; SI: BB#1: +; SI-NOT: cmp +; SI: buffer_load_dword +; SI: buffer_store_dword +; SI: s_cbranch_scc1 BB[[FNNUM]]_3 + +; SI: BB[[FNNUM]]_3: +; SI: s_endpgm +define void @cse_uniform_condition_different_blocks(i32 %cond, i32 addrspace(1)* %out) { +bb: + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 + %tmp1 = icmp sgt i32 %cond, 0 + br i1 %tmp1, label %bb2, label %bb9 + +bb2: ; preds = %bb + %tmp3 = load volatile i32, i32 addrspace(1)* undef + store volatile i32 0, i32 addrspace(1)* undef + %tmp9 = icmp sle i32 %cond, 0 + br i1 %tmp9, label %bb9, label %bb7 + +bb7: ; preds = %bb5 + store i32 %tmp3, i32 addrspace(1)* %out + br label %bb9 + +bb9: ; preds = %bb8, %bb4 + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/uniform-crash.ll b/test/CodeGen/AMDGPU/uniform-crash.ll new file mode 100644 index 000000000000..cfbb2af58677 --- /dev/null +++ b/test/CodeGen/AMDGPU/uniform-crash.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s + +; GCN-LABEL: {{^}}icmp_2_users: +; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 1 +; GCN: s_cbranch_scc1 [[LABEL:BB[0-9_A-Z]+]] +; GCN: [[LABEL]]: +; GCN-NEXT: s_endpgm +define void @icmp_2_users(i32 addrspace(1)* %out, i32 %cond) { +main_body: + %0 = icmp sgt i32 %cond, 0 + %1 = sext i1 %0 to i32 + br i1 %0, label %IF, label %ENDIF + +IF: + store i32 %1, i32 addrspace(1)* %out + br label %ENDIF + +ENDIF: ; preds = %IF, %main_body + ret void +} + +; GCN-LABEL: {{^}}fix_sgpr_live_ranges_crash: +; GCN: s_cbranch_scc1 [[BB0:[A-Z0-9_]+]] +; GCN: {{^}}[[LOOP:[A-Z0-9_]+]]: +; GCN: s_cbranch_scc1 [[LOOP]] +; GCN: {{^}}[[BB0]]: +define void @fix_sgpr_live_ranges_crash(i32 %arg, i32 %arg1) { +bb: + %cnd = trunc i32 %arg to i1 + br i1 %cnd, label %bb2, label %bb5 + +bb2: ; preds = %bb + %tmp = mul i32 10, %arg1 + br label %bb3 + +bb3: ; preds = %bb3, %bb2 + %val = load volatile i32, i32 addrspace(2)* undef + %tmp4 = icmp eq i32 %val, %arg1 + br i1 %tmp4, label %bb5, label %bb3 + +bb5: ; preds = %bb3, %bb + %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #1 + %tmp10 = icmp ult i32 %tmp6, %arg + br i1 %tmp10, label %bb11, label %bb12 + +bb11: ; preds = %bb11, %bb5 + br i1 undef, label %bb11, label %bb12 + +bb12: ; preds = %bb11, %bb5 + ret void +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.y() #1 + +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll b/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll new file mode 100644 index 000000000000..9f2f0d67d245 --- /dev/null +++ b/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll @@ -0,0 +1,67 @@ +; RUN: llc -march=amdgcn -mcpu=verde < %s | FileCheck %s + +; Test a simple uniform loop that lives inside non-uniform control flow. + +; CHECK-LABEL: {{^}}test1: +; CHECK: v_cmp_ne_i32_e32 vcc, 0 +; CHECK: s_and_saveexec_b64 + +; CHECK: [[LOOP_BODY_LABEL:BB[0-9]+_[0-9]+]]: +; CHECK: s_and_b64 vcc, exec, vcc +; CHECK: s_cbranch_vccz [[LOOP_BODY_LABEL]] + +; CHECK: s_endpgm +define amdgpu_ps void @test1(<8 x i32> inreg %rsrc, <2 x i32> %addr.base, i32 %y, i32 %p) { +main_body: + %cc = icmp eq i32 %p, 0 + br i1 %cc, label %out, label %loop_body + +loop_body: + %counter = phi i32 [ 0, %main_body ], [ %incr, %loop_body ] + + ; Prevent the loop from being optimized out + call void asm sideeffect "", "" () + + %incr = add i32 %counter, 1 + %lc = icmp sge i32 %incr, 1000 + br i1 %lc, label %out, label %loop_body + +out: + ret void +} + +;CHECK-LABEL: {{^}}test2: +;CHECK: s_and_saveexec_b64 +;CHECK: s_xor_b64 +;CHECK-NEXT: s_cbranch_execz +define void @test2(i32 addrspace(1)* %out, i32 %a, i32 %b) { +main_body: + %tid = call i32 @llvm.amdgcn.workitem.id.x() #1 + %cc = icmp eq i32 %tid, 0 + br i1 %cc, label %done1, label %if + +if: + %cmp = icmp eq i32 %a, 0 + br i1 %cmp, label %done0, label %loop_body + +loop_body: + %counter = phi i32 [ 0, %if ], [0, %done0], [ %incr, %loop_body ] + + ; Prevent the loop from being optimized out + call void asm sideeffect "", "" () + + %incr = add i32 %counter, 1 + %lc = icmp sge i32 %incr, 1000 + br i1 %lc, label %done1, label %loop_body + +done0: + %cmp0 = icmp eq i32 %b, 0 + br i1 %cmp0, label %done1, label %loop_body + +done1: + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #1 = { nounwind readonly } diff --git a/test/CodeGen/AMDGPU/unknown-processor.ll b/test/CodeGen/AMDGPU/unknown-processor.ll new file mode 100644 index 000000000000..941f4c601e34 --- /dev/null +++ b/test/CodeGen/AMDGPU/unknown-processor.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=amdgcn -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=GCN %s +; RUN: llc -march=r600 -mcpu=unknown < %s 2>&1 | FileCheck -check-prefix=ERROR -check-prefix=R600 %s + +; Should not crash when the processor is not recognized and the +; wavefront size feature not set. + +; Should also not have fragments of r600 and gcn isa mixed. + +; ERROR: 'unknown' is not a recognized processor for this target (ignoring processor) + +; GCN-NOT: MOV +; GCN: buffer_store_dword +; GCN: ScratchSize: 8{{$}} + +; R600: MOV +define void @foo() { + %alloca = alloca i32, align 4 + store volatile i32 0, i32* %alloca + ret void +} diff --git a/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll b/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll index 87b925a24a04..0435ed4d5525 100644 --- a/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll +++ b/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s declare float @llvm.fma.f32(float, float, float) #1 declare double @llvm.fma.f64(double, double, double) #1 declare float @llvm.fmuladd.f32(float, float, float) #1 -declare i32 @llvm.AMDGPU.imad24(i32, i32, i32) #1 +declare float @llvm.amdgcn.div.fixup.f32(float, float, float) #1 ; GCN-LABEL: {{^}}test_sgpr_use_twice_binop: @@ -28,10 +28,10 @@ define void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) } ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b: -; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[SGPR0]], [[VGPR1]] ; GCN: buffer_store_dword [[RESULT]] @@ -68,10 +68,10 @@ define void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float } ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a: -; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], [[SGPR0]], [[SGPR0]] ; GCN: buffer_store_dword [[RESULT]] @@ -82,10 +82,10 @@ define void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, floa } ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a: -; SI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; VI: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c -; VI: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 +; SI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; VI-DAG: s_load_dword [[SGPR0:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c +; VI-DAG: s_load_dword [[SGPR1:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30 ; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], [[SGPR1]] ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR0]], [[VGPR1]], [[SGPR0]] ; GCN: buffer_store_dword [[RESULT]] @@ -107,7 +107,7 @@ define void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, fl ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a: ; GCN: s_load_dword [[SGPR:s[0-9]+]] -; GCN: v_fma_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]] +; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]] ; GCN: buffer_store_dword [[RESULT]] define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 { %fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1 @@ -118,11 +118,11 @@ define void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, fl ; Don't use fma since fma c, x, y is canonicalized to fma x, c, y ; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a: ; GCN: s_load_dword [[SGPR:s[0-9]+]] -; GCN: v_mad_i32_i24 [[RESULT:v[0-9]+]], 2, [[SGPR]], [[SGPR]] +; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]] ; GCN: buffer_store_dword [[RESULT]] -define void @test_sgpr_use_twice_ternary_op_imm_a_a(i32 addrspace(1)* %out, i32 %a) #0 { - %fma = call i32 @llvm.AMDGPU.imad24(i32 2, i32 %a, i32 %a) #1 - store i32 %fma, i32 addrspace(1)* %out, align 4 +define void @test_sgpr_use_twice_ternary_op_imm_a_a(float addrspace(1)* %out, float %a) #0 { + %val = call float @llvm.amdgcn.div.fixup.f32(float 2.0, float %a, float %a) #1 + store float %val, float addrspace(1)* %out, align 4 ret void } @@ -227,7 +227,7 @@ define void @test_literal_use_twice_ternary_op_s_k_k_x2(float addrspace(1)* %out ; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000 ; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], [[SGPR1]] -; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK0]] +; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VS1]], [[SGPR0]], [[VK0]] ; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SGPR0]], [[VS1]], [[VK1]] @@ -254,7 +254,7 @@ define void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, float %b) #0 { ; Same zero component is re-used for half of each immediate. ; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000 -; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, [[SGPR0]], v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]}} +; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]}} ; GCN: buffer_store_dwordx2 [[RESULT0]] ; GCN: buffer_store_dwordx2 [[RESULT1]] diff --git a/test/CodeGen/AMDGPU/v_cndmask.ll b/test/CodeGen/AMDGPU/v_cndmask.ll index c368c5aaf7dc..ca6bff4f6fc8 100644 --- a/test/CodeGen/AMDGPU/v_cndmask.ll +++ b/test/CodeGen/AMDGPU/v_cndmask.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() #1 +declare i32 @llvm.amdgcn.workitem.id.x() #1 ; SI-LABEL: {{^}}v_cnd_nan_nosgpr: ; SI: v_cndmask_b32_e64 v{{[0-9]}}, v{{[0-9]}}, -1, s{{\[[0-9]+:[0-9]+\]}} @@ -9,7 +9,7 @@ declare i32 @llvm.r600.read.tidig.x() #1 ; All nan values are converted to 0xffffffff ; SI: s_endpgm define void @v_cnd_nan_nosgpr(float addrspace(1)* %out, i32 %c, float addrspace(1)* %fptr) #0 { - %idx = call i32 @llvm.r600.read.tidig.x() #1 + %idx = call i32 @llvm.amdgcn.workitem.id.x() #1 %f.gep = getelementptr float, float addrspace(1)* %fptr, i32 %idx %f = load float, float addrspace(1)* %fptr %setcc = icmp ne i32 %c, 0 diff --git a/test/CodeGen/AMDGPU/v_mac.ll b/test/CodeGen/AMDGPU/v_mac.ll index a4eaec3403c9..027c63817903 100644 --- a/test/CodeGen/AMDGPU/v_mac.ll +++ b/test/CodeGen/AMDGPU/v_mac.ll @@ -2,19 +2,19 @@ ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s ; GCN-LABEL: {{^}}mac_vvv: -; GCN: buffer_load_dword [[A:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0{{$}} -; GCN: buffer_load_dword [[B:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:4 -; GCN: buffer_load_dword [[C:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0 offset:8 +; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}} +; GCN: buffer_load_dword [[B:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 +; GCN: buffer_load_dword [[C:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8 ; GCN: v_mac_f32_e32 [[C]], [[B]], [[A]] ; GCN: buffer_store_dword [[C]] -define void @mac_vvv(float addrspace(1)* %out, float addrspace(1)* %in) { +define void @mac_vvv(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 - %a = load float, float addrspace(1)* %in - %b = load float, float addrspace(1)* %b_ptr - %c = load float, float addrspace(1)* %c_ptr + %a = load volatile float, float addrspace(1)* %in + %b = load volatile float, float addrspace(1)* %b_ptr + %c = load volatile float, float addrspace(1)* %c_ptr %tmp0 = fmul float %a, %b %tmp1 = fadd float %tmp0, %c @@ -24,8 +24,8 @@ entry: ; GCN-LABEL: {{^}}mad_inline_sgpr_inline: ; GCN-NOT: v_mac_f32 -; GCN: v_mad_f32 v{{[0-9]}}, 0.5, s{{[0-9]+}}, 0.5 -define void @mad_inline_sgpr_inline(float addrspace(1)* %out, float %in) { +; GCN: v_mad_f32 v{{[0-9]}}, s{{[0-9]+}}, 0.5, 0.5 +define void @mad_inline_sgpr_inline(float addrspace(1)* %out, float %in) #0 { entry: %tmp0 = fmul float 0.5, %in %tmp1 = fadd float %tmp0, 0.5 @@ -36,7 +36,7 @@ entry: ; GCN-LABEL: {{^}}mad_vvs: ; GCN-NOT: v_mac_f32 ; GCN: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}} -define void @mad_vvs(float addrspace(1)* %out, float addrspace(1)* %in, float %c) { +define void @mad_vvs(float addrspace(1)* %out, float addrspace(1)* %in, float %c) #0 { entry: %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 @@ -51,7 +51,7 @@ entry: ; GCN-LABEL: {{^}}mac_ssv: ; GCN: v_mac_f32_e64 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} -define void @mac_ssv(float addrspace(1)* %out, float addrspace(1)* %in, float %a) { +define void @mac_ssv(float addrspace(1)* %out, float addrspace(1)* %in, float %a) #0 { entry: %c = load float, float addrspace(1)* %in @@ -64,18 +64,18 @@ entry: ; GCN-LABEL: {{^}}mac_mad_same_add: ; GCN: v_mad_f32 v{{[0-9]}}, v{{[0-9]+}}, v{{[0-9]+}}, [[ADD:v[0-9]+]] ; GCN: v_mac_f32_e32 [[ADD]], v{{[0-9]+}}, v{{[0-9]+}} -define void @mac_mad_same_add(float addrspace(1)* %out, float addrspace(1)* %in) { +define void @mac_mad_same_add(float addrspace(1)* %out, float addrspace(1)* %in) #0 { entry: %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 %d_ptr = getelementptr float, float addrspace(1)* %in, i32 3 %e_ptr = getelementptr float, float addrspace(1)* %in, i32 4 - %a = load float, float addrspace(1)* %in - %b = load float, float addrspace(1)* %b_ptr - %c = load float, float addrspace(1)* %c_ptr - %d = load float, float addrspace(1)* %d_ptr - %e = load float, float addrspace(1)* %e_ptr + %a = load volatile float, float addrspace(1)* %in + %b = load volatile float, float addrspace(1)* %b_ptr + %c = load volatile float, float addrspace(1)* %c_ptr + %d = load volatile float, float addrspace(1)* %d_ptr + %e = load volatile float, float addrspace(1)* %e_ptr %tmp0 = fmul float %a, %b %tmp1 = fadd float %tmp0, %c @@ -104,6 +104,46 @@ entry: %b = load float, float addrspace(1)* %b_ptr %c = load float, float addrspace(1)* %c_ptr + %neg_a = fsub float -0.0, %a + %tmp0 = fmul float %neg_a, %b + %tmp1 = fadd float %tmp0, %c + + store float %tmp1, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}unsafe_mad_sub0_src0: +; GCN-NOT: v_mac_f32 +; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}} +define void @unsafe_mad_sub0_src0(float addrspace(1)* %out, float addrspace(1)* %in) #1 { +entry: + %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 + %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 + + %a = load float, float addrspace(1)* %in + %b = load float, float addrspace(1)* %b_ptr + %c = load float, float addrspace(1)* %c_ptr + + %neg_a = fsub float 0.0, %a + %tmp0 = fmul float %neg_a, %b + %tmp1 = fadd float %tmp0, %c + + store float %tmp1, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}safe_mad_sub0_src0: +; GCN: v_sub_f32_e32 [[SUB0:v[0-9]+]], 0, +; GCN: v_mac_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[SUB0]] +define void @safe_mad_sub0_src0(float addrspace(1)* %out, float addrspace(1)* %in) #0 { +entry: + %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 + %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 + + %a = load float, float addrspace(1)* %in + %b = load float, float addrspace(1)* %b_ptr + %c = load float, float addrspace(1)* %c_ptr + %neg_a = fsub float 0.0, %a %tmp0 = fmul float %neg_a, %b %tmp1 = fadd float %tmp0, %c @@ -124,6 +164,26 @@ entry: %b = load float, float addrspace(1)* %b_ptr %c = load float, float addrspace(1)* %c_ptr + %neg_b = fsub float -0.0, %b + %tmp0 = fmul float %a, %neg_b + %tmp1 = fadd float %tmp0, %c + + store float %tmp1, float addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}unsafe_mad_sub0_src1: +; GCN-NOT: v_mac_f32 +; GCN: v_mad_f32 v{{[0-9]+}}, -v{{[0-9]+}}, v{{[0-9]+}}, v{{[-0-9]}} +define void @unsafe_mad_sub0_src1(float addrspace(1)* %out, float addrspace(1)* %in) #1 { +entry: + %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 + %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 + + %a = load float, float addrspace(1)* %in + %b = load float, float addrspace(1)* %b_ptr + %c = load float, float addrspace(1)* %c_ptr + %neg_b = fsub float 0.0, %b %tmp0 = fmul float %a, %neg_b %tmp1 = fadd float %tmp0, %c @@ -144,7 +204,7 @@ entry: %b = load float, float addrspace(1)* %b_ptr %c = load float, float addrspace(1)* %c_ptr - %neg_c = fsub float 0.0, %c + %neg_c = fsub float -0.0, %c %tmp0 = fmul float %a, %b %tmp1 = fadd float %tmp0, %neg_c @@ -152,4 +212,5 @@ entry: ret void } -attributes #0 = { "true" "unsafe-fp-math"="true" } +attributes #0 = { nounwind "unsafe-fp-math"="false" } +attributes #1 = { nounwind "unsafe-fp-math"="true" } diff --git a/test/CodeGen/AMDGPU/valu-i1.ll b/test/CodeGen/AMDGPU/valu-i1.ll index 1cbefba60c95..02a1278f76cb 100644 --- a/test/CodeGen/AMDGPU/valu-i1.ll +++ b/test/CodeGen/AMDGPU/valu-i1.ll @@ -1,15 +1,16 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s +; RUN: llc -march=amdgcn -verify-machineinstrs -enable-misched -asm-verbose < %s | FileCheck -check-prefix=SI %s -declare i32 @llvm.r600.read.tidig.x() nounwind readnone +declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone ; SI-LABEL: @test_if ; Make sure the i1 values created by the cfg structurizer pass are ; moved using VALU instructions ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1 ; SI: v_mov_b32_e32 v{{[0-9]}}, -1 -define void @test_if(i32 %a, i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 { +define void @test_if(i32 %b, i32 addrspace(1)* %src, i32 addrspace(1)* %dst) #1 { entry: - switch i32 %a, label %default [ + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone + switch i32 %tid, label %default [ i32 0, label %case0 i32 1, label %case1 ] @@ -25,7 +26,7 @@ case1: br label %end default: - %cmp8 = icmp eq i32 %a, 2 + %cmp8 = icmp eq i32 %tid, 2 %arrayidx10 = getelementptr i32, i32 addrspace(1)* %dst, i32 %b br i1 %cmp8, label %if, label %else @@ -54,7 +55,7 @@ end: ; SI: s_or_b64 exec, exec, [[BR_SREG]] ; SI: s_endpgm define void @simple_test_v_if(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %is.0 = icmp ne i32 %tid, 0 br i1 %is.0, label %store, label %exit @@ -71,22 +72,22 @@ exit: ; SI: v_cmp_ne_i32_e32 vcc, 0, v{{[0-9]+}} ; SI: s_and_saveexec_b64 [[BR_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_xor_b64 [[BR_SREG]], exec, [[BR_SREG]] -; SI: s_cbranch_execz BB2_2 +; SI: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] -; SI: ; BB#1: ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} -; SI: BB2_3: +; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: ; SI: buffer_load_dword ; SI-DAG: buffer_store_dword ; SI-DAG: v_cmp_eq_i32_e32 vcc, -; SI: s_or_b64 [[OR_SREG:s\[[0-9]+:[0-9]+\]]] -; SI: s_andn2_b64 exec, exec, [[OR_SREG]] -; SI: s_cbranch_execnz BB2_3 +; SI-DAG: s_and_b64 vcc, exec, vcc +; SI: s_cbranch_vccz [[LABEL_LOOP]] +; SI: [[LABEL_EXIT]]: +; SI: s_endpgm define void @simple_test_v_loop(i32 addrspace(1)* %dst, i32 addrspace(1)* %src) #1 { entry: - %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone + %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %is.0 = icmp ne i32 %tid, 0 %limit = add i32 %tid, 64 br i1 %is.0, label %loop, label %exit @@ -114,7 +115,7 @@ exit: ; SI: v_cmp_lt_i32_e32 vcc ; SI: s_and_saveexec_b64 [[OUTER_CMP_SREG:s\[[0-9]+:[0-9]+\]]], vcc ; SI: s_xor_b64 [[OUTER_CMP_SREG]], exec, [[OUTER_CMP_SREG]] -; SI: s_cbranch_execz BB3_2 +; SI: s_cbranch_execz [[LABEL_EXIT:BB[0-9]+_[0-9]+]] ; Initialize inner condition to false ; SI: ; BB#1: @@ -122,7 +123,7 @@ exit: ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]] ; Clear exec bits for workitems that load -1s -; SI: BB3_3: +; SI: [[LABEL_LOOP:BB[0-9]+_[0-9]+]]: ; SI: buffer_load_dword [[B:v[0-9]+]] ; SI: buffer_load_dword [[A:v[0-9]+]] ; SI-DAG: v_cmp_ne_i32_e64 [[NEG1_CHECK_0:s\[[0-9]+:[0-9]+\]]], -1, [[A]] @@ -130,29 +131,29 @@ exit: ; SI: s_and_b64 [[ORNEG1:s\[[0-9]+:[0-9]+\]]], [[NEG1_CHECK_1]], [[NEG1_CHECK_0]] ; SI: s_and_saveexec_b64 [[ORNEG2:s\[[0-9]+:[0-9]+\]]], [[ORNEG1]] ; SI: s_xor_b64 [[ORNEG2]], exec, [[ORNEG2]] -; SI: s_cbranch_execz BB3_5 +; SI: s_cbranch_execz [[LABEL_FLOW:BB[0-9]+_[0-9]+]] -; SI: BB#4: +; SI: BB#3: ; SI: buffer_store_dword -; SI: v_cmp_ge_i64_e64 [[CMP:s\[[0-9]+:[0-9]+\]]] -; SI: s_or_b64 [[COND_STATE]], [[CMP]], [[COND_STATE]] +; SI: v_cmp_ge_i64_e32 [[CMP:s\[[0-9]+:[0-9]+\]|vcc]] +; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]] -; SI: BB3_5: +; SI: [[LABEL_FLOW]]: ; SI: s_or_b64 exec, exec, [[ORNEG2]] -; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[COND_STATE]] +; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]] ; SI: s_andn2_b64 exec, exec, [[COND_STATE]] -; SI: s_cbranch_execnz BB3_3 +; SI: s_cbranch_execnz [[LABEL_LOOP]] -; SI: BB#6 +; SI: BB#5 ; SI: s_or_b64 exec, exec, [[COND_STATE]] -; SI: BB3_2: +; SI: [[LABEL_EXIT]]: ; SI-NOT: [[COND_STATE]] ; SI: s_endpgm define void @multi_vcond_loop(i32 addrspace(1)* noalias nocapture %arg, i32 addrspace(1)* noalias nocapture readonly %arg1, i32 addrspace(1)* noalias nocapture readonly %arg2, i32 addrspace(1)* noalias nocapture readonly %arg3) #1 { bb: - %tmp = tail call i32 @llvm.r600.read.tidig.x() #0 + %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp4 = sext i32 %tmp to i64 %tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg3, i64 %tmp4 %tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4 diff --git a/test/CodeGen/AMDGPU/vector-alloca.ll b/test/CodeGen/AMDGPU/vector-alloca.ll index 6f3b4847fbdf..c151ca9ef9b4 100644 --- a/test/CodeGen/AMDGPU/vector-alloca.ll +++ b/test/CodeGen/AMDGPU/vector-alloca.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=verde -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG -check-prefix=FUNC %s ; FUNC-LABEL: {{^}}vector_read: ; EG: MOV diff --git a/test/CodeGen/AMDGPU/vector-extract-insert.ll b/test/CodeGen/AMDGPU/vector-extract-insert.ll new file mode 100644 index 000000000000..2d39f82e2499 --- /dev/null +++ b/test/CodeGen/AMDGPU/vector-extract-insert.ll @@ -0,0 +1,84 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; Test that when extracting the same unknown vector index from an +; insertelement the dynamic indexing is folded away. + +declare i32 @llvm.amdgcn.workitem.id.x() #0 + +; No dynamic indexing required +; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4i32: +; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} +; GCN-NOT buffer_load_dword +; GCN-NOT: [[VAL]] +; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOT: [[VVAL]] +; GCN: buffer_store_dword [[VVAL]] +define void @extract_insert_same_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext + %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext + %vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in + %insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx + %extract = extractelement <4 x i32> %insert, i32 %idx + store i32 %extract, i32 addrspace(1)* %gep.out + ret void +} + +; GCN-LABEL: {{^}}extract_insert_different_dynelt_v4i32: +; GCN: buffer_load_dwordx4 +; GCN: v_movreld_b32 +; GCN: v_movrels_b32 +; GCN: buffer_store_dword v +define void @extract_insert_different_dynelt_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx0, i32 %idx1) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext + %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext + %vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in + %insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx0 + %extract = extractelement <4 x i32> %insert, i32 %idx1 + store i32 %extract, i32 addrspace(1)* %gep.out + ret void +} + +; GCN-LABEL: {{^}}extract_insert_same_elt2_v4i32: +; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} +; GCN-NOT buffer_load_dword +; GCN-NOT: [[VAL]] +; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOT: [[VVAL]] +; GCN: buffer_store_dword [[VVAL]] +define void @extract_insert_same_elt2_v4i32(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %val, i32 %idx) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep.in = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %in, i64 %id.ext + %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %id.ext + %vec = load <4 x i32>, <4 x i32> addrspace(1)* %gep.in + %insert = insertelement <4 x i32> %vec, i32 %val, i32 %idx + %extract = extractelement <4 x i32> %insert, i32 %idx + store i32 %extract, i32 addrspace(1)* %gep.out + ret void +} + +; GCN-LABEL: {{^}}extract_insert_same_dynelt_v4f32: +; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd{{$}} +; GCN-NOT buffer_load_dword +; GCN-NOT: [[VAL]] +; GCN: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] +; GCN-NOT: [[VVAL]] +; GCN: buffer_store_dword [[VVAL]] +define void @extract_insert_same_dynelt_v4f32(float addrspace(1)* %out, <4 x float> addrspace(1)* %in, float %val, i32 %idx) #1 { + %id = call i32 @llvm.amdgcn.workitem.id.x() + %id.ext = sext i32 %id to i64 + %gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext + %gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext + %vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in + %insert = insertelement <4 x float> %vec, float %val, i32 %idx + %extract = extractelement <4 x float> %insert, i32 %idx + store float %extract, float addrspace(1)* %gep.out + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } \ No newline at end of file diff --git a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll index cd7c78f408dd..6c33bc98c605 100644 --- a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll +++ b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s -; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s -; XUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA %s -; XUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA %s +; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s +; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s +; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s +; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -mattr=+vgpr-spilling -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s ; This ends up using all 256 registers and requires register ; scavenging which will fail to find an unsued register. @@ -11,24 +11,33 @@ ; FIXME: The same register is initialized to 0 for every spill. -declare i32 @llvm.r600.read.tgid.x() #1 -declare i32 @llvm.r600.read.tgid.y() #1 -declare i32 @llvm.r600.read.tgid.z() #1 - ; GCN-LABEL: {{^}}spill_vgpr_compute: -; GCN: s_mov_b32 s16, s3 -; GCN: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 -; GCN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 -; GCN-NEXT: s_mov_b32 s14, -1 -; SI-NEXT: s_mov_b32 s15, 0x80f000 -; VI-NEXT: s_mov_b32 s15, 0x800000 +; HSA: enable_sgpr_private_segment_buffer = 1 +; HSA: enable_sgpr_flat_scratch_init = 0 +; HSA: workitem_private_segment_byte_size = 1024 + +; GCN-NOT: flat_scr + +; GCNMESA-DAG: s_mov_b32 s16, s3 +; GCNMESA-DAG: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 +; GCNMESA--DAG: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 +; GCNMESA-DAG: s_mov_b32 s14, -1 +; SIMESA-DAG: s_mov_b32 s15, 0xe8f000 +; VIMESA-DAG: s_mov_b32 s15, 0xe80000 -; GCN: buffer_store_dword {{v[0-9]+}}, s[12:15], s16 offset:{{[0-9]+}} ; 4-byte Folded Spill +; GCN: buffer_store_dword {{v[0-9]+}}, off, s[12:15], s16 offset:{{[0-9]+}} ; 4-byte Folded Spill -; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} -; GCN: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_store_dword {{v[0-9]}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_store_dword {{v[0-9]}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_store_dword {{v[0-9]}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_store_dword {{v[0-9]}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} + +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} +; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[12:15], s16 offen offset:{{[0-9]+}} ; GCN: NumVgprs: 256 ; GCN: ScratchSize: 1024 @@ -175,7 +184,8 @@ bb12: ; preds = %bb145, %bb %tmp140 = phi float [ 0.000000e+00, %bb ], [ %tmp405, %bb145 ] %tmp141 = phi float [ 0.000000e+00, %bb ], [ %tmp406, %bb145 ] %tmp142 = bitcast float %tmp95 to i32 - %tmp143 = icmp sgt i32 %tmp142, 125 + %tid = call i32 @llvm.r600.read.tidig.x() #1 + %tmp143 = icmp sgt i32 %tmp142, %tid br i1 %tmp143, label %bb144, label %bb145 bb144: ; preds = %bb12 @@ -581,5 +591,7 @@ bb145: ; preds = %bb12 br label %bb12 } +declare i32 @llvm.r600.read.tidig.x() #1 + attributes #0 = { nounwind } attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll index 16abb89bb0b8..7d97777a78bd 100644 --- a/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll +++ b/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll @@ -8,22 +8,25 @@ ; intermediate register class copies. ; FIXME: The same register is initialized to 0 for every spill. +; FIXME: The unused arguments are removed ; GCN-LABEL: {{^}}main: -; GCN: s_mov_b32 s12, SCRATCH_RSRC_DWORD0 -; GCN-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1 -; GCN-NEXT: s_mov_b32 s14, -1 -; SI-NEXT: s_mov_b32 s15, 0x80f000 -; VI-NEXT: s_mov_b32 s15, 0x800000 +; GCN-DAG: s_mov_b32 s13, s12 +; GCN-DAG: s_mov_b32 s16, SCRATCH_RSRC_DWORD0 +; GCN-DAG: s_mov_b32 s17, SCRATCH_RSRC_DWORD1 +; GCN-DAG: s_mov_b32 s18, -1 +; SI-DAG: s_mov_b32 s19, 0xe8f000 +; VI-DAG: s_mov_b32 s19, 0xe80000 -; s12 is offset user SGPR -; GCN: buffer_store_dword {{v[0-9]+}}, s[12:15], s11 offset:{{[0-9]+}} ; 4-byte Folded Spill +; s13 is offset system SGPR +; GCN: buffer_store_dword {{v[0-9]+}}, off, s[16:19], s13 offset:{{[0-9]+}} ; 16-byte Folded Spill +; GCN: buffer_load_dword v{{[0-9]+}}, off, s[16:19], s13 offset:{{[0-9]+}} ; 16-byte Folded Reload ; GCN: NumVgprs: 256 ; GCN: ScratchSize: 1024 -define void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { +define amdgpu_vs void @main([9 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { bb: %tmp = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %arg1, i64 0, i64 0 %tmp11 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, align 16, !tbaa !0 @@ -172,7 +175,8 @@ bb24: ; preds = %bb157, %bb %tmp152 = phi float [ 0.000000e+00, %bb ], [ %tmp417, %bb157 ] %tmp153 = phi float [ 0.000000e+00, %bb ], [ %tmp418, %bb157 ] %tmp154 = bitcast float %tmp107 to i32 - %tmp155 = icmp sgt i32 %tmp154, 125 + %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #1 + %tmp155 = icmp sgt i32 %tmp154, %tid br i1 %tmp155, label %bb156, label %bb157 bb156: ; preds = %bb24 @@ -487,7 +491,9 @@ declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="1" "enable-no-nans-fp-math"="true" } +declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1 + +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } !0 = !{!1, !1, i64 0, i32 1} diff --git a/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll b/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll new file mode 100644 index 000000000000..ad7521a3da9b --- /dev/null +++ b/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll @@ -0,0 +1,24 @@ +; RUN: not llc -march=amdgcn -mcpu=tonga < %s 2>&1 | FileCheck -check-prefix=ERROR %s + +; ERROR: error: :1:42: in function rsq_legacy_f32 void (float addrspace(1)*, float): intrinsic not supported on subtarget + +declare float @llvm.amdgcn.rsq.legacy(float) #0 + +define void @rsq_legacy_f32(float addrspace(1)* %out, float %src) #1 { + %rsq = call float @llvm.amdgcn.rsq.legacy(float %src), !dbg !4 + store float %rsq, float addrspace(1)* %out, align 4 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!2, !3} + +!0 = distinct !DICompileUnit(language: DW_LANG_OpenCL, file: !1, isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug) +!1 = !DIFile(filename: "foo.cl", directory: "/dev/null") +!2 = !{i32 2, !"Dwarf Version", i32 4} +!3 = !{i32 2, !"Debug Info Version", i32 3} +!4 = !DILocation(line: 1, column: 42, scope: !5) +!5 = distinct !DISubprogram(name: "rsq_legacy_f32", scope: null, line: 1, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0) diff --git a/test/CodeGen/AMDGPU/vop-shrink.ll b/test/CodeGen/AMDGPU/vop-shrink.ll index 2bfe1b2bd6ec..ae8ec58270c1 100644 --- a/test/CodeGen/AMDGPU/vop-shrink.ll +++ b/test/CodeGen/AMDGPU/vop-shrink.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; Test that we correctly commute a sub instruction ; FUNC-LABEL: {{^}}sub_rev: @@ -10,7 +10,7 @@ define void @sub_rev(i32 addrspace(1)* %out, <4 x i32> %sgpr, i32 %cond) { entry: - %vgpr = call i32 @llvm.r600.read.tidig.x() #1 + %vgpr = call i32 @llvm.amdgcn.workitem.id.x() #1 %tmp = icmp eq i32 %cond, 0 br i1 %tmp, label %if, label %else @@ -37,7 +37,7 @@ endif: ; preds = %else, %if ; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000 define void @add_fold(float addrspace(1)* %out) { entry: - %tmp = call i32 @llvm.r600.read.tidig.x() + %tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = uitofp i32 %tmp to float %tmp2 = fadd float %tmp1, 1.024000e+03 store float %tmp2, float addrspace(1)* %out @@ -45,7 +45,7 @@ entry: } ; Function Attrs: nounwind readnone -declare i32 @llvm.r600.read.tidig.x() #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 attributes #0 = { nounwind readnone } attributes #1 = { readnone } diff --git a/test/CodeGen/AMDGPU/vselect.ll b/test/CodeGen/AMDGPU/vselect.ll index dc1f1ea11b01..0cd706b642d7 100644 --- a/test/CodeGen/AMDGPU/vselect.ll +++ b/test/CodeGen/AMDGPU/vselect.ll @@ -1,29 +1,29 @@ -;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s -;RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s +;RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=VI --check-prefix=FUNC %s +;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG --check-prefix=FUNC %s -;FUNC-LABEL: {{^}}test_select_v2i32: +; FUNC-LABEL: {{^}}test_select_v2i32: -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y -;SI: v_cndmask_b32_e64 -;SI: v_cndmask_b32_e32 +; SI: v_cndmask_b32_e64 +; SI: v_cndmask_b32_e32 -define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1) { +define void @test_select_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in0, <2 x i32> addrspace(1)* %in1, <2 x i32> %val) { entry: - %0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0 - %1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1 - %cmp = icmp ne <2 x i32> %0, %1 - %result = select <2 x i1> %cmp, <2 x i32> %0, <2 x i32> %1 + %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0 + %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1 + %cmp = icmp sgt <2 x i32> %load0, %load1 + %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0 store <2 x i32> %result, <2 x i32> addrspace(1)* %out ret void } -;FUNC-LABEL: {{^}}test_select_v2f32: +; FUNC-LABEL: {{^}}test_select_v2f32: -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI: v_cndmask_b32_e64 ;SI: v_cndmask_b32_e32 @@ -40,24 +40,24 @@ entry: ;FUNC-LABEL: {{^}}test_select_v4i32: -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[4].X +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].W +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Z +; EG-DAG: CNDE_INT {{\** *}}T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}, KC0[3].Y ; FIXME: The shrinking does not happen on tonga -;SI: v_cndmask_b32 -;SI: v_cndmask_b32 -;SI: v_cndmask_b32 -;SI: v_cndmask_b32 +; SI: v_cndmask_b32 +; SI: v_cndmask_b32 +; SI: v_cndmask_b32 +; SI: v_cndmask_b32 -define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) { +define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1, <4 x i32> %val) { entry: - %0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0 - %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1 - %cmp = icmp ne <4 x i32> %0, %1 - %result = select <4 x i1> %cmp, <4 x i32> %0, <4 x i32> %1 + %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0 + %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1 + %cmp = icmp sgt <4 x i32> %load0, %load1 + %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0 store <4 x i32> %result, <4 x i32> addrspace(1)* %out ret void } diff --git a/test/CodeGen/AMDGPU/wait.ll b/test/CodeGen/AMDGPU/wait.ll index 107e84b33be9..265774180a7f 100644 --- a/test/CodeGen/AMDGPU/wait.ll +++ b/test/CodeGen/AMDGPU/wait.ll @@ -11,14 +11,14 @@ ; DEFAULT: exp ; DEFAULT: s_waitcnt lgkmcnt(0) ; DEFAULT: s_endpgm -define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 { +define amdgpu_vs void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) { main_body: %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0 %tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6) %tmp12 = extractelement <4 x float> %tmp11, i32 0 %tmp13 = extractelement <4 x float> %tmp11, i32 1 - call void @llvm.AMDGPU.barrier.global() #1 + call void @llvm.amdgcn.s.barrier() #1 %tmp14 = extractelement <4 x float> %tmp11, i32 2 ; %tmp15 = extractelement <4 x float> %tmp11, i32 3 %tmp15 = load float, float addrspace(2)* %constptr, align 4 ; Force waiting for expcnt and lgkmcnt @@ -45,8 +45,8 @@ main_body: ; ILPMAX: s_waitcnt vmcnt(0) ; ILPMAX: s_endpgm -define void @main2([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* -byval, i32 inreg, i32 inreg, i32, i32, i32, i32) #0 { +define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, [16 x <16 x i8>] addrspace(2)* +byval, i32 inreg, i32 inreg, i32, i32, i32, i32) { main_body: %11 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %4, i64 0, i64 0 %12 = load <16 x i8>, <16 x i8> addrspace(2)* %11, align 16, !tbaa !0 @@ -71,14 +71,13 @@ main_body: ; Function Attrs: convergent nounwind -declare void @llvm.AMDGPU.barrier.global() #1 +declare void @llvm.amdgcn.s.barrier() #1 ; Function Attrs: nounwind readnone declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="1" } attributes #1 = { convergent nounwind } attributes #2 = { nounwind readnone } diff --git a/test/CodeGen/AMDGPU/waitcnt-flat.ll b/test/CodeGen/AMDGPU/waitcnt-flat.ll new file mode 100644 index 000000000000..38dbf2794fc5 --- /dev/null +++ b/test/CodeGen/AMDGPU/waitcnt-flat.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji | FileCheck --check-prefix=GCN %s + +; If flat_store_dword and flat_load_dword use different registers for the data +; operand, this test is not broken. It just means it is no longer testing +; for the original bug. + +; GCN: {{^}}test: +; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]] +; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0) +; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}] +define void @test(i32 addrspace(1)* %out, i32 %in) { + store volatile i32 0, i32 addrspace(1)* %out + %val = load volatile i32, i32 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/AMDGPU/work-item-intrinsics.ll b/test/CodeGen/AMDGPU/work-item-intrinsics.ll deleted file mode 100644 index e7fcd1ff3650..000000000000 --- a/test/CodeGen/AMDGPU/work-item-intrinsics.ll +++ /dev/null @@ -1,275 +0,0 @@ -; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SI-NOHSA -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOHSA -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=HSA -check-prefix=CI-HSA -check-prefix=FUNC %s -; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=HSA -check-prefix=VI-HSA -check-prefix=FUNC %s -; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s - - -; FUNC-LABEL: {{^}}ngroups_x: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].X - -; HSA: .amd_kernel_code_t - -; HSA: enable_sgpr_private_segment_buffer = 1 -; HSA: enable_sgpr_dispatch_ptr = 0 -; HSA: enable_sgpr_queue_ptr = 0 -; HSA: enable_sgpr_kernarg_segment_ptr = 1 -; HSA: enable_sgpr_dispatch_id = 0 -; HSA: enable_sgpr_flat_scratch_init = 0 -; HSA: enable_sgpr_private_segment_size = 0 -; HSA: enable_sgpr_grid_workgroup_count_x = 0 -; HSA: enable_sgpr_grid_workgroup_count_y = 0 -; HSA: enable_sgpr_grid_workgroup_count_z = 0 - -; HSA: .end_amd_kernel_code_t - - -; GCN-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] - -define void @ngroups_x (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.ngroups.x() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}ngroups_y: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1 -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @ngroups_y (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.ngroups.y() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}ngroups_z: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2 -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @ngroups_z (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.ngroups.z() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}global_size_x: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[0].W - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3 -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @global_size_x (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.global.size.x() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}global_size_y: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[1].X - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4 -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @global_size_y (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.global.size.y() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}global_size_z: -; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]] -; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y - -; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5 -; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]] -; GCN-NOHSA: buffer_store_dword [[VVAL]] -define void @global_size_z (i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.global.size.z() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; The tgid values are stored in sgprs offset by the number of user -; sgprs. - -; FUNC-LABEL: {{^}}tgid_x: -; HSA: .amd_kernel_code_t -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 0 -; HSA: compute_pgm_rsrc2_tgid_z_en = 0 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 -; HSA: enable_sgpr_grid_workgroup_count_x = 0 -; HSA: enable_sgpr_grid_workgroup_count_y = 0 -; HSA: enable_sgpr_grid_workgroup_count_z = 0 -; HSA: .end_amd_kernel_code_t - -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s2{{$}} -; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s6{{$}} -; GCN-NOHSA: buffer_store_dword [[VVAL]] -; HSA: flat_store_dword [[VVAL]] - -; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 -; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 -; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 -; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 -; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 -; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 -define void @tgid_x(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tgid.x() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}tgid_y: -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 1 -; HSA: compute_pgm_rsrc2_tgid_z_en = 0 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 -; HSA: enable_sgpr_grid_workgroup_count_x = 0 -; HSA: enable_sgpr_grid_workgroup_count_y = 0 -; HSA: enable_sgpr_grid_workgroup_count_z = 0 -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3 -; GCN-HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7 -; GCN-NOHSA: buffer_store_dword [[VVAL]] -; HSA: flat_store_dword [[VVAL]] - -; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 -; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 -; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 -; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1 -; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 -; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 -define void @tgid_y(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tgid.y() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; FUNC-LABEL: {{^}}tgid_z: -; HSA: compute_pgm_rsrc2_user_sgpr = 6 -; HSA: compute_pgm_rsrc2_tgid_x_en = 1 -; HSA: compute_pgm_rsrc2_tgid_y_en = 0 -; HSA: compute_pgm_rsrc2_tgid_z_en = 1 -; HSA: compute_pgm_rsrc2_tg_size_en = 0 -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 -; HSA: enable_sgpr_private_segment_buffer = 1 -; HSA: enable_sgpr_dispatch_ptr = 0 -; HSA: enable_sgpr_queue_ptr = 0 -; HSA: enable_sgpr_kernarg_segment_ptr = 1 -; HSA: enable_sgpr_dispatch_id = 0 -; HSA: enable_sgpr_flat_scratch_init = 0 -; HSA: enable_sgpr_private_segment_size = 0 -; HSA: enable_sgpr_grid_workgroup_count_x = 0 -; HSA: enable_sgpr_grid_workgroup_count_y = 0 -; HSA: enable_sgpr_grid_workgroup_count_z = 0 - -; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}} -; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7{{$}} -; GCN-NOHSA: buffer_store_dword [[VVAL]] -; HSA: flat_store_dword [[VVAL]] - -; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6 -; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2 -; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1 -; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 -; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 -; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 -define void @tgid_z(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tgid.z() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; GCN-NOHSA: .section .AMDGPU.config -; GCN-NOHSA: .long 47180 -; GCN-NOHSA-NEXT: .long 132{{$}} - -; FUNC-LABEL: {{^}}tidig_x: -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0 -; GCN-NOHSA: buffer_store_dword v0 -; HSA: flat_store_dword v0 -define void @tidig_x(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tidig.x() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; GCN-NOHSA: .section .AMDGPU.config -; GCN-NOHSA: .long 47180 -; GCN-NOHSA-NEXT: .long 2180{{$}} - -; FUNC-LABEL: {{^}}tidig_y: - -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 1 -; GCN-NOHSA: buffer_store_dword v1 -; HSA: flat_store_dword v1 -define void @tidig_y(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tidig.y() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -; GCN-NOHSA: .section .AMDGPU.config -; GCN-NOHSA: .long 47180 -; GCN-NOHSA-NEXT: .long 4228{{$}} - -; FUNC-LABEL: {{^}}tidig_z: -; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 2 -; GCN-NOHSA: buffer_store_dword v2 -; HSA: flat_store_dword v2 -define void @tidig_z(i32 addrspace(1)* %out) { -entry: - %0 = call i32 @llvm.r600.read.tidig.z() #0 - store i32 %0, i32 addrspace(1)* %out - ret void -} - -declare i32 @llvm.r600.read.ngroups.x() #0 -declare i32 @llvm.r600.read.ngroups.y() #0 -declare i32 @llvm.r600.read.ngroups.z() #0 - -declare i32 @llvm.r600.read.global.size.x() #0 -declare i32 @llvm.r600.read.global.size.y() #0 -declare i32 @llvm.r600.read.global.size.z() #0 - -declare i32 @llvm.r600.read.tgid.x() #0 -declare i32 @llvm.r600.read.tgid.y() #0 -declare i32 @llvm.r600.read.tgid.z() #0 - -declare i32 @llvm.r600.read.tidig.x() #0 -declare i32 @llvm.r600.read.tidig.y() #0 -declare i32 @llvm.r600.read.tidig.z() #0 - -declare i32 @llvm.AMDGPU.read.workdim() #0 - -attributes #0 = { readnone } diff --git a/test/CodeGen/AMDGPU/wqm.ll b/test/CodeGen/AMDGPU/wqm.ll new file mode 100644 index 000000000000..23b0ffd5b3da --- /dev/null +++ b/test/CodeGen/AMDGPU/wqm.ll @@ -0,0 +1,366 @@ +;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI +;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI + +; Check that WQM isn't triggered by image load/store intrinsics. +; +;CHECK-LABEL: {{^}}test1: +;CHECK-NOT: s_wqm +define amdgpu_ps <4 x float> @test1(<8 x i32> inreg %rsrc, <4 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + call void @llvm.amdgcn.image.store.v4i32(<4 x float> %tex, <4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0) + ret <4 x float> %tex +} + +; Check that WQM is triggered by image samples and left untouched for loads... +; +;CHECK-LABEL: {{^}}test2: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: image_sample +;CHECK-NOT: exec +;CHECK: _load_dword v0, +define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) { +main_body: + %c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %c.2 = bitcast <4 x float> %c.1 to <4 x i32> + %c.3 = extractelement <4 x i32> %c.2, i32 0 + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3 + %data = load float, float addrspace(1)* %gep + ret float %data +} + +; ... but disabled for stores (and, in this simple case, not re-enabled). +; +;CHECK-LABEL: {{^}}test3: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: image_sample +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;CHECK: store +;CHECK-NOT: exec +;CHECK: .size test3 +define amdgpu_ps <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) { +main_body: + %tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tex.1 = bitcast <4 x float> %tex to <4 x i32> + %tex.2 = extractelement <4 x i32> %tex.1, i32 0 + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %tex.2 + %wr = extractelement <4 x float> %tex, i32 1 + store float %wr, float addrspace(1)* %gep + ret <4 x float> %tex +} + +; Check that WQM is re-enabled when required. +; +;CHECK-LABEL: {{^}}test4: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: v_mul_lo_i32 [[MUL:v[0-9]+]], v0, v1 +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;CHECK: store +;CHECK: s_wqm_b64 exec, exec +;CHECK: image_sample v[0:3], [[MUL]], s[0:7], s[8:11] dmask:0xf +define amdgpu_ps <4 x float> @test4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %d, float %data) { +main_body: + %c.1 = mul i32 %c, %d + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.1 + store float %data, float addrspace(1)* %gep + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.1, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + ret <4 x float> %tex +} + +; Check a case of one branch of an if-else requiring WQM, the other requiring +; exact. +; +; Note: In this particular case, the save-and-restore could be avoided if the +; analysis understood that the two branches of the if-else are mutually +; exclusive. +; +;CHECK-LABEL: {{^}}test_control_flow_0: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: %ELSE +;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]] +;CHECK: store +;CHECK: s_mov_b64 exec, [[SAVED]] +;CHECK: %IF +;CHECK: image_sample +define amdgpu_ps float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) { +main_body: + %cmp = icmp eq i32 %z, 0 + br i1 %cmp, label %IF, label %ELSE + +IF: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %data.if = extractelement <4 x float> %tex, i32 0 + br label %END + +ELSE: + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c + store float %data, float addrspace(1)* %gep + br label %END + +END: + %r = phi float [ %data.if, %IF ], [ %data, %ELSE ] + ret float %r +} + +; Reverse branch order compared to the previous test. +; +;CHECK-LABEL: {{^}}test_control_flow_1: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: %IF +;CHECK: image_sample +;CHECK: %Flow +;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], +;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]] +;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]] +;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]] +;CHECK-NEXT: mask branch [[END_BB:BB[0-9]+_[0-9]+]] +;CHECK-NEXT: ; BB#3: ; %ELSE +;CHECK: store_dword +;CHECK: [[END_BB]]: ; %END +;CHECK: s_or_b64 exec, exec, +;CHECK: v_mov_b32_e32 v0 +;CHECK: ; return +define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) { +main_body: + %cmp = icmp eq i32 %z, 0 + br i1 %cmp, label %ELSE, label %IF + +IF: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %data.if = extractelement <4 x float> %tex, i32 0 + br label %END + +ELSE: + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c + store float %data, float addrspace(1)* %gep + br label %END + +END: + %r = phi float [ %data.if, %IF ], [ %data, %ELSE ] + ret float %r +} + +; Check that branch conditions are properly marked as needing WQM... +; +;CHECK-LABEL: {{^}}test_control_flow_2: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;CHECK: store +;CHECK: s_wqm_b64 exec, exec +;CHECK: load +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;CHECK: store +;CHECK: s_wqm_b64 exec, exec +;CHECK: v_cmp +define amdgpu_ps <4 x float> @test_control_flow_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) { +main_body: + %idx.1 = extractelement <3 x i32> %idx, i32 0 + %gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1 + %data.1 = extractelement <2 x float> %data, i32 0 + store float %data.1, float addrspace(1)* %gep.1 + + ; The load that determines the branch (and should therefore be WQM) is + ; surrounded by stores that require disabled WQM. + %idx.2 = extractelement <3 x i32> %idx, i32 1 + %gep.2 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.2 + %z = load float, float addrspace(1)* %gep.2 + + %idx.3 = extractelement <3 x i32> %idx, i32 2 + %gep.3 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.3 + %data.3 = extractelement <2 x float> %data, i32 1 + store float %data.3, float addrspace(1)* %gep.3 + + %cc = fcmp ogt float %z, 0.0 + br i1 %cc, label %IF, label %ELSE + +IF: + %coord.IF = mul i32 %coord, 3 + br label %END + +ELSE: + %coord.ELSE = mul i32 %coord, 4 + br label %END + +END: + %coord.END = phi i32 [ %coord.IF, %IF ], [ %coord.ELSE, %ELSE ] + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord.END, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + ret <4 x float> %tex +} + +; ... but only if they really do need it. +; +;CHECK-LABEL: {{^}}test_control_flow_3: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: image_sample +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;CHECK: store +;CHECK: load +;CHECK: store +;CHECK: v_cmp +define amdgpu_ps float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) { +main_body: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %tex.1 = extractelement <4 x float> %tex, i32 0 + + %idx.1 = extractelement <3 x i32> %idx, i32 0 + %gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1 + %data.1 = extractelement <2 x float> %data, i32 0 + store float %data.1, float addrspace(1)* %gep.1 + + %idx.2 = extractelement <3 x i32> %idx, i32 1 + %gep.2 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.2 + %z = load float, float addrspace(1)* %gep.2 + + %idx.3 = extractelement <3 x i32> %idx, i32 2 + %gep.3 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.3 + %data.3 = extractelement <2 x float> %data, i32 1 + store float %data.3, float addrspace(1)* %gep.3 + + %cc = fcmp ogt float %z, 0.0 + br i1 %cc, label %IF, label %ELSE + +IF: + %tex.IF = fmul float %tex.1, 3.0 + br label %END + +ELSE: + %tex.ELSE = fmul float %tex.1, 4.0 + br label %END + +END: + %tex.END = phi float [ %tex.IF, %IF ], [ %tex.ELSE, %ELSE ] + ret float %tex.END +} + +; Another test that failed at some point because of terminator handling. +; +;CHECK-LABEL: {{^}}test_control_flow_4: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: %IF +;CHECK: load +;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] +;CHECK: store +;CHECK: s_mov_b64 exec, [[SAVE]] +;CHECK: %END +;CHECK: image_sample +define amdgpu_ps <4 x float> @test_control_flow_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %coord, i32 %y, float %z) { +main_body: + %cond = icmp eq i32 %y, 0 + br i1 %cond, label %IF, label %END + +IF: + %data = load float, float addrspace(1)* %ptr + %gep = getelementptr float, float addrspace(1)* %ptr, i32 1 + store float %data, float addrspace(1)* %gep + br label %END + +END: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + ret <4 x float> %tex +} + +; Kill is performed in WQM mode so that uniform kill behaves correctly ... +; +;CHECK-LABEL: {{^}}test_kill_0: +;CHECK-NEXT: ; %main_body +;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +;CHECK-NEXT: s_wqm_b64 exec, exec +;CHECK: image_sample +;CHECK: s_and_b64 exec, exec, [[ORIG]] +;SI: buffer_store_dword +;VI: flat_store_dword +;CHECK: s_wqm_b64 exec, exec +;CHECK: v_cmpx_ +;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]] +;SI: buffer_store_dword +;VI: flat_store_dword +;CHECK: s_mov_b64 exec, [[SAVE]] +;CHECK: image_sample +define amdgpu_ps <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <2 x i32> %idx, <2 x float> %data, i32 %coord, i32 %coord2, float %z) { +main_body: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + + %idx.0 = extractelement <2 x i32> %idx, i32 0 + %gep.0 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.0 + %data.0 = extractelement <2 x float> %data, i32 0 + store float %data.0, float addrspace(1)* %gep.0 + + call void @llvm.AMDGPU.kill(float %z) + + %idx.1 = extractelement <2 x i32> %idx, i32 1 + %gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1 + %data.1 = extractelement <2 x float> %data, i32 1 + store float %data.1, float addrspace(1)* %gep.1 + + %tex2 = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord2, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + %out = fadd <4 x float> %tex, %tex2 + + ret <4 x float> %out +} + +; ... but only if WQM is necessary. +; +; CHECK-LABEL: {{^}}test_kill_1: +; CHECK-NEXT: ; %main_body +; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +; CHECK: s_wqm_b64 exec, exec +; CHECK: image_sample +; CHECK: s_and_b64 exec, exec, [[ORIG]] +; SI: buffer_store_dword +; VI: flat_store_dword +; CHECK-NOT: wqm +; CHECK: v_cmpx_ +define amdgpu_ps <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %idx, float %data, i32 %coord, i32 %coord2, float %z) { +main_body: + %tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0) + + %gep = getelementptr float, float addrspace(1)* %ptr, i32 %idx + store float %data, float addrspace(1)* %gep + + call void @llvm.AMDGPU.kill(float %z) + + ret <4 x float> %tex +} + +; Check prolog shaders. +; +; CHECK-LABEL: {{^}}test_prolog_1: +; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec +; CHECK: s_wqm_b64 exec, exec +; CHECK: v_add_f32_e32 v0, +; CHECK: s_and_b64 exec, exec, [[ORIG]] +define amdgpu_ps float @test_prolog_1(float %a, float %b) #4 { +main_body: + %s = fadd float %a, %b + ret float %s +} + +declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 + +declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2 + +declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #3 +declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #3 + +declare void @llvm.AMDGPU.kill(float) +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + +attributes #1 = { nounwind } +attributes #2 = { nounwind readonly } +attributes #3 = { nounwind readnone } +attributes #4 = { "amdgpu-ps-wqm-outputs" } diff --git a/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll b/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll new file mode 100644 index 000000000000..deac809f9b05 --- /dev/null +++ b/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll @@ -0,0 +1,22 @@ +; XFAIL: * +; REQUIRES: asserts +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s + +; write_register doesn't prevent us from illegally trying to write a +; vgpr value into a scalar register, but I don't think there's much we +; can do to avoid this. + +declare void @llvm.write_register.i32(metadata, i32) #0 +declare i32 @llvm.amdgcn.workitem.id.x() #0 + + +define void @write_vgpr_into_sgpr() { + %tid = call i32 @llvm.amdgcn.workitem.id.x() + call void @llvm.write_register.i32(metadata !0, i32 %tid) + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + +!0 = !{!"exec_lo"} diff --git a/test/CodeGen/AMDGPU/write_register.ll b/test/CodeGen/AMDGPU/write_register.ll new file mode 100644 index 000000000000..88660ba6ec6a --- /dev/null +++ b/test/CodeGen/AMDGPU/write_register.ll @@ -0,0 +1,80 @@ +; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck %s + +declare void @llvm.write_register.i32(metadata, i32) #0 +declare void @llvm.write_register.i64(metadata, i64) #0 + +; CHECK-LABEL: {{^}}test_write_m0: +define void @test_write_m0(i32 %val) #0 { + call void @llvm.write_register.i32(metadata !0, i32 0) + call void @llvm.write_register.i32(metadata !0, i32 -1) + call void @llvm.write_register.i32(metadata !0, i32 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_exec: +; CHECK: s_mov_b64 exec, 0 +; CHECK: s_mov_b64 exec, -1 +; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}} +define void @test_write_exec(i64 %val) #0 { + call void @llvm.write_register.i64(metadata !1, i64 0) + call void @llvm.write_register.i64(metadata !1, i64 -1) + call void @llvm.write_register.i64(metadata !1, i64 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_flat_scratch: +; CHECK: s_mov_b64 flat_scratch, 0 +; CHECK: s_mov_b64 flat_scratch, -1 +; CHECK: s_mov_b64 flat_scratch, s{{\[[0-9]+:[0-9]+\]}} +define void @test_write_flat_scratch(i64 %val) #0 { + call void @llvm.write_register.i64(metadata !2, i64 0) + call void @llvm.write_register.i64(metadata !2, i64 -1) + call void @llvm.write_register.i64(metadata !2, i64 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_flat_scratch_lo: +; CHECK: s_mov_b32 flat_scratch_lo, 0 +; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}} +define void @test_write_flat_scratch_lo(i32 %val) #0 { + call void @llvm.write_register.i32(metadata !3, i32 0) + call void @llvm.write_register.i32(metadata !3, i32 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_flat_scratch_hi: +; CHECK: s_mov_b32 flat_scratch_hi, 0 +; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}} +define void @test_write_flat_scratch_hi(i32 %val) #0 { + call void @llvm.write_register.i32(metadata !4, i32 0) + call void @llvm.write_register.i32(metadata !4, i32 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_exec_lo: +; CHECK: s_mov_b32 exec_lo, 0 +; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}} +define void @test_write_exec_lo(i32 %val) #0 { + call void @llvm.write_register.i32(metadata !5, i32 0) + call void @llvm.write_register.i32(metadata !5, i32 %val) + ret void +} + +; CHECK-LABEL: {{^}}test_write_exec_hi: +; CHECK: s_mov_b32 exec_hi, 0 +; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}} +define void @test_write_exec_hi(i32 %val) #0 { + call void @llvm.write_register.i32(metadata !6, i32 0) + call void @llvm.write_register.i32(metadata !6, i32 %val) + ret void +} + +attributes #0 = { nounwind } + +!0 = !{!"m0"} +!1 = !{!"exec"} +!2 = !{!"flat_scratch"} +!3 = !{!"flat_scratch_lo"} +!4 = !{!"flat_scratch_hi"} +!5 = !{!"exec_lo"} +!6 = !{!"exec_hi"} diff --git a/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll b/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll index 8b383e4c393d..7f6b80459047 100644 --- a/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll +++ b/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll @@ -71,7 +71,7 @@ declare i32 @llvm.r600.read.global.size.y() #1 ; Function Attrs: nounwind readnone declare i32 @llvm.r600.read.global.size.z() #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind } attributes #1 = { nounwind readnone } !opencl.kernels = !{!0, !1, !2} diff --git a/test/CodeGen/AMDGPU/xor.ll b/test/CodeGen/AMDGPU/xor.ll index 655655d92f08..202170d6e229 100644 --- a/test/CodeGen/AMDGPU/xor.ll +++ b/test/CodeGen/AMDGPU/xor.ll @@ -64,8 +64,8 @@ define void @xor_i1(float addrspace(1)* %out, float addrspace(1)* %in0, float ad ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[XOR]] ; SI: buffer_store_byte [[RESULT]] define void @v_xor_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) { - %a = load i1, i1 addrspace(1)* %in0 - %b = load i1, i1 addrspace(1)* %in1 + %a = load volatile i1, i1 addrspace(1)* %in0 + %b = load volatile i1, i1 addrspace(1)* %in1 %xor = xor i1 %a, %b store i1 %xor, i1 addrspace(1)* %out ret void diff --git a/test/CodeGen/AMDGPU/zero_extend.ll b/test/CodeGen/AMDGPU/zero_extend.ll index 35ddf2b0a465..c3b76da5f778 100644 --- a/test/CodeGen/AMDGPU/zero_extend.ll +++ b/test/CodeGen/AMDGPU/zero_extend.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 -; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 ; R600: {{^}}test: ; R600: MEM_RAT_CACHELESS STORE_RAW diff --git a/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll b/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll new file mode 100644 index 000000000000..842c30b40df2 --- /dev/null +++ b/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s + +; GCN-LABEL: {{^}}zext_or_operand_i64: +; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; GCN: buffer_load_dword v[[LD32:[0-9]+]] +; GCN-NOT: _or_ +; GCN-NOT: v[[HI]] +; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 +; GCN: v_or_b32_e32 v[[LO]], v[[LD32]], v[[LO]] +; GCN-NOT: _or_ +; GCN-NOT: v[[HI]] +; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @zext_or_operand_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) { + %ld.64 = load volatile i64, i64 addrspace(1)* %in0 + %ld.32 = load volatile i32, i32 addrspace(1)* %in1 + %ext = zext i32 %ld.32 to i64 + %or = or i64 %ld.64, %ext + store i64 %or, i64 addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}zext_or_operand_commute_i64: +; GCN: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}} +; GCN: buffer_load_dword v[[LD32:[0-9]+]] +; GCN-NOT: _or_ +; GCN-NOT: v[[HI]] +; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 +; GCN: v_or_b32_e32 v[[LO]], v[[LD32]], v[[LO]] +; GCN-NOT: v[[HI]] +; GCN-NOT: _or_ +; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0 +; GCN: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @zext_or_operand_commute_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in0, i32 addrspace(1)* %in1) { + %ld.64 = load volatile i64, i64 addrspace(1)* %in0 + %ld.32 = load volatile i32, i32 addrspace(1)* %in1 + %ext = zext i32 %ld.32 to i64 + %or = or i64 %ext, %ld.64 + store i64 %or, i64 addrspace(1)* %out + ret void +} diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index d402c16ccacb..0a9fd8955746 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -1,8 +1,10 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin9 -march=arm | FileCheck %s -; CHECK: .cfi_lsda 16, [[LABEL:.*]] -; CHECK: .long [[LABEL]]- -; CHECK: [[LABEL]]: +; CHECK: ldr r0, [[CPI_PERSONALITY:[A-Za-z0-9_]+]] +; CHECK: ldr r0, [[CPI_LSDA:[A-Za-z0-9_]+]] +; CHECK: [[CPI_LSDA]]: +; CHECK: .long [[LSDA_LABEL:[A-Za-z0-9_]+]]- +; CHECK: [[LSDA_LABEL]]: ; CHECK: .byte 255 @ @LPStart Encoding = omit %struct.A = type { i32* } diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index 613694f091d1..3e687322de4f 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -22,10 +22,11 @@ declare void @llvm.dbg.declare(metadata, metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp +!llvm.dbg.cu = !{!0} !0 = !DILocation(line: 5, column: 2, scope: !1) !1 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !2) -!2 = distinct !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scope: !3) -!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: 0, file: !8, retainedTypes: !9) +!2 = distinct !DISubprogram(name: "bar", linkageName: "bar", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, scope: !3) +!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 1.1", isOptimized: true, emissionKind: FullDebug, file: !8, retainedTypes: !9) !4 = !DILocalVariable(name: "count_", line: 5, scope: !5, file: !3, type: !6) !5 = distinct !DILexicalBlock(line: 1, column: 1, file: null, scope: !1) !6 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index 1341830b4a4b..089cff82bc5d 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -15,10 +15,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!3} !llvm.module.flags = !{!15} !0 = !DILocalVariable(name: "b", line: 93, arg: 2, scope: !1, file: !2, type: !6) -!1 = distinct !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: null, type: !4) +!1 = distinct !DISubprogram(name: "__addvsi3", linkageName: "__addvsi3", line: 94, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !12, scope: null, type: !4) !2 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") !12 = !DIFile(filename: "libgcc2.c", directory: "/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc") -!3 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: 0, file: !12, enums: !13, retainedTypes: !13, subprograms: !14) +!3 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", isOptimized: true, emissionKind: FullDebug, file: !12, enums: !13, retainedTypes: !13) !4 = !DISubroutineType(types: !5) !5 = !{!6, !6, !6} !6 = !DIDerivedType(tag: DW_TAG_typedef, name: "SItype", line: 152, file: !12, baseType: !8) @@ -28,5 +28,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !10 = distinct !DILexicalBlock(line: 94, column: 0, file: !12, scope: !1) !11 = !DILocation(line: 100, scope: !10) !13 = !{} -!14 = !{!1} !15 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll index 38b352c473b1..5ae1b6626f1a 100644 --- a/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll +++ b/test/CodeGen/ARM/2010-06-25-Thumb2ITInvalidIterator.ll @@ -44,13 +44,12 @@ declare i32 @x1() optsize declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnone -!llvm.dbg.lv.fn = !{!0, !8, !10, !12} -!llvm.dbg.gv = !{!14} +!llvm.dbg.cu = !{!3} !0 = !DILocalVariable(name: "buf", line: 4, arg: 1, scope: !1, file: !2, type: !6) -!1 = distinct !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !26, scope: null, type: !4) +!1 = distinct !DISubprogram(name: "x0", linkageName: "x0", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !26, scope: null, type: !4) !2 = !DIFile(filename: "t.c", directory: "/private/tmp") -!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26) +!3 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang 2.0", isOptimized: true, file: !26, globals: !{!14}) !4 = !DISubroutineType(types: !5) !5 = !{null} !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !26, scope: !2, baseType: !7) diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index 14ddb59b5387..a90ea137cb7c 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -1,6 +1,9 @@ ; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_breg ; Use DW_OP_breg in variable's location expression if the variable is in a stack slot. +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" +target triple = "arm-apple-darwin" + %struct.SVal = type { i8*, i32 } define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) nounwind ssp !dbg !17 { @@ -78,9 +81,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.module.flags = !{!49} !0 = !DISubprogram(name: "SVal", line: 11, isLocal: false, isDefinition: false, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14) -!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 128, align: 64, file: !48, elements: !4) +!1 = !DICompositeType(tag: DW_TAG_structure_type, name: "SVal", line: 1, size: 64, align: 64, file: !48, elements: !4) !2 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330") -!3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: 1, file: !48, enums: !47, retainedTypes: !47, subprograms: !46, globals: !47, imports: !47) +!3 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", isOptimized: false, emissionKind: FullDebug, file: !48, enums: !47, retainedTypes: !47, globals: !47, imports: !47) !4 = !{!5, !7, !0, !9} !5 = !DIDerivedType(tag: DW_TAG_member, name: "Data", line: 7, size: 64, align: 64, file: !48, scope: !1, baseType: !6) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, baseType: null) @@ -93,24 +96,24 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !14 = !DISubroutineType(types: !15) !15 = !{null, !12} -!16 = distinct !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !1, type: !14) -!17 = distinct !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !18) +!16 = distinct !DISubprogram(name: "SVal", linkageName: "_ZN4SValC1Ev", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !48, scope: !1, type: !14) +!17 = distinct !DISubprogram(name: "foo", linkageName: "_Z3fooi4SVal", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !48, scope: !2, type: !18) !18 = !DISubroutineType(types: !19) !19 = !{!13, !13, !1} -!20 = distinct !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !48, scope: !2, type: !21) +!20 = distinct !DISubprogram(name: "main", linkageName: "main", line: 23, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !3, file: !48, scope: !2, type: !21) !21 = !DISubroutineType(types: !22) !22 = !{!13} !23 = !DILocalVariable(name: "i", line: 16, arg: 1, scope: !17, file: !2, type: !13) !24 = !DILocation(line: 16, scope: !17) !25 = !DILocalVariable(name: "location", line: 16, arg: 2, scope: !17, file: !2, type: !26) -!26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 64, align: 64, file: !48, scope: !2, baseType: !1) +!26 = !DIDerivedType(tag: DW_TAG_reference_type, name: "SVal", size: 32, align: 32, file: !48, scope: !2, baseType: !1) !27 = !DILocation(line: 17, scope: !28) !28 = distinct !DILexicalBlock(line: 16, column: 0, file: !2, scope: !17) !29 = !DILocation(line: 18, scope: !28) !30 = !DILocation(line: 20, scope: !28) !31 = !DILocalVariable(name: "this", line: 11, arg: 1, scope: !16, file: !2, type: !32) -!32 = !DIDerivedType(tag: DW_TAG_const_type, size: 64, align: 64, flags: DIFlagArtificial, file: !48, scope: !2, baseType: !33) -!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 64, align: 64, file: !48, scope: !2, baseType: !1) +!32 = !DIDerivedType(tag: DW_TAG_const_type, flags: DIFlagArtificial, file: !48, scope: !2, baseType: !33) +!33 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !48, scope: !2, baseType: !1) !34 = !DILocation(line: 11, scope: !16) !35 = !DILocation(line: 11, scope: !36) !36 = distinct !DILexicalBlock(line: 11, column: 0, file: !48, scope: !37) @@ -123,7 +126,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !43 = !DILocation(line: 26, scope: !39) !44 = !DILocalVariable(name: "k", line: 26, scope: !39, file: !2, type: !13) !45 = !DILocation(line: 27, scope: !39) -!46 = !{!16, !17, !20} !47 = !{} !48 = !DIFile(filename: "small.cc", directory: "/Users/manav/R8248330") !49 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index 4179d8c99d6a..15e17b4fd0f1 100644 --- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -1,24 +1,17 @@ -; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB2 +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s ; rdar://8690640 define i32* @t(i32* %x) nounwind { entry: -; ARM-LABEL: t: -; ARM: push -; ARM: mov r7, sp -; ARM: bl _foo -; ARM: bl _foo -; ARM: bl _foo -; ARM: pop {r7, pc} +; CHECK-LABEL: t: +; CHECK: push +; CHECK: mov r7, sp +; CHECK: bl _foo +; CHECK: bl _foo +; CHECK: bl _foo +; CHECK: pop {r7, pc} -; THUMB2-LABEL: t: -; THUMB2: push -; THUMB2: mov r7, sp -; THUMB2: blx _foo -; THUMB2: blx _foo -; THUMB2: blx _foo -; THUMB2: pop %0 = tail call i32* @foo(i32* %x) nounwind %1 = tail call i32* @foo(i32* %0) nounwind %2 = tail call i32* @foo(i32* %1) nounwind diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index d5eed8b6a2c4..8c6cf00cc3a0 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -78,16 +78,16 @@ entry: !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!49} -!0 = distinct !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 4, file: !47, scope: !1, type: !3, variables: !42) +!0 = distinct !DISubprogram(name: "get1", linkageName: "get1", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 4, file: !47, scope: !1, type: !3, variables: !42) !1 = !DIFile(filename: "foo.c", directory: "/tmp/") -!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: 0, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) +!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", isOptimized: true, emissionKind: FullDebug, file: !47, enums: !48, retainedTypes: !48, globals: !41, imports: !48) !3 = !DISubroutineType(types: !4) !4 = !{!5, !5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "_Bool", size: 8, align: 8, encoding: DW_ATE_boolean) -!6 = distinct !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 7, file: !47, scope: !1, type: !3, variables: !43) -!7 = distinct !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 10, file: !47, scope: !1, type: !3, variables: !44) -!8 = distinct !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 13, file: !47, scope: !1, type: !3, variables: !45) -!9 = distinct !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 16, file: !47, scope: !1, type: !3, variables: !46) +!6 = distinct !DISubprogram(name: "get2", linkageName: "get2", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 7, file: !47, scope: !1, type: !3, variables: !43) +!7 = distinct !DISubprogram(name: "get3", linkageName: "get3", line: 10, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 10, file: !47, scope: !1, type: !3, variables: !44) +!8 = distinct !DISubprogram(name: "get4", linkageName: "get4", line: 13, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 13, file: !47, scope: !1, type: !3, variables: !45) +!9 = distinct !DISubprogram(name: "get5", linkageName: "get5", line: 16, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 16, file: !47, scope: !1, type: !3, variables: !46) !10 = !DILocalVariable(name: "a", line: 4, arg: 1, scope: !0, file: !1, type: !5) !11 = !DILocalVariable(name: "b", line: 4, scope: !12, file: !1, type: !5) !12 = distinct !DILexicalBlock(line: 4, column: 0, file: !47, scope: !0) @@ -118,7 +118,6 @@ entry: !37 = !DILocation(line: 13, scope: !26) !38 = !DILocation(line: 16, scope: !9) !39 = !DILocation(line: 16, scope: !29) -!40 = !{!0, !6, !7, !8, !9} !41 = !{!13, !14, !15, !16, !17} !42 = !{!10, !11} !43 = !{!18, !19} diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll index f17884e0fa41..91adba41b1ac 100644 --- a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll +++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll @@ -3,7 +3,7 @@ ; CHECK: _f ; CHECK-NOT: ands ; CHECK: cmp -; CHECK: blxle _g +; CHECK: blle _g define i32 @f(i32 %a, i32 %b) nounwind ssp { entry: diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll index 864e2917b7bb..852038147b26 100644 --- a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -3,7 +3,7 @@ ; CHECK: _f ; CHECK: adds ; CHECK-NOT: cmp -; CHECK: blxeq _h +; CHECK: bleq _h define i32 @f(i32 %a, i32 %b) nounwind ssp { entry: @@ -22,7 +22,7 @@ if.end: ; preds = %if.then, %entry ; CHECK: _g ; CHECK: orrs ; CHECK-NOT: cmp -; CHECK: blxeq _h +; CHECK: bleq _h define i32 @g(i32 %a, i32 %b) nounwind ssp { entry: diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll index ee6d79c39f2f..3c5579acf6ae 100644 --- a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll +++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -38,9 +38,9 @@ bb: bb1: ; CHECK: %bb1 ; CHECK-NOT: umull -; CHECK: blx _Get +; CHECK: bl _Get ; CHECK: umull -; CHECK: blx _foo +; CHECK: bl _foo %tmp5 = load i32, i32* %block_size, align 4 %tmp6 = load i32, i32* %block_count, align 4 %tmp7 = call %struct.FF* @Get() nounwind diff --git a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll index 12cdd04b7bb7..f4b93ca74fc0 100644 --- a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -29,7 +29,7 @@ target triple = "thumbv7-apple-darwin10" @"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4 ; CHECK: _fnmatch -; CHECK: blx _fnmatch1 +; CHECK: bl _fnmatch1 define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { entry: diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 3d82e706862c..4da4fd4c926e 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -73,16 +73,16 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!49} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: 1, file: !47, enums: !48, retainedTypes: !48, subprograms: !40, globals: !41, imports: !48) -!1 = distinct !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !47, scope: !2, type: !3, variables: !42) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang", isOptimized: true, emissionKind: FullDebug, file: !47, enums: !48, retainedTypes: !48, globals: !41, imports: !48) +!1 = distinct !DISubprogram(name: "get1", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 5, file: !47, scope: !2, type: !3, variables: !42) !2 = !DIFile(filename: "ss3.c", directory: "/private/tmp") !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!6 = distinct !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 8, file: !47, scope: !2, type: !3, variables: !43) -!7 = distinct !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !47, scope: !2, type: !3, variables: !44) -!8 = distinct !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 14, file: !47, scope: !2, type: !3, variables: !45) -!9 = distinct !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 17, file: !47, scope: !2, type: !3, variables: !46) +!6 = distinct !DISubprogram(name: "get2", line: 8, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 8, file: !47, scope: !2, type: !3, variables: !43) +!7 = distinct !DISubprogram(name: "get3", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 11, file: !47, scope: !2, type: !3, variables: !44) +!8 = distinct !DISubprogram(name: "get4", line: 14, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 14, file: !47, scope: !2, type: !3, variables: !45) +!9 = distinct !DISubprogram(name: "get5", line: 17, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 17, file: !47, scope: !2, type: !3, variables: !46) !10 = !DILocalVariable(name: "a", line: 5, arg: 1, scope: !1, file: !2, type: !5) !11 = !DILocalVariable(name: "b", line: 5, scope: !12, file: !2, type: !5) !12 = distinct !DILexicalBlock(line: 5, column: 19, file: !47, scope: !1) @@ -110,7 +110,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !37 = !DILocation(line: 14, column: 32, scope: !21) !38 = !DILocation(line: 17, column: 16, scope: !9) !39 = !DILocation(line: 17, column: 32, scope: !29) -!40 = !{!1, !6, !7, !8, !9} !41 = !{!25, !26} !42 = !{!10, !11} !43 = !{!13, !14} diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll index 9163166177c1..e70f973d6a76 100644 --- a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll +++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a9 -jump-table-density=40 | FileCheck %s ; Test that ldmia_ret preserves implicit operands for return values. ; ; This CFG is reduced from a benchmark miscompile. With current diff --git a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll index b47247c5454f..a928543d7cf2 100644 --- a/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll +++ b/test/CodeGen/ARM/2012-09-25-InlineAsmScalarToVectorConv2.ll @@ -2,9 +2,10 @@ ; Check for error message: ; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type +; CHECK: scalar-to-vector conversion failed, possible invalid constraint for vector type define hidden void @f(i32* %corr, i32 %order) nounwind ssp { - tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, <2 x i64>* undef) nounwind, !srcloc !0 + tail call void asm sideeffect "vst1.s32 { ${1:q}, ${2:q} }, [$0]", "r,{q0},{q1}"(i32* %corr, <2 x i64>* undef, i32 %order) nounwind, !srcloc !0 ret void } diff --git a/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll b/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll new file mode 100644 index 000000000000..15e0dad18232 --- /dev/null +++ b/test/CodeGen/ARM/2016-05-01-RegScavengerAssert.ll @@ -0,0 +1,192 @@ +; RUN: llc < %s +; This test has around 4000 bytes of local variables and it also stresses register allocation +; to force a register scavenging. It tests if the stack is treated as "BigStack" and thus +; spill slots are reserved. If not, reg scavenger will assert. + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64" +target triple = "thumbv7--linux-android" + +%struct.r = type { i32 (...)**, [10 x [9 x float]], [10 x [9 x float]], [101 x [9 x float]], [101 x [9 x float]], i32, i32, i32, i32, i32, [8 x [2 x i32]], [432 x float], [432 x i32], [10 x i8*], [10 x i8*], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], [10 x i32], i32, i32, i32, i32, float, float, i32, i32, [9 x float], float*, float } + +define void @foo(%struct.r* %this, float* %srcR, float* %srcC, float* %tempPntsX, float* %tY, float* %ms, float* %sX, float* %sY, i32* dereferenceable(4) %num, float* %tm, i32 %SR, i32 %lev, i8* %tdata, i32 %siW, i32 %pyw, i32 %pyh, i8* %sdata) #0 align 2 { +entry: + %sFV = alloca [49 x float], align 4 + %tFV = alloca [49 x float], align 4 + %TIM = alloca [9 x float], align 4 + %sort_tmp = alloca [432 x float], align 4 + %msDiffs = alloca [432 x float], align 4 + %TM.sroa.0.0.copyload = load float, float* %tm, align 4 + %TM.sroa.8.0.copyload = load float, float* null, align 4 + %TM.sroa.9.0..sroa_idx813 = getelementptr inbounds float, float* %tm, i32 6 + %TM.sroa.9.0.copyload = load float, float* %TM.sroa.9.0..sroa_idx813, align 4 + %TM.sroa.11.0.copyload = load float, float* undef, align 4 + br i1 undef, label %for.body.lr.ph, label %if.then343 + +for.body.lr.ph: ; preds = %entry + %arrayidx8 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 0 + %arrayidx12 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 6 + %arrayidx15 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 4 + %arrayidx20 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 1, i32 %lev, i32 7 + %arrayidx24 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 0 + %arrayidx28 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 6 + %arrayidx32 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 4 + %arrayidx36 = getelementptr inbounds %struct.r, %struct.r* %this, i32 0, i32 2, i32 %lev, i32 7 + %arrayidx84 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 6 + %arrayidx92 = getelementptr inbounds [9 x float], [9 x float]* %TIM, i32 0, i32 7 + %add116 = add nsw i32 %pyh, 15 + br label %for.body + +for.body: ; preds = %for.cond.cleanup40, %for.body.lr.ph + %arrayidx.phi = phi float* [ %sX, %for.body.lr.ph ], [ %arrayidx.inc, %for.cond.cleanup40 ] + %arrayidx4.phi = phi float* [ %sY, %for.body.lr.ph ], [ %arrayidx4.inc, %for.cond.cleanup40 ] + %0 = load float, float* %arrayidx.phi, align 4 + %1 = load float, float* %arrayidx4.phi, align 4 + %2 = load float, float* %arrayidx12, align 4 + %add = fadd fast float 0.000000e+00, %2 + %3 = load float, float* %arrayidx20, align 4 + %add21 = fadd fast float 0.000000e+00, %3 + %mul3.i = fmul fast float %add21, %TM.sroa.8.0.copyload + %add.i = fadd fast float 0.000000e+00, %TM.sroa.11.0.copyload + %add5.i = fadd fast float %add.i, %mul3.i + %conv6.i = fdiv fast float 1.000000e+00, %add5.i + %mul8.i = fmul fast float %add, %TM.sroa.0.0.copyload + %add11.i = fadd fast float %mul8.i, %TM.sroa.9.0.copyload + %add13.i = fadd fast float %add11.i, 0.000000e+00 + %4 = load float, float* %arrayidx24, align 4 + %mul14.i = fmul fast float %add13.i, %4 + %mul25 = fmul fast float %mul14.i, %conv6.i + %add29 = fadd fast float %mul25, 0.000000e+00 + %arrayidx.inc = getelementptr float, float* %arrayidx.phi, i32 1 + %arrayidx4.inc = getelementptr float, float* %arrayidx4.phi, i32 1 + %conv64.1 = sitofp i32 undef to float + %conv64.6 = sitofp i32 undef to float + br label %for.body41 + +for.cond.cleanup40: ; preds = %for.body41 + %call = call fast float undef(%struct.r* nonnull %this, float* undef, i32 49) + br label %for.body + +for.body41: ; preds = %for.cond.cleanup56.for.body41_crit_edge, %for.body + %5 = phi float [ 0.000000e+00, %for.body ], [ %.pre, %for.cond.cleanup56.for.body41_crit_edge ] + %sFVData.0840 = phi float* [ undef, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ] + %dx.0838 = phi i32 [ -3, %for.body ], [ undef, %for.cond.cleanup56.for.body41_crit_edge ] + %conv42 = sitofp i32 %dx.0838 to float + %add43 = fadd fast float %conv42, %add29 + %conv44 = fptosi float %add43 to i32 + %conv48 = sitofp i32 %conv44 to float + %mul49 = fmul fast float %5, %conv48 + %add53 = fadd fast float %mul49, 0.000000e+00 + %conv111 = fptosi float undef to i32 + %cond = select i1 undef, i32 %conv111, i32 -16 + %cond.add116 = select i1 undef, i32 %cond, i32 %add116 + %cmp132 = icmp sgt i32 undef, -16 + %cond137 = select i1 %cmp132, i32 undef, i32 -16 + %cond153 = select i1 undef, i32 %cond137, i32 undef + %add.ptr = getelementptr inbounds i8, i8* %sdata, i32 %cond153 + %mul154 = mul nsw i32 %cond.add116, %siW + %add.ptr155 = getelementptr inbounds i8, i8* %add.ptr, i32 %mul154 + %6 = load i8, i8* %add.ptr155, align 1 + %conv157 = uitofp i8 %6 to float + %incdec.ptr = getelementptr inbounds float, float* %sFVData.0840, i32 1 + store float %conv157, float* %sFVData.0840, align 4 + %7 = load float, float* %arrayidx15, align 4 + %mul65.1 = fmul fast float %7, %conv64.1 + %8 = load float, float* %arrayidx20, align 4 + %add69.1 = fadd fast float %mul65.1, %8 + %conv78.1 = fdiv fast float 1.000000e+00, 0.000000e+00 + %9 = load float, float* undef, align 4 + %mul80.1 = fmul fast float %9, %add53 + %10 = load float, float* undef, align 4 + %mul82.1 = fmul fast float %10, %add69.1 + %add83.1 = fadd fast float %mul82.1, %mul80.1 + %11 = load float, float* %arrayidx84, align 4 + %add85.1 = fadd fast float %add83.1, %11 + %mul86.1 = fmul fast float %add85.1, %conv78.1 + %12 = load float, float* %arrayidx92, align 4 + %add93.1 = fadd fast float 0.000000e+00, %12 + %mul94.1 = fmul fast float %add93.1, %conv78.1 + %13 = load float, float* %arrayidx24, align 4 + %mul98.1 = fmul fast float %mul86.1, %13 + %14 = load float, float* %arrayidx28, align 4 + %add102.1 = fadd fast float %mul98.1, %14 + %15 = load float, float* %arrayidx32, align 4 + %mul106.1 = fmul fast float %mul94.1, %15 + %16 = load float, float* %arrayidx36, align 4 + %add110.1 = fadd fast float %mul106.1, %16 + %conv111.1 = fptosi float %add102.1 to i32 + %conv112.1 = fptosi float %add110.1 to i32 + %cond.1 = select i1 undef, i32 %conv111.1, i32 -16 + %cond.add116.1 = select i1 undef, i32 %cond.1, i32 %add116 + %cond137.1 = select i1 undef, i32 %conv112.1, i32 -16 + %cond153.1 = select i1 undef, i32 %cond137.1, i32 undef + %add.ptr.1 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.1 + %mul154.1 = mul nsw i32 %cond.add116.1, %siW + %add.ptr155.1 = getelementptr inbounds i8, i8* %add.ptr.1, i32 %mul154.1 + %17 = load i8, i8* %add.ptr155.1, align 1 + %conv157.1 = uitofp i8 %17 to float + %incdec.ptr.1 = getelementptr inbounds float, float* %sFVData.0840, i32 2 + store float %conv157.1, float* %incdec.ptr, align 4 + %conv112.2 = fptosi float undef to i32 + %cond137.2 = select i1 undef, i32 %conv112.2, i32 -16 + %cond153.2 = select i1 undef, i32 %cond137.2, i32 undef + %add.ptr.2 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.2 + %add.ptr155.2 = getelementptr inbounds i8, i8* %add.ptr.2, i32 0 + %18 = load i8, i8* %add.ptr155.2, align 1 + %conv157.2 = uitofp i8 %18 to float + %incdec.ptr.2 = getelementptr inbounds float, float* %sFVData.0840, i32 3 + store float %conv157.2, float* %incdec.ptr.1, align 4 + %cmp132.3 = icmp sgt i32 undef, -16 + %cond137.3 = select i1 %cmp132.3, i32 undef, i32 -16 + %cond153.3 = select i1 undef, i32 %cond137.3, i32 undef + %add.ptr.3 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.3 + %add.ptr155.3 = getelementptr inbounds i8, i8* %add.ptr.3, i32 0 + %19 = load i8, i8* %add.ptr155.3, align 1 + %conv157.3 = uitofp i8 %19 to float + store float %conv157.3, float* %incdec.ptr.2, align 4 + %incdec.ptr.5 = getelementptr inbounds float, float* %sFVData.0840, i32 6 + %20 = load float, float* %arrayidx15, align 4 + %mul65.6 = fmul fast float %20, %conv64.6 + %21 = load float, float* %arrayidx20, align 4 + %add69.6 = fadd fast float %mul65.6, %21 + %conv78.6 = fdiv fast float 1.000000e+00, 0.000000e+00 + %22 = load float, float* undef, align 4 + %mul82.6 = fmul fast float %22, %add69.6 + %add83.6 = fadd fast float %mul82.6, 0.000000e+00 + %23 = load float, float* %arrayidx84, align 4 + %add85.6 = fadd fast float %add83.6, %23 + %mul86.6 = fmul fast float %add85.6, %conv78.6 + %24 = load float, float* %arrayidx24, align 4 + %mul98.6 = fmul fast float %mul86.6, %24 + %25 = load float, float* %arrayidx28, align 4 + %add102.6 = fadd fast float %mul98.6, %25 + %conv111.6 = fptosi float %add102.6 to i32 + %conv112.6 = fptosi float undef to i32 + %cond.6 = select i1 undef, i32 %conv111.6, i32 -16 + %cond.add116.6 = select i1 undef, i32 %cond.6, i32 %add116 + %cmp132.6 = icmp sgt i32 %conv112.6, -16 + %cond137.6 = select i1 %cmp132.6, i32 %conv112.6, i32 -16 + %cond153.6 = select i1 undef, i32 %cond137.6, i32 undef + %add.ptr.6 = getelementptr inbounds i8, i8* %sdata, i32 %cond153.6 + %mul154.6 = mul nsw i32 %cond.add116.6, %siW + %add.ptr155.6 = getelementptr inbounds i8, i8* %add.ptr.6, i32 %mul154.6 + %26 = load i8, i8* %add.ptr155.6, align 1 + %conv157.6 = uitofp i8 %26 to float + store float %conv157.6, float* %incdec.ptr.5, align 4 + %exitcond874 = icmp eq i32 %dx.0838, 3 + br i1 %exitcond874, label %for.cond.cleanup40, label %for.cond.cleanup56.for.body41_crit_edge + +for.cond.cleanup56.for.body41_crit_edge: ; preds = %for.body41 + %.pre = load float, float* %arrayidx8, align 4 + br label %for.body41 + +if.then343: ; preds = %entry + ret void +} + +attributes #0 = { sspstrong uwtable "no-frame-pointer-elim"="false" "target-cpu"="cortex-a7" } + +!1 = !{!2, !2, i64 0} +!2 = !{!"float", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{!3, !3, i64 0} diff --git a/test/CodeGen/ARM/ARMLoadStoreDBG.mir b/test/CodeGen/ARM/ARMLoadStoreDBG.mir new file mode 100644 index 000000000000..b4f19ecc5610 --- /dev/null +++ b/test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -0,0 +1,164 @@ +# RUN: llc -mtriple thumbv7 -verify-machineinstrs -run-pass arm-ldst-opt %s -o - | FileCheck %s +--- | + ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' + target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv7" + + %struct.s = type opaque + + ; Function Attrs: nounwind + define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { + entry: + tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28 + tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 + %cmp = icmp ult i32 %n, 4, !dbg !29 + br i1 %cmp, label %return, label %if.end, !dbg !31 + + if.end: ; preds = %entry + tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 + br label %return, !dbg !33 + + return: ; preds = %if.end, %entry + %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] + ret i32 %retval.0, !dbg !34 + } + + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 + + ; Function Attrs: nounwind readnone + declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 + + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #2 = { nounwind readnone } + attributes #3 = { nounwind } + + !llvm.dbg.cu = !{!0} + !llvm.module.flags = !{!22, !23, !24, !25} + !llvm.ident = !{!26} + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) + !1 = !DIFile(filename: "", directory: "/Users/compnerd/Source/llvm") + !2 = !{} + !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17) + !5 = !DISubroutineType(types: !6) + !6 = !{!7, !8, !11, !12, !16} + !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) + !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32) + !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10) + !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl) + !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) + !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32) + !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) + !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15) + !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) + !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11) + !17 = !{!18, !19, !20, !21} + !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8) + !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11) + !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12) + !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16) + !22 = !{i32 2, !"Dwarf Version", i32 4} + !23 = !{i32 2, !"Debug Info Version", i32 3} + !24 = !{i32 1, !"wchar_size", i32 4} + !25 = !{i32 1, !"min_enum_size", i32 4} + !26 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} + !27 = !DIExpression() + !28 = !DILocation(line: 9, scope: !4) + !29 = !DILocation(line: 10, scope: !30) + !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10) + !31 = !DILocation(line: 10, scope: !4) + !32 = !DILocation(line: 13, scope: !4) + !33 = !DILocation(line: 14, scope: !4) + !34 = !DILocation(line: 15, scope: !4) + +... +--- +name: f +alignment: 1 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: true +isSSA: false +tracksRegLiveness: true +tracksSubRegLiveness: false +liveins: + - { reg: '%r0' } + - { reg: '%r1' } + - { reg: '%r2' } + - { reg: '%r3' } +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', + '%d11_d12_d13_d14' ] +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 8 + offsetAdjustment: 0 + maxAlignment: 4 + adjustsStack: true + hasCalls: true + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +stack: + - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } + - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } +body: | + bb.0.entry: + successors: %bb.1, %bb.2.if.end + liveins: %r0, %r1, %r2, %r3, %lr, %r7 + + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 + t2Bcc %bb.2.if.end, 2, killed %cpsr + + bb.1: + liveins: %lr, %r7 + + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + %r0 = t2MOVi -1, 14, _, _ + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + tBX_RET 14, _, implicit %r0, debug-location !34 + + bb.2.if.end: + liveins: %r0, %r2, %r3, %r7, %lr + + %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr + frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 + frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 + frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8 + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 + DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 + %r1 = COPY killed %r2, debug-location !32 + DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 + %r2 = COPY killed %r3, debug-location !32 + tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 + %r0 = t2MOVi 0, 14, _, _ + %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr + tBX_RET 14, _, implicit %r0, debug-location !34 +# Verify that the DBG_VALUE is ignored. +# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 + +... diff --git a/test/CodeGen/ARM/Windows/builtin_longjmp.ll b/test/CodeGen/ARM/Windows/builtin_longjmp.ll new file mode 100644 index 000000000000..52b6f301bb77 --- /dev/null +++ b/test/CodeGen/ARM/Windows/builtin_longjmp.ll @@ -0,0 +1,15 @@ +; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s + +declare void @llvm.eh.sjlj.longjmp(i8*) + +define arm_aapcs_vfpcc void @test___builtin_longjump(i8* %b) { +entry: + tail call void @llvm.eh.sjlj.longjmp(i8* %b) + unreachable +} + +; CHECK: push.w {r11, lr} +; CHECK: ldr.w r11, [r0] +; CHECK: ldr.w sp, [r0, #8] +; CHECK: ldr.w pc, [r0, #4] + diff --git a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll index a314259e499e..d303e9da8604 100644 --- a/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll +++ b/test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -filetype obj -o - %s \ +; RUN: llc -mtriple thumbv7--windows-itanium -code-model large -verify-machineinstrs -filetype obj -o - %s \ ; RUN: | llvm-objdump -no-show-raw-insn -d - | FileCheck %s ; ModuleID = 'reduced.c' diff --git a/test/CodeGen/ARM/Windows/chkstk.ll b/test/CodeGen/ARM/Windows/chkstk.ll index cb787e14b5ba..330c1f458500 100644 --- a/test/CodeGen/ARM/Windows/chkstk.ll +++ b/test/CodeGen/ARM/Windows/chkstk.ll @@ -1,7 +1,7 @@ -; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 %s -o - \ +; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -verify-machineinstrs %s -o - \ ; RUN: | FileCheck -check-prefix CHECK-DEFAULT-CODE-MODEL %s -; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -code-model=large %s -o - \ +; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -code-model=large -verify-machineinstrs %s -o - \ ; RUN: | FileCheck -check-prefix CHECK-LARGE-CODE-MODEL %s define arm_aapcs_vfpcc void @check_watermark() { diff --git a/test/CodeGen/ARM/Windows/dbzchk.ll b/test/CodeGen/ARM/Windows/dbzchk.ll new file mode 100644 index 000000000000..599a7cf094c4 --- /dev/null +++ b/test/CodeGen/ARM/Windows/dbzchk.ll @@ -0,0 +1,192 @@ +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-DIV + +; int f(int n, int d) { +; if (n / d) +; return 1; +; return 0; +; } + +define arm_aapcs_vfpcc i32 @f(i32 %n, i32 %d) { +entry: + %retval = alloca i32, align 4 + %n.addr = alloca i32, align 4 + %d.addr = alloca i32, align 4 + store i32 %n, i32* %n.addr, align 4 + store i32 %d, i32* %d.addr, align 4 + %0 = load i32, i32* %n.addr, align 4 + %1 = load i32, i32* %d.addr, align 4 + %div = sdiv i32 %0, %1 + %tobool = icmp ne i32 %div, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: + store i32 1, i32* %retval, align 4 + br label %return + +if.end: + store i32 0, i32* %retval, align 4 + br label %return + +return: + %2 = load i32, i32* %retval, align 4 + ret i32 %2 +} + +; CHECK-DIV-DAG: BB#0 +; CHECK-DIV-DAG: Successors according to CFG: BB#5({{.*}}) BB#4 +; CHECK-DIV-DAG: BB#1 +; CHECK-DIV-DAG: Successors according to CFG: BB#3 +; CHECK-DIV-DAG: BB#2 +; CHECK-DIV-DAG: Successors according to CFG: BB#3 +; CHECK-DIV-DAG: BB#3 +; CHECK-DIV-DAG: BB#4 +; CHECK-DIV-DAG: Successors according to CFG: BB#1({{.*}}) BB#2 +; CHECK-DIV-DAG: BB#5 + +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-MOD + +; int r; +; int g(int l, int m) { +; if (m <= 0) +; return 0; +; return (r = l % m); +; } + +@r = common global i32 0, align 4 + +define arm_aapcs_vfpcc i32 @g(i32 %l, i32 %m) { +entry: + %cmp = icmp eq i32 %m, 0 + br i1 %cmp, label %return, label %if.end + +if.end: + %rem = urem i32 %l, %m + store i32 %rem, i32* @r, align 4 + br label %return + +return: + %retval.0 = phi i32 [ %rem, %if.end ], [ 0, %entry ] + ret i32 %retval.0 +} + +; CHECK-MOD-DAG: BB#0 +; CHECK-MOD-DAG: Successors according to CFG: BB#2({{.*}}) BB#1 +; CHECK-MOD-DAG: BB#1 +; CHECK-MOD-DAG: Successors according to CFG: BB#4({{.*}}) BB#3 +; CHECK-MOD-DAG: BB#2 +; CHECK-MOD-DAG: BB#3 +; CHECK-MOD-DAG: Successors according to CFG: BB#2 +; CHECK-MOD-DAG: BB#4 + +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o /dev/null %s 2>&1 | FileCheck %s -check-prefix CHECK-CFG +; RUN: llc -mtriple thumbv7--windows-itanium -print-machineinstrs=expand-isel-pseudos -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-CFG-ASM + +; unsigned c; +; extern unsigned long g(void); +; int f(unsigned u, signed char b) { +; if (b) +; c = g() % u; +; return c; +; } + +@c = common global i32 0, align 4 + +declare arm_aapcs_vfpcc i32 @i() + +define arm_aapcs_vfpcc i32 @h(i32 %u, i8 signext %b) #0 { +entry: + %tobool = icmp eq i8 %b, 0 + br i1 %tobool, label %entry.if.end_crit_edge, label %if.then + +entry.if.end_crit_edge: + %.pre = load i32, i32* @c, align 4 + br label %if.end + +if.then: + %call = tail call arm_aapcs_vfpcc i32 @i() + %rem = urem i32 %call, %u + store i32 %rem, i32* @c, align 4 + br label %if.end + +if.end: + %0 = phi i32 [ %.pre, %entry.if.end_crit_edge ], [ %rem, %if.then ] + ret i32 %0 +} + +attributes #0 = { optsize } + +; CHECK-CFG-DAG: BB#0 +; CHECK-CFG-DAG: t2Bcc +; CHECK-CFG-DAG: t2B + +; CHECK-CFG-DAG: BB#1 +; CHECK-CFG-DAG: t2B + +; CHECK-CFG-DAG: BB#2 +; CHECK-CFG-DAG: tCBZ %vreg{{[0-9]}}, +; CHECK-CFG-DAG: t2B + +; CHECK-CFG-DAG: BB#4 + +; CHECK-CFG-DAG: BB#3 +; CHECK-CFG-DAG: tBX_RET + +; CHECK-CFG-DAG: BB#5 +; CHECK-CFG-DAG: t2UDF 249 + +; CHECK-CFG-ASM-LABEL: h: +; CHECK-CFG-ASM: cbz r{{[0-9]}}, .LBB2_2 +; CHECK-CFG-ASM: b .LBB2_4 +; CHECK-CFG-ASM-LABEL: .LBB2_2: +; CHECK-CFG-ASM-NEXT: udf.w #249 +; CHECK-CFG-ASM-LABEL: .LBB2_4: +; CHECK-CFG-ASM: bl __rt_udiv +; CHECK-CFG-ASM: pop.w {{{.*}}, r11, pc} + +; RUN: llc -O0 -mtriple thumbv7--windows-itanium -verify-machineinstrs -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-WIN__DBZCHK + +; long k(void); +; int l(void); +; int j(int i) { +; if (l() == -1) +; return 0; +; return k() % i; +; } + +declare arm_aapcs_vfpcc i32 @k() +declare arm_aapcs_vfpcc i32 @l() + +define arm_aapcs_vfpcc i32 @j(i32 %i) { +entry: + %retval = alloca i32, align 4 + %i.addr = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + %call = call arm_aapcs_vfpcc i32 @l() + %cmp = icmp eq i32 %call, -1 + br i1 %cmp, label %if.then, label %if.end + +if.then: + store i32 0, i32* %retval, align 4 + br label %return + +if.end: + %call1 = call arm_aapcs_vfpcc i32 @k() + %0 = load i32, i32* %i.addr, align 4 + %rem = srem i32 %call1, %0 + store i32 %rem, i32* %retval, align 4 + br label %return + +return: + %1 = load i32, i32* %retval, align 4 + ret i32 %1 +} + +; CHECK-WIN__DBZCHK-LABEL: j: +; CHECK-WIN__DBZCHK: cbz r{{[0-7]}}, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r8, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r9, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r10, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz r11, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz ip, .LBB +; CHECK-WIN__DBZCHK-NOT: cbz lr, .LBB + diff --git a/test/CodeGen/ARM/Windows/division.ll b/test/CodeGen/ARM/Windows/division.ll index b3ef9c6d278b..f4704ea7ff4b 100644 --- a/test/CodeGen/ARM/Windows/division.ll +++ b/test/CodeGen/ARM/Windows/division.ll @@ -7,8 +7,11 @@ entry: ret i32 %div } -; CHECK-LABEL: sdiv32 -; CHECK: b __rt_sdiv +; CHECK-LABEL: sdiv32: +; CHECK: cbz r0 +; CHECK: b +; CHECK: udf.w #249 +; CHECK: bl __rt_sdiv define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) { entry: @@ -17,7 +20,10 @@ entry: } ; CHECK-LABEL: udiv32: -; CHECK: b __rt_udiv +; CHECK: cbz r0 +; CHECK: b +; CHECK: udf.w #249 +; CHECK: bl __rt_udiv define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) { entry: @@ -25,7 +31,11 @@ entry: ret i64 %div } -; CHECK-LABEL: sdiv64 +; CHECK-LABEL: sdiv64: +; CHECK: orr.w r4, r0, r1 +; CHECK-NEXT: cbz r4 +; CHECK: b +; CHECK: udf.w #249 ; CHECK: bl __rt_sdiv64 define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) { @@ -35,4 +45,9 @@ entry: } ; CHECK-LABEL: udiv64: +; CHECK: orr.w r4, r0, r1 +; CHECK-NEXT: cbz r4 +; CHECK: b +; CHECK: udf.w #249 ; CHECK: bl __rt_udiv64 + diff --git a/test/CodeGen/ARM/Windows/dllexport.ll b/test/CodeGen/ARM/Windows/dllexport.ll new file mode 100644 index 000000000000..27496208862e --- /dev/null +++ b/test/CodeGen/ARM/Windows/dllexport.ll @@ -0,0 +1,75 @@ +; RUN: llc -mtriple thumbv7--windows-itanium -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-GNU +; RUN: llc -mtriple thumbv7--windows-gnu -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-GNU +; RUN: llc -mtriple thumbv7--windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefix CHECK -check-prefix CHECK-MSVC + +define void @f() { + ret void +} + +define dllexport void @g() { + ret void +} + +define dllexport void @h() unnamed_addr { + ret void +} + +declare dllexport void @i() + +define linkonce_odr dllexport void @j() { + ret void +} + +define linkonce_odr dllexport void @k() alwaysinline { + ret void +} + +define weak_odr dllexport void @l() { + ret void +} + +@m = dllexport global i32 0, align 4 +@n = dllexport unnamed_addr constant i32 0 +@o = common dllexport global i32 0, align 4 +@p = weak_odr dllexport global i32 0, align 4 +@q = weak_odr dllexport unnamed_addr constant i32 0 + +@r = dllexport alias void (), void () * @f +@s = dllexport alias void (), void () * @g +@t = dllexport alias void (), void () * @f +@u = weak_odr dllexport alias void (), void () * @g + +; CHECK: .section .drectve +; CHECK-GNU-NOT: -export:f +; CHECK-GNU: -export:g +; CHECK-GNU-SAME: -export:h +; CHECK-GNU-NOT: -export:i +; CHECK-GNU-SAME: -export:j +; CHECK-GNU-SAME: -export:k +; CHECK-GNU-SAME: -export:l +; CHECK-GNU-SAME: -export:m,data +; CHECK-GNU-SAME: -export:n,data +; CHECK-GNU-SAME: -export:o,data +; CHECK-GNU-SAME: -export:p,data +; CHECK-GNU-SAME: -export:q,data +; CHECK-GNU-SAME: -export:r +; CHECK-GNU-SAME: -export:s +; CHECK-GNU-SAME: -export:t +; CHECK-GNU-SAME: -export:u +; CHECK-MSVC-NOT: /EXPORT:f +; CHECK-MSVC: /EXPORT:g +; CHECK-MSVC-SAME: /EXPORT:h +; CHECK-MSVC-NOT: /EXPORT:i +; CHECK-MSVC-SAME: /EXPORT:j +; CHECK-MSVC-SAME: /EXPORT:k +; CHECK-MSVC-SAME: /EXPORT:l +; CHECK-MSVC-SAME: /EXPORT:m,DATA +; CHECK-MSVC-SAME: /EXPORT:n,DATA +; CHECK-MSVC-SAME: /EXPORT:o,DATA +; CHECK-MSVC-SAME: /EXPORT:p,DATA +; CHECK-MSVC-SAME: /EXPORT:q,DATA +; CHECK-MSVC-SAME: /EXPORT:r +; CHECK-MSVC-SAME: /EXPORT:s +; CHECK-MSVC-SAME: /EXPORT:t +; CHECK-MSVC-SAME: /EXPORT:u + diff --git a/test/CodeGen/ARM/Windows/long-calls.ll b/test/CodeGen/ARM/Windows/long-calls.ll index 4e5bdce146f0..29e6f783ae5f 100644 --- a/test/CodeGen/ARM/Windows/long-calls.ll +++ b/test/CodeGen/ARM/Windows/long-calls.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -mattr=+long-calls -o - %s \ +; RUN: llc -mtriple=thumbv7-windows -mcpu=cortex-a9 -relocation-model pic -mattr=+long-calls -o - %s \ ; RUN: | FileCheck %s declare arm_aapcs_vfpcc void @callee() @@ -12,7 +12,7 @@ entry: ; CHECK-LABEL: caller ; CHECK: ldr [[REG:r[0-9]+]], [[CPI:LCPI[_0-9]+]] ; CHECK: bx [[REG]] -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK: [[CPI]]: ; CHECK: .long callee diff --git a/test/CodeGen/ARM/Windows/no-aeabi.ll b/test/CodeGen/ARM/Windows/no-aeabi.ll index 3971b9ccf580..a4103b0a676e 100644 --- a/test/CodeGen/ARM/Windows/no-aeabi.ll +++ b/test/CodeGen/ARM/Windows/no-aeabi.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -o - %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-windows-itanium -mcpu=cortex-a9 -verify-machineinstrs -o - %s | FileCheck %s declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/CodeGen/ARM/Windows/overflow.ll b/test/CodeGen/ARM/Windows/overflow.ll deleted file mode 100644 index 5f74f25ac224..000000000000 --- a/test/CodeGen/ARM/Windows/overflow.ll +++ /dev/null @@ -1,77 +0,0 @@ -; RUN: llc -mtriple thumbv7-windows-gnu -filetype asm -o - %s - -define i32 @divsoverflow32(i32 %a, i32 %b) { - %1 = alloca i32, align 4 - %2 = alloca i32, align 4 - %3 = load i32, i32* %1, align 4 - %4 = load i32, i32* %2, align 4 - %5 = sub nsw i32 0, %4 - %6 = sdiv i32 -2147483647, %3 - %7 = icmp sgt i32 %5, %6 - br i1 %7, label %8, label %9 - call void (...) @abort_simpl32() - unreachable - %10 = load i32, i32* %1, align 4 - %11 = load i32, i32* %2, align 4 - %12 = mul nsw i32 %10, %11 - ret i32 %12 -} - -declare void @abort_simpl32(...) - -define i64 @divsoverflow64(i64 %a, i64 %b) { - %1 = alloca i64, align 8 - %2 = alloca i64, align 8 - %3 = load i64, i64* %1, align 8 - %4 = load i64, i64* %2, align 8 - %5 = sub nsw i64 0, %4 - %6 = sdiv i64 -9223372036854775808, %3 - %7 = icmp sgt i64 %5, %6 - br i1 %7, label %8, label %9 - call void (...) @abort_simpl64() - unreachable - %10 = load i64, i64* %1, align 8 - %11 = load i64, i64* %2, align 8 - %12 = mul nsw i64 %10, %11 - ret i64 %12 -} - -declare void @abort_simpl64(...) - -define i32 @divuoverflow32(i32 %a, i32 %b) { - %1 = alloca i32, align 4 - %2 = alloca i32, align 4 - %3 = load i32, i32* %1, align 4 - %4 = load i32, i32* %2, align 4 - %5 = sub nsw i32 0, %4 - %6 = udiv i32 4294967296, %3 - %7 = icmp sgt i32 %5, %6 - br i1 %7, label %8, label %9 - call void (...) @abort_uimpl32() - unreachable - %10 = load i32, i32* %1, align 4 - %11 = load i32, i32* %2, align 4 - %12 = mul nsw i32 %10, %11 - ret i32 %12 -} - -declare void @abort_uimpl32(...) - -define i64 @divuoverflow64(i64 %a, i64 %b) { - %1 = alloca i64, align 8 - %2 = alloca i64, align 8 - %3 = load i64, i64* %1, align 8 - %4 = load i64, i64* %2, align 8 - %5 = sub nsw i64 0, %4 - %6 = udiv i64 18446744073709551616, %3 - %7 = icmp sgt i64 %5, %6 - br i1 %7, label %8, label %9 - call void (...) @abort_uimpl64() - unreachable - %10 = load i64, i64* %1, align 8 - %11 = load i64, i64* %2, align 8 - %12 = mul nsw i64 %10, %11 - ret i64 %12 -} - -declare void @abort_uimpl64(...) diff --git a/test/CodeGen/ARM/Windows/tls.ll b/test/CodeGen/ARM/Windows/tls.ll new file mode 100644 index 000000000000..689f4e291872 --- /dev/null +++ b/test/CodeGen/ARM/Windows/tls.ll @@ -0,0 +1,157 @@ +; RUN: llc -mtriple thumbv7--windows-itanium %s -o - | FileCheck %s + +@i = thread_local global i32 0 +@j = external thread_local global i32 +@k = internal thread_local global i32 0 +@l = hidden thread_local global i32 0 +@m = external hidden thread_local global i32 +@n = thread_local global i16 0 +@o = thread_local global i8 0 + +define i32 @f() { + %1 = load i32, i32* @i + ret i32 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK-NEXT: .long i(SECREL32) + +define i32 @e() { + %1 = load i32, i32* @j + ret i32 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK-NEXT: .long j(SECREL32) + +define i32 @d() { + %1 = load i32, i32* @k + ret i32 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK-NEXT: .long k(SECREL32) + +define i32 @c() { + %1 = load i32, i32* @l + ret i32 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK-NEXT: .long l(SECREL32) + +define i32 @b() { + %1 = load i32, i32* @m + ret i32 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK: .long m(SECREL32) + +define i16 @a() { + %1 = load i16, i16* @n + ret i16 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldrh r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK: .long n(SECREL32) + +define i8 @Z() { + %1 = load i8, i8* @o + ret i8 %1 +} + +; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2 + +; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index +; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index +; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]] + +; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44] +; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2] + +; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:LCPI[0-9]+_[0-9]+]] + +; CHECK-NEXT: ldrb r0, {{\[}}[[TLS]], [[SLOT]]] + +; CHECK: [[CPI]]: +; CHECK-NEXT: .long o(SECREL32) + diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll index 9589e72df2f5..74525909148d 100644 --- a/test/CodeGen/ARM/align.ll +++ b/test/CodeGen/ARM/align.ll @@ -8,33 +8,33 @@ ; no alignment @c = global i16 2 -;ELF: .align 1 +;ELF: .p2align 1 ;ELF: c: -;DARWIN: .align 1 +;DARWIN: .p2align 1 ;DARWIN: _c: @d = global i32 3 -;ELF: .align 2 +;ELF: .p2align 2 ;ELF: d: -;DARWIN: .align 2 +;DARWIN: .p2align 2 ;DARWIN: _d: @e = global i64 4 -;ELF: .align 3 +;ELF: .p2align 3 ;ELF: e -;DARWIN: .align 3 +;DARWIN: .p2align 3 ;DARWIN: _e: @f = global float 5.0 -;ELF: .align 2 +;ELF: .p2align 2 ;ELF: f: -;DARWIN: .align 2 +;DARWIN: .p2align 2 ;DARWIN: _f: @g = global double 6.0 -;ELF: .align 3 +;ELF: .p2align 3 ;ELF: g: -;DARWIN: .align 3 +;DARWIN: .p2align 3 ;DARWIN: _g: @bar = common global [75 x i8] zeroinitializer, align 128 diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 04eae8f9afec..151cc1b12ed2 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -49,7 +49,7 @@ tailrecurse.switch: ; preds = %tailrecurse ; V8-NEXT: beq ; V8-NEXT: %tailrecurse.switch ; V8: cmp -; V8-NEXT: bne +; V8-NEXT: beq ; V8-NEXT: b ; The trailing space in the last line checks that the branch is unconditional switch i32 %and, label %sw.epilog [ diff --git a/test/CodeGen/ARM/arm-eabi.ll b/test/CodeGen/ARM/arm-eabi.ll index d1e7a947553f..898055dd1092 100644 --- a/test/CodeGen/ARM/arm-eabi.ll +++ b/test/CodeGen/ARM/arm-eabi.ll @@ -3,21 +3,29 @@ ; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI +; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=gnu -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=4 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-eabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-eabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-androideabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-gnueabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI ; RUN: llc < %s -mtriple=arm-none-gnueabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-musleabi -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI +; RUN: llc < %s -mtriple=arm-none-musleabihf -meabi=5 -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI %struct.my_s = type { [18 x i32] } diff --git a/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll b/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll new file mode 100644 index 000000000000..620cb6356411 --- /dev/null +++ b/test/CodeGen/ARM/arm-interleaved-accesses-extract-user.ll @@ -0,0 +1,86 @@ +; RUN: opt < %s -mtriple=arm-eabi -mattr=+neon -interleaved-access -S | FileCheck %s + +; CHECK-LABEL: @extract_user_basic( +; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 1 +define void @extract_user_basic(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + br i1 %C, label %if.then, label %if.merge + +if.then: + %E = extractelement <8 x i32> %L, i32 2 + br label %if.merge + +if.merge: + ret void +} + +; CHECK-LABEL: @extract_user_multi( +; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +; CHECK: %[[R:.+]] = extractvalue { <4 x i32>, <4 x i32> } %vldN, 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 0 +; CHECK: extractelement <4 x i32> %[[R]], i64 1 +define void @extract_user_multi(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + br i1 %C, label %if.then, label %if.merge + +if.then: + %E1 = extractelement <8 x i32> %L, i32 0 + br label %if.merge + +if.merge: + %E2 = extractelement <8 x i32> %L, i32 2 + ret void +} + +; CHECK-LABEL: @extract_user_multi_no_dom( +; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +define void @extract_user_multi_no_dom(<8 x i32>* %A, i1 %C) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %E1 = extractelement <8 x i32> %L, i32 0 + br i1 %C, label %if.then, label %if.merge + +if.then: + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E2 = extractelement <8 x i32> %L, i32 2 + br label %if.merge + +if.merge: + ret void +} + +; CHECK-LABEL: @extract_user_wrong_const_index( +; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +define void @extract_user_wrong_const_index(<8 x i32>* %A) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 1 + ret void +} + +; CHECK-LABEL: @extract_user_undef_index( +; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +define void @extract_user_undef_index(<8 x i32>* %A) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 undef + ret void +} + +; CHECK-LABEL: @extract_user_var_index( +; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8 +define void @extract_user_var_index(<8 x i32>* %A, i32 %I) { +entry: + %L = load <8 x i32>, <8 x i32>* %A, align 8 + %S = shufflevector <8 x i32> %L, <8 x i32> undef, <4 x i32> + %E = extractelement <8 x i32> %L, i32 %I + ret void +} diff --git a/test/CodeGen/ARM/arm-interleaved-accesses.ll b/test/CodeGen/ARM/arm-interleaved-accesses.ll index 002e71f6d9b8..6f3d537176c0 100644 --- a/test/CodeGen/ARM/arm-interleaved-accesses.ll +++ b/test/CodeGen/ARM/arm-interleaved-accesses.ll @@ -304,3 +304,15 @@ define void @store_illegal_factor2(<3 x float>* %p, <3 x float> %v) nounwind { store <3 x float> %tmp1, <3 x float>* %p, align 16 ret void } + +; NEON-LABEL: load_factor2_with_extract_user: +; NEON: vld2.32 {d16, d17, d18, d19}, [r0:64] +; NEON: vmov.32 r0, d16[1] +; NONEON-LABEL: load_factor2_with_extract_user: +; NONEON-NOT: vld2 +define i32 @load_factor2_with_extract_user(<8 x i32>* %a) { + %1 = load <8 x i32>, <8 x i32>* %a, align 8 + %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> + %3 = extractelement <8 x i32> %1, i32 2 + ret i32 %3 +} diff --git a/test/CodeGen/ARM/arm-shrink-wrapping.ll b/test/CodeGen/ARM/arm-shrink-wrapping.ll index 9375df4b15cb..cb608fc18d95 100644 --- a/test/CodeGen/ARM/arm-shrink-wrapping.ll +++ b/test/CodeGen/ARM/arm-shrink-wrapping.ll @@ -629,7 +629,7 @@ end: declare double @llvm.pow.f64(double, double) ; This function needs to spill floating point registers to -; exerce the path where we were deferencing the end iterator +; exercise the path where we were dereferencing the end iterator ; to access debug info location while inserting the spill code ; during PEI with shrink-wrapping enable. ; CHECK-LABEL: debug_info: @@ -677,7 +677,7 @@ bb13: ; preds = %bb3, %bb !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3} -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "LLVM", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !2, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "LLVM", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "a.cpp", directory: "b") !2 = !{} !3 = !{i32 2, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 573cd45c0825..8841483c97a4 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -172,31 +172,31 @@ define i64 @test6(i64* %ptr, i64 %val) { define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { ; CHECK-LABEL: test7: ; CHECK-DAG: mov [[VAL1LO:r[0-9]+]], r1 -; CHECK-DAG: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK-LE-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG1]], [[VAL1LO]] -; CHECK-LE-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG2]], r2 -; CHECK-BE-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG2]], r2 -; CHECK-BE-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG1]], r1 +; CHECK-LE-DAG: eor [[MISMATCH_LO:.*]], [[REG1]], [[VAL1LO]] +; CHECK-LE-DAG: eor [[MISMATCH_HI:.*]], [[REG2]], r2 +; CHECK-BE-DAG: eor [[MISMATCH_LO:.*]], [[REG2]], r2 +; CHECK-BE-DAG: eor [[MISMATCH_HI:.*]], [[REG1]], r1 ; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]] ; CHECK: bne +; CHECK-DAG: dmb {{ish$}} ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} ; CHECK: cmp -; CHECK: bne +; CHECK: beq ; CHECK: dmb {{ish$}} ; CHECK-THUMB-LABEL: test7: -; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2 ; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3 ; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG1]], r2 ; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG2]], r3 -; CHECK-THUMB-LE: orrs [[MISMATCH_HI]], [[MISMATCH_LO]] +; CHECK-THUMB-LE: orrs.w {{.*}}, [[MISMATCH_LO]], [[MISMATCH_HI]] ; CHECK-THUMB: bne +; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} ; CHECK-THUMB: cmp -; CHECK-THUMB: bne +; CHECK-THUMB: beq ; CHECK-THUMB: dmb {{ish$}} %pair = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst seq_cst @@ -251,21 +251,18 @@ define i64 @test10(i64* %ptr, i64 %val) { ; CHECK-LABEL: test10: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2 -; CHECK-LE: cmp [[REG1]], r1 -; CHECK-BE: cmp [[REG2]], r2 -; CHECK: movwls [[CARRY_LO]], #1 -; CHECK-LE: cmp [[REG2]], r2 -; CHECK-BE: cmp [[REG1]], r1 -; CHECK: movwle [[CARRY_HI]], #1 -; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK: cmp [[CARRY_HI]], #0 +; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]] +; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]] +; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]] +; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]] +; CHECK: mov [[CMP:[a-z0-9]+]], #0 +; CHECK: movwge [[CMP]], #1 +; CHECK: cmp [[CMP]], #0 ; CHECK: movne [[OUT_HI]], [[REG2]] ; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1 ; CHECK: movne [[OUT_LO]], [[REG1]] -; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK: cmp ; CHECK: bne ; CHECK: dmb {{ish$}} @@ -273,21 +270,18 @@ define i64 @test10(i64* %ptr, i64 %val) { ; CHECK-THUMB-LABEL: test10: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] -; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+|lr]], #0 -; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+|lr]], #0 -; CHECK-THUMB-LE: cmp [[REG1]], r2 -; CHECK-THUMB-BE: cmp [[REG2]], r3 -; CHECK-THUMB: movls.w [[CARRY_LO]], #1 -; CHECK-THUMB-LE: cmp [[REG2]], r3 -; CHECK-THUMB-BE: cmp [[REG1]], r2 -; CHECK-THUMB: movle [[CARRY_HI]], #1 -; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 -; CHECK-THUMB: cmp [[CARRY_HI]], #0 -; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0 +; CHECK-THUMB: movge.w [[CMP]], #1 +; CHECK-THUMB: cmp.w [[CMP]], #0 +; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 ; CHECK-THUMB: movne [[OUT_HI]], [[REG2]] ; CHECK-THUMB: movne [[OUT_LO]], [[REG1]] -; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK-THUMB: cmp ; CHECK-THUMB: bne ; CHECK-THUMB: dmb {{ish$}} @@ -300,21 +294,18 @@ define i64 @test11(i64* %ptr, i64 %val) { ; CHECK-LABEL: test11: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2 -; CHECK-LE: cmp [[REG1]], r1 -; CHECK-BE: cmp [[REG2]], r2 -; CHECK: movwls [[CARRY_LO]], #1 -; CHECK-LE: cmp [[REG2]], r2 -; CHECK-BE: cmp [[REG1]], r1 -; CHECK: movwls [[CARRY_HI]], #1 -; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK: cmp [[CARRY_HI]], #0 +; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]] +; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]] +; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]] +; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]] +; CHECK: mov [[CMP:[a-z0-9]+]], #0 +; CHECK: movwhs [[CMP]], #1 +; CHECK: cmp [[CMP]], #0 ; CHECK: movne [[OUT_HI]], [[REG2]] ; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1 ; CHECK: movne [[OUT_LO]], [[REG1]] -; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK: cmp ; CHECK: bne ; CHECK: dmb {{ish$}} @@ -322,21 +313,18 @@ define i64 @test11(i64* %ptr, i64 %val) { ; CHECK-THUMB-LABEL: test11: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] -; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0 -; CHECK-THUMB-LE: cmp [[REG1]], r2 -; CHECK-THUMB-BE: cmp [[REG2]], r3 -; CHECK-THUMB: movls.w [[CARRY_LO]], #1 -; CHECK-THUMB-LE: cmp [[REG2]], r3 -; CHECK-THUMB-BE: cmp [[REG1]], r2 -; CHECK-THUMB: movls [[CARRY_HI]], #1 -; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 -; CHECK-THUMB: cmp [[CARRY_HI]], #0 -; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0 +; CHECK-THUMB: movhs.w [[CMP]], #1 +; CHECK-THUMB: cmp.w [[CMP]], #0 +; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 ; CHECK-THUMB: movne [[OUT_HI]], [[REG2]] ; CHECK-THUMB: movne [[OUT_LO]], [[REG1]] -; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK-THUMB: cmp ; CHECK-THUMB: bne ; CHECK-THUMB: dmb {{ish$}} @@ -349,21 +337,18 @@ define i64 @test12(i64* %ptr, i64 %val) { ; CHECK-LABEL: test12: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2 -; CHECK-LE: cmp [[REG1]], r1 -; CHECK-BE: cmp [[REG2]], r2 -; CHECK: movwhi [[CARRY_LO]], #1 -; CHECK-LE: cmp [[REG2]], r2 -; CHECK-BE: cmp [[REG1]], r1 -; CHECK: movwgt [[CARRY_HI]], #1 -; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK: cmp [[CARRY_HI]], #0 +; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]] +; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]] +; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]] +; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]] +; CHECK: mov [[CMP:[a-z0-9]+]], #0 +; CHECK: movwlt [[CMP]], #1 +; CHECK: cmp [[CMP]], #0 ; CHECK: movne [[OUT_HI]], [[REG2]] ; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1 ; CHECK: movne [[OUT_LO]], [[REG1]] -; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK: cmp ; CHECK: bne ; CHECK: dmb {{ish$}} @@ -371,21 +356,18 @@ define i64 @test12(i64* %ptr, i64 %val) { ; CHECK-THUMB-LABEL: test12: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] -; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0 -; CHECK-THUMB-LE: cmp [[REG1]], r2 -; CHECK-THUMB-BE: cmp [[REG2]], r3 -; CHECK-THUMB: movhi.w [[CARRY_LO]], #1 -; CHECK-THUMB-LE: cmp [[REG2]], r3 -; CHECK-THUMB-BE: cmp [[REG1]], r2 -; CHECK-THUMB: movgt [[CARRY_HI]], #1 -; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 -; CHECK-THUMB: cmp [[CARRY_HI]], #0 -; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0 +; CHECK-THUMB: movlt.w [[CMP]], #1 +; CHECK-THUMB: cmp.w [[CMP]], #0 +; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 ; CHECK-THUMB: movne [[OUT_HI]], [[REG2]] ; CHECK-THUMB: movne [[OUT_LO]], [[REG1]] -; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK-THUMB: cmp ; CHECK-THUMB: bne ; CHECK-THUMB: dmb {{ish$}} @@ -398,21 +380,18 @@ define i64 @test13(i64* %ptr, i64 %val) { ; CHECK-LABEL: test13: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0 ; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2 -; CHECK-LE: cmp [[REG1]], r1 -; CHECK-BE: cmp [[REG2]], r2 -; CHECK: movwhi [[CARRY_LO]], #1 -; CHECK-LE: cmp [[REG2]], r2 -; CHECK-BE: cmp [[REG1]], r1 -; CHECK: movwhi [[CARRY_HI]], #1 -; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK: cmp [[CARRY_HI]], #0 +; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]] +; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]] +; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]] +; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]] +; CHECK: mov [[CMP:[a-z0-9]+]], #0 +; CHECK: movwlo [[CMP]], #1 +; CHECK: cmp [[CMP]], #0 ; CHECK: movne [[OUT_HI]], [[REG2]] ; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1 ; CHECK: movne [[OUT_LO]], [[REG1]] -; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK: cmp ; CHECK: bne ; CHECK: dmb {{ish$}} @@ -420,21 +399,18 @@ define i64 @test13(i64* %ptr, i64 %val) { ; CHECK-THUMB-LABEL: test13: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] -; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0 -; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0 -; CHECK-THUMB-LE: cmp [[REG1]], r2 -; CHECK-THUMB-BE: cmp [[REG2]], r3 -; CHECK-THUMB: movhi.w [[CARRY_LO]], #1 -; CHECK-THUMB-LE: cmp [[REG2]], r3 -; CHECK-THUMB-BE: cmp [[REG1]], r2 -; CHECK-THUMB: movhi [[CARRY_HI]], #1 -; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]] -; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 -; CHECK-THUMB: cmp [[CARRY_HI]], #0 -; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2 +; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]] +; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]] +; CHECK-THUMB: mov.w [[CMP:[a-z0-9]+]], #0 +; CHECK-THUMB: movlo.w [[CMP]], #1 +; CHECK-THUMB: cmp.w [[CMP]], #0 +; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3 ; CHECK-THUMB: movne [[OUT_HI]], [[REG2]] ; CHECK-THUMB: movne [[OUT_LO]], [[REG1]] -; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]] +; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]] ; CHECK-THUMB: cmp ; CHECK-THUMB: bne ; CHECK-THUMB: dmb {{ish$}} diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index 791389456619..17324d64153d 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix CHECK-ARMV7 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-T2 ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1 -; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-M0 +; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1 ; RUN: llc < %s -mtriple=thumbv7--none-eabi -thread-model single -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-BAREMETAL target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" @@ -29,8 +29,7 @@ entry: ; CHECK: ldrex ; CHECK: add ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_add_4 - ; CHECK-M0: bl ___sync_fetch_and_add_4 + ; CHECK-T1: bl ___sync_fetch_and_add_4 ; CHECK-BAREMETAL: add ; CHECK-BAREMETAL-NOT: __sync %0 = atomicrmw add i32* %val1, i32 %tmp monotonic @@ -38,8 +37,7 @@ entry: ; CHECK: ldrex ; CHECK: sub ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_sub_4 - ; CHECK-M0: bl ___sync_fetch_and_sub_4 + ; CHECK-T1: bl ___sync_fetch_and_sub_4 ; CHECK-BAREMETAL: sub ; CHECK-BAREMETAL-NOT: __sync %1 = atomicrmw sub i32* %val2, i32 30 monotonic @@ -47,8 +45,7 @@ entry: ; CHECK: ldrex ; CHECK: add ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_add_4 - ; CHECK-M0: bl ___sync_fetch_and_add_4 + ; CHECK-T1: bl ___sync_fetch_and_add_4 ; CHECK-BAREMETAL: add ; CHECK-BAREMETAL-NOT: __sync %2 = atomicrmw add i32* %val2, i32 1 monotonic @@ -56,8 +53,7 @@ entry: ; CHECK: ldrex ; CHECK: sub ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_sub_4 - ; CHECK-M0: bl ___sync_fetch_and_sub_4 + ; CHECK-T1: bl ___sync_fetch_and_sub_4 ; CHECK-BAREMETAL: sub ; CHECK-BAREMETAL-NOT: __sync %3 = atomicrmw sub i32* %val2, i32 1 monotonic @@ -65,8 +61,7 @@ entry: ; CHECK: ldrex ; CHECK: and ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_and_4 - ; CHECK-M0: bl ___sync_fetch_and_and_4 + ; CHECK-T1: bl ___sync_fetch_and_and_4 ; CHECK-BAREMETAL: and ; CHECK-BAREMETAL-NOT: __sync %4 = atomicrmw and i32* %andt, i32 4080 monotonic @@ -74,8 +69,7 @@ entry: ; CHECK: ldrex ; CHECK: or ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_or_4 - ; CHECK-M0: bl ___sync_fetch_and_or_4 + ; CHECK-T1: bl ___sync_fetch_and_or_4 ; CHECK-BAREMETAL: or ; CHECK-BAREMETAL-NOT: __sync %5 = atomicrmw or i32* %ort, i32 4080 monotonic @@ -83,8 +77,7 @@ entry: ; CHECK: ldrex ; CHECK: eor ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_xor_4 - ; CHECK-M0: bl ___sync_fetch_and_xor_4 + ; CHECK-T1: bl ___sync_fetch_and_xor_4 ; CHECK-BAREMETAL: eor ; CHECK-BAREMETAL-NOT: __sync %6 = atomicrmw xor i32* %xort, i32 4080 monotonic @@ -92,8 +85,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_min_4 - ; CHECK-M0: bl ___sync_fetch_and_min_4 + ; CHECK-T1: bl ___sync_fetch_and_min_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %7 = atomicrmw min i32* %val2, i32 16 monotonic @@ -102,8 +94,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_min_4 - ; CHECK-M0: bl ___sync_fetch_and_min_4 + ; CHECK-T1: bl ___sync_fetch_and_min_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %8 = atomicrmw min i32* %val2, i32 %neg monotonic @@ -111,8 +102,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_max_4 - ; CHECK-M0: bl ___sync_fetch_and_max_4 + ; CHECK-T1: bl ___sync_fetch_and_max_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %9 = atomicrmw max i32* %val2, i32 1 monotonic @@ -120,8 +110,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_max_4 - ; CHECK-M0: bl ___sync_fetch_and_max_4 + ; CHECK-T1: bl ___sync_fetch_and_max_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %10 = atomicrmw max i32* %val2, i32 0 monotonic @@ -129,8 +118,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_4 - ; CHECK-M0: bl ___sync_fetch_and_umin_4 + ; CHECK-T1: bl ___sync_fetch_and_umin_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %11 = atomicrmw umin i32* %val2, i32 16 monotonic @@ -139,8 +127,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_4 - ; CHECK-M0: bl ___sync_fetch_and_umin_4 + ; CHECK-T1: bl ___sync_fetch_and_umin_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic @@ -148,8 +135,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_4 - ; CHECK-M0: bl ___sync_fetch_and_umax_4 + ; CHECK-T1: bl ___sync_fetch_and_umax_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %13 = atomicrmw umax i32* %val2, i32 1 monotonic @@ -157,8 +143,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_4 - ; CHECK-M0: bl ___sync_fetch_and_umax_4 + ; CHECK-T1: bl ___sync_fetch_and_umax_4 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %14 = atomicrmw umax i32* %val2, i32 0 monotonic @@ -175,8 +160,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_2 - ; CHECK-M0: bl ___sync_fetch_and_umin_2 + ; CHECK-T1: bl ___sync_fetch_and_umin_2 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %0 = atomicrmw umin i16* %val, i16 16 monotonic @@ -185,8 +169,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_2 - ; CHECK-M0: bl ___sync_fetch_and_umin_2 + ; CHECK-T1: bl ___sync_fetch_and_umin_2 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %1 = atomicrmw umin i16* %val, i16 %uneg monotonic @@ -194,8 +177,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_2 - ; CHECK-M0: bl ___sync_fetch_and_umax_2 + ; CHECK-T1: bl ___sync_fetch_and_umax_2 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %2 = atomicrmw umax i16* %val, i16 1 monotonic @@ -203,8 +185,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_2 - ; CHECK-M0: bl ___sync_fetch_and_umax_2 + ; CHECK-T1: bl ___sync_fetch_and_umax_2 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %3 = atomicrmw umax i16* %val, i16 0 monotonic @@ -220,8 +201,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_1 - ; CHECK-M0: bl ___sync_fetch_and_umin_1 + ; CHECK-T1: bl ___sync_fetch_and_umin_1 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %0 = atomicrmw umin i8* %val, i8 16 monotonic @@ -229,8 +209,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umin_1 - ; CHECK-M0: bl ___sync_fetch_and_umin_1 + ; CHECK-T1: bl ___sync_fetch_and_umin_1 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %uneg = sub i8 0, 1 @@ -239,8 +218,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_1 - ; CHECK-M0: bl ___sync_fetch_and_umax_1 + ; CHECK-T1: bl ___sync_fetch_and_umax_1 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %2 = atomicrmw umax i8* %val, i8 1 monotonic @@ -248,8 +226,7 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex - ; CHECK-T1: blx ___sync_fetch_and_umax_1 - ; CHECK-M0: bl ___sync_fetch_and_umax_1 + ; CHECK-T1: bl ___sync_fetch_and_umax_1 ; CHECK-BAREMETAL: cmp ; CHECK-BAREMETAL-NOT: __sync %3 = atomicrmw umax i8* %val, i8 0 monotonic @@ -272,31 +249,37 @@ define i32 @test_cmpxchg_fail_order(i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 0 -; CHECK-ARMV7: dmb ish -; CHECK-ARMV7: [[LOOP_BB:\.?LBB[0-9]+_1]]: ; CHECK-ARMV7: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] ; CHECK-ARMV7: cmp [[OLDVAL]], r1 ; CHECK-ARMV7: bne [[FAIL_BB:\.?LBB[0-9]+_[0-9]+]] +; CHECK-ARMV7: dmb ish +; CHECK-ARMV7: [[LOOP_BB:\.?LBB.*]]: ; CHECK-ARMV7: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] ; CHECK-ARMV7: cmp [[SUCCESS]], #0 -; CHECK-ARMV7: bne [[LOOP_BB]] -; CHECK-ARMV7: dmb ish -; CHECK-ARMV7: bx lr +; CHECK-ARMV7: beq [[SUCCESS_BB:\.?LBB.*]] +; CHECK-ARMV7: ldrex [[OLDVAL]], [r[[ADDR]]] +; CHECK-ARMV7: cmp [[OLDVAL]], r1 +; CHECK-ARMV7: beq [[LOOP_BB]] ; CHECK-ARMV7: [[FAIL_BB]]: ; CHECK-ARMV7: clrex ; CHECK-ARMV7: bx lr +; CHECK-ARMV7: [[SUCCESS_BB]]: +; CHECK-ARMV7: dmb ish +; CHECK-ARMV7: bx lr -; CHECK-T2: dmb ish -; CHECK-T2: [[LOOP_BB:\.?LBB[0-9]+_1]]: ; CHECK-T2: ldrex [[OLDVAL:r[0-9]+]], [r[[ADDR:[0-9]+]]] ; CHECK-T2: cmp [[OLDVAL]], r1 -; CHECK-T2: clrexne -; CHECK-T2: bxne lr +; CHECK-T2: bne [[FAIL_BB:\.?LBB.*]] +; CHECK-T2: dmb ish +; CHECK-T2: [[LOOP_BB:\.?LBB.*]]: ; CHECK-T2: strex [[SUCCESS:r[0-9]+]], r2, [r[[ADDR]]] ; CHECK-T2: cmp [[SUCCESS]], #0 ; CHECK-T2: dmbeq ish ; CHECK-T2: bxeq lr -; CHECK-T2: b [[LOOP_BB]] +; CHECK-T2: ldrex [[OLDVAL]], [r[[ADDR]]] +; CHECK-T2: cmp [[OLDVAL]], r1 +; CHECK-T2: beq [[LOOP_BB]] +; CHECK-T2: clrex ret i32 %oldval } @@ -336,8 +319,8 @@ define i32 @load_load_add_acquire(i32* %mem1, i32* %mem2) nounwind { ; CHECK: dmb ; CHECK: add r0, -; CHECK-M0: ___sync_val_compare_and_swap_4 -; CHECK-M0: ___sync_val_compare_and_swap_4 +; CHECK-T1: ___sync_val_compare_and_swap_4 +; CHECK-T1: ___sync_val_compare_and_swap_4 ; CHECK-BAREMETAL: ldr {{r[0-9]}}, [r0] ; CHECK-BAREMETAL-NOT: dmb @@ -358,8 +341,8 @@ define void @store_store_release(i32* %mem1, i32 %val1, i32* %mem2, i32 %val2) { ; CHECK: dmb ; CHECK: str r3, [r2] -; CHECK-M0: ___sync_lock_test_and_set -; CHECK-M0: ___sync_lock_test_and_set +; CHECK-T1: ___sync_lock_test_and_set +; CHECK-T1: ___sync_lock_test_and_set ; CHECK-BAREMETAL-NOT: dmb ; CHECK-BAREMTEAL: str r1, [r0] @@ -379,9 +362,9 @@ define void @load_fence_store_monotonic(i32* %mem1, i32* %mem2) { ; CHECK: dmb ; CHECK: str [[R0]], [r1] -; CHECK-M0: ldr [[R0:r[0-9]]], [r0] -; CHECK-M0: dmb -; CHECK-M0: str [[R0]], [r1] +; CHECK-T1: ldr [[R0:r[0-9]]], [{{r[0-9]+}}] +; CHECK-T1: {{dmb|bl ___sync_synchronize}} +; CHECK-T1: str [[R0]], [{{r[0-9]+}}] ; CHECK-BAREMETAL: ldr [[R0:r[0-9]]], [r0] ; CHECK-BAREMETAL-NOT: dmb diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll index efdb75b63222..77b850bd617b 100644 --- a/test/CodeGen/ARM/atomic-ops-v8.ll +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -667,19 +667,14 @@ define void @test_atomic_load_min_i64(i64 %offset) nounwind { ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 -; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 -; CHECK-ARM-LE: cmp [[OLD1]], r0 -; CHECK-ARM-LE: movwls [[LOCARRY]], #1 -; CHECK-ARM-LE: cmp [[OLD2]], r1 -; CHECK-ARM-LE: movwle [[HICARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD2]], r1 -; CHECK-ARM-BE: movwls [[LOCARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD1]], r0 -; CHECK-ARM-BE: movwle [[HICARRY]], #1 -; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] -; CHECK-ARM: cmp [[HICARRY]], #0 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0 +; CHECK-ARM: movwge [[CMP:r[0-9]+|lr]], #1 +; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0 ; CHECK-ARM: movne [[MINHI]], [[OLD2]] ; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 ; CHECK-ARM: movne [[MINLO]], [[OLD1]] @@ -785,19 +780,14 @@ define void @test_atomic_load_max_i64(i64 %offset) nounwind { ; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 -; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 -; CHECK-ARM-LE: cmp [[OLD1]], r0 -; CHECK-ARM-LE: movwhi [[LOCARRY]], #1 -; CHECK-ARM-LE: cmp [[OLD2]], r1 -; CHECK-ARM-LE: movwgt [[HICARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD2]], r1 -; CHECK-ARM-BE: movwhi [[LOCARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD1]], r0 -; CHECK-ARM-BE: movwgt [[HICARRY]], #1 -; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] -; CHECK-ARM: cmp [[HICARRY]], #0 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0 +; CHECK-ARM: movwlt [[CMP:r[0-9]+|lr]], #1 +; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0 ; CHECK-ARM: movne [[MINHI]], [[OLD2]] ; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 ; CHECK-ARM: movne [[MINLO]], [[OLD1]] @@ -903,19 +893,14 @@ define void @test_atomic_load_umin_i64(i64 %offset) nounwind { ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 -; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 -; CHECK-ARM-LE: cmp [[OLD1]], r0 -; CHECK-ARM-LE: movwls [[LOCARRY]], #1 -; CHECK-ARM-LE: cmp [[OLD2]], r1 -; CHECK-ARM-LE: movwls [[HICARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD2]], r1 -; CHECK-ARM-BE: movwls [[LOCARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD1]], r0 -; CHECK-ARM-BE: movwls [[HICARRY]], #1 -; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] -; CHECK-ARM: cmp [[HICARRY]], #0 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0 +; CHECK-ARM: movwhs [[CMP:r[0-9]+|lr]], #1 +; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0 ; CHECK-ARM: movne [[MINHI]], [[OLD2]] ; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 ; CHECK-ARM: movne [[MINLO]], [[OLD1]] @@ -1021,19 +1006,14 @@ define void @test_atomic_load_umax_i64(i64 %offset) nounwind { ; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] ; r0, r1 below is a reasonable guess but could change: it certainly comes into the ; function there. -; CHECK-ARM: mov [[LOCARRY:r[0-9]+|lr]], #0 -; CHECK-ARM: mov [[HICARRY:r[0-9]+|lr]], #0 -; CHECK-ARM-LE: cmp [[OLD1]], r0 -; CHECK-ARM-LE: movwhi [[LOCARRY]], #1 -; CHECK-ARM-LE: cmp [[OLD2]], r1 -; CHECK-ARM-LE: movwhi [[HICARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD2]], r1 -; CHECK-ARM-BE: movwhi [[LOCARRY]], #1 -; CHECK-ARM-BE: cmp [[OLD1]], r0 -; CHECK-ARM-BE: movwhi [[HICARRY]], #1 -; CHECK-ARM: moveq [[HICARRY]], [[LOCARRY]] -; CHECK-ARM: cmp [[HICARRY]], #0 ; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1 +; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]] +; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]] +; CHECK-ARM: mov [[CMP:r[0-9]+|lr]], #0 +; CHECK-ARM: movwlo [[CMP:r[0-9]+|lr]], #1 +; CHECK-ARM: cmp [[CMP:r[0-9]+|lr]], #0 ; CHECK-ARM: movne [[MINHI]], [[OLD2]] ; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0 ; CHECK-ARM: movne [[MINLO]], [[OLD1]] diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll index edb0c1a5a54a..629060218e43 100644 --- a/test/CodeGen/ARM/bfx.ll +++ b/test/CodeGen/ARM/bfx.ll @@ -51,3 +51,19 @@ entry: %add7 = add i32 %add, %2 ret i32 %add7 } + +define i32 @ubfx3(i32 %a) { +; CHECK: ubfx3 +; CHECK: ubfx r0, r0, #11, #1 + %t1 = and i32 %a, 2048 + %t2 = lshr i32 %t1, 11 + ret i32 %t2 +} + +define i32 @ubfx4(i32 %a) { +; CHECK: ubfx4 +; CHECK: ubfx r0, r0, #7, #3 + %t1 = and i32 %a, 896 + %t2 = lshr i32 %t1, 7 + ret i32 %t2 +} diff --git a/test/CodeGen/ARM/build-attributes-encoding.s b/test/CodeGen/ARM/build-attributes-encoding.s index 29f13f09d319..5649726c12bb 100644 --- a/test/CodeGen/ARM/build-attributes-encoding.s +++ b/test/CodeGen/ARM/build-attributes-encoding.s @@ -54,6 +54,9 @@ // Tag_DIV_use (=44) .eabi_attribute 44, 2 +// Tag_DSP_extension (=46) +.eabi_attribute 46, 1 + // Tag_Virtualization_use (=68) .eabi_attribute 68, 3 @@ -71,15 +74,15 @@ // CHECK-NEXT: ] // CHECK-NEXT: Address: 0x0 // CHECK-NEXT: Offset: 0x34 -// CHECK-NEXT: Size: 71 +// CHECK-NEXT: Size: 73 // CHECK-NEXT: Link: 0 // CHECK-NEXT: Info: 0 // CHECK-NEXT: AddressAlignment: 1 // CHECK-NEXT: EntrySize: 0 // CHECK-NEXT: SectionData ( -// CHECK-NEXT: 0000: 41460000 00616561 62690001 3C000000 +// CHECK-NEXT: 0000: 41480000 00616561 62690001 3E000000 // CHECK-NEXT: 0010: 05636F72 7465782D 61380006 0A074108 // CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119 -// CHECK-NEXT: 0030: 011B001C 0124012A 012C0244 036EA001 -// CHECK-NEXT: 0040: 81013100 FA0101 +// CHECK-NEXT: 0030: 011B001C 0124012A 012C022E 0144036E +// CHECK-NEXT: 0040: A0018101 3100FA01 01 // CHECK-NEXT: ) diff --git a/test/CodeGen/ARM/build-attributes.ll b/test/CodeGen/ARM/build-attributes.ll index a74b3e441a13..b3b39a0d550f 100644 --- a/test/CodeGen/ARM/build-attributes.ll +++ b/test/CodeGen/ARM/build-attributes.ll @@ -27,12 +27,21 @@ ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO +; RUN: llc < %s -mtriple=thumbv8m.base-linux-gnueabi | FileCheck %s --check-prefix=V8MBASELINE +; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi | FileCheck %s --check-prefix=V8MMAINLINE +; RUN: llc < %s -mtriple=thumbv8m.main-linux-gnueabi -mattr=+dsp | FileCheck %s --check-prefix=V8MMAINLINE_DSP ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A8-SOFT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A8-SOFT-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A8-HARD +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A8-HARD-FAST +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A8-SOFT ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD @@ -96,6 +105,12 @@ ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 | FileCheck %s --check-prefix=CORTEX-R7 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R7-FAST ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r8 | FileCheck %s --check-prefix=CORTEX-R8 +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r8 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R8-FAST +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r8 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a32 | FileCheck %s --check-prefix=CORTEX-A32 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a32 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A32-FAST +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a32 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=CORTEX-A35 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A35-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a35 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING @@ -108,6 +123,7 @@ ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=CORTEX-A72 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a73 | FileCheck %s --check-prefix=CORTEX-A73 ; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=EXYNOS-M1 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST @@ -124,7 +140,6 @@ ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER -; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=RELOC-OTHER ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=PCS-R9-USE @@ -135,6 +150,8 @@ ; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8.1a-none-linux-gnueabi | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; ARMv8a (AArch32) +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a32 | FileCheck %s --check-prefix=NO-STRICT-ALIGN +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a32 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 | FileCheck %s --check-prefix=NO-STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a35 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN @@ -373,6 +390,31 @@ ; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3 +; V8MBASELINE: .syntax unified +; '6' is Tag_CPU_arch, '16' is ARM v8-M Baseline +; V8MBASELINE: .eabi_attribute 6, 16 +; '7' is Tag_CPU_arch_profile, '77' is 'M' +; V8MBASELINE: .eabi_attribute 7, 77 +; '8' is Tag_ARM_ISA_use +; V8MBASELINE: .eabi_attribute 8, 0 +; '9' is Tag_Thumb_ISA_use +; V8MBASELINE: .eabi_attribute 9, 3 + +; V8MMAINLINE: .syntax unified +; '6' is Tag_CPU_arch, '17' is ARM v8-M Mainline +; V8MMAINLINE: .eabi_attribute 6, 17 +; V8MMAINLINE: .eabi_attribute 7, 77 +; V8MMAINLINE: .eabi_attribute 8, 0 +; V8MMAINLINE: .eabi_attribute 9, 3 +; V8MMAINLINE_DSP-NOT: .eabi_attribute 46 + +; V8MMAINLINE_DSP: .syntax unified +; V8MBASELINE_DSP: .eabi_attribute 6, 17 +; V8MBASELINE_DSP: .eabi_attribute 7, 77 +; V8MMAINLINE_DSP: .eabi_attribute 8, 0 +; V8MMAINLINE_DSP: .eabi_attribute 9, 3 +; V8MMAINLINE_DSP: .eabi_attribute 46, 1 + ; Tag_CPU_unaligned_access ; NO-STRICT-ALIGN: .eabi_attribute 34, 1 ; STRICT-ALIGN: .eabi_attribute 34, 0 @@ -462,6 +504,9 @@ ; CORTEX-A7-NOFPU: .eabi_attribute 44, 2 ; CORTEX-A7-FPUV4: .eabi_attribute 44, 2 +; Tag_DSP_extension +; CORTEX-A7-CHECK-NOT: .eabi_attribute 46 + ; Tag_Virtualization_use ; CORTEX-A7-CHECK: .eabi_attribute 68, 3 ; CORTEX-A7-NOFPU: .eabi_attribute 68, 3 @@ -486,7 +531,7 @@ ; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19 -;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math +;; The A5 defaults to a VFPv4 FPU, so it flushed preserving the sign when -ffast-math ;; is given. ; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 20, 2 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21 @@ -543,6 +588,28 @@ ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22 ; CORTEX-A5-NOFPU-FAST: .eabi_attribute 23, 1 +; CORTEX-A8-SOFT: .cpu cortex-a8 +; CORTEX-A8-SOFT: .eabi_attribute 6, 10 +; CORTEX-A8-SOFT: .eabi_attribute 7, 65 +; CORTEX-A8-SOFT: .eabi_attribute 8, 1 +; CORTEX-A8-SOFT: .eabi_attribute 9, 2 +; CORTEX-A8-SOFT: .fpu neon +; CORTEX-A8-SOFT-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A8-SOFT: .eabi_attribute 20, 1 +; CORTEX-A8-SOFT: .eabi_attribute 21, 1 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 22 +; CORTEX-A8-SOFT: .eabi_attribute 23, 3 +; CORTEX-A8-SOFT: .eabi_attribute 24, 1 +; CORTEX-A8-SOFT: .eabi_attribute 25, 1 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 27 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 28 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 36, 1 +; CORTEX-A8-SOFT: .eabi_attribute 38, 1 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 42, 1 +; CORTEX-A8-SOFT-NOT: .eabi_attribute 44 +; CORTEX-A8-SOFT: .eabi_attribute 68, 1 + ; CORTEX-A9-SOFT: .cpu cortex-a9 ; CORTEX-A9-SOFT: .eabi_attribute 6, 10 ; CORTEX-A9-SOFT: .eabi_attribute 7, 65 @@ -565,14 +632,39 @@ ; CORTEX-A9-SOFT-NOT: .eabi_attribute 44 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1 +; CORTEX-A8-SOFT-FAST-NOT: .eabi_attribute 19 ; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19 -;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. +; CORTEX-A8-SOFT-FAST: .eabi_attribute 20, 2 ; CORTEX-A9-SOFT-FAST: .eabi_attribute 20, 2 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22 ; CORTEX-A5-SOFT-FAST: .eabi_attribute 23, 1 +; CORTEX-A8-HARD: .cpu cortex-a8 +; CORTEX-A8-HARD: .eabi_attribute 6, 10 +; CORTEX-A8-HARD: .eabi_attribute 7, 65 +; CORTEX-A8-HARD: .eabi_attribute 8, 1 +; CORTEX-A8-HARD: .eabi_attribute 9, 2 +; CORTEX-A8-HARD: .fpu neon +; CORTEX-A8-HARD-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A8-HARD: .eabi_attribute 20, 1 +; CORTEX-A8-HARD: .eabi_attribute 21, 1 +; CORTEX-A8-HARD-NOT: .eabi_attribute 22 +; CORTEX-A8-HARD: .eabi_attribute 23, 3 +; CORTEX-A8-HARD: .eabi_attribute 24, 1 +; CORTEX-A8-HARD: .eabi_attribute 25, 1 +; CORTEX-A8-HARD-NOT: .eabi_attribute 27 +; CORTEX-A8-HARD: .eabi_attribute 28, 1 +; CORTEX-A8-HARD-NOT: .eabi_attribute 36, 1 +; CORTEX-A8-HARD: .eabi_attribute 38, 1 +; CORTEX-A8-HARD-NOT: .eabi_attribute 42, 1 +; CORTEX-A8-HARD: .eabi_attribute 68, 1 + + + ; CORTEX-A9-HARD: .cpu cortex-a9 ; CORTEX-A9-HARD: .eabi_attribute 6, 10 ; CORTEX-A9-HARD: .eabi_attribute 7, 65 @@ -594,8 +686,16 @@ ; CORTEX-A9-HARD: .eabi_attribute 42, 1 ; CORTEX-A9-HARD: .eabi_attribute 68, 1 +; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 19 +;; The A8 defaults to a VFPv3 FPU, so it flushes preserving the sign when +;; -ffast-math is specified. +; CORTEX-A8-HARD-FAST: .eabi_attribute 20, 2 +; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 21 +; CORTEX-A8-HARD-FAST-NOT: .eabi_attribute 22 +; CORTEX-A8-HARD-FAST: .eabi_attribute 23, 1 + ; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 19 -;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; The A9 defaults to a VFPv3 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-A9-HARD-FAST: .eabi_attribute 20, 2 ; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 21 @@ -621,7 +721,7 @@ ; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3 ; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19 -;; The A12 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; The A12 defaults to a VFPv3 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-A12-DEFAULT-FAST: .eabi_attribute 20, 2 ; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 21 @@ -678,7 +778,7 @@ ; CORTEX-A15: .eabi_attribute 68, 3 ; CORTEX-A15-FAST-NOT: .eabi_attribute 19 -;; The A15 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; The A15 defaults to a VFPv3 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-A15-FAST: .eabi_attribute 20, 2 ; CORTEX-A15-FAST-NOT: .eabi_attribute 21 @@ -704,7 +804,7 @@ ; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3 ; CORTEX-A17-FAST-NOT: .eabi_attribute 19 -;; The A17 defaults to a VFPv3 FPU, so it flushes preseving sign when +;; The A17 defaults to a VFPv3 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-A17-FAST: .eabi_attribute 20, 2 ; CORTEX-A17-FAST-NOT: .eabi_attribute 21 @@ -950,7 +1050,7 @@ ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19 -;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when +;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-M4-SOFT-FAST: .eabi_attribute 20, 2 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 21 @@ -980,7 +1080,7 @@ ; CORTEX-M4-HARD-NOT: .eabi_attribute 68 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19 -;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when +;; The M4 defaults to a VFPv4 FPU, so it flushes preserving the sign when ;; -ffast-math is specified. ; CORTEX-M4-HARD-FAST: .eabi_attribute 20, 2 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 21 @@ -1100,7 +1200,7 @@ ; CORTEX-R7: .eabi_attribute 7, 82 ; CORTEX-R7: .eabi_attribute 8, 1 ; CORTEX-R7: .eabi_attribute 9, 2 -; CORTEX-R7: .fpu vfpv3xd +; CORTEX-R7: .fpu vfpv3-d16-fp16 ; CORTEX-R7-NOT: .eabi_attribute 19 ;; We default to IEEE 754 compliance ; CORTEX-R7: .eabi_attribute 20, 1 @@ -1109,7 +1209,6 @@ ; CORTEX-R7: .eabi_attribute 23, 3 ; CORTEX-R7: .eabi_attribute 24, 1 ; CORTEX-R7: .eabi_attribute 25, 1 -; CORTEX-R7: .eabi_attribute 27, 1 ; CORTEX-R7-NOT: .eabi_attribute 28 ; CORTEX-R7: .eabi_attribute 36, 1 ; CORTEX-R7: .eabi_attribute 38, 1 @@ -1124,6 +1223,64 @@ ; CORTEX-R7-FAST-NOT: .eabi_attribute 22 ; CORTEX-R7-FAST: .eabi_attribute 23, 1 +; CORTEX-R8: .cpu cortex-r8 +; CORTEX-R8: .eabi_attribute 6, 10 +; CORTEX-R8: .eabi_attribute 7, 82 +; CORTEX-R8: .eabi_attribute 8, 1 +; CORTEX-R8: .eabi_attribute 9, 2 +; CORTEX-R8: .fpu vfpv3-d16-fp16 +; CORTEX-R8-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-R8: .eabi_attribute 20, 1 +; CORTEX-R8: .eabi_attribute 21, 1 +; CORTEX-R8-NOT: .eabi_attribute 22 +; CORTEX-R8: .eabi_attribute 23, 3 +; CORTEX-R8: .eabi_attribute 24, 1 +; CORTEX-R8: .eabi_attribute 25, 1 +; CORTEX-R8-NOT: .eabi_attribute 28 +; CORTEX-R8: .eabi_attribute 36, 1 +; CORTEX-R8: .eabi_attribute 38, 1 +; CORTEX-R8: .eabi_attribute 42, 1 +; CORTEX-R8: .eabi_attribute 44, 2 +; CORTEX-R8-NOT: .eabi_attribute 68 + +; CORTEX-R8-FAST-NOT: .eabi_attribute 19 +;; The R8 has the VFPv3 FP unit, which always flushes preserving sign. +; CORTEX-R8-FAST: .eabi_attribute 20, 2 +; CORTEX-R8-FAST-NOT: .eabi_attribute 21 +; CORTEX-R8-FAST-NOT: .eabi_attribute 22 +; CORTEX-R8-FAST: .eabi_attribute 23, 1 + +; CORTEX-A32: .cpu cortex-a32 +; CORTEX-A32: .eabi_attribute 6, 14 +; CORTEX-A32: .eabi_attribute 7, 65 +; CORTEX-A32: .eabi_attribute 8, 1 +; CORTEX-A32: .eabi_attribute 9, 2 +; CORTEX-A32: .fpu crypto-neon-fp-armv8 +; CORTEX-A32: .eabi_attribute 12, 3 +; CORTEX-A32-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A32: .eabi_attribute 20, 1 +; CORTEX-A32: .eabi_attribute 21, 1 +; CORTEX-A32-NOT: .eabi_attribute 22 +; CORTEX-A32: .eabi_attribute 23, 3 +; CORTEX-A32: .eabi_attribute 24, 1 +; CORTEX-A32: .eabi_attribute 25, 1 +; CORTEX-A32-NOT: .eabi_attribute 27 +; CORTEX-A32-NOT: .eabi_attribute 28 +; CORTEX-A32: .eabi_attribute 36, 1 +; CORTEX-A32: .eabi_attribute 38, 1 +; CORTEX-A32: .eabi_attribute 42, 1 +; CORTEX-A32-NOT: .eabi_attribute 44 +; CORTEX-A32: .eabi_attribute 68, 3 + +; CORTEX-A32-FAST-NOT: .eabi_attribute 19 +;; The A32 has the ARMv8 FP unit, which always flushes preserving sign. +; CORTEX-A32-FAST: .eabi_attribute 20, 2 +; CORTEX-A32-FAST-NOT: .eabi_attribute 21 +; CORTEX-A32-FAST-NOT: .eabi_attribute 22 +; CORTEX-A32-FAST: .eabi_attribute 23, 1 + ; CORTEX-A35: .cpu cortex-a35 ; CORTEX-A35: .eabi_attribute 6, 14 ; CORTEX-A35: .eabi_attribute 7, 65 @@ -1244,6 +1401,30 @@ ; CORTEX-A72-FAST-NOT: .eabi_attribute 22 ; CORTEX-A72-FAST: .eabi_attribute 23, 1 +; CORTEX-A73: .cpu cortex-a73 +; CORTEX-A73: .eabi_attribute 6, 14 +; CORTEX-A73: .eabi_attribute 7, 65 +; CORTEX-A73: .eabi_attribute 8, 1 +; CORTEX-A73: .eabi_attribute 9, 2 +; CORTEX-A73: .fpu crypto-neon-fp-armv8 +; CORTEX-A73: .eabi_attribute 12, 3 +; CORTEX-A73-NOT: .eabi_attribute 19 +;; We default to IEEE 754 compliance +; CORTEX-A73: .eabi_attribute 20, 1 +; CORTEX-A73: .eabi_attribute 21, 1 +; CORTEX-A73-NOT: .eabi_attribute 22 +; CORTEX-A73: .eabi_attribute 23, 3 +; CORTEX-A73: .eabi_attribute 24, 1 +; CORTEX-A73: .eabi_attribute 25, 1 +; CORTEX-A73-NOT: .eabi_attribute 27 +; CORTEX-A73-NOT: .eabi_attribute 28 +; CORTEX-A73: .eabi_attribute 36, 1 +; CORTEX-A73: .eabi_attribute 38, 1 +; CORTEX-A73: .eabi_attribute 42, 1 +; CORTEX-A73-NOT: .eabi_attribute 44 +; CORTEX-A73: .eabi_attribute 14, 0 +; CORTEX-A73: .eabi_attribute 68, 3 + ; EXYNOS-M1: .cpu exynos-m1 ; EXYNOS-M1: .eabi_attribute 6, 14 ; EXYNOS-M1: .eabi_attribute 7, 65 diff --git a/test/CodeGen/ARM/byval_load_align.ll b/test/CodeGen/ARM/byval_load_align.ll index 2c0910c71d2f..d00d926c7a05 100644 --- a/test/CodeGen/ARM/byval_load_align.ll +++ b/test/CodeGen/ARM/byval_load_align.ll @@ -7,7 +7,7 @@ ; CHECK: ldr r2, [r[[REG]], #4] ; CHECK: ldr r3, [r[[REG]], #8] ; CHECK-NOT: ldm -; CHECK: .align 1 @ @sID +; CHECK: .p2align 1 @ @sID %struct.ModuleID = type { [32 x i8], [32 x i8], i16 } diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index 8821029520fe..53fa8920ec04 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -12,7 +12,7 @@ declare void @g(i32, i32, i32, i32) define void @t1() { ; CHECKELF-LABEL: t1: -; CHECKELF: bl g(PLT) +; CHECKELF: bl g call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } @@ -33,7 +33,7 @@ define void @t3() { ; CHECKV6-LABEL: t3: ; CHECKV6: b _t2 ; CHECKELF-LABEL: t3: -; CHECKELF: b t2(PLT) +; CHECKELF: b t2 ; CHECKT2D-LABEL: t3: ; CHECKT2D: b.w _t2 @@ -47,7 +47,7 @@ entry: ; CHECKV6-LABEL: t4: ; CHECKV6: b _sin ; CHECKELF-LABEL: t4: -; CHECKELF: b sin(PLT) +; CHECKELF: b sin %0 = tail call double @sin(double %a) nounwind readonly ; [#uses=1] ret double %0 } @@ -57,7 +57,7 @@ entry: ; CHECKV6-LABEL: t5: ; CHECKV6: b _sinf ; CHECKELF-LABEL: t5: -; CHECKELF: b sinf(PLT) +; CHECKELF: b sinf %0 = tail call float @sinf(float %a) nounwind readonly ; [#uses=1] ret float %0 } @@ -71,7 +71,7 @@ entry: ; CHECKV6-LABEL: t6: ; CHECKV6: b ___divsi3 ; CHECKELF-LABEL: t6: -; CHECKELF: b __aeabi_idiv(PLT) +; CHECKELF: b __aeabi_idiv %0 = sdiv i32 %a, %b ret i32 %0 } @@ -87,7 +87,7 @@ entry: ; CHECKT2D-NEXT: bne.w _foo ; CHECKT2D-NEXT: push ; CHECKT2D-NEXT: mov r7, sp -; CHECKT2D-NEXT: blx _foo +; CHECKT2D-NEXT: bl _foo br i1 undef, label %bb, label %bb1.lr.ph bb1.lr.ph: @@ -150,8 +150,8 @@ declare i32 @c(i32) define i32 @t9() nounwind { ; CHECKT2D-LABEL: t9: -; CHECKT2D: blx __ZN9MutexLockC1Ev -; CHECKT2D: blx __ZN9MutexLockD1Ev +; CHECKT2D: bl __ZN9MutexLockC1Ev +; CHECKT2D: bl __ZN9MutexLockD1Ev ; CHECKT2D: b.w ___divsi3 %lock = alloca %class.MutexLock, align 1 %1 = call %class.MutexLock* @_ZN9MutexLockC1Ev(%class.MutexLock* %lock) @@ -170,7 +170,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou ; otherwise the call to floorf is lost. define float @libcall_tc_test2(float* nocapture %a, float %b) { ; CHECKT2D-LABEL: libcall_tc_test2: -; CHECKT2D: blx _floorf +; CHECKT2D: bl _floorf ; CHECKT2D: b.w _truncf %1 = load float, float* %a, align 4 %call = tail call float @floorf(float %1) diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index 87252a91e1b0..05ea556e234c 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -12,7 +12,7 @@ declare void @g(i32, i32, i32, i32) define void @f() { -; CHECKELF: PLT +; CHECKELF: bl g call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index 7ea9be2c61e6..558e2b0e43f7 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -11,9 +11,10 @@ entry: define i64 @f2(i64 %a, i64 %b) { ; CHECK-LABEL: f2: -; CHECK: adc r -; CHECK: subs r -; CHECK: sbc r +; CHECK: lsl r +; CHECK: orr r +; CHECK: rsbs r +; CHECK: sbc r entry: %tmp1 = shl i64 %a, 1 %tmp2 = sub i64 %tmp1, %b diff --git a/test/CodeGen/ARM/cdp.ll b/test/CodeGen/ARM/cdp.ll new file mode 100644 index 000000000000..99ec3b284462 --- /dev/null +++ b/test/CodeGen/ARM/cdp.ll @@ -0,0 +1,13 @@ +; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s + +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp +define void @cdp(i32 %a) #0 { + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %1 = load i32, i32* %a.addr, align 4 + call void @llvm.arm.cdp(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6) + ret void +} + +declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/cdp2.ll b/test/CodeGen/ARM/cdp2.ll new file mode 100644 index 000000000000..c2a00d0fdd72 --- /dev/null +++ b/test/CodeGen/ARM/cdp2.ll @@ -0,0 +1,13 @@ +; RUN: not llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s +; RUN: not llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 2>&1 | FileCheck %s + +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.cdp2 +define void @cdp2(i32 %a) #0 { + %a.addr = alloca i32, align 4 + store i32 %a, i32* %a.addr, align 4 + %1 = load i32, i32* %a.addr, align 4 + call void @llvm.arm.cdp2(i32 %1, i32 2, i32 3, i32 4, i32 5, i32 6) + ret void +} + +declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/cmpxchg-O0.ll b/test/CodeGen/ARM/cmpxchg-O0.ll new file mode 100644 index 000000000000..ec3005dd8ada --- /dev/null +++ b/test/CodeGen/ARM/cmpxchg-O0.ll @@ -0,0 +1,113 @@ +; RUN: llc -verify-machineinstrs -mtriple=armv7-linux-gnu -O0 %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=thumbv8-linux-gnu -O0 %s -o - | FileCheck %s +; RUN: llc -verify-machineinstrs -mtriple=thumbv6m-none-eabi -O0 %s -o - | FileCheck %s --check-prefix=CHECK-T1 + +; CHECK-T1-NOT: ldrex +; CHECK-T1-NOT: strex + +define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_8: +; CHECK: dmb ish +; CHECK: uxtb [[DESIRED:r[0-9]+]], [[DESIRED]] +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldrexb [[OLD:r[0-9]+]], [r0] +; CHECK: cmp [[OLD]], [[DESIRED]] +; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: strexb [[STATUS:r[0-9]+]], r2, [r0] +; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 +; CHECK: bne [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]] +; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1 +; CHECK: dmb ish + %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic + ret { i8, i1 } %res +} + +define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_16: +; CHECK: dmb ish +; CHECK: uxth [[DESIRED:r[0-9]+]], [[DESIRED]] +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldrexh [[OLD:r[0-9]+]], [r0] +; CHECK: cmp [[OLD]], [[DESIRED]] +; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: strexh [[STATUS:r[0-9]+]], r2, [r0] +; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 +; CHECK: bne [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]] +; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1 +; CHECK: dmb ish + %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic + ret { i16, i1 } %res +} + +define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_32: +; CHECK: dmb ish +; CHECK-NOT: uxt +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldrex [[OLD:r[0-9]+]], [r0] +; CHECK: cmp [[OLD]], [[DESIRED]] +; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: strex [[STATUS:r[0-9]+]], r2, [r0] +; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 +; CHECK: bne [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: cmp{{(\.w)?}} [[OLD]], [[DESIRED]] +; CHECK: {{moveq|movweq}} {{r[0-9]+}}, #1 +; CHECK: dmb ish + %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic + ret { i32, i1 } %res +} + +define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind { +; CHECK-LABEL: test_cmpxchg_64: +; CHECK: dmb ish +; CHECK-NOT: uxt +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0] +; CHECK: cmp [[OLDLO]], r6 +; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], r7 +; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: strexd [[STATUS]], r4, r5, [r0] +; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 +; CHECK: bne [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: dmb ish + %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic + ret { i64, i1 } %res +} + +define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) { +; CHECK-LABEL: test_nontrivial_args: +; CHECK: dmb ish +; CHECK-NOT: uxt +; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]: +; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0] +; CHECK: cmp [[OLDLO]], {{r[0-9]+}} +; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], {{r[0-9]+}} +; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]] +; CHECK: strexd [[STATUS]], {{r[0-9]+}}, {{r[0-9]+}}, [r0] +; CHECK: cmp{{(\.w)?}} [[STATUS]], #0 +; CHECK: bne [[RETRY]] +; CHECK: [[DONE]]: +; CHECK: dmb ish + + %desired1 = add i64 %desired, 1 + %new1 = add i64 %new, 1 + %res = cmpxchg i64* %addr, i64 %desired1, i64 %new1 seq_cst seq_cst + ret { i64, i1 } %res +} + +; The following used to trigger an assertion when creating a spill on thumb2 +; for a physreg with RC==GPRPairRegClass. +; CHECK-LABEL: test_cmpxchg_spillbug: +; CHECK: ldrexd +; CHECK: strexd +; CHECK: bne +define void @test_cmpxchg_spillbug() { + %v = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst + ret void +} diff --git a/test/CodeGen/ARM/cmpxchg-idioms.ll b/test/CodeGen/ARM/cmpxchg-idioms.ll index 81e05acfef79..283202f0cc1f 100644 --- a/test/CodeGen/ARM/cmpxchg-idioms.ll +++ b/test/CodeGen/ARM/cmpxchg-idioms.ll @@ -3,26 +3,31 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) { ; CHECK-LABEL: test_return: -; CHECK: dmb ishst - -; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: ldrex [[LOADED:r[0-9]+]], [r0] ; CHECK: cmp [[LOADED]], r1 ; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]] +; CHECK: dmb ishst + +; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: strex [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0] -; CHECK: cmp [[STATUS]], #0 -; CHECK: bne [[LOOP]] +; CHECK: cbz [[STATUS]], [[SUCCESS:LBB[0-9]+_[0-9]+]] +; CHECK: ldrex [[LOADED]], [r0] +; CHECK: cmp [[LOADED]], r1 +; CHECK: beq [[LOOP]] + +; CHECK: [[FAILED]]: ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: clrex ; CHECK: dmb ish -; CHECK: movs r0, #1 +; CHECK: movs r0, #0 ; CHECK: bx lr -; CHECK: [[FAILED]]: +; CHECK: [[SUCCESS]]: ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} ; CHECK: dmb ish -; CHECK: movs r0, #0 +; CHECK: movs r0, #1 ; CHECK: bx lr %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst @@ -34,26 +39,33 @@ define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) { define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) { ; CHECK-LABEL: test_return_bool: -; CHECK: dmb ishst ; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1 -; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: ldrexb [[LOADED:r[0-9]+]], [r0] ; CHECK: cmp [[LOADED]], [[OLDBYTE]] ; CHECK: bne [[FAIL:LBB[0-9]+_[0-9]+]] +; CHECK: dmb ishst + +; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: strexb [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0] -; CHECK: cmp [[STATUS]], #0 -; CHECK: bne [[LOOP]] +; CHECK: cbz [[STATUS]], [[SUCCESS:LBB[0-9]+_[0-9]+]] + +; CHECK: ldrexb [[LOADED]], [r0] +; CHECK: cmp [[LOADED]], [[OLDBYTE]] +; CHECK: beq [[LOOP]] + ; FIXME: this eor is redundant. Need to teach DAG combine that. -; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} -; CHECK: movs [[TMP:r[0-9]+]], #1 +; CHECK: [[FAIL]]: +; CHECK: clrex +; CHECK: movs [[TMP:r[0-9]+]], #0 ; CHECK: eor r0, [[TMP]], #1 ; CHECK: bx lr -; CHECK: [[FAIL]]: -; CHECK: movs [[TMP:r[0-9]+]], #0 +; CHECK: [[SUCCESS]]: +; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: movs [[TMP:r[0-9]+]], #1 ; CHECK: eor r0, [[TMP]], #1 ; CHECK: bx lr @@ -67,26 +79,31 @@ define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) { define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) { ; CHECK-LABEL: test_conditional: -; CHECK: dmb ishst - -; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: ldrex [[LOADED:r[0-9]+]], [r0] ; CHECK: cmp [[LOADED]], r1 ; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]] +; CHECK: dmb ishst + +; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]: ; CHECK: strex [[STATUS:r[0-9]+]], r2, [r0] -; CHECK: cmp [[STATUS]], #0 -; CHECK: bne [[LOOP]] +; CHECK: cbz [[STATUS]], [[SUCCESS:LBB[0-9]+_[0-9]+]] -; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} -; CHECK: dmb ish -; CHECK: b.w _bar +; CHECK: ldrex [[LOADED]], [r0] +; CHECK: cmp [[LOADED]], r1 +; CHECK: beq [[LOOP]] ; CHECK: [[FAILED]]: ; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: clrex ; CHECK: dmb ish ; CHECK: b.w _baz +; CHECK: [[SUCCESS]]: +; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}} +; CHECK: dmb ish +; CHECK: b.w _bar + %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst %success = extractvalue { i32, i1 } %pair, 1 br i1 %success, label %true, label %false diff --git a/test/CodeGen/ARM/cmpxchg-weak.ll b/test/CodeGen/ARM/cmpxchg-weak.ll index 1eac9c41cf92..4038528c91bc 100644 --- a/test/CodeGen/ARM/cmpxchg-weak.ll +++ b/test/CodeGen/ARM/cmpxchg-weak.ll @@ -6,11 +6,11 @@ define void @test_cmpxchg_weak(i32 *%addr, i32 %desired, i32 %new) { %pair = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic %oldval = extractvalue { i32, i1 } %pair, 0 ; CHECK-NEXT: BB#0: -; CHECK-NEXT: dmb ish ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r0] ; CHECK-NEXT: cmp [[LOADED]], r1 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: BB#1: +; CHECK-NEXT: dmb ish ; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r2, [r0] ; CHECK-NEXT: cmp [[SUCCESS]], #0 ; CHECK-NEXT: bne [[FAILBB:LBB[0-9]+_[0-9]+]] @@ -36,13 +36,13 @@ define i1 @test_cmpxchg_weak_to_bool(i32, i32 *%addr, i32 %desired, i32 %new) { %success = extractvalue { i32, i1 } %pair, 1 ; CHECK-NEXT: BB#0: -; CHECK-NEXT: dmb ish ; CHECK-NEXT: ldrex [[LOADED:r[0-9]+]], [r1] ; CHECK-NEXT: cmp [[LOADED]], r2 ; CHECK-NEXT: bne [[LDFAILBB:LBB[0-9]+_[0-9]+]] ; CHECK-NEXT: BB#1: -; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1] +; CHECK-NEXT: dmb ish ; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: strex [[SUCCESS:r[0-9]+]], r3, [r1] ; CHECK-NEXT: cmp [[SUCCESS]], #0 ; CHECK-NEXT: bxne lr ; CHECK-NEXT: dmb ish diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll index 4468f1ec9c42..cd45af338fde 100644 --- a/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -79,11 +79,10 @@ attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !15, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.4 (trunk 182024) (llvm/trunk 182023)", isOptimized: true, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !15, imports: !2) !1 = !DIFile(filename: "pr16110.c", directory: "/d/b") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, scopeLine: 7, file: !1, scope: !5, type: !6, variables: !9) +!4 = distinct !DISubprogram(name: "pr16110", line: 7, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: true, unit: !0, scopeLine: 7, file: !1, scope: !5, type: !6, variables: !9) !5 = !DIFile(filename: "pr16110.c", directory: "/d/b") !6 = !DISubroutineType(types: !7) !7 = !{!8} diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll index bf5cf52d8b54..8eaf3d5ab6b2 100644 --- a/test/CodeGen/ARM/code-placement.ll +++ b/test/CodeGen/ARM/code-placement.ll @@ -12,9 +12,9 @@ entry: br i1 %0, label %bb2, label %bb bb: -; CHECK: LBB0_1: -; CHECK: bne LBB0_1 -; CHECK-NOT: b LBB0_1 +; CHECK: LBB0_2: +; CHECK: bne LBB0_2 +; CHECK-NOT: b LBB0_2 ; CHECK: bx lr %list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ] %next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ] diff --git a/test/CodeGen/ARM/crash-greedy.ll b/test/CodeGen/ARM/crash-greedy.ll index a3d49f620e9c..6a58bb871d35 100644 --- a/test/CodeGen/ARM/crash-greedy.ll +++ b/test/CodeGen/ARM/crash-greedy.ll @@ -30,7 +30,7 @@ for.end: ; preds = %cond.end %call85 = tail call double @exp(double %mul84) nounwind %mul86 = fmul double %conv78, %call85 %add88 = fadd double 0.000000e+00, %mul86 -; CHECK: blx _exp +; CHECK: bl _exp %call100 = tail call double @exp(double %mul84) nounwind %mul101 = fmul double undef, %call100 %add103 = fadd double %add46, %mul101 diff --git a/test/CodeGen/ARM/cxx-tlscc.ll b/test/CodeGen/ARM/cxx-tlscc.ll index 11173bbb1978..5d017bbeebca 100644 --- a/test/CodeGen/ARM/cxx-tlscc.ll +++ b/test/CodeGen/ARM/cxx-tlscc.ll @@ -1,7 +1,12 @@ ; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 | FileCheck %s -; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 -enable-shrink-wrap=true | FileCheck --check-prefix=CHECK %s +; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 -enable-shrink-wrap=true | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-ios8.0 | FileCheck %s -; RUN: llc < %s -mtriple=armv7-apple-ios8.0 -enable-shrink-wrap=true | FileCheck --check-prefix=CHECK %s +; RUN: llc < %s -mtriple=armv7-apple-ios8.0 -enable-shrink-wrap=true | FileCheck %s + +; RUN: llc < %s -mtriple=armv7k-apple-watchos2.0 -O0 | FileCheck --check-prefix=CHECK-O0 --check-prefix=WATCH-O0 %s +; RUN: llc < %s -mtriple=armv7-apple-ios8.0 -O0 | FileCheck --check-prefix=CHECK-O0 --check-prefix=IOS-O0 %s + +; RUN: llc < %s -mtriple=thumbv7-apple-ios8.0 | FileCheck --check-prefix=THUMB %s %struct.S = type { i8 } @@ -10,10 +15,24 @@ @__tls_guard = internal thread_local unnamed_addr global i1 false @sum1 = internal thread_local global i32 0, align 4 +%class.C = type { i32 } +@tC = internal thread_local global %class.C zeroinitializer, align 4 + declare %struct.S* @_ZN1SC1Ev(%struct.S* returned) declare %struct.S* @_ZN1SD1Ev(%struct.S* returned) declare i32 @_tlv_atexit(void (i8*)*, i8*, i8*) +; Make sure Epilog does not overwrite an explicitly-handled CSR in CXX_FAST_TLS. +; THUMB-LABEL: _ZTW2sg +; THUMB: push {{.*}}lr +; THUMB: blx +; THUMB: bne [[TH_end:.?LBB0_[0-9]+]] +; THUMB: blx +; THUMB: tlv_atexit +; THUMB: [[TH_end]]: +; THUMB: blx +; THUMB: r4 +; THUMB: pop {{.*}}r4 define cxx_fast_tlscc nonnull %struct.S* @_ZTW2sg() nounwind { %.b.i = load i1, i1* @__tls_guard, align 1 br i1 %.b.i, label %__tls_init.exit, label %init.i @@ -29,14 +48,13 @@ __tls_init.exit: } ; CHECK-LABEL: _ZTW2sg -; CHECK: push {lr} -; CHECK-NOT: push {r1, r2, r3, r4, r7, lr} -; CHECK-NOT: push {r9, r12} +; CHECK: push {r4, r5, r7, lr} +; CHECK: push {r11, r12} ; CHECK-NOT: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} ; CHECK-NOT: vpush {d0, d1, d2, d3, d4, d5, d6, d7} ; CHECK: blx ; CHECK: bne [[BB_end:.?LBB0_[0-9]+]] -; CHECK; blx +; CHECK: blx ; CHECK: tlv_atexit ; CHECK: [[BB_end]]: ; CHECK: blx @@ -44,7 +62,25 @@ __tls_init.exit: ; CHECK-NOT: vpop {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} ; CHECK-NOT: pop {r9, r12} ; CHECK-NOT: pop {r1, r2, r3, r4, r7, pc} -; CHECK: pop {lr} +; CHECK: pop {r4, r5, r7, pc} + +; CHECK-O0-LABEL: _ZTW2sg +; WATCH-O0: push {r1, r2, r3, r6, r7, lr} +; IOS-O0: push {r1, r2, r3, r7, lr} +; CHECK-O0: push {r9, r12} +; CHECK-O0: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +; CHECK-O0: vpush {d0, d1, d2, d3, d4, d5, d6, d7} +; CHECK-O0: blx +; CHECK-O0: bne [[BB_end:.?LBB0_[0-9]+]] +; CHECK-O0: blx +; CHECK-O0: tlv_atexit +; CHECK-O0: [[BB_end]]: +; CHECK-O0: blx +; CHECK-O0: vpop {d0, d1, d2, d3, d4, d5, d6, d7} +; CHECK-O0: vpop {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} +; CHECK-O0: pop {r9, r12} +; WATCH-O0: pop {r1, r2, r3, r6, r7, pc} +; IOS-O0: pop {r1, r2, r3, r7, pc} ; CHECK-LABEL: _ZTW4sum1 ; CHECK-NOT: push {r1, r2, r3, r4, r7, lr} @@ -52,6 +88,65 @@ __tls_init.exit: ; CHECK-NOT: vpush {d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30, d31} ; CHECK-NOT: vpush {d0, d1, d2, d3, d4, d5, d6, d7} ; CHECK: blx + +; CHECK-O0-LABEL: _ZTW4sum1 +; CHECK-O0-NOT: vpush +; CHECK-O0-NOT: vstr +; CHECK-O0-NOT: vpop +; CHECK-O0-NOT: vldr +; CHECK-O0: pop define cxx_fast_tlscc nonnull i32* @_ZTW4sum1() nounwind { ret i32* @sum1 } + +; Make sure at O0, we don't generate spilling/reloading of the CSRs. +; CHECK-O0-LABEL: tls_test2 +; CHECK-O0: push +; CHECK-O0-NOT: vpush +; CHECK-O0-NOT: vstr +; CHECK-O0: tls_helper +; CHECK-O0-NOT: vpop +; CHECK-O0-NOT: vldr +; CHECK-O0: pop +declare cxx_fast_tlscc void @tls_helper() +define cxx_fast_tlscc %class.C* @tls_test2() #1 { + call cxx_fast_tlscc void @tls_helper() + ret %class.C* @tC +} + +; Make sure we do not allow tail call when caller and callee have different +; calling conventions. +declare %class.C* @_ZN1CD1Ev(%class.C* readnone returned %this) +; CHECK-LABEL: tls_test +; CHECK: bl __tlv_atexit +define cxx_fast_tlscc void @__tls_test() { +entry: + store i32 0, i32* getelementptr inbounds (%class.C, %class.C* @tC, i64 0, i32 0), align 4 + %0 = tail call i32 @_tlv_atexit(void (i8*)* bitcast (%class.C* (%class.C*)* @_ZN1CD1Ev to void (i8*)*), i8* bitcast (%class.C* @tC to i8*), i8* nonnull @__dso_handle) #1 + ret void +} + +declare void @somefunc() +define cxx_fast_tlscc void @test_ccmismatch_notail() { +; A tail call is not possible here because somefunc does not preserve enough +; registers. +; CHECK-LABEL: test_ccmismatch_notail: +; CHECK-NOT: b _somefunc +; CHECK: bl _somefunc + tail call void @somefunc() + ret void +} + +declare cxx_fast_tlscc void @some_fast_tls_func() +define void @test_ccmismatch_tail() { +; We can perform a tail call here because some_fast_tls_func preserves all +; necessary registers (and more). +; CHECK-LABEL: test_ccmismatch_tail: +; CHECK-NOT: bl _some_fast_tls_func +; CHECK: b _some_fast_tls_func + tail call cxx_fast_tlscc void @some_fast_tls_func() + ret void +} + +attributes #0 = { nounwind "no-frame-pointer-elim"="true" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll index 8b7153503b1f..206371a8f4e4 100644 --- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll +++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll @@ -19,12 +19,48 @@ define float @f(<4 x i16>* nocapture %in) { ret float %7 } +; CHECK-LABEL: g: define float @g(<4 x i16>* nocapture %in) { ; CHECK: vldr %1 = load <4 x i16>, <4 x i16>* %in - ; CHECK-NOT: uxth + + ; For now we're generating a vmov.16 and a uxth instruction. + ; The uxth is redundant, and we should be able to extend without + ; having to generate cross-domain copies. Once we can do this + ; we should modify the checks below. + + ; CHECK: uxth %2 = extractelement <4 x i16> %1, i32 0 ; CHECK: vcvt.f32.u32 %3 = uitofp i16 %2 to float ret float %3 } + +; The backend generates for the following code an +; (and 0xff (i32 extract_vector_elt (zext load <4 x i8> to 4 x i16))) +; +; The and is not redundant and cannot be removed. Since +; extract_vector_elt is doing an implicit any_ext, the and +; is required to guarantee that the top bits are set to zero. + +; Ideally should be a zext from <4 x i8> to <4 x 32>. + +; CHECK-LABEL: h: +; CHECK: vld1.32 +; CHECK: uxtb +define <4 x i32> @h(<4 x i8> *%in) { + %1 = load <4 x i8>, <4 x i8>* %in, align 4 + %2 = extractelement <4 x i8> %1, i32 0 + %3 = zext i8 %2 to i32 + %4 = insertelement <4 x i32> undef, i32 %3, i32 0 + %5 = extractelement <4 x i8> %1, i32 1 + %6 = zext i8 %5 to i32 + %7 = insertelement <4 x i32> %4, i32 %6, i32 1 + %8 = extractelement <4 x i8> %1, i32 2 + %9 = zext i8 %8 to i32 + %10 = insertelement <4 x i32> %7, i32 %9, i32 2 + %11 = extractelement <4 x i8> %1, i32 3 + %12 = zext i8 %11 to i32 + %13 = insertelement <4 x i32> %10, i32 %12, i32 3 + ret <4 x i32> %13 +} diff --git a/test/CodeGen/ARM/darwin-tls.ll b/test/CodeGen/ARM/darwin-tls.ll index e19953222020..1043cce6218b 100644 --- a/test/CodeGen/ARM/darwin-tls.ll +++ b/test/CodeGen/ARM/darwin-tls.ll @@ -10,6 +10,8 @@ @local_tls_var = thread_local global i32 0 @external_tls_var = external thread_local global i32 +@hidden_external_tls_var = external hidden thread_local global i32 + define i32 @test_local_tls() { ; T2-MOVT-PIC-LABEL: test_local_tls: @@ -163,3 +165,18 @@ define i32 @test_external_tls() { %val = load i32, i32* @external_tls_var, align 4 ret i32 %val } + +; Just need something to trigger an indirect reference to the var. +define i32 @use_hidden_external_tls() { + %val = load i32, i32* @hidden_external_tls_var, align 4 + ret i32 %val +} + +; T2-MOVT-PIC: .section __DATA,__thread_ptr,thread_local_variable_pointers +; T2-MOVT-PIC: .p2align 2 +; T2-MOVT-PIC: L_external_tls_var$non_lazy_ptr: +; T2-MOVT-PIC: .indirect_symbol _external_tls_var +; T2-MOVT-PIC: .long 0 +; T2-MOVT-PIC: L_hidden_external_tls_var$non_lazy_ptr: +; T2-MOVT-PIC: .indirect_symbol _hidden_external_tls_var +; T2-MOVT-PIC: .long 0 diff --git a/test/CodeGen/ARM/debug-frame-vararg.ll b/test/CodeGen/ARM/debug-frame-vararg.ll index 13ca20c20359..b9eae59cc320 100644 --- a/test/CodeGen/ARM/debug-frame-vararg.ll +++ b/test/CodeGen/ARM/debug-frame-vararg.ll @@ -25,11 +25,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) +!4 = distinct !DISubprogram(name: "sum", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "var.c", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} diff --git a/test/CodeGen/ARM/debug-frame.ll b/test/CodeGen/ARM/debug-frame.ll index 4bd401b68496..9b54a4a463d1 100644 --- a/test/CodeGen/ARM/debug-frame.ll +++ b/test/CodeGen/ARM/debug-frame.ll @@ -125,11 +125,10 @@ declare void @_ZSt9terminatev() !llvm.module.flags = !{!10, !11} !llvm.ident = !{!12} -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "exp.cpp", directory: "/tmp") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) +!4 = distinct !DISubprogram(name: "test", linkageName: "_Z4testiiiiiddddd", line: 4, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "exp.cpp", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{null, !8, !8, !8, !8, !8, !9, !9, !9, !9, !9} diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index bf7e7321ae3d..9dd820134dd4 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -32,8 +32,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!33} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: 1, file: !32, enums: !{}, retainedTypes: !{}, subprograms: !30, imports: null) -!1 = distinct !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 11, file: !2, scope: !2, type: !3, variables: !31) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", isOptimized: true, emissionKind: FullDebug, file: !32, enums: !{}, retainedTypes: !{}, imports: null) +!1 = distinct !DISubprogram(name: "foo", line: 11, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 11, file: !2, scope: !2, type: !3, variables: !31) !2 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") !3 = !DISubroutineType(types: !4) !4 = !{null} @@ -62,7 +62,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !27 = distinct !DILexicalBlock(line: 11, column: 107, file: !2, scope: !1) !28 = !DILocation(line: 13, column: 5, scope: !27) !29 = !DILocation(line: 14, column: 1, scope: !27) -!30 = !{!1} !31 = !{!5, !13, !14, !17, !18, !19} !32 = !DIFile(filename: "one.c", directory: "/Volumes/Athwagate/R10048772") !33 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index c628c5e9038d..1e9d890e9333 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -111,7 +111,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!162} -!0 = distinct !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: 1, file: !153, enums: !147, retainedTypes: !{}, subprograms: !148) +!0 = distinct !DICompileUnit(language: DW_LANG_ObjC, producer: "Apple clang version 2.1", isOptimized: false, runtimeVersion: 2, emissionKind: FullDebug, file: !153, enums: !147, retainedTypes: !{}) !1 = !DICompositeType(tag: DW_TAG_enumeration_type, line: 248, size: 32, align: 32, file: !160, scope: !0, elements: !3) !2 = !DIFile(filename: "header.h", directory: "/Volumes/Sandbox/llvm") !3 = !{!4} @@ -134,7 +134,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !20 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm") !21 = !{!22} !22 = !DIEnumerator(name: "Eleven", value: 0) ; [ DW_TAG_enumerator ] -!23 = distinct !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 609, file: !152, scope: !24, type: !25) +!23 = distinct !DISubprogram(name: "foobar_func_block_invoke_0", line: 609, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 609, file: !152, scope: !24, type: !25) !24 = !DIFile(filename: "MyLibrary.m", directory: "/Volumes/Sandbox/llvm") !25 = !DISubroutineType(types: !26) !26 = !{null} @@ -259,7 +259,6 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !145 = !DILocation(line: 613, column: 17, scope: !142) !146 = !DILocation(line: 615, column: 13, scope: !142) !147 = !{!1, !1, !5, !5, !9, !14, !19, !19, !14, !14, !14, !19, !19, !19} -!148 = !{!23} !149 = !DIFile(filename: "header3.h", directory: "/Volumes/Sandbox/llvm") !150 = !DIFile(filename: "Private.h", directory: "/Volumes/Sandbox/llvm") !151 = !DIFile(filename: "header4.h", directory: "/Volumes/Sandbox/llvm") diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index b9d110e42cd4..b4e48c4c423e 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -42,9 +42,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.module.flags = !{!56} !llvm.dbg.cu = !{!2} -!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !3, variables: !51) +!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, file: !54, scope: null, type: !3, variables: !51) !1 = !DIFile(filename: "build2.c", directory: "/private/tmp") -!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: FullDebug, file: !54, enums: !{}, retainedTypes: !{}, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) @@ -52,11 +52,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} !9 = !DISubrange(count: 4) -!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !54, scope: null, type: !11, variables: !52) +!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, file: !54, scope: null, type: !11, variables: !52) !11 = !DISubroutineType(types: !12) !12 = !{!13} !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, file: !55, scope: null, type: !16, variables: !53) +!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, file: !55, scope: null, type: !16, variables: !53) !15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") !16 = !DISubroutineType(types: !17) !17 = !{null} @@ -92,7 +92,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !47 = distinct !DILexicalBlock(line: 41, column: 28, file: !15, scope: !14) !48 = !DILocation(line: 95, column: 3, scope: !25) !49 = !DILocation(line: 99, column: 3, scope: !25) -!50 = !{!0, !10, !14} !51 = !{!18} !52 = !{!19, !20, !24, !26, !27, !28, !29} !53 = !{!30} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 0d457d3a7371..46146c7b8bf5 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -59,17 +59,17 @@ declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!48} -!0 = distinct !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !46, scope: !1, type: !3, variables: !43) +!0 = distinct !DISubprogram(name: "printer", linkageName: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 12, file: !46, scope: !1, type: !3, variables: !43) !1 = !DIFile(filename: "a.c", directory: "/tmp/") -!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: 1, file: !46, enums: !47, retainedTypes: !47, subprograms: !42, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C89, producer: "(LLVM build 00)", isOptimized: true, emissionKind: FullDebug, file: !46, enums: !47, retainedTypes: !47, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5, !6, !7, !8} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) !6 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: null) !7 = !DIBasicType(tag: DW_TAG_base_type, name: "double", size: 64, align: 32, encoding: DW_ATE_float) !8 = !DIBasicType(tag: DW_TAG_base_type, name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) -!9 = distinct !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !46, scope: !1, type: !3, variables: !44) -!10 = distinct !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !46, scope: !1, type: !11, variables: !45) +!9 = distinct !DISubprogram(name: "inlineprinter", linkageName: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 5, file: !46, scope: !1, type: !3, variables: !44) +!10 = distinct !DISubprogram(name: "main", linkageName: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 18, file: !46, scope: !1, type: !11, variables: !45) !11 = !DISubroutineType(types: !12) !12 = !{!5, !5, !13} !13 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, file: !46, scope: !1, baseType: !14) @@ -106,7 +106,6 @@ declare i32 @puts(i8* nocapture) nounwind !39 = !DILocation(line: 6, scope: !28, inlinedAt: !37) !40 = !DILocation(line: 22, scope: !25) !41 = !DILocation(line: 23, scope: !25) -!42 = !{!0, !9, !10} !43 = !{!16, !17, !18} !44 = !{!19, !20, !21} !45 = !{!22, !23, !24} diff --git a/test/CodeGen/ARM/debug-info-no-frame.ll b/test/CodeGen/ARM/debug-info-no-frame.ll index d77a195b9528..861c4ecefa98 100644 --- a/test/CodeGen/ARM/debug-info-no-frame.ll +++ b/test/CodeGen/ARM/debug-info-no-frame.ll @@ -21,10 +21,10 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!7, !8} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !{!3}) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, emissionKind: FullDebug) !1 = !DIFile(filename: "file.c", directory: "/dir") !2 = !{} -!3 = distinct !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, variables: !2) +!3 = distinct !DISubprogram(name: "need_cfi_def_cfa_offset", scope: !1, file: !1, line: 1, type: !4, isLocal: false, isDefinition: true, scopeLine: 2, isOptimized: false, unit: !0, variables: !2) !4 = !DISubroutineType(types: !5) !5 = !{null} !6 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index 1cd90d433640..581b3e915ef1 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -38,9 +38,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!56} -!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 3, file: !54, scope: !1, type: !3, variables: !51) +!0 = distinct !DISubprogram(name: "test0001", line: 3, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 3, file: !54, scope: !1, type: !3, variables: !51) !1 = !DIFile(filename: "build2.c", directory: "/private/tmp") -!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !54, enums: !{}, retainedTypes: !{}, subprograms: !50, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: FullDebug, file: !54, enums: !{}, retainedTypes: !{}, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIDerivedType(tag: DW_TAG_typedef, name: "v4f32", line: 14, file: !54, scope: !2, baseType: !6) @@ -48,11 +48,11 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !7 = !DIBasicType(tag: DW_TAG_base_type, name: "float", size: 32, align: 32, encoding: DW_ATE_float) !8 = !{!9} !9 = !DISubrange(count: 4) -!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 59, file: !54, scope: !1, type: !11, variables: !52) +!10 = distinct !DISubprogram(name: "main", line: 59, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 59, file: !54, scope: !1, type: !11, variables: !52) !11 = !DISubroutineType(types: !12) !12 = !{!13} !13 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53) +!14 = distinct !DISubprogram(name: "printFV", line: 41, isLocal: true, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 41, file: !55, scope: !15, type: !16, variables: !53) !15 = !DIFile(filename: "/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", directory: "/private/tmp") !16 = !DISubroutineType(types: !17) !17 = !{null} @@ -88,7 +88,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !47 = distinct !DILexicalBlock(line: 41, column: 28, file: !55, scope: !14) !48 = !DILocation(line: 95, column: 3, scope: !25) !49 = !DILocation(line: 99, column: 3, scope: !25) -!50 = !{!0, !10, !14} !51 = !{!18} !52 = !{!19, !20, !24, !26, !27, !28, !29} !53 = !{!30} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index 654aa4545ca4..2987b9a2105a 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -65,14 +65,14 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!53} -!0 = distinct !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !51, scope: !1, type: !3, variables: !48) +!0 = distinct !DISubprogram(name: "inlineprinter", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 5, file: !51, scope: !1, type: !3, variables: !48) !1 = !DIFile(filename: "a.c", directory: "/private/tmp") -!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: 1, file: !51, enums: !52, retainedTypes: !52, subprograms: !47, imports: null) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.0 (trunk 129915)", isOptimized: true, emissionKind: FullDebug, file: !51, enums: !52, retainedTypes: !52, imports: null) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) -!6 = distinct !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 12, file: !51, scope: !1, type: !3, variables: !49) -!7 = distinct !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 18, file: !51, scope: !1, type: !3, variables: !50) +!6 = distinct !DISubprogram(name: "printer", line: 12, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 12, file: !51, scope: !1, type: !3, variables: !49) +!7 = distinct !DISubprogram(name: "main", line: 18, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !2, scopeLine: 18, file: !51, scope: !1, type: !3, variables: !50) !8 = !DILocalVariable(name: "ptr", line: 4, arg: 1, scope: !0, file: !1, type: !9) !9 = !DIDerivedType(tag: DW_TAG_pointer_type, size: 32, align: 32, scope: !2, baseType: null) !10 = !DILocalVariable(name: "val", line: 4, arg: 2, scope: !0, file: !1, type: !11) @@ -117,7 +117,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !44 = !DILocation(line: 6, column: 3, scope: !28, inlinedAt: !40) !45 = !DILocation(line: 22, column: 3, scope: !23) !46 = !DILocation(line: 23, column: 1, scope: !23) -!47 = !{!0, !6, !7} !48 = !{!8, !10, !12} !49 = !{!14, !15, !16} !50 = !{!17, !18, !22} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index eadf1b48156b..b31d1b7bed4f 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -43,8 +43,8 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!20} -!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: 1, file: !18, enums: !19, retainedTypes: !19, subprograms: !16, imports: null) -!1 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 5, file: !18, scope: !2, type: !3, variables: !17) +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, producer: "clang version 3.0 (trunk 130845)", isOptimized: true, emissionKind: FullDebug, file: !18, enums: !19, retainedTypes: !19, imports: null) +!1 = distinct !DISubprogram(name: "foo", linkageName: "_Z3foov", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 5, file: !18, scope: !2, type: !3, variables: !17) !2 = !DIFile(filename: "k.cc", directory: "/private/tmp") !3 = !DISubroutineType(types: !4) !4 = !{null} @@ -59,7 +59,6 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !13 = !DILocation(line: 8, column: 20, scope: !9) !14 = !DILocation(line: 7, column: 20, scope: !10) !15 = !DILocation(line: 10, column: 1, scope: !6) -!16 = !{!1} !17 = !{!5, !8} !18 = !DIFile(filename: "k.cc", directory: "/private/tmp") !19 = !{} diff --git a/test/CodeGen/ARM/debug-segmented-stacks.ll b/test/CodeGen/ARM/debug-segmented-stacks.ll index bd0abedc4133..3aa33f754118 100644 --- a/test/CodeGen/ARM/debug-segmented-stacks.ll +++ b/test/CodeGen/ARM/debug-segmented-stacks.ll @@ -39,11 +39,10 @@ define void @test_basic() #0 !dbg !4 { ; ARM-linux .cfi_same_value r5 } -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: 0, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "var.c", directory: "/tmp") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) +!4 = distinct !DISubprogram(name: "test_basic", line: 5, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: false, unit: !0, scopeLine: 5, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "var.c", directory: "/tmp") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} diff --git a/test/CodeGen/ARM/debugtrap.ll b/test/CodeGen/ARM/debugtrap.ll index 3d8cdea6cdae..5064a4ec2ca9 100644 --- a/test/CodeGen/ARM/debugtrap.ll +++ b/test/CodeGen/ARM/debugtrap.ll @@ -10,7 +10,7 @@ define void @test() nounwind { entry: ; CHECK: bl foo ; CHECK-NEXT: pop - ; CHECK-NEXT: trap + ; CHECK-NEXT: .inst 0xe7ffdefe call void @foo() call void @llvm.debugtrap() ret void diff --git a/test/CodeGen/ARM/default-float-abi.ll b/test/CodeGen/ARM/default-float-abi.ll index 1b26bbdd9259..78d79def82cf 100644 --- a/test/CodeGen/ARM/default-float-abi.ll +++ b/test/CodeGen/ARM/default-float-abi.ll @@ -1,7 +1,10 @@ ; RUN: llc -mtriple=armv7-linux-gnueabihf %s -o - | FileCheck %s --check-prefix=CHECK-HARD +; RUN: llc -mtriple=armv7-linux-musleabihf %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=armv7-linux-eabihf %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=armv7-linux-gnueabihf -float-abi=soft %s -o - | FileCheck %s --check-prefix=CHECK-SOFT +; RUN: llc -mtriple=armv7-linux-musleabihf -float-abi=soft %s -o - | FileCheck %s --check-prefix=CHECK-SOFT ; RUN: llc -mtriple=armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=CHECK-SOFT +; RUN: llc -mtriple=armv7-linux-musleabi %s -o - | FileCheck %s --check-prefix=CHECK-SOFT ; RUN: llc -mtriple=armv7-linux-eabi -float-abi=hard %s -o - | FileCheck %s --check-prefix=CHECK-HARD ; RUN: llc -mtriple=thumbv7-apple-ios6.0 %s -o - | FileCheck %s --check-prefix=CHECK-SOFT diff --git a/test/CodeGen/ARM/default-reloc.ll b/test/CodeGen/ARM/default-reloc.ll new file mode 100644 index 000000000000..0b80b73061bc --- /dev/null +++ b/test/CodeGen/ARM/default-reloc.ll @@ -0,0 +1,5 @@ +; RUN: llc -mtriple=armv7-linux-gnu -O0 < %s +@a = external global i32 +define i32* @get() { + ret i32* @a +} diff --git a/test/CodeGen/ARM/divmod-eabi.ll b/test/CodeGen/ARM/divmod-eabi.ll index 4178af397e66..1e4c8fc336da 100644 --- a/test/CodeGen/ARM/divmod-eabi.ll +++ b/test/CodeGen/ARM/divmod-eabi.ll @@ -1,16 +1,33 @@ +; We run the tests with both the default optimization level and O0, to make sure +; we don't have any ABI differences between them. In principle, the ABI checks +; should be the same for both optimization levels (there could be exceptions +; from this when a div and a mod with the same operands are not coallesced into +; the same divmod, but luckily this doesn't occur in practice even at O0). +; Sometimes the checks that the correct registers are used after the libcalls +; are different between optimization levels, so we have to separate them. ; RUN: llc -mtriple armv7-none-eabi %s -o - | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-none-eabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI ; RUN: llc -mtriple armv7-none-eabihf %s -o - | FileCheck %s --check-prefix=EABI -; Both "none-eabi" and "androideabi" must lower SREM/UREM to __aeabi_{u,i}divmod +; RUN: llc -mtriple armv7-none-eabihf %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI +; All "eabi" (Bare, GNU and Android) must lower SREM/UREM to __aeabi_{u,i}divmod ; RUN: llc -mtriple armv7-linux-androideabi %s -o - | FileCheck %s --check-prefix=EABI -; RUN: llc -mtriple armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=GNU -; RUN: llc -mtriple armv7-apple-darwin %s -o - | FileCheck %s --check-prefix=DARWIN +; RUN: llc -mtriple armv7-linux-androideabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-linux-gnueabi %s -o - | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-linux-gnueabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-linux-musleabi %s -o - | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-linux-musleabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefix=EABI +; RUN: llc -mtriple armv7-apple-darwin %s -o - | FileCheck %s --check-prefixes=DARWIN,DARWIN-DEFAULT +; RUN: llc -mtriple armv7-apple-darwin %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefixes=DARWIN,DARWIN-O0 ; FIXME: long-term, we will use "-apple-macho" and won't need this exception: -; RUN: llc -mtriple armv7-apple-darwin-eabi %s -o - | FileCheck %s --check-prefix=DARWIN +; RUN: llc -mtriple armv7-apple-darwin-eabi %s -o - | FileCheck %s --check-prefixes=DARWIN,DARWIN-DEFAULT +; RUN: llc -mtriple armv7-apple-darwin-eabi %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefixes=DARWIN,DARWIN-O0 +; RUN: llc -mtriple thumbv7-windows %s -o - | FileCheck %s --check-prefixes=WINDOWS,WINDOWS-DEFAULT +; RUN: llc -mtriple thumbv7-windows %s -o - -O0 -optimize-regalloc | FileCheck %s --check-prefixes=WINDOWS,WINDOWS-O0 define signext i16 @f16(i16 signext %a, i16 signext %b) { ; EABI-LABEL: f16: -; GNU-LABEL: f16: ; DARWIN-LABEL: f16: +; WINDOWS-LABEL: f16: entry: %conv = sext i16 %a to i32 %conv1 = sext i16 %b to i32 @@ -19,189 +36,238 @@ entry: ; EABI: __aeabi_idivmod ; EABI: mov [[div:r[0-9]+]], r0 ; EABI: mov [[rem:r[0-9]+]], r1 -; GNU: __aeabi_idiv -; GNU: mov [[sum:r[0-9]+]], r0 -; GNU: __modsi3 -; GNU: add [[sum]]{{.*}}r0 ; DARWIN: ___divsi3 -; DARWIN: mov [[sum:r[0-9]+]], r0 +; DARWIN: mov [[div:r[0-9]+]], r0 ; DARWIN: __modsi3 -; DARWIN: add [[sum]]{{.*}}r0 +; DARWIN-DEFAULT: add [[sum:r[0-9]+]], r0, [[div]] +; DARWIN-O0: mov [[rem:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS-DEFAULT: mls [[rem:r[0-9]+]], r0, +; WINDOWS-DEFAULT: adds [[sum:r[0-9]+]], [[rem]], r0 +; WINDOWS-O0: mov [[div:r[0-9]+]], r0 +; WINDOWS-O0: mls [[rem:r[0-9]+]], [[div]], %rem8 = srem i32 %conv1, %conv ; EABI: __aeabi_idivmod -; GNU: __modsi3 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem1:r[0-9]+]], r0, %add = add nsw i32 %rem, %div %add13 = add nsw i32 %add, %rem8 %conv14 = trunc i32 %add13 to i16 ; EABI: add r0{{.*}}r1 ; EABI: sxth r0, r0 -; GNU: add r0{{.*}}[[sum]] -; GNU: sxth r0, r0 -; DARWIN: add r0{{.*}}[[sum]] -; DARWIN: sxth r0, r0 +; DARWIN-DEFAULT: add [[res:r[0-9]+]], [[sum]], r0 +; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]] +; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0 +; DARWIN: sxth r0, [[res]] +; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]] +; WINDOWS: add [[rem1]], [[sum]] +; WINDOWS: sxth [[res:r[0-9]+]], [[rem1]] ret i16 %conv14 } define i32 @f32(i32 %a, i32 %b) { ; EABI-LABEL: f32: -; GNU-LABEL: f32: ; DARWIN-LABEL: f32: +; WINDOWS-LABEL: f32: entry: %div = sdiv i32 %a, %b %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod ; EABI: mov [[div:r[0-9]+]], r0 ; EABI: mov [[rem:r[0-9]+]], r1 -; GNU: __aeabi_idiv -; GNU: mov [[sum:r[0-9]+]], r0 -; GNU: __modsi3 -; GNU: add [[sum]]{{.*}}r0 ; DARWIN: ___divsi3 -; DARWIN: mov [[sum:r[0-9]+]], r0 +; DARWIN: mov [[div:r[0-9]+]], r0 ; DARWIN: __modsi3 -; DARWIN: add [[sum]]{{.*}}r0 +; DARWIN-DEFAULT: add [[sum:r[0-9]+]], r0, [[div]] +; DARWIN-O0: mov [[rem:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mov [[div:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, +; WINDOWS-DEFAULT: add [[div]], [[rem]] %rem1 = srem i32 %b, %a ; EABI: __aeabi_idivmod -; GNU: __modsi3 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem1:r[0-9]+]], r0, %add = add nsw i32 %rem, %div %add2 = add nsw i32 %add, %rem1 ; EABI: add r0{{.*}}r1 -; GNU: add r0{{.*}}[[sum]] -; DARWIN: add r0{{.*}}[[sum]] +; DARWIN-DEFAULT: add r0, [[sum]], r0 +; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]] +; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0 +; WINDOWS-DEFAULT: add [[rem1]], [[div]] +; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]] +; WINDOWS-O0: add [[rem1]], [[sum]] ret i32 %add2 } define i32 @uf(i32 %a, i32 %b) { ; EABI-LABEL: uf: -; GNU-LABEL: uf: ; DARWIN-LABEL: uf: +; WINDOWS-LABEL: uf: entry: %div = udiv i32 %a, %b %rem = urem i32 %a, %b ; EABI: __aeabi_uidivmod -; GNU: __aeabi_uidiv -; GNU: mov [[sum:r[0-9]+]], r0 -; GNU: __umodsi3 -; GNU: add [[sum]]{{.*}}r0 ; DARWIN: ___udivsi3 -; DARWIN: mov [[sum:r[0-9]+]], r0 +; DARWIN: mov [[div:r[0-9]+]], r0 ; DARWIN: __umodsi3 -; DARWIN: add [[sum]]{{.*}}r0 +; DARWIN-DEFAULT: add [[sum:r[0-9]+]], r0, [[div]] +; DARWIN-O0: mov [[rem:r[0-9]+]], r0 +; WINDOWS: __rt_udiv +; WINDOWS: mov [[div:r[0-9]+]], r0 +; WINDOWS: __rt_udiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, +; WINDOWS-DEFAULT: add [[div]], [[rem]] %rem1 = urem i32 %b, %a ; EABI: __aeabi_uidivmod -; GNU: __umodsi3 ; DARWIN: __umodsi3 +; WINDOWS: __rt_udiv +; WINDOWS: mls [[rem1:r[0-9]+]], r0, %add = add nuw i32 %rem, %div %add2 = add nuw i32 %add, %rem1 ; EABI: add r0{{.*}}r1 -; GNU: add r0{{.*}}[[sum]] -; DARWIN: add r0{{.*}}[[sum]] +; DARWIN-DEFAULT: add r0, [[sum]], r0 +; DARWIN-O0: add [[sum:r[0-9]+]], [[rem]], [[div]] +; DARWIN-O0: add [[res:r[0-9]+]], [[sum]], r0 +; WINDOWS-DEFAULT: add [[rem1]], [[div]] +; WINDOWS-O0: adds [[sum:r[0-9]+]], [[rem]], [[div]] +; WINDOWS-O0: add [[rem1]], [[sum]] ret i32 %add2 } -; FIXME: AEABI is not lowering long u/srem into u/ldivmod define i64 @longf(i64 %a, i64 %b) { ; EABI-LABEL: longf: -; GNU-LABEL: longf: ; DARWIN-LABEL: longf: +; WINDOWS-LABEL: longf: entry: %div = sdiv i64 %a, %b %rem = srem i64 %a, %b ; EABI: __aeabi_ldivmod -; GNU: __aeabi_ldivmod -; GNU: mov [[div1:r[0-9]+]], r0 -; GNU: mov [[div2:r[0-9]+]], r1 +; EABI-NEXT: adds r0 +; EABI-NEXT: adc r1 +; EABI-NOT: __aeabi_ldivmod ; DARWIN: ___divdi3 ; DARWIN: mov [[div1:r[0-9]+]], r0 ; DARWIN: mov [[div2:r[0-9]+]], r1 ; DARWIN: __moddi3 +; WINDOWS: __rt_sdiv64 +; WINDOWS: mov [[div1:r[0-9]+]], r0 +; WINDOWS: mov [[div2:r[0-9]+]], r1 +; WINDOWS: __moddi3 %add = add nsw i64 %rem, %div -; GNU: adds r0{{.*}}[[div1]] -; GNU: adc r1{{.*}}[[div2]] ; DARWIN: adds r0{{.*}}[[div1]] ; DARWIN: adc r1{{.*}}[[div2]] +; WINDOWS: adds.w r0, r0, [[div1]] +; WINDOWS: adc.w r1, r1, [[div2]] ret i64 %add } +define i16 @shortf(i16 %a, i16 %b) { +; EABI-LABEL: shortf: +; DARWIN-LABEL: shortf: +; WINDOWS-LABEL: shortf: +entry: + %div = sdiv i16 %a, %b + %rem = srem i16 %a, %b +; EABI: __aeabi_idivmod +; DARWIN: ___divsi3 +; DARWIN: mov [[div1:r[0-9]+]], r0 +; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mov [[div:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, + %add = add nsw i16 %rem, %div +; EABI: add r0, r1 +; DARWIN: add r0{{.*}}[[div1]] +; WINDOWS: add [[rem]], [[div]] + ret i16 %add +} + define i32 @g1(i32 %a, i32 %b) { ; EABI-LABEL: g1: -; GNU-LABEL: g1: ; DARWIN-LABEL: g1: +; WINDOWS-LABEL: g1: entry: %div = sdiv i32 %a, %b %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod -; GNU: __aeabi_idiv -; GNU: mov [[sum:r[0-9]+]], r0 -; GNU: __modsi3 ; DARWIN: ___divsi3 ; DARWIN: mov [[sum:r[0-9]+]], r0 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mov [[div:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, %add = add nsw i32 %rem, %div ; EABI: add r0{{.*}}r1 -; GNU: add r0{{.*}}[[sum]] ; DARWIN: add r0{{.*}}[[sum]] +; WINDOWS: add [[rem]], [[div]] ret i32 %add } ; On both Darwin and Gnu, this is just a call to __modsi3 define i32 @g2(i32 %a, i32 %b) { ; EABI-LABEL: g2: -; GNU-LABEL: g2: ; DARWIN-LABEL: g2: +; WINDOWS-LABEL: g2: entry: %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod -; GNU: __modsi3 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv ret i32 %rem ; EABI: mov r0, r1 +; WINDOWS: mls r0, r0, } define i32 @g3(i32 %a, i32 %b) { ; EABI-LABEL: g3: -; GNU-LABEL: g3: ; DARWIN-LABEL: g3: +; WINDOWS-LABEL: g3: entry: %rem = srem i32 %a, %b ; EABI: __aeabi_idivmod ; EABI: mov [[mod:r[0-9]+]], r1 -; GNU: __modsi3 -; GNU: mov [[sum:r[0-9]+]], r0 ; DARWIN: __modsi3 ; DARWIN: mov [[sum:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, %rem1 = srem i32 %b, %rem ; EABI: __aeabi_idivmod -; GNU: __modsi3 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem1:r[0-9]+]], r0, %add = add nsw i32 %rem1, %rem ; EABI: add r0, r1, [[mod]] -; GNU: add r0{{.*}}[[sum]] ; DARWIN: add r0{{.*}}[[sum]] +; WINDOWS: add [[rem1]], [[rem]] ret i32 %add } define i32 @g4(i32 %a, i32 %b) { ; EABI-LABEL: g4: -; GNU-LABEL: g4: ; DARWIN-LABEL: g4: +; WINDOWS-LABEL: g4: entry: %div = sdiv i32 %a, %b ; EABI: __aeabi_idiv{{$}} ; EABI: mov [[div:r[0-9]+]], r0 -; GNU: __aeabi_idiv -; GNU: mov [[sum:r[0-9]+]], r0 ; DARWIN: ___divsi3 ; DARWIN: mov [[sum:r[0-9]+]], r0 +; WINDOWS: __rt_sdiv +; WINDOWS: mov [[div:r[0-9]+]], r0 %rem = srem i32 %b, %div ; EABI: __aeabi_idivmod -; GNU: __modsi3 ; DARWIN: __modsi3 +; WINDOWS: __rt_sdiv +; WINDOWS: mls [[rem:r[0-9]+]], r0, %add = add nsw i32 %rem, %div ; EABI: add r0, r1, [[div]] -; GNU: add r0{{.*}}[[sum]] ; DARWIN: add r0{{.*}}[[sum]] +; WINDOWS: add [[rem]], [[div]] ret i32 %add } diff --git a/test/CodeGen/ARM/eh-resume-darwin.ll b/test/CodeGen/ARM/eh-resume-darwin.ll index d3a8481275f3..6c2716bffa6d 100644 --- a/test/CodeGen/ARM/eh-resume-darwin.ll +++ b/test/CodeGen/ARM/eh-resume-darwin.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=IOS -; RUN: llc < %s -mtriple=armv7k-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=IOS -; RUN: llc < %s -mtriple=armv7k-apple-watchos -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=WATCHOS +; RUN: llc < %s -mtriple=armv7-apple-watchos -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=IOS +; RUN: llc < %s -mtriple=armv7k-apple-ios -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=WATCHABI +; RUN: llc < %s -mtriple=armv7k-apple-watchos -arm-atomic-cfg-tidy=0 | FileCheck %s -check-prefix=WATCHABI declare void @func() @@ -21,4 +22,4 @@ lpad: } ; IOS: __Unwind_SjLj_Resume -; WATCHOS: __Unwind_Resume +; WATCHABI: __Unwind_Resume diff --git a/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll b/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll index 3d380bf8f22a..517d5597bb28 100644 --- a/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll +++ b/test/CodeGen/ARM/ehabi-handlerdata-nounwind.ll @@ -42,7 +42,7 @@ try.cont: } ; CHECK: .globl test1 -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK: .type test1,%function ; CHECK-LABEL: test1: ; CHECK: .fnstart @@ -51,7 +51,7 @@ try.cont: ; CHECK: .personality __gxx_personality_v0 ; CHECK: .handlerdata -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK-LABEL: GCC_except_table0: ; CHECK-LABEL: .Lexception0: ; CHECK: .byte 255 @ @LPStart Encoding = omit diff --git a/test/CodeGen/ARM/ehabi-handlerdata.ll b/test/CodeGen/ARM/ehabi-handlerdata.ll index c53b36ffe18f..ecb23c3424e2 100644 --- a/test/CodeGen/ARM/ehabi-handlerdata.ll +++ b/test/CodeGen/ARM/ehabi-handlerdata.ll @@ -40,13 +40,13 @@ try.cont: } ; CHECK: .globl test1 -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK: .type test1,%function ; CHECK-LABEL: test1: ; CHECK: .fnstart ; CHECK: .personality __gxx_personality_v0 ; CHECK: .handlerdata -; CHECK: .align 2 +; CHECK: .p2align 2 ; CHECK-LABEL: GCC_except_table0: ; CHECK-LABEL: .Lexception0: ; CHECK: .byte 255 @ @LPStart Encoding = omit diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll index 923cffcf6532..e2984de9ce4d 100644 --- a/test/CodeGen/ARM/ehabi.ll +++ b/test/CodeGen/ARM/ehabi.ll @@ -34,6 +34,22 @@ ; RUN: -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM +; RUN: llc -mtriple arm-unknown-linux-musleabi \ +; RUN: -disable-fp-elim -filetype=asm -o - %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-FP + +; RUN: llc -mtriple arm-unknown-linux-musleabi \ +; RUN: -filetype=asm -o - %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM + +; RUN: llc -mtriple armv7-unknown-linux-musleabi \ +; RUN: -disable-fp-elim -filetype=asm -o - %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP + +; RUN: llc -mtriple armv7-unknown-linux-musleabi \ +; RUN: -filetype=asm -o - %s \ +; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM + ; RUN: llc -mtriple arm-unknown-linux-androideabi \ ; RUN: -disable-fp-elim -filetype=asm -o - %s \ ; RUN: | FileCheck %s --check-prefix=CHECK-FP diff --git a/test/CodeGen/ARM/emutls.ll b/test/CodeGen/ARM/emutls.ll index 7ba50dd249bb..e66d93ebcb89 100644 --- a/test/CodeGen/ARM/emutls.ll +++ b/test/CodeGen/ARM/emutls.ll @@ -11,8 +11,9 @@ define i32 @my_get_xyz() { ; ARM32-LABEL: my_get_xyz: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl my_emutls_get_address(PLT) +; ARM32-NEXT: bl my_emutls_get_address ; ARM32-NEXT: ldr r0, [r0] +; ARM32: .long my_emutls_v_xyz(GOT_PREL) entry: %call = call i8* @my_emutls_get_address(i8* bitcast (i8** @my_emutls_v_xyz to i8*)) @@ -33,8 +34,9 @@ define i32 @f1() { ; ARM32-LABEL: f1: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldr r0, [r0] +; ARM32: .long __emutls_v.i1(GOT_PREL) entry: %tmp1 = load i32, i32* @i1 @@ -45,8 +47,9 @@ define i32* @f2() { ; ARM32-LABEL: f2: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: pop +; ARM32: .long __emutls_v.i1(GOT_PREL) entry: ret i32* @i1 @@ -56,8 +59,9 @@ define i32 @f3() nounwind { ; ARM32-LABEL: f3: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldr r0, [r0] +; ARM32: .long __emutls_v.i2(GOT_PREL) entry: %tmp1 = load i32, i32* @i2 @@ -68,8 +72,9 @@ define i32* @f4() { ; ARM32-LABEL: f4: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: pop +; ARM32: .long __emutls_v.i2(GOT_PREL) entry: ret i32* @i2 @@ -78,9 +83,10 @@ entry: define i32 @f5() nounwind { ; ARM32-LABEL: f5: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldr r0, [r0] +; ARM32: .long __emutls_v.i3- entry: %tmp1 = load i32, i32* @i3 @@ -90,9 +96,10 @@ entry: define i32* @f6() { ; ARM32-LABEL: f6: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: pop +; ARM32: .long __emutls_v.i3- entry: ret i32* @i3 @@ -101,9 +108,10 @@ entry: define i32 @f7() { ; ARM32-LABEL: f7: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldr r0, [r0] +; ARM32: .long __emutls_v.i4-(.LPC entry: %tmp1 = load i32, i32* @i4 @@ -113,9 +121,10 @@ entry: define i32* @f8() { ; ARM32-LABEL: f8: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: pop +; ARM32: .long __emutls_v.i4-(.LPC entry: ret i32* @i4 @@ -124,8 +133,8 @@ entry: define i32 @f9() { ; ARM32-LABEL: f9: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldr r0, [r0] entry: @@ -136,8 +145,8 @@ entry: define i32* @f10() { ; ARM32-LABEL: f10: ; ARM32: ldr r0, -; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32: add r0, pc, r0 +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: pop entry: @@ -148,7 +157,7 @@ define i16 @f11() { ; ARM32-LABEL: f11: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldrh r0, [r0] entry: @@ -160,7 +169,7 @@ define i32 @f12() { ; ARM32-LABEL: f12: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldrsh r0, [r0] entry: @@ -173,7 +182,7 @@ define i8 @f13() { ; ARM32-LABEL: f13: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldrb r0, [r0] ; ARM32-NEXT: pop @@ -186,7 +195,7 @@ define i32 @f14() { ; ARM32-LABEL: f14: ; ARM32: ldr r0, ; ARM32: ldr r0, [pc, r0] -; ARM32-NEXT: bl __emutls_get_address(PLT) +; ARM32-NEXT: bl __emutls_get_address ; ARM32-NEXT: ldrsb r0, [r0] ; ARM32-NEXT: pop @@ -198,46 +207,50 @@ entry: ;;;;;;;;;;;;;; 32-bit __emutls_v. and __emutls_t. -; ARM32 .section .data.rel.local, +; ARM32: .data{{$}} +; ARM32: .globl __emutls_v.i1 ; ARM32-LABEL: __emutls_v.i1: ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 0 ; ARM32-NEXT: .long __emutls_t.i1 -; ARM32 .section .rodata, +; ARM32: .section .rodata, ; ARM32-LABEL: __emutls_t.i1: ; ARM32-NEXT: .long 15 ; ARM32-NOT: __emutls_v.i2 -; ARM32 .section .data.rel.local, +; ARM32: .data{{$}} +; ARM32-NOT: .globl ; ARM32-LABEL: __emutls_v.i3: ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 0 ; ARM32-NEXT: .long __emutls_t.i3 -; ARM32 .section .rodata, +; ARM32: .section .rodata, ; ARM32-LABEL: __emutls_t.i3: ; ARM32-NEXT: .long 15 -; ARM32 .section .data.rel.local, +; ARM32: .data{{$}} +; ARM32: .globl __emutls_v.i4 ; ARM32-LABEL: __emutls_v.i4: ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 4 ; ARM32-NEXT: .long 0 ; ARM32-NEXT: .long __emutls_t.i4 -; ARM32 .section .rodata, +; ARM32: .section .rodata, ; ARM32-LABEL: __emutls_t.i4: ; ARM32-NEXT: .long 15 ; ARM32-NOT: __emutls_v.i5: -; ARM32 .hidden __emutls_v.i5 +; ARM32: .hidden __emutls_v.i5 ; ARM32-NOT: __emutls_v.i5: -; ARM32 .section .data.rel.local, +; ARM32: .data{{$}} +; ARM32: .globl __emutls_v.s1 ; ARM32-LABEL: __emutls_v.s1: ; ARM32-NEXT: .long 2 ; ARM32-NEXT: .long 2 @@ -248,7 +261,8 @@ entry: ; ARM32-LABEL: __emutls_t.s1: ; ARM32-NEXT: .short 15 -; ARM32 .section .data.rel.local, +; ARM32: .data{{$}} +; ARM32: .globl __emutls_v.b1 ; ARM32-LABEL: __emutls_v.b1: ; ARM32-NEXT: .long 1 ; ARM32-NEXT: .long 1 diff --git a/test/CodeGen/ARM/emutls_generic.ll b/test/CodeGen/ARM/emutls_generic.ll index 0fada88fb5d9..f5633dc23bcd 100644 --- a/test/CodeGen/ARM/emutls_generic.ll +++ b/test/CodeGen/ARM/emutls_generic.ll @@ -35,12 +35,13 @@ entry: ; ARM_32: bl __emutls_get_address ; ARM_32: .long __emutls_v.external_y ; ARM_32-LABEL: get_internal_y: -; ARM_32: bl __emutls_get_address -; ARM_32: .long __emutls_v.internal_y -; ARM_32-NOT: __emutls_t.external_x -; ARM_32-NOT: __emutls_v.external_x: -; ARM_32: .data -; ARM_32: .align 2 +; ARM_32: bl __emutls_get_address +; ARM_32: .long __emutls_v.internal_y +; ARM_32-NOT: __emutls_t.external_x +; ARM_32-NOT: __emutls_v.external_x: +; ARM_32: .data{{$}} +; ARM_32: .globl __emutls_v.external_y +; ARM_32: .p2align 2 ; ARM_32-LABEL: __emutls_v.external_y: ; ARM_32-NEXT: .long 1 ; ARM_32-NEXT: .long 2 @@ -49,8 +50,9 @@ entry: ; ARM_32: .section .rodata, ; ARM_32-LABEL: __emutls_t.external_y: ; ARM_32-NEXT: .byte 7 -; ARM_32: .data -; ARM_32: .align 2 +; ARM_32: .data{{$}} +; ARM_32-NOT: .globl +; ARM_32: .p2align 2 ; ARM_32-LABEL: __emutls_v.internal_y: ; ARM_32-NEXT: .long 8 ; ARM_32-NEXT: .long 16 diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll index e382e78a9950..1122867356b3 100644 --- a/test/CodeGen/ARM/fast-isel-call.ll +++ b/test/CodeGen/ARM/fast-isel-call.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-MACHO +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-ELF ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=THUMB-LONG ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP @@ -111,9 +111,14 @@ entry: ; ARM: str [[R4]], [sp, #4] ; ARM: bl {{_?}}bar ; ARM-LONG: @t10 -; ARM-LONG: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} -; ARM-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} -; ARM-LONG: ldr [[R]], {{\[}}[[R]]{{\]}} + +; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} +; ARM-LONG-MACHO: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} +; ARM-LONG-MACHO: ldr [[R]], {{\[}}[[R]]{{\]}} + +; ARM-LONG-ELF: movw [[R:l?r[0-9]*]], :lower16:bar +; ARM-LONG-ELF: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}} + ; ARM-LONG: blx [[R]] ; THUMB: @t10 ; THUMB: movs [[R0:l?r[0-9]*]], #0 @@ -167,9 +172,14 @@ entry: ; ARM: LibCall ; ARM: bl {{___udivsi3|__aeabi_uidiv}} ; ARM-LONG: LibCall -; ARM-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} -; ARM-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} -; ARM-LONG: ldr r2, [r2] + +; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} +; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} +; ARM-LONG-MACHO: ldr r2, [r2] + +; ARM-LONG-ELF: movw r2, :lower16:__aeabi_uidiv +; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv + ; ARM-LONG: blx r2 ; THUMB: LibCall ; THUMB: bl {{___udivsi3|__aeabi_uidiv}} diff --git a/test/CodeGen/ARM/fast-isel-deadcode.ll b/test/CodeGen/ARM/fast-isel-deadcode.ll index e584c54b48a2..d66a81c7cdb2 100644 --- a/test/CodeGen/ARM/fast-isel-deadcode.ll +++ b/test/CodeGen/ARM/fast-isel-deadcode.ll @@ -7,7 +7,7 @@ define i32 @main(i32 %argc, i8** %argv) nounwind { entry: ; THUMB: main call void @printArgsNoRet(i32 1, float 0x4000CCCCC0000000, i8 signext 99, double 4.100000e+00) -; THUMB: blx _printArgsNoRet +; THUMB: bl _printArgsNoRet ; THUMB-NOT: ldr ; THUMB-NOT: vldr ; THUMB-NOT: vmov diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll index 1c7ff6879386..277461aa566b 100644 --- a/test/CodeGen/ARM/fast-isel-intrinsic.ll +++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-MACHO +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-ELF ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-MACHO +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-ELF ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG ; Note that some of these tests assume that relocations are either @@ -22,9 +22,14 @@ define void @t1() nounwind ssp { ; ARM: and r1, r1, #255 ; ARM: bl {{_?}}memset ; ARM-LONG-LABEL: t1: -; ARM-LONG: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}} -; ARM-LONG: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}} -; ARM-LONG: ldr r3, [r3] + +; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memset\$non_lazy_ptr)|(ldr r3, .LCPI)}} +; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memset\$non_lazy_ptr)?}} +; ARM-LONG-MACHO: ldr r3, [r3] + +; ARM-LONG-ELF: movw r3, :lower16:memset +; ARM-LONG-ELF: movt r3, :upper16:memset + ; ARM-LONG: blx r3 ; THUMB-LABEL: t1: ; THUMB: {{(movw r0, :lower16:_?message1)|(ldr.n r0, .LCPI)}} @@ -47,9 +52,14 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind define void @t2() nounwind ssp { ; ARM-LABEL: t2: -; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] + +; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:temp +; ARM-ELF: movt r0, :upper16:temp + ; ARM: add r1, r0, #4 ; ARM: add r0, r0, #16 ; ARM: movw r2, #17 @@ -58,9 +68,14 @@ define void @t2() nounwind ssp { ; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload ; ARM: bl {{_?}}memcpy ; ARM-LONG-LABEL: t2: -; ARM-LONG: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}} -; ARM-LONG: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}} -; ARM-LONG: ldr r3, [r3] + +; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memcpy\$non_lazy_ptr)|(ldr r3, .LCPI)}} +; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memcpy\$non_lazy_ptr)?}} +; ARM-LONG-MACHO: ldr r3, [r3] + +; ARM-LONG-ELF: movw r3, :lower16:memcpy +; ARM-LONG-ELF: movt r3, :upper16:memcpy + ; ARM-LONG: blx r3 ; THUMB-LABEL: t2: ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} @@ -86,18 +101,29 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, define void @t3() nounwind ssp { ; ARM-LABEL: t3: -; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] + +; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:temp +; ARM-ELF: movt r0, :upper16:temp + + ; ARM: add r1, r0, #4 ; ARM: add r0, r0, #16 ; ARM: movw r2, #10 ; ARM: mov r0, r1 ; ARM: bl {{_?}}memmove ; ARM-LONG-LABEL: t3: -; ARM-LONG: {{(movw r3, :lower16:L_memmove\$non_lazy_ptr)|(ldr r3, .LCPI)}} -; ARM-LONG: {{(movt r3, :upper16:L_memmove\$non_lazy_ptr)?}} -; ARM-LONG: ldr r3, [r3] + +; ARM-LONG-MACHO: {{(movw r3, :lower16:L_memmove\$non_lazy_ptr)|(ldr r3, .LCPI)}} +; ARM-LONG-MACHO: {{(movt r3, :upper16:L_memmove\$non_lazy_ptr)?}} +; ARM-LONG-MACHO: ldr r3, [r3] + +; ARM-LONG-ELF: movw r3, :lower16:memmove +; ARM-LONG-ELF: movt r3, :upper16:memmove + ; ARM-LONG: blx r3 ; THUMB-LABEL: t3: ; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}} @@ -121,9 +147,14 @@ define void @t3() nounwind ssp { define void @t4() nounwind ssp { ; ARM-LABEL: t4: -; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] + +; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:temp +; ARM-ELF: movt r0, :upper16:temp + ; ARM: ldr r1, [r0, #16] ; ARM: str r1, [r0, #4] ; ARM: ldr r1, [r0, #20] @@ -150,9 +181,14 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, define void @t5() nounwind ssp { ; ARM-LABEL: t5: -; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] + +; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:temp +; ARM-ELF: movt r0, :upper16:temp + ; ARM: ldrh r1, [r0, #16] ; ARM: strh r1, [r0, #4] ; ARM: ldrh r1, [r0, #18] @@ -185,9 +221,14 @@ define void @t5() nounwind ssp { define void @t6() nounwind ssp { ; ARM-LABEL: t6: -; ARM: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] + +; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:temp +; ARM-ELF: movt r0, :upper16:temp + ; ARM: ldrb r1, [r0, #16] ; ARM: strb r1, [r0, #4] ; ARM: ldrb r1, [r0, #17] diff --git a/test/CodeGen/ARM/fast-isel-pie.ll b/test/CodeGen/ARM/fast-isel-pie.ll new file mode 100644 index 000000000000..23a88bdaa22e --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-pie.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=pic -mtriple=armv7-pc-linux-gnueabi | FileCheck %s + +@var = global i32 42 + +define i32* @foo() { +; CHECK: foo: +; CHECK: ldr r0, .L[[POOL:.*]] +; CHECK-NEXT: .L[[ADDR:.*]]: +; CHECK-NEXT: add r0, pc, r0 +; CHECK-NEXT: bx lr + +; CHECK: .L[[POOL]]: +; CHECK-NEXT: .long var-(.L[[ADDR]]+8) + + ret i32* @var +} + +!llvm.module.flags = !{!0} +!0 = !{i32 1, !"PIE Level", i32 2} diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 49460220c47c..502285e85dfd 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-MACHO +; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM --check-prefix=ARM-ELF ; RUN: llc < %s -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. @@ -154,9 +154,13 @@ define void @test4() { ; THUMB: adds r1, #1 ; THUMB: str r1, [r0] -; ARM: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} -; ARM: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} -; ARM: ldr r0, [r0] +; ARM-MACHO: {{(movw r0, :lower16:L_test4g\$non_lazy_ptr)|(ldr r0, .LCPI)}} +; ARM-MACHO: {{(movt r0, :upper16:L_test4g\$non_lazy_ptr)?}} +; ARM-MACHO: ldr r0, [r0] + +; ARM-ELF: movw r0, :lower16:test4g +; ARM-ELF: movt r0, :upper16:test4g + ; ARM: ldr r1, [r0] ; ARM: add r1, r1, #1 ; ARM: str r1, [r0] diff --git a/test/CodeGen/ARM/fast-tail-call.ll b/test/CodeGen/ARM/fast-tail-call.ll index 6472016c0572..c93028bad50c 100644 --- a/test/CodeGen/ARM/fast-tail-call.ll +++ b/test/CodeGen/ARM/fast-tail-call.ll @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=thumbv7-linux-gnueabi -O0 < %s | FileCheck %s +; RUN: llc -mtriple=thumbv8m.base-arm-none-eabi -filetype=obj < %s ; Primarily a non-crash test: Thumbv7 Linux does not have FastISel support, ; which led (via a convoluted route) to DAG nodes after a TC_RETURN that diff --git a/test/CodeGen/ARM/fp16-promote.ll b/test/CodeGen/ARM/fp16-promote.ll index 2a2eb8d2b6ba..ebc5934df022 100644 --- a/test/CodeGen/ARM/fp16-promote.ll +++ b/test/CodeGen/ARM/fp16-promote.ll @@ -642,6 +642,40 @@ define void @test_maxnum(half* %p, half* %q) #0 { ret void } +; CHECK-ALL-LABEL: test_minnan: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vmin.f32 +; CHECK-NOVFP: bl __aeabi_fcmpge +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL: bl __aeabi_f2h +define void @test_minnan(half* %p) #0 { + %a = load half, half* %p, align 2 + %c = fcmp ult half %a, 1.0 + %r = select i1 %c, half %a, half 1.0 + store half %r, half* %p + ret void +} + +; CHECK-ALL-LABEL: test_maxnan: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vmax.f32 +; CHECK-NOVFP: bl __aeabi_fcmple +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL: bl __aeabi_f2h +define void @test_maxnan(half* %p) #0 { + %a = load half, half* %p, align 2 + %c = fcmp ugt half %a, 1.0 + %r = select i1 %c, half %a, half 1.0 + store half %r, half* %p + ret void +} + ; CHECK-FP16-LABEL: test_copysign: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 @@ -889,4 +923,44 @@ define half @test_struct_arg(%struct.dummy %p) { ret half %a } +; CHECK-LABEL: test_uitofp_i32_fadd: +; CHECK-VFP-DAG: vcvt.f32.u32 +; CHECK-NOVFP-DAG: bl __aeabi_ui2f + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-FP16-DAG: vcvtb.f32.f16 +; CHECK-LIBCALL-DAG: bl __aeabi_h2f +; CHECK-LIBCALL-DAG: bl __aeabi_h2f + +; CHECK-VFP-DAG: vadd.f32 +; CHECK-NOVFP-DAG: bl __aeabi_fadd + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-LIBCALL-DAG: bl __aeabi_f2h +define half @test_uitofp_i32_fadd(i32 %a, half %b) #0 { + %c = uitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + +; CHECK-LABEL: test_sitofp_i32_fadd: +; CHECK-VFP-DAG: vcvt.f32.s32 +; CHECK-NOVFP-DAG: bl __aeabi_i2f + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-FP16-DAG: vcvtb.f32.f16 +; CHECK-LIBCALL-DAG: bl __aeabi_h2f +; CHECK-LIBCALL-DAG: bl __aeabi_h2f + +; CHECK-VFP-DAG: vadd.f32 +; CHECK-NOVFP-DAG: bl __aeabi_fadd + +; CHECK-FP16-DAG: vcvtb.f16.f32 +; CHECK-LIBCALL-DAG: bl __aeabi_f2h +define half @test_sitofp_i32_fadd(i32 %a, half %b) #0 { + %c = sitofp i32 %a to half + %r = fadd half %b, %c + ret half %r +} + attributes #0 = { nounwind } diff --git a/test/CodeGen/ARM/fp16-v3.ll b/test/CodeGen/ARM/fp16-v3.ll index 6ed9c9d22c9d..e26455e61e7f 100644 --- a/test/CodeGen/ARM/fp16-v3.ll +++ b/test/CodeGen/ARM/fp16-v3.ll @@ -1,14 +1,16 @@ -; RUN: llc -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mattr=+fp16 < %s | FileCheck %s target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "armv7a--none-eabi" ; CHECK-LABEL: test_vec3: -; CHECK: vcvtb.f32.f16 -; CHECK: vcvt.f32.s32 -; CHECK: vadd.f32 -; CHECK-NEXT: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{.*}} -; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG1:s[0-9]+]], +; CHECK-DAG: vcvt.f32.s32 [[SREG2:s[0-9]+]], +; CHECK-DAG: vcvtb.f16.f32 [[SREG3:s[0-9]+]], [[SREG2]] +; CHECK-DAG: vcvtb.f32.f16 [[SREG4:s[0-9]+]], [[SREG3]] +; CHECK: vadd.f32 [[SREG5:s[0-9]+]], [[SREG4]], [[SREG1]] +; CHECK-NEXT: vcvtb.f16.f32 [[SREG6:s[0-9]+]], [[SREG5]] +; CHECK-NEXT: vmov [[RREG1:r[0-9]+]], [[SREG6]] ; CHECK-NEXT: uxth [[RREG2:r[0-9]+]], [[RREG1]] ; CHECK-NEXT: pkhbt [[RREG3:r[0-9]+]], [[RREG1]], [[RREG1]], lsl #16 ; CHECK-DAG: strh [[RREG1]], [r0, #4] @@ -25,4 +27,16 @@ define void @test_vec3(<3 x half>* %arr, i32 %i) #0 { ret void } +; CHECK-LABEL: test_bitcast: +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: vcvtb.f16.f32 +; CHECK: pkhbt +; CHECK: uxth +define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 { + %bc = bitcast <3 x half> %inp to <3 x i16> + store <3 x i16> %bc, <3 x i16>* %arr, align 8 + ret void +} + attributes #0 = { nounwind } diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll index 73d5c36a9c2f..b2cccd832198 100644 --- a/test/CodeGen/ARM/fp16.ll +++ b/test/CodeGen/ARM/fp16.ll @@ -1,9 +1,17 @@ ; RUN: llc -mtriple=armv7a--none-eabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-HARDFLOAT-EABI %s ; RUN: llc -mtriple=armv7a--none-gnueabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-HARDFLOAT-GNU %s -; RUN: llc -mattr=+vfp3,+fp16 < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-FP16 %s +; RUN: llc -mtriple=armv7a--none-musleabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-HARDFLOAT-GNU %s ; RUN: llc -mtriple=armv8-eabihf < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARMV8 %s ; RUN: llc -mtriple=thumbv7m-eabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SOFTFLOAT-EABI %s ; RUN: llc -mtriple=thumbv7m-gnueabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SOFTFLOAT-GNU %s +; RUN: llc -mtriple=thumbv7m-musleabi < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-SOFTFLOAT-GNU %s + +;; +fp16 is special: it has f32->f16 (unlike v7), but not f64->f16 (unlike v8). +;; This exposes unsafe-fp-math optimization opportunities; test that. +; RUN: llc -mattr=+vfp3,+fp16 < %s |\ +; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-FP16 --check-prefix=CHECK-FP16-SAFE %s +; RUN: llc -mattr=+vfp3,+fp16 < %s -enable-unsafe-fp-math |\ +; RUN: FileCheck --check-prefix=CHECK --check-prefix=CHECK-FP16 --check-prefix=CHECK-FP16-UNSAFE %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv7---eabihf" @@ -76,7 +84,10 @@ define i16 @test_to_fp16(double %in) { ; CHECK-HARDFLOAT-GNU: bl __aeabi_d2h -; CHECK-FP16: bl __aeabi_d2h +; CHECK-FP16-SAFE: bl __aeabi_d2h + +; CHECK-FP16-UNSAFE: vcvt.f32.f64 s0, d0 +; CHECK-FP16-UNSAFE-NEXT: vcvtb.f16.f32 s0, s0 ; CHECK-ARMV8: vcvtb.f16.f64 [[TMP:s[0-9]+]], d0 ; CHECK-ARMV8: vmov r0, [[TMP]] diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index e6aa2db744d5..399d5208ae2c 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -15,7 +15,7 @@ define i32 @test1() { ; DarwinStatic: ldr r0, [r0] ; DarwinStatic: bx lr -; DarwinStatic: .align 2 +; DarwinStatic: .p2align 2 ; DarwinStatic: LCPI0_0: ; DarwinStatic: .long {{_G$}} @@ -26,12 +26,12 @@ define i32 @test1() { ; DarwinDynamic: ldr r0, [r0] ; DarwinDynamic: bx lr -; DarwinDynamic: .align 2 +; DarwinDynamic: .p2align 2 ; DarwinDynamic: LCPI0_0: ; DarwinDynamic: .long L_G$non_lazy_ptr ; DarwinDynamic: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers -; DarwinDynamic: .align 2 +; DarwinDynamic: .p2align 2 ; DarwinDynamic: L_G$non_lazy_ptr: ; DarwinDynamic: .indirect_symbol _G ; DarwinDynamic: .long 0 @@ -46,12 +46,12 @@ define i32 @test1() { ; DarwinPIC-NOT: ldr ; DarwinPIC: bx lr -; DarwinPIC: .align 2 +; DarwinPIC: .p2align 2 ; DarwinPIC: LCPI0_0: ; DarwinPIC: .long L_G$non_lazy_ptr-(LPC0_0+8) ; DarwinPIC: .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers -; DarwinPIC: .align 2 +; DarwinPIC: .p2align 2 ; DarwinPIC: L_G$non_lazy_ptr: ; DarwinPIC: .indirect_symbol _G ; DarwinPIC: .long 0 @@ -66,7 +66,7 @@ define i32 @test1() { ; LinuxPIC: ldr r0, [r0] ; LinuxPIC: bx lr -; LinuxPIC: .align 2 +; LinuxPIC: .p2align 2 ; LinuxPIC: .LCPI0_0: ; LinuxPIC: .Ltmp0: ; LinuxPIC: .long G(GOT_PREL)-((.LPC0_0+8)-.Ltmp0) diff --git a/test/CodeGen/ARM/half.ll b/test/CodeGen/ARM/half.ll index b40eaf638519..ad039b9d6865 100644 --- a/test/CodeGen/ARM/half.ll +++ b/test/CodeGen/ARM/half.ll @@ -41,7 +41,7 @@ define float @test_extend32(half* %addr) { define double @test_extend64(half* %addr) { ; CHECK-LABEL: test_extend64: -; CHECK-OLD: blx ___extendhfsf2 +; CHECK-OLD: bl ___extendhfsf2 ; CHECK-OLD: vcvt.f64.f32 ; CHECK-F16: vcvtb.f32.f16 ; CHECK-F16: vcvt.f64.f32 @@ -54,7 +54,7 @@ define double @test_extend64(half* %addr) { define void @test_trunc32(float %in, half* %addr) { ; CHECK-LABEL: test_trunc32: -; CHECK-OLD: blx ___truncsfhf2 +; CHECK-OLD: bl ___truncsfhf2 ; CHECK-F16: vcvtb.f16.f32 ; CHECK-V8: vcvtb.f16.f32 %val16 = fptrunc float %in to half @@ -65,8 +65,8 @@ define void @test_trunc32(float %in, half* %addr) { define void @test_trunc64(double %in, half* %addr) { ; CHECK-LABEL: test_trunc64: -; CHECK-OLD: blx ___truncdfhf2 -; CHECK-F16: blx ___truncdfhf2 +; CHECK-OLD: bl ___truncdfhf2 +; CHECK-F16: bl ___truncdfhf2 ; CHECK-V8: vcvtb.f16.f64 %val16 = fptrunc double %in to half store half %val16, half* %addr diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index 08e6104bbcf6..b03a60ab60c9 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -16,9 +16,11 @@ define i32 @main() { declare i32 @puts(i8*) +; CHECK-LABEL: main ; CHECK: mov ; CHECK-NOT: mov +; CHECK-FP-ELIM-LABEL: main ; CHECK-FP-ELIM: mov ; CHECK-FP-ELIM: mov ; CHECK-FP-ELIM-NOT: mov diff --git a/test/CodeGen/ARM/ifcvt-iter-indbr.ll b/test/CodeGen/ARM/ifcvt-iter-indbr.ll index a96b6e8a1e83..967d6ebce277 100644 --- a/test/CodeGen/ARM/ifcvt-iter-indbr.ll +++ b/test/CodeGen/ARM/ifcvt-iter-indbr.ll @@ -27,7 +27,7 @@ declare i8* @bar(i32, i8*, i8*) ; CHECK-NEXT: LBB{{[0-9_]+}}: ; CHECK-NEXT: movw r0, #4567 ; CHECK-NEXT: [[FOOCALL]]: -; CHECK-NEXT: blx _foo +; CHECK-NEXT: bl _foo ; ; CHECK-PROB: BB#0: ; CHECK-PROB: Successors according to CFG: BB#1({{[0-9a-fx/= ]+}}50.00%) BB#2({{[0-9a-fx/= ]+}}25.00%) BB#4({{[0-9a-fx/= ]+}}25.00%) diff --git a/test/CodeGen/ARM/inlineasm-X-allocation.ll b/test/CodeGen/ARM/inlineasm-X-allocation.ll new file mode 100644 index 000000000000..e88d668f5ccf --- /dev/null +++ b/test/CodeGen/ARM/inlineasm-X-allocation.ll @@ -0,0 +1,21 @@ +; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfpv2 %s -o - | FileCheck %s -check-prefix=novfp +; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefix=vfp + +; vfp-LABEL: f1 +; vfp-CHECK: vadd.f32 s0, s0, s0 + +; In the novfp case, the compiler is forced to assign a core register. +; Although this register class can't be used with the vadd.f32 instruction, +; the compiler behaved as expected since it is allowed to emit anything. + +; novfp-LABEL: f1 +; novfp-CHECK: vadd.f32 r0, r0, r0 + +; This can be generated by a function such as: +; void f1(float f) {asm volatile ("add.f32 $0, $0, $0" : : "X" (f));} + +define arm_aapcs_vfpcc void @f1(float %f) { +entry: + call void asm sideeffect "vadd.f32 $0, $0, $0", "X" (float %f) nounwind + ret void +} diff --git a/test/CodeGen/ARM/inlineasm-X-constraint.ll b/test/CodeGen/ARM/inlineasm-X-constraint.ll new file mode 100644 index 000000000000..d3d53df11b56 --- /dev/null +++ b/test/CodeGen/ARM/inlineasm-X-constraint.ll @@ -0,0 +1,157 @@ +; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon < %s -o - | FileCheck %s + +; The following functions test the use case where an X constraint is used to +; add a dependency between an assembly instruction (vmsr in this case) and +; another instruction. In each function, we use a different type for the +; X constraint argument. +; +; We can something similar from the following C code: +; double f1(double f, int pscr_value) { +; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value)); +; return f+f; +; } + +; CHECK-LABEL: f1 +; CHECK: vmsr fpscr +; CHECK: vadd.f64 + +define arm_aapcs_vfpcc double @f1(double %f, i32 %pscr_value) { +entry: + %f.addr = alloca double, align 8 + store double %f, double* %f.addr, align 8 + call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(double* nonnull %f.addr, i32 %pscr_value) nounwind + %0 = load double, double* %f.addr, align 8 + %add = fadd double %0, %0 + ret double %add +} + +; int f2(int f, int pscr_value) { +; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value)); +; return f+f; +; } + +; CHECK-LABEL: f2 +; CHECK: vmsr fpscr +; CHECK: mul +define arm_aapcs_vfpcc i32 @f2(i32 %f, i32 %pscr_value) { +entry: + %f.addr = alloca i32, align 4 + store i32 %f, i32* %f.addr, align 4 + call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(i32* nonnull %f.addr, i32 %pscr_value) nounwind + %0 = load i32, i32* %f.addr, align 4 + %mul = mul i32 %0, %0 + ret i32 %mul +} + + +; int f3(int f, int pscr_value) { +; asm volatile("vmsr fpscr,%0" : "=X" ((f)): "r" (pscr_value)); +; return f+f; +; } + +; typedef signed char int8_t; +; typedef __attribute__((neon_vector_type(8))) int8_t int8x8_t; +; void f3 (void) +; { +; int8x8_t vector_res_int8x8; +; unsigned int fpscr; +; asm volatile ("vmsr fpscr,%1" : "=X" ((vector_res_int8x8)) : "r" (fpscr)); +; return vector_res_int8x8 * vector_res_int8x8; +; } + +; CHECK-LABEL: f3 +; CHECK: vmsr fpscr +; CHECK: vmul.i8 +define arm_aapcs_vfpcc <8 x i8> @f3() { +entry: + %vector_res_int8x8 = alloca <8 x i8>, align 8 + %0 = getelementptr inbounds <8 x i8>, <8 x i8>* %vector_res_int8x8, i32 0, i32 0 + call void asm sideeffect "vmsr fpscr,$1", "=*X,r"(<8 x i8>* nonnull %vector_res_int8x8, i32 undef) nounwind + %1 = load <8 x i8>, <8 x i8>* %vector_res_int8x8, align 8 + %mul = mul <8 x i8> %1, %1 + ret <8 x i8> %mul +} + +; We can emit integer constants. +; We can get this from: +; void f() { +; int x = 2; +; asm volatile ("add r0, r0, %0" : : "X" (x)); +; } +; +; CHECK-LABEL: f4 +; CHECK: add r0, r0, #2 +define void @f4() { +entry: + tail call void asm sideeffect "add r0, r0, $0", "X"(i32 2) + ret void +} + +; We can emit function labels. This is equivalent to the following C code: +; void f(void) { +; void (*x)(void) = &foo; +; asm volatile ("bl %0" : : "X" (x)); +; } +; CHECK-LABEL: f5 +; CHECK: bl f4 +define void @f5() { +entry: + tail call void asm sideeffect "bl $0", "X"(void ()* nonnull @f4) + ret void +} + +declare void @foo(...) + +; This tests the behavior of the X constraint when used on functions pointers, +; or functions with a cast. In the first asm call we figure out that this +; is a function pointer and emit the label. However, in the second asm call +; we can't see through the bitcast and we end up having to lower this constraint +; to something else. This is not ideal, but it is a correct behaviour according +; to the definition of the X constraint. +; +; In this case (and other cases where we could have emitted something else), +; what we're doing with the X constraint is not particularly useful either, +; since the user could have used "r" in this situation for the same effect. + +; CHECK-LABEL: f6 +; CHECK: bl foo +; CHECK: bl r + +define void @f6() nounwind { +entry: + tail call void asm sideeffect "bl $0", "X"(void (...)* @foo) nounwind + tail call void asm sideeffect "bl $0", "X"(void (...)* bitcast (void ()* @f4 to void (...)*)) nounwind + ret void +} + +; The following IR can be generated from C code with a function like: +; void a() { +; void* a = &&A; +; asm volatile ("bl %0" : : "X" (a)); +; A: +; return; +; } +; +; Ideally this would give the block address of bb, but it requires us to see +; through blockaddress, which we can't do at the moment. This might break some +; existing use cases where a user would expect to get a block label and instead +; gets the block address in a register. However, note that according to the +; "no constraints" definition this behaviour is correct (although not very nice). + +; CHECK-LABEL: f7 +; CHECK: bl +define void @f7() { + call void asm sideeffect "bl $0", "X"( i8* blockaddress(@f7, %bb) ) + br label %bb +bb: + ret void +} + +; If we use a constraint "=*X", we should get a store back to *%x (in r0). +; CHECK-LABEL: f8 +; CHECK: str r{{.*}}, [r0] +define void @f8(i32 *%x) { +entry: + tail call void asm sideeffect "add $0, r0, r0", "=*X"(i32 *%x) + ret void +} diff --git a/test/CodeGen/ARM/inlineasm-ldr-pseudo.ll b/test/CodeGen/ARM/inlineasm-ldr-pseudo.ll index f63e4b0b3a17..98665f056a21 100644 --- a/test/CodeGen/ARM/inlineasm-ldr-pseudo.ll +++ b/test/CodeGen/ARM/inlineasm-ldr-pseudo.ll @@ -9,9 +9,9 @@ ; CHECK: 0: 00 00 9f e5 ldr r0, [pc] ; CHECK: 4: 0e f0 a0 e1 mov pc, lr ; Make sure the constant pool entry comes after the return -; CHECK: 8: 01 00 00 00 +; CHECK: 8: 78 56 34 12 define i32 @foo() nounwind { entry: - %0 = tail call i32 asm sideeffect "ldr $0,=1", "=r"() nounwind + %0 = tail call i32 asm sideeffect "ldr $0,=0x12345678", "=r"() nounwind ret i32 %0 } diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index eb7ba59b69bf..f725f534c73d 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -6,6 +6,7 @@ define void @t() nounwind { entry: +; CHECK-LABEL: t ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], ; CHECK: vmov q8, q15 @@ -19,6 +20,7 @@ entry: define void @t2() nounwind { entry: +; CHECK-LABEL: t2 ; CHECK: vmov d30, d16 ; CHECK: vmov.32 r0, d30[0] %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind @@ -64,7 +66,7 @@ ret i32 0 define float @t6(float %y) nounwind { entry: -; CHECK: t6 +; CHECK-LABEL: t6 ; CHECK: flds s15, s0 %0 = tail call float asm "flds s15, $0", "=x"() nounwind ret float %0 @@ -74,7 +76,7 @@ entry: define double @t7(double %y) nounwind { entry: -; CHECK: t7 +; CHECK-LABEL: t7 ; CHECK: flds s15, d0 %0 = tail call double asm "flds s15, $0", "=x"() nounwind ret double %0 @@ -84,7 +86,7 @@ entry: define float @t8(float %y) nounwind { entry: -; CHECK: t8 +; CHECK-LABEL: t8 ; CHECK: flds s15, s0 %0 = tail call float asm "flds s15, $0", "=t"() nounwind ret float %0 @@ -94,7 +96,7 @@ entry: define i32 @t9(i32 %r0) nounwind { entry: -; CHECK: t9 +; CHECK-LABEL: t9 ; CHECK: movw r0, #27182 %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind ret i32 %0 @@ -104,7 +106,7 @@ entry: define void @t10(i8* %f, i32 %g) nounwind { entry: -; CHECK: t10 +; CHECK-LABEL: t10 ; CHECK: str r1, [r0] %f.addr = alloca i8*, align 4 store i8* %f, i8** %f.addr, align 4 @@ -116,8 +118,19 @@ entry: define <4 x i32> @t11(i32* %p) nounwind { entry: -; CHECK: t11 +; CHECK-LABEL: t11 ; CHECK: vld1.s32 {d16[], d17[]}, [r0] %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind ret <4 x i32> %0 } + +; Bugzilla PR26038 + +define i32 @fn1() local_unnamed_addr nounwind { +; CHECK-LABEL: fn1 +entry: +; CHECK: mov [[addr:r[0-9]+]], #5 +; CHECK: ldrh {{.*}}[[addr]] + %0 = tail call i32 asm "ldrh $0, $1", "=r,*Q"(i8* inttoptr (i32 5 to i8*)) nounwind + ret i32 %0 +} diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll index 43bd5815a558..794f672534dc 100644 --- a/test/CodeGen/ARM/interrupt-attr.ll +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -35,15 +35,15 @@ define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to ; appropriate sentinel so no special return needed). ; CHECK-M-LABEL: irq_fn: -; CHECK-M: push.w {r4, r7, r11, lr} -; CHECK-M: add.w r11, sp, #8 +; CHECK-M: push {r4, r6, r7, lr} +; CHECK-M: add r7, sp, #8 ; CHECK-M: mov r4, sp ; CHECK-M: bfc r4, #0, #3 ; CHECK-M: mov sp, r4 ; CHECK-M: bl _bar -; CHECK-M: sub.w r4, r11, #8 +; CHECK-M: sub.w r4, r7, #8 ; CHECK-M: mov sp, r4 -; CHECK-M: pop.w {r4, r7, r11, pc} +; CHECK-M: pop {r4, r6, r7, pc} call arm_aapcscc void @bar() ret void diff --git a/test/CodeGen/ARM/interval-update-remat.ll b/test/CodeGen/ARM/interval-update-remat.ll new file mode 100644 index 000000000000..6391d4c29604 --- /dev/null +++ b/test/CodeGen/ARM/interval-update-remat.ll @@ -0,0 +1,162 @@ +; RUN: llc -verify-regalloc < %s +; PR27275: When enabling remat for vreg defined by PHIs, make sure the update +; of the live range removes dead phi. Otherwise, we may end up with PHIs with +; incorrect operands and that will trigger assertions or verifier failures +; in later passes. + +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7-apple-ios9.0.0" + +%class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326 = type { %class.MockTransportClientSocketPool.0.225.275.1300.2325, i32 } +%class.MockTransportClientSocketPool.0.225.275.1300.2325 = type { i8 } +%class.StaticSocketDataProvider.6.231.281.1306.2331 = type { i8, %struct.MockConnect.5.230.280.1305.2330 } +%struct.MockConnect.5.230.280.1305.2330 = type { %class.IPEndPoint.4.229.279.1304.2329 } +%class.IPEndPoint.4.229.279.1304.2329 = type { %class.IPAddress.3.228.278.1303.2328 } +%class.IPAddress.3.228.278.1303.2328 = type { %"class.(anonymous namespace)::vector.2.227.277.1302.2327" } +%"class.(anonymous namespace)::vector.2.227.277.1302.2327" = type { i8 } +%class.TestCompletionCallback.9.234.284.1309.2334 = type { %class.TestCompletionCallbackTemplate.8.233.283.1308.2333, i32 } +%class.TestCompletionCallbackTemplate.8.233.283.1308.2333 = type { i32 } +%class.AssertionResult.24.249.299.1324.2349 = type { i8, %class.scoped_ptr.23.248.298.1323.2348 } +%class.scoped_ptr.23.248.298.1323.2348 = type { %class.Trans_NS___1_basic_string.18.243.293.1318.2343* } +%class.Trans_NS___1_basic_string.18.243.293.1318.2343 = type { %class.Trans_NS___1___libcpp_compressed_pair_imp.17.242.292.1317.2342 } +%class.Trans_NS___1___libcpp_compressed_pair_imp.17.242.292.1317.2342 = type { %"struct.Trans_NS___1_basic_string::__rep.16.241.291.1316.2341" } +%"struct.Trans_NS___1_basic_string::__rep.16.241.291.1316.2341" = type { %"struct.Trans_NS___1_basic_string::__long.15.240.290.1315.2340" } +%"struct.Trans_NS___1_basic_string::__long.15.240.290.1315.2340" = type { i64, i32 } +%class.AssertHelper.10.235.285.1310.2335 = type { i8 } +%class.Message.13.238.288.1313.2338 = type { %class.scoped_ptr.0.12.237.287.1312.2337 } +%class.scoped_ptr.0.12.237.287.1312.2337 = type { %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"* } +%"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336" = type { i8 } +%class.scoped_refptr.19.244.294.1319.2344 = type { i8 } +%class.BoundNetLog.20.245.295.1320.2345 = type { i32 } +%struct.MockReadWrite.7.232.282.1307.2332 = type { i32 } +%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347" = type { i8 } +%class.ClientSocketHandle.14.239.289.1314.2339 = type { i8 } +%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346" = type { i8 } + +@.str = private unnamed_addr constant [1 x i8] zeroinitializer, align 1 + +define void @_ZN53SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test6m_fn10Ev(%class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this) align 2 { +entry: + %socket_data = alloca %class.StaticSocketDataProvider.6.231.281.1306.2331, align 1 + %agg.tmp = alloca %struct.MockConnect.5.230.280.1305.2330, align 1 + %callback = alloca %class.TestCompletionCallback.9.234.284.1309.2334, align 4 + %gtest_ar = alloca %class.AssertionResult.24.249.299.1324.2349, align 4 + %temp.lvalue = alloca %class.AssertHelper.10.235.285.1310.2335, align 1 + %agg.tmp10 = alloca %class.Message.13.238.288.1313.2338, align 4 + %ref.tmp = alloca %class.Trans_NS___1_basic_string.18.243.293.1318.2343, align 4 + %agg.tmp16 = alloca %class.scoped_refptr.19.244.294.1319.2344, align 1 + %agg.tmp18 = alloca %class.BoundNetLog.20.245.295.1320.2345, align 4 + %call2 = call %class.StaticSocketDataProvider.6.231.281.1306.2331* @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(%class.StaticSocketDataProvider.6.231.281.1306.2331* nonnull %socket_data, %struct.MockReadWrite.7.232.282.1307.2332* undef, i32 1, %struct.MockReadWrite.7.232.282.1307.2332* null, i32 0) + %call3 = call %struct.MockConnect.5.230.280.1305.2330* @_ZN11MockConnectC1Ev(%struct.MockConnect.5.230.280.1305.2330* nonnull %agg.tmp) + call void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(%class.StaticSocketDataProvider.6.231.281.1306.2331* nonnull %socket_data, %struct.MockConnect.5.230.280.1305.2330* nonnull %agg.tmp) + %call5 = call %class.TestCompletionCallback.9.234.284.1309.2334* @_ZN22TestCompletionCallbackC1Ev(%class.TestCompletionCallback.9.234.284.1309.2334* nonnull %callback) + %transport_socket_pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 0 + %call6 = call i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(%class.MockTransportClientSocketPool.0.225.275.1300.2325* %transport_socket_pool_) + call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret %gtest_ar, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 0, i64 undef) + %tmp = load i8, i8* undef, align 4 + %tobool.i = icmp eq i8 %tmp, 0 + br i1 %tobool.i, label %if.else, label %if.end + +if.else: ; preds = %entry + br i1 undef, label %_ZN15AssertionResult5m_fn6Ev.exit, label %cond.true.i + +cond.true.i: ; preds = %if.else + %call4.i = call i8* @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull undef) + br label %_ZN15AssertionResult5m_fn6Ev.exit + +_ZN15AssertionResult5m_fn6Ev.exit: ; preds = %cond.true.i, %if.else + %cond.i = phi i8* [ %call4.i, %cond.true.i ], [ getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), %if.else ] + %call9 = call %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperC1EPKc(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue, i8* %cond.i) + %call11 = call %class.Message.13.238.288.1313.2338* @_ZN7MessageC1Ev(%class.Message.13.238.288.1313.2338* nonnull %agg.tmp10) + call void @_ZN12AssertHelperaSE7Message(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue, %class.Message.13.238.288.1313.2338* nonnull %agg.tmp10) + %call.i.i.i.i27 = call zeroext i1 @_Z6IsTruev() + %brmerge = or i1 false, undef + br i1 %brmerge, label %_ZN7MessageD1Ev.exit33, label %delete.notnull.i.i.i.i32 + +delete.notnull.i.i.i.i32: ; preds = %_ZN15AssertionResult5m_fn6Ev.exit + %call.i.i.i.i.i.i31 = call %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* undef) + call void @_ZdlPv(i8* undef) + br label %_ZN7MessageD1Ev.exit33 + +_ZN7MessageD1Ev.exit33: ; preds = %delete.notnull.i.i.i.i32, %_ZN15AssertionResult5m_fn6Ev.exit + %call13 = call %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperD1Ev(%class.AssertHelper.10.235.285.1310.2335* nonnull %temp.lvalue) + br label %if.end + +if.end: ; preds = %_ZN7MessageD1Ev.exit33, %entry + %message_.i.i = getelementptr inbounds %class.AssertionResult.24.249.299.1324.2349, %class.AssertionResult.24.249.299.1324.2349* %gtest_ar, i32 0, i32 1 + %call.i.i.i = call %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* %message_.i.i) + call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 12, i32 4, i1 false) + call void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull %ref.tmp) + call void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* nonnull sret %agg.tmp16) + %callback_.i = getelementptr inbounds %class.TestCompletionCallback.9.234.284.1309.2334, %class.TestCompletionCallback.9.234.284.1309.2334* %callback, i32 0, i32 1 + %pool_ = getelementptr inbounds %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326, %class.SOCKSClientSocketPoolTest_AsyncSOCKSConnectError_Test.1.226.276.1301.2326* %this, i32 0, i32 1 + %tmp1 = getelementptr inbounds %class.BoundNetLog.20.245.295.1320.2345, %class.BoundNetLog.20.245.295.1320.2345* %agg.tmp18, i32 0, i32 0 + store i32 0, i32* %tmp1, align 4 + call void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339* nonnull undef, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* nonnull dereferenceable(12) %ref.tmp, %class.scoped_refptr.19.244.294.1319.2344* nonnull %agg.tmp16, i32 0, i32 1, i32* nonnull dereferenceable(4) %callback_.i, i32* %pool_, %class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18) + %call19 = call %class.BoundNetLog.20.245.295.1320.2345* @_ZN11BoundNetLogD1Ev(%class.BoundNetLog.20.245.295.1320.2345* nonnull %agg.tmp18) + call void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* nonnull sret undef, i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str, i32 0, i32 0), i64 -1, i64 0) + br i1 undef, label %if.then.i.i.i.i, label %_ZN7MessageD1Ev.exit + +if.then.i.i.i.i: ; preds = %if.end + %tmp2 = load %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"*, %"class.(anonymous namespace)::basic_stringstream.11.236.286.1311.2336"** undef, align 4 + br label %_ZN7MessageD1Ev.exit + +_ZN7MessageD1Ev.exit: ; preds = %if.then.i.i.i.i, %if.end + %connect_.i.i = getelementptr inbounds %class.StaticSocketDataProvider.6.231.281.1306.2331, %class.StaticSocketDataProvider.6.231.281.1306.2331* %socket_data, i32 0, i32 1 + %tmp3 = bitcast %struct.MockConnect.5.230.280.1305.2330* %connect_.i.i to %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* + %call.i.i.i.i.i.i.i.i.i.i = call %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* @_ZN12_GLOBAL__N_113__vector_baseD2Ev(%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* %tmp3) + ret void +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start(i64, i8* nocapture) #0 + +declare %class.StaticSocketDataProvider.6.231.281.1306.2331* @_ZN24StaticSocketDataProviderC1EP13MockReadWritejS1_j(%class.StaticSocketDataProvider.6.231.281.1306.2331* returned, %struct.MockReadWrite.7.232.282.1307.2332*, i32, %struct.MockReadWrite.7.232.282.1307.2332*, i32) unnamed_addr + +declare void @_ZN24StaticSocketDataProvider5m_fn8E11MockConnect(%class.StaticSocketDataProvider.6.231.281.1306.2331*, %struct.MockConnect.5.230.280.1305.2330*) + +declare %struct.MockConnect.5.230.280.1305.2330* @_ZN11MockConnectC1Ev(%struct.MockConnect.5.230.280.1305.2330* returned) unnamed_addr + +declare %class.TestCompletionCallback.9.234.284.1309.2334* @_ZN22TestCompletionCallbackC1Ev(%class.TestCompletionCallback.9.234.284.1309.2334* returned) unnamed_addr + +declare i32 @_ZN29MockTransportClientSocketPool5m_fn9Ev(%class.MockTransportClientSocketPool.0.225.275.1300.2325*) + +declare %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperC1EPKc(%class.AssertHelper.10.235.285.1310.2335* returned, i8*) unnamed_addr + +declare void @_ZN12AssertHelperaSE7Message(%class.AssertHelper.10.235.285.1310.2335*, %class.Message.13.238.288.1313.2338*) + +declare %class.Message.13.238.288.1313.2338* @_ZN7MessageC1Ev(%class.Message.13.238.288.1313.2338* returned) unnamed_addr + +declare %class.AssertHelper.10.235.285.1310.2335* @_ZN12AssertHelperD1Ev(%class.AssertHelper.10.235.285.1310.2335* returned) unnamed_addr + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end(i64, i8* nocapture) #0 + +declare void @_ZN18ClientSocketHandle5m_fn3IPiEEvRK25Trans_NS___1_basic_stringIciiE13scoped_refptr15RequestPriorityN16ClientSocketPool13RespectLimitsERiT_11BoundNetLog(%class.ClientSocketHandle.14.239.289.1314.2339*, %class.Trans_NS___1_basic_string.18.243.293.1318.2343* dereferenceable(12), %class.scoped_refptr.19.244.294.1319.2344*, i32, i32, i32* dereferenceable(4), i32*, %class.BoundNetLog.20.245.295.1320.2345*) + +declare void @_Z19CreateSOCKSv5Paramsv(%class.scoped_refptr.19.244.294.1319.2344* sret) + +; Function Attrs: argmemonly nounwind +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) #0 + +declare %class.BoundNetLog.20.245.295.1320.2345* @_ZN11BoundNetLogD1Ev(%class.BoundNetLog.20.245.295.1320.2345* returned) unnamed_addr + +declare %class.scoped_refptr.19.244.294.1319.2344* @_ZN13scoped_refptrD1Ev(%class.scoped_refptr.19.244.294.1319.2344* returned) unnamed_addr + +declare %"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* @_ZN12_GLOBAL__N_113__vector_baseD2Ev(%"class.(anonymous namespace)::__vector_base.21.246.296.1321.2346"* returned) unnamed_addr + +declare i8* @_ZN25Trans_NS___1_basic_stringIciiE5m_fn1Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343*) + +declare zeroext i1 @_Z6IsTruev() + +declare void @_ZdlPv(i8*) + +declare %"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* @_ZN12_GLOBAL__N_114basic_iostreamD2Ev(%"class.(anonymous namespace)::basic_iostream.22.247.297.1322.2347"* returned) unnamed_addr + +declare %class.scoped_ptr.23.248.298.1323.2348* @_ZN10scoped_ptrI25Trans_NS___1_basic_stringIciiEED2Ev(%class.scoped_ptr.23.248.298.1323.2348* readonly returned) unnamed_addr align 2 + +declare void @_Z11CmpHelperEQPcS_xx(%class.AssertionResult.24.249.299.1324.2349* sret, i8*, i8*, i64, i64) + +declare void @_ZN25Trans_NS___1_basic_stringIciiE5m_fn2Ev(%class.Trans_NS___1_basic_string.18.243.293.1318.2343*) + +attributes #0 = { argmemonly nounwind } diff --git a/test/CodeGen/ARM/intrinsics-coprocessor.ll b/test/CodeGen/ARM/intrinsics-coprocessor.ll new file mode 100644 index 000000000000..8fea49b39fb6 --- /dev/null +++ b/test/CodeGen/ARM/intrinsics-coprocessor.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s + +define void @coproc(i8* %i) nounwind { +entry: + ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4 + %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4 + tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind + ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4 + %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4 + tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 + tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 + tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: cdp p7, #3, c1, c1, c1, #5 + tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ; CHECK: cdp2 p7, #3, c1, c1, c1, #5 + tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ; CHECK: ldc p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldcl p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stcl p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc2 p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc2l p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind + ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 + %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind + ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 + %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind + ret void +} + +declare void @llvm.arm.ldc(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc(i32, i32, i8*) nounwind + +declare void @llvm.arm.stcl(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc2(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind + +declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind + +declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind + +declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/intrinsics.ll b/test/CodeGen/ARM/intrinsics.ll deleted file mode 100644 index 54cc3e0a027c..000000000000 --- a/test/CodeGen/ARM/intrinsics.ll +++ /dev/null @@ -1,39 +0,0 @@ -; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s -; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s - -define void @coproc() nounwind { -entry: - ; CHECK: mrc - %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcr - tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind - ; CHECK: mrc2 - %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcr2 - tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcrr - tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind - ; CHECK: mcrr2 - tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind - ; CHECK: cdp - tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind - ; CHECK: cdp2 - tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind - ret void -} - -declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind - -declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind - -declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind - -declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind - -declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind - -declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind - -declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind - -declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/invalidated-save-point.ll b/test/CodeGen/ARM/invalidated-save-point.ll new file mode 100644 index 000000000000..0ff153b6799d --- /dev/null +++ b/test/CodeGen/ARM/invalidated-save-point.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple thumbv7 -stop-after=if-converter < %s 2>&1 | FileCheck %s + +; Make sure the save point and restore point are dropped from MFI at +; this point. Notably, if it isn't is will be invalid and reference a +; deleted block (%bb.-1.if.end) + +; CHECK-NOT: savePoint: +; CHECK-NOT: restorePoint: + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv7" + +define i32 @f(i32 %n) { +entry: + %cmp = icmp ult i32 %n, 4 + br i1 %cmp, label %return, label %if.end + +if.end: + tail call void @g(i32 %n) + br label %return + +return: + %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] + ret i32 %retval.0 +} + +declare void @g(i32) diff --git a/test/CodeGen/ARM/ldc2l.ll b/test/CodeGen/ARM/ldc2l.ll new file mode 100644 index 000000000000..58d9509b1672 --- /dev/null +++ b/test/CodeGen/ARM/ldc2l.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s + +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.ldc2l +define void @ldc2l(i8* %i) nounwind { +entry: + call void @llvm.arm.ldc2l(i32 1, i32 2, i8* %i) nounwind + ret void +} + +declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind diff --git a/test/CodeGen/ARM/ldm-base-writeback.ll b/test/CodeGen/ARM/ldm-base-writeback.ll new file mode 100644 index 000000000000..375f58a24a19 --- /dev/null +++ b/test/CodeGen/ARM/ldm-base-writeback.ll @@ -0,0 +1,21 @@ +; RUN: llc -O3 < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "armv7--linux-gnu" + +@a = global i32 0, align 4 +@b = global i32 0, align 4 +@c = global i32 0, align 4 + +; CHECK-LABEL: bar: +; CHECK: ldm r{{[0-9]}}!, {r0, r{{[0-9]}}, r{{[0-9]}}} +define void @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize { + %1 = load i32, i32* @a, align 4 + %2 = load i32, i32* @b, align 4 + %3 = load i32, i32* @c, align 4 + %4 = tail call i32 @baz(i32 %1, i32 %3) minsize optsize + %5 = tail call i32 @baz(i32 %2, i32 %3) minsize optsize + ret void +} + +declare i32 @baz(i32,i32) minsize optsize diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll index 01b18bccc337..24c10b42a445 100644 --- a/test/CodeGen/ARM/ldr_frame.ll +++ b/test/CodeGen/ARM/ldr_frame.ll @@ -1,5 +1,7 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s +; CHECK-LABEL: f1 +; CHECK-NOT: mov define i32 @f1() { %buf = alloca [32 x i32], align 4 %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 0 @@ -7,6 +9,8 @@ define i32 @f1() { ret i32 %tmp1 } +; CHECK-LABEL: f2 +; CHECK-NOT: mov define i32 @f2() { %buf = alloca [32 x i8], align 4 %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 0 @@ -15,6 +19,8 @@ define i32 @f2() { ret i32 %tmp2 } +; CHECK-LABEL: f3 +; CHECK-NOT: mov define i32 @f3() { %buf = alloca [32 x i32], align 4 %tmp = getelementptr [32 x i32], [32 x i32]* %buf, i32 0, i32 32 @@ -22,6 +28,8 @@ define i32 @f3() { ret i32 %tmp1 } +; CHECK-LABEL: f4 +; CHECK-NOT: mov define i32 @f4() { %buf = alloca [32 x i8], align 4 %tmp = getelementptr [32 x i8], [32 x i8]* %buf, i32 0, i32 2 @@ -29,6 +37,3 @@ define i32 @f4() { %tmp2 = zext i8 %tmp1 to i32 ret i32 %tmp2 } - -; CHECK-NOT: mov - diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index b2596346bfa1..dd97fbfd6404 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK -check-prefix=NORMAL +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK -check-prefix=NORMAL ; rdar://6949835 -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK -; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT -check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK -check-prefix=NORMAL +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK -check-prefix=NORMAL +; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT -check-prefix=CHECK -check-prefix=NORMAL + +; RUN: llc < %s -mtriple=thumbv7-apple-ios -arm-assume-misaligned-load-store | FileCheck %s -check-prefix=CHECK -check-prefix=CONSERVATIVE ; Magic ARM pair hints works best with linearscan / fast. @@ -15,12 +17,13 @@ declare void @use_i64(i64 %v) define void @test_ldrd(i64 %a) nounwind readonly { ; CHECK-LABEL: test_ldrd: -; CHECK: bl{{x?}} _get_ptr +; NORMAL: bl{{x?}} _get_ptr ; A8: ldrd r0, r1, [r0] ; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base ; register when interrupted or faulted. ; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]] -; CHECK: bl{{x?}} _use_i64 +; CONSERVATIVE-NOT: ldrd +; NORMAL: bl{{x?}} _use_i64 %ptr = call i64* @get_ptr() %v = load i64, i64* %ptr, align 8 call void @use_i64(i64 %v) @@ -39,11 +42,10 @@ define void @test_ldrd(i64 %a) nounwind readonly { ; evict another live range or use callee saved regs. Sorry if the test ; is sensitive to Regalloc changes, but it is an interesting case. ; -; BASIC: @f +; CHECK-LABEL: f: ; BASIC: %bb ; BASIC: ldrd ; BASIC: str -; GREEDY: @f ; GREEDY: %bb ; GREEDY: ldrd ; GREEDY: str @@ -76,14 +78,15 @@ return: ; preds = %bb, %entry @TestVar = external global %struct.Test +; CHECK-LABEL: Func1: define void @Func1() nounwind ssp { -; CHECK: @Func1 entry: ; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} ; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}} ; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] ; A8-NEXT: add [[FIELD1]], [[FIELD2]] ; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}} +; CONSERVATIVE-NOT: ldrd %orig_blocks = alloca [256 x i16], align 2 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 @@ -97,8 +100,9 @@ entry: declare void @extfunc(i32, i32, i32, i32) ; CHECK-LABEL: Func2: +; CONSERVATIVE-NOT: ldrd ; A8: ldrd -; A8: blx +; CHECK: bl{{x?}} _extfunc ; A8: pop define void @Func2(i32* %p) { entry: @@ -116,12 +120,14 @@ entry: ; M3: strd r1, r0, [sp, #-8]! ; BASIC: strd r1, r0, [sp, #-8]! ; GREEDY: strd r0, r1, [sp, #-8]! -; CHECK: @ InlineAsm Start -; CHECK: @ InlineAsm End +; CONSERVATIVE: strd r0, r1, [sp, #-8]! +; NORMAL: @ InlineAsm Start +; NORMAL: @ InlineAsm End ; A8: ldrd r2, r1, [sp] ; M3: ldrd r2, r1, [sp] ; BASIC: ldrd r2, r1, [sp] ; GREEDY: ldrd r1, r2, [sp] +; CONSERVATIVE: ldrd r1, r2, [sp] ; CHECK: bl{{x?}} _extfunc define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) { ; force %v0 and %v1 to be spilled @@ -134,8 +140,9 @@ define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) { declare void @extfunc2(i32*, i32, i32) ; CHECK-LABEL: ldrd_postupdate_dec: -; CHECK: ldrd r1, r2, [r0], #-8 -; CHECK-NEXT: bl{{x?}} _extfunc +; NORMAL: ldrd r1, r2, [r0], #-8 +; CONSERVATIVE-NOT: ldrd +; CHECK: bl{{x?}} _extfunc define void @ldrd_postupdate_dec(i32* %p0) { %p0.1 = getelementptr i32, i32* %p0, i32 1 %v0 = load i32, i32* %p0 @@ -146,8 +153,9 @@ define void @ldrd_postupdate_dec(i32* %p0) { } ; CHECK-LABEL: ldrd_postupdate_inc: -; CHECK: ldrd r1, r2, [r0], #8 -; CHECK-NEXT: bl{{x?}} _extfunc +; NORMAL: ldrd r1, r2, [r0], #8 +; CONSERVATIVE-NOT: ldrd +; CHECK: bl{{x?}} _extfunc define void @ldrd_postupdate_inc(i32* %p0) { %p0.1 = getelementptr i32, i32* %p0, i32 1 %v0 = load i32, i32* %p0 @@ -158,8 +166,9 @@ define void @ldrd_postupdate_inc(i32* %p0) { } ; CHECK-LABEL: strd_postupdate_dec: -; CHECK: strd r1, r2, [r0], #-8 -; CHECK-NEXT: bx lr +; NORMAL: strd r1, r2, [r0], #-8 +; CONSERVATIVE-NOT: strd +; CHECK: bx lr define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) { %p0.1 = getelementptr i32, i32* %p0, i32 1 store i32 %v0, i32* %p0 @@ -169,8 +178,9 @@ define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) { } ; CHECK-LABEL: strd_postupdate_inc: -; CHECK: strd r1, r2, [r0], #8 -; CHECK-NEXT: bx lr +; NORMAL: strd r1, r2, [r0], #8 +; CONSERVATIVE-NOT: strd +; CHECK: bx lr define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) { %p0.1 = getelementptr i32, i32* %p0, i32 1 store i32 %v0, i32* %p0 diff --git a/test/CodeGen/ARM/ldstrex-m.ll b/test/CodeGen/ARM/ldstrex-m.ll index 3d83a9d78e35..5b717f7f1ae9 100644 --- a/test/CodeGen/ARM/ldstrex-m.ll +++ b/test/CodeGen/ARM/ldstrex-m.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7m-none-eabi -mcpu=cortex-m4 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi | FileCheck %s ; CHECK-LABEL: f0: ; CHECK-NOT: ldrexd diff --git a/test/CodeGen/ARM/legalize-unaligned-load.ll b/test/CodeGen/ARM/legalize-unaligned-load.ll index fa5b21aa4a23..eb4e942f0742 100644 --- a/test/CodeGen/ARM/legalize-unaligned-load.ll +++ b/test/CodeGen/ARM/legalize-unaligned-load.ll @@ -1,4 +1,4 @@ -; RUN: llc -O3 -code-model=default -relocation-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s +; RUN: llc -O3 -code-model=default -mtriple=armv7l-unknown-linux-gnueabihf -mcpu=generic %s -o - | FileCheck %s ; Check that we respect the existing chain between loads and stores when we ; legalize unaligned loads. ; Test case from PR24669. diff --git a/test/CodeGen/ARM/litpool-licm.ll b/test/CodeGen/ARM/litpool-licm.ll new file mode 100644 index 000000000000..dc6b37feaf05 --- /dev/null +++ b/test/CodeGen/ARM/litpool-licm.ll @@ -0,0 +1,46 @@ +; RUN: llc -mtriple=thumbv7-linux-gnueabihf -relocation-model=pic %s -o - | FileCheck %s + +@var = thread_local global i32 0, align 4 + +define void @func(i32 %n) { +; CHECK-LABEL: func: +; CHECK: ldr [[REF1:r[0-9]+]], [[CP1:.LCPI[0-9]+_[0-9]+]] +; CHECK: ldr [[REF2:r[0-9]+]], [[CP2:.LCPI[0-9]+_[0-9]+]] + +; CHECK: [[PCPOS1:.LPC[0-9]+_[0-9]+]]: +; CHECK-NEXT: add [[REF1]], pc + +; CHECK: [[PCPOS2:.LPC[0-9]+_[0-9]+]]: +; CHECK-NEXT: add [[REF2]], pc + +; CHECK: [[CP1]]: +; CHECK-NEXT: [[CP1_TMP:.Ltmp[0-9]+]]: +; CHECK-NEXT: .long var(TLSGD)-(([[PCPOS1]]+4)-[[CP1_TMP]]) + +; CHECK: [[CP2]]: +; CHECK-NEXT: [[CP2_TMP:.Ltmp[0-9]+]]: +; CHECK-NEXT: .long var(TLSGD)-(([[PCPOS2]]+4)-[[CP2_TMP]]) + +entry: + br label %loop + +loop: + %i = phi i32 [ %inc, %next ], [ 0, %entry ] + %val = load i32, i32* @var + %tst = icmp eq i32 %val, 0 + br i1 %tst, label %next, label %call + +call: + tail call void @foo(i32* nonnull @var) #2 + br label %next + +next: + %inc = add i32 %i, 1 + %stop = icmp eq i32 %inc, %n + br i1 %stop, label %done, label %loop + +done: + ret void +} + +declare void @foo(i32*) \ No newline at end of file diff --git a/test/CodeGen/ARM/local-call.ll b/test/CodeGen/ARM/local-call.ll new file mode 100644 index 000000000000..a38df62ff905 --- /dev/null +++ b/test/CodeGen/ARM/local-call.ll @@ -0,0 +1,20 @@ +; RUN: llc -mtriple=thumbv7-apple-ios -filetype=obj %s -o %t +; RUN: llvm-objdump -macho -d %t | FileCheck %s + +; This function just messes up the offsets enough to make the libcall in +; test_local_call unencodable with a blx. +define void @thing() { + ret void +} + +define i64 @__udivdi3(i64 %a, i64 %b) { + ret i64 %b +} + +define i64 @test_local_call(i64 %a, i64 %b) { +; CHECK-LABEL: test_local_call: +; CHECK: bl ___udivdi3 + +%res = udiv i64 %a, %b + ret i64 %res +} \ No newline at end of file diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll index 3f30fd40b7e7..cc2d745aae8e 100644 --- a/test/CodeGen/ARM/longMAC.ll +++ b/test/CodeGen/ARM/longMAC.ll @@ -116,3 +116,32 @@ define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) { ret i64 %add } +define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) { +;CHECK-LABEL: MACLongTest9: +;CHECK-V7-LE:umaal +;CHECK-V7-BE:umaal +;CHECK-NOT:umaal + %conv = zext i32 %lhs to i64 + %conv1 = zext i32 %rhs to i64 + %mul = mul nuw i64 %conv1, %conv + %conv2 = zext i32 %lo to i64 + %add = add i64 %mul, %conv2 + %conv3 = zext i32 %hi to i64 + %add2 = add i64 %add, %conv3 + ret i64 %add2 +} + +define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) { +;CHECK-LABEL: MACLongTest10: +;CHECK-V7-LE:umaal +;CHECK-V7-BE:umaal +;CHECK-NOT:umaal + %conv = zext i32 %lhs to i64 + %conv1 = zext i32 %rhs to i64 + %mul = mul nuw i64 %conv1, %conv + %conv2 = zext i32 %lo to i64 + %conv3 = zext i32 %hi to i64 + %add = add i64 %conv2, %conv3 + %add2 = add i64 %add, %mul + ret i64 %add2 +} diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index aa2b2d26d121..766710fd1d64 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -9,8 +9,8 @@ ; ; CHECK: ldr [[R6:r[0-9*]+]], LCP ; CHECK: cmp {{.*}}, [[R6]] -; CHECK: ldrle -; CHECK-NEXT: strle +; CHECK-NOT: lt +; CHECK: strlt target triple = "arm-apple-darwin8" diff --git a/test/CodeGen/ARM/macho-frame-offset.ll b/test/CodeGen/ARM/macho-frame-offset.ll new file mode 100644 index 000000000000..f3dacf66b6c3 --- /dev/null +++ b/test/CodeGen/ARM/macho-frame-offset.ll @@ -0,0 +1,12 @@ +; RUN: llc -mtriple thumbv7m-apple-macho -disable-fp-elim -o - %s | FileCheck %s + +define void @func() { +; CHECK-LABEL: func: +; CHECK: push {r6, r7, lr} +; CHECK: add r7, sp, #4 + call void @bar() + call void asm sideeffect "", "~{r11}"() + ret void +} + +declare void @bar() diff --git a/test/CodeGen/ARM/memcpy-no-inline.ll b/test/CodeGen/ARM/memcpy-no-inline.ll new file mode 100644 index 000000000000..126546095e1f --- /dev/null +++ b/test/CodeGen/ARM/memcpy-no-inline.ll @@ -0,0 +1,33 @@ +; RUN: llc -mtriple=thumbv7m-arm-none-eabi -mcpu=cortex-m3 < %s | FileCheck %s + +%struct.mystruct = type { [31 x i8] } + +@.str = private unnamed_addr constant [31 x i8] c"012345678901234567890123456789\00", align 1 +@.str.1 = private unnamed_addr constant [21 x i8] c"01234567890123456789\00", align 1 + +@myglobal = common global %struct.mystruct zeroinitializer, align 1 + +define void @foo() #0 { +entry: +; CHECK-LABEL: foo: +; CHECK: __aeabi_memcpy +; CHECK-NOT: ldm + %mystring = alloca [31 x i8], align 1 + %0 = getelementptr inbounds [31 x i8], [31 x i8]* %mystring, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str, i32 0, i32 0), i32 31, i32 1, i1 false) + ret void +} + +define void @bar() #0 { +entry: +; CHECK-LABEL: bar: +; CHECK-NOT: __aeabi_memcpy + %mystring = alloca [31 x i8], align 1 + %0 = getelementptr inbounds [31 x i8], [31 x i8]* %mystring, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([21 x i8], [21 x i8]* @.str.1, i32 0, i32 0), i32 21, i32 1, i1 false) + ret void +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1 + +attributes #0 = { minsize noinline nounwind optsize } diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll index 46fef7629cc4..bc60d8e4f0ec 100644 --- a/test/CodeGen/ARM/memfunc.ll +++ b/test/CodeGen/ARM/memfunc.ll @@ -5,6 +5,8 @@ ; RUN: llc < %s -mtriple=arm-none-androideabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-EABI --check-prefix=CHECK ; RUN: llc < %s -mtriple=arm-none-gnueabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK ; RUN: llc < %s -mtriple=arm-none-gnueabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK +; RUN: llc < %s -mtriple=arm-none-musleabi -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK +; RUN: llc < %s -mtriple=arm-none-musleabihf -disable-post-ra -o - | FileCheck %s --check-prefix=CHECK-GNUEABI --check-prefix=CHECK define void @f1(i8* %dest, i8* %src) { entry: @@ -384,6 +386,8 @@ entry: @arr5 = weak global [7 x i8] c"\01\02\03\04\05\06\07", align 1 @arr6 = weak_odr global [7 x i8] c"\01\02\03\04\05\06\07", align 1 @arr7 = external global [7 x i8], align 1 +@arr8 = internal global [128 x i8] undef +@arr9 = weak_odr global [128 x i8] undef define void @f9(i8* %dest, i32 %n) { entry: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr1, i32 0, i32 0), i32 %n, i32 1, i1 false) @@ -393,28 +397,35 @@ entry: call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr5, i32 0, i32 0), i32 %n, i32 1, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr6, i32 0, i32 0), i32 %n, i32 1, i1 false) call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @arr7, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @arr8, i32 0, i32 0), i32 %n, i32 1, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dest, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @arr9, i32 0, i32 0), i32 %n, i32 1, i1 false) unreachable } ; CHECK: {{\.data|\.section.+data}} -; CHECK-NOT: .align +; CHECK-NOT: .p2align ; CHECK: arr1: -; CHECK-IOS: .align 3 -; CHECK-DARWIN: .align 2 -; CHECK-EABI-NOT: .align -; CHECK-GNUEABI-NOT: .align +; CHECK-IOS: .p2align 3 +; CHECK-DARWIN: .p2align 2 +; CHECK-EABI-NOT: .p2align +; CHECK-GNUEABI-NOT: .p2align ; CHECK: arr2: ; CHECK: {{\.section.+foo,bar}} -; CHECK-NOT: .align +; CHECK-NOT: .p2align ; CHECK: arr3: -; CHECK-NOT: .align +; CHECK-NOT: .p2align ; CHECK: arr4: ; CHECK: {{\.data|\.section.+data}} -; CHECK-NOT: .align +; CHECK-NOT: .p2align ; CHECK: arr5: -; CHECK-NOT: .align +; CHECK-NOT: .p2align ; CHECK: arr6: +; CHECK: .p2align 4 +; CHECK: arr8: +; CHECK: .p2align 4 +; CHECK: arr9: + ; CHECK-NOT: arr7: declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/CodeGen/ARM/minsize-call-cse.ll b/test/CodeGen/ARM/minsize-call-cse.ll new file mode 100644 index 000000000000..072b76f03ba3 --- /dev/null +++ b/test/CodeGen/ARM/minsize-call-cse.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv7m-arm-none-eabi" + +; CHECK-LABEL: f: +; CHECK: blx r +; CHECK: blx r +; CHECK: blx r +define void @f() minsize optsize { +entry: + call void @g(i32 45, i32 66) + call void @g(i32 88, i32 32) + call void @g(i32 55, i32 33) + ret void +} + +; CHECK-LABEL: h: +; CHECK: bl g +; CHECK: bl g +define void @h() minsize optsize { +entry: + call void @g(i32 45, i32 66) + call void @g(i32 88, i32 32) + ret void +} + +declare void @g(i32,i32) diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll index 94c022ee2712..da9b698f2099 100644 --- a/test/CodeGen/ARM/movt.ll +++ b/test/CodeGen/ARM/movt.ll @@ -1,9 +1,11 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s ; rdar://7317664 +; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s + define i32 @t(i32 %X) nounwind { ; CHECK-LABEL: t: -; CHECK: movt r0, #65535 +; CHECK: movt r{{[0-9]}}, #65535 entry: %0 = or i32 %X, -65536 ret i32 %0 @@ -11,7 +13,7 @@ entry: define i32 @t2(i32 %X) nounwind { ; CHECK-LABEL: t2: -; CHECK: movt r0, #65534 +; CHECK: movt r{{[0-9]}}, #65534 entry: %0 = or i32 %X, -131072 %1 = and i32 %0, -65537 diff --git a/test/CodeGen/ARM/msr-it-block.ll b/test/CodeGen/ARM/msr-it-block.ll new file mode 100644 index 000000000000..0f9ff6b29d79 --- /dev/null +++ b/test/CodeGen/ARM/msr-it-block.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s --check-prefix=V6M --check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7m-none-eabi | FileCheck %s --check-prefix=V7M --check-prefix=CHECK +; RUN: llc < %s -mtriple=thumbv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK +; RUN: llc < %s -mtriple=armv7a-none-eabi | FileCheck %s --check-prefix=V7A --check-prefix=CHECK + + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "armv7a-arm-none-eabi" + +define void @test_const(i32 %val) { +; CHECK-LABEL: test_const: +entry: + %cmp = icmp eq i32 %val, 0 + br i1 %cmp, label %write_reg, label %exit + +write_reg: + tail call void @llvm.write_register.i32(metadata !0, i32 0) + tail call void @llvm.write_register.i32(metadata !0, i32 0) +; V6M: msr apsr, {{r[0-9]+}} +; V6M: msr apsr, {{r[0-9]+}} +; V7M: msr apsr_nzcvq, {{r[0-9]+}} +; V7M: msr apsr_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvqg, {{r[0-9]+}} + br label %exit + +exit: + ret void +} + +define void @test_var(i32 %val, i32 %apsr) { +; CHECK-LABEL: test_var: +entry: + %cmp = icmp eq i32 %val, 0 + br i1 %cmp, label %write_reg, label %exit + +write_reg: + tail call void @llvm.write_register.i32(metadata !0, i32 %apsr) + tail call void @llvm.write_register.i32(metadata !0, i32 %apsr) +; V6M: msr apsr, {{r[0-9]+}} +; V6M: msr apsr, {{r[0-9]+}} +; V7M: msr apsr_nzcvq, {{r[0-9]+}} +; V7M: msr apsr_nzcvq, {{r[0-9]+}} +; V7A: msr APSR_nzcvqg, {{r[0-9]+}} +; V7A: msr APSR_nzcvqg, {{r[0-9]+}} + br label %exit + +exit: + ret void +} + + +declare void @llvm.write_register.i32(metadata, i32) + +!0 = !{!"apsr"} diff --git a/test/CodeGen/ARM/none-macho.ll b/test/CodeGen/ARM/none-macho.ll index 733ba4ba2d2c..fee459f4f5e1 100644 --- a/test/CodeGen/ARM/none-macho.ll +++ b/test/CodeGen/ARM/none-macho.ll @@ -43,8 +43,8 @@ define i32 @test_frame_ptr() { ; CHECK-LABEL: test_frame_ptr: call void @test_trap() - ; Frame pointer is r11. -; CHECK: mov r11, sp + ; Frame pointer is r7. +; CHECK: mov r7, sp ret i32 42 } @@ -58,9 +58,11 @@ define void @test_two_areas(%big_arr* %addr) { ; This goes with the choice of r7 as FP (largely). FP and LR have to be stored ; consecutively on the stack for the frame record to be valid, which means we ; need the 2 register-save areas employed by iOS. -; CHECK-NON-FAST: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-NON-FAST: push {r4, r5, r6, r7, lr} +; CHECK-NON-FAST: push.w {r8, r9, r10, r11} ; ... -; CHECK-NON-FAST: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} +; CHECK-NON-FAST: pop.w {r8, r9, r10, r11} +; CHECK-NON-FAST: pop {r4, r5, r6, r7, pc} ret void } diff --git a/test/CodeGen/ARM/pic.ll b/test/CodeGen/ARM/pic.ll index 9fc7a63bd687..d12addb69d77 100644 --- a/test/CodeGen/ARM/pic.ll +++ b/test/CodeGen/ARM/pic.ll @@ -11,10 +11,10 @@ define void @test() { entry: %0 = call i32 @get() -; CHECK: bl get(PLT) +; CHECK: bl get call void @put(i32 %0) -; CHECK: bl put(PLT) +; CHECK: bl put ret void } diff --git a/test/CodeGen/ARM/pie.ll b/test/CodeGen/ARM/pie.ll new file mode 100644 index 000000000000..1b1e6e62fda5 --- /dev/null +++ b/test/CodeGen/ARM/pie.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=armv7-pc-linux-gnueabi -relocation-model=pic < %s | FileCheck %s + +@foo = global i32 42 + +define i32* @get_foo() { + ret i32* @foo +} + +; Test that we only use one load. Even that is only needed because there +; doesn't seem to be pc relative relocations for movw movt. +; CHECK: ldr r0, .LCPI0_0 +; CHECK-NEXT: .L{{.*}}: +; CHECK-NEXT: add r0, pc, r0 +; CHECK-NEXT: bx lr + +!llvm.module.flags = !{!0} + +!0 = !{i32 1, !"PIE Level", i32 2} diff --git a/test/CodeGen/ARM/plt-relative-reloc.ll b/test/CodeGen/ARM/plt-relative-reloc.ll new file mode 100644 index 000000000000..08dcfdf1298f --- /dev/null +++ b/test/CodeGen/ARM/plt-relative-reloc.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=armv7-unknown-linux -o - %s | FileCheck %s + +@vtable = constant [4 x i32] [i32 0, + i32 sub (i32 ptrtoint (void ()* @fn1 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32)), + i32 sub (i32 ptrtoint (void ()* @fn2 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32)), + i32 sub (i32 ptrtoint (void ()* @fn3 to i32), i32 ptrtoint (i32* getelementptr ([4 x i32], [4 x i32]* @vtable, i32 0, i32 1) to i32)) +] + +declare void @fn1() unnamed_addr +declare void @fn2() unnamed_addr +declare void @fn3() + +; CHECK: .long 0 +; CHECK-NEXT: .long (fn1(prel31)-vtable)-4 +; CHECK-NEXT: .long (fn2(prel31)-vtable)-4 +; CHECK-NEXT: .long (fn3-vtable)-4 diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll index 74f90640ca6e..fd61811f49cf 100644 --- a/test/CodeGen/ARM/popcnt.ll +++ b/test/CodeGen/ARM/popcnt.ll @@ -71,12 +71,28 @@ define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } +define <1 x i64> @vcnt64(<1 x i64>* %A) nounwind { +; CHECK-LABEL: vcnt64: + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.ctpop.v1i64(<1 x i64> %tmp1) + ret <1 x i64> %tmp2 +} + +define <2 x i64> @vcntQ64(<2 x i64>* %A) nounwind { +; CHECK-LABEL: vcntQ64: + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp1) + ret <2 x i64> %tmp2 +} + declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone declare <4 x i16> @llvm.ctpop.v4i16(<4 x i16>) nounwind readnone declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone +declare <1 x i64> @llvm.ctpop.v1i64(<1 x i64>) nounwind readnone +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclz8: diff --git a/test/CodeGen/ARM/pr26669.ll b/test/CodeGen/ARM/pr26669.ll new file mode 100644 index 000000000000..6c28ddd2d848 --- /dev/null +++ b/test/CodeGen/ARM/pr26669.ll @@ -0,0 +1,31 @@ +; RUN: opt -S -globaldce -sjljehprepare < %s | FileCheck %s +target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7--ios5.0.0" + +define void @g() personality i32 (...)* @__gxx_personality_sj0 { +entry: + %exn.slot = alloca i8* + %ehselector.slot = alloca i32 + invoke void @f() + to label %try.cont unwind label %lpad + +lpad: ; preds = %entry + %0 = landingpad { i8*, i32 } + cleanup + br label %try.cont + +try.cont: ; preds = %catch, %invoke.cont + ret void +} + +declare void @f() + +declare i32 @__gxx_personality_sj0(...) + +; CHECK-LABEL: define void @g( +; CHECK: call void @llvm.eh.sjlj.callsite( +; CHECK: call void @_Unwind_SjLj_Register( +; CHECK: invoke void @f( +; CHECK: landingpad +; CHECK-NEXT: cleanup +; CHECK: call void @_Unwind_SjLj_Unregister( diff --git a/test/CodeGen/ARM/preferred-align.ll b/test/CodeGen/ARM/preferred-align.ll index 8cd4ef615468..a9a17229e064 100644 --- a/test/CodeGen/ARM/preferred-align.ll +++ b/test/CodeGen/ARM/preferred-align.ll @@ -3,19 +3,19 @@ @var_agg = global {i8, i8} zeroinitializer ; CHECK: .globl var_agg -; CHECK-NEXT: .align 2 +; CHECK-NEXT: .p2align 2 @var1 = global i1 zeroinitializer ; CHECK: .globl var1 -; CHECK-NOT: .align +; CHECK-NOT: .p2align @var8 = global i8 zeroinitializer ; CHECK: .globl var8 -; CHECK-NOT: .align +; CHECK-NOT: .p2align @var16 = global i16 zeroinitializer ; CHECK: .globl var16 -; CHECK-NEXT: .align 1 \ No newline at end of file +; CHECK-NEXT: .p2align 1 \ No newline at end of file diff --git a/test/CodeGen/ARM/rem_crash.ll b/test/CodeGen/ARM/rem_crash.ll new file mode 100644 index 000000000000..bce597c030d2 --- /dev/null +++ b/test/CodeGen/ARM/rem_crash.ll @@ -0,0 +1,257 @@ +; RUN: llc < %s -mtriple=arm-unknown-unknown + +define i8 @test_minsize_uu8(i8 %x) minsize optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_ss8(i8 %x) minsize optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_us8(i8 %x) minsize optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_minsize_su8(i8 %x) minsize optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i16 @test_minsize_uu16(i16 %x) minsize optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_ss16(i16 %x) minsize optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_us16(i16 %x) minsize optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_minsize_su16(i16 %x) minsize optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i32 @test_minsize_uu32(i32 %x) minsize optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_ss32(i32 %x) minsize optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_us32(i32 %x) minsize optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_minsize_su32(i32 %x) minsize optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i64 @test_minsize_uu64(i64 %x) minsize optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_ss64(i64 %x) minsize optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_us64(i64 %x) minsize optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_minsize_su64(i64 %x) minsize optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i8 @test_uu8(i8 %x) optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_ss8(i8 %x) optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_us8(i8 %x) optsize { +entry: + %0 = udiv i8 %x, 10 + %1 = srem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i8 @test_su8(i8 %x) optsize { +entry: + %0 = sdiv i8 %x, 10 + %1 = urem i8 %x, 10 + %res = add i8 %0, %1 + ret i8 %res +} + +define i16 @test_uu16(i16 %x) optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_ss16(i16 %x) optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_us16(i16 %x) optsize { +entry: + %0 = udiv i16 %x, 10 + %1 = srem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i16 @test_su16(i16 %x) optsize { +entry: + %0 = sdiv i16 %x, 10 + %1 = urem i16 %x, 10 + %res = add i16 %0, %1 + ret i16 %res +} + +define i32 @test_uu32(i32 %x) optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_ss32(i32 %x) optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_us32(i32 %x) optsize { +entry: + %0 = udiv i32 %x, 10 + %1 = srem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i32 @test_su32(i32 %x) optsize { +entry: + %0 = sdiv i32 %x, 10 + %1 = urem i32 %x, 10 + %res = add i32 %0, %1 + ret i32 %res +} + +define i64 @test_uu64(i64 %x) optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_ss64(i64 %x) optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_us64(i64 %x) optsize { +entry: + %0 = udiv i64 %x, 10 + %1 = srem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} + +define i64 @test_su64(i64 %x) optsize { +entry: + %0 = sdiv i64 %x, 10 + %1 = urem i64 %x, 10 + %res = add i64 %0, %1 + ret i64 %res +} diff --git a/test/CodeGen/ARM/returned-ext.ll b/test/CodeGen/ARM/returned-ext.ll index 925e9e729f44..f592d0aec5f7 100644 --- a/test/CodeGen/ARM/returned-ext.ll +++ b/test/CodeGen/ARM/returned-ext.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s -check-prefix=CHECKELF -; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 | FileCheck %s -check-prefix=CHECKT2D +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -arm-this-return-forwarding | FileCheck %s -check-prefix=CHECKELF +; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 -arm-this-return-forwarding | FileCheck %s -check-prefix=CHECKT2D declare i16 @identity16(i16 returned %x) declare i32 @identity32(i32 returned %x) @@ -18,9 +18,9 @@ entry: ; CHECKELF: mov r0, [[SAVEX]] ; CHECKT2D-LABEL: test_identity: ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 -; CHECKT2D: blx _identity16 +; CHECKT2D: bl _identity16 ; CHECKT2D: uxth r0, r0 -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 ; CHECKT2D: mov r0, [[SAVEX]] %call = tail call i16 @identity16(i16 %x) %b = zext i16 %call to i32 @@ -49,9 +49,9 @@ entry: ; This shouldn't be required ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 -; CHECKT2D: blx _retzext16 +; CHECKT2D: bl _retzext16 ; CHECKT2D-NOT: uxth r0, {{r[0-9]+}} -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 ; This shouldn't be required ; CHECKT2D: mov r0, [[SAVEX]] @@ -72,9 +72,9 @@ entry: ; CHECKELF: mov r0, [[SAVEX]] ; CHECKT2D-LABEL: test_mismatched_ret: ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 -; CHECKT2D: blx _retzext16 +; CHECKT2D: bl _retzext16 ; CHECKT2D: sxth r0, {{r[0-9]+}} -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 ; CHECKT2D: mov r0, [[SAVEX]] %call = tail call i16 @retzext16(i16 %x) %b = sext i16 %call to i32 @@ -92,9 +92,9 @@ entry: ; CHECKELF: b paramzext16 ; CHECKT2D-LABEL: test_matched_paramext: ; CHECKT2D: uxth r0, r0 -; CHECKT2D: blx _paramzext16 +; CHECKT2D: bl _paramzext16 ; CHECKT2D: uxth r0, r0 -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 ; CHECKT2D: b.w _paramzext16 %call = tail call i16 @paramzext16(i16 %x) %b = zext i16 %call to i32 @@ -118,8 +118,8 @@ entry: ; CHECKELF: bl identity32 ; CHECKELF: b paramzext16 ; CHECKT2D-LABEL: test_matched_paramext2: -; CHECKT2D: blx _paramzext16 -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _paramzext16 +; CHECKT2D: bl _identity32 ; CHECKT2D: b.w _paramzext16 %call = tail call i16 @paramzext16(i16 %x) @@ -143,11 +143,11 @@ entry: ; CHECKT2D-LABEL: test_matched_bothext: ; CHECKT2D: uxth r0, r0 -; CHECKT2D: blx _bothzext16 +; CHECKT2D: bl _bothzext16 ; CHECKT2D-NOT: uxth r0, r0 ; FIXME: Tail call should be OK here -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 %call = tail call i16 @bothzext16(i16 %x) %b = zext i16 %x to i32 @@ -167,9 +167,9 @@ entry: ; CHECKT2D-LABEL: test_mismatched_bothext: ; CHECKT2D: mov [[SAVEX:r[0-9]+]], r0 ; CHECKT2D: uxth r0, {{r[0-9]+}} -; CHECKT2D: blx _bothzext16 +; CHECKT2D: bl _bothzext16 ; CHECKT2D: sxth r0, [[SAVEX]] -; CHECKT2D: blx _identity32 +; CHECKT2D: bl _identity32 ; CHECKT2D: mov r0, [[SAVEX]] %call = tail call i16 @bothzext16(i16 %x) %b = sext i16 %x to i32 diff --git a/test/CodeGen/ARM/sincos.ll b/test/CodeGen/ARM/sincos.ll index 30b2664e3726..5be0044ddbd3 100644 --- a/test/CodeGen/ARM/sincos.ll +++ b/test/CodeGen/ARM/sincos.ll @@ -1,5 +1,8 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios6 -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT ; RUN: llc < %s -mtriple=armv7-apple-ios7 -mcpu=cortex-a8 | FileCheck %s --check-prefix=SINCOS +; RUN: llc < %s -mtriple=armv7-linux-gnu -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT-GNU +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 \ +; RUN: --enable-unsafe-fp-math | FileCheck %s --check-prefix=SINCOS-GNU ; Combine sin / cos into a single call. ; rdar://12856873 @@ -9,9 +12,17 @@ entry: ; SINCOS-LABEL: test1: ; SINCOS: bl ___sincosf_stret +; SINCOS-GNU-LABEL: test1: +; SINCOS-GNU: bl sincosf + ; NOOPT-LABEL: test1: ; NOOPT: bl _sinf ; NOOPT: bl _cosf + +; NOOPT-GNU-LABEL: test1: +; NOOPT-GNU: bl sinf +; NOOPT-GNU: bl cosf + %call = tail call float @sinf(float %x) nounwind readnone %call1 = tail call float @cosf(float %x) nounwind readnone %add = fadd float %call, %call1 @@ -23,9 +34,16 @@ entry: ; SINCOS-LABEL: test2: ; SINCOS: bl ___sincos_stret +; SINCOS-GNU-LABEL: test2: +; SINCOS-GNU: bl sincos + ; NOOPT-LABEL: test2: ; NOOPT: bl _sin ; NOOPT: bl _cos + +; NOOPT-GNU-LABEL: test2: +; NOOPT-GNU: bl sin +; NOOPT-GNU: bl cos %call = tail call double @sin(double %x) nounwind readnone %call1 = tail call double @cos(double %x) nounwind readnone %add = fadd double %call, %call1 diff --git a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll index a1abef9605ca..17393e44b12e 100644 --- a/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll +++ b/test/CodeGen/ARM/sjlj-prepare-critical-edge.ll @@ -74,8 +74,8 @@ declare void @terminatev() ; %do.body.i.i.i. ; CHECK-LABEL: __Z4foo1c: -; CHECK: blx __Znwm -; CHECK: {{.*}}@ %entry.do.body.i.i.i_crit_edge +; CHECK: bl __Znwm +; CHECK: {{.*}}@ %do.body.i.i.i.preheader ; CHECK: str r0, [sp, [[OFFSET:#[0-9]+]]] ; CHECK: {{.*}}@ %do.body.i.i.i ; CHECK: ldr [[R0:r[0-9]+]], [sp, [[OFFSET]]] diff --git a/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll b/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll index b44b447b3dff..323d5037138e 100644 --- a/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll +++ b/test/CodeGen/ARM/sjljehprepare-lower-empty-struct.ll @@ -2,7 +2,8 @@ ; RUN: llc -mtriple=armv7-apple-ios -O1 < %s | FileCheck %s ; RUN: llc -mtriple=armv7-apple-ios -O2 < %s | FileCheck %s ; RUN: llc -mtriple=armv7-apple-ios -O3 < %s | FileCheck %s -; RUN: llc -mtriple=armv7k-apple-ios < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-watchos -O3 < %s | FileCheck %s +; RUN: llc -mtriple=armv7k-apple-ios < %s | FileCheck %s --check-prefix=CHECK-WATCH ; SjLjEHPrepare shouldn't crash when lowering empty structs. ; @@ -16,6 +17,9 @@ entry: ; CHECK: bl __Unwind_SjLj_Register ; CHECK-NEXT: {{[A-Z][a-zA-Z0-9]*}}: ; CHECK-NEXT: bl _bar + +; CHECK-WATCH-NOT: bl __Unwind_SjLj_Register + invoke void @bar () to label %unreachable unwind label %handler diff --git a/test/CodeGen/ARM/smul.ll b/test/CodeGen/ARM/smul.ll index 13873f511e1f..4e6f7d5c67b0 100644 --- a/test/CodeGen/ARM/smul.ll +++ b/test/CodeGen/ARM/smul.ll @@ -1,11 +1,12 @@ ; RUN: llc -mtriple=arm-eabi -mcpu=generic %s -o /dev/null ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s +; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s @x = weak global i16 0 ; [#uses=1] @y = weak global i16 0 ; [#uses=0] define i32 @f1(i32 %y) { -; CHECK: f1 +; CHECK-LABEL: f1: ; CHECK: smulbt %tmp = load i16, i16* @x ; [#uses=1] %tmp1 = add i16 %tmp, 2 ; [#uses=1] @@ -16,7 +17,7 @@ define i32 @f1(i32 %y) { } define i32 @f2(i32 %x, i32 %y) { -; CHECK: f2 +; CHECK-LABEL: f2: ; CHECK: smultt %tmp1 = ashr i32 %x, 16 ; [#uses=1] %tmp3 = ashr i32 %y, 16 ; [#uses=1] @@ -25,7 +26,7 @@ define i32 @f2(i32 %x, i32 %y) { } define i32 @f3(i32 %a, i16 %x, i32 %y) { -; CHECK: f3 +; CHECK-LABEL: f3: ; CHECK: smlabt %tmp = sext i16 %x to i32 ; [#uses=1] %tmp2 = ashr i32 %y, 16 ; [#uses=1] @@ -34,3 +35,107 @@ define i32 @f3(i32 %a, i16 %x, i32 %y) { ret i32 %tmp5 } +define i32 @f4(i32 %a, i32 %x, i32 %y) { +; CHECK-LABEL: f4: +; CHECK: smlatt + %tmp1 = ashr i32 %x, 16 + %tmp3 = ashr i32 %y, 16 + %tmp4 = mul i32 %tmp3, %tmp1 + %tmp5 = add i32 %tmp4, %a + ret i32 %tmp5 +} + +define i32 @f5(i32 %a, i16 %x, i16 %y) { +; CHECK-LABEL: f5: +; CHECK: smlabb + %tmp1 = sext i16 %x to i32 + %tmp3 = sext i16 %y to i32 + %tmp4 = mul i32 %tmp3, %tmp1 + %tmp5 = add i32 %tmp4, %a + ret i32 %tmp5 +} + +define i32 @f6(i32 %a, i16 %x, i32 %y) { +; CHECK-LABEL: f6: +; CHECK: smlabt + %tmp1 = sext i16 %x to i32 + %tmp3 = ashr i32 %y, 16 + %tmp4 = mul i32 %tmp3, %tmp1 + %tmp5 = add i32 %tmp4, %a + ret i32 %tmp5 +} + +define i32 @f7(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f7: +; CHECK: smlawb + %shl = shl i32 %b, 16 + %shr = ashr exact i32 %shl, 16 + %conv = sext i32 %a to i64 + %conv2 = sext i32 %shr to i64 + %mul = mul nsw i64 %conv2, %conv + %shr49 = lshr i64 %mul, 16 + %conv5 = trunc i64 %shr49 to i32 + %add = add nsw i32 %conv5, %c + ret i32 %add +} + +define i32 @f8(i32 %a, i16 signext %b, i32 %c) { +; CHECK-LABEL: f8: +; CHECK: smlawb + %conv = sext i32 %a to i64 + %conv1 = sext i16 %b to i64 + %mul = mul nsw i64 %conv1, %conv + %shr5 = lshr i64 %mul, 16 + %conv2 = trunc i64 %shr5 to i32 + %add = add nsw i32 %conv2, %c + ret i32 %add +} + +define i32 @f9(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f9: +; CHECK: smlawt + %conv = sext i32 %a to i64 + %shr = ashr i32 %b, 16 + %conv1 = sext i32 %shr to i64 + %mul = mul nsw i64 %conv1, %conv + %shr26 = lshr i64 %mul, 16 + %conv3 = trunc i64 %shr26 to i32 + %add = add nsw i32 %conv3, %c + ret i32 %add +} + +define i32 @f10(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f10: +; CHECK: smulwb + %shl = shl i32 %b, 16 + %shr = ashr exact i32 %shl, 16 + %conv = sext i32 %a to i64 + %conv2 = sext i32 %shr to i64 + %mul = mul nsw i64 %conv2, %conv + %shr37 = lshr i64 %mul, 16 + %conv4 = trunc i64 %shr37 to i32 + ret i32 %conv4 +} + +define i32 @f11(i32 %a, i16 signext %b, i32 %c) { +; CHECK-LABEL: f11: +; CHECK: smulwb + %conv = sext i32 %a to i64 + %conv1 = sext i16 %b to i64 + %mul = mul nsw i64 %conv1, %conv + %shr4 = lshr i64 %mul, 16 + %conv2 = trunc i64 %shr4 to i32 + ret i32 %conv2 +} + +define i32 @f12(i32 %a, i32 %b, i32 %c) { +; CHECK-LABEL: f12: +; CHECK: smulwt + %conv = sext i32 %a to i64 + %shr = ashr i32 %b, 16 + %conv1 = sext i32 %shr to i64 + %mul = mul nsw i64 %conv1, %conv + %shr25 = lshr i64 %mul, 16 + %conv3 = trunc i64 %shr25 to i32 + ret i32 %conv3 +} diff --git a/test/CodeGen/ARM/smulw.ll b/test/CodeGen/ARM/smulw.ll deleted file mode 100644 index 8653903eee53..000000000000 --- a/test/CodeGen/ARM/smulw.ll +++ /dev/null @@ -1,26 +0,0 @@ -; RUN: llc -mtriple=arm--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s - -; We cannot codegen the smulw[bt] or smlaw[bt] instructions for these functions, -; as the top 16 bits of the result would differ - -define i32 @f1(i32 %a, i16 %b) { -; CHECK-LABEL: f1: -; CHECK: mul -; CHECK: asr - %tmp1 = sext i16 %b to i32 - %tmp2 = mul i32 %a, %tmp1 - %tmp3 = ashr i32 %tmp2, 16 - ret i32 %tmp3 -} - -define i32 @f2(i32 %a, i16 %b, i32 %c) { -; CHECK-LABEL: f2: -; CHECK: mul -; CHECK: add{{.*}}, asr #16 - %tmp1 = sext i16 %b to i32 - %tmp2 = mul i32 %a, %tmp1 - %tmp3 = ashr i32 %tmp2, 16 - %tmp4 = add i32 %tmp3, %c - ret i32 %tmp4 -} diff --git a/test/CodeGen/ARM/special-reg-v8m-base.ll b/test/CodeGen/ARM/special-reg-v8m-base.ll new file mode 100644 index 000000000000..20284daa0463 --- /dev/null +++ b/test/CodeGen/ARM/special-reg-v8m-base.ll @@ -0,0 +1,142 @@ +; RUN: not llc < %s -mtriple=thumb-none-eabi -mcpu=cortex-m4 2>&1 | FileCheck %s --check-prefix=V7M +; RUN: llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s + +; V7M: LLVM ERROR: Invalid register name "sp_ns". + +define i32 @read_mclass_registers() nounwind { +entry: + ; CHECK-LABEL: read_mclass_registers: + ; CHECK: mrs r0, apsr + ; CHECK: mrs r1, iapsr + ; CHECK: mrs r1, eapsr + ; CHECK: mrs r1, xpsr + ; CHECK: mrs r1, ipsr + ; CHECK: mrs r1, epsr + ; CHECK: mrs r1, iepsr + ; CHECK: mrs r1, msp + ; CHECK: mrs r1, psp + ; CHECK: mrs r1, primask + ; CHECK: mrs r1, control + ; CHECK: mrs r1, msplim + ; CHECK: mrs r1, psplim + ; CHECK: mrs r1, msp_ns + ; CHECK: mrs r1, psp_ns + ; CHECK: mrs r1, primask_ns + ; CHECK: mrs r1, control_ns + ; CHECK: mrs r1, sp_ns + + %0 = call i32 @llvm.read_register.i32(metadata !0) + %1 = call i32 @llvm.read_register.i32(metadata !4) + %add1 = add i32 %1, %0 + %2 = call i32 @llvm.read_register.i32(metadata !8) + %add2 = add i32 %add1, %2 + %3 = call i32 @llvm.read_register.i32(metadata !12) + %add3 = add i32 %add2, %3 + %4 = call i32 @llvm.read_register.i32(metadata !16) + %add4 = add i32 %add3, %4 + %5 = call i32 @llvm.read_register.i32(metadata !17) + %add5 = add i32 %add4, %5 + %6 = call i32 @llvm.read_register.i32(metadata !18) + %add6 = add i32 %add5, %6 + %7 = call i32 @llvm.read_register.i32(metadata !19) + %add7 = add i32 %add6, %7 + %8 = call i32 @llvm.read_register.i32(metadata !20) + %add8 = add i32 %add7, %8 + %9 = call i32 @llvm.read_register.i32(metadata !21) + %add9 = add i32 %add8, %9 + %10 = call i32 @llvm.read_register.i32(metadata !25) + %add10 = add i32 %add9, %10 + %11 = call i32 @llvm.read_register.i32(metadata !26) + %add11 = add i32 %add10, %11 + %12 = call i32 @llvm.read_register.i32(metadata !27) + %add12 = add i32 %add11, %12 + %13 = call i32 @llvm.read_register.i32(metadata !28) + %add13 = add i32 %add12, %13 + %14 = call i32 @llvm.read_register.i32(metadata !29) + %add14 = add i32 %add13, %14 + %15 = call i32 @llvm.read_register.i32(metadata !32) + %add15 = add i32 %add14, %15 + %16 = call i32 @llvm.read_register.i32(metadata !35) + %add16 = add i32 %add15, %16 + %17 = call i32 @llvm.read_register.i32(metadata !36) + %add17 = add i32 %add16, %17 + ret i32 %add10 +} + +define void @write_mclass_registers(i32 %x) nounwind { +entry: + ; CHECK-LABEL: write_mclass_registers: + ; CHECK: msr apsr, r0 + ; CHECK: msr apsr, r0 + ; CHECK: msr iapsr, r0 + ; CHECK: msr iapsr, r0 + ; CHECK: msr eapsr, r0 + ; CHECK: msr eapsr, r0 + ; CHECK: msr xpsr, r0 + ; CHECK: msr xpsr, r0 + ; CHECK: msr ipsr, r0 + ; CHECK: msr epsr, r0 + ; CHECK: msr iepsr, r0 + ; CHECK: msr msp, r0 + ; CHECK: msr psp, r0 + ; CHECK: msr primask, r0 + ; CHECK: msr control, r0 + ; CHECK: msr msplim, r0 + ; CHECK: msr psplim, r0 + ; CHECK: msr msp_ns, r0 + ; CHECK: msr psp_ns, r0 + ; CHECK: msr primask_ns, r0 + ; CHECK: msr control_ns, r0 + ; CHECK: msr sp_ns, r0 + + call void @llvm.write_register.i32(metadata !0, i32 %x) + call void @llvm.write_register.i32(metadata !1, i32 %x) + call void @llvm.write_register.i32(metadata !4, i32 %x) + call void @llvm.write_register.i32(metadata !5, i32 %x) + call void @llvm.write_register.i32(metadata !8, i32 %x) + call void @llvm.write_register.i32(metadata !9, i32 %x) + call void @llvm.write_register.i32(metadata !12, i32 %x) + call void @llvm.write_register.i32(metadata !13, i32 %x) + call void @llvm.write_register.i32(metadata !16, i32 %x) + call void @llvm.write_register.i32(metadata !17, i32 %x) + call void @llvm.write_register.i32(metadata !18, i32 %x) + call void @llvm.write_register.i32(metadata !19, i32 %x) + call void @llvm.write_register.i32(metadata !20, i32 %x) + call void @llvm.write_register.i32(metadata !21, i32 %x) + call void @llvm.write_register.i32(metadata !25, i32 %x) + call void @llvm.write_register.i32(metadata !26, i32 %x) + call void @llvm.write_register.i32(metadata !27, i32 %x) + call void @llvm.write_register.i32(metadata !28, i32 %x) + call void @llvm.write_register.i32(metadata !29, i32 %x) + call void @llvm.write_register.i32(metadata !32, i32 %x) + call void @llvm.write_register.i32(metadata !35, i32 %x) + call void @llvm.write_register.i32(metadata !36, i32 %x) + ret void +} + +declare i32 @llvm.read_register.i32(metadata) nounwind +declare void @llvm.write_register.i32(metadata, i32) nounwind + +!0 = !{!"apsr"} +!1 = !{!"apsr_nzcvq"} +!4 = !{!"iapsr"} +!5 = !{!"iapsr_nzcvq"} +!8 = !{!"eapsr"} +!9 = !{!"eapsr_nzcvq"} +!12 = !{!"xpsr"} +!13 = !{!"xpsr_nzcvq"} +!16 = !{!"ipsr"} +!17 = !{!"epsr"} +!18 = !{!"iepsr"} +!19 = !{!"msp"} +!20 = !{!"psp"} +!21 = !{!"primask"} +!25 = !{!"control"} +!26 = !{!"msplim"} +!27 = !{!"psplim"} +!28 = !{!"msp_ns"} +!29 = !{!"psp_ns"} +!32 = !{!"primask_ns"} +!35 = !{!"control_ns"} +!36 = !{!"sp_ns"} + diff --git a/test/CodeGen/ARM/special-reg-v8m-main.ll b/test/CodeGen/ARM/special-reg-v8m-main.ll new file mode 100644 index 000000000000..cde296c6b218 --- /dev/null +++ b/test/CodeGen/ARM/special-reg-v8m-main.ll @@ -0,0 +1,214 @@ +; RUN: not llc < %s -mtriple=thumbv8m.base-none-eabi 2>&1 | FileCheck %s --check-prefix=BASELINE +; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+dsp 2>&1 | FileCheck %s --check-prefix=MAINLINE + +; BASELINE: LLVM ERROR: Invalid register name "basepri_max_ns". + +define i32 @read_mclass_registers() nounwind { +entry: + ; MAINLINE-LABEL: read_mclass_registers: + ; MAINLINE: mrs r0, apsr + ; MAINLINE: mrs r1, iapsr + ; MAINLINE: mrs r1, eapsr + ; MAINLINE: mrs r1, xpsr + ; MAINLINE: mrs r1, ipsr + ; MAINLINE: mrs r1, epsr + ; MAINLINE: mrs r1, iepsr + ; MAINLINE: mrs r1, msp + ; MAINLINE: mrs r1, psp + ; MAINLINE: mrs r1, primask + ; MAINLINE: mrs r1, basepri + ; MAINLINE: mrs r1, basepri_max + ; MAINLINE: mrs r1, faultmask + ; MAINLINE: mrs r1, control + ; MAINLINE: mrs r1, msplim + ; MAINLINE: mrs r1, psplim + ; MAINLINE: mrs r1, msp_ns + ; MAINLINE: mrs r1, psp_ns + ; MAINLINE: mrs r1, msplim_ns + ; MAINLINE: mrs r1, psplim_ns + ; MAINLINE: mrs r1, primask_ns + ; MAINLINE: mrs r1, basepri_ns + ; MAINLINE: mrs r1, faultmask_ns + ; MAINLINE: mrs r1, control_ns + ; MAINLINE: mrs r1, sp_ns + ; MAINLINE: mrs r1, basepri_max_ns + + %0 = call i32 @llvm.read_register.i32(metadata !0) + %1 = call i32 @llvm.read_register.i32(metadata !4) + %add1 = add i32 %1, %0 + %2 = call i32 @llvm.read_register.i32(metadata !8) + %add2 = add i32 %add1, %2 + %3 = call i32 @llvm.read_register.i32(metadata !12) + %add3 = add i32 %add2, %3 + %4 = call i32 @llvm.read_register.i32(metadata !16) + %add4 = add i32 %add3, %4 + %5 = call i32 @llvm.read_register.i32(metadata !17) + %add5 = add i32 %add4, %5 + %6 = call i32 @llvm.read_register.i32(metadata !18) + %add6 = add i32 %add5, %6 + %7 = call i32 @llvm.read_register.i32(metadata !19) + %add7 = add i32 %add6, %7 + %8 = call i32 @llvm.read_register.i32(metadata !20) + %add8 = add i32 %add7, %8 + %9 = call i32 @llvm.read_register.i32(metadata !21) + %add9 = add i32 %add8, %9 + %10 = call i32 @llvm.read_register.i32(metadata !22) + %add10 = add i32 %add9, %10 + %11 = call i32 @llvm.read_register.i32(metadata !23) + %add11 = add i32 %add10, %11 + %12 = call i32 @llvm.read_register.i32(metadata !24) + %add12 = add i32 %add11, %12 + %13 = call i32 @llvm.read_register.i32(metadata !25) + %add13 = add i32 %add12, %13 + %14 = call i32 @llvm.read_register.i32(metadata !26) + %add14 = add i32 %add13, %14 + %15 = call i32 @llvm.read_register.i32(metadata !27) + %add15 = add i32 %add14, %15 + %16 = call i32 @llvm.read_register.i32(metadata !28) + %add16 = add i32 %add15, %16 + %17 = call i32 @llvm.read_register.i32(metadata !29) + %add17 = add i32 %add16, %17 + %18 = call i32 @llvm.read_register.i32(metadata !30) + %add18 = add i32 %add17, %18 + %19 = call i32 @llvm.read_register.i32(metadata !31) + %add19 = add i32 %add18, %19 + %20 = call i32 @llvm.read_register.i32(metadata !32) + %add20 = add i32 %add19, %20 + %21 = call i32 @llvm.read_register.i32(metadata !33) + %add21 = add i32 %add20, %21 + %22 = call i32 @llvm.read_register.i32(metadata !34) + %add22 = add i32 %add21, %22 + %23 = call i32 @llvm.read_register.i32(metadata !35) + %add23 = add i32 %add22, %23 + %24 = call i32 @llvm.read_register.i32(metadata !36) + %add24 = add i32 %add23, %24 + %25 = call i32 @llvm.read_register.i32(metadata !37) + %add25 = add i32 %add24, %25 + ret i32 %add25 +} + +define void @write_mclass_registers(i32 %x) nounwind { +entry: + ; MAINLINE-LABEL: write_mclass_registers: + ; MAINLINE: msr apsr_nzcvqg, r0 + ; MAINLINE: msr apsr_nzcvq, r0 + ; MAINLINE: msr apsr_g, r0 + ; MAINLINE: msr apsr_nzcvqg, r0 + ; MAINLINE: msr iapsr_nzcvqg, r0 + ; MAINLINE: msr iapsr_nzcvq, r0 + ; MAINLINE: msr iapsr_g, r0 + ; MAINLINE: msr iapsr_nzcvqg, r0 + ; MAINLINE: msr eapsr_nzcvqg, r0 + ; MAINLINE: msr eapsr_nzcvq, r0 + ; MAINLINE: msr eapsr_g, r0 + ; MAINLINE: msr eapsr_nzcvqg, r0 + ; MAINLINE: msr xpsr_nzcvqg, r0 + ; MAINLINE: msr xpsr_nzcvq, r0 + ; MAINLINE: msr xpsr_g, r0 + ; MAINLINE: msr xpsr_nzcvqg, r0 + ; MAINLINE: msr ipsr, r0 + ; MAINLINE: msr epsr, r0 + ; MAINLINE: msr iepsr, r0 + ; MAINLINE: msr msp, r0 + ; MAINLINE: msr psp, r0 + ; MAINLINE: msr primask, r0 + ; MAINLINE: msr basepri, r0 + ; MAINLINE: msr basepri_max, r0 + ; MAINLINE: msr faultmask, r0 + ; MAINLINE: msr control, r0 + ; MAINLINE: msr msplim, r0 + ; MAINLINE: msr psplim, r0 + ; MAINLINE: msr msp_ns, r0 + ; MAINLINE: msr psp_ns, r0 + ; MAINLINE: msr msplim_ns, r0 + ; MAINLINE: msr psplim_ns, r0 + ; MAINLINE: msr primask_ns, r0 + ; MAINLINE: msr basepri_ns, r0 + ; MAINLINE: msr faultmask_ns, r0 + ; MAINLINE: msr control_ns, r0 + ; MAINLINE: msr sp_ns, r0 + ; MAINLINE: msr basepri_max_ns, r0 + + call void @llvm.write_register.i32(metadata !0, i32 %x) + call void @llvm.write_register.i32(metadata !1, i32 %x) + call void @llvm.write_register.i32(metadata !2, i32 %x) + call void @llvm.write_register.i32(metadata !3, i32 %x) + call void @llvm.write_register.i32(metadata !4, i32 %x) + call void @llvm.write_register.i32(metadata !5, i32 %x) + call void @llvm.write_register.i32(metadata !6, i32 %x) + call void @llvm.write_register.i32(metadata !7, i32 %x) + call void @llvm.write_register.i32(metadata !8, i32 %x) + call void @llvm.write_register.i32(metadata !9, i32 %x) + call void @llvm.write_register.i32(metadata !10, i32 %x) + call void @llvm.write_register.i32(metadata !11, i32 %x) + call void @llvm.write_register.i32(metadata !12, i32 %x) + call void @llvm.write_register.i32(metadata !13, i32 %x) + call void @llvm.write_register.i32(metadata !14, i32 %x) + call void @llvm.write_register.i32(metadata !15, i32 %x) + call void @llvm.write_register.i32(metadata !16, i32 %x) + call void @llvm.write_register.i32(metadata !17, i32 %x) + call void @llvm.write_register.i32(metadata !18, i32 %x) + call void @llvm.write_register.i32(metadata !19, i32 %x) + call void @llvm.write_register.i32(metadata !20, i32 %x) + call void @llvm.write_register.i32(metadata !21, i32 %x) + call void @llvm.write_register.i32(metadata !22, i32 %x) + call void @llvm.write_register.i32(metadata !23, i32 %x) + call void @llvm.write_register.i32(metadata !24, i32 %x) + call void @llvm.write_register.i32(metadata !25, i32 %x) + call void @llvm.write_register.i32(metadata !26, i32 %x) + call void @llvm.write_register.i32(metadata !27, i32 %x) + call void @llvm.write_register.i32(metadata !28, i32 %x) + call void @llvm.write_register.i32(metadata !29, i32 %x) + call void @llvm.write_register.i32(metadata !30, i32 %x) + call void @llvm.write_register.i32(metadata !31, i32 %x) + call void @llvm.write_register.i32(metadata !32, i32 %x) + call void @llvm.write_register.i32(metadata !33, i32 %x) + call void @llvm.write_register.i32(metadata !34, i32 %x) + call void @llvm.write_register.i32(metadata !35, i32 %x) + call void @llvm.write_register.i32(metadata !36, i32 %x) + call void @llvm.write_register.i32(metadata !37, i32 %x) + ret void +} + +declare i32 @llvm.read_register.i32(metadata) nounwind +declare void @llvm.write_register.i32(metadata, i32) nounwind + +!0 = !{!"apsr"} +!1 = !{!"apsr_nzcvq"} +!2 = !{!"apsr_g"} +!3 = !{!"apsr_nzcvqg"} +!4 = !{!"iapsr"} +!5 = !{!"iapsr_nzcvq"} +!6 = !{!"iapsr_g"} +!7 = !{!"iapsr_nzcvqg"} +!8 = !{!"eapsr"} +!9 = !{!"eapsr_nzcvq"} +!10 = !{!"eapsr_g"} +!11 = !{!"eapsr_nzcvqg"} +!12 = !{!"xpsr"} +!13 = !{!"xpsr_nzcvq"} +!14 = !{!"xpsr_g"} +!15 = !{!"xpsr_nzcvqg"} +!16 = !{!"ipsr"} +!17 = !{!"epsr"} +!18 = !{!"iepsr"} +!19 = !{!"msp"} +!20 = !{!"psp"} +!21 = !{!"primask"} +!22 = !{!"basepri"} +!23 = !{!"basepri_max"} +!24 = !{!"faultmask"} +!25 = !{!"control"} +!26 = !{!"msplim"} +!27 = !{!"psplim"} +!28 = !{!"msp_ns"} +!29 = !{!"psp_ns"} +!30 = !{!"msplim_ns"} +!31 = !{!"psplim_ns"} +!32 = !{!"primask_ns"} +!33 = !{!"basepri_ns"} +!34 = !{!"faultmask_ns"} +!35 = !{!"control_ns"} +!36 = !{!"sp_ns"} +!37 = !{!"basepri_max_ns"} + diff --git a/test/CodeGen/ARM/ssat.ll b/test/CodeGen/ARM/ssat.ll new file mode 100644 index 000000000000..2b75bc410aa8 --- /dev/null +++ b/test/CodeGen/ARM/ssat.ll @@ -0,0 +1,215 @@ +; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s + +; Check for several conditions that should result in SSAT. +; For example, the base test is equivalent to +; x < -k ? -k : (x > k ? k : x) in C. All patterns that bound x +; to the interval [-k, k] where k is a power of 2 can be +; transformed into SSAT. At the end there are some tests +; checking that conditionals are not transformed if they don't +; match the right pattern. + +; +; Base tests with different bit widths +; + +; x < -k ? -k : (x > k ? k : x) +; 32-bit base test +define i32 @sat_base_32bit(i32 %x) #0 { +; CHECK-LABEL: sat_base_32bit: +; CHECK: ssat r0, #24, r0 +entry: + %cmpLow = icmp slt i32 %x, -8388608 + %cmpUp = icmp sgt i32 %x, 8388607 + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %x + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %saturateUp + ret i32 %saturateLow +} + +; x < -k ? -k : (x > k ? k : x) +; 16-bit base test +define i16 @sat_base_16bit(i16 %x) #0 { +; CHECK-LABEL: sat_base_16bit: +; CHECK: ssat r0, #12, r0 +entry: + %cmpLow = icmp slt i16 %x, -2048 + %cmpUp = icmp sgt i16 %x, 2047 + %saturateUp = select i1 %cmpUp, i16 2047, i16 %x + %saturateLow = select i1 %cmpLow, i16 -2048, i16 %saturateUp + ret i16 %saturateLow +} + +; x < -k ? -k : (x > k ? k : x) +; 8-bit base test +define i8 @sat_base_8bit(i8 %x) #0 { +; CHECK-LABEL: sat_base_8bit: +; CHECK: ssat r0, #6, r0 +entry: + %cmpLow = icmp slt i8 %x, -32 + %cmpUp = icmp sgt i8 %x, 31 + %saturateUp = select i1 %cmpUp, i8 31, i8 %x + %saturateLow = select i1 %cmpLow, i8 -32, i8 %saturateUp + ret i8 %saturateLow +} + +; +; Tests where the conditionals that check for upper and lower bounds, +; or the < and > operators, are arranged in different ways. Only some +; of the possible combinations that lead to SSAT are tested. +; + +; x < -k ? -k : (x < k ? x : k) +define i32 @sat_lower_upper_1(i32 %x) #0 { +; CHECK-LABEL: sat_lower_upper_1: +; CHECK: ssat r0, #24, r0 +entry: + %cmpLow = icmp slt i32 %x, -8388608 + %cmpUp = icmp slt i32 %x, 8388607 + %saturateUp = select i1 %cmpUp, i32 %x, i32 8388607 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %saturateUp + ret i32 %saturateLow +} + +; x > -k ? (x > k ? k : x) : -k +define i32 @sat_lower_upper_2(i32 %x) #0 { +; CHECK-LABEL: sat_lower_upper_2: +; CHECK: ssat r0, #24, r0 +entry: + %cmpLow = icmp sgt i32 %x, -8388608 + %cmpUp = icmp sgt i32 %x, 8388607 + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %x + %saturateLow = select i1 %cmpLow, i32 %saturateUp, i32 -8388608 + ret i32 %saturateLow +} + +; x < k ? (x < -k ? -k : x) : k +define i32 @sat_upper_lower_1(i32 %x) #0 { +; CHECK-LABEL: sat_upper_lower_1: +; CHECK: ssat r0, #24, r0 +entry: + %cmpUp = icmp slt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %x + %saturateUp = select i1 %cmpUp, i32 %saturateLow, i32 8388607 + ret i32 %saturateUp +} + +; x > k ? k : (x < -k ? -k : x) +define i32 @sat_upper_lower_2(i32 %x) #0 { +; CHECK-LABEL: sat_upper_lower_2: +; CHECK: ssat r0, #24, r0 +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; k < x ? k : (x > -k ? x : -k) +define i32 @sat_upper_lower_3(i32 %x) #0 { +; CHECK-LABEL: sat_upper_lower_3: +; CHECK: ssat r0, #24, r0 +entry: + %cmpUp = icmp slt i32 8388607, %x + %cmpLow = icmp sgt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 %x, i32 -8388608 + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; +; Miscellanea +; + +; Check that >= and <= work the same as > and < +; k <= x ? k : (x >= -k ? x : -k) +define i32 @sat_le_ge(i32 %x) #0 { +; CHECK-LABEL: sat_le_ge: +; CHECK: ssat r0, #24, r0 +entry: + %cmpUp = icmp sle i32 8388607, %x + %cmpLow = icmp sge i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 %x, i32 -8388608 + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; +; The following tests check for patterns that should not transform +; into SSAT but are similar enough that could confuse the selector. +; + +; x > k ? k : (x > -k ? -k : x) +; First condition upper-saturates, second doesn't lower-saturate. +define i32 @no_sat_missing_lower(i32 %x) #0 { +; CHECK-LABEL: no_sat_missing_lower +; CHECK-NOT: ssat +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp sgt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; x < k ? k : (x < -k ? -k : x) +; Second condition lower-saturates, first doesn't upper-saturate. +define i32 @no_sat_missing_upper(i32 %x) #0 { +; CHECK-LABEL: no_sat_missing_upper: +; CHECK-NOT: ssat +entry: + %cmpUp = icmp slt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; Lower constant is different in the select and in the compare +define i32 @no_sat_incorrect_constant(i32 %x) #0 { +; CHECK-LABEL: no_sat_incorrect_constant: +; CHECK-NOT: ssat +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388607, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; The interval is not [k, ~k] +define i32 @no_sat_incorrect_interval(i32 %x) #0 { +; CHECK-LABEL: no_sat_incorrect_interval: +; CHECK-NOT: ssat +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -19088744 + %saturateLow = select i1 %cmpLow, i32 -19088744, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; The returned value (y) is not the same as the tested value (x). +define i32 @no_sat_incorrect_return(i32 %x, i32 %y) #0 { +; CHECK-LABEL: no_sat_incorrect_return: +; CHECK-NOT: ssat +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp slt i32 %x, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %y + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} + +; One of the values in a compare (y) is not the same as the rest +; of the compare and select values (x). +define i32 @no_sat_incorrect_compare(i32 %x, i32 %y) #0 { +; CHECK-LABEL: no_sat_incorrect_compare: +; CHECK-NOT: ssat +entry: + %cmpUp = icmp sgt i32 %x, 8388607 + %cmpLow = icmp slt i32 %y, -8388608 + %saturateLow = select i1 %cmpLow, i32 -8388608, i32 %x + %saturateUp = select i1 %cmpUp, i32 8388607, i32 %saturateLow + ret i32 %saturateUp +} diff --git a/test/CodeGen/ARM/static-addr-hoisting.ll b/test/CodeGen/ARM/static-addr-hoisting.ll new file mode 100644 index 000000000000..3d47e02f965e --- /dev/null +++ b/test/CodeGen/ARM/static-addr-hoisting.ll @@ -0,0 +1,22 @@ +; RUN: llc -mtriple=thumbv7-apple-ios %s -o - | FileCheck %s + +define void @multiple_store() { +; CHECK-LABEL: multiple_store: +; CHECK: movw r[[BASE1:[0-9]+]], #16960 +; CHECK: movs [[VAL:r[0-9]+]], #42 +; CHECK: movt r[[BASE1]], #15 + +; CHECK: str [[VAL]], [r[[BASE1]]] +; CHECK: str [[VAL]], [r[[BASE1]], #24] +; CHECK: str.w [[VAL]], [r[[BASE1]], #42] + +; CHECK: movw r[[BASE2:[0-9]+]], #20394 +; CHECK: movt r[[BASE2]], #18 + +; CHECK: str [[VAL]], [r[[BASE2]]] + store i32 42, i32* inttoptr(i32 1000000 to i32*) + store i32 42, i32* inttoptr(i32 1000024 to i32*) + store i32 42, i32* inttoptr(i32 1000042 to i32*) + store i32 42, i32* inttoptr(i32 1200042 to i32*) + ret void +} diff --git a/test/CodeGen/ARM/stc2.ll b/test/CodeGen/ARM/stc2.ll new file mode 100644 index 000000000000..1127796387bb --- /dev/null +++ b/test/CodeGen/ARM/stc2.ll @@ -0,0 +1,11 @@ +; RUN: not llc < %s -mtriple=armv8-eabi 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=thumbv8-eabi 2>&1 | FileCheck %s + +; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.arm.stc2 +define void @stc2(i8* %i) nounwind { +entry: + call void @llvm.arm.stc2(i32 1, i32 2, i8* %i) nounwind + ret void +} + +declare void @llvm.arm.stc2(i32, i32, i8*) nounwind diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index d7b9b477ec1e..6c8f6fa0b39c 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s ; RUN: llc < %s -mtriple=armv7-unknown-nacl-gnueabi | FileCheck %s -check-prefix=NACL ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi | FileCheck %s -check-prefix=NOMOVT @@ -15,10 +15,6 @@ entry: ; CHECK: ldr ; CHECK: str ; CHECK-NOT:bne -; THUMB-LABEL: f: -; THUMB: ldr -; THUMB: str -; THUMB-NOT:bne %st = alloca %struct.SmallStruct, align 4 %call = call i32 @e1(%struct.SmallStruct* byval %st) ret i32 0 @@ -32,11 +28,6 @@ entry: ; CHECK: sub ; CHECK: str ; CHECK: bne -; THUMB-LABEL: g: -; THUMB: ldr -; THUMB: sub -; THUMB: str -; THUMB: bne ; NACL-LABEL: g: ; Ensure that use movw instead of constpool for the loop trip count. But don't ; match the __stack_chk_guard movw @@ -58,11 +49,6 @@ entry: ; CHECK: sub ; CHECK: vst1 ; CHECK: bne -; THUMB-LABEL: h: -; THUMB: vld1 -; THUMB: sub -; THUMB: vst1 -; THUMB: bne ; NACL: movw r{{[1-9]}}, # ; NACL: vld1 ; NACL: sub @@ -83,8 +69,6 @@ declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize { ; CHECK-LABEL: f3 ; CHECK: bl _consumestruct -; THUMB-LABEL: f3 -; THUMB: blx _consumestruct entry: %0 = bitcast %struct.SmallStruct* %s to i8* tail call void @consumestruct(i8* %0, i32 80) optsize @@ -94,8 +78,6 @@ entry: define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize { ; CHECK-LABEL: f4 ; CHECK: bl _consumestruct -; THUMB-LABEL: f4 -; THUMB: blx _consumestruct entry: %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* @@ -106,9 +88,7 @@ entry: ; We can do tail call here since s is in the incoming argument area. define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { ; CHECK-LABEL: f5 -; CHECK: b _consumestruct -; THUMB-LABEL: f5 -; THUMB: b.w _consumestruct +; CHECK: b{{(\.w)?}} _consumestruct entry: %0 = bitcast %struct.SmallStruct* %s to i8* tail call void @consumestruct(i8* %0, i32 80) optsize @@ -117,9 +97,7 @@ entry: define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { ; CHECK-LABEL: f6 -; CHECK: b _consumestruct -; THUMB-LABEL: f6 -; THUMB: b.w _consumestruct +; CHECK: b{{(\.w)?}} _consumestruct entry: %addr = getelementptr inbounds %struct.SmallStruct, %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* @@ -137,9 +115,6 @@ define void @test_I_16() { ; CHECK-LABEL: test_I_16 ; CHECK: ldrb ; CHECK: strb -; THUMB-LABEL: test_I_16 -; THUMB: ldrb -; THUMB: strb entry: call void @use_I(%struct.I.8* byval align 16 undef) ret void diff --git a/test/CodeGen/ARM/swift-ios.ll b/test/CodeGen/ARM/swift-ios.ll new file mode 100644 index 000000000000..a5d09524e11d --- /dev/null +++ b/test/CodeGen/ARM/swift-ios.ll @@ -0,0 +1,68 @@ +; RUN: llc -mtriple=armv7-apple-ios < %s | FileCheck %s + +define swiftcc float @t1(float %a, float %b) { +entry: +; CHECK: t1 +; CHECK-NOT: vmov +; CHECK: vadd.f32 + %add = fadd float %a, %b + ret float %add +} + +define swiftcc double @t2(double %a, double %b) { +entry: +; CHECK: t2 +; CHECK-NOT: vmov +; CHECK: vadd.f64 + %add = fadd double %a, %b + ret double %add +} + +define swiftcc double @t9(double %d0, double %d1, double %d2, double %d3, + double %d4, double %d5, double %d6, double %d7, float %a, float %b) { +entry: +; CHECK-LABEL: t9: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd float %a, %b + %conv = fpext float %add to double + ret double %conv +} + +define swiftcc double @t10(double %d0, double %d1, double %d2, double %d3, + double %d4, double %d5, double %a, float %b, double %c) { +entry: +; CHECK-LABEL: t10: +; CHECK-NOT: vmov +; CHECK: vldr + %add = fadd double %a, %c + ret double %add +} + +define swiftcc float @t11(double %d0, double %d1, double %d2, double %d3, + double %d4, double %d5, double %d6, float %a, double %b, float %c) { +entry: +; CHECK-LABEL: t11: +; CHECK: vldr + %add = fadd float %a, %c + ret float %add +} + +define swiftcc double @t12(double %a, double %b) { +entry: +; CHECK-LABEL: t12: +; CHECK: vstr + %add = fadd double %a, %b + %sub = fsub double %a, %b + %call = tail call swiftcc double @x(double 0.000000e+00, double 0.000000e+00, + double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, + double 0.000000e+00, double %add, float 0.000000e+00, + double %sub) + ret double %call +} + +declare swiftcc double @x(double, double, double, double, double, double, + double, float, double) + +attributes #0 = { readnone } +attributes #1 = { readonly } diff --git a/test/CodeGen/ARM/swift-return.ll b/test/CodeGen/ARM/swift-return.ll new file mode 100644 index 000000000000..4a5ef5e382ca --- /dev/null +++ b/test/CodeGen/ARM/swift-return.ll @@ -0,0 +1,133 @@ +; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s + +; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=armv7-apple-ios -verify-machineinstrs < %s -O0 | FileCheck --check-prefix=CHECK-O0 %s + +; Test how llvm handles return type of {i16, i8}. The return value will be +; passed in %r0 and %r1. +; CHECK-LABEL: test: +; CHECK: bl {{.*}}gen +; CHECK: sxth {{.*}}, r0 +; CHECK: sxtab r0, {{.*}}, r1 +; CHECK-O0-LABEL: test: +; CHECK-O0: bl {{.*}}gen +; CHECK-O0: sxth r0, r0 +; CHECK-O0: sxtb r1, r1 +; CHECK-O0: add r0, r0, r1 +define i16 @test(i32 %key) { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i16, i8 } @gen(i32 %0) + %v3 = extractvalue { i16, i8 } %call, 0 + %v1 = sext i16 %v3 to i32 + %v5 = extractvalue { i16, i8 } %call, 1 + %v2 = sext i8 %v5 to i32 + %add = add nsw i32 %v1, %v2 + %conv = trunc i32 %add to i16 + ret i16 %conv +} + +declare swiftcc { i16, i8 } @gen(i32) + +; We can't pass every return value in register, instead, pass everything in +; memroy. +; The caller provides space for the return value and passes the address in %r0. +; The first input argument will be in %r1. +; CHECK-LABEL: test2: +; CHECK: mov r1, r0 +; CHECK: mov r0, sp +; CHECK: bl {{.*}}gen2 +; CHECK-DAG: add +; CHECK-DAG: ldr {{.*}}, [sp, #16] +; CHECK-DAG: add +; CHECK-DAG: add +; CHECK-DAG: add +; CHECK-O0-LABEL: test2: +; CHECK-O0: str r0 +; CHECK-O0: mov r0, sp +; CHECK-O0: bl {{.*}}gen2 +; CHECK-O0-DAG: ldr {{.*}}, [sp] +; CHECK-O0-DAG: ldr {{.*}}, [sp, #4] +; CHECK-O0-DAG: ldr {{.*}}, [sp, #8] +; CHECK-O0-DAG: ldr {{.*}}, [sp, #12] +; CHECK-O0-DAG: ldr {{.*}}, [sp, #16] +; CHECK-O0-DAG: add +; CHECK-O0-DAG: add +; CHECK-O0-DAG: add +; CHECK-O0-DAG: add +define i32 @test2(i32 %key) #0 { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %0) + + %v3 = extractvalue { i32, i32, i32, i32, i32 } %call, 0 + %v5 = extractvalue { i32, i32, i32, i32, i32 } %call, 1 + %v6 = extractvalue { i32, i32, i32, i32, i32 } %call, 2 + %v7 = extractvalue { i32, i32, i32, i32, i32 } %call, 3 + %v8 = extractvalue { i32, i32, i32, i32, i32 } %call, 4 + + %add = add nsw i32 %v3, %v5 + %add1 = add nsw i32 %add, %v6 + %add2 = add nsw i32 %add1, %v7 + %add3 = add nsw i32 %add2, %v8 + ret i32 %add3 +} + +; The address of the return value is passed in %r0. +; CHECK-LABEL: gen2: +; CHECK-DAG: str r1, [r0] +; CHECK-DAG: str r1, [r0, #4] +; CHECK-DAG: str r1, [r0, #8] +; CHECK-DAG: str r1, [r0, #12] +; CHECK-DAG: str r1, [r0, #16] +; CHECK-O0-LABEL: gen2: +; CHECK-O0-DAG: str r1, [r0] +; CHECK-O0-DAG: str r1, [r0, #4] +; CHECK-O0-DAG: str r1, [r0, #8] +; CHECK-O0-DAG: str r1, [r0, #12] +; CHECK-O0-DAG: str r1, [r0, #16] +define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) { + %Y = insertvalue { i32, i32, i32, i32, i32 } undef, i32 %key, 0 + %Z = insertvalue { i32, i32, i32, i32, i32 } %Y, i32 %key, 1 + %Z2 = insertvalue { i32, i32, i32, i32, i32 } %Z, i32 %key, 2 + %Z3 = insertvalue { i32, i32, i32, i32, i32 } %Z2, i32 %key, 3 + %Z4 = insertvalue { i32, i32, i32, i32, i32 } %Z3, i32 %key, 4 + ret { i32, i32, i32, i32, i32 } %Z4 +} + +; The return value {i32, i32, i32, i32} will be returned via registers %r0, %r1, +; %r2, %r3. +; CHECK-LABEL: test3: +; CHECK: bl {{.*}}gen3 +; CHECK: add r0, r0, r1 +; CHECK: add r0, r0, r2 +; CHECK: add r0, r0, r3 +; CHECK-O0-LABEL: test3: +; CHECK-O0: bl {{.*}}gen3 +; CHECK-O0: add r0, r0, r1 +; CHECK-O0: add r0, r0, r2 +; CHECK-O0: add r0, r0, r3 +define i32 @test3(i32 %key) #0 { +entry: + %key.addr = alloca i32, align 4 + store i32 %key, i32* %key.addr, align 4 + %0 = load i32, i32* %key.addr, align 4 + %call = call swiftcc { i32, i32, i32, i32 } @gen3(i32 %0) + + %v3 = extractvalue { i32, i32, i32, i32 } %call, 0 + %v5 = extractvalue { i32, i32, i32, i32 } %call, 1 + %v6 = extractvalue { i32, i32, i32, i32 } %call, 2 + %v7 = extractvalue { i32, i32, i32, i32 } %call, 3 + + %add = add nsw i32 %v3, %v5 + %add1 = add nsw i32 %add, %v6 + %add2 = add nsw i32 %add1, %v7 + ret i32 %add2 +} + +declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key) diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll index 9e507279fa09..a53b2413bde1 100644 --- a/test/CodeGen/ARM/swift-vldm.ll +++ b/test/CodeGen/ARM/swift-vldm.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s +; RUN: llc < %s -arm-assume-misaligned-load-store -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s ; Check that we avoid producing vldm instructions using d registers that ; begin in the most-significant half of a q register. These require more diff --git a/test/CodeGen/ARM/swifterror.ll b/test/CodeGen/ARM/swifterror.ll new file mode 100644 index 000000000000..17bd7059f6d4 --- /dev/null +++ b/test/CodeGen/ARM/swifterror.ll @@ -0,0 +1,381 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-APPLE %s +; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=armv7-apple-ios | FileCheck --check-prefix=CHECK-O0 %s + +declare i8* @malloc(i64) +declare void @free(i8*) +%swift_error = type { i64, i8 } +%struct.S = type { i32, i32, i32, i32, i32, i32 } + +; This tests the basic usage of a swifterror parameter. "foo" is the function +; that takes a swifterror parameter and "caller" is the caller of "foo". +define float @foo(%swift_error** swifterror %error_ptr_ref) { +; CHECK-APPLE-LABEL: foo: +; CHECK-APPLE: mov r0, #16 +; CHECK-APPLE: malloc +; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], #1 +; CHECK-APPLE-DAG: mov r6, r{{.*}} +; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8] + +; CHECK-O0-LABEL: foo: +; CHECK-O0: mov r{{.*}}, #16 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID2:r[0-9]+]], r0 +; CHECK-O0: mov [[ID:r[0-9]+]], #1 +; CHECK-O0: strb [[ID]], [r0, #8] +; CHECK-O0: mov r6, [[ID2]] +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 +} + +; "caller" calls "foo" that takes a swifterror parameter. +define float @caller(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller: +; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], r0 +; CHECK-APPLE-DAG: mov r6, #0 +; CHECK-APPLE: bl {{.*}}foo +; CHECK-APPLE: cmp r6, #0 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8] +; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov r0, r6 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller: +; spill r0 +; CHECK-O0-DAG: str r0, +; CHECK-O0-DAG: mov r6, #0 +; CHECK-O0: bl {{.*}}foo +; CHECK-O0: mov r{{.*}}, r6 +; CHECK-O0: bne +; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8] +; reload r0 +; CHECK-O0: ldr [[ID:r[0-9]+]], +; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-O0: mov r0, +; CHECK-O0: free +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "caller2" is the caller of "foo", it calls "foo" inside a loop. +define float @caller2(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller2: +; CHECK-APPLE-DAG: mov [[ID:r[0-9]+]], r0 +; CHECK-APPLE-DAG: mov r6, #0 +; CHECK-APPLE: bl {{.*}}foo +; CHECK-APPLE: cmp r6, #0 +; CHECK-APPLE: bne +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrb [[CODE:r[0-9]+]], [r6, #8] +; CHECK-APPLE: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov r0, r6 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller2: +; spill r0 +; CHECK-O0-DAG: str r0, +; CHECK-O0-DAG: mov r6, #0 +; CHECK-O0: bl {{.*}}foo +; CHECK-O0: mov r{{.*}}, r6 +; CHECK-O0: bne +; CHECK-O0: ble +; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8] +; reload r0 +; CHECK-O0: ldr [[ID:r[0-9]+]], +; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-O0: mov r0, +; CHECK-O0: free +entry: + %error_ptr_ref = alloca swifterror %swift_error* + br label %bb_loop +bb_loop: + store %swift_error* null, %swift_error** %error_ptr_ref + %call = call float @foo(%swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %cmp = fcmp ogt float %call, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "foo_if" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition. +define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) { +; CHECK-APPLE-LABEL: foo_if: +; CHECK-APPLE: cmp r0, #0 +; CHECK-APPLE: eq +; CHECK-APPLE: mov r0, #16 +; CHECK-APPLE: malloc +; CHECK-APPLE: mov [[ID:r[0-9]+]], #1 +; CHECK-APPLE-DAG: mov r6, r{{.*}} +; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8] + +; CHECK-O0-LABEL: foo_if: +; CHECK-O0: cmp r0, #0 +; spill to stack +; CHECK-O0: str r6 +; CHECK-O0: beq +; CHECK-O0: mov r0, #16 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID:r[0-9]+]], r0 +; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1 +; CHECK-O0: strb [[ID2]], [r0, #8] +; CHECK-O0: mov r6, [[ID]] +; reload from stack +; CHECK-O0: ldr r6 +entry: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %normal + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + ret float 1.0 + +normal: + ret float 0.0 +} + +; "foo_loop" is a function that takes a swifterror parameter, it sets swifterror +; under a certain condition inside a loop. +define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float %cc2) { +; CHECK-APPLE-LABEL: foo_loop: +; CHECK-APPLE: mov [[CODE:r[0-9]+]], r0 +; swifterror is kept in a register +; CHECK-APPLE: mov [[ID:r[0-9]+]], r6 +; CHECK-APPLE: cmp [[CODE]], #0 +; CHECK-APPLE: beq +; CHECK-APPLE: mov r0, #16 +; CHECK-APPLE: malloc +; CHECK-APPLE: strb r{{.*}}, [{{.*}}[[ID]], #8] +; CHECK-APPLE: ble +; CHECK-APPLE: mov r6, [[ID]] + +; CHECK-O0-LABEL: foo_loop: +; CHECK-O0: mov r{{.*}}, r6 +; CHECK-O0: cmp r{{.*}}, #0 +; CHECK-O0: beq +; CHECK-O0-DAG: movw r{{.*}}, #1 +; CHECK-O0-DAG: mov r{{.*}}, #16 +; CHECK-O0: malloc +; CHECK-O0-DAG: mov [[ID:r[0-9]+]], r0 +; CHECK-O0-DAG: ldr [[ID2:r[0-9]+]], [sp{{.*}}] +; CHECK-O0: strb [[ID2]], [{{.*}}[[ID]], #8] +; spill r0 +; CHECK-O0: str r0, [sp{{.*}}] +; CHECK-O0: vcmpe +; CHECK-O0: ble +; reload from stack +; CHECK-O0: ldr r6 +entry: + br label %bb_loop + +bb_loop: + %cond = icmp ne i32 %cc, 0 + br i1 %cond, label %gen_error, label %bb_cont + +gen_error: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + br label %bb_cont + +bb_cont: + %cmp = fcmp ogt float %cc2, 1.000000e+00 + br i1 %cmp, label %bb_end, label %bb_loop +bb_end: + ret float 0.0 +} + +; "foo_sret" is a function that takes a swifterror parameter, it also has a sret +; parameter. +define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swifterror %error_ptr_ref) { +; CHECK-APPLE-LABEL: foo_sret: +; CHECK-APPLE: mov [[SRET:r[0-9]+]], r0 +; CHECK-APPLE: mov r0, #16 +; CHECK-APPLE: malloc +; CHECK-APPLE: mov [[REG:r[0-9]+]], #1 +; CHECK-APPLE-DAG: mov r6, r0 +; CHECK-APPLE-DAG: strb [[REG]], [r0, #8] +; CHECK-APPLE-DAG: str r{{.*}}, [{{.*}}[[SRET]], #4] + +; CHECK-O0-LABEL: foo_sret: +; CHECK-O0: mov r{{.*}}, #16 +; spill to stack: sret and val1 +; CHECK-O0-DAG: str r0 +; CHECK-O0-DAG: str r1 +; CHECK-O0: malloc +; CHECK-O0: mov [[ID:r[0-9]+]], #1 +; CHECK-O0: strb [[ID]], [r0, #8] +; reload from stack: sret and val1 +; CHECK-O0: ldr +; CHECK-O0: ldr +; CHECK-O0: str r{{.*}}, [{{.*}}, #4] +; CHECK-O0: mov r6 +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + %v2 = getelementptr inbounds %struct.S, %struct.S* %agg.result, i32 0, i32 1 + store i32 %val1, i32* %v2 + ret void +} + +; "caller3" calls "foo_sret" that takes a swifterror parameter. +define float @caller3(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller3: +; CHECK-APPLE: mov [[ID:r[0-9]+]], r0 +; CHECK-APPLE: mov r6, #0 +; CHECK-APPLE: bl {{.*}}foo_sret +; CHECK-APPLE: cmp r6, #0 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8] +; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov r0, r6 +; CHECK_APPLE: bl {{.*}}free + +; CHECK-O0-LABEL: caller3: +; CHECK-O0-DAG: mov r6, #0 +; CHECK-O0-DAG: mov r0 +; CHECK-O0-DAG: mov r1 +; CHECK-O0: bl {{.*}}foo_sret +; CHECK-O0: mov [[ID2:r[0-9]+]], r6 +; CHECK-O0: cmp [[ID2]] +; CHECK-O0: bne +; Access part of the error object and save it to error_ref +; CHECK-O0: ldrb [[CODE:r[0-9]+]] +; CHECK-O0: ldr [[ID:r[0-9]+]] +; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]] +; CHECK-O0: mov r0, +; CHECK_O0: bl {{.*}}free +entry: + %s = alloca %struct.S, align 8 + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + call void @foo_sret(%struct.S* sret %s, i32 1, %swift_error** swifterror %error_ptr_ref) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} + +; "foo_vararg" is a function that takes a swifterror parameter, it also has +; variable number of arguments. +declare void @llvm.va_start(i8*) nounwind +define float @foo_vararg(%swift_error** swifterror %error_ptr_ref, ...) { +; CHECK-APPLE-LABEL: foo_vararg: +; CHECK-APPLE: mov r0, #16 +; CHECK-APPLE: malloc +; CHECK-APPLE: mov [[REG:r[0-9]+]], r0 +; CHECK-APPLE: mov [[ID:r[0-9]+]], #1 +; CHECK-APPLE-DAG: strb [[ID]], [{{.*}}[[REG]], #8] +; CHECK-APPLE-DAG: mov r6, [[REG]] + +entry: + %call = call i8* @malloc(i64 16) + %call.0 = bitcast i8* %call to %swift_error* + store %swift_error* %call.0, %swift_error** %error_ptr_ref + %tmp = getelementptr inbounds i8, i8* %call, i64 8 + store i8 1, i8* %tmp + + %args = alloca i8*, align 8 + %a10 = alloca i32, align 4 + %a11 = alloca i32, align 4 + %a12 = alloca i32, align 4 + %v10 = bitcast i8** %args to i8* + call void @llvm.va_start(i8* %v10) + %v11 = va_arg i8** %args, i32 + store i32 %v11, i32* %a10, align 4 + %v12 = va_arg i8** %args, i32 + store i32 %v12, i32* %a11, align 4 + %v13 = va_arg i8** %args, i32 + store i32 %v13, i32* %a12, align 4 + + ret float 1.0 +} + +; "caller4" calls "foo_vararg" that takes a swifterror parameter. +define float @caller4(i8* %error_ref) { +; CHECK-APPLE-LABEL: caller4: +; CHECK-APPLE: mov [[ID:r[0-9]+]], r0 +; CHECK-APPLE: mov r6, #0 +; CHECK-APPLE: bl {{.*}}foo_vararg +; CHECK-APPLE: cmp r6, #0 +; Access part of the error object and save it to error_ref +; CHECK-APPLE: ldrbeq [[CODE:r[0-9]+]], [r6, #8] +; CHECK-APPLE: strbeq [[CODE]], [{{.*}}[[ID]]] +; CHECK-APPLE: mov r0, r6 +; CHECK_APPLE: bl {{.*}}free +entry: + %error_ptr_ref = alloca swifterror %swift_error* + store %swift_error* null, %swift_error** %error_ptr_ref + + %a10 = alloca i32, align 4 + %a11 = alloca i32, align 4 + %a12 = alloca i32, align 4 + store i32 10, i32* %a10, align 4 + store i32 11, i32* %a11, align 4 + store i32 12, i32* %a12, align 4 + %v10 = load i32, i32* %a10, align 4 + %v11 = load i32, i32* %a11, align 4 + %v12 = load i32, i32* %a12, align 4 + + %call = call float (%swift_error**, ...) @foo_vararg(%swift_error** swifterror %error_ptr_ref, i32 %v10, i32 %v11, i32 %v12) + %error_from_foo = load %swift_error*, %swift_error** %error_ptr_ref + %had_error_from_foo = icmp ne %swift_error* %error_from_foo, null + %tmp = bitcast %swift_error* %error_from_foo to i8* + br i1 %had_error_from_foo, label %handler, label %cont + +cont: + %v1 = getelementptr inbounds %swift_error, %swift_error* %error_from_foo, i64 0, i32 1 + %t = load i8, i8* %v1 + store i8 %t, i8* %error_ref + br label %handler +handler: + call void @free(i8* %tmp) + ret float 1.0 +} diff --git a/test/CodeGen/ARM/swiftself.ll b/test/CodeGen/ARM/swiftself.ll new file mode 100644 index 000000000000..6826b123472f --- /dev/null +++ b/test/CodeGen/ARM/swiftself.ll @@ -0,0 +1,65 @@ +; RUN: llc -verify-machineinstrs -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT --check-prefix=TAILCALL %s +; RUN: llc -O0 -verify-machineinstrs -mtriple=armv7k-apple-ios8.0 -mcpu=cortex-a7 -o - %s | FileCheck %s + +; RUN: llc -verify-machineinstrs -mtriple=armv7-apple-ios -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT %s +; RUN: llc -O0 -verify-machineinstrs -mtriple=armv7-apple-ios -o - %s | FileCheck %s + +; Parameter with swiftself should be allocated to r10. +; CHECK-LABEL: swiftself_param: +; CHECK: mov r0, r10 +define i8 *@swiftself_param(i8* swiftself %addr0) { + ret i8 *%addr0 +} + +; Check that r10 is used to pass a swiftself argument. +; CHECK-LABEL: call_swiftself: +; CHECK: mov r10, r0 +; CHECK: bl {{_?}}swiftself_param +define i8 *@call_swiftself(i8* %arg) { + %res = call i8 *@swiftself_param(i8* swiftself %arg) + ret i8 *%res +} + +; r10 should be saved by the callee even if used for swiftself +; CHECK-LABEL: swiftself_clobber: +; CHECK: push {r10} +; ... +; CHECK: pop {r10} +define i8 *@swiftself_clobber(i8* swiftself %addr0) { + call void asm sideeffect "", "~{r10}"() + ret i8 *%addr0 +} + +; Demonstrate that we do not need any movs when calling multiple functions +; with swiftself argument. +; CHECK-LABEL: swiftself_passthrough: +; OPT-NOT: mov{{.*}}r10 +; OPT: bl {{_?}}swiftself_param +; OPT-NOT: mov{{.*}}r10 +; OPT-NEXT: bl {{_?}}swiftself_param +define void @swiftself_passthrough(i8* swiftself %addr0) { + call i8 *@swiftself_param(i8* swiftself %addr0) + call i8 *@swiftself_param(i8* swiftself %addr0) + ret void +} + +; We can use a tail call if the callee swiftself is the same as the caller one. +; CHECK-LABEL: swiftself_tail: +; TAILCALL: b {{_?}}swiftself_param +; TAILCALL-NOT: pop +define i8* @swiftself_tail(i8* swiftself %addr0) { + call void asm sideeffect "", "~{r10}"() + %res = tail call i8* @swiftself_param(i8* swiftself %addr0) + ret i8* %res +} + +; We can not use a tail call if the callee swiftself is not the same as the +; caller one. +; CHECK-LABEL: swiftself_notail: +; CHECK: mov r10, r0 +; CHECK: bl {{_?}}swiftself_param +; CHECK: pop +define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind { + %res = tail call i8* @swiftself_param(i8* swiftself %addr1) + ret i8* %res +} diff --git a/test/CodeGen/ARM/t2-shrink-ldrpost.ll b/test/CodeGen/ARM/t2-shrink-ldrpost.ll new file mode 100644 index 000000000000..e26f3848ddcd --- /dev/null +++ b/test/CodeGen/ARM/t2-shrink-ldrpost.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" +target triple = "thumbv7m--linux-gnu" + +; CHECK-LABEL: f: +; CHECK: ldm r{{[0-9]}}!, {r[[x:[0-9]]]} +; CHECK: add.w r[[x]], r[[x]], #3 +; CHECK: stm r{{[0-9]}}!, {r[[x]]} +define void @f(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize minsize { + %1 = icmp sgt i32 %n, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %.lr.ph, %0 + %i.04 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ] + %.03 = phi i32* [ %2, %.lr.ph ], [ %b, %0 ] + %.012 = phi i32* [ %5, %.lr.ph ], [ %a, %0 ] + %2 = getelementptr inbounds i32, i32* %.03, i32 1 + %3 = load i32, i32* %.03, align 4 + %4 = add nsw i32 %3, 3 + %5 = getelementptr inbounds i32, i32* %.012, i32 1 + store i32 %4, i32* %.012, align 4 + %6 = add nsw i32 %i.04, 1 + %exitcond = icmp eq i32 %6, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + ret void +} + +; CHECK-LABEL: f_nominsize: +; CHECK-NOT: ldm +define void @f_nominsize(i32 %n, i32* nocapture %a, i32* nocapture readonly %b) optsize { + %1 = icmp sgt i32 %n, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %.lr.ph, %0 + %i.04 = phi i32 [ %6, %.lr.ph ], [ 0, %0 ] + %.03 = phi i32* [ %2, %.lr.ph ], [ %b, %0 ] + %.012 = phi i32* [ %5, %.lr.ph ], [ %a, %0 ] + %2 = getelementptr inbounds i32, i32* %.03, i32 1 + %3 = load i32, i32* %.03, align 4 + %4 = add nsw i32 %3, 3 + %5 = getelementptr inbounds i32, i32* %.012, i32 1 + store i32 %4, i32* %.012, align 4 + %6 = add nsw i32 %i.04, 1 + %exitcond = icmp eq i32 %6, %n + br i1 %exitcond, label %._crit_edge, label %.lr.ph + +._crit_edge: ; preds = %.lr.ph, %0 + ret void +} diff --git a/test/CodeGen/ARM/tail-call-builtin.ll b/test/CodeGen/ARM/tail-call-builtin.ll new file mode 100644 index 000000000000..c829cc52462e --- /dev/null +++ b/test/CodeGen/ARM/tail-call-builtin.ll @@ -0,0 +1,37 @@ +; RUN: llc -mtriple=thumbv7-linux-gnueabihf %s -o - | FileCheck %s + +define i64 @test_mismatched_call(double %in) { +; CHECK-LABEL: test_mismatched_call: +; CHECK: bl floor +; CHECK: vmov r0, r1, d0 + + %val = tail call double @floor(double %in) + %res = bitcast double %val to i64 + ret i64 %res +} + +define double @test_matched_call(double %in) { +; CHECK-LABEL: test_matched_call: +; CHECK: b floor + + %val = tail call double @floor(double %in) + ret double %val +} + +define void @test_irrelevant_call(double %in) { +; CHECK-LABEL: test_irrelevant_call: +; CHECK-NOT: bl floor + + %val = tail call double @floor(double %in) + ret void +} + +define arm_aapcscc double @test_callingconv(double %in) { +; CHECK: test_callingconv: +; CHECK: bl floor + + %val = tail call double @floor(double %in) + ret double %val +} + +declare double @floor(double) nounwind readonly diff --git a/test/CodeGen/ARM/tail-call-weak.ll b/test/CodeGen/ARM/tail-call-weak.ll index 466c33d38786..e0117dffecbf 100644 --- a/test/CodeGen/ARM/tail-call-weak.ll +++ b/test/CodeGen/ARM/tail-call-weak.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple thumbv7-windows-coff -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-COFF -; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-ELF -; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-MACHO +; RUN: llc -mtriple thumbv7-elf -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER +; RUN: llc -mtriple thumbv7-macho -filetype asm -o - %s | FileCheck %s -check-prefix CHECK-OTHER declare i8* @f() declare extern_weak i8* @g(i8*) @@ -14,6 +14,5 @@ define void @test() { } ; CHECK-COFF: b g -; CHECK-ELF: bl g -; CHECK-MACHO: blx _g +; CHECK-OTHER: bl {{_?}}g diff --git a/test/CodeGen/ARM/this-return.ll b/test/CodeGen/ARM/this-return.ll index 802f880c1380..931210c2a8ed 100644 --- a/test/CodeGen/ARM/this-return.ll +++ b/test/CodeGen/ARM/this-return.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s -check-prefix=CHECKELF -; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 | FileCheck %s -check-prefix=CHECKT2D +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -arm-this-return-forwarding | FileCheck %s -check-prefix=CHECKELF +; RUN: llc < %s -mtriple=thumbv7-apple-ios5.0 -arm-this-return-forwarding | FileCheck %s -check-prefix=CHECKT2D %struct.A = type { i8 } %struct.B = type { i32 } @@ -24,7 +24,7 @@ entry: ; CHECKELF: b B_ctor_base ; CHECKT2D-LABEL: C_ctor_base: ; CHECKT2D-NOT: mov {{r[0-9]+}}, r0 -; CHECKT2D: blx _A_ctor_base +; CHECKT2D: bl _A_ctor_base ; CHECKT2D-NOT: mov r0, {{r[0-9]+}} ; CHECKT2D: b.w _B_ctor_base %0 = bitcast %struct.C* %this to %struct.A* @@ -43,7 +43,7 @@ entry: ; CHECKELF-NOT: b B_ctor_base_nothisret ; CHECKT2D-LABEL: C_ctor_base_nothisret: ; CHECKT2D: mov [[SAVETHIS:r[0-9]+]], r0 -; CHECKT2D: blx _A_ctor_base_nothisret +; CHECKT2D: bl _A_ctor_base_nothisret ; CHECKT2D: mov r0, [[SAVETHIS]] ; CHECKT2D-NOT: b.w _B_ctor_base_nothisret %0 = bitcast %struct.C* %this to %struct.A* @@ -82,7 +82,7 @@ entry: ; CHECKELF: b B_ctor_complete ; CHECKT2D-LABEL: D_ctor_base: ; CHECKT2D-NOT: mov {{r[0-9]+}}, r0 -; CHECKT2D: blx _B_ctor_complete +; CHECKT2D: bl _B_ctor_complete ; CHECKT2D-NOT: mov r0, {{r[0-9]+}} ; CHECKT2D: b.w _B_ctor_complete %b = getelementptr inbounds %struct.D, %struct.D* %this, i32 0, i32 0 diff --git a/test/CodeGen/ARM/thread_pointer.ll b/test/CodeGen/ARM/thread_pointer.ll index c403fa5c4a2a..fe1d3a4dfd0f 100644 --- a/test/CodeGen/ARM/thread_pointer.ll +++ b/test/CodeGen/ARM/thread_pointer.ll @@ -3,8 +3,8 @@ define i8* @test() { entry: - %tmp1 = call i8* @llvm.arm.thread.pointer( ) ; [#uses=0] + %tmp1 = call i8* @llvm.thread.pointer( ) ; [#uses=0] ret i8* %tmp1 } -declare i8* @llvm.arm.thread.pointer() +declare i8* @llvm.thread.pointer() diff --git a/test/CodeGen/ARM/thumb-alignment.ll b/test/CodeGen/ARM/thumb-alignment.ll index b9ddfbb714d1..8e894d28b6c6 100644 --- a/test/CodeGen/ARM/thumb-alignment.ll +++ b/test/CodeGen/ARM/thumb-alignment.ll @@ -3,13 +3,13 @@ @x = external global i32 ; CHECK: .globl foo -; CHECK-NEXT: .align 2 +; CHECK-NEXT: .p2align 2 define i32* @foo() { ret i32* @x } ; CHECK: .globl bar -; CHECK-NEXT: .align 1 +; CHECK-NEXT: .p2align 1 define i32* @bar() { ret i32* zeroinitializer } @@ -22,7 +22,7 @@ define i32* @bar() { ; Create a Thumb-2 jump table, which should force alignment to 4 bytes. ; CHECK: .globl baz -; CHECK-NEXT: .align 2 +; CHECK-NEXT: .p2align 2 ; CHECK: tbb define i32 @baz() { %1 = load i32, i32* @c, align 4 diff --git a/test/CodeGen/ARM/thumb-stub.ll b/test/CodeGen/ARM/thumb-stub.ll new file mode 100644 index 000000000000..68001b6c0eec --- /dev/null +++ b/test/CodeGen/ARM/thumb-stub.ll @@ -0,0 +1,10 @@ +; RUN: llc -relocation-model=pic -mtriple=thumb-apple-darwin < %s | FileCheck %s + +declare hidden void @f() + +; CHECK: bl _f + +define void @g() { + call void @f() + ret void +} diff --git a/test/CodeGen/ARM/thumb1-ldst-opt.ll b/test/CodeGen/ARM/thumb1-ldst-opt.ll index eb82385de0c5..f3c83f04588f 100644 --- a/test/CodeGen/ARM/thumb1-ldst-opt.ll +++ b/test/CodeGen/ARM/thumb1-ldst-opt.ll @@ -1,4 +1,4 @@ -; RUN: llc -stop-after block-placement -o /dev/null %s | FileCheck %s +; RUN: llc -stop-after block-placement -o - %s | FileCheck %s target triple = "thumbv6m-none-none" diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll index 0637be03d565..3787c4282b28 100644 --- a/test/CodeGen/ARM/thumb1-varalloc.ll +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -52,7 +52,7 @@ define void @test_simple_var() { ; CHECK: mov r0, sp ; CHECK-NOT: adds r0 -; CHECK: blx +; CHECK: bl call void @take_ptr(i8* %addr8) ret void } @@ -67,12 +67,12 @@ define void @test_local_var_addr_aligned() { %addr2 = bitcast i32* %addr2.32 to i8* ; CHECK: add r0, sp, #{{[0-9]+}} -; CHECK: blx +; CHECK: bl call void @take_ptr(i8* %addr1) ; CHECK: mov r0, sp ; CHECK-NOT: add r0 -; CHECK: blx +; CHECK: bl call void @take_ptr(i8* %addr2) ret void @@ -87,7 +87,7 @@ define void @test_local_var_big_offset() { ; CHECK: add [[RTMP:r[0-9]+]], sp, #1020 ; CHECK: adds [[RTMP]], #8 -; CHECK: blx +; CHECK: bl call void @take_ptr(i8* %addr1) ret void @@ -100,7 +100,7 @@ define void @test_local_var_offset_1020() { %addr2 = alloca i8, i32 1020 ; CHECK: add r0, sp, #1020 -; CHECK-NEXT: blx +; CHECK-NEXT: bl call void @take_ptr(i8* %addr1) ret void @@ -116,7 +116,7 @@ define void @test_local_var_offset_1268() { ; CHECK: add r0, sp, #1020 ; CHECK: adds r0, #248 -; CHECK-NEXT: blx +; CHECK-NEXT: bl call void @take_ptr(i8* %addr1) ret void diff --git a/test/CodeGen/ARM/thumb2-size-opt.ll b/test/CodeGen/ARM/thumb2-size-opt.ll index 0084a456a72e..aba027607ea7 100644 --- a/test/CodeGen/ARM/thumb2-size-opt.ll +++ b/test/CodeGen/ARM/thumb2-size-opt.ll @@ -82,3 +82,19 @@ entry: %shr = lshr i32 %a, %b ret i32 %shr } + +define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize { +; CHECK-LABEL: bundled_instruction: +; CHECK: iteee ne +; CHECK: ldmeq r0!, {{{r[0-9]+}}} + br i1 %tst, label %true, label %false + +true: + ret i32 0 + +false: + %res = load i32, i32* %addr, align 4 + %next = getelementptr i32, i32* %addr, i32 1 + store i32* %next, i32** %addr2 + ret i32 %res +} diff --git a/test/CodeGen/ARM/tls-models.ll b/test/CodeGen/ARM/tls-models.ll index f3c58f74ebf7..d8c74d213b13 100644 --- a/test/CodeGen/ARM/tls-models.ll +++ b/test/CodeGen/ARM/tls-models.ll @@ -130,7 +130,7 @@ entry: ; EMU-NOT: __emutls_t.external_gd ; EMU-NOT: __emutls_v.external_gd -; EMU: .align 2 +; EMU: .p2align 2 ; EMU-LABEL: __emutls_v.internal_gd: ; EMU-NEXT: .long 4 ; EMU-NEXT: .long 4 @@ -144,7 +144,7 @@ entry: ; EMU-NOT: __emutls_t.external_gd ; EMU-NOT: __emutls_v.external_gd -; EMU: .align 2 +; EMU: .p2align 2 ; EMU-LABEL: __emutls_v.internal_le: ; EMU-NEXT: .long 4 ; EMU-NEXT: .long 4 diff --git a/test/CodeGen/ARM/tls3.ll b/test/CodeGen/ARM/tls3.ll index 94cadeedd938..ca3cde264da7 100644 --- a/test/CodeGen/ARM/tls3.ll +++ b/test/CodeGen/ARM/tls3.ll @@ -23,7 +23,7 @@ entry: ; CHECK-NOT: __emutls_t.teste -; EMU: .align 2 +; EMU: .p2align 2 ; EMU-LABEL: __emutls_v.teste: ; EMU-NEXT: .long 8 ; EMU-NEXT: .long 4 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index 0baf50b45b20..585218cf337c 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,38 +1,56 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=INSTR +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN ; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC ; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap -O0 | FileCheck %s -check-prefix=FUNC -; RUN: llc -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \ -; RUN: | llvm-objdump -disassemble -triple armv7-unknown-nacl - \ -; RUN: | FileCheck %s -check-prefix=ENCODING-NACL -; RUN: llc -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \ -; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \ -; RUN: | FileCheck %s -check-prefix=ENCODING-NACL +; RUN: llc < %s -mtriple=armv7 -mattr=+nacl-trap | FileCheck %s -check-prefix=NACL +; RUN: llc < %s -mtriple=armv7 | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=thumbv7 | FileCheck %s -check-prefix=THUMB + ; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-NACL -; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \ -; RUN: | llvm-objdump -disassemble -triple armv7-unknown-nacl - \ +; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \ +; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-NACL + ; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 - \ -; RUN: | FileCheck %s -check-prefix=ENCODING-ALL +; RUN: | FileCheck %s -check-prefix=ENCODING-ARM ; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 - \ -; RUN: | FileCheck %s -check-prefix=ENCODING-ALL +; RUN: | FileCheck %s -check-prefix=ENCODING-ARM + +; RUN: llc -mtriple=thumbv7 -filetype=obj %s -o - \ +; RUN: | llvm-objdump -disassemble -triple thumbv7 - \ +; RUN: | FileCheck %s -check-prefix=ENCODING-THUMB +; RUN: llc -verify-machineinstrs -fast-isel -mtriple=thumbv7 -filetype=obj %s -o - \ +; RUN: | llvm-objdump -disassemble -triple thumbv7 - \ +; RUN: | FileCheck %s -check-prefix=ENCODING-THUMB + ; rdar://7961298 ; rdar://9249183 define void @t() nounwind { entry: -; INSTR-LABEL: t: -; INSTR: trap +; DARWIN-LABEL: t: +; DARWIN: trap ; FUNC-LABEL: t: ; FUNC: bl __trap -; ENCODING-NACL: f0 de fe e7 +; NACL-LABEL: t: +; NACL: .inst 0xe7fedef0 -; ENCODING-ALL: fe de ff e7 +; ARM-LABEL: t: +; ARM: .inst 0xe7ffdefe + +; THUMB-LABEL: t: +; THUMB: .inst.n 0xdefe + +; ENCODING-NACL: f0 de fe e7 trap + +; ENCODING-ARM: fe de ff e7 trap + +; ENCODING-THUMB: fe de trap call void @llvm.trap() unreachable @@ -40,15 +58,26 @@ entry: define void @t2() nounwind { entry: -; INSTR-LABEL: t2: -; INSTR: trap +; DARWIN-LABEL: t2: +; DARWIN: trap ; FUNC-LABEL: t2: ; FUNC: bl __trap -; ENCODING-NACL: f0 de fe e7 +; NACL-LABEL: t2: +; NACL: .inst 0xe7fedef0 + +; ARM-LABEL: t2: +; ARM: .inst 0xe7ffdefe + +; THUMB-LABEL: t2: +; THUMB: .inst.n 0xdefe + +; ENCODING-NACL: f0 de fe e7 trap + +; ENCODING-ARM: fe de ff e7 trap -; ENCODING-ALL: fe de ff e7 +; ENCODING-THUMB: fe de trap call void @llvm.debugtrap() unreachable diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll index 11fa022451f6..5142a305b3a7 100644 --- a/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -1,5 +1,8 @@ ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s +; CHECK-LABEL: bar +; CHECK-NOT: orr +; CHECK-NOT: mov define void @bar(i8* %P, i16* %Q) { entry: %P1 = bitcast i8* %P to i16* ; [#uses=1] @@ -8,6 +11,9 @@ entry: ret void } +; CHECK-LABEL: foo +; CHECK-NOT: orr +; CHECK-NOT: mov define void @foo(i8* %P, i32* %Q) { entry: %P1 = bitcast i8* %P to i32* ; [#uses=1] @@ -15,7 +21,3 @@ entry: store i32 %tmp, i32* %P1, align 1 ret void } - -; CHECK-NOT: orr -; CHECK-NOT: mov - diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll index 97a49334b742..f0a95c833c6b 100644 --- a/test/CodeGen/ARM/twoaddrinstr.ll +++ b/test/CodeGen/ARM/twoaddrinstr.ll @@ -5,6 +5,7 @@ define void @PR13378() nounwind { ; This was orriginally a crasher trying to schedule the instructions. ; CHECK-LABEL: PR13378: ; CHECK: vld1.32 +; CHECK-NEXT: vmov.i32 ; CHECK-NEXT: vst1.32 ; CHECK-NEXT: vst1.32 ; CHECK-NEXT: vmov.f32 diff --git a/test/CodeGen/ARM/urem-opt-size.ll b/test/CodeGen/ARM/urem-opt-size.ll new file mode 100644 index 000000000000..7f1cd43bc4e3 --- /dev/null +++ b/test/CodeGen/ARM/urem-opt-size.ll @@ -0,0 +1,45 @@ +; When optimising for minimum size, we don't want to expand a div to a mul +; and a shift sequence. As a result, the urem instruction e.g. will not be +; expanded to a sequence of umull, lsrs, muls and sub instructions, but +; just a call to __aeabi_uidivmod. +; +; RUN: llc -mtriple=armv7a-eabi -mattr=-neon -verify-machineinstrs %s -o - | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" +target triple = "thumbv7m-arm-none-eabi" + +define i32 @foo1() local_unnamed_addr #0 { +entry: +; CHECK-LABEL: foo1: +; CHECK:__aeabi_idiv +; CHECK-NOT: smmul + %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() + %div = sdiv i32 %call, 1000000 + ret i32 %div +} + +define i32 @foo2() local_unnamed_addr #0 { +entry: +; CHECK-LABEL: foo2: +; CHECK: __aeabi_uidiv +; CHECK-NOT: umull + %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() + %div = udiv i32 %call, 1000000 + ret i32 %div +} + +define i32 @foo3() local_unnamed_addr #0 { +entry: +; CHECK-LABEL: foo3: +; CHECK: __aeabi_uidivmod +; CHECK-NOT: umull + %call = tail call i32 bitcast (i32 (...)* @GetValue to i32 ()*)() + %rem = urem i32 %call, 1000000 + %cmp = icmp eq i32 %rem, 0 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +declare i32 @GetValue(...) local_unnamed_addr + +attributes #0 = { minsize nounwind optsize } diff --git a/test/CodeGen/ARM/v7k-libcalls.ll b/test/CodeGen/ARM/v7k-libcalls.ll index a1dfb07ca614..8ca31ef4e652 100644 --- a/test/CodeGen/ARM/v7k-libcalls.ll +++ b/test/CodeGen/ARM/v7k-libcalls.ll @@ -145,6 +145,15 @@ define arm_aapcs_vfpcc double @t14(double %x) { ret double %__exp10 } +define i16 @t15(double %x) { +; CHECK-LABEL: t15: +; CHECK-NOT: vmov +; CHECK: bl ___truncdfhf2 + %tmp0 = fptrunc double %x to half + %tmp1 = bitcast half %tmp0 to i16 + ret i16 %tmp1 +} + declare arm_aapcs_vfpcc double @x(double, double, double, double, double, double, double, float, double) declare arm_aapcs_vfpcc double @cos(double) #0 declare arm_aapcs_vfpcc double @sin(double) #0 diff --git a/test/CodeGen/ARM/v7k-sincos.ll b/test/CodeGen/ARM/v7k-sincos.ll index b89d4dc8120b..2db2dc088d95 100644 --- a/test/CodeGen/ARM/v7k-sincos.ll +++ b/test/CodeGen/ARM/v7k-sincos.ll @@ -5,7 +5,7 @@ declare double @cos(double) nounwind readnone define double @test_stret(double %in) { ; CHECK-LABEL: test_stret: -; CHECK: blx ___sincos_stret +; CHECK: bl ___sincos_stret ; CHECK-NOT: ldr ; CHECK: vadd.f64 d0, d0, d1 diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll index de251c58e6b9..6d9667bda6f3 100644 --- a/test/CodeGen/ARM/vcnt.ll +++ b/test/CodeGen/ARM/vcnt.ll @@ -44,6 +44,13 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { ret <2 x i32> %tmp2 } +define <1 x i64> @vclz64(<1 x i64>* %A) nounwind { +;CHECK-LABEL: vclz64: + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 0) + ret <1 x i64> %tmp2 +} + define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} @@ -68,13 +75,84 @@ define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } +define <2 x i64> @vclzQ64(<2 x i64>* %A) nounwind { +;CHECK-LABEL: vclzQ64: + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 0) + ret <2 x i64> %tmp2 +} + +define <8 x i8> @vclz8b(<8 x i8>* %A) nounwind { +;CHECK-LABEL: vclz8b: +;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <8 x i8>, <8 x i8>* %A + %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 1) + ret <8 x i8> %tmp2 +} + +define <4 x i16> @vclz16b(<4 x i16>* %A) nounwind { +;CHECK-LABEL: vclz16b: +;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <4 x i16>, <4 x i16>* %A + %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 1) + ret <4 x i16> %tmp2 +} + +define <2 x i32> @vclz32b(<2 x i32>* %A) nounwind { +;CHECK-LABEL: vclz32b: +;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} + %tmp1 = load <2 x i32>, <2 x i32>* %A + %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 1) + ret <2 x i32> %tmp2 +} + +define <1 x i64> @vclz64b(<1 x i64>* %A) nounwind { +;CHECK-LABEL: vclz64b: + %tmp1 = load <1 x i64>, <1 x i64>* %A + %tmp2 = call <1 x i64> @llvm.ctlz.v1i64(<1 x i64> %tmp1, i1 1) + ret <1 x i64> %tmp2 +} + +define <16 x i8> @vclzQ8b(<16 x i8>* %A) nounwind { +;CHECK-LABEL: vclzQ8b: +;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <16 x i8>, <16 x i8>* %A + %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 1) + ret <16 x i8> %tmp2 +} + +define <8 x i16> @vclzQ16b(<8 x i16>* %A) nounwind { +;CHECK-LABEL: vclzQ16b: +;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <8 x i16>, <8 x i16>* %A + %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 1) + ret <8 x i16> %tmp2 +} + +define <4 x i32> @vclzQ32b(<4 x i32>* %A) nounwind { +;CHECK-LABEL: vclzQ32b: +;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} + %tmp1 = load <4 x i32>, <4 x i32>* %A + %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 1) + ret <4 x i32> %tmp2 +} + +define <2 x i64> @vclzQ64b(<2 x i64>* %A) nounwind { +;CHECK-LABEL: vclzQ64b: + %tmp1 = load <2 x i64>, <2 x i64>* %A + %tmp2 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %tmp1, i1 1) + ret <2 x i64> %tmp2 +} + declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone +declare <1 x i64> @llvm.ctlz.v1i64(<1 x i64>, i1) nounwind readnone declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclss8: diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll index 9a8f084d2303..11bed5a1a474 100644 --- a/test/CodeGen/ARM/vcvt_combine.ll +++ b/test/CodeGen/ARM/vcvt_combine.ll @@ -62,3 +62,11 @@ define <4 x i32> @t5(<4 x float> %in) { %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32> ret <4 x i32> %vcvt.i } + +; CHECK-LABEL: test_illegal_fp_to_int: +; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2 +define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { + %scale = fmul <3 x float> %in, + %val = fptosi <3 x float> %scale to <3 x i32> + ret <3 x i32> %val +} \ No newline at end of file diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 8511dbcb6876..4a6c36b42772 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -153,3 +153,11 @@ define <4 x float> @test8(<4 x i32> %in) { %div.i = fdiv <4 x float> %vcvt.i, ret <4 x float> %div.i } + +; CHECK-LABEL: test_illegal_int_to_fp: +; CHECK: vcvt.f32.s32 +define <3 x float> @test_illegal_int_to_fp(<3 x i32> %in) { + %conv = sitofp <3 x i32> %in to <3 x float> + %res = fdiv <3 x float> %conv, + ret <3 x float> %res +} \ No newline at end of file diff --git a/test/CodeGen/ARM/vfp-libcalls.ll b/test/CodeGen/ARM/vfp-libcalls.ll index b08073ab62b3..59d5ccc95840 100644 --- a/test/CodeGen/ARM/vfp-libcalls.ll +++ b/test/CodeGen/ARM/vfp-libcalls.ll @@ -4,7 +4,7 @@ define float @test_call(float %a, float %b) { ; CHECK-HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} -; CHECK-SOFTISH: blx ___addsf3vfp +; CHECK-SOFTISH: bl ___addsf3vfp ; CHECK-SOFT: bl ___addsf3{{$}} %sum = fadd float %a, %b ret float %sum diff --git a/test/CodeGen/ARM/vfp-regs-dwarf.ll b/test/CodeGen/ARM/vfp-regs-dwarf.ll index 1b2055e5aff1..2ab85053a91f 100644 --- a/test/CodeGen/ARM/vfp-regs-dwarf.ll +++ b/test/CodeGen/ARM/vfp-regs-dwarf.ll @@ -31,11 +31,10 @@ define void @stack_offsets() !dbg !4 { !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !9} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: 1, file: !1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 3.5.0 ", isOptimized: false, emissionKind: FullDebug, file: !1, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2) +!4 = distinct !DISubprogram(name: "bar", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !0, scopeLine: 1, file: !1, scope: !5, type: !6, variables: !2) !5 = !DIFile(filename: "tmp.c", directory: "/Users/tim/llvm/build") !6 = !DISubroutineType(types: !7) !7 = !{null} diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll index 011bfd7ff88e..e4f30faa9177 100644 --- a/test/CodeGen/ARM/vminmax.ll +++ b/test/CodeGen/ARM/vminmax.ll @@ -291,3 +291,20 @@ declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind read declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone + +declare float @llvm.maxnum.f32(float %a, float %b) +declare float @llvm.minnum.f32(float %a, float %b) + +define float @maxnum(float %a, float %b) { +;CHECK-LABEL: maxnum: +;CHECK: vmax.f32 + %r = call nnan float @llvm.maxnum.f32(float %a, float %b) + ret float %r +} + +define float @minnum(float %a, float %b) { +;CHECK-LABEL: minnum: +;CHECK: vmin.f32 + %r = call nnan float @llvm.minnum.f32(float %a, float %b) + ret float %r +} diff --git a/test/CodeGen/ARM/warn-stack.ll b/test/CodeGen/ARM/warn-stack.ll index 474dc1dfb447..6e819e404323 100644 --- a/test/CodeGen/ARM/warn-stack.ll +++ b/test/CodeGen/ARM/warn-stack.ll @@ -12,7 +12,7 @@ entry: ret void } -; CHECK: warning: stack size limit exceeded (96) in warn +; CHECK: warning: stack size limit exceeded (92) in warn define void @warn() nounwind ssp { entry: %buffer = alloca [80 x i8], align 1 diff --git a/test/CodeGen/ARM/wide-compares.ll b/test/CodeGen/ARM/wide-compares.ll new file mode 100644 index 000000000000..08e07ef76ad7 --- /dev/null +++ b/test/CodeGen/ARM/wide-compares.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=armv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-ARM %s +; RUN: llc -mtriple=thumbv6-unknown-linux < %s | FileCheck --check-prefix=CHECK-THUMB1 %s +; RUN: llc -mtriple=thumbv7-unknown-linux < %s | FileCheck --check-prefix=CHECK --check-prefix=CHECK-THUMB2 %s + +; CHECK-THUMB1-NOT: sbc + +; CHECK-LABEL: test_slt1: +define i32 @test_slt1(i64 %a, i64 %b) { +entry: + ; CHECK-ARM: subs {{[^,]+}}, r0, r2 + ; CHECK-ARM: mov [[TMP:[0-9a-z]+]], #2 + ; CHECK-ARM: sbcs {{[^,]+}}, r1, r3 + ; CHECK-ARM: movwlt [[TMP]], #1 + ; CHECK-ARM: mov r0, [[TMP]] + ; CHECK-ARM: bx lr + ; CHECK-THUMB2: subs {{[^,]+}}, r0, r2 + ; CHECK-THUMB2: mov.w [[TMP:[0-9a-z]+]], #2 + ; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3 + ; CHECK-THUMB2: it lt + ; CHECK-THUMB2: movlt.w [[TMP]], #1 + ; CHECK-THUMB2: mov r0, [[TMP]] + ; CHECK-THUMB2: bx lr + %cmp = icmp slt i64 %a, %b + br i1 %cmp, label %bb1, label %bb2 +bb1: + ret i32 1 +bb2: + ret i32 2 +} + +; CHECK-LABEL: test_slt2: +define void @test_slt2(i64 %a, i64 %b) { +entry: + %cmp = icmp slt i64 %a, %b + ; CHECK-ARM: subs {{[^,]+}}, r0, r2 + ; CHECK-ARM: sbcs {{[^,]+}}, r1, r3 + ; CHECK-THUMB2: subs {{[^,]+}}, r0, r2 + ; CHECK-THUMB2: sbcs.w {{[^,]+}}, r1, r3 + ; CHECK: bge [[BB2:\.[0-9A-Za-z_]+]] + br i1 %cmp, label %bb1, label %bb2 +bb1: + call void @f() + ret void +bb2: + ; CHECK: [[BB2]]: + ; CHECK-NEXT: bl g + call void @g() + ret void +} + +declare void @f() +declare void @g() diff --git a/test/CodeGen/ARM/widen-vmovs.ll b/test/CodeGen/ARM/widen-vmovs.ll index 316cfabab48c..2abf8d9701fc 100644 --- a/test/CodeGen/ARM/widen-vmovs.ll +++ b/test/CodeGen/ARM/widen-vmovs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -widen-vmovs -mcpu=cortex-a8 -verify-machineinstrs -disable-block-placement | FileCheck %s +; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -disable-block-placement | FileCheck %s target triple = "thumbv7-apple-ios" ; The 1.0e+10 constant is loaded from the constant pool and kept in a register. diff --git a/test/CodeGen/ARM/zero-cycle-zero.ll b/test/CodeGen/ARM/zero-cycle-zero.ll index 4e8696f4418a..2022d88dd0ee 100644 --- a/test/CodeGen/ARM/zero-cycle-zero.ll +++ b/test/CodeGen/ARM/zero-cycle-zero.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=armv8 -mcpu=cyclone < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT -; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s --check-prefix=CHECK +; RUN: llc -mtriple=armv8 -mcpu=swift < %s | FileCheck %s ; RUN: llc -mtriple=armv8 -mcpu=cortex-a57 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NOTSWIFT declare arm_aapcs_vfpcc void @take_vec64(<2 x i32>) diff --git a/test/CodeGen/BPF/sdiv_error.ll b/test/CodeGen/BPF/sdiv_error.ll new file mode 100644 index 000000000000..053b82dd98fa --- /dev/null +++ b/test/CodeGen/BPF/sdiv_error.ll @@ -0,0 +1,9 @@ +; RUN: not llc -march=bpf < %s 2> %t1 +; RUN: FileCheck %s < %t1 +; CHECK: Unsupport signed division + +; Function Attrs: norecurse nounwind readnone +define i32 @test(i32 %len) #0 { + %1 = srem i32 %len, 15 + ret i32 %1 +} diff --git a/test/CodeGen/CPP/2007-06-16-Funcname.ll b/test/CodeGen/CPP/2007-06-16-Funcname.ll deleted file mode 100644 index 71fea12d9c2c..000000000000 --- a/test/CodeGen/CPP/2007-06-16-Funcname.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llc < %s -march=cpp -cppfname=WAKKA | not grep makeLLVMModule -; PR1515 - -define void @foo() { - ret void -} - diff --git a/test/CodeGen/CPP/2009-05-01-Long-Double.ll b/test/CodeGen/CPP/2009-05-01-Long-Double.ll deleted file mode 100644 index 470303d6bb05..000000000000 --- a/test/CodeGen/CPP/2009-05-01-Long-Double.ll +++ /dev/null @@ -1,13 +0,0 @@ -; RUN: llc < %s -march=cpp -cppgen=program -o %t - -define x86_fp80 @some_func() nounwind { -entry: - %retval = alloca x86_fp80 ; [#uses=2] - %call = call i32 (...) @other_func() ; [#uses=1] - %conv = sitofp i32 %call to x86_fp80 ; [#uses=1] - store x86_fp80 %conv, x86_fp80* %retval - %0 = load x86_fp80, x86_fp80* %retval ; [#uses=1] - ret x86_fp80 %0 -} - -declare i32 @other_func(...) diff --git a/test/CodeGen/CPP/2009-05-04-CondBr.ll b/test/CodeGen/CPP/2009-05-04-CondBr.ll deleted file mode 100644 index 9ce1e5f02042..000000000000 --- a/test/CodeGen/CPP/2009-05-04-CondBr.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc < %s -march=cpp -cppgen=program -o %t -; RUN: grep "BranchInst::Create(label_if_then, label_if_end, int1_cmp, label_entry);" %t - -define i32 @some_func(i32 %a) nounwind { -entry: - %retval = alloca i32 ; [#uses=2] - %a.addr = alloca i32 ; [#uses=8] - store i32 %a, i32* %a.addr - %tmp = load i32, i32* %a.addr ; [#uses=1] - %inc = add i32 %tmp, 1 ; [#uses=1] - store i32 %inc, i32* %a.addr - %tmp1 = load i32, i32* %a.addr ; [#uses=1] - %cmp = icmp slt i32 %tmp1, 3 ; [#uses=1] - br i1 %cmp, label %if.then, label %if.end - -if.then: ; preds = %entry - store i32 7, i32* %a.addr - br label %if.end - -if.end: ; preds = %if.then, %entry - %tmp2 = load i32, i32* %a.addr ; [#uses=1] - %inc3 = add i32 %tmp2, 1 ; [#uses=1] - store i32 %inc3, i32* %a.addr - %tmp4 = load i32, i32* %a.addr ; [#uses=1] - store i32 %tmp4, i32* %retval - %0 = load i32, i32* %retval ; [#uses=1] - ret i32 %0 -} diff --git a/test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll b/test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll deleted file mode 100644 index 419f59476784..000000000000 --- a/test/CodeGen/CPP/2012-02-05-UnitVarCrash.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=cpp -declare void @foo(<4 x i32>) -define void @bar() { - call void @foo(<4 x i32> ) - ret void -} diff --git a/test/CodeGen/CPP/atomic.ll b/test/CodeGen/CPP/atomic.ll deleted file mode 100644 index e79c45d166a5..000000000000 --- a/test/CodeGen/CPP/atomic.ll +++ /dev/null @@ -1,89 +0,0 @@ -; RUN: llc -march=cpp -o - %s | FileCheck %s - -define void @test_atomicrmw(i32* %addr, i32 %inc) { - %inst0 = atomicrmw xchg i32* %addr, i32 %inc seq_cst - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThread - ; CHECK: [[INST]]->setName("inst0"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst1 = atomicrmw add i32* %addr, i32 %inc seq_cst - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThread - ; CHECK: [[INST]]->setName("inst1"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst2 = atomicrmw volatile sub i32* %addr, i32 %inc singlethread monotonic - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Sub, {{.*}}, Monotonic, SingleThread - ; CHECK: [[INST]]->setName("inst2"); - ; CHECK: [[INST]]->setVolatile(true); - - %inst3 = atomicrmw and i32* %addr, i32 %inc acq_rel - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::And, {{.*}}, AcquireRelease, CrossThread - ; CHECK: [[INST]]->setName("inst3"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst4 = atomicrmw nand i32* %addr, i32 %inc release - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Nand, {{.*}}, Release, CrossThread - ; CHECK: [[INST]]->setName("inst4"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst5 = atomicrmw volatile or i32* %addr, i32 %inc singlethread seq_cst - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThread - ; CHECK: [[INST]]->setName("inst5"); - ; CHECK: [[INST]]->setVolatile(true); - - %inst6 = atomicrmw xor i32* %addr, i32 %inc release - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xor, {{.*}}, Release, CrossThread - ; CHECK: [[INST]]->setName("inst6"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst7 = atomicrmw volatile max i32* %addr, i32 %inc singlethread monotonic - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Max, {{.*}}, Monotonic, SingleThread - ; CHECK: [[INST]]->setName("inst7"); - ; CHECK: [[INST]]->setVolatile(true); - - %inst8 = atomicrmw min i32* %addr, i32 %inc acquire - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Min, {{.*}}, Acquire, CrossThread - ; CHECK: [[INST]]->setName("inst8"); - ; CHECK: [[INST]]->setVolatile(false); - - %inst9 = atomicrmw volatile umax i32* %addr, i32 %inc monotonic - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMax, {{.*}}, Monotonic, CrossThread - ; CHECK: [[INST]]->setName("inst9"); - ; CHECK: [[INST]]->setVolatile(true); - - %inst10 = atomicrmw umin i32* %addr, i32 %inc singlethread release - ; CHECK: AtomicRMWInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::UMin, {{.*}}, Release, SingleThread - ; CHECK: [[INST]]->setName("inst10"); - ; CHECK: [[INST]]->setVolatile(false); - - - ret void -} - -define void @test_cmpxchg(i32* %addr, i32 %desired, i32 %new) { - %inst0 = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic - ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread - ; CHECK: [[INST]]->setName("inst0"); - ; CHECK: [[INST]]->setVolatile(false); - ; CHECK: [[INST]]->setWeak(false); - - %inst1 = cmpxchg volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire - ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread - ; CHECK: [[INST]]->setName("inst1"); - ; CHECK: [[INST]]->setVolatile(true); - ; CHECK: [[INST]]->setWeak(false); - - %inst2 = cmpxchg weak i32* %addr, i32 %desired, i32 %new seq_cst monotonic - ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic, CrossThread - ; CHECK: [[INST]]->setName("inst2"); - ; CHECK: [[INST]]->setVolatile(false); - ; CHECK: [[INST]]->setWeak(true); - - %inst3 = cmpxchg weak volatile i32* %addr, i32 %desired, i32 %new singlethread acq_rel acquire - ; CHECK: AtomicCmpXchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, AcquireRelease, Acquire, SingleThread - ; CHECK: [[INST]]->setName("inst3"); - ; CHECK: [[INST]]->setVolatile(true); - ; CHECK: [[INST]]->setWeak(true); - - ret void -} diff --git a/test/CodeGen/CPP/attributes.ll b/test/CodeGen/CPP/attributes.ll deleted file mode 100644 index 3dab617d80b9..000000000000 --- a/test/CodeGen/CPP/attributes.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llc < %s -march=cpp | FileCheck %s - -define void @f1(i8* byval, i8* inalloca) { -; CHECK: ByVal -; CHECK: InAlloca - ret void -} diff --git a/test/CodeGen/CPP/gep.ll b/test/CodeGen/CPP/gep.ll deleted file mode 100644 index 88a0bf1f216d..000000000000 --- a/test/CodeGen/CPP/gep.ll +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llc -march=cpp -o - %s | FileCheck %s - -define void @f1(i32* %addr) { - %x = getelementptr i32, i32* %addr, i32 1 -; CHECK: ConstantInt* [[INT_1:.*]] = ConstantInt::get(mod->getContext(), APInt(32, StringRef("1"), 10)); -; CHECK: GetElementPtrInst::Create(IntegerType::get(mod->getContext(), 32), ptr_addr, -; CHECK-NEXT: [[INT_1]] -; CHECK-NEXT: }, "x", label_3); - ret void -} diff --git a/test/CodeGen/CPP/lit.local.cfg b/test/CodeGen/CPP/lit.local.cfg deleted file mode 100644 index 3ff5c6b69737..000000000000 --- a/test/CodeGen/CPP/lit.local.cfg +++ /dev/null @@ -1,3 +0,0 @@ -if not 'CppBackend' in config.root.targets: - config.unsupported = True - diff --git a/test/CodeGen/Generic/MachineBranchProb.ll b/test/CodeGen/Generic/MachineBranchProb.ll index ae3c8da21471..e70215049995 100644 --- a/test/CodeGen/Generic/MachineBranchProb.ll +++ b/test/CodeGen/Generic/MachineBranchProb.ll @@ -2,7 +2,7 @@ ; ARM & AArch64 run an extra SimplifyCFG which disrupts this test. ; Hexagon crashes (PR23377) -; XFAIL: arm,aarch64,hexagon +; XFAIL: arm,aarch64 ; Make sure we have the correct weight attached to each successor. define i32 @test2(i32 %x) nounwind uwtable readnone ssp { @@ -41,11 +41,11 @@ define void @left_leaning_weight_balanced_tree(i32 %x) { entry: switch i32 %x, label %return [ i32 0, label %bb0 - i32 10, label %bb1 - i32 20, label %bb2 - i32 30, label %bb3 - i32 40, label %bb4 - i32 50, label %bb5 + i32 100, label %bb1 + i32 200, label %bb2 + i32 300, label %bb3 + i32 400, label %bb4 + i32 500, label %bb5 ], !prof !1 bb0: tail call void @g(i32 0) br label %return bb1: tail call void @g(i32 1) br label %return @@ -68,7 +68,7 @@ return: ret void !1 = !{!"branch_weights", ; Default: i32 1, - ; Case 0, 10, 20: + ; Case 0, 100, 200: i32 10, i32 1, i32 1, - ; Case 30, 40, 50: + ; Case 300, 400, 500: i32 1, i32 10, i32 10} diff --git a/test/CodeGen/Generic/Makefile b/test/CodeGen/Generic/Makefile deleted file mode 100644 index 26ebc316a215..000000000000 --- a/test/CodeGen/Generic/Makefile +++ /dev/null @@ -1,23 +0,0 @@ -# Makefile for running ad-hoc custom LLVM tests -# -%.bc: %.ll - llvm-as $< - -%.llc.s: %.bc - llc $< -o $@ - -%.gcc.s: %.c - gcc -O0 -S $< -o $@ - -%.nat: %.s - gcc -O0 -lm $< -o $@ - -%.cbe.out: %.cbe.nat - ./$< > $@ - -%.out: %.nat - ./$< > $@ - -%.clean: - rm -f $(patsubst %.clean,%.bc,$@) $(patsubst %.clean,%.*.s,$@) \ - $(patsubst %.clean,%.*.nat,$@) $(patsubst %.clean,%.*.out,$@) diff --git a/test/CodeGen/Generic/dont-remove-empty-preheader.ll b/test/CodeGen/Generic/dont-remove-empty-preheader.ll new file mode 100644 index 000000000000..36af1ffa8bad --- /dev/null +++ b/test/CodeGen/Generic/dont-remove-empty-preheader.ll @@ -0,0 +1,39 @@ +; RUN: opt -codegenprepare -S < %s | FileCheck %s +; CHECK: for.body.preheader + +@N = common global i32 0, align 4 +@E = common global i8** null, align 8 +@B = common global i8** null, align 8 + +; Function Attrs: nounwind +define i32 @foo() { +entry: + %0 = load i32, i32* @N, align 4 + %1 = load i8**, i8*** @E, align 8 + %2 = load i8**, i8*** @B, align 8 + %cmp7 = icmp eq i8** %2, %1 + br i1 %cmp7, label %for.cond.cleanup, label %for.body.preheader + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + %add.lcssa = phi i32 [ %add, %for.body ] + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + %n.0.lcssa = phi i32 [ %0, %entry ], [ %add.lcssa, %for.cond.cleanup.loopexit ] + ret i32 %n.0.lcssa + +for.body: ; preds = %for.body.preheader, %for.body + %I.09 = phi i8** [ %incdec.ptr, %for.body ], [ %2, %for.body.preheader ] + %n.08 = phi i32 [ %add, %for.body ], [ %0, %for.body.preheader ] + %3 = load i8*, i8** %I.09, align 8 + %call = tail call i32 @map(i8* %3) + %add = add nsw i32 %call, %n.08 + %incdec.ptr = getelementptr inbounds i8*, i8** %I.09, i64 1 + %cmp = icmp eq i8** %incdec.ptr, %1 + br i1 %cmp, label %for.cond.cleanup.loopexit, label %for.body +} + +declare i32 @map(i8*) diff --git a/test/CodeGen/Generic/run-pass.ll b/test/CodeGen/Generic/run-pass.ll deleted file mode 100644 index 55d62ec18648..000000000000 --- a/test/CodeGen/Generic/run-pass.ll +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llc < %s -debug-pass=Structure -run-pass=gc-lowering -o /dev/null 2>&1 | FileCheck %s - -; CHECK: -gc-lowering -; CHECK: FunctionPass Manager -; CHECK-NEXT: Lower Garbage Collection Instructions -; CHECK-NEXT: Machine Function Analysis -; CHECK-NEXT: MIR Printing Pass diff --git a/test/CodeGen/Generic/stop-after.ll b/test/CodeGen/Generic/stop-after.ll index 791378c3737d..07a60f7381ab 100644 --- a/test/CodeGen/Generic/stop-after.ll +++ b/test/CodeGen/Generic/stop-after.ll @@ -6,6 +6,6 @@ ; STOP-NEXT: Machine Function Analysis ; STOP-NEXT: MIR Printing Pass -; START: -machine-branch-prob -gc-lowering +; START: -machine-branch-prob -pre-isel-intrinsic-lowering ; START: FunctionPass Manager ; START-NEXT: Lower Garbage Collection Instructions diff --git a/test/CodeGen/Generic/vector-redux.ll b/test/CodeGen/Generic/vector-redux.ll new file mode 100644 index 000000000000..8efdbf85b8c0 --- /dev/null +++ b/test/CodeGen/Generic/vector-redux.ll @@ -0,0 +1,237 @@ +; RUN: llc < %s -debug-only=isel -o /dev/null 2>&1 | FileCheck %s +; REQUIRES: asserts + +@a = global [1024 x i32] zeroinitializer, align 16 + +define i32 @reduce_add() { +; CHECK-LABEL: reduce_add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add +; CHECK: Detected a reduction operation: {{.*}} add + +min.iters.checked: + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %min.iters.checked ], [ %index.next.4, %vector.body ] + %vec.phi = phi <4 x i32> [ zeroinitializer, %min.iters.checked ], [ %28, %vector.body ] + %vec.phi4 = phi <4 x i32> [ zeroinitializer, %min.iters.checked ], [ %29, %vector.body ] + %0 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load = load <4 x i32>, <4 x i32>* %1, align 16 + %2 = getelementptr i32, i32* %0, i64 4 + %3 = bitcast i32* %2 to <4 x i32>* + %wide.load5 = load <4 x i32>, <4 x i32>* %3, align 16 + %4 = add nsw <4 x i32> %wide.load, %vec.phi + %5 = add nsw <4 x i32> %wide.load5, %vec.phi4 + %index.next = add nuw nsw i64 %index, 8 + %6 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next + %7 = bitcast i32* %6 to <4 x i32>* + %wide.load.1 = load <4 x i32>, <4 x i32>* %7, align 16 + %8 = getelementptr i32, i32* %6, i64 4 + %9 = bitcast i32* %8 to <4 x i32>* + %wide.load5.1 = load <4 x i32>, <4 x i32>* %9, align 16 + %10 = add nsw <4 x i32> %wide.load.1, %4 + %11 = add nsw <4 x i32> %wide.load5.1, %5 + %index.next.1 = add nsw i64 %index, 16 + %12 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.1 + %13 = bitcast i32* %12 to <4 x i32>* + %wide.load.2 = load <4 x i32>, <4 x i32>* %13, align 16 + %14 = getelementptr i32, i32* %12, i64 4 + %15 = bitcast i32* %14 to <4 x i32>* + %wide.load5.2 = load <4 x i32>, <4 x i32>* %15, align 16 + %16 = add nsw <4 x i32> %wide.load.2, %10 + %17 = add nsw <4 x i32> %wide.load5.2, %11 + %index.next.2 = add nsw i64 %index, 24 + %18 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.2 + %19 = bitcast i32* %18 to <4 x i32>* + %wide.load.3 = load <4 x i32>, <4 x i32>* %19, align 16 + %20 = getelementptr i32, i32* %18, i64 4 + %21 = bitcast i32* %20 to <4 x i32>* + %wide.load5.3 = load <4 x i32>, <4 x i32>* %21, align 16 + %22 = add nsw <4 x i32> %wide.load.3, %16 + %23 = add nsw <4 x i32> %wide.load5.3, %17 + %index.next.3 = add nsw i64 %index, 32 + %24 = getelementptr inbounds [1024 x i32], [1024 x i32]* @a, i64 0, i64 %index.next.3 + %25 = bitcast i32* %24 to <4 x i32>* + %wide.load.4 = load <4 x i32>, <4 x i32>* %25, align 16 + %26 = getelementptr i32, i32* %24, i64 4 + %27 = bitcast i32* %26 to <4 x i32>* + %wide.load5.4 = load <4 x i32>, <4 x i32>* %27, align 16 + %28 = add nsw <4 x i32> %wide.load.4, %22 + %29 = add nsw <4 x i32> %wide.load5.4, %23 + %index.next.4 = add nsw i64 %index, 40 + %30 = icmp eq i64 %index.next.4, 1000 + br i1 %30, label %middle.block, label %vector.body + +middle.block: + %.lcssa10 = phi <4 x i32> [ %29, %vector.body ] + %.lcssa = phi <4 x i32> [ %28, %vector.body ] + %bin.rdx = add <4 x i32> %.lcssa10, %.lcssa + %rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> + %bin.rdx6 = add <4 x i32> %bin.rdx, %rdx.shuf + %rdx.shuf7 = shufflevector <4 x i32> %bin.rdx6, <4 x i32> undef, <4 x i32> + %bin.rdx8 = add <4 x i32> %bin.rdx6, %rdx.shuf7 + %31 = extractelement <4 x i32> %bin.rdx8, i32 0 + ret i32 %31 +} + +define i32 @reduce_and() { +; CHECK-LABEL: reduce_and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and +; CHECK: Detected a reduction operation: {{.*}} and + +entry: + br label %vector.body + +vector.body: + %lsr.iv = phi i64 [ %lsr.iv.next, %vector.body ], [ -4096, %entry ] + %vec.phi = phi <4 x i32> [ , %entry ], [ %6, %vector.body ] + %vec.phi9 = phi <4 x i32> [ , %entry ], [ %7, %vector.body ] + %uglygep33 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep3334 = bitcast i8* %uglygep33 to <4 x i32>* + %scevgep35 = getelementptr <4 x i32>, <4 x i32>* %uglygep3334, i64 256 + %wide.load = load <4 x i32>, <4 x i32>* %scevgep35, align 16 + %scevgep36 = getelementptr <4 x i32>, <4 x i32>* %uglygep3334, i64 257 + %wide.load10 = load <4 x i32>, <4 x i32>* %scevgep36, align 16 + %0 = and <4 x i32> %wide.load, %vec.phi + %1 = and <4 x i32> %wide.load10, %vec.phi9 + %uglygep30 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep3031 = bitcast i8* %uglygep30 to <4 x i32>* + %scevgep32 = getelementptr <4 x i32>, <4 x i32>* %uglygep3031, i64 258 + %wide.load.1 = load <4 x i32>, <4 x i32>* %scevgep32, align 16 + %uglygep27 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep2728 = bitcast i8* %uglygep27 to <4 x i32>* + %scevgep29 = getelementptr <4 x i32>, <4 x i32>* %uglygep2728, i64 259 + %wide.load10.1 = load <4 x i32>, <4 x i32>* %scevgep29, align 16 + %2 = and <4 x i32> %wide.load.1, %0 + %3 = and <4 x i32> %wide.load10.1, %1 + %uglygep24 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep2425 = bitcast i8* %uglygep24 to <4 x i32>* + %scevgep26 = getelementptr <4 x i32>, <4 x i32>* %uglygep2425, i64 260 + %wide.load.2 = load <4 x i32>, <4 x i32>* %scevgep26, align 16 + %uglygep21 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep2122 = bitcast i8* %uglygep21 to <4 x i32>* + %scevgep23 = getelementptr <4 x i32>, <4 x i32>* %uglygep2122, i64 261 + %wide.load10.2 = load <4 x i32>, <4 x i32>* %scevgep23, align 16 + %4 = and <4 x i32> %wide.load.2, %2 + %5 = and <4 x i32> %wide.load10.2, %3 + %uglygep18 = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep1819 = bitcast i8* %uglygep18 to <4 x i32>* + %scevgep20 = getelementptr <4 x i32>, <4 x i32>* %uglygep1819, i64 262 + %wide.load.3 = load <4 x i32>, <4 x i32>* %scevgep20, align 16 + %uglygep = getelementptr i8, i8* bitcast ([1024 x i32]* @a to i8*), i64 %lsr.iv + %uglygep17 = bitcast i8* %uglygep to <4 x i32>* + %scevgep = getelementptr <4 x i32>, <4 x i32>* %uglygep17, i64 263 + %wide.load10.3 = load <4 x i32>, <4 x i32>* %scevgep, align 16 + %6 = and <4 x i32> %wide.load.3, %4 + %7 = and <4 x i32> %wide.load10.3, %5 + %lsr.iv.next = add nsw i64 %lsr.iv, 128 + %8 = icmp eq i64 %lsr.iv.next, 0 + br i1 %8, label %middle.block, label %vector.body + +middle.block: + %bin.rdx = and <4 x i32> %7, %6 + %rdx.shuf = shufflevector <4 x i32> %bin.rdx, <4 x i32> undef, <4 x i32> + %bin.rdx11 = and <4 x i32> %bin.rdx, %rdx.shuf + %rdx.shuf12 = shufflevector <4 x i32> %bin.rdx11, <4 x i32> undef, <4 x i32> + %bin.rdx13 = and <4 x i32> %bin.rdx11, %rdx.shuf12 + %9 = extractelement <4 x i32> %bin.rdx13, i32 0 + ret i32 %9 +} + +define float @reduce_add_float(float* nocapture readonly %a) { +; CHECK-LABEL: reduce_add_float +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; CHECK: Detected a reduction operation: {{.*}} fadd fast +; +entry: + br label %vector.body + +vector.body: + %index = phi i64 [ 0, %entry ], [ %index.next.4, %vector.body ] + %vec.phi = phi <4 x float> [ zeroinitializer, %entry ], [ %28, %vector.body ] + %vec.phi9 = phi <4 x float> [ zeroinitializer, %entry ], [ %29, %vector.body ] + %0 = getelementptr inbounds float, float* %a, i64 %index + %1 = bitcast float* %0 to <4 x float>* + %wide.load = load <4 x float>, <4 x float>* %1, align 4 + %2 = getelementptr float, float* %0, i64 4 + %3 = bitcast float* %2 to <4 x float>* + %wide.load10 = load <4 x float>, <4 x float>* %3, align 4 + %4 = fadd fast <4 x float> %wide.load, %vec.phi + %5 = fadd fast <4 x float> %wide.load10, %vec.phi9 + %index.next = add nuw nsw i64 %index, 8 + %6 = getelementptr inbounds float, float* %a, i64 %index.next + %7 = bitcast float* %6 to <4 x float>* + %wide.load.1 = load <4 x float>, <4 x float>* %7, align 4 + %8 = getelementptr float, float* %6, i64 4 + %9 = bitcast float* %8 to <4 x float>* + %wide.load10.1 = load <4 x float>, <4 x float>* %9, align 4 + %10 = fadd fast <4 x float> %wide.load.1, %4 + %11 = fadd fast <4 x float> %wide.load10.1, %5 + %index.next.1 = add nsw i64 %index, 16 + %12 = getelementptr inbounds float, float* %a, i64 %index.next.1 + %13 = bitcast float* %12 to <4 x float>* + %wide.load.2 = load <4 x float>, <4 x float>* %13, align 4 + %14 = getelementptr float, float* %12, i64 4 + %15 = bitcast float* %14 to <4 x float>* + %wide.load10.2 = load <4 x float>, <4 x float>* %15, align 4 + %16 = fadd fast <4 x float> %wide.load.2, %10 + %17 = fadd fast <4 x float> %wide.load10.2, %11 + %index.next.2 = add nsw i64 %index, 24 + %18 = getelementptr inbounds float, float* %a, i64 %index.next.2 + %19 = bitcast float* %18 to <4 x float>* + %wide.load.3 = load <4 x float>, <4 x float>* %19, align 4 + %20 = getelementptr float, float* %18, i64 4 + %21 = bitcast float* %20 to <4 x float>* + %wide.load10.3 = load <4 x float>, <4 x float>* %21, align 4 + %22 = fadd fast <4 x float> %wide.load.3, %16 + %23 = fadd fast <4 x float> %wide.load10.3, %17 + %index.next.3 = add nsw i64 %index, 32 + %24 = getelementptr inbounds float, float* %a, i64 %index.next.3 + %25 = bitcast float* %24 to <4 x float>* + %wide.load.4 = load <4 x float>, <4 x float>* %25, align 4 + %26 = getelementptr float, float* %24, i64 4 + %27 = bitcast float* %26 to <4 x float>* + %wide.load10.4 = load <4 x float>, <4 x float>* %27, align 4 + %28 = fadd fast <4 x float> %wide.load.4, %22 + %29 = fadd fast <4 x float> %wide.load10.4, %23 + %index.next.4 = add nsw i64 %index, 40 + %30 = icmp eq i64 %index.next.4, 1000 + br i1 %30, label %middle.block, label %vector.body + +middle.block: + %.lcssa15 = phi <4 x float> [ %29, %vector.body ] + %.lcssa = phi <4 x float> [ %28, %vector.body ] + %bin.rdx = fadd fast <4 x float> %.lcssa15, %.lcssa + %rdx.shuf = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> + %bin.rdx11 = fadd fast <4 x float> %bin.rdx, %rdx.shuf + %rdx.shuf12 = shufflevector <4 x float> %bin.rdx11, <4 x float> undef, <4 x i32> + %bin.rdx13 = fadd fast <4 x float> %bin.rdx11, %rdx.shuf12 + %31 = extractelement <4 x float> %bin.rdx13, i32 0 + ret float %31 +} diff --git a/test/CodeGen/Hexagon/Atomics.ll b/test/CodeGen/Hexagon/Atomics.ll index bbac5d73c868..cedf9a48754b 100644 --- a/test/CodeGen/Hexagon/Atomics.ll +++ b/test/CodeGen/Hexagon/Atomics.ll @@ -69,3 +69,16 @@ entry: return: ; preds = %entry ret void } + + +define i64 @fred() nounwind { +entry: + %s0 = cmpxchg i32* undef, i32 undef, i32 undef seq_cst seq_cst + %s1 = extractvalue { i32, i1 } %s0, 0 + %t0 = cmpxchg i64* undef, i64 undef, i64 undef seq_cst seq_cst + %t1 = extractvalue { i64, i1 } %t0, 0 + %u0 = zext i32 %s1 to i64 + %u1 = add i64 %u0, %t1 + ret i64 %u1 +} + diff --git a/test/CodeGen/Hexagon/absaddr-store.ll b/test/CodeGen/Hexagon/absaddr-store.ll index f4e97d22e7d2..dac8607d88db 100644 --- a/test/CodeGen/Hexagon/absaddr-store.ll +++ b/test/CodeGen/Hexagon/absaddr-store.ll @@ -1,6 +1,5 @@ ; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s ; Check that we generate load instructions with absolute addressing mode. -; XFAIL: * @a0 = external global i32 @a1 = external global i32 diff --git a/test/CodeGen/Hexagon/adde.ll b/test/CodeGen/Hexagon/adde.ll index 4a88914dc6cb..43ddb4307ef2 100644 --- a/test/CodeGen/Hexagon/adde.ll +++ b/test/CodeGen/Hexagon/adde.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1) ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0) diff --git a/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll b/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll new file mode 100644 index 000000000000..561013b174dd --- /dev/null +++ b/test/CodeGen/Hexagon/avoid-predspill-calleesaved.ll @@ -0,0 +1,49 @@ +; Check that a callee-saved register will be saved correctly if +; the predicate-to-GPR spilling code uses it. +; +; RUN: llc -march=hexagon < %s | FileCheck %s +; +; We expect to spill p0 into a general-purpose register and keep it there, +; without adding an extra spill of that register. +; +; CHECK: PredSpill: +; CHECK: memd(r29{{.*}}) = r17:16 +; CHECK-DAG: r{{[0-9]+}} = p0 +; CHECK-DAG: p0 = r{{[0-9]+}} +; CHECK-NOT: = memw(r29 +; + +define void @PredSpill() { +entry: + br i1 undef, label %if.then, label %if.else.14 + +if.then: ; preds = %entry + br i1 undef, label %if.end.57, label %if.else + +if.else: ; preds = %if.then + unreachable + +if.else.14: ; preds = %entry + br i1 undef, label %if.then.17, label %if.end.57 + +if.then.17: ; preds = %if.else.14 + br i1 undef, label %if.end.57, label %if.then.20 + +if.then.20: ; preds = %if.then.17 + %call21 = tail call i32 @myfun() + %tobool22 = icmp eq i32 %call21, 0 + %0 = tail call i32 @myfun() + br i1 %tobool22, label %if.else.42, label %if.then.23 + +if.then.23: ; preds = %if.then.20 + unreachable + +if.else.42: ; preds = %if.then.20 + ret void + +if.end.57: ; preds = %if.then.17, %if.else.14, %if.then + ret void +} + +declare i32 @myfun() + diff --git a/test/CodeGen/Hexagon/avoid-predspill.ll b/test/CodeGen/Hexagon/avoid-predspill.ll new file mode 100644 index 000000000000..159c149c4422 --- /dev/null +++ b/test/CodeGen/Hexagon/avoid-predspill.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; +; This checks that predicate registers are moved to GPRs instead of spilling +; where possible. + +; CHECK: p0 = +; CHECK-NOT: memw(r29 + +define i32 @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { +entry: + %cmp = icmp eq i32 %a, 1 + %cmp1 = icmp eq i32 %b, 2 + %or.cond = and i1 %cmp, %cmp1 + %cmp3 = icmp eq i32 %c, 3 + %or.cond30 = and i1 %or.cond, %cmp3 + %cmp5 = icmp eq i32 %d, 4 + %or.cond31 = and i1 %or.cond30, %cmp5 + %cmp7 = icmp eq i32 %e, 5 + %or.cond32 = and i1 %or.cond31, %cmp7 + %ret.0 = zext i1 %or.cond32 to i32 + %cmp8 = icmp eq i32 %a, 3 + %cmp10 = icmp eq i32 %b, 4 + %or.cond33 = and i1 %cmp8, %cmp10 + %cmp12 = icmp eq i32 %c, 5 + %or.cond34 = and i1 %or.cond33, %cmp12 + %cmp14 = icmp eq i32 %d, 6 + %or.cond35 = and i1 %or.cond34, %cmp14 + %cmp16 = icmp eq i32 %e, 7 + %or.cond36 = and i1 %or.cond35, %cmp16 + %ret.1 = select i1 %or.cond36, i32 2, i32 %ret.0 + %cmp21 = icmp eq i32 %b, 8 + %or.cond37 = and i1 %cmp, %cmp21 + %cmp23 = icmp eq i32 %c, 2 + %or.cond38 = and i1 %or.cond37, %cmp23 + %cmp25 = icmp eq i32 %d, 1 + %or.cond39 = and i1 %or.cond38, %cmp25 + %cmp27 = icmp eq i32 %e, 3 + %or.cond40 = and i1 %or.cond39, %cmp27 + %ret.2 = select i1 %or.cond40, i32 3, i32 %ret.1 + ret i32 %ret.2 +} + diff --git a/test/CodeGen/Hexagon/bit-extractu-half.ll b/test/CodeGen/Hexagon/bit-extractu-half.ll new file mode 100644 index 000000000000..fec4a02d9269 --- /dev/null +++ b/test/CodeGen/Hexagon/bit-extractu-half.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Pick lsr (in bit-simplification) for extracting high halfword. +; CHECK: lsr{{.*}}#16 + +define i32 @foo(i32 %x) #0 { + %a = call i32 @llvm.hexagon.S2.extractu(i32 %x, i32 16, i32 16) + ret i32 %a +} + +declare i32 @llvm.hexagon.S2.extractu(i32, i32, i32) #0 + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/Hexagon/bitconvert-vector.ll b/test/CodeGen/Hexagon/bitconvert-vector.ll new file mode 100644 index 000000000000..c090721b8fff --- /dev/null +++ b/test/CodeGen/Hexagon/bitconvert-vector.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; This testcase would fail on a bitcast from v64i16 to v32i32. Check that +; is compiles without errors. +; CHECK: valign +; CHECK: vshuff + +target triple = "hexagon" + +declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #0 +declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #0 +declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 + +define void @fred() #1 { +entry: + %t0 = bitcast <64 x i16> zeroinitializer to <32 x i32> + %t1 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> %t0, <32 x i32> undef, i32 2) + %t2 = tail call <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32> undef, <32 x i32> %t1, i32 -2) + %t3 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %t2) + store <64 x i16> zeroinitializer, <64 x i16>* undef, align 128 + store <32 x i32> %t3, <32 x i32>* undef, align 128 + unreachable +} + + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } diff --git a/test/CodeGen/Hexagon/block-addr.ll b/test/CodeGen/Hexagon/block-addr.ll index eda167a67f28..420af2fee1c9 100644 --- a/test/CodeGen/Hexagon/block-addr.ll +++ b/test/CodeGen/Hexagon/block-addr.ll @@ -3,7 +3,7 @@ ; Allow combine(..##JTI..): ; CHECK: r{{[0-9]+}}{{.*}} = {{.*}}#.LJTI ; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+<<#[0-9]+}}) -; CHECK: jumpr r{{[0-9]+}} +; CHECK: jumpr:nt r{{[0-9]+}} define void @main() #0 { entry: diff --git a/test/CodeGen/Hexagon/block-ranges-nodef.ll b/test/CodeGen/Hexagon/block-ranges-nodef.ll new file mode 100644 index 000000000000..aaa365243327 --- /dev/null +++ b/test/CodeGen/Hexagon/block-ranges-nodef.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target triple = "hexagon" + +declare void @foo() #0 + +define hidden fastcc void @fred(i32 %a, i64 %b, i64 %c) unnamed_addr #1 { +entry: + %cmp17 = icmp ne i64 %c, 0 + %conv19 = zext i1 %cmp17 to i64 + %or = or i64 %conv19, %b + store i64 %or, i64* undef, align 8 + br i1 undef, label %if.then44, label %if.end96 + +if.then44: ; preds = %entry + br i1 undef, label %overflow, label %lor.lhs.false + +lor.lhs.false: ; preds = %if.then44 + br i1 undef, label %overflow, label %if.end52 + +if.end52: ; preds = %lor.lhs.false + br i1 undef, label %if.then55, label %if.end96 + +if.then55: ; preds = %if.end52 + %cmp60 = icmp slt i32 %a, 0 + %or.cond = or i1 %cmp60, false + %cmp63 = icmp ule i64 %or, undef + %.cmp63 = or i1 %cmp63, %or.cond + call void @foo() + %or.cond299 = and i1 %.cmp63, undef + br i1 %or.cond299, label %if.then72, label %if.end73 + +if.then72: ; preds = %if.then55 + unreachable + +if.end73: ; preds = %if.then55 + unreachable + +if.end96: ; preds = %if.end52, %entry + br i1 undef, label %if.end102, label %if.then98 + +if.then98: ; preds = %if.end96 + br label %if.end102 + +if.end102: ; preds = %if.then98, %if.end96 + unreachable + +overflow: ; preds = %lor.lhs.false, %if.then44 + ret void +} + +attributes #0 = { noinline norecurse nounwind } +attributes #1 = { noinline nounwind } + diff --git a/test/CodeGen/Hexagon/branch-non-mbb.ll b/test/CodeGen/Hexagon/branch-non-mbb.ll new file mode 100644 index 000000000000..e86ca2ed4023 --- /dev/null +++ b/test/CodeGen/Hexagon/branch-non-mbb.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts +; +; The tail calls to foo and bar are branches with functions as operands, +; instead of basic blocks. Make sure we don't crash on such instructions. + +target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" +target triple = "hexagon" + +%struct.t0 = type { i8, [2 x i8] } +%struct.t1 = type { i8, i8, [1900 x i8], %struct.t0 } + +@var = internal global [3 x %struct.t1] zeroinitializer, align 8 +declare void @foo() #2 +declare void @bar(i32, i32) #2 + +; Function Attrs: nounwind +define void @fred(i8 signext %a, i8 signext %b) #1 { +entry: + %i = sext i8 %a to i32 + %t = getelementptr inbounds [3 x %struct.t1], [3 x %struct.t1]* @var, i32 0, i32 %i, i32 3, i32 0 + %0 = load i8, i8* %t, align 8 + switch i8 %0, label %if.end14 [ + i8 1, label %if.then + i8 0, label %do.body + ] + +if.then: ; preds = %entry + %j = sext i8 %b to i32 + %u = getelementptr inbounds [3 x %struct.t1], [3 x %struct.t1]* @var, i32 0, i32 %i, i32 3, i32 1, i32 %j + store i8 1, i8* %u, align 1 + tail call void @foo() #0 + br label %if.end14 + +do.body: ; preds = %entry + %conv11 = sext i8 %b to i32 + tail call void @bar(i32 %i, i32 %conv11) #0 + br label %if.end14 + +if.end14: ; preds = %entry, %do.body, %if.then + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind "disable-tail-calls"="false" } +attributes #2 = { "disable-tail-calls"="false" } diff --git a/test/CodeGen/Hexagon/brev_ld.ll b/test/CodeGen/Hexagon/brev_ld.ll index 12edb4c2b8f7..a2914296ec41 100644 --- a/test/CodeGen/Hexagon/brev_ld.ll +++ b/test/CodeGen/Hexagon/brev_ld.ll @@ -29,9 +29,9 @@ entry: %1 = bitcast i64* %inputLR to i8* %sub = sub i32 13, %shr1 %shl = shl i32 1, %sub -; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %2 = call i8* @llvm.hexagon.brev.ldd(i8* %0, i8* %1, i32 %shl) - %3 = bitcast i8* %2 to i64* + %3 = bitcast i8* %1 to i64* %4 = load i64, i64* %3, align 8, !tbaa !0 ret i64 %4 } @@ -49,9 +49,9 @@ entry: %1 = bitcast i32* %inputLR to i8* %sub = sub i32 14, %shr1 %shl = shl i32 1, %sub -; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %2 = call i8* @llvm.hexagon.brev.ldw(i8* %0, i8* %1, i32 %shl) - %3 = bitcast i8* %2 to i32* + %3 = bitcast i8* %1 to i32* %4 = load i32, i32* %3, align 4, !tbaa !2 ret i32 %4 } @@ -69,9 +69,9 @@ entry: %1 = bitcast i16* %inputLR to i8* %sub = sub i32 15, %shr1 %shl = shl i32 1, %sub -; CHECK: memh(r{{[0-9]*}} ++ m0:brev) +; CHECK: = memh(r{{[0-9]*}} ++ m0:brev) %2 = call i8* @llvm.hexagon.brev.ldh(i8* %0, i8* %1, i32 %shl) - %3 = bitcast i8* %2 to i16* + %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !3 ret i16 %4 } @@ -89,9 +89,9 @@ entry: %1 = bitcast i16* %inputLR to i8* %sub = sub i32 15, %shr1 %shl = shl i32 1, %sub -; CHECK: memuh(r{{[0-9]*}} ++ m0:brev) +; CHECK: = memuh(r{{[0-9]*}} ++ m0:brev) %2 = call i8* @llvm.hexagon.brev.lduh(i8* %0, i8* %1, i32 %shl) - %3 = bitcast i8* %2 to i16* + %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !3 ret i16 %4 } @@ -108,15 +108,15 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub nsw i32 16, %shr1 %shl = shl i32 1, %sub -; CHECK: memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memub(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %1 = call i8* @llvm.hexagon.brev.ldub(i8* %0, i8* %inputLR, i32 %shl) - %2 = load i8, i8* %1, align 1, !tbaa !0 + %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 } declare i8* @llvm.hexagon.brev.ldub(i8*, i8*, i32) nounwind -define zeroext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +define signext i8 @foo5(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { entry: %inputLR = alloca i8, align 1 %conv = zext i16 %filtMemLen to i32 @@ -126,9 +126,9 @@ entry: %0 = bitcast i16* %arrayidx to i8* %sub = sub nsw i32 16, %shr1 %shl = shl i32 1, %sub -; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) +; CHECK: = memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %1 = call i8* @llvm.hexagon.brev.ldb(i8* %0, i8* %inputLR, i32 %shl) - %2 = load i8, i8* %1, align 1, !tbaa !0 + %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 } diff --git a/test/CodeGen/Hexagon/brev_st.ll b/test/CodeGen/Hexagon/brev_st.ll index b80579185317..6c55681a683b 100644 --- a/test/CodeGen/Hexagon/brev_st.ll +++ b/test/CodeGen/Hexagon/brev_st.ll @@ -28,9 +28,7 @@ entry: %shl = shl i32 1, %sub ; CHECK: memd(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.std(i8* %0, i64 undef, i32 %shl) - %2 = bitcast i8* %1 to i64* - %3 = load i64, i64* %2, align 8, !tbaa !0 - ret i64 %3 + ret i64 0 } declare i8* @llvm.hexagon.brev.std(i8*, i64, i32) nounwind @@ -46,9 +44,7 @@ entry: %shl = shl i32 1, %sub ; CHECK: memw(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.stw(i8* %0, i32 undef, i32 %shl) - %2 = bitcast i8* %1 to i32* - %3 = load i32, i32* %2, align 4, !tbaa !2 - ret i32 %3 + ret i32 0 } declare i8* @llvm.hexagon.brev.stw(i8*, i32, i32) nounwind @@ -64,9 +60,7 @@ entry: %shl = shl i32 1, %sub ; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %1 = tail call i8* @llvm.hexagon.brev.sth(i8* %0, i32 0, i32 %shl) - %2 = bitcast i8* %1 to i16* - %3 = load i16, i16* %2, align 2, !tbaa !3 - ret i16 %3 + ret i16 0 } declare i8* @llvm.hexagon.brev.sth(i8*, i32, i32) nounwind @@ -82,9 +76,7 @@ entry: %shl = shl i32 1, %sub ; CHECK: memh(r{{[0-9]*}} ++ m{{[0-1]}}:brev){{ *}}={{ *}}r{{[0-9]*}}.h %1 = tail call i8* @llvm.hexagon.brev.sthhi(i8* %0, i32 0, i32 %shl) - %2 = bitcast i8* %1 to i16* - %3 = load i16, i16* %2, align 2, !tbaa !3 - ret i16 %3 + ret i16 0 } declare i8* @llvm.hexagon.brev.sthhi(i8*, i32, i32) nounwind @@ -100,8 +92,7 @@ entry: ; CHECK: memb(r{{[0-9]*}} ++ m{{[0-1]}}:brev) %shl = shl i32 1, %sub %1 = tail call i8* @llvm.hexagon.brev.stb(i8* %0, i32 0, i32 %shl) - %2 = load i8, i8* %1, align 1, !tbaa !0 - ret i8 %2 + ret i8 0 } declare i8* @llvm.hexagon.brev.stb(i8*, i32, i32) nounwind diff --git a/test/CodeGen/Hexagon/builtin-prefetch-offset.ll b/test/CodeGen/Hexagon/builtin-prefetch-offset.ll new file mode 100644 index 000000000000..b542308abd3e --- /dev/null +++ b/test/CodeGen/Hexagon/builtin-prefetch-offset.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check for the immediate offset. It must be a multiple of 8. +; CHECK: dcfetch({{.*}}+{{ *}}#8) +; In 6.2 (which supports v4+ only), we generate indexed dcfetch in all cases +; (unlike in 6.1, which supported v2, where dcfetch did not allow an immediate +; offset). +; For expression %2, where the offset is +9, the offset on dcfetch should be +; a multiple of 8, and the offset of 0 is most likely (although not the only +; possible one). Check for #0 anyways, if the test fails with a false +; positive, the second check can be eliminated, or rewritten, and in the +; meantime it can help catch real problems. +; CHECK: dcfetch({{.*}}+{{ *}}#0) +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +define void @foo(i8* %addr) nounwind { +entry: + %addr.addr = alloca i8*, align 4 + store i8* %addr, i8** %addr.addr, align 4 + %0 = load i8*, i8** %addr.addr, align 4 + %1 = getelementptr i8, i8* %0, i32 8 + call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) + %2 = getelementptr i8, i8* %0, i32 9 + call void @llvm.prefetch(i8* %2, i32 0, i32 3, i32 1) + ret void +} + +declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind diff --git a/test/CodeGen/Hexagon/builtin-prefetch.ll b/test/CodeGen/Hexagon/builtin-prefetch.ll new file mode 100644 index 000000000000..ae236645b282 --- /dev/null +++ b/test/CodeGen/Hexagon/builtin-prefetch.ll @@ -0,0 +1,29 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: dcfetch +; CHECK: dcfetch{{.*}}#8 +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind +define zeroext i8 @foo(i8* %addr) #0 { +entry: + %addr.addr = alloca i8*, align 4 + store i8* %addr, i8** %addr.addr, align 4 + %0 = load i8*, i8** %addr.addr, align 4 + call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) + %1 = load i8*, i8** %addr.addr, align 4 + %2 = bitcast i8* %1 to i32* + %3 = load i32, i32* %2, align 4 + %4 = add i32 %3, 8 + %5 = inttoptr i32 %4 to i8* + call void @llvm.hexagon.prefetch(i8* %5) + %6 = load i8, i8* %5 + ret i8 %6 +} + +; Function Attrs: nounwind +declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) #1 +declare void @llvm.hexagon.prefetch(i8* nocapture) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/Hexagon/callr-dep-edge.ll b/test/CodeGen/Hexagon/callr-dep-edge.ll new file mode 100644 index 000000000000..d2c6ae4df62a --- /dev/null +++ b/test/CodeGen/Hexagon/callr-dep-edge.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check that the callr and the load into r0 are not packetized together. + +target triple = "hexagon" + +@fp = common global i32 (...)* null, align 4 + +; CHECK: r0 = memw +; CHECK: { +; CHECK: callr r0 + +; Function Attrs: nounwind +define i32 @foo() #0 { +entry: + %0 = load i32 ()*, i32 ()** bitcast (i32 (...)** @fp to i32 ()**), align 4 + %call = tail call i32 %0() #0 + ret i32 %call +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/Hexagon/cext-check.ll b/test/CodeGen/Hexagon/cext-check.ll index 19b91c5245b2..46e816d15e5f 100644 --- a/test/CodeGen/Hexagon/cext-check.ll +++ b/test/CodeGen/Hexagon/cext-check.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-eif=0 -ifcvt-limit=0 < %s | FileCheck %s ; Check that we constant extended instructions only when necessary. define i32 @cext_test1(i32* %a) nounwind { diff --git a/test/CodeGen/Hexagon/cfi-late.ll b/test/CodeGen/Hexagon/cfi-late.ll index ce38711ae8d7..d24732929adf 100644 --- a/test/CodeGen/Hexagon/cfi-late.ll +++ b/test/CodeGen/Hexagon/cfi-late.ll @@ -41,11 +41,10 @@ attributes #3 = { nounwind } !llvm.module.flags = !{!11, !12} !llvm.ident = !{!13} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (http://llvm.org/git/clang.git 15506a21305e212c406f980ed9b6b1bac785df56)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, subprograms: !3) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.8.0 (http://llvm.org/git/clang.git 15506a21305e212c406f980ed9b6b1bac785df56)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !1 = !DIFile(filename: "cfi-late.c", directory: "/test") !2 = !{} -!3 = !{!4} -!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, variables: !8) +!4 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 3, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !8) !5 = !DISubroutineType(types: !6) !6 = !{!7, !7, !7} !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) diff --git a/test/CodeGen/Hexagon/cfi-offset.ll b/test/CodeGen/Hexagon/cfi-offset.ll new file mode 100644 index 000000000000..100034a0c6c4 --- /dev/null +++ b/test/CodeGen/Hexagon/cfi-offset.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check that all the offsets in the .cfi_offset instructions are negative. +; They are all based on R30+8 which points to the pair FP/LR stored by an +; allocframe. Since the stack grows towards negative addresses, anything +; in the current stack frame will have a negative offset with respect to +; R30+8. + +; CHECK: cfi_def_cfa r30 +; CHECK-NOT: .cfi_offset r{{[0-9]+}}, {{[^-]}} + +target triple = "hexagon" + +define i64 @_Z3fooxxx(i64 %x, i64 %y, i64 %z) #0 personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +entry: + %call = invoke i64 @_Z3barxxx(i64 %x, i64 %y, i64 %z) + to label %try.cont unwind label %lpad + +lpad: ; preds = %entry + %0 = landingpad { i8*, i32 } + catch i8* null + %1 = extractvalue { i8*, i32 } %0, 0 + %2 = tail call i8* @__cxa_begin_catch(i8* %1) #1 + tail call void @__cxa_end_catch() + br label %try.cont + +try.cont: ; preds = %entry, %lpad + %a.0 = phi i64 [ 0, %lpad ], [ %call, %entry ] + %mul = mul nsw i64 %y, %x + %sub = sub i64 %mul, %z + %add = add nsw i64 %sub, %a.0 + ret i64 %add +} + +declare i64 @_Z3barxxx(i64, i64, i64) #0 + +declare i32 @__gxx_personality_v0(...) + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } diff --git a/test/CodeGen/Hexagon/circ-load-isel.ll b/test/CodeGen/Hexagon/circ-load-isel.ll new file mode 100644 index 000000000000..576fbdf53cfc --- /dev/null +++ b/test/CodeGen/Hexagon/circ-load-isel.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: = memw{{.*}}circ + +target triple = "hexagon" + +@l = external global i32, align 4 + +; Function Attrs: nounwind optsize +define void @circ2() #0 { +entry: + store i32 0, i32* @l, align 4 + %0 = tail call i8* @llvm.hexagon.circ.ldw(i8* undef, i8* undef, i32 150995968, i32 4) + unreachable +} + +declare i8* @llvm.hexagon.circ.ldw(i8*, i8*, i32, i32) #1 +attributes #0 = { nounwind optsize } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/Hexagon/circ_ld.ll b/test/CodeGen/Hexagon/circ_ld.ll index 6d372403ca7a..ffa5f2cd2220 100644 --- a/test/CodeGen/Hexagon/circ_ld.ll +++ b/test/CodeGen/Hexagon/circ_ld.ll @@ -17,7 +17,7 @@ target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" -define zeroext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { +define signext i8 @foo1(i16 zeroext %filtMemLen, i16* %filtMemLR, i16 signext %filtMemIndex) nounwind { entry: %inputLR = alloca i8, align 1 %conv = zext i16 %filtMemLen to i32 @@ -26,9 +26,9 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr1, 33554432 -; CHECK: memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) +; CHECK: = memb(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) %1 = call i8* @llvm.hexagon.circ.ldb(i8* %0, i8* %inputLR, i32 %or, i32 -1) - %2 = load i8, i8* %1, align 1, !tbaa !0 + %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 } @@ -45,9 +45,9 @@ entry: %1 = bitcast i64* %inputLR to i8* %shl = shl nuw nsw i32 %shr1, 3 %or = or i32 %shl, 83886080 -; CHECK: memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}})) +; CHECK: = memd(r{{[0-9]*.}}++{{.}}#-8:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldd(i8* %0, i8* %1, i32 %or, i32 -8) - %3 = bitcast i8* %2 to i64* + %3 = bitcast i8* %1 to i64* %4 = load i64, i64* %3, align 8, !tbaa !0 ret i64 %4 } @@ -64,9 +64,9 @@ entry: %0 = bitcast i16* %arrayidx to i8* %1 = bitcast i16* %inputLR to i8* %or = or i32 %shr1, 50331648 -; CHECK: memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) +; CHECK: = memh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldh(i8* %0, i8* %1, i32 %or, i32 -2) - %3 = bitcast i8* %2 to i16* + %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !2 ret i16 %4 } @@ -82,9 +82,9 @@ entry: %arrayidx = getelementptr inbounds i16, i16* %filtMemLR, i32 %idxprom %0 = bitcast i16* %arrayidx to i8* %or = or i32 %shr1, 33554432 -; CHECK: memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) +; CHECK: = memub(r{{[0-9]*.}}++{{.}}#-1:circ(m{{[0-1]}})) %1 = call i8* @llvm.hexagon.circ.ldub(i8* %0, i8* %inputLR, i32 %or, i32 -1) - %2 = load i8, i8* %1, align 1, !tbaa !0 + %2 = load i8, i8* %inputLR, align 1, !tbaa !0 ret i8 %2 } @@ -100,9 +100,9 @@ entry: %0 = bitcast i16* %arrayidx to i8* %1 = bitcast i16* %inputLR to i8* %or = or i32 %shr1, 50331648 -; CHECK: memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) +; CHECK: = memuh(r{{[0-9]*.}}++{{.}}#-2:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.lduh(i8* %0, i8* %1, i32 %or, i32 -2) - %3 = bitcast i8* %2 to i16* + %3 = bitcast i8* %1 to i16* %4 = load i16, i16* %3, align 2, !tbaa !2 ret i16 %4 } @@ -120,9 +120,9 @@ entry: %1 = bitcast i32* %inputLR to i8* %shl = shl nuw nsw i32 %shr1, 2 %or = or i32 %shl, 67108864 -; CHECK: memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}})) +; CHECK: = memw(r{{[0-9]*.}}++{{.}}#-4:circ(m{{[0-1]}})) %2 = call i8* @llvm.hexagon.circ.ldw(i8* %0, i8* %1, i32 %or, i32 -4) - %3 = bitcast i8* %2 to i32* + %3 = bitcast i8* %1 to i32* %4 = load i32, i32* %3, align 4, !tbaa !3 ret i32 %4 } diff --git a/test/CodeGen/Hexagon/circ_st.ll b/test/CodeGen/Hexagon/circ_st.ll index 244ca3bae714..4b54afbc611d 100644 --- a/test/CodeGen/Hexagon/circ_st.ll +++ b/test/CodeGen/Hexagon/circ_st.ll @@ -12,7 +12,6 @@ ; memh(r1++#-2:circ(m0)) = r3.h ; memw(r1++#-4:circ(m0)) = r0 -; ModuleID = 'circ_st.i' target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" target triple = "hexagon" @@ -26,8 +25,7 @@ entry: %or = or i32 %shr2, 33554432 ; CHECK: memb(r{{[0-9]*}}{{.}}++{{.}}#-1:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.stb(i8* %0, i32 0, i32 %or, i32 -1) - %2 = load i8, i8* %1, align 1, !tbaa !0 - ret i8 %2 + ret i8 0 } declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) nounwind @@ -43,9 +41,7 @@ entry: %or = or i32 %shl, 83886080 ; CHECK: memd(r{{[0-9]*}}{{.}}++{{.}}#-8:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.std(i8* %0, i64 undef, i32 %or, i32 -8) - %2 = bitcast i8* %1 to i64* - %3 = load i64, i64* %2, align 8, !tbaa !0 - ret i64 %3 + ret i64 0 } declare i8* @llvm.hexagon.circ.std(i8*, i64, i32, i32) nounwind @@ -60,9 +56,7 @@ entry: %or = or i32 %shr2, 50331648 ; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.sth(i8* %0, i32 0, i32 %or, i32 -2) - %2 = bitcast i8* %1 to i16* - %3 = load i16, i16* %2, align 2, !tbaa !2 - ret i16 %3 + ret i16 0 } declare i8* @llvm.hexagon.circ.sth(i8*, i32, i32, i32) nounwind @@ -77,9 +71,7 @@ entry: %or = or i32 %shr2, 50331648 ; CHECK: memh(r{{[0-9]*}}{{.}}++{{.}}#-2:circ(m{{[0-1]}})){{ *}}={{ *}}r{{[0-9]*}}.h %1 = tail call i8* @llvm.hexagon.circ.sthhi(i8* %0, i32 0, i32 %or, i32 -2) - %2 = bitcast i8* %1 to i16* - %3 = load i16, i16* %2, align 2, !tbaa !2 - ret i16 %3 + ret i16 0 } declare i8* @llvm.hexagon.circ.sthhi(i8*, i32, i32, i32) nounwind @@ -95,9 +87,7 @@ entry: %or = or i32 %shl, 67108864 ; CHECK: memw(r{{[0-9]*}}{{.}}++{{.}}#-4:circ(m{{[0-1]}})) %1 = tail call i8* @llvm.hexagon.circ.stw(i8* %0, i32 undef, i32 %or, i32 -4) - %2 = bitcast i8* %1 to i32* - %3 = load i32, i32* %2, align 4, !tbaa !3 - ret i32 %3 + ret i32 0 } declare i8* @llvm.hexagon.circ.stw(i8*, i32, i32, i32) nounwind diff --git a/test/CodeGen/Hexagon/clr_set_toggle.ll b/test/CodeGen/Hexagon/clr_set_toggle.ll index 4e90f3d99a1e..19e3ed0cf897 100644 --- a/test/CodeGen/Hexagon/clr_set_toggle.ll +++ b/test/CodeGen/Hexagon/clr_set_toggle.ll @@ -3,6 +3,7 @@ define i32 @my_clrbit(i32 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 @@ -13,6 +14,7 @@ entry: define i64 @my_clrbit2(i64 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit2 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -23,6 +25,7 @@ entry: define i64 @my_clrbit3(i64 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit3 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #31) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -33,6 +36,7 @@ entry: define i32 @my_clrbit4(i32 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit4 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 @@ -43,6 +47,7 @@ entry: define i64 @my_clrbit5(i64 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit5 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -53,6 +58,7 @@ entry: define i64 @my_clrbit6(i64 %x) nounwind { entry: +; CHECK-LABEL: my_clrbit6 ; CHECK: r{{[0-9]+}} = clrbit(r{{[0-9]+}}, #27) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -63,7 +69,8 @@ entry: define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind { entry: -; CHECK: memh(r{{[0-9]+}}+#0){{ *}}={{ *}}setbit(#15) +; CHECK-LABEL: my_setbit +; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}){{ *}}={{ *}}setbit(#15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 %0 = load i16, i16* %crc.addr, align 2 @@ -77,6 +84,7 @@ entry: define i32 @my_setbit2(i32 %x) nounwind { entry: +; CHECK-LABEL: my_setbit2 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 @@ -87,6 +95,7 @@ entry: define i64 @my_setbit3(i64 %x) nounwind { entry: +; CHECK-LABEL: my_setbit3 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -97,6 +106,7 @@ entry: define i32 @my_setbit4(i32 %x) nounwind { entry: +; CHECK-LABEL: my_setbit4 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #31) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 @@ -107,6 +117,7 @@ entry: define i64 @my_setbit5(i64 %x) nounwind { entry: +; CHECK-LABEL: my_setbit5 ; CHECK: r{{[0-9]+}}{{ *}}={{ *}}setbit(r{{[0-9]+}}, #13) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -117,6 +128,7 @@ entry: define zeroext i16 @my_togglebit(i16 zeroext %crc) nounwind { entry: +; CHECK-LABEL: my_togglebit ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) %crc.addr = alloca i16, align 2 store i16 %crc, i16* %crc.addr, align 2 @@ -131,6 +143,7 @@ entry: define i32 @my_togglebit2(i32 %x) nounwind { entry: +; CHECK-LABEL: my_togglebit2 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) %x.addr = alloca i32, align 4 store i32 %x, i32* %x.addr, align 4 @@ -141,6 +154,7 @@ entry: define i64 @my_togglebit3(i64 %x) nounwind { entry: +; CHECK-LABEL: my_togglebit3 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #15) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 @@ -151,6 +165,7 @@ entry: define i64 @my_togglebit4(i64 %x) nounwind { entry: +; CHECK-LABEL: my_togglebit4 ; CHECK: r{{[0-9]+}} = togglebit(r{{[0-9]+}}, #20) %x.addr = alloca i64, align 8 store i64 %x, i64* %x.addr, align 8 diff --git a/test/CodeGen/Hexagon/const64.ll b/test/CodeGen/Hexagon/const64.ll new file mode 100644 index 000000000000..018157d97024 --- /dev/null +++ b/test/CodeGen/Hexagon/const64.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon -disable-const64=0 < %s | FileCheck %s +; RUN: llc -march=hexagon -disable-const64=1 < %s | FileCheck %s --check-prefix=CHECKOLD + +; CHECK: CONST64 +; CHECKOLD-NOT: CONST64 + +target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind +define void @foo() optsize { +entry: + call void @bar(i32 32768, i32 32768, i8 zeroext 1) + ret void +} + +declare void @bar(i32, i32, i8 zeroext) + diff --git a/test/CodeGen/Hexagon/csr-func-usedef.ll b/test/CodeGen/Hexagon/csr-func-usedef.ll new file mode 100644 index 000000000000..a9f81b9f521a --- /dev/null +++ b/test/CodeGen/Hexagon/csr-func-usedef.ll @@ -0,0 +1,72 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target triple = "hexagon" + +declare i8* @llvm.hexagon.circ.ldb(i8*, i8*, i32, i32) #1 +declare i8* @llvm.hexagon.circ.stb(i8*, i32, i32, i32) #1 + +define zeroext i8 @circular_loop_test10(i8* %A, i8* %B, i32 %x, i32 %y, i32 %z, i32 %w) #0 { +entry: + %element_load0 = alloca i8, align 1 + %element_load2 = alloca i8, align 1 + %element_load3 = alloca i8, align 1 + %element_load5 = alloca i8, align 1 + %or = or i32 %x, 100663296 + %or5 = or i32 %z, 100663296 + %or7 = or i32 %w, 100663296 + br label %for.body + +for.body: ; preds = %for.body, %entry + %p0.082 = phi i8* [ %A, %entry ], [ undef, %for.body ] + %element_load.080 = phi i32 [ 0, %entry ], [ %add18, %for.body ] + %p1.079 = phi i8* [ %B, %entry ], [ %1, %for.body ] + %p2.078 = phi i8* [ undef, %entry ], [ %3, %for.body ] + %p3.077 = phi i8* [ undef, %entry ], [ %4, %for.body ] + %0 = call i8* @llvm.hexagon.circ.ldb(i8* %p0.082, i8* nonnull %element_load0, i32 %or, i32 2) + %1 = call i8* @llvm.hexagon.circ.ldb(i8* %p1.079, i8* nonnull null, i32 0, i32 1) + %2 = call i8* @llvm.hexagon.circ.ldb(i8* %p2.078, i8* nonnull %element_load2, i32 %or5, i32 3) + %3 = call i8* @llvm.hexagon.circ.ldb(i8* %2, i8* nonnull %element_load5, i32 %or5, i32 1) + %4 = call i8* @llvm.hexagon.circ.ldb(i8* %p3.077, i8* nonnull %element_load3, i32 %or7, i32 1) + %5 = load i8, i8* null, align 1 + %conv = zext i8 %5 to i32 + %6 = load i8, i8* %element_load2, align 1 + %conv8 = zext i8 %6 to i32 + %7 = load i8, i8* %element_load3, align 1 + %conv9 = zext i8 %7 to i32 + %8 = load i8, i8* undef, align 1 + %conv11 = zext i8 %8 to i32 + %9 = load i8, i8* %element_load5, align 1 + %conv13 = zext i8 %9 to i32 + %10 = load i8, i8* %element_load0, align 1 + %conv15 = zext i8 %10 to i32 + %conv17 = and i32 %element_load.080, 255 + %add = add nuw nsw i32 %conv, %conv17 + %add10 = add nuw nsw i32 %add, %conv8 + %add12 = add nuw nsw i32 %add10, %conv9 + %add14 = add nuw nsw i32 %add12, %conv11 + %add16 = add nuw nsw i32 %add14, %conv13 + %add18 = add nuw nsw i32 %add16, %conv15 + %exitcond84 = icmp eq i32 undef, 200 + br i1 %exitcond84, label %for.body23, label %for.body + +for.body23: ; preds = %for.body23, %for.body + %11 = call i8* @llvm.hexagon.circ.stb(i8* undef, i32 undef, i32 %or, i32 3) + br i1 undef, label %for.body34, label %for.body23 + +for.body34: ; preds = %for.body34, %for.body23 + %element_load.173 = phi i32 [ %add38, %for.body34 ], [ %add18, %for.body23 ] + %arrayidx35 = getelementptr inbounds i8, i8* %B, i32 0 + %12 = load i8, i8* %arrayidx35, align 1 + %conv36 = zext i8 %12 to i32 + %conv37 = and i32 %element_load.173, 255 + %add38 = add nuw nsw i32 %conv36, %conv37 + br i1 undef, label %for.end42, label %for.body34 + +for.end42: ; preds = %for.body34 + %conv39 = trunc i32 %add38 to i8 + ret i8 %conv39 +} + +attributes #0 = { nounwind optsize } +attributes #1 = { argmemonly nounwind } diff --git a/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/test/CodeGen/Hexagon/eliminate-pred-spill.ll new file mode 100644 index 000000000000..6fb0a3e2658d --- /dev/null +++ b/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -0,0 +1,144 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx-double \ +; RUN: -hexagon-bit=0 < %s | FileCheck %s + +; This spill should be eliminated. +; CHECK-NOT: vmem(r29+#6) + +define void @test(i8* noalias nocapture %key, i8* noalias nocapture %data1) #0 { +entry: + %0 = bitcast i8* %key to <32 x i32>* + %1 = bitcast i8* %data1 to <32 x i32>* + br label %for.body + +for.body: + %pkey.0542 = phi <32 x i32>* [ %0, %entry ], [ null, %for.body ] + %pdata0.0541 = phi <32 x i32>* [ null, %entry ], [ %add.ptr48, %for.body ] + %pdata1.0540 = phi <32 x i32>* [ %1, %entry ], [ %add.ptr49, %for.body ] + %dAccum0.0539 = phi <64 x i32> [ undef, %entry ], [ %86, %for.body ] + %2 = load <32 x i32>, <32 x i32>* %pkey.0542, align 128 + %3 = load <32 x i32>, <32 x i32>* %pdata0.0541, align 128 + %4 = load <32 x i32>, <32 x i32>* undef, align 128 + %arrayidx4 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 2 + %5 = load <32 x i32>, <32 x i32>* %arrayidx4, align 128 + %arrayidx5 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 2 + %6 = load <32 x i32>, <32 x i32>* %arrayidx5, align 128 + %7 = load <32 x i32>, <32 x i32>* null, align 128 + %8 = load <32 x i32>, <32 x i32>* undef, align 128 + %9 = load <32 x i32>, <32 x i32>* null, align 128 + %arrayidx9 = getelementptr inbounds <32 x i32>, <32 x i32>* %pkey.0542, i32 3 + %arrayidx10 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 6 + %10 = load <32 x i32>, <32 x i32>* %arrayidx10, align 128 + %arrayidx12 = getelementptr inbounds <32 x i32>, <32 x i32>* %pkey.0542, i32 4 + %11 = load <32 x i32>, <32 x i32>* %arrayidx12, align 128 + %arrayidx13 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 8 + %arrayidx14 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 8 + %12 = load <32 x i32>, <32 x i32>* %arrayidx14, align 128 + %arrayidx15 = getelementptr inbounds <32 x i32>, <32 x i32>* %pkey.0542, i32 5 + %13 = load <32 x i32>, <32 x i32>* %arrayidx15, align 128 + %arrayidx16 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 10 + %arrayidx17 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 10 + %14 = load <32 x i32>, <32 x i32>* %arrayidx17, align 128 + %arrayidx18 = getelementptr inbounds <32 x i32>, <32 x i32>* %pkey.0542, i32 6 + %15 = load <32 x i32>, <32 x i32>* %arrayidx18, align 128 + %arrayidx19 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 12 + %16 = load <32 x i32>, <32 x i32>* %arrayidx19, align 128 + %arrayidx20 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 12 + %17 = load <32 x i32>, <32 x i32>* %arrayidx20, align 128 + %arrayidx22 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 14 + %18 = load <32 x i32>, <32 x i32>* %arrayidx22, align 128 + %arrayidx23 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 14 + %19 = load <32 x i32>, <32 x i32>* %arrayidx23, align 128 + %20 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %2, <32 x i32> %11) + %21 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %11, <32 x i32> %2) + %22 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %2, <32 x i32> %11) + %23 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> undef, <32 x i32> %3) + %24 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %20, <32 x i32> %12, <32 x i32> undef) + %25 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %7, <32 x i32> %15) + %26 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %15, <32 x i32> %7) + %27 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %7, <32 x i32> %15) + %28 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %16, <32 x i32> %8) + %29 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %8, <32 x i32> %16) + %30 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %17, <32 x i32> %9) + %31 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %25, <32 x i32> %9, <32 x i32> %17) + %32 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %4, <32 x i32> %13) + %33 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> %13, <32 x i32> %4) + %34 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> %4, <32 x i32> %13) + %35 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> undef, <32 x i32> %5) + %36 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> %5, <32 x i32> undef) + %37 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> %14, <32 x i32> %6) + %38 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %32, <32 x i32> %6, <32 x i32> %14) + %39 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> undef) + %40 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> undef, <32 x i32> zeroinitializer) + %41 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> %18, <32 x i32> %10) + %42 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> %10, <32 x i32> %18) + %43 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> %19, <32 x i32> undef) + %44 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> zeroinitializer, <32 x i32> undef, <32 x i32> %19) + %45 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %21, <32 x i32> %26) + %46 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %26, <32 x i32> %21) + %47 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %21, <32 x i32> %26) + %48 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %28, <32 x i32> %23) + %49 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %23, <32 x i32> %28) + %50 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %30, <32 x i32> %24) + %51 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %45, <32 x i32> %24, <32 x i32> %30) + %52 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %22, <32 x i32> %27) + %53 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %52, <32 x i32> %27, <32 x i32> %22) + %54 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %52, <32 x i32> %22, <32 x i32> %27) + %55 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %52, <32 x i32> %29, <32 x i32> undef) + %56 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %52, <32 x i32> undef, <32 x i32> %31) + %57 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %33, <32 x i32> %39) + %58 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %57, <32 x i32> %39, <32 x i32> %33) + %59 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %57, <32 x i32> %33, <32 x i32> %39) + %60 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %57, <32 x i32> %41, <32 x i32> %35) + %61 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %57, <32 x i32> %43, <32 x i32> %37) + %62 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %34, <32 x i32> %40) + %63 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %62, <32 x i32> %42, <32 x i32> %36) + %64 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %62, <32 x i32> %38, <32 x i32> %44) + %65 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %46, <32 x i32> %58) + %66 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %65, <32 x i32> %58, <32 x i32> %46) + %67 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %65, <32 x i32> %60, <32 x i32> %48) + %68 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %65, <32 x i32> %61, <32 x i32> %50) + %69 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %47, <32 x i32> %59) + %70 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %69, <32 x i32> %51, <32 x i32> zeroinitializer) + %71 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %53, <32 x i32> zeroinitializer) + %72 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %71, <32 x i32> %63, <32 x i32> %55) + %73 = tail call <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32> %54, <32 x i32> undef) + %74 = tail call <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1> %73, <32 x i32> %56, <32 x i32> %64) + %75 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> %68, <32 x i32> %67) + %76 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> %70, <32 x i32> undef) + %77 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> zeroinitializer, <32 x i32> %72) + %78 = tail call <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32> %74, <32 x i32> zeroinitializer) + %79 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %dAccum0.0539, <32 x i32> %75, i32 65537) + %80 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %79, <32 x i32> zeroinitializer, i32 65537) + %81 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %80, <32 x i32> zeroinitializer, i32 65537) + %82 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %81, <32 x i32> %76, i32 65537) + %83 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %82, <32 x i32> %77, i32 65537) + %84 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %83, <32 x i32> zeroinitializer, i32 65537) + %85 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %84, <32 x i32> undef, i32 65537) + %86 = tail call <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32> %85, <32 x i32> %78, i32 65537) + store <32 x i32> %66, <32 x i32>* %pkey.0542, align 128 + store <32 x i32> %75, <32 x i32>* %pdata0.0541, align 128 + store <32 x i32> zeroinitializer, <32 x i32>* %arrayidx4, align 128 + store <32 x i32> zeroinitializer, <32 x i32>* undef, align 128 + store <32 x i32> zeroinitializer, <32 x i32>* %arrayidx20, align 128 + store <32 x i32> zeroinitializer, <32 x i32>* null, align 128 + %add.ptr48 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata0.0541, i32 16 + %add.ptr49 = getelementptr inbounds <32 x i32>, <32 x i32>* %pdata1.0540, i32 16 + br i1 false, label %for.end, label %for.body + +for.end: + %87 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %86) + ret void +} + +declare <1024 x i1> @llvm.hexagon.V6.vgtb.128B(<32 x i32>, <32 x i32>) #1 + +declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) #1 + +declare <32 x i32> @llvm.hexagon.V6.vshuffeb.128B(<32 x i32>, <32 x i32>) #1 + +declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) #1 + +declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll b/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll new file mode 100644 index 000000000000..284170b5edb4 --- /dev/null +++ b/test/CodeGen/Hexagon/expand-condsets-pred-undef.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target triple = "hexagon" + +%struct.0 = type { i64, i16 } + +declare void @foo(%struct.0* noalias nocapture sret, i8 zeroext, i32, i64) #0 + +define hidden fastcc void @fred(%struct.0* noalias nocapture %p, i8 zeroext %t, i32 %r) unnamed_addr #0 { +entry: + %. = select i1 undef, i64 549755813888, i64 1024 + %cmp104 = icmp ult i64 undef, %. + %inc = zext i1 %cmp104 to i32 + %inc.r = add nsw i32 %inc, %r + %.inc.r = select i1 undef, i32 0, i32 %inc.r + tail call void @foo(%struct.0* sret %p, i8 zeroext %t, i32 %.inc.r, i64 undef) + ret void +} + +attributes #0 = { noinline nounwind } + diff --git a/test/CodeGen/Hexagon/extload-combine.ll b/test/CodeGen/Hexagon/extload-combine.ll index 773b10b2b288..c492343d7915 100644 --- a/test/CodeGen/Hexagon/extload-combine.ll +++ b/test/CodeGen/Hexagon/extload-combine.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 -O3 -disable-hsdr < %s | FileCheck %s +; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hsdr < %s | FileCheck %s ; Check that the combine/stxw instructions are being generated. ; In case of combine one of the operand should be 0 and another should be ; the output of absolute addressing load instruction. diff --git a/test/CodeGen/Hexagon/gp-plus-offset-load.ll b/test/CodeGen/Hexagon/gp-plus-offset-load.ll index cd1aacc2318a..55edb22f46dc 100644 --- a/test/CodeGen/Hexagon/gp-plus-offset-load.ll +++ b/test/CodeGen/Hexagon/gp-plus-offset-load.ll @@ -21,7 +21,7 @@ if.end: ; preds = %if.then, %entry } define void @loadByte(i32 %val1, i32 %val2, i8* nocapture %ival) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(##foo{{ *}}+{{ *}}1) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(##foo{{ *}}+{{ *}}1) entry: %cmp = icmp sgt i32 %val1, %val2 br i1 %cmp, label %if.then, label %if.end @@ -36,7 +36,7 @@ if.end: ; preds = %if.then, %entry } define void @loadHWord(i32 %val1, i32 %val2, i16* %ival) nounwind { -; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(##foo{{ *}}+{{ *}}2) +; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(##foo{{ *}}+{{ *}}2) entry: %cmp = icmp sgt i32 %val1, %val2 br i1 %cmp, label %if.then, label %if.end diff --git a/test/CodeGen/Hexagon/hwloop-dbg.ll b/test/CodeGen/Hexagon/hwloop-dbg.ll index 341f8db9e336..1e305e30f628 100644 --- a/test/CodeGen/Hexagon/hwloop-dbg.ll +++ b/test/CodeGen/Hexagon/hwloop-dbg.ll @@ -37,10 +37,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!29} -!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", isOptimized: true, emissionKind: 1, file: !28, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2) +!0 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "QuIC LLVM Hexagon Clang version 6.1-pre-unknown, (git://git-hexagon-aus.quicinc.com/llvm/clang-mainline.git e9382867661454cdf44addb39430741578e9765c) (llvm/llvm-mainline.git 36412bb1fcf03ed426d4437b41198bae066675ac)", isOptimized: true, emissionKind: FullDebug, file: !28, enums: !2, retainedTypes: !2, globals: !2) !2 = !{} -!3 = !{!5} -!5 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, scopeLine: 1, file: !28, scope: null, type: !7, variables: !11) +!5 = distinct !DISubprogram(name: "foo", line: 1, isLocal: false, isDefinition: true, virtualIndex: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, scopeLine: 1, file: !28, scope: null, type: !7, variables: !11) !6 = !DIFile(filename: "hwloop-dbg.c", directory: "/usr2/kparzysz/s.hex/t") !7 = !DISubroutineType(types: !8) !8 = !{null, !9, !9} diff --git a/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll b/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll new file mode 100644 index 000000000000..e4bee8354a7c --- /dev/null +++ b/test/CodeGen/Hexagon/ifcvt-diamond-bad.ll @@ -0,0 +1,43 @@ +; RUN: llc -march=hexagon -minimum-jump-tables=1 < %s +; REQUIRES: asserts + +target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" +target triple = "hexagon" + +%struct.t0 = type { i8, [2 x i8] } +%struct.t1 = type { i8, i8, [1900 x i8], %struct.t0 } + +@var = internal global [3 x %struct.t1] zeroinitializer, align 8 +declare void @foo() #2 +declare void @bar(i32, i32) #2 + +; Function Attrs: nounwind +define void @fred(i8 signext %a, i8 signext %b) #1 { +entry: + %i = sext i8 %a to i32 + %t = getelementptr inbounds [3 x %struct.t1], [3 x %struct.t1]* @var, i32 0, i32 %i, i32 3, i32 0 + %0 = load i8, i8* %t, align 8 + switch i8 %0, label %if.end14 [ + i8 1, label %if.then + i8 0, label %do.body + ] + +if.then: ; preds = %entry + %j = sext i8 %b to i32 + %u = getelementptr inbounds [3 x %struct.t1], [3 x %struct.t1]* @var, i32 0, i32 %i, i32 3, i32 1, i32 %j + store i8 1, i8* %u, align 1 + tail call void @foo() #0 + br label %if.end14 + +do.body: ; preds = %entry + %conv11 = sext i8 %b to i32 + tail call void @bar(i32 %i, i32 %conv11) #0 + br label %if.end14 + +if.end14: ; preds = %entry, %do.body, %if.then + ret void +} + +attributes #0 = { nounwind } +attributes #1 = { nounwind "disable-tail-calls"="false" } +attributes #2 = { "disable-tail-calls"="false" } diff --git a/test/CodeGen/Hexagon/inline-asm-qv.ll b/test/CodeGen/Hexagon/inline-asm-qv.ll new file mode 100644 index 000000000000..256342170313 --- /dev/null +++ b/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Check that constraints q and v are handled correctly. +; CHECK: q{{.}} = vgtw(v{{.}}.w,v{{.}}.w) +; CHECK: vand +; CHECK: vmem + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @foo(<16 x i32> %v0, <16 x i32> %v1, <16 x i32>* nocapture %p) #0 { +entry: + %0 = tail call <16 x i32> asm "$0 = vgtw($1.w,$2.w)", "=q,v,v"(<16 x i32> %v0, <16 x i32> %v1) #1 + store <16 x i32> %0, <16 x i32>* %p, align 64 + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/Hexagon/insert4.ll b/test/CodeGen/Hexagon/insert4.ll new file mode 100644 index 000000000000..96c8bba24d7c --- /dev/null +++ b/test/CodeGen/Hexagon/insert4.ll @@ -0,0 +1,112 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check that we are generating insert instructions. +; CHECK: insert +; CHECK: insert +; CHECK: insert +; CHECK: insert + +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +%struct.a = type { i16 } + +define i32 @fun(%struct.a* nocapture %pData, i64 %c, i64* nocapture %d, i64* nocapture %e, i64* nocapture %f) #0 { +entry: + %g = getelementptr inbounds %struct.a, %struct.a* %pData, i32 0, i32 0 + %0 = load i16, i16* %g, align 2, !tbaa !0 + %conv185 = sext i16 %0 to i32 + %shr86 = ashr i32 %conv185, 2 + %cmp87 = icmp sgt i32 %shr86, 0 + br i1 %cmp87, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: ; preds = %entry + %h.sroa.0.0.extract.trunc = trunc i64 %c to i32 + %sext = shl i32 %h.sroa.0.0.extract.trunc, 16 + %conv8 = ashr exact i32 %sext, 16 + %l.sroa.2.4.extract.shift = lshr i64 %c, 32 + %sext76 = ashr i32 %h.sroa.0.0.extract.trunc, 16 + %m.sroa.2.6.extract.shift = lshr i64 %c, 48 + %sext7980 = shl nuw nsw i64 %l.sroa.2.4.extract.shift, 16 + %sext79 = trunc i64 %sext7980 to i32 + %conv38 = ashr exact i32 %sext79, 16 + %sext8283 = shl nuw nsw i64 %m.sroa.2.6.extract.shift, 16 + %sext82 = trunc i64 %sext8283 to i32 + %conv53 = ashr exact i32 %sext82, 16 + br label %for.body + +for.body: ; preds = %for.body.lr.ph, %for.body + %arrayidx.phi = phi i64* [ %d, %for.body.lr.ph ], [ %arrayidx.inc, %for.body ] + %arrayidx30.phi = phi i64* [ %f, %for.body.lr.ph ], [ %arrayidx30.inc, %for.body ] + %arrayidx60.phi = phi i64* [ %e, %for.body.lr.ph ], [ %arrayidx60.inc, %for.body ] + %j.088.pmt = phi i32 [ 0, %for.body.lr.ph ], [ %inc.pmt, %for.body ] + %1 = load i64, i64* %arrayidx.phi, align 8, !tbaa !1 + %n_union3.sroa.0.0.extract.trunc = trunc i64 %1 to i32 + %n_union3.sroa.1.4.extract.shift = lshr i64 %1, 32 + %2 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %n_union3.sroa.0.0.extract.trunc, i32 %conv8) + %3 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %2, i32 -25) + %conv9 = trunc i64 %3 to i32 + %4 = tail call i32 @llvm.hexagon.A2.sath(i32 %conv9) + %n_union13.sroa.1.4.extract.trunc = trunc i64 %n_union3.sroa.1.4.extract.shift to i32 + %5 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %n_union13.sroa.1.4.extract.trunc, i32 %sext76) + %6 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %5, i32 -25) + %conv24 = trunc i64 %6 to i32 + %7 = tail call i32 @llvm.hexagon.A2.sath(i32 %conv24) + %8 = load i64, i64* %arrayidx30.phi, align 8, !tbaa !1 + %n_union28.sroa.0.0.extract.trunc = trunc i64 %8 to i32 + %n_union28.sroa.1.4.extract.shift = lshr i64 %8, 32 + %9 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %n_union28.sroa.0.0.extract.trunc, i32 %conv38) + %10 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %9, i32 -25) + %conv39 = trunc i64 %10 to i32 + %11 = tail call i32 @llvm.hexagon.A2.sath(i32 %conv39) + %n_union43.sroa.1.4.extract.trunc = trunc i64 %n_union28.sroa.1.4.extract.shift to i32 + %12 = tail call i64 @llvm.hexagon.M2.dpmpyss.s0(i32 %n_union43.sroa.1.4.extract.trunc, i32 %conv53) + %13 = tail call i64 @llvm.hexagon.S2.asl.r.p(i64 %12, i32 -25) + %conv54 = trunc i64 %13 to i32 + %14 = tail call i32 @llvm.hexagon.A2.sath(i32 %conv54) + %n_union.sroa.3.6.insert.ext = zext i32 %14 to i64 + %n_union.sroa.3.6.insert.shift = shl i64 %n_union.sroa.3.6.insert.ext, 48 + %conv40.mask = and i32 %11, 65535 + %n_union.sroa.2.4.insert.ext = zext i32 %conv40.mask to i64 + %n_union.sroa.2.4.insert.shift = shl nuw nsw i64 %n_union.sroa.2.4.insert.ext, 32 + %conv25.mask = and i32 %7, 65535 + %n_union.sroa.1.2.insert.ext = zext i32 %conv25.mask to i64 + %n_union.sroa.1.2.insert.shift = shl nuw nsw i64 %n_union.sroa.1.2.insert.ext, 16 + %conv10.mask = and i32 %4, 65535 + %n_union.sroa.0.0.insert.ext = zext i32 %conv10.mask to i64 + %n_union.sroa.2.4.insert.insert = or i64 %n_union.sroa.1.2.insert.shift, %n_union.sroa.0.0.insert.ext + %n_union.sroa.1.2.insert.insert = or i64 %n_union.sroa.2.4.insert.insert, %n_union.sroa.2.4.insert.shift + %n_union.sroa.0.0.insert.insert = or i64 %n_union.sroa.1.2.insert.insert, %n_union.sroa.3.6.insert.shift + %15 = load i64, i64* %arrayidx60.phi, align 8, !tbaa !1 + %16 = tail call i64 @llvm.hexagon.A2.vaddhs(i64 %15, i64 %n_union.sroa.0.0.insert.insert) + store i64 %16, i64* %arrayidx60.phi, align 8, !tbaa !1 + %inc.pmt = add i32 %j.088.pmt, 1 + %17 = load i16, i16* %g, align 2, !tbaa !0 + %conv1 = sext i16 %17 to i32 + %shr = ashr i32 %conv1, 2 + %cmp = icmp slt i32 %inc.pmt, %shr + %arrayidx.inc = getelementptr i64, i64* %arrayidx.phi, i32 1 + %arrayidx30.inc = getelementptr i64, i64* %arrayidx30.phi, i32 1 + %arrayidx60.inc = getelementptr i64, i64* %arrayidx60.phi, i32 1 + br i1 %cmp, label %for.body, label %for.end.loopexit + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %entry + ret i32 0 +} + +declare i32 @llvm.hexagon.A2.sath(i32) #1 + +declare i64 @llvm.hexagon.S2.asl.r.p(i64, i32) #1 + +declare i64 @llvm.hexagon.M2.dpmpyss.s0(i32, i32) #1 + +declare i64 @llvm.hexagon.A2.vaddhs(i64, i64) #1 + +attributes #0 = { nounwind "fp-contract-model"="standard" "no-frame-pointer-elim-non-leaf" "realign-stack" "relocation-model"="static" "ssp-buffers-size"="8" } +attributes #1 = { nounwind readnone } + +!0 = !{!"short", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/intrinsics/system_user.ll b/test/CodeGen/Hexagon/intrinsics/system_user.ll new file mode 100644 index 000000000000..dad4effb0a14 --- /dev/null +++ b/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; RUN: llc -march=hexagon -O0 < %s | FileCheck -check-prefix=CHECK-CALL %s +; Hexagon Programmer's Reference Manual 11.9.1 SYSTEM/USER + +; CHECK-CALL-NOT: call + +; Data cache prefetch +declare void @llvm.hexagon.prefetch(i8*) +define void @prefetch(i8* %a) { + call void @llvm.hexagon.prefetch(i8* %a) + ret void +} +; CHECK: dcfetch({{.*}} + #0) diff --git a/test/CodeGen/Hexagon/memops-stack.ll b/test/CodeGen/Hexagon/memops-stack.ll new file mode 100644 index 000000000000..a8dc664591e9 --- /dev/null +++ b/test/CodeGen/Hexagon/memops-stack.ll @@ -0,0 +1,147 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +; CHECK-LABEL: test0 +; CHECK: memw(r29+#{{[0-9]+}}) += #1 +define void @test0() #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = add nsw i32 %1, 1 + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test1 +; CHECK: memw(r29+#{{[0-9]+}}) -= #1 +define void @test1() #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = sub nsw i32 %1, 1 + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test2 +; CHECK: memw(r29+#{{[0-9]+}}) = setbit(#0) +define void @test2() #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = or i32 %1, 1 + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test3 +; CHECK: memw(r29+#{{[0-9]+}}) = clrbit(#0) +define void @test3() #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = and i32 %1, -2 + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test4 +; CHECK: memw(r29+#{{[0-9]+}}) += r +define void @test4(i32 %a) #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = add nsw i32 %1, %a + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test5 +; CHECK: memw(r29+#{{[0-9]+}}) -= r +define void @test5(i32 %a) #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = sub nsw i32 %1, %a + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test6 +; CHECK: memw(r29+#{{[0-9]+}}) |= r +define void @test6(i32 %a) #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = or i32 %1, %a + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + +; CHECK-LABEL: test7 +; CHECK: memw(r29+#{{[0-9]+}}) &= r +define void @test7(i32 %a) #0 { +entry: + %x = alloca i32, align 4 + %0 = bitcast i32* %x to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #3 + call void @foo(i32* nonnull %x) #3 + %1 = load i32, i32* %x, align 4, !tbaa !1 + %inc = and i32 %1, %a + store i32 %inc, i32* %x, align 4, !tbaa !1 + call void @foo(i32* nonnull %x) #3 + call void @llvm.lifetime.end(i64 4, i8* %0) #3 + ret void +} + + +declare void @foo(i32*) #2 +declare void @llvm.lifetime.start(i64, i8* nocapture) #1 +declare void @llvm.lifetime.end(i64, i8* nocapture) #1 + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/memops.ll b/test/CodeGen/Hexagon/memops.ll index e4a8bf7c95e9..011a4e50e5d8 100644 --- a/test/CodeGen/Hexagon/memops.ll +++ b/test/CodeGen/Hexagon/memops.ll @@ -3,6 +3,7 @@ define void @memop_unsigned_char_add5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 @@ -14,6 +15,7 @@ entry: define void @memop_unsigned_char_add(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 @@ -26,6 +28,7 @@ entry: define void @memop_unsigned_char_sub(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_sub: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 @@ -38,6 +41,7 @@ entry: define void @memop_unsigned_char_or(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_or: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x @@ -47,6 +51,7 @@ entry: define void @memop_unsigned_char_and(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_and: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x @@ -56,6 +61,7 @@ entry: define void @memop_unsigned_char_clrbit(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_clrbit: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 @@ -67,6 +73,7 @@ entry: define void @memop_unsigned_char_setbit(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_setbit: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i8, i8* %p, align 1 %conv = zext i8 %0 to i32 @@ -78,6 +85,7 @@ entry: define void @memop_unsigned_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add5_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -90,6 +98,7 @@ entry: define void @memop_unsigned_char_add_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i @@ -103,6 +112,7 @@ entry: define void @memop_unsigned_char_sub_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_sub_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i @@ -116,6 +126,7 @@ entry: define void @memop_unsigned_char_or_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_or_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -126,6 +137,7 @@ entry: define void @memop_unsigned_char_and_index(i8* nocapture %p, i32 %i, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_and_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -136,6 +148,7 @@ entry: define void @memop_unsigned_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_clrbit_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -148,6 +161,7 @@ entry: define void @memop_unsigned_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_setbit_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -160,6 +174,7 @@ entry: define void @memop_unsigned_char_add5_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add5_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -172,6 +187,7 @@ entry: define void @memop_unsigned_char_add_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_add_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 @@ -185,6 +201,7 @@ entry: define void @memop_unsigned_char_sub_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_sub_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 @@ -198,6 +215,7 @@ entry: define void @memop_unsigned_char_or_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_or_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -208,6 +226,7 @@ entry: define void @memop_unsigned_char_and_index5(i8* nocapture %p, i8 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_and_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -218,6 +237,7 @@ entry: define void @memop_unsigned_char_clrbit_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_clrbit_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -230,6 +250,7 @@ entry: define void @memop_unsigned_char_setbit_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_char_setbit_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -242,6 +263,7 @@ entry: define void @memop_signed_char_add5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 @@ -253,6 +275,7 @@ entry: define void @memop_signed_char_add(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 @@ -265,6 +288,7 @@ entry: define void @memop_signed_char_sub(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_sub: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %0 = load i8, i8* %p, align 1 @@ -277,6 +301,7 @@ entry: define void @memop_signed_char_or(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_or: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %or3 = or i8 %0, %x @@ -286,6 +311,7 @@ entry: define void @memop_signed_char_and(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_and: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i8, i8* %p, align 1 %and3 = and i8 %0, %x @@ -295,6 +321,7 @@ entry: define void @memop_signed_char_clrbit(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_clrbit: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 @@ -306,6 +333,7 @@ entry: define void @memop_signed_char_setbit(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_setbit: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i8, i8* %p, align 1 %conv2 = zext i8 %0 to i32 @@ -317,6 +345,7 @@ entry: define void @memop_signed_char_add5_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add5_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -329,6 +358,7 @@ entry: define void @memop_signed_char_add_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i @@ -342,6 +372,7 @@ entry: define void @memop_signed_char_sub_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_sub_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i @@ -355,6 +386,7 @@ entry: define void @memop_signed_char_or_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_or_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -365,6 +397,7 @@ entry: define void @memop_signed_char_and_index(i8* nocapture %p, i32 %i, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_and_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -375,6 +408,7 @@ entry: define void @memop_signed_char_clrbit_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_char_clrbit_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -387,6 +421,7 @@ entry: define void @memop_signed_char_setbit_index(i8* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_char_setbit_index: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 %i %0 = load i8, i8* %add.ptr, align 1 @@ -399,6 +434,7 @@ entry: define void @memop_signed_char_add5_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add5_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -411,6 +447,7 @@ entry: define void @memop_signed_char_add_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_add_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 @@ -424,6 +461,7 @@ entry: define void @memop_signed_char_sub_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_sub_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i8 %x to i32 %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 @@ -437,6 +475,7 @@ entry: define void @memop_signed_char_or_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_or_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -447,6 +486,7 @@ entry: define void @memop_signed_char_and_index5(i8* nocapture %p, i8 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_char_and_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -457,6 +497,7 @@ entry: define void @memop_signed_char_clrbit_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_clrbit_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -469,6 +510,7 @@ entry: define void @memop_signed_char_setbit_index5(i8* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_char_setbit_index5: ; CHECK: memb(r{{[0-9]+}}{{ *}}+{{ *}}#5){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i8, i8* %p, i32 5 %0 = load i8, i8* %add.ptr, align 1 @@ -481,6 +523,7 @@ entry: define void @memop_unsigned_short_add5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 @@ -492,6 +535,7 @@ entry: define void @memop_unsigned_short_add(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 @@ -504,6 +548,7 @@ entry: define void @memop_unsigned_short_sub(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_sub: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 @@ -516,6 +561,7 @@ entry: define void @memop_unsigned_short_or(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_or: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x @@ -525,6 +571,7 @@ entry: define void @memop_unsigned_short_and(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_and: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x @@ -534,6 +581,7 @@ entry: define void @memop_unsigned_short_clrbit(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_clrbit: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 @@ -545,6 +593,7 @@ entry: define void @memop_unsigned_short_setbit(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_setbit: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i16, i16* %p, align 2 %conv = zext i16 %0 to i32 @@ -556,6 +605,7 @@ entry: define void @memop_unsigned_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add5_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -568,6 +618,7 @@ entry: define void @memop_unsigned_short_add_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i @@ -581,6 +632,7 @@ entry: define void @memop_unsigned_short_sub_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_sub_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i @@ -594,6 +646,7 @@ entry: define void @memop_unsigned_short_or_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_or_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -604,6 +657,7 @@ entry: define void @memop_unsigned_short_and_index(i16* nocapture %p, i32 %i, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_and_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -614,6 +668,7 @@ entry: define void @memop_unsigned_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_clrbit_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -626,6 +681,7 @@ entry: define void @memop_unsigned_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_setbit_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -638,6 +694,7 @@ entry: define void @memop_unsigned_short_add5_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add5_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -650,6 +707,7 @@ entry: define void @memop_unsigned_short_add_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_add_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 @@ -663,6 +721,7 @@ entry: define void @memop_unsigned_short_sub_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_sub_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 @@ -676,6 +735,7 @@ entry: define void @memop_unsigned_short_or_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_or_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -686,6 +746,7 @@ entry: define void @memop_unsigned_short_and_index5(i16* nocapture %p, i16 zeroext %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_and_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -696,6 +757,7 @@ entry: define void @memop_unsigned_short_clrbit_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_clrbit_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -708,6 +770,7 @@ entry: define void @memop_unsigned_short_setbit_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_short_setbit_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -720,6 +783,7 @@ entry: define void @memop_signed_short_add5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 @@ -731,6 +795,7 @@ entry: define void @memop_signed_short_add(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 @@ -743,6 +808,7 @@ entry: define void @memop_signed_short_sub(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_sub: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %0 = load i16, i16* %p, align 2 @@ -755,6 +821,7 @@ entry: define void @memop_signed_short_or(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_or: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %or3 = or i16 %0, %x @@ -764,6 +831,7 @@ entry: define void @memop_signed_short_and(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_and: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i16, i16* %p, align 2 %and3 = and i16 %0, %x @@ -773,6 +841,7 @@ entry: define void @memop_signed_short_clrbit(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_clrbit: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 @@ -784,6 +853,7 @@ entry: define void @memop_signed_short_setbit(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_setbit: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i16, i16* %p, align 2 %conv2 = zext i16 %0 to i32 @@ -795,6 +865,7 @@ entry: define void @memop_signed_short_add5_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add5_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -807,6 +878,7 @@ entry: define void @memop_signed_short_add_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i @@ -820,6 +892,7 @@ entry: define void @memop_signed_short_sub_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_sub_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i @@ -833,6 +906,7 @@ entry: define void @memop_signed_short_or_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_or_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -843,6 +917,7 @@ entry: define void @memop_signed_short_and_index(i16* nocapture %p, i32 %i, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_and_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -853,6 +928,7 @@ entry: define void @memop_signed_short_clrbit_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_short_clrbit_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -865,6 +941,7 @@ entry: define void @memop_signed_short_setbit_index(i16* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_short_setbit_index: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 %i %0 = load i16, i16* %add.ptr, align 2 @@ -877,6 +954,7 @@ entry: define void @memop_signed_short_add5_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add5_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -889,6 +967,7 @@ entry: define void @memop_signed_short_add_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_add_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}+={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 @@ -902,6 +981,7 @@ entry: define void @memop_signed_short_sub_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_sub_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}-={{ *}}r{{[0-9]+}} %conv4 = zext i16 %x to i32 %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 @@ -915,6 +995,7 @@ entry: define void @memop_signed_short_or_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_or_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -925,6 +1006,7 @@ entry: define void @memop_signed_short_and_index5(i16* nocapture %p, i16 signext %x) nounwind { entry: +; CHECK-LABEL: memop_signed_short_and_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -935,6 +1017,7 @@ entry: define void @memop_signed_short_clrbit_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_clrbit_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -947,6 +1030,7 @@ entry: define void @memop_signed_short_setbit_index5(i16* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_short_setbit_index5: ; CHECK: memh(r{{[0-9]+}}{{ *}}+{{ *}}#10){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i16, i16* %p, i32 5 %0 = load i16, i16* %add.ptr, align 2 @@ -959,6 +1043,7 @@ entry: define void @memop_signed_int_add5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i32, i32* %p, align 4 %add = add i32 %0, 5 @@ -968,6 +1053,7 @@ entry: define void @memop_signed_int_add(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %add = add i32 %0, %x @@ -977,6 +1063,7 @@ entry: define void @memop_signed_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_sub: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %sub = sub i32 %0, %x @@ -986,6 +1073,7 @@ entry: define void @memop_signed_int_or(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_or: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x @@ -995,6 +1083,7 @@ entry: define void @memop_signed_int_and(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_and: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x @@ -1004,6 +1093,7 @@ entry: define void @memop_signed_int_clrbit(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_clrbit: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 @@ -1013,6 +1103,7 @@ entry: define void @memop_signed_int_setbit(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_setbit: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 @@ -1022,6 +1113,7 @@ entry: define void @memop_signed_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add5_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1032,6 +1124,7 @@ entry: define void @memop_signed_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1042,6 +1135,7 @@ entry: define void @memop_signed_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_sub_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1052,6 +1146,7 @@ entry: define void @memop_signed_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_or_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1062,6 +1157,7 @@ entry: define void @memop_signed_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_and_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1072,6 +1168,7 @@ entry: define void @memop_signed_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_int_clrbit_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1082,6 +1179,7 @@ entry: define void @memop_signed_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_signed_int_setbit_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1092,6 +1190,7 @@ entry: define void @memop_signed_int_add5_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add5_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1102,6 +1201,7 @@ entry: define void @memop_signed_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_add_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1112,6 +1212,7 @@ entry: define void @memop_signed_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_sub_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1122,6 +1223,7 @@ entry: define void @memop_signed_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_or_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1132,6 +1234,7 @@ entry: define void @memop_signed_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_signed_int_and_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1142,6 +1245,7 @@ entry: define void @memop_signed_int_clrbit_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_clrbit_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1152,6 +1256,7 @@ entry: define void @memop_signed_int_setbit_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_signed_int_setbit_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1162,6 +1267,7 @@ entry: define void @memop_unsigned_int_add5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, 5 @@ -1171,6 +1277,7 @@ entry: define void @memop_unsigned_int_add(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %add = add nsw i32 %0, %x @@ -1180,6 +1287,7 @@ entry: define void @memop_unsigned_int_sub(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_sub: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %sub = sub nsw i32 %0, %x @@ -1189,6 +1297,7 @@ entry: define void @memop_unsigned_int_or(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_or: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %or = or i32 %0, %x @@ -1198,6 +1307,7 @@ entry: define void @memop_unsigned_int_and(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_and: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %0 = load i32, i32* %p, align 4 %and = and i32 %0, %x @@ -1207,6 +1317,7 @@ entry: define void @memop_unsigned_int_clrbit(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_clrbit: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %0 = load i32, i32* %p, align 4 %and = and i32 %0, -33 @@ -1216,6 +1327,7 @@ entry: define void @memop_unsigned_int_setbit(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_setbit: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %0 = load i32, i32* %p, align 4 %or = or i32 %0, 128 @@ -1225,6 +1337,7 @@ entry: define void @memop_unsigned_int_add5_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add5_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1235,6 +1348,7 @@ entry: define void @memop_unsigned_int_add_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1245,6 +1359,7 @@ entry: define void @memop_unsigned_int_sub_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_sub_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1255,6 +1370,7 @@ entry: define void @memop_unsigned_int_or_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_or_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1265,6 +1381,7 @@ entry: define void @memop_unsigned_int_and_index(i32* nocapture %p, i32 %i, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_and_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1275,6 +1392,7 @@ entry: define void @memop_unsigned_int_clrbit_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_clrbit_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1285,6 +1403,7 @@ entry: define void @memop_unsigned_int_setbit_index(i32* nocapture %p, i32 %i) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_setbit_index: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#0){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 %i %0 = load i32, i32* %add.ptr, align 4 @@ -1295,6 +1414,7 @@ entry: define void @memop_unsigned_int_add5_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add5_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}#5 %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1305,6 +1425,7 @@ entry: define void @memop_unsigned_int_add_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_add_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}+={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1315,6 +1436,7 @@ entry: define void @memop_unsigned_int_sub_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_sub_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}-={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1325,6 +1447,7 @@ entry: define void @memop_unsigned_int_or_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_or_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}|={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1335,6 +1458,7 @@ entry: define void @memop_unsigned_int_and_index5(i32* nocapture %p, i32 %x) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_and_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}&={{ *}}r{{[0-9]+}} %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1345,6 +1469,7 @@ entry: define void @memop_unsigned_int_clrbit_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_clrbit_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}clrbit({{ *}}#5{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 @@ -1355,6 +1480,7 @@ entry: define void @memop_unsigned_int_setbit_index5(i32* nocapture %p) nounwind { entry: +; CHECK-LABEL: memop_unsigned_int_setbit_index5: ; CHECK: memw(r{{[0-9]+}}{{ *}}+{{ *}}#20){{ *}}={{ *}}setbit({{ *}}#7{{ *}}) %add.ptr = getelementptr inbounds i32, i32* %p, i32 5 %0 = load i32, i32* %add.ptr, align 4 diff --git a/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll b/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll new file mode 100644 index 000000000000..5fe16db6f806 --- /dev/null +++ b/test/CodeGen/Hexagon/misched-top-rptracker-sync.ll @@ -0,0 +1,151 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; Check that we no longer get this error: +; void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): +; Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. + +target triple = "hexagon" + +%struct.A = type { %struct.B*, %struct.B* } +%struct.B = type { i8*, %struct.B*, %struct.B* } + +@.str.4 = external hidden unnamed_addr constant [41 x i8], align 1 +@__func__.fred = external hidden unnamed_addr constant [16 x i8], align 1 +@.str.5 = external hidden unnamed_addr constant [43 x i8], align 1 + +; Function Attrs: nounwind +declare void @_Assert(i8*, i8*) #0 + +; Function Attrs: nounwind +define void @fred(%struct.A* %pA, %struct.B* %p) #0 !dbg !6 { +entry: + tail call void @llvm.dbg.value(metadata %struct.A* %pA, i64 0, metadata !26, metadata !28), !dbg !29 + tail call void @llvm.dbg.value(metadata %struct.B* %p, i64 0, metadata !27, metadata !28), !dbg !30 + %cmp = icmp eq %struct.B* %p, null, !dbg !31 + br i1 %cmp, label %cond.false, label %cond.end, !dbg !31 + +cond.false: ; preds = %entry + tail call void @_Assert(i8* getelementptr inbounds ([41 x i8], [41 x i8]* @.str.4, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8], [16 x i8]* @__func__.fred, i32 0, i32 0)) #0, !dbg !32 + br label %cond.end, !dbg !32 + +cond.end: ; preds = %cond.false, %entry + %cmp1 = icmp eq %struct.A* %pA, null, !dbg !34 + br i1 %cmp1, label %cond.false3, label %cond.end4, !dbg !34 + +cond.false3: ; preds = %cond.end + tail call void @_Assert(i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str.5, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8], [16 x i8]* @__func__.fred, i32 0, i32 0)) #0, !dbg !35 + br label %cond.end4, !dbg !35 + +cond.end4: ; preds = %cond.false3, %cond.end + %p2 = getelementptr inbounds %struct.A, %struct.A* %pA, i32 0, i32 0, !dbg !36 + %0 = load %struct.B*, %struct.B** %p2, align 4, !dbg !38, !tbaa !39 + %cmp5 = icmp eq %struct.B* %0, null, !dbg !44 + br i1 %cmp5, label %if.then, label %if.end, !dbg !45 + +if.then: ; preds = %cond.end4 + %p1 = getelementptr inbounds %struct.A, %struct.A* %pA, i32 0, i32 1, !dbg !46 + store %struct.B* %p, %struct.B** %p1, align 4, !dbg !48, !tbaa !49 + store %struct.B* %p, %struct.B** %p2, align 4, !dbg !50, !tbaa !39 + %p4 = getelementptr inbounds %struct.B, %struct.B* %p, i32 0, i32 1, !dbg !51 + store %struct.B* null, %struct.B** %p4, align 4, !dbg !52, !tbaa !53 + %p5 = getelementptr inbounds %struct.B, %struct.B* %p, i32 0, i32 2, !dbg !55 + store %struct.B* null, %struct.B** %p5, align 4, !dbg !56, !tbaa !57 + br label %return, !dbg !58 + +if.end: ; preds = %cond.end4 + %1 = ptrtoint %struct.B* %0 to i32, !dbg !59 + %p57 = getelementptr inbounds %struct.B, %struct.B* %p, i32 0, i32 2, !dbg !60 + store %struct.B* null, %struct.B** %p57, align 4, !dbg !61, !tbaa !57 + %p49 = getelementptr inbounds %struct.B, %struct.B* %p, i32 0, i32 1, !dbg !62 + %2 = bitcast %struct.B** %p49 to i32*, !dbg !63 + store i32 %1, i32* %2, align 4, !dbg !63, !tbaa !53 + %p511 = getelementptr inbounds %struct.B, %struct.B* %0, i32 0, i32 2, !dbg !64 + store %struct.B* %p, %struct.B** %p511, align 4, !dbg !65, !tbaa !57 + store %struct.B* %p, %struct.B** %p2, align 4, !dbg !66, !tbaa !39 + br label %return, !dbg !67 + +return: ; preds = %if.end, %if.then + ret void, !dbg !68 +} + +; Function Attrs: nounwind readnone +declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!3, !4} +!llvm.ident = !{!5} + +!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.9.0 (http://llvm.org/git/clang.git 4b380bc1db8b0c72bdbdaf0e4697b1a84100a369) (http://llvm.org/git/llvm.git 6217a62bc009d55e160dbb694f2e94a22c80809f)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) +!1 = !DIFile(filename: "bug.c", directory: "/") +!2 = !{} +!3 = !{i32 2, !"Dwarf Version", i32 4} +!4 = !{i32 2, !"Debug Info Version", i32 3} +!5 = !{!"clang version 3.9.0 (http://llvm.org/git/clang.git 4b380bc1db8b0c72bdbdaf0e4697b1a84100a369) (http://llvm.org/git/llvm.git 6217a62bc009d55e160dbb694f2e94a22c80809f)"} +!6 = distinct !DISubprogram(name: "fred", scope: !1, file: !1, line: 138, type: !7, isLocal: false, isDefinition: true, scopeLine: 139, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !25) +!7 = !DISubroutineType(types: !8) +!8 = !{null, !9, !15} +!9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 32, align: 32) +!10 = !DIDerivedType(tag: DW_TAG_typedef, name: "A", file: !11, line: 57, baseType: !12) +!11 = !DIFile(filename: "bug.h", directory: "/") +!12 = distinct !DICompositeType(tag: DW_TAG_structure_type, file: !11, line: 54, size: 64, align: 32, elements: !13) +!13 = !{!14, !24} +!14 = !DIDerivedType(tag: DW_TAG_member, name: "p2", scope: !12, file: !11, line: 55, baseType: !15, size: 32, align: 32) +!15 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !16, size: 32, align: 32) +!16 = !DIDerivedType(tag: DW_TAG_typedef, name: "B", file: !11, line: 50, baseType: !17) +!17 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "B", file: !11, line: 45, size: 96, align: 32, elements: !18) +!18 = !{!19, !21, !23} +!19 = !DIDerivedType(tag: DW_TAG_member, name: "p3", scope: !17, file: !11, line: 47, baseType: !20, size: 32, align: 32) +!20 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: null, size: 32, align: 32) +!21 = !DIDerivedType(tag: DW_TAG_member, name: "p4", scope: !17, file: !11, line: 48, baseType: !22, size: 32, align: 32, offset: 32) +!22 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !17, size: 32, align: 32) +!23 = !DIDerivedType(tag: DW_TAG_member, name: "p5", scope: !17, file: !11, line: 49, baseType: !22, size: 32, align: 32, offset: 64) +!24 = !DIDerivedType(tag: DW_TAG_member, name: "p1", scope: !12, file: !11, line: 56, baseType: !15, size: 32, align: 32, offset: 32) +!25 = !{!26, !27} +!26 = !DILocalVariable(name: "pA", arg: 1, scope: !6, file: !1, line: 138, type: !9) +!27 = !DILocalVariable(name: "p", arg: 2, scope: !6, file: !1, line: 138, type: !15) +!28 = !DIExpression() +!29 = !DILocation(line: 138, column: 34, scope: !6) +!30 = !DILocation(line: 138, column: 57, scope: !6) +!31 = !DILocation(line: 140, column: 5, scope: !6) +!32 = !DILocation(line: 140, column: 5, scope: !33) +!33 = !DILexicalBlockFile(scope: !6, file: !1, discriminator: 2) +!34 = !DILocation(line: 141, column: 5, scope: !6) +!35 = !DILocation(line: 141, column: 5, scope: !33) +!36 = !DILocation(line: 143, column: 30, scope: !37) +!37 = distinct !DILexicalBlock(scope: !6, file: !1, line: 143, column: 9) +!38 = !DILocation(line: 155, column: 18, scope: !6) +!39 = !{!40, !41, i64 0} +!40 = !{!"", !41, i64 0, !41, i64 4} +!41 = !{!"any pointer", !42, i64 0} +!42 = !{!"omnipotent char", !43, i64 0} +!43 = !{!"Simple C/C++ TBAA"} +!44 = !DILocation(line: 143, column: 14, scope: !37) +!45 = !DILocation(line: 143, column: 9, scope: !6) +!46 = !DILocation(line: 146, column: 26, scope: !47) +!47 = distinct !DILexicalBlock(scope: !37, file: !1, line: 143, column: 41) +!48 = !DILocation(line: 146, column: 36, scope: !47) +!49 = !{!40, !41, i64 4} +!50 = !DILocation(line: 145, column: 32, scope: !47) +!51 = !DILocation(line: 147, column: 20, scope: !47) +!52 = !DILocation(line: 147, column: 29, scope: !47) +!53 = !{!54, !41, i64 4} +!54 = !{!"B", !41, i64 0, !41, i64 4, !41, i64 8} +!55 = !DILocation(line: 148, column: 20, scope: !47) +!56 = !DILocation(line: 148, column: 29, scope: !47) +!57 = !{!54, !41, i64 8} +!58 = !DILocation(line: 149, column: 9, scope: !47) +!59 = !DILocation(line: 154, column: 41, scope: !6) +!60 = !DILocation(line: 153, column: 16, scope: !6) +!61 = !DILocation(line: 153, column: 25, scope: !6) +!62 = !DILocation(line: 154, column: 16, scope: !6) +!63 = !DILocation(line: 154, column: 26, scope: !6) +!64 = !DILocation(line: 155, column: 29, scope: !6) +!65 = !DILocation(line: 155, column: 39, scope: !6) +!66 = !DILocation(line: 156, column: 28, scope: !6) +!67 = !DILocation(line: 157, column: 1, scope: !6) +!68 = !DILocation(line: 157, column: 1, scope: !69) +!69 = !DILexicalBlockFile(scope: !6, file: !1, discriminator: 1) diff --git a/test/CodeGen/Hexagon/newvaluestore.ll b/test/CodeGen/Hexagon/newvaluestore.ll index 13cbba2d08e1..cc1ff00ecdcd 100644 --- a/test/CodeGen/Hexagon/newvaluestore.ll +++ b/test/CodeGen/Hexagon/newvaluestore.ll @@ -1,22 +1,13 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-hexagon-misched < %s | FileCheck %s -; Check that we generate new value store packet in V4 +; RUN: llc -march=hexagon < %s | FileCheck %s +; Check that we generate new value store. @i = global i32 0, align 4 -@j = global i32 10, align 4 -@k = global i32 100, align 4 -define i32 @main() nounwind { +define i32 @main(i32 %x, i32* %p) nounwind { entry: ; CHECK: memw(r{{[0-9]+}}+#{{[0-9]+}}) = r{{[0-9]+}}.new - %number1 = alloca i32, align 4 - %number2 = alloca i32, align 4 - %number3 = alloca i32, align 4 - %0 = load i32 , i32 * @i, align 4 - store i32 %0, i32* %number1, align 4 - %1 = load i32 , i32 * @j, align 4 - store i32 %1, i32* %number2, align 4 - %2 = load i32 , i32 * @k, align 4 - store i32 %2, i32* %number3, align 4 - ret i32 %0 + %t0 = load i32, i32* @i, align 4 + store i32 %t0, i32* %p, align 4 + ret i32 %x } diff --git a/test/CodeGen/Hexagon/opt-addr-mode.ll b/test/CodeGen/Hexagon/opt-addr-mode.ll new file mode 100644 index 000000000000..7cb437c327cf --- /dev/null +++ b/test/CodeGen/Hexagon/opt-addr-mode.ll @@ -0,0 +1,107 @@ +; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt < %s | FileCheck %s --check-prefix=CHECK-NO-AMODE +; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 -disable-hexagon-amodeopt=0 -hexagon-amode-growth-limit=4 < %s | FileCheck %s --check-prefix=CHECK-AMODE + +; CHECK-NO-AMODE: [[REG0:(r[0-9]+)]] = ##global_2 +; CHECK-NO-AMODE: memw([[REG0]] + {{.*}}<<#2) = + +; CHECK-AMODE: [[REG1:(r[0-9]+)]] = memw(##global_1) +; CHECK-AMODE: memw([[REG1]]<<#2 + ##global_2) = + +@global_1 = external global i32, align 4 +@global_2 = external global [128 x i32], align 8 + +declare i32 @foo(i32, i32) #0 + +define i32 @fred(i32 %a0, i32 %a1, i32* %p) #0 { +entry: + %call24 = tail call i32 @foo(i32 %a0, i32 1) #0 + %tobool26 = icmp eq i32 %call24, 0 + br i1 %tobool26, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %entry + %cmp3 = icmp sgt i32 %a1, 19 + %sub = sub nsw i32 19, %a0 + %xor = xor i32 %a0, 1 + br i1 %cmp3, label %while.body.us.preheader, label %while.body.preheader + +while.body.preheader: ; preds = %while.body.lr.ph + br label %while.body + +while.body.us.preheader: ; preds = %while.body.lr.ph + br label %while.body.us + +while.body.us: ; preds = %while.body.us.preheader, %while.cond.backedge.us + %call27.us = phi i32 [ %call.us, %while.cond.backedge.us ], [ %call24, %while.body.us.preheader ] + %x0 = load i32, i32* %p, align 4, !tbaa !4 + %cmp.us = icmp sgt i32 %x0, 0 + br i1 %cmp.us, label %if.then.us, label %if.end.us + +if.then.us: ; preds = %while.body.us + %sext.us = shl i32 %call27.us, 24 + %conv2.us = ashr i32 %sext.us, 24 + %x10 = tail call i32 @foo(i32 %conv2.us, i32 %sext.us) #0 + br label %if.end.us + +if.end.us: ; preds = %if.then.us, %while.body.us + %x1 = load i32, i32* %p, align 4, !tbaa !4 + %call8.us = tail call i32 @foo(i32 %sub, i32 %a1) #0 + %tobool11.us = icmp eq i32 %call8.us, 0 + br i1 %tobool11.us, label %while.cond.backedge.us, label %if.then12.us + +if.then12.us: ; preds = %if.end.us + %x3 = load i32, i32* %p, align 4, !tbaa !4 + %sub13.us = sub i32 %x3, %x1 + %x4 = load i32, i32* @global_1, align 4, !tbaa !4 + %arrayidx.us = getelementptr inbounds [128 x i32], [128 x i32]* @global_2, i32 0, i32 %x4 + store i32 %sub13.us, i32* %arrayidx.us, align 4, !tbaa !4 + br label %while.cond.backedge.us + +while.cond.backedge.us: ; preds = %if.then12.us, %if.end.us + %call.us = tail call i32 @foo(i32 %a0, i32 2) #0 + %tobool.us = icmp eq i32 %call.us, 0 + br i1 %tobool.us, label %while.end.loopexit, label %while.body.us + +while.body: ; preds = %while.body.preheader, %while.cond.backedge + %call27 = phi i32 [ %call, %while.cond.backedge ], [ %call24, %while.body.preheader ] + %x5 = load i32, i32* %p, align 4, !tbaa !4 + %cmp = icmp sgt i32 %x5, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %while.body + %sext = shl i32 %call27, 24 + %conv2 = ashr i32 %sext, 24 + %x11 = tail call i32 @foo(i32 %conv2, i32 %sext) #0 + br label %if.end + +if.end: ; preds = %if.then, %while.body + %tobool11 = icmp eq i32 %call27, 0 + br i1 %tobool11, label %while.cond.backedge, label %if.then12 + +if.then12: ; preds = %if.end + %x7 = load i32, i32* @global_1, align 4, !tbaa !4 + %arrayidx = getelementptr inbounds [128 x i32], [128 x i32]* @global_2, i32 0, i32 %x7 + store i32 0, i32* %arrayidx, align 4, !tbaa !4 + br label %while.cond.backedge + +while.cond.backedge: ; preds = %if.then12, %if.end + %call = tail call i32 @foo(i32 %a0, i32 3) #0 + %tobool = icmp eq i32 %call, 0 + br i1 %tobool, label %while.end.loopexit33, label %while.body + +while.end.loopexit: ; preds = %while.cond.backedge.us + br label %while.end + +while.end.loopexit33: ; preds = %while.cond.backedge + br label %while.end + +while.end: ; preds = %while.end.loopexit33, %while.end.loopexit, %entry + ret i32 0 +} + +attributes #0 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} +!4 = !{!5, !5, i64 0} +!5 = !{!"int", !2, i64 0} diff --git a/test/CodeGen/Hexagon/packetize-tailcall-arg.ll b/test/CodeGen/Hexagon/packetize-tailcall-arg.ll new file mode 100644 index 000000000000..17afd7df94a3 --- /dev/null +++ b/test/CodeGen/Hexagon/packetize-tailcall-arg.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; There should only be one packet: +; { +; jump free +; r0 = memw(r0 + #-4) +; } +; +; CHECK: { +; CHECK-NOT: { + +define void @fred(i8* %p) nounwind { +entry: + %arrayidx = getelementptr inbounds i8, i8* %p, i32 -4 + %t0 = bitcast i8* %arrayidx to i8** + %t1 = load i8*, i8** %t0, align 4 + tail call void @free(i8* %t1) + ret void +} + +; Function Attrs: nounwind +declare void @free(i8* nocapture) nounwind + diff --git a/test/CodeGen/Hexagon/peephole-op-swap.ll b/test/CodeGen/Hexagon/peephole-op-swap.ll new file mode 100644 index 000000000000..32db7851fb8b --- /dev/null +++ b/test/CodeGen/Hexagon/peephole-op-swap.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; The operand-swapping code in HexagonPeephole was not handling subregisters +; correctly, resulting in a crash on this code. + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +@float_rounding_mode = external global i8, align 1 +@float_exception_flags = external global i8, align 1 + +; Function Attrs: nounwind +define i64 @fred(i32 %a) #0 { +entry: + br i1 undef, label %cleanup, label %lor.lhs.false + +lor.lhs.false: ; preds = %entry + %cmp3 = icmp eq i32 undef, 255 + %tobool4 = icmp ne i32 undef, 0 + %or.cond = and i1 %tobool4, %cmp3 + %. = select i1 %or.cond, i64 9223372036854775807, i64 -9223372036854775808 + br label %cleanup + +cleanup: ; preds = %lor.lhs.false, %entry + %retval.0 = phi i64 [ 9223372036854775807, %entry ], [ %., %lor.lhs.false ] + ret i64 %retval.0 +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/Hexagon/pic-local.ll b/test/CodeGen/Hexagon/pic-local.ll new file mode 100644 index 000000000000..48b0096aa652 --- /dev/null +++ b/test/CodeGen/Hexagon/pic-local.ll @@ -0,0 +1,19 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv5 -relocation-model=pic < %s | FileCheck %s + +define private void @f1() { + ret void +} + +define internal void @f2() { + ret void +} + +define void()* @get_f1() { + ; CHECK: r0 = add(pc, ##.Lf1@PCREL) + ret void()* @f1 +} + +define void()* @get_f2() { + ; CHECK: r0 = add(pc, ##f2@PCREL) + ret void()* @f2 +} diff --git a/test/CodeGen/Hexagon/pic-regusage.ll b/test/CodeGen/Hexagon/pic-regusage.ll new file mode 100644 index 000000000000..53c4ba40cb9a --- /dev/null +++ b/test/CodeGen/Hexagon/pic-regusage.ll @@ -0,0 +1,69 @@ +; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s + +; Force the use of R14 (by clobbering everything else in the inline asm). +; Make sure that R14 is not set before the __save call (which will clobber +; R14, R15 and R28). +; CHECK: call __save_r16_through_r27 +; CHECK: } +; CHECK: r14{{ *}}= + +@.str = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1 + +; Function Attrs: nounwind optsize +define i32 @_Z7testR14Pi(i32* nocapture %res) #0 { +entry: + %0 = load i32, i32* %res, align 4 + %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1 + %asmresult = extractvalue { i32, i32 } %1, 0 + %asmresult1 = extractvalue { i32, i32 } %1, 1 + store i32 %asmresult, i32* %res, align 4 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2 + %2 = load i32, i32* %res, align 4 + %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2 + ret i32 0 +} + +; Function Attrs: nounwind optsize +declare i32 @printf(i8*, ...) #0 + +; Same as above for R15. +; CHECK: call __save_r16_through_r27 +; CHECK: } +; CHECK: r15{{ *}}= + +; Function Attrs: nounwind optsize +define i32 @_Z7testR15Pi(i32* nocapture %res) #0 { +entry: + %0 = load i32, i32* %res, align 4 + %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27}"(i32 %0, i32 40, i32 50) #1 + %asmresult = extractvalue { i32, i32 } %1, 0 + %asmresult1 = extractvalue { i32, i32 } %1, 1 + store i32 %asmresult, i32* %res, align 4 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2 + %2 = load i32, i32* %res, align 4 + %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2 + ret i32 0 +} + +; Same as above for R28. +; CHECK: call __save_r16_through_r27 +; CHECK: } +; CHECK: r28{{ *}}= + +; Function Attrs: nounwind optsize +define i32 @_Z7testR28Pi(i32* nocapture %res) #0 { +entry: + %0 = load i32, i32* %res, align 4 + %1 = tail call { i32, i32 } asm "r0=$2\0A\09$1=add(r0,#$3)\0A\09$0=add(r0,#$4)\0A\09", "=r,=r,r,i,i,~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26}"(i32 %0, i32 40, i32 50) #1 + %asmresult = extractvalue { i32, i32 } %1, 0 + %asmresult1 = extractvalue { i32, i32 } %1, 1 + store i32 %asmresult, i32* %res, align 4 + %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %asmresult1) #2 + %2 = load i32, i32* %res, align 4 + %call2 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %2) #2 + ret i32 0 +} + +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } +attributes #2 = { nounwind optsize } diff --git a/test/CodeGen/Hexagon/rdf-copy-undef2.ll b/test/CodeGen/Hexagon/rdf-copy-undef2.ll new file mode 100644 index 000000000000..5f29d414ffc1 --- /dev/null +++ b/test/CodeGen/Hexagon/rdf-copy-undef2.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target triple = "hexagon" + +declare void @llvm.lifetime.start(i64, i8* nocapture) #0 +declare void @llvm.lifetime.end(i64, i8* nocapture) #0 +declare signext i16 @cat(i16 signext) #1 +declare void @danny(i16 signext, i16 signext, i16 signext, i16* nocapture readonly, i16 signext, i16* nocapture) #1 +declare void @sammy(i16* nocapture readonly, i16* nocapture readonly, i16* nocapture readonly, i32* nocapture, i16* nocapture, i16 signext, i16 signext, i16 signext) #1 +declare i8* @llvm.stacksave() #2 +declare void @llvm.stackrestore(i8*) #2 + +define i32 @fred(i16 signext %p0, i16 signext %p1, i16* nocapture readonly %p2, i16 signext %p3, i16* nocapture readonly %p4, i16* nocapture %p5) #1 { +entry: + %0 = tail call i8* @llvm.stacksave() + %vla = alloca i16, i32 undef, align 8 + %call17 = call signext i16 @cat(i16 signext 1) #1 + br i1 undef, label %for.cond23.preheader, label %for.end47 + +for.cond23.preheader: ; preds = %for.end40, %entry + %i.190 = phi i16 [ %inc46, %for.end40 ], [ 0, %entry ] + br i1 undef, label %for.body27, label %for.end40 + +for.body27: ; preds = %for.body27, %for.cond23.preheader + %indvars.iv = phi i32 [ %indvars.iv.next, %for.body27 ], [ 0, %for.cond23.preheader ] + %call30 = call signext i16 @cat(i16 signext 7) #1 + %arrayidx32 = getelementptr inbounds i16, i16* %vla, i32 %indvars.iv + store i16 %call30, i16* %arrayidx32, align 2 + %arrayidx37 = getelementptr inbounds i16, i16* undef, i32 %indvars.iv + %indvars.iv.next = add nuw nsw i32 %indvars.iv, 1 + %exitcond = icmp eq i16 undef, %p3 + br i1 %exitcond, label %for.end40, label %for.body27 + +for.end40: ; preds = %for.body27, %for.cond23.preheader + call void @sammy(i16* nonnull undef, i16* undef, i16* %p4, i32* null, i16* undef, i16 signext undef, i16 signext undef, i16 signext undef) #1 + %inc46 = add nuw nsw i16 %i.190, 1 + %exitcond94 = icmp eq i16 %inc46, %call17 + br i1 %exitcond94, label %for.end47.loopexit, label %for.cond23.preheader + +for.end47.loopexit: ; preds = %for.end40 + %.pre = load i16, i16* undef, align 2 + br label %for.end47 + +for.end47: ; preds = %for.end47.loopexit, %entry + %1 = phi i16 [ %.pre, %for.end47.loopexit ], [ 0, %entry ] + call void @danny(i16 signext %1, i16 signext %p0, i16 signext %p1, i16* %p2, i16 signext %p3, i16* %p5) #1 + call void @llvm.stackrestore(i8* %0) + ret i32 undef +} + + +attributes #0 = { argmemonly nounwind } +attributes #1 = { optsize } +attributes #2 = { nounwind } diff --git a/test/CodeGen/Hexagon/rdf-copy.ll b/test/CodeGen/Hexagon/rdf-copy.ll index 96153ca31fa4..afb03a6315d7 100644 --- a/test/CodeGen/Hexagon/rdf-copy.ll +++ b/test/CodeGen/Hexagon/rdf-copy.ll @@ -16,7 +16,7 @@ ; CHECK-LABEL: LBB0_1 ; CHECK: [[DST:r[0-9]+]] = [[SRC:r[0-9]+]] ; CHECK-DAG: memw([[SRC]] -; CHECK-DAG-NOT: memw([[DST]] +; CHECK-NOT: memw([[DST]] ; CHECK-LABEL: LBB0_2 target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" diff --git a/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll new file mode 100644 index 000000000000..7adf7e8a5355 --- /dev/null +++ b/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -0,0 +1,37 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: r0 = #24 +; CHECK-NEXT: r1 = +; // R2 should be assigned a value from R3+. +; CHECK-NEXT: r2 = r{{[3-9]}} +; CHECK-NEXT: trap0 + +target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" +target triple = "hexagon" + +; Function Attrs: nounwind +define i32 @foo(i32 %status) #0 { +entry: + %arg1 = alloca i32, align 4 + %0 = bitcast i32* %arg1 to i8* + call void @llvm.lifetime.start(i64 4, i8* %0) #2 + store i32 %status, i32* %arg1, align 4, !tbaa !1 + %1 = call i32 asm sideeffect "r0 = #$1\0Ar1 = $2\0Ar2 = $4\0Atrap0 (#0)\0A$0 = r0", "=r,i,r,*m,r,~{r0},~{r1},~{r2}"(i32 24, i32* nonnull %arg1, i32* nonnull %arg1, i32 %status) #2, !srcloc !5 + call void @llvm.lifetime.end(i64 4, i8* %0) #2 + ret i32 %1 +} + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.start(i64, i8* nocapture) #1 + +; Function Attrs: argmemonly nounwind +declare void @llvm.lifetime.end(i64, i8* nocapture) #1 + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { argmemonly nounwind } +attributes #2 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} +!5 = !{i32 110, i32 129, i32 146, i32 163, i32 183} diff --git a/test/CodeGen/Hexagon/rdf-inline-asm.ll b/test/CodeGen/Hexagon/rdf-inline-asm.ll new file mode 100644 index 000000000000..ae09062638dc --- /dev/null +++ b/test/CodeGen/Hexagon/rdf-inline-asm.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32" +target triple = "hexagon" + +@x = common global i32* null, align 4 + +; Function Attrs: nounwind +define i32 @inotify_init() #0 { +entry: + %0 = tail call i32 asm sideeffect "trap0(#1);\0A", "={r0},{r6},~{memory}"(i32 1043) #1, !srcloc !1 + %cmp = icmp sgt i32 %0, -4096 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %sub = sub nsw i32 0, %0 + %1 = load i32*, i32** @x, align 4, !tbaa !2 + store i32 %sub, i32* %1, align 4, !tbaa !6 + br label %if.end + +if.end: ; preds = %if.then, %entry + %retval1.0 = phi i32 [ -1, %if.then ], [ %0, %entry ] + ret i32 %retval1.0 +} + +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } + +!1 = !{i32 155} +!2 = !{!3, !3, i64 0} +!3 = !{!"any pointer", !4, i64 0} +!4 = !{!"omnipotent char", !5, i64 0} +!5 = !{!"Simple C/C++ TBAA"} +!6 = !{!7, !7, i64 0} +!7 = !{!"long", !4, i64 0} diff --git a/test/CodeGen/Hexagon/rdf-reset-kills.ll b/test/CodeGen/Hexagon/rdf-reset-kills.ll new file mode 100644 index 000000000000..37db8c5f64e6 --- /dev/null +++ b/test/CodeGen/Hexagon/rdf-reset-kills.ll @@ -0,0 +1,28 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; This test used to crash in register scavenger due to incorrectly set +; kill flags. + +target triple = "hexagon" + +define void @foo(i64 %a) #0 { +entry: + %conv.i = and i64 %a, 9218868437227405312 + %cmp = icmp ne i64 %conv.i, 9218868437227405312 + %and.i37 = and i64 %a, 4503599627370495 + %tobool = icmp eq i64 %and.i37, 0 + %or.cond = or i1 %cmp, %tobool + br i1 %or.cond, label %lor.lhs.false, label %if.then + +lor.lhs.false: ; preds = %entry + br i1 undef, label %return, label %if.then + +if.then: ; preds = %lor.lhs.false, %entry + br label %return + +return: ; preds = %if.then, %lor.lhs.false + ret void +} + +attributes #0 = { norecurse nounwind } diff --git a/test/CodeGen/Hexagon/reg-scavengebug-3.ll b/test/CodeGen/Hexagon/reg-scavengebug-3.ll new file mode 100644 index 000000000000..db9ed55d2da6 --- /dev/null +++ b/test/CodeGen/Hexagon/reg-scavengebug-3.ll @@ -0,0 +1,80 @@ +; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s + +; CHECK: vmem + +target triple = "hexagon" + +@vecpreds = external global [15 x <16 x i32>], align 64 +@vectors = external global [15 x <16 x i32>], align 64 +@vector_pairs = external global [15 x <32 x i32>], align 128 +@.str1 = external hidden unnamed_addr constant [20 x i8], align 1 +@.str2 = external hidden unnamed_addr constant [43 x i8], align 1 +@Q6VecPredResult = external global <16 x i32>, align 64 +@.str52 = external hidden unnamed_addr constant [57 x i8], align 1 +@.str54 = external hidden unnamed_addr constant [59 x i8], align 1 +@VectorResult = external global <16 x i32>, align 64 +@.str243 = external hidden unnamed_addr constant [60 x i8], align 1 +@.str251 = external hidden unnamed_addr constant [77 x i8], align 1 +@.str290 = external hidden unnamed_addr constant [65 x i8], align 1 +@VectorPairResult = external global <32 x i32>, align 128 + +; Function Attrs: nounwind +declare void @print_vector(i32, i8*) #0 + +; Function Attrs: nounwind +declare i32 @printf(i8*, ...) #0 + +; Function Attrs: nounwind +declare void @print_vecpred(i32, i8*) #0 + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 + +; Function Attrs: nounwind +declare void @init_vectors() #0 + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 + +; Function Attrs: nounwind +declare void @init_addresses() #0 + +; Function Attrs: nounwind +declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1 + +; Function Attrs: nounwind +define i32 @main() #0 { +entry: + %0 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64 + %1 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 + call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) + %2 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 + %call50 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([57 x i8], [57 x i8]* @.str52, i32 0, i32 0)) #3 + %3 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 + %call52 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @.str54, i32 0, i32 0)) #3 + %4 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 + %call300 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([65 x i8], [65 x i8]* @.str290, i32 0, i32 0)) #3 + %5 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 0), align 64 + %6 = load <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vectors, i32 0, i32 1), align 64 + %call1373 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([60 x i8], [60 x i8]* @.str243, i32 0, i32 0)) #3 + %7 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %call1381 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([20 x i8], [20 x i8]* @.str1, i32 0, i32 0), i8* getelementptr inbounds ([43 x i8], [43 x i8]* @.str2, i32 0, i32 0), i8* getelementptr inbounds ([77 x i8], [77 x i8]* @.str251, i32 0, i32 0)) #3 + %8 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %9 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %8, i32 16843009) + call void @print_vector(i32 64, i8* bitcast (<16 x i32>* @VectorResult to i8*)) + %10 = call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %11 = call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %10, i32 16843009) + %12 = bitcast <512 x i1> %11 to <16 x i32> + %13 = bitcast <16 x i32> %12 to <512 x i1> + %14 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1> %13, <16 x i32> undef, <16 x i32> undef) + store <16 x i32> %14, <16 x i32>* @VectorResult, align 64 + ret i32 0 +} + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind readnone } +attributes #2 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind } diff --git a/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll b/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll new file mode 100644 index 000000000000..78c4b989b7ac --- /dev/null +++ b/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll @@ -0,0 +1,100 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +; This testcase tries to force spills of both vector and int registers +; in a function where scavenging slots were reserved for both register +; classes. The original problem was that the scavenger selected an int +; slot (with size/alignment of 4) for a vector register (with size/ +; alignment of 64). This caused an assertion in the assembler printer +; due to an offset in a vector store having unexpected low-order bits. + +; We cannot directly whether the bits appear or not, since they will be +; truncated off by the time we see the output, but we can check that +; we got to the end of the function without crashing. + +; CHECK: endloop +; CHECK: dealloc_return + +target triple = "hexagon" + +define void @foo(<16 x i32>* nocapture readnone %p) #0 { +entry: + %0 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"() #1 + %asmresult = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 0 + %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 1 + %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 2 + %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 3 + %asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 4 + %asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 5 + %asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 6 + %asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 7 + %asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 8 + %asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 9 + %asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 10 + %asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 11 + %asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 12 + %asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 13 + %asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 14 + %asmresult15 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 15 + %asmresult16 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 16 + %asmresult17 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 17 + %asmresult18 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 18 + %asmresult19 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 19 + %asmresult20 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 20 + %asmresult21 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 21 + %asmresult22 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 22 + %asmresult23 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 23 + %asmresult24 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 24 + %asmresult25 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 25 + %asmresult26 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 26 + %asmresult27 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 27 + %asmresult28 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %0, 28 + %1 = tail call { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } asm "nop", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v"() #1 + %asmresult29 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 0 + %asmresult30 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 1 + %asmresult31 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 2 + %asmresult32 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 3 + %asmresult33 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 4 + %asmresult34 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 5 + %asmresult35 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 6 + %asmresult36 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 7 + %asmresult37 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 8 + %asmresult38 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 9 + %asmresult39 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 10 + %asmresult40 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 11 + %asmresult41 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 12 + %asmresult42 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 13 + %asmresult43 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 14 + %asmresult44 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 15 + %asmresult45 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 16 + %asmresult46 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 17 + %asmresult47 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 18 + %asmresult48 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 19 + %asmresult49 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 20 + %asmresult50 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 21 + %asmresult51 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 22 + %asmresult52 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 23 + %asmresult53 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 24 + %asmresult54 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 25 + %asmresult55 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 26 + %asmresult56 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 27 + %asmresult57 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 28 + %asmresult58 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 29 + %asmresult59 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 30 + %asmresult60 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %1, 31 + %2 = tail call { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } asm "nop", "=q,=q,=q,=q"() #1 + %asmresult61 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %2, 0 + %asmresult62 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %2, 1 + %asmresult63 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %2, 2 + %asmresult64 = extractvalue { <16 x i32>, <16 x i32>, <16 x i32>, <16 x i32> } %2, 3 + %3 = tail call <16 x i32> asm "nop", "=q,q,q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63, <16 x i32> %asmresult64) #1 + tail call void asm sideeffect "nop", "q,q,q"(<16 x i32> %asmresult61, <16 x i32> %asmresult62, <16 x i32> %asmresult63) #2 + tail call void asm sideeffect "nop", "q,q"(<16 x i32> %asmresult64, <16 x i32> %3) #2 + tail call void asm sideeffect "nop", "v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v,v"(<16 x i32> %asmresult29, <16 x i32> %asmresult30, <16 x i32> %asmresult31, <16 x i32> %asmresult32, <16 x i32> %asmresult33, <16 x i32> %asmresult34, <16 x i32> %asmresult35, <16 x i32> %asmresult36, <16 x i32> %asmresult37, <16 x i32> %asmresult38, <16 x i32> %asmresult39, <16 x i32> %asmresult40, <16 x i32> %asmresult41, <16 x i32> %asmresult42, <16 x i32> %asmresult43, <16 x i32> %asmresult44, <16 x i32> %asmresult45, <16 x i32> %asmresult46, <16 x i32> %asmresult47, <16 x i32> %asmresult48, <16 x i32> %asmresult49, <16 x i32> %asmresult50, <16 x i32> %asmresult51, <16 x i32> %asmresult52, <16 x i32> %asmresult53, <16 x i32> %asmresult54, <16 x i32> %asmresult55, <16 x i32> %asmresult56, <16 x i32> %asmresult57, <16 x i32> %asmresult58, <16 x i32> %asmresult59, <16 x i32> %asmresult60) #2 + tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14, i32 %asmresult15, i32 %asmresult16, i32 %asmresult17, i32 %asmresult18, i32 %asmresult19, i32 %asmresult20, i32 %asmresult21, i32 %asmresult22, i32 %asmresult23, i32 %asmresult24, i32 %asmresult25, i32 %asmresult26, i32 %asmresult27, i32 %asmresult28) #2 + ret void +} + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } diff --git a/test/CodeGen/Hexagon/restore-single-reg.ll b/test/CodeGen/Hexagon/restore-single-reg.ll new file mode 100644 index 000000000000..8abd4a855463 --- /dev/null +++ b/test/CodeGen/Hexagon/restore-single-reg.ll @@ -0,0 +1,42 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" +target triple = "hexagon" + +; Generate the inline restore for single register pair for functions +; with "optsize" attribute. + +; CHECK-LABEL: fred_os +; CHECK-DAG: memd{{.*}} = r17:16 +; CHECK-DAG: r17:16 = memd{{.*}} +; CHECK-DAG: deallocframe +; CHECK-NOT: call __restore + +define i32 @fred_os(i32 %x) #0 { +entry: + %call = tail call i32 @foo(i32 %x) #2 + %call1 = tail call i32 @bar(i32 %x, i32 %call) #2 + ret i32 %call1 +} + +; Generate the restoring call for single register pair for functions +; with "minsize" attribute. + +; CHECK-LABEL: fred_oz +; CHECK-DAG: memd{{.*}} = r17:16 +; CHECK-NOT: r17:16 = memd{{.*}} +; CHECK-DAG: call __restore + +define i32 @fred_oz(i32 %x) #1 { +entry: + %call = tail call i32 @foo(i32 %x) #2 + %call1 = tail call i32 @bar(i32 %x, i32 %call) #2 + ret i32 %call1 +} + +declare i32 @foo(i32) #2 +declare i32 @bar(i32, i32) #2 + +attributes #0 = { nounwind optsize "disable-tail-calls"="false" } +attributes #1 = { nounwind minsize "disable-tail-calls"="false" } +attributes #2 = { nounwind optsize } diff --git a/test/CodeGen/Hexagon/ret-struct-by-val.ll b/test/CodeGen/Hexagon/ret-struct-by-val.ll new file mode 100644 index 000000000000..26ed2ff36f77 --- /dev/null +++ b/test/CodeGen/Hexagon/ret-struct-by-val.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: r0 = add(r0, r1) + +; Allow simple structures to be returned by value. + +%s = type { i32, i32 } + +declare %s @foo() #0 + +define i32 @fred() #0 { + %t0 = call %s @foo() + %x = extractvalue %s %t0, 0 + %y = extractvalue %s %t0, 1 + %r = add i32 %x, %y + ret i32 %r +} + +attributes #0 = { nounwind } diff --git a/test/CodeGen/Hexagon/runtime-stkchk.ll b/test/CodeGen/Hexagon/runtime-stkchk.ll new file mode 100644 index 000000000000..a4e8f117679e --- /dev/null +++ b/test/CodeGen/Hexagon/runtime-stkchk.ll @@ -0,0 +1,44 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv55 -enable-stackovf-sanitizer < %s | FileCheck %s + +; CHECK-LABEL: foo_1 +; CHECK: __runtime_stack_check +define i32 @foo_1(i32 %n) #0 { +entry: + %local = alloca [1024 x i32], align 8 + %0 = bitcast [1024 x i32]* %local to i8* + call void @llvm.lifetime.start(i64 4096, i8* %0) #1 + %arraydecay = getelementptr inbounds [1024 x i32], [1024 x i32]* %local, i32 0, i32 0 + call void @baz_1(i32* %arraydecay) #3 + %arrayidx = getelementptr inbounds [1024 x i32], [1024 x i32]* %local, i32 0, i32 %n + %1 = load i32, i32* %arrayidx, align 4 + call void @llvm.lifetime.end(i64 4096, i8* %0) #1 + ret i32 %1 +} + +; CHECK-LABEL: foo_2 +; CHECK: __save_r16_through_r19_stkchk +define i32 @foo_2(i32 %n, i32* %y) #0 { +entry: + %local = alloca [2048 x i32], align 8 + %0 = bitcast [2048 x i32]* %local to i8* + call void @llvm.lifetime.start(i64 8192, i8* %0) #1 + %arraydecay = getelementptr inbounds [2048 x i32], [2048 x i32]* %local, i32 0, i32 0 + call void @baz_2(i32* %y, i32* %arraydecay) #3 + %1 = load i32, i32* %y, align 4 + %add = add nsw i32 %n, %1 + %arrayidx = getelementptr inbounds [2048 x i32], [2048 x i32]* %local, i32 0, i32 %add + %2 = load i32, i32* %arrayidx, align 4 + call void @llvm.lifetime.end(i64 8192, i8* %0) #1 + ret i32 %2 +} + +declare void @baz_1(i32*) #2 +declare void @baz_2(i32*, i32*) #2 +declare void @llvm.lifetime.start(i64, i8* nocapture) #1 +declare void @llvm.lifetime.end(i64, i8* nocapture) #1 + +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } +attributes #2 = { optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { optsize } + diff --git a/test/CodeGen/Hexagon/sdata-array.ll b/test/CodeGen/Hexagon/sdata-array.ll new file mode 100644 index 000000000000..89ef46079f7c --- /dev/null +++ b/test/CodeGen/Hexagon/sdata-array.ll @@ -0,0 +1,13 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; No arrays in sdata. +; CHECK: memb(##foo) + +@foo = common global [4 x i8] zeroinitializer, align 1 + +define void @set() nounwind { +entry: + store i8 0, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @foo, i32 0, i32 0), align 1 + ret void +} + diff --git a/test/CodeGen/Hexagon/sdata-basic.ll b/test/CodeGen/Hexagon/sdata-basic.ll new file mode 100644 index 000000000000..db7375417df9 --- /dev/null +++ b/test/CodeGen/Hexagon/sdata-basic.ll @@ -0,0 +1,16 @@ +; RUN: llc -march=hexagon -O2 < %s | FileCheck %s +; CHECK-NOT: ##var +target datalayout = "e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a0:0-n16:32" +target triple = "hexagon" + +@var = external global i32 + +define i32 @foo() nounwind readonly { +entry: + %0 = load i32, i32* @var, align 4, !tbaa !0 + ret i32 %0 +} + +!0 = !{!"int", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/section_7275.ll b/test/CodeGen/Hexagon/section_7275.ll new file mode 100644 index 000000000000..c2b80ae3f69d --- /dev/null +++ b/test/CodeGen/Hexagon/section_7275.ll @@ -0,0 +1,54 @@ +; The reason for the bug was that when deciding if a global +; variable can be part of sdata, we were wrongly ignoring +; the presence of any section specified for the variable +; using the section attribute. If such a section is specified, +; and that section is not sdata*/sbss* then the variable +; cannot use GPREL addressing, i.e. memw(#variablename). + +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK-LABEL: foo +; CHECK-DAG: memw(##b) +; CHECK-DAG: memw(#d) +; CHECK-DAG: memw(##g) +; CHECK-DAG: memw(#h) +; CHECK-DAG: memw(#f) +; CHECK-DAG: memw(##e) +; CHECK-DAG: memw(#a) +; CHECK-DAG: memw(#c) +; CHECK-LABEL: bar +; CHECK: memw(##b) + +@b = global i32 0, section ".data.section", align 4 +@a = common global i32 0, align 4 +@d = global i32 0, section ".sbss", align 4 +@c = global i32 0, section ".sdata", align 4 +@f = global i32 0, section ".sbss.4", align 4 +@e = global i32 0, section ".sdatafoo", align 4 +@h = global i32 0, section ".sdata.4", align 4 +@g = global i32 0, section ".sbssfoo", align 4 + +define void @foo() nounwind { +entry: + %0 = load i32, i32* @b, align 4 + store i32 %0, i32* @a, align 4 + %1 = load i32, i32* @d, align 4 + store i32 %1, i32* @c, align 4 + %2 = load i32, i32* @f, align 4 + store i32 %2, i32* @e, align 4 + %3 = load i32, i32* @h, align 4 + store i32 %3, i32* @g, align 4 + ret void +} + +define void @bar() nounwind section ".function.section" { +entry: + %0 = load i32, i32* @a, align 4 + store i32 %0, i32* @b, align 4 + ret void +} + +define i32 @main() nounwind readnone { +entry: + ret i32 0 +} + diff --git a/test/CodeGen/Hexagon/select-instr-align.ll b/test/CodeGen/Hexagon/select-instr-align.ll new file mode 100644 index 000000000000..e3b2929d52f1 --- /dev/null +++ b/test/CodeGen/Hexagon/select-instr-align.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s +; CHECK-LABEL: aligned_load: +; CHECK: = vmem({{.*}}) +; CHECK-LABEL: aligned_store: +; CHECK: vmem({{.*}}) = +; CHECK-LABEL: unaligned_load: +; CHECK: = vmemu({{.*}}) +; CHECK-LABEL: unaligned_store: +; CHECK: vmemu({{.*}}) = + +define <16 x i32> @aligned_load(<16 x i32>* %p, <16 x i32> %a) { + %v = load <16 x i32>, <16 x i32>* %p, align 64 + ret <16 x i32> %v +} + +define void @aligned_store(<16 x i32>* %p, <16 x i32> %a) { + store <16 x i32> %a, <16 x i32>* %p, align 64 + ret void +} + +define <16 x i32> @unaligned_load(<16 x i32>* %p, <16 x i32> %a) { + %v = load <16 x i32>, <16 x i32>* %p, align 32 + ret <16 x i32> %v +} + +define void @unaligned_store(<16 x i32>* %p, <16 x i32> %a) { + store <16 x i32> %a, <16 x i32>* %p, align 32 + ret void +} + + diff --git a/test/CodeGen/Hexagon/static.ll b/test/CodeGen/Hexagon/static.ll index 760b8b559725..c3237b748881 100644 --- a/test/CodeGen/Hexagon/static.ll +++ b/test/CodeGen/Hexagon/static.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 -disable-dfa-sched -disable-hexagon-misched < %s | FileCheck %s +; RUN: llc -march=hexagon < %s | FileCheck %s @num = external global i32 @acc = external global i32 @val = external global i32 -; CHECK: memw(##num) -; CHECK: memw(##acc) -; CHECK: memw(##val) +; CHECK-DAG: memw(#num) +; CHECK-DAG: memw(#acc) +; CHECK-DAG: memw(#val) define void @foo() nounwind { entry: diff --git a/test/CodeGen/Hexagon/store-shift.ll b/test/CodeGen/Hexagon/store-shift.ll new file mode 100644 index 000000000000..866930990baa --- /dev/null +++ b/test/CodeGen/Hexagon/store-shift.ll @@ -0,0 +1,50 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; CHECK-DAG: r[[BASE:[0-9]+]] += add +; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2, #5) +; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2, #6) +; CHECK-DAG: memw(r0 + r[[IDX0]]<<#2) = r3 +; CHECK-DAG: memw(r0 + r[[IDX1]]<<#2) = r3 +; CHECK-DAG: memw(r[[BASE]] + r[[IDX0]]<<#2) = r[[IDX0]] +; CHECK-DAG: memw(r[[BASE]] + r[[IDX1]]<<#2) = r[[IDX0]] + +target triple = "hexagon" + +@G = external global i32, align 4 + +; Function Attrs: norecurse nounwind +define void @fred(i32* nocapture %A, [50 x i32]* nocapture %B, i32 %N, i32 %M) #0 { +entry: + %add = add nsw i32 %N, 5 + %arrayidx = getelementptr inbounds i32, i32* %A, i32 %add + store i32 %M, i32* %arrayidx, align 4, !tbaa !1 + %add2 = add nsw i32 %N, 6 + %arrayidx3 = getelementptr inbounds i32, i32* %A, i32 %add2 + store i32 %M, i32* %arrayidx3, align 4, !tbaa !1 + %add4 = add nsw i32 %N, 35 + %arrayidx5 = getelementptr inbounds i32, i32* %A, i32 %add4 + store i32 %add, i32* %arrayidx5, align 4, !tbaa !1 + %arrayidx8 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %add + store i32 %add, i32* %arrayidx8, align 4, !tbaa !1 + %inc = add nsw i32 %N, 6 + %arrayidx8.1 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %inc + store i32 %add, i32* %arrayidx8.1, align 4, !tbaa !1 + %sub = add nsw i32 %N, 4 + %arrayidx10 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %sub + %0 = load i32, i32* %arrayidx10, align 4, !tbaa !1 + %add11 = add nsw i32 %0, 1 + store i32 %add11, i32* %arrayidx10, align 4, !tbaa !1 + %1 = load i32, i32* %arrayidx, align 4, !tbaa !1 + %add13 = add nsw i32 %N, 25 + %arrayidx15 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add13, i32 %add + store i32 %1, i32* %arrayidx15, align 4, !tbaa !1 + store i32 5, i32* @G, align 4, !tbaa !1 + ret void +} + +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } + +!1 = !{!2, !2, i64 0} +!2 = !{!"int", !3, i64 0} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/storerinewabs.ll b/test/CodeGen/Hexagon/storerinewabs.ll new file mode 100644 index 000000000000..73e513a8bcee --- /dev/null +++ b/test/CodeGen/Hexagon/storerinewabs.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=hexagon -hexagon-small-data-threshold=0 < %s | FileCheck %s + +@global = external global i32, align 4 + +; There was a bug causing ### to be printed. Make sure we print ## instead. +; CHECK-LABEL: foo +; CHECK: memw(##global) = + +define void @foo(i32 %x) #0 { +entry: + %add = add nsw i32 %x, 1 + store i32 %add, i32* @global, align 4 + ret void +} + +attributes #0 = { norecurse nounwind } + diff --git a/test/CodeGen/Hexagon/struct_args_large.ll b/test/CodeGen/Hexagon/struct_args_large.ll index 1438d73eacf7..fb4780b0e5a9 100644 --- a/test/CodeGen/Hexagon/struct_args_large.ll +++ b/test/CodeGen/Hexagon/struct_args_large.ll @@ -1,4 +1,4 @@ -; XFAIL: +; XFAIL: * ; RUN: llc -march=hexagon < %s | FileCheck %s ; CHECK: r[[T0:[0-9]+]] = CONST32(#s2) ; CHECK: memw(r29+#0) = r{{.}} diff --git a/test/CodeGen/Hexagon/sube.ll b/test/CodeGen/Hexagon/sube.ll index fab3dcaefa86..7bc00759303f 100644 --- a/test/CodeGen/Hexagon/sube.ll +++ b/test/CodeGen/Hexagon/sube.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 < %s | FileCheck %s +; RUN: llc -march=hexagon -disable-hsdr -hexagon-expand-condsets=0 -hexagon-bit=0 -disable-post-ra < %s | FileCheck %s -; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1) ; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #0) +; CHECK: r{{[0-9]+:[0-9]+}} = combine(#0, #1) ; CHECK: p{{[0-9]+}} = cmp.gtu(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) ; CHECK: r{{[0-9]+:[0-9]+}} = sub(r{{[0-9]+:[0-9]+}}, r{{[0-9]+:[0-9]+}}) ; CHECK: r{{[0-9]+}} = mux(p{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}) diff --git a/test/CodeGen/Hexagon/tail-dup-subreg-map.ll b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll new file mode 100644 index 000000000000..08dadeb9aaa4 --- /dev/null +++ b/test/CodeGen/Hexagon/tail-dup-subreg-map.ll @@ -0,0 +1,67 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; REQUIRES: asserts + +; When tail-duplicating a block with PHI nodes that use subregisters, the +; subregisters were dropped by the tail duplicator, resulting in invalid +; COPY instructions being generated. + +; CHECK: = extractu(r{{[0-9]+}}, #15, #17) + +target triple = "hexagon" + +%struct.0 = type { i64, i16 } +%struct.1 = type { i64, i64 } + +declare hidden fastcc void @foo(%struct.0* noalias nocapture, i8 signext, i8 zeroext, i32, i64, i64) unnamed_addr #0 + +define void @fred(%struct.0* noalias nocapture sret %agg.result, %struct.1* byval nocapture readonly align 8 %a) #1 { +entry: + %0 = load i64, i64* undef, align 8 + switch i32 undef, label %if.else [ + i32 32767, label %if.then + i32 0, label %if.then7 + ] + +if.then: ; preds = %entry + ret void + +if.then7: ; preds = %entry + br i1 undef, label %if.then.i, label %if.else16.i + +if.then.i: ; preds = %if.then7 + br i1 undef, label %if.then5.i, label %if.else.i + +if.then5.i: ; preds = %if.then.i + %shl.i21 = shl i64 %0, 0 + br label %if.end.i + +if.else.i: ; preds = %if.then.i + %shl12.i = shl i64 %0, undef + br label %if.end.i + +if.end.i: ; preds = %if.else.i, %if.then5.i + %aSig0.0 = phi i64 [ undef, %if.then5.i ], [ %shl12.i, %if.else.i ] + %storemerge43.i = phi i64 [ %shl.i21, %if.then5.i ], [ 0, %if.else.i ] + %sub15.i = sub nsw i32 -63, undef + br label %if.end13 + +if.else16.i: ; preds = %if.then7 + br label %if.end13 + +if.else: ; preds = %entry + %or12 = or i64 undef, 281474976710656 + br label %if.end13 + +if.end13: ; preds = %if.else, %if.else16.i, %if.end.i + %aSig1.1 = phi i64 [ %0, %if.else ], [ %storemerge43.i, %if.end.i ], [ undef, %if.else16.i ] + %aSig0.2 = phi i64 [ %or12, %if.else ], [ %aSig0.0, %if.end.i ], [ undef, %if.else16.i ] + %aExp.0 = phi i32 [ undef, %if.else ], [ %sub15.i, %if.end.i ], [ undef, %if.else16.i ] + %shl2.i = shl i64 %aSig0.2, 15 + %shr.i = lshr i64 %aSig1.1, 49 + %or.i = or i64 %shl2.i, %shr.i + tail call fastcc void @foo(%struct.0* noalias %agg.result, i8 signext 80, i8 zeroext undef, i32 %aExp.0, i64 %or.i, i64 undef) + unreachable +} + +attributes #0 = { norecurse nounwind } +attributes #1 = { nounwind } diff --git a/test/CodeGen/Hexagon/tls_pic.ll b/test/CodeGen/Hexagon/tls_pic.ll new file mode 100644 index 000000000000..190e1d71d39b --- /dev/null +++ b/test/CodeGen/Hexagon/tls_pic.ll @@ -0,0 +1,37 @@ +; RUN: llc -O0 -march=hexagon -relocation-model=pic < %s | FileCheck %s + +@dst_ie = thread_local(initialexec) global i32 0, align 4 +@src_ie = thread_local(initialexec) global i32 0, align 4 + +; CHECK-LABEL: test_initial_exec +; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK-DAG: = ##src_ie@IEGOT +; CHECK-DAG: = ##dst_ie@IEGOT +; CHECK-NOT: call +define i32 @test_initial_exec() nounwind { +entry: + %0 = load i32, i32* @src_ie, align 4 + store i32 %0, i32* @dst_ie, align 4 + ret i32 0 +} + +@dst_gd = external thread_local global i32 +@src_gd = external thread_local global i32 + +; At the moment, the local-dynamic model uses the same code as the +; general-dynamic model. + +; CHECK-LABEL: test_dynamic +; CHECK-DAG: = add(pc, ##_GLOBAL_OFFSET_TABLE_@PCREL) +; CHECK-DAG: = ##src_gd@GDGOT +; CHECK-DAG: = ##dst_gd@GDGOT +; CHECK-DAG: call src_gd@GDPLT +; CHECK-DAG: call dst_gd@GDPLT + +define i32 @test_dynamic() nounwind { +entry: + %0 = load i32, i32* @src_gd, align 4 + store i32 %0, i32* @dst_gd, align 4 + ret i32 0 +} + diff --git a/test/CodeGen/Hexagon/tls_static.ll b/test/CodeGen/Hexagon/tls_static.ll new file mode 100644 index 000000000000..ad2ca716b70d --- /dev/null +++ b/test/CodeGen/Hexagon/tls_static.ll @@ -0,0 +1,28 @@ +; RUN: llc -O0 -march=hexagon -relocation-model=static < %s | FileCheck %s + +@dst_le = thread_local global i32 0, align 4 +@src_le = thread_local global i32 0, align 4 + +; CHECK-LABEL: test_local_exec +; CHECK-DAG: = ##src_le@TPREL +; CHECK-DAG: = ##dst_le@TPREL +define i32 @test_local_exec() nounwind { +entry: + %0 = load i32, i32* @src_le, align 4 + store i32 %0, i32* @dst_le, align 4 + ret i32 0 +} + +@dst_ie = external thread_local global i32 +@src_ie = external thread_local global i32 + +; CHECK-LABEL: test_initial_exec: +; CHECK-DAG: = memw(##src_ie@IE) +; CHECK-DAG: = memw(##dst_ie@IE) +define i32 @test_initial_exec() nounwind { +entry: + %0 = load i32, i32* @src_ie, align 4 + store i32 %0, i32* @dst_ie, align 4 + ret i32 0 +} + diff --git a/test/CodeGen/Hexagon/v60-cur.ll b/test/CodeGen/Hexagon/v60-cur.ll new file mode 100644 index 000000000000..fe24309f5b87 --- /dev/null +++ b/test/CodeGen/Hexagon/v60-cur.ll @@ -0,0 +1,62 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s + +; Test that we generate a .cur + +; CHECK: v{{[0-9]*}}.cur{{ *}} +; CHECK: v{{[0-9]*}}.cur{{ *}} + +define void @conv3x3_i(i8* noalias nocapture readonly %iptr0, i32 %shift, i32 %width) #0 { +entry: + br i1 undef, label %for.body.lr.ph, label %for.end + +for.body.lr.ph: + br label %for.body + +for.body: + %iptr0.pn = phi i8* [ %iptr0, %for.body.lr.ph ], [ %iptr0.addr.0121, %for.body ] + %j.0115 = phi i32 [ 0, %for.body.lr.ph ], [ %add, %for.body ] + %sline000.0114 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ %1, %for.body ] + %sline100.0113 = phi <16 x i32> [ zeroinitializer, %for.body.lr.ph ], [ zeroinitializer, %for.body ] + %iptr0.addr.0121 = getelementptr inbounds i8, i8* %iptr0.pn, i32 64 + %0 = bitcast i8* %iptr0.addr.0121 to <16 x i32>* + %1 = load <16 x i32>, <16 x i32>* %0, align 64, !tbaa !1 + %2 = load <16 x i32>, <16 x i32>* null, align 64, !tbaa !1 + %3 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %1, <16 x i32> %sline000.0114, i32 4) + %4 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> zeroinitializer, <16 x i32> %sline100.0113, i32 4) + %5 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %2, <16 x i32> zeroinitializer, i32 4) + %6 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %3, <16 x i32> %sline000.0114) + %7 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %5, <16 x i32> zeroinitializer) + %8 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32> %6, i32 0, i32 0) + %9 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %8, <32 x i32> zeroinitializer, i32 undef, i32 0) + %10 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> %9, <32 x i32> undef, i32 undef, i32 0) + %11 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %10) + %12 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %11, <16 x i32> undef, i32 %shift) + %13 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> undef, <16 x i32> %12) + store <16 x i32> %13, <16 x i32>* undef, align 64, !tbaa !1 + %14 = tail call <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32> zeroinitializer, <32 x i32> %7, i32 undef, i32 1) + %15 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %14) + %16 = tail call <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32> %15, <16 x i32> undef, i32 %shift) + %17 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %16, <16 x i32> undef) + store <16 x i32> %17, <16 x i32>* undef, align 64, !tbaa !1 + %add = add nsw i32 %j.0115, 64 + %cmp = icmp slt i32 %add, %width + br i1 %cmp, label %for.body, label %for.end + +for.end: + ret void +} + +declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 +declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vrmpybusi(<32 x i32>, i32, i32) #1 +declare <32 x i32> @llvm.hexagon.V6.vrmpybusi.acc(<32 x i32>, <32 x i32>, i32, i32) #1 +declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1 +declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 +declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { nounwind readnone } + +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/v60Intrins.ll b/test/CodeGen/Hexagon/v60Intrins.ll index 5f4f294c405b..d0064c50e71d 100644 --- a/test/CodeGen/Hexagon/v60Intrins.ll +++ b/test/CodeGen/Hexagon/v60Intrins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -disable-post-ra < %s | FileCheck %s ; CHECK: q{{[0-3]}} = vand(v{{[0-9]*}},r{{[0-9]*}}) ; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]*}}) diff --git a/test/CodeGen/Hexagon/vec-pred-spill1.ll b/test/CodeGen/Hexagon/vec-pred-spill1.ll new file mode 100644 index 000000000000..d120295fa52c --- /dev/null +++ b/test/CodeGen/Hexagon/vec-pred-spill1.ll @@ -0,0 +1,80 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s + +; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} +; CHECK: call puts +; CHECK: call print_vecpred +; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3) + +target triple = "hexagon" + +@K = global i64 0, align 8 +@src = global i32 -1, align 4 +@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 +@dst_addresses = common global [15 x i64] zeroinitializer, align 8 +@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8 +@src_addresses = common global [15 x i8*] zeroinitializer, align 8 +@ptr = common global [32768 x i32] zeroinitializer, align 8 +@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64 +@VectorResult = common global <16 x i32> zeroinitializer, align 64 +@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64 +@VectorPairResult = common global <32 x i32> zeroinitializer, align 128 +@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128 +@str = private unnamed_addr constant [106 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),INT32_MIN)\00" +@str3 = private unnamed_addr constant [99 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),-1)\00" +@str4 = private unnamed_addr constant [98 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),0)\00" + +; Function Attrs: nounwind +define i32 @main() #0 { +entry: + %call = tail call i32 bitcast (i32 (...)* @init_addresses to i32 ()*)() #3 + %call1 = tail call i32 @acquire_vector_unit(i8 zeroext 0) #3 + tail call void @init_vectors() #3 + %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) + %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009) + %2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %3 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -2147483648) + %4 = bitcast <512 x i1> %3 to <16 x i32> + store <16 x i32> %4, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 + %puts = tail call i32 @puts(i8* getelementptr inbounds ([106 x i8], [106 x i8]* @str, i32 0, i32 0)) + tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 + %5 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -1) + %6 = bitcast <512 x i1> %5 to <16 x i32> + store <16 x i32> %6, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 + %puts5 = tail call i32 @puts(i8* getelementptr inbounds ([99 x i8], [99 x i8]* @str3, i32 0, i32 0)) + tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 + %7 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 0) + %8 = bitcast <512 x i1> %7 to <16 x i32> + store <16 x i32> %8, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1 + %puts6 = tail call i32 @puts(i8* getelementptr inbounds ([98 x i8], [98 x i8]* @str4, i32 0, i32 0)) + tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 + ret i32 0 +} + +declare i32 @init_addresses(...) #1 + +declare i32 @acquire_vector_unit(i8 zeroext) #1 + +declare void @init_vectors() #1 + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1>, <16 x i32>, i32) #2 + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #2 + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #2 + +declare void @print_vecpred(i32, i8*) #1 + +; Function Attrs: nounwind +declare i32 @puts(i8* nocapture readonly) #3 + +attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind readnone } +attributes #3 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/vector-align.ll b/test/CodeGen/Hexagon/vector-align.ll new file mode 100644 index 000000000000..557ee3f97f2e --- /dev/null +++ b/test/CodeGen/Hexagon/vector-align.ll @@ -0,0 +1,38 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ +; RUN: | FileCheck %s + +; Check that the store to Q6VecPredResult does not get expanded into multiple +; stores. There should be no memd's. This relies on the alignment specified +; in the data layout string, so don't provide one here to make sure that the +; default one from HexagonTargetMachine is correct. + +; CHECK-NOT: memd + + +@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64 + +; Function Attrs: nounwind +define i32 @foo() #0 { +entry: + %0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) + %1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 -2147483648) + store <512 x i1> %1, <512 x i1>* bitcast (<16 x i32>* @Q6VecPredResult to <512 x i1>*), align 64, !tbaa !1 + tail call void @print_vecpred(i32 64, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3 + ret i32 0 +} + +; Function Attrs: nounwind readnone +declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1 + +; Function Attrs: nounwind readnone +declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1 + +declare void @print_vecpred(i32, i8*) #2 + +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { nounwind readnone } +attributes #2 = { nounwind } + +!1 = !{!2, !2, i64 0} +!2 = !{!"omnipotent char", !3, i64 0} +!3 = !{!"Simple C/C++ TBAA"} diff --git a/test/CodeGen/Hexagon/vload-postinc-sel.ll b/test/CodeGen/Hexagon/vload-postinc-sel.ll new file mode 100644 index 000000000000..70ed3a9b1e8d --- /dev/null +++ b/test/CodeGen/Hexagon/vload-postinc-sel.ll @@ -0,0 +1,52 @@ +; RUN: llc -march=hexagon < %s | FileCheck %s +; CHECK: = vmem(r{{[0-9]+}}++#1) + +target triple = "hexagon-unknown--elf" + +declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #0 +declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #0 +declare <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32>) #0 +declare <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32>, <32 x i32>) #0 +declare <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32>, <64 x i32>) #0 +declare <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32>, <64 x i32>) #0 +declare <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32>, <32 x i32>) #0 + +define void @fred() #1 { +entry: + br i1 undef, label %b1, label %call_destructor.exit + +b1: ; preds = %entry + br label %b2 + +b2: ; preds = %b1, %b2 + %c2.host32.sroa.3.0 = phi <128 x i8> [ %5, %b2 ], [ undef, %b1 ] + %sobel_halide.s0.x.x = phi i32 [ %17, %b2 ], [ 0, %b1 ] + %0 = add nsw i32 %sobel_halide.s0.x.x, undef + %1 = shl i32 %0, 7 + %2 = add nsw i32 %1, 128 + %3 = getelementptr inbounds i8, i8* undef, i32 %2 + %4 = bitcast i8* %3 to <128 x i8>* + %5 = load <128 x i8>, <128 x i8>* %4, align 128 + %6 = bitcast <128 x i8> %c2.host32.sroa.3.0 to <32 x i32> + %7 = tail call <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32> undef, <32 x i32> %6, i32 1) + %8 = tail call <64 x i32> @llvm.hexagon.V6.vzb.128B(<32 x i32> %7) #1 + %9 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> undef, <64 x i32> %8) #1 + %10 = tail call <64 x i32> @llvm.hexagon.V6.vadduhsat.dv.128B(<64 x i32> %9, <64 x i32> undef) #1 + %11 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %10) + %12 = tail call <32 x i32> @llvm.hexagon.V6.vabsdiffuh.128B(<32 x i32> undef, <32 x i32> %11) #1 + %13 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> %12, <32 x i32> undef) + %14 = tail call <64 x i32> @llvm.hexagon.V6.vaddh.dv.128B(<64 x i32> undef, <64 x i32> %13) #1 + %15 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %14) #1 + %16 = tail call <32 x i32> @llvm.hexagon.V6.vsathub.128B(<32 x i32> %15, <32 x i32> undef) #1 + store <32 x i32> %16, <32 x i32>* undef, align 128 + %17 = add nuw nsw i32 %sobel_halide.s0.x.x, 1 + br label %b2 + +call_destructor.exit: ; preds = %entry + ret void +} + +declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } diff --git a/test/CodeGen/Hexagon/vselect-pseudo.ll b/test/CodeGen/Hexagon/vselect-pseudo.ll new file mode 100644 index 000000000000..ef86e47e3959 --- /dev/null +++ b/test/CodeGen/Hexagon/vselect-pseudo.ll @@ -0,0 +1,33 @@ +; RUN: llc -march=hexagon < %s +; REQUIRES: asserts + +target triple = "hexagon" + +; Function Attrs: nounwind +define void @fred() #0 { +entry: + br label %for.body9.us + +for.body9.us: + %cmp10.us = icmp eq i32 0, undef + %.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef + %0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2) + %1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1> undef, <16 x i32> undef, <16 x i32> %0) + %2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1) + %3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62) + %4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3) + store <16 x i32> %4, <16 x i32>* undef, align 64 + br i1 undef, label %for.body9.us, label %for.body43.us.preheader + +for.body43.us.preheader: ; preds = %for.body9.us + ret void +} + +declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1 +declare <32 x i32> @llvm.hexagon.V6.vswap(<512 x i1>, <16 x i32>, <16 x i32>) #1 +declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 +declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1 +declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/test/CodeGen/Hexagon/vsplat-isel.ll b/test/CodeGen/Hexagon/vsplat-isel.ll new file mode 100644 index 000000000000..9c5e3e17c4e8 --- /dev/null +++ b/test/CodeGen/Hexagon/vsplat-isel.ll @@ -0,0 +1,10 @@ +; RUN: llc -march=hexagon -O0 < %s | FileCheck %s +; CHECK: vsplatb + +declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0 + +define i32 @foo(i8 %x) { + %p0 = zext i8 %x to i32 + %p1 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %p0) + ret i32 %p1 +} diff --git a/test/CodeGen/Hexagon/zextloadi1.ll b/test/CodeGen/Hexagon/zextloadi1.ll index 9ce7bea9fce6..582120d0f355 100644 --- a/test/CodeGen/Hexagon/zextloadi1.ll +++ b/test/CodeGen/Hexagon/zextloadi1.ll @@ -1,23 +1,28 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s - -; CHECK: r{{[0-9]+}} = ##i129_l+16 -; CHECK: r{{[0-9]+}} = ##i129_s+16 -; CHECK: memd(##i129_s) = r{{[0-9]+:[0-9]+}} -; CHECK: r{{[0-9]+}} = ##i65_l+8 -; CHECK: r{{[0-9]+}} = ##i65_s+8 -; CHECK: memd(##i65_s) = r{{[0-9]+:[0-9]+}} +; RUN: llc -march=hexagon < %s | FileCheck %s @i65_l = external global i65 @i65_s = external global i65 @i129_l = external global i129 @i129_s = external global i129 +; CHECK-LABEL: i129_ls +; CHECK-DAG: r[[REG0:[0-9:]+]] = memd(##i129_l) +; CHECK-DAG: r[[REG1:[0-9:]+]] = memd(##i129_l+8) +; CHECK-DAG: r[[REG2:[0-9]+]] = memub(##i129_l+16) +; CHECK-DAG: memb(##i129_s+16) = r[[REG2]] +; CHECK-DAG: memd(##i129_s+8) = r[[REG1]] +; CHECK-DAG: memd(##i129_s) = r[[REG0]] define void @i129_ls() nounwind { %tmp = load i129, i129* @i129_l store i129 %tmp, i129* @i129_s ret void } +; CHECK-LABEL: i65_ls +; CHECK-DAG: r[[REG0:[0-9:]+]] = memd(##i65_l) +; CHECK-DAG: r[[REG1:[0-9]+]] = memub(##i65_l+8) +; CHECK-DAG: memd(##i65_s) = r[[REG0]] +; CHECK-DAG: memb(##i65_s+8) = r[[REG1]] define void @i65_ls() nounwind { %tmp = load i65, i65* @i65_l store i65 %tmp, i65* @i65_s diff --git a/test/CodeGen/Inputs/DbgValueOtherTargets.ll b/test/CodeGen/Inputs/DbgValueOtherTargets.ll index 440073fea153..ce015c0727ca 100644 --- a/test/CodeGen/Inputs/DbgValueOtherTargets.ll +++ b/test/CodeGen/Inputs/DbgValueOtherTargets.ll @@ -14,9 +14,9 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!2} !llvm.module.flags = !{!13} -!0 = distinct !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, file: !12, scope: !1, type: !3) +!0 = distinct !DISubprogram(name: "main", line: 2, isLocal: false, isDefinition: true, virtualIndex: 6, isOptimized: false, unit: !2, file: !12, scope: !1, type: !3) !1 = !DIFile(filename: "/tmp/x.c", directory: "/Users/manav") -!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 120996)", isOptimized: false, emissionKind: 0, file: !12, enums: !6, retainedTypes: !6, subprograms: !11) +!2 = distinct !DICompileUnit(language: DW_LANG_C99, producer: "clang version 2.9 (trunk 120996)", isOptimized: false, emissionKind: FullDebug, file: !12, enums: !6, retainedTypes: !6) !3 = !DISubroutineType(types: !4) !4 = !{!5} !5 = !DIBasicType(tag: DW_TAG_base_type, name: "int", size: 32, align: 32, encoding: DW_ATE_signed) @@ -25,6 +25,5 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !8 = distinct !DILexicalBlock(line: 2, column: 12, file: !12, scope: !0) !9 = !DILocation(line: 3, column: 11, scope: !8) !10 = !DILocation(line: 4, column: 2, scope: !8) -!11 = !{!0} !12 = !DIFile(filename: "/tmp/x.c", directory: "/Users/manav") !13 = !{i32 1, !"Debug Info Version", i32 3} diff --git a/test/CodeGen/Lanai/codemodel.ll b/test/CodeGen/Lanai/codemodel.ll new file mode 100644 index 000000000000..e5ec7265924e --- /dev/null +++ b/test/CodeGen/Lanai/codemodel.ll @@ -0,0 +1,30 @@ +; RUN: llc -march=lanai < %s | FileCheck %s +; RUN: llc -march=lanai < %s -code-model=small | FileCheck -check-prefix CHECK-SMALL %s + +@data = external global [0 x i32] ; <[0 x i32]*> [#uses=5] + +define i32 @foo() nounwind readonly { +entry: +; CHECK-SMALL-LABEL: foo: +; CHECK-SMALL: ld [data], %rv +; CHECK-LABEL: foo: +; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]] +; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]] +; CHECK: ld 0[%r[[REGISTER]]], %rv + %0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i64 0, i64 0), align 4 ; [#uses=1] + ret i32 %0 +} + +define i32 @foo1() nounwind readonly { +entry: +; CHECK-SMALL-LABEL: foo1: +; CHECK-SMALL: mov data, %r[[REGISTER:[0-9]+]] +; CHECK-SMALL: ld 40[%r[[REGISTER]]], %rv +; CHECK-LABEL: foo1: +; CHECK: mov hi(data), %r[[REGISTER:[0-9]+]] +; CHECK: or %r[[REGISTER]], lo(data), %r[[REGISTER]] +; CHECK: ld 40[%r[[REGISTER]]], %rv + %0 = load i32, i32* getelementptr ([0 x i32], [0 x i32]* @data, i32 0, i64 10), align 4 ; [#uses=1] + ret i32 %0 +} + diff --git a/test/CodeGen/Lanai/comparisons_i32.ll b/test/CodeGen/Lanai/comparisons_i32.ll new file mode 100644 index 000000000000..fd8ca725c4cb --- /dev/null +++ b/test/CodeGen/Lanai/comparisons_i32.ll @@ -0,0 +1,96 @@ +; RUN: llc < %s | FileCheck %s + +; Test that basic 32-bit integer comparison operations assemble as expected. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; CHECK-LABEL: eq_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: seq +define i32 @eq_i32(i32 %x, i32 %y) { + %a = icmp eq i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ne_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sne +define i32 @ne_i32(i32 %x, i32 %y) { + %a = icmp ne i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: slt_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: slt +define i32 @slt_i32(i32 %x, i32 %y) { + %a = icmp slt i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sle_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sle +define i32 @sle_i32(i32 %x, i32 %y) { + %a = icmp sle i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ult_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sult +define i32 @ult_i32(i32 %x, i32 %y) { + %a = icmp ult i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ule_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sule +define i32 @ule_i32(i32 %x, i32 %y) { + %a = icmp ule i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sgt_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sgt +define i32 @sgt_i32(i32 %x, i32 %y) { + %a = icmp sgt i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sge_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sge +define i32 @sge_i32(i32 %x, i32 %y) { + %a = icmp sge i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ugt_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: sugt +define i32 @ugt_i32(i32 %x, i32 %y) { + %a = icmp ugt i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: uge_i32: +; CHECK: sub.f %r{{[0-9]+}}, %r{{[0-9]+}}, %r0 +; CHECK-NEXT: suge +define i32 @uge_i32(i32 %x, i32 %y) { + %a = icmp uge i32 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} diff --git a/test/CodeGen/Lanai/comparisons_i64.ll b/test/CodeGen/Lanai/comparisons_i64.ll new file mode 100644 index 000000000000..853ac139b2d6 --- /dev/null +++ b/test/CodeGen/Lanai/comparisons_i64.ll @@ -0,0 +1,108 @@ +; RUN: llc < %s | FileCheck %s + +; Test that basic 64-bit integer comparison operations assemble as expected. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; CHECK-LABEL: eq_i64: +; CHECK: xor +; CHECK: xor +; CHECK: or.f +; CHECK-NEXT: seq +define i32 @eq_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp eq i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ne_i64: +; CHECK: xor +; CHECK: xor +; CHECK: or.f +; CHECK-NEXT: sne +define i32 @ne_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp ne i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: slt_i64: +; CHECK: sub.f %r7, %r19, %r3 +; CHECK: subb.f %r6, %r18, %r3 +; CHECK-NEXT: slt +define i32 @slt_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp slt i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sle_i64: +; CHECK: sub.f %r19, %r7, %r3 +; CHECK: subb.f %r18, %r6, %r3 +; CHECK-NEXT: sge %rv +define i32 @sle_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp sle i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ult_i64: +; CHECK: sub.f %r7, %r19, %r3 +; CHECK: subb.f %r6, %r18, %r3 +; CHECK-NEXT: sult %rv +define i32 @ult_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp ult i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ule_i64: +; CHECK: sub.f %r19, %r7, %r3 +; CHECK: subb.f %r18, %r6, %r3 +; CHECK-NEXT: suge %rv +define i32 @ule_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp ule i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sgt_i64: +; CHECK: sub.f %r19, %r7, %r3 +; CHECK: subb.f %r18, %r6, %r3 +; CHECK-NEXT: slt %rv +define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp sgt i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: sge_i64: +; CHECK: sub.f %r7, %r19, %r3 +; CHECK: subb.f %r6, %r18, %r3 +; CHECK-NEXT: sge %rv +define i32 @sge_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp sge i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: ugt_i64: +; CHECK: sub.f %r19, %r7, %r3 +; CHECK: subb.f %r18, %r6, %r3 +; CHECK-NEXT: sult %rv +define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp ugt i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +; CHECK-LABEL: uge_i64: +; CHECK: sub.f %r7, %r19, %r3 +; CHECK: subb.f %r6, %r18, %r3 +; CHECK-NEXT: suge %rv +define i32 @uge_i64(i64 inreg %x, i64 inreg %y) { + %a = icmp uge i64 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} diff --git a/test/CodeGen/Lanai/constant_multiply.ll b/test/CodeGen/Lanai/constant_multiply.ll new file mode 100644 index 000000000000..77c9805e4419 --- /dev/null +++ b/test/CodeGen/Lanai/constant_multiply.ll @@ -0,0 +1,107 @@ +; RUN: llc < %s | FileCheck %s + +; Test custom lowering for 32-bit integer multiplication. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; CHECK-LABEL: f6: +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @f6(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, 6 + ret i32 %1 +} + +; CHECK-LABEL: f7: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r6, %rv +define i32 @f7(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, 7 + ret i32 %1 +} + +; CHECK-LABEL: f8: +; CHECK: sh %r6, 0x3, %rv +define i32 @f8(i32 inreg %a) #0 { + %1 = shl nsw i32 %a, 3 + ret i32 %1 +} + +; CHECK-LABEL: f9: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: add %r{{[0-9]+}}, %r6, %rv +define i32 @f9(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, 9 + ret i32 %1 +} + +; CHECK-LABEL: f10: +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @f10(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, 10 + ret i32 %1 +} + +; CHECK-LABEL: f1280: +; CHECK: sh %r6, 0x8, %r{{[0-9]+}} +; CHECK: sh %r6, 0xa, %r{{[0-9]+}} +; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @f1280(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, 1280 + ret i32 %1 +} + +; CHECK-LABEL: fm6: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @fm6(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, -6 + ret i32 %1 +} + +; CHECK-LABEL: fm7: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r6, %r{{[0-9]+}}, %rv +define i32 @fm7(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, -7 + ret i32 %1 +} + +; CHECK-LABEL: fm8: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @fm8(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, -8 + ret i32 %1 +} + +; CHECK-LABEL: fm9: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r6, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @fm9(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, -9 + ret i32 %1 +} + +; CHECK-LABEL: fm10: +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @fm10(i32 inreg %a) #0 { + %1 = mul nsw i32 %a, -10 + ret i32 %1 +} + +; CHECK-LABEL: h1: +; CHECK: __mulsi3 +define i32 @h1(i32 inreg %a) #0 { + %1 = mul i32 %a, -1431655765 + ret i32 %1 +} diff --git a/test/CodeGen/Lanai/delay_filler.ll b/test/CodeGen/Lanai/delay_filler.ll new file mode 100644 index 000000000000..bb74276d46de --- /dev/null +++ b/test/CodeGen/Lanai/delay_filler.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=lanai < %s | FileCheck %s +; RUN: llc -march=lanai --lanai-nop-delay-filler < %s | \ +; RUN: FileCheck %s --check-prefix=NOP + +; CHECK: bt f +; CHECK-NEXT: or +; NOP: bt f +; NOP-NEXT: nop + +; ModuleID = 'delay_filler.c' +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; Function Attrs: nounwind +define i32 @g(i32 inreg %n) #0 { +entry: + %cmp5 = icmp sgt i32 %n, 0 + br i1 %cmp5, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + %call.lcssa = phi i32 [ %call, %for.body ] + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + %a.0.lcssa = phi i32 [ undef, %entry ], [ %call.lcssa, %for.cond.cleanup.loopexit ] + ret i32 %a.0.lcssa + +for.body: ; preds = %for.body.preheader, %for.body + %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %a.06 = phi i32 [ %call, %for.body ], [ undef, %for.body.preheader ] + %call = tail call i32 @f(i32 inreg %a.06) #2 + %inc = add nuw nsw i32 %i.07, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body +} + +declare i32 @f(i32 inreg) #1 + diff --git a/test/CodeGen/Lanai/i32.ll b/test/CodeGen/Lanai/i32.ll new file mode 100644 index 000000000000..632cc467d681 --- /dev/null +++ b/test/CodeGen/Lanai/i32.ll @@ -0,0 +1,145 @@ +; RUN: llc < %s -asm-verbose=false | FileCheck %s + +; Test that basic 32-bit integer operations assemble as expected. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; Function Attrs: nounwind readnone +declare i32 @llvm.ctpop.i32(i32) #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) #1 + +; Function Attrs: nounwind readnone +declare i32 @llvm.cttz.i32(i32, i1) #1 + +; CHECK-LABEL: add32: +; CHECK: add %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @add32(i32 %x, i32 %y) { + %a = add i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: sub32: +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @sub32(i32 %x, i32 %y) { + %a = sub i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: mul32: +; CHECK: bt __mulsi3 +define i32 @mul32(i32 %x, i32 %y) { + %a = mul i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: sdiv32: +; CHECK: bt __divsi3 +define i32 @sdiv32(i32 %x, i32 %y) { + %a = sdiv i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: udiv32: +; CHECK: bt __udivsi3 +define i32 @udiv32(i32 %x, i32 %y) { + %a = udiv i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: srem32: +; CHECK: bt __modsi3 +define i32 @srem32(i32 %x, i32 %y) { + %a = srem i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: urem32: +; CHECK: bt __umodsi3 +define i32 @urem32(i32 %x, i32 %y) { + %a = urem i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: and32: +; CHECK: and %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @and32(i32 %x, i32 %y) { + %a = and i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: or32: +; CHECK: or %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @or32(i32 %x, i32 %y) { + %a = or i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: xor32: +; CHECK: xor %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @xor32(i32 %x, i32 %y) { + %a = xor i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: shl32: +; CHECK: sh %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @shl32(i32 %x, i32 %y) { + %a = shl i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: shr32: +; CHECK: sub %r0, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sh %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @shr32(i32 %x, i32 %y) { + %a = lshr i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: sar32 +; CHECK: sub %r0, %r{{[0-9]+}}, %r{{[0-9]+}} +; CHECK: sha %r{{[0-9]+}}, %r{{[0-9]+}}, %rv +define i32 @sar32(i32 %x, i32 %y) { + %a = ashr i32 %x, %y + ret i32 %a +} + +; CHECK-LABEL: clz32: +; CHECK: leadz %r{{[0-9]+}}, %rv +define i32 @clz32(i32 %x) { + %a = call i32 @llvm.ctlz.i32(i32 %x, i1 false) + ret i32 %a +} + +; CHECK-LABEL: clz32_zero_undef: +; CHECK-NOT: sub.f +; CHECK: leadz %r{{[0-9]+}}, %rv +define i32 @clz32_zero_undef(i32 %x) { + %a = call i32 @llvm.ctlz.i32(i32 %x, i1 true) + ret i32 %a +} + +; CHECK-LABEL: ctz32: +; CHECK: trailz %r{{[0-9]+}}, %rv +define i32 @ctz32(i32 %x) { + %a = call i32 @llvm.cttz.i32(i32 %x, i1 false) + ret i32 %a +} + +; CHECK-LABEL: ctz32_zero_undef: +; CHECK-NOT: sub.f +; CHECK: trailz %r{{[0-9]+}}, %rv +define i32 @ctz32_zero_undef(i32 %x) { + %a = call i32 @llvm.cttz.i32(i32 %x, i1 true) + ret i32 %a +} + +; CHECK-LABEL: popcnt32: +; CHECK: popc %r{{[0-9]+}}, %rv +define i32 @popcnt32(i32 %x) { + %a = call i32 @llvm.ctpop.i32(i32 %x) + ret i32 %a +} diff --git a/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll new file mode 100644 index 000000000000..619417f02c15 --- /dev/null +++ b/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll @@ -0,0 +1,55 @@ +; RUN: llc %s -mtriple=lanai-unknown-unknown -debug-only=misched -o /dev/null 2>&1 | FileCheck %s + +; Make sure there are no control dependencies between memory operations that +; are trivially disjoint. + +; Function Attrs: norecurse nounwind uwtable +define i32 @foo(i8* inreg nocapture %x) { +entry: + %0 = bitcast i8* %x to i32* + store i32 1, i32* %0, align 4 + %arrayidx1 = getelementptr inbounds i8, i8* %x, i32 4 + %1 = bitcast i8* %arrayidx1 to i32* + store i32 2, i32* %1, align 4 + %arrayidx2 = getelementptr inbounds i8, i8* %x, i32 12 + %2 = bitcast i8* %arrayidx2 to i32* + %3 = load i32, i32* %2, align 4 + %arrayidx3 = getelementptr inbounds i8, i8* %x, i32 10 + %4 = bitcast i8* %arrayidx3 to i16* + store i16 3, i16* %4, align 2 + %5 = bitcast i8* %arrayidx2 to i16* + store i16 4, i16* %5, align 2 + %arrayidx5 = getelementptr inbounds i8, i8* %x, i32 14 + store i8 5, i8* %arrayidx5, align 1 + %arrayidx6 = getelementptr inbounds i8, i8* %x, i32 15 + store i8 6, i8* %arrayidx6, align 1 + %arrayidx7 = getelementptr inbounds i8, i8* %x, i32 16 + store i8 7, i8* %arrayidx7, align 1 + ret i32 %3 +} + +; CHECK-LABEL: foo +; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 0, +; CHECK: # preds left : 2 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): SW_RI{{.*}}, 4, +; CHECK: # preds left : 2 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): %vreg{{.*}} = LDW_RI{{.*}}, 12, +; CHECK: # preds left : 1 +; CHECK: # succs left : 4 +; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 10, +; CHECK: # preds left : 2 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): STH_RI{{.*}}, 12, +; CHECK: # preds left : 3 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 14, +; CHECK: # preds left : 3 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 15, +; CHECK: # preds left : 3 +; CHECK: # succs left : 0 +; CHECK-LABEL: SU({{.*}}): STB_RI{{.*}}, 16, +; CHECK: # preds left : 2 +; CHECK: # succs left : 0 \ No newline at end of file diff --git a/test/CodeGen/Lanai/lit.local.cfg b/test/CodeGen/Lanai/lit.local.cfg new file mode 100644 index 000000000000..3f30d055364c --- /dev/null +++ b/test/CodeGen/Lanai/lit.local.cfg @@ -0,0 +1,3 @@ +if not 'Lanai' in config.root.targets: + config.unsupported = True + diff --git a/test/CodeGen/Lanai/mem_alu_combiner.ll b/test/CodeGen/Lanai/mem_alu_combiner.ll new file mode 100644 index 000000000000..4e6e77361444 --- /dev/null +++ b/test/CodeGen/Lanai/mem_alu_combiner.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -march=lanai | FileCheck %s +; RUN: llc < %s -march=lanai -disable-lanai-mem-alu-combiner | \ +; RUN: FileCheck %s -check-prefix=CHECK-DIS + +; CHECK-LABEL: sum, +; CHECK: ld [%r{{[0-9]+}}++], %r{{[0-9]+}}{{$}} +; CHECK-DIS-LABEL: sum, +; CHECK-DIS-NOT: ++], + +define i32 @sum(i32* inreg nocapture readonly %data, i32 inreg %n) { +entry: + %cmp6 = icmp sgt i32 %n, 0 + br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup + +for.body.preheader: ; preds = %entry + br label %for.body + +for.cond.cleanup.loopexit: ; preds = %for.body + %add.lcssa = phi i32 [ %add, %for.body ] + br label %for.cond.cleanup + +for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry + %sum_.0.lcssa = phi i32 [ 0, %entry ], [ %add.lcssa, %for.cond.cleanup.loopexit ] + ret i32 %sum_.0.lcssa + +for.body: ; preds = %for.body.preheader, %for.body + %i.08 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ] + %sum_.07 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ] + %arrayidx = getelementptr inbounds i32, i32* %data, i32 %i.08 + %0 = load i32, i32* %arrayidx, align 4 + %add = add nsw i32 %0, %sum_.07 + %inc = add nuw nsw i32 %i.08, 1 + %exitcond = icmp eq i32 %inc, %n + br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body +} diff --git a/test/CodeGen/Lanai/multiply.ll b/test/CodeGen/Lanai/multiply.ll new file mode 100644 index 000000000000..c92a06c3f017 --- /dev/null +++ b/test/CodeGen/Lanai/multiply.ll @@ -0,0 +1,60 @@ +; RUN: llc -march=lanai < %s | FileCheck %s + +; Test the in place lowering of mul i32. + +define i32 @f6(i32 inreg %a) #0 { +entry: + %mul = mul nsw i32 %a, 6 + ret i32 %mul +} +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv + +define i32 @f7(i32 inreg %a) #0 { +entry: + %mul = mul nsw i32 %a, 7 + ret i32 %mul +} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r6, %rv + +define i32 @f8(i32 inreg %a) #0 { +entry: + %mul = shl nsw i32 %a, 3 + ret i32 %mul +} +; CHECK: sh %r6, 0x3, %rv + +define i32 @fm6(i32 inreg %a) #0 { +entry: + %mul = mul nsw i32 %a, -6 + ret i32 %mul +} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sh %r6, 0x1, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv + +define i32 @fm7(i32 inreg %a) #0 { +entry: + %mul = mul nsw i32 %a, -7 + ret i32 %mul +} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r6, %r{{[0-9]+}}, %rv + +define i32 @fm8(i32 inreg %a) #0 { +entry: + %mul = mul nsw i32 %a, -8 + ret i32 %mul +} +; CHECK: sh %r6, 0x3, %r{{[0-9]+}} +; CHECK: sub %r{{[0-9]+}}, %r{{[0-9]+}}, %rv + +define i32 @h1(i32 inreg %a) #0 { +entry: + %mul = mul i32 %a, -1431655765 + ret i32 %mul +} +; CHECK: h1 +; CHECK: mulsi3 diff --git a/test/CodeGen/Lanai/rshift64.ll b/test/CodeGen/Lanai/rshift64.ll new file mode 100644 index 000000000000..2009edd001c8 --- /dev/null +++ b/test/CodeGen/Lanai/rshift64.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=lanai-unknown-unknown | FileCheck %s + +; Test right-shift i64 lowering does not result in call being inserted. + +; CHECK-LABEL: shift +; CHECK-NOT: bt __lshrdi3 +; CHECK: %rv +define i64 @shift(i64 inreg, i32 inreg) { + %3 = zext i32 %1 to i64 + %4 = lshr i64 %0, %3 + ret i64 %4 +} diff --git a/test/CodeGen/Lanai/select.ll b/test/CodeGen/Lanai/select.ll new file mode 100644 index 000000000000..0c5b2307ab2c --- /dev/null +++ b/test/CodeGen/Lanai/select.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s | FileCheck %s + +; Test that Lanai select instruction is selected from LLVM select instruction. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +; CHECK-LABEL: select_i32_bool: +; CHECK: sub.f %r6, 0x0, %r0 +; CHECK: sel.ne %r7, %r18, %rv +define i32 @select_i32_bool(i1 zeroext inreg %a, i32 inreg %b, i32 inreg %c) { + %cond = select i1 %a, i32 %b, i32 %c + ret i32 %cond +} + +; CHECK-LABEL: select_i32_eq: +; CHECK: sub.f %r6, 0x0, %r0 +; CHECK: sel.eq %r7, %r18, %rv +define i32 @select_i32_eq(i32 inreg %a, i32 inreg %b, i32 inreg %c) { + %cmp = icmp eq i32 %a, 0 + %cond = select i1 %cmp, i32 %b, i32 %c + ret i32 %cond +} + +; CHECK-LABEL: select_i32_ne: +; CHECK: sub.f %r6, 0x0, %r0 +; CHECK: sel.ne %r7, %r18, %rv +define i32 @select_i32_ne(i32 inreg %a, i32 inreg %b, i32 inreg %c) { + %cmp = icmp ne i32 %a, 0 + %cond = select i1 %cmp, i32 %b, i32 %c + ret i32 %cond +} + +; CHECK-LABEL: select_i32_lt: +; CHECK: sub.f %r6, %r7, %r0 +; CHECK: sel.lt %r6, %r7, %rv +define i32 @select_i32_lt(i32 inreg %x, i32 inreg %y) #0 { + %1 = icmp slt i32 %x, %y + %2 = select i1 %1, i32 %x, i32 %y + ret i32 %2 +} diff --git a/test/CodeGen/Lanai/set_and_hi.ll b/test/CodeGen/Lanai/set_and_hi.ll new file mode 100644 index 000000000000..bfce094050cb --- /dev/null +++ b/test/CodeGen/Lanai/set_and_hi.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s | FileCheck %s + +; Test matching of and_hi. + +target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" +target triple = "lanai" + +@x = common global i32 0, align 4 + +; CHECK-LABEL: setandhi: +; CHECK: mov 0xfffffe4a, %r{{[0-9]+}} +define void @setandhi() #0 { + store volatile i32 -438, i32* @x, align 4 + ret void +} diff --git a/test/CodeGen/Lanai/shift.ll b/test/CodeGen/Lanai/shift.ll new file mode 100644 index 000000000000..df5f91122ed8 --- /dev/null +++ b/test/CodeGen/Lanai/shift.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -march=lanai | FileCheck %s + +; Test lowering of shifts. + +define i32 @irs(i32 inreg %a) #0 { +entry: + %shr = ashr i32 %a, 13 + ret i32 %shr +} +; CHECK-LABEL: irs +; CHECK: sha %r6, -0xd, %rv + +define i32 @urs(i32 inreg %a) #0 { +entry: + %shr = lshr i32 %a, 13 + ret i32 %shr +} +; CHECK-LABEL: urs +; CHECK: sh %r6, -0xd, %rv + +define i32 @ls(i32 inreg %a) #0 { +entry: + %shl = shl i32 %a, 13 + ret i32 %shl +} +; CHECK-LABEL: ls +; CHECK: sh %r6, 0xd, %rv + diff --git a/test/CodeGen/Lanai/stack-frame.ll b/test/CodeGen/Lanai/stack-frame.ll new file mode 100644 index 000000000000..3564658fa0fd --- /dev/null +++ b/test/CodeGen/Lanai/stack-frame.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=lanai < %s -o - | FileCheck %s + +define void @f1() { + %c = alloca i8, align 1 + ret void +} +; CHECK-LABEL: f1: +; CHECK: sub %sp, 0x10 + +define i32 @f2() { + ret i32 1 +} +; CHECK-LABEL: f2: +; CHECK: sub %sp, 0x8 diff --git a/test/CodeGen/Lanai/sub-cmp-peephole.ll b/test/CodeGen/Lanai/sub-cmp-peephole.ll new file mode 100644 index 000000000000..7e88364f273a --- /dev/null +++ b/test/CodeGen/Lanai/sub-cmp-peephole.ll @@ -0,0 +1,109 @@ +; RUN: llc < %s -mtriple=lanai | FileCheck %s + +define i32 @f(i32 inreg %a, i32 inreg %b) nounwind ssp { +entry: +; CHECK-LABEL: f: +; CHECK: sub.f %r6, %r7, [[IN:%.*]] +; CHECK: sel.gt [[IN]], %r0, %rv + %cmp = icmp sgt i32 %a, %b + %sub = sub nsw i32 %a, %b + %sub. = select i1 %cmp, i32 %sub, i32 0 + ret i32 %sub. +} + +define i32 @g(i32 inreg %a, i32 inreg %b) nounwind ssp { +entry: +; CHECK-LABEL: g: +; CHECK: sub.f %r7, %r6, [[IN:%.*]] +; CHECK: sel.lt [[IN]], %r0, %rv + %cmp = icmp slt i32 %a, %b + %sub = sub nsw i32 %b, %a + %sub. = select i1 %cmp, i32 %sub, i32 0 + ret i32 %sub. +} + +define i32 @h(i32 inreg %a, i32 inreg %b) nounwind ssp { +entry: +; CHECK-LABEL: h: +; CHECK: sub.f %r6, 0x3, [[IN:%.*]] +; CHECK: sel.gt [[IN]], %r7, %rv + %cmp = icmp sgt i32 %a, 3 + %sub = sub nsw i32 %a, 3 + %sub. = select i1 %cmp, i32 %sub, i32 %b + ret i32 %sub. +} + +define i32 @i(i32 inreg %a, i32 inreg %b) nounwind readnone ssp { +entry: +; CHECK-LABEL: i: +; CHECK: sub.f %r7, %r6, [[IN:%.*]] +; CHECK: sel.ult [[IN]], %r0, %rv + %cmp = icmp ult i32 %a, %b + %sub = sub i32 %b, %a + %sub. = select i1 %cmp, i32 %sub, i32 0 + ret i32 %sub. +} +; If SR is live-out, we can't remove cmp if there exists a swapped sub. +define i32 @j(i32 inreg %a, i32 inreg %b) nounwind { +entry: +; CHECK-LABEL: j: +; CHECK: sub.f %r7, %r6, %r0 +; CHECK: sub %r6, %r7, %rv + %cmp = icmp eq i32 %b, %a + %sub = sub nsw i32 %a, %b + br i1 %cmp, label %if.then, label %if.else + +if.then: + %cmp2 = icmp sgt i32 %b, %a + %sel = select i1 %cmp2, i32 %sub, i32 %a + ret i32 %sel + +if.else: + ret i32 %sub +} + +declare void @abort() +declare void @exit(i32) +@t = common global i32 0 + +; If the comparison uses the C bit (signed overflow/underflow), we can't +; omit the comparison. +define i32 @cmp_ult0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) { +entry: +; CHECK-LABEL: cmp_ult0 +; CHECK: sub {{.*}}, 0x11, [[IN:%.*]] +; CHECK: sub.f [[IN]], 0x0, %r0 + %load = load i32, i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp ult i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} + +; Same for the V bit. +; TODO: add test that exercises V bit individually (VC/VS). +define i32 @cmp_gt0(i32 inreg %a, i32 inreg %b, i32 inreg %x, i32 inreg %y) { +entry: +; CHECK-LABEL: cmp_gt0 +; CHECK: sub {{.*}}, 0x11, [[IN:%.*]] +; CHECK: sub.f [[IN]], 0x1, %r0 + %load = load i32, i32* @t, align 4 + %sub = sub i32 %load, 17 + %cmp = icmp sgt i32 %sub, 0 + br i1 %cmp, label %if.then, label %if.else + +if.then: + call void @abort() + unreachable + +if.else: + call void @exit(i32 0) + unreachable +} diff --git a/test/CodeGen/Lanai/subword.ll b/test/CodeGen/Lanai/subword.ll new file mode 100644 index 000000000000..c0e1eaf6ad36 --- /dev/null +++ b/test/CodeGen/Lanai/subword.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -mtriple=lanai-unknown-unknown | FileCheck %s + +; Test scheduling of subwords. + +%struct.X = type { i16, i16 } + +define void @f(%struct.X* inreg nocapture %c) #0 { +entry: + %a = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 0 + %0 = load i16, i16* %a, align 2 + %inc = add i16 %0, 1 + store i16 %inc, i16* %a, align 2 + %b = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 1 + %1 = load i16, i16* %b, align 2 + %dec = add i16 %1, -1 + store i16 %dec, i16* %b, align 2 + ret void +} + +; Verify that the two loads occur before the stores. Without memory +; disambiguation and subword schedule, the resultant code was a per subword +; load-modify-store sequence instead of the more optimal schedule where all +; loads occurred before modification and storage. +; CHECK: uld.h +; CHECK-NEXT: uld.h +; CHECK-NEXT: add +; CHECK-NEXT: st.h +; CHECK-NEXT: sub +; CHECK-NEXT: st.h diff --git a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir index cf7572ecad37..9a6f8dbafa00 100644 --- a/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir +++ b/test/CodeGen/MIR/AArch64/cfi-def-cfa.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the .cfi_def_cfa operands # correctly. diff --git a/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir b/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir index b7bac2682c70..f94f09a485d9 100644 --- a/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir +++ b/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir b/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir new file mode 100644 index 000000000000..b3d8c5c3d361 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir @@ -0,0 +1,43 @@ +# RUN: not llc -mtriple=aarch64-apple-ios -run-pass none -o - %s 2> %t.log \ +# RUN: | FileCheck %s --check-prefix=CHECK +# RUN: FileCheck %s -input-file=%t.log --check-prefix=ERR +# RUN: rm -f %t.log +# REQUIRES: global-isel +# This test ensures that the MIR parser errors out when +# generic virtual register definitions are not correct. + +--- | + define void @bar() { ret void } + + define void @baz() { ret void } +... + +--- +name: bar +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: gpr } +registers: + - { id: 0, class: gpr } +body: | + bb.0: + liveins: %w0 + ; ERR: generic virtual registers must have a size + ; ERR-NEXT: %0 + %0 = G_ADD i32 %w0, %w0 +... + +--- +name: baz +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: _ } +registers: + - { id: 0, class: _ } +body: | + bb.0: + liveins: %w0 + ; ERR: generic virtual registers must have a size + ; ERR-NEXT: %0 + %0 = G_ADD i32 %w0, %w0 +... diff --git a/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir b/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir index d4145b8961df..e2a257535314 100644 --- a/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir +++ b/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple=aarch64-none-linux-gnu -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/AArch64/machine-dead-copy.mir b/test/CodeGen/MIR/AArch64/machine-dead-copy.mir new file mode 100644 index 000000000000..90f2f3c09993 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -0,0 +1,71 @@ + +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s + +--- | + define i32 @copyprop1(i32 %a, i32 %b) { ret i32 %a } + define i32 @copyprop2(i32 %a, i32 %b) { ret i32 %a } + define i32 @copyprop3(i32 %a, i32 %b) { ret i32 %a } + define i32 @copyprop4(i32 %a, i32 %b) { ret i32 %a } + declare i32 @foo(i32) +... +--- +# The first copy is dead copy which is not used. +# CHECK-LABEL: name: copyprop1 +# CHECK: bb.0: +# CHECK-NOT: %w20 = COPY +name: copyprop1 +allVRegsAllocated: true +body: | + bb.0: + liveins: %w0, %w1 + %w20 = COPY %w1 + BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 + RET_ReallyLR implicit %w0 +... +--- +# The first copy is not a dead copy which is used in the second copy after the +# call. +# CHECK-LABEL: name: copyprop2 +# CHECK: bb.0: +# CHECK: %w20 = COPY +name: copyprop2 +allVRegsAllocated: true +body: | + bb.0: + liveins: %w0, %w1 + %w20 = COPY %w1 + BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 + %w0 = COPY %w20 + RET_ReallyLR implicit %w0 +... +--- +# Both the first and second copy are dead copies which are not used. +# CHECK-LABEL: name: copyprop3 +# CHECK: bb.0: +# CHECK-NOT: COPY +name: copyprop3 +allVRegsAllocated: true +body: | + bb.0: + liveins: %w0, %w1 + %w20 = COPY %w1 + BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 + %w20 = COPY %w0 + RET_ReallyLR implicit %w0 +... +# The second copy is removed as a NOP copy, after then the first copy become +# dead which should be removed as well. +# CHECK-LABEL: name: copyprop4 +# CHECK: bb.0: +# CHECK-NOT: COPY +name: copyprop4 +allVRegsAllocated: true +body: | + bb.0: + liveins: %w0, %w1 + %w20 = COPY %w0 + %w0 = COPY %w20 + BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0 + RET_ReallyLR implicit %w0 +... + diff --git a/test/CodeGen/MIR/AArch64/machine-scheduler.mir b/test/CodeGen/MIR/AArch64/machine-scheduler.mir new file mode 100644 index 000000000000..9ea5c6811b65 --- /dev/null +++ b/test/CodeGen/MIR/AArch64/machine-scheduler.mir @@ -0,0 +1,35 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o - %s | FileCheck %s + +--- | + define i64 @load_imp-def(i64* nocapture %P, i32 %v) { + entry: + %0 = bitcast i64* %P to i32* + %1 = load i32, i32* %0 + %conv = zext i32 %1 to i64 + %arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1 + %arrayidx1 = bitcast i64* %arrayidx19 to i32* + store i32 %v, i32* %arrayidx1 + %2 = load i64, i64* %arrayidx19 + %and = and i64 %2, 4294967295 + %add = add nuw nsw i64 %and, %conv + ret i64 %add + } +... +--- +# CHECK-LABEL: name: load_imp-def +# CHECK: bb.0.entry: +# CHECK: LDRWui %x0, 0 +# CHECK: LDRWui %x0, 1 +# CHECK: STRWui %w1, %x0, 2 +name: load_imp-def +isSSA: true +body: | + bb.0.entry: + liveins: %w1, %x0 + %w8 = LDRWui %x0, 1, implicit-def %x8 :: (load 4 from %ir.0) + STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1) + %w9 = LDRWui killed %x0, 0, implicit-def %x9 :: (load 4 from %ir.arrayidx19, align 8) + %x0 = ADDXrr killed %x9, killed %x8 + RET_ReallyLR implicit %x0 +... + diff --git a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir index e23a352dff21..e19b618123de 100644 --- a/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir +++ b/test/CodeGen/MIR/AArch64/multiple-lhs-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser can parse multiple register machine # operands before '='. diff --git a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir index 9471516db647..a2ad2092cb0e 100644 --- a/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir +++ b/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s --- | @var = global i64 0 @@ -26,7 +26,7 @@ frameInfo: maxAlignment: 8 # CHECK-LABEL: stack_local # CHECK: stack: -# CHECK_NEXT: { id:0, name:local_var, offset:0, size:8, alignment:8, local-offset: -8 } +# CHECK-NEXT: { id: 0, name: local_var, offset: 0, size: 8, alignment: 8, local-offset: -8 } stack: - { id: 0,name: local_var,offset: 0,size: 8,alignment: 8, local-offset: -8 } body: | diff --git a/test/CodeGen/MIR/AArch64/target-flags.mir b/test/CodeGen/MIR/AArch64/target-flags.mir index e96fce7c2f2b..e0a41015531b 100644 --- a/test/CodeGen/MIR/AArch64/target-flags.mir +++ b/test/CodeGen/MIR/AArch64/target-flags.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s --- | diff --git a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir index 34793880a60b..d4d2ae15af96 100644 --- a/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir +++ b/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir index e20cf376414a..1b67edc6bb43 100644 --- a/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir +++ b/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=amdgcn -mcpu=SI -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir index 839fd3212c61..b0b7ea4eabd0 100644 --- a/test/CodeGen/MIR/AMDGPU/target-index-operands.mir +++ b/test/CodeGen/MIR/AMDGPU/target-index-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=amdgcn -mcpu=SI -start-after postrapseudos -stop-after postrapseudos -o /dev/null %s | FileCheck %s +# RUN: llc -march=amdgcn -mcpu=SI -run-pass none -o - %s | FileCheck %s # This test verifies that the MIR parser can parse target index operands. --- | diff --git a/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir b/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir deleted file mode 100644 index e351713dc290..000000000000 --- a/test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir +++ /dev/null @@ -1,165 +0,0 @@ -# RUN: llc -start-after machine-cp -stop-after=if-converter -mtriple=thumbv7 %s -o /dev/null 2>&1 | FileCheck %s ---- | - ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' - target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" - target triple = "thumbv7" - - %struct.s = type opaque - - ; Function Attrs: nounwind - define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { - entry: - tail call void @llvm.dbg.value(metadata %struct.s* %s, i64 0, metadata !18, metadata !27), !dbg !28 - tail call void @llvm.dbg.value(metadata i32 %u, i64 0, metadata !19, metadata !27), !dbg !28 - tail call void @llvm.dbg.value(metadata i8* %b, i64 0, metadata !20, metadata !27), !dbg !28 - tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 - %cmp = icmp ult i32 %n, 4, !dbg !29 - br i1 %cmp, label %return, label %if.end, !dbg !31 - - if.end: ; preds = %entry - tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 - br label %return, !dbg !33 - - return: ; preds = %if.end, %entry - %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] - ret i32 %retval.0, !dbg !34 - } - - declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 - - ; Function Attrs: nounwind readnone - declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 - - attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #2 = { nounwind readnone } - attributes #3 = { nounwind } - - !llvm.dbg.cu = !{!0} - !llvm.module.flags = !{!22, !23, !24, !25} - !llvm.ident = !{!26} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) - !1 = !DIFile(filename: "", directory: "/Users/compnerd/Source/llvm") - !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, variables: !17) - !5 = !DISubroutineType(types: !6) - !6 = !{!7, !8, !11, !12, !16} - !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) - !8 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !9, size: 32, align: 32) - !9 = !DIDerivedType(tag: DW_TAG_typedef, name: "s", file: !1, line: 5, baseType: !10) - !10 = !DICompositeType(tag: DW_TAG_structure_type, name: "s", file: !1, line: 5, flags: DIFlagFwdDecl) - !11 = !DIBasicType(name: "unsigned int", size: 32, align: 32, encoding: DW_ATE_unsigned) - !12 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !13, size: 32, align: 32) - !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14) - !14 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint8_t", file: !1, line: 2, baseType: !15) - !15 = !DIBasicType(name: "unsigned char", size: 8, align: 8, encoding: DW_ATE_unsigned_char) - !16 = !DIDerivedType(tag: DW_TAG_typedef, name: "size_t", file: !1, line: 3, baseType: !11) - !17 = !{!18, !19, !20, !21} - !18 = !DILocalVariable(name: "s", arg: 1, scope: !4, file: !1, line: 9, type: !8) - !19 = !DILocalVariable(name: "u", arg: 2, scope: !4, file: !1, line: 9, type: !11) - !20 = !DILocalVariable(name: "b", arg: 3, scope: !4, file: !1, line: 9, type: !12) - !21 = !DILocalVariable(name: "n", arg: 4, scope: !4, file: !1, line: 9, type: !16) - !22 = !{i32 2, !"Dwarf Version", i32 4} - !23 = !{i32 2, !"Debug Info Version", i32 3} - !24 = !{i32 1, !"wchar_size", i32 4} - !25 = !{i32 1, !"min_enum_size", i32 4} - !26 = !{!"clang version 3.7.0 (llvm/trunk 237059)"} - !27 = !DIExpression() - !28 = !DILocation(line: 9, scope: !4) - !29 = !DILocation(line: 10, scope: !30) - !30 = distinct !DILexicalBlock(scope: !4, file: !1, line: 10) - !31 = !DILocation(line: 10, scope: !4) - !32 = !DILocation(line: 13, scope: !4) - !33 = !DILocation(line: 14, scope: !4) - !34 = !DILocation(line: 15, scope: !4) - -... ---- -name: f -alignment: 1 -exposesReturnsTwice: false -hasInlineAsm: false -isSSA: false -tracksRegLiveness: true -tracksSubRegLiveness: false -liveins: - - { reg: '%r0' } - - { reg: '%r2' } - - { reg: '%r3' } -calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', - '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', - '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', - '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', - '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', - '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', - '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', - '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', - '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', - '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', - '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', - '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', - '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', - '%d11_d12_d13_d14' ] -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 8 - offsetAdjustment: 0 - maxAlignment: 4 - adjustsStack: true - hasCalls: true - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false - savePoint: '%bb.2.if.end' - restorePoint: '%bb.2.if.end' -stack: - - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } - - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } -body: | - bb.0.entry: - successors: %bb.1, %bb.2.if.end - liveins: %r0, %r2, %r3, %lr, %r7 - - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 - t2CMPri %r3, 4, 14, _, implicit-def %cpsr, debug-location !31 - t2Bcc %bb.2.if.end, 2, killed %cpsr - - bb.1: - liveins: %lr, %r7 - - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - %r0 = t2MOVi -1, 14, _, _ - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - tBX_RET 14, _, implicit %r0, debug-location !34 - - bb.2.if.end: - liveins: %r0, %r2, %r3, %r7, %lr - - %sp = frame-setup t2STMDB_UPD %sp, 14, _, killed %r7, killed %lr - frame-setup CFI_INSTRUCTION .cfi_def_cfa_offset 8 - frame-setup CFI_INSTRUCTION .cfi_offset %lr, -4 - frame-setup CFI_INSTRUCTION .cfi_offset %r7, -8 - DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 - DBG_VALUE debug-use %r3, debug-use _, !21, !27, debug-location !28 - %r1 = COPY killed %r2, debug-location !32 - %r2 = COPY killed %r3, debug-location !32 - tBL 14, _, @g, csr_aapcs, implicit-def dead %lr, implicit %sp, implicit %r0, implicit %r1, implicit %r2, implicit-def %sp, debug-location !32 - %r0 = t2MOVi 0, 14, _, _ - %sp = t2LDMIA_UPD %sp, 14, _, def %r7, def %lr - DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 - tBX_RET 14, _, implicit %r0, debug-location !34 -# Verify that the DBG_VALUE is ignored. -# CHECK: %sp = t2LDMIA_RET %sp, 14, _, def %r7, def %pc, implicit %r0 - -... diff --git a/test/CodeGen/MIR/ARM/bundled-instructions.mir b/test/CodeGen/MIR/ARM/bundled-instructions.mir index 814c4e188ea5..56e21e362707 100644 --- a/test/CodeGen/MIR/ARM/bundled-instructions.mir +++ b/test/CodeGen/MIR/ARM/bundled-instructions.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple thumbv7-apple-ios -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the bundled machine instructions # and 'internal' register flags correctly. diff --git a/test/CodeGen/MIR/ARM/cfi-same-value.mir b/test/CodeGen/MIR/ARM/cfi-same-value.mir index f9850abe0463..32d0a85b5484 100644 --- a/test/CodeGen/MIR/ARM/cfi-same-value.mir +++ b/test/CodeGen/MIR/ARM/cfi-same-value.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=arm-linux-unknown-gnueabi -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=arm-linux-unknown-gnueabi -run-pass none -o - %s | FileCheck %s --- | declare void @dummy_use(i32*, i32) diff --git a/test/CodeGen/MIR/ARM/expected-closing-brace.mir b/test/CodeGen/MIR/ARM/expected-closing-brace.mir index 78d91aead247..4304935067ad 100644 --- a/test/CodeGen/MIR/ARM/expected-closing-brace.mir +++ b/test/CodeGen/MIR/ARM/expected-closing-brace.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple thumbv7-apple-ios -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @G = external global i32 diff --git a/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir b/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir index a069dd307936..fcd938efbb91 100644 --- a/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir +++ b/test/CodeGen/MIR/ARM/extraneous-closing-brace-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple thumbv7-apple-ios -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test1(i32 %a) { diff --git a/test/CodeGen/MIR/ARM/imm-peephole-arm.mir b/test/CodeGen/MIR/ARM/imm-peephole-arm.mir new file mode 100644 index 000000000000..cd30bdb74d57 --- /dev/null +++ b/test/CodeGen/MIR/ARM/imm-peephole-arm.mir @@ -0,0 +1,60 @@ +# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s + +# CHECK: [[IN:%.*]] = COPY %r0 +# CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133 +# CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600 + +# CHECK: [[SUM2TMP:%.*]] = SUBri [[IN]], 133 +# CHECK: [[SUM2:%.*]] = SUBri killed [[SUM2TMP]], 25600 + +# CHECK: [[SUM3TMP:%.*]] = SUBri [[IN]], 133 +# CHECK: [[SUM3:%.*]] = SUBri killed [[SUM3TMP]], 25600 + +# CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133 +# CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600 + + +--- | + target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" + target triple = "armv7-apple-ios" + + define i32 @foo(i32 %in) { + ret i32 undef + } +... +--- +name: foo +registers: + - { id: 0, class: gprnopc } + - { id: 1, class: rgpr } + - { id: 2, class: rgpr } + - { id: 3, class: rgpr } + - { id: 4, class: rgpr } + - { id: 5, class: rgpr } + - { id: 6, class: rgpr } + - { id: 7, class: rgpr } + - { id: 8, class: rgpr } +liveins: + - { reg: '%r0', virtual-reg: '%0' } +body: | + bb.0 (%ir-block.0): + liveins: %r0 + + %0 = COPY %r0 + %1 = MOVi32imm -25733 + %2 = SUBrr %0, killed %1, 14, _, _ + + %3 = MOVi32imm 25733 + %4 = SUBrr %0, killed %3, 14, _, _ + + %5 = MOVi32imm -25733 + %6 = ADDrr %0, killed %5, 14, _, _ + + %7 = MOVi32imm 25733 + %8 = ADDrr killed %0, killed %7, 14, _, _ + + %r0 = COPY killed %8 + BX_RET 14, _, implicit %r0 + +... + diff --git a/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir b/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir new file mode 100644 index 000000000000..3d342902d80d --- /dev/null +++ b/test/CodeGen/MIR/ARM/imm-peephole-thumb.mir @@ -0,0 +1,59 @@ +# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s + +# CHECK: [[IN:%.*]] = COPY %r0 +# CHECK: [[SUM1TMP:%.*]] = t2ADDri [[IN]], 25600 +# CHECK: [[SUM1:%.*]] = t2ADDri killed [[SUM1TMP]], 133 + +# CHECK: [[SUM2TMP:%.*]] = t2SUBri [[IN]], 25600 +# CHECK: [[SUM2:%.*]] = t2SUBri killed [[SUM2TMP]], 133 + +# CHECK: [[SUM3TMP:%.*]] = t2SUBri [[IN]], 25600 +# CHECK: [[SUM3:%.*]] = t2SUBri killed [[SUM3TMP]], 133 + +# CHECK: [[SUM4TMP:%.*]] = t2ADDri killed [[IN]], 25600 +# CHECK: [[SUM4:%.*]] = t2ADDri killed [[SUM4TMP]], 133 + + +--- | + target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" + target triple = "thumbv7-apple-ios" + + define i32 @foo(i32 %in) { + ret i32 undef + } +... +--- +name: foo +registers: + - { id: 0, class: gprnopc } + - { id: 1, class: rgpr } + - { id: 2, class: rgpr } + - { id: 3, class: rgpr } + - { id: 4, class: rgpr } + - { id: 5, class: rgpr } + - { id: 6, class: rgpr } + - { id: 7, class: rgpr } + - { id: 8, class: rgpr } +liveins: + - { reg: '%r0', virtual-reg: '%0' } +body: | + bb.0 (%ir-block.0): + liveins: %r0 + %0 = COPY %r0 + %1 = t2MOVi32imm -25733 + %2 = t2SUBrr %0, killed %1, 14, _, _ + + %3 = t2MOVi32imm 25733 + %4 = t2SUBrr %0, killed %3, 14, _, _ + + %5 = t2MOVi32imm -25733 + %6= t2ADDrr %0, killed %5, 14, _, _ + + %7 = t2MOVi32imm 25733 + %8 = t2ADDrr killed %0, killed %7, 14, _, _ + + %r0 = COPY killed %8 + tBX_RET 14, _, implicit %r0 + +... + diff --git a/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir b/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir index b93697857e79..63b997046d02 100644 --- a/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir +++ b/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -mtriple thumbv7-apple-ios -start-after block-placement -stop-after block-placement -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -mtriple thumbv7-apple-ios -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test1(i32 %a) { diff --git a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir index 5b5750b8d1e8..eb4a44b7e175 100644 --- a/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ b/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -1,11 +1,11 @@ -# RUN: llc -mtriple thumbv7 -start-after if-converter -print-before=post-RA-sched -print-after=post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s +# RUN: llc -mtriple thumbv7 -verify-machineinstrs -start-after if-converter -print-before post-RA-sched -print-after post-RA-sched %s -o /dev/null 2>&1 | FileCheck %s --- | ; ModuleID = '/Volumes/Data/llvm/test/CodeGen/ARM/sched-it-debug-nodes.ll' target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" target triple = "thumbv7" - + %struct.s = type opaque - + ; Function Attrs: nounwind define arm_aapcscc i32 @f(%struct.s* %s, i32 %u, i8* %b, i32 %n) #0 !dbg !4 { entry: @@ -15,11 +15,11 @@ tail call void @llvm.dbg.value(metadata i32 %n, i64 0, metadata !21, metadata !27), !dbg !28 %cmp = icmp ult i32 %n, 4, !dbg !29 br i1 %cmp, label %return, label %if.end, !dbg !31 - + if.end: ; preds = %entry tail call arm_aapcscc void @g(%struct.s* %s, i8* %b, i32 %n) #3, !dbg !32 br label %return, !dbg !33 - + return: ; preds = %if.end, %entry %retval.0 = phi i32 [ 0, %if.end ], [ -1, %entry ] ret i32 %retval.0, !dbg !34 @@ -31,30 +31,29 @@ ; attempts to schedule the Machine Instr, and tries to tag the register in the ; debug value as KILL'ed, resulting in a DEBUG_VALUE node changing codegen! (or ; hopefully, triggering an assert). - + ; CHECK: BUNDLE %ITSTATE ; CHECK: * DBG_VALUE %R1, %noreg, !"u" ; CHECK-NOT: * DBG_VALUE %R1, %noreg, !"u" - + declare arm_aapcscc void @g(%struct.s*, i8*, i32) #1 - + ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 - + attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } - + !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22, !23, !24, !25} !llvm.ident = !{!26} - - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0 (llvm/trunk 237059)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "", directory: "/Users/compnerd/Source/llvm") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, variables: !17) + !4 = distinct !DISubprogram(name: "f", scope: !1, file: !1, line: 9, type: !5, isLocal: false, isDefinition: true, scopeLine: 9, flags: DIFlagPrototyped, isOptimized: true, unit: !0, variables: !17) !5 = !DISubroutineType(types: !6) !6 = !{!7, !8, !11, !12, !16} !7 = !DIBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed) @@ -92,28 +91,30 @@ name: f alignment: 1 exposesReturnsTwice: false hasInlineAsm: false +allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false -liveins: +liveins: - { reg: '%r0' } + - { reg: '%r1' } - { reg: '%r2' } - { reg: '%r3' } -calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', - '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', - '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', - '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', - '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', - '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', - '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', - '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', - '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', - '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', - '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', - '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', - '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', +calleeSavedRegisters: [ '%lr', '%d8', '%d9', '%d10', '%d11', '%d12', '%d13', + '%d14', '%d15', '%q4', '%q5', '%q6', '%q7', '%r4', + '%r5', '%r6', '%r7', '%r8', '%r9', '%r10', '%r11', + '%s16', '%s17', '%s18', '%s19', '%s20', '%s21', + '%s22', '%s23', '%s24', '%s25', '%s26', '%s27', + '%s28', '%s29', '%s30', '%s31', '%d8_d10', '%d9_d11', + '%d10_d12', '%d11_d13', '%d12_d14', '%d13_d15', + '%q4_q5', '%q5_q6', '%q6_q7', '%q4_q5_q6_q7', '%r4_r5', + '%r6_r7', '%r8_r9', '%r10_r11', '%d8_d9_d10', '%d9_d10_d11', + '%d10_d11_d12', '%d11_d12_d13', '%d12_d13_d14', + '%d13_d14_d15', '%d8_d10_d12', '%d9_d11_d13', '%d10_d12_d14', + '%d11_d13_d15', '%d8_d10_d12_d14', '%d9_d11_d13_d15', + '%d9_d10', '%d11_d12', '%d13_d14', '%d9_d10_d11_d12', '%d11_d12_d13_d14' ] -frameInfo: +frameInfo: isFrameAddressTaken: false isReturnAddressTaken: false hasStackMap: false @@ -127,13 +128,13 @@ frameInfo: hasOpaqueSPAdjustment: false hasVAStart: false hasMustTailInVarArgFunc: false -stack: +stack: - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%lr' } - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '%r7' } body: | bb.0.entry: - liveins: %r0, %r2, %r3, %lr, %r7 - + liveins: %r0, %r1, %r2, %r3, %lr, %r7 + DBG_VALUE debug-use %r0, debug-use _, !18, !27, debug-location !28 DBG_VALUE debug-use %r1, debug-use _, !19, !27, debug-location !28 DBG_VALUE debug-use %r2, debug-use _, !20, !27, debug-location !28 diff --git a/test/CodeGen/MIR/Generic/basic-blocks.mir b/test/CodeGen/MIR/Generic/basic-blocks.mir index 22f8d28290db..0df7a9c8c633 100644 --- a/test/CodeGen/MIR/Generic/basic-blocks.mir +++ b/test/CodeGen/MIR/Generic/basic-blocks.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine functions correctly. --- | diff --git a/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir index 892258666d10..040ab7c44c4a 100644 --- a/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir +++ b/test/CodeGen/MIR/Generic/expected-colon-after-basic-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir index a5e04f86c6d1..42996568fe27 100644 --- a/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir +++ b/test/CodeGen/MIR/Generic/expected-mbb-reference-for-successor-mbb.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/Generic/frame-info.mir b/test/CodeGen/MIR/Generic/frame-info.mir index 6e4e3955cb17..71448c8a71ba 100644 --- a/test/CodeGen/MIR/Generic/frame-info.mir +++ b/test/CodeGen/MIR/Generic/frame-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine frame info properties # correctly. diff --git a/test/CodeGen/MIR/Generic/function-missing-machine-function.mir b/test/CodeGen/MIR/Generic/function-missing-machine-function.mir index 71b5b2845340..f3a834801671 100644 --- a/test/CodeGen/MIR/Generic/function-missing-machine-function.mir +++ b/test/CodeGen/MIR/Generic/function-missing-machine-function.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test verifies that an error is reported when a MIR file has some # function but is missing a corresponding machine function. diff --git a/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir index 576de4bd9dc7..5f96d2d57e7c 100644 --- a/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir +++ b/test/CodeGen/MIR/Generic/invalid-jump-table-kind.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir b/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir index 3508c341c44d..15824cb2ca6d 100644 --- a/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir +++ b/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures an error is reported if the embedded LLVM IR contains an # error. diff --git a/test/CodeGen/MIR/Generic/llvmIR.mir b/test/CodeGen/MIR/Generic/llvmIR.mir index c7a220afa505..432b18ff939d 100644 --- a/test/CodeGen/MIR/Generic/llvmIR.mir +++ b/test/CodeGen/MIR/Generic/llvmIR.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the LLVM IR that's embedded with MIR is parsed # correctly. diff --git a/test/CodeGen/MIR/Generic/llvmIRMissing.mir b/test/CodeGen/MIR/Generic/llvmIRMissing.mir index afa96010f297..9f361e8d3fe4 100644 --- a/test/CodeGen/MIR/Generic/llvmIRMissing.mir +++ b/test/CodeGen/MIR/Generic/llvmIRMissing.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s # This test ensures that the MIR parser accepts files without the LLVM IR. --- diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir index d6ecd5dc8514..a5737c2c1526 100644 --- a/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-ir-block-reference.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s 2>&1 | FileCheck %s # This test ensures that the MIR parser preserves unnamed LLVM IR block # references. diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir index 41747535c351..538c3f456b0b 100644 --- a/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir index df559f852ec0..ac9a12b3e44d 100644 --- a/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-undefined-ir-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir index 876947b868b0..98d68f7cd46c 100644 --- a/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir +++ b/test/CodeGen/MIR/Generic/machine-basic-block-unknown-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported whenever the MIR parser can't find # a basic block with the machine basis block's name. diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir b/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir index 0dc7477f6275..1896371db36a 100644 --- a/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-body-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when it encounters a # machine function with an empty body. diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir index 6800f8724324..c547bb25d753 100644 --- a/test/CodeGen/MIR/Generic/machine-function-missing-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-function.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when the mir file has LLVM IR and # one of the machine functions has a name that doesn't match any function in # the LLVM IR. diff --git a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir index f65b77880e97..30f0e51b3b66 100644 --- a/test/CodeGen/MIR/Generic/machine-function-missing-name.mir +++ b/test/CodeGen/MIR/Generic/machine-function-missing-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when a machine function doesn't # have a name attribute. diff --git a/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir b/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir index be84161b5630..a05d5357182e 100644 --- a/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir +++ b/test/CodeGen/MIR/Generic/machine-function-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the machine function errors are reported correctly. --- diff --git a/test/CodeGen/MIR/Generic/machine-function.mir b/test/CodeGen/MIR/Generic/machine-function.mir index 1c4ca3d07d2a..64802a13060e 100644 --- a/test/CodeGen/MIR/Generic/machine-function.mir +++ b/test/CodeGen/MIR/Generic/machine-function.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine functions correctly. --- | diff --git a/test/CodeGen/MIR/Generic/multiRunPass.mir b/test/CodeGen/MIR/Generic/multiRunPass.mir new file mode 100644 index 000000000000..bca007de80b7 --- /dev/null +++ b/test/CodeGen/MIR/Generic/multiRunPass.mir @@ -0,0 +1,20 @@ +# RUN: llc -run-pass expand-isel-pseudos -run-pass peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE +# RUN: llc -run-pass expand-isel-pseudos,peephole-opt -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PSEUDO_PEEPHOLE +# RUN: llc -run-pass peephole-opt -run-pass expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO +# RUN: llc -run-pass peephole-opt,expand-isel-pseudos -debug-pass=Arguments -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=PEEPHOLE_PSEUDO +# REQUIRES: asserts + +# This test ensures that the command line accepts +# several run passes on the same command line and +# actually create the proper pipeline for it. +# PSEUDO_PEEPHOLE: -expand-isel-pseudos -peephole-opt +# PEEPHOLE_PSEUDO: -peephole-opt -expand-isel-pseudos + +# Make sure there are no other passes happening after what we asked. +# CHECK-NEXT: --- | +--- +# CHECK: name: foo +name: foo +body: | + bb.0: +... diff --git a/test/CodeGen/MIR/Generic/register-info.mir b/test/CodeGen/MIR/Generic/register-info.mir index 229cf0f9130f..bf90196b3e6e 100644 --- a/test/CodeGen/MIR/Generic/register-info.mir +++ b/test/CodeGen/MIR/Generic/register-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine register info properties # correctly. diff --git a/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir b/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir new file mode 100644 index 000000000000..a83c53e57cd3 --- /dev/null +++ b/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -0,0 +1,35 @@ +# RUN: llc -march=hexagon -post-RA-scheduler -run-pass post-RA-sched %s -o - | FileCheck %s + +--- | + declare void @check(i64, i32, i32, i64) + define void @foo() { + ret void + } +... + +--- +name: foo +tracksRegLiveness: true +allVRegsAllocated: true +body: | + bb.0: + successors: + liveins: %r0, %r1, %d1, %d2, %r16, %r17, %r19, %r22, %r23 + %r2 = A2_add %r23, killed %r17 + %r6 = M2_mpyi %r16, %r16 + %r22 = M2_accii %r22, killed %r2, 2 + %r7 = A2_tfrsi 12345678 + %r3 = A2_tfr killed %r16 + %d2 = A2_tfrp killed %d0 + %r2 = L2_loadri_io %r29, 28 + %r2 = M2_mpyi killed %r6, killed %r2 + %r23 = S2_asr_i_r %r22, 31 + S2_storeri_io killed %r29, 0, killed %r7 + ; The anti-dependency on r23 between the first A2_add and the + ; S2_asr_i_r was causing d11 to be renamed, while r22 remained + ; unchanged. Check that the renaming of d11 does not happen. + ; CHECK: d11 + %d0 = A2_tfrp killed %d11 + J2_call @check, implicit-def %d0, implicit-def %d1, implicit-def %d2, implicit %d0, implicit %d1, implicit %d2 +... + diff --git a/test/CodeGen/MIR/Hexagon/lit.local.cfg b/test/CodeGen/MIR/Hexagon/lit.local.cfg new file mode 100644 index 000000000000..cc6a7edf05f3 --- /dev/null +++ b/test/CodeGen/MIR/Hexagon/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'Hexagon' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/Lanai/lit.local.cfg b/test/CodeGen/MIR/Lanai/lit.local.cfg new file mode 100644 index 000000000000..f1b8b4f4e21f --- /dev/null +++ b/test/CodeGen/MIR/Lanai/lit.local.cfg @@ -0,0 +1,2 @@ +if not 'Lanai' in config.root.targets: + config.unsupported = True diff --git a/test/CodeGen/MIR/Lanai/peephole-compare.mir b/test/CodeGen/MIR/Lanai/peephole-compare.mir new file mode 100644 index 000000000000..763fe2b9b961 --- /dev/null +++ b/test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -0,0 +1,714 @@ +# RUN: llc -run-pass=peephole-opt %s -o - | FileCheck %s + +# Test the compare fold peephole. + +# CHECK-LABEL: name: test0a +# TODO: Enhance combiner to handle this case. This expands into: +# sub %r7, %r6, %r3 +# sub.f %r7, %r6, %r0 +# sel.eq %r18, %r3, %rv +# This is different from the pattern currently matched. If the lowered form had +# been sub.f %r3, 0, %r0 then it would have matched. + +# CHECK-LABEL: name: test1a +# CHECK: [[IN1:%.*]] = COPY %r7 +# CHECK: [[IN2:%.*]] = COPY %r6 +# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr + +# CHECK-LABEL: name: test1b +# CHECK: [[IN1:%.*]] = COPY %r7 +# CHECK: [[IN2:%.*]] = COPY %r6 +# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr + +# CHECK-LABEL: name: test2a +# CHECK: [[IN1:%.*]] = COPY %r7 +# CHECK: [[IN2:%.*]] = COPY %r6 +# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr + +# CHECK-LABEL: name: test2b +# CHECK: [[IN1:%.*]] = COPY %r7 +# CHECK: [[IN2:%.*]] = COPY %r6 +# CHECK: SUB_F_R [[IN1]], [[IN2]], 0, implicit-def %sr + +# CHECK-LABEL: name: test3 +# CHECK: AND_F_R +# CHECK: AND_F_R +# CHECK: AND_F_R + +--- | + target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64" + target triple = "lanai-unknown-unknown" + + @a = global i32 -1, align 4 + @b = global i32 0, align 4 + + define i32 @test0a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp eq i32 %sub, 0 + %cond = select i1 %cmp, i32 %c, i32 %sub + ret i32 %cond + } + + define i32 @test0b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %cmp = icmp eq i32 %b, %a + %cond = select i1 %cmp, i32 %c, i32 %b + ret i32 %cond + } + + define i32 @test1a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp slt i32 %sub, 0 + %cond = select i1 %cmp, i32 %c, i32 %d + ret i32 %cond + } + + define i32 @test1b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp slt i32 %sub, 0 + %cond = select i1 %cmp, i32 %c, i32 %d + ret i32 %cond + } + + define i32 @test2a(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp sgt i32 %sub, -1 + %cond = select i1 %cmp, i32 %c, i32 %d + ret i32 %cond + } + + define i32 @test2b(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp sgt i32 %sub, -1 + %cond = select i1 %cmp, i32 %c, i32 %d + ret i32 %cond + } + + define i32 @test3(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %sub = sub i32 %b, %a + %cmp = icmp slt i32 %sub, 1 + %cond = select i1 %cmp, i32 %c, i32 %d + ret i32 %cond + } + + define i32 @test4(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) { + entry: + %cmp = icmp ne i32 %a, 0 + %cmp1 = icmp ult i32 %a, %b + %or.cond = and i1 %cmp, %cmp1 + br i1 %or.cond, label %return, label %if.end + + if.end: ; preds = %entry + %cmp2 = icmp ne i32 %b, 0 + %cmp4 = icmp ult i32 %b, %c + %or.cond29 = and i1 %cmp2, %cmp4 + br i1 %or.cond29, label %return, label %if.end6 + + if.end6: ; preds = %if.end + %cmp7 = icmp ne i32 %c, 0 + %cmp9 = icmp ult i32 %c, %d + %or.cond30 = and i1 %cmp7, %cmp9 + br i1 %or.cond30, label %return, label %if.end11 + + if.end11: ; preds = %if.end6 + %cmp12 = icmp ne i32 %d, 0 + %cmp14 = icmp ult i32 %d, %a + %or.cond31 = and i1 %cmp12, %cmp14 + %b. = select i1 %or.cond31, i32 %b, i32 21 + ret i32 %b. + + return: ; preds = %if.end6, %if.end, %entry + %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ] + ret i32 %retval.0 + } + + define void @testBB() { + entry: + %0 = load i32, i32* @a, align 4, !tbaa !0 + %1 = load i32, i32* @b, align 4, !tbaa !0 + %sub.i = sub i32 %1, %0 + %tobool = icmp sgt i32 %sub.i, -1 + br i1 %tobool, label %if.end, label %if.then + + if.then: ; preds = %entry + %call1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() + br label %while.body + + while.body: ; preds = %while.body, %if.then + br label %while.body + + if.end: ; preds = %entry + %cmp.i = icmp slt i32 %sub.i, 1 + br i1 %cmp.i, label %if.then4, label %if.end7 + + if.then4: ; preds = %if.end + %call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)() + br label %while.body6 + + while.body6: ; preds = %while.body6, %if.then4 + br label %while.body6 + + if.end7: ; preds = %if.end + ret void + } + + declare i32 @g(...) + + ; Function Attrs: nounwind + declare void @llvm.stackprotector(i8*, i8**) #0 + + attributes #0 = { nounwind } + + !0 = !{!1, !1, i64 0} + !1 = !{!"int", !2, i64 0} + !2 = !{!"omnipotent char", !3, i64 0} + !3 = !{!"Simple C/C++ TBAA"} + +... +--- +name: test0a +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18 + + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO %4, 0, implicit-def %sr + %5 = SELECT %2, %4, 7, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test0b +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18 + + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + SFSUB_F_RR %1, %0, implicit-def %sr + %4 = SELECT %2, %1, 7, implicit %sr + %rv = COPY %4 + RET implicit %rca, implicit %rv + +... +--- +name: test1a +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } + - { reg: '%r19', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18, %r19 + + %3 = COPY %r19 + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO killed %4, 0, implicit-def %sr + %5 = SELECT %2, %3, 11, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test1b +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } + - { reg: '%r19', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18, %r19 + + %3 = COPY %r19 + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO killed %4, 0, implicit-def %sr + %5 = SELECT %2, %3, 11, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test2a +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } + - { reg: '%r19', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18, %r19 + + %3 = COPY %r19 + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO killed %4, 0, implicit-def %sr + %5 = SELECT %2, %3, 10, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test2b +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } + - { reg: '%r19', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18, %r19 + + %3 = COPY %r19 + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO killed %4, 0, implicit-def %sr + %5 = SELECT %2, %3, 10, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test3 +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%0' } + - { reg: '%r7', virtual-reg: '%1' } + - { reg: '%r18', virtual-reg: '%2' } + - { reg: '%r19', virtual-reg: '%3' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + liveins: %r6, %r7, %r18, %r19 + + %3 = COPY %r19 + %2 = COPY %r18 + %1 = COPY %r7 + %0 = COPY %r6 + %4 = SUB_R %1, %0, 0 + SFSUB_F_RI_LO killed %4, 1, implicit-def %sr + %5 = SELECT %2, %3, 13, implicit %sr + %rv = COPY %5 + RET implicit %rca, implicit %rv + +... +--- +name: test4 +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } + - { id: 9, class: gpr } + - { id: 10, class: gpr } + - { id: 11, class: gpr } + - { id: 12, class: gpr } + - { id: 13, class: gpr } + - { id: 14, class: gpr } + - { id: 15, class: gpr } + - { id: 16, class: gpr } + - { id: 17, class: gpr } + - { id: 18, class: gpr } + - { id: 19, class: gpr } + - { id: 20, class: gpr } + - { id: 21, class: gpr } + - { id: 22, class: gpr } +liveins: + - { reg: '%r6', virtual-reg: '%1' } + - { reg: '%r7', virtual-reg: '%2' } + - { reg: '%r18', virtual-reg: '%3' } + - { reg: '%r19', virtual-reg: '%4' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: false + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + successors: %bb.4.return, %bb.1.if.end + liveins: %r6, %r7, %r18, %r19 + + %4 = COPY %r19 + %3 = COPY %r18 + %2 = COPY %r7 + %1 = COPY %r6 + SFSUB_F_RI_LO %1, 0, implicit-def %sr + %5 = SCC 6, implicit %sr + SFSUB_F_RR %1, %2, implicit-def %sr + %6 = SCC 4, implicit %sr + %7 = AND_R killed %5, killed %6, 0 + %8 = SLI 1 + %9 = AND_R killed %7, %8, 0 + SFSUB_F_RI_LO killed %9, 0, implicit-def %sr + BRCC %bb.4.return, 6, implicit %sr + BT %bb.1.if.end + + bb.1.if.end: + successors: %bb.4.return, %bb.2.if.end6 + + SFSUB_F_RI_LO %2, 0, implicit-def %sr + %10 = SCC 6, implicit %sr + SFSUB_F_RR %2, %3, implicit-def %sr + %11 = SCC 4, implicit %sr + %12 = AND_R killed %10, killed %11, 0 + %14 = AND_R killed %12, %8, 0 + SFSUB_F_RI_LO killed %14, 0, implicit-def %sr + BRCC %bb.4.return, 6, implicit %sr + BT %bb.2.if.end6 + + bb.2.if.end6: + successors: %bb.4.return, %bb.3.if.end11 + + SFSUB_F_RI_LO %3, 0, implicit-def %sr + %15 = SCC 6, implicit %sr + SFSUB_F_RR %3, %4, implicit-def %sr + %16 = SCC 4, implicit %sr + %17 = AND_R killed %15, killed %16, 0 + %18 = SLI 1 + %19 = AND_R killed %17, killed %18, 0 + SFSUB_F_RI_LO killed %19, 0, implicit-def %sr + BRCC %bb.4.return, 6, implicit %sr + BT %bb.3.if.end11 + + bb.3.if.end11: + %20 = SLI 21 + SFSUB_F_RR %4, %1, implicit-def %sr + %21 = SELECT %2, %20, 4, implicit %sr + SFSUB_F_RI_LO %4, 0, implicit-def %sr + %22 = SELECT killed %21, %20, 6, implicit %sr + %rv = COPY %22 + RET implicit %rca, implicit %rv + + bb.4.return: + %0 = PHI %3, %bb.0.entry, %4, %bb.1.if.end, %1, %bb.2.if.end6 + %rv = COPY %0 + RET implicit %rca, implicit %rv + +... +--- +name: testBB +alignment: 2 +exposesReturnsTwice: false +hasInlineAsm: false +allVRegsAllocated: false +isSSA: true +tracksRegLiveness: true +tracksSubRegLiveness: false +registers: + - { id: 0, class: gpr } + - { id: 1, class: gpr } + - { id: 2, class: gpr } + - { id: 3, class: gpr } + - { id: 4, class: gpr } + - { id: 5, class: gpr } + - { id: 6, class: gpr } + - { id: 7, class: gpr } + - { id: 8, class: gpr } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 0 + adjustsStack: false + hasCalls: true + maxCallFrameSize: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false +body: | + bb.0.entry: + successors: %bb.3.if.end, %bb.1.if.then + + %1 = MOVHI target-flags(lanai-hi) @a + %2 = OR_I_LO killed %1, target-flags(lanai-lo) @a + %3 = LDW_RI killed %2, 0, 0 :: (load 4 from @a, !tbaa !0) + %4 = MOVHI target-flags(lanai-hi) @b + %5 = OR_I_LO killed %4, target-flags(lanai-lo) @b + %6 = LDW_RI killed %5, 0, 0 :: (load 4 from @b, !tbaa !0) + %0 = SUB_R killed %6, killed %3, 0 + SFSUB_F_RI_LO %0, 0, implicit-def %sr + BRCC %bb.3.if.end, 10, implicit %sr + BT %bb.1.if.then + + bb.1.if.then: + successors: %bb.2.while.body + + ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp + CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + + bb.2.while.body: + successors: %bb.2.while.body + + BT %bb.2.while.body + + bb.3.if.end: + successors: %bb.4.if.then4, %bb.6.if.end7 + liveins: %sr + + BRCC %bb.6.if.end7, 14, implicit %sr + BT %bb.4.if.then4 + + bb.4.if.then4: + successors: %bb.5.while.body6 + + ADJCALLSTACKDOWN 0, implicit-def dead %sp, implicit %sp + CALL @g, csr, implicit-def dead %rca, implicit %sp, implicit-def %sp, implicit-def %rv + ADJCALLSTACKUP 0, 0, implicit-def dead %sp, implicit %sp + + bb.5.while.body6: + successors: %bb.5.while.body6 + + BT %bb.5.while.body6 + + bb.6.if.end7: + RET implicit %rca + +... diff --git a/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir b/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir index ea94c9906557..cc7a96ff50cc 100644 --- a/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir +++ b/test/CodeGen/MIR/Mips/expected-global-value-or-symbol-after-call-entry.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=mipsel -mattr=mips16 -relocation-model=pic -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { entry: diff --git a/test/CodeGen/MIR/Mips/memory-operands.mir b/test/CodeGen/MIR/Mips/memory-operands.mir index d4206b067f7e..69ecf985fcc0 100644 --- a/test/CodeGen/MIR/Mips/memory-operands.mir +++ b/test/CodeGen/MIR/Mips/memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the call entry pseudo source # values in memory operands correctly. @@ -50,8 +50,8 @@ body: | %v0 = SllX16 killed %v0, 16 %v0 = AdduRxRyRz16 killed %v1, killed %v0 ; CHECK-LABEL: name: test - ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry @foo) - %v1 = LwRxRyOffMemX16 %v0, @foo, 0 :: (load 4 from call-entry @foo) + ; CHECK: %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo) + %v1 = LwRxRyOffMemX16 %v0, @foo :: (load 4 from call-entry @foo) %t9 = COPY %v1 %gp = COPY killed %v0 JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit killed %t9, implicit %a0, implicit killed %gp, implicit-def %sp, implicit-def dead %v0 @@ -87,13 +87,13 @@ body: | %v0, %v1 = GotPrologue16 $_gp_disp, $_gp_disp %v0 = SllX16 killed %v0, 16 %s0 = AdduRxRyRz16 killed %v1, killed %v0 - %v0 = LwRxRyOffMemX16 %s0, @g, 0 :: (load 4 from call-entry @g) + %v0 = LwRxRyOffMemX16 %s0, @g :: (load 4 from call-entry @g) ; CHECK-LABEL: test2 - ; CHECK: %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0, 0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) - %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0, 0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) + ; CHECK: %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) + %v1 = LwRxRyOffMemX16 %s0, $__mips16_call_stub_sf_0 :: (load 4 from call-entry $__mips16_call_stub_sf_0) %gp = COPY %s0 JumpLinkReg16 killed %v1, csr_o32, implicit-def %ra, implicit %v0, implicit killed %gp, implicit-def %sp, implicit-def %v0 - %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf, 0 :: (load 4 from call-entry @__mips16_ret_sf) + %v1 = LwRxRyOffMemX16 %s0, @__mips16_ret_sf :: (load 4 from call-entry @__mips16_ret_sf) %t9 = COPY %v1 %gp = COPY killed %s0 JumpLinkReg16 killed %v1, csr_mips16rethelper, implicit-def %ra, implicit killed %t9, implicit %v0, implicit killed %gp, implicit-def %sp diff --git a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir index 28fb2a2cf5c9..d35fd323bf5d 100644 --- a/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir +++ b/test/CodeGen/MIR/NVPTX/expected-floating-point-literal.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir index 18866d58a946..312bf004a9ce 100644 --- a/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir +++ b/test/CodeGen/MIR/NVPTX/floating-point-immediate-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=nvptx -mcpu=sm_20 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses floating point constant operands # correctly. diff --git a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir index e4080f80ee52..2ff7f1a9451d 100644 --- a/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir +++ b/test/CodeGen/MIR/NVPTX/floating-point-invalid-type-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=nvptx -mcpu=sm_20 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=nvptx -mcpu=sm_20 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir index 39d14e72ffee..3caab2c7a578 100644 --- a/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir +++ b/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=powerpc64-unknown-linux-gnu -start-after machine-combiner -stop-after machine-combiner -o /dev/null %s | FileCheck %s +# RUN: llc -mtriple=powerpc64-unknown-linux-gnu -run-pass none -o - %s | FileCheck %s # PR24724 --- | diff --git a/test/CodeGen/MIR/X86/basic-block-liveins.mir b/test/CodeGen/MIR/X86/basic-block-liveins.mir index 00732975495d..35f5512936ba 100644 --- a/test/CodeGen/MIR/X86/basic-block-liveins.mir +++ b/test/CodeGen/MIR/X86/basic-block-liveins.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block liveins correctly. --- | diff --git a/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir index b4b7dddea56c..01c226a34537 100644 --- a/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir +++ b/test/CodeGen/MIR/X86/basic-block-not-at-start-of-line-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/block-address-operands.mir b/test/CodeGen/MIR/X86/block-address-operands.mir index 3c2d2aefff20..2207f9360965 100644 --- a/test/CodeGen/MIR/X86/block-address-operands.mir +++ b/test/CodeGen/MIR/X86/block-address-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the block address operands # correctly. diff --git a/test/CodeGen/MIR/X86/callee-saved-info.mir b/test/CodeGen/MIR/X86/callee-saved-info.mir index 17c7739951d9..883f6fdb0d22 100644 --- a/test/CodeGen/MIR/X86/callee-saved-info.mir +++ b/test/CodeGen/MIR/X86/callee-saved-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after prologepilog -stop-after prologepilog -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses callee saved information in the # stack objects correctly. diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir index 47051a53e3f4..ed26df684b00 100644 --- a/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir +++ b/test/CodeGen/MIR/X86/cfi-def-cfa-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the .cfi_def_cfa_offset operands # correctly. diff --git a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir index 74a33b5c3437..9a57eb047b87 100644 --- a/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir +++ b/test/CodeGen/MIR/X86/cfi-def-cfa-register.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the .cfi_def_cfa_register # operands correctly. diff --git a/test/CodeGen/MIR/X86/cfi-offset.mir b/test/CodeGen/MIR/X86/cfi-offset.mir index fd9e605a036a..0a50fe1866f4 100644 --- a/test/CodeGen/MIR/X86/cfi-offset.mir +++ b/test/CodeGen/MIR/X86/cfi-offset.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the .cfi_offset operands # correctly. diff --git a/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir index 2ddf5736b977..2f016a7599e3 100644 --- a/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir +++ b/test/CodeGen/MIR/X86/constant-pool-item-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/constant-pool.mir b/test/CodeGen/MIR/X86/constant-pool.mir index 213e4e283485..3312e6f67bde 100644 --- a/test/CodeGen/MIR/X86/constant-pool.mir +++ b/test/CodeGen/MIR/X86/constant-pool.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses constant pool constants and # constant pool operands correctly. diff --git a/test/CodeGen/MIR/X86/constant-value-error.mir b/test/CodeGen/MIR/X86/constant-value-error.mir index 1e14d2282c5a..baf933a87105 100644 --- a/test/CodeGen/MIR/X86/constant-value-error.mir +++ b/test/CodeGen/MIR/X86/constant-value-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing an invalid # constant value. diff --git a/test/CodeGen/MIR/X86/dead-register-flag.mir b/test/CodeGen/MIR/X86/dead-register-flag.mir index 309e776de46a..e6ab458e7389 100644 --- a/test/CodeGen/MIR/X86/dead-register-flag.mir +++ b/test/CodeGen/MIR/X86/dead-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'dead' register flags # correctly. diff --git a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir index 69c816f59b9b..bd9365b5f416 100644 --- a/test/CodeGen/MIR/X86/def-register-already-tied-error.mir +++ b/test/CodeGen/MIR/X86/def-register-already-tied-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir index 7d01810c792b..0c15e84f2268 100644 --- a/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir +++ b/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir index d80c6ed061de..9d8f4f159304 100644 --- a/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir +++ b/test/CodeGen/MIR/X86/duplicate-register-flag-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir index 4dc442e4fb94..0870fa062be6 100644 --- a/test/CodeGen/MIR/X86/early-clobber-register-flag.mir +++ b/test/CodeGen/MIR/X86/early-clobber-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'early-clobber' register # flags correctly. diff --git a/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir index f2e349454c5d..f65a5e6c9486 100644 --- a/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir index 7ce377f8c5fb..9bde7bf279a9 100644 --- a/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir index 861baec4bcbc..0de5b5bc6878 100644 --- a/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir +++ b/test/CodeGen/MIR/X86/expected-basic-block-at-start-of-body.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir index ef7df4c8c20f..c74d42d4dcc7 100644 --- a/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir +++ b/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir index ba7b2ab64c3e..52ba166094f3 100644 --- a/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir +++ b/test/CodeGen/MIR/X86/expected-comma-after-cfi-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir index dd5693952573..f617ddfa0eb0 100644 --- a/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir index 601551a7720a..d96d263a3204 100644 --- a/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir +++ b/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir index 6494960d3264..bd6cf6bd576d 100644 --- a/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir +++ b/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir deleted file mode 100644 index f9e9d0b22968..000000000000 --- a/test/CodeGen/MIR/X86/expected-from-in-memory-operand.mir +++ /dev/null @@ -1,24 +0,0 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s - ---- | - - define i32 @test(i32* %a) { - entry: - %b = load i32, i32* %a - ret i32 %b - } - -... ---- -name: test -tracksRegLiveness: true -liveins: - - { reg: '%rdi' } -body: | - bb.0.entry: - liveins: %rdi - ; CHECK: [[@LINE+1]]:55: expected 'from' - %eax = MOV32rm killed %rdi, 1, _, 0, _ :: (load 4 %ir.a) - RETQ %eax -... - diff --git a/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir index de6a745fd702..2f53023ecdb2 100644 --- a/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir +++ b/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir index f737c06c3e1e..1cabcfc73c2a 100644 --- a/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir +++ b/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir index e337292f17a2..f2f354b5a7c9 100644 --- a/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir +++ b/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir index 580d2bc0a419..c3f4fca11eaa 100644 --- a/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir +++ b/test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir index 83874eb67476..e8f06358505b 100644 --- a/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir +++ b/test/CodeGen/MIR/X86/expected-integer-in-successor-weight.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir index 8fcd622a18e6..225f767c5558 100644 --- a/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-machine-operand.mir b/test/CodeGen/MIR/X86/expected-machine-operand.mir index 3ba5126b9982..70fff3daa093 100644 --- a/test/CodeGen/MIR/X86/expected-machine-operand.mir +++ b/test/CodeGen/MIR/X86/expected-machine-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir index 620bb5d961ee..c5d7d5eb2893 100644 --- a/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir +++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -20,11 +20,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.ll", directory: "") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir index 6497f5db2026..c94fd9f5028e 100644 --- a/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir +++ b/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -20,11 +20,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.ll", directory: "") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} diff --git a/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir b/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir index 9a4696779fb5..dc8cb02338ea 100644 --- a/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir +++ b/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %x) { entry: diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir index 04568f6dde57..bba7b1a6e4a0 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-scheduler -stop-after machine-scheduler -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir index be57734ecf33..424f7cb21c45 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after prologepilog -stop-after prologepilog -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir index ae9f776ad769..a6384bb07197 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-named-register-livein.mir b/test/CodeGen/MIR/X86/expected-named-register-livein.mir index 41e6a4a6cc88..fcd68d3f614c 100644 --- a/test/CodeGen/MIR/X86/expected-named-register-livein.mir +++ b/test/CodeGen/MIR/X86/expected-named-register-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir index 1f0439d126f4..238d7aa6ffb8 100644 --- a/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir +++ b/test/CodeGen/MIR/X86/expected-newline-at-end-of-list.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-number-after-bb.mir b/test/CodeGen/MIR/X86/expected-number-after-bb.mir index a239cf176f5f..6770031da807 100644 --- a/test/CodeGen/MIR/X86/expected-number-after-bb.mir +++ b/test/CodeGen/MIR/X86/expected-number-after-bb.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir index aefeed9ce05e..e3c5ee9b9c88 100644 --- a/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir +++ b/test/CodeGen/MIR/X86/expected-offset-after-cfi-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir index fca078c3497c..3d127f855ced 100644 --- a/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir index 31b4c5be1251..1119133fc113 100644 --- a/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir +++ b/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir index 3280fca6d551..eea795821465 100644 --- a/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir +++ b/test/CodeGen/MIR/X86/expected-register-after-cfi-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-register-after-flags.mir b/test/CodeGen/MIR/X86/expected-register-after-flags.mir index 68f1060ad873..dc679ea7fc22 100644 --- a/test/CodeGen/MIR/X86/expected-register-after-flags.mir +++ b/test/CodeGen/MIR/X86/expected-register-after-flags.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when a register operand doesn't # follow register flags. diff --git a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir index 71ff15bd9c52..cfa03247e31f 100644 --- a/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir +++ b/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-stack-object.mir b/test/CodeGen/MIR/X86/expected-stack-object.mir index ff0c10d59e33..c536295c42f4 100644 --- a/test/CodeGen/MIR/X86/expected-stack-object.mir +++ b/test/CodeGen/MIR/X86/expected-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir index 6283427c10b3..d1d62461d371 100644 --- a/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir +++ b/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-target-flag-name.mir b/test/CodeGen/MIR/X86/expected-target-flag-name.mir index 3d094a11e9f3..c3ee45d96606 100644 --- a/test/CodeGen/MIR/X86/expected-target-flag-name.mir +++ b/test/CodeGen/MIR/X86/expected-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir index e8d6afd5333e..9e307f8833d9 100644 --- a/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir +++ b/test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir index f99443f1726d..a76202eb55b4 100644 --- a/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir index da0d1e166a1c..cdfcabbbf827 100644 --- a/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir +++ b/test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/external-symbol-operands.mir b/test/CodeGen/MIR/X86/external-symbol-operands.mir index 7e85d946b75a..599f957f66d5 100644 --- a/test/CodeGen/MIR/X86/external-symbol-operands.mir +++ b/test/CodeGen/MIR/X86/external-symbol-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the external symbol machine # operands correctly. diff --git a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir index 75d0f8a39c1c..f7a48d2eec06 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack memory operands # correctly. diff --git a/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir index c4c57a1d2443..d1b7c1633c29 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-object-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/fixed-stack-objects.mir b/test/CodeGen/MIR/X86/fixed-stack-objects.mir index 70e5a7428359..a7ecac841a64 100644 --- a/test/CodeGen/MIR/X86/fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | diff --git a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir index 54fa8ad0b616..2d5347e5d30d 100644 --- a/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir +++ b/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -enable-shrink-wrap=true -start-after shrink-wrap -stop-after shrink-wrap -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the save and restore points in # the machine frame info correctly. diff --git a/test/CodeGen/MIR/X86/frame-info-stack-references.mir b/test/CodeGen/MIR/X86/frame-info-stack-references.mir index c8fa3bbe226f..e64b44c65f81 100644 --- a/test/CodeGen/MIR/X86/frame-info-stack-references.mir +++ b/test/CodeGen/MIR/X86/frame-info-stack-references.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the stack protector stack # object reference in the machine frame info correctly. diff --git a/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir index 87c1fc68046e..5ae4df459437 100644 --- a/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir +++ b/test/CodeGen/MIR/X86/frame-setup-instruction-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the frame setup instruction flag. --- | diff --git a/test/CodeGen/MIR/X86/function-liveins.mir b/test/CodeGen/MIR/X86/function-liveins.mir index 95f8786b47a8..cbdc36281b71 100644 --- a/test/CodeGen/MIR/X86/function-liveins.mir +++ b/test/CodeGen/MIR/X86/function-liveins.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine function's liveins # correctly. diff --git a/test/CodeGen/MIR/X86/generic-instr-type-error.mir b/test/CodeGen/MIR/X86/generic-instr-type-error.mir new file mode 100644 index 000000000000..1f196919afa0 --- /dev/null +++ b/test/CodeGen/MIR/X86/generic-instr-type-error.mir @@ -0,0 +1,15 @@ +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that the MIR parser report an error for +# opaque types used on generic instruction. + +--- +name: bar +isSSA: true +registers: + - { id: 0, class: gr32 } +body: | + bb.0.entry: + liveins: %edi + ; CHECK: [[@LINE+1]]:20: expected a sized type + %0(32) = G_ADD %opaque %edi, %edi +... diff --git a/test/CodeGen/MIR/X86/generic-virtual-registers.mir b/test/CodeGen/MIR/X86/generic-virtual-registers.mir new file mode 100644 index 000000000000..225ddfbc452a --- /dev/null +++ b/test/CodeGen/MIR/X86/generic-virtual-registers.mir @@ -0,0 +1,48 @@ +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# REQUIRES: global-isel +# This test ensures that the MIR parser parses generic virtual +# register definitions correctly. + +--- | + ; ModuleID = 'generic-virtual-registers-type-error.mir' + target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128" + %type_alias = type <2 x i32> + %structure_alias = type { i32, i16 } + define void @bar() { + entry: + ret void + } + +... + +--- +name: bar +isSSA: true +# CHECK: registers: +# CHECK-NEXT: - { id: 0, class: _ } +# CHECK-NEXT: - { id: 1, class: _ } +# CHECK-NEXT: - { id: 2, class: _ } +# CHECK-NEXT: - { id: 3, class: _ } +# CHECK-NEXT: - { id: 4, class: _ } +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } + - { id: 4, class: _ } +body: | + bb.0.entry: + liveins: %edi + ; CHECK: %0(32) = G_ADD i32 %edi + %0(32) = G_ADD i32 %edi, %edi + ; CHECK: %1(64) = G_ADD <2 x i32> %edi + %1(64) = G_ADD <2 x i32> %edi, %edi + ; CHECK: %2(64) = G_ADD <2 x i32> %edi + %2(64) = G_ADD %type_alias %edi, %edi + ; G_ADD is actually not a valid operand for structure type, + ; but that is the only one we have for now for testing. + ; CHECK: %3(64) = G_ADD { i32, i32 } %edi + %3(64) = G_ADD {i32, i32} %edi, %edi + ; CHECK: %4(48) = G_ADD %structure_alias %edi + %4(48) = G_ADD %structure_alias %edi, %edi +... diff --git a/test/CodeGen/MIR/X86/global-value-operands.mir b/test/CodeGen/MIR/X86/global-value-operands.mir index 394aa397aef4..9b9554da7bd6 100644 --- a/test/CodeGen/MIR/X86/global-value-operands.mir +++ b/test/CodeGen/MIR/X86/global-value-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses global value operands correctly. --- | diff --git a/test/CodeGen/MIR/X86/immediate-operands.mir b/test/CodeGen/MIR/X86/immediate-operands.mir index 34bd0fa14904..4d47219bf3b1 100644 --- a/test/CodeGen/MIR/X86/immediate-operands.mir +++ b/test/CodeGen/MIR/X86/immediate-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses immediate machine operands. --- | diff --git a/test/CodeGen/MIR/X86/implicit-register-flag.mir b/test/CodeGen/MIR/X86/implicit-register-flag.mir index b0a15ed93a8f..70b1cc500944 100644 --- a/test/CodeGen/MIR/X86/implicit-register-flag.mir +++ b/test/CodeGen/MIR/X86/implicit-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'implicit' and 'implicit-def' # register flags correctly. diff --git a/test/CodeGen/MIR/X86/inline-asm-registers.mir b/test/CodeGen/MIR/X86/inline-asm-registers.mir index 3fd565891091..f0e8d1fcd8ff 100644 --- a/test/CodeGen/MIR/X86/inline-asm-registers.mir +++ b/test/CodeGen/MIR/X86/inline-asm-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after block-placement -stop-after block-placement -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s --- | define i64 @test(i64 %x, i64 %y) #0 { diff --git a/test/CodeGen/MIR/X86/instructions-debug-location.mir b/test/CodeGen/MIR/X86/instructions-debug-location.mir index ea2cdbf7cb2f..12ee5d873d94 100644 --- a/test/CodeGen/MIR/X86/instructions-debug-location.mir +++ b/test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the machine instruction's # debug location metadata correctly. @@ -31,11 +31,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.ll", directory: "") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} @@ -62,9 +61,9 @@ stack: body: | bb.0.entry: liveins: %edi - ; CHECK: DBG_VALUE debug-use _, 0, !12, !13, debug-location !14 - ; CHECK: %eax = COPY %0, debug-location !15 - ; CHECK: RETQ %eax, debug-location !15 + ; CHECK: DBG_VALUE debug-use _, 0, !11, !12, debug-location !13 + ; CHECK: %eax = COPY %0, debug-location !14 + ; CHECK: RETQ %eax, debug-location !14 %0 = COPY %edi DBG_VALUE debug-use _, 0, !12, !13, debug-location !14 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 @@ -86,9 +85,9 @@ body: | liveins: %edi %0 = COPY %edi - ; CHECK: DBG_VALUE _, i32 0, !12, !13 - ; CHECK-NEXT: DBG_VALUE _, i64 -22, !12, !13 - ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13 + ; CHECK: DBG_VALUE _, i32 0, !11, !12 + ; CHECK-NEXT: DBG_VALUE _, i64 -22, !11, !12 + ; CHECK-NEXT: DBG_VALUE _, i128 123492148938512984928424384934328985928, !11, !12 DBG_VALUE _, i32 0, !12, !13 DBG_VALUE _, i64 -22, !12, !13 DBG_VALUE _, i128 123492148938512984928424384934328985928, !12, !13 diff --git a/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir index afd6c78546ce..0b1eb2f5275b 100644 --- a/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir +++ b/test/CodeGen/MIR/X86/invalid-constant-pool-item.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing an invalid # constant pool item operand. diff --git a/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir index a6c2e509da0c..42d05274e7cd 100644 --- a/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir +++ b/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | declare void @llvm.dbg.declare(metadata, metadata, metadata) #0 @@ -6,7 +6,7 @@ entry: %x.i = alloca i8, align 1 %y.i = alloca [256 x i8], align 16 - %0 = bitcast [256 x i8]* %y.i to i8* + %0 = bitcast i8* %x.i to i8* br label %for.body for.body: @@ -22,12 +22,12 @@ !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3} - !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: 0, enums: !2, retainedTypes: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2) !1 = !DIFile(filename: "t.c", directory: "") !2 = !{} !3 = !{i32 1, !"Debug Info Version", i32 3} !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !6) - !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false) + !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false, unit: !0) !6 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) !7 = !DIExpression() !8 = !DILocation(line: 0, scope: !5) diff --git a/test/CodeGen/MIR/X86/invalid-target-flag-name.mir b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir index 313c5bdafed8..1cc9bed2349f 100644 --- a/test/CodeGen/MIR/X86/invalid-target-flag-name.mir +++ b/test/CodeGen/MIR/X86/invalid-target-flag-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir index 00436adca484..2ba3288335fb 100644 --- a/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir +++ b/test/CodeGen/MIR/X86/invalid-tied-def-index-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/test/CodeGen/MIR/X86/jump-table-info.mir b/test/CodeGen/MIR/X86/jump-table-info.mir index a4e6f6a1728c..e44f4b237df4 100644 --- a/test/CodeGen/MIR/X86/jump-table-info.mir +++ b/test/CodeGen/MIR/X86/jump-table-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the jump table info and jump # table operands correctly. @@ -62,7 +62,7 @@ name: test_jumptable # CHECK-NEXT: entries: # CHECK-NEXT: - id: 0 # CHECK-NEXT: blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ] -# CHECK_NEXT: body: +# CHECK-NEXT: body: jumpTable: kind: label-difference32 entries: diff --git a/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir index d4ab11f40787..1eeabfba8124 100644 --- a/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir +++ b/test/CodeGen/MIR/X86/jump-table-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/killed-register-flag.mir b/test/CodeGen/MIR/X86/killed-register-flag.mir index 9e8f3ba3b368..159553ba4829 100644 --- a/test/CodeGen/MIR/X86/killed-register-flag.mir +++ b/test/CodeGen/MIR/X86/killed-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'killed' register flags # correctly. diff --git a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir index 93ce30abec7c..3339115c8bdf 100644 --- a/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir +++ b/test/CodeGen/MIR/X86/large-cfi-offset-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/large-immediate-operand-error.mir b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir index f815c63e18e9..0d72690401d4 100644 --- a/test/CodeGen/MIR/X86/large-immediate-operand-error.mir +++ b/test/CodeGen/MIR/X86/large-immediate-operand-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/large-index-number-error.mir b/test/CodeGen/MIR/X86/large-index-number-error.mir index 272cd685b381..f8423fd43e14 100644 --- a/test/CodeGen/MIR/X86/large-index-number-error.mir +++ b/test/CodeGen/MIR/X86/large-index-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/large-offset-number-error.mir b/test/CodeGen/MIR/X86/large-offset-number-error.mir index 5463cdbce444..0b2225f15414 100644 --- a/test/CodeGen/MIR/X86/large-offset-number-error.mir +++ b/test/CodeGen/MIR/X86/large-offset-number-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir index c570f0992a3f..616adfad1eda 100644 --- a/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir +++ b/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/liveout-register-mask.mir b/test/CodeGen/MIR/X86/liveout-register-mask.mir index 7ded7287060e..c2a5a34a85ca 100644 --- a/test/CodeGen/MIR/X86/liveout-register-mask.mir +++ b/test/CodeGen/MIR/X86/liveout-register-mask.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after stackmap-liveness -stop-after stackmap-liveness -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the liveout register mask # machine operands correctly. diff --git a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir index 0d7a9f8ef34c..f59157386796 100644 --- a/test/CodeGen/MIR/X86/machine-basic-block-operands.mir +++ b/test/CodeGen/MIR/X86/machine-basic-block-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses machine basic block operands. --- | diff --git a/test/CodeGen/MIR/X86/machine-instructions.mir b/test/CodeGen/MIR/X86/machine-instructions.mir index 0e46d01e0bd1..28d4d47e3e7f 100644 --- a/test/CodeGen/MIR/X86/machine-instructions.mir +++ b/test/CodeGen/MIR/X86/machine-instructions.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses X86 machine instructions # correctly. diff --git a/test/CodeGen/MIR/X86/machine-verifier.mir b/test/CodeGen/MIR/X86/machine-verifier.mir index a7413d4d03bc..c56bab8c998c 100644 --- a/test/CodeGen/MIR/X86/machine-verifier.mir +++ b/test/CodeGen/MIR/X86/machine-verifier.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser runs the machine verifier after parsing. --- | diff --git a/test/CodeGen/MIR/X86/memory-operands.mir b/test/CodeGen/MIR/X86/memory-operands.mir index 3c9463d2f313..a25538d9b1fc 100644 --- a/test/CodeGen/MIR/X86/memory-operands.mir +++ b/test/CodeGen/MIR/X86/memory-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the machine memory operands # correctly. @@ -186,6 +186,9 @@ %0 = load i8*, i8** undef, align 8 ret i8* %0 } + + define void @dummy0() { ret void } + define void @dummy1() { ret void } ... --- name: test @@ -506,3 +509,28 @@ body: | %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8 from `i8** undef`) RETQ %rax ... +--- +# Test memory operand without associated value. +# CHECK-LABEL: name: dummy0 +# CHECK: %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) +name: dummy0 +tracksRegLiveness: true +body: | + bb.0: + %rax = MOV64rm undef %rax, 1, _, 0, _ :: (load 8) + RETQ %rax +... +--- +# Test parsing of stack references in machine memory operands. +# CHECK-LABEL: name: dummy1 +# CHECK: %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) +name: dummy1 +tracksRegLiveness: true +stack: + - { id: 0, size: 4, alignment: 4 } +body: | + bb.0: + %rax = MOV64rm %rsp, 1, _, 0, _ :: (load 8 from %stack.0) + RETQ %rax + +... diff --git a/test/CodeGen/MIR/X86/metadata-operands.mir b/test/CodeGen/MIR/X86/metadata-operands.mir index 89a1e6fcb815..42f3fe1c86c7 100644 --- a/test/CodeGen/MIR/X86/metadata-operands.mir +++ b/test/CodeGen/MIR/X86/metadata-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the metadata machine operands # correctly. @@ -22,11 +22,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.ll", directory: "") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} @@ -54,7 +53,7 @@ body: | bb.0.entry: liveins: %edi ; CHECK: %0 = COPY %edi - ; CHECK-NEXT: DBG_VALUE _, 0, !12, !13 + ; CHECK-NEXT: DBG_VALUE _, 0, !11, !12 %0 = COPY %edi DBG_VALUE _, 0, !12, ! 13 MOV32mr %stack.0.x.addr, 1, _, 0, _, %0 diff --git a/test/CodeGen/MIR/X86/missing-closing-quote.mir b/test/CodeGen/MIR/X86/missing-closing-quote.mir index 9f4b369a3df4..0e912f5ea788 100644 --- a/test/CodeGen/MIR/X86/missing-closing-quote.mir +++ b/test/CodeGen/MIR/X86/missing-closing-quote.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/missing-comma.mir b/test/CodeGen/MIR/X86/missing-comma.mir index 092995e59c70..0aaba6ddaa3a 100644 --- a/test/CodeGen/MIR/X86/missing-comma.mir +++ b/test/CodeGen/MIR/X86/missing-comma.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/missing-implicit-operand.mir b/test/CodeGen/MIR/X86/missing-implicit-operand.mir index 0135c756e138..fd26f19d1847 100644 --- a/test/CodeGen/MIR/X86/missing-implicit-operand.mir +++ b/test/CodeGen/MIR/X86/missing-implicit-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when an instruction # is missing one of its implicit register operands. diff --git a/test/CodeGen/MIR/X86/named-registers.mir b/test/CodeGen/MIR/X86/named-registers.mir index e547c326563e..eedc2dbe853f 100644 --- a/test/CodeGen/MIR/X86/named-registers.mir +++ b/test/CodeGen/MIR/X86/named-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses X86 registers correctly. --- | diff --git a/test/CodeGen/MIR/X86/newline-handling.mir b/test/CodeGen/MIR/X86/newline-handling.mir index bce06d540114..ce43a83ecae5 100644 --- a/test/CodeGen/MIR/X86/newline-handling.mir +++ b/test/CodeGen/MIR/X86/newline-handling.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/null-register-operands.mir b/test/CodeGen/MIR/X86/null-register-operands.mir index 5563ef8e8f75..9cba00bc9e5e 100644 --- a/test/CodeGen/MIR/X86/null-register-operands.mir +++ b/test/CodeGen/MIR/X86/null-register-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses null register operands correctly. --- | diff --git a/test/CodeGen/MIR/X86/register-mask-operands.mir b/test/CodeGen/MIR/X86/register-mask-operands.mir index 9fa4e6e3994e..c683a635f147 100644 --- a/test/CodeGen/MIR/X86/register-mask-operands.mir +++ b/test/CodeGen/MIR/X86/register-mask-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses register mask operands correctly. --- | diff --git a/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir index 64d46d20db74..d4d3f5692e90 100644 --- a/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir +++ b/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir index d7e76329be73..27ca266f7794 100644 --- a/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir +++ b/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-scheduler -stop-after machine-scheduler -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses simple register allocation hints # correctly. diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir index b62cd755fec1..5e191ba11942 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir index c89216bea67a..91288aa40b39 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir index 7e13a26f0b68..1771d6fafcae 100644 --- a/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir +++ b/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses fixed stack objects correctly. --- | diff --git a/test/CodeGen/MIR/X86/stack-object-debug-info.mir b/test/CodeGen/MIR/X86/stack-object-debug-info.mir index 509b196416fd..d80b7d0bfcb1 100644 --- a/test/CodeGen/MIR/X86/stack-object-debug-info.mir +++ b/test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the stack object's debug info # correctly. --- | @@ -31,15 +31,18 @@ !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!3} - !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: 0, enums: !2, retainedTypes: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2) !1 = !DIFile(filename: "t.c", directory: "") !2 = !{} !3 = !{i32 1, !"Debug Info Version", i32 3} - !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !6) - !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false) + !4 = !DILocalVariable(name: "x", scope: !5, file: !1, line: 16, type: !9) + !5 = distinct !DISubprogram(scope: null, isLocal: false, isDefinition: true, isOptimized: false, unit: !0) !6 = !DIBasicType(name: "char", size: 8, align: 8, encoding: DW_ATE_signed_char) !7 = !DIExpression() !8 = !DILocation(line: 0, scope: !5) + !9 = !DICompositeType(tag: DW_TAG_array_type, baseType: !6, size: 2048, align: 8, elements: !10) + !10 = !{!11} + !11 = !DISubrange(count: 256) ... --- name: foo @@ -50,7 +53,7 @@ frameInfo: # CHECK-LABEL: foo # CHECK: stack: # CHECK: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', -# CHECK-NEXT: di-expression: '!7', di-location: '!8' } +# CHECK-NEXT: di-expression: '!10', di-location: '!11' } stack: - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4', di-expression: '!7', di-location: '!8' } diff --git a/test/CodeGen/MIR/X86/stack-object-invalid-name.mir b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir index e42e1e59f1e7..4572f106256d 100644 --- a/test/CodeGen/MIR/X86/stack-object-invalid-name.mir +++ b/test/CodeGen/MIR/X86/stack-object-invalid-name.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when it encounters a # stack object with a name that can't be associated with an alloca instruction. diff --git a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir index 46661d95e727..2115a11ae693 100644 --- a/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir +++ b/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an stack object reference # uses a different name then the stack object definition. diff --git a/test/CodeGen/MIR/X86/stack-object-operands.mir b/test/CodeGen/MIR/X86/stack-object-operands.mir index fce5bf717d1a..6ff15aef4d7f 100644 --- a/test/CodeGen/MIR/X86/stack-object-operands.mir +++ b/test/CodeGen/MIR/X86/stack-object-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses stack object machine operands # correctly. diff --git a/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir index b84863ebca67..0fccff0425ee 100644 --- a/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir +++ b/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/stack-objects.mir b/test/CodeGen/MIR/X86/stack-objects.mir index bdd911075da0..08b9ec0b4347 100644 --- a/test/CodeGen/MIR/X86/stack-objects.mir +++ b/test/CodeGen/MIR/X86/stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses stack objects correctly. --- | diff --git a/test/CodeGen/MIR/X86/standalone-register-error.mir b/test/CodeGen/MIR/X86/standalone-register-error.mir index f17451bfc89c..b50393390289 100644 --- a/test/CodeGen/MIR/X86/standalone-register-error.mir +++ b/test/CodeGen/MIR/X86/standalone-register-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { body: diff --git a/test/CodeGen/MIR/X86/subreg-on-physreg.mir b/test/CodeGen/MIR/X86/subreg-on-physreg.mir new file mode 100644 index 000000000000..f20195e7ddf5 --- /dev/null +++ b/test/CodeGen/MIR/X86/subreg-on-physreg.mir @@ -0,0 +1,12 @@ +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported for subreg index on a physreg. +--- | + define void @t() { ret void } +... +--- +name: t +body: | + bb.0: + ; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register + %eax:sub_8bit = COPY %bl +... diff --git a/test/CodeGen/MIR/X86/subregister-index-operands.mir b/test/CodeGen/MIR/X86/subregister-index-operands.mir new file mode 100644 index 000000000000..a9a45adadf6e --- /dev/null +++ b/test/CodeGen/MIR/X86/subregister-index-operands.mir @@ -0,0 +1,32 @@ +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s +# This test ensures that the MIR parser parses and prints subregisters index +# operands correctly. + +--- | + + define zeroext i1 @t(i1 %c) { + entry: + ret i1 %c + } + +... +--- +# CHECK-LABEL: name: t +# CHECK: %0 = INSERT_SUBREG %edi, %al, {{[0-9]+}} +# CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}} +# CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}} +name: t +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr8 } +body: | + bb.0.entry: + liveins: %edi, %eax + %0 = INSERT_SUBREG %edi, %al, %subreg.sub_8bit + %1 = EXTRACT_SUBREG %eax, %subreg.sub_8bit_hi + %ax = REG_SEQUENCE %1, %subreg.sub_8bit, %1, %subreg.sub_8bit_hi + RETQ %ax +... + diff --git a/test/CodeGen/MIR/X86/subregister-operands.mir b/test/CodeGen/MIR/X86/subregister-operands.mir index 8a3fcf69aca6..a02bfe8359dc 100644 --- a/test/CodeGen/MIR/X86/subregister-operands.mir +++ b/test/CodeGen/MIR/X86/subregister-operands.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses subregisters in register operands # correctly. diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir index 64af6121189a..8de31f3274df 100644 --- a/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir +++ b/test/CodeGen/MIR/X86/successor-basic-blocks-weights.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block successors and # probabilities correctly. diff --git a/test/CodeGen/MIR/X86/successor-basic-blocks.mir b/test/CodeGen/MIR/X86/successor-basic-blocks.mir index a6c14f70bc7c..6f15f522bd5f 100644 --- a/test/CodeGen/MIR/X86/successor-basic-blocks.mir +++ b/test/CodeGen/MIR/X86/successor-basic-blocks.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses basic block successors correctly. --- | diff --git a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir index fe5263df355f..05502fff4062 100644 --- a/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir +++ b/test/CodeGen/MIR/X86/tied-def-operand-invalid.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i64 @test(i64 %x) #0 { entry: diff --git a/test/CodeGen/MIR/X86/undef-register-flag.mir b/test/CodeGen/MIR/X86/undef-register-flag.mir index 0b26c528aee1..2c332d848bbc 100644 --- a/test/CodeGen/MIR/X86/undef-register-flag.mir +++ b/test/CodeGen/MIR/X86/undef-register-flag.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the 'undef' register flags # correctly. diff --git a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir index 8d8f8614f32b..18cb758408ff 100644 --- a/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir +++ b/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/test/CodeGen/MIR/X86/undefined-global-value.mir b/test/CodeGen/MIR/X86/undefined-global-value.mir index f82c626397a9..e717c1ee5976 100644 --- a/test/CodeGen/MIR/X86/undefined-global-value.mir +++ b/test/CodeGen/MIR/X86/undefined-global-value.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an invalid global value index # is used. diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir index f6b10e3123ca..5c2a45eec2a1 100644 --- a/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir +++ b/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir index 0b3c0093dc62..ef7dd4802aca 100644 --- a/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir +++ b/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/undefined-jump-table-id.mir b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir index b463dc4bd9f4..765bb9d97d19 100644 --- a/test/CodeGen/MIR/X86/undefined-jump-table-id.mir +++ b/test/CodeGen/MIR/X86/undefined-jump-table-id.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/undefined-named-global-value.mir b/test/CodeGen/MIR/X86/undefined-named-global-value.mir index a1ada4b42e46..435257b8fac1 100644 --- a/test/CodeGen/MIR/X86/undefined-named-global-value.mir +++ b/test/CodeGen/MIR/X86/undefined-named-global-value.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an undefined global value is # used. diff --git a/test/CodeGen/MIR/X86/undefined-register-class.mir b/test/CodeGen/MIR/X86/undefined-register-class.mir index 348f6af5c44f..70b413b5ad37 100644 --- a/test/CodeGen/MIR/X86/undefined-register-class.mir +++ b/test/CodeGen/MIR/X86/undefined-register-class.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when it encounters an # unknown register class. @@ -15,7 +15,7 @@ name: test isSSA: true tracksRegLiveness: true registers: - # CHECK: [[@LINE+1]]:20: use of undefined register class 'gr3200' + # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200' - {id: 0, class: 'gr3200'} body: | bb.0.entry: diff --git a/test/CodeGen/MIR/X86/undefined-stack-object.mir b/test/CodeGen/MIR/X86/undefined-stack-object.mir index 416e6789ba0f..5d40791b4c31 100644 --- a/test/CodeGen/MIR/X86/undefined-stack-object.mir +++ b/test/CodeGen/MIR/X86/undefined-stack-object.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir index a3907d7a3a4a..42e94c1ce5a3 100644 --- a/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir +++ b/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/undefined-virtual-register.mir b/test/CodeGen/MIR/X86/undefined-virtual-register.mir index 2f9a304ffe5c..fe41e0a4d2fc 100644 --- a/test/CodeGen/MIR/X86/undefined-virtual-register.mir +++ b/test/CodeGen/MIR/X86/undefined-virtual-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that the MIR parser reports an error when parsing a # reference to an undefined virtual register. diff --git a/test/CodeGen/MIR/X86/unknown-instruction.mir b/test/CodeGen/MIR/X86/unknown-instruction.mir index cec354948832..4377347f0a9f 100644 --- a/test/CodeGen/MIR/X86/unknown-instruction.mir +++ b/test/CodeGen/MIR/X86/unknown-instruction.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown instruction is # encountered. diff --git a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir index a512d9aa08e6..0634fb2e0ed8 100644 --- a/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir +++ b/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an invalid machine basic # block index is used. diff --git a/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir b/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir index c58c38ab1322..ddd5686b0cf3 100644 --- a/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir +++ b/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @inc(i32* %x) { diff --git a/test/CodeGen/MIR/X86/unknown-metadata-node.mir b/test/CodeGen/MIR/X86/unknown-metadata-node.mir index 958a30678be1..793f9123776a 100644 --- a/test/CodeGen/MIR/X86/unknown-metadata-node.mir +++ b/test/CodeGen/MIR/X86/unknown-metadata-node.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | @@ -20,11 +20,10 @@ !llvm.module.flags = !{!9, !10} !llvm.ident = !{!11} - !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: 1, enums: !2, retainedTypes: !2, subprograms: !3, globals: !2, imports: !2) + !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 3.7.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, retainedTypes: !2, globals: !2, imports: !2) !1 = !DIFile(filename: "test.ll", directory: "") !2 = !{} - !3 = !{!4} - !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, variables: !2) + !4 = distinct !DISubprogram(name: "test", scope: !5, file: !5, line: 4, type: !6, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !5 = !DIFile(filename: "test.c", directory: "") !6 = !DISubroutineType(types: !7) !7 = !{!8, !8} diff --git a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir index 6627273d4470..5ba6402353ef 100644 --- a/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir +++ b/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown named machine # basic block is encountered. diff --git a/test/CodeGen/MIR/X86/unknown-register.mir b/test/CodeGen/MIR/X86/unknown-register.mir index da0798ca1b52..74e9bfa72157 100644 --- a/test/CodeGen/MIR/X86/unknown-register.mir +++ b/test/CodeGen/MIR/X86/unknown-register.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown register is # encountered. diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir b/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir new file mode 100644 index 000000000000..2d997b07dbd5 --- /dev/null +++ b/test/CodeGen/MIR/X86/unknown-subregister-index-op.mir @@ -0,0 +1,26 @@ +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s +# This test ensures that an error is reported when an unknown subregister index +# is encountered. + +--- | + + define zeroext i1 @t(i1 %c) { + entry: + ret i1 %c + } + +... +--- +name: t +isSSA: true +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr8 } + - { id: 2, class: gr8 } +body: | + bb.0.entry: + ; CHECK: [[@LINE+1]]:35: unknown subregister index 'bit8' + %0 = INSERT_SUBREG %edi, %al, %subreg.bit8 + RETQ %0 +... diff --git a/test/CodeGen/MIR/X86/unknown-subregister-index.mir b/test/CodeGen/MIR/X86/unknown-subregister-index.mir index 5dde34561236..6ad6242f79a3 100644 --- a/test/CodeGen/MIR/X86/unknown-subregister-index.mir +++ b/test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s # This test ensures that an error is reported when an unknown subregister index # is encountered. diff --git a/test/CodeGen/MIR/X86/unrecognized-character.mir b/test/CodeGen/MIR/X86/unrecognized-character.mir index cf99028677fa..4b6631099716 100644 --- a/test/CodeGen/MIR/X86/unrecognized-character.mir +++ b/test/CodeGen/MIR/X86/unrecognized-character.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/used-physical-register-info.mir b/test/CodeGen/MIR/X86/used-physical-register-info.mir index 9a81578703e0..9edc4113b279 100644 --- a/test/CodeGen/MIR/X86/used-physical-register-info.mir +++ b/test/CodeGen/MIR/X86/used-physical-register-info.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses the callee saved register mask # correctly and that the MIR parser can infer it as well. diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir index e6a9ef8d4c88..2633ea59bf55 100644 --- a/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir +++ b/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | define i32 @test(i32 %a) { diff --git a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir index a58be69ae046..5e7d99352e57 100644 --- a/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir +++ b/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses variable sized stack objects # correctly. diff --git a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir index 5dae6e666c83..4d2350a01b8d 100644 --- a/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir +++ b/test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir @@ -1,4 +1,4 @@ -# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s +# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s --- | diff --git a/test/CodeGen/MIR/X86/virtual-registers.mir b/test/CodeGen/MIR/X86/virtual-registers.mir index 93c2fea6fd95..3f7b0fdcc0e3 100644 --- a/test/CodeGen/MIR/X86/virtual-registers.mir +++ b/test/CodeGen/MIR/X86/virtual-registers.mir @@ -1,4 +1,4 @@ -# RUN: llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s | FileCheck %s +# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s # This test ensures that the MIR parser parses virtual register definitions and # references correctly. diff --git a/test/CodeGen/MIR/lit.local.cfg b/test/CodeGen/MIR/lit.local.cfg deleted file mode 100644 index e69aa5765356..000000000000 --- a/test/CodeGen/MIR/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -config.suffixes = ['.mir'] - diff --git a/test/CodeGen/MSP430/spill-to-stack.ll b/test/CodeGen/MSP430/spill-to-stack.ll new file mode 100644 index 000000000000..d925bc91b72d --- /dev/null +++ b/test/CodeGen/MSP430/spill-to-stack.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=msp430 < %s +%VeryLarge = type { i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 } + +; intentionally cause a spill +define void @inc(%VeryLarge* byval align 1 %s) { +entry: + %p0 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 0 + %0 = load i8, i8* %p0 + %p1 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 1 + %1 = load i32, i32* %p1 + %p2 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 2 + %2 = load i32, i32* %p2 + %p3 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 3 + %3 = load i32, i32* %p3 + %p4 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 4 + %4 = load i32, i32* %p4 + %p5 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 5 + %5 = load i32, i32* %p5 + %p6 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 6 + %6 = load i32, i32* %p6 + %p7 = getelementptr inbounds %VeryLarge, %VeryLarge* %s, i32 0, i32 7 + %7 = load i32, i32* %p7 + %add = add i8 %0, 1 + store i8 %add, i8* %p0 + %add2 = add i32 %1, 2 + store i32 %add2, i32* %p1 + %add3 = add i32 %2, 3 + store i32 %add3, i32* %p2 + %add4 = add i32 %3, 4 + store i32 %add4, i32* %p3 + %add5 = add i32 %4, 5 + store i32 %add5, i32* %p4 + %add6 = add i32 %5, 6 + store i32 %add6, i32* %p5 + %add7 = add i32 %6, 7 + store i32 %add7, i32* %p6 + %add8 = add i32 %7, 8 + store i32 %add8, i32* %p7 + ret void +} diff --git a/test/CodeGen/Mips/2010-07-20-Switch.ll b/test/CodeGen/Mips/2010-07-20-Switch.ll index fd0254e9f5ec..7d66d1a1a204 100644 --- a/test/CodeGen/Mips/2010-07-20-Switch.ll +++ b/test/CodeGen/Mips/2010-07-20-Switch.ll @@ -55,19 +55,19 @@ bb5: ; preds = %entry ret i32 1 } -; STATIC-O32: .align 2 +; STATIC-O32: .p2align 2 ; STATIC-O32: $JTI0_0: ; STATIC-O32: .4byte ; STATIC-O32: .4byte ; STATIC-O32: .4byte ; STATIC-O32: .4byte -; PIC-O32: .align 2 +; PIC-O32: .p2align 2 ; PIC-O32: $JTI0_0: ; PIC-O32: .gpword ; PIC-O32: .gpword ; PIC-O32: .gpword ; PIC-O32: .gpword -; N64: .align 3 +; N64: .p2align 3 ; N64: $JTI0_0: ; N64: .gpdword ; N64: .gpdword diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll index 34616a50b1a0..9988622db54f 100644 --- a/test/CodeGen/Mips/Fast-ISel/callabi.ll +++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -O0 \ -; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 \ -; RUN: -relocation-model=pic -fast-isel-abort=1 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 +; RUN: llc -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R2 declare void @xb(i8) diff --git a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll index 203e5a7e1595..290e4ecb7405 100644 --- a/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll +++ b/test/CodeGen/Mips/Fast-ISel/check-disabled-mcpus.ll @@ -1,20 +1,22 @@ ; RUN: llc -march=mips -mcpu=mips2 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips4 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+micromips -O0 -relocation-model=pic \ +; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r2 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r3 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s -; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic \ +; RUN: llc -march=mips -mcpu=mips64r5 -O0 -relocation-model=pic -target-abi n64 \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s ; RUN: llc -march=mips -mcpu=mips32r6 -O0 -relocation-model=pic \ ; RUN: -fast-isel-verbose <%s 2>&1 | FileCheck %s diff --git a/test/CodeGen/Mips/Fast-ISel/div1.ll b/test/CodeGen/Mips/Fast-ISel/div1.ll index 89055aa12805..b0865e649d96 100644 --- a/test/CodeGen/Mips/Fast-ISel/div1.ll +++ b/test/CodeGen/Mips/Fast-ISel/div1.ll @@ -22,7 +22,7 @@ define void @divs() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -44,7 +44,7 @@ define void @divu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mflo $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll index 00bc7f485e08..9c91567eabf0 100644 --- a/test/CodeGen/Mips/Fast-ISel/fastalloca.ll +++ b/test/CodeGen/Mips/Fast-ISel/fastalloca.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s +; RUN: < %s -verify-machineinstrs | FileCheck %s %struct.x = type { i32 } diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll index e346acfeff13..d661a281ea1d 100644 --- a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll +++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32r2 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=1 -mcpu=mips32 \ -; RUN: < %s | FileCheck %s +; RUN: -verify-machineinstrs < %s | FileCheck %s @f1 = common global float 0.000000e+00, align 4 @f2 = common global float 0.000000e+00, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/test/CodeGen/Mips/Fast-ISel/memtest1.ll index b98200d7456d..7deb5c08ec69 100644 --- a/test/CodeGen/Mips/Fast-ISel/memtest1.ll +++ b/test/CodeGen/Mips/Fast-ISel/memtest1.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R1 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \ -; RUN: -fast-isel-abort=1 | FileCheck %s \ +; RUN: -fast-isel-abort=1 -verify-machineinstrs | FileCheck %s \ ; RUN: -check-prefix=ALL -check-prefix=32R2 @str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1 diff --git a/test/CodeGen/Mips/Fast-ISel/rem1.ll b/test/CodeGen/Mips/Fast-ISel/rem1.ll index cf709e7e4954..a5cc24361e6a 100644 --- a/test/CodeGen/Mips/Fast-ISel/rem1.ll +++ b/test/CodeGen/Mips/Fast-ISel/rem1.ll @@ -22,7 +22,7 @@ define void @rems() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: div $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @sj, align 4 @@ -45,7 +45,7 @@ define void @remu() { ; CHECK-DAG: lw $[[J:[0-9]+]], 0($[[J_ADDR]]) ; CHECK-DAG: lw $[[K:[0-9]+]], 0($[[K_ADDR]]) ; CHECK-DAG: divu $zero, $[[J]], $[[K]] - ; CHECK_DAG: teq $[[K]], $zero, 7 + ; CHECK-DAG: teq $[[K]], $zero, 7 ; CHECK-DAG: mfhi $[[RESULT:[0-9]+]] ; CHECK: sw $[[RESULT]], 0($[[I_ADDR]]) %1 = load i32, i32* @uj, align 4 diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll index 9fe694bb5827..651fb6ad1f5a 100644 --- a/test/CodeGen/Mips/Fast-ISel/shift.ll +++ b/test/CodeGen/Mips/Fast-ISel/shift.ll @@ -1,5 +1,5 @@ ; RUN: llc -march=mipsel -mcpu=mips32r2 -O0 -fast-isel=true -filetype=obj %s -o - \ -; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s +; RUN: | llvm-objdump -d - | FileCheck %s ; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used. diff --git a/test/CodeGen/Mips/abicalls.ll b/test/CodeGen/Mips/abicalls.ll index 7edc3e25c352..26bbab40b3b3 100644 --- a/test/CodeGen/Mips/abicalls.ll +++ b/test/CodeGen/Mips/abicalls.ll @@ -1,7 +1,7 @@ -; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=STATIC %s -; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s -; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefix=ABICALLS -check-prefix=PIC %s +; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,STATIC %s +; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -relocation-model=pic %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s +; RUN: llc -filetype=asm -mtriple mips64el-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefixes=ABICALLS,PIC %s ; RUN: llc -filetype=asm -mtriple mipsel-unknown-linux -mcpu=mips32 -mattr noabicalls -relocation-model=static %s -o - | FileCheck -implicit-check-not='.abicalls' -implicit-check-not='pic0' %s diff --git a/test/CodeGen/Mips/adjust-callstack-sp.ll b/test/CodeGen/Mips/adjust-callstack-sp.ll index e4afcd835005..32d77ac19ae6 100644 --- a/test/CodeGen/Mips/adjust-callstack-sp.ll +++ b/test/CodeGen/Mips/adjust-callstack-sp.ll @@ -2,18 +2,18 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips3 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64 | FileCheck %s -check-prefix=GP64 -; RUN: llc < %s -march=mips -mcpu=mips64r6 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips3 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64 -target-abi n64 | FileCheck %s -check-prefix=GP64 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 | FileCheck %s -check-prefix=GP64 declare void @bar(i32*) define void @foo(i32 %sz) { ; ALL-LABEL: foo: - ; M16-NOT: addiu $sp, 0 # 16 bit inst - ; GP32-NOT: addiu $sp, $sp, 0 - ; GP64-NOT: daddiu $sp, $sp, 0 + ; M16-NOT: addiu $sp, 0 # 16 bit inst + ; GP32-NOT: addiu $sp, $sp, 0 + ; GP64-NOT: daddiu $sp, $sp, 0 %a = alloca i32, i32 %sz call void @bar(i32* %a) ret void diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll index 747a1362161d..b708ddb134ce 100644 --- a/test/CodeGen/Mips/alloca.ll +++ b/test/CodeGen/Mips/alloca.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s define i32 @twoalloca(i32 %size) nounwind { entry: diff --git a/test/CodeGen/Mips/analyzebranch.ll b/test/CodeGen/Mips/analyzebranch.ll index d5ecaaeddc33..377fe9327e0e 100644 --- a/test/CodeGen/Mips/analyzebranch.ll +++ b/test/CodeGen/Mips/analyzebranch.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR -; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=FCC -; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64r2 < %s | FileCheck %s -check-prefixes=ALL,FCC +; RUN: llc -march=mips64 -mcpu=mips64r6 < %s | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define double @foo(double %a, double %b) nounwind readnone { entry: @@ -19,7 +19,7 @@ entry: ; GPR: cmp.lt.d $[[FGRCC:f[0-9]+]], $[[Z]], $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB +; GPR: bnezc $[[GPRCC]], $BB %cmp = fcmp ogt double %a, 0.000000e+00 br i1 %cmp, label %if.end6, label %if.else @@ -50,7 +50,8 @@ entry: ; GPR: cmp.eq.s $[[FGRCC:f[0-9]+]], $f12, $[[Z]] ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB +; 64-GPR beqzc $[[GPRCC]], $BB +; 32-GPR beqz $[[GPRCC]], $BB %cmp = fcmp une float %f, 0.000000e+00 br i1 %cmp, label %if.then, label %if.end diff --git a/test/CodeGen/Mips/assertzext-trunc.ll b/test/CodeGen/Mips/assertzext-trunc.ll new file mode 100644 index 000000000000..2295727834eb --- /dev/null +++ b/test/CodeGen/Mips/assertzext-trunc.ll @@ -0,0 +1,62 @@ +; RUN: llc < %s -march=mips64 -mcpu=mips3 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | \ +; RUN: FileCheck %s -check-prefixes=ALL,PRE-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ +; RUN: FileCheck %s -check-prefixes=ALL,R6 + +; Check that we don't emit redundant SLLs for sequences of +; (AssertZext:i32 (trunc:i32 (AssertZext:i64 X, i32)), i8) +define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: udiv_i8: + + ; PRE-R6-NOT: sll {{.*}} + ; PRE-R6: divu $zero, $4, $5 + ; PRE-R6: teq $5, $zero, 7 + ; PRE-R6: mflo $2 + + ; R6-NOT: sll {{.*}} + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i8 %a, %b + ret i8 %r +} + +; Check that we do sign-extend when we have a (trunc:i32 (AssertZext:i64 X, i32)) +define i64 @foo1(i64 zeroext %var) { +entry: +; ALL-LABEL: foo1: + + %shr = lshr i64 %var, 32 + %cmp = icmp eq i64 %shr, 0 + br i1 %cmp, label %if.end6, label %if.then + + ; ALL: dsrl $[[T0:[0-9]+]], $4, 32 + ; ALL: sll $[[T1:[0-9]+]], $[[T0]], 0 + if.then: ; preds = %entry + %conv = trunc i64 %shr to i32 + %cmp2 = icmp slt i32 %conv, 0 + br i1 %cmp2, label %if.then4, label %if.else + + if.then4: ; preds = %if.then + %add = add i64 %var, 16 + br label %if.end6 + + if.else: ; preds = %if.then + %add5 = add i64 %var, 32 + br label %if.end6 + + if.end6: ; preds = %entry, %if.then4, %if.else + %var.addr.0 = phi i64 [ %add, %if.then4 ], [ %add5, %if.else ], [ %var, %entry ] + ret i64 %var.addr.0 +} diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll index 031cce0b6074..8f4ccb19958a 100644 --- a/test/CodeGen/Mips/atomic.ll +++ b/test/CodeGen/Mips/atomic.ll @@ -1,15 +1,26 @@ -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=NOT-MICROMIPS -; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=HAS-SEB-SEH -check-prefix=CHECK-EL -check-prefix=MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r6 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6 +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips4 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,NO-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r2 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,NOT-MICROMIPS +; RUN: llc -march=mips64el --disable-machine-licm -mcpu=mips64r6 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS64-ANY,HAS-SEB-SEH,CHECK-EL,MIPSR6 +; RUN: llc -march=mips64 -O0 -mcpu=mips64r6 -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL-LABEL,MIPS64-ANY,O0 +; RUN: llc -march=mipsel --disable-machine-licm -mcpu=mips32r2 -mattr=micromips -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,HAS-SEB-SEH,CHECK-EL,MICROMIPS ; Keep one big-endian check so that we don't reduce testing, but don't add more ; since endianness doesn't affect the body of the atomic operations. -; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32-ANY -check-prefix=NO-SEB-SEH -check-prefix=CHECK-EB -check-prefix=NOT-MICROMIPS +; RUN: llc -march=mips --disable-machine-licm -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MIPS32-ANY,NO-SEB-SEH,CHECK-EB,NOT-MICROMIPS @x = common global i32 0, align 4 @@ -23,12 +34,17 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R1:[0-9]+]] +; O0-NEXT: ll $[[R2:[0-9]+]], 0($[[R1]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) -; ALL: addu $[[R2:[0-9]+]], $[[R1]], $4 -; ALL: sc $[[R2]], 0($[[R0]]) -; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] -; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; ALL: ll $[[R3:[0-9]+]], 0($[[R0]]) +; ALL: addu $[[R4:[0-9]+]], $[[R3]], $4 +; ALL: sc $[[R4]], 0($[[R0]]) +; NOT-MICROMIPS: beqz $[[R4]], $[[BB0]] +; MICROMIPS: beqzc $[[R4]], $[[BB0]] +; MIPSR6: beqzc $[[R4]], $[[BB0]] } define i32 @AtomicLoadNand32(i32 signext %incr) nounwind { @@ -41,6 +57,8 @@ entry: ; MIPS32-ANY: lw $[[R0:[0-9]+]], %got(x) ; MIPS64-ANY: ld $[[R0:[0-9]+]], %got_disp(x)( + + ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R1:[0-9]+]], 0($[[R0]]) ; ALL: and $[[R3:[0-9]+]], $[[R1]], $4 @@ -48,6 +66,7 @@ entry: ; ALL: sc $[[R2]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicSwap32(i32 signext %newval) nounwind { @@ -68,6 +87,7 @@ entry: ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind { @@ -86,10 +106,13 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $2, 0($[[R0]]) -; ALL: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $2, $4, $[[BB1:[A-Z_0-9]+]] ; ALL: sc $[[R2:[0-9]+]], 0($[[R0]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] ; ALL: $[[BB1]]: } @@ -118,23 +141,28 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 +; NO-SEB-SEH: sra $2, $[[R19]], 24 -; HAS-SEB-SEH: seb $2, $[[R16]] +; HAS-SEB-SEH: seb $2, $[[R18]] } define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { @@ -158,23 +186,28 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: subu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 24 +; NO-SEB-SEH: sra $2, $[[R19]], 24 -; HAS-SEB-SEH:seb $2, $[[R16]] +; HAS-SEB-SEH:seb $2, $[[R18]] } define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { @@ -198,24 +231,29 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] -; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] -; ALL: nor $[[R11:[0-9]+]], $zero, $[[R18]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] - -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 24 -; NO-SEB-SEH: sra $2, $[[R17]], 24 - -; HAS-SEB-SEH: seb $2, $[[R16]] +; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: and $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: nor $[[R14:[0-9]+]], $zero, $[[R13]] +; ALL: and $[[R15:[0-9]+]], $[[R14]], $[[R7]] +; ALL: and $[[R16:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R17:[0-9]+]], $[[R16]], $[[R15]] +; ALL: sc $[[R17]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R17]], $[[BB0]] +; MICROMIPS: beqzc $[[R17]], $[[BB0]] +; MIPSR6: beqzc $[[R17]], $[[BB0]] + +; ALL: and $[[R18:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R19:[0-9]+]], $[[R18]], $[[R5]] + +; NO-SEB-SEH: sll $[[R20:[0-9]+]], $[[R19]], 24 +; NO-SEB-SEH: sra $2, $[[R20]], 24 + +; HAS-SEB-SEH: seb $2, $[[R19]] } define signext i8 @AtomicSwap8(i8 signext %newval) nounwind { @@ -247,6 +285,7 @@ entry: ; ALL: sc $[[R14]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] ; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; MIPSR6: beqzc $[[R14]], $[[BB0]] ; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] ; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] @@ -286,13 +325,16 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -327,13 +369,16 @@ entry: ; ALL: $[[BB0:[A-Z_0-9]+]]: ; ALL: ll $[[R13:[0-9]+]], 0($[[R2]]) ; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] -; ALL: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; NOT-MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MICROMIPS: bne $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] +; MIPSR6: bnec $[[R14]], $[[R10]], $[[BB1:[A-Z_0-9]+]] ; ALL: and $[[R15:[0-9]+]], $[[R13]], $[[R8]] ; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R12]] ; ALL: sc $[[R16]], 0($[[R2]]) ; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] ; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] ; ALL: $[[BB1]]: ; ALL: srlv $[[R17:[0-9]+]], $[[R14]], $[[R5]] @@ -341,10 +386,17 @@ entry: ; NO-SEB-SEH: sll $[[R18:[0-9]+]], $[[R17]], 24 ; NO-SEB-SEH: sra $[[R19:[0-9]+]], $[[R18]], 24 +; FIXME: -march=mips produces a redundant sign extension here... +; NO-SEB-SEH: sll $[[R20:[0-9]+]], $5, 24 +; NO-SEB-SEH: sra $[[R20]], $[[R20]], 24 + ; HAS-SEB-SEH: seb $[[R19:[0-9]+]], $[[R17]] -; ALL: xor $[[R20:[0-9]+]], $[[R19]], $5 -; ALL: sltiu $2, $[[R20]], 1 +; FIXME: ...Leading to this split check. +; NO-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $[[R20]] +; HAS-SEB-SEH: xor $[[R21:[0-9]+]], $[[R19]], $5 + +; ALL: sltiu $2, $[[R21]], 1 } ; Check one i16 so that we cover the seh sign extend @@ -371,25 +423,73 @@ entry: ; ALL: nor $[[R8:[0-9]+]], $zero, $[[R7]] ; ALL: sllv $[[R9:[0-9]+]], $4, $[[R5]] +; O0: $[[BB0:[A-Z_0-9]+]]: +; O0: ld $[[R10:[0-9]+]] +; O0-NEXT: ll $[[R11:[0-9]+]], 0($[[R10]]) + ; ALL: $[[BB0:[A-Z_0-9]+]]: -; ALL: ll $[[R10:[0-9]+]], 0($[[R2]]) -; ALL: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] -; ALL: and $[[R12:[0-9]+]], $[[R11]], $[[R7]] -; ALL: and $[[R13:[0-9]+]], $[[R10]], $[[R8]] -; ALL: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] -; ALL: sc $[[R14]], 0($[[R2]]) -; NOT-MICROMIPS: beqz $[[R14]], $[[BB0]] -; MICROMIPS: beqzc $[[R14]], $[[BB0]] +; ALL: ll $[[R12:[0-9]+]], 0($[[R2]]) +; ALL: addu $[[R13:[0-9]+]], $[[R12]], $[[R9]] +; ALL: and $[[R14:[0-9]+]], $[[R13]], $[[R7]] +; ALL: and $[[R15:[0-9]+]], $[[R12]], $[[R8]] +; ALL: or $[[R16:[0-9]+]], $[[R15]], $[[R14]] +; ALL: sc $[[R16]], 0($[[R2]]) +; NOT-MICROMIPS: beqz $[[R16]], $[[BB0]] +; MICROMIPS: beqzc $[[R16]], $[[BB0]] +; MIPSR6: beqzc $[[R16]], $[[BB0]] -; ALL: and $[[R15:[0-9]+]], $[[R10]], $[[R7]] -; ALL: srlv $[[R16:[0-9]+]], $[[R15]], $[[R5]] +; ALL: and $[[R17:[0-9]+]], $[[R12]], $[[R7]] +; ALL: srlv $[[R18:[0-9]+]], $[[R17]], $[[R5]] -; NO-SEB-SEH: sll $[[R17:[0-9]+]], $[[R16]], 16 -; NO-SEB-SEH: sra $2, $[[R17]], 16 +; NO-SEB-SEH: sll $[[R19:[0-9]+]], $[[R18]], 16 +; NO-SEB-SEH: sra $2, $[[R19]], 16 -; MIPS32R2: seh $2, $[[R16]] +; MIPS32R2: seh $2, $[[R18]] } +; Test that the i16 return value from cmpxchg is recognised as signed, +; so that setCC doesn't end up comparing an unsigned value to a signed +; value. +; The rest of the functions here are testing the atomic expansion, so +; we just match the end of the function. +define {i16, i1} @foo(i16* %addr, i16 %l, i16 %r, i16 %new) { + %desired = add i16 %l, %r + %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst seq_cst + ret {i16, i1} %res + +; ALL-LABEL: foo +; MIPSR6: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] +; NOT-MICROMIPS: addu $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] +; MICROMIPS: addu16 $[[R2:[0-9]+]], $[[R1:[0-9]+]], $[[R0:[0-9]+]] + +; ALL: sync + +; ALL: andi $[[R3:[0-9]+]], $[[R2]], 65535 +; ALL: $[[BB0:[A-Z_0-9]+]]: +; ALL: ll $[[R4:[0-9]+]], 0($[[R5:[0-9]+]]) +; ALL: and $[[R6:[0-9]+]], $[[R4]], $ +; ALL: and $[[R7:[0-9]+]], $[[R4]], $ +; ALL: or $[[R8:[0-9]+]], $[[R7]], $ +; ALL: sc $[[R8]], 0($[[R5]]) +; NOT-MICROMIPS: beqz $[[R8]], $[[BB0]] +; MICROMIPS: beqzc $[[R8]], $[[BB0]] +; MIPSR6: beqzc $[[R8]], $[[BB0]] + +; ALL: srlv $[[R9:[0-9]+]], $[[R6]], $ + +; NO-SEB-SEH: sll $[[R10:[0-9]+]], $[[R9]], 16 +; NO-SEB-SEH: sra $[[R11:[0-9]+]], $[[R10]], 16 + +; NO-SEB-SEH: sll $[[R12:[0-9]+]], $[[R2]], 16 +; NO-SEB-SEH: sra $[[R13:[0-9]+]], $[[R12]], 16 + +; HAS-SEB-SEH: seh $[[R11:[0-9]+]], $[[R9]] +; HAS-SEB-SEH: seh $[[R13:[0-9]+]], $[[R2]] + +; ALL: xor $[[R12:[0-9]+]], $[[R11]], $[[R13]] +; ALL: sltiu $3, $[[R12]], 1 +; ALL: sync +} @countsint = common global i32 0, align 4 @@ -444,4 +544,5 @@ entry: ; ALL: sc $[[R2]], 0($[[PTR]]) ; NOT-MICROMIPS: beqz $[[R2]], $[[BB0]] ; MICROMIPS: beqzc $[[R2]], $[[BB0]] +; MIPSR6: beqzc $[[R2]], $[[BB0]] } diff --git a/test/CodeGen/Mips/atomicCmpSwapPW.ll b/test/CodeGen/Mips/atomicCmpSwapPW.ll new file mode 100644 index 000000000000..981f0983fa4c --- /dev/null +++ b/test/CodeGen/Mips/atomicCmpSwapPW.ll @@ -0,0 +1,17 @@ +; RUN: llc -O0 -march=mipsel -mcpu=mips32r2 -target-abi=o32 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR32,ALL %s +; RUN: llc -O0 -march=mips64el -mcpu=mips64r2 -target-abi=n32 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR32,ALL %s +; RUN: llc -O0 -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s -filetype=asm -o - \ +; RUN: | FileCheck -check-prefixes=PTR64,ALL %s + +; PTR32: lw $[[R0:[0-9]+]] +; PTR64: ld $[[R0:[0-9]+]] + +; ALL: ll ${{[0-9]+}}, 0($[[R0]]) + +define {i16, i1} @foo(i16* %addr, i16 signext %r, i16 zeroext %new) { + %res = cmpxchg i16* %addr, i16 %r, i16 %new seq_cst seq_cst + ret {i16, i1} %res +} + diff --git a/test/CodeGen/Mips/biggot.ll b/test/CodeGen/Mips/biggot.ll index b56ce6ba87b1..aafaf55ae184 100644 --- a/test/CodeGen/Mips/biggot.ll +++ b/test/CodeGen/Mips/biggot.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel -mxgot < %s | FileCheck %s -check-prefix=O32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -mxgot < %s | \ +; RUN: llc -march=mipsel -mxgot -relocation-model=pic < %s | FileCheck %s -check-prefix=O32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -mxgot -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=N64 @v0 = external global i32 diff --git a/test/CodeGen/Mips/brdelayslot.ll b/test/CodeGen/Mips/brdelayslot.ll index 0f46619b8272..3a5d4dcded26 100644 --- a/test/CodeGen/Mips/brdelayslot.ll +++ b/test/CodeGen/Mips/brdelayslot.ll @@ -1,23 +1,24 @@ ; RUN: llc -march=mipsel -O0 < %s | FileCheck %s -check-prefix=None -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=Default +; RUN: llc -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefix=Default ; RUN: llc -march=mipsel -O1 -relocation-model=static < %s | \ ; RUN: FileCheck %s -check-prefix=STATICO1 ; RUN: llc -march=mipsel -disable-mips-df-forward-search=false \ ; RUN: -relocation-model=static < %s | FileCheck %s -check-prefix=FORWARD -; RUN: llc -march=mipsel -disable-mips-df-backward-search \ -; RUN: -disable-mips-df-succbb-search=false < %s | \ +; RUN: llc -march=mipsel -disable-mips-df-backward-search -relocation-model=pic \ +; RUN: -disable-mips-df-succbb-search=false -disable-preheader-prot=true < %s | \ ; RUN: FileCheck %s -check-prefix=SUCCBB define void @foo1() nounwind { entry: -; Default: jalr -; Default-NOT: nop -; Default: jr +; Default: jalr +; Default-NOT: nop +; Default: jr ; Default-NOT: nop ; Default: .end -; None: jalr -; None: nop -; None: jr +; None: jalr +; None: nop +; None: jr ; None: nop ; None: .end diff --git a/test/CodeGen/Mips/brsize3.ll b/test/CodeGen/Mips/brsize3.ll index 1e76879409c6..ce8b8f6e35b1 100644 --- a/test/CodeGen/Mips/brsize3.ll +++ b/test/CodeGen/Mips/brsize3.ll @@ -1,6 +1,12 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-no-short +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ +; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=b-no-short -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -mattr=+soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=b-long +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -mattr=+soft-float -mips16-hard-float -relocation-model=pic \ +; RUN: -mips16-constant-islands -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=b-long ; ModuleID = 'brsize3.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64" diff --git a/test/CodeGen/Mips/buildpairextractelementf64.ll b/test/CodeGen/Mips/buildpairextractelementf64.ll index 7682a98ace99..19ef04f040d8 100644 --- a/test/CodeGen/Mips/buildpairextractelementf64.ll +++ b/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips < %s | FileCheck %s -check-prefix=NO-MFHC1 -check-prefix=ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefix=HAS-MFHC1 -check-prefix=ALL +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -march=mips < %s | FileCheck %s -check-prefixes=NO-MFHC1,ALL +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck %s -check-prefixes=HAS-MFHC1,ALL @a = external global i32 diff --git a/test/CodeGen/Mips/call-optimization.ll b/test/CodeGen/Mips/call-optimization.ll index bfa09eaae3cb..762b00effc97 100644 --- a/test/CodeGen/Mips/call-optimization.ll +++ b/test/CodeGen/Mips/call-optimization.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | \ +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=O32 ; RUN: llc -march=mipsel -mips-load-target-from-got=false \ -; RUN: -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=O32-LOADTGT +; RUN: -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-LOADTGT @gd1 = common global double 0.000000e+00, align 8 @gd2 = common global double 0.000000e+00, align 8 diff --git a/test/CodeGen/Mips/cannot-copy-registers.ll b/test/CodeGen/Mips/cannot-copy-registers.ll new file mode 100644 index 000000000000..75cceb2011eb --- /dev/null +++ b/test/CodeGen/Mips/cannot-copy-registers.ll @@ -0,0 +1,24 @@ +; RUN: llc -march=mips64 -mcpu=mips64r6 -mattr=+micromips \ +; RUN: -relocation-model=pic -O3 < %s + +; Check that message "Cannot copy registers" is not asserted in case of microMIPS64r6. + +@x = global i32 65504, align 4 +@y = global i32 60929, align 4 +@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32, i32* @x, align 4 + %and1 = and i32 %0, 4 + %call1 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds + ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and1) + + %1 = load i32, i32* @y, align 4 + %and2 = and i32 %1, 5 + %call2 = call i32 (i8*, ...) @printf(i8* getelementptr inbounds + ([7 x i8], [7 x i8]* @.str, i32 0, i32 0), i32 %and2) + ret i32 0 +} + +declare i32 @printf(i8*, ...) diff --git a/test/CodeGen/Mips/cconv/arguments-float.ll b/test/CodeGen/Mips/cconv/arguments-float.ll index c81c7215e164..a76cf6226dc0 100644 --- a/test/CodeGen/Mips/cconv/arguments-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the floating point arguments for all ABI's and byte orders as specified ; by section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/arguments-fp128.ll b/test/CodeGen/Mips/cconv/arguments-fp128.ll index 6c62609396c5..70df97608aa9 100644 --- a/test/CodeGen/Mips/cconv/arguments-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s -; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s -; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s +; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s +; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s ; Test the fp128 arguments for all ABI's and byte orders as specified ; by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll index 9f1fe91ec172..5f7a86534bdf 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float-varargs.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWBE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=N32 --check-prefix=NEW --check-prefix=NEWLE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,N32,NEW,NEWBE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,N32,NEW,NEWLE %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWBE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=N64 --check-prefix=NEW --check-prefix=NEWLE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWBE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,N64,NEW,NEWLE %s ; Test the effect of varargs on floating point types in the non-variable part ; of the argument list as specified by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-hard-float.ll b/test/CodeGen/Mips/cconv/arguments-hard-float.ll index 24148ed176db..2e753d0f07cb 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-float.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32BE %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 --check-prefix=O32LE %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the floating point arguments for all ABI's and byte orders as specified ; by section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll index 26eb569f865d..1a3b664d9159 100644 --- a/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/arguments-hard-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64 %s ; Test the fp128 arguments for all ABI's and byte orders as specified ; by section 2 of the MIPSpro N32 Handbook. diff --git a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll index 087a0515f379..56f9a64908bc 100644 --- a/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll +++ b/test/CodeGen/Mips/cconv/arguments-small-structures-bigger-than-32bits.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL -; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEB -; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=MIPSEL +; RUN: llc < %s -march=mips64 -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n64 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL +; RUN: llc < %s -march=mips64 -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEB +; RUN: llc < %s -march=mips64el -target-abi n32 -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,MIPSEL ; #include ; diff --git a/test/CodeGen/Mips/cconv/arguments-struct.ll b/test/CodeGen/Mips/cconv/arguments-struct.ll index ee6bfaeb9537..44ea7c0f8337 100644 --- a/test/CodeGen/Mips/cconv/arguments-struct.ll +++ b/test/CodeGen/Mips/cconv/arguments-struct.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s +; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s -; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-BE %s -; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32-LE %s +; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s +; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s -; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-BE %s +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-LE %s -; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW-BE %s +; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW-LE %s ; Test small structures for all ABI's and byte orders. ; diff --git a/test/CodeGen/Mips/cconv/arguments-varargs.ll b/test/CodeGen/Mips/cconv/arguments-varargs.ll index d1a196738aee..9c20b882dcb6 100644 --- a/test/CodeGen/Mips/cconv/arguments-varargs.ll +++ b/test/CodeGen/Mips/cconv/arguments-varargs.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-linux -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-BE %s +; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-LE %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-BE %s -; RUN: llc -mtriple=mips64el-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N32 --check-prefix=NEW-LE %s +; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,NEW,N32,NEW-BE %s +; RUN: llc -mtriple=mips64el-linux -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,NEW,N32,NEW-LE %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-BE %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=NEW --check-prefix=N64 --check-prefix=NEW-LE %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,NEW,N64,NEW-BE %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,NEW,N64,NEW-LE %s @hwords = global [3 x i16] zeroinitializer, align 1 @words = global [3 x i32] zeroinitializer, align 1 diff --git a/test/CodeGen/Mips/cconv/arguments.ll b/test/CodeGen/Mips/cconv/arguments.ll index 430705f8d418..7af4e5517d51 100644 --- a/test/CodeGen/Mips/cconv/arguments.ll +++ b/test/CodeGen/Mips/cconv/arguments.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN: llc -march=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s +; RUN-TODO: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM32 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=SYM64 --check-prefix=NEW %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s ; Test the integer arguments for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/callee-saved-float.ll b/test/CodeGen/Mips/cconv/callee-saved-float.ll index c84f0f439c26..30a5727f344d 100644 --- a/test/CodeGen/Mips/cconv/callee-saved-float.ll +++ b/test/CodeGen/Mips/cconv/callee-saved-float.ll @@ -1,22 +1,24 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=O32-INV %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N32-INV %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N32-INV %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=ALL-INV --check-prefix=N64-INV %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,ALL-INV,N64-INV %s + +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -filetype=obj < %s -o - | llvm-objdump -no-show-raw-insn -arch mips -mcpu=mips32r6 -mattr=micromips -d - | FileCheck --check-prefix=MM32R6 %s ; Test the the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. @@ -109,3 +111,6 @@ entry: ; N64-DAG: ldc1 [[F30]], [[OFF30]]($sp) ; N64-DAG: ldc1 [[F31]], [[OFF31]]($sp) ; N64: addiu $sp, $sp, 64 + +; Check the mapping between LDC164 and LDC1_64_MMR6. +; MM32R6: ldc1 diff --git a/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll index 4b28b9962075..bd33e0c51697 100644 --- a/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll +++ b/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll @@ -1,12 +1,12 @@ -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX %s -; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s -; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefix=ALL --check-prefix=O32-FPXX-INV --check-prefix=O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s +; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s +; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s define void @fpu_clobber() nounwind { entry: diff --git a/test/CodeGen/Mips/cconv/callee-saved.ll b/test/CodeGen/Mips/cconv/callee-saved.ll index 0570ab35fd00..b7e94f882282 100644 --- a/test/CodeGen/Mips/cconv/callee-saved.ll +++ b/test/CodeGen/Mips/cconv/callee-saved.ll @@ -1,22 +1,22 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32-INV %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32-INV %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32-INV %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32-INV %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32-INV %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32-INV %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64-INV %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64-INV %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64-INV %s ; Test the callee-saved registers are callee-saved as specified by section ; 2 of the MIPSpro N32 Handbook and section 3 of the SYSV ABI spec. diff --git a/test/CodeGen/Mips/cconv/memory-layout.ll b/test/CodeGen/Mips/cconv/memory-layout.ll index 33a68da157f6..e992169f6b64 100644 --- a/test/CodeGen/Mips/cconv/memory-layout.ll +++ b/test/CodeGen/Mips/cconv/memory-layout.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the memory layout for all ABI's and byte orders as specified by section ; 4 of MD00305 (MIPS ABIs Described). @@ -27,39 +27,39 @@ @double = global double 1.0, align 1 @pointer = global i8* @byte -; ALL-NOT: .align +; ALL-NOT: .p2align ; ALL-LABEL: byte: ; ALL: .byte 1 ; ALL: .size byte, 1 -; ALL: .align 1 +; ALL: .p2align 1 ; ALL-LABEL: halfword: ; ALL: .2byte 258 ; ALL: .size halfword, 2 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: word: ; ALL: .4byte 16909060 ; ALL: .size word, 4 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: float: ; ALL: .4byte 1065353216 ; ALL: .size float, 4 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: dword: ; ALL: .8byte 283686952306183 ; ALL: .size dword, 8 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: double: ; ALL: .8byte 4607182418800017408 ; ALL: .size double, 8 -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL-LABEL: pointer: ; O32: .4byte byte ; O32: .size pointer, 4 @@ -76,44 +76,44 @@ @double_array = global [2 x double] [double 1.0, double 2.0], align 1 @pointer_array = global [2 x i8*] [i8* @byte, i8* @byte] -; ALL-NOT: .align +; ALL-NOT: .p2align ; ALL-LABEL: byte_array: ; ALL: .ascii "\001\002" ; ALL: .size byte_array, 2 -; ALL: .align 1 +; ALL: .p2align 1 ; ALL-LABEL: halfword_array: ; ALL: .2byte 1 ; ALL: .2byte 2 ; ALL: .size halfword_array, 4 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: word_array: ; ALL: .4byte 1 ; ALL: .4byte 2 ; ALL: .size word_array, 8 -; ALL: .align 2 +; ALL: .p2align 2 ; ALL-LABEL: float_array: ; ALL: .4byte 1065353216 ; ALL: .4byte 1073741824 ; ALL: .size float_array, 8 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: dword_array: ; ALL: .8byte 1 ; ALL: .8byte 2 ; ALL: .size dword_array, 16 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: double_array: ; ALL: .8byte 4607182418800017408 ; ALL: .8byte 4611686018427387904 ; ALL: .size double_array, 16 -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL-LABEL: pointer_array: ; O32: .4byte byte ; O32: .4byte byte @@ -128,7 +128,7 @@ %mixed = type { i8, double, i16 } @mixed = global %mixed { i8 1, double 1.0, i16 515 }, align 1 -; ALL: .align 3 +; ALL: .p2align 3 ; ALL-LABEL: mixed: ; ALL: .byte 1 ; ALL: .space 7 diff --git a/test/CodeGen/Mips/cconv/reserved-space.ll b/test/CodeGen/Mips/cconv/reserved-space.ll index 23190c2790cc..a17377ba0e56 100644 --- a/test/CodeGen/Mips/cconv/reserved-space.ll +++ b/test/CodeGen/Mips/cconv/reserved-space.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test that O32 correctly reserved space for the four arguments, even when ; there aren't any as per section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-float.ll b/test/CodeGen/Mips/cconv/return-float.ll index 8eb8c411e081..b9a6d6c5bc0d 100644 --- a/test/CodeGen/Mips/cconv/return-float.ll +++ b/test/CodeGen/Mips/cconv/return-float.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+soft-float -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -mattr=+soft-float -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the float returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-float.ll b/test/CodeGen/Mips/cconv/return-hard-float.ll index 14853c8ca6f7..768cb6a9f2c6 100644 --- a/test/CodeGen/Mips/cconv/return-hard-float.ll +++ b/test/CodeGen/Mips/cconv/return-hard-float.ll @@ -1,17 +1,17 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefix=ALL --check-prefix=032FP64 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static -mattr=+o32,+fp64 < %s | FileCheck --check-prefixes=ALL,032FP64 %s ; Test the float returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-fp128.ll b/test/CodeGen/Mips/cconv/return-hard-fp128.ll index 34e9647acddd..bdbfb80bd4aa 100644 --- a/test/CodeGen/Mips/cconv/return-hard-fp128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-fp128.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the fp128 returns for N32/N64 and all byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll index c4c8f10ca3b4..9b178e4380d1 100644 --- a/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll +++ b/test/CodeGen/Mips/cconv/return-hard-struct-f128.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test return of {fp128} agrees with de-facto N32/N64 ABI. diff --git a/test/CodeGen/Mips/cconv/return-struct.ll b/test/CodeGen/Mips/cconv/return-struct.ll index 8decd04f089b..da20919ffd42 100644 --- a/test/CodeGen/Mips/cconv/return-struct.ll +++ b/test/CodeGen/Mips/cconv/return-struct.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-BE %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 --check-prefix=O32-LE %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-BE %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32,O32-LE %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-BE %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 --check-prefix=N32-LE %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32,N32-BE %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32,N32-LE %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-BE %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 --check-prefix=N64-LE %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64,N64-BE %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64,N64-LE %s ; Test struct returns for all ABI's and byte orders. @@ -158,9 +158,6 @@ entry: ; sret pointer is already in $4 ; N32-DAG: lui [[PTR_HI:\$[0-9]+]], %hi(struct_128xi16) ; N32-DAG: addiu [[PTR:\$[0-9]+]], [[PTR_HI]], %lo(struct_128xi16) -; FIXME: This signext isn't necessary. Like integers, pointers are -; but unlike integers, pointers cannot have the signext attribute. -; N32-DAG: sll $5, [[PTR]], 0 ; N32: jal memcpy ; sret pointer is already in $4 diff --git a/test/CodeGen/Mips/cconv/return.ll b/test/CodeGen/Mips/cconv/return.ll index a53767275434..561c94cb5783 100644 --- a/test/CodeGen/Mips/cconv/return.ll +++ b/test/CodeGen/Mips/cconv/return.ll @@ -1,14 +1,14 @@ -; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -mtriple=mips-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -mtriple=mips64-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-gnu -relocation-model=static -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the integer returns for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cconv/roundl-call.ll b/test/CodeGen/Mips/cconv/roundl-call.ll new file mode 100644 index 000000000000..8e4d6597784c --- /dev/null +++ b/test/CodeGen/Mips/cconv/roundl-call.ll @@ -0,0 +1,40 @@ +; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n32 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N32,HARD-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,HARD-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n32 \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,N32,SOFT-FLOAT + +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < %s \ +; RUN: | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=+soft-float -target-abi=n64 < \ +; RUN: %s | FileCheck %s -check-prefixes=ALL,N64,SOFT-FLOAT + +@fp128 = global fp128 zeroinitializer + +define void @roundl_call(fp128 %value) { +entry: +; ALL-LABEL: roundl_call: +; N32: lw $25, %call16(roundl)($gp) +; N64: ld $25, %call16(roundl)($gp) + +; SOFT-FLOAT: sd $4, 8(${{[0-9]+}}) +; SOFT-FLOAT: sd $2, 0(${{[0-9]+}}) + +; HARD-FLOAT: sdc1 $f2, 8(${{[0-9]+}}) +; HARD-FLOAT: sdc1 $f0, 0(${{[0-9]+}}) + + %call = call fp128 @roundl(fp128 %value) + store fp128 %call, fp128* @fp128 + ret void +} + +declare fp128 @roundl(fp128) nounwind readnone diff --git a/test/CodeGen/Mips/cconv/stack-alignment.ll b/test/CodeGen/Mips/cconv/stack-alignment.ll index f21bc3066f72..c957e311b1b3 100644 --- a/test/CodeGen/Mips/cconv/stack-alignment.ll +++ b/test/CodeGen/Mips/cconv/stack-alignment.ll @@ -1,14 +1,14 @@ -; RUN: llc -march=mips < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN: llc -march=mipsel < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN: llc -march=mips < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s -; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefix=ALL --check-prefix=O32 %s +; RUN-TODO: llc -march=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s +; RUN-TODO: llc -march=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s -; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefix=ALL --check-prefix=N32 %s +; RUN: llc -march=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s -; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s -; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefix=ALL --check-prefix=N64 %s +; RUN: llc -march=mips64 -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -target-abi n64 < %s | FileCheck --check-prefixes=ALL,N64 %s ; Test the stack alignment for all ABI's and byte orders as specified by ; section 5 of MD00305 (MIPS ABIs Described). diff --git a/test/CodeGen/Mips/cfi_offset.ll b/test/CodeGen/Mips/cfi_offset.ll index 97233328fd55..0e85ea0a42be 100644 --- a/test/CodeGen/Mips/cfi_offset.ll +++ b/test/CodeGen/Mips/cfi_offset.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL -; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EB -; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-EL +; RUN: llc -march=mips -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL +; RUN: llc -march=mips -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EB +; RUN: llc -march=mipsel -mattr=+o32,+fp64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-EL @var = global double 0.0 diff --git a/test/CodeGen/Mips/check-adde-redundant-moves.ll b/test/CodeGen/Mips/check-adde-redundant-moves.ll index 7bc63a494ac7..cf0fda66ad62 100644 --- a/test/CodeGen/Mips/check-adde-redundant-moves.ll +++ b/test/CodeGen/Mips/check-adde-redundant-moves.ll @@ -1,15 +1,9 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s -check-prefix=ALL ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index a8008a2cb29f..b0ef2b973d6a 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32 -regalloc=basic -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,32-CMP +; RUN: llc -march=mips64el -mcpu=mips4 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -march=mips64el -mcpu=mips64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc -march=mips64el -mcpu=mips64r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,64-CMP @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 @@ -521,14 +521,14 @@ entry: ; 64-CMOV-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 ; 64-CMOV-DAG: movn $[[I4]], $[[I5]], $[[R0]] -; 64-CMP-DAG: daddiu $[[I5:[0-9]+]], $zero, 5 -; 64-CMP-DAG: daddiu $[[I4:2]], $zero, 4 +; 64-CMP-DAG: daddiu $[[I4:[0-9]+]], $zero, 4 +; 64-CMP-DAG: daddiu $[[I5:2]], $zero, 5 ; 64-CMP-DAG: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, 32766 ; 64-CMP-DAG: slt $[[R0:[0-9]+]], $[[R1]], $4 ; FIXME: We can do better than this by using selccz to choose between -0 and -2 -; 64-CMP-DAG: selnez $[[T0:[0-9]+]], $[[I5]], $[[R0]] -; 64-CMP-DAG: seleqz $[[T1:[0-9]+]], $[[I4]], $[[R0]] -; 64-CMP-DAG: or $2, $[[T0]], $[[T1]] +; 64-CMP-DAG: seleqz $[[T0:[0-9]+]], $[[I4]], $[[R0]] +; 64-CMP-DAG: selnez $[[T1:[0-9]+]], $[[I5]], $[[R0]] +; 64-CMP-DAG: or $2, $[[T1]], $[[T0]] define i64 @slti64_3(i64 %a) { entry: diff --git a/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll b/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll new file mode 100644 index 000000000000..3cec194a3786 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/beqc-bnec-register-constraint.ll @@ -0,0 +1,55 @@ +; RUN: llc -march=mips -mcpu=mips32r6 -O1 -start-after=dwarfehprepare < %s | FileCheck %s + +; beqc/bnec have the constraint that $rs < $rt && $rs != 0 && $rt != 0 +; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc. +; Cases where $rs > $rt can have the operands swapped as ==,!= are commutative. + +; Cases where beq & bne where $rs == $rt have to inhibited from being turned +; into compact branches but arguably should not occur. This test covers the +; $rs == $rt case. + +; Starting from dwarf exception handling preparation skips optimizations that +; may simplify out the crucical bnec $4, $4 instruction. + +define internal void @_ZL14TestRemoveLastv(i32* %alist.sroa.0.4) { +entry: + %ascevgep = getelementptr i32, i32* %alist.sroa.0.4, i64 99 + br label %do.body121 + +for.cond117: + %alsr.iv.next = add nsw i32 %alsr.iv, -1 + %ascevgep340 = getelementptr i32, i32* %alsr.iv339, i64 -1 + %acmp118 = icmp sgt i32 %alsr.iv.next, 0 + br i1 %acmp118, label %do.body121, label %if.then143 + +do.body121: + %alsr.iv339 = phi i32* [ %ascevgep, %entry ], [ %ascevgep340, %for.cond117 ] + %alsr.iv = phi i32 [ 100, %entry ], [ %alsr.iv.next, %for.cond117 ] + %a9 = add i32 %alsr.iv, -1 + %alnot124 = icmp eq i32 %alsr.iv, %alsr.iv + br i1 %alnot124, label %do.body134, label %if.then143, !prof !11 + +do.body134: + %a10 = add i32 %alsr.iv, -1 + %a11 = load i32, i32* %alsr.iv339, align 4, !tbaa !5 +; CHECK-NOT: bnec $[[R0:[0-9]+]], $[[R0]] +; CHECK-NOT: beqc $[[R1:[0-9]+]], $[[R1]] + %alnot137 = icmp eq i32 %a9, %a11 + br i1 %alnot137, label %do.end146, label %if.then143, !prof !11 + +if.then143: + ret void + unreachable + +do.end146: + %alnot151 = icmp eq i32 %a9, %a10 + br i1 %alnot151, label %for.cond117, label %if.then143, !prof !11 + +} +!3 = !{!"omnipotent char", !4, i64 0} +!4 = !{!"Simple C++ TBAA"} +!5 = !{!6, !6, i64 0} +!6 = !{!"int", !3, i64 0} +!11 = !{!"branch_weights", i32 2000, i32 1} +!12 = !{!"branch_weights", i32 -388717296, i32 7818360} + diff --git a/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll b/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll new file mode 100644 index 000000000000..c819bf59ace6 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/compact-branch-policy.ll @@ -0,0 +1,28 @@ +; Check that -mips-compact-branches={never,optimal,always} is accepted and honoured. +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=never < %s | FileCheck %s -check-prefix=NEVER +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=optimal < %s | FileCheck %s -check-prefix=OPTIMAL +; RUN: llc -march=mips -mcpu=mips32r6 -mips-compact-branches=always < %s | FileCheck %s -check-prefix=ALWAYS + +define i32 @l(i32 signext %a, i32 signext %b) { +entry: + %add = add nsw i32 %b, %a + %cmp = icmp slt i32 %add, 100 +; NEVER: beq +; OPTIMAL: beq +; ALWAYS: beqzc +; This nop is required for correct as having (j|b)al as the instruction +; immediately following beqzc would cause a forbidden slot hazard. +; ALWAYS: nop + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = tail call i32 @k() + br label %if.end + +if.end: ; preds = %entry, %if.then + %call.pn = phi i32 [ %call, %if.then ], [ -1, %entry ] + %c.0 = add nsw i32 %call.pn, %add + ret i32 %c.0 +} + +declare i32 @k() #1 diff --git a/test/CodeGen/Mips/compactbranches/compact-branches.ll b/test/CodeGen/Mips/compactbranches/compact-branches.ll new file mode 100644 index 000000000000..75ff8a0bbcbb --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/compact-branches.ll @@ -0,0 +1,206 @@ +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=static -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=STATIC32 +; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -disable-mips-delay-filler < %s | FileCheck %s -check-prefix=PIC + +; Function Attrs: nounwind +define void @l() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %call1 = tail call i32 @j() + %cmp = icmp eq i32 %call, %call1 +; CHECK: bnec + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext -2) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +declare i32 @k() + +declare i32 @j() + +declare void @f(i32 signext) + +; Function Attrs: define void @l2() { +define void @l2() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %call1 = tail call i32 @i() + %cmp = icmp eq i32 %call, %call1 +; CHECK beqc + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext -1) + br label %if.end + +if.end: ; preds = %entry, %if.then +; CHECK: jrc $ra + ret void +} + +declare i32 @i() + +; Function Attrs: nounwind +define void @l3() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp slt i32 %call, 0 +; CHECK : bgez + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 0) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l4() { +entry: + %call = tail call i32 @k() + %cmp = icmp slt i32 %call, 1 +; CHECK: bgtzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal + tail call void @f(i32 signext 1) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l5() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %cmp = icmp sgt i32 %call, 0 +; CHECK: blezc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 2) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l6() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() +; PIC: jalrc $25 + %cmp = icmp sgt i32 %call, -1 +; CHECK: bltzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 3) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l7() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp eq i32 %call, 0 +; CHECK: bnezc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 4) + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret void +} + +; Function Attrs: nounwind +define void @l8() { +entry: +; PIC: jalrc $25 + %call = tail call i32 @k() + %cmp = icmp eq i32 %call, 0 +; CHECK: beqzc + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry: +; STATIC: nop +; STATIC: jal +; PIC: jalrc $25 + tail call void @f(i32 signext 5) + br label %if.end + +if.end: ; preds = %entry, %if.then +; CHECK: jrc $ra + ret void +} + +define i32 @l9(i8* ()* %i) #0 { +entry: + %i.addr = alloca i8* ()*, align 4 + store i8* ()* %i, i8* ()** %i.addr, align 4 +; STATIC32: jal +; STATIC32: nop +; PIC: jalrc $25 + %call = call i32 @k() +; PIC: jalrc $25 + %cmp = icmp ne i32 %call, 0 +; CHECK: beqzc + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %0 = load i8* ()*, i8* ()** %i.addr, align 4 +; CHECK: jalrc $25 + %call1 = call i8* %0() + br label %if.end + +if.end: ; preds = %if.then, %entry +; CHECK: jrc $ra + ret i32 -1 +} diff --git a/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll b/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll new file mode 100644 index 000000000000..f6fef90d01b9 --- /dev/null +++ b/test/CodeGen/Mips/compactbranches/no-beqzc-bnezc.ll @@ -0,0 +1,53 @@ +; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s +; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s \ +; RUN: -filetype=obj -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING + +; bnezc and beqzc have restriction that $rt != 0 + +define i32 @f() { +; CHECK-LABEL: f +; CHECK-NOT: bnezc $0 + + %cmp = icmp eq i32 1, 1 + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + +define i32 @f1() { +; CHECK-LABEL: f1 +; CHECK-NOT: beqzc $0 + + %cmp = icmp eq i32 0, 0 + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + +; We silently fixup cases where the register allocator or user has given us +; an instruction with incorrect operands that is trivially acceptable. +; beqc and bnec have the restriction that $rs < $rt. + +define i32 @f2(i32 %a, i32 %b) { +; ENCODING-LABEL: f2 +; ENCODING-NOT: beqc $5, $4 +; ENCODING-NOT: bnec $5, $4 + + %cmp = icmp eq i32 %b, %a + br i1 %cmp, label %if.then, label %if.end + + if.then: + ret i32 1 + + if.end: + ret i32 0 +} + diff --git a/test/CodeGen/Mips/const-mult.ll b/test/CodeGen/Mips/const-mult.ll index 60b2a88196bd..7f4e896572a6 100644 --- a/test/CodeGen/Mips/const-mult.ll +++ b/test/CodeGen/Mips/const-mult.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=CHECK -; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK64 +; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips64el < %s | FileCheck %s -check-prefixes=CHECK,CHECK64 ; CHECK-LABEL: mul5_32: ; CHECK: sll $[[R0:[0-9]+]], $4, 2 diff --git a/test/CodeGen/Mips/const4a.ll b/test/CodeGen/Mips/const4a.ll index d1182d7fc6ec..df4a1d9ff9ae 100644 --- a/test/CodeGen/Mips/const4a.ll +++ b/test/CodeGen/Mips/const4a.ll @@ -21,7 +21,7 @@ entry: ; no-load-relax: beqz ${{[0-9]+}}, $BB0_3 ; no-load-relax: lw ${{[0-9]+}}, %call16(foo)(${{[0-9]+}}) ; no-load-relax: b $BB0_4 -; no-load-relax: .align 2 +; no-load-relax: .p2align 2 ; no-load-relax: $CPI0_1: ; no-load-relax: .4byte 3735943886 ; no-load-relax: $BB0_3: diff --git a/test/CodeGen/Mips/const6.ll b/test/CodeGen/Mips/const6.ll index c576f573a43b..9085e38b3f60 100644 --- a/test/CodeGen/Mips/const6.ll +++ b/test/CodeGen/Mips/const6.ll @@ -18,7 +18,7 @@ entry: store i32 -559023410, i32* @i, align 4 ; load-relax: lw ${{[0-9]+}}, $CPI0_0 ; load-relax: jrc $ra -; load-relax: .align 2 +; load-relax: .p2align 2 ; load-relax: $CPI0_0: ; load-relax: .4byte 3735943886 ; load-relax: .end t @@ -26,7 +26,7 @@ entry: ; no-load-relax: lw ${{[0-9]+}}, $CPI0_1 # 16 bit inst ; no-load-relax: jalrc ${{[0-9]+}} ; no-load-relax: b $BB0_2 -; no-load-relax: .align 2 +; no-load-relax: .p2align 2 ; no-load-relax: $CPI0_1: ; no-load-relax: .4byte 3735943886 ; no-load-relax: $BB0_2: diff --git a/test/CodeGen/Mips/const6a.ll b/test/CodeGen/Mips/const6a.ll index 653cdeb920f3..80eedb4c897d 100644 --- a/test/CodeGen/Mips/const6a.ll +++ b/test/CodeGen/Mips/const6a.ll @@ -15,7 +15,7 @@ entry: ; load-relax-NOT: lw ${{[0-9]+}}, $CPI0_0 # 16 bit inst ; load-relax1: lw ${{[0-9]+}}, $CPI0_0 ; load-relax: jrc $ra -; load-relax: .align 2 +; load-relax: .p2align 2 ; load-relax: $CPI0_0: ; load-relax: .4byte 3735943886 ; load-relax: .end t diff --git a/test/CodeGen/Mips/countleading.ll b/test/CodeGen/Mips/countleading.ll index b7aad049e8ab..1b61be5ed2ac 100644 --- a/test/CodeGen/Mips/countleading.ll +++ b/test/CodeGen/Mips/countleading.ll @@ -1,10 +1,11 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R1-R2 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS32-R6 -check-prefix=MIPS32-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 %s -; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s -; R!N: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS64-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,MIPS32-R1-R2,MIPS32-GT-R1 %s +; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck -check-prefixes=ALL,MIPS32-R6,MIPS32-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips4 < %s | FileCheck -check-prefixes=ALL,MIPS4 %s +; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 < %s | FileCheck -check-prefixes=ALL,MIPS64-GT-R1 %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS64 %s ; Prefixes: ; ALL - All @@ -21,6 +22,8 @@ entry: ; MIPS64-GT-R1: clz $2, $4 +; MICROMIPS64: clz $2, $4 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %X, i1 true) ret i32 %tmp1 } @@ -37,6 +40,8 @@ entry: ; MIPS64-GT-R1: clo $2, $4 +; MICROMIPS64: clo $2, $4 + %neg = xor i32 %X, -1 %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %neg, i1 true) ret i32 %tmp1 @@ -58,6 +63,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclz $2, $4 +; MICROMIPS64: dclz $2, $4 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) ret i64 %tmp1 @@ -83,6 +89,7 @@ entry: ; MIPS32-GT-R1-DAG: addiu $3, $zero, 0 ; MIPS64-GT-R1: dclo $2, $4 +; MICROMIPS64: dclo $2, $4 %neg = xor i64 %X, -1 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) diff --git a/test/CodeGen/Mips/cstmaterialization/stack.ll b/test/CodeGen/Mips/cstmaterialization/stack.ll new file mode 100644 index 000000000000..7266d00069cc --- /dev/null +++ b/test/CodeGen/Mips/cstmaterialization/stack.ll @@ -0,0 +1,54 @@ +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=CHECK-MIPS32 +; RUN: llc -march=mips64el -mcpu=mips64 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-MIPS64 +; RUN: llc -march=mipsel -mcpu=mips64 -target-abi n32 < %s | \ +; RUN: FileCheck %s -check-prefix=CHECK-MIPSN32 + +; Test that the expansion of ADJCALLSTACKDOWN and ADJCALLSTACKUP generate +; (d)subu and (d)addu rather than just (d)addu. The (d)subu sequences are +; generally shorter as the constant that has to be materialized is smaller. + +define i32 @main() { +entry: + %z = alloca [1048576 x i8], align 1 + %arraydecay = getelementptr inbounds [1048576 x i8], [1048576 x i8]* %z, i32 0, i32 0 + %call = call i32 @foo(i8* %arraydecay) + ret i32 0 +; CHECK-LABEL: main + +; CHECK-MIPS32: lui $[[R0:[0-9]+]], 16 +; CHECK-MIPS32: addiu $[[R0]], $[[R0]], 24 +; CHECK-MIPS32: subu $sp, $sp, $[[R0]] + +; CHECK-MIPS32: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPS32: addiu $[[R1]], $[[R1]], 24 +; CHECK-MIPS32: addu $sp, $sp, $[[R1]] + +; CHECK-MIPS64: lui $[[R0:[0-9]+]], 1 +; CHECK-MIPS64: daddiu $[[R0]], $[[R0]], 32 +; CHECK-MIPS64: dsubu $sp, $sp, $[[R0]] + +; FIXME: +; These are here to match other lui's used in address computations. We need to +; investigate why address computations are not CSE'd. Or implement it. + +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui +; CHECK-MIPS64: lui + +; CHECK-MIPS64: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPS64: daddiu $[[R1]], $[[R1]], 32 +; CHECK-MIPS64: daddu $sp, $sp, $[[R1]] + +; CHECK-MIPSN32: lui $[[R0:[0-9]+]], 16 +; CHECK-MIPSN32: addiu $[[R0]], $[[R0]], 16 +; CHECK-MIPSN32: subu $sp, $sp, $[[R0]] + +; CHECK-MIPSN32: lui $[[R1:[0-9]+]], 16 +; CHECK-MIPSN32: addiu $[[R1]], $[[R1]], 16 +; CHECK-MIPSN32: addu $sp, $sp, $[[R1]] + +} + +declare i32 @foo(i8*) diff --git a/test/CodeGen/Mips/divrem.ll b/test/CodeGen/Mips/divrem.ll index 918db053f5b6..7703a8cecf5c 100644 --- a/test/CodeGen/Mips/divrem.ll +++ b/test/CodeGen/Mips/divrem.ll @@ -1,16 +1,16 @@ -; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=ACC32-TRAP -; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=GPR32-TRAP -; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=ACC64-TRAP -; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=GPR64-TRAP - -; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=NOCHECK -; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC32 -check-prefix=NOCHECK -; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=ACC64 -check-prefix=NOCHECK -; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=NOCHECK +; RUN: llc -march=mips -mcpu=mips32 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -march=mips -mcpu=mips32r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,ACC32-TRAP +; RUN: llc -march=mips -mcpu=mips32r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,GPR32-TRAP +; RUN: llc -march=mips64 -mcpu=mips64 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -march=mips64 -mcpu=mips64r2 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,ACC64-TRAP +; RUN: llc -march=mips64 -mcpu=mips64r6 -verify-machineinstrs -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,GPR64-TRAP + +; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC32,NOCHECK +; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR32,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,ACC64,NOCHECK +; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,GPR64,NOCHECK ; FileCheck Prefixes: ; ALL - All targets @@ -81,7 +81,7 @@ entry: ret i32 %rem } -define i32 @udiv1(i32 zeroext %a0, i32 zeroext %a1) nounwind readnone { +define i32 @udiv1(i32 signext %a0, i32 signext %a1) nounwind readnone { entry: ; ALL-LABEL: udiv1: @@ -107,7 +107,7 @@ entry: ret i32 %div } -define i32 @urem1(i32 zeroext %a0, i32 zeroext %a1) nounwind readnone { +define i32 @urem1(i32 signext %a0, i32 signext %a1) nounwind readnone { entry: ; ALL-LABEL: urem1: @@ -152,20 +152,20 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32: mod $[[R0:[0-9]+]], $4, $5 +; GPR32-DAG: div $2, $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: div $2, $4, $5 +; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 +; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64: mod $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: div $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: div $2, $4, $5 +; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sw $[[R0]], 0(${{[0-9]+}}) ; ALL: .end sdivrem1 @@ -175,7 +175,7 @@ entry: ret i32 %div } -define i32 @udivrem1(i32 zeroext %a0, i32 zeroext %a1, i32* nocapture %r) nounwind { +define i32 @udivrem1(i32 signext %a0, i32 signext %a1, i32* nocapture %r) nounwind { entry: ; ALL-LABEL: udivrem1: @@ -193,21 +193,21 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32: modu $[[R0:[0-9]+]], $4, $5 +; GPR32-DAG: divu $2, $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: divu $2, $4, $5 +; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64: modu $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: divu $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: divu $2, $4, $5 +; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sw $[[R0]], 0(${{[0-9]+}}) ; ALL: .end udivrem1 @@ -335,14 +335,14 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64: dmod $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddiv $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddiv $2, $4, $5 +; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end sdivrem2 @@ -370,14 +370,14 @@ entry: ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddivu $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddivu $2, $4, $5 +; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end udivrem2 diff --git a/test/CodeGen/Mips/dsp-r1.ll b/test/CodeGen/Mips/dsp-r1.ll index fbd970399640..edd6258270a0 100644 --- a/test/CodeGen/Mips/dsp-r1.ll +++ b/test/CodeGen/Mips/dsp-r1.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp < %s | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+dsp -verify-machineinstrs < %s | \ +; RUN: FileCheck %s define i32 @test__builtin_mips_extr_w1(i32 %i0, i32, i64 %a0) nounwind { entry: diff --git a/test/CodeGen/Mips/dynamic-stack-realignment.ll b/test/CodeGen/Mips/dynamic-stack-realignment.ll index 777930a37ad5..2ee1ca2e0dfc 100644 --- a/test/CodeGen/Mips/dynamic-stack-realignment.ll +++ b/test/CodeGen/Mips/dynamic-stack-realignment.ll @@ -1,21 +1,21 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP32 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N64 -; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 | FileCheck %s \ -; RUN: --check-prefix=ALL --check-prefix=GP64 -check-prefix=N32 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N64 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -target-abi n32 -relocation-model=pic | FileCheck %s \ +; RUN: --check-prefixes=ALL,GP64,N32 ; Check dynamic stack realignment in functions without variable-sized objects. diff --git a/test/CodeGen/Mips/eh-dwarf-cfa.ll b/test/CodeGen/Mips/eh-dwarf-cfa.ll index 6554974bf849..c4019c78d69e 100644 --- a/test/CodeGen/Mips/eh-dwarf-cfa.ll +++ b/test/CodeGen/Mips/eh-dwarf-cfa.ll @@ -13,6 +13,8 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f1: + ; CHECK: addiu $sp, $sp, -32 ; CHECK: addiu $2, $sp, 32 } @@ -24,10 +26,12 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f2: + ; check stack size (65536 + 8) -; CHECK: lui $[[R0:[a-z0-9]+]], 65535 -; CHECK: addiu $[[R0]], $[[R0]], -8 -; CHECK: addu $sp, $sp, $[[R0]] +; CHECK: lui $[[R0:[a-z0-9]+]], 1 +; CHECK: addiu $[[R0]], $[[R0]], 8 +; CHECK: subu $sp, $sp, $[[R0]] ; check return value ($sp + stack size) ; CHECK: lui $[[R1:[a-z0-9]+]], 1 @@ -46,6 +50,8 @@ entry: %add = add i32 %1, %3 ret i32 %add +; CHECK-LABEL: f3: + ; CHECK: addiu $sp, $sp, -40 ; check return value ($fp + stack size + $fp) @@ -60,6 +66,8 @@ entry: %0 = call i8* @llvm.eh.dwarf.cfa(i32 0) ret i8* %0 +; CHECK-LABEL: f4: + ; CHECK-MIPS64: daddiu $sp, $sp, -32 ; CHECK-MIPS64: daddiu $2, $sp, 32 } diff --git a/test/CodeGen/Mips/eh-return32.ll b/test/CodeGen/Mips/eh-return32.ll index 542c5bf4462e..a11a43cb406e 100644 --- a/test/CodeGen/Mips/eh-return32.ll +++ b/test/CodeGen/Mips/eh-return32.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6 +; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mipsel -mcpu=mips32r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mipsel -mcpu=mips32r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i32(i32, i8*) declare void @foo(...) diff --git a/test/CodeGen/Mips/eh-return64.ll b/test/CodeGen/Mips/eh-return64.ll index 2f8203d77c84..496e3abcf9c5 100644 --- a/test/CodeGen/Mips/eh-return64.ll +++ b/test/CodeGen/Mips/eh-return64.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6 -; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=R6 +; RUN: llc -march=mips64el -mcpu=mips4 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64r2 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,NOT-R6 +; RUN: llc -march=mips64el -mcpu=mips64r6 -asm-show-inst -relocation-model=pic < %s | FileCheck %s -check-prefixes=CHECK,R6 declare void @llvm.eh.return.i64(i64, i8*) declare void @foo(...) diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll index 19f3d4d23d64..2f843d9da9a6 100644 --- a/test/CodeGen/Mips/eh.ll +++ b/test/CodeGen/Mips/eh.ll @@ -24,7 +24,7 @@ entry: lpad: ; preds = %entry ; CHECK-EL: # %lpad -; CHECK-EL: beq $5 +; CHECK-EL: bne $5 %exn.val = landingpad { i8*, i32 } cleanup diff --git a/test/CodeGen/Mips/ehframe-indirect.ll b/test/CodeGen/Mips/ehframe-indirect.ll index a51cfb7e0fcd..d6d47678590a 100644 --- a/test/CodeGen/Mips/ehframe-indirect.ll +++ b/test/CodeGen/Mips/ehframe-indirect.ll @@ -1,9 +1,9 @@ -; RUN: llc -mtriple=mipsel-linux-gnu < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-android -target-abi=n32 < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N64 %s -; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose | FileCheck -check-prefix=ALL -check-prefix=N64 %s +; RUN: llc -mtriple=mipsel-linux-gnu < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-android -target-abi=n32 < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N64 %s +; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose -relocation-model=pic | FileCheck -check-prefixes=ALL,N64 %s @_ZTISt9exception = external constant i8* @@ -42,9 +42,9 @@ declare void @foo() ; ALL: .hidden DW.ref.__gxx_personality_v0 ; ALL: .weak DW.ref.__gxx_personality_v0 ; ALL: .section .data.DW.ref.__gxx_personality_v0,"aGw",@progbits,DW.ref.__gxx_personality_v0,comdat -; O32: .align 2 -; N32: .align 2 -; N64: .align 3 +; O32: .p2align 2 +; N32: .p2align 2 +; N64: .p2align 3 ; ALL: .type DW.ref.__gxx_personality_v0,@object ; O32: .size DW.ref.__gxx_personality_v0, 4 ; N32: .size DW.ref.__gxx_personality_v0, 4 diff --git a/test/CodeGen/Mips/elf_eflags.ll b/test/CodeGen/Mips/elf_eflags.ll index 00d8584fdad2..40910d8987d2 100644 --- a/test/CodeGen/Mips/elf_eflags.ll +++ b/test/CodeGen/Mips/elf_eflags.ll @@ -23,13 +23,13 @@ ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MICROMIPS %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+micromips %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MICROMIPS_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips4 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64R2 %s -; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64_PIC %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 -relocation-model=static %s -o - | FileCheck -check-prefix=CHECK-LE64R2 %s +; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n64 %s -o - | FileCheck -check-prefix=CHECK-LE64R2_PIC %s ; RUN: llc -mtriple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+mips16 -relocation-model=pic %s -o - | FileCheck -check-prefix=CHECK-LE32R2-MIPS16 %s diff --git a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll index 54092b4e3ebe..a08b68149a70 100644 --- a/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll +++ b/test/CodeGen/Mips/emergency-spill-slot-near-fp.ll @@ -1,5 +1,5 @@ ; Check that register scavenging spill slot is close to $fp. -; RUN: llc -march=mipsel -O0 < %s | FileCheck %s +; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s ; CHECK: sw ${{.*}}, 8($sp) ; CHECK: lw ${{.*}}, 8($sp) diff --git a/test/CodeGen/Mips/emutls_generic.ll b/test/CodeGen/Mips/emutls_generic.ll index a6cf23aa67ff..cda8dec7d12f 100644 --- a/test/CodeGen/Mips/emutls_generic.ll +++ b/test/CodeGen/Mips/emutls_generic.ll @@ -31,13 +31,13 @@ entry: ; MIPS_32-NOT: __emutls_t.external_x ; MIPS_32-NOT: __emutls_v.external_x: ; MIPS_32: .data -; MIPS_32: .align 2 +; MIPS_32: .p2align 2 ; MIPS_32-LABEL: __emutls_v.external_y: ; MIPS_32: .section .rodata, ; MIPS_32-LABEL: __emutls_t.external_y: ; MIPS_32-NEXT: .byte 7 ; MIPS_32: .data -; MIPS_32: .align 2 +; MIPS_32: .p2align 2 ; MIPS_32-LABEL: __emutls_v.internal_y: ; MIPS_32-NEXT: .4byte 8 ; MIPS_32-NEXT: .4byte 16 @@ -59,7 +59,7 @@ entry: ; MIPS_64-LABEL: __emutls_t.external_y: ; MIPS_64-NEXT: .byte 7 ; MIPS_64: .data -; MIPS_64: .align 3 +; MIPS_64: .p2align 3 ; MIPS_64-LABEL: __emutls_v.internal_y: ; MIPS_64-NEXT: .8byte 8 ; MIPS_64-NEXT: .8byte 16 diff --git a/test/CodeGen/Mips/fastcc.ll b/test/CodeGen/Mips/fastcc.ll index 299e0d696cbb..4b6191f9ae89 100644 --- a/test/CodeGen/Mips/fastcc.ll +++ b/test/CodeGen/Mips/fastcc.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s -; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu \ +; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s +; RUN: llc < %s -mtriple=mipsel-none-nacl-gnu -relocation-model=pic \ ; RUN: | FileCheck %s -check-prefix=CHECK-NACL -; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg | FileCheck %s -check-prefix=NOODDSPREG -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg | FileCheck %s -check-prefix=FP64-NOODDSPREG +; RUN: llc < %s -march=mipsel -mcpu=mips32 -mattr=+nooddspreg -relocation-model=pic | FileCheck %s -check-prefix=NOODDSPREG +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+fp64,+nooddspreg -relocation-model=pic | FileCheck %s -check-prefix=FP64-NOODDSPREG @gi0 = external global i32 diff --git a/test/CodeGen/Mips/fcmp.ll b/test/CodeGen/Mips/fcmp.ll index aa1f09bf7aba..142ee1144bbe 100644 --- a/test/CodeGen/Mips/fcmp.ll +++ b/test/CodeGen/Mips/fcmp.ll @@ -1,21 +1,35 @@ ; RUN: llc < %s -march=mips -mcpu=mips32 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: FileCheck %s -check-prefixes=ALL,32-C ; RUN: llc < %s -march=mips -mcpu=mips32r2 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-C +; RUN: FileCheck %s -check-prefixes=ALL,32-C ; RUN: llc < %s -march=mips -mcpu=mips32r6 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32-CMP +; RUN: FileCheck %s -check-prefixes=ALL,32-CMP ; RUN: llc < %s -march=mips64 -mcpu=mips4 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C +; RUN: FileCheck %s -check-prefixes=ALL,64-C ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP +; RUN: FileCheck %s -check-prefixes=ALL,64-CMP +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32R3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6,MM32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6,MM64R6 define i32 @false_f32(float %a, float %b) nounwind { ; ALL-LABEL: false_f32: -; ALL: addiu $2, $zero, 0 +; 32-C: addiu $2, $zero, 0 + +; 32-CMP: addiu $2, $zero, 0 + +; 64-C: addiu $2, $zero, 0 + +; 64-CMP: addiu $2, $zero, 0 + +; MM-DAG: lui $2, 0 %1 = fcmp false float %a, %b %2 = zext i1 %1 to i32 @@ -41,6 +55,16 @@ define i32 @oeq_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oeq float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -65,6 +89,16 @@ define i32 @ogt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ogt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -89,6 +123,16 @@ define i32 @oge_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oge float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -113,6 +157,16 @@ define i32 @olt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp olt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -137,6 +191,16 @@ define i32 @ole_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ole float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -163,6 +227,17 @@ define i32 @one_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp one float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -189,6 +264,17 @@ define i32 @ord_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp ord float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -213,6 +299,16 @@ define i32 @ueq_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ueq float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -237,6 +333,16 @@ define i32 @ugt_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ugt float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -261,6 +367,16 @@ define i32 @uge_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uge float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -285,6 +401,15 @@ define i32 @ult_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 %1 = fcmp ult float %a, %b %2 = zext i1 %1 to i32 @@ -310,6 +435,16 @@ define i32 @ule_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ule float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -336,6 +471,17 @@ define i32 @une_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.s $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp une float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -360,6 +506,16 @@ define i32 @uno_f32(float %a, float %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.s $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uno float %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -367,7 +523,15 @@ define i32 @uno_f32(float %a, float %b) nounwind { define i32 @true_f32(float %a, float %b) nounwind { ; ALL-LABEL: true_f32: -; ALL: addiu $2, $zero, 1 +; 32-C: addiu $2, $zero, 1 + +; 32-CMP: addiu $2, $zero, 1 + +; 64-C: addiu $2, $zero, 1 + +; 64-CMP: addiu $2, $zero, 1 + +; MM-DAG: li16 $2, 1 %1 = fcmp true float %a, %b %2 = zext i1 %1 to i32 @@ -376,7 +540,15 @@ define i32 @true_f32(float %a, float %b) nounwind { define i32 @false_f64(double %a, double %b) nounwind { ; ALL-LABEL: false_f64: -; ALL: addiu $2, $zero, 0 +; 32-C: addiu $2, $zero, 0 + +; 32-CMP: addiu $2, $zero, 0 + +; 64-C: addiu $2, $zero, 0 + +; 64-CMP: addiu $2, $zero, 0 + +; MM-DAG: lui $2, 0 %1 = fcmp false double %a, %b %2 = zext i1 %1 to i32 @@ -402,6 +574,16 @@ define i32 @oeq_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oeq double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -426,6 +608,16 @@ define i32 @ogt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ogt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -450,6 +642,16 @@ define i32 @oge_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp oge double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -474,6 +676,16 @@ define i32 @olt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp olt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -498,6 +710,16 @@ define i32 @ole_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ole double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -524,6 +746,17 @@ define i32 @one_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp one double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -550,6 +783,17 @@ define i32 @ord_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp ord double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -574,6 +818,16 @@ define i32 @ueq_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ueq.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ueq double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -598,6 +852,16 @@ define i32 @ugt_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ole.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ugt double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -622,6 +886,16 @@ define i32 @uge_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.olt.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 +; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uge double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -646,6 +920,16 @@ define i32 @ult_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ult.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ult double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -670,6 +954,16 @@ define i32 @ule_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.ule.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp ule double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -696,6 +990,17 @@ define i32 @une_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.eq.d $f12, $f14 +; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: not $[[T2:[0-9]+]], $[[T1]] +; MMR6-DAG: andi16 $2, $[[T2]], 1 + %1 = fcmp une double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -720,6 +1025,16 @@ define i32 @uno_f64(double %a, double %b) nounwind { ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 +; MM32R3-DAG: lui $[[T0:[0-9]+]], 0 +; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: c.un.d $f12, $f14 +; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 + +; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 +; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 +; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] +; MMR6-DAG: andi16 $2, $[[T1]], 1 + %1 = fcmp uno double %a, %b %2 = zext i1 %1 to i32 ret i32 %2 @@ -727,7 +1042,15 @@ define i32 @uno_f64(double %a, double %b) nounwind { define i32 @true_f64(double %a, double %b) nounwind { ; ALL-LABEL: true_f64: -; ALL: addiu $2, $zero, 1 +; 32-C: addiu $2, $zero, 1 + +; 32-CMP: addiu $2, $zero, 1 + +; 64-C: addiu $2, $zero, 1 + +; 64-CMP: addiu $2, $zero, 1 + +; MM-DAG: li16 $2, 1 %1 = fcmp true double %a, %b %2 = zext i1 %1 to i32 @@ -750,7 +1073,7 @@ entry: ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 32-CMP-DAG: bnez $[[T4]], +; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.s $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: lwc1 $[[T1:f[0-9]+]], %got_ofst($CPI32_0)( @@ -763,7 +1086,32 @@ entry: ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 64-CMP-DAG: bnez $[[T4]], +; 64-CMP-DAG: bnezc $[[T4]], + +; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 +; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) +; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) +; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]] +; MM32R3-DAG: bc1t + +; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12 +; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0) +; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]]) +; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]] +; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]] +; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 +; MM32R6-DAG: bnez $[[T5]], + +; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32))) +; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32))) +; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]]) +; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]]) +; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]] +; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] +; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 +; MM64R6-DAG: bnez $[[T8]], %add = fadd fast float %at, %angle %cmp = fcmp ogt float %add, 1.000000e+00 @@ -794,7 +1142,7 @@ entry: ; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 32-CMP-DAG: bnez $[[T4]], +; 32-CMP-DAG: bnezc $[[T4]], ; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12 ; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %got_ofst($CPI33_0)( @@ -807,7 +1155,32 @@ entry: ; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]] ; FIXME: This instruction is redundant. ; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1 -; 64-CMP-DAG: bnez $[[T4]], +; 64-CMP-DAG: bnezc $[[T4]], + +; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 +; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) +; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) +; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]] +; MM32R3-DAG: bc1t + +; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12 +; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0) +; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]]) +; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]] +; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]] +; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1 +; MM32R6-DAG: bnez $[[T5]], + +; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64))) +; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25 +; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64))) +; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12 +; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]]) +; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]]) +; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]] +; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]] +; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1 +; MM64R6-DAG: bnez $[[T8]], %add = fadd fast double %at, %angle %cmp = fcmp ogt double %add, 1.000000e+00 diff --git a/test/CodeGen/Mips/fcopysign-f32-f64.ll b/test/CodeGen/Mips/fcopysign-f32-f64.ll index 860bc79956fc..b1f065af0745 100644 --- a/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ b/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -1,6 +1,9 @@ -; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \ +; RUN: FileCheck %s -check-prefixes=ALL,64R2 declare double @copysign(double, double) nounwind readnone @@ -8,7 +11,8 @@ declare float @copysignf(float, float) nounwind readnone define float @func2(float %d, double %f) nounwind readnone { entry: -; 64: func2 +; ALL-LABEL: func2: + ; 64-DAG: lui $[[T0:[0-9]+]], 32767 ; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 ; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] @@ -18,7 +22,7 @@ entry: ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]] ; 64: mtc1 $[[OR]], $f0 -; 64R2: dext ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 +; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1 ; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1 ; 64R2: mtc1 $[[INS]], $f0 @@ -30,17 +34,18 @@ entry: define double @func3(double %d, float %f) nounwind readnone { entry: - -; 64: func3 -; 64-DAG: daddiu $[[T0:[0-9]+]], $zero, 1 -; 64-DAG: dsll $[[T1:[0-9]+]], $[[T0]], 63 -; 64-DAG: daddiu $[[MSK0:[0-9]+]], $[[T1]], -1 -; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]] -; 64-DAG: srl $[[SRL:[0-9]+]], ${{[0-9]+}}, 31 -; 64-DAG: sll $[[SLL:[0-9]+]], $[[SRL]], 0 -; 64-DAG: dsll $[[DSLL:[0-9]+]], $[[SLL]], 63 -; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] -; 64: dmtc1 $[[OR]], $f0 +; ALL-LABEL: func3: + +; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13 +; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 +; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 +; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 +; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 +; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]] +; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] +; 64: dmtc1 $[[OR]], $f0 ; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1 ; 64R2: dins $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1 @@ -51,4 +56,3 @@ entry: %call = tail call double @copysign(double %add, double %conv) nounwind readnone ret double %call } - diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 6928f2fe507f..ffc72a12f23d 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -27,7 +27,7 @@ entry: ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] ; 64: dmtc1 $[[OR]], $f0 -; 64R2: dext $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 +; 64R2: dextu $[[EXT:[0-9]+]], ${{[0-9]+}}, 63, 1 ; 64R2: dins $[[INS:[0-9]+]], $[[EXT]], 63, 1 ; 64R2: dmtc1 $[[INS]], $f0 diff --git a/test/CodeGen/Mips/fmadd1.ll b/test/CodeGen/Mips/fmadd1.ll index 99d99fada1cf..c155eedd62c4 100644 --- a/test/CodeGen/Mips/fmadd1.ll +++ b/test/CodeGen/Mips/fmadd1.ll @@ -5,18 +5,18 @@ ; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only ; available when -enable-no-nans-fp-math is given. -; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NONAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NONAN -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -check-prefix=32-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -check-prefix=32R2-NAN -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -check-prefix=32R6-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -check-prefix=64-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -check-prefix=64R2-NAN -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 -check-prefix=64R6-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32,32-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6,32R6-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6,64R6-NONAN +; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32,32-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6,32R6-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6,64R6-NAN define float @FOO0float(float %a, float %b, float %c) nounwind readnone { entry: diff --git a/test/CodeGen/Mips/fp-indexed-ls.ll b/test/CodeGen/Mips/fp-indexed-ls.ll index 219ca99d3f94..87fb248e56fd 100644 --- a/test/CodeGen/Mips/fp-indexed-ls.ll +++ b/test/CodeGen/Mips/fp-indexed-ls.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R1 -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R2 -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS32R6 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS4 -; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64R6 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R2 +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS32R6 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS4 +; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MIPS64R6 ; Check that [ls][dwu]xc1 are not emitted for nacl. ; RUN: llc -mtriple=mipsel-none-nacl-gnu -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=CHECK-NACL diff --git a/test/CodeGen/Mips/fp-spill-reload.ll b/test/CodeGen/Mips/fp-spill-reload.ll index 4a53ad8c8e13..431389ae9acb 100644 --- a/test/CodeGen/Mips/fp-spill-reload.ll +++ b/test/CodeGen/Mips/fp-spill-reload.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; check that $fp is not reserved. define void @foo0(i32* nocapture %b) nounwind { diff --git a/test/CodeGen/Mips/fp16-promote.ll b/test/CodeGen/Mips/fp16-promote.ll index 2ac46e028072..f060f6ab03ee 100644 --- a/test/CodeGen/Mips/fp16-promote.ll +++ b/test/CodeGen/Mips/fp16-promote.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -mtriple=mipsel-linux-gnueabi < %s | FileCheck %s -check-prefix=CHECK-LIBCALL +; RUN: llc -asm-verbose=false -mtriple=mipsel-linux-gnueabi -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-LIBCALL ; CHECK-LIBCALL-LABEL: test_fadd: ; CHECK-LIBCALL: %call16(__gnu_h2f_ieee) diff --git a/test/CodeGen/Mips/fp64a.ll b/test/CodeGen/Mips/fp64a.ll index fadce5cb748b..528a0c816842 100644 --- a/test/CodeGen/Mips/fp64a.ll +++ b/test/CodeGen/Mips/fp64a.ll @@ -11,14 +11,14 @@ ; incorrectly using this case. We should fix those test cases then add ; this check here. -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-BE -; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NO-FP64A-LE -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FP64A +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-BE +; RUN: llc -march=mips -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,32R2-NO-FP64A-LE +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fp64,nooddspreg < %s | FileCheck %s -check-prefixes=ALL,32R2-FP64A -; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A +; RUN: llc -march=mips64 -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A -; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NO-FP64A +; RUN: llc -march=mips64el -mcpu=mips64 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,64-NO-FP64A ; RUN: not llc -march=mips64el -mcpu=mips64 -mattr=fp64,nooddspreg < %s 2>&1 | FileCheck %s -check-prefix=64-FP64A ; 64-FP64A: LLVM ERROR: -mattr=+nooddspreg requires the O32 ABI. diff --git a/test/CodeGen/Mips/fpbr.ll b/test/CodeGen/Mips/fpbr.ll index 27d7094376e6..bf1b045dbf28 100644 --- a/test/CodeGen/Mips/fpbr.ll +++ b/test/CodeGen/Mips/fpbr.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=32-FCC -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=32-GPR -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=FCC -check-prefix=64-FCC -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=GPR -check-prefix=64-GPR +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR +; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR define void @func0(float %f2, float %f3) nounwind { entry: @@ -18,7 +18,8 @@ entry: ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB0_2 +; 32-GPR: bnez $[[GPRCC]], $BB0_2 +; 64-GPR: bnezc $[[GPRCC]], $BB0_2 %cmp = fcmp oeq float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -51,7 +52,8 @@ entry: ; 64-GPR: cmp.ule.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB1_2 +; 32-GPR: bnez $[[GPRCC]], $BB1_2 +; 64-GPR: bnezc $[[GPRCC]], $BB1_2 %cmp = fcmp olt float %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -80,7 +82,8 @@ entry: ; 64-GPR: cmp.ult.s $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB2_2 +; 32-GPR: beqz $[[GPRCC]], $BB2_2 +; 64-GPR: beqzc $[[GPRCC]], $BB2_2 %cmp = fcmp ugt float %f2, %f3 br i1 %cmp, label %if.else, label %if.then @@ -110,7 +113,8 @@ entry: ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; FIXME: We ought to be able to transform not+bnez -> beqz ; GPR: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB3_2 +; 32-GPR: bnez $[[GPRCC]], $BB3_2 +; 64-GPR: bnezc $[[GPRCC]], $BB3_2 %cmp = fcmp oeq double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -139,7 +143,8 @@ entry: ; 64-GPR: cmp.ule.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: bnez $[[GPRCC]], $BB4_2 +; 32-GPR: bnez $[[GPRCC]], $BB4_2 +; 64-GPR: bnezc $[[GPRCC]], $BB4_2 %cmp = fcmp olt double %f2, %f3 br i1 %cmp, label %if.then, label %if.else @@ -168,7 +173,8 @@ entry: ; 64-GPR: cmp.ult.d $[[FGRCC:f[0-9]+]], $f13, $f12 ; GPR: mfc1 $[[GPRCC:[0-9]+]], $[[FGRCC:f[0-9]+]] ; GPR-NOT: not $[[GPRCC]], $[[GPRCC]] -; GPR: beqz $[[GPRCC]], $BB5_2 +; 32-GPR: beqz $[[GPRCC]], $BB5_2 +; 64-GPR: beqzc $[[GPRCC]], $BB5_2 %cmp = fcmp ugt double %f2, %f3 br i1 %cmp, label %if.else, label %if.then diff --git a/test/CodeGen/Mips/fpxx.ll b/test/CodeGen/Mips/fpxx.ll index 5b42ecec53e8..6fdb95efe8ec 100644 --- a/test/CodeGen/Mips/fpxx.ll +++ b/test/CodeGen/Mips/fpxx.ll @@ -1,20 +1,20 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32-FPXX +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32-NOFPXX +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32-FPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-NOFPXX -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=32R2-FPXX +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32R2-NOFPXX +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,32R2-FPXX -; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-NOFPXX +; RUN: llc -march=mips64 -mcpu=mips4 < %s | FileCheck %s -check-prefixes=ALL,4-NOFPXX ; RUN: not llc -march=mips64 -mcpu=mips4 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=4-FPXX -; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-NOFPXX +; RUN: llc -march=mips64 -mcpu=mips64 < %s | FileCheck %s -check-prefixes=ALL,64-NOFPXX ; RUN: not llc -march=mips64 -mcpu=mips64 -mattr=fpxx < %s 2>&1 | FileCheck %s -check-prefix=64-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=4-O32-FPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,4-O32-NOFPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips4 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,4-O32-FPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-NOFPXX -; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefix=ALL -check-prefix=64-O32-FPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 < %s | FileCheck %s -check-prefixes=ALL,64-O32-NOFPXX +; RUN-TODO: llc -march=mips64 -mcpu=mips64 -target-abi o32 -mattr=fpxx < %s | FileCheck %s -check-prefixes=ALL,64-O32-FPXX declare double @dbl(); diff --git a/test/CodeGen/Mips/gpreg-lazy-binding.ll b/test/CodeGen/Mips/gpreg-lazy-binding.ll index 800a74f5358f..98849ded7070 100644 --- a/test/CodeGen/Mips/gpreg-lazy-binding.ll +++ b/test/CodeGen/Mips/gpreg-lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | FileCheck %s +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | FileCheck %s @g = external global i32 diff --git a/test/CodeGen/Mips/hf16call32.ll b/test/CodeGen/Mips/hf16call32.ll index 9fc94cac5175..5159477f2c69 100644 --- a/test/CodeGen/Mips/hf16call32.ll +++ b/test/CodeGen/Mips/hf16call32.ll @@ -820,7 +820,7 @@ declare void @v_df_df(double, double) #1 declare float @sf_v() #1 ; stel: .section .mips16.call.fp.sf_v,"ax",@progbits ; stel: .ent __call_stub_fp_sf_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal sf_v ; stel: mfc1 $2, $f0 ; stel: jr $18 @@ -898,7 +898,7 @@ declare float @sf_df_df(double, double) #1 declare double @df_v() #1 ; stel: .section .mips16.call.fp.df_v,"ax",@progbits ; stel: .ent __call_stub_fp_df_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal df_v ; stel: mfc1 $2, $f0 ; stel: mfc1 $3, $f1 @@ -983,7 +983,7 @@ declare double @df_df_df(double, double) #1 declare { float, float } @sc_v() #1 ; stel: .section .mips16.call.fp.sc_v,"ax",@progbits ; stel: .ent __call_stub_fp_sc_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal sc_v ; stel: mfc1 $2, $f0 ; stel: mfc1 $3, $f2 @@ -1004,7 +1004,7 @@ declare { float, float } @sc_sf(float) #1 declare { double, double } @dc_v() #1 ; stel: .section .mips16.call.fp.dc_v,"ax",@progbits ; stel: .ent __call_stub_fp_dc_v -; stel: move $18, $31 +; stel: move $18, $ra ; stel: jal dc_v ; stel: mfc1 $4, $f2 ; stel: mfc1 $5, $f3 diff --git a/test/CodeGen/Mips/hf16call32_body.ll b/test/CodeGen/Mips/hf16call32_body.ll index 1a04fd46f8bd..49ce181b015a 100644 --- a/test/CodeGen/Mips/hf16call32_body.ll +++ b/test/CodeGen/Mips/hf16call32_body.ll @@ -20,7 +20,8 @@ entry: } ; stel: .section .mips16.fn.v_sf,"ax",@progbits ; stel: .ent __fn_stub_v_sf -; stel: la $25, v_sf +; stel: lui $25, %hi(v_sf) +; stel: addiu $25, $25, %lo(v_sf) ; stel: mfc1 $4, $f12 ; stel: jr $25 ; stel: __fn_local_v_sf = v_sf @@ -40,7 +41,8 @@ entry: ; stel: .section .mips16.fn.v_df,"ax",@progbits ; stel: .ent __fn_stub_v_df -; stel: la $25, v_df +; stel: lui $25, %hi(v_df) +; stel: addiu $25, $25, %lo(v_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: jr $25 @@ -63,7 +65,8 @@ entry: ; stel: .section .mips16.fn.v_sf_sf,"ax",@progbits ; stel: .ent __fn_stub_v_sf_sf -; stel: la $25, v_sf_sf +; stel: lui $25, %hi(v_sf_sf) +; stel: addiu $25, $25, %lo(v_sf_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f14 ; stel: jr $25 @@ -86,7 +89,8 @@ entry: ; stel: .section .mips16.fn.v_sf_df,"ax",@progbits ; stel: .ent __fn_stub_v_sf_df -; stel: la $25, v_sf_df +; stel: lui $25, %hi(v_sf_df) +; stel: addiu $25, $25, %lo(v_sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $6, $f14 ; stel: mfc1 $7, $f15 @@ -110,7 +114,8 @@ entry: ; stel: .section .mips16.fn.v_df_sf,"ax",@progbits ; stel: .ent __fn_stub_v_df_sf -; stel: la $25, v_df_sf +; stel: lui $25, %hi(v_df_sf) +; stel: addiu $25, $25, %lo(v_df_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -134,7 +139,8 @@ entry: ; stel: .section .mips16.fn.v_df_df,"ax",@progbits ; stel: .ent __fn_stub_v_df_df -; stel: la $25, v_df_df +; stel: lui $25, %hi(v_df_df) +; stel: addiu $25, $25, %lo(v_df_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -164,7 +170,8 @@ entry: ; stel: .section .mips16.fn.sf_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_sf -; stel: la $25, sf_sf +; stel: lui $25, %hi(sf_sf) +; stel: addiu $25, $25, %lo(sf_sf) ; stel: mfc1 $4, $f12 ; stel: jr $25 ; stel: __fn_local_sf_sf = sf_sf @@ -184,7 +191,8 @@ entry: ; stel: .section .mips16.fn.sf_df,"ax",@progbits ; stel: .ent __fn_stub_sf_df -; stel: la $25, sf_df +; stel: lui $25, %hi(sf_df) +; stel: addiu $25, $25, %lo(sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: jr $25 @@ -208,7 +216,8 @@ entry: ; stel: .section .mips16.fn.sf_sf_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_sf_sf -; stel: la $25, sf_sf_sf +; stel: lui $25, %hi(sf_sf_sf) +; stel: addiu $25, $25, %lo(sf_sf_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f14 ; stel: jr $25 @@ -232,7 +241,8 @@ entry: ; stel: .section .mips16.fn.sf_sf_df,"ax",@progbits ; stel: .ent __fn_stub_sf_sf_df -; stel: la $25, sf_sf_df +; stel: lui $25, %hi(sf_sf_df) +; stel: addiu $25, $25, %lo(sf_sf_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $6, $f14 ; stel: mfc1 $7, $f15 @@ -257,7 +267,8 @@ entry: ; stel: .section .mips16.fn.sf_df_sf,"ax",@progbits ; stel: .ent __fn_stub_sf_df_sf -; stel: la $25, sf_df_sf +; stel: lui $25, %hi(sf_df_sf) +; stel: addiu $25, $25, %lo(sf_df_sf) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 @@ -282,7 +293,8 @@ entry: ; stel: .section .mips16.fn.sf_df_df,"ax",@progbits ; stel: .ent __fn_stub_sf_df_df -; stel: la $25, sf_df_df +; stel: lui $25, %hi(sf_df_df) +; stel: addiu $25, $25, %lo(sf_df_df) ; stel: mfc1 $4, $f12 ; stel: mfc1 $5, $f13 ; stel: mfc1 $6, $f14 diff --git a/test/CodeGen/Mips/hf1_body.ll b/test/CodeGen/Mips/hf1_body.ll index adf45109d69a..b6469716176f 100644 --- a/test/CodeGen/Mips/hf1_body.ll +++ b/test/CodeGen/Mips/hf1_body.ll @@ -1,4 +1,11 @@ -; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=picfp16 +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -relocation-model=pic -no-integrated-as < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,GAS + +; The integrated assembler expands assembly macros before printing. +; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mattr=mips16 \ +; RUN: -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,IAS @x = external global float @@ -11,11 +18,13 @@ entry: store float %0, float* @x, align 4 ret void } -; picfp16: .ent __fn_stub_v_sf -; picfp16: .cpload $25 -; picfp16: .set reorder -; picfp16: .reloc 0, R_MIPS_NONE, v_sf -; picfp16: la $25, $__fn_local_v_sf -; picfp16: mfc1 $4, $f12 -; picfp16: jr $25 -; picfp16: .end __fn_stub_v_sf +; ALL-LABEL: .ent __fn_stub_v_sf +; ALL: .cpload $25 +; ALL: .set reorder +; ALL: .reloc 0, R_MIPS_NONE, v_sf +; GAS: la $25, $__fn_local_v_sf +; IAS: lw $25, %got($$__fn_local_v_sf)($gp) +; IAS: addiu $25, $25, %lo($$__fn_local_v_sf) +; ALL: mfc1 $4, $f12 +; ALL: jr $25 +; ALL: .end __fn_stub_v_sf diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 5b2d13518035..22a0c1f51f7d 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: diff --git a/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll new file mode 100644 index 000000000000..a99cb976eaa9 --- /dev/null +++ b/test/CodeGen/Mips/inlineasm-constraint_ZC_2.ll @@ -0,0 +1,36 @@ +; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -march=mips -mcpu=mips64r6 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,R6 +; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s --check-prefixes=ALL,PRER6 +; RUN: llc -march=mips -mcpu=mips64 -target-abi=n64 < %s | FileCheck %s --check-prefixes=ALL,PRER6 + + +%struct.anon = type { [63 x i32], i32, i32 } + +define i32 @Atomic() { +; CHECK-LABEL: Atomic: +entry: + %s = alloca %struct.anon, align 4 + %0 = bitcast %struct.anon* %s to i8* + %count = getelementptr inbounds %struct.anon, %struct.anon* %s, i64 0, i32 1 + store i32 0, i32* %count, align 4 +; R6: addiu $[[R0:[0-9a-z]+]], $sp, {{[0-9]+}} + +; ALL: #APP + +; R6: ll ${{[0-9a-z]+}}, 0($[[R0]]) +; R6: sc ${{[0-9a-z]+}}, 0($[[R0]]) + +; PRER6: ll ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}}) +; PRER6: sc ${{[0-9a-z]+}}, {{[0-9]+}}(${{[0-9a-z]+}}) + +; ALL: #NO_APP + + %1 = call { i32, i32 } asm sideeffect ".set push\0A.set noreorder\0A1:\0All $0, $2\0Aaddu $1, $0, $3\0Asc $1, $2\0Abeqz $1, 1b\0Aaddu $1, $0, $3\0A.set pop\0A", "=&r,=&r,=*^ZC,Ir,*^ZC,~{memory},~{$1}"(i32* %count, i32 10, i32* %count) + %asmresult1.i = extractvalue { i32, i32 } %1, 1 + %cmp = icmp ne i32 %asmresult1.i, 10 + %conv = zext i1 %cmp to i32 + %call2 = call i32 @f(i32 signext %conv) + ret i32 %call2 +} + +declare i32 @f(i32 signext) diff --git a/test/CodeGen/Mips/inlineasm-operand-code.ll b/test/CodeGen/Mips/inlineasm-operand-code.ll index 6d41385d18de..6b46884e9af7 100644 --- a/test/CodeGen/Mips/inlineasm-operand-code.ll +++ b/test/CodeGen/Mips/inlineasm-operand-code.ll @@ -1,9 +1,15 @@ ; Positive test for inline register constraints ; -; RUN: llc -no-integrated-as -march=mipsel < %s | \ -; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s -; RUN: llc -no-integrated-as -march=mips < %s | \ -; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s +; RUN: llc -no-integrated-as -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,LE32,GAS %s +; RUN: llc -no-integrated-as -march=mips -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,BE32,GAS %s + +; IAS might not print in the same way since it parses the assembly. +; RUN: llc -march=mipsel -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,LE32,IAS %s +; RUN: llc -march=mips -relocation-model=pic < %s | \ +; RUN: FileCheck -check-prefixes=ALL,BE32,IAS %s %union.u_tag = type { i64 } %struct.anon = type { i32, i32 } @@ -15,6 +21,7 @@ entry: ; ALL-LABEL: constraint_X: ; ALL: #APP ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 @@ -26,6 +33,9 @@ entry: ; ALL-LABEL: constraint_x: ; ALL: #APP ; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd +; This is _also_ -3 because uimm16 values are silently coerced to simm16 when +; it would otherwise fail to match. +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ; ret i32 0 @@ -54,39 +64,66 @@ entry: } ; z with -3 -define i32 @constraint_z() nounwind { +define void @constraint_z_0() nounwind { entry: -; ALL-LABEL: constraint_z: +; ALL-LABEL: constraint_z_0: ; ALL: #APP ; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3 ; ALL: #NO_APP tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ; + ret void +} ; z with 0 +define void @constraint_z_1() nounwind { +entry: +; ALL-LABEL: constraint_z_1: ; ALL: #APP -; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0 +; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, $0 +; IAS: move ${{[0-9]+}}, ${{[0-9]+}} ; ALL: #NO_APP - tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + tail call i32 asm sideeffect "addu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind + ret void +} ; z with non-zero and the "r"(register) and "J"(integer zero) constraints +define void @constraint_z_2() nounwind { +entry: +; ALL-LABEL: constraint_z_2: ; ALL: #APP ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind + ret void +} ; z with zero and the "r"(register) and "J"(integer zero) constraints +define void @constraint_z_3() nounwind { +entry: +; ALL-LABEL: constraint_z_3: ; ALL: #APP -; ALL: mtc0 $0, ${{[0-9]+}} +; GAS: mtc0 $0, ${{[0-9]+}} +; IAS: mtc0 $zero, ${{[0-9]+}}, 0 ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind + ret void +} ; z with non-zero and just the "r"(register) constraint +define void @constraint_z_4() nounwind { +entry: +; ALL-LABEL: constraint_z_4: ; ALL: #APP ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind + ret void +} ; z with zero and just the "r"(register) constraint +define void @constraint_z_5() nounwind { +entry: +; ALL-LABEL: constraint_z_5: ; FIXME: Check for $0, instead of other registers. ; We should be using $0 directly in this case, not real registers. ; When the materialization of 0 gets fixed, this test will fail. @@ -94,7 +131,7 @@ entry: ; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}} ; ALL: #NO_APP call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind - ret i32 0 + ret void } ; A long long in 32 bit mode (use to assert) diff --git a/test/CodeGen/Mips/inlineasm_constraint.ll b/test/CodeGen/Mips/inlineasm_constraint.ll index a6ac07182ff5..164d28f733e4 100644 --- a/test/CodeGen/Mips/inlineasm_constraint.ll +++ b/test/CodeGen/Mips/inlineasm_constraint.ll @@ -1,5 +1,6 @@ ; RUN: llc -no-integrated-as -march=mipsel < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=GAS +; RUN: FileCheck %s -check-prefixes=ALL,GAS +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefixes=ALL,IAS define void @constraint_I() nounwind { ; First I with short @@ -31,6 +32,7 @@ define void @constraint_K() nounwind { ; Now K with 64 ; ALL: #APP ; GAS: addu ${{[0-9]+}}, ${{[0-9]+}}, 64 +; IAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 64 ; ALL: #NO_APP tail call i16 asm sideeffect "addu $0, $1, $2\0A\09 ", "=r,r,K"(i16 7, i16 64) nounwind ret void diff --git a/test/CodeGen/Mips/inlineasm_constraint_R.ll b/test/CodeGen/Mips/inlineasm_constraint_R.ll index c4105ae6b22c..9c7611ba81d5 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_R.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_R.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasm_constraint_ZC.ll b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll index c1746a67564f..59778df3b423 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_ZC.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_ZC.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=ALL -check-prefix=09BIT -; RUN: llc -march=mipsel -mattr=+micromips < %s | FileCheck %s -check-prefix=ALL -check-prefix=12BIT -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=ALL -check-prefix=16BIT +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,09BIT +; RUN: llc -march=mipsel -mattr=+micromips -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,12BIT +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,16BIT @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasm_constraint_m.ll b/test/CodeGen/Mips/inlineasm_constraint_m.ll index 00053ad3c105..11ef8341cbdb 100644 --- a/test/CodeGen/Mips/inlineasm_constraint_m.ll +++ b/test/CodeGen/Mips/inlineasm_constraint_m.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @data = global [8193 x i32] zeroinitializer diff --git a/test/CodeGen/Mips/inlineasmmemop.ll b/test/CodeGen/Mips/inlineasmmemop.ll index bdf3ae55b802..61cbf93e667b 100644 --- a/test/CodeGen/Mips/inlineasmmemop.ll +++ b/test/CodeGen/Mips/inlineasmmemop.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; Simple memory @g1 = external global i32 diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index 2b4a0397f45f..b6b1c96c5f3b 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -march=mipsel -relocation-model=pic | FileCheck %s @caller.sf1 = internal unnamed_addr global void (...)* null, align 4 @gf1 = external global void (...)* diff --git a/test/CodeGen/Mips/interrupt-attr-64-error.ll b/test/CodeGen/Mips/interrupt-attr-64-error.ll index 830c199d91d9..9626bda45f51 100644 --- a/test/CodeGen/Mips/interrupt-attr-64-error.ll +++ b/test/CodeGen/Mips/interrupt-attr-64-error.ll @@ -1,4 +1,4 @@ -; RUN: not llc -mcpu=mips64r6 -march=mipsel -relocation-model=static < %s 2>%t +; RUN: not llc -mcpu=mips64r6 -march=mipsel -target-abi n64 -relocation-model=static < %s 2>%t ; RUN: FileCheck %s < %t ; CHECK: LLVM ERROR: "interrupt" attribute is only supported for the O32 ABI on MIPS32R2+ at the present time. diff --git a/test/CodeGen/Mips/largeimm1.ll b/test/CodeGen/Mips/largeimm1.ll index 06c4d6bd9603..b4d15f9e1e8c 100644 --- a/test/CodeGen/Mips/largeimm1.ll +++ b/test/CodeGen/Mips/largeimm1.ll @@ -1,13 +1,19 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -; CHECK: lui ${{[0-9]+}}, 49152 -; CHECK: lui ${{[0-9]+}}, 16384 define void @f() nounwind { entry: %a1 = alloca [1073741824 x i8], align 1 %arrayidx = getelementptr inbounds [1073741824 x i8], [1073741824 x i8]* %a1, i32 0, i32 1048676 call void @f2(i8* %arrayidx) nounwind ret void +; CHECK-LABEL: f: + +; CHECK: lui $[[R0:[a-z0-9]+]], 16384 +; CHECK: addiu $[[R1:[a-z0-9]+]], $[[R0]], 24 +; CHECK: subu $sp, $sp, $[[R1]] + +; CHECK: lui $[[R2:[a-z0-9]+]], 16384 +; CHECK: addu ${{[0-9]+}}, $sp, $[[R2]] } declare void @f2(i8*) diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll index a53a953a7883..f27e11425b97 100644 --- a/test/CodeGen/Mips/largeimmprinting.ll +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32 -; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 < %s | \ +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=32 +; RUN: llc -march=mips64el -mcpu=mips4 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 -; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 < %s | \ +; RUN: llc -march=mips64el -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | \ ; RUN: FileCheck %s -check-prefix=64 %struct.S1 = type { [65536 x i8] } @@ -10,21 +10,19 @@ define void @f() nounwind { entry: -; 32: lui $[[R0:[0-9]+]], 65535 -; 32: addiu $[[R0]], $[[R0]], -24 -; 32: addu $sp, $sp, $[[R0]] -; 32: lui $[[R1:[0-9]+]], 1 -; 32: addu $[[R1]], $sp, $[[R1]] -; 32: sw $ra, 20($[[R1]]) -; 64: daddiu $[[R0:[0-9]+]], $zero, 1 -; 64: dsll $[[R0]], $[[R0]], 48 -; 64: daddiu $[[R0]], $[[R0]], -1 -; 64: dsll $[[R0]], $[[R0]], 16 -; 64: daddiu $[[R0]], $[[R0]], -32 -; 64: daddu $sp, $sp, $[[R0]] -; 64: lui $[[R1:[0-9]+]], 1 -; 64: daddu $[[R1]], $sp, $[[R1]] -; 64: sd $ra, 24($[[R1]]) +; 32: lui $[[R0:[0-9]+]], 1 +; 32: addiu $[[R0]], $[[R0]], 24 +; 32: subu $sp, $sp, $[[R0]] +; 32: lui $[[R1:[0-9]+]], 1 +; 32: addu $[[R1]], $sp, $[[R1]] +; 32: sw $ra, 20($[[R1]]) + +; 64: lui $[[R0:[0-9]+]], 1 +; 64: daddiu $[[R0]], $[[R0]], 32 +; 64: dsubu $sp, $sp, $[[R0]] +; 64: lui $[[R1:[0-9]+]], 1 +; 64: daddu $[[R1]], $sp, $[[R1]] +; 64: sd $ra, 24($[[R1]]) %agg.tmp = alloca %struct.S1, align 1 %tmp = getelementptr inbounds %struct.S1, %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 diff --git a/test/CodeGen/Mips/lazy-binding.ll b/test/CodeGen/Mips/lazy-binding.ll index 839155adad9a..87040cc2b3ac 100644 --- a/test/CodeGen/Mips/lazy-binding.ll +++ b/test/CodeGen/Mips/lazy-binding.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; CHECK-LABEL: foo6: ; CHECK: %while.body diff --git a/test/CodeGen/Mips/lcb5.ll b/test/CodeGen/Mips/lcb5.ll index ec4c3da6515c..83f5fa0fb1c2 100644 --- a/test/CodeGen/Mips/lcb5.ll +++ b/test/CodeGen/Mips/lcb5.ll @@ -212,7 +212,7 @@ if.end: ; preds = %if.then, %entry ; ci: btnez $BB7_1 # 16 bit inst ; ci: jal $BB7_2 # branch ; ci: nop -; ci: .align 2 +; ci: .p2align 2 ; ci: $BB7_1: ; ci: .end z4 diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll index 6cccc7df19f9..7a60585d8fbf 100644 --- a/test/CodeGen/Mips/llvm-ir/add.ll +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -1,37 +1,51 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: -check-prefixes=ALL,R2-R6,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,NOT-R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: -check-prefixes=ALL,R2-R6,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips -O2 | FileCheck %s \ +; RUN: -check-prefixes=ALL,MMR6,MM64 define signext i1 @add_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: add_i1: - ; ALL: addu $[[T0:[0-9]+]], $4, $5 - ; ALL: sll $[[T0]], $[[T0]], 31 - ; ALL: sra $2, $[[T0]], 31 + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 31 + ; NOT-R2-R6: sra $2, $[[T0]], 31 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: sll $[[T0]], $[[T0]], 31 + ; R2-R6: sra $2, $[[T0]], 31 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; MMR6: sra $2, $[[T1]], 31 %r = add i1 %a, %b ret i1 %r @@ -45,8 +59,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 ; NOT-R2-R6: sra $2, $[[T0]], 24 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seb $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seb $2, $[[T0]] %r = add i8 %a, %b ret i8 %r @@ -60,8 +77,11 @@ entry: ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 ; NOT-R2-R6: sra $2, $[[T0]], 16 - ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 - ; R2-R6: seh $2, $[[T0:[0-9]+]] + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 + ; MMR6: seh $2, $[[T0]] %r = add i16 %a, %b ret i16 %r @@ -71,7 +91,10 @@ define signext i32 @add_i32(i32 signext %a, i32 signext %b) { entry: ; ALL-LABEL: add_i32: - ; ALL: addu $2, $4, $5 + ; NOT-R2-R6: addu $2, $4, $5 + ; R2-R6: addu $2, $4, $5 + + ; MMR6: addu16 $[[T0:[0-9]+]], $4, $5 %r = add i32 %a, %b ret i32 %r @@ -88,6 +111,13 @@ entry: ; GP64: daddu $2, $4, $5 + ; MM32: addu $3, $5, $7 + ; MM32: sltu $[[T0:[0-9]+]], $3, $7 + ; MM32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM32: addu $2, $4, $[[T1]] + + ; MM64: daddu $2, $4, $5 + %r = add i64 %a, %b ret i64 %r } @@ -102,13 +132,13 @@ entry: ; GP32: lw $[[T3:[0-9]+]], 24($sp) ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: lw $[[T6:[0-9]+]], 16($sp) ; GP32: lw $[[T7:[0-9]+]], 20($sp) - ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] - ; GP32: lw $[[T9:[0-9]+]], 16($sp) + ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]] ; GP32: addu $3, $5, $[[T8]] ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]] ; GP32: addu $2, $4, $[[T11]] ; GP32: move $4, $[[T5]] ; GP32: move $5, $[[T1]] @@ -118,6 +148,285 @@ entry: ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 ; GP64: daddu $2, $4, $[[T1]] + ; MM32: lw $[[T0:[0-9]+]], 28($sp) + ; MM32: addu $[[T1:[0-9]+]], $7, $[[T0]] + ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32: lw $[[T3:[0-9]+]], 24($sp) + ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; MM32: lw $[[T7:[0-9]+]], 20($sp) + ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; MM32: addu $[[T9:[0-9]+]], $5, $[[T8]] + ; MM32: lw $[[T10:[0-9]+]], 16($sp) + ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]] + ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T10]] + ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]] + ; MM32: move $4, $[[T5]] + ; MM32: move $5, $[[T1]] + + ; MM64: daddu $3, $5, $7 + ; MM64: sltu $[[T0:[0-9]+]], $3, $7 + ; MM64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; MM64: daddu $2, $4, $[[T1]] + %r = add i128 %a, %b ret i128 %r } + +define signext i1 @add_i1_4(i1 signext %a) { +; ALL-LABEL: add_i1_4: + + ; ALL: move $2, $4 + + %r = add i1 4, %a + ret i1 %r +} + +define signext i8 @add_i8_4(i8 signext %a) { +; ALL-LABEL: add_i8_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 1024 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seb $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seb $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seb $2, $[[T0]] + + %r = add i8 4, %a + ret i8 %r +} + +define signext i16 @add_i16_4(i16 signext %a) { +; ALL-LABEL: add_i16_4: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 4 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 4 + ; R2-R6: seh $2, $[[T0]] + + ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM32: seh $2, $[[T0]] + + ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4 + ; MM64: seh $2, $[[T0]] + + %r = add i16 4, %a + ret i16 %r +} + +define signext i32 @add_i32_4(i32 signext %a) { +; ALL-LABEL: add_i32_4: + + ; GP32: addiu $2, $4, 4 + + ; GP64: addiu $2, $4, 4 + + ; MM32: addiur2 $2, $4, 4 + + ; MM64: addiur2 $2, $4, 4 + + %r = add i32 4, %a + ret i32 %r +} + +define signext i64 @add_i64_4(i64 signext %a) { +; ALL-LABEL: add_i64_4: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 4 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 4 + + %r = add i64 4, %a + ret i64 %r +} + +define signext i128 @add_i128_4(i128 signext %a) { +; ALL-LABEL: add_i128_4: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 4 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 4 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T1]], $[[T2]], $zero + ; GP32: addu $[[T3:[0-9]+]], $5, $[[T1]] + ; GP32: sltu $[[T1]], $[[T3]], $zero + ; GP32: addu $[[T1]], $4, $[[T1]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 4 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 4 + ; MM32: li16 $[[T1:[0-9]+]], 4 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T1]], 0 + ; MM32: sltu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; MM32: addu $[[T3]], $5, $[[T3]] + ; MM32: sltu $[[T1]], $[[T3]], $[[T1]] + ; MM32: addu $[[T1]], $4, $[[T1]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 4 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 4 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 4, %a + ret i128 %r +} + +define signext i1 @add_i1_3(i1 signext %a) { +; ALL-LABEL: add_i1_3: + + ; ALL: sll $[[T0:[0-9]+]], $4, 31 + ; ALL: lui $[[T1:[0-9]+]], 32768 + + ; GP32: addu $[[T0]], $[[T0]], $[[T1]] + ; GP32: sra $[[T1]], $[[T0]], 31 + + ; GP64: addu $[[T0]], $[[T0]], $[[T1]] + ; GP64: sra $[[T1]], $[[T0]], 31 + + ; MMR6: addu16 $[[T0]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T0]], $[[T0]], 31 + + %r = add i1 3, %a + ret i1 %r +} + +define signext i8 @add_i8_3(i8 signext %a) { +; ALL-LABEL: add_i8_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 24 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 768 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seb $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seb $2, $[[T0]] + + %r = add i8 3, %a + ret i8 %r +} + +define signext i16 @add_i16_3(i16 signext %a) { +; ALL-LABEL: add_i16_3: + + ; NOT-R2-R6: sll $[[T0:[0-9]+]], $4, 16 + ; NOT-R2-R6: lui $[[T1:[0-9]+]], 3 + ; NOT-R2-R6: addu $[[T0]], $[[T0]], $[[T1]] + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addiu $[[T0:[0-9]+]], $4, 3 + ; R2-R6: seh $2, $[[T0]] + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: seh $2, $[[T0]] + + %r = add i16 3, %a + ret i16 %r +} + +define signext i32 @add_i32_3(i32 signext %a) { +; ALL-LABEL: add_i32_3: + + ; NOT-R2-R6: addiu $2, $4, 3 + + ; R2-R6: addiu $2, $4, 3 + + ; MMR6: addius5 $[[T0:[0-9]+]], 3 + ; MMR6: move $2, $[[T0]] + + %r = add i32 3, %a + ret i32 %r +} + +define signext i64 @add_i64_3(i64 signext %a) { +; ALL-LABEL: add_i64_3: + + ; GP32: addiu $[[T0:[0-9]+]], $5, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddiu $2, $4, 3 + + ; MM32: addiu $[[T0:[0-9]+]], $5, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MM32: addu $2, $4, $[[T2]] + + ; MM64: daddiu $2, $4, 3 + + %r = add i64 3, %a + ret i64 %r +} + +define signext i128 @add_i128_3(i128 signext %a) { +; ALL-LABEL: add_i128_3: + + ; GP32: addiu $[[T0:[0-9]+]], $7, 3 + ; GP32: addiu $[[T1:[0-9]+]], $zero, 3 + ; GP32: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; GP32: sltu $[[T3:[0-9]+]], $[[T2]], $zero + ; GP32: addu $[[T4:[0-9]+]], $5, $[[T3]] + ; GP32: sltu $[[T5:[0-9]+]], $[[T4]], $zero + ; GP32: addu $[[T5]], $4, $[[T5]] + ; GP32: move $4, $[[T2]] + ; GP32: move $5, $[[T0]] + + ; GP64: daddiu $[[T0:[0-9]+]], $5, 3 + ; GP64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; GP64: sltu $[[T1]], $[[T0]], $[[T1]] + ; GP64: daddu $2, $4, $[[T1]] + + ; MM32: addiu $[[T0:[0-9]+]], $7, 3 + ; MM32: li16 $[[T1:[0-9]+]], 3 + ; MM32: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM32: addu $[[T2:[0-9]+]], $6, $[[T1]] + ; MM32: lui $[[T3:[0-9]+]], 0 + ; MM32: sltu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; MM32: addu $[[T4]], $5, $[[T4]] + ; MM32: sltu $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; MM32: addu $[[T5]], $4, $[[T5]] + ; MM32: move $4, $[[T2]] + ; MM32: move $5, $[[T0]] + + ; MM64: daddiu $[[T0:[0-9]+]], $5, 3 + ; MM64: daddiu $[[T1:[0-9]+]], $zero, 3 + ; MM64: sltu $[[T1]], $[[T0]], $[[T1]] + ; MM64: daddu $2, $4, $[[T1]] + + %r = add i128 3, %a + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll index c4121701ec15..d320ce60f291 100644 --- a/test/CodeGen/Mips/llvm-ir/and.ll +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -1,35 +1,46 @@ ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: -check-prefixes=ALL,GP32 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: -check-prefixes=ALL,GP64 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM32 +; RUN: llc < %s -march=mips -mcpu=mips64r6 -target-abi n64 -mattr=+micromips | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MM64 define signext i1 @and_i1(i1 signext %a, i1 signext %b) { entry: ; ALL-LABEL: and_i1: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i1 %a, %b ret i1 %r @@ -39,7 +50,12 @@ define signext i8 @and_i8(i8 signext %a, i8 signext %b) { entry: ; ALL-LABEL: and_i8: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i8 %a, %b ret i8 %r @@ -49,7 +65,12 @@ define signext i16 @and_i16(i16 signext %a, i16 signext %b) { entry: ; ALL-LABEL: and_i16: - ; ALL: and $2, $4, $5 + ; GP32: and $2, $4, $5 + + ; GP64: and $2, $4, $5 + + ; MM: and16 $[[T0:[0-9]+]], $5 + ; MM: move $2, $[[T0]] %r = and i16 %a, %b ret i16 %r @@ -64,6 +85,12 @@ entry: ; GP64: and $[[T0:[0-9]+]], $4, $5 ; GP64: sll $2, $[[T0]], 0 + ; MM32: and16 $[[T0:[0-9]+]], $5 + ; MM32: move $2, $[[T0]] + + ; MM64: and $[[T0:[0-9]+]], $4, $5 + ; MM64: sll $2, $[[T0]], 0 + %r = and i32 %a, %b ret i32 %r } @@ -77,6 +104,13 @@ entry: ; GP64: and $2, $4, $5 + ; MM32: and16 $[[T0:[0-9]+]], $6 + ; MM32: and16 $[[T1:[0-9]+]], $7 + ; MM32: move $2, $[[T0]] + ; MM32: move $3, $[[T1]] + + ; MM64: and $2, $4, $5 + %r = and i64 %a, %b ret i64 %r } @@ -97,6 +131,573 @@ entry: ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 + ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) + ; MM32: and16 $[[T3]], $7 + + ; MM64: and $2, $4, $6 + ; MM64: and $3, $5, $7 + %r = and i128 %a, %b ret i128 %r } + +define signext i1 @and_i1_4(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_4: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 4, %b + ret i1 %r +} + +define signext i8 @and_i8_4(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i8 4, %b + ret i8 %r +} + +define signext i16 @and_i16_4(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i16 4, %b + ret i16 %r +} + +define signext i32 @and_i32_4(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_4: + + ; GP32: andi $2, $4, 4 + + ; GP64: andi $2, $4, 4 + + ; MM: andi16 $2, $4, 4 + + %r = and i32 4, %b + ret i32 %r +} + +define signext i64 @and_i64_4(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_4: + + ; GP32: andi $3, $5, 4 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 4 + + ; MM32: andi16 $3, $5, 4 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 4 + + %r = and i64 4, %b + ret i64 %r +} + +define signext i128 @and_i128_4(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_4: + + ; GP32: andi $5, $7, 4 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 4 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 4 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 4 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 4, %b + ret i128 %r +} + +define signext i1 @and_i1_31(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_31: + + ; ALL: move $2, $4 + + %r = and i1 31, %b + ret i1 %r +} + +define signext i8 @and_i8_31(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i8 31, %b + ret i8 %r +} + +define signext i16 @and_i16_31(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i16 31, %b + ret i16 %r +} + +define signext i32 @and_i32_31(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_31: + + ; GP32: andi $2, $4, 31 + + ; GP64: andi $2, $4, 31 + + ; MM: andi16 $2, $4, 31 + + %r = and i32 31, %b + ret i32 %r +} + +define signext i64 @and_i64_31(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_31: + + ; GP32: andi $3, $5, 31 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 31 + + ; MM32: andi16 $3, $5, 31 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 31 + + %r = and i64 31, %b + ret i64 %r +} + +define signext i128 @and_i128_31(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_31: + + ; GP32: andi $5, $7, 31 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 31 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 31 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 31 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 31, %b + ret i128 %r +} + +define signext i1 @and_i1_255(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_255: + + ; ALL: move $2, $4 + + %r = and i1 255, %b + ret i1 %r +} + +define signext i8 @and_i8_255(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_255: + + ; ALL: move $2, $4 + + %r = and i8 255, %b + ret i8 %r +} + +define signext i16 @and_i16_255(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i16 255, %b + ret i16 %r +} + +define signext i32 @and_i32_255(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_255: + + ; GP32: andi $2, $4, 255 + + ; GP64: andi $2, $4, 255 + + ; MM: andi16 $2, $4, 255 + + %r = and i32 255, %b + ret i32 %r +} + +define signext i64 @and_i64_255(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_255: + + ; GP32: andi $3, $5, 255 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 255 + + ; MM32: andi16 $3, $5, 255 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 255 + + %r = and i64 255, %b + ret i64 %r +} + +define signext i128 @and_i128_255(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_255: + + ; GP32: andi $5, $7, 255 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 255 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 255 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 255 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 255, %b + ret i128 %r +} + +define signext i1 @and_i1_32768(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 32768, %b + ret i1 %r +} + +define signext i8 @and_i8_32768(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_32768: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 32768, %b + ret i8 %r +} + +define signext i16 @and_i16_32768(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_32768: + + ; GP32: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP32: and $2, $4, $[[T0]] + + ; GP64: addiu $[[T0:[0-9]+]], $zero, -32768 + ; GP64: and $2, $4, $[[T0]] + + ; MM: addiu $2, $zero, -32768 + ; MM: and16 $2, $4 + + %r = and i16 32768, %b + ret i16 %r +} + +define signext i32 @and_i32_32768(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_32768: + + ; GP32: andi $2, $4, 32768 + + ; GP64: andi $2, $4, 32768 + + ; MM: andi16 $2, $4, 32768 + + %r = and i32 32768, %b + ret i32 %r +} + +define signext i64 @and_i64_32768(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_32768: + + ; GP32: andi $3, $5, 32768 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 32768 + + ; MM32: andi16 $3, $5, 32768 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 32768 + + %r = and i64 32768, %b + ret i64 %r +} + +define signext i128 @and_i128_32768(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_32768: + + ; GP32: andi $5, $7, 32768 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 32768 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi16 $5, $7, 32768 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 32768 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 32768, %b + ret i128 %r +} + +define signext i1 @and_i1_65(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_65: + + ; ALL: move $2, $4 + + %r = and i1 65, %b + ret i1 %r +} + +define signext i8 @and_i8_65(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_65: + + ; ALL: andi $2, $4, 65 + + %r = and i8 65, %b + ret i8 %r +} + +define signext i16 @and_i16_65(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_65: + + ; ALL: andi $2, $4, 65 + + %r = and i16 65, %b + ret i16 %r +} + +define signext i32 @and_i32_65(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_65: + + ; ALL: andi $2, $4, 65 + + %r = and i32 65, %b + ret i32 %r +} + +define signext i64 @and_i64_65(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_65: + + ; GP32: andi $3, $5, 65 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 65 + + ; MM32: andi $3, $5, 65 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 65 + + %r = and i64 65, %b + ret i64 %r +} + +define signext i128 @and_i128_65(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_65: + + ; GP32: andi $5, $7, 65 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 65 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 65 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 65 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 65, %b + ret i128 %r +} + +define signext i1 @and_i1_256(i1 signext %b) { +entry: +; ALL-LABEL: and_i1_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i1 256, %b + ret i1 %r +} + +define signext i8 @and_i8_256(i8 signext %b) { +entry: +; ALL-LABEL: and_i8_256: + + ; GP32: addiu $2, $zero, 0 + + ; GP64: addiu $2, $zero, 0 + + ; MM: lui $2, 0 + + %r = and i8 256, %b + ret i8 %r +} + +define signext i16 @and_i16_256(i16 signext %b) { +entry: +; ALL-LABEL: and_i16_256: + + ; ALL: andi $2, $4, 256 + + %r = and i16 256, %b + ret i16 %r +} + +define signext i32 @and_i32_256(i32 signext %b) { +entry: +; ALL-LABEL: and_i32_256: + + ; ALL: andi $2, $4, 256 + + %r = and i32 256, %b + ret i32 %r +} + +define signext i64 @and_i64_256(i64 signext %b) { +entry: +; ALL-LABEL: and_i64_256: + + ; GP32: andi $3, $5, 256 + ; GP32: addiu $2, $zero, 0 + + ; GP64: andi $2, $4, 256 + + ; MM32: andi $3, $5, 256 + ; MM32: lui $2, 0 + + ; MM64: andi $2, $4, 256 + + %r = and i64 256, %b + ret i64 %r +} + +define signext i128 @and_i128_256(i128 signext %b) { +entry: +; ALL-LABEL: and_i128_256: + + ; GP32: andi $5, $7, 256 + ; GP32: addiu $2, $zero, 0 + ; GP32: addiu $3, $zero, 0 + ; GP32: addiu $4, $zero, 0 + + ; GP64: andi $3, $5, 256 + ; GP64: daddiu $2, $zero, 0 + + ; MM32: andi $5, $7, 256 + ; MM32: lui $2, 0 + ; MM32: lui $3, 0 + ; MM32: lui $4, 0 + + ; MM64: andi $3, $5, 256 + ; MM64: daddiu $2, $zero, 0 + + %r = and i128 256, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll index cad4a39d7743..af9b81f9203f 100644 --- a/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -1,42 +1,33 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R1-R5 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP32 \ -; RUN: -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=M3 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=GP64-NOT-R6 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=GP64 \ -; RUN: -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,M2 +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP32,32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,GP64,64R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR3 +; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips -relocation-model=pic | FileCheck %s \ +; RUN: -check-prefixes=ALL,MM,MMR6 define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { entry: @@ -53,7 +44,9 @@ entry: ; ALL-LABEL: ashr_i8: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; GP32: andi $[[T0:[0-9]+]], $5, 255 + ; GP64: andi $[[T0:[0-9]+]], $5, 255 + ; MM: andi16 $[[T0:[0-9]+]], $5, 255 ; ALL: srav $2, $4, $[[T0]] %r = ashr i8 %a, %b @@ -65,7 +58,9 @@ entry: ; ALL-LABEL: ashr_i16: ; FIXME: The andi instruction is redundant. - ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; GP32: andi $[[T0:[0-9]+]], $5, 65535 + ; GP64: andi $[[T0:[0-9]+]], $5, 65535 + ; MM: andi16 $[[T0:[0-9]+]], $5, 65535 ; ALL: srav $2, $4, $[[T0]] %r = ashr i16 %a, %b @@ -133,6 +128,32 @@ entry: ; GP64: dsrav $2, $4, $5 + ; MMR3: srlv $[[T0:[0-9]+]], $5, $7 + ; MMR3: sll16 $[[T1:[0-9]+]], $4, 1 + ; MMR3: not16 $[[T2:[0-9]+]], $7 + ; MMR3: sllv $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; MMR3: or16 $[[T4:[0-9]+]], $[[T0]] + ; MMR3: srav $[[T5:[0-9]+]], $4, $7 + ; MMR3: andi16 $[[T6:[0-9]+]], $7, 32 + ; MMR3: movn $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; MMR3: sra $[[T8:[0-9]+]], $4, 31 + ; MMR3: movn $2, $[[T8]], $[[T6]] + + ; MMR6: srav $[[T0:[0-9]+]], $4, $7 + ; MMR6: andi16 $[[T1:[0-9]+]], $7, 32 + ; MMR6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: sra $[[T3:[0-9]+]], $4, 31 + ; MMR6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; MMR6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; MMR6: srlv $[[T6:[0-9]+]], $5, $7 + ; MMR6: sll16 $[[T7:[0-9]+]], $4, 1 + ; MMR6: not16 $[[T8:[0-9]+]], $7 + ; MMR6: sllv $[[T9:[0-9]+]], $[[T7]], $[[T8]] + ; MMR6: or16 $[[T10:[0-9]+]], $[[T6]] + ; MMR6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; MMR6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; MMR6: or $3, $[[T12]], $[[T11]] + %r = ashr i64 %a, %b ret i64 %r } @@ -192,6 +213,8 @@ entry: ; 64R6: jr $ra ; 64R6: or $3, $[[T13]], $[[T12]] + ; MM: lw $25, %call16(__ashrti3)($2) + %r = ashr i128 %a, %b ret i128 %r } diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index a4b03405f72b..0d524d439600 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -1,18 +1,18 @@ ; Test the 'call' instruction and the tailcall variant. ; FIXME: We should remove the need for -enable-mips-tail-calls -; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+fp64,+nooddspreg -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 -; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 -; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 +; RUN: llc -march=mips -mcpu=mips32 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r2 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r3 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r5 -relocation-model=pic -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,NOT-R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips -mcpu=mips32r6 -relocation-model=pic -mattr=+fp64,+nooddspreg -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,O32,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,NOT-R6C +; RUN: llc -march=mips64 -mcpu=mips64r6 -disable-mips-delay-filler -enable-mips-tail-calls < %s | FileCheck %s -check-prefixes=ALL,N64,R6C declare void @extern_void_void() declare i32 @extern_i32_void() @@ -25,9 +25,11 @@ define i32 @call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] call void @extern_void_void() +; R6C: jrc $ra ret i32 0 } @@ -38,10 +40,12 @@ define i32 @call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] %1 = call i32 @extern_i32_void() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -55,12 +59,13 @@ define float @call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] -; O32: move $gp, $[[GP]] %1 = call float @extern_float_void() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -71,8 +76,7 @@ define void @musttail_call_void_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_void_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] musttail call void @extern_void_void() ret void @@ -85,8 +89,7 @@ define i32 @musttail_call_i32_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_i32_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call i32 @extern_i32_void() ret i32 %1 @@ -99,8 +102,7 @@ define float @musttail_call_float_void() { ; N64: ld $[[TGT:[0-9]+]], %call16(extern_float_void)($gp) -; NOT-R6: jr $[[TGT]] -; R6: r6.jr $[[TGT]] +; ALL: jr $[[TGT]] %1 = musttail call float @extern_float_void() ret float %1 @@ -110,9 +112,11 @@ define i32 @indirect_call_void_void(void ()* %addr) { ; ALL-LABEL: indirect_call_void_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 call void %addr() +; R6C: jrc $ra ret i32 0 } @@ -120,10 +124,13 @@ define i32 @indirect_call_i32_void(i32 ()* %addr) { ; ALL-LABEL: indirect_call_i32_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call i32 %addr() %2 = add i32 %1, 1 +; R6C: jrc $ra ret i32 %2 } @@ -131,10 +138,13 @@ define float @indirect_call_float_void(float ()* %addr) { ; ALL-LABEL: indirect_call_float_void: ; ALL: move $25, $4 -; ALL: jalr $25 +; NOT-R6C: jalr $25 +; R6C: jalrc $25 + %1 = call float %addr() %2 = fadd float %1, 1.0 +; R6C: jrc $ra ret float %2 } @@ -178,7 +188,8 @@ define hidden void @thunk_undef_double(i32 %this, double %volume) unnamed_addr a ; ALL-LABEL: thunk_undef_double: ; O32: # implicit-def: %A2 ; O32: # implicit-def: %A3 -; ALL: jr $25 +; ALL: jr $25 + tail call void @undef_double(i32 undef, double undef) #8 ret void } @@ -190,10 +201,12 @@ define i32 @jal_only_allows_symbols() { ; ALL-NOT: {{jal }} ; ALL: addiu $[[TGT:[0-9]+]], $zero, 1234 ; ALL-NOT: {{jal }} -; ALL: jalr $[[TGT]] +; NOT-R6C: jalr $[[TGT]] +; R6C: jalrc $[[TGT]] ; ALL-NOT: {{jal }} call void () inttoptr (i32 1234 to void ()*)() +; R6C: jrc $ra ret i32 0 } diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll index debfeb35b213..d982b570d7c2 100644 --- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -1,30 +1,33 @@ ; Test all important variants of the unconditional 'br' instruction. -; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 -; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 -; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 +; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6C +; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefixes=ALL,R6 define i32 @br(i8 *%addr) { ; ALL-LABEL: br: ; NOT-R6: jr $4 # &1 | FileCheck --check-prefix=DSP %s +; RUN: llc -march=mipsel -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s +; RUN: not llc -march=mipsel -mcpu=mips64r6 -target-abi n64 -mattr=+dsp < %s 2>&1 | FileCheck --check-prefix=DSP %s ; CHECK: foo: ; DSP: MIPS64r6 is not compatible with the DSP ASE diff --git a/test/CodeGen/Mips/mips64shift.ll b/test/CodeGen/Mips/mips64shift.ll index 52c6f9066392..e93140f18c9b 100644 --- a/test/CodeGen/Mips/mips64shift.ll +++ b/test/CodeGen/Mips/mips64shift.ll @@ -1,64 +1,65 @@ -; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s +; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s +; RUN: llc -march=mips64el -mcpu=mips64r6 -mattr=micromips < %s | FileCheck -check-prefixes=ALL,MICROMIPS %s define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsllv +; ALL: dsllv %shl = shl i64 %a0, %a1 ret i64 %shl } define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsrav +; ALL: dsrav %shr = ashr i64 %a0, %a1 ret i64 %shr } define i64 @f2(i64 %a0, i64 %a1) nounwind readnone { entry: -; CHECK: dsrlv +; ALL: dsrlv %shr = lshr i64 %a0, %a1 ret i64 %shr } define i64 @f3(i64 %a0) nounwind readnone { entry: -; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10 %shl = shl i64 %a0, 10 ret i64 %shl } define i64 @f4(i64 %a0) nounwind readnone { entry: -; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = ashr i64 %a0, 10 ret i64 %shr } define i64 @f5(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = lshr i64 %a0, 10 ret i64 %shr } define i64 @f6(i64 %a0) nounwind readnone { entry: -; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40 %shl = shl i64 %a0, 40 ret i64 %shl } define i64 @f7(i64 %a0) nounwind readnone { entry: -; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = ashr i64 %a0, 40 ret i64 %shr } define i64 @f8(i64 %a0) nounwind readnone { entry: -; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 +; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40 %shr = lshr i64 %a0, 40 ret i64 %shr } @@ -66,7 +67,7 @@ entry: define i64 @f9(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK-NOT: sll -; CHECK: drotrv +; ALL: drotrv %shr = lshr i64 %a0, %a1 %sub = sub i64 64, %a1 %shl = shl i64 %a0, %sub @@ -77,7 +78,7 @@ entry: define i64 @f10(i64 %a0, i64 %a1) nounwind readnone { entry: ; CHECK-NOT: sll -; CHECK: drotrv +; ALL: drotrv %shl = shl i64 %a0, %a1 %sub = sub i64 64, %a1 %shr = lshr i64 %a0, %sub @@ -87,7 +88,7 @@ entry: define i64 @f11(i64 %a0) nounwind readnone { entry: -; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 +; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10 %shr = lshr i64 %a0, 10 %shl = shl i64 %a0, 54 %or = or i64 %shr, %shl @@ -96,7 +97,7 @@ entry: define i64 @f12(i64 %a0) nounwind readnone { entry: -; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 +; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54 %shl = shl i64 %a0, 10 %shr = lshr i64 %a0, 54 %or = or i64 %shl, %shr diff --git a/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/test/CodeGen/Mips/mno-ldc1-sdc1.ll index c7eda3320bc6..9663138d4c81 100644 --- a/test/CodeGen/Mips/mno-ldc1-sdc1.ll +++ b/test/CodeGen/Mips/mno-ldc1-sdc1.ll @@ -1,52 +1,63 @@ ; Check that [sl]dc1 are normally emitted. MIPS32r2 should have [sl]dxc1 too. -; RUN: llc -march=mipsel -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1-LDC1 -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2-LDXC1 -; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R1-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R2-LDXC1 +; RUN: llc -march=mipsel -mcpu=mips32r6 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1 +; RUN: llc -march=mipsel -mcpu=mips32r3 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \ +; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefixes=ALL,MM ; Check that -mno-ldc1-sdc1 disables [sl]dc1 ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-PIC ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-PIC ; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-PIC +; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC +; RUN: llc -march=mipsel -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-LE-PIC ; Check again for big-endian ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-BE -check-prefix=32R1-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-BE,32R1-BE-PIC ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-BE -check-prefix=32R2-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-BE,32R2-BE-PIC ; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-BE -check-prefix=32R6-BE-PIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-BE,32R6-BE-PIC +; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC +; RUN: llc -march=mips -relocation-model=pic -mno-ldc1-sdc1 -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,MM-MNO-PIC,MM-MNO-BE-PIC ; Check again for the static relocation model ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R1 \ -; RUN: -check-prefix=32R1-LE -check-prefix=32R1-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R1,32R1-LE,32R1-LE-STATIC ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r2 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R2 \ -; RUN: -check-prefix=32R2-LE -check-prefix=32R2-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R2,32R2-LE,32R2-LE-STATIC ; RUN: llc -march=mipsel -relocation-model=static -mno-ldc1-sdc1 \ ; RUN: -mcpu=mips32r6 < %s | \ -; RUN: FileCheck %s -check-prefix=ALL -check-prefix=32R6 \ -; RUN: -check-prefix=32R6-LE -check-prefix=32R6-LE-STATIC +; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC +; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \ +; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC_PIC +; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \ +; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC @g0 = common global double 0.000000e+00, align 8 @@ -109,6 +120,26 @@ ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) +; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM: ldc1 $f0, 0($[[R3]]) + +; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM-MNO-PIC: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM-MNO-PIC: lw16 $[[R4:[0-9]+]], 0($[[R3]]) +; MM-MNO-PIC: lw16 $[[R5:[0-9]+]], 4($[[R3]]) +; MM-MNO-LE-PIC: mtc1 $[[R4]], $f0 +; MM-MNO-LE-PIC: mthc1 $[[R5]], $f0 +; MM-MNO-BE-PIC: mtc1 $[[R5]], $f0 +; MM-MNO-BE-PIC: mthc1 $[[R4]], $f0 + +; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) +; MM-STATIC-PIC: ldc1 $f0, %lo(g0)($[[R0]]) + define double @test_ldc1() { entry: %0 = load double, double* @g0, align 8 @@ -174,6 +205,26 @@ entry: ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) +; MM: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM: lw $[[R3:[0-9]+]], %got(g0)($[[R2]]) +; MM: sdc1 $f12, 0($[[R3]]) + +; MM-MNO-PIC: lui $[[R0:[0-9]+]], %hi(_gp_disp) +; MM-MNO-PIC: addiu $[[R1:[0-9]+]], $[[R0]], %lo(_gp_disp) +; MM-MNO-PIC: addu $[[R2:[0-9]+]], $[[R1]], $25 +; MM-MNO-LE-PIC: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC: lw $[[R4:[0-9]+]], %got(g0)($[[R2]]) +; MM-MNO-PIC: sw16 $[[R3]], 0($[[R4]]) +; MM-MNO-LE-PIC: mfhc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfc1 $[[R5:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R5]], 4($[[R4]]) + +; MM-STATIC-PIC: lui $[[R0:[0-9]+]], %hi(g0) +; MM-STATIC-PIC: sdc1 $f12, %lo(g0)($[[R0]]) + define void @test_sdc1(double %a) { entry: store double %a, double* @g0, align 8 @@ -210,6 +261,23 @@ entry: ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}}) +; MM: sll16 $[[R0:[0-9]+]], $5, 3 +; MM: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM: ldc1 $f0, 0($[[R1]]) + +; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $5, 3 +; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM-MNO-PIC: lw16 $[[R2:[0-9]+]], 0($[[R1]]) +; MM-MNO-PIC: lw16 $[[R3:[0-9]+]], 4($[[R1]]) +; MM-MNO-LE-PIC: mtc1 $[[R2]], $f0 +; MM-MNO-LE-PIC: mthc1 $[[R3]], $f0 +; MM-MNO-BE-PIC: mtc1 $[[R3]], $f0 +; MM-MNO-BE-PIC: mthc1 $[[R2]], $f0 + +; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $5, 3 +; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $4, $[[R0]] +; MM-STATIC-PIC: ldc1 $f0, 0($[[R1]]) + define double @test_ldxc1(double* nocapture readonly %a, i32 %i) { entry: %arrayidx = getelementptr inbounds double, double* %a, i32 %i @@ -241,6 +309,23 @@ entry: ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}}) +; MM: sll16 $[[R0:[0-9]+]], $7, 3 +; MM: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM: sdc1 $f12, 0($[[R1]]) + +; MM-MNO-PIC: sll16 $[[R0:[0-9]+]], $7, 3 +; MM-MNO-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM-MNO-LE-PIC: mfc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfhc1 $[[R2:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R2]], 0($[[R1]]) +; MM-MNO-LE-PIC: mfhc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-BE-PIC: mfc1 $[[R3:[0-9]+]], $f12 +; MM-MNO-PIC: sw16 $[[R3]], 4($[[R1]]) + +; MM-STATIC-PIC: sll16 $[[R0:[0-9]+]], $7, 3 +; MM-STATIC-PIC: addu16 $[[R1:[0-9]+]], $6, $[[R0]] +; MM-STATIC-PIC: sdc1 $f12, 0($[[R1]]) + define void @test_sdxc1(double %b, double* nocapture %a, i32 %i) { entry: %arrayidx = getelementptr inbounds double, double* %a, i32 %i diff --git a/test/CodeGen/Mips/msa/2r.ll b/test/CodeGen/Mips/msa/2r.ll index 501936c76e73..0abd73f180a0 100644 --- a/test/CodeGen/Mips/msa/2r.ll +++ b/test/CodeGen/Mips/msa/2r.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_nloc_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_nloc_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index ddcd3cf757d9..db0eb5ad5a43 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,14 +1,14 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 @llvm_mips_fill_b_RES = global <16 x i8> , align 16 @@ -97,4 +97,4 @@ declare <2 x i64> @llvm.mips.fill.d(i64) nounwind ; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES) ; MIPS64-DAG: st.d [[WD]], 0([[RD]]) ; MIPS-ANY: .size llvm_mips_fill_d_test -; \ No newline at end of file +; diff --git a/test/CodeGen/Mips/msa/2rf.ll b/test/CodeGen/Mips/msa/2rf.ll index 1dbfbda1b612..885e2c64bcfc 100644 --- a/test/CodeGen/Mips/msa/2rf.ll +++ b/test/CodeGen/Mips/msa/2rf.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_flog2_w_ARG1 = global <4 x float> , align 16 @llvm_mips_flog2_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_float_int.ll b/test/CodeGen/Mips/msa/2rf_float_int.ll index 369015814b0e..44861caf4650 100644 --- a/test/CodeGen/Mips/msa/2rf_float_int.ll +++ b/test/CodeGen/Mips/msa/2rf_float_int.ll @@ -1,8 +1,8 @@ ; Test the MSA integer to floating point conversion intrinsics that are encoded ; with the 2RF instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_ffint_s_w_ARG1 = global <4 x i32> , align 16 @llvm_mips_ffint_s_w_RES = global <4 x float> , align 16 diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll index 77d1404f9cfa..f845f3ddd740 100644 --- a/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -2,8 +2,8 @@ ; 2RF instruction format. This includes conversions but other instructions such ; as fclass are also here. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_fclass_w_ARG1 = global <4 x float> , align 16 @llvm_mips_fclass_w_RES = global <4 x i32> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-a.ll b/test/CodeGen/Mips/msa/3r-a.ll index db772f918614..8feb928a8add 100644 --- a/test/CodeGen/Mips/msa/3r-a.ll +++ b/test/CodeGen/Mips/msa/3r-a.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'a' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s ; It should fail to compile without fp64. ; RUN: not llc -march=mips -mattr=+msa < %s 2>&1 | \ diff --git a/test/CodeGen/Mips/msa/3r-b.ll b/test/CodeGen/Mips/msa/3r-b.ll index 2ecdc4290067..1c4f14814a2a 100644 --- a/test/CodeGen/Mips/msa/3r-b.ll +++ b/test/CodeGen/Mips/msa/3r-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclr_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclr_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r-s.ll b/test/CodeGen/Mips/msa/3r-s.ll index d04c5ff165f2..fe4365110366 100644 --- a/test/CodeGen/Mips/msa/3r-s.ll +++ b/test/CodeGen/Mips/msa/3r-s.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the 3R instruction format. ; There are lots of these so this covers those beginning with 's' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_sld_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_sld_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/3r_splat.ll b/test/CodeGen/Mips/msa/3r_splat.ll index 56d26b030de9..78c485f4f868 100644 --- a/test/CodeGen/Mips/msa/3r_splat.ll +++ b/test/CodeGen/Mips/msa/3r_splat.ll @@ -1,9 +1,9 @@ ; Test the MSA splat intrinsics that are encoded with the 3R instruction ; format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ ; RUN: FileCheck -check-prefix=MIPS32 %s @llvm_mips_splat_b_ARG1 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/basic_operations.ll b/test/CodeGen/Mips/msa/basic_operations.ll index 2efec2911935..5d253d7af253 100644 --- a/test/CodeGen/Mips/msa/basic_operations.ll +++ b/test/CodeGen/Mips/msa/basic_operations.ll @@ -1,9 +1,21 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-BE %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 -check-prefix=MIPS32 -check-prefix=ALL-LE %s -; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-BE %s -; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 -check-prefix=MIPS64 -check-prefix=ALL-LE %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-BE %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 -check-prefix=MIPS64 -check-prefix=ALL-LE %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,O32,MIPS32,ALL-LE %s +; RUN: llc -march=mips64 -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-BE %s +; RUN: llc -march=mips64el -target-abi n32 -mattr=+msa,+fp64 \ +; RUN: -relocation-model=pic -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N32,MIPS64,ALL-LE %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-BE %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic \ +; RUN: -verify-machineinstrs < %s | \ +; RUN: FileCheck -check-prefixes=ALL,N64,MIPS64,ALL-LE %s @v4i8 = global <4 x i8> @v16i8 = global <16 x i8> diff --git a/test/CodeGen/Mips/msa/basic_operations_float.ll b/test/CodeGen/Mips/msa/basic_operations_float.ll index f19cb9b7c2e5..d714b3eec1f2 100644 --- a/test/CodeGen/Mips/msa/basic_operations_float.ll +++ b/test/CodeGen/Mips/msa/basic_operations_float.ll @@ -1,9 +1,9 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=O32 %s -; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N32 %s -; RUN: llc -march=mips64 -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s -; RUN: llc -march=mips64el -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=N64 %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,O32 %s +; RUN: llc -march=mips64 -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64el -target-abi=n32 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N32 %s +; RUN: llc -march=mips64 -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s +; RUN: llc -march=mips64el -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,N64 %s @v4f32 = global <4 x float> @v2f64 = global <2 x double> diff --git a/test/CodeGen/Mips/msa/elm_copy.ll b/test/CodeGen/Mips/msa/elm_copy.ll index 251b535fd76c..8befecbdd65a 100644 --- a/test/CodeGen/Mips/msa/elm_copy.ll +++ b/test/CodeGen/Mips/msa/elm_copy.ll @@ -1,14 +1,14 @@ ; Test the MSA intrinsics that are encoded with the ELM instruction format and ; are element extraction operations. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_copy_s_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_copy_s_b_RES = global i32 0, align 16 diff --git a/test/CodeGen/Mips/msa/elm_cxcmsa.ll b/test/CodeGen/Mips/msa/elm_cxcmsa.ll index 8d6b0ee20ab8..b96499c15235 100644 --- a/test/CodeGen/Mips/msa/elm_cxcmsa.ll +++ b/test/CodeGen/Mips/msa/elm_cxcmsa.ll @@ -1,8 +1,8 @@ ; Test the MSA ctcmsa and cfcmsa intrinsics (which are encoded with the ELM ; instruction format). -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -verify-machineinstrs < %s | FileCheck %s define i32 @msa_ir_cfcmsa_test() nounwind { entry: diff --git a/test/CodeGen/Mips/msa/elm_insv.ll b/test/CodeGen/Mips/msa/elm_insv.ll index 46e6289189df..6458b6dc23db 100644 --- a/test/CodeGen/Mips/msa/elm_insv.ll +++ b/test/CodeGen/Mips/msa/elm_insv.ll @@ -1,14 +1,14 @@ ; Test the MSA element insertion intrinsics that are encoded with the ELM ; instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ -; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=MIPS-ANY,MIPS64 @llvm_mips_insert_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_insert_b_ARG3 = global i32 27, align 16 diff --git a/test/CodeGen/Mips/msa/frameindex.ll b/test/CodeGen/Mips/msa/frameindex.ll index afd28ae184dd..f903381f9ef0 100644 --- a/test/CodeGen/Mips/msa/frameindex.ll +++ b/test/CodeGen/Mips/msa/frameindex.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-BE %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=MIPS32-AE -check-prefix=MIPS32-LE %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-BE %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefixes=MIPS32-AE,MIPS32-LE %s define void @loadstore_v16i8_near() nounwind { ; MIPS32-AE: loadstore_v16i8_near: diff --git a/test/CodeGen/Mips/msa/i5-b.ll b/test/CodeGen/Mips/msa/i5-b.ll index 40ab095f6809..c588c8b2407e 100644 --- a/test/CodeGen/Mips/msa/i5-b.ll +++ b/test/CodeGen/Mips/msa/i5-b.ll @@ -1,8 +1,8 @@ ; Test the MSA intrinsics that are encoded with the I5 instruction format. ; There are lots of these so this covers those beginning with 'b' -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_bclri_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_bclri_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/i8.ll b/test/CodeGen/Mips/msa/i8.ll index 4af9c588fdef..5f8b4663c387 100644 --- a/test/CodeGen/Mips/msa/i8.ll +++ b/test/CodeGen/Mips/msa/i8.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the I8 instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck %s @llvm_mips_andi_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_andi_b_RES = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/msa/vec.ll b/test/CodeGen/Mips/msa/vec.ll index 8790923ce727..f206975990af 100644 --- a/test/CodeGen/Mips/msa/vec.ll +++ b/test/CodeGen/Mips/msa/vec.ll @@ -1,7 +1,7 @@ ; Test the MSA intrinsics that are encoded with the VEC instruction format. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck -check-prefix=ANYENDIAN %s +; RUN: llc -march=mips -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s +; RUN: llc -march=mipsel -mattr=+msa,+fp64 -relocation-model=pic < %s | FileCheck -check-prefix=ANYENDIAN %s @llvm_mips_and_v_b_ARG1 = global <16 x i8> , align 16 @llvm_mips_and_v_b_ARG2 = global <16 x i8> , align 16 diff --git a/test/CodeGen/Mips/nacl-align.ll b/test/CodeGen/Mips/nacl-align.ll index 8191c7dec6f2..74b6286648dd 100644 --- a/test/CodeGen/Mips/nacl-align.ll +++ b/test/CodeGen/Mips/nacl-align.ll @@ -7,8 +7,8 @@ define void @test0() { ret void -; CHECK: .align 4 -; CHECK-NOT: .align +; CHECK: .p2align 4 +; CHECK-NOT: .p2align ; CHECK-LABEL: test0: } @@ -40,18 +40,18 @@ default: ; CHECK-LABEL: test1: -; CHECK: .align 4 +; CHECK: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 111 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 555 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 222 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 333 @@ -81,12 +81,12 @@ bb2: ; Note that there are two consecutive labels - one temporary and one for ; basic block. -; CHECK: .align 4 +; CHECK: .p2align 4 ; CHECK-NEXT: ${{[a-zA-Z0-9]+}}: ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra ; CHECK-NEXT: addiu $2, $zero, 111 -; CHECK-NEXT: .align 4 +; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: ${{[a-zA-Z0-9]+}}: ; CHECK-NEXT: ${{BB[0-9]+_[0-9]+}}: ; CHECK-NEXT: jr $ra diff --git a/test/CodeGen/Mips/no-odd-spreg-msa.ll b/test/CodeGen/Mips/no-odd-spreg-msa.ll index 7213044a2300..603a99e267f6 100644 --- a/test/CodeGen/Mips/no-odd-spreg-msa.ll +++ b/test/CodeGen/Mips/no-odd-spreg-msa.ll @@ -1,9 +1,9 @@ ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,-nooddspreg \ -; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=ODDSPREG +; RUN: -no-integrated-as -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,ODDSPREG ; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+fp64,+msa,+nooddspreg \ -; RUN: -no-integrated-as < %s | FileCheck %s -check-prefix=ALL \ -; RUN: -check-prefix=NOODDSPREG +; RUN: -no-integrated-as -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=ALL,NOODDSPREG @v4f32 = global <4 x float> zeroinitializer diff --git a/test/CodeGen/Mips/no-odd-spreg.ll b/test/CodeGen/Mips/no-odd-spreg.ll index 572e940bc467..411441a7bd94 100644 --- a/test/CodeGen/Mips/no-odd-spreg.ll +++ b/test/CodeGen/Mips/no-odd-spreg.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-NO-EMIT -; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-NO-EMIT -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOODDSPREG -; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck %s -check-prefix=ALL -check-prefix=ODDSPREG -check-prefix=ODDSPREG-EMIT +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT +; RUN: llc -march=mipsel -mcpu=mips32 -mattr=+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64 < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-NO-EMIT +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fp64,+nooddspreg < %s | FileCheck %s -check-prefixes=ALL,NOODDSPREG +; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=fpxx,-nooddspreg < %s | FileCheck %s -check-prefixes=ALL,ODDSPREG,ODDSPREG-EMIT ; We don't emit a directive unless we need to. This is to support versions of ; GAS which do not support the directive. diff --git a/test/CodeGen/Mips/o32_cc.ll b/test/CodeGen/Mips/o32_cc.ll index c28f9abcadcd..cef1290a75bd 100644 --- a/test/CodeGen/Mips/o32_cc.ll +++ b/test/CodeGen/Mips/o32_cc.ll @@ -1,8 +1,7 @@ ; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mattr=+fp64 < %s | FileCheck -check-prefix=ALL %s -; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefix=ALL -check-prefix=NO-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s +; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s ; $f12, $f14 ; ALL-LABEL: testlowercall0: diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll index 108c663ab1cd..33431dba43c4 100644 --- a/test/CodeGen/Mips/o32_cc_byval.ll +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s %0 = type { i8, i16, i32, i64, double, i32, [4 x i8] } %struct.S1 = type { i8, i16, i32, i64, double, i32 } diff --git a/test/CodeGen/Mips/octeon.ll b/test/CodeGen/Mips/octeon.ll index 499ce3c1ddbf..b441274cec6b 100644 --- a/test/CodeGen/Mips/octeon.ll +++ b/test/CodeGen/Mips/octeon.ll @@ -1,5 +1,5 @@ -; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON -; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64 +; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefixes=ALL,OCTEON +; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,MIPS64 define i64 @addi64(i64 %a, i64 %b) nounwind { entry: diff --git a/test/CodeGen/Mips/octeon_popcnt.ll b/test/CodeGen/Mips/octeon_popcnt.ll index 3432b3992984..13488ed59504 100644 --- a/test/CodeGen/Mips/octeon_popcnt.ll +++ b/test/CodeGen/Mips/octeon_popcnt.ll @@ -21,7 +21,7 @@ define i16 @cnt16(i16 %x) nounwind readnone { ; MIPS64-NOT: pop } -define i32 @cnt32(i32 zeroext %x) nounwind readnone { +define i32 @cnt32(i32 signext %x) nounwind readnone { %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %cnt ; OCTEON-LABEL: cnt32: diff --git a/test/CodeGen/Mips/optimize-pic-o0.ll b/test/CodeGen/Mips/optimize-pic-o0.ll index 454bc851484d..8790b8e92b74 100644 --- a/test/CodeGen/Mips/optimize-pic-o0.ll +++ b/test/CodeGen/Mips/optimize-pic-o0.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=mipsel -O0 < %s | FileCheck %s +; RUN: llc -mtriple=mipsel -O0 -relocation-model=pic < %s | FileCheck %s ; Function Attrs: nounwind define i32 @main() { diff --git a/test/CodeGen/Mips/prevent-hoisting.ll b/test/CodeGen/Mips/prevent-hoisting.ll index 81b14d7441b3..200848ac5485 100644 --- a/test/CodeGen/Mips/prevent-hoisting.ll +++ b/test/CodeGen/Mips/prevent-hoisting.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel -O3 < %s | FileCheck %s +; RUN: llc -march=mipsel -O3 -relocation-model=pic < %s | FileCheck %s ; MIPS direct branches implicitly define register $at. This test makes sure that @@ -11,12 +11,12 @@ ; CHECK-LABEL: readLumaCoeff8x8_CABAC ; The check for first "addiu" instruction is added so that we can match the correct "b" instruction. -; CHECK: addiu ${{[0-9]+}}, $zero, -1 +; CHECK: andi ; CHECK: b $[[BB0:BB[0-9_]+]] -; CHECK-NEXT: addiu ${{[0-9]+}}, $zero, 0 +; CHECK-NEXT: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK-NEXT: {{BB[0-9_#]+}}: +; CHECK-NEXT: {{BB[0-9_#]+}}: ; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) ; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4 diff --git a/test/CodeGen/Mips/private-addr.ll b/test/CodeGen/Mips/private-addr.ll new file mode 100644 index 000000000000..37dd6fe53c40 --- /dev/null +++ b/test/CodeGen/Mips/private-addr.ll @@ -0,0 +1,14 @@ +; RUN: llc -mtriple=mips-pc-linux -relocation-model=pic < %s | FileCheck %s + +define private void @bar() { + ret void +} + +define void()* @foo() { +; CHECK: foo: +; CHECK: lw $[[REG:.*]], %got($bar)($1) +; CHECK-NEXT: jr $ra +; CHECK-NEXT: addiu $2, $[[REG]], %lo($bar) + + ret void()* @bar +} diff --git a/test/CodeGen/Mips/private.ll b/test/CodeGen/Mips/private.ll index 5907dbd644ae..07affbf30c38 100644 --- a/test/CodeGen/Mips/private.ll +++ b/test/CodeGen/Mips/private.ll @@ -1,6 +1,6 @@ ; Test to make sure that the 'private' is used correctly. ; -; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips -relocation-model=pic < %s | FileCheck %s define private void @foo() { ; CHECK-LABEL: foo: diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll index 3870fe092156..08eddf370096 100644 --- a/test/CodeGen/Mips/return-vector.ll +++ b/test/CodeGen/Mips/return-vector.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s ; Check that function accesses vector return value from stack in cases when diff --git a/test/CodeGen/Mips/rotate.ll b/test/CodeGen/Mips/rotate.ll index 70eff6e224d0..77936b7bef9b 100644 --- a/test/CodeGen/Mips/rotate.ll +++ b/test/CodeGen/Mips/rotate.ll @@ -1,8 +1,15 @@ ; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s ; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 < %s | FileCheck %s -check-prefix=mips16 +; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 +; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips < %s | FileCheck %s \ +; RUN: -check-prefix=MM32 ; CHECK: rotrv $2, $4 ; mips16: .ent rot0 +; MM32: li16 $2, 32 +; MM32: subu16 $2, $2, $5 +; MM32: rotrv $2, $4, $2 define i32 @rot0(i32 %a, i32 %b) nounwind readnone { entry: %shl = shl i32 %a, %b @@ -14,6 +21,7 @@ entry: ; CHECK: rotr $2, $4, 22 ; mips16: .ent rot1 +; MM32: rotr $2, $4, 22 define i32 @rot1(i32 %a) nounwind readnone { entry: %shl = shl i32 %a, 10 @@ -24,6 +32,7 @@ entry: ; CHECK: rotrv $2, $4, $5 ; mips16: .ent rot2 +; MM32: rotrv $2, $4, $5 define i32 @rot2(i32 %a, i32 %b) nounwind readnone { entry: %shr = lshr i32 %a, %b @@ -35,6 +44,7 @@ entry: ; CHECK: rotr $2, $4, 10 ; mips16: .ent rot3 +; MM32: rotr $2, $4, 10 define i32 @rot3(i32 %a) nounwind readnone { entry: %shr = lshr i32 %a, 10 diff --git a/test/CodeGen/Mips/select.ll b/test/CodeGen/Mips/select.ll index 96bd3782c058..0ef8f36333f2 100644 --- a/test/CodeGen/Mips/select.ll +++ b/test/CodeGen/Mips/select.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32 -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32R2 -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64 -; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64R2 -; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32 +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R2 +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -march=mips64el -mcpu=mips64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64 +; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R2 +; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 @d2 = external global double @d3 = external global double diff --git a/test/CodeGen/Mips/selectcc.ll b/test/CodeGen/Mips/selectcc.ll index 9790a0a3e411..865e4b38acad 100644 --- a/test/CodeGen/Mips/selectcc.ll +++ b/test/CodeGen/Mips/selectcc.ll @@ -1,7 +1,7 @@ -; RUN: llc -march=mipsel -mcpu=mips32 < %s -; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED -; RUN: llc -march=mipsel -mcpu=mips32r2 < %s -; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s +; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED +; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s +; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED @gf0 = external global float @gf1 = external global float diff --git a/test/CodeGen/Mips/selectiondag-optlevel.ll b/test/CodeGen/Mips/selectiondag-optlevel.ll new file mode 100644 index 000000000000..999361131745 --- /dev/null +++ b/test/CodeGen/Mips/selectiondag-optlevel.ll @@ -0,0 +1,22 @@ +; RUN: llc -march=mips -fast-isel=false -O0 < %s 2>&1 | FileCheck %s -check-prefix=O0 +; RUN: llc -march=mips -fast-isel=false -O2 < %s 2>&1 | FileCheck %s -check-prefix=O2 + +; At -O0, DAGCombine won't try to merge these consecutive loads but it will at +; -O2. + +define void @foo() nounwind { +entry: + %0 = alloca [2 x i8], align 32 + %1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0 + store i8 1, i8* %1 + %2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1 + store i8 1, i8* %2 + ret void +} + +; O0: addiu $[[REG:[0-9]+]], $zero, 1 +; O0-DAG: sb $[[REG]], 0($sp) +; O0-DAG: sb $[[REG]], 1($sp) + +; O2: addiu $[[REG:[0-9]+]], $zero, 257 +; O2: sh $[[REG]], 0($sp) diff --git a/test/CodeGen/Mips/stackcoloring.ll b/test/CodeGen/Mips/stackcoloring.ll index 5516b5a3c023..817caee2f275 100644 --- a/test/CodeGen/Mips/stackcoloring.ll +++ b/test/CodeGen/Mips/stackcoloring.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s @g1 = external global i32* diff --git a/test/CodeGen/Mips/start-asm-file.ll b/test/CodeGen/Mips/start-asm-file.ll index 60c047a4e8cc..6d0a5425230a 100644 --- a/test/CodeGen/Mips/start-asm-file.ll +++ b/test/CodeGen/Mips/start-asm-file.ll @@ -3,53 +3,53 @@ ; ### O32 ABI ### ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=static %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-O32 -check-prefix=CHECK-STATIC-O32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-O32,CHECK-STATIC-O32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=pic %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-O32 -check-prefix=CHECK-PIC-O32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-O32,CHECK-PIC-O32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=static -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-O32 -check-prefix=CHECK-STATIC-O32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-O32,CHECK-STATIC-O32-N2008 %s ; RUN: llc -filetype=asm -mtriple mips-unknown-linux -mcpu=mips32 \ ; RUN: -relocation-model=pic -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-O32 -check-prefix=CHECK-PIC-O32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-O32,CHECK-PIC-O32-N2008 %s ; ### N32 ABI ### ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n32 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N32,CHECK-STATIC-N32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n32 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N32,CHECK-PIC-N32-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n32 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N32 -check-prefix=CHECK-STATIC-N32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N32,CHECK-STATIC-N32-N2008 %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n32 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N32 -check-prefix=CHECK-PIC-N32-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N32,CHECK-PIC-N32-N2008 %s ; ### N64 ABI ### ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n64 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N64,CHECK-STATIC-N64-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n64 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-NLEGACY %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N64,CHECK-PIC-N64-NLEGACY %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=static -target-abi n64 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-STATIC-N64 -check-prefix=CHECK-STATIC-N64-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-STATIC-N64,CHECK-STATIC-N64-N2008 %s ; RUN: llc -filetype=asm -mtriple mips64-unknown-linux -mcpu=mips64 \ ; RUN: -relocation-model=pic -target-abi n64 -mattr=+nan2008 %s -o - | \ -; RUN: FileCheck -check-prefix=CHECK-PIC-N64 -check-prefix=CHECK-PIC-N64-N2008 %s +; RUN: FileCheck -check-prefixes=CHECK-PIC-N64,CHECK-PIC-N64-N2008 %s ; CHECK-STATIC-O32: .abicalls ; CHECK-STATIC-O32: .option pic0 diff --git a/test/CodeGen/Mips/stchar.ll b/test/CodeGen/Mips/stchar.ll index 4b3c8fb79315..34493e9ae338 100644 --- a/test/CodeGen/Mips/stchar.ll +++ b/test/CodeGen/Mips/stchar.ll @@ -5,32 +5,8 @@ @sp = common global i16* null, align 4 @cp = common global i8* null, align 4 -define void @p1(i16 signext %s, i8 signext %c) nounwind { -entry: - %conv = sext i16 %s to i32 - %conv1 = sext i8 %c to i32 - %call = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv, i32 %conv1) nounwind - ret void -} - declare i32 @printf(i8* nocapture, ...) nounwind -define void @p2() nounwind { -entry: - %0 = load i16*, i16** @sp, align 4 - %1 = load i16, i16* %0, align 2 - %2 = load i8*, i8** @cp, align 4 - %3 = load i8, i8* %2, align 1 - %conv.i = sext i16 %1 to i32 - %conv1.i = sext i8 %3 to i32 - %call.i = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind - %4 = load i16*, i16** @sp, align 4 - store i16 32, i16* %4, align 2 - %5 = load i8*, i8** @cp, align 4 - store i8 97, i8* %5, align 1 - ret void -} - define void @test() nounwind { entry: %s = alloca i16, align 4 @@ -58,32 +34,6 @@ entry: ; 16_h: lh ${{[0-9]+}}, [[offset2]](${{[0-9]+}}) } -define i32 @main() nounwind { -entry: - %s.i = alloca i16, align 4 - %c.i = alloca i8, align 4 - %0 = bitcast i16* %s.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) nounwind - call void @llvm.lifetime.start(i64 -1, i8* %c.i) nounwind - store i16 16, i16* %s.i, align 4 - store i8 99, i8* %c.i, align 4 - store i16* %s.i, i16** @sp, align 4 - store i8* %c.i, i8** @cp, align 4 - %call.i.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 16, i32 99) nounwind - %1 = load i16*, i16** @sp, align 4 - store i16 32, i16* %1, align 2 - %2 = load i8*, i8** @cp, align 4 - store i8 97, i8* %2, align 1 - %3 = load i16, i16* %s.i, align 4 - %4 = load i8, i8* %c.i, align 4 - %conv.i.i = sext i16 %3 to i32 - %conv1.i.i = sext i8 %4 to i32 - %call.i.i = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([9 x i8], [9 x i8]* @.str, i32 0, i32 0), i32 %conv.i.i, i32 %conv1.i.i) nounwind - call void @llvm.lifetime.end(i64 -1, i8* %0) nounwind - call void @llvm.lifetime.end(i64 -1, i8* %c.i) nounwind - ret i32 0 -} - declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/Mips/stldst.ll b/test/CodeGen/Mips/stldst.ll index 8aecca4aed67..62d5f1f92b45 100644 --- a/test/CodeGen/Mips/stldst.ll +++ b/test/CodeGen/Mips/stldst.ll @@ -33,9 +33,9 @@ entry: %call7 = tail call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([32 x i8], [32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind ret i32 0 } -; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill -; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload -; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill -; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload +; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload +; 16: sw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}}($sp) # 4-byte Folded Reload declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/Mips/tailcall.ll b/test/CodeGen/Mips/tailcall.ll index b0868255053a..61f8e508f40d 100644 --- a/test/CodeGen/Mips/tailcall.ll +++ b/test/CodeGen/Mips/tailcall.ll @@ -1,11 +1,12 @@ -; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls < %s | \ -; RUN: FileCheck %s -check-prefix=PIC32 -; RUN: llc -march=mipsel -relocation-model=static \ -; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=STATIC32 -; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+n64 -enable-mips-tail-calls \ -; RUN: < %s | FileCheck %s -check-prefix=N64 +; RUN: llc -march=mipsel -relocation-model=pic -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=PIC32 +; RUN: llc -march=mipsel -relocation-model=static -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=STATIC32 +; RUN: llc -march=mips64el -mcpu=mips64r2 -enable-mips-tail-calls \ +; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=N64 ; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic \ -; RUN: -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=PIC16 +; RUN: -enable-mips-tail-calls -verify-machineinstrs < %s | \ +; RUN: FileCheck %s -check-prefix=PIC16 @g0 = common global i32 0, align 4 @g1 = common global i32 0, align 4 diff --git a/test/CodeGen/Mips/thread-pointer.ll b/test/CodeGen/Mips/thread-pointer.ll new file mode 100644 index 000000000000..60bee3d03031 --- /dev/null +++ b/test/CodeGen/Mips/thread-pointer.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=mips < %s | FileCheck %s +; RUN: llc -march=mips64 < %s | FileCheck %s +; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mips64el < %s | FileCheck %s + +declare i8* @llvm.thread.pointer() nounwind readnone + +define i8* @thread_pointer() { +; CHECK: rdhwr $3, $29 + %1 = tail call i8* @llvm.thread.pointer() + ret i8* %1 +} diff --git a/test/CodeGen/Mips/tls-models.ll b/test/CodeGen/Mips/tls-models.ll index 1a958dceaa28..ca3c7fde19d4 100644 --- a/test/CodeGen/Mips/tls-models.ll +++ b/test/CodeGen/Mips/tls-models.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK-PIC %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck -check-prefix=CHECK-PIC %s ; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck -check-prefix=CHECK-NONPIC %s @external_gd = external thread_local global i32 diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll index 97e270fc59a6..8968567cb423 100644 --- a/test/CodeGen/Mips/tls.ll +++ b/test/CodeGen/Mips/tls.ll @@ -1,10 +1,10 @@ -; RUN: llc -march=mipsel -disable-mips-delay-filler < %s | \ -; RUN: FileCheck %s -check-prefix=PIC -check-prefix=CHECK +; RUN: llc -march=mipsel -disable-mips-delay-filler -relocation-model=pic < %s | \ +; RUN: FileCheck %s -check-prefixes=PIC,CHECK ; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler < \ -; RUN: %s | FileCheck %s -check-prefix=STATIC -check-prefix=CHECK +; RUN: %s | FileCheck %s -check-prefixes=STATIC,CHECK ; RUN: llc -march=mipsel -relocation-model=static -disable-mips-delay-filler \ ; RUN: -mips-fix-global-base-reg=false < %s | \ -; RUN: FileCheck %s -check-prefix=STATICGP -check-prefix=CHECK +; RUN: FileCheck %s -check-prefixes=STATICGP,CHECK @t1 = thread_local global i32 0, align 4 diff --git a/test/CodeGen/Mips/unalignedload.ll b/test/CodeGen/Mips/unalignedload.ll index 9e453a6e794b..ba476b6c4554 100644 --- a/test/CodeGen/Mips/unalignedload.ll +++ b/test/CodeGen/Mips/unalignedload.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32-EL -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32-EB -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EL -check-prefix=MIPS32R6-EL -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=ALL-EB -check-prefix=MIPS32R6-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL +; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32R6-EL +; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32R6-EB %struct.S2 = type { %struct.S1, %struct.S1 } %struct.S1 = type { i8, i8 } %struct.S4 = type { [7 x i8] } diff --git a/test/CodeGen/Mips/zeroreg.ll b/test/CodeGen/Mips/zeroreg.ll index 6baf9d4fbff2..c024d04a39b0 100644 --- a/test/CodeGen/Mips/zeroreg.ll +++ b/test/CodeGen/Mips/zeroreg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV -; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32R6 +; RUN: llc < %s -march=mipsel -mcpu=mips4 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64r2 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64-CMOV +; RUN: llc < %s -march=mipsel -mcpu=mips64r6 -target-abi n64 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,64R6 @g1 = external global i32 diff --git a/test/CodeGen/NVPTX/MachineSink-call.ll b/test/CodeGen/NVPTX/MachineSink-call.ll new file mode 100644 index 000000000000..3a6d43b76aeb --- /dev/null +++ b/test/CodeGen/NVPTX/MachineSink-call.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +target triple = "nvptx64-nvidia-cuda" + +declare void @foo() + +; Load a value, then call a function. Branch, and use the loaded value only on +; one side of the branch. The load shouldn't be sunk beneath the call, because +; the call may modify memory. +define i32 @f(i32 %x, i32* %ptr, i1 %cond) { +Start: + ; CHECK: ld.u32 + %ptr_val = load i32, i32* %ptr + ; CHECK: call.uni + call void @foo() + br i1 %cond, label %L1, label %L2 +L1: + %ptr_val2 = add i32 %ptr_val, 100 + br label %L2 +L2: + %v4 = phi i32 [ %x, %Start ], [ %ptr_val2, %L1 ] + %v5 = add i32 %v4, 1000 + ret i32 %v5 +} diff --git a/test/CodeGen/NVPTX/MachineSink-convergent.ll b/test/CodeGen/NVPTX/MachineSink-convergent.ll new file mode 100644 index 000000000000..91c80182e2f8 --- /dev/null +++ b/test/CodeGen/NVPTX/MachineSink-convergent.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +target triple = "nvptx64-nvidia-cuda" + +declare void @llvm.nvvm.barrier0() + +; Load a value, then syncthreads. Branch, and use the loaded value only on one +; side of the branch. The load shouldn't be sunk beneath the call, because +; syncthreads is modeled as maystore. +define i32 @f(i32 %x, i32* %ptr, i1 %cond) { +Start: + ; CHECK: ld.u32 + %ptr_val = load i32, i32* %ptr + ; CHECK: bar.sync + call void @llvm.nvvm.barrier0() + br i1 %cond, label %L1, label %L2 +L1: + %ptr_val2 = add i32 %ptr_val, 100 + br label %L2 +L2: + %v4 = phi i32 [ %x, %Start ], [ %ptr_val2, %L1 ] + %v5 = add i32 %v4, 1000 + ret i32 %v5 +} diff --git a/test/CodeGen/NVPTX/TailDuplication-convergent.ll b/test/CodeGen/NVPTX/TailDuplication-convergent.ll new file mode 100644 index 000000000000..fc6867eca417 --- /dev/null +++ b/test/CodeGen/NVPTX/TailDuplication-convergent.ll @@ -0,0 +1,45 @@ +; RUN: llc -O2 -tail-dup-size=100 -enable-tail-merge=0 < %s | FileCheck %s +target triple = "nvptx64-nvidia-cuda" + +declare void @foo() +declare void @llvm.nvvm.barrier0() + +; syncthreads shouldn't be duplicated. +; CHECK: .func call_syncthreads +; CHECK: bar.sync +; CHECK-NOT: bar.sync +define void @call_syncthreads(i32* %a, i32* %b, i1 %cond, i1 %cond2) nounwind { + br i1 %cond, label %L1, label %L2 + br i1 %cond2, label %Ret, label %L1 +Ret: + ret void +L1: + store i32 0, i32* %a + br label %L42 +L2: + store i32 1, i32* %a + br label %L42 +L42: + call void @llvm.nvvm.barrier0() + br label %Ret +} + +; Check that call_syncthreads really does trigger tail duplication. +; CHECK: .func call_foo +; CHECK: call +; CHECK: call +define void @call_foo(i32* %a, i32* %b, i1 %cond, i1 %cond2) nounwind { + br i1 %cond, label %L1, label %L2 + br i1 %cond2, label %Ret, label %L1 +Ret: + ret void +L1: + store i32 0, i32* %a + br label %L42 +L2: + store i32 1, i32* %a + br label %L42 +L42: + call void @foo() + br label %Ret +} diff --git a/test/CodeGen/NVPTX/access-non-generic.ll b/test/CodeGen/NVPTX/access-non-generic.ll index c1327274a9cf..3cd5a9225087 100644 --- a/test/CodeGen/NVPTX/access-non-generic.ll +++ b/test/CodeGen/NVPTX/access-non-generic.ll @@ -1,9 +1,18 @@ ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix PTX ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix PTX +; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -nvptx-use-infer-addrspace | FileCheck %s --check-prefix PTX ; RUN: opt < %s -S -nvptx-favor-non-generic -dce | FileCheck %s --check-prefix IR +; RUN: opt < %s -S -nvptx-infer-addrspace | FileCheck %s --check-prefix IR --check-prefix IR-WITH-LOOP @array = internal addrspace(3) global [10 x float] zeroinitializer, align 4 @scalar = internal addrspace(3) global float 0.000000e+00, align 4 +@generic_scalar = internal global float 0.000000e+00, align 4 + +define float @ld_from_shared() { + %1 = addrspacecast float* @generic_scalar to float addrspace(3)* + %2 = load float, float addrspace(3)* %1 + ret float %2 +} ; Verifies nvptx-favor-non-generic correctly optimizes generic address space ; usage to non-generic address space usage for the patterns we claim to handle: @@ -13,65 +22,66 @@ ; 4. store gep cast ; gep and cast can be an instruction or a constant expression. This function ; tries all possible combinations. -define float @ld_st_shared_f32(i32 %i, float %v) { +define void @ld_st_shared_f32(i32 %i, float %v) { ; IR-LABEL: @ld_st_shared_f32 ; IR-NOT: addrspacecast ; PTX-LABEL: ld_st_shared_f32( ; load cast %1 = load float, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4 + call void @use(float %1) ; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar]; ; store cast store float %v, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4 ; PTX: st.shared.f32 [scalar], %f{{[0-9]+}}; ; use syncthreads to disable optimizations across components - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() ; PTX: bar.sync 0; ; cast; load %2 = addrspacecast float addrspace(3)* @scalar to float* %3 = load float, float* %2, align 4 + call void @use(float %3) ; PTX: ld.shared.f32 %f{{[0-9]+}}, [scalar]; ; cast; store store float %v, float* %2, align 4 ; PTX: st.shared.f32 [scalar], %f{{[0-9]+}}; - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() ; PTX: bar.sync 0; ; load gep cast %4 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4 + call void @use(float %4) ; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20]; ; store gep cast store float %v, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4 ; PTX: st.shared.f32 [array+20], %f{{[0-9]+}}; - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() ; PTX: bar.sync 0; ; gep cast; load %5 = getelementptr inbounds [10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5 %6 = load float, float* %5, align 4 + call void @use(float %6) ; PTX: ld.shared.f32 %f{{[0-9]+}}, [array+20]; ; gep cast; store store float %v, float* %5, align 4 ; PTX: st.shared.f32 [array+20], %f{{[0-9]+}}; - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() ; PTX: bar.sync 0; ; cast; gep; load %7 = addrspacecast [10 x float] addrspace(3)* @array to [10 x float]* %8 = getelementptr inbounds [10 x float], [10 x float]* %7, i32 0, i32 %i %9 = load float, float* %8, align 4 + call void @use(float %9) ; PTX: ld.shared.f32 %f{{[0-9]+}}, [%{{(r|rl|rd)[0-9]+}}]; ; cast; gep; store store float %v, float* %8, align 4 ; PTX: st.shared.f32 [%{{(r|rl|rd)[0-9]+}}], %f{{[0-9]+}}; - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() ; PTX: bar.sync 0; - %sum2 = fadd float %1, %3 - %sum3 = fadd float %sum2, %4 - %sum4 = fadd float %sum3, %6 - %sum5 = fadd float %sum4, %9 - ret float %sum5 + ret void } ; When hoisting an addrspacecast between different pointer types, replace the @@ -117,13 +127,62 @@ define void @rauw(float addrspace(1)* %input) { store float %v, float* %addr ret void ; IR-LABEL: @rauw( -; IR-NEXT: %1 = getelementptr float, float addrspace(1)* %input, i64 10 -; IR-NEXT: %v = load float, float addrspace(1)* %1 -; IR-NEXT: store float %v, float addrspace(1)* %1 +; IR-NEXT: %addr = getelementptr float, float addrspace(1)* %input, i64 10 +; IR-NEXT: %v = load float, float addrspace(1)* %addr +; IR-NEXT: store float %v, float addrspace(1)* %addr ; IR-NEXT: ret void } -declare void @llvm.cuda.syncthreads() #3 +define void @loop() { +; IR-WITH-LOOP-LABEL: @loop( +entry: + %p = addrspacecast [10 x float] addrspace(3)* @array to float* + %end = getelementptr float, float* %p, i64 10 + br label %loop -attributes #3 = { noduplicate nounwind } +loop: + %i = phi float* [ %p, %entry ], [ %i2, %loop ] +; IR-WITH-LOOP: phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ] + %v = load float, float* %i +; IR-WITH-LOOP: %v = load float, float addrspace(3)* %i + call void @use(float %v) + %i2 = getelementptr float, float* %i, i64 1 +; IR-WITH-LOOP: %i2 = getelementptr float, float addrspace(3)* %i, i64 1 + %exit_cond = icmp eq float* %i2, %end + br i1 %exit_cond, label %exit, label %loop + +exit: + ret void +} + +@generic_end = external global float* +define void @loop_with_generic_bound() { +; IR-WITH-LOOP-LABEL: @loop_with_generic_bound( +entry: + %p = addrspacecast [10 x float] addrspace(3)* @array to float* + %end = load float*, float** @generic_end + br label %loop + +loop: + %i = phi float* [ %p, %entry ], [ %i2, %loop ] +; IR-WITH-LOOP: phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ] + %v = load float, float* %i +; IR-WITH-LOOP: %v = load float, float addrspace(3)* %i + call void @use(float %v) + %i2 = getelementptr float, float* %i, i64 1 +; IR-WITH-LOOP: %i2 = getelementptr float, float addrspace(3)* %i, i64 1 + %exit_cond = icmp eq float* %i2, %end +; IR-WITH-LOOP: addrspacecast float addrspace(3)* %i2 to float* +; IR-WITH-LOOP: icmp eq float* %{{[0-9]+}}, %end + br i1 %exit_cond, label %exit, label %loop + +exit: + ret void +} + +declare void @llvm.nvvm.barrier0() #3 + +declare void @use(float) + +attributes #3 = { noduplicate nounwind } diff --git a/test/CodeGen/NVPTX/alias.ll b/test/CodeGen/NVPTX/alias.ll new file mode 100644 index 000000000000..a27851927696 --- /dev/null +++ b/test/CodeGen/NVPTX/alias.ll @@ -0,0 +1,7 @@ +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s + +; Check that llc dies gracefully when given an alias. + +define i32 @a() { ret i32 0 } +; CHECK: ERROR: Module has aliases +@b = internal alias i32 (), i32 ()* @a diff --git a/test/CodeGen/NVPTX/arithmetic-int.ll b/test/CodeGen/NVPTX/arithmetic-int.ll index b5a2872299b7..e7c968c4c0bf 100644 --- a/test/CodeGen/NVPTX/arithmetic-int.ll +++ b/test/CodeGen/NVPTX/arithmetic-int.ll @@ -29,6 +29,30 @@ define i64 @mul_i64(i64 %a, i64 %b) { ret i64 %ret } +define i64 @umul_lohi_i64(i64 %a) { +; CHECK-LABEL: umul_lohi_i64( +entry: + %0 = zext i64 %a to i128 + %1 = mul i128 %0, 288 +; CHECK: mul.lo.{{u|s}}64 +; CHECK: mul.hi.{{u|s}}64 + %2 = lshr i128 %1, 1 + %3 = trunc i128 %2 to i64 + ret i64 %3 +} + +define i64 @smul_lohi_i64(i64 %a) { +; CHECK-LABEL: smul_lohi_i64( +entry: + %0 = sext i64 %a to i128 + %1 = mul i128 %0, 288 +; CHECK: mul.lo.{{u|s}}64 +; CHECK: mul.hi.{{u|s}}64 + %2 = ashr i128 %1, 1 + %3 = trunc i128 %2 to i64 + ret i64 %3 +} + define i64 @sdiv_i64(i64 %a, i64 %b) { ; CHECK: div.s64 %rd{{[0-9]+}}, %rd{{[0-9]+}}, %rd{{[0-9]+}} ; CHECK: ret diff --git a/test/CodeGen/NVPTX/bug22322.ll b/test/CodeGen/NVPTX/bug22322.ll index 97863b9ea546..e073e361445b 100644 --- a/test/CodeGen/NVPTX/bug22322.ll +++ b/test/CodeGen/NVPTX/bug22322.ll @@ -10,10 +10,10 @@ target triple = "nvptx64-nvidia-cuda" define void @some_kernel(%class.float3* nocapture %dst) #0 { _ZL11compute_vecRK6float3jb.exit: %ret_vec.sroa.8.i = alloca float, align 4 - %0 = tail call i32 @llvm.ptx.read.ctaid.x() - %1 = tail call i32 @llvm.ptx.read.ntid.x() + %0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() + %1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() %2 = mul nsw i32 %1, %0 - %3 = tail call i32 @llvm.ptx.read.tid.x() + %3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() %4 = add nsw i32 %2, %3 %5 = zext i32 %4 to i64 %6 = bitcast float* %ret_vec.sroa.8.i to i8* @@ -37,13 +37,13 @@ _ZL11compute_vecRK6float3jb.exit: } ; Function Attrs: nounwind readnone -declare i32 @llvm.ptx.read.ctaid.x() #1 +declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.ptx.read.ntid.x() #1 +declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1 ; Function Attrs: nounwind readnone -declare i32 @llvm.ptx.read.tid.x() #1 +declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1 ; Function Attrs: nounwind declare void @llvm.lifetime.start(i64, i8* nocapture) #2 diff --git a/test/CodeGen/NVPTX/bug26185-2.ll b/test/CodeGen/NVPTX/bug26185-2.ll new file mode 100644 index 000000000000..55e9dad96c01 --- /dev/null +++ b/test/CodeGen/NVPTX/bug26185-2.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s + +; Verify that we correctly emit code for extending ldg/ldu. We do not expose +; extending variants in the backend, but the ldg/ldu selection code may pick +; extending loads as candidates. We do want to support this, so make sure we +; emit the necessary cvt.* instructions to implement the extension and let ptxas +; emit the real extending loads. + +target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" +target triple = "nvptx64-nvidia-cuda" + +; CHECK-LABEL: spam +define ptx_kernel void @spam(i8 addrspace(1)* noalias nocapture readonly %arg, i8 addrspace(1)* noalias nocapture %arg1, i64 %arg2, i64 %arg3) #0 { +bb: + %tmp = bitcast i8 addrspace(1)* %arg to i16 addrspace(1)* + %tmp4 = bitcast i8 addrspace(1)* %arg1 to i64 addrspace(1)* + %tmp5 = add nsw i64 %arg3, 8 + %tmp6 = getelementptr i16, i16 addrspace(1)* %tmp, i64 %tmp5 +; CHECK: ld.global.nc.u16 + %tmp7 = load i16, i16 addrspace(1)* %tmp6, align 2 +; CHECK: cvt.s32.s16 + %tmp8 = sext i16 %tmp7 to i64 + %tmp9 = mul nsw i64 %tmp8, %tmp8 + %tmp10 = load i64, i64 addrspace(1)* %tmp4, align 8 + %tmp11 = add nsw i64 %tmp9, %tmp10 + store i64 %tmp11, i64 addrspace(1)* %tmp4, align 8 + ret void +} + +attributes #0 = { norecurse nounwind "polly.skip.fn" } + +!nvvm.annotations = !{!0} + +!0 = !{void (i8 addrspace(1)*, i8 addrspace(1)*, i64, i64)* @spam, !"maxntidx", i64 1, !"maxntidy", i64 1, !"maxntidz", i64 1} diff --git a/test/CodeGen/NVPTX/bug26185.ll b/test/CodeGen/NVPTX/bug26185.ll new file mode 100644 index 000000000000..30313481deb0 --- /dev/null +++ b/test/CodeGen/NVPTX/bug26185.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s + +; Verify that we correctly emit code for i8 ldg/ldu. We do not expose 8-bit +; registers in the backend, so these loads need special handling. + +target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64" +target triple = "nvptx64-unknown-unknown" + +; CHECK-LABEL: ex_zext +define void @ex_zext(i8* noalias readonly %data, i32* %res) { +entry: +; CHECK: ld.global.nc.u8 + %val = load i8, i8* %data +; CHECK: cvt.u32.u8 + %valext = zext i8 %val to i32 + store i32 %valext, i32* %res + ret void +} + +; CHECK-LABEL: ex_sext +define void @ex_sext(i8* noalias readonly %data, i32* %res) { +entry: +; CHECK: ld.global.nc.u8 + %val = load i8, i8* %data +; CHECK: cvt.s32.s8 + %valext = sext i8 %val to i32 + store i32 %valext, i32* %res + ret void +} + +; CHECK-LABEL: ex_zext_v2 +define void @ex_zext_v2(<2 x i8>* noalias readonly %data, <2 x i32>* %res) { +entry: +; CHECK: ld.global.nc.v2.u8 + %val = load <2 x i8>, <2 x i8>* %data +; CHECK: cvt.u32.u16 + %valext = zext <2 x i8> %val to <2 x i32> + store <2 x i32> %valext, <2 x i32>* %res + ret void +} + +; CHECK-LABEL: ex_sext_v2 +define void @ex_sext_v2(<2 x i8>* noalias readonly %data, <2 x i32>* %res) { +entry: +; CHECK: ld.global.nc.v2.u8 + %val = load <2 x i8>, <2 x i8>* %data +; CHECK: cvt.s32.s8 + %valext = sext <2 x i8> %val to <2 x i32> + store <2 x i32> %valext, <2 x i32>* %res + ret void +} + +!nvvm.annotations = !{!0,!1,!2,!3} +!0 = !{void (i8*, i32*)* @ex_zext, !"kernel", i32 1} +!1 = !{void (i8*, i32*)* @ex_sext, !"kernel", i32 1} +!2 = !{void (<2 x i8>*, <2 x i32>*)* @ex_zext_v2, !"kernel", i32 1} +!3 = !{void (<2 x i8>*, <2 x i32>*)* @ex_sext_v2, !"kernel", i32 1} diff --git a/test/CodeGen/NVPTX/convergent-mir-call.ll b/test/CodeGen/NVPTX/convergent-mir-call.ll new file mode 100644 index 000000000000..18142450490c --- /dev/null +++ b/test/CodeGen/NVPTX/convergent-mir-call.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple nvptx64-nvidia-cuda -stop-after machine-cp -o - < %s 2>&1 | FileCheck %s + +; Check that convergent calls are emitted using convergent MIR instructions, +; while non-convergent calls are not. + +target triple = "nvptx64-nvidia-cuda" + +declare void @conv() convergent +declare void @not_conv() + +define void @test(void ()* %f) { + ; CHECK: ConvergentCallUniPrintCall + ; CHECK-NEXT: @conv + call void @conv() + + ; CHECK: CallUniPrintCall + ; CHECK-NEXT: @not_conv + call void @not_conv() + + ; CHECK: ConvergentCallPrintCall + call void %f() convergent + + ; CHECK: CallPrintCall + call void %f() + + ret void +} diff --git a/test/CodeGen/NVPTX/debug-file-loc.ll b/test/CodeGen/NVPTX/debug-file-loc.ll new file mode 100644 index 000000000000..008e9ce54583 --- /dev/null +++ b/test/CodeGen/NVPTX/debug-file-loc.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda | FileCheck %s + +; // Bitcode int this test case is reduced version of compiled code below: +;extern "C" { +;#line 1 "/source/dir/foo.h" +;__device__ void foo() {} +;#line 2 "/source/dir/bar.cu" +;__device__ void bar() {} +;} + +; CHECK: .file 1 "/source/dir{{/|\\\\}}bar.cu" +; CHECK: .file 2 "/source/dir{{/|\\\\}}foo.h" + +; CHECK-LABEL: @foo +define void @foo() !dbg !4 { +bb: + ret void, !dbg !10 +} +; CHECK: .loc 2 1 +; CHECK: ret + +; CHECK-LABEL: @bar +define void @bar() !dbg !7 { +bb: + ret void, !dbg !11 +} +; CHECK: .loc 1 2 +; CHECK: ret + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!8, !9} + +!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2) +!1 = !DIFile(filename: "bar.cu", directory: "/source/dir") +!2 = !{} +!4 = distinct !DISubprogram(name: "foo", scope: !5, file: !5, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!5 = !DIFile(filename: "foo.h", directory: "/source/dir") +!6 = !DISubroutineType(types: !2) +!7 = distinct !DISubprogram(name: "bar", scope: !1, file: !1, line: 2, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) +!8 = !{i32 2, !"Dwarf Version", i32 4} +!9 = !{i32 2, !"Debug Info Version", i32 3} +!10 = !DILocation(line: 1, column: 31, scope: !4) +!11 = !DILocation(line: 2, column: 31, scope: !7) diff --git a/test/CodeGen/NVPTX/disable-opt.ll b/test/CodeGen/NVPTX/disable-opt.ll new file mode 100644 index 000000000000..15e4913c1695 --- /dev/null +++ b/test/CodeGen/NVPTX/disable-opt.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 -O0 | FileCheck %s + +define void @foo(i32* %output) { +; CHECK-LABEL: .visible .func foo( +entry: + %local = alloca i32 +; CHECK: __local_depot + store i32 1, i32* %local + %0 = load i32, i32* %local + store i32 %0, i32* %output + ret void +} diff --git a/test/CodeGen/NVPTX/global-ctor-empty.ll b/test/CodeGen/NVPTX/global-ctor-empty.ll new file mode 100644 index 000000000000..10ca0168b30c --- /dev/null +++ b/test/CodeGen/NVPTX/global-ctor-empty.ll @@ -0,0 +1,5 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 2>&1 + +; Check that llc doesn't die when given an empty global ctor / dtor. +@llvm.global_ctors = appending global [0 x { i32, void ()*, i8* }] [] +@llvm.global_dtors = appending global [0 x { i32, void ()*, i8* }] [] diff --git a/test/CodeGen/NVPTX/global-ctor.ll b/test/CodeGen/NVPTX/global-ctor.ll new file mode 100644 index 000000000000..89155db08ea5 --- /dev/null +++ b/test/CodeGen/NVPTX/global-ctor.ll @@ -0,0 +1,9 @@ +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s + +; Check that llc dies when given a nonempty global ctor. +@llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] + +; CHECK: ERROR: Module has a nontrivial global ctor +define internal void @foo() { + ret void +} diff --git a/test/CodeGen/NVPTX/global-dtor.ll b/test/CodeGen/NVPTX/global-dtor.ll new file mode 100644 index 000000000000..9d01f9bd387c --- /dev/null +++ b/test/CodeGen/NVPTX/global-dtor.ll @@ -0,0 +1,9 @@ +; RUN: not llc < %s -march=nvptx -mcpu=sm_20 2>&1 | FileCheck %s + +; Check that llc dies when given a nonempty global dtor. +@llvm.global_dtors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 65535, void ()* @foo, i8* null }] + +; CHECK: ERROR: Module has a nontrivial global dtor +define internal void @foo() { + ret void +} diff --git a/test/CodeGen/NVPTX/global-visibility.ll b/test/CodeGen/NVPTX/global-visibility.ll new file mode 100644 index 000000000000..90af2950fb40 --- /dev/null +++ b/test/CodeGen/NVPTX/global-visibility.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s + +; PTX does not support .hidden or .protected. +; Make sure we do not emit them. + +define hidden void @f_hidden() { + ret void +} +; CHECK-NOT: .hidden +; CHECK: .visible .func f_hidden + +define protected void @f_protected() { + ret void +} +; CHECK-NOT: .protected +; CHECK: .visible .func f_protected diff --git a/test/CodeGen/NVPTX/intrinsic-old.ll b/test/CodeGen/NVPTX/intrinsic-old.ll index 3c51776c0ec9..daf83a870075 100644 --- a/test/CodeGen/NVPTX/intrinsic-old.ll +++ b/test/CodeGen/NVPTX/intrinsic-old.ll @@ -1,282 +1,323 @@ ; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s ; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s +; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -nvvm-intr-range \ +; RUN: | FileCheck --check-prefix=RANGE --check-prefix=RANGE_20 %s +; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda \ +; RUN: -nvvm-intr-range -nvvm-intr-range-sm=30 \ +; RUN: | FileCheck --check-prefix=RANGE --check-prefix=RANGE_30 %s define ptx_device i32 @test_tid_x() { ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.x; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range ![[BLK_IDX_XY:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.tid.x() + %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() ret i32 %x } define ptx_device i32 @test_tid_y() { ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.y; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.y(), !range ![[BLK_IDX_XY]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.tid.y() + %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y() ret i32 %x } define ptx_device i32 @test_tid_z() { ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.z; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.tid.z(), !range ![[BLK_IDX_Z:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.tid.z() + %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z() ret i32 %x } define ptx_device i32 @test_tid_w() { ; CHECK: mov.u32 %r{{[0-9]+}}, %tid.w; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.tid.w() + %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w() ret i32 %x } define ptx_device i32 @test_ntid_x() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.x; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !range ![[BLK_SIZE_XY:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ntid.x() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x() ret i32 %x } define ptx_device i32 @test_ntid_y() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.y; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.y(), !range ![[BLK_SIZE_XY]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ntid.y() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.y() ret i32 %x } define ptx_device i32 @test_ntid_z() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.z; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ntid.z(), !range ![[BLK_SIZE_Z:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ntid.z() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.z() ret i32 %x } define ptx_device i32 @test_ntid_w() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ntid.w; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ntid.w() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ntid.w() ret i32 %x } define ptx_device i32 @test_laneid() { ; CHECK: mov.u32 %r{{[0-9]+}}, %laneid; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.laneid(), !range ![[LANEID:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.laneid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.laneid() ret i32 %x } -define ptx_device i32 @test_warpid() { -; CHECK: mov.u32 %r{{[0-9]+}}, %warpid; +define ptx_device i32 @test_warpsize() { +; CHECK: mov.u32 %r{{[0-9]+}}, WARP_SZ; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.warpsize(), !range ![[WARPSIZE:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.warpid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.warpsize() ret i32 %x } -define ptx_device i32 @test_nwarpid() { -; CHECK: mov.u32 %r{{[0-9]+}}, %nwarpid; +define ptx_device i32 @test_warpid() { +; CHECK: mov.u32 %r{{[0-9]+}}, %warpid; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nwarpid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.warpid() ret i32 %x } -define ptx_device i32 @test_ctaid_x() { -; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.x; +define ptx_device i32 @test_nwarpid() { +; CHECK: mov.u32 %r{{[0-9]+}}, %nwarpid; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ctaid.x() + %x = call i32 @llvm.nvvm.read.ptx.sreg.nwarpid() ret i32 %x } define ptx_device i32 @test_ctaid_y() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.y; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y(), !range ![[GRID_IDX_YZ:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ctaid.y() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.y() ret i32 %x } define ptx_device i32 @test_ctaid_z() { ; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.z; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z(), !range ![[GRID_IDX_YZ]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ctaid.z() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.z() ret i32 %x } -define ptx_device i32 @test_ctaid_w() { -; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.w; +define ptx_device i32 @test_ctaid_x() { +; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.x; +; RANGE_30: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !range ![[GRID_IDX_X:[0-9]+]] +; RANGE_20: call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x(), !range ![[GRID_IDX_YZ]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.ctaid.w() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() ret i32 %x } -define ptx_device i32 @test_nctaid_x() { -; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.x; +define ptx_device i32 @test_ctaid_w() { +; CHECK: mov.u32 %r{{[0-9]+}}, %ctaid.w; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nctaid.x() + %x = call i32 @llvm.nvvm.read.ptx.sreg.ctaid.w() ret i32 %x } define ptx_device i32 @test_nctaid_y() { ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.y; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y(), !range ![[GRID_SIZE_YZ:[0-9]+]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nctaid.y() + %x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.y() ret i32 %x } define ptx_device i32 @test_nctaid_z() { ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.z; +; RANGE: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z(), !range ![[GRID_SIZE_YZ]] +; CHECK: ret; + %x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.z() + ret i32 %x +} + +define ptx_device i32 @test_nctaid_x() { +; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.x; +; RANGE_30: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x(), !range ![[GRID_SIZE_X:[0-9]+]] +; RANGE_20: call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x(), !range ![[GRID_SIZE_YZ]] ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nctaid.z() + %x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.x() ret i32 %x } + define ptx_device i32 @test_nctaid_w() { ; CHECK: mov.u32 %r{{[0-9]+}}, %nctaid.w; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nctaid.w() + %x = call i32 @llvm.nvvm.read.ptx.sreg.nctaid.w() ret i32 %x } define ptx_device i32 @test_smid() { ; CHECK: mov.u32 %r{{[0-9]+}}, %smid; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.smid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.smid() ret i32 %x } define ptx_device i32 @test_nsmid() { ; CHECK: mov.u32 %r{{[0-9]+}}, %nsmid; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.nsmid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.nsmid() ret i32 %x } define ptx_device i32 @test_gridid() { ; CHECK: mov.u32 %r{{[0-9]+}}, %gridid; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.gridid() + %x = call i32 @llvm.nvvm.read.ptx.sreg.gridid() ret i32 %x } define ptx_device i32 @test_lanemask_eq() { ; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_eq; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.lanemask.eq() + %x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq() ret i32 %x } define ptx_device i32 @test_lanemask_le() { ; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_le; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.lanemask.le() + %x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.le() ret i32 %x } define ptx_device i32 @test_lanemask_lt() { ; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_lt; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.lanemask.lt() + %x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt() ret i32 %x } define ptx_device i32 @test_lanemask_ge() { ; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_ge; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.lanemask.ge() + %x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge() ret i32 %x } define ptx_device i32 @test_lanemask_gt() { ; CHECK: mov.u32 %r{{[0-9]+}}, %lanemask_gt; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.lanemask.gt() + %x = call i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt() ret i32 %x } define ptx_device i32 @test_clock() { ; CHECK: mov.u32 %r{{[0-9]+}}, %clock; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.clock() + %x = call i32 @llvm.nvvm.read.ptx.sreg.clock() ret i32 %x } define ptx_device i64 @test_clock64() { ; CHECK: mov.u64 %rd{{[0-9]+}}, %clock64; ; CHECK: ret; - %x = call i64 @llvm.ptx.read.clock64() + %x = call i64 @llvm.nvvm.read.ptx.sreg.clock64() ret i64 %x } define ptx_device i32 @test_pm0() { ; CHECK: mov.u32 %r{{[0-9]+}}, %pm0; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.pm0() + %x = call i32 @llvm.nvvm.read.ptx.sreg.pm0() ret i32 %x } define ptx_device i32 @test_pm1() { ; CHECK: mov.u32 %r{{[0-9]+}}, %pm1; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.pm1() + %x = call i32 @llvm.nvvm.read.ptx.sreg.pm1() ret i32 %x } define ptx_device i32 @test_pm2() { ; CHECK: mov.u32 %r{{[0-9]+}}, %pm2; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.pm2() + %x = call i32 @llvm.nvvm.read.ptx.sreg.pm2() ret i32 %x } define ptx_device i32 @test_pm3() { ; CHECK: mov.u32 %r{{[0-9]+}}, %pm3; ; CHECK: ret; - %x = call i32 @llvm.ptx.read.pm3() + %x = call i32 @llvm.nvvm.read.ptx.sreg.pm3() ret i32 %x } define ptx_device void @test_bar_sync() { ; CHECK: bar.sync 0 ; CHECK: ret; - call void @llvm.ptx.bar.sync(i32 0) + call void @llvm.nvvm.bar.sync(i32 0) ret void } -declare i32 @llvm.ptx.read.tid.x() -declare i32 @llvm.ptx.read.tid.y() -declare i32 @llvm.ptx.read.tid.z() -declare i32 @llvm.ptx.read.tid.w() -declare i32 @llvm.ptx.read.ntid.x() -declare i32 @llvm.ptx.read.ntid.y() -declare i32 @llvm.ptx.read.ntid.z() -declare i32 @llvm.ptx.read.ntid.w() - -declare i32 @llvm.ptx.read.laneid() -declare i32 @llvm.ptx.read.warpid() -declare i32 @llvm.ptx.read.nwarpid() - -declare i32 @llvm.ptx.read.ctaid.x() -declare i32 @llvm.ptx.read.ctaid.y() -declare i32 @llvm.ptx.read.ctaid.z() -declare i32 @llvm.ptx.read.ctaid.w() -declare i32 @llvm.ptx.read.nctaid.x() -declare i32 @llvm.ptx.read.nctaid.y() -declare i32 @llvm.ptx.read.nctaid.z() -declare i32 @llvm.ptx.read.nctaid.w() - -declare i32 @llvm.ptx.read.smid() -declare i32 @llvm.ptx.read.nsmid() -declare i32 @llvm.ptx.read.gridid() - -declare i32 @llvm.ptx.read.lanemask.eq() -declare i32 @llvm.ptx.read.lanemask.le() -declare i32 @llvm.ptx.read.lanemask.lt() -declare i32 @llvm.ptx.read.lanemask.ge() -declare i32 @llvm.ptx.read.lanemask.gt() - -declare i32 @llvm.ptx.read.clock() -declare i64 @llvm.ptx.read.clock64() - -declare i32 @llvm.ptx.read.pm0() -declare i32 @llvm.ptx.read.pm1() -declare i32 @llvm.ptx.read.pm2() -declare i32 @llvm.ptx.read.pm3() - -declare void @llvm.ptx.bar.sync(i32 %i) +declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() +declare i32 @llvm.nvvm.read.ptx.sreg.tid.y() +declare i32 @llvm.nvvm.read.ptx.sreg.tid.z() +declare i32 @llvm.nvvm.read.ptx.sreg.tid.w() +declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() +declare i32 @llvm.nvvm.read.ptx.sreg.ntid.y() +declare i32 @llvm.nvvm.read.ptx.sreg.ntid.z() +declare i32 @llvm.nvvm.read.ptx.sreg.ntid.w() + +declare i32 @llvm.nvvm.read.ptx.sreg.warpsize() +declare i32 @llvm.nvvm.read.ptx.sreg.laneid() +declare i32 @llvm.nvvm.read.ptx.sreg.warpid() +declare i32 @llvm.nvvm.read.ptx.sreg.nwarpid() + +declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() +declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.y() +declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.z() +declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.w() +declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.x() +declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.y() +declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.z() +declare i32 @llvm.nvvm.read.ptx.sreg.nctaid.w() + +declare i32 @llvm.nvvm.read.ptx.sreg.smid() +declare i32 @llvm.nvvm.read.ptx.sreg.nsmid() +declare i32 @llvm.nvvm.read.ptx.sreg.gridid() + +declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.eq() +declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.le() +declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.lt() +declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.ge() +declare i32 @llvm.nvvm.read.ptx.sreg.lanemask.gt() + +declare i32 @llvm.nvvm.read.ptx.sreg.clock() +declare i64 @llvm.nvvm.read.ptx.sreg.clock64() + +declare i32 @llvm.nvvm.read.ptx.sreg.pm0() +declare i32 @llvm.nvvm.read.ptx.sreg.pm1() +declare i32 @llvm.nvvm.read.ptx.sreg.pm2() +declare i32 @llvm.nvvm.read.ptx.sreg.pm3() + +declare void @llvm.nvvm.bar.sync(i32 %i) + +; RANGE-DAG: ![[BLK_IDX_XY]] = !{i32 0, i32 1024} +; RANGE-DAG: ![[BLK_IDX_Z]] = !{i32 0, i32 64} +; RANGE-DAG: ![[BLK_SIZE_XY]] = !{i32 1, i32 1025} +; RANGE-DAG: ![[BLK_SIZE_Z]] = !{i32 1, i32 65} +; RANGE-DAG: ![[LANEID]] = !{i32 0, i32 32} +; RANGE-DAG: ![[WARPSIZE]] = !{i32 32, i32 33} +; RANGE_30-DAG: ![[GRID_IDX_X]] = !{i32 0, i32 2147483647} +; RANGE-DAG: ![[GRID_IDX_YZ]] = !{i32 0, i32 65535} +; RANGE_30-DAG: ![[GRID_SIZE_X]] = !{i32 1, i32 -2147483648} +; RANGE-DAG: ![[GRID_SIZE_YZ]] = !{i32 1, i32 65536} diff --git a/test/CodeGen/NVPTX/noduplicate-syncthreads.ll b/test/CodeGen/NVPTX/noduplicate-syncthreads.ll index 2fec31b3791d..ca7fb6eddfe8 100644 --- a/test/CodeGen/NVPTX/noduplicate-syncthreads.ll +++ b/test/CodeGen/NVPTX/noduplicate-syncthreads.ll @@ -3,8 +3,8 @@ ; Make sure the call to syncthreads is not duplicate here by the LLVM ; optimizations, because it has the noduplicate attribute set. -; CHECK: call void @llvm.cuda.syncthreads -; CHECK-NOT: call void @llvm.cuda.syncthreads +; CHECK: call void @llvm.nvvm.barrier0 +; CHECK-NOT: call void @llvm.nvvm.barrier0 ; Function Attrs: nounwind define void @foo(float* %output) #1 { @@ -37,7 +37,7 @@ if.else: ; preds = %entry br label %if.end if.end: ; preds = %if.else, %if.then - call void @llvm.cuda.syncthreads() + call void @llvm.nvvm.barrier0() %6 = load float*, float** %output.addr, align 8 %arrayidx6 = getelementptr inbounds float, float* %6, i64 0 %7 = load float, float* %arrayidx6, align 4 @@ -68,7 +68,7 @@ if.end17: ; preds = %if.else13, %if.then } ; Function Attrs: noduplicate nounwind -declare void @llvm.cuda.syncthreads() #2 +declare void @llvm.nvvm.barrier0() #2 !0 = !{void (float*)* @foo, !"kernel", i32 1} !1 = !{null, !"align", i32 8} diff --git a/test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll b/test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll new file mode 100644 index 000000000000..4fdab5c087de --- /dev/null +++ b/test/CodeGen/NVPTX/nvvm-reflect-module-flag.ll @@ -0,0 +1,13 @@ +; RUN: opt < %s -S -nvvm-reflect | FileCheck %s + +declare i32 @__nvvm_reflect(i8*) +@str = private unnamed_addr addrspace(1) constant [11 x i8] c"__CUDA_FTZ\00" + +define i32 @foo() { + %call = call i32 @__nvvm_reflect(i8* addrspacecast (i8 addrspace(1)* getelementptr inbounds ([11 x i8], [11 x i8] addrspace(1)* @str, i32 0, i32 0) to i8*)) + ; CHECK: ret i32 42 + ret i32 %call +} + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"nvvm-reflect-ftz", i32 42} diff --git a/test/CodeGen/NVPTX/shfl.ll b/test/CodeGen/NVPTX/shfl.ll new file mode 100644 index 000000000000..e4899f66fb65 --- /dev/null +++ b/test/CodeGen/NVPTX/shfl.ll @@ -0,0 +1,90 @@ +; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 -disable-nvptx-favor-non-generic | FileCheck %s + +declare i32 @llvm.nvvm.shfl.down.i32(i32, i32, i32) +declare float @llvm.nvvm.shfl.down.f32(float, i32, i32) +declare i32 @llvm.nvvm.shfl.up.i32(i32, i32, i32) +declare float @llvm.nvvm.shfl.up.f32(float, i32, i32) +declare i32 @llvm.nvvm.shfl.bfly.i32(i32, i32, i32) +declare float @llvm.nvvm.shfl.bfly.f32(float, i32, i32) +declare i32 @llvm.nvvm.shfl.idx.i32(i32, i32, i32) +declare float @llvm.nvvm.shfl.idx.f32(float, i32, i32) + +; Try all four permutations of register and immediate parameters with +; shfl.down. + +; CHECK-LABEL: .func{{.*}}shfl.down1 +define i32 @shfl.down1(i32 %in) { + ; CHECK: ld.param.u32 [[IN:%r[0-9]+]] + ; CHECK: shfl.down.b32 [[OUT:%r[0-9]+]], [[IN]], 1, 2; + ; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]] + %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 1, i32 2) + ret i32 %val +} + +; CHECK-LABEL: .func{{.*}}shfl.down2 +define i32 @shfl.down2(i32 %in, i32 %width) { + ; CHECK: ld.param.u32 [[IN1:%r[0-9]+]] + ; CHECK: ld.param.u32 [[IN2:%r[0-9]+]] + ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], 3; + %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 3) + ret i32 %val +} + +; CHECK-LABEL: .func{{.*}}shfl.down3 +define i32 @shfl.down3(i32 %in, i32 %mask) { + ; CHECK: ld.param.u32 [[IN1:%r[0-9]+]] + ; CHECK: ld.param.u32 [[IN2:%r[0-9]+]] + ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], 4, [[IN2]]; + %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 4, i32 %mask) + ret i32 %val +} + +; CHECK-LABEL: .func{{.*}}shfl.down4 +define i32 @shfl.down4(i32 %in, i32 %width, i32 %mask) { + ; CHECK: ld.param.u32 [[IN1:%r[0-9]+]] + ; CHECK: ld.param.u32 [[IN2:%r[0-9]+]] + ; CHECK: ld.param.u32 [[IN3:%r[0-9]+]] + ; CHECK: shfl.down.{{.}}32 %r{{[0-9]+}}, [[IN1]], [[IN2]], [[IN3]]; + %val = call i32 @llvm.nvvm.shfl.down.i32(i32 %in, i32 %width, i32 %mask) + ret i32 %val +} + +; Try shfl.down with floating-point params. +; CHECK-LABEL: .func{{.*}}shfl.down.float +define float @shfl.down.float(float %in) { + ; CHECK: ld.param.f32 [[IN:%f[0-9]+]] + ; CHECK: shfl.down.b32 [[OUT:%f[0-9]+]], [[IN]], 5, 6; + ; CHECK: st.param.{{.}}32 {{.*}}, [[OUT]] + %out = call float @llvm.nvvm.shfl.down.f32(float %in, i32 5, i32 6) + ret float %out +} + +; Try the rest of the shfl modes. Hopefully they're declared in such a way +; that if shfl.down works correctly, they also work correctly. +define void @shfl.rest(i32 %in_i32, float %in_float, i32* %out_i32, float* %out_float) { + ; CHECK: shfl.up.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 1, 2; + %up_i32 = call i32 @llvm.nvvm.shfl.up.i32(i32 %in_i32, i32 1, i32 2) + store i32 %up_i32, i32* %out_i32 + + ; CHECK: shfl.up.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 3, 4; + %up_float = call float @llvm.nvvm.shfl.up.f32(float %in_float, i32 3, i32 4) + store float %up_float, float* %out_float + + ; CHECK: shfl.bfly.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 5, 6; + %bfly_i32 = call i32 @llvm.nvvm.shfl.bfly.i32(i32 %in_i32, i32 5, i32 6) + store i32 %bfly_i32, i32* %out_i32 + + ; CHECK: shfl.bfly.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 7, 8; + %bfly_float = call float @llvm.nvvm.shfl.bfly.f32(float %in_float, i32 7, i32 8) + store float %bfly_float, float* %out_float + + ; CHECK: shfl.idx.b32 %r{{[0-9]+}}, %r{{[0-9]+}}, 9, 10; + %idx_i32 = call i32 @llvm.nvvm.shfl.idx.i32(i32 %in_i32, i32 9, i32 10) + store i32 %idx_i32, i32* %out_i32 + + ; CHECK: shfl.idx.b32 %f{{[0-9]+}}, %f{{[0-9]+}}, 11, 12; + %idx_float = call float @llvm.nvvm.shfl.idx.f32(float %in_float, i32 11, i32 12) + store float %idx_float, float* %out_float + + ret void +} diff --git a/test/CodeGen/NVPTX/sm-version-60.ll b/test/CodeGen/NVPTX/sm-version-60.ll new file mode 100644 index 000000000000..4f6b508a70b5 --- /dev/null +++ b/test/CodeGen/NVPTX/sm-version-60.ll @@ -0,0 +1,5 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_60 | FileCheck %s +; RUN: llc < %s -march=nvptx64 -mcpu=sm_60 | FileCheck %s + +; CHECK: .version 5.0 +; CHECK: .target sm_60 diff --git a/test/CodeGen/NVPTX/sm-version-61.ll b/test/CodeGen/NVPTX/sm-version-61.ll new file mode 100644 index 000000000000..535ef066d0c3 --- /dev/null +++ b/test/CodeGen/NVPTX/sm-version-61.ll @@ -0,0 +1,5 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_61 | FileCheck %s +; RUN: llc < %s -march=nvptx64 -mcpu=sm_61 | FileCheck %s + +; CHECK: .version 5.0 +; CHECK: .target sm_61 diff --git a/test/CodeGen/NVPTX/sm-version-62.ll b/test/CodeGen/NVPTX/sm-version-62.ll new file mode 100644 index 000000000000..7d425b6d12e9 --- /dev/null +++ b/test/CodeGen/NVPTX/sm-version-62.ll @@ -0,0 +1,5 @@ +; RUN: llc < %s -march=nvptx -mcpu=sm_62 | FileCheck %s +; RUN: llc < %s -march=nvptx64 -mcpu=sm_62 | FileCheck %s + +; CHECK: .version 5.0 +; CHECK: .target sm_62 diff --git a/test/CodeGen/NVPTX/speculative-execution-divergent-target.ll b/test/CodeGen/NVPTX/speculative-execution-divergent-target.ll new file mode 100644 index 000000000000..128e9e9ba2a3 --- /dev/null +++ b/test/CodeGen/NVPTX/speculative-execution-divergent-target.ll @@ -0,0 +1,24 @@ +; Checks that speculative-execution only runs on divergent targets, if you pass +; -spec-exec-only-if-divergent-target. + +; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -speculative-execution | \ +; RUN: FileCheck --check-prefix=ON %s +; RUN: opt < %s -S -mtriple=nvptx-nvidia-cuda -speculative-execution \ +; RUN: -spec-exec-only-if-divergent-target | \ +; RUN: FileCheck --check-prefix=ON %s +; RUN: opt < %s -S -speculative-execution -spec-exec-only-if-divergent-target | \ +; RUN: FileCheck --check-prefix=OFF %s + +; Hoist in if-then pattern. +define void @f() { +; ON: %x = add i32 2, 3 +; ON: br i1 true +; OFF: br i1 true +; OFF: %x = add i32 2, 3 + br i1 true, label %a, label %b +a: + %x = add i32 2, 3 + br label %b +b: + ret void +} diff --git a/test/CodeGen/NVPTX/zeroext-32bit.ll b/test/CodeGen/NVPTX/zeroext-32bit.ll new file mode 100644 index 000000000000..c2f0ec4b1447 --- /dev/null +++ b/test/CodeGen/NVPTX/zeroext-32bit.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=nvptx64 -mcpu=sm_30 | FileCheck %s + +; The zeroext attribute below should be silently ignored because +; we can pass a 32-bit integer across a function call without +; needing to extend it. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64" +target triple = "nvptx64-unknown-cuda" + +; CHECK-LABEL: .visible .func zeroext_test +; CHECK-NOT: cvt.u32.u16 +define void @zeroext_test() { + tail call void @call1(i32 zeroext 0) + ret void +} + +declare void @call1(i32 zeroext) + +; CHECK-LABEL: .visible .func signext_test +; CHECK-NOT: cvt.s32.s16 +define void @signext_test() { + tail call void @call2(i32 zeroext 0) + ret void +} + +declare void @call2(i32 zeroext) diff --git a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll index aae914ecc435..3be596f9a531 100644 --- a/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll +++ b/test/CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=ppc64 | FileCheck %s +; RUN: llc < %s -march=ppc64 -O1 | FileCheck %s +; RUN: llc < %s -march=ppc64 | FileCheck --check-prefix=CHECK-OPT %s %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] } %struct.__mutex_t = type { i32 } @@ -15,6 +16,24 @@ entry: ; CHECK: @foo ; CHECK: lwzx ; CHECK: blr +; CHECK-OPT: @foo +; CHECK-OPT: lwz +; CHECK-OPT: blr } +define signext i32 @test(i32* noalias nocapture readonly %b, i32 signext %n) { +entry: + %idxprom = sext i32 %n to i64 + %arrayidx = getelementptr inbounds i32, i32* %b, i64 %idxprom + %0 = load i32, i32* %arrayidx, align 4 + %mul = mul nsw i32 %0, 7 + ret i32 %mul + +; CHECK-OPT: @test +; CHECK-OPT: lwzx +; CHECK-OPT: blr + +} + + declare i32 @bork(...) diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll index 01c83cb4bcbe..e1d19a7b246a 100644 --- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -12,7 +12,7 @@ %struct.objc_selector = type opaque %struct.pthread_mutex_t = type { i32, [40 x i8] } %struct.pthread_rwlock_t = type { i32, [124 x i8] } -external constant %struct.__builtin_CFString ; <%struct.__builtin_CFString*>:0 [#uses=1] +@0 = external constant %struct.__builtin_CFString ; <%struct.__builtin_CFString*>:0 [#uses=1] define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber:flags:owner:]"(%struct.PFTPersistentSymbols* %self, %struct.objc_selector* %_cmd, %struct.NSArray* %name, i64 %address, %struct.NSArray* %path, i32 %lineNumber, i64 %flags, %struct..0objc_object* %owner) nounwind { entry: diff --git a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll index b271048fd045..ab1973fa429c 100644 --- a/test/CodeGen/PowerPC/2008-07-15-Bswap.ll +++ b/test/CodeGen/PowerPC/2008-07-15-Bswap.ll @@ -68,8 +68,6 @@ declare void @_Z33LoopFilter_Internal_FilterChromaHPhiiiiii(i8*, i32, i32, i32, declare void @_Z42LoopFilter_Internal_filter_macroblock_lumaPK14LoopFilterInfoPhS2_iiiPK30PerMacroblockBoundaryStrengthsjj(%struct.LoopFilterInfo*, i8*, i8*, i32, i32, i32, %struct.PerMacroblockBoundaryStrengths*, i32, i32) nounwind -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind - declare i32 @_Z40LoopFilter_Internal_FilterLumaPlaneMBAFFPK14LoopFilterInfojjj(%struct.LoopFilterInfo*, i32, i32, i32) nounwind declare void @_Z18LoopFilter_DestroyP14LoopFilterInfo(%struct.LoopFilterInfo*) @@ -86,8 +84,6 @@ declare void @jvtDisposePTRMemAligned(i8*) declare void @_Z31LoopFilter_Internal_ResetTablesP14LoopFilterInfo(%struct.LoopFilterInfo*) nounwind -declare void @llvm.memset.i32(i8*, i8, i32, i32) nounwind - define i32 @_Z60LoopFilter_Internal_CalculateBoundaryStrengths_MbaffFramePicPK14LoopFilterInfoP22FrameMotionVectorCachejj(%struct.LoopFilterInfo* %lfiPtr, %struct.FrameMotionVectorCache* %frameMotionVectorCachePtr, i32 %mbY_min, i32 %mbY_maxPlus1) nounwind { entry: icmp ult i32 %mbY_min, %mbY_maxPlus1 ; :0 [#uses=1] @@ -383,4 +379,3 @@ declare i32 @_Z22LoopFilter_FilterFrameP14LoopFilterInfoP11FramePixelsP22FrameMo declare void @_Z34LF_Threading2_ProcessTasks_WrapperPv(i8*) -declare void @llvm.memset.i64(i8*, i8, i64, i32) nounwind diff --git a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll index 1ba11d3fd036..160b26e9078d 100644 --- a/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll +++ b/test/CodeGen/PowerPC/2010-02-04-EmptyGlobal.ll @@ -6,7 +6,7 @@ @_cmd = constant %cmd.type zeroinitializer ; CHECK: .globl __cmd -; CHECK-NEXT: .align 3 +; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: __cmd: ; CHECK-NEXT: .byte 0 diff --git a/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll index 35e3fdd26e72..dbc521fb8f1f 100644 --- a/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll +++ b/test/CodeGen/PowerPC/2012-11-16-mischedcall.ll @@ -8,10 +8,10 @@ declare void @init() nounwind declare void @clock() nounwind -; CHECK: %entry +; CHECK: mflr 0 ; CHECK: fmr 31, 1 ; CHECK: bl init -define void @s332(double %t) nounwind { +define double @s332(double %t) nounwind { entry: tail call void @init() tail call void @clock() nounwind @@ -29,5 +29,7 @@ for.body4: ; preds = %for.cond2 L20: ; preds = %for.body4, %for.cond2 %index.0 = phi i32 [ -2, %for.cond2 ], [ %i.0, %for.body4 ] - unreachable + %index.d = sitofp i32 %index.0 to double + %retval = fadd double %t, %index.d + ret double %retval } diff --git a/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll b/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll new file mode 100644 index 000000000000..c0b48d30bd48 --- /dev/null +++ b/test/CodeGen/PowerPC/2016-04-16-ADD8TLS.ll @@ -0,0 +1,43 @@ +; RUN: llc <%s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@x = external thread_local global i32, align 4 + +; Function Attrs: nounwind +; CHECK-NOT: add [[REG1:[0-9]+]], 0, x@tls +define void @f() { + %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "={r3},={r4},={r5},={r6},={r7},={r8},={r9},={r10},={r11},={r12},={r14},={r15},={r16},={r17},={r18},={r19},={r20},={r21},={r22},={r23},={r24},={r25},={r26},={r27},={r28},={r29},={r30},~{memory}"() + %2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0 + %3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1 + %4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2 + %5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3 + %6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4 + %7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5 + %8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6 + %9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7 + %10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8 + %11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9 + %12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10 + %13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11 + %14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12 + %15 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13 + %16 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14 + %17 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 15 + %18 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 16 + %19 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 17 + %20 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 18 + %21 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 19 + %22 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 20 + %23 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 21 + %24 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 22 + %25 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 23 + %26 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 24 + %27 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 25 + %28 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 26 + %29 = load i32, i32* @x, align 4 + %30 = add nsw i32 %29, 1 + store i32 %30, i32* @x, align 4 + tail call void asm sideeffect "nop", "{r3},{r4},{r5},{r6},{r7},{r8},{r9},{r10},{r11},{r12},{r14},{r15},{r16},{r17},{r18},{r19},{r20},{r21},{r22},{r23},{r24},{r25},{r26},{r27},{r28},{r29},{r30},~{memory}"(i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7, i32 %8, i32 %9, i32 %10, i32 %11, i32 %12, i32 %13, i32 %14, i32 %15, i32 %16, i32 %17, i32 %18, i32 %19, i32 %20, i32 %21, i32 %22, i32 %23, i32 %24, i32 %25, i32 %26, i32 %27, i32 %28) + ret void +} diff --git a/test/CodeGen/PowerPC/2016-04-17-combine.ll b/test/CodeGen/PowerPC/2016-04-17-combine.ll new file mode 100644 index 000000000000..7ad943cf35fe --- /dev/null +++ b/test/CodeGen/PowerPC/2016-04-17-combine.ll @@ -0,0 +1,26 @@ +; RUN: llc <%s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; PR27390 crasher + +%typ = type { i32, i32 } + +; On release builds, it doesn't crash, spewing nonsense instead. +; To make sure it works, check that and is still alive. +; CHECK: and +; Also, in release, it emits a COPY from a 32-bit register to +; a 64-bit register, which happens to be emitted as cror [!] +; by the confused CodeGen. Just to be sure, check there isn't one. +; CHECK-NOT: cror +; Function Attrs: uwtable +define signext i32 @_Z8access_pP1Tc(%typ* %p, i8 zeroext %type) { + %b = getelementptr inbounds %typ, %typ* %p, i64 0, i32 1 + %1 = load i32, i32* %b, align 4 + %2 = ptrtoint i32* %b to i64 + %3 = and i64 %2, -35184372088833 + %4 = inttoptr i64 %3 to i32* + %_msld = load i32, i32* %4, align 4 + %zzz = add i32 %1, %_msld + ret i32 %zzz +} diff --git a/test/CodeGen/PowerPC/2016-04-28-setjmp.ll b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll new file mode 100644 index 000000000000..09c0fa7ba972 --- /dev/null +++ b/test/CodeGen/PowerPC/2016-04-28-setjmp.ll @@ -0,0 +1,48 @@ +; RUN: llc -filetype=obj <%s | llvm-objdump --disassemble - | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +@ptr = common global i8* null, align 8 + +; Verify there's no junk between these two instructions from misemitted +; EH_SjLj_Setup. + +; CHECK: li 3, 1 +; CHECK-NEXT: b .+4 + +define void @h() nounwind { + %1 = load i8**, i8*** bitcast (i8** @ptr to i8***), align 8 + %2 = tail call i8* @llvm.frameaddress(i32 0) + store i8* %2, i8** %1, align 8 + %3 = tail call i8* @llvm.stacksave() + %4 = getelementptr inbounds i8*, i8** %1, i64 2 + store i8* %3, i8** %4, align 8 + %5 = bitcast i8** %1 to i8* + %6 = tail call i32 @llvm.eh.sjlj.setjmp(i8* %5) + %7 = icmp eq i32 %6, 0 + br i1 %7, label %9, label %8 + +;