From 30815c536baacc07e925f0aef23a5395883173dc Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Thu, 20 Oct 2011 21:10:27 +0000 Subject: Vendor import of llvm release_30 branch r142614: http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614 --- test/CodeGen/ARM/2009-10-16-Scope.ll | 4 +- test/CodeGen/ARM/2010-11-30-reloc-movt.ll | 16 +- test/CodeGen/ARM/2010-12-15-elf-lcomm.ll | 21 +- test/CodeGen/ARM/2011-06-09-TailCallByVal.ll | 1 + test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 124 ++ test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll | 12 + test/CodeGen/ARM/2011-08-25-ldmia_ret.ll | 100 + test/CodeGen/ARM/2011-08-29-SchedCycle.ll | 45 + test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll | 34 + test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll | 23 + test/CodeGen/ARM/2011-09-19-cpsr.ll | 54 + test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll | 30 + test/CodeGen/ARM/atomic-64bit.ll | 128 ++ test/CodeGen/ARM/atomic-cmp.ll | 8 +- test/CodeGen/ARM/atomic-load-store.ll | 56 + test/CodeGen/ARM/atomic-op.ll | 48 +- test/CodeGen/ARM/avoid-cpsr-rmw.ll | 6 +- test/CodeGen/ARM/call-tc.ll | 4 + test/CodeGen/ARM/carry.ll | 10 + test/CodeGen/ARM/crash-greedy-v6.ll | 32 + test/CodeGen/ARM/crash.ll | 44 +- test/CodeGen/ARM/debug-info-arg.ll | 65 + test/CodeGen/ARM/debug-info-blocks.ll | 2 +- test/CodeGen/ARM/debug-info-sreg2.ll | 6 +- test/CodeGen/ARM/divmod.ll | 58 + test/CodeGen/ARM/elf-lcomm-align.ll | 14 + test/CodeGen/ARM/fabss.ll | 4 +- test/CodeGen/ARM/fast-isel.ll | 4 +- test/CodeGen/ARM/fp_convert.ll | 6 +- test/CodeGen/ARM/fpmem.ll | 18 + test/CodeGen/ARM/hidden-vis-2.ll | 2 +- test/CodeGen/ARM/hidden-vis-3.ll | 2 +- test/CodeGen/ARM/iabs.ll | 8 +- test/CodeGen/ARM/ifcvt4.ll | 10 +- test/CodeGen/ARM/indirectbr.ll | 1 - test/CodeGen/ARM/inlineasm3.ll | 12 + test/CodeGen/ARM/inlineasm4.ll | 17 + test/CodeGen/ARM/lsr-on-unrolled-loops.ll | 495 ++--- test/CodeGen/ARM/lsr-unfolded-offset.ll | 3 +- test/CodeGen/ARM/mulhi.ll | 44 +- test/CodeGen/ARM/select.ll | 12 +- test/CodeGen/ARM/shifter_operand.ll | 9 +- test/CodeGen/ARM/str_pre-2.ll | 4 +- test/CodeGen/ARM/subreg-remat.ll | 52 + test/CodeGen/ARM/sxt_rot.ll | 41 +- test/CodeGen/ARM/tail-opts.ll | 2 +- test/CodeGen/ARM/thumb2-it-block.ll | 20 + test/CodeGen/ARM/va_arg.ll | 1 + test/CodeGen/ARM/vext.ll | 17 + test/CodeGen/ARM/widen-vmovs.ll | 35 + test/CodeGen/Alpha/2006-04-04-zextload.ll | 4 - test/CodeGen/Alpha/mb.ll | 4 +- test/CodeGen/Alpha/wmb.ll | 8 - test/CodeGen/CBackend/X86/dg.exp | 2 +- test/CodeGen/CellSPU/jumptable.ll | 12 +- test/CodeGen/CellSPU/or_ops.ll | 13 +- test/CodeGen/Generic/2004-02-08-UnwindSupport.ll | 17 - test/CodeGen/Generic/2007-02-25-invoke.ll | 6 +- .../Generic/2007-04-30-LandingPadBranchFolding.ll | 6 +- test/CodeGen/Generic/2007-12-17-InvokeAsm.ll | 12 +- test/CodeGen/Generic/2007-12-31-UnusedSelector.ll | 5 +- .../Generic/2009-06-03-UnreachableSplitPad.ll | 4 + test/CodeGen/Generic/2009-11-16-BadKillsCrash.ll | 8 +- .../CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll | 3 + test/CodeGen/Generic/exception-handling.ll | 29 + ...ltiple-return-values-cross-block-with-invoke.ll | 3 + test/CodeGen/Generic/promote-integers.ll | 15 - test/CodeGen/Mips/2008-07-05-ByVal.ll | 18 - test/CodeGen/Mips/2008-07-06-fadd64.ll | 6 +- test/CodeGen/Mips/2008-07-07-FPExtend.ll | 6 +- .../Mips/2008-07-07-IntDoubleConvertions.ll | 17 +- test/CodeGen/Mips/2008-07-15-InternalConstant.ll | 19 +- test/CodeGen/Mips/2008-07-15-SmallSection.ll | 23 +- test/CodeGen/Mips/2008-07-16-SignExtInReg.ll | 8 +- test/CodeGen/Mips/2008-08-03-fabs64.ll | 8 +- test/CodeGen/Mips/2008-08-07-FPRound.ll | 6 +- test/CodeGen/Mips/2008-08-08-bswap.ll | 5 +- test/CodeGen/Mips/2010-07-20-Select.ll | 22 - test/CodeGen/Mips/2010-11-09-CountLeading.ll | 2 +- test/CodeGen/Mips/2010-11-09-Mul.ll | 2 +- test/CodeGen/Mips/alloca.ll | 2 +- test/CodeGen/Mips/atomic.ll | 125 +- test/CodeGen/Mips/brdelayslot.ll | 15 + test/CodeGen/Mips/cmov.ll | 4 +- test/CodeGen/Mips/constantfp0.ll | 11 + test/CodeGen/Mips/cprestore.ll | 20 + test/CodeGen/Mips/double2int.ll | 2 +- test/CodeGen/Mips/eh.ll | 15 +- test/CodeGen/Mips/extins.ll | 21 + test/CodeGen/Mips/fcopysign.ll | 4 +- test/CodeGen/Mips/fpcmp.ll | 15 +- test/CodeGen/Mips/frame-address.ll | 2 +- test/CodeGen/Mips/i64arg.ll | 2 +- test/CodeGen/Mips/inlineasmmemop.ll | 2 +- test/CodeGen/Mips/internalfunc.ll | 2 +- test/CodeGen/Mips/largeimmprinting.ll | 6 +- test/CodeGen/Mips/madd-msub.ll | 14 +- test/CodeGen/Mips/mips64fpldst.ll | 58 + test/CodeGen/Mips/mips64instrs.ll | 143 ++ test/CodeGen/Mips/mips64intldst.ll | 157 ++ test/CodeGen/Mips/mips64shift.ll | 104 ++ test/CodeGen/Mips/mipslopat.ll | 19 + test/CodeGen/Mips/o32_cc.ll | 2 +- test/CodeGen/Mips/o32_cc_byval.ll | 2 +- test/CodeGen/Mips/o32_cc_vararg.ll | 2 +- test/CodeGen/Mips/rotate.ll | 2 +- test/CodeGen/Mips/select.ll | 96 +- test/CodeGen/Mips/tls.ll | 4 +- test/CodeGen/Mips/unalignedload.ll | 41 + test/CodeGen/PTX/20110926-sitofp.ll | 24 + test/CodeGen/PTX/add.ll | 40 +- test/CodeGen/PTX/aggregates.ll | 1 + test/CodeGen/PTX/bitwise.ll | 6 +- test/CodeGen/PTX/bra.ll | 8 +- test/CodeGen/PTX/cvt.ll | 186 +- test/CodeGen/PTX/fdiv-sm10.ll | 8 +- test/CodeGen/PTX/fdiv-sm13.ll | 8 +- test/CodeGen/PTX/fneg.ll | 8 +- test/CodeGen/PTX/intrinsic.ll | 134 +- test/CodeGen/PTX/ld.ll | 255 +-- test/CodeGen/PTX/llvm-intrinsic.ll | 24 +- test/CodeGen/PTX/mad.ll | 8 +- test/CodeGen/PTX/mov.ll | 24 +- test/CodeGen/PTX/mul.ll | 16 +- test/CodeGen/PTX/parameter-order.ll | 4 +- test/CodeGen/PTX/selp.ll | 8 +- test/CodeGen/PTX/setp.ll | 136 +- test/CodeGen/PTX/shl.ll | 6 +- test/CodeGen/PTX/shr.ll | 12 +- test/CodeGen/PTX/simple-call.ll | 27 + test/CodeGen/PTX/st.ll | 235 +-- test/CodeGen/PTX/stack-object.ll | 19 + test/CodeGen/PTX/sub.ll | 40 +- .../CodeGen/PowerPC/2007-11-16-landingpad-split.ll | 17 +- test/CodeGen/PowerPC/2009-01-16-DeclareISelBug.ll | 7 - test/CodeGen/PowerPC/2009-08-23-linkerprivate.ll | 2 +- test/CodeGen/PowerPC/Atomics-32.ll | 1402 +++++++------- test/CodeGen/PowerPC/Atomics-64.ll | 1433 +++++++-------- test/CodeGen/PowerPC/atomic-1.ll | 25 +- test/CodeGen/PowerPC/atomic-2.ll | 25 +- test/CodeGen/PowerPC/cr1eq.ll | 18 + test/CodeGen/PowerPC/trampoline.ll | 6 +- test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll | 6 +- test/CodeGen/Thumb/barrier.ll | 14 +- test/CodeGen/Thumb/iabs.ll | 11 +- test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll | 4 +- test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll | 18 +- test/CodeGen/Thumb2/machine-licm.ll | 2 +- test/CodeGen/Thumb2/thumb2-barrier.ll | 31 - test/CodeGen/Thumb2/thumb2-bcc.ll | 23 +- test/CodeGen/Thumb2/thumb2-branch.ll | 18 +- test/CodeGen/Thumb2/thumb2-ifcvt1.ll | 8 +- test/CodeGen/Thumb2/thumb2-ldm.ll | 2 +- test/CodeGen/Thumb2/thumb2-mls.ll | 2 +- test/CodeGen/Thumb2/thumb2-mul.ll | 2 +- test/CodeGen/Thumb2/thumb2-sxt-uxt.ll | 29 + test/CodeGen/X86/2006-05-11-InstrSched.ll | 2 +- test/CodeGen/X86/2006-07-19-ATTAsm.ll | 49 - test/CodeGen/X86/2007-05-07-InvokeSRet.ll | 4 + test/CodeGen/X86/2008-01-08-SchedulerCrash.ll | 10 +- test/CodeGen/X86/2008-04-17-CoalescerBug.ll | 6 + test/CodeGen/X86/2008-05-28-LocalRegAllocBug.ll | 6 +- test/CodeGen/X86/2008-08-19-SubAndFetch.ll | 4 +- test/CodeGen/X86/2008-09-18-inline-asm-2.ll | 2 +- test/CodeGen/X86/2008-10-02-Atomics32-2.ll | 969 ---------- test/CodeGen/X86/2009-03-13-PHIElimBug.ll | 4 + test/CodeGen/X86/2009-03-16-PHIElimInLPad.ll | 4 + .../X86/2009-06-05-ScalarToVectorByteMMX.ll | 2 +- .../X86/2009-06-18-movlp-shuffle-register.ll | 3 +- test/CodeGen/X86/2009-09-10-LoadFoldingBug.ll | 4 + test/CodeGen/X86/2009-10-16-Scope.ll | 4 +- test/CodeGen/X86/2009-10-19-atomic-cmp-eflags.ll | 6 +- test/CodeGen/X86/2009-11-25-ImpDefBug.ll | 4 + test/CodeGen/X86/2010-01-08-Atomic64Bug.ll | 8 +- test/CodeGen/X86/2010-04-06-SSEDomainFixCrash.ll | 4 + .../X86/2010-04-30-LocalAlloc-LandingPad.ll | 2 - test/CodeGen/X86/2010-10-08-cmpxchg8b.ll | 4 +- test/CodeGen/X86/2011-05-31-movmsk.ll | 79 - .../CodeGen/X86/2011-08-23-PerformSubCombine128.ll | 18 + test/CodeGen/X86/2011-08-23-Trampoline.ll | 16 + test/CodeGen/X86/2011-08-29-BlockConstant.ll | 34 + test/CodeGen/X86/2011-08-29-InitOrder.ll | 28 + test/CodeGen/X86/2011-09-14-valcoalesce.ll | 174 ++ test/CodeGen/X86/2011-09-18-sse2cmp.ll | 12 + test/CodeGen/X86/2011-09-21-setcc-bug.ll | 27 + test/CodeGen/X86/2011-10-11-SpillDead.ll | 19 + test/CodeGen/X86/2011-10-11-srl.ll | 11 + test/CodeGen/X86/2011-10-12-MachineCSE.ll | 116 ++ test/CodeGen/X86/Atomics-32.ll | 818 --------- test/CodeGen/X86/Atomics-64.ll | 1919 ++++++++++---------- test/CodeGen/X86/MachineSink-DbgValue.ll | 49 + test/CodeGen/X86/MachineSink-eflags.ll | 74 + test/CodeGen/X86/SIMD/dg.exp | 5 - test/CodeGen/X86/SIMD/notvunpcklpd.ll | 20 - test/CodeGen/X86/SIMD/notvunpcklps.ll | 20 - test/CodeGen/X86/SIMD/vunpcklpd.ll | 20 - test/CodeGen/X86/SIMD/vunpcklps.ll | 20 - test/CodeGen/X86/alignment-2.ll | 28 + test/CodeGen/X86/alignment.ll | 2 +- test/CodeGen/X86/asm-label2.ll | 4 + test/CodeGen/X86/atomic-load-store-wide.ll | 19 + test/CodeGen/X86/atomic-load-store.ll | 23 + test/CodeGen/X86/atomic-or.ll | 12 +- test/CodeGen/X86/atomic_add.ll | 116 +- test/CodeGen/X86/atomic_op.ll | 62 +- test/CodeGen/X86/avx-128.ll | 54 - test/CodeGen/X86/avx-256-arith.ll | 116 -- test/CodeGen/X86/avx-256-arith.s | 0 test/CodeGen/X86/avx-256-logic.ll | 161 -- test/CodeGen/X86/avx-256.ll | 15 - test/CodeGen/X86/avx-arith.ll | 261 +++ test/CodeGen/X86/avx-basic.ll | 107 ++ test/CodeGen/X86/avx-bitcast.ll | 10 + test/CodeGen/X86/avx-blend.ll | 104 ++ test/CodeGen/X86/avx-cast.ll | 47 + test/CodeGen/X86/avx-cmp.ll | 150 ++ test/CodeGen/X86/avx-cvt.ll | 83 + test/CodeGen/X86/avx-load-store.ll | 85 +- test/CodeGen/X86/avx-logic.ll | 179 ++ test/CodeGen/X86/avx-minmax.ll | 65 + test/CodeGen/X86/avx-movdup.ll | 34 + test/CodeGen/X86/avx-select.ll | 22 + test/CodeGen/X86/avx-shift.ll | 75 + test/CodeGen/X86/avx-shuffle.ll | 10 + test/CodeGen/X86/avx-splat.ll | 103 ++ test/CodeGen/X86/avx-unpack.ll | 89 + test/CodeGen/X86/avx-vbroadcast.ll | 94 + test/CodeGen/X86/avx-vextractf128.ll | 18 + test/CodeGen/X86/avx-vinsertf128.ll | 58 + test/CodeGen/X86/avx-vmovddup.ll | 14 + test/CodeGen/X86/avx-vperm2f128.ll | 62 + test/CodeGen/X86/avx-vpermil.ll | 45 + test/CodeGen/X86/avx-vshufp.ll | 29 + test/CodeGen/X86/avx-vzeroupper.ll | 26 + test/CodeGen/X86/barrier-sse.ll | 18 +- test/CodeGen/X86/barrier.ll | 5 +- test/CodeGen/X86/bmi.ll | 53 + test/CodeGen/X86/bswap.ll | 2 +- test/CodeGen/X86/change-compare-stride-0.ll | 5 +- test/CodeGen/X86/change-compare-stride-1.ll | 5 +- test/CodeGen/X86/cmov.ll | 4 +- test/CodeGen/X86/cmpxchg16b.ll | 13 + test/CodeGen/X86/coalescer-dce.ll | 80 + test/CodeGen/X86/coalescer-remat.ll | 12 +- test/CodeGen/X86/code_placement_eh.ll | 10 +- test/CodeGen/X86/crash-nosse.ll | 27 + test/CodeGen/X86/crash.ll | 75 + test/CodeGen/X86/dbg-at-specficiation.ll | 20 + test/CodeGen/X86/dbg-inline.ll | 140 ++ test/CodeGen/X86/dbg-large-unsigned-const.ll | 61 + test/CodeGen/X86/dbg-value-isel.ll | 4 +- test/CodeGen/X86/extractelement-load.ll | 20 +- test/CodeGen/X86/fast-isel-atomic.ll | 6 +- test/CodeGen/X86/fast-isel-cmp-branch.ll | 4 + test/CodeGen/X86/fast-isel-gep.ll | 30 + test/CodeGen/X86/fast-isel-tls.ll | 18 +- test/CodeGen/X86/fast-isel-x86-64.ll | 25 +- test/CodeGen/X86/fp-stack-O0-crash.ll | 21 +- test/CodeGen/X86/global-sections.ll | 2 +- test/CodeGen/X86/haddsub.ll | 194 ++ test/CodeGen/X86/hidden-vis.ll | 19 +- test/CodeGen/X86/inline-asm-fpstack.ll | 11 + test/CodeGen/X86/iv-users-in-other-loops.ll | 6 +- test/CodeGen/X86/lfence.ll | 6 +- test/CodeGen/X86/licm-dominance.ll | 36 + test/CodeGen/X86/licm-nested.ll | 2 +- test/CodeGen/X86/lock-inst-encoding.ll | 43 +- test/CodeGen/X86/loop-strength-reduce3.ll | 4 +- test/CodeGen/X86/lzcnt.ll | 38 + test/CodeGen/X86/membarrier.ll | 9 +- test/CodeGen/X86/mfence.ll | 16 +- test/CodeGen/X86/movbe.ll | 36 + test/CodeGen/X86/movgs.ll | 2 +- test/CodeGen/X86/movmsk.ll | 110 ++ test/CodeGen/X86/nofence.ll | 27 - test/CodeGen/X86/norex-subreg.ll | 80 + test/CodeGen/X86/opt-shuff-tstore.ll | 39 + test/CodeGen/X86/or-address.ll | 8 +- test/CodeGen/X86/palignr.ll | 31 +- test/CodeGen/X86/personality.ll | 10 +- test/CodeGen/X86/pr10420.ll | 21 + test/CodeGen/X86/pr3495.ll | 8 +- test/CodeGen/X86/pr3522.ll | 4 + test/CodeGen/X86/ptr-rotate.ll | 11 + test/CodeGen/X86/scev-interchange.ll | 44 + test/CodeGen/X86/segmented-stacks.ll | 87 + test/CodeGen/X86/sfence.ll | 6 +- test/CodeGen/X86/sink-hoist.ll | 10 +- test/CodeGen/X86/split-eh-lpad-edges.ll | 4 + test/CodeGen/X86/split-vector-bitcast.ll | 12 + test/CodeGen/X86/sse-minmax.ll | 38 +- test/CodeGen/X86/sse2-blend.ll | 55 + test/CodeGen/X86/sse41-blend.ll | 82 + test/CodeGen/X86/sub.ll | 11 + test/CodeGen/X86/tail-call-got.ll | 24 + test/CodeGen/X86/tlv-1.ll | 17 + test/CodeGen/X86/trunc-ext-ld-st.ll | 82 + test/CodeGen/X86/twoaddr-sink-terminator.ll | 43 + test/CodeGen/X86/uint64-to-float.ll | 33 +- test/CodeGen/X86/uint_to_fp-2.ll | 31 +- test/CodeGen/X86/v2f32.ll | 2 +- test/CodeGen/X86/vec_compare-sse4.ll | 35 + test/CodeGen/X86/vec_set-C.ll | 6 +- test/CodeGen/X86/vec_shuffle-37.ll | 24 +- test/CodeGen/X86/vec_shuffle-38.ll | 59 + test/CodeGen/X86/widen_shuffle-1.ll | 8 + test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll | 20 + test/CodeGen/XCore/2011-08-01-VarargsBug.ll | 17 + test/CodeGen/XCore/licm-ldwcp.ll | 18 + test/CodeGen/XCore/misc-intrinsics.ll | 48 + test/CodeGen/XCore/resources.ll | 41 + test/CodeGen/XCore/trampoline.ll | 6 +- 312 files changed, 9969 insertions(+), 6578 deletions(-) create mode 100644 test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll create mode 100644 test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll create mode 100644 test/CodeGen/ARM/2011-08-25-ldmia_ret.ll create mode 100644 test/CodeGen/ARM/2011-08-29-SchedCycle.ll create mode 100644 test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll create mode 100644 test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll create mode 100644 test/CodeGen/ARM/2011-09-19-cpsr.ll create mode 100644 test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll create mode 100644 test/CodeGen/ARM/atomic-64bit.ll create mode 100644 test/CodeGen/ARM/atomic-load-store.ll create mode 100644 test/CodeGen/ARM/crash-greedy-v6.ll create mode 100644 test/CodeGen/ARM/debug-info-arg.ll create mode 100644 test/CodeGen/ARM/divmod.ll create mode 100644 test/CodeGen/ARM/elf-lcomm-align.ll create mode 100644 test/CodeGen/ARM/inlineasm4.ll create mode 100644 test/CodeGen/ARM/subreg-remat.ll create mode 100644 test/CodeGen/ARM/thumb2-it-block.ll create mode 100644 test/CodeGen/ARM/widen-vmovs.ll delete mode 100644 test/CodeGen/Alpha/wmb.ll delete mode 100644 test/CodeGen/Generic/2004-02-08-UnwindSupport.ll create mode 100644 test/CodeGen/Generic/exception-handling.ll delete mode 100644 test/CodeGen/Generic/promote-integers.ll delete mode 100644 test/CodeGen/Mips/2008-07-05-ByVal.ll delete mode 100644 test/CodeGen/Mips/2010-07-20-Select.ll create mode 100644 test/CodeGen/Mips/brdelayslot.ll create mode 100644 test/CodeGen/Mips/constantfp0.ll create mode 100644 test/CodeGen/Mips/cprestore.ll create mode 100644 test/CodeGen/Mips/extins.ll create mode 100644 test/CodeGen/Mips/mips64fpldst.ll create mode 100644 test/CodeGen/Mips/mips64instrs.ll create mode 100644 test/CodeGen/Mips/mips64intldst.ll create mode 100644 test/CodeGen/Mips/mips64shift.ll create mode 100644 test/CodeGen/Mips/mipslopat.ll create mode 100644 test/CodeGen/Mips/unalignedload.ll create mode 100644 test/CodeGen/PTX/20110926-sitofp.ll create mode 100644 test/CodeGen/PTX/simple-call.ll create mode 100644 test/CodeGen/PTX/stack-object.ll create mode 100644 test/CodeGen/PowerPC/cr1eq.ll delete mode 100644 test/CodeGen/Thumb2/thumb2-barrier.ll create mode 100644 test/CodeGen/Thumb2/thumb2-sxt-uxt.ll delete mode 100644 test/CodeGen/X86/2006-07-19-ATTAsm.ll delete mode 100644 test/CodeGen/X86/2008-10-02-Atomics32-2.ll delete mode 100644 test/CodeGen/X86/2011-05-31-movmsk.ll create mode 100644 test/CodeGen/X86/2011-08-23-PerformSubCombine128.ll create mode 100644 test/CodeGen/X86/2011-08-23-Trampoline.ll create mode 100644 test/CodeGen/X86/2011-08-29-BlockConstant.ll create mode 100644 test/CodeGen/X86/2011-08-29-InitOrder.ll create mode 100644 test/CodeGen/X86/2011-09-14-valcoalesce.ll create mode 100644 test/CodeGen/X86/2011-09-18-sse2cmp.ll create mode 100644 test/CodeGen/X86/2011-09-21-setcc-bug.ll create mode 100644 test/CodeGen/X86/2011-10-11-SpillDead.ll create mode 100644 test/CodeGen/X86/2011-10-11-srl.ll create mode 100644 test/CodeGen/X86/2011-10-12-MachineCSE.ll delete mode 100644 test/CodeGen/X86/Atomics-32.ll create mode 100644 test/CodeGen/X86/MachineSink-DbgValue.ll create mode 100644 test/CodeGen/X86/MachineSink-eflags.ll delete mode 100644 test/CodeGen/X86/SIMD/dg.exp delete mode 100644 test/CodeGen/X86/SIMD/notvunpcklpd.ll delete mode 100644 test/CodeGen/X86/SIMD/notvunpcklps.ll delete mode 100644 test/CodeGen/X86/SIMD/vunpcklpd.ll delete mode 100644 test/CodeGen/X86/SIMD/vunpcklps.ll create mode 100644 test/CodeGen/X86/alignment-2.ll create mode 100644 test/CodeGen/X86/atomic-load-store-wide.ll create mode 100644 test/CodeGen/X86/atomic-load-store.ll delete mode 100644 test/CodeGen/X86/avx-128.ll delete mode 100644 test/CodeGen/X86/avx-256-arith.ll delete mode 100644 test/CodeGen/X86/avx-256-arith.s delete mode 100644 test/CodeGen/X86/avx-256-logic.ll delete mode 100644 test/CodeGen/X86/avx-256.ll create mode 100644 test/CodeGen/X86/avx-arith.ll create mode 100644 test/CodeGen/X86/avx-basic.ll create mode 100644 test/CodeGen/X86/avx-bitcast.ll create mode 100644 test/CodeGen/X86/avx-blend.ll create mode 100644 test/CodeGen/X86/avx-cast.ll create mode 100644 test/CodeGen/X86/avx-cmp.ll create mode 100644 test/CodeGen/X86/avx-cvt.ll create mode 100644 test/CodeGen/X86/avx-logic.ll create mode 100644 test/CodeGen/X86/avx-minmax.ll create mode 100644 test/CodeGen/X86/avx-movdup.ll create mode 100644 test/CodeGen/X86/avx-select.ll create mode 100644 test/CodeGen/X86/avx-shift.ll create mode 100644 test/CodeGen/X86/avx-shuffle.ll create mode 100644 test/CodeGen/X86/avx-splat.ll create mode 100644 test/CodeGen/X86/avx-unpack.ll create mode 100644 test/CodeGen/X86/avx-vbroadcast.ll create mode 100644 test/CodeGen/X86/avx-vextractf128.ll create mode 100644 test/CodeGen/X86/avx-vinsertf128.ll create mode 100644 test/CodeGen/X86/avx-vmovddup.ll create mode 100644 test/CodeGen/X86/avx-vperm2f128.ll create mode 100644 test/CodeGen/X86/avx-vpermil.ll create mode 100644 test/CodeGen/X86/avx-vshufp.ll create mode 100644 test/CodeGen/X86/avx-vzeroupper.ll create mode 100644 test/CodeGen/X86/bmi.ll create mode 100644 test/CodeGen/X86/cmpxchg16b.ll create mode 100644 test/CodeGen/X86/coalescer-dce.ll create mode 100644 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test/CodeGen/X86/tail-call-got.ll create mode 100644 test/CodeGen/X86/trunc-ext-ld-st.ll create mode 100644 test/CodeGen/X86/twoaddr-sink-terminator.ll create mode 100644 test/CodeGen/X86/vec_compare-sse4.ll create mode 100644 test/CodeGen/X86/vec_shuffle-38.ll create mode 100644 test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll create mode 100644 test/CodeGen/XCore/2011-08-01-VarargsBug.ll create mode 100644 test/CodeGen/XCore/licm-ldwcp.ll (limited to 'test/CodeGen') diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index ce440e986de0..a2e7ff718b4a 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -23,10 +23,10 @@ declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone declare i32 @foo(i32) ssp !0 = metadata !{i32 5, i32 2, metadata !1, null} -!1 = metadata !{i32 458763, metadata !2}; [DW_TAG_lexical_block ] +!1 = metadata !{i32 458763, metadata !2, i32 1, i32 1}; [DW_TAG_lexical_block ] !2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", metadata !3, i32 4, null, i1 false, i1 true}; [DW_TAG_subprogram ] !3 = metadata !{i32 458769, i32 0, i32 12, metadata !"genmodes.i", metadata !"/Users/yash/Downloads", metadata !"clang 1.1", i1 true, i1 false, metadata !"", i32 0}; [DW_TAG_compile_unit ] !4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ] -!5 = metadata !{i32 458763, metadata !1}; [DW_TAG_lexical_block ] +!5 = metadata !{i32 458763, metadata !1, i32 1, i32 1}; [DW_TAG_lexical_block ] !6 = metadata !{i32 458788, metadata !3, metadata !"int", metadata !3, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5}; [DW_TAG_base_type ] !7 = metadata !{i32 6, i32 1, metadata !2, null} diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll index 930cd8d41563..8b164c5d91f8 100644 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll @@ -21,20 +21,20 @@ entry: ; OBJ-NEXT: 'sh_entsize' ; OBJ-NEXT: '_section_data', '00482de9 000000e3 000040e3 feffffeb 0088bde8' -; OBJ: Relocation 0x00000000 +; OBJ: Relocation 0 ; OBJ-NEXT: 'r_offset', 0x00000004 -; OBJ-NEXT: 'r_sym', 0x00000007 -; OBJ-NEXT: 'r_type', 0x0000002b +; OBJ-NEXT: 'r_sym', 0x000007 +; OBJ-NEXT: 'r_type', 0x2b -; OBJ: Relocation 0x00000001 +; OBJ: Relocation 1 ; OBJ-NEXT: 'r_offset', 0x00000008 ; OBJ-NEXT: 'r_sym' -; OBJ-NEXT: 'r_type', 0x0000002c +; OBJ-NEXT: 'r_type', 0x2c -; OBJ: # Relocation 0x00000002 +; OBJ: # Relocation 2 ; OBJ-NEXT: 'r_offset', 0x0000000c -; OBJ-NEXT: 'r_sym', 0x00000008 -; OBJ-NEXT: 'r_type', 0x0000001c +; OBJ-NEXT: 'r_sym', 0x000008 +; OBJ-NEXT: 'r_type', 0x1c } diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index 69d4a1482299..5cfbb4f944f7 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -5,7 +5,7 @@ @dummy = internal global i32 666 -@array00 = internal global [20 x i32] zeroinitializer +@array00 = internal global [80 x i8] zeroinitializer, align 1 @sum = internal global i32 55 @STRIDE = internal global i32 8 @@ -15,21 +15,22 @@ -; OBJ: Section 0x00000004 +; OBJ: Section 4 ; OBJ-NEXT: '.bss' ; OBJ: 'array00' ; OBJ-NEXT: 'st_value', 0x00000000 ; OBJ-NEXT: 'st_size', 0x00000050 -; OBJ-NEXT: 'st_bind', 0x00000000 -; OBJ-NEXT: 'st_type', 0x00000001 -; OBJ-NEXT: 'st_other', 0x00000000 -; OBJ-NEXT: 'st_shndx', 0x00000004 +; OBJ-NEXT: 'st_bind', 0x0 +; OBJ-NEXT: 'st_type', 0x1 +; OBJ-NEXT: 'st_other', 0x00 +; OBJ-NEXT: 'st_shndx', 0x0004 define i32 @main(i32 %argc) nounwind { %1 = load i32* @sum, align 4 - %2 = getelementptr [20 x i32]* @array00, i32 0, i32 %argc - %3 = load i32* %2, align 4 - %4 = add i32 %1, %3 - ret i32 %4; + %2 = getelementptr [80 x i8]* @array00, i32 0, i32 %argc + %3 = load i8* %2 + %4 = zext i8 %3 to i32 + %5 = add i32 %1, %4 + ret i32 %5 } diff --git a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll index 4db3acf6b420..7f0f795486f8 100644 --- a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll +++ b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s + target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll new file mode 100644 index 000000000000..f681c34bdaa2 --- /dev/null +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -0,0 +1,124 @@ +; RUN: llc < %s | FileCheck %s + +; Check debug info output for merged global. +; DW_AT_location +; DW_OP_addr +; DW_OP_plus +; .long __MergedGlobals +; DW_OP_constu +; offset + +;CHECK: .ascii "x2" @ DW_AT_name +;CHECK-NEXT: .byte 0 +;CHECK-NEXT: @ DW_AT_type +;CHECK-NEXT: @ DW_AT_decl_file +;CHECK-NEXT: @ DW_AT_decl_line +;CHECK-NEXT: @ DW_AT_location +;CHECK-NEXT: .byte 3 +;CHECK-NEXT: .long __MergedGlobals +;CHECK-NEXT: .byte 16 +; 4 is byte offset of x2 in __MergedGobals +;CHECK-NEXT: .byte 4 +;CHECK-NEXT: .byte 34 + + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.7.0" + +@x1 = internal unnamed_addr global i32 1, align 4 +@x2 = internal unnamed_addr global i32 2, align 4 +@x3 = internal unnamed_addr global i32 3, align 4 +@x4 = internal unnamed_addr global i32 4, align 4 +@x5 = global i32 0, align 4 + +define i32 @get1(i32 %a) nounwind optsize ssp { + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !10), !dbg !30 + %1 = load i32* @x1, align 4, !dbg !31 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !11), !dbg !31 + store i32 %a, i32* @x1, align 4, !dbg !31 + ret i32 %1, !dbg !31 +} + +define i32 @get2(i32 %a) nounwind optsize ssp { + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !13), !dbg !32 + %1 = load i32* @x2, align 4, !dbg !33 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !14), !dbg !33 + store i32 %a, i32* @x2, align 4, !dbg !33 + ret i32 %1, !dbg !33 +} + +define i32 @get3(i32 %a) nounwind optsize ssp { + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !16), !dbg !34 + %1 = load i32* @x3, align 4, !dbg !35 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !17), !dbg !35 + store i32 %a, i32* @x3, align 4, !dbg !35 + ret i32 %1, !dbg !35 +} + +define i32 @get4(i32 %a) nounwind optsize ssp { + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !19), !dbg !36 + %1 = load i32* @x4, align 4, !dbg !37 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !20), !dbg !37 + store i32 %a, i32* @x4, align 4, !dbg !37 + ret i32 %1, !dbg !37 +} + +define i32 @get5(i32 %a) nounwind optsize ssp { + tail call void @llvm.dbg.value(metadata !{i32 %a}, i64 0, metadata !27), !dbg !38 + %1 = load i32* @x5, align 4, !dbg !39 + tail call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !28), !dbg !39 + store i32 %a, i32* @x5, align 4, !dbg !39 + ret i32 %1, !dbg !39 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !6, !7, !8, !9} +!llvm.dbg.lv.get1 = !{!10, !11} +!llvm.dbg.lv.get2 = !{!13, !14} +!llvm.dbg.lv.get3 = !{!16, !17} +!llvm.dbg.lv.get4 = !{!19, !20} +!llvm.dbg.gv = !{!22, !23, !24, !25, !26} +!llvm.dbg.lv.get5 = !{!27, !28} + +!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"ss3.c", metadata !"/private/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get1", metadata !"get1", metadata !"", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"ss3.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get2", metadata !"get2", metadata !"", metadata !2, i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get3", metadata !"get3", metadata !"", metadata !2, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get4", metadata !"get4", metadata !"", metadata !2, i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null} ; [ DW_TAG_subprogram ] +!9 = metadata !{i32 589870, i32 0, metadata !2, metadata !"get5", metadata !"get5", metadata !"", metadata !2, i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 590081, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 590080, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!12 = metadata !{i32 589835, metadata !1, i32 5, i32 19, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!13 = metadata !{i32 590081, metadata !6, metadata !"a", metadata !2, i32 16777224, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!14 = metadata !{i32 590080, metadata !15, metadata !"b", metadata !2, i32 8, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!15 = metadata !{i32 589835, metadata !6, i32 8, i32 17, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!16 = metadata !{i32 590081, metadata !7, metadata !"a", metadata !2, i32 16777227, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 590080, metadata !18, metadata !"b", metadata !2, i32 11, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!18 = metadata !{i32 589835, metadata !7, i32 11, i32 19, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!19 = metadata !{i32 590081, metadata !8, metadata !"a", metadata !2, i32 16777230, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590080, metadata !21, metadata !"b", metadata !2, i32 14, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!21 = metadata !{i32 589835, metadata !8, i32 14, i32 19, metadata !2, i32 3} ; [ DW_TAG_lexical_block ] +!22 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x5", metadata !"x5", metadata !"", metadata !2, i32 16, metadata !5, i32 0, i32 1, i32* @x5} ; [ DW_TAG_variable ] +!23 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x4", metadata !"x4", metadata !"", metadata !2, i32 13, metadata !5, i32 1, i32 1, i32* @x4} ; [ DW_TAG_variable ] +!24 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x3", metadata !"x3", metadata !"", metadata !2, i32 10, metadata !5, i32 1, i32 1, i32* @x3} ; [ DW_TAG_variable ] +!25 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x2", metadata !"x2", metadata !"", metadata !2, i32 7, metadata !5, i32 1, i32 1, i32* @x2} ; [ DW_TAG_variable ] +!26 = metadata !{i32 589876, i32 0, metadata !0, metadata !"x1", metadata !"x1", metadata !"", metadata !2, i32 4, metadata !5, i32 1, i32 1, i32* @x1} ; [ DW_TAG_variable ] +!27 = metadata !{i32 590081, metadata !9, metadata !"a", metadata !2, i32 16777233, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!28 = metadata !{i32 590080, metadata !29, metadata !"b", metadata !2, i32 17, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 589835, metadata !9, i32 17, i32 19, metadata !2, i32 4} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 5, i32 16, metadata !1, null} +!31 = metadata !{i32 5, i32 32, metadata !12, null} +!32 = metadata !{i32 8, i32 14, metadata !6, null} +!33 = metadata !{i32 8, i32 29, metadata !15, null} +!34 = metadata !{i32 11, i32 16, metadata !7, null} +!35 = metadata !{i32 11, i32 32, metadata !18, null} +!36 = metadata !{i32 14, i32 16, metadata !8, null} +!37 = metadata !{i32 14, i32 32, metadata !21, null} +!38 = metadata !{i32 17, i32 16, metadata !9, null} +!39 = metadata !{i32 17, i32 32, metadata !29, null} diff --git a/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll new file mode 100644 index 000000000000..3cbc4cdcd707 --- /dev/null +++ b/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll @@ -0,0 +1,12 @@ +; RUN: llc %s -mtriple=thumbv7-apple-darwin -verify-machineinstrs -mcpu=cortex-a9 -O0 -o - +; Make sure that the VMOVQQQQ pseudo instruction is handled properly +; by codegen. + +define void @test_vmovqqqq_pseudo() nounwind ssp { +entry: + %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2) + store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef + ret void +} + +declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll new file mode 100644 index 000000000000..17264ee44ae5 --- /dev/null +++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -0,0 +1,100 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; Test that ldmia_ret preserves implicit operands for return values. +; +; This CFG is reduced from a benchmark miscompile. With current +; if-conversion heuristics, one of the return paths is if-converted +; into sw.bb18 resulting in an ldmia_ret in the middle of the +; block. The postra scheduler needs to know that the return implicitly +; uses the return register, otherwise its antidep breaker scavenges +; the register in order to hoist the constant load required to test +; the switch. + +declare i32 @getint() +declare i1 @getbool() +declare void @foo(i32) +declare i32 @bar(i32) + +define i32 @test(i32 %in1, i32 %in2) nounwind { +entry: + %call = tail call zeroext i1 @getbool() nounwind + br i1 %call, label %sw.bb18, label %sw.bb2 + +sw.bb2: ; preds = %entry + %cmp = tail call zeroext i1 @getbool() nounwind + br i1 %cmp, label %sw.epilog58, label %land.lhs.true + +land.lhs.true: ; preds = %sw.bb2 + %cmp13 = tail call zeroext i1 @getbool() nounwind + br i1 %cmp13, label %if.then, label %sw.epilog58 + +if.then: ; preds = %land.lhs.true + tail call void @foo(i32 %in1) nounwind + br label %sw.epilog58 + +; load the return value +; CHECK: movs [[RRET:r.]], #2 +; hoist the switch constant without clobbering RRET +; CHECK: movw +; CHECK-NOT: [[RRET]] +; CHECK: , #63707 +; CHECK-NOT: [[RRET]] +; CHECK: tst +; If-convert the return +; CHECK: it ne +; Fold the CSR+return into a pop +; CHECK: popne {r4, r5, r7, pc} +sw.bb18: + %call20 = tail call i32 @bar(i32 %in2) nounwind + switch i32 %call20, label %sw.default56 [ + i32 168, label %sw.bb21 + i32 165, label %sw.bb21 + i32 261, label %sw.epilog58 + i32 188, label %sw.epilog58 + i32 187, label %sw.epilog58 + i32 186, label %sw.epilog58 + i32 185, label %sw.epilog58 + i32 184, label %sw.epilog58 + i32 175, label %sw.epilog58 + i32 174, label %sw.epilog58 + i32 173, label %sw.epilog58 + i32 172, label %sw.epilog58 + i32 171, label %sw.epilog58 + i32 167, label %sw.epilog58 + i32 166, label %sw.epilog58 + i32 164, label %sw.epilog58 + i32 163, label %sw.epilog58 + i32 161, label %sw.epilog58 + i32 160, label %sw.epilog58 + i32 -1, label %sw.bb33 + ] + +sw.bb21: ; preds = %sw.bb18, %sw.bb18 + tail call void @foo(i32 %in2) nounwind + %call28 = tail call i32 @getint() nounwind + %tobool = icmp eq i32 %call28, 0 + br i1 %tobool, label %if.then29, label %sw.epilog58 + +if.then29: ; preds = %sw.bb21 + tail call void @foo(i32 %in2) nounwind + br label %sw.epilog58 + +sw.bb33: ; preds = %sw.bb18 + %cmp42 = tail call zeroext i1 @getbool() nounwind + br i1 %cmp42, label %sw.default56, label %land.lhs.true44 + +land.lhs.true44: ; preds = %sw.bb33 + %call50 = tail call i32 @getint() nounwind + %cmp51 = icmp slt i32 %call50, 0 + br i1 %cmp51, label %if.then53, label %sw.default56 + +if.then53: ; preds = %land.lhs.true44 + tail call void @foo(i32 %in2) nounwind + br label %sw.default56 + +sw.default56: ; preds = %sw.bb33, %land.lhs.true44, %if.then53, %sw.bb18 + br label %sw.epilog58 + +sw.epilog58: + %retval.0 = phi i32 [ 4, %sw.default56 ], [ 2, %sw.bb21 ], [ 2, %if.then29 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb18 ], [ 2, %sw.bb2 ], [ 2, %land.lhs.true ], [ 2, %if.then ] + ret i32 %retval.0 +} diff --git a/test/CodeGen/ARM/2011-08-29-SchedCycle.ll b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll new file mode 100644 index 000000000000..be188ef630f2 --- /dev/null +++ b/test/CodeGen/ARM/2011-08-29-SchedCycle.ll @@ -0,0 +1,45 @@ +; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -o - + +; When a i64 sub is expanded to subc + sube. +; libcall #1 +; \ +; \ subc +; \ / \ +; \ / \ +; \ / libcall #2 +; sube +; +; If the libcalls are not serialized (i.e. both have chains which are dag +; entry), legalizer can serialize them in arbitrary orders. If it's +; unlucky, it can force libcall #2 before libcall #1 in the above case. +; +; subc +; | +; libcall #2 +; | +; libcall #1 +; | +; sube +; +; However since subc and sube are "glued" together, this ends up being a +; cycle when the scheduler combine subc and sube as a single scheduling +; unit. +; +; The right solution is to fix LegalizeType too chains the libcalls together. +; However, LegalizeType is not processing nodes in order. The fix now is to +; fix subc / sube (and addc / adde) to use physical register dependency instead. +; rdar://10019576 + +define void @t() nounwind { +entry: + %tmp = load i64* undef, align 4 + %tmp5 = udiv i64 %tmp, 30 + %tmp13 = and i64 %tmp5, 64739244643450880 + %tmp16 = sub i64 0, %tmp13 + %tmp19 = and i64 %tmp16, 63 + %tmp20 = urem i64 %tmp19, 3 + %tmp22 = and i64 %tmp16, -272346829004752 + store i64 %tmp22, i64* undef, align 4 + store i64 %tmp20, i64* undef, align 4 + ret void +} diff --git a/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll new file mode 100644 index 000000000000..6647ed8106d5 --- /dev/null +++ b/test/CodeGen/ARM/2011-08-29-ldr_pre_imm.ll @@ -0,0 +1,34 @@ +; RUN: llc -O3 -mtriple=armv6-apple-darwin -relocation-model=pic < %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32" + +define void @compdecomp() nounwind { +entry: + %heap = alloca [256 x i32], align 4 + br i1 undef, label %bb25.lr.ph, label %bb17 + +bb17: ; preds = %bb17, %entry + br label %bb17 + +bb25.lr.ph: ; preds = %entry + %0 = sdiv i32 undef, 2 + br label %bb5.i + +bb.i: ; preds = %bb5.i + %1 = shl nsw i32 %k_addr.0.i, 1 + %.sum8.i = add i32 %1, -1 + %2 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum8.i + %3 = load i32* %2, align 4 + br i1 false, label %bb5.i, label %bb4.i + +bb4.i: ; preds = %bb.i + %.sum10.i = add i32 %k_addr.0.i, -1 + %4 = getelementptr inbounds [256 x i32]* %heap, i32 0, i32 %.sum10.i + store i32 %3, i32* %4, align 4 + br label %bb5.i + +bb5.i: ; preds = %bb5.i, %bb4.i, %bb.i, %bb25.lr.ph + %k_addr.0.i = phi i32 [ %1, %bb4.i ], [ undef, %bb25.lr.ph ], [ undef, %bb5.i ], [ undef, %bb.i ] + %5 = icmp slt i32 %0, %k_addr.0.i + br i1 %5, label %bb5.i, label %bb.i +} diff --git a/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll new file mode 100644 index 000000000000..8fe91028e0c2 --- /dev/null +++ b/test/CodeGen/ARM/2011-09-09-OddVectorDivision.ll @@ -0,0 +1,23 @@ +; RUN: llc -mtriple=armv7-- < %s -mattr=-neon + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32" +target triple = "armv7-none-linux-gnueabi" + +@x1 = common global <3 x i16> zeroinitializer +@y1 = common global <3 x i16> zeroinitializer +@z1 = common global <3 x i16> zeroinitializer +@x2 = common global <4 x i16> zeroinitializer +@y2 = common global <4 x i16> zeroinitializer +@z2 = common global <4 x i16> zeroinitializer + +define void @f() { + %1 = load <3 x i16>* @x1 + %2 = load <3 x i16>* @y1 + %3 = sdiv <3 x i16> %1, %2 + store <3 x i16> %3, <3 x i16>* @z1 + %4 = load <4 x i16>* @x2 + %5 = load <4 x i16>* @y2 + %6 = sdiv <4 x i16> %4, %5 + store <4 x i16> %6, <4 x i16>* @z2 + ret void +} diff --git a/test/CodeGen/ARM/2011-09-19-cpsr.ll b/test/CodeGen/ARM/2011-09-19-cpsr.ll new file mode 100644 index 000000000000..749a6d2b4b52 --- /dev/null +++ b/test/CodeGen/ARM/2011-09-19-cpsr.ll @@ -0,0 +1,54 @@ +; RUN: llc -march=thumb -mcpu=cortex-a8 < %s +; rdar://problem/10137436: sqlite3 miscompile +; +; CHECK: subs +; CHECK: cmp +; CHECK: it + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-ios4.0.0" + +declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind + +define hidden fastcc i32 @sqlite3VdbeExec(i32* %p) nounwind { +entry: + br label %sqlite3VarintLen.exit7424 + +sqlite3VarintLen.exit7424: ; preds = %do.body.i7423 + br label %do.body.i + +do.body.i: ; preds = %do.body.i, %sqlite3VarintLen.exit7424 + br i1 undef, label %do.body.i, label %sqlite3VarintLen.exit + +sqlite3VarintLen.exit: ; preds = %do.body.i + %sub2322 = add i64 undef, undef + br i1 undef, label %too_big, label %if.end2327 + +if.end2327: ; preds = %sqlite3VarintLen.exit + br i1 undef, label %if.end2341, label %no_mem + +if.end2341: ; preds = %if.end2327 + br label %for.body2355 + +for.body2355: ; preds = %for.body2355, %if.end2341 + %add2366 = add nsw i32 undef, undef + br i1 undef, label %for.body2377, label %for.body2355 + +for.body2377: ; preds = %for.body2355 + %conv23836154 = zext i32 %add2366 to i64 + %sub2384 = sub i64 %sub2322, %conv23836154 + %conv2385 = trunc i64 %sub2384 to i32 + %len.0.i = select i1 undef, i32 %conv2385, i32 undef + %sub.i7384 = sub nsw i32 %len.0.i, 0 + %call.i.i7385 = call i8* @__memset_chk(i8* undef, i32 0, i32 %sub.i7384, i32 undef) nounwind + unreachable + +too_big: ; preds = %sqlite3VarintLen.exit + unreachable + +no_mem: ; preds = %if.end2327, %for.body, %entry.no_mem_crit_edge + unreachable + +sqlite3ErrStr.exit: ; preds = %if.then82 + unreachable +} diff --git a/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll new file mode 100644 index 000000000000..c6f4a93def13 --- /dev/null +++ b/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll @@ -0,0 +1,30 @@ +; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s + +; rdar://10196296 +; ARM target specific dag combine created a cycle in DAG. + +define void @t() nounwind ssp { + %1 = load i64* undef, align 4 + %2 = shl i32 5, 0 + %3 = zext i32 %2 to i64 + %4 = and i64 %1, %3 + %5 = lshr i64 %4, undef + switch i64 %5, label %8 [ + i64 0, label %9 + i64 1, label %6 + i64 4, label %9 + i64 5, label %7 + ] + +;