From 59d6cff90eecf31cb3dd860c4e786674cfdd42eb Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Mon, 10 Jun 2013 20:36:52 +0000 Subject: Vendor import of llvm tags/RELEASE_33/final r183502 (effectively, 3.3 release): http://llvm.org/svn/llvm-project/llvm/tags/RELEASE_33/final@183502 --- .../InstCombine/2012-05-27-Negative-Shift-Crash.ll | 16 +-- test/Transforms/InstCombine/add4.ll | 58 ++++++++++ test/Transforms/InstCombine/and-fcmp.ll | 21 ++++ .../Transforms/InstCombine/apint-shift-simplify.ll | 15 ++- test/Transforms/InstCombine/debuginfo.ll | 19 ++-- test/Transforms/InstCombine/fprintf-1.ll | 9 ++ test/Transforms/InstCombine/icmp.ll | 90 +++++++++++++++ test/Transforms/InstCombine/load-cmp.ll | 4 +- test/Transforms/InstCombine/objsize.ll | 108 ------------------ test/Transforms/InstCombine/or.ll | 6 +- test/Transforms/InstCombine/select.ll | 122 +++++++++++++++++++++ test/Transforms/InstCombine/sub-xor.ll | 10 ++ test/Transforms/InstCombine/vec_demanded_elts.ll | 2 +- test/Transforms/InstCombine/vec_extract_2elts.ll | 12 ++ test/Transforms/InstCombine/vec_extract_var_elt.ll | 18 +++ test/Transforms/InstCombine/vec_phi_extract.ll | 27 +++++ test/Transforms/InstCombine/vec_shuffle.ll | 43 -------- 17 files changed, 399 insertions(+), 181 deletions(-) create mode 100644 test/Transforms/InstCombine/add4.ll create mode 100644 test/Transforms/InstCombine/vec_extract_2elts.ll create mode 100644 test/Transforms/InstCombine/vec_extract_var_elt.ll create mode 100644 test/Transforms/InstCombine/vec_phi_extract.ll (limited to 'test/Transforms/InstCombine') diff --git a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll index 2ec0a32ffcbf..ba83fe9ec0ad 100644 --- a/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll +++ b/test/Transforms/InstCombine/2012-05-27-Negative-Shift-Crash.ll @@ -20,10 +20,10 @@ entry: define void @fn4() nounwind uwtable ssp { entry: - %0 = load i32* @d, align 4, !tbaa !0 + %0 = load i32* @d, align 4 %cmp = icmp eq i32 %0, 0 %conv = zext i1 %cmp to i32 - store i32 %conv, i32* @c, align 4, !tbaa !0 + store i32 %conv, i32* @c, align 4 tail call void @fn3(i32 %conv) nounwind ret void } @@ -31,15 +31,15 @@ entry: define void @fn3(i32 %p1) nounwind uwtable ssp { entry: %and = and i32 %p1, 8 - store i32 %and, i32* @e, align 4, !tbaa !0 + store i32 %and, i32* @e, align 4 %sub = add nsw i32 %and, -1 - store i32 %sub, i32* @f, align 4, !tbaa !0 - %0 = load i32* @a, align 4, !tbaa !0 + store i32 %sub, i32* @f, align 4 + %0 = load i32* @a, align 4 %tobool = icmp eq i32 %0, 0 br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %1 = load i32* @b, align 4, !tbaa !0 + %1 = load i32* @b, align 4 %.lobit = lshr i32 %1, 31 %2 = trunc i32 %.lobit to i8 %.not = xor i8 %2, 1 @@ -55,7 +55,3 @@ if.end: ; preds = %if.else, %if.then store i32 %storemerge, i32* @b, align 4 ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/Transforms/InstCombine/add4.ll b/test/Transforms/InstCombine/add4.ll new file mode 100644 index 000000000000..0fc0a6c1ac26 --- /dev/null +++ b/test/Transforms/InstCombine/add4.ll @@ -0,0 +1,58 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +;; Target triple for gep raising case below. +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" +target triple = "i686-apple-darwin8" + +define float @test1(float %A, float %B, i1 %C) { +EntryBlock: + ;; A*(1 - uitofp i1 C) -> select C, 0, A + %cf = uitofp i1 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + ret float %p1 +; CHECK: @test1 +; CHECK: select i1 %C, float -0.000000e+00, float %A +} + +define float @test2(float %A, float %B, i1 %C) { +EntryBlock: + ;; B*(uitofp i1 C) -> select C, B, 0 + %cf = uitofp i1 %C to float + %p2 = fmul fast float %B, %cf + ret float %p2 +; CHECK: @test2 +; CHECK: select i1 %C, float %B, float -0.000000e+00 +} + +define float @test3(float %A, float %B, i1 %C) { +EntryBlock: + ;; A*(1 - uitofp i1 C) + B*(uitofp i1 C) -> select C, A, B + %cf = uitofp i1 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + %p2 = fmul fast float %B, %cf + %s1 = fadd fast float %p1, %p2 + ret float %s1 +; CHECK: @test3 +; CHECK: select i1 %C, float %B, float %A +} + +; PR15952 +define float @test4(float %A, float %B, i32 %C) { + %cf = uitofp i32 %C to float + %mc = fsub float 1.000000e+00, %cf + %p1 = fmul fast float %A, %mc + ret float %p1 +; CHECK: @test4 +; CHECK: uitofp +} + +define float @test5(float %A, float %B, i32 %C) { + %cf = uitofp i32 %C to float + %p2 = fmul fast float %B, %cf + ret float %p2 +; CHECK: @test5 +; CHECK: uitofp +} + diff --git a/test/Transforms/InstCombine/and-fcmp.ll b/test/Transforms/InstCombine/and-fcmp.ll index 40c44c09a8c0..a398307f869e 100644 --- a/test/Transforms/InstCombine/and-fcmp.ll +++ b/test/Transforms/InstCombine/and-fcmp.ll @@ -77,3 +77,24 @@ define zeroext i8 @t7(float %x, float %y) nounwind { ; CHECK: fcmp uno ; CHECK-NOT: fcmp ult } + +; PR15737 +define i1 @t8(float %a, double %b) { + %cmp = fcmp ord float %a, 0.000000e+00 + %cmp1 = fcmp ord double %b, 0.000000e+00 + %and = and i1 %cmp, %cmp1 + ret i1 %and +; CHECK: t8 +; CHECK: fcmp ord +; CHECK: fcmp ord +} + +define <2 x i1> @t9(<2 x float> %a, <2 x double> %b) { + %cmp = fcmp ord <2 x float> %a, zeroinitializer + %cmp1 = fcmp ord <2 x double> %b, zeroinitializer + %and = and <2 x i1> %cmp, %cmp1 + ret <2 x i1> %and +; CHECK: t9 +; CHECK: fcmp ord +; CHECK: fcmp ord +} diff --git a/test/Transforms/InstCombine/apint-shift-simplify.ll b/test/Transforms/InstCombine/apint-shift-simplify.ll index 818ae6659b26..14e895ad4bf6 100644 --- a/test/Transforms/InstCombine/apint-shift-simplify.ll +++ b/test/Transforms/InstCombine/apint-shift-simplify.ll @@ -1,11 +1,14 @@ -; RUN: opt < %s -instcombine -S | \ -; RUN: egrep "shl|lshr|ashr" | count 3 +; RUN: opt < %s -instcombine -S | FileCheck %s define i41 @test0(i41 %A, i41 %B, i41 %C) { %X = shl i41 %A, %C %Y = shl i41 %B, %C %Z = and i41 %X, %Y ret i41 %Z +; CHECK: @test0 +; CHECK-NEXT: and i41 %A, %B +; CHECK-NEXT: shl i41 +; CHECK-NEXT: ret } define i57 @test1(i57 %A, i57 %B, i57 %C) { @@ -13,6 +16,10 @@ define i57 @test1(i57 %A, i57 %B, i57 %C) { %Y = lshr i57 %B, %C %Z = or i57 %X, %Y ret i57 %Z +; CHECK: @test1 +; CHECK-NEXT: or i57 %A, %B +; CHECK-NEXT: lshr i57 +; CHECK-NEXT: ret } define i49 @test2(i49 %A, i49 %B, i49 %C) { @@ -20,4 +27,8 @@ define i49 @test2(i49 %A, i49 %B, i49 %C) { %Y = ashr i49 %B, %C %Z = xor i49 %X, %Y ret i49 %Z +; CHECK: @test2 +; CHECK-NEXT: xor i49 %A, %B +; CHECK-NEXT: ashr i49 +; CHECK-NEXT: ret } diff --git a/test/Transforms/InstCombine/debuginfo.ll b/test/Transforms/InstCombine/debuginfo.ll index cdbcd865117c..a9e3de3b3f7b 100644 --- a/test/Transforms/InstCombine/debuginfo.ll +++ b/test/Transforms/InstCombine/debuginfo.ll @@ -11,18 +11,18 @@ entry: %__dest.addr = alloca i8*, align 8 %__val.addr = alloca i32, align 4 %__len.addr = alloca i64, align 8 - store i8* %__dest, i8** %__dest.addr, align 8, !tbaa !1 + store i8* %__dest, i8** %__dest.addr, align 8 ; CHECK-NOT: call void @llvm.dbg.declare ; CHECK: call void @llvm.dbg.value call void @llvm.dbg.declare(metadata !{i8** %__dest.addr}, metadata !0), !dbg !16 - store i32 %__val, i32* %__val.addr, align 4, !tbaa !17 + store i32 %__val, i32* %__val.addr, align 4 call void @llvm.dbg.declare(metadata !{i32* %__val.addr}, metadata !7), !dbg !18 - store i64 %__len, i64* %__len.addr, align 8, !tbaa !19 + store i64 %__len, i64* %__len.addr, align 8 call void @llvm.dbg.declare(metadata !{i64* %__len.addr}, metadata !9), !dbg !20 - %tmp = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 - %tmp1 = load i32* %__val.addr, align 4, !dbg !21, !tbaa !17 - %tmp2 = load i64* %__len.addr, align 8, !dbg !21, !tbaa !19 - %tmp3 = load i8** %__dest.addr, align 8, !dbg !21, !tbaa !13 + %tmp = load i8** %__dest.addr, align 8, !dbg !21 + %tmp1 = load i32* %__val.addr, align 4, !dbg !21 + %tmp2 = load i64* %__len.addr, align 8, !dbg !21 + %tmp3 = load i8** %__dest.addr, align 8, !dbg !21 %0 = call i64 @llvm.objectsize.i64(i8* %tmp3, i1 false), !dbg !21 %call = call i8* @foo(i8* %tmp, i32 %tmp1, i64 %tmp2, i64 %0), !dbg !21 ret i8* %call, !dbg !21 @@ -43,13 +43,8 @@ entry: !10 = metadata !{i32 589846, metadata !3, metadata !"size_t", metadata !2, i32 80, i64 0, i64 0, i64 0, i32 0, metadata !11} ; [ DW_TAG_typedef ] !11 = metadata !{i32 589846, metadata !3, metadata !"__darwin_size_t", metadata !2, i32 90, i64 0, i64 0, i64 0, i32 0, metadata !12} ; [ DW_TAG_typedef ] !12 = metadata !{i32 786468, metadata !3, metadata !"long unsigned int", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] -!13 = metadata !{metadata !"any pointer", metadata !14} -!14 = metadata !{metadata !"omnipotent char", metadata !15} -!15 = metadata !{metadata !"Simple C/C++ TBAA", null} !16 = metadata !{i32 78, i32 28, metadata !1, null} -!17 = metadata !{metadata !"int", metadata !14} !18 = metadata !{i32 78, i32 40, metadata !1, null} -!19 = metadata !{metadata !"long", metadata !14} !20 = metadata !{i32 78, i32 54, metadata !1, null} !21 = metadata !{i32 80, i32 3, metadata !22, null} !22 = metadata !{i32 786443, metadata !23, i32 80, i32 3, metadata !2, i32 7} ; [ DW_TAG_lexical_block ] diff --git a/test/Transforms/InstCombine/fprintf-1.ll b/test/Transforms/InstCombine/fprintf-1.ll index 39d86b4588cc..e1dc191bd700 100644 --- a/test/Transforms/InstCombine/fprintf-1.ll +++ b/test/Transforms/InstCombine/fprintf-1.ll @@ -78,3 +78,12 @@ define void @test_no_simplify2(%FILE* %fp, double %d) { ret void ; CHECK-NEXT: ret void } + +define i32 @test_no_simplify3(%FILE* %fp) { +; CHECK: @test_no_simplify3 + %fmt = getelementptr [13 x i8]* @hello_world, i32 0, i32 0 + %1 = call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* %fmt) +; CHECK-NEXT: call i32 (%FILE*, i8*, ...)* @fprintf(%FILE* %fp, i8* getelementptr inbounds ([13 x i8]* @hello_world, i32 0, i32 0)) + ret i32 %1 +; CHECK-NEXT: ret i32 %1 +} diff --git a/test/Transforms/InstCombine/icmp.ll b/test/Transforms/InstCombine/icmp.ll index 446c0e01dcaa..c912a576c3d2 100644 --- a/test/Transforms/InstCombine/icmp.ll +++ b/test/Transforms/InstCombine/icmp.ll @@ -886,3 +886,93 @@ define i1 @icmp_mul0_ne0(i32 %x) { %cmp = icmp ne i32 %mul, 0 ret i1 %cmp } + +; CHECK: @icmp_sub1_sge +; CHECK-NEXT: icmp sgt i32 %x, %y +define i1 @icmp_sub1_sge(i32 %x, i32 %y) { + %sub = add nsw i32 %x, -1 + %cmp = icmp sge i32 %sub, %y + ret i1 %cmp +} + +; CHECK: @icmp_add1_sgt +; CHECK-NEXT: icmp sge i32 %x, %y +define i1 @icmp_add1_sgt(i32 %x, i32 %y) { + %add = add nsw i32 %x, 1 + %cmp = icmp sgt i32 %add, %y + ret i1 %cmp +} + +; CHECK: @icmp_sub1_slt +; CHECK-NEXT: icmp sle i32 %x, %y +define i1 @icmp_sub1_slt(i32 %x, i32 %y) { + %sub = add nsw i32 %x, -1 + %cmp = icmp slt i32 %sub, %y + ret i1 %cmp +} + +; CHECK: @icmp_add1_sle +; CHECK-NEXT: icmp slt i32 %x, %y +define i1 @icmp_add1_sle(i32 %x, i32 %y) { + %add = add nsw i32 %x, 1 + %cmp = icmp sle i32 %add, %y + ret i1 %cmp +} + +; CHECK: @icmp_add20_sge_add57 +; CHECK-NEXT: [[ADD:%[a-z0-9]+]] = add nsw i32 %y, 37 +; CHECK-NEXT: icmp sle i32 [[ADD]], %x +define i1 @icmp_add20_sge_add57(i32 %x, i32 %y) { + %1 = add nsw i32 %x, 20 + %2 = add nsw i32 %y, 57 + %cmp = icmp sge i32 %1, %2 + ret i1 %cmp +} + +; CHECK: @icmp_sub57_sge_sub20 +; CHECK-NEXT: [[SUB:%[a-z0-9]+]] = add nsw i32 %x, -37 +; CHECK-NEXT: icmp sge i32 [[SUB]], %y +define i1 @icmp_sub57_sge_sub20(i32 %x, i32 %y) { + %1 = add nsw i32 %x, -57 + %2 = add nsw i32 %y, -20 + %cmp = icmp sge i32 %1, %2 + ret i1 %cmp +} + +; CHECK: @icmp_and_shl_neg_ne_0 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp eq i32 [[AND]], 0 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { + %neg = xor i32 %A, -1 + %shl = shl i32 1, %B + %and = and i32 %shl, %neg + %cmp = icmp ne i32 %and, 0 + ret i1 %cmp +} + +; CHECK: @icmp_and_shl_neg_eq_0 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 1, %B +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], %A +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 0 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { + %neg = xor i32 %A, -1 + %shl = shl i32 1, %B + %and = and i32 %shl, %neg + %cmp = icmp eq i32 %and, 0 + ret i1 %cmp +} + +; CHECK: @icmp_add_and_shr_ne_0 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %X, 240 +; CHECK-NEXT: [[CMP:%[a-z0-9]+]] = icmp ne i32 [[AND]], 224 +; CHECK-NEXT: ret i1 [[CMP]] +define i1 @icmp_add_and_shr_ne_0(i32 %X) { + %shr = lshr i32 %X, 4 + %and = and i32 %shr, 15 + %add = add i32 %and, -14 + %tobool = icmp ne i32 %add, 0 + ret i1 %tobool +} diff --git a/test/Transforms/InstCombine/load-cmp.ll b/test/Transforms/InstCombine/load-cmp.ll index d88188e4109c..869215cb58d4 100644 --- a/test/Transforms/InstCombine/load-cmp.ll +++ b/test/Transforms/InstCombine/load-cmp.ll @@ -100,8 +100,8 @@ define i1 @test8(i32 %X) { %S = icmp eq i16 %R, 0 ret i1 %S ; CHECK: @test8 -; CHECK-NEXT: add i32 %X, -8 -; CHECK-NEXT: icmp ult i32 {{.*}}, 2 +; CHECK-NEXT: and i32 %X, -2 +; CHECK-NEXT: icmp eq i32 {{.*}}, 8 ; CHECK-NEXT: ret i1 } diff --git a/test/Transforms/InstCombine/objsize.ll b/test/Transforms/InstCombine/objsize.ll index 0ead9d123749..122c6501a3f5 100644 --- a/test/Transforms/InstCombine/objsize.ll +++ b/test/Transforms/InstCombine/objsize.ll @@ -257,114 +257,6 @@ return: ret i32 7 } -declare noalias i8* @valloc(i32) nounwind - -; CHECK: @test14 -; CHECK: ret i32 6 -define i32 @test14(i32 %a) nounwind { - switch i32 %a, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %call = tail call noalias i8* @malloc(i32 6) nounwind - br label %sw.epilog - -sw.bb1: - %call2 = tail call noalias i8* @calloc(i32 3, i32 2) nounwind - br label %sw.epilog - -sw.default: - %call3 = tail call noalias i8* @valloc(i32 6) nounwind - br label %sw.epilog - -sw.epilog: - %b.0 = phi i8* [ %call3, %sw.default ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ] - %1 = tail call i32 @llvm.objectsize.i32(i8* %b.0, i1 false) - ret i32 %1 -} - -; CHECK: @test15 -; CHECK: llvm.objectsize -define i32 @test15(i32 %a) nounwind { - switch i32 %a, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %call = tail call noalias i8* @malloc(i32 3) nounwind - br label %sw.epilog - -sw.bb1: - %call2 = tail call noalias i8* @calloc(i32 2, i32 1) nounwind - br label %sw.epilog - -sw.default: - %call3 = tail call noalias i8* @valloc(i32 3) nounwind - br label %sw.epilog - -sw.epilog: - %b.0 = phi i8* [ %call3, %sw.default ], [ %call2, %sw.bb1 ], [ %call, %sw.bb ] - %1 = tail call i32 @llvm.objectsize.i32(i8* %b.0, i1 false) - ret i32 %1 -} - -; CHECK: @test16 -; CHECK: llvm.objectsize -define i32 @test16(i8* %a, i32 %n) nounwind { - %b = alloca [5 x i8], align 1 - %c = alloca [5 x i8], align 1 - switch i32 %n, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - %bp = bitcast [5 x i8]* %b to i8* - br label %sw.epilog - -sw.bb1: - %cp = bitcast [5 x i8]* %c to i8* - br label %sw.epilog - -sw.default: - br label %sw.epilog - -sw.epilog: - %phi = phi i8* [ %a, %sw.default ], [ %cp, %sw.bb1 ], [ %bp, %sw.bb ] - %sz = call i32 @llvm.objectsize.i32(i8* %phi, i1 false) - ret i32 %sz -} - -; CHECK: @test17 -; CHECK: ret i32 5 -define i32 @test17(i32 %n) nounwind { - %b = alloca [5 x i8], align 1 - %c = alloca [5 x i8], align 1 - %bp = bitcast [5 x i8]* %b to i8* - switch i32 %n, label %sw.default [ - i32 1, label %sw.bb - i32 2, label %sw.bb1 - ] - -sw.bb: - br label %sw.epilog - -sw.bb1: - %cp = bitcast [5 x i8]* %c to i8* - br label %sw.epilog - -sw.default: - br label %sw.epilog - -sw.epilog: - %phi = phi i8* [ %bp, %sw.default ], [ %cp, %sw.bb1 ], [ %bp, %sw.bb ] - %sz = call i32 @llvm.objectsize.i32(i8* %phi, i1 false) - ret i32 %sz -} - @globalalias = alias internal [60 x i8]* @a ; CHECK: @test18 diff --git a/test/Transforms/InstCombine/or.ll b/test/Transforms/InstCombine/or.ll index bde2a54048ad..7226bd93996f 100644 --- a/test/Transforms/InstCombine/or.ll +++ b/test/Transforms/InstCombine/or.ll @@ -178,12 +178,12 @@ define i1 @test18(i32 %A) { define i1 @test19(i32 %A) { %B = icmp eq i32 %A, 50 %C = icmp eq i32 %A, 51 - ;; (A-50) < 2 + ;; (A&-2) == 50 %D = or i1 %B, %C ret i1 %D ; CHECK: @test19 -; CHECK: add i32 -; CHECK: icmp ult +; CHECK: and i32 +; CHECK: icmp eq ; CHECK: ret i1 } diff --git a/test/Transforms/InstCombine/select.ll b/test/Transforms/InstCombine/select.ll index cc3aacdce3c8..c72a6f7c49c6 100644 --- a/test/Transforms/InstCombine/select.ll +++ b/test/Transforms/InstCombine/select.ll @@ -863,3 +863,125 @@ while.body: ; CHECK: @test64 ; CHECK-NOT: select } + +; CHECK: @select_icmp_eq_and_1_0_or_2 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 1 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 2 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_1_0_or_2(i32 %x, i32 %y) { + %and = and i32 %x, 1 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 2 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_and_32_0_or_8 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 2 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_32_0_or_8(i32 %x, i32 %y) { + %and = and i32 %x, 32 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 8 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_4096_or_4096 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_4096_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_and_4096_0_or_4096 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 %x, 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[AND]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_and_4096_0_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp eq i32 %and, 0 + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_eq_0_and_1_or_1 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i64 %x, 1 +; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = trunc i64 [[AND]] to i32 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_eq_0_and_1_or_1(i64 %x, i32 %y) { + %and = and i64 %x, 1 + %cmp = icmp eq i64 %and, 0 + %or = or i32 %y, 1 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_4096_or_32 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 7 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 32 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 32 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_4096_or_32(i32 %x, i32 %y) { + %and = and i32 %x, 4096 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 32 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_32_or_4096 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl i32 %x, 7 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[SHL]], 4096 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[AND]], 4096 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_32_or_4096(i32 %x, i32 %y) { + %and = and i32 %x, 32 + %cmp = icmp ne i32 0, %and + %or = or i32 %y, 4096 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} + +; CHECK: @select_icmp_ne_0_and_1073741824_or_8 +; CHECK-NEXT: [[LSHR:%[a-z0-9]+]] = lshr i32 %x, 27 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i32 [[LSHR]], 8 +; CHECK-NEXT: [[TRUNC:%[a-z0-9]+]] = trunc i32 [[AND]] to i8 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i8 [[TRUNC]], 8 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i8 [[XOR]], %y +; CHECK-NEXT: ret i8 [[OR]] +define i8 @select_icmp_ne_0_and_1073741824_or_8(i32 %x, i8 %y) { + %and = and i32 %x, 1073741824 + %cmp = icmp ne i32 0, %and + %or = or i8 %y, 8 + %select = select i1 %cmp, i8 %y, i8 %or + ret i8 %select +} + +; CHECK: @select_icmp_ne_0_and_8_or_1073741824 +; CHECK-NEXT: [[AND:%[a-z0-9]+]] = and i8 %x, 8 +; CHECK-NEXT: [[ZEXT:%[a-z0-9]+]] = zext i8 [[AND]] to i32 +; CHECK-NEXT: [[SHL:%[a-z0-9]+]] = shl nuw nsw i32 [[ZEXT]], 27 +; CHECK-NEXT: [[XOR:%[a-z0-9]+]] = xor i32 [[SHL]], 1073741824 +; CHECK-NEXT: [[OR:%[a-z0-9]+]] = or i32 [[XOR]], %y +; CHECK-NEXT: ret i32 [[OR]] +define i32 @select_icmp_ne_0_and_8_or_1073741824(i8 %x, i32 %y) { + %and = and i8 %x, 8 + %cmp = icmp ne i8 0, %and + %or = or i32 %y, 1073741824 + %select = select i1 %cmp, i32 %y, i32 %or + ret i32 %select +} diff --git a/test/Transforms/InstCombine/sub-xor.ll b/test/Transforms/InstCombine/sub-xor.ll index 279e4aca9de4..1d14852bc803 100644 --- a/test/Transforms/InstCombine/sub-xor.ll +++ b/test/Transforms/InstCombine/sub-xor.ll @@ -35,3 +35,13 @@ define i32 @test3(i32 %x) nounwind { ; CHECK-NEXT: sub i32 73, %and ; CHECK-NEXT: ret } + +define i32 @test4(i32 %x) nounwind { + %sub = xor i32 %x, 2147483648 + %add = add i32 %sub, 42 + ret i32 %add + +; CHECK: @test4 +; CHECK-NEXT: add i32 %x, -2147483606 +; CHECK-NEXT: ret +} diff --git a/test/Transforms/InstCombine/vec_demanded_elts.ll b/test/Transforms/InstCombine/vec_demanded_elts.ll index 2d90750a2f1e..0019a57627cb 100644 --- a/test/Transforms/InstCombine/vec_demanded_elts.ll +++ b/test/Transforms/InstCombine/vec_demanded_elts.ll @@ -196,7 +196,7 @@ define <4 x float> @test_select(float %f, float %g) { ; CHECK-NOT: insertelement ; CHECK: %a3 = insertelement <4 x float> %a0, float 3.000000e+00, i32 3 ; CHECK-NOT: insertelement -; CHECK: shufflevector <4 x float> %a3, <4 x float> , <4 x i32> +; CHECK: %ret = select <4 x i1> , <4 x float> %a3, <4 x float> %a0 = insertelement <4 x float> undef, float %f, i32 0 %a1 = insertelement <4 x float> %a0, float 1.000000e+00, i32 1 %a2 = insertelement <4 x float> %a1, float 2.000000e+00, i32 2 diff --git a/test/Transforms/InstCombine/vec_extract_2elts.ll b/test/Transforms/InstCombine/vec_extract_2elts.ll new file mode 100644 index 000000000000..5972340d60a9 --- /dev/null +++ b/test/Transforms/InstCombine/vec_extract_2elts.ll @@ -0,0 +1,12 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @test(<4 x i32> %v, i64 *%r1, i64 *%r2) { +;CHECK: %1 = extractelement <4 x i32> %v, i32 0 +;CHECK: %2 = zext i32 %1 to i64 + %1 = zext <4 x i32> %v to <4 x i64> + %2 = extractelement <4 x i64> %1, i32 0 + store i64 %2, i64 *%r1 + store i64 %2, i64 *%r2 + ret void +} + diff --git a/test/Transforms/InstCombine/vec_extract_var_elt.ll b/test/Transforms/InstCombine/vec_extract_var_elt.ll new file mode 100644 index 000000000000..3c982873e288 --- /dev/null +++ b/test/Transforms/InstCombine/vec_extract_var_elt.ll @@ -0,0 +1,18 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @test (float %b, <8 x float> * %p) { +; CHECK: extractelement +; CHECK: fptosi + %1 = load <8 x float> * %p + %2 = bitcast <8 x float> %1 to <8 x i32> + %3 = bitcast <8 x i32> %2 to <8 x float> + %a = fptosi <8 x float> %3 to <8 x i32> + %4 = fptosi float %b to i32 + %5 = add i32 %4, -2 + %6 = extractelement <8 x i32> %a, i32 %5 + %7 = insertelement <8 x i32> undef, i32 %6, i32 7 + %8 = sitofp <8 x i32> %7 to <8 x float> + store <8 x float> %8, <8 x float>* %p + ret void +} + diff --git a/test/Transforms/InstCombine/vec_phi_extract.ll b/test/Transforms/InstCombine/vec_phi_extract.ll new file mode 100644 index 000000000000..2f10fc2c1ed2 --- /dev/null +++ b/test/Transforms/InstCombine/vec_phi_extract.ll @@ -0,0 +1,27 @@ +; RUN: opt < %s -instcombine -S | FileCheck %s + +define void @f(i64 %val, i32 %limit, i32 *%ptr) { +;CHECK: %0 = trunc i64 +;CHECK: %1 = phi i32 +entry: + %tempvector = insertelement <16 x i64> undef, i64 %val, i32 0 + %vector = shufflevector <16 x i64> %tempvector, <16 x i64> undef, <16 x i32> zeroinitializer + %0 = add <16 x i64> %vector, + %1 = trunc <16 x i64> %0 to <16 x i32> + br label %loop + +loop: + %2 = phi <16 x i32> [ %1, %entry ], [ %inc, %loop ] + %elt = extractelement <16 x i32> %2, i32 0 + %end = icmp ult i32 %elt, %limit + %3 = add i32 10, %elt + %4 = sext i32 %elt to i64 + %5 = getelementptr i32* %ptr, i64 %4 + store i32 %3, i32* %5 + %inc = add <16 x i32> %2, + br i1 %end, label %loop, label %ret + +ret: + ret void +} + diff --git a/test/Transforms/InstCombine/vec_shuffle.ll b/test/Transforms/InstCombine/vec_shuffle.ll index 14f532195d7c..8f78c2e6bd50 100644 --- a/test/Transforms/InstCombine/vec_shuffle.ll +++ b/test/Transforms/InstCombine/vec_shuffle.ll @@ -153,46 +153,3 @@ define <8 x i8> @test12a(<8 x i8> %tmp6, <8 x i8> %tmp2) nounwind { ret <8 x i8> %tmp3 } -; We should form a shuffle out of a select with constant condition. -define <4 x i16> @test13a(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13a -; CHECK-NEXT: shufflevector <4 x i16> %lhs, <4 x i16> %rhs, <4 x i32> -; CHECK-NEXT: ret - %A = select <4 x i1> , - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13b(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13b -; CHECK-NEXT: ret <4 x i16> %lhs - %A = select <4 x i1> , - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13c(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13c -; CHECK-NEXT: shufflevector <4 x i16> %lhs, <4 x i16> %rhs, <4 x i32> -; CHECK-NEXT: ret - %A = select <4 x i1> , - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13d(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13d -; CHECK: select -; CHECK-NEXT: ret - %A = select <4 x i1> (<4 x i16>, <4 x i16>)* @test13a, <4 x i16>(<4 x i16>, <4 x i16>)* @test13b), i1 true, i1 false>, - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} - -define <4 x i16> @test13e(<4 x i16> %lhs, <4 x i16> %rhs) { -; CHECK: @test13e -; CHECK-NEXT: ret <4 x i16> %rhs - %A = select <4 x i1> , - <4 x i16> %lhs, <4 x i16> %rhs - ret <4 x i16> %A -} -- cgit v1.3