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| author | Kevin Bowling <kbowling@FreeBSD.org> | 2022-05-02 17:29:45 +0000 |
|---|---|---|
| committer | Kevin Bowling <kbowling@FreeBSD.org> | 2022-05-02 17:29:45 +0000 |
| commit | cfac74ea122408b0bd6baec80e6bdce880a42bad (patch) | |
| tree | 3bf54d32ea34839bf7115d29771f1681a6f87e6f | |
| parent | 0ca40de94d392e9ff031ef314e4b5d5935371f88 (diff) | |
| download | ports-cfac74ea122408b0bd6baec80e6bdce880a42bad.tar.gz ports-cfac74ea122408b0bd6baec80e6bdce880a42bad.zip | |
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index 741eb3fdd9c4..3b8aba2764b7 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -6,7 +6,7 @@ CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v11/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= ports@FreeBSD.org +MAINTAINER= kbowling@FreeBSD.org COMMENT= Verilog simulation and synthesis tool LICENSE= GPLv2 |