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authorYuri Victorovich <yuri@FreeBSD.org>2020-01-05 08:08:14 +0000
committerYuri Victorovich <yuri@FreeBSD.org>2020-01-05 08:08:14 +0000
commit07b7dd9f77877e052cec4bb434f6eaeed317ddc9 (patch)
treefb80b1aacd28dfdd7a3a9caa21329c8bb9b1aa24 /cad/Makefile
parent9f2cefb4ee6fe36bc3619966e6a122f7be6c2c5b (diff)
downloadports-07b7dd9f77877e052cec4bb434f6eaeed317ddc9.tar.gz
ports-07b7dd9f77877e052cec4bb434f6eaeed317ddc9.zip
New port: cad/cascade-compiler: Just-In-Time Compiler for Verilog from VMware Research
Notes
Notes: svn path=/head/; revision=522114
Diffstat (limited to 'cad/Makefile')
-rw-r--r--cad/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile
index 2fe49277a517..954ef9d1b545 100644
--- a/cad/Makefile
+++ b/cad/Makefile
@@ -18,6 +18,7 @@
SUBDIR += calculix-ccx
SUBDIR += caneda
SUBDIR += cascade
+ SUBDIR += cascade-compiler
SUBDIR += chipvault
SUBDIR += cura-engine
SUBDIR += digital