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| author | Yuri Victorovich <yuri@FreeBSD.org> | 2020-01-06 00:23:18 +0000 |
|---|---|---|
| committer | Yuri Victorovich <yuri@FreeBSD.org> | 2020-01-06 00:23:18 +0000 |
| commit | 23c1939827adf5d39e54cc1b83cb94d0f48826cc (patch) | |
| tree | d6ed001e48082f06da78c9f31da2b35c82f5921f /cad/Makefile | |
| parent | 22278abb7ff8e8945abe114f9f8f302ca52c61e4 (diff) | |
| download | ports-23c1939827adf5d39e54cc1b83cb94d0f48826cc.tar.gz ports-23c1939827adf5d39e54cc1b83cb94d0f48826cc.zip | |
New port: cad/ujprog: ULX2S/ULX3S FPGA JTAG programmer
Notes
Notes:
svn path=/head/; revision=522176
Diffstat (limited to 'cad/Makefile')
| -rw-r--r-- | cad/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/Makefile b/cad/Makefile index 660936671949..ac7f182d833d 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -106,6 +106,7 @@ SUBDIR += tkgate SUBDIR += tochnog SUBDIR += transcalc + SUBDIR += ujprog SUBDIR += varkon SUBDIR += verilator SUBDIR += verilog-mode.el |