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| author | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2007-07-21 01:21:52 +0000 |
|---|---|---|
| committer | Ying-Chieh Liao <ijliao@FreeBSD.org> | 2007-07-21 01:21:52 +0000 |
| commit | 107f1fb1fcf8564b98fd52a210233be920264e59 (patch) | |
| tree | 6e406445e21b5523bd280456060ee058a3b62794 /cad/gplcver | |
| parent | a50957b0e885ab187dc21d5f8603651b39dd57d3 (diff) | |
| download | ports-107f1fb1fcf8564b98fd52a210233be920264e59.tar.gz ports-107f1fb1fcf8564b98fd52a210233be920264e59.zip | |
'actually' pass maintainership
Notes
Notes:
svn path=/head/; revision=195965
Diffstat (limited to 'cad/gplcver')
| -rw-r--r-- | cad/gplcver/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/gplcver/Makefile b/cad/gplcver/Makefile index 2f9e8f2a37d1..561f9293d846 100644 --- a/cad/gplcver/Makefile +++ b/cad/gplcver/Makefile @@ -12,7 +12,7 @@ CATEGORIES= cad MASTER_SITES= http://www.pragmatic-c.com/gpl-cver/downloads/ DISTNAME= ${PORTNAME}-${PORTVERSION:R}${PORTVERSION:E}.src -MAINTAINER= ijliao@FreeBSD.org +MAINTAINER= thomas@goodking.ca COMMENT= A Verilog HDL simulator USE_BZIP2= yes |