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| author | Dmitry Marakasov <amdmi3@FreeBSD.org> | 2016-05-19 10:21:23 +0000 |
|---|---|---|
| committer | Dmitry Marakasov <amdmi3@FreeBSD.org> | 2016-05-19 10:21:23 +0000 |
| commit | 1d1f878054efdd1171a8cb006e59ad0727610293 (patch) | |
| tree | e4434b89d2dbba884e57f6a6cd3c7fc294554ccf /cad/iverilog | |
| parent | 43b793a6f26531f807a7b7c16a1db3bf6b53f26d (diff) | |
| download | ports-1d1f878054efdd1171a8cb006e59ad0727610293.tar.gz ports-1d1f878054efdd1171a8cb006e59ad0727610293.zip | |
- Fix trailing whitespace in pkg-descrs, categories [a-f]*
Approved by: portmgr blanket
Notes
Notes:
svn path=/head/; revision=415498
Diffstat (limited to 'cad/iverilog')
| -rw-r--r-- | cad/iverilog/pkg-descr | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/cad/iverilog/pkg-descr b/cad/iverilog/pkg-descr index d11b892e0798..2b56cfb04552 100644 --- a/cad/iverilog/pkg-descr +++ b/cad/iverilog/pkg-descr @@ -4,12 +4,12 @@ operates as a compiler, compiling source code written in Verilog compiler can generate C++ code that is compiled and linked with a run time library (called "vvm") then executed as a command to run the simulation. For synthesis, the compiler generates netlists -in the desired format. +in the desired format. The compiler proper is intended to parse and elaborate design descriptions written to the IEEE standard IEEE Std 1364-2000. The standard proper is due to be release towards the middle of the year 2000. This is a fairly large and complex standard, so it will -take some time for it to get there, but that's the goal. +take some time for it to get there, but that's the goal. WWW: http://iverilog.icarus.com/ |