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| author | Chris Rees <crees@FreeBSD.org> | 2012-01-16 21:11:10 +0000 |
|---|---|---|
| committer | Chris Rees <crees@FreeBSD.org> | 2012-01-16 21:11:10 +0000 |
| commit | b81435c1c2d5c5f489ed43cf0fb8eff9ad216f29 (patch) | |
| tree | f0e15ae1dee461d84a0556a46bc837b900a623da /cad/iverilog | |
| parent | 5066df799de5fb60866b980b3a899c08991b10a4 (diff) | |
| download | ports-b81435c1c2d5c5f489ed43cf0fb8eff9ad216f29.tar.gz ports-b81435c1c2d5c5f489ed43cf0fb8eff9ad216f29.zip | |
Update maintainer email address
PR: ports/164211
Submitted by: Niclas Zeising <zeising@daemonic.se> (maintainer)
Notes
Notes:
svn path=/head/; revision=289349
Diffstat (limited to 'cad/iverilog')
| -rw-r--r-- | cad/iverilog/Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile index e0efb2a1948e..ba9746180fd3 100644 --- a/cad/iverilog/Makefile +++ b/cad/iverilog/Makefile @@ -13,7 +13,7 @@ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]$,,}/ \ ftp://ftp.geda.seul.org/pub/geda/dist/ DISTNAME= verilog-${PORTVERSION} -MAINTAINER= niclas.zeising@gmail.com +MAINTAINER= zeising@daemonic.se COMMENT= A Verilog simulation and synthesis tool LICENSE= GPLv2 |