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| author | Baptiste Daroussin <bapt@FreeBSD.org> | 2013-09-20 15:58:41 +0000 |
|---|---|---|
| committer | Baptiste Daroussin <bapt@FreeBSD.org> | 2013-09-20 15:58:41 +0000 |
| commit | 8e91f3161f9c1603aa8633d03faa39d0eb27baf5 (patch) | |
| tree | ad09b4f24df8e2cf74670acb86a133957eb333d0 /cad/p5-Verilog-Perl | |
| parent | 2324655f200dcb66c0a26dc9f7ba34216e5a7c3f (diff) | |
| download | ports-8e91f3161f9c1603aa8633d03faa39d0eb27baf5.tar.gz ports-8e91f3161f9c1603aa8633d03faa39d0eb27baf5.zip | |
Add NO_STAGE all over the place in preparation for the staging support (cat: cad)
Notes
Notes:
svn path=/head/; revision=327711
Diffstat (limited to 'cad/p5-Verilog-Perl')
| -rw-r--r-- | cad/p5-Verilog-Perl/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/cad/p5-Verilog-Perl/Makefile b/cad/p5-Verilog-Perl/Makefile index 9783d6d5f51b..7f9ec722107b 100644 --- a/cad/p5-Verilog-Perl/Makefile +++ b/cad/p5-Verilog-Perl/Makefile @@ -26,6 +26,7 @@ MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \ Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \ Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3 +NO_STAGE= yes .include <bsd.port.pre.mk> post-patch: |