diff options
| author | Yuri Victorovich <yuri@FreeBSD.org> | 2020-03-22 10:02:44 +0000 |
|---|---|---|
| committer | Yuri Victorovich <yuri@FreeBSD.org> | 2020-03-22 10:02:44 +0000 |
| commit | 647c9273f1a542bef2e866b7397529d237df0743 (patch) | |
| tree | 45fd999a07f2eb20ddfb4228d00a7856b5fc0aeb /cad/qflow/pkg-plist | |
| parent | fb4f343c243ce044a0265e2c0084666a1c2d1700 (diff) | |
| download | ports-647c9273f1a542bef2e866b7397529d237df0743.tar.gz ports-647c9273f1a542bef2e866b7397529d237df0743.zip | |
New port: cad/qflow: End-to-end digital synthesis flow for ASIC designs
Notes
Notes:
svn path=/head/; revision=528909
Diffstat (limited to 'cad/qflow/pkg-plist')
| -rw-r--r-- | cad/qflow/pkg-plist | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/cad/qflow/pkg-plist b/cad/qflow/pkg-plist new file mode 100644 index 000000000000..ba4998d0957d --- /dev/null +++ b/cad/qflow/pkg-plist @@ -0,0 +1,115 @@ +bin/qflow +%%DATADIR%%/bin/DEF2Verilog +%%DATADIR%%/bin/addspacers +%%DATADIR%%/bin/blif2BSpice +%%DATADIR%%/bin/blif2Verilog +%%DATADIR%%/bin/blifFanout +%%DATADIR%%/bin/magic +%%DATADIR%%/bin/netgen +%%DATADIR%%/bin/qrouter +%%DATADIR%%/bin/rc2dly +%%DATADIR%%/bin/spice2delay +%%DATADIR%%/bin/vesta +%%DATADIR%%/bin/vlog2Cel +%%DATADIR%%/bin/vlog2Def +%%DATADIR%%/bin/vlog2Spice +%%DATADIR%%/bin/vlog2Verilog +%%DATADIR%%/bin/vlogFanout +%%DATADIR%%/bin/yosys +%%DATADIR%%/bin/yosys-abc +%%DATADIR%%/scripts/addspacers.tcl +%%DATADIR%%/scripts/annotate.tcl +%%DATADIR%%/scripts/arrangepins.tcl +%%DATADIR%%/scripts/blif2cel.tcl +%%DATADIR%%/scripts/blifanno.tcl +%%DATADIR%%/scripts/checkdirs.sh +%%DATADIR%%/scripts/cleanup.sh +%%DATADIR%%/scripts/consoletext.py +%%DATADIR%%/scripts/count_lvs.py +%%DATADIR%%/scripts/decongest.tcl +%%DATADIR%%/scripts/getantennacell.tcl +%%DATADIR%%/scripts/getfillcell.tcl +%%DATADIR%%/scripts/getpowerground.tcl +%%DATADIR%%/scripts/graywolf.sh +%%DATADIR%%/scripts/helpwindow.py +%%DATADIR%%/scripts/magic_db.sh +%%DATADIR%%/scripts/magic_drc.sh +%%DATADIR%%/scripts/magic_gds.sh +%%DATADIR%%/scripts/magic_view.sh +%%DATADIR%%/scripts/netgen_lvs.sh +%%DATADIR%%/scripts/opensta.sh +%%DATADIR%%/scripts/opentimer.sh +%%DATADIR%%/scripts/pinmanager.py +%%DATADIR%%/scripts/place2def.tcl +%%DATADIR%%/scripts/place2lef2.tcl +%%DATADIR%%/scripts/place2net2.tcl +%%DATADIR%%/scripts/powerbus.tcl +%%DATADIR%%/scripts/preproc.py +%%DATADIR%%/scripts/qflow.sh +%%DATADIR%%/scripts/qflow_help.txt +%%DATADIR%%/scripts/qflow_manager.py +%%DATADIR%%/scripts/qrouter.sh +%%DATADIR%%/scripts/removeblocks.tcl +%%DATADIR%%/scripts/replace.sh +%%DATADIR%%/scripts/spi2xspice.py +%%DATADIR%%/scripts/textreport.py +%%DATADIR%%/scripts/tksimpledialog.py +%%DATADIR%%/scripts/tooltip.py +%%DATADIR%%/scripts/vesta.sh +%%DATADIR%%/scripts/ybuffer.tcl +%%DATADIR%%/scripts/yosys.sh +%%DATADIR%%/scripts/ypostproc.tcl +%%DATADIR%%/tech/gscl45nm/gscl45nm.gds +%%DATADIR%%/tech/gscl45nm/gscl45nm.lef +%%DATADIR%%/tech/gscl45nm/gscl45nm.lib +%%DATADIR%%/tech/gscl45nm/gscl45nm.magicrc +%%DATADIR%%/tech/gscl45nm/gscl45nm.par +%%DATADIR%%/tech/gscl45nm/gscl45nm.prm +%%DATADIR%%/tech/gscl45nm/gscl45nm.sh +%%DATADIR%%/tech/gscl45nm/gscl45nm.sp +%%DATADIR%%/tech/gscl45nm/gscl45nm.tech +%%DATADIR%%/tech/gscl45nm/gscl45nm.v +%%DATADIR%%/tech/gscl45nm/gscl45nm_setup.tcl +%%DATADIR%%/tech/osu018/SCN6M_SUBM.10.tech +%%DATADIR%%/tech/osu018/osu018.magicrc +%%DATADIR%%/tech/osu018/osu018.par +%%DATADIR%%/tech/osu018/osu018.prm +%%DATADIR%%/tech/osu018/osu018.sh +%%DATADIR%%/tech/osu018/osu018_setup.tcl +%%DATADIR%%/tech/osu018/osu018_stdcells.gds2 +%%DATADIR%%/tech/osu018/osu018_stdcells.lef +%%DATADIR%%/tech/osu018/osu018_stdcells.lib +%%DATADIR%%/tech/osu018/osu018_stdcells.sp +%%DATADIR%%/tech/osu018/osu018_stdcells.v +%%DATADIR%%/tech/osu035/SCN4M_SUBM.20.tech +%%DATADIR%%/tech/osu035/osu035.magicrc +%%DATADIR%%/tech/osu035/osu035.par +%%DATADIR%%/tech/osu035/osu035.prm +%%DATADIR%%/tech/osu035/osu035.sh +%%DATADIR%%/tech/osu035/osu035_setup.tcl +%%DATADIR%%/tech/osu035/osu035_stdcells.gds2 +%%DATADIR%%/tech/osu035/osu035_stdcells.lef +%%DATADIR%%/tech/osu035/osu035_stdcells.lib +%%DATADIR%%/tech/osu035/osu035_stdcells.sp +%%DATADIR%%/tech/osu035/osu035_stdcells.v +%%DATADIR%%/tech/osu035_redm4/osu035.prm +%%DATADIR%%/tech/osu035_redm4/osu035_redm4.magicrc +%%DATADIR%%/tech/osu035_redm4/osu035_redm4.par +%%DATADIR%%/tech/osu035_redm4/osu035_redm4.sh +%%DATADIR%%/tech/osu035_redm4/osu035_redm4_setup.tcl +%%DATADIR%%/tech/osu035_redm4/osu035_redm4_stdcells.lef +%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.gds2 +%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.lib +%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.sp +%%DATADIR%%/tech/osu035_redm4/osu035_stdcells.v +%%DATADIR%%/tech/osu050/SCN3ME_SUBM.30.tech +%%DATADIR%%/tech/osu050/osu050.magicrc +%%DATADIR%%/tech/osu050/osu050.par +%%DATADIR%%/tech/osu050/osu050.prm +%%DATADIR%%/tech/osu050/osu050.sh +%%DATADIR%%/tech/osu050/osu050_setup.tcl +%%DATADIR%%/tech/osu050/osu050_stdcells.lef +%%DATADIR%%/tech/osu050/osu050_stdcells.sp +%%DATADIR%%/tech/osu050/osu05_stdcells.gds2 +%%DATADIR%%/tech/osu050/osu05_stdcells.lib +%%DATADIR%%/tech/osu050/osu05_stdcells.v |