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| author | Dmitry Marakasov <amdmi3@FreeBSD.org> | 2018-10-19 09:30:10 +0000 |
|---|---|---|
| committer | Dmitry Marakasov <amdmi3@FreeBSD.org> | 2018-10-19 09:30:10 +0000 |
| commit | 6b985f46285d5d4948869a1c9b56a05064f2de41 (patch) | |
| tree | 0704ada39577866292eee886c10273a5cf0f7646 /cad/verilog-mode.el | |
| parent | 1a59ecf3d48fc762715fc250eb25ece7e5aa01ff (diff) | |
| download | ports-6b985f46285d5d4948869a1c9b56a05064f2de41.tar.gz ports-6b985f46285d5d4948869a1c9b56a05064f2de41.zip | |
- Update WWW
Approved by: portmgr blanket
Notes
Notes:
svn path=/head/; revision=482419
Diffstat (limited to 'cad/verilog-mode.el')
| -rw-r--r-- | cad/verilog-mode.el/pkg-descr | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/cad/verilog-mode.el/pkg-descr b/cad/verilog-mode.el/pkg-descr index 21bddb3f6125..77062c89de70 100644 --- a/cad/verilog-mode.el/pkg-descr +++ b/cad/verilog-mode.el/pkg-descr @@ -6,4 +6,4 @@ Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to see what ports will be connected by simulators. -WWW: http://www.veripool.org/wiki/verilog-mode +WWW: https://www.veripool.org/wiki/verilog-mode |