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| author | Sunpoet Po-Chuan Hsieh <sunpoet@FreeBSD.org> | 2021-01-26 13:59:25 +0000 |
|---|---|---|
| committer | Sunpoet Po-Chuan Hsieh <sunpoet@FreeBSD.org> | 2021-01-26 13:59:25 +0000 |
| commit | becaac537e3b0b9adb629868791db4bd22cdbf59 (patch) | |
| tree | cd5714fafbc188aa7dd52153a4b6e9861807f43a /cad | |
| parent | d058df382b09b3f9d007466d720d4e2985d83f53 (diff) | |
| download | ports-becaac537e3b0b9adb629868791db4bd22cdbf59.tar.gz ports-becaac537e3b0b9adb629868791db4bd22cdbf59.zip | |
Fix build with bison 3.7.4
PR: 248911
Exp-run by: antoine
Notes
Notes:
svn path=/head/; revision=562665
Diffstat (limited to 'cad')
| -rw-r--r-- | cad/verilator/files/patch-src-verilog.y | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/cad/verilator/files/patch-src-verilog.y b/cad/verilator/files/patch-src-verilog.y index d58477806498..36fecfa89945 100644 --- a/cad/verilator/files/patch-src-verilog.y +++ b/cad/verilator/files/patch-src-verilog.y @@ -1,14 +1,6 @@ ---- src/verilog.y.orig 2020-07-11 01:58:03 UTC +--- src/verilog.y.orig 2020-08-14 11:38:09 UTC +++ src/verilog.y -@@ -17,6 +17,7 @@ - //************************************************************************* - // clang-format off - -+%define parse.error verbose - %{ - #ifdef NEVER_JUST_FOR_CLANG_FORMAT - } -@@ -31,7 +32,6 @@ +@@ -31,7 +31,6 @@ #include <cstdarg> #include <stack> |