7 files changed, 145 insertions, 0 deletions

diff --git a/emulators/riscv-isa-sim/Makefile b/emulators/riscv-isa-sim/Makefile
new file mode 100644
index 000000000000..54c7ddede028
--- /dev/null
+++ b/emulators/riscv-isa-sim/Makefile
@@ -0,0 +1,50 @@
+# $FreeBSD$
+
+PORTNAME=	riscv-isa-sim
+DISTVERSION=	git
+PORTREVISION=	20170206
+CATEGORIES=	emulators
+
+MAINTAINER=	lwhsu@FreeBSD.org
+COMMENT=	Spike, a RISC-V ISA Simulator
+
+LICENSE=	BSD3CLAUSE
+
+LIB_DEPENDS=	libfesvr.so:emulators/riscv-fesvr
+
+GH_ACCOUNT=	freebsd-riscv
+GH_TAGNAME=	11ec3a3
+
+USES=	compiler:c++11-lang gmake shebangfix
+
+HAS_CONFIGURE=	yes
+SHEBANG_FILES=	scripts/vcs-version.sh
+USE_GITHUB=	yes
+USE_LDCONFIG=	yes
+
+LDFLAGS+=	-L${LOCALBASE}/lib
+CFLAGS+=	-I${LOCALBASE}/include
+
+STRIP_FILES=	bin/spike \
+		bin/spike-dasm \
+		bin/termios-xspike \
+		bin/xspike \
+		lib/libdummy_rocc.so \
+		lib/libriscv.so \
+		lib/libsoftfloat.so \
+		lib/libspike_main.so
+
+post-extract:
+	@${MV} ${WRKSRC}/riscv/insn_template.h ${WRKSRC}/riscv/insn_template.hpp
+
+post-patch:
+	${REINPLACE_CMD} -e \
+	's|[(]install_libs_dir[)]/pkgconfig|(INSTALLDIR)/libdata/pkgconfig|g' \
+	${WRKSRC}/Makefile.in
+
+post-install:
+.	for f in ${STRIP_FILES}
+		${STRIP_CMD} ${STAGEDIR}${PREFIX}/${f}
+.	endfor
+
+.include <bsd.port.mk>
diff --git a/emulators/riscv-isa-sim/distinfo b/emulators/riscv-isa-sim/distinfo
new file mode 100644
index 000000000000..d97f4b0e68ca
--- /dev/null
+++ b/emulators/riscv-isa-sim/distinfo
@@ -0,0 +1,3 @@
+TIMESTAMP = 1486479711
+SHA256 (freebsd-riscv-riscv-isa-sim-git-11ec3a3_GH0.tar.gz) = fc2e48c69477c8b25994cf540f508d0beaec578d972d83c1683ec32eb49d1d85
+SIZE (freebsd-riscv-riscv-isa-sim-git-11ec3a3_GH0.tar.gz) = 187995
diff --git a/emulators/riscv-isa-sim/files/patch-Makefile.in b/emulators/riscv-isa-sim/files/patch-Makefile.in
new file mode 100644
index 000000000000..47b2e8ad21df
--- /dev/null
+++ b/emulators/riscv-isa-sim/files/patch-Makefile.in
@@ -0,0 +1,19 @@
+--- Makefile.in.orig	2016-08-01 15:40:47 UTC
++++ Makefile.in
+@@ -188,13 +188,13 @@ _$(1).cc :
+ 
+ # Build the object files for this subproject
+ 
+-$(2)_pch := $$(patsubst %.h, %.h.gch, $$($(2)_precompiled_hdrs))
++$(2)_pch := $$(patsubst %.hpp, %.h.gch, $$($(2)_precompiled_hdrs))
+ $(2)_objs := $$(patsubst %.cc, %.o, $$($(2)_srcs))
+ $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
+ $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
+ $(2)_deps += $$(patsubst %.o, %.d, $$($(2)_c_objs))
+-$(2)_deps += $$(patsubst %.h, %.h.d, $$($(2)_precompiled_hdrs))
+-$$($(2)_pch) : %.h.gch : %.h
++$(2)_deps += $$(patsubst %.hpp, %.h.d, $$($(2)_precompiled_hdrs))
++$$($(2)_pch) : %.h.gch : %.hpp
+ 	$(COMPILE) $$< -o $$@
+ # If using clang, don't depend (and thus don't build) precompiled headers
+ $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))
diff --git a/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc b/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
new file mode 100644
index 000000000000..8cb0f8c45734
--- /dev/null
+++ b/emulators/riscv-isa-sim/files/patch-riscv_insn__template.cc
@@ -0,0 +1,10 @@
+--- riscv/insn_template.cc.orig	2016-08-01 15:40:47 UTC
++++ riscv/insn_template.cc
+@@ -1,6 +1,6 @@
+ // See LICENSE for license details.
+ 
+-#include "insn_template.h"
++#include "insn_template.hpp"
+ 
+ reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
+ {
diff --git a/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in b/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
new file mode 100644
index 000000000000..1010ac5e72cf
--- /dev/null
+++ b/emulators/riscv-isa-sim/files/patch-riscv_riscv.mk.in
@@ -0,0 +1,18 @@
+--- riscv/riscv.mk.in.orig	2016-08-01 15:40:47 UTC
++++ riscv/riscv.mk.in
+@@ -21,13 +21,13 @@ riscv_hdrs = \
+ 	tracer.h \
+ 	extension.h \
+ 	rocc.h \
+-	insn_template.h \
++	insn_template.hpp \
+ 	mulhi.h \
+ 	gdbserver.h \
+ 	debug_module.h \
+ 
+ riscv_precompiled_hdrs = \
+-	insn_template.h \
++	insn_template.hpp \
+ 
+ riscv_srcs = \
+ 	processor.cc \
diff --git a/emulators/riscv-isa-sim/pkg-descr b/emulators/riscv-isa-sim/pkg-descr
new file mode 100644
index 000000000000..00b305eb3f10
--- /dev/null
+++ b/emulators/riscv-isa-sim/pkg-descr
@@ -0,0 +1,6 @@
+Spike, a RISC-V ISA Simulator
+
+The RISC-V ISA Simulator implements a functional model of one or more RISC-V
+processors.
+
+WWW: https://github.com/freebsd-riscv/riscv-isa-sim
diff --git a/emulators/riscv-isa-sim/pkg-plist b/emulators/riscv-isa-sim/pkg-plist
new file mode 100644
index 000000000000..27e028a459b8
--- /dev/null
+++ b/emulators/riscv-isa-sim/pkg-plist
@@ -0,0 +1,39 @@
+bin/spike
+bin/spike-dasm
+bin/termios-xspike
+bin/xspike
+include/spike/cachesim.h
+include/spike/common.h
+include/spike/config.h
+include/spike/debug_module.h
+include/spike/decode.h
+include/spike/devices.h
+include/spike/disasm.h
+include/spike/encoding.h
+include/spike/extension.h
+include/spike/gdbserver.h
+include/spike/icache.h
+include/spike/insn_list.h
+include/spike/insn_template.hpp
+include/spike/internals.h
+include/spike/memtracer.h
+include/spike/mmu.h
+include/spike/mulhi.h
+include/spike/primitives.h
+include/spike/primitiveTypes.h
+include/spike/processor.h
+include/spike/rocc.h
+include/spike/sim.h
+include/spike/softfloat_types.h
+include/spike/softfloat.h
+include/spike/specialize.h
+include/spike/tracer.h
+include/spike/trap.h
+lib/libdummy_rocc.so
+lib/libriscv.so
+lib/libsoftfloat.so
+lib/libspike_main.so
+libdata/pkgconfig/riscv-dummy_rocc.pc
+libdata/pkgconfig/riscv-riscv.pc
+libdata/pkgconfig/riscv-softfloat.pc
+libdata/pkgconfig/riscv-spike_main.pc