3 files changed, 199 insertions, 0 deletions

diff --git a/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_atomicAccess__bsd__ppc.hpp b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_atomicAccess__bsd__ppc.hpp
new file mode 100644
index 000000000000..b72ed96107c4
--- /dev/null
+++ b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_atomicAccess__bsd__ppc.hpp
@@ -0,0 +1,30 @@
+--- src/hotspot/os_cpu/bsd_ppc/atomicAccess_bsd_ppc.hpp.orig	2026-04-13 10:20:52 UTC
++++ src/hotspot/os_cpu/bsd_ppc/atomicAccess_bsd_ppc.hpp
+@@ -0,0 +1,27 @@
++/*
++ * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
++ * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
++ * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
++ *
++ * This code is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 only, as
++ * published by the Free Software Foundation.
++ *
++ * This code is distributed in the hope that it will be useful, but WITHOUT
++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
++ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
++ * version 2 for more details (a copy is included in the LICENSE file that
++ * accompanied this code).
++ *
++ * You should have received a copy of the GNU General Public License version
++ * 2 along with this work; if not, write to the Free Software Foundation,
++ * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
++ *
++ * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
++ * or visit www.oracle.com if you need additional information or have any
++ * questions.
++ *
++ */
++
++// Including inline assembler functions that are shared between multiple PPC64 platforms.
++#include "atomicAccess_ppc.hpp"
diff --git a/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_orderAccess__bsd__ppc.hpp b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_orderAccess__bsd__ppc.hpp
new file mode 100644
index 000000000000..07877328b08c
--- /dev/null
+++ b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_orderAccess__bsd__ppc.hpp
@@ -0,0 +1,80 @@
+--- src/hotspot/os_cpu/bsd_ppc/orderAccess_bsd_ppc.hpp.orig	2026-04-13 11:00:19 UTC
++++ src/hotspot/os_cpu/bsd_ppc/orderAccess_bsd_ppc.hpp
+@@ -1,6 +1,6 @@
+ /*
+- * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
+- * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
++ * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
++ * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
+  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
+  *
+  * This code is free software; you can redistribute it and/or modify it
+@@ -23,66 +23,5 @@
+  *
+  */
+ 
+-#ifndef OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
+-#define OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
+-
+-// Included in orderAccess.hpp header file.
+-
+-#ifndef PPC64
+-#error "OrderAccess currently only implemented for PPC64"
+-#endif
+-
+-// Compiler version last used for testing: gcc 4.1.2
+-// Please update this information when this file changes
+-
+-// Implementation of class OrderAccess.
+-
+-//
+-// Machine barrier instructions:
+-//
+-// - sync            Two-way memory barrier, aka fence.
+-// - lwsync          orders  Store|Store,
+-//                            Load|Store,
+-//                            Load|Load,
+-//                   but not Store|Load
+-// - eieio           orders  Store|Store
+-// - isync           Invalidates speculatively executed instructions,
+-//                   but isync may complete before storage accesses
+-//                   associated with instructions preceding isync have
+-//                   been performed.
+-//
+-// Semantic barrier instructions:
+-// (as defined in orderAccess.hpp)
+-//
+-// - release         orders Store|Store,       (maps to lwsync)
+-//                           Load|Store
+-// - acquire         orders  Load|Store,       (maps to lwsync)
+-//                           Load|Load
+-// - fence           orders Store|Store,       (maps to sync)
+-//                           Load|Store,
+-//                           Load|Load,
+-//                          Store|Load
+-//
+-
+-#define inlasm_sync()     __asm__ __volatile__ ("sync"   : : : "memory");
+-#define inlasm_lwsync()   __asm__ __volatile__ ("lwsync" : : : "memory");
+-#define inlasm_eieio()    __asm__ __volatile__ ("eieio"  : : : "memory");
+-#define inlasm_isync()    __asm__ __volatile__ ("isync"  : : : "memory");
+-
+-inline void   OrderAccess::loadload()   { inlasm_lwsync(); }
+-inline void   OrderAccess::storestore() { inlasm_lwsync(); }
+-inline void   OrderAccess::loadstore()  { inlasm_lwsync(); }
+-inline void   OrderAccess::storeload()  { inlasm_sync();   }
+-
+-inline void   OrderAccess::acquire()    { inlasm_lwsync(); }
+-inline void   OrderAccess::release()    { inlasm_lwsync(); }
+-inline void   OrderAccess::fence()      { inlasm_sync();   }
+-inline void   OrderAccess::cross_modify_fence_impl()
+-                                        { inlasm_isync();  }
+-
+-#undef inlasm_sync
+-#undef inlasm_lwsync
+-#undef inlasm_eieio
+-#undef inlasm_isync
+-
+-#endif // OS_CPU_BSD_PPC_VM_ORDERACCESS_BSD_PPC_HPP
++// Including inline assembler functions that are shared between multiple PPC64 platforms.
++#include "orderAccess_ppc.hpp"
diff --git a/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_os__bsd__ppc.cpp b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_os__bsd__ppc.cpp
new file mode 100644
index 000000000000..d6c4a26c8093
--- /dev/null
+++ b/java/openjdk26/files/patch-src_hotspot_os__cpu_bsd__ppc_os__bsd__ppc.cpp
@@ -0,0 +1,89 @@
+--- src/hotspot/os_cpu/bsd_ppc/os_bsd_ppc.cpp.orig	2026-04-13 11:53:22 UTC
++++ src/hotspot/os_cpu/bsd_ppc/os_bsd_ppc.cpp
+@@ -179,7 +179,7 @@ intptr_t* os::fetch_bcp_from_context(const void* ucVoi
+   assert(ucVoid != nullptr, "invariant");
+   const ucontext_t* uc = (const ucontext_t*)ucVoid;
+   assert(os::Posix::ucontext_is_interpreter(uc), "invariant");
+-  return reinterpret_cast<intptr_t*>(uc->uc_mcontext.regs->gpr[14]); // R14_bcp
++  return reinterpret_cast<intptr_t*>(uc->uc_mcontext.mc_gpr[14]); // R14_bcp
+ }
+ 
+ frame os::get_sender_for_C_frame(frame* fr) {
+@@ -204,7 +204,6 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, 
+   address stub = nullptr;
+   address pc   = nullptr;
+ 
+-  //%note os_trap_1
+   if (info != nullptr && uc != nullptr && thread != nullptr) {
+     pc = (address) os::Posix::ucontext_get_pc(uc);
+ 
+@@ -279,15 +278,7 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, 
+ 
+       CodeBlob *cb = nullptr;
+       int stop_type = -1;
+-      // Handle signal from NativeJump::patch_verified_entry().
+-      if (sig == SIGILL && nativeInstruction_at(pc)->is_sigill_not_entrant()) {
+-        if (TraceTraps) {
+-          tty->print_cr("trap: not_entrant");
+-        }
+-        stub = SharedRuntime::get_handle_wrong_method_stub();
+-      }
+-
+-      else if ((sig == (USE_POLL_BIT_ONLY ? SIGTRAP : SIGSEGV)) &&
++      if ((sig == (USE_POLL_BIT_ONLY ? SIGTRAP : SIGSEGV)) &&
+                // A bsd-ppc64 kernel before 2.6.6 doesn't set si_addr on some segfaults
+                // in 64bit mode (cf. http://www.kernel.org/pub/bsd/kernel/v2.6/ChangeLog-2.6.6),
+                // especially when we try to read from the safepoint polling page. So the check
+@@ -315,6 +306,17 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, 
+         stub = SharedRuntime::polling_page_return_handler_blob()->entry_point();
+       }
+ 
++      // SIGTRAP-based nmethod entry barriers.
++      else if (sig == SIGTRAP && TrapBasedNMethodEntryBarriers &&
++               nativeInstruction_at(pc)->is_sigtrap_nmethod_entry_barrier() &&
++               CodeCache::contains((void*) pc)) {
++        if (TraceTraps) {
++          tty->print_cr("trap: nmethod entry barrier at " INTPTR_FORMAT " (SIGTRAP)", p2i(pc));
++        }
++        stub = StubRoutines::method_entry_barrier();
++        uc->uc_mcontext.mc_lr = (uintptr_t)(pc + BytesPerInstWord); // emulate call by setting LR
++      }
++
+       // SIGTRAP-based ic miss check in compiled code.
+       else if (sig == SIGTRAP && TrapBasedICMissChecks &&
+                nativeInstruction_at(pc)->is_sigtrap_ic_miss_check()) {
+@@ -408,7 +410,8 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, 
+                         // flushing of icache is not necessary.
+         stub = pc + 4;  // continue with next instruction.
+       }
+-      else if (thread->thread_state() == _thread_in_vm &&
++      else if ((thread->thread_state() == _thread_in_vm ||
++                thread->thread_state() == _thread_in_native) &&
+                sig == SIGBUS && thread->doing_unsafe_access()) {
+         address next_pc = pc + 4;
+         if (UnsafeMemoryAccess::contains_pc(pc)) {
+@@ -419,6 +422,15 @@ bool PosixSignals::pd_hotspot_signal_handler(int sig, 
+         return true;
+       }
+     }
++
++    // jni_fast_Get<Primitive>Field can trap at certain pc's if a GC kicks in
++    // and the heap gets shrunk before the field access.
++    if ((sig == SIGSEGV) || (sig == SIGBUS)) {
++      address addr = JNI_FastGetField::find_slowcase_pc(pc);
++      if (addr != (address)-1) {
++        stub = addr;
++      }
++    }
+   }
+ 
+   if (stub != nullptr) {
+@@ -497,7 +509,7 @@ void os::print_register_info(outputStream *st, const v
+       break;
+     default:
+       st->print("r%-2d=", n-3);
+-      print_location(st, uc->uc_mcontext.mc_gpr[n-3]);
++      print_location(st, (intptr_t)uc->uc_mcontext.mc_gpr[n-3]);
+       break;
+     }
+     ++n;