* Updated to 162

 - Fix memory controller bank channel mappings for Skylake
 - Add decoding for Optane DC persistent memory mode

3 files changed, 14 insertions, 14 deletions

diff --git a/sysutils/mcelog/Makefile b/sysutils/mcelog/Makefile
index 3a10bc737ff5..ca342d265333 100644
--- a/sysutils/mcelog/Makefile
+++ b/sysutils/mcelog/Makefile
@@ -2,7 +2,7 @@
 # $FreeBSD$
 
 PORTNAME=	mcelog
-PORTVERSION=	161
+PORTVERSION=	162
 DISTVERSIONPREFIX=	v
 CATEGORIES=	sysutils
 
diff --git a/sysutils/mcelog/distinfo b/sysutils/mcelog/distinfo
index 306970c73c18..2c067124d1f9 100644
--- a/sysutils/mcelog/distinfo
+++ b/sysutils/mcelog/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1540433813
-SHA256 (andikleen-mcelog-v161_GH0.tar.gz) = 485f5be8f2d5ff8ec1382b54033f75f88b2960ef18f1d87bcf865bb1c094dbd5
-SIZE (andikleen-mcelog-v161_GH0.tar.gz) = 308227
+TIMESTAMP = 1550099603
+SHA256 (andikleen-mcelog-v162_GH0.tar.gz) = 875e98572e86240ea319ab1f69ee6d744eb8b73ac5d700e474f6410d0f52d3fc
+SIZE (andikleen-mcelog-v162_GH0.tar.gz) = 308347
diff --git a/sysutils/mcelog/files/patch-p4.c b/sysutils/mcelog/files/patch-p4.c
index acea7aa5bedc..cf96572ae33f 100644
--- a/sysutils/mcelog/files/patch-p4.c
+++ b/sysutils/mcelog/files/patch-p4.c
@@ -1,6 +1,6 @@
---- p4.c.orig	2016-10-10 22:08:11 UTC
+--- p4.c.orig	2019-02-05 19:57:07 UTC
 +++ p4.c
-@@ -176,8 +176,10 @@ static int decode_mca(u64 status, u64 mi
+@@ -177,8 +177,10 @@ static int decode_mca(u64 status, u64 misc, u64 track,
  		levelnum = mca & 3;
  		level = get_LL_str(levelnum);
  		Wprintf("%s Generic cache hierarchy error\n", level);
@@ -11,7 +11,7 @@
  	} else if (test_prefix(4, mca)) {
  		unsigned levelnum, typenum;
  		char *level, *type;
-@@ -186,8 +188,10 @@ static int decode_mca(u64 status, u64 mi
+@@ -187,8 +189,10 @@ static int decode_mca(u64 status, u64 misc, u64 track,
  		levelnum = (mca & TLB_LL_MASK) >> TLB_LL_SHIFT;
  		level = get_LL_str(levelnum);
  		Wprintf("%s TLB %s Error\n", type, level);
@@ -22,7 +22,7 @@
  	} else if (test_prefix(8, mca)) {
  		unsigned typenum = (mca & CACHE_TT_MASK) >> CACHE_TT_SHIFT;
  		unsigned levelnum = (mca & CACHE_LL_MASK) >> CACHE_LL_SHIFT;
-@@ -196,8 +200,10 @@ static int decode_mca(u64 status, u64 mi
+@@ -197,8 +201,10 @@ static int decode_mca(u64 status, u64 misc, u64 track,
  		Wprintf("%s CACHE %s %s Error\n", type, level,
  				get_RRRR_str((mca & CACHE_RRRR_MASK) >> 
  					      CACHE_RRRR_SHIFT));
@@ -30,10 +30,10 @@
  		if (track == 2)
  			run_yellow_trigger(cpu, typenum, levelnum, type, level,socket);
 +#endif
- 	} else if (test_prefix(10, mca)) {
- 		if (mca == 0x400)
- 			Wprintf("Internal Timer error\n");
-@@ -216,7 +222,9 @@ static int decode_mca(u64 status, u64 mi
+ 	} else if (test_prefix(9, mca) && EXTRACT(mca, 7, 8) == 1) {
+ 		Wprintf("Memory as cache: ");
+ 		decode_memory_controller(mca, bank);
+@@ -220,7 +226,9 @@ static int decode_mca(u64 status, u64 misc, u64 track,
  
  		Wprintf("BUS error: %d %d %s %s %s %s %s\n", socket, cpu,
  			level, pp, rrrr, ii, timeout);
@@ -43,7 +43,7 @@
  		/* IO MCA - reported as bus/interconnect with specific PP,T,RRRR,II,LL values
  		 * and MISCV set. MISC register points to root port that reported the error
  		 * need to cross check with AER logs for more details.
-@@ -232,7 +240,9 @@ static int decode_mca(u64 status, u64 mi
+@@ -236,7 +244,9 @@ static int decode_mca(u64 status, u64 misc, u64 track,
  			fn = EXTRACT(misc, 16, 18);
  			Wprintf("IO MCA reported by root port %x:%02x:%02x.%x\n",
  				seg, bus, dev, fn);
@@ -53,7 +53,7 @@
  		}
  	} else if (test_prefix(7, mca)) {
  		decode_memory_controller(mca, bank);
-@@ -382,19 +392,25 @@ static void decode_thermal(struct mce *l
+@@ -386,19 +396,25 @@ static void decode_thermal(struct mce *log, int cpu)
  
  void decode_intel_mc(struct mce *log, int cputype, int *ismemerr, unsigned size)
  {