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Diffstat (limited to 'cad/py-verilog-parser/pkg-descr')
| -rw-r--r-- | cad/py-verilog-parser/pkg-descr | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/cad/py-verilog-parser/pkg-descr b/cad/py-verilog-parser/pkg-descr new file mode 100644 index 000000000000..24ea3cd3d8fb --- /dev/null +++ b/cad/py-verilog-parser/pkg-descr @@ -0,0 +1,3 @@ +Lark-based parser for Verilog netlists (structural Verilog without behavioral +statements). This is meant to be used to read netlists as generated by HDL logic +synthesizers such as Yosys. |