Commit message (Expand) | Author | Age | Files | Lines | |
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* | Remove WWW entries moved into port Makefiles | Stefan Eßer | 2022-09-07 | 1 | -2/+0 |
* | - Fix trailing whitespace in pkg-descrs, categories [a-f]* | Dmitry Marakasov | 2016-05-19 | 1 | -2/+2 |
* | - Update to version 0.9.5 | Pawel Pekala | 2011-11-04 | 1 | -1/+1 |
* | Fix a few typos in ports/cad. | Jimmy Olgeni | 2010-07-30 | 1 | -1/+1 |
* | add iverilog, a Verilog simulation and synthesis tool | Ying-Chieh Liao | 2001-02-13 | 1 | -0/+15 |