| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cad/iverilog: Update to 11.0 | Niclas Zeising | 2020-10-21 | 1 | -5/+1 |
| * | Update to 10.0 | Niclas Zeising | 2015-10-04 | 1 | -0/+19 |
| * | Cleanup plist | Baptiste Daroussin | 2014-10-20 | 1 | -3/+0 |
| * | Update to 0.9.7. | Niclas Zeising | 2013-12-10 | 1 | -0/+3 |
| * | - Update to 0.9.1. | Stanislav Sedov | 2009-06-09 | 1 | -8/+13 |
| * | - Update to 0.8.7. | Stanislav Sedov | 2009-01-23 | 1 | -5/+6 |
| * | - Update to 0.8.2 | Stanislav Sedov | 2006-10-03 | 1 | -1/+4 |
| * | Update to 0.8 | Tilman Keskinoz | 2004-11-05 | 1 | -0/+1 |
| * | Update to 20031202 snapshot. Summary of changes listed on | Mark Linimon | 2003-12-17 | 1 | -1/+9 |
| * | Maintainer Update to latest snapshot. Changes: add AMD64 support | Mark Linimon | 2003-10-27 | 1 | -0/+1 |
| * | Fix this port and remove BROKEN. | Will Andrews | 2003-05-16 | 1 | -16/+4 |
| * | Update to iverilog 0.7 | Michael C . Wu | 2003-01-31 | 1 | -0/+6 |
| * | Add missing files | Kris Kennaway | 2002-09-19 | 1 | -0/+4 |
| * | add iverilog, a Verilog simulation and synthesis tool | Ying-Chieh Liao | 2001-02-13 | 1 | -0/+19 |
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