index
:
ports
2014Q1
2014Q2
2014Q3
2014Q4
2015Q1
2015Q2
2015Q3
2015Q4
2016Q1
2016Q2
2016Q3
2016Q4
2017Q1
2017Q2
2017Q3
2017Q4
2018Q1
2018Q2
2018Q3
2018Q4
2019Q1
2019Q2
2019Q3
2019Q4
2020Q1
2020Q2
2020Q3
2020Q4
2021Q1
2021Q2
2021Q3
2021Q4
2022Q1
2022Q2
2022Q3
2022Q4
2023Q1
2023Q2
2023Q3
2023Q4
2024Q1
2024Q2
main
FreeBSD ports tree
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
cad
/
nvc
Commit message (
Expand
)
Author
Age
Files
Lines
*
New port: cad/nvc: VHDL compiler and simulator
Yuri Victorovich
2019-10-23
4
-0
/
+124
