| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | cad/surelog: Update 0.0.3924 .> 0.0.3950 | Yuri Victorovich | 2022-01-01 | 1 | -5/+5 |
| * | cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc | Yuri Victorovich | 2021-12-27 | 1 | -0/+13 |
 |
index : ports | |
| FreeBSD ports tree |
| aboutsummaryrefslogtreecommitdiff |