| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | lang/rust: Bump revisions after 1.71.0 | Mikael Urankar | 2023-07-17 | 1 | -0/+1 |
| * | cad/svlint: Update 0.7.2 → 0.8.0 | Yuri Victorovich | 2023-06-27 | 2 | -50/+58 |
| * | lang/rust: Bump revisions after 1.70.0 | Mikael Urankar | 2023-06-09 | 1 | -0/+1 |
| * | cad/svlint: Update 0.7.1 → 0.7.2 | Yuri Victorovich | 2023-06-03 | 2 | -71/+97 |
| * | lang/rust: Bump revisions after 1.69.0 | Mikael Urankar | 2023-04-23 | 1 | -0/+1 |
| * | cad/svlint: Update 0.6.1 → 0.7.1 | Yuri Victorovich | 2023-03-24 | 2 | -146/+124 |
| * | lang/rust: Bump revisions after 1.68.0 | Mikael Urankar | 2023-03-16 | 1 | -1/+1 |
| * | lang/rust: Bump revisions after 1.67.1 | Mikael Urankar | 2023-02-13 | 1 | -1/+1 |
| * | */*: Bump rust (cargo) ports to reflect on WITH_LTO | Daniel Engberg | 2023-01-07 | 1 | -0/+1 |
| * | cad/svlint: New port: SystemVerilog linter | Yuri Victorovich | 2023-01-03 | 3 | -0/+286 |
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