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* lang/rust: Bump revisions after 1.77.0Mikael Urankar2024-03-231-1/+1
* lang/rust: Bump revisions after 1.76.0Mikael Urankar2024-02-191-1/+1
* lang/rust: Bump revisions after 1.75.0Mikael Urankar2024-01-091-0/+1
* cad/svlint: update 0.9.1 → 0.9.2Yuri Victorovich2023-12-282-31/+31
* cad/svlint: update 0.9.0 → 0.9.1Yuri Victorovich2023-12-192-173/+154
* lang/rust: Bump revisions after 1.74.1Mikael Urankar2023-12-081-1/+1
* lang/rust: Bump revisions after 1.73.0Mikael Urankar2023-10-241-1/+1
* lang/rust: Bump revisions after 1.72.0Mikael Urankar2023-09-081-0/+1
* cad/svlint: Update 0.8.0 → 0.9.0Yuri Victorovich2023-08-102-62/+91
* lang/rust: Bump revisions after 1.71.0Mikael Urankar2023-07-171-0/+1
* cad/svlint: Update 0.7.2 → 0.8.0Yuri Victorovich2023-06-272-50/+58
* lang/rust: Bump revisions after 1.70.0Mikael Urankar2023-06-091-0/+1
* cad/svlint: Update 0.7.1 → 0.7.2Yuri Victorovich2023-06-032-71/+97
* lang/rust: Bump revisions after 1.69.0Mikael Urankar2023-04-231-0/+1
* cad/svlint: Update 0.6.1 → 0.7.1Yuri Victorovich2023-03-242-146/+124
* lang/rust: Bump revisions after 1.68.0Mikael Urankar2023-03-161-1/+1
* lang/rust: Bump revisions after 1.67.1Mikael Urankar2023-02-131-1/+1
* */*: Bump rust (cargo) ports to reflect on WITH_LTODaniel Engberg2023-01-071-0/+1
* cad/svlint: New port: SystemVerilog linterYuri Victorovich2023-01-033-0/+286
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