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* lang/rust: Bump revisions after 1.71.0Mikael Urankar2023-07-171-1/+1
* lang/rust: Bump revisions after 1.70.0Mikael Urankar2023-06-091-1/+1
* lang/rust: Bump revisions after 1.69.0Mikael Urankar2023-04-231-1/+1
* lang/rust: Bump revisions after 1.68.0Mikael Urankar2023-03-161-0/+1
* cad/veryl: Update 0.5.2 → 0.5.5Yuri Victorovich2023-03-052-250/+247
* cad/veryl: Update 0.5.0 → 0.5.2Yuri Victorovich2023-03-022-28/+34
* cad/veryl: Update 0.3.4 → 0.5.0Yuri Victorovich2023-02-222-297/+350
* lang/rust: Bump revisions after 1.67.1Mikael Urankar2023-02-131-0/+1
* cad/veryl: Update 0.3.2 → 0.3.4Yuri Victorovich2023-02-102-16/+16
* cad/veryl: Update 0.3.1 → 0.3.2Yuri Victorovich2023-02-072-37/+37
* cad/veryl: Update 0.3.0 → 0.3.1Yuri Victorovich2023-01-312-55/+58
* cad/veryl: Update 0.2.2 → 0.3.0Yuri Victorovich2023-01-292-31/+43
* cad/veryl: Update 0.2.1 → 0.2.2Yuri Victorovich2023-01-262-52/+394
* cad/veryl: Update 0.2.0 -> 0.2.1Yuri Victorovich2023-01-192-10/+13
* cad/veryl: Update 0.1.13 -> 0.2.0Yuri Victorovich2023-01-172-79/+364
* cad/veryl: Update 0.1.8 -> 0.1.13Yuri Victorovich2023-01-122-7/+7
* cad/veryl: Update 0.1.3 -> 0.1.8Yuri Victorovich2023-01-102-35/+40
* */*: Bump rust (cargo) ports to reflect on WITH_LTODaniel Engberg2023-01-071-0/+1
* cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL)Yuri Victorovich2023-01-063-0/+628