2 files changed, 38 insertions, 3 deletions

diff --git a/sys/dev/nvme/nvme.h b/sys/dev/nvme/nvme.h
index 6b2b722922194..8e91c46c254d2 100644
--- a/sys/dev/nvme/nvme.h
+++ b/sys/dev/nvme/nvme.h
@@ -98,12 +98,20 @@
 #define NVME_CAP_HI_REG_CMBS_MASK			(0x1)
 #define NVME_CAP_HI_DSTRD(x) \
 	(((x) >> NVME_CAP_HI_REG_DSTRD_SHIFT) & NVME_CAP_HI_REG_DSTRD_MASK)
-#define NVME_CAP_HI_CSS_NVM(x) \
+#define NVME_CAP_HI_NSSRS(x) \
+	(((x) >> NVME_CAP_HI_REG_NSSRS_SHIFT) & NVME_CAP_HI_REG_NSSRS_MASK)
+#define NVME_CAP_HI_CSS(x) \
 	(((x) >> NVME_CAP_HI_REG_CSS_NVM_SHIFT) & NVME_CAP_HI_REG_CSS_NVM_MASK)
+#define NVME_CAP_HI_BPS(x) \
+	(((x) >> NVME_CAP_HI_REG_BPS_SHIFT) & NVME_CAP_HI_REG_BPS_MASK)
 #define NVME_CAP_HI_MPSMIN(x) \
 	(((x) >> NVME_CAP_HI_REG_MPSMIN_SHIFT) & NVME_CAP_HI_REG_MPSMIN_MASK)
 #define NVME_CAP_HI_MPSMAX(x) \
 	(((x) >> NVME_CAP_HI_REG_MPSMAX_SHIFT) & NVME_CAP_HI_REG_MPSMAX_MASK)
+#define NVME_CAP_HI_PMRS(x) \
+	(((x) >> NVME_CAP_HI_REG_PMRS_SHIFT) & NVME_CAP_HI_REG_PMRS_MASK)
+#define NVME_CAP_HI_CMBS(x) \
+	(((x) >> NVME_CAP_HI_REG_CMBS_SHIFT) & NVME_CAP_HI_REG_CMBS_MASK)
 
 #define NVME_CC_REG_EN_SHIFT				(0)
 #define NVME_CC_REG_EN_MASK				(0x1)
diff --git a/sys/dev/nvme/nvme_ctrlr.c b/sys/dev/nvme/nvme_ctrlr.c
index 1336888074526..437f49b4f5283 100644
--- a/sys/dev/nvme/nvme_ctrlr.c
+++ b/sys/dev/nvme/nvme_ctrlr.c
@@ -1365,7 +1365,7 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
 	struct make_dev_args	md_args;
 	uint32_t	cap_lo;
 	uint32_t	cap_hi;
-	uint32_t	to;
+	uint32_t	to, vs;
 	uint8_t		mpsmin;
 	int		status, timeout_period;
 
@@ -1375,14 +1375,41 @@ nvme_ctrlr_construct(struct nvme_controller *ctrlr, device_t dev)
 	if (bus_get_domain(dev, &ctrlr->domain) != 0)
 		ctrlr->domain = 0;
 
+	cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
+	if (bootverbose) {
+		device_printf(dev, "CapLo: 0x%08x: MQES %u%s%s%s%s, TO %u\n",
+		    cap_lo, NVME_CAP_LO_MQES(cap_lo),
+		    NVME_CAP_LO_CQR(cap_lo) ? ", CQR" : "",
+		    NVME_CAP_LO_AMS(cap_lo) ? ", AMS" : "",
+		    (NVME_CAP_LO_AMS(cap_lo) & 0x1) ? " WRRwUPC" : "",
+		    (NVME_CAP_LO_AMS(cap_lo) & 0x2) ? " VS" : "",
+		    NVME_CAP_LO_TO(cap_lo));
+	}
 	cap_hi = nvme_mmio_read_4(ctrlr, cap_hi);
+	if (bootverbose) {
+		device_printf(dev, "CapHi: 0x%08x: DSTRD %u%s, CSS %x%s, "
+		    "MPSMIN %u, MPSMAX %u %s%s\n", cap_hi,
+		    NVME_CAP_HI_DSTRD(cap_hi),
+		    NVME_CAP_HI_NSSRS(cap_lo) ? ", NSSRS" : "",
+		    NVME_CAP_HI_CSS(cap_hi),
+		    NVME_CAP_HI_BPS(cap_lo) ? ", BPS" : "",
+		    NVME_CAP_HI_MPSMIN(cap_hi),
+		    NVME_CAP_HI_MPSMAX(cap_hi),
+		    NVME_CAP_HI_PMRS(cap_lo) ? ", PMRS" : "",
+		    NVME_CAP_HI_CMBS(cap_lo) ? ", CMBS" : "");
+	}
+	if (bootverbose) {
+		vs = nvme_mmio_read_4(ctrlr, vs);
+		device_printf(dev, "Version: 0x%08x: %d.%d\n", vs,
+		    NVME_MAJOR(vs), NVME_MINOR(vs));
+	}
+
 	ctrlr->dstrd = NVME_CAP_HI_DSTRD(cap_hi) + 2;
 
 	mpsmin = NVME_CAP_HI_MPSMIN(cap_hi);
 	ctrlr->min_page_size = 1 << (12 + mpsmin);
 
 	/* Get ready timeout value from controller, in units of 500ms. */
-	cap_lo = nvme_mmio_read_4(ctrlr, cap_lo);
 	to = NVME_CAP_LO_TO(cap_lo) + 1;
 	ctrlr->ready_timeout_in_ms = to * 500;