vendor/lld/lld-trunk-r351319

13 files changed, 1159 insertions, 141 deletions

diff --git a/ELF/Arch/AArch64.cpp b/ELF/Arch/AArch64.cpp
index c7b3c0801de21..08ffe2a08c0fd 100644
--- a/ELF/Arch/AArch64.cpp
+++ b/ELF/Arch/AArch64.cpp
@@ -41,6 +41,7 @@ public:
                 int32_t Index, unsigned RelOff) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
+  uint32_t getThunkSectionSpacing() const override;
   bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
   bool usesOnlyLowPageBits(RelType Type) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
@@ -57,6 +58,7 @@ AArch64::AArch64() {
   RelativeRel = R_AARCH64_RELATIVE;
   IRelativeRel = R_AARCH64_IRELATIVE;
   GotRel = R_AARCH64_GLOB_DAT;
+  NoneRel = R_AARCH64_NONE;
   PltRel = R_AARCH64_JUMP_SLOT;
   TlsDescRel = R_AARCH64_TLSDESC;
   TlsGotRel = R_AARCH64_TLS_TPREL64;
@@ -66,22 +68,18 @@ AArch64::AArch64() {
   PltHeaderSize = 32;
   DefaultMaxPageSize = 65536;
 
-  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
-  // 1 of the tls structures and the tcb size is 16.
-  TcbSize = 16;
-  NeedsThunks = true;
+  // Align to the 2 MiB page size (known as a superpage or huge page).
+  // FreeBSD automatically promotes 2 MiB-aligned allocations.
+  DefaultImageBase = 0x200000;
 
-  // See comment in Arch/ARM.cpp for a more detailed explanation of
-  // ThunkSectionSpacing. For AArch64 the only branches we are permitted to
-  // Thunk have a range of +/- 128 MiB
-  ThunkSectionSpacing = (128 * 1024 * 1024) - 0x30000;
+  NeedsThunks = true;
 }
 
 RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
                             const uint8_t *Loc) const {
   switch (Type) {
   case R_AARCH64_TLSDESC_ADR_PAGE21:
-    return R_TLSDESC_PAGE;
+    return R_AARCH64_TLSDESC_PAGE;
   case R_AARCH64_TLSDESC_LD64_LO12:
   case R_AARCH64_TLSDESC_ADD_LO12:
     return R_TLSDESC;
@@ -107,13 +105,13 @@ RelExpr AArch64::getRelExpr(RelType Type, const Symbol &S,
   case R_AARCH64_LD_PREL_LO19:
     return R_PC;
   case R_AARCH64_ADR_PREL_PG_HI21:
-    return R_PAGE_PC;
+    return R_AARCH64_PAGE_PC;
   case R_AARCH64_LD64_GOT_LO12_NC:
   case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
     return R_GOT;
   case R_AARCH64_ADR_GOT_PAGE:
   case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
-    return R_GOT_PAGE_PC;
+    return R_AARCH64_GOT_PAGE_PC;
   case R_AARCH64_NONE:
     return R_NONE;
   default:
@@ -125,7 +123,7 @@ RelExpr AArch64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
                                  RelExpr Expr) const {
   if (Expr == R_RELAX_TLS_GD_TO_IE) {
     if (Type == R_AARCH64_TLSDESC_ADR_PAGE21)
-      return R_RELAX_TLS_GD_TO_IE_PAGE_PC;
+      return R_AARCH64_RELAX_TLS_GD_TO_IE_PAGE_PC;
     return R_RELAX_TLS_GD_TO_IE_ABS;
   }
   return Expr;
@@ -156,7 +154,7 @@ RelType AArch64::getDynRel(RelType Type) const {
 }
 
 void AArch64::writeGotPlt(uint8_t *Buf, const Symbol &) const {
-  write64le(Buf, InX::Plt->getVA());
+  write64le(Buf, In.Plt->getVA());
 }
 
 void AArch64::writePltHeader(uint8_t *Buf) const {
@@ -172,8 +170,8 @@ void AArch64::writePltHeader(uint8_t *Buf) const {
   };
   memcpy(Buf, PltData, sizeof(PltData));
 
-  uint64_t Got = InX::GotPlt->getVA();
-  uint64_t Plt = InX::Plt->getVA();
+  uint64_t Got = In.GotPlt->getVA();
+  uint64_t Plt = In.Plt->getVA();
   relocateOne(Buf + 4, R_AARCH64_ADR_PREL_PG_HI21,
               getAArch64Page(Got + 16) - getAArch64Page(Plt + 4));
   relocateOne(Buf + 8, R_AARCH64_LDST64_ABS_LO12_NC, Got + 16);
@@ -208,6 +206,13 @@ bool AArch64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
   return !inBranchRange(Type, BranchAddr, Dst);
 }
 
+uint32_t AArch64::getThunkSectionSpacing() const {
+  // See comment in Arch/ARM.cpp for a more detailed explanation of
+  // getThunkSectionSpacing(). For AArch64 the only branches we are permitted to
+  // Thunk have a range of +/- 128 MiB
+  return (128 * 1024 * 1024) - 0x30000;
+}
+
 bool AArch64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
   if (Type != R_AARCH64_CALL26 && Type != R_AARCH64_JUMP26)
     return true;
@@ -338,7 +343,7 @@ void AArch64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
     or32le(Loc, (Val & 0xFFFC) << 3);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
-    checkInt(Loc, Val, 24, Type);
+    checkUInt(Loc, Val, 24, Type);
     or32AArch64Imm(Loc, Val >> 12);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
diff --git a/ELF/Arch/AMDGPU.cpp b/ELF/Arch/AMDGPU.cpp
index 48b27f23510c8..a7c6c84ceecd4 100644
--- a/ELF/Arch/AMDGPU.cpp
+++ b/ELF/Arch/AMDGPU.cpp
@@ -35,6 +35,7 @@ public:
 AMDGPU::AMDGPU() {
   RelativeRel = R_AMDGPU_RELATIVE64;
   GotRel = R_AMDGPU_ABS64;
+  NoneRel = R_AMDGPU_NONE;
   GotEntrySize = 8;
 }
 
diff --git a/ELF/Arch/ARM.cpp b/ELF/Arch/ARM.cpp
index acf9a615f20b9..120caca671afe 100644
--- a/ELF/Arch/ARM.cpp
+++ b/ELF/Arch/ARM.cpp
@@ -40,6 +40,7 @@ public:
   void addPltHeaderSymbols(InputSection &ISD) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
+  uint32_t getThunkSectionSpacing() const override;
   bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
 };
@@ -50,6 +51,7 @@ ARM::ARM() {
   RelativeRel = R_ARM_RELATIVE;
   IRelativeRel = R_ARM_IRELATIVE;
   GotRel = R_ARM_GLOB_DAT;
+  NoneRel = R_ARM_NONE;
   PltRel = R_ARM_JUMP_SLOT;
   TlsGotRel = R_ARM_TLS_TPOFF32;
   TlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
@@ -59,41 +61,8 @@ ARM::ARM() {
   GotPltEntrySize = 4;
   PltEntrySize = 16;
   PltHeaderSize = 32;
-  TrapInstr = 0xd4d4d4d4;
-  // ARM uses Variant 1 TLS
-  TcbSize = 8;
+  TrapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
   NeedsThunks = true;
-
-  // The placing of pre-created ThunkSections is controlled by the
-  // ThunkSectionSpacing parameter. The aim is to place the
-  // ThunkSection such that all branches from the InputSections prior to the
-  // ThunkSection can reach a Thunk placed at the end of the ThunkSection.
-  // Graphically:
-  // | up to ThunkSectionSpacing .text input sections |
-  // | ThunkSection                                   |
-  // | up to ThunkSectionSpacing .text input sections |
-  // | ThunkSection                                   |
-
-  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARM. This is to
-  // match the most common expected case of a Thumb 2 encoded BL, BLX or B.W
-  // ARM B, BL, BLX range +/- 32MiB
-  // Thumb B.W, BL, BLX range +/- 16MiB
-  // Thumb B<cc>.W range +/- 1MiB
-  // If a branch cannot reach a pre-created ThunkSection a new one will be
-  // created so we can handle the rare cases of a Thumb 2 conditional branch.
-  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
-  // branch range so the end of the ThunkSection is more likely to be within
-  // range of the branch instruction that is furthest away. The value we shorten
-  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
-  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
-  // one of the Thunks going out of range.
-
-  // FIXME: lld assumes that the Thumb BL and BLX encoding permits the J1 and
-  // J2 bits to be used to extend the branch range. On earlier Architectures
-  // such as ARMv4, ARMv5 and ARMv6 (except ARMv6T2) the range is +/- 4MiB. If
-  // support for the earlier encodings is added then when they are used the
-  // ThunkSectionSpacing will need lowering.
-  ThunkSectionSpacing = 0x1000000 - 0x30000;
 }
 
 uint32_t ARM::calcEFlags() const {
@@ -165,6 +134,12 @@ RelExpr ARM::getRelExpr(RelType Type, const Symbol &S,
     return R_NONE;
   case R_ARM_TLS_LE32:
     return R_TLS;
+  case R_ARM_V4BX:
+    // V4BX is just a marker to indicate there's a "bx rN" instruction at the
+    // given address. It can be used to implement a special linker mode which
+    // rewrites ARMv4T inputs to ARMv4. Since we support only ARMv4 input and
+    // not ARMv4 output, we can just ignore it.
+    return R_HINT;
   default:
     return R_ABS;
   }
@@ -177,7 +152,7 @@ RelType ARM::getDynRel(RelType Type) const {
 }
 
 void ARM::writeGotPlt(uint8_t *Buf, const Symbol &) const {
-  write32le(Buf, InX::Plt->getVA());
+  write32le(Buf, In.Plt->getVA());
 }
 
 void ARM::writeIgotPlt(uint8_t *Buf, const Symbol &S) const {
@@ -198,8 +173,8 @@ static void writePltHeaderLong(uint8_t *Buf) {
       0xd4, 0xd4, 0xd4, 0xd4, //     Pad to 32-byte boundary
       0xd4, 0xd4, 0xd4, 0xd4};
   memcpy(Buf, PltData, sizeof(PltData));
-  uint64_t GotPlt = InX::GotPlt->getVA();
-  uint64_t L1 = InX::Plt->getVA() + 8;
+  uint64_t GotPlt = In.GotPlt->getVA();
+  uint64_t L1 = In.Plt->getVA() + 8;
   write32le(Buf + 16, GotPlt - L1 - 8);
 }
 
@@ -217,7 +192,7 @@ void ARM::writePltHeader(uint8_t *Buf) const {
       0xe5bef000, //     ldr pc, [lr, #0x00000NNN] &(.got.plt -L1 - 4)
   };
 
-  uint64_t Offset = InX::GotPlt->getVA() - InX::Plt->getVA() - 4;
+  uint64_t Offset = In.GotPlt->getVA() - In.Plt->getVA() - 4;
   if (!llvm::isUInt<27>(Offset)) {
     // We cannot encode the Offset, use the long form.
     writePltHeaderLong(Buf);
@@ -227,10 +202,10 @@ void ARM::writePltHeader(uint8_t *Buf) const {
   write32le(Buf + 4, PltData[1] | ((Offset >> 20) & 0xff));
   write32le(Buf + 8, PltData[2] | ((Offset >> 12) & 0xff));
   write32le(Buf + 12, PltData[3] | (Offset & 0xfff));
-  write32le(Buf + 16, TrapInstr); // Pad to 32-byte boundary
-  write32le(Buf + 20, TrapInstr);
-  write32le(Buf + 24, TrapInstr);
-  write32le(Buf + 28, TrapInstr);
+  memcpy(Buf + 16, TrapInstr.data(), 4); // Pad to 32-byte boundary
+  memcpy(Buf + 20, TrapInstr.data(), 4);
+  memcpy(Buf + 24, TrapInstr.data(), 4);
+  memcpy(Buf + 28, TrapInstr.data(), 4);
 }
 
 void ARM::addPltHeaderSymbols(InputSection &IS) const {
@@ -279,7 +254,7 @@ void ARM::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
   write32le(Buf + 0, PltData[0] | ((Offset >> 20) & 0xff));
   write32le(Buf + 4, PltData[1] | ((Offset >> 12) & 0xff));
   write32le(Buf + 8, PltData[2] | (Offset & 0xfff));
-  write32le(Buf + 12, TrapInstr); // Pad to 16-byte boundary
+  memcpy(Buf + 12, TrapInstr.data(), 4); // Pad to 16-byte boundary
 }
 
 void ARM::addPltSymbols(InputSection &IS, uint64_t Off) const {
@@ -324,6 +299,40 @@ bool ARM::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
   return false;
 }
 
+uint32_t ARM::getThunkSectionSpacing() const {
+  // The placing of pre-created ThunkSections is controlled by the value
+  // ThunkSectionSpacing returned by getThunkSectionSpacing(). The aim is to
+  // place the ThunkSection such that all branches from the InputSections
+  // prior to the ThunkSection can reach a Thunk placed at the end of the
+  // ThunkSection. Graphically:
+  // | up to ThunkSectionSpacing .text input sections |
+  // | ThunkSection                                   |
+  // | up to ThunkSectionSpacing .text input sections |
+  // | ThunkSection                                   |
+
+  // Pre-created ThunkSections are spaced roughly 16MiB apart on ARMv7. This
+  // is to match the most common expected case of a Thumb 2 encoded BL, BLX or
+  // B.W:
+  // ARM B, BL, BLX range +/- 32MiB
+  // Thumb B.W, BL, BLX range +/- 16MiB
+  // Thumb B<cc>.W range +/- 1MiB
+  // If a branch cannot reach a pre-created ThunkSection a new one will be
+  // created so we can handle the rare cases of a Thumb 2 conditional branch.
+  // We intentionally use a lower size for ThunkSectionSpacing than the maximum
+  // branch range so the end of the ThunkSection is more likely to be within
+  // range of the branch instruction that is furthest away. The value we shorten
+  // ThunkSectionSpacing by is set conservatively to allow us to create 16,384
+  // 12 byte Thunks at any offset in a ThunkSection without risk of a branch to
+  // one of the Thunks going out of range.
+
+  // On Arm the ThunkSectionSpacing depends on the range of the Thumb Branch
+  // range. On earlier Architectures such as ARMv4, ARMv5 and ARMv6 (except
+  // ARMv6T2) the range is +/- 4MiB.
+
+  return (Config->ARMJ1J2BranchEncoding) ? 0x1000000 - 0x30000
+                                         : 0x400000 - 0x7500;
+}
+
 bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
   uint64_t Range;
   uint64_t InstrSize;
@@ -342,7 +351,7 @@ bool ARM::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
     break;
   case R_ARM_THM_JUMP24:
   case R_ARM_THM_CALL:
-    Range = 0x1000000;
+    Range = Config->ARMJ1J2BranchEncoding ? 0x1000000 : 0x400000;
     InstrSize = 2;
     break;
   default:
@@ -447,11 +456,23 @@ void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
     }
     // Bit 12 is 0 for BLX, 1 for BL
     write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
+    if (!Config->ARMJ1J2BranchEncoding) {
+      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
+      // different encoding rules and range due to J1 and J2 always being 1.
+      checkInt(Loc, Val, 23, Type);
+      write16le(Loc,
+                0xf000 |                     // opcode
+                    ((Val >> 12) & 0x07ff)); // imm11
+      write16le(Loc + 2,
+                (read16le(Loc + 2) & 0xd000) | // opcode
+                    0x2800 |                   // J1 == J2 == 1
+                    ((Val >> 1) & 0x07ff));    // imm11
+      break;
+    }
     // Fall through as rest of encoding is the same as B.W
     LLVM_FALLTHROUGH;
   case R_ARM_THM_JUMP24:
     // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
-    // FIXME: Use of I1 and I2 require v6T2ops
     checkInt(Loc, Val, 25, Type);
     write16le(Loc,
               0xf000 |                     // opcode
@@ -470,14 +491,12 @@ void ARM::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
     break;
   case R_ARM_MOVT_ABS:
   case R_ARM_MOVT_PREL:
-    checkInt(Loc, Val, 32, Type);
     write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
                        (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
     break;
   case R_ARM_THM_MOVT_ABS:
   case R_ARM_THM_MOVT_PREL:
     // Encoding T1: A = imm4:i:imm3:imm8
-    checkInt(Loc, Val, 32, Type);
     write16le(Loc,
               0xf2c0 |                     // opcode
                   ((Val >> 17) & 0x0400) | // i
@@ -542,10 +561,19 @@ int64_t ARM::getImplicitAddend(const uint8_t *Buf, RelType Type) const {
                             ((Lo & 0x07ff) << 1));  // imm11:0
   }
   case R_ARM_THM_CALL:
+    if (!Config->ARMJ1J2BranchEncoding) {
+      // Older Arm architectures do not support R_ARM_THM_JUMP24 and have
+      // different encoding rules and range due to J1 and J2 always being 1.
+      uint16_t Hi = read16le(Buf);
+      uint16_t Lo = read16le(Buf + 2);
+      return SignExtend64<22>(((Hi & 0x7ff) << 12) | // imm11
+                              ((Lo & 0x7ff) << 1));  // imm11:0
+      break;
+    }
+    LLVM_FALLTHROUGH;
   case R_ARM_THM_JUMP24: {
     // Encoding B T4, BL T1, BLX T2: A = S:I1:I2:imm10:imm11:0
     // I1 = NOT(J1 EOR S), I2 = NOT(J2 EOR S)
-    // FIXME: I1 and I2 require v6T2ops
     uint16_t Hi = read16le(Buf);
     uint16_t Lo = read16le(Buf + 2);
     return SignExtend64<24>(((Hi & 0x0400) << 14) |                    // S
diff --git a/ELF/Arch/AVR.cpp b/ELF/Arch/AVR.cpp
index 02ac770127b97..637da3778bd20 100644
--- a/ELF/Arch/AVR.cpp
+++ b/ELF/Arch/AVR.cpp
@@ -43,12 +43,15 @@ using namespace lld::elf;
 namespace {
 class AVR final : public TargetInfo {
 public:
+  AVR();
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
 };
 } // namespace
 
+AVR::AVR() { NoneRel = R_AVR_NONE; }
+
 RelExpr AVR::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   return R_ABS;
diff --git a/ELF/Arch/Hexagon.cpp b/ELF/Arch/Hexagon.cpp
index ff5e862bafa2f..b4d33be2ad39b 100644
--- a/ELF/Arch/Hexagon.cpp
+++ b/ELF/Arch/Hexagon.cpp
@@ -9,6 +9,7 @@
 
 #include "InputFiles.h"
 #include "Symbols.h"
+#include "SyntheticSections.h"
 #include "Target.h"
 #include "lld/Common/ErrorHandler.h"
 #include "llvm/BinaryFormat/ELF.h"
@@ -25,15 +26,48 @@ using namespace lld::elf;
 namespace {
 class Hexagon final : public TargetInfo {
 public:
+  Hexagon();
   uint32_t calcEFlags() const override;
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void writePltHeader(uint8_t *Buf) const override;
+  void writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr, uint64_t PltEntryAddr,
+                int32_t Index, unsigned RelOff) const override;
 };
 } // namespace
 
-// Support V60 only at the moment.
-uint32_t Hexagon::calcEFlags() const { return 0x60; }
+Hexagon::Hexagon() {
+  PltRel = R_HEX_JMP_SLOT;
+  RelativeRel = R_HEX_RELATIVE;
+  GotRel = R_HEX_GLOB_DAT;
+  GotEntrySize = 4;
+  // The zero'th GOT entry is reserved for the address of _DYNAMIC.  The
+  // next 3 are reserved for the dynamic loader.
+  GotPltHeaderEntriesNum = 4;
+  GotPltEntrySize = 4;
+
+  PltEntrySize = 16;
+  PltHeaderSize = 32;
+
+  // Hexagon Linux uses 64K pages by default.
+  DefaultMaxPageSize = 0x10000;
+  NoneRel = R_HEX_NONE;
+}
+
+uint32_t Hexagon::calcEFlags() const {
+  assert(!ObjectFiles.empty());
+
+  // The architecture revision must always be equal to or greater than
+  // greatest revision in the list of inputs.
+  uint32_t Ret = 0;
+  for (InputFile *F : ObjectFiles) {
+    uint32_t EFlags = cast<ObjFile<ELF32LE>>(F)->getObj().getHeader()->e_flags;
+    if (EFlags > Ret)
+      Ret = EFlags;
+  }
+  return Ret;
+}
 
 static uint32_t applyMask(uint32_t Mask, uint32_t Data) {
   uint32_t Result = 0;
@@ -53,29 +87,143 @@ static uint32_t applyMask(uint32_t Mask, uint32_t Data) {
 RelExpr Hexagon::getRelExpr(RelType Type, const Symbol &S,
                             const uint8_t *Loc) const {
   switch (Type) {
+  case R_HEX_B9_PCREL:
+  case R_HEX_B9_PCREL_X:
+  case R_HEX_B13_PCREL:
   case R_HEX_B15_PCREL:
   case R_HEX_B15_PCREL_X:
+  case R_HEX_6_PCREL_X:
+  case R_HEX_32_PCREL:
+    return R_PC;
   case R_HEX_B22_PCREL:
+  case R_HEX_PLT_B22_PCREL:
   case R_HEX_B22_PCREL_X:
   case R_HEX_B32_PCREL_X:
-    return R_PC;
+    return R_PLT_PC;
+  case R_HEX_GOT_11_X:
+  case R_HEX_GOT_16_X:
+  case R_HEX_GOT_32_6_X:
+    return R_HEXAGON_GOT;
   default:
     return R_ABS;
   }
 }
 
+static uint32_t findMaskR6(uint32_t Insn) {
+  // There are (arguably too) many relocation masks for the DSP's
+  // R_HEX_6_X type.  The table below is used to select the correct mask
+  // for the given instruction.
+  struct InstructionMask {
+    uint32_t CmpMask;
+    uint32_t RelocMask;
+  };
+
+  static const InstructionMask R6[] = {
+      {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
+      {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
+      {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
+      {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
+      {0x44000000, 0x000020f8}, {0x45000000, 0x000007e0},
+      {0x46000000, 0x000020f8}, {0x47000000, 0x000007e0},
+      {0x6a000000, 0x00001f80}, {0x7c000000, 0x001f2000},
+      {0x9a000000, 0x00000f60}, {0x9b000000, 0x00000f60},
+      {0x9c000000, 0x00000f60}, {0x9d000000, 0x00000f60},
+      {0x9f000000, 0x001f0100}, {0xab000000, 0x0000003f},
+      {0xad000000, 0x0000003f}, {0xaf000000, 0x00030078},
+      {0xd7000000, 0x006020e0}, {0xd8000000, 0x006020e0},
+      {0xdb000000, 0x006020e0}, {0xdf000000, 0x006020e0}};
+
+  // Duplex forms have a fixed mask and parse bits 15:14 are always
+  // zero.  Non-duplex insns will always have at least one bit set in the
+  // parse field.
+  if ((0xC000 & Insn) == 0x0)
+    return 0x03f00000;
+
+  for (InstructionMask I : R6)
+    if ((0xff000000 & Insn) == I.CmpMask)
+      return I.RelocMask;
+
+  error("unrecognized instruction for R_HEX_6 relocation: 0x" +
+        utohexstr(Insn));
+  return 0;
+}
+
+static uint32_t findMaskR8(uint32_t Insn) {
+  if ((0xff000000 & Insn) == 0xde000000)
+    return 0x00e020e8;
+  if ((0xff000000 & Insn) == 0x3c000000)
+    return 0x0000207f;
+  return 0x00001fe0;
+}
+
+static uint32_t findMaskR11(uint32_t Insn) {
+  if ((0xff000000 & Insn) == 0xa1000000)
+    return 0x060020ff;
+  return 0x06003fe0;
+}
+
+static uint32_t findMaskR16(uint32_t Insn) {
+  if ((0xff000000 & Insn) == 0x48000000)
+    return 0x061f20ff;
+  if ((0xff000000 & Insn) == 0x49000000)
+    return 0x061f3fe0;
+  if ((0xff000000 & Insn) == 0x78000000)
+    return 0x00df3fe0;
+  if ((0xff000000 & Insn) == 0xb0000000)
+    return 0x0fe03fe0;
+
+  error("unrecognized instruction for R_HEX_16_X relocation: 0x" +
+        utohexstr(Insn));
+  return 0;
+}
+
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
 
 void Hexagon::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   switch (Type) {
   case R_HEX_NONE:
     break;
+  case R_HEX_6_PCREL_X:
+  case R_HEX_6_X:
+    or32le(Loc, applyMask(findMaskR6(read32le(Loc)), Val));
+    break;
+  case R_HEX_8_X:
+    or32le(Loc, applyMask(findMaskR8(read32le(Loc)), Val));
+    break;
+  case R_HEX_9_X:
+    or32le(Loc, applyMask(0x00003fe0, Val & 0x3f));
+    break;
+  case R_HEX_10_X:
+    or32le(Loc, applyMask(0x00203fe0, Val & 0x3f));
+    break;
+  case R_HEX_11_X:
+  case R_HEX_GOT_11_X:
+    or32le(Loc, applyMask(findMaskR11(read32le(Loc)), Val & 0x3f));
+    break;
   case R_HEX_12_X:
     or32le(Loc, applyMask(0x000007e0, Val));
     break;
+  case R_HEX_16_X: // These relocs only have 6 effective bits.
+  case R_HEX_GOT_16_X:
+    or32le(Loc, applyMask(findMaskR16(read32le(Loc)), Val & 0x3f));
+    break;
+  case R_HEX_32:
+  case R_HEX_32_PCREL:
+    or32le(Loc, Val);
+    break;
   case R_HEX_32_6_X:
+  case R_HEX_GOT_32_6_X:
     or32le(Loc, applyMask(0x0fff3fff, Val >> 6));
     break;
+  case R_HEX_B9_PCREL:
+    or32le(Loc, applyMask(0x003000fe, Val >> 2));
+    break;
+  case R_HEX_B9_PCREL_X:
+    or32le(Loc, applyMask(0x003000fe, Val & 0x3f));
+    break;
+  case R_HEX_B13_PCREL:
+    or32le(Loc, applyMask(0x00202ffe, Val >> 2));
+    break;
   case R_HEX_B15_PCREL:
     or32le(Loc, applyMask(0x00df20fe, Val >> 2));
     break;
@@ -83,6 +231,7 @@ void Hexagon::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
     or32le(Loc, applyMask(0x00df20fe, Val & 0x3f));
     break;
   case R_HEX_B22_PCREL:
+  case R_HEX_PLT_B22_PCREL:
     or32le(Loc, applyMask(0x1ff3ffe, Val >> 2));
     break;
   case R_HEX_B22_PCREL_X:
@@ -91,12 +240,52 @@ void Hexagon::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_HEX_B32_PCREL_X:
     or32le(Loc, applyMask(0x0fff3fff, Val >> 6));
     break;
+  case R_HEX_HI16:
+    or32le(Loc, applyMask(0x00c03fff, Val >> 16));
+    break;
+  case R_HEX_LO16:
+    or32le(Loc, applyMask(0x00c03fff, Val));
+    break;
   default:
     error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
     break;
   }
 }
 
+void Hexagon::writePltHeader(uint8_t *Buf) const {
+  const uint8_t PltData[] = {
+      0x00, 0x40, 0x00, 0x00, // { immext (#0)
+      0x1c, 0xc0, 0x49, 0x6a, //   r28 = add (pc, ##GOT0@PCREL) } # @GOT0
+      0x0e, 0x42, 0x9c, 0xe2, // { r14 -= add (r28, #16)  # offset of GOTn
+      0x4f, 0x40, 0x9c, 0x91, //   r15 = memw (r28 + #8)  # object ID at GOT2
+      0x3c, 0xc0, 0x9c, 0x91, //   r28 = memw (r28 + #4) }# dynamic link at GOT1
+      0x0e, 0x42, 0x0e, 0x8c, // { r14 = asr (r14, #2)    # index of PLTn
+      0x00, 0xc0, 0x9c, 0x52, //   jumpr r28 }            # call dynamic linker
+      0x0c, 0xdb, 0x00, 0x54, // trap0(#0xdb) # bring plt0 into 16byte alignment
+  };
+  memcpy(Buf, PltData, sizeof(PltData));
+
+  // Offset from PLT0 to the GOT.
+  uint64_t Off = In.GotPlt->getVA() - In.Plt->getVA();
+  relocateOne(Buf, R_HEX_B32_PCREL_X, Off);
+  relocateOne(Buf + 4, R_HEX_6_PCREL_X, Off);
+}
+
+void Hexagon::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
+                       uint64_t PltEntryAddr, int32_t Index,
+                       unsigned RelOff) const {
+  const uint8_t Inst[] = {
+      0x00, 0x40, 0x00, 0x00, // { immext (#0)
+      0x0e, 0xc0, 0x49, 0x6a, //   r14 = add (pc, ##GOTn@PCREL) }
+      0x1c, 0xc0, 0x8e, 0x91, // r28 = memw (r14)
+      0x00, 0xc0, 0x9c, 0x52, // jumpr r28
+  };
+  memcpy(Buf, Inst, sizeof(Inst));
+
+  relocateOne(Buf, R_HEX_B32_PCREL_X, GotPltEntryAddr - PltEntryAddr);
+  relocateOne(Buf + 4, R_HEX_6_PCREL_X, GotPltEntryAddr - PltEntryAddr);
+}
+
 TargetInfo *elf::getHexagonTargetInfo() {
   static Hexagon Target;
   return &Target;
diff --git a/ELF/Arch/MSP430.cpp b/ELF/Arch/MSP430.cpp
new file mode 100644
index 0000000000000..fe0c0fe64daf0
--- /dev/null
+++ b/ELF/Arch/MSP430.cpp
@@ -0,0 +1,94 @@
+//===- MSP430.cpp ---------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// The MSP430 is a 16-bit microcontroller RISC architecture. The instruction set
+// has only 27 core instructions orthogonally augmented with a variety
+// of addressing modes for source and destination operands. Entire address space
+// of MSP430 is 64KB (the extended MSP430X architecture is not considered here).
+// A typical MSP430 MCU has several kilobytes of RAM and ROM, plenty
+// of peripherals and is generally optimized for a low power consumption.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Symbols.h"
+#include "Target.h"
+#include "lld/Common/ErrorHandler.h"
+#include "llvm/Object/ELF.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+class MSP430 final : public TargetInfo {
+public:
+  MSP430();
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+} // namespace
+
+MSP430::MSP430() {
+  // mov.b #0, r3
+  TrapInstr = {0x43, 0x43, 0x43, 0x43};
+}
+
+RelExpr MSP430::getRelExpr(RelType Type, const Symbol &S,
+                           const uint8_t *Loc) const {
+  switch (Type) {
+  case R_MSP430_10_PCREL:
+  case R_MSP430_16_PCREL:
+  case R_MSP430_16_PCREL_BYTE:
+  case R_MSP430_2X_PCREL:
+  case R_MSP430_RL_PCREL:
+  case R_MSP430_SYM_DIFF:
+    return R_PC;
+  default:
+    return R_ABS;
+  }
+}
+
+void MSP430::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  switch (Type) {
+  case R_MSP430_8:
+    checkIntUInt(Loc, Val, 8, Type);
+    *Loc = Val;
+    break;
+  case R_MSP430_16:
+  case R_MSP430_16_PCREL:
+  case R_MSP430_16_BYTE:
+  case R_MSP430_16_PCREL_BYTE:
+    checkIntUInt(Loc, Val, 16, Type);
+    write16le(Loc, Val);
+    break;
+  case R_MSP430_32:
+    checkIntUInt(Loc, Val, 32, Type);
+    write32le(Loc, Val);
+    break;
+  case R_MSP430_10_PCREL: {
+    int16_t Offset = ((int16_t)Val >> 1) - 1;
+    checkInt(Loc, Offset, 10, Type);
+    write16le(Loc, (read16le(Loc) & 0xFC00) | (Offset & 0x3FF));
+    break;
+  }
+  default:
+    error(getErrorLocation(Loc) + "unrecognized reloc " + toString(Type));
+  }
+}
+
+TargetInfo *elf::getMSP430TargetInfo() {
+  static MSP430 Target;
+  return &Target;
+}
diff --git a/ELF/Arch/Mips.cpp b/ELF/Arch/Mips.cpp
index dc70401c0b0eb..23b0c1dd8a2d1 100644
--- a/ELF/Arch/Mips.cpp
+++ b/ELF/Arch/Mips.cpp
@@ -53,9 +53,12 @@ template <class ELFT> MIPS<ELFT>::MIPS() {
   PltEntrySize = 16;
   PltHeaderSize = 32;
   CopyRel = R_MIPS_COPY;
+  NoneRel = R_MIPS_NONE;
   PltRel = R_MIPS_JUMP_SLOT;
   NeedsThunks = true;
-  TrapInstr = 0xefefefef;
+
+  // Set `sigrie 1` as a trap instruction.
+  write32(TrapInstr.data(), 0x04170001);
 
   if (ELFT::Is64Bits) {
     RelativeRel = (R_MIPS_64 << 8) | R_MIPS_REL32;
@@ -185,7 +188,7 @@ template <class ELFT> RelType MIPS<ELFT>::getDynRel(RelType Type) const {
 
 template <class ELFT>
 void MIPS<ELFT>::writeGotPlt(uint8_t *Buf, const Symbol &) const {
-  uint64_t VA = InX::Plt->getVA();
+  uint64_t VA = In.Plt->getVA();
   if (isMicroMips())
     VA |= 1;
   write32<ELFT::TargetEndianness>(Buf, VA);
@@ -239,8 +242,8 @@ static void writeMicroRelocation16(uint8_t *Loc, uint64_t V, uint8_t BitsSize,
 template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
   const endianness E = ELFT::TargetEndianness;
   if (isMicroMips()) {
-    uint64_t GotPlt = InX::GotPlt->getVA();
-    uint64_t Plt = InX::Plt->getVA();
+    uint64_t GotPlt = In.GotPlt->getVA();
+    uint64_t Plt = In.Plt->getVA();
     // Overwrite trap instructions written by Writer::writeTrapInstr.
     memset(Buf, 0, PltHeaderSize);
 
@@ -292,7 +295,7 @@ template <class ELFT> void MIPS<ELFT>::writePltHeader(uint8_t *Buf) const {
   write32<E>(Buf + 24, JalrInst); // jalr.hb $25 or jalr $25
   write32<E>(Buf + 28, 0x2718fffe); // subu  $24, $24, 2
 
-  uint64_t GotPlt = InX::GotPlt->getVA();
+  uint64_t GotPlt = In.GotPlt->getVA();
   writeValue<E>(Buf, GotPlt + 0x8000, 16, 16);
   writeValue<E>(Buf + 4, GotPlt, 16, 0);
   writeValue<E>(Buf + 8, GotPlt, 16, 0);
diff --git a/ELF/Arch/PPC.cpp b/ELF/Arch/PPC.cpp
index 20cae0e59cf4e..7673780673413 100644
--- a/ELF/Arch/PPC.cpp
+++ b/ELF/Arch/PPC.cpp
@@ -29,6 +29,7 @@ public:
 } // namespace
 
 PPC::PPC() {
+  NoneRel = R_PPC_NONE;
   GotBaseSymOff = 0x8000;
   GotBaseSymInGotPlt = false;
 }
@@ -36,6 +37,7 @@ PPC::PPC() {
 RelExpr PPC::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   switch (Type) {
+  case R_PPC_REL14:
   case R_PPC_REL24:
   case R_PPC_REL32:
     return R_PC;
@@ -61,6 +63,9 @@ void PPC::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC_REL32:
     write32be(Loc, Val);
     break;
+  case R_PPC_REL14:
+    write32be(Loc, read32be(Loc) | (Val & 0xFFFC));
+    break;
   case R_PPC_PLTREL24:
   case R_PPC_REL24:
     write32be(Loc, read32be(Loc) | (Val & 0x3FFFFFC));
diff --git a/ELF/Arch/PPC64.cpp b/ELF/Arch/PPC64.cpp
index fa3bf6c62a0d3..8a320c9a4e9ef 100644
--- a/ELF/Arch/PPC64.cpp
+++ b/ELF/Arch/PPC64.cpp
@@ -23,12 +23,49 @@ using namespace lld::elf;
 static uint64_t PPC64TocOffset = 0x8000;
 static uint64_t DynamicThreadPointerOffset = 0x8000;
 
+// The instruction encoding of bits 21-30 from the ISA for the Xform and Dform
+// instructions that can be used as part of the initial exec TLS sequence.
+enum XFormOpcd {
+  LBZX = 87,
+  LHZX = 279,
+  LWZX = 23,
+  LDX = 21,
+  STBX = 215,
+  STHX = 407,
+  STWX = 151,
+  STDX = 149,
+  ADD = 266,
+};
+
+enum DFormOpcd {
+  LBZ = 34,
+  LBZU = 35,
+  LHZ = 40,
+  LHZU = 41,
+  LHAU = 43,
+  LWZ = 32,
+  LWZU = 33,
+  LFSU = 49,
+  LD = 58,
+  LFDU = 51,
+  STB = 38,
+  STBU = 39,
+  STH = 44,
+  STHU = 45,
+  STW = 36,
+  STWU = 37,
+  STFSU = 53,
+  STFDU = 55,
+  STD = 62,
+  ADDI = 14
+};
+
 uint64_t elf::getPPC64TocBase() {
   // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
   // TOC starts where the first of these sections starts. We always create a
   // .got when we see a relocation that uses it, so for us the start is always
   // the .got.
-  uint64_t TocVA = InX::Got->getVA();
+  uint64_t TocVA = In.Got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
   // thus permitting a full 64 Kbytes segment. Note that the glibc startup
@@ -37,6 +74,31 @@ uint64_t elf::getPPC64TocBase() {
   return TocVA + PPC64TocOffset;
 }
 
+unsigned elf::getPPC64GlobalEntryToLocalEntryOffset(uint8_t StOther) {
+  // The offset is encoded into the 3 most significant bits of the st_other
+  // field, with some special values described in section 3.4.1 of the ABI:
+  // 0   --> Zero offset between the GEP and LEP, and the function does NOT use
+  //         the TOC pointer (r2). r2 will hold the same value on returning from
+  //         the function as it did on entering the function.
+  // 1   --> Zero offset between the GEP and LEP, and r2 should be treated as a
+  //         caller-saved register for all callers.
+  // 2-6 --> The  binary logarithm of the offset eg:
+  //         2 --> 2^2 = 4 bytes -->  1 instruction.
+  //         6 --> 2^6 = 64 bytes --> 16 instructions.
+  // 7   --> Reserved.
+  uint8_t GepToLep = (StOther >> 5) & 7;
+  if (GepToLep < 2)
+    return 0;
+
+  // The value encoded in the st_other bits is the
+  // log-base-2(offset).
+  if (GepToLep < 7)
+    return 1 << GepToLep;
+
+  error("reserved value of 7 in the 3 most-significant-bits of st_other");
+  return 0;
+}
+
 namespace {
 class PPC64 final : public TargetInfo {
 public:
@@ -51,11 +113,16 @@ public:
   void writeGotHeader(uint8_t *Buf) const override;
   bool needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                   uint64_t BranchAddr, const Symbol &S) const override;
+  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
   RelExpr adjustRelaxExpr(RelType Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+  void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+
+  bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
+                                        uint8_t StOther) const override;
 };
 } // namespace
 
@@ -71,8 +138,64 @@ static uint16_t highera(uint64_t V) { return (V + 0x8000) >> 32; }
 static uint16_t highest(uint64_t V) { return V >> 48; }
 static uint16_t highesta(uint64_t V) { return (V + 0x8000) >> 48; }
 
+// Extracts the 'PO' field of an instruction encoding.
+static uint8_t getPrimaryOpCode(uint32_t Encoding) { return (Encoding >> 26); }
+
+static bool isDQFormInstruction(uint32_t Encoding) {
+  switch (getPrimaryOpCode(Encoding)) {
+  default:
+    return false;
+  case 56:
+    // The only instruction with a primary opcode of 56 is `lq`.
+    return true;
+  case 61:
+    // There are both DS and DQ instruction forms with this primary opcode.
+    // Namely `lxv` and `stxv` are the DQ-forms that use it.
+    // The DS 'XO' bits being set to 01 is restricted to DQ form.
+    return (Encoding & 3) == 0x1;
+  }
+}
+
+static bool isInstructionUpdateForm(uint32_t Encoding) {
+  switch (getPrimaryOpCode(Encoding)) {
+  default:
+    return false;
+  case LBZU:
+  case LHAU:
+  case LHZU:
+  case LWZU:
+  case LFSU:
+  case LFDU:
+  case STBU:
+  case STHU:
+  case STWU:
+  case STFSU:
+  case STFDU:
+    return true;
+    // LWA has the same opcode as LD, and the DS bits is what differentiates
+    // between LD/LDU/LWA
+  case LD:
+  case STD:
+    return (Encoding & 3) == 1;
+  }
+}
+
+// There are a number of places when we either want to read or write an
+// instruction when handling a half16 relocation type. On big-endian the buffer
+// pointer is pointing into the middle of the word we want to extract, and on
+// little-endian it is pointing to the start of the word. These 2 helpers are to
+// simplify reading and writing in that context.
+static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) {
+  write32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0), Instr);
+}
+
+static uint32_t readInstrFromHalf16(const uint8_t *Loc) {
+  return read32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0));
+}
+
 PPC64::PPC64() {
   GotRel = R_PPC64_GLOB_DAT;
+  NoneRel = R_PPC64_NONE;
   PltRel = R_PPC64_JMP_SLOT;
   RelativeRel = R_PPC64_RELATIVE;
   IRelativeRel = R_PPC64_IRELATIVE;
@@ -85,14 +208,14 @@ PPC64::PPC64() {
   GotPltHeaderEntriesNum = 2;
   PltHeaderSize = 60;
   NeedsThunks = true;
-  TcbSize = 8;
-  TlsTpOffset = 0x7000;
 
   TlsModuleIndexRel = R_PPC64_DTPMOD64;
   TlsOffsetRel = R_PPC64_DTPREL64;
 
   TlsGotRel = R_PPC64_TPREL64;
 
+  NeedsMoreStackNonSplit = false;
+
   // We need 64K pages (at least under glibc/Linux, the loader won't
   // set different permissions on a finer granularity than that).
   DefaultMaxPageSize = 65536;
@@ -107,8 +230,7 @@ PPC64::PPC64() {
   // use 0x10000000 as the starting address.
   DefaultImageBase = 0x10000000;
 
-  TrapInstr =
-      (Config->IsLE == sys::IsLittleEndianHost) ? 0x7fe00008 : 0x0800e07f;
+  write32(TrapInstr.data(), 0x7fe00008);
 }
 
 static uint32_t getEFlags(InputFile *File) {
@@ -146,27 +268,29 @@ void PPC64::relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   // bl __tls_get_addr(x@tlsgd)      into      nop
   // nop                             into      addi r3, r3, x@tprel@l
 
-  uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
-
   switch (Type) {
   case R_PPC64_GOT_TLSGD16_HA:
-    write32(Loc - EndianOffset, 0x60000000); // nop
+    writeInstrFromHalf16(Loc, 0x60000000); // nop
     break;
+  case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSGD16_LO:
-    write32(Loc - EndianOffset, 0x3c6d0000); // addis r3, r13
+    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13
     relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
     break;
   case R_PPC64_TLSGD:
     write32(Loc, 0x60000000);     // nop
     write32(Loc + 4, 0x38630000); // addi r3, r3
-    relocateOne(Loc + 4 + EndianOffset, R_PPC64_TPREL16_LO, Val);
+    // Since we are relocating a half16 type relocation and Loc + 4 points to
+    // the start of an instruction we need to advance the buffer by an extra
+    // 2 bytes on BE.
+    relocateOne(Loc + 4 + (Config->EKind == ELF64BEKind ? 2 : 0),
+                R_PPC64_TPREL16_LO, Val);
     break;
   default:
     llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
   }
 }
 
-
 void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   // Reference: 3.7.4.3 of the 64-bit ELF V2 abi supplement.
   // The local dynamic code sequence for a global `x` will look like:
@@ -183,13 +307,12 @@ void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   // bl __tls_get_addr(x@tlsgd)     into      nop
   // nop                            into      addi r3, r3, 4096
 
-  uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
   switch (Type) {
   case R_PPC64_GOT_TLSLD16_HA:
-    write32(Loc - EndianOffset, 0x60000000); // nop
+    writeInstrFromHalf16(Loc, 0x60000000); // nop
     break;
   case R_PPC64_GOT_TLSLD16_LO:
-    write32(Loc - EndianOffset, 0x3c6d0000); // addis r3, r13, 0
+    writeInstrFromHalf16(Loc, 0x3c6d0000); // addis r3, r13, 0
     break;
   case R_PPC64_TLSLD:
     write32(Loc, 0x60000000);     // nop
@@ -212,9 +335,90 @@ void PPC64::relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   }
 }
 
+static unsigned getDFormOp(unsigned SecondaryOp) {
+  switch (SecondaryOp) {
+  case LBZX:
+    return LBZ;
+  case LHZX:
+    return LHZ;
+  case LWZX:
+    return LWZ;
+  case LDX:
+    return LD;
+  case STBX:
+    return STB;
+  case STHX:
+    return STH;
+  case STWX:
+    return STW;
+  case STDX:
+    return STD;
+  case ADD:
+    return ADDI;
+  default:
+    error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    return 0;
+  }
+}
+
+void PPC64::relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const {
+  // The initial exec code sequence for a global `x` will look like:
+  // Instruction                    Relocation                Symbol
+  // addis r9, r2, x@got@tprel@ha   R_PPC64_GOT_TPREL16_HA      x
+  // ld    r9, x@got@tprel@l(r9)    R_PPC64_GOT_TPREL16_LO_DS   x
+  // add r9, r9, x@tls              R_PPC64_TLS                 x
+
+  // Relaxing to local exec entails converting:
+  // addis r9, r2, x@got@tprel@ha       into        nop
+  // ld r9, x@got@tprel@l(r9)           into        addis r9, r13, x@tprel@ha
+  // add r9, r9, x@tls                  into        addi r9, r9, x@tprel@l
+
+  // x@tls R_PPC64_TLS is a relocation which does not compute anything,
+  // it is replaced with r13 (thread pointer).
+
+  // The add instruction in the initial exec sequence has multiple variations
+  // that need to be handled. If we are building an address it will use an add
+  // instruction, if we are accessing memory it will use any of the X-form
+  // indexed load or store instructions.
+
+  unsigned Offset = (Config->EKind == ELF64BEKind) ? 2 : 0;
+  switch (Type) {
+  case R_PPC64_GOT_TPREL16_HA:
+    write32(Loc - Offset, 0x60000000); // nop
+    break;
+  case R_PPC64_GOT_TPREL16_LO_DS:
+  case R_PPC64_GOT_TPREL16_DS: {
+    uint32_t RegNo = read32(Loc - Offset) & 0x03E00000; // bits 6-10
+    write32(Loc - Offset, 0x3C0D0000 | RegNo);          // addis RegNo, r13
+    relocateOne(Loc, R_PPC64_TPREL16_HA, Val);
+    break;
+  }
+  case R_PPC64_TLS: {
+    uint32_t PrimaryOp = getPrimaryOpCode(read32(Loc));
+    if (PrimaryOp != 31)
+      error("unrecognized instruction for IE to LE R_PPC64_TLS");
+    uint32_t SecondaryOp = (read32(Loc) & 0x000007FE) >> 1; // bits 21-30
+    uint32_t DFormOp = getDFormOp(SecondaryOp);
+    write32(Loc, ((DFormOp << 26) | (read32(Loc) & 0x03FFFFFF)));
+    relocateOne(Loc + Offset, R_PPC64_TPREL16_LO, Val);
+    break;
+  }
+  default:
+    llvm_unreachable("unknown relocation for IE to LE");
+    break;
+  }
+}
+
 RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
                           const uint8_t *Loc) const {
   switch (Type) {
+  case R_PPC64_GOT16:
+  case R_PPC64_GOT16_DS:
+  case R_PPC64_GOT16_HA:
+  case R_PPC64_GOT16_HI:
+  case R_PPC64_GOT16_LO:
+  case R_PPC64_GOT16_LO_DS:
+    return R_GOT_OFF;
   case R_PPC64_TOC16:
   case R_PPC64_TOC16_DS:
   case R_PPC64_TOC16_HA:
@@ -224,6 +428,7 @@ RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
     return R_GOTREL;
   case R_PPC64_TOC:
     return R_PPC_TOC;
+  case R_PPC64_REL14:
   case R_PPC64_REL24:
     return R_PPC_CALL_PLT;
   case R_PPC64_REL16_LO:
@@ -279,7 +484,7 @@ RelExpr PPC64::getRelExpr(RelType Type, const Symbol &S,
   case R_PPC64_TLSLD:
     return R_TLSLD_HINT;
   case R_PPC64_TLS:
-    return R_HINT;
+    return R_TLSIE_HINT;
   default:
     return R_ABS;
   }
@@ -308,16 +513,16 @@ void PPC64::writePltHeader(uint8_t *Buf) const {
   // The 'bcl' instruction will set the link register to the address of the
   // following instruction ('mflr r11'). Here we store the offset from that
   // instruction  to the first entry in the GotPlt section.
-  int64_t GotPltOffset = InX::GotPlt->getVA() - (InX::Plt->getVA() + 8);
+  int64_t GotPltOffset = In.GotPlt->getVA() - (In.Plt->getVA() + 8);
   write64(Buf + 52, GotPltOffset);
 }
 
 void PPC64::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
                      uint64_t PltEntryAddr, int32_t Index,
                      unsigned RelOff) const {
- int32_t Offset = PltHeaderSize + Index * PltEntrySize;
- // bl __glink_PLTresolve
- write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
+  int32_t Offset = PltHeaderSize + Index * PltEntrySize;
+  // bl __glink_PLTresolve
+  write32(Buf, 0x48000000 | ((-Offset) & 0x03FFFFFc));
 }
 
 static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
@@ -328,30 +533,36 @@ static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
 
   switch (Type) {
   // TOC biased relocation.
+  case R_PPC64_GOT16:
   case R_PPC64_GOT_TLSGD16:
   case R_PPC64_GOT_TLSLD16:
   case R_PPC64_TOC16:
     return {R_PPC64_ADDR16, TocBiasedVal};
+  case R_PPC64_GOT16_DS:
   case R_PPC64_TOC16_DS:
   case R_PPC64_GOT_TPREL16_DS:
   case R_PPC64_GOT_DTPREL16_DS:
     return {R_PPC64_ADDR16_DS, TocBiasedVal};
+  case R_PPC64_GOT16_HA:
   case R_PPC64_GOT_TLSGD16_HA:
   case R_PPC64_GOT_TLSLD16_HA:
   case R_PPC64_GOT_TPREL16_HA:
   case R_PPC64_GOT_DTPREL16_HA:
   case R_PPC64_TOC16_HA:
     return {R_PPC64_ADDR16_HA, TocBiasedVal};
+  case R_PPC64_GOT16_HI:
   case R_PPC64_GOT_TLSGD16_HI:
   case R_PPC64_GOT_TLSLD16_HI:
   case R_PPC64_GOT_TPREL16_HI:
   case R_PPC64_GOT_DTPREL16_HI:
   case R_PPC64_TOC16_HI:
     return {R_PPC64_ADDR16_HI, TocBiasedVal};
+  case R_PPC64_GOT16_LO:
   case R_PPC64_GOT_TLSGD16_LO:
   case R_PPC64_GOT_TLSLD16_LO:
   case R_PPC64_TOC16_LO:
     return {R_PPC64_ADDR16_LO, TocBiasedVal};
+  case R_PPC64_GOT16_LO_DS:
   case R_PPC64_TOC16_LO_DS:
   case R_PPC64_GOT_TPREL16_LO_DS:
   case R_PPC64_GOT_DTPREL16_LO_DS:
@@ -386,9 +597,27 @@ static std::pair<RelType, uint64_t> toAddr16Rel(RelType Type, uint64_t Val) {
   }
 }
 
+static bool isTocOptType(RelType Type) {
+  switch (Type) {
+  case R_PPC64_GOT16_HA:
+  case R_PPC64_GOT16_LO_DS:
+  case R_PPC64_TOC16_HA:
+  case R_PPC64_TOC16_LO_DS:
+  case R_PPC64_TOC16_LO:
+    return true;
+  default:
+    return false;
+  }
+}
+
 void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
-  // For a TOC-relative relocation, proceed in terms of the corresponding
-  // ADDR16 relocation type.
+  // We need to save the original relocation type to use in diagnostics, and
+  // use the original type to determine if we should toc-optimize the
+  // instructions being relocated.
+  RelType OriginalType = Type;
+  bool ShouldTocOptimize =  isTocOptType(Type);
+  // For dynamic thread pointer relative, toc-relative, and got-indirect
+  // relocations, proceed in terms of the corresponding ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
@@ -401,18 +630,25 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   }
   case R_PPC64_ADDR16:
   case R_PPC64_TPREL16:
-    checkInt(Loc, Val, 16, Type);
+    checkInt(Loc, Val, 16, OriginalType);
     write16(Loc, Val);
     break;
   case R_PPC64_ADDR16_DS:
-  case R_PPC64_TPREL16_DS:
-    checkInt(Loc, Val, 16, Type);
-    write16(Loc, (read16(Loc) & 3) | (Val & ~3));
-    break;
+  case R_PPC64_TPREL16_DS: {
+    checkInt(Loc, Val, 16, OriginalType);
+    // DQ-form instructions use bits 28-31 as part of the instruction encoding
+    // DS-form instructions only use bits 30-31.
+    uint16_t Mask = isDQFormInstruction(readInstrFromHalf16(Loc)) ? 0xF : 0x3;
+    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
+    write16(Loc, (read16(Loc) & Mask) | lo(Val));
+  } break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
   case R_PPC64_TPREL16_HA:
-    write16(Loc, ha(Val));
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0)
+      writeInstrFromHalf16(Loc, 0x60000000);
+    else
+      write16(Loc, ha(Val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
@@ -438,12 +674,40 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC64_ADDR16_LO:
   case R_PPC64_REL16_LO:
   case R_PPC64_TPREL16_LO:
+    // When the high-adjusted part of a toc relocation evalutes to 0, it is
+    // changed into a nop. The lo part then needs to be updated to use the
+    // toc-pointer register r2, as the base register.
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
+      uint32_t Instr = readInstrFromHalf16(Loc);
+      if (isInstructionUpdateForm(Instr))
+        error(getErrorLocation(Loc) +
+              "can't toc-optimize an update instruction: 0x" +
+              utohexstr(Instr));
+      Instr = (Instr & 0xFFE00000) | 0x00020000;
+      writeInstrFromHalf16(Loc, Instr);
+    }
     write16(Loc, lo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
-  case R_PPC64_TPREL16_LO_DS:
-    write16(Loc, (read16(Loc) & 3) | (lo(Val) & ~3));
-    break;
+  case R_PPC64_TPREL16_LO_DS: {
+    // DQ-form instructions use bits 28-31 as part of the instruction encoding
+    // DS-form instructions only use bits 30-31.
+    uint32_t Inst = readInstrFromHalf16(Loc);
+    uint16_t Mask = isDQFormInstruction(Inst) ? 0xF : 0x3;
+    checkAlignment(Loc, lo(Val), Mask + 1, OriginalType);
+    if (Config->TocOptimize && ShouldTocOptimize && ha(Val) == 0) {
+      // When the high-adjusted part of a toc relocation evalutes to 0, it is
+      // changed into a nop. The lo part then needs to be updated to use the toc
+      // pointer register r2, as the base register.
+      if (isInstructionUpdateForm(Inst))
+        error(getErrorLocation(Loc) +
+              "Can't toc-optimize an update instruction: 0x" +
+              Twine::utohexstr(Inst));
+      Inst = (Inst & 0xFFE0000F) | 0x00020000;
+      writeInstrFromHalf16(Loc, Inst);
+    }
+    write16(Loc, (read16(Loc) & Mask) | lo(Val));
+  } break;
   case R_PPC64_ADDR32:
   case R_PPC64_REL32:
     checkInt(Loc, Val, 32, Type);
@@ -454,9 +718,17 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC64_TOC:
     write64(Loc, Val);
     break;
+  case R_PPC64_REL14: {
+    uint32_t Mask = 0x0000FFFC;
+    checkInt(Loc, Val, 16, Type);
+    checkAlignment(Loc, Val, 4, Type);
+    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
+    break;
+  }
   case R_PPC64_REL24: {
     uint32_t Mask = 0x03FFFFFC;
-    checkInt(Loc, Val, 24, Type);
+    checkInt(Loc, Val, 26, Type);
+    checkAlignment(Loc, Val, 4, Type);
     write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
     break;
   }
@@ -470,9 +742,30 @@ void PPC64::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
 
 bool PPC64::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
                        uint64_t BranchAddr, const Symbol &S) const {
-  // If a function is in the plt it needs to be called through
-  // a call stub.
-  return Type == R_PPC64_REL24 && S.isInPlt();
+  if (Type != R_PPC64_REL14 && Type != R_PPC64_REL24)
+    return false;
+
+  // If a function is in the Plt it needs to be called with a call-stub.
+  if (S.isInPlt())
+    return true;
+
+  // If a symbol is a weak undefined and we are compiling an executable
+  // it doesn't need a range-extending thunk since it can't be called.
+  if (S.isUndefWeak() && !Config->Shared)
+    return false;
+
+  // If the offset exceeds the range of the branch type then it will need
+  // a range-extending thunk.
+  return !inBranchRange(Type, BranchAddr, S.getVA());
+}
+
+bool PPC64::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
+  int64_t Offset = Dst - Src;
+  if (Type == R_PPC64_REL14)
+    return isInt<16>(Offset);
+  if (Type == R_PPC64_REL24)
+    return isInt<26>(Offset);
+  llvm_unreachable("unsupported relocation type used in branch");
 }
 
 RelExpr PPC64::adjustRelaxExpr(RelType Type, const uint8_t *Data,
@@ -511,9 +804,8 @@ void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   case R_PPC64_GOT_TLSGD16_LO: {
     // Relax from addi  r3, rA, sym@got@tlsgd@l to
     //            ld r3, sym@got@tprel@l(rA)
-    uint32_t EndianOffset = Config->EKind == ELF64BEKind ? 2U : 0U;
-    uint32_t InputRegister = (read32(Loc - EndianOffset) & (0x1f << 16));
-    write32(Loc - EndianOffset, 0xE8600000 | InputRegister);
+    uint32_t InputRegister = (readInstrFromHalf16(Loc) & (0x1f << 16));
+    writeInstrFromHalf16(Loc, 0xE8600000 | InputRegister);
     relocateOne(Loc, R_PPC64_GOT_TPREL16_LO_DS, Val);
     return;
   }
@@ -526,6 +818,113 @@ void PPC64::relaxTlsGdToIe(uint8_t *Loc, RelType Type, uint64_t Val) const {
   }
 }
 
+// The prologue for a split-stack function is expected to look roughly
+// like this:
+//    .Lglobal_entry_point:
+//      # TOC pointer initalization.
+//      ...
+//    .Llocal_entry_point:
+//      # load the __private_ss member of the threads tcbhead.
+//      ld r0,-0x7000-64(r13)
+//      # subtract the functions stack size from the stack pointer.
+//      addis r12, r1, ha(-stack-frame size)
+//      addi  r12, r12, l(-stack-frame size)
+//      # compare needed to actual and branch to allocate_more_stack if more
+//      # space is needed, otherwise fallthrough to 'normal' function body.
+//      cmpld cr7,r12,r0
+//      blt- cr7, .Lallocate_more_stack
+//
+// -) The allocate_more_stack block might be placed after the split-stack
+//    prologue and the `blt-` replaced with a `bge+ .Lnormal_func_body`
+//    instead.
+// -) If either the addis or addi is not needed due to the stack size being
+//    smaller then 32K or a multiple of 64K they will be replaced with a nop,
+//    but there will always be 2 instructions the linker can overwrite for the
+//    adjusted stack size.
+//
+// The linkers job here is to increase the stack size used in the addis/addi
+// pair by split-stack-size-adjust.
+// addis r12, r1, ha(-stack-frame size - split-stack-adjust-size)
+// addi  r12, r12, l(-stack-frame size - split-stack-adjust-size)
+bool PPC64::adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
+                                             uint8_t StOther) const {
+  // If the caller has a global entry point adjust the buffer past it. The start
+  // of the split-stack prologue will be at the local entry point.
+  Loc += getPPC64GlobalEntryToLocalEntryOffset(StOther);
+
+  // At the very least we expect to see a load of some split-stack data from the
+  // tcb, and 2 instructions that calculate the ending stack address this
+  // function will require. If there is not enough room for at least 3
+  // instructions it can't be a split-stack prologue.
+  if (Loc + 12 >= End)
+    return false;
+
+  // First instruction must be `ld r0, -0x7000-64(r13)`
+  if (read32(Loc) != 0xe80d8fc0)
+    return false;
+
+  int16_t HiImm = 0;
+  int16_t LoImm = 0;
+  // First instruction can be either an addis if the frame size is larger then
+  // 32K, or an addi if the size is less then 32K.
+  int32_t FirstInstr = read32(Loc + 4);
+  if (getPrimaryOpCode(FirstInstr) == 15) {
+    HiImm = FirstInstr & 0xFFFF;
+  } else if (getPrimaryOpCode(FirstInstr) == 14) {
+    LoImm = FirstInstr & 0xFFFF;
+  } else {
+    return false;
+  }
+
+  // Second instruction is either an addi or a nop. If the first instruction was
+  // an addi then LoImm is set and the second instruction must be a nop.
+  uint32_t SecondInstr = read32(Loc + 8);
+  if (!LoImm && getPrimaryOpCode(SecondInstr) == 14) {
+    LoImm = SecondInstr & 0xFFFF;
+  } else if (SecondInstr != 0x60000000) {
+    return false;
+  }
+
+  // The register operands of the first instruction should be the stack-pointer
+  // (r1) as the input (RA) and r12 as the output (RT). If the second
+  // instruction is not a nop, then it should use r12 as both input and output.
+  auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT,
+                             uint8_t ExpectedRA) {
+    return ((Instr & 0x3E00000) >> 21 == ExpectedRT) &&
+           ((Instr & 0x1F0000) >> 16 == ExpectedRA);
+  };
+  if (!CheckRegOperands(FirstInstr, 12, 1))
+    return false;
+  if (SecondInstr != 0x60000000 && !CheckRegOperands(SecondInstr, 12, 12))
+    return false;
+
+  int32_t StackFrameSize = (HiImm * 65536) + LoImm;
+  // Check that the adjusted size doesn't overflow what we can represent with 2
+  // instructions.
+  if (StackFrameSize < Config->SplitStackAdjustSize + INT32_MIN) {
+    error(getErrorLocation(Loc) + "split-stack prologue adjustment overflows");
+    return false;
+  }
+
+  int32_t AdjustedStackFrameSize =
+      StackFrameSize - Config->SplitStackAdjustSize;
+
+  LoImm = AdjustedStackFrameSize & 0xFFFF;
+  HiImm = (AdjustedStackFrameSize + 0x8000) >> 16;
+  if (HiImm) {
+    write32(Loc + 4, 0x3D810000 | (uint16_t)HiImm);
+    // If the low immediate is zero the second instruction will be a nop.
+    SecondInstr = LoImm ? 0x398C0000 | (uint16_t)LoImm : 0x60000000;
+    write32(Loc + 8, SecondInstr);
+  } else {
+    // addi r12, r1, imm
+    write32(Loc + 4, (0x39810000) | (uint16_t)LoImm);
+    write32(Loc + 8, 0x60000000);
+  }
+
+  return true;
+}
+
 TargetInfo *elf::getPPC64TargetInfo() {
   static PPC64 Target;
   return &Target;
diff --git a/ELF/Arch/RISCV.cpp b/ELF/Arch/RISCV.cpp
new file mode 100644
index 0000000000000..461e8d35c3e6c
--- /dev/null
+++ b/ELF/Arch/RISCV.cpp
@@ -0,0 +1,279 @@
+//===- RISCV.cpp ----------------------------------------------------------===//
+//
+//                             The LLVM Linker
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Target.h"
+
+using namespace llvm;
+using namespace llvm::object;
+using namespace llvm::support::endian;
+using namespace llvm::ELF;
+using namespace lld;
+using namespace lld::elf;
+
+namespace {
+
+class RISCV final : public TargetInfo {
+public:
+  RISCV();
+  uint32_t calcEFlags() const override;
+  RelExpr getRelExpr(RelType Type, const Symbol &S,
+                     const uint8_t *Loc) const override;
+  void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
+};
+
+} // end anonymous namespace
+
+RISCV::RISCV() { NoneRel = R_RISCV_NONE; }
+
+static uint32_t getEFlags(InputFile *F) {
+  if (Config->Is64)
+    return cast<ObjFile<ELF64LE>>(F)->getObj().getHeader()->e_flags;
+  return cast<ObjFile<ELF32LE>>(F)->getObj().getHeader()->e_flags;
+}
+
+uint32_t RISCV::calcEFlags() const {
+  assert(!ObjectFiles.empty());
+
+  uint32_t Target = getEFlags(ObjectFiles.front());
+
+  for (InputFile *F : ObjectFiles) {
+    uint32_t EFlags = getEFlags(F);
+    if (EFlags & EF_RISCV_RVC)
+      Target |= EF_RISCV_RVC;
+
+    if ((EFlags & EF_RISCV_FLOAT_ABI) != (Target & EF_RISCV_FLOAT_ABI))
+      error(toString(F) +
+            ": cannot link object files with different floating-point ABI");
+
+    if ((EFlags & EF_RISCV_RVE) != (Target & EF_RISCV_RVE))
+      error(toString(F) +
+            ": cannot link object files with different EF_RISCV_RVE");
+  }
+
+  return Target;
+}
+
+RelExpr RISCV::getRelExpr(const RelType Type, const Symbol &S,
+                          const uint8_t *Loc) const {
+  switch (Type) {
+  case R_RISCV_JAL:
+  case R_RISCV_BRANCH:
+  case R_RISCV_CALL:
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_RVC_BRANCH:
+  case R_RISCV_RVC_JUMP:
+  case R_RISCV_32_PCREL:
+    return R_PC;
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_PCREL_LO12_S:
+    return R_RISCV_PC_INDIRECT;
+  case R_RISCV_RELAX:
+  case R_RISCV_ALIGN:
+    return R_HINT;
+  default:
+    return R_ABS;
+  }
+}
+
+// Extract bits V[Begin:End], where range is inclusive, and Begin must be < 63.
+static uint32_t extractBits(uint64_t V, uint32_t Begin, uint32_t End) {
+  return (V & ((1ULL << (Begin + 1)) - 1)) >> End;
+}
+
+void RISCV::relocateOne(uint8_t *Loc, const RelType Type,
+                        const uint64_t Val) const {
+  switch (Type) {
+  case R_RISCV_32:
+    write32le(Loc, Val);
+    return;
+  case R_RISCV_64:
+    write64le(Loc, Val);
+    return;
+
+  case R_RISCV_RVC_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 8, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE383;
+    uint16_t Imm8 = extractBits(Val, 8, 8) << 12;
+    uint16_t Imm4_3 = extractBits(Val, 4, 3) << 10;
+    uint16_t Imm7_6 = extractBits(Val, 7, 6) << 5;
+    uint16_t Imm2_1 = extractBits(Val, 2, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm8 | Imm4_3 | Imm7_6 | Imm2_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_JUMP: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 11, Type);
+    checkAlignment(Loc, Val, 2, Type);
+    uint16_t Insn = read16le(Loc) & 0xE003;
+    uint16_t Imm11 = extractBits(Val, 11, 11) << 12;
+    uint16_t Imm4 = extractBits(Val, 4, 4) << 11;
+    uint16_t Imm9_8 = extractBits(Val, 9, 8) << 9;
+    uint16_t Imm10 = extractBits(Val, 10, 10) << 8;
+    uint16_t Imm6 = extractBits(Val, 6, 6) << 7;
+    uint16_t Imm7 = extractBits(Val, 7, 7) << 6;
+    uint16_t Imm3_1 = extractBits(Val, 3, 1) << 3;
+    uint16_t Imm5 = extractBits(Val, 5, 5) << 2;
+    Insn |= Imm11 | Imm4 | Imm9_8 | Imm10 | Imm6 | Imm7 | Imm3_1 | Imm5;
+
+    write16le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_RVC_LUI: {
+    int32_t Imm = ((Val + 0x800) >> 12);
+    checkUInt(Loc, Imm, 6, Type);
+    if (Imm == 0) { // `c.lui rd, 0` is illegal, convert to `c.li rd, 0`
+      write16le(Loc, (read16le(Loc) & 0x0F83) | 0x4000);
+    } else {
+      uint16_t Imm17 = extractBits(Val + 0x800, 17, 17) << 12;
+      uint16_t Imm16_12 = extractBits(Val + 0x800, 16, 12) << 2;
+      write16le(Loc, (read16le(Loc) & 0xEF83) | Imm17 | Imm16_12);
+    }
+    return;
+  }
+
+  case R_RISCV_JAL: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 20, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0xFFF;
+    uint32_t Imm20 = extractBits(Val, 20, 20) << 31;
+    uint32_t Imm10_1 = extractBits(Val, 10, 1) << 21;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 20;
+    uint32_t Imm19_12 = extractBits(Val, 19, 12) << 12;
+    Insn |= Imm20 | Imm10_1 | Imm11 | Imm19_12;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  case R_RISCV_BRANCH: {
+    checkInt(Loc, static_cast<int64_t>(Val) >> 1, 12, Type);
+    checkAlignment(Loc, Val, 2, Type);
+
+    uint32_t Insn = read32le(Loc) & 0x1FFF07F;
+    uint32_t Imm12 = extractBits(Val, 12, 12) << 31;
+    uint32_t Imm10_5 = extractBits(Val, 10, 5) << 25;
+    uint32_t Imm4_1 = extractBits(Val, 4, 1) << 8;
+    uint32_t Imm11 = extractBits(Val, 11, 11) << 7;
+    Insn |= Imm12 | Imm10_5 | Imm4_1 | Imm11;
+
+    write32le(Loc, Insn);
+    return;
+  }
+
+  // auipc + jalr pair
+  case R_RISCV_CALL: {
+    checkInt(Loc, Val, 32, Type);
+    if (isInt<32>(Val)) {
+      relocateOne(Loc, R_RISCV_PCREL_HI20, Val);
+      relocateOne(Loc + 4, R_RISCV_PCREL_LO12_I, Val);
+    }
+    return;
+  }
+
+  case R_RISCV_PCREL_HI20:
+  case R_RISCV_HI20: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    write32le(Loc, (read32le(Loc) & 0xFFF) | (Hi & 0xFFFFF000));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_I:
+  case R_RISCV_LO12_I: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    write32le(Loc, (read32le(Loc) & 0xFFFFF) | ((Lo & 0xFFF) << 20));
+    return;
+  }
+
+  case R_RISCV_PCREL_LO12_S:
+  case R_RISCV_LO12_S: {
+    checkInt(Loc, Val, 32, Type);
+    uint32_t Hi = Val + 0x800;
+    uint32_t Lo = Val - (Hi & 0xFFFFF000);
+    uint32_t Imm11_5 = extractBits(Lo, 11, 5) << 25;
+    uint32_t Imm4_0 = extractBits(Lo, 4, 0) << 7;
+    write32le(Loc, (read32le(Loc) & 0x1FFF07F) | Imm11_5 | Imm4_0);
+    return;
+  }
+
+  case R_RISCV_ADD8:
+    *Loc += Val;
+    return;
+  case R_RISCV_ADD16:
+    write16le(Loc, read16le(Loc) + Val);
+    return;
+  case R_RISCV_ADD32:
+    write32le(Loc, read32le(Loc) + Val);
+    return;
+  case R_RISCV_ADD64:
+    write64le(Loc, read64le(Loc) + Val);
+    return;
+  case R_RISCV_SUB6:
+    *Loc = (*Loc & 0xc0) | (((*Loc & 0x3f) - Val) & 0x3f);
+    return;
+  case R_RISCV_SUB8:
+    *Loc -= Val;
+    return;
+  case R_RISCV_SUB16:
+    write16le(Loc, read16le(Loc) - Val);
+    return;
+  case R_RISCV_SUB32:
+    write32le(Loc, read32le(Loc) - Val);
+    return;
+  case R_RISCV_SUB64:
+    write64le(Loc, read64le(Loc) - Val);
+    return;
+  case R_RISCV_SET6:
+    *Loc = (*Loc & 0xc0) | (Val & 0x3f);
+    return;
+  case R_RISCV_SET8:
+    *Loc = Val;
+    return;
+  case R_RISCV_SET16:
+    write16le(Loc, Val);
+    return;
+  case R_RISCV_SET32:
+  case R_RISCV_32_PCREL:
+    write32le(Loc, Val);
+    return;
+
+  case R_RISCV_ALIGN:
+  case R_RISCV_RELAX:
+    return; // Ignored (for now)
+  case R_RISCV_NONE:
+    return; // Do nothing
+
+  // These are handled by the dynamic linker
+  case R_RISCV_RELATIVE:
+  case R_RISCV_COPY:
+  case R_RISCV_JUMP_SLOT:
+  // GP-relative relocations are only produced after relaxation, which
+  // we don't support for now
+  case R_RISCV_GPREL_I:
+  case R_RISCV_GPREL_S:
+  default:
+    error(getErrorLocation(Loc) +
+          "unimplemented relocation: " + toString(Type));
+    return;
+  }
+}
+
+TargetInfo *elf::getRISCVTargetInfo() {
+  static RISCV Target;
+  return &Target;
+}
diff --git a/ELF/Arch/SPARCV9.cpp b/ELF/Arch/SPARCV9.cpp
index 36f5c836930ec..831aa2028e7fd 100644
--- a/ELF/Arch/SPARCV9.cpp
+++ b/ELF/Arch/SPARCV9.cpp
@@ -35,6 +35,7 @@ public:
 SPARCV9::SPARCV9() {
   CopyRel = R_SPARC_COPY;
   GotRel = R_SPARC_GLOB_DAT;
+  NoneRel = R_SPARC_NONE;
   PltRel = R_SPARC_JMP_SLOT;
   RelativeRel = R_SPARC_RELATIVE;
   GotEntrySize = 8;
diff --git a/ELF/Arch/X86.cpp b/ELF/Arch/X86.cpp
index 19a0b6017f1a0..e910375d2fc75 100644
--- a/ELF/Arch/X86.cpp
+++ b/ELF/Arch/X86.cpp
@@ -48,6 +48,7 @@ public:
 X86::X86() {
   CopyRel = R_386_COPY;
   GotRel = R_386_GLOB_DAT;
+  NoneRel = R_386_NONE;
   PltRel = R_386_JUMP_SLOT;
   IRelativeRel = R_386_IRELATIVE;
   RelativeRel = R_386_RELATIVE;
@@ -59,7 +60,11 @@ X86::X86() {
   PltEntrySize = 16;
   PltHeaderSize = 16;
   TlsGdRelaxSkip = 2;
-  TrapInstr = 0xcccccccc; // 0xcc = INT3
+  TrapInstr = {0xcc, 0xcc, 0xcc, 0xcc}; // 0xcc = INT3
+
+  // Align to the non-PAE large page size (known as a superpage or huge page).
+  // FreeBSD automatically promotes large, superpage-aligned allocations.
+  DefaultImageBase = 0x400000;
 }
 
 static bool hasBaseReg(uint8_t ModRM) { return (ModRM & 0xc7) != 0x5; }
@@ -152,7 +157,7 @@ RelExpr X86::adjustRelaxExpr(RelType Type, const uint8_t *Data,
 }
 
 void X86::writeGotPltHeader(uint8_t *Buf) const {
-  write32le(Buf, InX::Dynamic->getVA());
+  write32le(Buf, In.Dynamic->getVA());
 }
 
 void X86::writeGotPlt(uint8_t *Buf, const Symbol &S) const {
@@ -183,8 +188,8 @@ void X86::writePltHeader(uint8_t *Buf) const {
     };
     memcpy(Buf, V, sizeof(V));
 
-    uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
-    uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
+    uint32_t Ebx = In.Got->getVA() + In.Got->getSize();
+    uint32_t GotPlt = In.GotPlt->getVA() - Ebx;
     write32le(Buf + 2, GotPlt + 4);
     write32le(Buf + 8, GotPlt + 8);
     return;
@@ -196,7 +201,7 @@ void X86::writePltHeader(uint8_t *Buf) const {
       0x90, 0x90, 0x90, 0x90, // nop
   };
   memcpy(Buf, PltData, sizeof(PltData));
-  uint32_t GotPlt = InX::GotPlt->getVA();
+  uint32_t GotPlt = In.GotPlt->getVA();
   write32le(Buf + 2, GotPlt + 4);
   write32le(Buf + 8, GotPlt + 8);
 }
@@ -213,7 +218,7 @@ void X86::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
 
   if (Config->Pic) {
     // jmp *foo@GOT(%ebx)
-    uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
+    uint32_t Ebx = In.Got->getVA() + In.Got->getSize();
     Buf[1] = 0xa3;
     write32le(Buf + 2, GotPltEntryAddr - Ebx);
   } else {
@@ -447,8 +452,8 @@ void RetpolinePic::writePltHeader(uint8_t *Buf) const {
   };
   memcpy(Buf, Insn, sizeof(Insn));
 
-  uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
-  uint32_t GotPlt = InX::GotPlt->getVA() - Ebx;
+  uint32_t Ebx = In.Got->getVA() + In.Got->getSize();
+  uint32_t GotPlt = In.GotPlt->getVA() - Ebx;
   write32le(Buf + 2, GotPlt + 4);
   write32le(Buf + 9, GotPlt + 8);
 }
@@ -467,7 +472,7 @@ void RetpolinePic::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
   };
   memcpy(Buf, Insn, sizeof(Insn));
 
-  uint32_t Ebx = InX::Got->getVA() + InX::Got->getSize();
+  uint32_t Ebx = In.Got->getVA() + In.Got->getSize();
   unsigned Off = getPltEntryOffset(Index);
   write32le(Buf + 3, GotPltEntryAddr - Ebx);
   write32le(Buf + 8, -Off - 12 + 32);
@@ -506,7 +511,7 @@ void RetpolineNoPic::writePltHeader(uint8_t *Buf) const {
   };
   memcpy(Buf, Insn, sizeof(Insn));
 
-  uint32_t GotPlt = InX::GotPlt->getVA();
+  uint32_t GotPlt = In.GotPlt->getVA();
   write32le(Buf + 2, GotPlt + 4);
   write32le(Buf + 8, GotPlt + 8);
 }
diff --git a/ELF/Arch/X86_64.cpp b/ELF/Arch/X86_64.cpp
index d4bdb3730c58b..06314155dcc92 100644
--- a/ELF/Arch/X86_64.cpp
+++ b/ELF/Arch/X86_64.cpp
@@ -43,8 +43,8 @@ public:
   void relaxTlsGdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, RelType Type, uint64_t Val) const override;
-  bool adjustPrologueForCrossSplitStack(uint8_t *Loc,
-                                        uint8_t *End) const override;
+  bool adjustPrologueForCrossSplitStack(uint8_t *Loc, uint8_t *End,
+                                        uint8_t StOther) const override;
 
 private:
   void relaxGotNoPic(uint8_t *Loc, uint64_t Val, uint8_t Op,
@@ -55,6 +55,7 @@ private:
 template <class ELFT> X86_64<ELFT>::X86_64() {
   CopyRel = R_X86_64_COPY;
   GotRel = R_X86_64_GLOB_DAT;
+  NoneRel = R_X86_64_NONE;
   PltRel = R_X86_64_JUMP_SLOT;
   RelativeRel = R_X86_64_RELATIVE;
   IRelativeRel = R_X86_64_IRELATIVE;
@@ -66,7 +67,7 @@ template <class ELFT> X86_64<ELFT>::X86_64() {
   PltEntrySize = 16;
   PltHeaderSize = 16;
   TlsGdRelaxSkip = 2;
-  TrapInstr = 0xcccccccc; // 0xcc = INT3
+  TrapInstr = {0xcc, 0xcc, 0xcc, 0xcc}; // 0xcc = INT3
 
   // Align to the large page size (known as a superpage or huge page).
   // FreeBSD automatically promotes large, superpage-aligned allocations.
@@ -124,7 +125,7 @@ template <class ELFT> void X86_64<ELFT>::writeGotPltHeader(uint8_t *Buf) const {
   // required, but it is documented in the psabi and the glibc dynamic linker
   // seems to use it (note that this is relevant for linking ld.so, not any
   // other program).
-  write64le(Buf, InX::Dynamic->getVA());
+  write64le(Buf, In.Dynamic->getVA());
 }
 
 template <class ELFT>
@@ -140,8 +141,8 @@ template <class ELFT> void X86_64<ELFT>::writePltHeader(uint8_t *Buf) const {
       0x0f, 0x1f, 0x40, 0x00, // nop
   };
   memcpy(Buf, PltData, sizeof(PltData));
-  uint64_t GotPlt = InX::GotPlt->getVA();
-  uint64_t Plt = InX::Plt->getVA();
+  uint64_t GotPlt = In.GotPlt->getVA();
+  uint64_t Plt = In.Plt->getVA();
   write32le(Buf + 2, GotPlt - Plt + 2); // GOTPLT+8
   write32le(Buf + 8, GotPlt - Plt + 4); // GOTPLT+16
 }
@@ -481,23 +482,27 @@ namespace {
 // B) Or a load of a stack pointer offset with an lea to r10 or r11.
 template <>
 bool X86_64<ELF64LE>::adjustPrologueForCrossSplitStack(uint8_t *Loc,
-                                                       uint8_t *End) const {
+                                                       uint8_t *End,
+                                                       uint8_t StOther) const {
+  if (Loc + 8 >= End)
+    return false;
+
   // Replace "cmp %fs:0x70,%rsp" and subsequent branch
   // with "stc, nopl 0x0(%rax,%rax,1)"
-  if (Loc + 8 < End && memcmp(Loc, "\x64\x48\x3b\x24\x25", 4) == 0) {
+  if (memcmp(Loc, "\x64\x48\x3b\x24\x25", 5) == 0) {
     memcpy(Loc, "\xf9\x0f\x1f\x84\x00\x00\x00\x00", 8);
     return true;
   }
 
-  // Adjust "lea -0x200(%rsp),%r10" to lea "-0x4200(%rsp),%r10"
-  if (Loc + 7 < End && memcmp(Loc, "\x4c\x8d\x94\x24\x00\xfe\xff", 7) == 0) {
-    memcpy(Loc, "\x4c\x8d\x94\x24\x00\xbe\xff", 7);
-    return true;
-  }
-
-  // Adjust "lea -0x200(%rsp),%r11" to lea "-0x4200(%rsp),%r11"
-  if (Loc + 7 < End && memcmp(Loc, "\x4c\x8d\x9c\x24\x00\xfe\xff", 7) == 0) {
-    memcpy(Loc, "\x4c\x8d\x9c\x24\x00\xbe\xff", 7);
+  // Adjust "lea X(%rsp),%rYY" to lea "(X - 0x4000)(%rsp),%rYY" where rYY could
+  // be r10 or r11. The lea instruction feeds a subsequent compare which checks
+  // if there is X available stack space. Making X larger effectively reserves
+  // that much additional space. The stack grows downward so subtract the value.
+  if (memcmp(Loc, "\x4c\x8d\x94\x24", 4) == 0 ||
+      memcmp(Loc, "\x4c\x8d\x9c\x24", 4) == 0) {
+    // The offset bytes are encoded four bytes after the start of the
+    // instruction.
+    write32le(Loc + 4, read32le(Loc + 4) - 0x4000);
     return true;
   }
   return false;
@@ -505,7 +510,8 @@ bool X86_64<ELF64LE>::adjustPrologueForCrossSplitStack(uint8_t *Loc,
 
 template <>
 bool X86_64<ELF32LE>::adjustPrologueForCrossSplitStack(uint8_t *Loc,
-                                                       uint8_t *End) const {
+                                                       uint8_t *End,
+                                                       uint8_t StOther) const {
   llvm_unreachable("Target doesn't support split stacks.");
 }
 
@@ -566,8 +572,8 @@ template <class ELFT> void Retpoline<ELFT>::writePltHeader(uint8_t *Buf) const {
   };
   memcpy(Buf, Insn, sizeof(Insn));
 
-  uint64_t GotPlt = InX::GotPlt->getVA();
-  uint64_t Plt = InX::Plt->getVA();
+  uint64_t GotPlt = In.GotPlt->getVA();
+  uint64_t Plt = In.Plt->getVA();
   write32le(Buf + 2, GotPlt - Plt - 6 + 8);
   write32le(Buf + 9, GotPlt - Plt - 13 + 16);
 }
@@ -586,7 +592,7 @@ void Retpoline<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
   };
   memcpy(Buf, Insn, sizeof(Insn));
 
-  uint64_t Off = TargetInfo::getPltEntryOffset(Index);
+  uint64_t Off = getPltEntryOffset(Index);
 
   write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
   write32le(Buf + 8, -Off - 12 + 32);
@@ -629,7 +635,7 @@ void RetpolineZNow<ELFT>::writePlt(uint8_t *Buf, uint64_t GotPltEntryAddr,
   memcpy(Buf, Insn, sizeof(Insn));
 
   write32le(Buf + 3, GotPltEntryAddr - PltEntryAddr - 7);
-  write32le(Buf + 8, -TargetInfo::getPltEntryOffset(Index) - 12);
+  write32le(Buf + 8, -getPltEntryOffset(Index) - 12);
 }
 
 template <class ELFT> static TargetInfo *getTargetInfo() {