diff options
| author | Ed Maste <emaste@FreeBSD.org> | 2020-12-16 14:01:04 +0000 |
|---|---|---|
| committer | Ed Maste <emaste@FreeBSD.org> | 2020-12-16 14:01:04 +0000 |
| commit | 546114d08ec693263d9c030c16f83ed826e4a379 (patch) | |
| tree | e634e2a6f8957c63ed3cb97db3de72ea49513f43 /contrib/binutils/include/opcode | |
| parent | 7efe93ce08e74a85307ed8fc7a4b510b04e6c180 (diff) | |
Notes
Diffstat (limited to 'contrib/binutils/include/opcode')
20 files changed, 0 insertions, 12475 deletions
diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog deleted file mode 100644 index 689e278c721c7..0000000000000 --- a/contrib/binutils/include/opcode/ChangeLog +++ /dev/null @@ -1,691 +0,0 @@ -2006-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> - - * cr16.h: New file for CR16 target. - -2007-05-02 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPERAND_PLUS1): Update comment. - -2007-04-23 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (mcfisa_c): New. - (mcfusp, mcf_mask): Adjust. - -2007-04-20 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". - (num_powerpc_operands): Declare. - (PPC_OPERAND_SIGNED et al): Redefine as hex. - (PPC_OPERAND_PLUS1): Define. - -2007-03-21 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (REX_MODE64): Renamed to ... - (REX_W): This. - (REX_EXTX): Renamed to ... - (REX_R): This. - (REX_EXTY): Renamed to ... - (REX_X): This. - (REX_EXTZ): Renamed to ... - (REX_B): This. - -2007-03-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h: Add entries from config/tc-i386.h and move tables - to opcodes/i386-opc.h. - -2007-03-13 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (FloatDR): Removed. - (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. - -2007-03-01 Alan Modra <amodra@bigpond.net.au> - - * spu-insns.h: Add soma double-float insns. - -2007-02-20 Thiemo Seufer <ths@mips.com> - Chao-Ying Fu <fu@mips.com> - - * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. - (INSN_DSPR2): Add flag for DSP R2 instructions. - (M_BALIGN): New macro. - -2007-02-14 Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm - and Seg3ShortFrom with Shortform. - -2007-02-11 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/4027 - * i386.h (i386_optab): Put the real "test" before the pseudo - one. - -2007-01-08 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (m68010up): OR fido_a. - -2006-12-25 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (fido_a): New. - -2006-12-24 Kazu Hirata <kazu@codesourcery.com> - - * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, - mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined - values. - -2006-11-08 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. - -2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> - - * score-inst.h (enum score_insn_type): Add Insn_internal. - -2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> - Yukishige Shibata <shibata@rd.scei.sony.co.jp> - Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> - Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> - Alan Modra <amodra@bigpond.net.au> - - * spu-insns.h: New file. - * spu.h: New file. - -2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> - - * ppc.h (PPC_OPCODE_CELL): Define. - -2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> - - * i386.h : Modify opcode to support for the change in POPCNT opcode - in amdfam10 architecture. - -2006-09-28 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h: Replace CpuMNI with CpuSSSE3. - -2006-09-26 Mark Shinwell <shinwell@codesourcery.com> - Joseph Myers <joseph@codesourcery.com> - Ian Lance Taylor <ian@wasabisystems.com> - Ben Elliston <bje@wasabisystems.com> - - * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. - -2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> - - * score-datadep.h: New file. - * score-inst.h: New file. - -2006-07-14 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, - movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, - movdq2q and movq2dq. - -2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> - Michael Meissner <michael.meissner@amd.com> - - * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). - -2006-06-12 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Add "nop" with memory reference. - -2006-06-12 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Update comment for 64bit NOP. - -2006-06-06 Ben Elliston <bje@au.ibm.com> - Anton Blanchard <anton@samba.org> - - * ppc.h (PPC_OPCODE_POWER6): Define. - Adjust whitespace. - -2006-06-05 Thiemo Seufer <ths@mips.com> - - * mips.h: Improve description of MT flags. - -2006-05-25 Richard Sandiford <richard@codesourcery.com> - - * m68k.h (mcf_mask): Define. - -2006-05-05 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> - - * mips.h (enum): Add macro M_CACHE_AB. - -2006-05-04 Thiemo Seufer <ths@mips.com> - Nigel Stephens <nigel@mips.com> - David Ung <davidu@mips.com> - - * mips.h: Add INSN_SMARTMIPS define. - -2006-04-30 Thiemo Seufer <ths@mips.com> - David Ung <davidu@mips.com> - - * mips.h: Defines udi bits and masks. Add description of - characters which may appear in the args field of udi - instructions. - -2006-04-26 Thiemo Seufer <ths@networkno.de> - - * mips.h: Improve comments describing the bitfield instruction - fields. - -2006-04-26 Julian Brown <julian@codesourcery.com> - - * arm.h (FPU_VFP_EXT_V3): Define constant. - (FPU_NEON_EXT_V1): Likewise. - (FPU_VFP_HARD): Update. - (FPU_VFP_V3): Define macro. - (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. - -2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> - - * avr.h (AVR_ISA_PWMx): New. - -2006-03-28 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010, - cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851, - cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e, - cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x, - cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove. - -2006-03-10 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions. - -2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come - first. Correct mask of bb "B" opcode. - -2006-02-27 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel Merom New Instructions. - -2006-02-24 Paul Brook <paul@codesourcery.com> - - * arm.h: Add V7 feature bits. - -2006-02-23 H.J. Lu <hongjiu.lu@intel.com> - - * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b. - -2006-01-31 Paul Brook <paul@codesourcery.com> - Richard Earnshaw <rearnsha@arm.com> - - * arm.h: Use ARM_CPU_FEATURE. - (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New. - (arm_feature_set): Change to a structure. - (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE, - ARM_FEATURE): New macros. - -2005-12-07 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS) - (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros. - (ADD_PC_INCR_OPCODE): Don't define. - -2005-12-06 H.J. Lu <hongjiu.lu@intel.com> - - PR gas/1874 - * i386.h (i386_optab): Add 64bit support for monitor and mwait. - -2005-11-14 David Ung <davidu@mips.com> - - * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore - instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for - save/restore encoding of the args field. - -2005-10-28 Dave Brolley <brolley@redhat.com> - - Contribute the following changes: - 2005-02-16 Dave Brolley <brolley@redhat.com> - - * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename - cgen_isa_mask_* to cgen_bitset_*. - * cgen.h: Likewise. - - 2003-10-21 Richard Sandiford <rsandifo@redhat.com> - - * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition. - (CGEN_ATTR_ENTRY): Change "value" to type "unsigned". - (CGEN_CPU_TABLE): Make isas a ponter. - - 2003-09-29 Dave Brolley <brolley@redhat.com> - - * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef. - (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto. - (CGEN_ATTR_VALUE_TYPE): Use these new typedefs. - - 2002-12-13 Dave Brolley <brolley@redhat.com> - - * cgen.h (symcat.h): #include it. - (cgen-bitset.h): #include it. - (CGEN_ATTR_VALUE_TYPE): Now a union. - (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h. - (CGEN_ATTR_ENTRY): 'value' now unsigned. - (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*). - * cgen-bitset.h: New file. - -2005-09-30 Catherine Moore <clm@cm00re.com> - - * bfin.h: New file. - -2005-10-24 Jan Beulich <jbeulich@novell.com> - - * ia64.h (enum ia64_opnd): Move memory operand out of set of - indirect operands. - -2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes. - Add FLAG_STRICT to pa10 ftest opcode. - -2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Remove lha entries. - -2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (FLAG_STRICT): Revise comment. - (pa_opcode): Revise ordering rules. Add/move strict pa10 variants - before corresponding pa11 opcodes. Add strict pa10 register-immediate - entries for "fdc". - -2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries. - -2005-09-06 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H, - OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New - define. - Document !, $, *, &, g, +t, +T operand formats for MT instructions. - (INSN_ASE_MASK): Update to include INSN_MT. - (INSN_MT): New define for MT ASE. - -2005-08-25 Chao-ying Fu <fu@mips.com> - - * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S, - OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7, - OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4, - OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP, - OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define. - Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP - instructions. - (INSN_DSP): New define for DSP ASE. - -2005-08-18 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Delete. - -2005-08-15 Daniel Jacobowitz <dan@codesourcery.com> - - * ppc.h (PPC_OPCODE_E300): Define. - -2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109. - -2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - PR gas/336 - * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb - and pitlb. - -2005-07-27 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add comment to movd. Use LongMem for all - movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers. - Add movq-s as 64-bit variants of movd-s. - -2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h: Fix punctuation in comment. - - * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for - implicit space-register addressing. Set space-register bits on opcodes - using implicit space-register addressing. Add various missing pa20 - long-immediate opcodes. Remove various opcodes using implicit 3-bit - space-register addressing. Use "fE" instead of "fe" in various - fstw opcodes. - -2005-07-18 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Operands of aam and aad are unsigned. - -2007-07-15 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel VMX Instructions. - -2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores. - -2005-07-05 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add new insns. - -2005-07-01 Nick Clifton <nickc@redhat.com> - - * sparc.h: Add typedefs to structure declarations. - -2005-06-20 H.J. Lu <hongjiu.lu@intel.com> - - PR 1013 - * i386.h (i386_optab): Update comments for 64bit addressing on - mov. Allow 64bit addressing for mov and movq. - -2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx, - respectively, in various floating-point load and store patterns. - -2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca> - - * hppa.h (FLAG_STRICT): Correct comment. - (pa_opcodes): Update load and store entries to allow both PA 1.X and - PA 2.0 mneumonics when equivalent. Entries with cache control - completers now require PA 1.1. Adjust whitespace. - -2005-05-19 Anton Blanchard <anton@samba.org> - - * ppc.h (PPC_OPCODE_POWER5): Define. - -2005-05-10 Nick Clifton <nickc@redhat.com> - - * Update the address and phone number of the FSF organization in - the GPL notices in the following files: - a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h, - crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h, - i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h, - mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h, - pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h, - tic54x.h, tic80.h, v850.h, vax.h - -2005-05-09 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add ht and hnt. - -2005-04-18 Mark Kettenis <kettenis@gnu.org> - - * i386.h: Insert hyphens into selected VIA PadLock extensions. - Add xcrypt-ctr. Provide aliases without hyphens. - -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - Moved from ../ChangeLog - - 2005-04-12 Paul Brook <paul@codesourcery.com> - * m88k.h: Rename psr macros to avoid conflicts. - - 2005-03-12 Zack Weinberg <zack@codesourcery.com> - * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T. - Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2, - and ARM_ARCH_V6ZKT2. - - 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4. - Remove redundant instruction types. - (struct argument): X_op - new field. - (struct cst4_entry): Remove. - (no_op_insn): Declare. - - 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum argtype): Rename types, remove unused types. - - 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'. - (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE. - (enum operand_type): Rearrange operands, edit comments. - replace us<N> with ui<N> for unsigned immediate. - replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped - displacements (respectively). - replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index. - (instruction type): Add NO_TYPE_INS. - (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR. - (operand_entry): New field - 'flags'. - (operand flags): New. - - 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com> - * crx.h (operand_type): Remove redundant types i3, i4, - i5, i8, i12. - Add new unsigned immediate types us3, us4, us5, us16. - -2005-04-12 Mark Kettenis <kettenis@gnu.org> - - * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and - adjust them accordingly. - -2005-04-01 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): Add rdtscp. - -2005-03-29 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Don't allow the `l' suffix for moving - between memory and segment register. Allow movq for moving between - general-purpose register and segment register. - -2005-02-09 Jan Beulich <jbeulich@novell.com> - - PR gas/707 - * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and - FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and - fnstsw. - -2006-02-07 Nathan Sidwell <nathan@codesourcery.com> - - * m68k.h (m68008, m68ec030, m68882): Remove. - (m68k_mask): New. - (cpu_m68k, cpu_cf): New. - (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407, - mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants. - -2005-01-25 Alexandre Oliva <aoliva@redhat.com> - - 2004-11-10 Alexandre Oliva <aoliva@redhat.com> - * cgen.h (enum cgen_parse_operand_type): Add - CGEN_PARSE_OPERAND_SYMBOLIC. - -2005-01-21 Fred Fish <fnf@specifixinc.com> - - * mips.h: Change INSN_ALIAS to INSN2_ALIAS. - Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. - Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. - -2005-01-19 Fred Fish <fnf@specifixinc.com> - - * mips.h (struct mips_opcode): Add new pinfo2 member. - (INSN_ALIAS): New define for opcode table entries that are - specific instances of another entry, such as 'move' for an 'or' - with a zero operand. - (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. - (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. - -2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> - - * mips.h (CPU_RM9000): Define. - (OPCODE_IS_MEMBER): Handle CPU_RM9000. - -2004-11-25 Jan Beulich <jbeulich@novell.com> - - * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves - to/from test registers are illegal in 64-bit mode. Add missing - NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix - (previously one had to explicitly encode a rex64 prefix). Re-enable - lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings - support it there. Add cmpxchg16b as per Intel's 64-bit documentation. - -2004-11-23 Jan Beulich <jbeulich@novell.com> - - * i386.h (i386_optab): paddq and psubq, even in their MMX form, are - available only with SSE2. Change the MMX additions introduced by SSE - and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A - instructions by their now designated identifier (since combining i686 - and 3DNow! does not really imply 3DNow!A). - -2004-11-19 Alan Modra <amodra@bigpond.net.au> - - * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, - struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. - -2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> - Vineet Sharma <vineets@noida.hcltech.com> - - * maxq.h: New file: Disassembly information for the maxq port. - -2004-11-05 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Put back "movzb". - -2004-11-04 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Tweak formatting and - comments. Remove member cris_ver_sim. Add members - cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, - cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. - (struct cris_support_reg, struct cris_cond15): New types. - (cris_conds15): Declare. - (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) - (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) - (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. - (NOP_Z_BITS): Define in terms of NOP_OPCODE. - (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and - SIZE_FIELD_UNSIGNED. - -2004-11-04 Jan Beulich <jbeulich@novell.com> - - * i386.h (sldx_Suf): Remove. - (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. - (q_FP): Define, implying no REX64. - (x_FP, sl_FP): Imply FloatMF. - (i386_optab): Split reg and mem forms of moving from segment registers - so that the memory forms can ignore the 16-/32-bit operand size - distinction. Adjust a few others for Intel mode. Remove *FP uses from - all non-floating-point instructions. Unite 32- and 64-bit forms of - movsx, movzx, and movd. Adjust floating point operations for the above - changes to the *FP macros. Add DefaultSize to floating point control - insns operating on larger memory ranges. Remove left over comments - hinting at certain insns being Intel-syntax ones where the ones - actually meant are already gone. - -2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: Add COPS_REG_INS - Coprocessor Special register - instruction type. - -2004-09-30 Paul Brook <paul@codesourcery.com> - - * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. - (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. - -2004-09-11 Theodore A. Roth <troth@openavr.org> - - * avr.h: Add support for - atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. - -2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> - - * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. - -2004-08-24 Dmitry Diky <diwil@spec.ru> - - * msp430.h (msp430_opc): Add new instructions. - (msp430_rcodes): Declare new instructions. - (msp430_hcodes): Likewise.. - -2004-08-13 Nick Clifton <nickc@redhat.com> - - PR/301 - * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX - processors. - -2004-08-30 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. - -2004-07-22 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. - -2004-07-21 Jan Beulich <jbeulich@novell.com> - - * i386.h: Adjust instruction descriptions to better match the - specification. - -2004-07-16 Richard Earnshaw <rearnsha@arm.com> - - * arm.h: Remove all old content. Replace with architecture defines - from gas/config/tc-arm.c. - -2004-07-09 Andreas Schwab <schwab@suse.de> - - * m68k.h: Fix comment. - -2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> - - * crx.h: New file. - -2004-06-24 Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. - -2004-05-24 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add 'size' to m68k_opcode. - -2004-05-05 Peter Barada <peter@the-baradas.com> - - * m68k.h: Switch from ColdFire chip name to core variant. - -2004-04-22 Peter Barada <peter@the-baradas.com> - - * m68k.h: Add mcfmac/mcfemac definitions. Update operand - descriptions for new EMAC cases. - Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly - handle Motorola MAC syntax. - Allow disassembly of ColdFire V4e object files. - -2004-03-16 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. - -2004-03-12 Jakub Jelinek <jakub@redhat.com> - - * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore as an alias for xstorerng. - -2004-03-12 Michal Ludvig <mludvig@suse.cz> - - * i386.h (i386_optab): Added xstore/xcrypt insns. - -2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (32bit ldc/stc): Add relaxing support. - -2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Pass MEMRELAX flag. - -2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com> - - * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32 - except for the H8S. - -For older changes see ChangeLog-9103 - -Local Variables: -mode: change-log -left-margin: 8 -fill-column: 74 -version-control: never -End: diff --git a/contrib/binutils/include/opcode/ChangeLog-9103 b/contrib/binutils/include/opcode/ChangeLog-9103 deleted file mode 100644 index 9a04bf5f5c7eb..0000000000000 --- a/contrib/binutils/include/opcode/ChangeLog-9103 +++ /dev/null @@ -1,3121 +0,0 @@ -2005-04-13 H.J. Lu <hongjiu.lu@intel.com> - - 2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * mips.h: Define new enum members, M_LCA_AB and M_DLCA_AB. - - 2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> - * tic4x.h: Namespace cleanup. Replace s/c4x/tic4x - - 2002-11-16 Klee Dienes <kdienes@apple.com> - * m88k.h (INSTAB): Remove 'next' field. - (instruction): Remove definition; replace with extern declaration - and mark as const. - - 2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> - * tic4x.h: New file. - - 2002-07-25 Richard Sandiford <rsandifo@redhat.com> - * mips.h (CPU_R2000): Remove. - -2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> - Bernardo Innocenti <bernie@develer.com> - - * m68k.h: Add MCFv4/MCF5528x support. - -2003-10-19 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h (JMP_INSN_BYTE): Define. - -2003-09-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document +E, +F, +G, +H, and +I operand types. - Update documentation of I, +B and +C operand types. - (INSN_ISA64R2, ISA_MIPS64R2, CPU_MIPS64R2): New defines. - (M_DEXT, M_DINS): New enum values. - -2003-09-04 Nick Clifton <nickc@redhat.com> - - * v850.h (PROCESSOR_V850E1): Define. - -2003-08-19 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other - PPC_OPCODE_* defines. - -2003-08-16 Jason Eckhardt <jle@rice.edu> - - * i860.h (fmov.ds): Expand as famov.ds. - (fmov.sd): Expand as famov.sd. - (pfmov.ds): Expand as pfamov.ds. - -2003-08-07 Michael Meissner <gnu@the-meissners.org> - - * cgen.h: Remove PARAM macro usage in all prototypes. - (CGEN_EXTRACT_INFO): Use void * instead of PTR. - (cgen_print_fn): Ditto. - (CGEN_HW_ENTRY): Ditto. - (CGEN_MAYBE_MULTI_IFLD): Ditto. - (struct cgen_insn): Ditto. - (CGEN_CPU_TABLE): Ditto. - -2003-08-07 Alan Modra <amodra@bigpond.net.au> - - * alpha.h: Remove PARAMS macro. - * arc.h: Likewise. - * d10v.h: Likewise. - * d30v.h: Likewise. - * i370.h: Likewise. - * or32.h: Likewise. - * pj.h: Likewise. - * ppc.h: Likewise. - * sparc.h: Likewise. - * tic80.h: Likewise. - * v850.h: Likewise. - -2003-07-18 Michael Snyder <msnyder@redhat.com> - - * include/opcode/h8sx.h (DO_MOVA1, DO_MOVA2): Reformatting. - -2003-07-15 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (CPU_RM7000): New macro. - (OPCODE_IS_MEMBER): Match CPU_RM7000 against 4650 insns. - -2003-07-09 Alexandre Oliva <aoliva@redhat.com> - - 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM33_2): Renamed from AM33. - 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> - * mn10300.h (AM332, FMT_D3): Defined. - (MN10300_OPERAND_FSREG, MN10300_OPERAND_FDREG): Likewise. - (MN10300_OPERAND_FPCR): Likewise. - -2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_cpu_val): Add enum for cpu type z990. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. - (IMM8U, IMM8U_NS): Define. - (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. - -2003-06-25 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and - mov.l ERs,@(dd:32,ERd) entries. - -2003-06-23 H.J. Lu <hongjiu.lu@intel.com> - - * i386.h (i386_optab): Support Intel Precott New Instructions. - -2003-06-10 Gary Hade <garyhade@us.ibm.com> - - * ppc.h (PPC_OPERAND_DQ): Define. - -2003-06-10 Richard Sandiford <rsandifo@redhat.com> - - * h8300.h (IMM4_NS, IMM8_NS): New. - (h8_opcodes): Replace IMM4 with IMM4_NS in mov.b and mov.w entries. - Likewise IMM8 for mov.w and mov.l. Likewise IMM16U for mov.l. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - - * h8300.h (enum h8_model): Add AV_H8S to distinguish from H8H. - (ldc): Split ccr ops from exr ops (which are only available - on H8S or H8SX). - (stc): Ditto. - (andc, orc, xorc): Ditto. - (ldmac, stmac, clrmac, mac): Change access to AV_H8S. - -2003-06-03 Michael Snyder <msnyder@redhat.com> - and Bernd Schmidt <bernds@redhat.com> - and Alexandre Oliva <aoliva@redhat.com> - * h8300.h: Add support for h8300sx instruction set. - -2003-05-23 Jason Eckhardt <jle@rice.edu> - - * i860.h (expand_type): Add XP_ONLY. - (scyc.b): New XP instruction. - (ldio.l): Likewise. - (ldio.s): Likewise. - (ldio.b): Likewise. - (ldint.l): Likewise. - (ldint.s): Likewise. - (ldint.b): Likewise. - (stio.l): Likewise. - (stio.s): Likewise. - (stio.b): Likewise. - (pfld.q): Likewise. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (flush): Set lower 3 bits properly and use 'L' - for the immediate operand type instead of 'i'. - -2003-05-20 Jason Eckhardt <jle@rice.edu> - - * i860.h (fzchks): Both S and R bits must be set. - (pfzchks): Likewise. - (faddp): Likewise. - (pfaddp): Likewise. - (fix.ss): Remove (invalid instruction). - (pfix.ss): Likewise. - (ftrunc.ss): Likewise. - (pftrunc.ss): Likewise. - -2003-05-18 Jason Eckhardt <jle@rice.edu> - - * i860.h (form, pform): Add missing .dd suffix. - -2003-05-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M68HC12_BANK_VIRT): Define to 0x010000 - -2003-04-07 Michael Snyder <msnyder@redhat.com> - - * h8300.h (ldc/stc): Fix up src/dst swaps. - -2003-04-09 J. Grant <jg-binutils@jguk.org> - - * mips.h: Correct comment typo. - -2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h (s390_opcode_arch_val): Rename to s390_opcode_mode_val. - (S390_OPCODE_ESAME): Rename to S390_OPCODE_ZARCH. - (s390_opcode): Remove architecture. Add modes and min_cpu. - -2003-03-17 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (O_SYS_CMDLINE): New pseudo opcode for command line - processing. - -2003-02-21 Noida D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h (ldmac, stmac): Replace MACREG with MS32 and MD32. - -2003-01-23 Alan Modra <amodra@bigpond.net.au> - - * m68hc11.h (cpu6812s): Define. - -2003-01-07 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Fix missing space in comment. - (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, INSN_ISA5) - (INSN_ISA32, INSN_ISA32R2, INSN_ISA64): Shift values right - by four bits. - -2003-01-02 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Update copyright years to include 2002 (which had - been missed previously) and 2003. Make comments about "+A", - "+B", and "+C" operand types more descriptive. - -2002-12-31 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Note that the "+D" operand type name is now used. - -2002-12-30 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Document "+" as the start of two-character operand - type names, and add new "K", "+A", "+B", and "+C" operand types. - (OP_MASK_INSMSB, OP_SH_INSMSB, OP_MASK_EXTMSB) - (OP_SH_EXTMSB, INSN_ISA32R2, ISA_MIPS32R2, CPU_MIPS32R2): New - defines. - -2002-12-24 Dmitry Diky <diwil@mail.ru> - - * msp430.h: New file. Defines msp430 opcodes. - -2002-12-30 D.Venkatasubramanian <dvenkat@noida.hcltech.com> - - * h8300.h: Added some more pseudo opcodes for system call - processing. - -2002-12-19 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3) - (OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2) - (OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1) - (OP_OP_SDC2, OP_OP_SDC3): Define. - -2002-12-16 Alan Modra <amodra@bigpond.net.au> - - * hppa.h (completer_chars): #if 0 out. - - * ns32k.h (struct ns32k_opcode): Constify "name", "operands" and - "default_args". - (struct not_wot): Constify "args". - (struct not): Constify "name". - (numopcodes): Delete. - (endop): Delete. - -2002-12-13 Alan Modra <amodra@bigpond.net.au> - - * pj.h (pj_opc_info_t): Add union. - -2002-12-04 David Mosberger <davidm@hpl.hp.com> - - * ia64.h: Fix copyright message. - (IA64_OPND_AR_CSD): New operand kind. - -2002-12-03 Richard Henderson <rth@redhat.com> - - * ia64.h (enum ia64_opnd): Add IA64_OPND_LDXMOV. - -2002-12-03 Alan Modra <amodra@bigpond.net.au> - - * cgen.h (struct cgen_maybe_multi_ifield): Add "const PTR p" to union. - Constify "leaf" and "multi". - -2002-11-19 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'noperands', 'idx', and 'size' - fields. - (h8_opcodes). Modify initializer and initializer macros to no - longer initialize the removed fields. - -2002-11-19 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h (c4x_insts): Fixed LDHI constraint - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * h8300.h (h8_opcode): Remove 'length' field. - (h8_opcodes): Mark as 'const' (both the declaration and - definition). Modify initializer and initializer macros to no - longer initialize the length field. - -2002-11-18 Klee Dienes <kdienes@apple.com> - - * arc.h (arc_ext_opcodes): Declare as extern. - (arc_ext_operands): Declare as extern. - * i860.h (i860_opcodes): Declare as const. - -2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: File reordering. Added enhanced opcodes. - -2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Major rewrite of entire file. Define instruction - classes, and put each instruction into a class. - -2002-11-11 Svein E. Seldal <Svein.Seldal@solidas.com> - - * tic4x.h: Added new opcodes and corrected some bugs. Add support - for new DSP types. - -2002-10-14 Alan Modra <amodra@bigpond.net.au> - - * cgen.h: Test __BFD_H_SEEN__ rather than BFD_VERSION_DATE. - -2002-09-30 Gavin Romig-Koch <gavin@redhat.com> - Ken Raeburn <raeburn@cygnus.com> - Aldy Hernandez <aldyh@redhat.com> - Eric Christopher <echristo@redhat.com> - Richard Sandiford <rsandifo@redhat.com> - - * mips.h: Update comment for new opcodes. - (OP_MASK_VECBYTE, OP_SH_VECBYTE): New. - (OP_MASK_VECALIGN, OP_SH_VECALIGN): New. - (INSN_4111, INSN_4120, INSN_5400, INSN_5500): New. - (CPU_VR4120, CPU_VR5400, CPU_VR5500): New. - (OPCODE_IS_MEMBER): Handle the new CPU_* values and INSN_* flags. - Don't match CPU_R4111 with INSN_4100. - -2002-08-19 Elena Zannoni <ezannoni@redhat.com> - - From matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500 - instructions. - (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR, - PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the - e500x2 Integer select, branch locking, performance monitor, - cache locking and machine check APUs, respectively. - (PPC_OPCODE_EFS): New opcode type for efs* instructions. - (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions. - -2002-08-13 Stephane Carrez <stcarrez@nerim.fr> - - * m68hc11.h (M6812_OP_PAGE): Define to identify call operand. - (M68HC12_BANK_VIRT, M68HC12_BANK_MASK, M68HC12_BANK_BASE, - M68HC12_BANK_SHIFT, M68HC12_BANK_PAGE_MASK): Define for 68HC12 - memory banks. - (M6811_OC1M5, M6811_OC1M4, M6811_MODF): Fix value. - -2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_MIPS16): New define. - -2002-07-08 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Remove IgnoreSize from movsx and movzx. - -2002-06-08 Alan Modra <amodra@bigpond.net.au> - - * a29k.h: Replace CONST with const. - (CONST): Don't define. - * convex.h: Replace CONST with const. - (CONST): Don't define. - * dlx.h: Replace CONST with const. - * or32.h (CONST): Don't define. - -2002-05-30 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (OP_SH_ALN, OP_MASK_ALN, OP_SH_VSEL, OP_MASK_VSEL) - (MDMX_FMTSEL_IMM_QH, MDMX_FMTSEL_IMM_OB, MDMX_FMTSEL_VEC_QH) - (MDMX_FMTSEL_VEC_OB, INSN_READ_MDMX_ACC, INSN_WRITE_MDMX_ACC) - (INSN_MDMX): New constants, for MDMX support. - (opcode character list): Add "O", "Q", "X", "Y", and "Z" for MDMX. - -2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> - - * dlx.h: New file. - -2002-05-25 Alan Modra <amodra@bigpond.net.au> - - * ia64.h: Use #include "" instead of <> for local header files. - * sparc.h: Likewise. - -2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h: Add M_DROL, M_DROL_I, M_DROR, M_DROR_I macro cases. - -2002-05-17 Andrey Volkov <avolkov@sources.redhat.com> - - * h8300.h: Corrected defs of all control regs - and eepmov instr. - -2002-04-11 Alan Modra <amodra@bigpond.net.au> - - * i386.h: Add intel mode cmpsd and movsd. - Put them before SSE2 insns, so that rep prefix works. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips.h (INSN_MIPS3D): New definition used to mark MIPS-3D - instructions. - (OPCODE_IS_MEMBER): Adjust comments to indicate that ASE bit masks - may be passed along with the ISA bitmask. - -2002-03-05 Paul Koning <pkoning@equallogic.com> - - * pdp11.h: Add format codes for float instruction formats. - -2002-02-25 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define. - -Mon Feb 18 17:31:48 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands. - -Mon Feb 11 12:53:19 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386.h (push,pop): Allow 16bit operands in 64bit mode. - (xchg): Fix. - (in, out): Disable 64bit operands. - (call, jmp): Avoid REX prefixes. - (jcxz): Prohibit in 64bit mode - (jrcxz, loop): Add 64bit variants. - (movq): Fix patterns. - (movmskps, pextrw, pinstrw): Add 64bit variants. - -2002-01-31 Ivan Guzvinec <ivang@opencores.org> - - * or32.h: New file. - -2002-01-22 Graydon Hoare <graydon@redhat.com> - - * cgen.h (CGEN_MAYBE_MULTI_IFLD): New structure. - (CGEN_OPERAND): Add CGEN_MAYBE_MULTI_IFLD field. - -2002-01-21 Thomas Klausner <wiz@danbala.ifoer.tuwien.ac.at> - - * h8300.h: Comment typo fix. - -2002-01-03 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE): BookE is not Motorola specific. - (PPC_OPCODE_BOOKE64): Likewise. - -Mon Dec 31 16:45:41 2001 Jeffrey A Law (law@cygnus.com) - - * hppa.h (call, ret): Move to end of table. - (addb, addib): PA2.0 variants should have been PA2.0W. - (ldw, ldh, ldb, stw, sth, stb, stwa): Reorder to keep disassembler - happy. - (fldw, fldd, fstw, fstd, bb): Likewise. - (short loads/stores): Tweak format specifier slightly to keep - disassembler happy. - (indexed loads/stores): Likewise. - (absolute loads/stores): Likewise. - -2001-12-04 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_NOSP): New macro. - -2001-11-29 Alexandre Oliva <aoliva@redhat.com> - - * d10v.h (OPERAND_SP): New macro. - -2001-11-15 Alan Modra <amodra@bigpond.net.au> - - * ppc.h (struct powerpc_operand <insert, extract>): Add dialect param. - -2001-11-11 Timothy Wall <twall@alum.mit.edu> - - * tic54x.h: Revise opcode layout; don't really need a separate - structure for parallel opcodes. - -2001-11-13 Zack Weinberg <zack@codesourcery.com> - Alan Modra <amodra@bigpond.net.au> - - * i386.h (i386_optab): Add entries for "sldr", "smsw" and "str" to - accept WordReg. - -2001-11-04 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Remove extra space. - -2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> - - * mmix.h: New file. - -2001-10-18 Chris Demetriou <cgd@broadcom.com> - - * mips.h (OPCODE_IS_MEMBER): Add a no-op term to the end - of the expression, to make source code merging easier. - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h: Sort coprocessor instruction argument characters - in comment, add a few more words of description for "H". - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips.h (INSN_SB1): New cpu-specific instruction bit. - (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1 - if cpu is CPU_SB1. - -2001-10-17 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE64): Fix typo. - -2001-10-12 matthew green <mrg@redhat.com> - - * ppc.h (PPC_OPCODE_BOOKE, PPC_OPCODE_BOOKE64, PPC_OPCODE_403): New - opcode flags for BookE 32-bit, BookE 64-bit and PowerPC 403 - instructions, respectively. - -2001-09-27 Nick Clifton <nickc@cambridge.redhat.com> - - * v850.h: Remove spurious comment. - -2001-09-21 Nick Clifton <nickc@cambridge.redhat.com> - - * h8300.h: Fix compile time warning messages - -2001-09-04 Richard Henderson <rth@redhat.com> - - * alpha.h (struct alpha_operand): Pack elements into bitfields. - -2001-08-31 Eric Christopher <echristo@redhat.com> - - * mips.h: Remove CPU_MIPS32_4K. - -2001-08-27 Torbjorn Granlund <tege@swox.com> - - * ppc.h (PPC_OPERAND_DS): Define. - -2001-08-25 Andreas Jaeger <aj@suse.de> - - * d30v.h: Fix declaration of reg_name_cnt. - - * d10v.h: Fix declaration of d10v_reg_name_cnt. - - * arc.h: Add prototypes from opcodes/arc-opc.c. - -2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_10000): Define. - (OPCODE_IS_MEMBER): Check for INSN_10000. - -2001-08-10 Alan Modra <amodra@one.net.au> - - * ppc.h: Revert 2001-08-08. - -2001-08-10 Richard Sandiford <rsandifo@redhat.com> - - * mips.h (INSN_GP32): Remove. - (OPCODE_IS_MEMBER): Remove gp32 parameter. - (M_MOVE): New macro identifier. - -2001-08-08 Alan Modra <amodra@one.net.au> - - 1999-10-25 Torbjorn Granlund <tege@swox.com> - * ppc.h (struct powerpc_operand): New field `reloc'. - -2001-08-01 Aldy Hernandez <aldyh@redhat.com> - - * mips.h (INSN_ISA_MASK): Nuke bits 12-15. - -2001-07-12 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_INSN): Add regex support. - (build_insn_regex): Declare. - -2001-07-11 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MACH): Add insn_chunk_bitsize field. - (cgen_cpu_desc): Ditto. - -2001-07-07 Ben Elliston <bje@redhat.com> - - * m88k.h: Clean up and reformat. Remove unused code. - -2001-06-14 Geoffrey Keating <geoffk@redhat.com> - - * cgen.h (cgen_keyword): Add nonalpha_chars field. - -2001-05-23 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (CPU_R12000): Define. - -2001-05-23 John Healy <jhealy@redhat.com> - - * cgen.h: Increased CGEN_MAX_SYNTAX_ELEMENTS to 48. - -2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips.h (INSN_ISA_MASK): Define. - -2001-05-12 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Second operand of cvtps2dq is an xmm reg, - not an mmx reg. Swap xmm/mmx regs on both movdq2q and movq2dq, - and use InvMem as these insns must have register operands. - -2001-05-04 Alan Modra <amodra@one.net.au> - - * i386.h (i386_optab): Move InvMem to first operand of pmovmskb - and pextrw to swap reg/rm assignments. - -2001-04-05 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (enum cris_insn_version_usage): Correct comment for - cris_ver_v3p. - -2001-03-24 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". - Add InvMem to first operand of "maskmovdqu". - -2001-03-22 Hans-Peter Nilsson <hp@axis.com> - - * cris.h (ADD_PC_INCR_OPCODE): New macro. - -2001-03-21 Kazu Hirata <kazu@hxi.com> - - * h8300.h: Fix formatting. - -2001-03-22 Alan Modra <alan@linuxcare.com.au> - - * i386.h (i386_optab): Add paddq, psubq. - -2001-03-19 Alan Modra <alan@linuxcare.com.au> - - * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. - -2001-02-28 Igor Shevlyakov <igor@windriver.com> - - * m68k.h: new defines for Coldfire V4. Update mcf to know - about mcf5407. - -2001-02-18 lars brinkhoff <lars@nocrew.org> - - * pdp11.h: New file. - -2001-02-12 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): SSE integer converison instructions have - 64bit versions on x86-64. - -2001-02-10 Nick Clifton <nickc@redhat.com> - - * mips.h: Remove extraneous whitespace. Formating change to allow - for future contribution. - -2001-02-09 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390.h: New file. - -2001-02-02 Patrick Macdonald <patrickm@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): Typedef as unsigned short. - (CGEN_MAX_SYNTAX_ELEMENTS): Rename from CGEN_MAX_SYNTAX_BYTES. - (CGEN_SYNTAX): Define using CGEN_MAX_SYNTAX_ELEMENTS. - -2001-01-24 Karsten Keil <kkeil@suse.de> - - * i386.h (i386_optab): Fix swapgs - -2001-01-14 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Describe new '<' and '>' operand types, and tidy - existing comments. - (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. - Remove duplicate "ldw j(s,b),x". Sort some entries. - -2001-01-13 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix pusha and ret templates. - -2001-01-11 Peter Targett <peter.targett@arccores.com> - - * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New - definitions for masking cpu type. - (arc_ext_operand_value) New structure for storing extended - operands. - (ARC_OPERAND_*) Flags for operand values. - -2001-01-10 Jan Hubicka <jh@suse.cz> - - * i386.h (pinsrw): Add. - (pshufw): Remove. - (cvttpd2dq): Fix operands. - (cvttps2dq): Likewise. - (movq2q): Rename to movdq2q. - -2001-01-10 Richard Schaal <richard.schaal@intel.com> - - * i386.h: Correct movnti instruction. - -2001-01-09 Jeff Johnston <jjohnstn@redhat.com> - - * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number - of operands (unsigned char or unsigned short). - (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. - (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. - -2001-01-05 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Make [sml]fence template to use immext field. - -2001-01-03 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Fix 64bit pushf template; Add instructions - introduced by Pentium4 - -2000-12-30 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Add "rex*" instructions; - add swapgs; disable jmp/call far direct instructions for - 64bit mode; add syscall and sysret; disable registers for 0xc6 - template. Add 'q' suffixes to extendable instructions, disable - obsolete instructions, add new sign/zero extension ones. - (i386_regtab): Add extended registers. - (*Suf): Add No_qSuf. - (q_Suf, wlq_Suf, bwlq_Suf): New. - -2000-12-20 Jan Hubicka <jh@suse.cz> - - * i386.h (i386_optab): Replace "Imm" with "EncImm". - (i386_regtab): Add flags field. - -2000-12-12 Nick Clifton <nickc@redhat.com> - - * mips.h: Fix formatting. - -2000-12-01 Chris Demetriou <cgd@sibyte.com> - - mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. - (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old - OP_*_SYSCALL definitions. - (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as - 19 bit wait codes. - (MIPS operand specifier comments): Remove 'm', add 'U' and - 'J', and update the meaning of 'B' so that it's more general. - - * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, - INSN_ISA5): Renumber, redefine to mean the ISA at which the - instruction was added. - (INSN_ISA32): New constant. - (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): - Renumber to avoid new and/or renumbered INSN_* constants. - (INSN_MIPS32): Delete. - (ISA_UNKNOWN): New constant to indicate unknown ISA. - (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, - ISA_MIPS32): New constants, defined to be the mask of INSN_* - constants available at that ISA level. - (CPU_UNKNOWN): New constant to indicate unknown CPU. - (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, - define it with a unique value. - (OPCODE_IS_MEMBER): Update for new ISA membership-related - constant meanings. - - * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New - definitions. - - * mips.h (CPU_SB1): New constant. - -2000-10-20 Jakub Jelinek <jakub@redhat.com> - - * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. - Note that '3' is used for siam operand. - -2000-09-22 Jim Wilson <wilson@cygnus.com> - - * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. - -2000-09-13 Anders Norlander <anorland@acc.umu.se> - - * mips.h: Use defines instead of hard-coded processor numbers. - (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, - CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, - CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, - CPU_4KC, CPU_4KM, CPU_4KP): Define.. - (OPCODE_IS_MEMBER): Use new defines. - (OP_MASK_SEL, OP_SH_SEL): Define. - (OP_MASK_CODE20, OP_SH_CODE20): Define. - Add 'P' to used characters. - Use 'H' for coprocessor select field. - Use 'm' for 20 bit breakpoint code. - Document new arg characters and add to used characters. - (INSN_MIPS32): New define for MIPS32 extensions. - (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. - -2000-09-05 Alan Modra <alan@linuxcare.com.au> - - * hppa.h: Mention cz completer. - -2000-08-16 Jim Wilson <wilson@cygnus.com> - - * ia64.h (IA64_OPCODE_POSTINC): New. - -2000-08-15 H.J. Lu <hjl@gnu.org> - - * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the - IgnoreSize change. - -2000-08-08 Jason Eckhardt <jle@cygnus.com> - - * i860.h: Small formatting adjustments. - -2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. - Move related opcodes closer to each other. - Minor changes in comments, list undefined opcodes. - -2000-07-26 Dave Brolley <brolley@redhat.com> - - * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. - -2000-07-22 Jason Eckhardt <jle@cygnus.com> - - * i860.h (btne, bte, bla): Changed these opcodes - to use sbroff ('r') instead of split16 ('s'). - (J, K, L, M): New operand types for 16-bit aligned fields. - (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to - use I, J, K, L, M instead of just I. - (T, U): New operand types for split 16-bit aligned fields. - (st.x): Changed these opcodes to use S, T, U instead of just S. - (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not - exist on the i860. - (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. - (pfeq.ss, pfeq.dd): New opcodes. - (st.s): Fixed incorrect mask bits. - (fmlow): Fixed incorrect mask bits. - (fzchkl, pfzchkl): Fixed incorrect mask bits. - (faddz, pfaddz): Fixed incorrect mask bits. - (form, pform): Fixed incorrect mask bits. - (pfld.l): Fixed incorrect mask bits. - (fst.q): Fixed incorrect mask bits. - (all floating point opcodes): Fixed incorrect mask bits for - handling of dual bit. - -2000-07-20 Hans-Peter Nilsson <hp@axis.com> - - cris.h: New file. - -2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. - (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. - (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. - (AVR_ISA_M83): Define for ATmega83, ATmega85. - (espm): Remove, because ESPM removed in databook update. - (eicall, eijmp): Move to the end of opcode table. - -2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> - - * m68hc11.h: New file for support of Motorola 68hc11. - -Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: clr,lsl,rol, ... moved after add,adc, ... - -Wed Jun 7 21:39:54 2000 Denis Chertykov <denisc@overta.ru> - - * avr.h: New file with AVR opcodes. - -Wed Apr 12 17:11:20 2000 Donald Lindsay <dlindsay@hound.cygnus.com> - - * d10v.h: added ALONE attribute for d10v_opcode.exec_type. - -2000-05-23 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Allow d suffix on iret, and add DefaultSize modifier. - -2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * i386.h: Use sl_FP, not sl_Suf for fild. - -2000-05-16 Frank Ch. Eigler <fche@redhat.com> - - * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that - it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. - (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds - CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - - * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. - -2000-05-13 Alan Modra <alan@linuxcare.com.au>, - Alexander Sokolov <robocop@netlink.ru> - - * i386.h (i386_optab): Add cpu_flags for all instructions. - -2000-05-13 Alan Modra <alan@linuxcare.com.au> - - From Gavin Romig-Koch <gavin@cygnus.com> - * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. - -2000-05-04 Timothy Wall <twall@cygnus.com> - - * tic54x.h: New. - -2000-05-03 J.T. Conklin <jtc@redback.com> - - * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. - (PPC_OPERAND_VR): New operand flag for vector registers. - -2000-05-01 Kazu Hirata <kazu@hxi.com> - - * h8300.h (EOP): Add missing initializer. - -Fri Apr 21 15:03:37 2000 Jason Eckhardt <jle@cygnus.com> - - * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode - forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). - New operand types l,y,&,fe,fE,fx added to support above forms. - (pa_opcodes): Replaced usage of 'x' as source/target for - floating point double-word loads/stores with 'fx'. - -Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> - David Mosberger <davidm@hpl.hp.com> - Timothy Wall <twall@cygnus.com> - Jim Wilson <wilson@cygnus.com> - - * ia64.h: New file. - -2000-03-27 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_A1): Fix value. - (SHORT_AR): Renumber so that it is at the end of the list of short - instructions, not the end of the list of long instructions. - -2000-03-26 Alan Modra <alan@linuxcare.com> - - * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the - problem isn't really specific to Unixware. - (OLDGCC_COMPAT): Define. - (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with - destination %st(0). - Fix lots of comments. - -2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d30v.h: - (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. - (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. - (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. - (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. - (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. - (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. - (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. - -2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (fild, fistp): Change intel d_Suf form to fildd and - fistpd without suffix. - -2000-02-24 Nick Clifton <nickc@cygnus.com> - - * cgen.h (cgen_cpu_desc): Rename field 'flags' to - 'signed_overflow_ok_p'. - Delete prototypes for cgen_set_flags() and cgen_get_flags(). - -2000-02-24 Andrew Haley <aph@cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - (CGEN_CPU_TABLE): flags: new field. - Add prototypes for new functions. - -2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add some more UNIXWARE_COMPAT comments. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370.h: New file. - -2000-02-22 Chandra Chavva <cchavva@cygnus.com> - - * d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation - cannot be combined in parallel with ADD/SUBppp. - -2000-02-22 Andrew Haley <aph@cygnus.com> - - * mips.h: (OPCODE_IS_MEMBER): Add comment. - -1999-12-30 Andrew Haley <aph@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines - whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit - insns. - -2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Qualify intel mode far call and jmp with x_Suf. - -1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add JumpAbsolute qualifier to all non-intel mode - indirect jumps and calls. Add FF/3 call for intel mode. - -Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add new operand types. Add new instruction formats. - -Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" - instruction. - -1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_ISA5): New. - -1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (OPCODE_IS_MEMBER): New. - -1999-10-29 Nick Clifton <nickc@cygnus.com> - - * d30v.h (SHORT_AR): Define. - -1999-10-18 Michael Meissner <meissner@cygnus.com> - - * alpha.h (alpha_num_opcodes): Convert to unsigned. - (alpha_num_operands): Ditto. - -Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> - - * hppa.h (pa_opcodes): Add load and store cache control to - instructions. Add ordered access load and store. - - * hppa.h (pa_opcode): Add new entries for addb and addib. - - * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. - - * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. - -Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> - - * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. - -Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" - and "be" using completer prefixes. - - * hppa.h (pa_opcodes): Add initializers to silence compiler. - - * hppa.h: Update comments about character usage. - -Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning - up the new fstw & bve instructions. - -Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store - instructions. - - * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. - - * hppa.h (pa_opcodes): Add long offset double word load/store - instructions. - - * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and - stores. - - * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. - - * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. - - * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. - - * hppa.h (pa_opcodes): Add new syntax "be" instructions. - - * hppa.h (pa_opcodes): Note use of 'M' and 'L'. - - * hppa.h (pa_opcodes): Add support for "b,l". - - * hppa.h (pa_opcodes): Add support for "b,gate". - -Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Use 'fX' for first register operand - in xmpyu. - - * hppa.h (pa_opcodes): Fix mask for probe and probei. - - * hppa.h (pa_opcodes): Fix mask for depwi. - -Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as - an explicit output argument. - -Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. - Add a few PA2.0 loads and store variants. - -1999-09-04 Steve Chamberlain <sac@pobox.com> - - * pj.h: New file. - -1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Move %st to top of table, and split off - other fp reg entries. - (i386_float_regtab): To here. - -Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args - by 'f'. - - * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. - Add supporting args. - - * hppa.h: Document new completers and args. - * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, - uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 - extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions - pmenb and pmdis. - - * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, - hshr, hsub, mixh, mixw, permh. - - * hppa.h (pa_opcodes): Change completers in instructions to - use 'c' prefix. - - * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, - hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. - - * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, - fnegabs to use 'I' instead of 'F'. - -1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. - Document pf2iw and pi2fw as athlon insns. Remove pswapw. - Alphabetically sort PIII insns. - -Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. - -Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, - and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. - - * hppa.h: Document 64 bit condition completers. - -Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> - - * hppa.h (pa_opcodes): Change condition args to use '?' prefix. - -1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add DefaultSize modifier to all insns - that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, - sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. - -Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". - - * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. - - * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, - and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. - -1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. - -Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (struct pa_opcode): Add new field "flags". - (FLAGS_STRICT): Define. - -Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> - Jeff Law <law@cygnus.com> - - * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. - - * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. - -1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, - lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP - flag to fcomi and friends. - -Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Move integer arithmetic instructions after - integer logical instructions. - -1999-05-28 Linus Nordberg <linus.nordberg@canit.se> - - * m68k.h: Document new formats `E', `G', `H' and new places `N', - `n', `o'. - - * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' - and new places `m', `M', `h'. - -Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com - - * hppa.h (pa_opcodes): Add several processor specific system - instructions. - -Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pa_opcodes): Add second entry for "comb", "comib", - "addb", and "addib" to be used by the disassembler. - -1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> - - * i386.h (ReverseModrm): Remove all occurences. - (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, - movmskps, pextrw, pmovmskb, maskmovq. - Change NoSuf to FP on all MMX, XMM and AMD insns as these all - ignore the data size prefix. - - * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. - Mostly stolen from Doug Ledford <dledford@redhat.com> - -Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> - - * ppc.h (PPC_OPCODE_64_BRIDGE): New. - -1999-04-14 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR): Delete member num_nonbools. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_MASK): Number booleans starting at 0. - (CGEN_ATTR_VALUE): Update. - (CGEN_INSN_ATTR): Update. - -Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 - instructions. - -Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bb, bvb): Tweak opcode/mask. - - -1999-03-22 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. - (struct cgen_cpu_desc): Rename member mach to machs. New member isas. - New members word_bitsize,default_insn_bitsize,base_insn-bitsize, - min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. - Delete member max_insn_size. - (enum cgen_cpu_open_arg): New enum. - (cpu_open): Update prototype. - (cpu_open_1): Declare. - (cgen_set_cpu): Delete. - -1999-03-11 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. - (CGEN_OPERAND_NIL): New macro. - (CGEN_OPERAND): New member `type'. - (@arch@_cgen_operand_table): Delete decl. - (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. - (CGEN_OPERAND_TABLE): New struct. - (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. - (CGEN_OPINST): Pointer to operand table entry replaced with enum. - (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', - now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to - {get,set}_{int,vma}_operand. - (@arch@_cgen_cpu_open): New arg `isa'. - (cgen_set_cpu): Ditto. - -Fri Feb 26 02:36:45 1999 Richard Henderson <rth@cygnus.com> - - * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. - -1999-02-25 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. - (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to - enum cgen_hw_type. - (CGEN_HW_TABLE): New struct. - (hw_table): Delete declaration. - (CGEN_OPERAND): Change member hw to hw_type, change type from pointer - to table entry to enum. - (CGEN_OPINST): Ditto. - (CGEN_CPU_TABLE): Change member hw_list to hw_table. - -Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> - - * alpha.h (AXP_OPCODE_EV6): New. - (AXP_OPCODE_NOPAL): Include it. - -1999-02-09 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. - All uses updated. New members int_insn_p, max_insn_size, - parse_operand,insert_operand,extract_operand,print_operand, - sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, - get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, - extract_handlers,print_handlers. - (CGEN_ATTR): Change type of num_nonbools to unsigned int. - (CGEN_ATTR_BOOL_OFFSET): New macro. - (CGEN_ATTR_MASK): Subtract it to compute bit number. - (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. - (cgen_opcode_handler): Renamed from cgen_base. - (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. - (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, - all uses updated. - (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. - (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. - (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. - (CGEN_OPCODE,CGEN_IBASE): New types. - (CGEN_INSN): Rewrite. - (CGEN_{ASM,DIS}_HASH*): Delete. - (init_opcode_table,init_ibld_table): Declare. - (CGEN_INSN_ATTR): New type. - -Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> - - * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. - (x_FP, d_FP, dls_FP, sldx_FP): Define. - Change *Suf definitions to include x and d suffixes. - (movsx): Use w_Suf and b_Suf. - (movzx): Likewise. - (movs): Use bwld_Suf. - (fld): Change ordering. Use sld_FP. - (fild): Add Intel Syntax equivalent of fildq. - (fst): Use sld_FP. - (fist): Use sld_FP. - (fstp): Use sld_FP. Add x_FP version. - (fistp): LLongMem version for Intel Syntax. - (fcom, fcomp): Use sld_FP. - (fadd, fiadd, fsub): Use sld_FP. - (fsubr): Use sld_FP. - (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. - -1999-01-27 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, - CGEN_MODE_UINT. - -1999-01-16 Jeffrey A Law (law@cygnus.com) - - * hppa.h (bv): Fix mask. - -1999-01-05 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. - (CGEN_ATTR): Use it. - (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. - (CGEN_ATTR_TABLE): New member dfault. - -1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (MIPS16_INSN_BRANCH): New. - -Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> - - The following is part of a change made by Edith Epstein - <eepstein@sophia.cygnus.com> as part of a project to merge in - changes by HP; HP did not create ChangeLog entries. - - * hppa.h (completer_chars): list of chars to not put a space - after. - -Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (i386_optab): Permit w suffix on processor control and - status word instructions. - -1998-11-30 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (struct cgen_hw_entry): Delete const on attrs member. - (struct cgen_keyword_entry): Ditto. - (struct cgen_operand): Ditto. - (CGEN_IFLD): New typedef, with associated access macros. - (CGEN_IFMT): New typedef, with associated access macros. - (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. - (CGEN_IVALUE): New typedef. - (struct cgen_insn): Delete const on syntax,attrs members. - `format' now points to format data. Type of `value' is now - CGEN_IVALUE. - (struct cgen_opcode_table): New member ifld_table. - -1998-11-18 Doug Evans <devans@casey.cygnus.com> - - * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. - (CGEN_OPERAND_INSTANCE): New member `attrs'. - (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. - (cgen_dis_lookup_insn): Update type of `base_insn' arg. - (cgen_opcode_table): Update type of dis_hash fn. - (extract_operand): Update type of `insn_value' arg. - -Thu Oct 29 11:38:36 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. - -Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com> - - * mips.h (INSN_MULT): Added. - -Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. - -Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_INT): New typedef. - (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. - (CGEN_INSN_BYTES): Renamed from cgen_insn_t. - (CGEN_INSN_BYTES_PTR): New typedef. - (CGEN_EXTRACT_INFO): New typedef. - (cgen_insert_fn,cgen_extract_fn): Update. - (cgen_opcode_table): New member `insn_endian'. - (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. - (insert_operand,extract_operand): Update. - (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. - -Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_BOOLS): New macro. - (struct CGEN_HW_ENTRY): New member `attrs'. - (CGEN_HW_ATTR): New macro. - (struct CGEN_OPERAND_INSTANCE): New member `name'. - (CGEN_INSN_INVALID_P): New macro. - -Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add "fid". - -Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - From Robert Andrew Dale <rob@nb.net> - * i386.h (i386_optab): Add AMD 3DNow! instructions. - (AMD_3DNOW_OPCODE): Define. - -Tue Sep 22 17:53:47 1998 Nick Clifton <nickc@cygnus.com> - - * d30v.h (EITHER_BUT_PREFER_MU): Define. - -Mon Aug 10 14:09:38 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_insn): #if 0 out element `cdx'. - -Mon Aug 3 12:21:57 1998 Doug Evans <devans@seba.cygnus.com> - - Move all global state data into opcode table struct, and treat - opcode table as something that is "opened/closed". - * cgen.h (CGEN_OPCODE_DESC): New type. - (all fns): New first arg of opcode table descriptor. - (cgen_set_parse_operand_fn): Add prototype. - (cgen_current_machine,cgen_current_endian): Delete. - (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, - parse_operand_fn,asm_hash_table,asm_hash_table_entries, - dis_hash_table,dis_hash_table_entries. - (opcode_open,opcode_close): Add prototypes. - - * cgen.h (cgen_insn): New element `cdx'. - -Thu Jul 30 21:44:25 1998 Frank Ch. Eigler <fche@cygnus.com> - - * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. - -Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "no_match_operands" field for instructions. - (MN10300_MAX_OPERANDS): Define. - -Fri Jul 24 11:44:24 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (cgen_macro_insn_count): Declare. - -Tue Jul 21 13:12:13 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. - (cgen_insert_fn,cgen_extract_fn): New arg `pc'. - (get_operand,put_operand): Replaced with get_{int,vma}_operand, - set_{int,vma}_operand. - -Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) - - * mn10300.h: Add "machine" field for instructions. - (MN103, AM30): Define machine types. - -Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. - -1998-06-18 Ulrich Drepper <drepper@cygnus.com> - - * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. - -Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Add general form of aad and aam. Add ud2a - and ud2b. - (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just - those that happen to be implemented on pentiums. - -Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, - IgnoreDataSize to IgnoreSize. Flag address and data size prefixes - with Size16|IgnoreSize or Size32|IgnoreSize. - -Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. - (REPE): Rename to REPE_PREFIX_OPCODE. - (i386_regtab_end): Remove. - (i386_prefixtab, i386_prefixtab_end): Remove. - (i386_optab): Use NULL as sentinel rather than "" to suit rewrite - of md_begin. - (MAX_OPCODE_SIZE): Define. - (i386_optab_end): Remove. - (sl_Suf): Define. - (sl_FP): Use sl_Suf. - - * i386.h (i386_optab): Allow 16 bit displacement for `mov - mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 - bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, - data32, dword, and adword prefixes. - (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index - regs. - -Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_regtab): Remove BaseIndex modifier from esp. - - * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with - register operands, because this is a common idiom. Flag them with - a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, - fdivrp because gcc erroneously generates them. Also flag with a - warning. - - * i386.h: Add suffix modifiers to most insns, and tighter operand - checks in some cases. Fix a number of UnixWare compatibility - issues with float insns. Merge some floating point opcodes, using - new FloatMF modifier. - (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for - consistency. - - * i386.h: Change occurence of ShortformW to W|ShortForm. Add - IgnoreDataSize where appropriate. - -Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: (one_byte_segment_defaults): Remove. - (two_byte_segment_defaults): Remove. - (i386_regtab): Add BaseIndex to 32 bit regs reg_type. - -Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. - (cgen_hw_lookup_by_num): Declare. - -Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com> - - * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower - ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" - -Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com> - - * cgen.h (cgen_asm_init_parse): Delete. - (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. - (cgen_asm_record_register,cgen_asm_finish_insn): Delete. - -Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. - (cgen_asm_finish_insn): Update prototype. - (cgen_insn): New members num, data. - (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, - dis_hash, dis_hash_table_size moved to ... - (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. - All uses updated. New members asm_hash_p, dis_hash_p. - (CGEN_MINSN_EXPANSION): New struct. - (cgen_expand_macro_insn): Declare. - (cgen_macro_insn_count): Declare. - (get_insn_operands): Update prototype. - (lookup_get_insn_operands): Declare. - -Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Change iclrKludge and imulKludge to - regKludge. Add operands types for string instructions. - -Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (X): Renamed from `Z_' to preserve formatting of opcode - table. - -Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com> - - * i386.h (Z_): Renamed from `_' to avoid clash with common alias - for `gettext'. - -Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h: Remove NoModrm flag from all insns: it's never checked. - Add IsString flag to string instructions. - (IS_STRING): Don't define. - (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. - (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. - (SS_PREFIX_OPCODE): Define. - -Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert March 24 patch; no more LinearAddress. - -Mon Mar 30 10:25:54 1998 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove fwait (9b) from all floating point - instructions, and instead add FWait opcode modifier. Add short - form of fldenv and fstenv. - (FWAIT_OPCODE): Define. - - * i386.h (i386_optab): Change second operand constraint of `mov - sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to - allow legal instructions such as `movl %gs,%esi' - -Fri Mar 27 18:30:52 1998 Ian Lance Taylor <ian@cygnus.com> - - * h8300.h: Various changes to fully bracket initializers. - -Tue Mar 24 18:32:47 1998 H.J. Lu <hjl@gnu.org> - - * i386.h: Set LinearAddress for lidt and lgdt. - -Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_BOOL_ATTR): New macro. - -Thu Feb 26 15:54:31 1998 Michael Meissner <meissner@cygnus.com> - - * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. - -Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. - (cgen_insn): Record syntax and format entries here, rather than - separately. - -Tue Feb 17 21:42:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro. - -Tue Feb 17 16:00:56 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (cgen_insert_fn): Change type of result to const char *. - (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. - (CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS. - -Thu Feb 12 18:30:41 1998 Doug Evans <devans@canuck.cygnus.com> - - * cgen.h (lookup_insn): New argument alias_p. - -Thu Feb 12 03:41:00 1998 J"orn Rennecke <amylaar@cygnus.co.uk> - -Fix rac to accept only a0: - * d10v.h (OPERAND_ACC): Split into: - (OPERAND_ACC0, OPERAND_ACC1) . - (OPERAND_GPR): Define. - -Wed Feb 11 17:31:53 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_FIELDS): Define here. - (CGEN_HW_ENTRY): New member `type'. - (hw_list): Delete decl. - (enum cgen_mode): Declare. - (CGEN_OPERAND): New member `hw'. - (enum cgen_operand_instance_type): Declare. - (CGEN_OPERAND_INSTANCE): New type. - (CGEN_INSN): New member `operands'. - (CGEN_OPCODE_DATA): Make hw_list const. - (get_insn_operands,lookup_insn): Add prototypes for. - -Tue Feb 3 17:11:23 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS. - (CGEN_HW_ENTRY): Move `next' entry to end of struct. - (CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS. - (CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS. - -Mon Feb 2 19:19:15 1998 Ian Lance Taylor <ian@cygnus.com> - - * cgen.h: Correct typo in comment end marker. - -Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> - - * tic30.h: New file. - -Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Add prototypes for cgen_save_fixups(), - cgen_restore_fixups(), and cgen_swap_fixups(). Change prototype - of cgen_asm_finish_insn() to return a char *. - -Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> - - * cgen.h: Formatting changes to improve readability. - -Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> - - * cgen.h (*): Clean up pass over `struct foo' usage. - (CGEN_ATTR): Make unsigned char. - (CGEN_ATTR_TYPE): Update. - (CGEN_ATTR_{ENTRY,TABLE}): New types. - (cgen_base): Move member `attrs' to cgen_insn. - (CGEN_KEYWORD): New member `null_entry'. - (CGEN_{SYNTAX,FORMAT}): New types. - (cgen_insn): Format and syntax separated from each other. - -Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for - 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make - flags_{used,set} long. - (d30v_operand): Make flags field long. - -Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> - - * m68k.h: Fix comment describing operand types. - -Sun Nov 23 22:31:27 1997 Michael Meissner <meissner@cygnus.com> - - * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move - everything else after down. - -Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> - - * d10v.h (OPERAND_FLAG): Split into: - (OPERAND_FFLAG, OPERAND_CFLAG) . - -Thu Nov 13 11:04:24 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): Changed comments to reflect new - field usage. - -Fri Oct 24 22:36:20 1997 Ken Raeburn <raeburn@cygnus.com> - - * mips.h: Added to comments a quick-ref list of all assigned - operand type characters. - (OP_{MASK,SH}_PERFREG): New macros. - -Wed Oct 22 17:28:33 1997 Richard Henderson <rth@cygnus.com> - - * sparc.h: Add '_' and '/' for v9a asr's. - Patch from David Miller <davem@vger.rutgers.edu> - -Tue Oct 14 13:22:29 1997 Jeffrey A Law (law@cygnus.com) - - * h8300.h: Bit ops with absolute addresses not in the 8 bit - area are not available in the base model (H8/300). - -Thu Sep 25 13:03:41 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Remove documentation of ` operand specifier. - -Wed Sep 24 19:00:34 1997 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document q and v operand specifiers. - -Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add processors field. - (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. - (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. - (PROCESSOR_V850EA): New bit constants. - -Mon Sep 15 11:29:43 1997 Ken Raeburn <raeburn@cygnus.com> - - Merge changes from Martin Hunt: - - * d30v.h: Allow up to 64 control registers. Add - SHORT_A5S format. - - * d30v.h (LONG_Db): New form for delayed branches. - - * d30v.h: (LONG_Db): New form for repeati. - - * d30v.h (SHORT_D2B): New form. - - * d30v.h (SHORT_A2): New form. - - * d30v.h (OPERAND_2REG): Add new operand to indicate 2 - registers are used. Needed for VLIW optimization. - -Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: Move assembler interface section - up so cgen_parse_operand_result is defined for cgen_parse_address. - (cgen_parse_address): Update prototype. - -Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. - -Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h (two_byte_segment_defaults): Correct base register 5 in - modes 1 and 2 to be ss rather than ds. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Set ud2 to 0x0f0b. From Gabriel Paubert - <paubert@iram.es>. - - * i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert - <paubert@iram.es>. - - * i386.h (JUMP_ON_CX_ZERO): Uncomment (define again). - (JUMP_ON_ECX_ZERO): Remove commented out macro. - -Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (V850_NOT_R0): New flag. - -Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Remove flags field. - -Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> - - * v850.h (struct v850_opcode): Add flags field. - (struct v850_operand): Extend meaning of 'bits' and 'shift' - fields. - (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. - (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. - -Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> - - * arc.h: New file. - -Thu Jul 24 21:16:58 1997 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_opcodes): Declare as const. - -Thu Jul 10 12:53:25 1997 Jeffrey A Law (law@cygnus.com) - - * mips.h (FP_S, FP_D): Define. Bitmasks indicating if an insn - uses single or double precision floating point resources. - (INSN_NO_ISA, INSN_ISA1): Define. - (cpu specific INSN macros): Tweak into bitmasks outside the range - of INSN_ISA field. - -Mon Jun 16 14:10:00 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Fix pand opcode. - -Mon Jun 2 11:35:09 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h: Widen INSN_ISA and move it to a more convenient - bit position. Add INSN_3900. - -Tue May 20 11:25:29 1997 Gavin Koch <gavin@cygnus.com> - - * mips.h (struct mips_opcode): added new field membership. - -Mon May 12 16:26:50 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h (movd): only Reg32 is allowed. - - * i386.h: add fcomp and ud2. From Wayne Scott - <wscott@ichips.intel.com>. - -Mon May 5 17:16:21 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add MMX instructions. - -Mon May 5 12:45:19 1997 H.J. Lu <hjl@gnu.ai.mit.edu> - - * i386.h: Remove W modifier from conditional move instructions. - -Mon Apr 14 14:56:58 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change the opcodes for fsubp, fsubrp, fdivp, and fdivrp - with no arguments to match that generated by the UnixWare - assembler. - -Thu Apr 10 14:35:00 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h (<cpu>_cgen_assemble_insn): New arg for errmsg. - (cgen_parse_operand_fn): Declare. - (cgen_init_parse_operand): Declare. - (cgen_parse_operand): Renamed from cgen_asm_parse_operand, - new argument `want'. - (enum cgen_parse_operand_result): Renamed from cgen_asm_result. - (enum cgen_parse_operand_type): New enum. - -Sat Apr 5 13:14:05 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Revert last patch for the NON_BROKEN_OPCODES cases. - -Fri Apr 4 11:46:11 1997 Doug Evans <dje@canuck.cygnus.com> - - * cgen.h: New file. - -Fri Apr 4 14:02:32 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and - fdivrp. - -Tue Mar 25 22:57:26 1997 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h (extract): Make unsigned. - -Mon Mar 24 14:38:15 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Add iclr. - -Thu Mar 20 19:49:10 1997 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Change DW to W for cmpxchg and xadd, since they don't - take a direction bit. - -Sat Mar 15 19:03:29 1997 H.J. Lu <hjl@lucon.org> - - * sparc.h (sparc_opcode_lookup_arch): Use full prototype. - -Fri Mar 14 15:22:01 1997 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h: Include <ansidecl.h>. Update function declarations to - use prototypes, and to use const when appropriate. - -Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_RELAX): Define. - -Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Change pre_defined_registers to - d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. - -Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> - - * mips.h: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, - and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table - dynamically. - -Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h (FLAG_X): Remove unused flag. - -Tue Feb 18 17:37:20 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d30v.h: New file. - -Fri Feb 14 13:16:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. - (PDS_VALUE): Macro to access value field of predefined symbols. - (tic80_next_predefined_symbol): Add prototype. - -Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (tic80_symbol_to_value): Change prototype to match - change in function, added class parameter. - -Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 - endmask fields, which are somewhat weird in that 0 and 32 are - treated exactly the same. - -Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h: Change all the OPERAND defines to use the form (1 << X) - rather than a constant that is 2**X. Reorder them to put bits for - operands that have symbolic names in the upper bits, so they can - be packed into an int where the lower bits contain the value that - corresponds to that symbolic name. - (predefined_symbo): Add struct. - (tic80_predefined_symbols): Declare array of translations. - (tic80_num_predefined_symbols): Declare size of that array. - (tic80_value_to_symbol): Declare function. - (tic80_symbol_to_value): Declare function. - -Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_RELAX): Define. - -Sat Jan 18 15:18:59 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot - be the destination register. - -Thu Jan 16 20:48:55 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Change "format" field to "flags". - (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. - (TIC80_VECTOR): Define a flag bit for the flags. This one means - that the opcode can have two vector instructions in a single - 32 bit word and we have to encode/decode both. - -Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_PCREL): Renamed from - TIC80_OPERAND_RELATIVE for PC relative. - (TIC80_OPERAND_BASEREL): New flag bit for register - base relative. - -Mon Jan 13 15:56:38 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. - -Mon Jan 6 10:51:15 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional - ":s" modifier for scaling. - -Sun Jan 5 12:12:19 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". - (TIC80_OPERAND_M_LI): Ditto - -Sat Jan 4 19:02:44 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. - (TIC80_OPERAND_CC): New define for condition code operand. - (TIC80_OPERAND_CR): New define for control register operand. - -Fri Jan 3 16:22:23 1997 Fred Fish <fnf@cygnus.com> - - * tic80.h (struct tic80_opcode): Name changed. - (struct tic80_opcode): Remove format field. - (struct tic80_operand): Add insertion and extraction functions. - (TIC80_OPERAND_*): Remove old bogus values, start adding new - correct ones. - (FMT_*): Ditto. - -Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> - - * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust - type IV instruction offsets. - -Fri Dec 27 22:23:10 1996 Fred Fish <fnf@cygnus.com> - - * tic80.h: New file. - -Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h (MN10200_OPERAND_NOCHECK): Define. - -Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> - - * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. - * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. - * v850.h: Fix comment, v850_operand not powerpc_operand. - -Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) - - * mn10200.h: Flesh out structures and definitions needed by - the mn10200 assembler & disassembler. - -Tue Nov 26 10:46:56 1996 Ian Lance Taylor <ian@cygnus.com> - - * mips.h: Add mips16 definitions. - -Mon Nov 25 17:56:54 1996 J.T. Conklin <jtc@cygnus.com> - - * m68k.h: Document new <, >, m, n, o and p operand specifiers. - -Wed Nov 20 10:59:41 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PCREL): Define. - (MN10300_OPERAND_MEMADDR): Define. - -Tue Nov 19 13:30:40 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REG_LIST): Define. - -Wed Nov 6 13:41:08 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_SPLIT): Define. - -Tue Nov 5 13:26:12 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_EXTENDED): Define. - -Mon Nov 4 12:52:48 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_REPEATED): Define. - -Fri Nov 1 10:31:02 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: Don't include "bfd.h"; private relocation types are now - negative to minimize problems with shared libraries. Organize - instruction subsets by AMASK extensions and PALcode - implementation. - (struct alpha_operand): Move flags slot for better packing. - -Tue Oct 29 12:19:10 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_RELAX): New operand flag. - -Thu Oct 10 14:29:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (FMT_*): Move operand format definitions - here. - -Tue Oct 8 14:48:07 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (MN10300_OPERAND_PAREN): Define. - -Mon Oct 7 16:52:11 1996 Jeffrey A Law (law@cygnus.com) - - * mn10300.h (mn10300_opcode): Add "format" field. - (MN10300_OPERAND_*): Define. - -Thu Oct 3 10:33:46 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: Delete. - * mn10200.h, mn10300.h: New files. - -Wed Oct 2 21:31:26 1996 Jeffrey A Law (law@cygnus.com) - - * mn10x00.h: New file. - -Fri Sep 27 18:26:46 1996 Stu Grossman (grossman@critters.cygnus.com) - - * v850.h: Add new flag to indicate this instruction uses a PC - displacement. - -Fri Sep 13 14:58:13 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (stmac): Add missing instruction. - -Sat Aug 31 16:02:03 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (v850_opcode): Remove "size" field. Add "memop" - field. - -Fri Aug 23 10:39:08 1996 Jeffrey A Law (law@cygnus.com) - - * v850.h (V850_OPERAND_EP): Define. - - * v850.h (v850_opcode): Add size field. - -Thu Aug 22 16:51:25 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add insert and extract fields, pointers - to functions used to handle unusual operand encoding. - (V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC, - V850_OPERAND_SIGNED): Defined. - -Wed Aug 21 17:45:10 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h (v850_operands): Add flags field. - (OPERAND_REG, OPERAND_NUM): Defined. - -Tue Aug 20 14:52:02 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * v850.h: New file. - -Fri Aug 16 14:44:15 1996 James G. Smith <jsmith@cygnus.co.uk> - - * mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM, - OP_MASK_COP1NORM, OP_SH_COP1SPEC, OP_MASK_COP1SPEC, - OP_MASK_COP1SCLR, OP_MASK_COP1CMP, OP_SH_COP1CMP, OP_SH_FORMAT, - OP_MASK_FORMAT, OP_SH_TRUE, OP_MASK_TRUE, OP_SH_GE, OP_MASK_GE, - OP_SH_UNSIGNED, OP_MASK_UNSIGNED, OP_SH_HINT, OP_MASK_HINT): - Defined. - -Fri Aug 16 00:15:15 1996 Jeffrey A Law (law@cygnus.com) - - * hppa.h (pitlb, pitlbe, iitlba, iitlbp, fic, fice): Accept - a 3 bit space id instead of a 2 bit space id. - -Thu Aug 15 13:11:46 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Add some additional defines to support the - assembler in determining which operations can be done in parallel. - -Tue Aug 6 11:13:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SN): Define. - (eepmov.b): Renamed from "eepmov" - (nop, bpt, rte, rts, sleep, clrmac): These have no size associated - with them. - -Fri Jul 26 11:47:10 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (OPERAND_SHIFT): New operand flag. - -Thu Jul 25 12:06:22 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: Changes for divs, parallel-only instructions, and - signed numbers. - -Mon Jul 22 11:21:15 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h (pd_reg): Define. Putting the definition here allows - the assembler and disassembler to share the same struct. - -Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (i960_opcodes): "halt" takes an argument. From Stephen - Williams <steve@icarus.com>. - -Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - - * d10v.h: New file. - -Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (band, bclr): Force high bit of immediate nibble to zero. - -Wed Jul 3 14:30:12 1996 J.T. Conklin <jtc@rtl.cygnus.com> - - * m68k.h (mcf5200): New macro. - Document names of coldfire control registers. - -Tue Jul 2 23:05:45 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (SRC_IN_DST): Define. - - * h8300.h (UNOP3): Mark the register operand in this insn - as a source operand, not a destination operand. - (SHIFT_2, SHIFT_IMM): Remove. Eliminate all references. - (UNOP3): Change SHIFT_IMM to IMM for H8/S bitops. Mark - register operand with SRC_IN_DST. - -Fri Jun 21 13:52:17 1996 Richard Henderson <rth@tamu.edu> - - * alpha.h: New file. - -Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com> - - * rs6k.h: Remove obsolete file. - -Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp, - fdivp, and fdivrp. Add ffreep. - -Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> - - * h8300.h: Reorder various #defines for readability. - (ABS32SRC, ABS32DST, DSP32LIST, ABS32LIST, A32LIST): Define. - (BITOP): Accept additional (unused) argument. All callers changed. - (EBITOP): Likewise. - (O_LAST): Bump. - (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. - - * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. - (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. - (BITOP, EBITOP): Handle new H8/S addressing modes for - bit insns. - (UNOP3): Handle new shift/rotate insns on the H8/S. - (insns using exr): New instructions. - (tas, mac, ldmac, clrmac, ldm, stm): New instructions. - -Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (add.l): Undo Apr 5th change. The manual I had - was incorrect. - -Mon May 6 23:38:22 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (START): Remove. - (MEMRELAX): Define. Mark absolute memory operands in mov.b, mov.w - and mov.l insns that can be relaxed. - -Tue Apr 30 18:30:58 1996 Ian Lance Taylor <ian@cygnus.com> - - * i386.h: Remove Abs32 from lcall. - -Mon Apr 22 17:09:23 1996 Doug Evans <dje@blues.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_V9_P): New macro. - (SLCPOP): New macro. - Mark X,Y opcode letters as in use. - -Thu Apr 11 17:28:18 1996 Ian Lance Taylor <ian@cygnus.com> - - * sparc.h (F_FLOAT, F_FBR): Define. - -Fri Apr 5 16:55:34 1996 Jeffrey A Law (law@cygnus.com) - - * h8300.h (ABS8MEM): Renamed from ABSMOV. Remove ABSMOV - from all insns. - (ABS8SRC,ABS8DST): Add ABS8MEM. - (add.l): Fix reg+reg variant. - (eepmov.w): Renamed from eepmovw. - (ldc,stc): Fix many cases. - -Sun Mar 31 13:30:03 1996 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (SPARC_OPCODE_ARCH_MASK): New macro. - -Thu Mar 7 15:08:23 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (O): Mark operand letter as in use. - -Tue Feb 20 20:46:21 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_{encode,decode}_sparclet_cpreg): Declare. - Mark operand letters uU as in use. - -Mon Feb 19 01:59:08 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_SPARCLET. - (sparc_opcode_arch): Delete member `conflicts'. Add `supported'. - (SPARC_OPCODE_SUPPORTED): New macro. - (SPARC_OPCODE_CONFLICT_P): Rewrite. - (F_NOTV9): Delete. - -Fri Feb 16 12:23:34 1996 Jeffrey A Law (law@cygnus.com) - - * sparc.h (sparc_opcode_lookup_arch) Make return type in - declaration consistent with return type in definition. - -Wed Feb 14 18:14:11 1996 Alan Modra <alan@spri.levels.unisa.edu.au> - - * i386.h (i386_optab): Remove Data32 from pushf and popf. - -Thu Feb 8 14:27:21 1996 James Carlson <carlson@xylogics.com> - - * i386.h (i386_regtab): Add 80486 test registers. - -Mon Feb 5 18:35:46 1996 Ian Lance Taylor <ian@cygnus.com> - - * i960.h (I_HX): Define. - (i960_opcodes): Add HX instruction. - -Mon Jan 29 12:43:39 1996 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix waiting forms of finit, fstenv, fsave, fstsw, fstcw, - and fclex. - -Wed Jan 24 22:36:59 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_opcode_arch_val): Replaces sparc_architecture. - (SPARC_OPCODE_CONFLICT_P): Renamed from ARCHITECTURES_CONFLICT_P. - (bfd_* defines): Delete. - (sparc_opcode_archs): Replaces architecture_pname. - (sparc_opcode_lookup_arch): Declare. - (NUMOPCODES): Delete. - -Mon Jan 22 08:24:32 1996 Doug Evans <dje@charmed.cygnus.com> - - * sparc.h (enum sparc_architecture): Add v9a. - (ARCHITECTURES_CONFLICT_P): Update. - -Thu Dec 28 13:27:53 1995 John Hassey <hassey@rtp.dg.com> - - * i386.h: Added Pentium Pro instructions. - -Thu Nov 2 22:59:22 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Document new 'W' operand place. - -Tue Oct 24 10:49:10 1995 Jeffrey A Law (law@cygnus.com) - - * hppa.h: Add lci and syncdma instructions. - -Mon Oct 23 11:09:16 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> - - * mips.h: Added INSN_4100 flag to mark NEC VR4100 specific - instructions. - -Mon Oct 16 10:28:15 1995 Michael Meissner <meissner@tiktok.cygnus.com> - - * ppc.h (PPC_OPCODE_{COMMON,ANY}): New opcode flags for - assembler's -mcom and -many switches. - -Wed Oct 11 16:56:33 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Fix cmpxchg8b extension opcode description. - -Thu Oct 5 18:03:36 1995 Ken Raeburn <raeburn@cygnus.com> - - * i386.h: Add Pentium instructions wrmsr, rdtsc, rdmsr, cmpxchg8b, - and register cr4. - -Tue Sep 19 15:26:43 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68k.h: Change comment: split type P into types 0, 1 and 2. - -Wed Aug 30 13:50:55 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_prefetch): Declare. - -Tue Aug 29 15:34:58 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (sparc_{encode,decode}_{asi,membar}): Declare. - -Wed Aug 2 18:32:19 1995 Ian Lance Taylor <ian@cygnus.com> - - * m68kmri.h: Remove. - - * m68k.h: Move tables into opcodes/m68k-opc.c, leaving just the - declarations. Remove F_ALIAS and flag field of struct - m68k_opcode. Change arch field of struct m68k_opcode to unsigned - int. Make name and args fields of struct m68k_opcode const. - -Wed Aug 2 08:16:46 1995 Doug Evans <dje@canuck.cygnus.com> - - * sparc.h (F_NOTV9): Define. - -Tue Jul 11 14:20:42 1995 Jeff Spiegel <jeffs@lsil.com> - - * mips.h (INSN_4010): Define. - -Wed Jun 21 18:49:51 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (TBL1): Reverse sense of "round" argument in result. - - Changes from Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>: - * m68k.h: Fix argument descriptions of coprocessor - instructions to allow only alterable operands where appropriate. - [!NO_DEFAULT_SIZES]: An omitted size defaults to `w'. - (m68k_opcode_aliases): Add more aliases. - -Fri Apr 14 22:15:34 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h: Added explcitly short-sized conditional branches, and a - bunch of aliases (fmov*, ftest*, tdivul) to support gcc's - svr4-based configurations. - -Mon Mar 13 21:30:01 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Mon Feb 27 08:36:39 1995 Bryan Ford <baford@cs.utah.edu> - * i386.h: added missing Data16/Data32 flags to a few instructions. - -Wed Mar 8 15:19:53 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (OP_MASK_FR, OP_SH_FR): Define. - (OP_MASK_BCC, OP_SH_BCC): Define. - (OP_MASK_PREFX, OP_SH_PREFX): Define. - (OP_MASK_CCC, OP_SH_CCC): Define. - (INSN_READ_FPR_R): Define. - (INSN_RFE): Delete. - -Wed Mar 8 03:13:23 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * m68k.h (enum m68k_architecture): Deleted. - (struct m68k_opcode_alias): New type. - (m68k_opcodes): Now const. Deleted opcode aliases with exactly - matching constraints, values and flags. As a side effect of this, - the MOTOROLA_SYNTAX_ONLY and MIT_SYNTAX_ONLY macros, which so far - as I know were never used, now may need re-examining. - (numopcodes): Now const. - (m68k_opcode_aliases, numaliases): New variables. - (endop): Deleted. - [DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and - m68k_opcode_aliases; update declaration of m68k_opcodes. - -Mon Mar 6 10:02:00 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (delay_type): Delete unused enumeration. - (pa_opcode): Replace unused delayed field with an architecture - field. - (pa_opcodes): Mark each instruction as either PA1.0 or PA1.1. - -Fri Mar 3 16:10:24 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (INSN_ISA4): Define. - -Fri Feb 24 19:13:37 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_DLA_AB, M_DLI): Define. - -Thu Feb 23 17:33:09 1995 Jeff Law (law@snake.cs.utah.edu) - - * hppa.h (fstwx): Fix single-bit error. - -Wed Feb 15 12:19:52 1995 Ian Lance Taylor <ian@cygnus.com> - - * mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define. - -Mon Feb 6 10:35:23 1995 J.T. Conklin <jtc@rtl.cygnus.com> - - * i386.h: added cpuid instruction , and dr[0-7] aliases for the - debug registers. From Charles Hannum (mycroft@netbsd.org). - -Mon Feb 6 03:31:54 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Changes from Bryan Ford <baford@schirf.cs.utah.edu> for 16-bit - i386 support: - * i386.h (MOV_AX_DISP32): New macro. - (i386_optab): Added Data16 and Data32 as needed. Added "w" forms - of several call/return instructions. - (ADDR_PREFIX_OPCODE): New macro. - -Mon Jan 23 16:45:43 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - Sat Jan 21 17:50:38 1995 Pat Rankin (rankin@eql.caltech.edu) - - * vax.h (struct vot_wot, field `args'): Make it pointer to const - char. - (struct vot, field `name'): ditto. - -Thu Jan 19 14:47:53 1995 Ken Raeburn <raeburn@cujo.cygnus.com> - - * vax.h: Supply and properly group all values in end sentinel. - -Tue Jan 17 10:55:30 1995 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * mips.h (INSN_ISA, INSN_4650): Define. - -Wed Oct 19 13:34:17 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> - - * a29k.h: Add operand type 'I' for `inv' and `iretinv'. On - systems with a separate instruction and data cache, such as the - 29040, these instructions take an optional argument. - -Wed Sep 14 17:44:20 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Correct value to not conflict with - INSN_TRAP. - -Tue Sep 6 11:39:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com) - - * mips.h (INSN_STORE_MEMORY): Define. - -Thu Jul 28 19:28:07 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Document new operand type 'x'. - -Tue Jul 26 17:48:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i960.h (I_CX2): New instruction category. It includes - instructions available on Cx and Jx processors. - (I_JX): New instruction category, for JX-only instructions. - (i960_opcodes): Put eshro and sysctl in I_CX2 category. Added - Jx-only instructions, in I_JX category. - -Wed Jul 13 18:43:47 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * ns32k.h (endop): Made pointer const too. - -Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) - - * ns32k.h: Drop Q operand type as there is no correct use - for it. Add I and Z operand types which allow better checking. - -Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) - - * h8300.h (xor.l) :fix bit pattern. - (L_2): New size of operand. - (trapa): Use it. - -Fri Jun 10 16:38:11 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h: Move "trap" before "tpcc" to change disassembly. - -Fri Jun 3 15:57:36 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * sparc.h: Include v9 definitions. - -Thu Jun 2 12:23:17 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (m68060): Defined. - (m68040up, mfloat, mmmu): Include it. - (struct m68k_opcode): Widen `arch' field. - (m68k_opcodes): Updated for M68060. Removed comments that were - instructions commented out by "JF" years ago. - -Thu Apr 28 18:31:14 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * m68k.h (struct m68k_opcode): Shorten `arch' field to 8 bits, and - add a one-bit `flags' field. - (F_ALIAS): New macro. - -Wed Apr 27 11:29:52 1994 Steve Chamberlain (sac@cygnus.com) - - * h8300.h (dec, inc): Get encoding right. - -Mon Apr 4 13:12:43 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_operand): Removed signedp field; just use - a flag instead. - (PPC_OPERAND_SIGNED): Define. - (PPC_OPERAND_SIGNOPT): Define. - -Thu Mar 31 19:34:08 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (IS_JUMP_ON_ECX_ZERO, "jcxz" pattern): Operand size - prefix is 0x66, not 0x67. Patch from H.J. Lu (hlu@nynexst.com). - -Thu Mar 3 15:51:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h: Reverse last change. It'll be handled in gas instead. - -Thu Feb 24 15:29:05 1994 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (sar): Disabled the two-operand Imm1 form, since it was - slower on the 486 and used the implicit shift count despite the - explicit operand. The one-operand form is still available to get - the shorter form with the implicit shift count. - -Thu Feb 17 12:27:52 1994 Torbjorn Granlund (tege@mexican.cygnus.com) - - * hppa.h: Fix typo in fstws arg string. - -Wed Feb 9 21:23:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (struct powerpc_opcode): Make operands field unsigned. - -Mon Feb 7 19:14:58 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPCODE_601): Define. - -Fri Feb 4 23:43:50 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h (addb): Use '@' for addb and addib pseudo ops. - (so we can determine valid completers for both addb and addb[tf].) - - * hppa.h (xmpyu): No floating point format specifier for the - xmpyu instruction. - -Fri Feb 4 23:36:52 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h (PPC_OPERAND_NEXT): Define. - (PPC_OPERAND_NEGATIVE): Change value to make room for above. - (struct powerpc_macro): Define. - (powerpc_macros, powerpc_num_macros): Declare. - -Fri Jan 21 19:13:50 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * ppc.h: New file. Header file for PowerPC opcode table. - -Mon Jan 17 00:14:23 1994 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: More minor template fixes for sfu and copr (to allow - for easier disassembly). - - * hppa.h: Fix templates for all the sfu and copr instructions. - -Wed Dec 15 15:12:42 1993 Ken Raeburn (raeburn@cujo.cygnus.com) - - * i386.h (push): Permit Imm16 operand too. - -Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h (andc): Exists in base arch. - -Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> - * hppa.h: #undef NONE to avoid conflict with hiux include files. - -Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Add FP quadword store instructions. - -Wed Nov 17 17:13:16 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: (M_J_A): Added. - (M_LA): Removed. - -Mon Nov 8 12:12:47 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (OP_MASK_CACHE, OP_SH_CACHE): Define. From Ted Lemon - <mellon@pepper.ncd.com>. - -Sun Nov 7 00:30:11 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - - * hppa.h: Immediate field in probei instructions is unsigned, - not low-sign extended. - -Wed Nov 3 10:30:00 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * m88k.h (RRI10MASK): Change from 0xfc00ffe0 to 0xfc00fc00. - -Tue Nov 2 12:41:30 1993 Ken Raeburn (raeburn@rover.cygnus.com) - - * i386.h: Add "fxch" without operand. - -Mon Nov 1 18:13:03 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_JAL_1, M_JAL_2, M_JAL_A): Added. - -Sat Oct 2 22:26:11 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h: Add gfw and gfr to the opcode table. - -Wed Sep 29 16:23:00 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h: extended to handle m88110. - -Tue Sep 28 19:19:08 1993 Jeffrey A Law (law@snake.cs.utah.edu) - - * hppa.h (be, ble): Use operand type 'z' to denote absolute branch - addresses. - -Tue Sep 14 14:04:35 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i960.h (i960_opcodes): Properly bracket initializers. - -Mon Sep 13 12:50:52 1993 K. Richard Pixley (rich@sendai.cygnus.com) - - * m88k.h (BOFLAG): rewrite to avoid nested comment. - -Mon Sep 13 15:46:06 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m68k.h (two): Protect second argument with parentheses. - -Fri Sep 10 16:29:47 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (i386_optab): Added new instruction "rsm" (for i386sl). - Deleted old in/out instructions in "#if 0" section. - -Thu Sep 9 17:42:19 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * i386.h (i386_optab): Properly bracket initializers. - -Wed Aug 25 13:50:56 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * hppa.h (pa_opcode): Use '|' for movb and movib insns. (From - Jeff Law, law@cs.utah.edu). - -Mon Aug 23 16:55:03 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * i386.h (lcall): Accept Imm32 operand also. - -Mon Aug 23 12:43:11 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (M_ABSU): Removed (absolute value of unsigned number??). - (M_DABS): Added. - -Thu Aug 19 15:08:37 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h (INSN_*): Changed values. Removed unused definitions. - Added INSN_COND_BRANCH_LIKELY, INSN_ISA2 and INSN_ISA3. Split - INSN_LOAD_DELAY into INSN_LOAD_MEMORY_DELAY and - INSN_LOAD_COPROC_DELAY. Split INSN_COPROC_DELAY into - INSN_COPROC_MOVE_DELAY and INSN_COPROC_MEMORY_DELAY. - (M_*): Added new values for r6000 and r4000 macros. - (ANY_DELAY): Removed. - -Wed Aug 18 15:37:48 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Added M_LI_S and M_LI_SS. - -Tue Aug 17 07:08:08 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: Get some rare mov.bs correct. - -Thu Aug 5 09:15:17 1993 Jim Kingdon (kingdon@lioth.cygnus.com) - - * sparc.h: Don't define const ourself; rely on ansidecl.h having - been included. - -Fri Jul 30 18:41:11 1993 John Gilmore (gnu@cygnus.com) - - * sparc.h (F_JSR, F_UNBR, F_CONDBR): Add new flags to mark - jump instructions, for use in disassemblers. - -Thu Jul 22 07:25:27 1993 Ian Lance Taylor (ian@cygnus.com) - - * m88k.h: Make bitfields just unsigned, not unsigned long or - unsigned short. - -Wed Jul 21 11:55:31 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h: New argument type 'y'. Use in various float instructions. - -Mon Jul 19 17:17:03 1993 Jim Kingdon (kingdon@deneb.cygnus.com) - - * hppa.h (break): First immediate field is unsigned. - - * hppa.h: Add rfir instruction. - -Sun Jul 18 16:28:08 1993 Jim Kingdon (kingdon@rtl.cygnus.com) - - * mips.h: Split the actual table out into ../../opcodes/mips-opc.c. - -Fri Jul 16 09:59:29 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Reworked the hazard information somewhat, and fixed some - bugs in the instruction hazard descriptions. - -Thu Jul 15 12:42:01 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * m88k.h: Corrected a couple of opcodes. - -Tue Jul 6 15:17:35 1993 Ian Lance Taylor (ian@cygnus.com) - - * mips.h: Replaced with version from Ralph Campbell and OSF. The - new version includes instruction hazard information, but is - otherwise reasonably similar. - -Thu Jul 1 20:36:17 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Fix typo in UNOP3 (affected sh[al][lr].l). - -Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) - - Patches from Jeff Law, law@cs.utah.edu: - * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. - Make the tables be the same for the following instructions: - "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", - "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", - "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", - "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", - "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", - "fcmp", and "ftest". - - * hppa.h: Make new and old tables the same for "break", "mtctl", - "mfctl", "bb", "ssm", "rsm", "xmpyu", "fmpyadd", "fmpysub". - Fix typo in last patch. Collapse several #ifdefs into a - single #ifdef. - - * hppa.h: Delete remaining OLD_TABLE code. Bring some - of the comments up-to-date. - - * hppa.h: Update "free list" of letters and update - comments describing each letter's function. - -Thu Jul 8 09:05:26 1993 Doug Evans (dje@canuck.cygnus.com) - - * h8300.h: Lots of little fixes for the h8/300h. - -Tue Jun 8 12:16:03 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - Support for H8/300-H - * h8300.h: Lots of new opcodes. - -Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) - - * h8300.h: checkpoint, includes H8/300-H opcodes. - -Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) - - * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa.h: Rework single precision FP - instructions so that they correctly disassemble code - PA1.1 code. - -Thu May 27 19:21:22 1993 Bruce Bauman (boot@osf.org) - - * i386.h (i386_optab, mov pattern): Remove Mem16 restriction from - mov to allow instructions like mov ss,xyz(ecx) to assemble. - -Tue May 25 00:39:40 1993 Ken Raeburn (raeburn@cygnus.com) - - * hppa.h: Use new version from Utah if OLD_TABLE isn't defined; - gdb will define it for now. - -Mon May 24 15:20:06 1993 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * sparc.h: Don't end enumerator list with comma. - -Fri May 14 15:15:50 1993 Ian Lance Taylor (ian@cygnus.com) - - * Based on patches from davidj@ICSI.Berkeley.EDU (David Johnson): - * mips.h (OP_MASK_COPZ, OP_SH_COPZ): Define. - ("bc2t"): Correct typo. - ("[ls]wc[023]"): Use T rather than t. - ("c[0123]"): Define general coprocessor instructions. - -Mon May 10 06:02:25 1993 Ken Raeburn (raeburn@kr-pc.cygnus.com) - - * m68k.h: Move split point for gcc compilation more towards - middle. - -Fri Apr 9 13:26:16 1993 Jim Kingdon (kingdon@cygnus.com) - - * rs6k.h: Clean up instructions for primary opcode 19 (many were - simply wrong, ics, rfi, & rfsvc were missing). - Add "a" to opr_ext for "bb". Doc fix. - -Thu Mar 18 13:45:31 1993 Per Bothner (bothner@rtl.cygnus.com) - - * i386.h: 486 extensions from John Hassey (hassey@dg-rtp.dg.com). - * mips.h: Add casts, to suppress warnings about shifting too much. - * m68k.h: Document the placement code '9'. - -Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) - - * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which - allows callers to break up the large initialized struct full of - opcodes into two half-sized ones. This permits GCC to compile - this module, since it takes exponential space for initializers. - (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. - -Thu Feb 4 02:06:56 1993 John Gilmore (gnu@cygnus.com) - - * a29k.h: Remove RCS crud, update GPL to v2, update copyrights. - * convex.h: Added, from GDB's convx-opcode.h. Added CONST to all - initialized structs in it. - -Thu Jan 28 21:32:22 1993 John Gilmore (gnu@cygnus.com) - - Delta 88 changes inspired by Carl Greco, <cgreco@Creighton.Edu>: - * m88k.h (PMEM): Avoid previous definition from <sys/param.h>. - (AND): Change to AND_ to avoid ansidecl.h `AND' conflict. - -Sat Jan 23 18:10:49 PST 1993 Ralph Campbell (ralphc@pyramid.com) - - * mips.h: document "i" and "j" operands correctly. - -Thu Jan 7 15:58:13 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - - * mips.h: Removed endianness dependency. - -Sun Jan 3 14:13:35 1993 Steve Chamberlain (sac@thepub.cygnus.com) - - * h8300.h: include info on number of cycles per instruction. - -Mon Dec 21 21:29:08 1992 Stu Grossman (grossman at cygnus.com) - - * hppa.h: Move handy aliases to the front. Fix masks for extract - and deposit instructions. - -Sat Dec 12 16:09:48 1992 Ian Lance Taylor (ian@cygnus.com) - - * i386.h: accept shld and shrd both with and without the shift - count argument, which is always %cl. - -Fri Nov 27 17:13:18 1992 Ken Raeburn (raeburn at cygnus.com) - - * i386.h (i386_optab_end, i386_regtab_end): Now const. - (one_byte_segment_defaults, two_byte_segment_defaults, - i386_prefixtab_end): Ditto. - -Mon Nov 23 10:47:25 1992 Ken Raeburn (raeburn@cygnus.com) - - * vax.h (bb*): Use "v" (bitfield type), not "a" (address operand) - for operand 2; from John Carr, jfc@dsg.dec.com. - -Wed Nov 4 07:36:49 1992 Ken Raeburn (raeburn@cygnus.com) - - * m68k.h: Define FIXED_SIZE_BRANCH, so bsr and bra instructions - always use 16-bit offsets. Makes calculated-size jump tables - feasible. - -Fri Oct 16 22:52:43 1992 Ken Raeburn (raeburn@cygnus.com) - - * i386.h: Fix one-operand forms of in* and out* patterns. - -Tue Sep 22 14:08:14 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h: Added CPU32 support. - -Tue Sep 22 00:38:41 1992 John Gilmore (gnu@cygnus.com) - - * mips.h (break): Disassemble the argument. Patch from - jonathan@cs.stanford.edu (Jonathan Stone). - -Wed Sep 9 11:25:28 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: merged Motorola and MIT syntax. - -Thu Sep 3 09:33:22 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h (pmove): make the tests less strict, the 68k book is - wrong. - -Tue Aug 25 23:25:19 1992 Ken Raeburn (raeburn@cambridge.cygnus.com) - - * m68k.h (m68ec030): Defined as alias for 68030. - (m68k_opcodes): New type characters "3" for 68030 MMU regs and "t" - for immediate 0-7 added. Set up some opcodes (ptest, bkpt) to use - them. Tightened description of "fmovex" to distinguish it from - some "pmove" encodings. Added "pmove" for 68030 MMU regs, cleaned - up descriptions that claimed versions were available for chips not - supporting them. Added "pmovefd". - -Mon Aug 24 12:04:51 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68k.h: fix where the . goes in divull - -Wed Aug 19 11:22:24 1992 Ian Lance Taylor (ian@cygnus.com) - - * m68k.h: the cas2 instruction is supposed to be written with - indirection on the last two operands, which can be either data or - address registers. Added a new operand type 'r' which accepts - either register type. Added new cases for cas2l and cas2w which - use them. Corrected masks for cas2 which failed to recognize use - of address register. - -Fri Aug 14 14:20:38 1992 Per Bothner (bothner@cygnus.com) - - * m68k.h: Merged in patches (mostly m68040-specific) from - Colin Smith <colin@wrs.com>. - - * m68k.h: Merged m68kmri.h and m68k.h (using the former as a - base). Also cleaned up duplicates, re-ordered instructions for - the sake of dis-assembling (so aliases come after standard names). - * m68kmri.h: Now just defines some macros, and #includes m68k.h. - -Wed Aug 12 16:38:15 1992 Steve Chamberlain (sac@thepub.cygnus.com) - - * m68kmri.h: added various opcodes. Moved jbxx to bxxes. Filled in - all missing .s - -Mon Aug 10 23:22:33 1992 Ken Raeburn (raeburn@cygnus.com) - - * sparc.h: Moved tables to BFD library. - - * i386.h (i386_optab): Add fildq, fistpq aliases used by gcc. - -Sun Jun 28 13:29:03 1992 Fred Fish (fnf@cygnus.com) - - * h8300.h: Finish filling in all the holes in the opcode table, - so that the Lucid C compiler can digest this as well... - -Fri Jun 26 21:27:17 1992 John Gilmore (gnu at cygnus.com) - - * i386.h: Add setc, setnc, addr16, data16, repz, repnz aliases. - Fix opcodes on various sizes of fild/fist instructions - (16bit=no suffix, 32bit="l" suffix, 64bit="ll" suffix). - Use tabs to indent for comments. Fixes suggested by Minh Tran-Le. - -Thu Jun 25 16:13:26 1992 Stu Grossman (grossman at cygnus.com) - - * h8300.h: Fill in all the holes in the opcode table so that the - losing HPUX C compiler can digest this... - -Thu Jun 11 12:15:25 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Fix decoding of coprocessor instructions, somewhat. - (Fix by Eric Anderson, 3jean@maas-neotek.arc.nasa.gov.) - -Thu May 28 11:17:44 1992 Jim Wilson (wilson@sphagnum.cygnus.com) - - * sparc.h: Add new architecture variant sparclite; add its scan - and divscc opcodes. Define ARCHITECTURES_CONFLICT_P macro. - -Tue May 5 14:23:27 1992 Per Bothner (bothner@rtl.cygnus.com) - - * mips.h: Add some more opcode synonyms (from Frank Yellin, - fy@lucid.com). - -Thu Apr 16 18:25:26 1992 Per Bothner (bothner@cygnus.com) - - * rs6k.h: New version from IBM (Metin). - -Thu Apr 9 00:31:19 1992 Per Bothner (bothner@rtl.cygnus.com) - - * rs6k.h: Fix incorrect extended opcode for instructions `fm' - and `fd'. (From metin@ibmpa.awdpa.ibm.com (Metin G. Ozisik).) - -Tue Apr 7 13:38:47 1992 Stu Grossman (grossman at cygnus.com) - - * rs6k.h: Move from ../../gdb/rs6k-opcode.h. - -Fri Apr 3 11:30:20 1992 Fred Fish (fnf@cygnus.com) - - * m68k.h (one, two): Cast macro args to unsigned to suppress - complaints from compiler and lint about integer overflow during - shift. - -Sun Mar 29 12:22:08 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h (OP): Avoid signed overflow when shifting to high order bit. - -Fri Mar 6 00:22:38 1992 John Gilmore (gnu at cygnus.com) - - * mips.h: Make bitfield layout depend on the HOST compiler, - not on the TARGET system. - -Fri Feb 21 01:29:51 1992 K. Richard Pixley (rich@cygnus.com) - - * i386.h: added inb, inw, outb, outw opcodes, added att syntax for - scmp, slod, smov, ssca, ssto. Curtesy Minh Tran-Le - <TRANLE@INTELLICORP.COM>. - -Thu Jan 30 07:31:44 1992 Steve Chamberlain (sac at rtl.cygnus.com) - - * h8300.h: turned op_type enum into #define list - -Thu Jan 30 01:07:24 1992 John Gilmore (gnu at cygnus.com) - - * sparc.h: Remove "cypress" architecture. Remove "fitox" and - similar instructions -- they've been renamed to "fitoq", etc. - REALLY fix tsubcctv. Fix "fcmpeq" and "fcmpq" which had wrong - number of arguments. - * h8300.h: Remove extra ; which produces compiler warning. - -Tue Jan 28 22:59:22 1992 Stu Grossman (grossman at cygnus.com) - - * sparc.h: fix opcode for tsubcctv. - -Tue Jan 7 17:19:39 1992 K. Richard Pixley (rich at cygnus.com) - - * sparc.h: fba and cba are now aliases for fb and cb respectively. - -Fri Dec 27 10:55:50 1991 Per Bothner (bothner at cygnus.com) - - * sparc.h (nop): Made the 'lose' field be even tighter, - so only a standard 'nop' is disassembled as a nop. - -Sun Dec 22 12:18:18 1991 Michael Tiemann (tiemann at cygnus.com) - - * sparc.h (nop): Add RD_GO to `lose' so that only %g0 in dest is - disassembled as a nop. - -Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) - - * m68k.h, sparc.h: ANSIfy enums. - -Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) - - * sparc.h: fix a typo. - -Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) - - * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, - m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, - vax.h: Renamed from ../<foo>-opcode.h. - - -Local Variables: -version-control: never -End: diff --git a/contrib/binutils/include/opcode/alpha.h b/contrib/binutils/include/opcode/alpha.h deleted file mode 100644 index 22c85a1f5efcb..0000000000000 --- a/contrib/binutils/include/opcode/alpha.h +++ /dev/null @@ -1,237 +0,0 @@ -/* alpha.h -- Header file for Alpha opcode table - Copyright 1996, 1999, 2001, 2003 Free Software Foundation, Inc. - Contributed by Richard Henderson <rth@tamu.edu>, - patterned after the PPC opcode table written by Ian Lance Taylor. - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef OPCODE_ALPHA_H -#define OPCODE_ALPHA_H - -/* The opcode table is an array of struct alpha_opcode. */ - -struct alpha_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned mask; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[4]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct alpha_opcode alpha_opcodes[]; -extern const unsigned alpha_num_opcodes; - -/* Values defined for the flags field of a struct alpha_opcode. */ - -/* CPU Availability */ -#define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ -#define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ -#define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ -#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ -#define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ -#define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ -#define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ - -#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) - -/* A macro to extract the major opcode from an instruction. */ -#define AXP_OP(i) (((i) >> 26) & 0x3F) - -/* The total number of major opcodes. */ -#define AXP_NOPS 0x40 - - -/* The operands table is an array of struct alpha_operand. */ - -struct alpha_operand -{ - /* The number of bits in the operand. */ - unsigned int bits : 5; - - /* How far the operand is left shifted in the instruction. */ - unsigned int shift : 5; - - /* The default relocation type for this operand. */ - signed int default_reloc : 16; - - /* One bit syntax flags. */ - unsigned int flags : 16; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned (*insert) (unsigned instruction, int op, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & AXP_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - int (*extract) (unsigned instruction, int *invalid); -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the alpha_opcodes table. */ - -extern const struct alpha_operand alpha_operands[]; -extern const unsigned alpha_num_operands; - -/* Values defined for the flags field of a struct alpha_operand. */ - -/* Mask for selecting the type for typecheck purposes */ -#define AXP_OPERAND_TYPECHECK_MASK \ - (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR | \ - AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED | \ - AXP_OPERAND_UNSIGNED) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics, for which two operands fields - are identical. The assembler should call the insert function with - any op value. The disassembler should call the extract function, - ignore the return value, and check the value placed in the invalid - argument. */ -#define AXP_OPERAND_FAKE 01 - -/* The operand should be wrapped in parentheses rather than separated - from the previous by a comma. This is used for the load and store - instructions which want their operands to look like "Ra,disp(Rb)". */ -#define AXP_OPERAND_PARENS 02 - -/* Used in combination with PARENS, this supresses the supression of - the comma. This is used for "jmp Ra,(Rb),hint". */ -#define AXP_OPERAND_COMMA 04 - -/* This operand names an integer register. */ -#define AXP_OPERAND_IR 010 - -/* This operand names a floating point register. */ -#define AXP_OPERAND_FPR 020 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define AXP_OPERAND_RELATIVE 040 - -/* This operand takes signed values. */ -#define AXP_OPERAND_SIGNED 0100 - -/* This operand takes unsigned values. This exists primarily so that - a flags value of 0 can be treated as end-of-arguments. */ -#define AXP_OPERAND_UNSIGNED 0200 - -/* Supress overflow detection on this field. This is used for hints. */ -#define AXP_OPERAND_NOOVERFLOW 0400 - -/* Mask for optional argument default value. */ -#define AXP_OPERAND_OPTIONAL_MASK 07000 - -/* This operand defaults to zero. This is used for jump hints. */ -#define AXP_OPERAND_DEFAULT_ZERO 01000 - -/* This operand should default to the first (real) operand and is used - in conjunction with AXP_OPERAND_OPTIONAL. This allows - "and $0,3,$0" to be written as "and $0,3", etc. I don't like - it, but it's what DEC does. */ -#define AXP_OPERAND_DEFAULT_FIRST 02000 - -/* Similarly, this operand should default to the second (real) operand. - This allows "negl $0" instead of "negl $0,$0". */ -#define AXP_OPERAND_DEFAULT_SECOND 04000 - - -/* Register common names */ - -#define AXP_REG_V0 0 -#define AXP_REG_T0 1 -#define AXP_REG_T1 2 -#define AXP_REG_T2 3 -#define AXP_REG_T3 4 -#define AXP_REG_T4 5 -#define AXP_REG_T5 6 -#define AXP_REG_T6 7 -#define AXP_REG_T7 8 -#define AXP_REG_S0 9 -#define AXP_REG_S1 10 -#define AXP_REG_S2 11 -#define AXP_REG_S3 12 -#define AXP_REG_S4 13 -#define AXP_REG_S5 14 -#define AXP_REG_FP 15 -#define AXP_REG_A0 16 -#define AXP_REG_A1 17 -#define AXP_REG_A2 18 -#define AXP_REG_A3 19 -#define AXP_REG_A4 20 -#define AXP_REG_A5 21 -#define AXP_REG_T8 22 -#define AXP_REG_T9 23 -#define AXP_REG_T10 24 -#define AXP_REG_T11 25 -#define AXP_REG_RA 26 -#define AXP_REG_PV 27 -#define AXP_REG_T12 27 -#define AXP_REG_AT 28 -#define AXP_REG_GP 29 -#define AXP_REG_SP 30 -#define AXP_REG_ZERO 31 - -#endif /* OPCODE_ALPHA_H */ diff --git a/contrib/binutils/include/opcode/arc.h b/contrib/binutils/include/opcode/arc.h deleted file mode 100644 index 8ddcf5433a4d4..0000000000000 --- a/contrib/binutils/include/opcode/arc.h +++ /dev/null @@ -1,323 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001, 2002, 2003 - Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, - MA 02110-1301, USA. */ - - -/* List of the various cpu types. - The tables currently use bit masks to say whether the instruction or - whatever is supported by a particular cpu. This lets us have one entry - apply to several cpus. - - The `base' cpu must be 0. The cpu type is treated independently of - endianness. The complete `mach' number includes endianness. - These values are internal to opcodes/bfd/binutils/gas. */ -#define ARC_MACH_5 0 -#define ARC_MACH_6 1 -#define ARC_MACH_7 2 -#define ARC_MACH_8 4 - -/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ -#define ARC_MACH_BIG 16 - -/* Mask of number of bits necessary to record cpu type. */ -#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) - -/* Mask of number of bits necessary to record cpu type + endianness. */ -#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) - -/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ - -typedef unsigned int arc_insn; - -struct arc_opcode { - char *syntax; /* syntax of insn */ - unsigned long mask, value; /* recognize insn if (op&mask) == value */ - int flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) - -/* Return MACH number, given flag bits. */ -#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* First opcode flag bit available after machine mask. */ -#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) - -/* This insn is a conditional branch. */ -#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) -#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) -#define SYNTAX_LENGTH (SYNTAX_3OP ) -#define SYNTAX_2OP (SYNTAX_3OP << 1) -#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) -#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) -#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* These values are used to optimize assembly and disassembly. Each insn - is on a list of related insns (same first letter for assembly, same - insn code for disassembly). */ - - struct arc_opcode *next_asm; /* Next instr to try during assembly. */ - struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ - -/* Macros to create the hash values for the lists. */ -#define ARC_HASH_OPCODE(string) \ - ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) -#define ARC_HASH_ICODE(insn) \ - ((unsigned int) (insn) >> 27) - - /* Macros to access `next_asm', `next_dis' so users needn't care about the - underlying mechanism. */ -#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) -#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) -}; - -/* this is an "insert at front" linked list per Metaware spec - that new definitions override older ones. */ -extern struct arc_opcode *arc_ext_opcodes; - -struct arc_operand_value { - char *name; /* eg: "eq" */ - short value; /* eg: 1 */ - unsigned char type; /* index into `arc_operands' */ - unsigned char flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* Return MACH number, given flag bits. */ -#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) -}; - -struct arc_ext_operand_value { - struct arc_ext_operand_value *next; - struct arc_operand_value operand; -}; - -extern struct arc_ext_operand_value *arc_ext_operands; - -struct arc_operand { -/* One of the insn format chars. */ - unsigned char fmt; - -/* The number of bits in the operand (may be unused for a modifier). */ - unsigned char bits; - -/* How far the operand is left shifted in the instruction, or - the modifier's flag bit (may be unused for a modifier. */ - unsigned char shift; - -/* Various flag bits. */ - int flags; - -/* Values for `flags'. */ - -/* This operand is a suffix to the opcode. */ -#define ARC_OPERAND_SUFFIX 1 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_RELATIVE_BRANCH 2 - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ABSOLUTE_BRANCH 4 - -/* This operand is an address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ADDRESS 8 - -/* This operand is a long immediate value. */ -#define ARC_OPERAND_LIMM 0x10 - -/* This operand takes signed values. */ -#define ARC_OPERAND_SIGNED 0x20 - -/* This operand takes signed values, but also accepts a full positive - range of values. That is, if bits is 16, it takes any value from - -0x8000 to 0xffff. */ -#define ARC_OPERAND_SIGNOPT 0x40 - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define ARC_OPERAND_NEGATIVE 0x80 - -/* This operand doesn't really exist. The program uses these operands - in special ways. */ -#define ARC_OPERAND_FAKE 0x100 - -/* separate flags operand for j and jl instructions */ -#define ARC_OPERAND_JUMPFLAGS 0x200 - -/* allow warnings and errors to be issued after call to insert_xxxxxx */ -#define ARC_OPERAND_WARN 0x400 -#define ARC_OPERAND_ERROR 0x800 - -/* this is a load operand */ -#define ARC_OPERAND_LOAD 0x8000 - -/* this is a store operand */ -#define ARC_OPERAND_STORE 0x10000 - -/* Modifier values. */ -/* A dot is required before a suffix. Eg: .le */ -#define ARC_MOD_DOT 0x1000 - -/* A normal register is allowed (not used, but here for completeness). */ -#define ARC_MOD_REG 0x2000 - -/* An auxiliary register name is expected. */ -#define ARC_MOD_AUXREG 0x4000 - -/* Sum of all ARC_MOD_XXX bits. */ -#define ARC_MOD_BITS 0x7000 - -/* Non-zero if the operand type is really a modifier. */ -#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) - -/* enforce read/write only register restrictions */ -#define ARC_REGISTER_READONLY 0x01 -#define ARC_REGISTER_WRITEONLY 0x02 -#define ARC_REGISTER_NOSHORT_CUT 0x04 - -/* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (p & ((1 << o->bits) - 1)) << o->shift; - (I is the instruction which we are filling in, O is a pointer to - this structure, and OP is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged. - - REG is non-NULL when inserting a register value. */ - - arc_insn (*insert) - (arc_insn insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, const char **errmsg); - -/* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & ARC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (I is the instruction, O is a pointer to this structure, and OP - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. - - INSN is a pointer to an array of two `arc_insn's. The first element is - the insn, the second is the limm if present. - - Operands that have a printable form like registers and suffixes have - their struct arc_operand_value pointer stored in OPVAL. */ - - long (*extract) - (arc_insn *insn, const struct arc_operand *operand, int mods, - const struct arc_operand_value **opval, int *invalid); -}; - -/* Bits that say what version of cpu we have. These should be passed to - arc_init_opcode_tables. At present, all there is is the cpu type. */ - -/* CPU number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* MACH number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* Special register values: */ -#define ARC_REG_SHIMM_UPDATE 61 -#define ARC_REG_SHIMM 63 -#define ARC_REG_LIMM 62 - -/* Non-zero if REG is a constant marker. */ -#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) - -/* Positions and masks of various fields: */ -#define ARC_SHIFT_REGA 21 -#define ARC_SHIFT_REGB 15 -#define ARC_SHIFT_REGC 9 -#define ARC_MASK_REG 63 - -/* Delay slot types. */ -#define ARC_DELAY_NONE 0 /* no delay slot */ -#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ -#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ - -/* Non-zero if X will fit in a signed 9 bit field. */ -#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) - -extern const struct arc_operand arc_operands[]; -extern const int arc_operand_count; -extern struct arc_opcode arc_opcodes[]; -extern const int arc_opcodes_count; -extern const struct arc_operand_value arc_suffixes[]; -extern const int arc_suffixes_count; -extern const struct arc_operand_value arc_reg_names[]; -extern const int arc_reg_names_count; -extern unsigned char arc_operand_map[]; - -/* Utility fns in arc-opc.c. */ -int arc_get_opcode_mach (int, int); - -/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ -void arc_opcode_init_tables (int); -void arc_opcode_init_insert (void); -void arc_opcode_init_extract (void); -const struct arc_opcode *arc_opcode_lookup_asm (const char *); -const struct arc_opcode *arc_opcode_lookup_dis (unsigned int); -int arc_opcode_limm_p (long *); -const struct arc_operand_value *arc_opcode_lookup_suffix - (const struct arc_operand *type, int value); -int arc_opcode_supported (const struct arc_opcode *); -int arc_opval_supported (const struct arc_operand_value *); -int arc_limm_fixup_adjust (arc_insn); -int arc_insn_is_j (arc_insn); -int arc_insn_not_jl (arc_insn); -int arc_operand_type (int); -struct arc_operand_value *get_ext_suffix (char *); -int arc_get_noshortcut_flag (void); diff --git a/contrib/binutils/include/opcode/arm.h b/contrib/binutils/include/opcode/arm.h deleted file mode 100644 index 24a89cfcb1d13..0000000000000 --- a/contrib/binutils/include/opcode/arm.h +++ /dev/null @@ -1,197 +0,0 @@ -/* ARM assembler/disassembler support. - Copyright 2004 Free Software Foundation, Inc. - - This file is part of GDB and GAS. - - GDB and GAS are free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 1, or (at - your option) any later version. - - GDB and GAS are distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GDB or GAS; see the file COPYING. If not, write to the - Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -/* The following bitmasks control CPU extensions: */ -#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ -#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ -#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ -#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ -#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ -#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ -#define ARM_EXT_V4T 0x00000040 /* Thumb. */ -#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ -#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */ -#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ -#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ -#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ -#define ARM_EXT_V6 0x00001000 /* ARM V6. */ -#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ -#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ -#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */ -#define ARM_EXT_DIV 0x00010000 /* Integer division. */ -/* The 'M' in Arm V7M stands for Microcontroller. - On earlier architecture variants it stands for Multiply. */ -#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */ -#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */ -#define ARM_EXT_V7 0x00080000 /* Arm V7. */ -#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */ -#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */ -#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */ - -/* Co-processor space extensions. */ -#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ -#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ -#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ -#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ - -#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ -#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ -#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ -#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ -#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ -#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ -#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ -#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ -#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */ -#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */ - -/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) - defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, - ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add - three more to cover cores prior to ARM6. Finally, there are cores which - implement further extensions in the co-processor space. */ -#define ARM_AEXT_V1 ARM_EXT_V1 -#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2) -#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S) -#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3) -#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M) -#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4) -#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4) -#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T) -#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T) -#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5) -#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5) -#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T) -#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP) -#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E) -#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J) -#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6) -#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K) -#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z) -#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) -#define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM) -#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K) -#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z) -#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z) -#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7) -#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A) -#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV) -#define ARM_AEXT_NOTM \ - (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM) -#define ARM_AEXT_V7M \ - ((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM)) -#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M) - -/* Processors with specific extensions in the co-processor space. */ -#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) -#define ARM_ARCH_IWMMXT \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) -#define ARM_ARCH_IWMMXT2 \ - ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) - -#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) -#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) -#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) -#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3) -#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ - | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1) -#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) - -/* Deprecated */ -#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE) - -#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1) -#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA) - -#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) -#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) -#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) -#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) -#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) -#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ - ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) -#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) - -#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) - -#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK) - -#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0) -#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0) -#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0) -#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0) -#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0) -#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0) -#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0) -#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0) -#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0) -#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0) -#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0) -#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0) -#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0) -#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0) -#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0) -#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0) -#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0) -#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0) -#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0) -#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0) -#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0) -#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0) -#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0) -#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0) -#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0) -#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0) -#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0) -#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0) - -/* Some useful combinations: */ -#define ARM_ARCH_NONE ARM_FEATURE (0, 0) -#define FPU_NONE ARM_FEATURE (0, 0) -#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */ -#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) -#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0) - -/* There are too many feature bits to fit in a single word, so use a - structure. For simplicity we put all core features in one word and - everything else in the other. */ -typedef struct -{ - unsigned long core; - unsigned long coproc; -} arm_feature_set; - -#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \ - (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0) - -#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \ - do { \ - (TARG).core = (F1).core | (F2).core; \ - (TARG).coproc = (F1).coproc | (F2).coproc; \ - } while (0) - -#define ARM_CLEAR_FEATURE(TARG,F1,F2) \ - do { \ - (TARG).core = (F1).core &~ (F2).core; \ - (TARG).coproc = (F1).coproc &~ (F2).coproc; \ - } while (0) - -#define ARM_FEATURE(core, coproc) {(core), (coproc)} diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h deleted file mode 100644 index e8fd5d3d9f731..0000000000000 --- a/contrib/binutils/include/opcode/cgen.h +++ /dev/null @@ -1,1473 +0,0 @@ -/* Header file for targets using CGEN: Cpu tools GENerator. - -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 -Free Software Foundation, Inc. - -This file is part of GDB, the GNU debugger, and the GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef CGEN_H -#define CGEN_H - -#include "symcat.h" -#include "cgen-bitset.h" -/* ??? This file requires bfd.h but only to get bfd_vma. - Seems like an awful lot to require just to get such a fundamental type. - Perhaps the definition of bfd_vma can be moved outside of bfd.h. - Or perhaps one could duplicate its definition in another file. - Until such time, this file conditionally compiles definitions that require - bfd_vma using __BFD_H_SEEN__. */ - -/* Enums must be defined before they can be used. - Allow them to be used in struct definitions, even though the enum must - be defined elsewhere. - If CGEN_ARCH isn't defined, this file is being included by something other - than <arch>-desc.h. */ - -/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. - The lack of spaces in the arg list is important for non-stdc systems. - This file is included by <arch>-desc.h. - It can be included independently of <arch>-desc.h, in which case the arch - dependent portions will be declared as "unknown_cgen_foo". */ - -#ifndef CGEN_SYM -#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s) -#endif - -/* This file contains the static (unchanging) pieces and as much other stuff - as we can reasonably put here. It's generally cleaner to put stuff here - rather than having it machine generated if possible. */ - -/* The assembler syntax is made up of expressions (duh...). - At the lowest level the values are mnemonics, register names, numbers, etc. - Above that are subexpressions, if any (an example might be the - "effective address" in m68k cpus). Subexpressions are wip. - At the second highest level are the insns themselves. Above that are - pseudo-insns, synthetic insns, and macros, if any. */ - -/* Lots of cpu's have a fixed insn size, or one which rarely changes, - and it's generally easier to handle these by treating the insn as an - integer type, rather than an array of characters. So we allow targets - to control this. When an integer type the value is in host byte order, - when an array of characters the value is in target byte order. */ - -typedef unsigned int CGEN_INSN_INT; -#if CGEN_INT_INSN_P -typedef CGEN_INSN_INT CGEN_INSN_BYTES; -typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; -#else -typedef unsigned char *CGEN_INSN_BYTES; -typedef unsigned char *CGEN_INSN_BYTES_PTR; -#endif - -#ifdef __GNUC__ -#define CGEN_INLINE __inline__ -#else -#define CGEN_INLINE -#endif - -enum cgen_endian -{ - CGEN_ENDIAN_UNKNOWN, - CGEN_ENDIAN_LITTLE, - CGEN_ENDIAN_BIG -}; - -/* Forward decl. */ - -typedef struct cgen_insn CGEN_INSN; - -/* Opaque pointer version for use by external world. */ - -typedef struct cgen_cpu_desc *CGEN_CPU_DESC; - -/* Attributes. - Attributes are used to describe various random things associated with - an object (ifield, hardware, operand, insn, whatever) and are specified - as name/value pairs. - Integer attributes computed at compile time are currently all that's - supported, though adding string attributes and run-time computation is - straightforward. Integer attribute values are always host int's - (signed or unsigned). For portability, this means 32 bits. - Integer attributes are further categorized as boolean, bitset, integer, - and enum types. Boolean attributes appear frequently enough that they're - recorded in one host int. This limits the maximum number of boolean - attributes to 32, though that's a *lot* of attributes. */ - -/* Type of attribute values. */ - -typedef CGEN_BITSET CGEN_ATTR_VALUE_BITSET_TYPE; -typedef int CGEN_ATTR_VALUE_ENUM_TYPE; -typedef union -{ - CGEN_ATTR_VALUE_BITSET_TYPE bitset; - CGEN_ATTR_VALUE_ENUM_TYPE nonbitset; -} CGEN_ATTR_VALUE_TYPE; - -/* Struct to record attribute information. */ - -typedef struct -{ - /* Boolean attributes. */ - unsigned int bool; - /* Non-boolean integer attributes. */ - CGEN_ATTR_VALUE_TYPE nonbool[1]; -} CGEN_ATTR; - -/* Define a structure member for attributes with N non-boolean entries. - There is no maximum number of non-boolean attributes. - There is a maximum of 32 boolean attributes (since they are all recorded - in one host int). */ - -#define CGEN_ATTR_TYPE(n) \ -struct { unsigned int bool; \ - CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } - -/* Return the boolean attributes. */ - -#define CGEN_ATTR_BOOLS(a) ((a)->bool) - -/* Non-boolean attribute numbers are offset by this much. */ - -#define CGEN_ATTR_NBOOL_OFFSET 32 - -/* Given a boolean attribute number, return its mask. */ - -#define CGEN_ATTR_MASK(attr) (1 << (attr)) - -/* Return the value of boolean attribute ATTR in ATTRS. */ - -#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) - -/* Return value of attribute ATTR in ATTR_TABLE for OBJ. - OBJ is a pointer to the entity that has the attributes - (??? not used at present but is reserved for future purposes - eventually - the goal is to allow recording attributes in source form and computing - them lazily at runtime, not sure of the details yet). */ - -#define CGEN_ATTR_VALUE(obj, attr_table, attr) \ -((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ - ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ - : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].nonbitset)) -#define CGEN_BITSET_ATTR_VALUE(obj, attr_table, attr) \ - ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET].bitset) - -/* Attribute name/value tables. - These are used to assist parsing of descriptions at run-time. */ - -typedef struct -{ - const char * name; - unsigned value; -} CGEN_ATTR_ENTRY; - -/* For each domain (ifld,hw,operand,insn), list of attributes. */ - -typedef struct -{ - const char * name; - const CGEN_ATTR_ENTRY * dfault; - const CGEN_ATTR_ENTRY * vals; -} CGEN_ATTR_TABLE; - -/* Instruction set variants. */ - -typedef struct { - const char *name; - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; -} CGEN_ISA; - -/* Machine variants. */ - -typedef struct { - const char *name; - /* The argument to bfd_arch_info->scan. */ - const char *bfd_name; - /* one of enum mach_attr */ - int num; - /* parameter from mach->cpu */ - unsigned int insn_chunk_bitsize; -} CGEN_MACH; - -/* Parse result (also extraction result). - - The result of parsing an insn is stored here. - To generate the actual insn, this is passed to the insert handler. - When printing an insn, the result of extraction is stored here. - To print the insn, this is passed to the print handler. - - It is machine generated so we don't define it here, - but we do need a forward decl for the handler fns. - - There is one member for each possible field in the insn. - The type depends on the field. - Also recorded here is the computed length of the insn for architectures - where it varies. -*/ - -typedef struct cgen_fields CGEN_FIELDS; - -/* Total length of the insn, as recorded in the `fields' struct. */ -/* ??? The field insert handler has lots of opportunities for optimization - if it ever gets inlined. On architectures where insns all have the same - size, may wish to detect that and make this macro a constant - to allow - further optimizations. */ - -#define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) - -/* Extraction support for variable length insn sets. */ - -/* When disassembling we don't know the number of bytes to read at the start. - So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest - are read when needed. This struct controls this. It is basically the - disassemble_info stuff, except that we provide a cache for values already - read (since bytes can typically be read several times to fetch multiple - operands that may be in them), and that extraction of fields is needed - in contexts other than disassembly. */ - -typedef struct { - /* A pointer to the disassemble_info struct. - We don't require dis-asm.h so we use void * for the type here. - If NULL, BYTES is full of valid data (VALID == -1). */ - void *dis_info; - /* Points to a working buffer of sufficient size. */ - unsigned char *insn_bytes; - /* Mask of bytes that are valid in INSN_BYTES. */ - unsigned int valid; -} CGEN_EXTRACT_INFO; - -/* Associated with each insn or expression is a set of "handlers" for - performing operations like parsing, printing, etc. These require a bfd_vma - value to be passed around but we don't want all applications to need bfd.h. - So this stuff is only provided if bfd.h has been included. */ - -/* Parse handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - STRP is a pointer to a pointer to the text being parsed. - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - If the expression is successfully parsed, *STRP is updated. - If not it is left alone. - The result is NULL if success or an error message. */ -typedef const char * (cgen_parse_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - const char **strp_, CGEN_FIELDS *fields_); - -/* Insert handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - FIELDS is a pointer to a cgen_fields struct from which the values - are fetched. - INSNP is a pointer to a buffer in which to place the insn. - PC is the pc value of the insn. - The result is an error message or NULL if success. */ - -#ifdef __BFD_H_SEEN__ -typedef const char * (cgen_insert_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, - bfd_vma pc_); -#else -typedef const char * (cgen_insert_fn) (); -#endif - -/* Extract handler. - CD is a cpu table descriptor. - INSN is a pointer to a struct describing the insn being parsed. - The second argument is a pointer to a struct controlling extraction - (only used for variable length insns). - EX_INFO is a pointer to a struct for controlling reading of further - bytes for the insn. - BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). - FIELDS is a pointer to a cgen_fields struct in which the results are placed. - PC is the pc value of the insn. - The result is the length of the insn in bits or zero if not recognized. */ - -#ifdef __BFD_H_SEEN__ -typedef int (cgen_extract_fn) - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, - CGEN_FIELDS *fields_, bfd_vma pc_); -#else -typedef int (cgen_extract_fn) (); -#endif - -/* Print handler. - CD is a cpu table descriptor. - INFO is a pointer to the disassembly info. - Eg: disassemble_info. It's defined as `PTR' so this file can be included - without dis-asm.h. - INSN is a pointer to a struct describing the insn being printed. - FIELDS is a pointer to a cgen_fields struct. - PC is the pc value of the insn. - LEN is the length of the insn, in bits. */ - -#ifdef __BFD_H_SEEN__ -typedef void (cgen_print_fn) - (CGEN_CPU_DESC, void * info_, const CGEN_INSN *insn_, - CGEN_FIELDS *fields_, bfd_vma pc_, int len_); -#else -typedef void (cgen_print_fn) (); -#endif - -/* Parse/insert/extract/print handlers. - - Indices into the handler tables. - We could use pointers here instead, but 90% of them are generally identical - and that's a lot of redundant data. Making these unsigned char indices - into tables of pointers saves a bit of space. - Using indices also keeps assembler code out of the disassembler and - vice versa. */ - -struct cgen_opcode_handler -{ - unsigned char parse, insert, extract, print; -}; - -/* Assembler interface. - - The interface to the assembler is intended to be clean in the sense that - libopcodes.a is a standalone entity and could be used with any assembler. - Not that one would necessarily want to do that but rather that it helps - keep a clean interface. The interface will obviously be slanted towards - GAS, but at least it's a start. - ??? Note that one possible user of the assembler besides GAS is GDB. - - Parsing is controlled by the assembler which calls - CGEN_SYM (assemble_insn). If it can parse and build the entire insn - it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, cgen_parse_operand_fn is called which can either - - - return a number to be inserted in the insn - - return a "register" value to be inserted - (the register might not be a register per pe) - - queue the argument and return a marker saying the expression has been - queued (eg: a fix-up) - - return an error message indicating the expression wasn't recognizable - - The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ - -/* Values for indicating what the caller wants. */ - -enum cgen_parse_operand_type -{ - CGEN_PARSE_OPERAND_INIT, - CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS, - CGEN_PARSE_OPERAND_SYMBOLIC -}; - -/* Values for indicating what was parsed. */ - -enum cgen_parse_operand_result -{ - CGEN_PARSE_OPERAND_RESULT_NUMBER, - CGEN_PARSE_OPERAND_RESULT_REGISTER, - CGEN_PARSE_OPERAND_RESULT_QUEUED, - CGEN_PARSE_OPERAND_RESULT_ERROR -}; - -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -typedef const char * (cgen_parse_operand_fn) - (CGEN_CPU_DESC, - enum cgen_parse_operand_type, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -#else -typedef const char * (cgen_parse_operand_fn) (); -#endif - -/* Set the cgen_parse_operand_fn callback. */ - -extern void cgen_set_parse_operand_fn - (CGEN_CPU_DESC, cgen_parse_operand_fn); - -/* Called before trying to match a table entry with the insn. */ - -extern void cgen_init_parse_operand (CGEN_CPU_DESC); - -/* Operand values (keywords, integers, symbols, etc.) */ - -/* Types of assembler elements. */ - -enum cgen_asm_type -{ - CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX -}; - -#ifndef CGEN_ARCH -enum cgen_hw_type { CGEN_HW_MAX }; -#endif - -/* List of hardware elements. */ - -typedef struct -{ - char *name; - enum cgen_hw_type type; - /* There is currently no example where both index specs and value specs - are required, so for now both are clumped under "asm_data". */ - enum cgen_asm_type asm_type; - void *asm_data; -#ifndef CGEN_HW_NBOOL_ATTRS -#define CGEN_HW_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; -#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) -} CGEN_HW_ENTRY; - -/* Return value of attribute ATTR in HW. */ - -#define CGEN_HW_ATTR_VALUE(hw, attr) \ -CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) - -/* Table of hardware elements for selected mach, computed at runtime. - enum cgen_hw_type is an index into this table (specifically `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_HW_ENTRY *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_HW_ENTRY **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_HW_TABLE; - -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num - (CGEN_CPU_DESC, unsigned int); - -/* This struct is used to describe things like register names, etc. */ - -typedef struct cgen_keyword_entry -{ - /* Name (as in register name). */ - char * name; - - /* Value (as in register number). - The value cannot be -1 as that is used to indicate "not found". - IDEA: Have "FUNCTION" attribute? [function is called to fetch value]. */ - int value; - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ - /* ??? Moving this last should be done by treating keywords like insn lists - and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ - /* FIXME: Not used yet. */ -#ifndef CGEN_KEYWORD_NBOOL_ATTRS -#define CGEN_KEYWORD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; - - /* ??? Putting these here means compiled in entries can't be const. - Not a really big deal, but something to consider. */ - /* Next name hash table entry. */ - struct cgen_keyword_entry *next_name; - /* Next value hash table entry. */ - struct cgen_keyword_entry *next_value; -} CGEN_KEYWORD_ENTRY; - -/* Top level struct for describing a set of related keywords - (e.g. register names). - - This struct supports run-time entry of new values, and hashed lookups. */ - -typedef struct cgen_keyword -{ - /* Pointer to initial [compiled in] values. */ - CGEN_KEYWORD_ENTRY *init_entries; - - /* Number of entries in `init_entries'. */ - unsigned int num_init_entries; - - /* Hash table used for name lookup. */ - CGEN_KEYWORD_ENTRY **name_hash_table; - - /* Hash table used for value lookup. */ - CGEN_KEYWORD_ENTRY **value_hash_table; - - /* Number of entries in the hash_tables. */ - unsigned int hash_table_size; - - /* Pointer to null keyword "" entry if present. */ - const CGEN_KEYWORD_ENTRY *null_entry; - - /* String containing non-alphanumeric characters used - in keywords. - At present, the highest number of entries used is 1. */ - char nonalpha_chars[8]; -} CGEN_KEYWORD; - -/* Structure used for searching. */ - -typedef struct -{ - /* Table being searched. */ - const CGEN_KEYWORD *table; - - /* Specification of what is being searched for. */ - const char *spec; - - /* Current index in hash table. */ - unsigned int current_hash; - - /* Current element in current hash chain. */ - CGEN_KEYWORD_ENTRY *current_entry; -} CGEN_KEYWORD_SEARCH; - -/* Lookup a keyword from its name. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name - (CGEN_KEYWORD *, const char *); - -/* Lookup a keyword from its value. */ - -const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value - (CGEN_KEYWORD *, int); - -/* Add a keyword. */ - -void cgen_keyword_add (CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *); - -/* Keyword searching. - This can be used to retrieve every keyword, or a subset. */ - -CGEN_KEYWORD_SEARCH cgen_keyword_search_init - (CGEN_KEYWORD *, const char *); -const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next - (CGEN_KEYWORD_SEARCH *); - -/* Operand value support routines. */ - -extern const char *cgen_parse_keyword - (CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *); -#ifdef __BFD_H_SEEN__ /* Don't require bfd.h unnecessarily. */ -extern const char *cgen_parse_signed_integer - (CGEN_CPU_DESC, const char **, int, long *); -extern const char *cgen_parse_unsigned_integer - (CGEN_CPU_DESC, const char **, int, unsigned long *); -extern const char *cgen_parse_address - (CGEN_CPU_DESC, const char **, int, int, - enum cgen_parse_operand_result *, bfd_vma *); -extern const char *cgen_validate_signed_integer - (long, long, long); -extern const char *cgen_validate_unsigned_integer - (unsigned long, unsigned long, unsigned long); -#endif - -/* Operand modes. */ - -/* ??? This duplicates the values in arch.h. Revisit. - These however need the CGEN_ prefix [as does everything in this file]. */ -/* ??? Targets may need to add their own modes so we may wish to move this - to <arch>-opc.h, or add a hook. */ - -enum cgen_mode { - CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ - CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, - CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, - CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, - CGEN_MODE_TARGET_MAX, - CGEN_MODE_INT, CGEN_MODE_UINT, - CGEN_MODE_MAX -}; - -/* FIXME: Until simulator is updated. */ - -#define CGEN_MODE_VM CGEN_MODE_VOID - -/* Operands. */ - -#ifndef CGEN_ARCH -enum cgen_operand_type { CGEN_OPERAND_MAX }; -#endif - -/* "nil" indicator for the operand instance table */ -#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX - -/* A tree of these structs represents the multi-ifield - structure of an operand's hw-index value, if it exists. */ - -struct cgen_ifld; - -typedef struct cgen_maybe_multi_ifield -{ - int count; /* 0: indexed by single cgen_ifld (possibly null: dead entry); - n: indexed by array of more cgen_maybe_multi_ifields. */ - union - { - const void *p; - const struct cgen_maybe_multi_ifield * multi; - const struct cgen_ifld * leaf; - } val; -} -CGEN_MAYBE_MULTI_IFLD; - -/* This struct defines each entry in the operand table. */ - -typedef struct -{ - /* Name as it appears in the syntax string. */ - char *name; - - /* Operand type. */ - enum cgen_operand_type type; - - /* The hardware element associated with this operand. */ - enum cgen_hw_type hw_type; - - /* FIXME: We don't yet record ifield definitions, which we should. - When we do it might make sense to delete start/length (since they will - be duplicated in the ifield's definition) and replace them with a - pointer to the ifield entry. */ - - /* Bit position. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char start; - - /* The number of bits in the operand. - This is just a hint, and may be unused in more complex operands. - May be unused for a modifier. */ - unsigned char length; - - /* The (possibly-multi) ifield used as an index for this operand, if it - is indexed by a field at all. This substitutes / extends the start and - length fields above, but unsure at this time whether they are used - anywhere. */ - CGEN_MAYBE_MULTI_IFLD index_fields; -#if 0 /* ??? Interesting idea but relocs tend to get too complicated, - and ABI dependent, for simple table lookups to work. */ - /* Ideally this would be the internal (external?) reloc type. */ - int reloc_type; -#endif - - /* Attributes. - This should, but technically needn't, appear last. It is a variable sized - array in that one architecture may have 1 nonbool attribute and another - may have more. Having this last means the non-architecture specific code - needn't care, now or tomorrow. The goal is to eventually record - attributes in their raw form, evaluate them at run-time, and cache the - values, so this worry will go away anyway. */ -#ifndef CGEN_OPERAND_NBOOL_ATTRS -#define CGEN_OPERAND_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs; -#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs) -} CGEN_OPERAND; - -/* Return value of attribute ATTR in OPERAND. */ - -#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ -CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) - -/* Table of operands for selected mach/isa, computed at runtime. - enum cgen_operand_type is an index into this table (specifically - `entries'). */ - -typedef struct { - /* Pointer to null terminated table of all compiled in entries. */ - const CGEN_OPERAND *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - /* Array of all entries, initial and run-time added. */ - const CGEN_OPERAND **entries; - /* Number of elements in `entries'. */ - unsigned int num_entries; - /* For now, xrealloc is called each time a new entry is added at runtime. - ??? May wish to keep track of some slop to reduce the number of calls to - xrealloc, except that there's unlikely to be many and not expected to be - in speed critical code. */ -} CGEN_OPERAND_TABLE; - -extern const CGEN_OPERAND * cgen_operand_lookup_by_name - (CGEN_CPU_DESC, const char *); -extern const CGEN_OPERAND * cgen_operand_lookup_by_num - (CGEN_CPU_DESC, int); - -/* Instruction operand instances. - - For each instruction, a list of the hardware elements that are read and - written are recorded. */ - -/* The type of the instance. */ - -enum cgen_opinst_type { - /* End of table marker. */ - CGEN_OPINST_END = 0, - CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT -}; - -typedef struct -{ - /* Input or output indicator. */ - enum cgen_opinst_type type; - - /* Name of operand. */ - const char *name; - - /* The hardware element referenced. */ - enum cgen_hw_type hw_type; - - /* The mode in which the operand is being used. */ - enum cgen_mode mode; - - /* The operand table entry CGEN_OPERAND_NIL if there is none - (i.e. an explicit hardware reference). */ - enum cgen_operand_type op_type; - - /* If `operand' is "nil", the index (e.g. into array of registers). */ - int index; - - /* Attributes. - ??? This perhaps should be a real attribute struct but there's - no current need, so we save a bit of space and just have a set of - flags. The interface is such that this can easily be made attributes - should it prove useful. */ - unsigned int attrs; -#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) -/* Return value of attribute ATTR in OPINST. */ -#define CGEN_OPINST_ATTR(opinst, attr) \ -((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) -/* Operand is conditionally referenced (read/written). */ -#define CGEN_OPINST_COND_REF 1 -} CGEN_OPINST; - -/* Syntax string. - - Each insn format and subexpression has one of these. - - The syntax "string" consists of characters (n > 0 && n < 128), and operand - values (n >= 128), and is terminated by 0. Operand values are 128 + index - into the operand table. The operand table doesn't exist in C, per se, as - the data is recorded in the parse/insert/extract/print switch statements. */ - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_SYNTAX_ELEMENTS 48 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS -#if CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS > CGEN_MAX_SYNTAX_ELEMENTS -#error "CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS too high - enlarge CGEN_MAX_SYNTAX_ELEMENTS" -#endif -#endif - -typedef unsigned short CGEN_SYNTAX_CHAR_TYPE; - -typedef struct -{ - CGEN_SYNTAX_CHAR_TYPE syntax[CGEN_MAX_SYNTAX_ELEMENTS]; -} CGEN_SYNTAX; - -#define CGEN_SYNTAX_STRING(syn) (syn->syntax) -#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128) -#define CGEN_SYNTAX_CHAR(c) ((unsigned char)c) -#define CGEN_SYNTAX_FIELD(c) ((c) - 128) -#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128) - -/* ??? I can't currently think of any case where the mnemonic doesn't come - first [and if one ever doesn't building the hash tables will be tricky]. - However, we treat mnemonics as just another operand of the instruction. - A value of 1 means "this is where the mnemonic appears". 1 isn't - special other than it's a non-printable ASCII char. */ - -#define CGEN_SYNTAX_MNEMONIC 1 -#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) - -/* Instruction fields. - - ??? We currently don't allow adding fields at run-time. - Easy to fix when needed. */ - -typedef struct cgen_ifld { - /* Enum of ifield. */ - int num; -#define CGEN_IFLD_NUM(f) ((f)->num) - - /* Name of the field, distinguishes it from all other fields. */ - const char *name; -#define CGEN_IFLD_NAME(f) ((f)->name) - - /* Default offset, in bits, from the start of the insn to the word - containing the field. */ - int word_offset; -#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) - - /* Default length of the word containing the field. */ - int word_size; -#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) - - /* Default starting bit number. - Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ - int start; -#define CGEN_IFLD_START(f) ((f)->start) - - /* Length of the field, in bits. */ - int length; -#define CGEN_IFLD_LENGTH(f) ((f)->length) - -#ifndef CGEN_IFLD_NBOOL_ATTRS -#define CGEN_IFLD_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; -#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) -} CGEN_IFLD; - -/* Return value of attribute ATTR in IFLD. */ -#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ -CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) - -/* Instruction data. */ - -/* Instruction formats. - - Instructions are grouped by format. Associated with an instruction is its - format. Each insn's opcode table entry contains a format table entry. - ??? There is usually very few formats compared with the number of insns, - so one can reduce the size of the opcode table by recording the format table - as a separate entity. Given that we currently don't, format table entries - are also distinguished by their operands. This increases the size of the - table, but reduces the number of tables. It's all minutiae anyway so it - doesn't really matter [at this point in time]. - - ??? Support for variable length ISA's is wip. */ - -/* Accompanying each iformat description is a list of its fields. */ - -typedef struct { - const CGEN_IFLD *ifld; -#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) -} CGEN_IFMT_IFLD; - -/* This should be at least as large as necessary for any target. */ -#define CGEN_MAX_IFMT_OPERANDS 16 - -/* A target may know its own precise maximum. Assert that it falls below - the above limit. */ -#ifdef CGEN_ACTUAL_MAX_IFMT_OPERANDS -#if CGEN_ACTUAL_MAX_IFMT_OPERANDS > CGEN_MAX_IFMT_OPERANDS -#error "CGEN_ACTUAL_MAX_IFMT_OPERANDS too high - enlarge CGEN_MAX_IFMT_OPERANDS" -#endif -#endif - - -typedef struct -{ - /* Length that MASK and VALUE have been calculated to - [VALUE is recorded elsewhere]. - Normally it is base_insn_bitsize. On [V]LIW architectures where the base - insn size may be larger than the size of an insn, this field is less than - base_insn_bitsize. */ - unsigned char mask_length; -#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) - - /* Total length of instruction, in bits. */ - unsigned char length; -#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) - - /* Mask to apply to the first MASK_LENGTH bits. - Each insn's value is stored with the insn. - The first step in recognizing an insn for disassembly is - (opcode & mask) == value. */ - CGEN_INSN_INT mask; -#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) - - /* Instruction fields. - +1 for trailing NULL. */ - CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; -#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) -} CGEN_IFMT; - -/* Instruction values. */ - -typedef struct -{ - /* The opcode portion of the base insn. */ - CGEN_INSN_INT base_value; - -#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS - /* Extra opcode values beyond base_value. */ - unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; -#endif -} CGEN_IVALUE; - -/* Instruction opcode table. - This contains the syntax and format data of an instruction. */ - -/* ??? Some ports already have an opcode table yet still need to use the rest - of what cgen_insn has. Plus keeping the opcode data with the operand - instance data can create a pretty big file. So we keep them separately. - Not sure this is a good idea in the long run. */ - -typedef struct -{ - /* Indices into parse/insert/extract/print handler tables. */ - struct cgen_opcode_handler handlers; -#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) - - /* Syntax string. */ - CGEN_SYNTAX syntax; -#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) - - /* Format entry. */ - const CGEN_IFMT *format; -#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) -#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) -#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) - - /* Instruction opcode value. */ - CGEN_IVALUE value; -#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) -#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) -#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) -} CGEN_OPCODE; - -/* Instruction attributes. - This is made a published type as applications can cache a pointer to - the attributes for speed. */ - -#ifndef CGEN_INSN_NBOOL_ATTRS -#define CGEN_INSN_NBOOL_ATTRS 1 -#endif -typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; - -/* Enum of architecture independent attributes. */ - -#ifndef CGEN_ARCH -/* ??? Numbers here are recorded in two places. */ -typedef enum cgen_insn_attr { - CGEN_INSN_ALIAS = 0 -} CGEN_INSN_ATTR; -#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) ((attrs)->bool & (1 << CGEN_INSN_ALIAS)) -#endif - -/* This struct defines each entry in the instruction table. */ - -typedef struct -{ - /* Each real instruction is enumerated. */ - /* ??? This may go away in time. */ - int num; -#define CGEN_INSN_NUM(insn) ((insn)->base->num) - - /* Name of entry (that distinguishes it from all other entries). */ - /* ??? If mnemonics have operands, try to print full mnemonic. */ - const char *name; -#define CGEN_INSN_NAME(insn) ((insn)->base->name) - - /* Mnemonic. This is used when parsing and printing the insn. - In the case of insns that have operands on the mnemonics, this is - only the constant part. E.g. for conditional execution of an `add' insn, - where the full mnemonic is addeq, addne, etc., and the condition is - treated as an operand, this is only "add". */ - const char *mnemonic; -#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) - - /* Total length of instruction, in bits. */ - int bitsize; -#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) - -#if 0 /* ??? Disabled for now as there is a problem with embedded newlines - and the table is already pretty big. Should perhaps be moved - to a file of its own. */ - /* Semantics, as RTL. */ - /* ??? Plain text or bytecodes? */ - /* ??? Note that the operand instance table could be computed at run-time - if we parse this and cache the results. Something to eventually do. */ - const char *rtx; -#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) -#endif - - /* Attributes. - This must appear last. It is a variable sized array in that one - architecture may have 1 nonbool attribute and another may have more. - Having this last means the non-architecture specific code needn't - care. The goal is to eventually record attributes in their raw form, - evaluate them at run-time, and cache the values, so this worry will go - away anyway. */ - CGEN_INSN_ATTR_TYPE attrs; -#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) -/* Return value of attribute ATTR in INSN. */ -#define CGEN_INSN_ATTR_VALUE(insn, attr) \ -CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) -#define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ - CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) -} CGEN_IBASE; - -/* Return non-zero if INSN is the "invalid" insn marker. */ - -#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) - -/* Main struct contain instruction information. - BASE is always present, the rest is present only if asked for. */ - -struct cgen_insn -{ - /* ??? May be of use to put a type indicator here. - Then this struct could different info for different classes of insns. */ - /* ??? A speedup can be had by moving `base' into this struct. - Maybe later. */ - const CGEN_IBASE *base; - const CGEN_OPCODE *opcode; - const CGEN_OPINST *opinst; - - /* Regex to disambiguate overloaded opcodes */ - void *rx; -#define CGEN_INSN_RX(insn) ((insn)->rx) -#define CGEN_MAX_RX_ELEMENTS (CGEN_MAX_SYNTAX_ELEMENTS * 5) -}; - -/* Instruction lists. - This is used for adding new entries and for creating the hash lists. */ - -typedef struct cgen_insn_list -{ - struct cgen_insn_list *next; - const CGEN_INSN *insn; -} CGEN_INSN_LIST; - -/* Table of instructions. */ - -typedef struct -{ - const CGEN_INSN *init_entries; - unsigned int entry_size; /* since the attribute member is variable sized */ - unsigned int num_init_entries; - CGEN_INSN_LIST *new_entries; -} CGEN_INSN_TABLE; - -/* Return number of instructions. This includes any added at run-time. */ - -extern int cgen_insn_count (CGEN_CPU_DESC); -extern int cgen_macro_insn_count (CGEN_CPU_DESC); - -/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ - -/* Fetch INSN's operand instance table. */ -/* ??? Doesn't handle insns added at runtime. */ -#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) - -/* Return INSN's opcode table entry. */ -#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) - -/* Return INSN's handler data. */ -#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) - -/* Return INSN's syntax. */ -#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) - -/* Return size of base mask in bits. */ -#define CGEN_INSN_MASK_BITSIZE(insn) \ - CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) - -/* Return mask of base part of INSN. */ -#define CGEN_INSN_BASE_MASK(insn) \ - CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) - -/* Return value of base part of INSN. */ -#define CGEN_INSN_BASE_VALUE(insn) \ - CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) - -/* Standard way to test whether INSN is supported by MACH. - MACH is one of enum mach_attr. - The "|1" is because the base mach is always selected. */ -#define CGEN_INSN_MACH_HAS_P(insn, mach) \ -((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) - -/* Macro instructions. - Macro insns aren't real insns, they map to one or more real insns. - E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or - some such. - - Macro insns can expand to nothing (e.g. a nop that is optimized away). - This is useful in multi-insn macros that build a constant in a register. - Of course this isn't the default behaviour and must be explicitly enabled. - - Assembly of macro-insns is relatively straightforward. Disassembly isn't. - However, disassembly of at least some kinds of macro insns is important - in order that the disassembled code preserve the readability of the original - insn. What is attempted here is to disassemble all "simple" macro-insns, - where "simple" is currently defined to mean "expands to one real insn". - - Simple macro-insns are handled specially. They are emitted as ALIAS's - of real insns. This simplifies their handling since there's usually more - of them than any other kind of macro-insn, and proper disassembly of them - falls out for free. */ - -/* For each macro-insn there may be multiple expansion possibilities, - depending on the arguments. This structure is accessed via the `data' - member of CGEN_INSN. */ - -typedef struct cgen_minsn_expansion { - /* Function to do the expansion. - If the expansion fails (e.g. "no match") NULL is returned. - Space for the expansion is obtained with malloc. - It is up to the caller to free it. */ - const char * (* fn) - (const struct cgen_minsn_expansion *, - const char *, const char **, int *, - CGEN_OPERAND **); -#define CGEN_MIEXPN_FN(ex) ((ex)->fn) - - /* Instruction(s) the macro expands to. - The format of STR is defined by FN. - It is typically the assembly code of the real insn, but it could also be - the original Scheme expression or a tokenized form of it (with FN being - an appropriate interpreter). */ - const char * str; -#define CGEN_MIEXPN_STR(ex) ((ex)->str) -} CGEN_MINSN_EXPANSION; - -/* Normal expander. - When supported, this function will convert the input string to another - string and the parser will be invoked recursively. The output string - may contain further macro invocations. */ - -extern const char * cgen_expand_macro_insn - (CGEN_CPU_DESC, const struct cgen_minsn_expansion *, - const char *, const char **, int *, CGEN_OPERAND **); - -/* The assembler insn table is hashed based on some function of the mnemonic - (the actually hashing done is up to the target, but we provide a few - examples like the first letter or a function of the entire mnemonic). */ - -extern CGEN_INSN_LIST * cgen_asm_lookup_insn - (CGEN_CPU_DESC, const char *); -#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) -#define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) - -/* The disassembler insn table is hashed based on some function of machine - instruction (the actually hashing done is up to the target). */ - -extern CGEN_INSN_LIST * cgen_dis_lookup_insn - (CGEN_CPU_DESC, const char *, CGEN_INSN_INT); -/* FIXME: delete these two */ -#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) -#define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) - -/* The CPU description. - A copy of this is created when the cpu table is "opened". - All global state information is recorded here. - Access macros are provided for "public" members. */ - -typedef struct cgen_cpu_desc -{ - /* Bitmap of selected machine(s) (a la BFD machine number). */ - int machs; - - /* Bitmap of selected isa(s). */ - CGEN_BITSET *isas; -#define CGEN_CPU_ISAS(cd) ((cd)->isas) - - /* Current endian. */ - enum cgen_endian endian; -#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) - - /* Current insn endian. */ - enum cgen_endian insn_endian; -#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) - - /* Word size (in bits). */ - /* ??? Or maybe maximum word size - might we ever need to allow a cpu table - to be opened for both sparc32/sparc64? - ??? Another alternative is to create a table of selected machs and - lazily fetch the data from there. */ - unsigned int word_bitsize; - - /* Instruction chunk size (in bits), for purposes of endianness - conversion. */ - unsigned int insn_chunk_bitsize; - - /* Indicator if sizes are unknown. - This is used by default_insn_bitsize,base_insn_bitsize if there is a - difference between the selected isa's. */ -#define CGEN_SIZE_UNKNOWN 65535 - - /* Default instruction size (in bits). - This is used by the assembler when it encounters an unknown insn. */ - unsigned int default_insn_bitsize; - - /* Base instruction size (in bits). - For non-LIW cpus this is generally the length of the smallest insn. - For LIW cpus its wip (work-in-progress). For the m32r its 32. */ - unsigned int base_insn_bitsize; - - /* Minimum/maximum instruction size (in bits). */ - unsigned int min_insn_bitsize; - unsigned int max_insn_bitsize; - - /* Instruction set variants. */ - const CGEN_ISA *isa_table; - - /* Machine variants. */ - const CGEN_MACH *mach_table; - - /* Hardware elements. */ - CGEN_HW_TABLE hw_table; - - /* Instruction fields. */ - const CGEN_IFLD *ifld_table; - - /* Operands. */ - CGEN_OPERAND_TABLE operand_table; - - /* Main instruction table. */ - CGEN_INSN_TABLE insn_table; -#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) - - /* Macro instructions are defined separately and are combined with real - insns during hash table computation. */ - CGEN_INSN_TABLE macro_insn_table; - - /* Copy of CGEN_INT_INSN_P. */ - int int_insn_p; - - /* Called to rebuild the tables after something has changed. */ - void (*rebuild_tables) (CGEN_CPU_DESC); - - /* Operand parser callback. */ - cgen_parse_operand_fn * parse_operand_fn; - - /* Parse/insert/extract/print cover fns for operands. */ - const char * (*parse_operand) - (CGEN_CPU_DESC, int opindex_, const char **, CGEN_FIELDS *fields_); -#ifdef __BFD_H_SEEN__ - const char * (*insert_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, - CGEN_INSN_BYTES_PTR, bfd_vma pc_); - int (*extract_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - CGEN_FIELDS *fields_, bfd_vma pc_); - void (*print_operand) - (CGEN_CPU_DESC, int opindex_, void * info_, CGEN_FIELDS * fields_, - void const *attrs_, bfd_vma pc_, int length_); -#else - const char * (*insert_operand) (); - int (*extract_operand) (); - void (*print_operand) (); -#endif -#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) -#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) -#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) -#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) - - /* Size of CGEN_FIELDS struct. */ - unsigned int sizeof_fields; -#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) - - /* Set the bitsize field. */ - void (*set_fields_bitsize) (CGEN_FIELDS *fields_, int size_); -#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) - - /* CGEN_FIELDS accessors. */ - int (*get_int_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_int_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_); -#ifdef __BFD_H_SEEN__ - bfd_vma (*get_vma_operand) - (CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_); - void (*set_vma_operand) - (CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_); -#else - long (*get_vma_operand) (); - void (*set_vma_operand) (); -#endif -#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) -#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) -#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) -#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) - - /* Instruction parse/insert/extract/print handlers. */ - /* FIXME: make these types uppercase. */ - cgen_parse_fn * const *parse_handlers; - cgen_insert_fn * const *insert_handlers; - cgen_extract_fn * const *extract_handlers; - cgen_print_fn * const *print_handlers; -#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) -#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) -#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) -#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) - - /* Return non-zero if insn should be added to hash table. */ - int (* asm_hash_p) (const CGEN_INSN *); - - /* Assembler hash function. */ - unsigned int (* asm_hash) (const char *); - - /* Number of entries in assembler hash table. */ - unsigned int asm_hash_size; - - /* Return non-zero if insn should be added to hash table. */ - int (* dis_hash_p) (const CGEN_INSN *); - - /* Disassembler hash function. */ - unsigned int (* dis_hash) (const char *, CGEN_INSN_INT); - - /* Number of entries in disassembler hash table. */ - unsigned int dis_hash_size; - - /* Assembler instruction hash table. */ - CGEN_INSN_LIST **asm_hash_table; - CGEN_INSN_LIST *asm_hash_table_entries; - - /* Disassembler instruction hash table. */ - CGEN_INSN_LIST **dis_hash_table; - CGEN_INSN_LIST *dis_hash_table_entries; - - /* This field could be turned into a bitfield if room for other flags is needed. */ - unsigned int signed_overflow_ok_p; - -} CGEN_CPU_TABLE; - -/* wip */ -#ifndef CGEN_WORD_ENDIAN -#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) -#endif -#ifndef CGEN_INSN_WORD_ENDIAN -#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) -#endif - -/* Prototypes of major functions. */ -/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. - Not the init fns though, as that would drag in things that mightn't be - used and might not even exist. */ - -/* Argument types to cpu_open. */ - -enum cgen_cpu_open_arg { - CGEN_CPU_OPEN_END, - /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_ISAS, - /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ - CGEN_CPU_OPEN_MACHS, - /* Select machine, arg is mach's bfd name. - Multiple machines can be specified by repeated use. */ - CGEN_CPU_OPEN_BFDMACH, - /* Select endian, arg is CGEN_ENDIAN_*. */ - CGEN_CPU_OPEN_ENDIAN -}; - -/* Open a cpu descriptor table for use. - ??? We only support ISO C stdargs here, not K&R. - Laziness, plus experiment to see if anything requires K&R - eventually - K&R will no longer be supported - e.g. GDB is currently trying this. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); - -/* Cover fn to handle simple case. */ - -extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) - (const char *mach_name_, enum cgen_endian endian_); - -/* Close it. */ - -extern void CGEN_SYM (cpu_close) (CGEN_CPU_DESC); - -/* Initialize the opcode table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_opcode_table) (CGEN_CPU_DESC cd_); - -/* build the insn selection regex. - called by init_opcode_table */ - -extern char * CGEN_SYM(build_insn_regex) (CGEN_INSN *insn_); - -/* Initialize the ibld table for use. - Called by init_asm/init_dis. */ - -extern void CGEN_SYM (init_ibld_table) (CGEN_CPU_DESC cd_); - -/* Initialize an cpu table for assembler or disassembler use. - These must be called immediately after cpu_open. */ - -extern void CGEN_SYM (init_asm) (CGEN_CPU_DESC); -extern void CGEN_SYM (init_dis) (CGEN_CPU_DESC); - -/* Initialize the operand instance table for use. */ - -extern void CGEN_SYM (init_opinst_table) (CGEN_CPU_DESC cd_); - -/* Assemble an instruction. */ - -extern const CGEN_INSN * CGEN_SYM (assemble_insn) - (CGEN_CPU_DESC, const char *, CGEN_FIELDS *, - CGEN_INSN_BYTES_PTR, char **); - -extern const CGEN_KEYWORD CGEN_SYM (operand_mach); -extern int CGEN_SYM (get_mach) (const char *); - -/* Operand index computation. */ -extern const CGEN_INSN * cgen_lookup_insn - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, CGEN_FIELDS *fields_, int alias_p_); -extern void cgen_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN * insn_, - const CGEN_FIELDS *fields_, int *indices_); -extern const CGEN_INSN * cgen_lookup_get_insn_operands - (CGEN_CPU_DESC, const CGEN_INSN *insn_, - CGEN_INSN_INT int_value_, unsigned char *bytes_value_, - int length_, int *indices_, CGEN_FIELDS *fields_); - -/* Cover fns to bfd_get/set. */ - -extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); -extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); - -/* Read in a cpu description file. - ??? For future concerns, including adding instructions to the assembler/ - disassembler at run-time. */ - -extern const char * cgen_read_cpu_file (CGEN_CPU_DESC, const char * filename_); - -/* Allow signed overflow of instruction fields. */ -extern void cgen_set_signed_overflow_ok (CGEN_CPU_DESC); - -/* Generate an error message if a signed field in an instruction overflows. */ -extern void cgen_clear_signed_overflow_ok (CGEN_CPU_DESC); - -/* Will an error message be generated if a signed field in an instruction overflows ? */ -extern unsigned int cgen_signed_overflow_ok_p (CGEN_CPU_DESC); - -#endif /* CGEN_H */ diff --git a/contrib/binutils/include/opcode/convex.h b/contrib/binutils/include/opcode/convex.h deleted file mode 100644 index 7843dce8b5b69..0000000000000 --- a/contrib/binutils/include/opcode/convex.h +++ /dev/null @@ -1,1707 +0,0 @@ -/* Information for instruction disassembly on the Convex. - Copyright 1989, 1993, 2002 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#define xxx 0 -#define rrr 1 -#define rr 2 -#define rxr 3 -#define r 4 -#define nops 5 -#define nr 6 -#define pcrel 7 -#define lr 8 -#define rxl 9 -#define rlr 10 -#define rrl 11 -#define iml 12 -#define imr 13 -#define a1r 14 -#define a1l 15 -#define a2r 16 -#define a2l 17 -#define a3 18 -#define a4 19 -#define a5 20 -#define V 1 -#define S 2 -#define VM 3 -#define A 4 -#define VL 5 -#define VS 6 -#define VLS 7 -#define PSW 8 -/* Prevent an error during "make depend". */ -#if !defined (PC) -#define PC 9 -#endif -#define ITR 10 -#define VV 11 -#define ITSR 12 -#define TOC 13 -#define CIR 14 -#define TTR 15 -#define VMU 16 -#define VML 17 -#define ICR 18 -#define TCPU 19 -#define CPUID 20 -#define TID 21 - -const char *op[] = { - "", - "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", - "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", - "vm", - "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", - "vl", - "vs", - "vls", - "psw", - "pc", - "itr", - "vv", - "itsr", - "toc", - "cir", - "ttr", - "vmu", - "vml", - "icr", - "tcpu", - "cpuid", - "tid", -}; - -const struct formstr format0[] = { - {0,0,rrr,V,S,S}, /* mov */ - {0,0,rrr,S,S,V}, /* mov */ - {1,1,rrr,V,V,V}, /* merg.t */ - {2,1,rrr,V,V,V}, /* mask.t */ - {1,2,rrr,V,S,V}, /* merg.f */ - {2,2,rrr,V,S,V}, /* mask.f */ - {1,1,rrr,V,S,V}, /* merg.t */ - {2,1,rrr,V,S,V}, /* mask.t */ - {3,3,rrr,V,V,V}, /* mul.s */ - {3,4,rrr,V,V,V}, /* mul.d */ - {4,3,rrr,V,V,V}, /* div.s */ - {4,4,rrr,V,V,V}, /* div.d */ - {3,3,rrr,V,S,V}, /* mul.s */ - {3,4,rrr,V,S,V}, /* mul.d */ - {4,3,rrr,V,S,V}, /* div.s */ - {4,4,rrr,V,S,V}, /* div.d */ - {5,0,rrr,V,V,V}, /* and */ - {6,0,rrr,V,V,V}, /* or */ - {7,0,rrr,V,V,V}, /* xor */ - {8,0,rrr,V,V,V}, /* shf */ - {5,0,rrr,V,S,V}, /* and */ - {6,0,rrr,V,S,V}, /* or */ - {7,0,rrr,V,S,V}, /* xor */ - {8,0,rrr,V,S,V}, /* shf */ - {9,3,rrr,V,V,V}, /* add.s */ - {9,4,rrr,V,V,V}, /* add.d */ - {10,3,rrr,V,V,V}, /* sub.s */ - {10,4,rrr,V,V,V}, /* sub.d */ - {9,3,rrr,V,S,V}, /* add.s */ - {9,4,rrr,V,S,V}, /* add.d */ - {10,3,rrr,V,S,V}, /* sub.s */ - {10,4,rrr,V,S,V}, /* sub.d */ - {9,5,rrr,V,V,V}, /* add.b */ - {9,6,rrr,V,V,V}, /* add.h */ - {9,7,rrr,V,V,V}, /* add.w */ - {9,8,rrr,V,V,V}, /* add.l */ - {9,5,rrr,V,S,V}, /* add.b */ - {9,6,rrr,V,S,V}, /* add.h */ - {9,7,rrr,V,S,V}, /* add.w */ - {9,8,rrr,V,S,V}, /* add.l */ - {10,5,rrr,V,V,V}, /* sub.b */ - {10,6,rrr,V,V,V}, /* sub.h */ - {10,7,rrr,V,V,V}, /* sub.w */ - {10,8,rrr,V,V,V}, /* sub.l */ - {10,5,rrr,V,S,V}, /* sub.b */ - {10,6,rrr,V,S,V}, /* sub.h */ - {10,7,rrr,V,S,V}, /* sub.w */ - {10,8,rrr,V,S,V}, /* sub.l */ - {3,5,rrr,V,V,V}, /* mul.b */ - {3,6,rrr,V,V,V}, /* mul.h */ - {3,7,rrr,V,V,V}, /* mul.w */ - {3,8,rrr,V,V,V}, /* mul.l */ - {3,5,rrr,V,S,V}, /* mul.b */ - {3,6,rrr,V,S,V}, /* mul.h */ - {3,7,rrr,V,S,V}, /* mul.w */ - {3,8,rrr,V,S,V}, /* mul.l */ - {4,5,rrr,V,V,V}, /* div.b */ - {4,6,rrr,V,V,V}, /* div.h */ - {4,7,rrr,V,V,V}, /* div.w */ - {4,8,rrr,V,V,V}, /* div.l */ - {4,5,rrr,V,S,V}, /* div.b */ - {4,6,rrr,V,S,V}, /* div.h */ - {4,7,rrr,V,S,V}, /* div.w */ - {4,8,rrr,V,S,V}, /* div.l */ -}; - -const struct formstr format1[] = { - {11,0,xxx,0,0,0}, /* exit */ - {12,0,a3,0,0,0}, /* jmp */ - {13,2,a3,0,0,0}, /* jmpi.f */ - {13,1,a3,0,0,0}, /* jmpi.t */ - {14,2,a3,0,0,0}, /* jmpa.f */ - {14,1,a3,0,0,0}, /* jmpa.t */ - {15,2,a3,0,0,0}, /* jmps.f */ - {15,1,a3,0,0,0}, /* jmps.t */ - {16,0,a3,0,0,0}, /* tac */ - {17,0,a1r,A,0,0}, /* ldea */ - {18,8,a1l,VLS,0,0}, /* ld.l */ - {18,9,a1l,VM,0,0}, /* ld.x */ - {19,0,a3,0,0,0}, /* tas */ - {20,0,a3,0,0,0}, /* pshea */ - {21,8,a2l,VLS,0,0}, /* st.l */ - {21,9,a2l,VM,0,0}, /* st.x */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {22,0,a3,0,0,0}, /* call */ - {23,0,a3,0,0,0}, /* calls */ - {24,0,a3,0,0,0}, /* callq */ - {25,0,a1r,A,0,0}, /* pfork */ - {26,5,a2r,S,0,0}, /* ste.b */ - {26,6,a2r,S,0,0}, /* ste.h */ - {26,7,a2r,S,0,0}, /* ste.w */ - {26,8,a2r,S,0,0}, /* ste.l */ - {18,5,a1r,A,0,0}, /* ld.b */ - {18,6,a1r,A,0,0}, /* ld.h */ - {18,7,a1r,A,0,0}, /* ld.w */ - {27,7,a1r,A,0,0}, /* incr.w */ - {21,5,a2r,A,0,0}, /* st.b */ - {21,6,a2r,A,0,0}, /* st.h */ - {21,7,a2r,A,0,0}, /* st.w */ - {27,8,a1r,S,0,0}, /* incr.l */ - {18,5,a1r,S,0,0}, /* ld.b */ - {18,6,a1r,S,0,0}, /* ld.h */ - {18,7,a1r,S,0,0}, /* ld.w */ - {18,8,a1r,S,0,0}, /* ld.l */ - {21,5,a2r,S,0,0}, /* st.b */ - {21,6,a2r,S,0,0}, /* st.h */ - {21,7,a2r,S,0,0}, /* st.w */ - {21,8,a2r,S,0,0}, /* st.l */ - {18,5,a1r,V,0,0}, /* ld.b */ - {18,6,a1r,V,0,0}, /* ld.h */ - {18,7,a1r,V,0,0}, /* ld.w */ - {18,8,a1r,V,0,0}, /* ld.l */ - {21,5,a2r,V,0,0}, /* st.b */ - {21,6,a2r,V,0,0}, /* st.h */ - {21,7,a2r,V,0,0}, /* st.w */ - {21,8,a2r,V,0,0}, /* st.l */ -}; - -const struct formstr format2[] = { - {28,5,rr,A,A,0}, /* cvtw.b */ - {28,6,rr,A,A,0}, /* cvtw.h */ - {29,7,rr,A,A,0}, /* cvtb.w */ - {30,7,rr,A,A,0}, /* cvth.w */ - {28,5,rr,S,S,0}, /* cvtw.b */ - {28,6,rr,S,S,0}, /* cvtw.h */ - {29,7,rr,S,S,0}, /* cvtb.w */ - {30,7,rr,S,S,0}, /* cvth.w */ - {28,3,rr,S,S,0}, /* cvtw.s */ - {31,7,rr,S,S,0}, /* cvts.w */ - {32,3,rr,S,S,0}, /* cvtd.s */ - {31,4,rr,S,S,0}, /* cvts.d */ - {31,8,rr,S,S,0}, /* cvts.l */ - {32,8,rr,S,S,0}, /* cvtd.l */ - {33,3,rr,S,S,0}, /* cvtl.s */ - {33,4,rr,S,S,0}, /* cvtl.d */ - {34,0,rr,A,A,0}, /* ldpa */ - {8,0,nr,A,0,0}, /* shf */ - {18,6,nr,A,0,0}, /* ld.h */ - {18,7,nr,A,0,0}, /* ld.w */ - {33,7,rr,S,S,0}, /* cvtl.w */ - {28,8,rr,S,S,0}, /* cvtw.l */ - {35,1,rr,S,S,0}, /* plc.t */ - {36,0,rr,S,S,0}, /* tzc */ - {37,6,rr,A,A,0}, /* eq.h */ - {37,7,rr,A,A,0}, /* eq.w */ - {37,6,nr,A,0,0}, /* eq.h */ - {37,7,nr,A,0,0}, /* eq.w */ - {37,5,rr,S,S,0}, /* eq.b */ - {37,6,rr,S,S,0}, /* eq.h */ - {37,7,rr,S,S,0}, /* eq.w */ - {37,8,rr,S,S,0}, /* eq.l */ - {38,6,rr,A,A,0}, /* leu.h */ - {38,7,rr,A,A,0}, /* leu.w */ - {38,6,nr,A,0,0}, /* leu.h */ - {38,7,nr,A,0,0}, /* leu.w */ - {38,5,rr,S,S,0}, /* leu.b */ - {38,6,rr,S,S,0}, /* leu.h */ - {38,7,rr,S,S,0}, /* leu.w */ - {38,8,rr,S,S,0}, /* leu.l */ - {39,6,rr,A,A,0}, /* ltu.h */ - {39,7,rr,A,A,0}, /* ltu.w */ - {39,6,nr,A,0,0}, /* ltu.h */ - {39,7,nr,A,0,0}, /* ltu.w */ - {39,5,rr,S,S,0}, /* ltu.b */ - {39,6,rr,S,S,0}, /* ltu.h */ - {39,7,rr,S,S,0}, /* ltu.w */ - {39,8,rr,S,S,0}, /* ltu.l */ - {40,6,rr,A,A,0}, /* le.h */ - {40,7,rr,A,A,0}, /* le.w */ - {40,6,nr,A,0,0}, /* le.h */ - {40,7,nr,A,0,0}, /* le.w */ - {40,5,rr,S,S,0}, /* le.b */ - {40,6,rr,S,S,0}, /* le.h */ - {40,7,rr,S,S,0}, /* le.w */ - {40,8,rr,S,S,0}, /* le.l */ - {41,6,rr,A,A,0}, /* lt.h */ - {41,7,rr,A,A,0}, /* lt.w */ - {41,6,nr,A,0,0}, /* lt.h */ - {41,7,nr,A,0,0}, /* lt.w */ - {41,5,rr,S,S,0}, /* lt.b */ - {41,6,rr,S,S,0}, /* lt.h */ - {41,7,rr,S,S,0}, /* lt.w */ - {41,8,rr,S,S,0}, /* lt.l */ - {9,7,rr,S,A,0}, /* add.w */ - {8,0,rr,A,A,0}, /* shf */ - {0,0,rr,A,A,0}, /* mov */ - {0,0,rr,S,A,0}, /* mov */ - {0,7,rr,S,S,0}, /* mov.w */ - {8,0,rr,S,S,0}, /* shf */ - {0,0,rr,S,S,0}, /* mov */ - {0,0,rr,A,S,0}, /* mov */ - {5,0,rr,A,A,0}, /* and */ - {6,0,rr,A,A,0}, /* or */ - {7,0,rr,A,A,0}, /* xor */ - {42,0,rr,A,A,0}, /* not */ - {5,0,rr,S,S,0}, /* and */ - {6,0,rr,S,S,0}, /* or */ - {7,0,rr,S,S,0}, /* xor */ - {42,0,rr,S,S,0}, /* not */ - {40,3,rr,S,S,0}, /* le.s */ - {40,4,rr,S,S,0}, /* le.d */ - {41,3,rr,S,S,0}, /* lt.s */ - {41,4,rr,S,S,0}, /* lt.d */ - {9,3,rr,S,S,0}, /* add.s */ - {9,4,rr,S,S,0}, /* add.d */ - {10,3,rr,S,S,0}, /* sub.s */ - {10,4,rr,S,S,0}, /* sub.d */ - {37,3,rr,S,S,0}, /* eq.s */ - {37,4,rr,S,S,0}, /* eq.d */ - {43,6,rr,A,A,0}, /* neg.h */ - {43,7,rr,A,A,0}, /* neg.w */ - {3,3,rr,S,S,0}, /* mul.s */ - {3,4,rr,S,S,0}, /* mul.d */ - {4,3,rr,S,S,0}, /* div.s */ - {4,4,rr,S,S,0}, /* div.d */ - {9,6,rr,A,A,0}, /* add.h */ - {9,7,rr,A,A,0}, /* add.w */ - {9,6,nr,A,0,0}, /* add.h */ - {9,7,nr,A,0,0}, /* add.w */ - {9,5,rr,S,S,0}, /* add.b */ - {9,6,rr,S,S,0}, /* add.h */ - {9,7,rr,S,S,0}, /* add.w */ - {9,8,rr,S,S,0}, /* add.l */ - {10,6,rr,A,A,0}, /* sub.h */ - {10,7,rr,A,A,0}, /* sub.w */ - {10,6,nr,A,0,0}, /* sub.h */ - {10,7,nr,A,0,0}, /* sub.w */ - {10,5,rr,S,S,0}, /* sub.b */ - {10,6,rr,S,S,0}, /* sub.h */ - {10,7,rr,S,S,0}, /* sub.w */ - {10,8,rr,S,S,0}, /* sub.l */ - {3,6,rr,A,A,0}, /* mul.h */ - {3,7,rr,A,A,0}, /* mul.w */ - {3,6,nr,A,0,0}, /* mul.h */ - {3,7,nr,A,0,0}, /* mul.w */ - {3,5,rr,S,S,0}, /* mul.b */ - {3,6,rr,S,S,0}, /* mul.h */ - {3,7,rr,S,S,0}, /* mul.w */ - {3,8,rr,S,S,0}, /* mul.l */ - {4,6,rr,A,A,0}, /* div.h */ - {4,7,rr,A,A,0}, /* div.w */ - {4,6,nr,A,0,0}, /* div.h */ - {4,7,nr,A,0,0}, /* div.w */ - {4,5,rr,S,S,0}, /* div.b */ - {4,6,rr,S,S,0}, /* div.h */ - {4,7,rr,S,S,0}, /* div.w */ - {4,8,rr,S,S,0}, /* div.l */ -}; - -const struct formstr format3[] = { - {32,3,rr,V,V,0}, /* cvtd.s */ - {31,4,rr,V,V,0}, /* cvts.d */ - {33,4,rr,V,V,0}, /* cvtl.d */ - {32,8,rr,V,V,0}, /* cvtd.l */ - {0,0,rrl,S,S,VM}, /* mov */ - {0,0,rlr,S,VM,S}, /* mov */ - {0,0,0,0,0,0}, - {44,0,rr,S,S,0}, /* lop */ - {36,0,rr,V,V,0}, /* tzc */ - {44,0,rr,V,V,0}, /* lop */ - {0,0,0,0,0,0}, - {42,0,rr,V,V,0}, /* not */ - {8,0,rr,S,V,0}, /* shf */ - {35,1,rr,V,V,0}, /* plc.t */ - {45,2,rr,V,V,0}, /* cprs.f */ - {45,1,rr,V,V,0}, /* cprs.t */ - {37,3,rr,V,V,0}, /* eq.s */ - {37,4,rr,V,V,0}, /* eq.d */ - {43,3,rr,V,V,0}, /* neg.s */ - {43,4,rr,V,V,0}, /* neg.d */ - {37,3,rr,S,V,0}, /* eq.s */ - {37,4,rr,S,V,0}, /* eq.d */ - {43,3,rr,S,S,0}, /* neg.s */ - {43,4,rr,S,S,0}, /* neg.d */ - {40,3,rr,V,V,0}, /* le.s */ - {40,4,rr,V,V,0}, /* le.d */ - {41,3,rr,V,V,0}, /* lt.s */ - {41,4,rr,V,V,0}, /* lt.d */ - {40,3,rr,S,V,0}, /* le.s */ - {40,4,rr,S,V,0}, /* le.d */ - {41,3,rr,S,V,0}, /* lt.s */ - {41,4,rr,S,V,0}, /* lt.d */ - {37,5,rr,V,V,0}, /* eq.b */ - {37,6,rr,V,V,0}, /* eq.h */ - {37,7,rr,V,V,0}, /* eq.w */ - {37,8,rr,V,V,0}, /* eq.l */ - {37,5,rr,S,V,0}, /* eq.b */ - {37,6,rr,S,V,0}, /* eq.h */ - {37,7,rr,S,V,0}, /* eq.w */ - {37,8,rr,S,V,0}, /* eq.l */ - {40,5,rr,V,V,0}, /* le.b */ - {40,6,rr,V,V,0}, /* le.h */ - {40,7,rr,V,V,0}, /* le.w */ - {40,8,rr,V,V,0}, /* le.l */ - {40,5,rr,S,V,0}, /* le.b */ - {40,6,rr,S,V,0}, /* le.h */ - {40,7,rr,S,V,0}, /* le.w */ - {40,8,rr,S,V,0}, /* le.l */ - {41,5,rr,V,V,0}, /* lt.b */ - {41,6,rr,V,V,0}, /* lt.h */ - {41,7,rr,V,V,0}, /* lt.w */ - {41,8,rr,V,V,0}, /* lt.l */ - {41,5,rr,S,V,0}, /* lt.b */ - {41,6,rr,S,V,0}, /* lt.h */ - {41,7,rr,S,V,0}, /* lt.w */ - {41,8,rr,S,V,0}, /* lt.l */ - {43,5,rr,V,V,0}, /* neg.b */ - {43,6,rr,V,V,0}, /* neg.h */ - {43,7,rr,V,V,0}, /* neg.w */ - {43,8,rr,V,V,0}, /* neg.l */ - {43,5,rr,S,S,0}, /* neg.b */ - {43,6,rr,S,S,0}, /* neg.h */ - {43,7,rr,S,S,0}, /* neg.w */ - {43,8,rr,S,S,0}, /* neg.l */ -}; - -const struct formstr format4[] = { - {46,0,nops,0,0,0}, /* nop */ - {47,0,pcrel,0,0,0}, /* br */ - {48,2,pcrel,0,0,0}, /* bri.f */ - {48,1,pcrel,0,0,0}, /* bri.t */ - {49,2,pcrel,0,0,0}, /* bra.f */ - {49,1,pcrel,0,0,0}, /* bra.t */ - {50,2,pcrel,0,0,0}, /* brs.f */ - {50,1,pcrel,0,0,0}, /* brs.t */ -}; - -const struct formstr format5[] = { - {51,5,rr,V,V,0}, /* ldvi.b */ - {51,6,rr,V,V,0}, /* ldvi.h */ - {51,7,rr,V,V,0}, /* ldvi.w */ - {51,8,rr,V,V,0}, /* ldvi.l */ - {28,3,rr,V,V,0}, /* cvtw.s */ - {31,7,rr,V,V,0}, /* cvts.w */ - {28,8,rr,V,V,0}, /* cvtw.l */ - {33,7,rr,V,V,0}, /* cvtl.w */ - {52,5,rxr,V,V,0}, /* stvi.b */ - {52,6,rxr,V,V,0}, /* stvi.h */ - {52,7,rxr,V,V,0}, /* stvi.w */ - {52,8,rxr,V,V,0}, /* stvi.l */ - {52,5,rxr,S,V,0}, /* stvi.b */ - {52,6,rxr,S,V,0}, /* stvi.h */ - {52,7,rxr,S,V,0}, /* stvi.w */ - {52,8,rxr,S,V,0}, /* stvi.l */ -}; - -const struct formstr format6[] = { - {53,0,r,A,0,0}, /* ldsdr */ - {54,0,r,A,0,0}, /* ldkdr */ - {55,3,r,S,0,0}, /* ln.s */ - {55,4,r,S,0,0}, /* ln.d */ - {56,0,nops,0,0,0}, /* patu */ - {57,0,r,A,0,0}, /* pate */ - {58,0,nops,0,0,0}, /* pich */ - {59,0,nops,0,0,0}, /* plch */ - {0,0,lr,PSW,A,0}, /* mov */ - {0,0,rxl,A,PSW,0}, /* mov */ - {0,0,lr,PC,A,0}, /* mov */ - {60,0,r,S,0,0}, /* idle */ - {0,0,lr,ITR,S,0}, /* mov */ - {0,0,rxl,S,ITR,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,rxl,S,ITSR,0}, /* mov */ - {61,0,nops,0,0,0}, /* rtnq */ - {62,0,nops,0,0,0}, /* cfork */ - {63,0,nops,0,0,0}, /* rtn */ - {64,0,nops,0,0,0}, /* wfork */ - {65,0,nops,0,0,0}, /* join */ - {66,0,nops,0,0,0}, /* rtnc */ - {67,3,r,S,0,0}, /* exp.s */ - {67,4,r,S,0,0}, /* exp.d */ - {68,3,r,S,0,0}, /* sin.s */ - {68,4,r,S,0,0}, /* sin.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {69,3,r,S,0,0}, /* cos.s */ - {69,4,r,S,0,0}, /* cos.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {70,7,r,A,0,0}, /* psh.w */ - {0,0,0,0,0,0}, - {71,7,r,A,0,0}, /* pop.w */ - {0,0,0,0,0,0}, - {70,7,r,S,0,0}, /* psh.w */ - {70,8,r,S,0,0}, /* psh.l */ - {71,7,r,S,0,0}, /* pop.w */ - {71,8,r,S,0,0}, /* pop.l */ - {72,0,nops,0,0,0}, /* eni */ - {73,0,nops,0,0,0}, /* dsi */ - {74,0,nops,0,0,0}, /* bkpt */ - {75,0,nops,0,0,0}, /* msync */ - {76,0,r,S,0,0}, /* mski */ - {77,0,r,S,0,0}, /* xmti */ - {0,0,rxl,S,VV,0}, /* mov */ - {78,0,nops,0,0,0}, /* tstvv */ - {0,0,lr,VS,A,0}, /* mov */ - {0,0,rxl,A,VS,0}, /* mov */ - {0,0,lr,VL,A,0}, /* mov */ - {0,0,rxl,A,VL,0}, /* mov */ - {0,7,lr,VS,S,0}, /* mov.w */ - {0,7,rxl,S,VS,0}, /* mov.w */ - {0,7,lr,VL,S,0}, /* mov.w */ - {0,7,rxl,S,VL,0}, /* mov.w */ - {79,0,r,A,0,0}, /* diag */ - {80,0,nops,0,0,0}, /* pbkpt */ - {81,3,r,S,0,0}, /* sqrt.s */ - {81,4,r,S,0,0}, /* sqrt.d */ - {82,0,nops,0,0,0}, /* casr */ - {0,0,0,0,0,0}, - {83,3,r,S,0,0}, /* atan.s */ - {83,4,r,S,0,0}, /* atan.d */ -}; - -const struct formstr format7[] = { - {84,5,r,V,0,0}, /* sum.b */ - {84,6,r,V,0,0}, /* sum.h */ - {84,7,r,V,0,0}, /* sum.w */ - {84,8,r,V,0,0}, /* sum.l */ - {85,0,r,V,0,0}, /* all */ - {86,0,r,V,0,0}, /* any */ - {87,0,r,V,0,0}, /* parity */ - {0,0,0,0,0,0}, - {88,5,r,V,0,0}, /* max.b */ - {88,6,r,V,0,0}, /* max.h */ - {88,7,r,V,0,0}, /* max.w */ - {88,8,r,V,0,0}, /* max.l */ - {89,5,r,V,0,0}, /* min.b */ - {89,6,r,V,0,0}, /* min.h */ - {89,7,r,V,0,0}, /* min.w */ - {89,8,r,V,0,0}, /* min.l */ - {84,3,r,V,0,0}, /* sum.s */ - {84,4,r,V,0,0}, /* sum.d */ - {90,3,r,V,0,0}, /* prod.s */ - {90,4,r,V,0,0}, /* prod.d */ - {88,3,r,V,0,0}, /* max.s */ - {88,4,r,V,0,0}, /* max.d */ - {89,3,r,V,0,0}, /* min.s */ - {89,4,r,V,0,0}, /* min.d */ - {90,5,r,V,0,0}, /* prod.b */ - {90,6,r,V,0,0}, /* prod.h */ - {90,7,r,V,0,0}, /* prod.w */ - {90,8,r,V,0,0}, /* prod.l */ - {35,2,lr,VM,S,0}, /* plc.f */ - {35,1,lr,VM,S,0}, /* plc.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr formatx[] = { - {0,0,0,0,0,0}, -}; - -const struct formstr format1a[] = { - {91,0,imr,A,0,0}, /* halt */ - {92,0,a4,0,0,0}, /* sysc */ - {18,6,imr,A,0,0}, /* ld.h */ - {18,7,imr,A,0,0}, /* ld.w */ - {5,0,imr,A,0,0}, /* and */ - {6,0,imr,A,0,0}, /* or */ - {7,0,imr,A,0,0}, /* xor */ - {8,0,imr,A,0,0}, /* shf */ - {9,6,imr,A,0,0}, /* add.h */ - {9,7,imr,A,0,0}, /* add.w */ - {10,6,imr,A,0,0}, /* sub.h */ - {10,7,imr,A,0,0}, /* sub.w */ - {3,6,imr,A,0,0}, /* mul.h */ - {3,7,imr,A,0,0}, /* mul.w */ - {4,6,imr,A,0,0}, /* div.h */ - {4,7,imr,A,0,0}, /* div.w */ - {18,7,iml,VL,0,0}, /* ld.w */ - {18,7,iml,VS,0,0}, /* ld.w */ - {0,0,0,0,0,0}, - {8,7,imr,S,0,0}, /* shf.w */ - {93,0,a5,0,0,0}, /* trap */ - {0,0,0,0,0,0}, - {37,6,imr,A,0,0}, /* eq.h */ - {37,7,imr,A,0,0}, /* eq.w */ - {38,6,imr,A,0,0}, /* leu.h */ - {38,7,imr,A,0,0}, /* leu.w */ - {39,6,imr,A,0,0}, /* ltu.h */ - {39,7,imr,A,0,0}, /* ltu.w */ - {40,6,imr,A,0,0}, /* le.h */ - {40,7,imr,A,0,0}, /* le.w */ - {41,6,imr,A,0,0}, /* lt.h */ - {41,7,imr,A,0,0}, /* lt.w */ -}; - -const struct formstr format1b[] = { - {18,4,imr,S,0,0}, /* ld.d */ - {18,10,imr,S,0,0}, /* ld.u */ - {18,8,imr,S,0,0}, /* ld.l */ - {18,7,imr,S,0,0}, /* ld.w */ - {5,0,imr,S,0,0}, /* and */ - {6,0,imr,S,0,0}, /* or */ - {7,0,imr,S,0,0}, /* xor */ - {8,0,imr,S,0,0}, /* shf */ - {9,6,imr,S,0,0}, /* add.h */ - {9,7,imr,S,0,0}, /* add.w */ - {10,6,imr,S,0,0}, /* sub.h */ - {10,7,imr,S,0,0}, /* sub.w */ - {3,6,imr,S,0,0}, /* mul.h */ - {3,7,imr,S,0,0}, /* mul.w */ - {4,6,imr,S,0,0}, /* div.h */ - {4,7,imr,S,0,0}, /* div.w */ - {9,3,imr,S,0,0}, /* add.s */ - {10,3,imr,S,0,0}, /* sub.s */ - {3,3,imr,S,0,0}, /* mul.s */ - {4,3,imr,S,0,0}, /* div.s */ - {40,3,imr,S,0,0}, /* le.s */ - {41,3,imr,S,0,0}, /* lt.s */ - {37,6,imr,S,0,0}, /* eq.h */ - {37,7,imr,S,0,0}, /* eq.w */ - {38,6,imr,S,0,0}, /* leu.h */ - {38,7,imr,S,0,0}, /* leu.w */ - {39,6,imr,S,0,0}, /* ltu.h */ - {39,7,imr,S,0,0}, /* ltu.w */ - {40,6,imr,S,0,0}, /* le.h */ - {40,7,imr,S,0,0}, /* le.w */ - {41,6,imr,S,0,0}, /* lt.h */ - {41,7,imr,S,0,0}, /* lt.w */ -}; - -const struct formstr e0_format0[] = { - {10,3,rrr,S,V,V}, /* sub.s */ - {10,4,rrr,S,V,V}, /* sub.d */ - {4,3,rrr,S,V,V}, /* div.s */ - {4,4,rrr,S,V,V}, /* div.d */ - {10,11,rrr,S,V,V}, /* sub.s.f */ - {10,12,rrr,S,V,V}, /* sub.d.f */ - {4,11,rrr,S,V,V}, /* div.s.f */ - {4,12,rrr,S,V,V}, /* div.d.f */ - {3,11,rrr,V,V,V}, /* mul.s.f */ - {3,12,rrr,V,V,V}, /* mul.d.f */ - {4,11,rrr,V,V,V}, /* div.s.f */ - {4,12,rrr,V,V,V}, /* div.d.f */ - {3,11,rrr,V,S,V}, /* mul.s.f */ - {3,12,rrr,V,S,V}, /* mul.d.f */ - {4,11,rrr,V,S,V}, /* div.s.f */ - {4,12,rrr,V,S,V}, /* div.d.f */ - {5,2,rrr,V,V,V}, /* and.f */ - {6,2,rrr,V,V,V}, /* or.f */ - {7,2,rrr,V,V,V}, /* xor.f */ - {8,2,rrr,V,V,V}, /* shf.f */ - {5,2,rrr,V,S,V}, /* and.f */ - {6,2,rrr,V,S,V}, /* or.f */ - {7,2,rrr,V,S,V}, /* xor.f */ - {8,2,rrr,V,S,V}, /* shf.f */ - {9,11,rrr,V,V,V}, /* add.s.f */ - {9,12,rrr,V,V,V}, /* add.d.f */ - {10,11,rrr,V,V,V}, /* sub.s.f */ - {10,12,rrr,V,V,V}, /* sub.d.f */ - {9,11,rrr,V,S,V}, /* add.s.f */ - {9,12,rrr,V,S,V}, /* add.d.f */ - {10,11,rrr,V,S,V}, /* sub.s.f */ - {10,12,rrr,V,S,V}, /* sub.d.f */ - {9,13,rrr,V,V,V}, /* add.b.f */ - {9,14,rrr,V,V,V}, /* add.h.f */ - {9,15,rrr,V,V,V}, /* add.w.f */ - {9,16,rrr,V,V,V}, /* add.l.f */ - {9,13,rrr,V,S,V}, /* add.b.f */ - {9,14,rrr,V,S,V}, /* add.h.f */ - {9,15,rrr,V,S,V}, /* add.w.f */ - {9,16,rrr,V,S,V}, /* add.l.f */ - {10,13,rrr,V,V,V}, /* sub.b.f */ - {10,14,rrr,V,V,V}, /* sub.h.f */ - {10,15,rrr,V,V,V}, /* sub.w.f */ - {10,16,rrr,V,V,V}, /* sub.l.f */ - {10,13,rrr,V,S,V}, /* sub.b.f */ - {10,14,rrr,V,S,V}, /* sub.h.f */ - {10,15,rrr,V,S,V}, /* sub.w.f */ - {10,16,rrr,V,S,V}, /* sub.l.f */ - {3,13,rrr,V,V,V}, /* mul.b.f */ - {3,14,rrr,V,V,V}, /* mul.h.f */ - {3,15,rrr,V,V,V}, /* mul.w.f */ - {3,16,rrr,V,V,V}, /* mul.l.f */ - {3,13,rrr,V,S,V}, /* mul.b.f */ - {3,14,rrr,V,S,V}, /* mul.h.f */ - {3,15,rrr,V,S,V}, /* mul.w.f */ - {3,16,rrr,V,S,V}, /* mul.l.f */ - {4,13,rrr,V,V,V}, /* div.b.f */ - {4,14,rrr,V,V,V}, /* div.h.f */ - {4,15,rrr,V,V,V}, /* div.w.f */ - {4,16,rrr,V,V,V}, /* div.l.f */ - {4,13,rrr,V,S,V}, /* div.b.f */ - {4,14,rrr,V,S,V}, /* div.h.f */ - {4,15,rrr,V,S,V}, /* div.w.f */ - {4,16,rrr,V,S,V}, /* div.l.f */ -}; - -const struct formstr e0_format1[] = { - {0,0,0,0,0,0}, - {94,0,a3,0,0,0}, /* tst */ - {95,0,a3,0,0,0}, /* lck */ - {96,0,a3,0,0,0}, /* ulk */ - {17,0,a1r,S,0,0}, /* ldea */ - {97,0,a1r,A,0,0}, /* spawn */ - {98,0,a1r,A,0,0}, /* ldcmr */ - {99,0,a2r,A,0,0}, /* stcmr */ - {100,0,a1r,A,0,0}, /* popr */ - {101,0,a2r,A,0,0}, /* pshr */ - {102,7,a1r,A,0,0}, /* rcvr.w */ - {103,7,a2r,A,0,0}, /* matm.w */ - {104,7,a2r,A,0,0}, /* sndr.w */ - {104,8,a2r,S,0,0}, /* sndr.l */ - {102,8,a1r,S,0,0}, /* rcvr.l */ - {103,8,a2r,S,0,0}, /* matm.l */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {105,7,a2r,A,0,0}, /* putr.w */ - {105,8,a2r,S,0,0}, /* putr.l */ - {106,7,a1r,A,0,0}, /* getr.w */ - {106,8,a1r,S,0,0}, /* getr.l */ - {26,13,a2r,S,0,0}, /* ste.b.f */ - {26,14,a2r,S,0,0}, /* ste.h.f */ - {26,15,a2r,S,0,0}, /* ste.w.f */ - {26,16,a2r,S,0,0}, /* ste.l.f */ - {107,7,a2r,A,0,0}, /* matr.w */ - {108,7,a2r,A,0,0}, /* mat.w */ - {109,7,a1r,A,0,0}, /* get.w */ - {110,7,a1r,A,0,0}, /* rcv.w */ - {0,0,0,0,0,0}, - {111,7,a1r,A,0,0}, /* inc.w */ - {112,7,a2r,A,0,0}, /* put.w */ - {113,7,a2r,A,0,0}, /* snd.w */ - {107,8,a2r,S,0,0}, /* matr.l */ - {108,8,a2r,S,0,0}, /* mat.l */ - {109,8,a1r,S,0,0}, /* get.l */ - {110,8,a1r,S,0,0}, /* rcv.l */ - {0,0,0,0,0,0}, - {111,8,a1r,S,0,0}, /* inc.l */ - {112,8,a2r,S,0,0}, /* put.l */ - {113,8,a2r,S,0,0}, /* snd.l */ - {18,13,a1r,V,0,0}, /* ld.b.f */ - {18,14,a1r,V,0,0}, /* ld.h.f */ - {18,15,a1r,V,0,0}, /* ld.w.f */ - {18,16,a1r,V,0,0}, /* ld.l.f */ - {21,13,a2r,V,0,0}, /* st.b.f */ - {21,14,a2r,V,0,0}, /* st.h.f */ - {21,15,a2r,V,0,0}, /* st.w.f */ - {21,16,a2r,V,0,0}, /* st.l.f */ -}; - -const struct formstr e0_format2[] = { - {28,5,rr,V,V,0}, /* cvtw.b */ - {28,6,rr,V,V,0}, /* cvtw.h */ - {29,7,rr,V,V,0}, /* cvtb.w */ - {30,7,rr,V,V,0}, /* cvth.w */ - {28,13,rr,V,V,0}, /* cvtw.b.f */ - {28,14,rr,V,V,0}, /* cvtw.h.f */ - {29,15,rr,V,V,0}, /* cvtb.w.f */ - {30,15,rr,V,V,0}, /* cvth.w.f */ - {31,8,rr,V,V,0}, /* cvts.l */ - {32,7,rr,V,V,0}, /* cvtd.w */ - {33,3,rr,V,V,0}, /* cvtl.s */ - {28,4,rr,V,V,0}, /* cvtw.d */ - {31,16,rr,V,V,0}, /* cvts.l.f */ - {32,15,rr,V,V,0}, /* cvtd.w.f */ - {33,11,rr,V,V,0}, /* cvtl.s.f */ - {28,12,rr,V,V,0}, /* cvtw.d.f */ - {114,0,rr,S,S,0}, /* enal */ - {8,7,rr,S,S,0}, /* shf.w */ - {115,0,rr,S,S,0}, /* enag */ - {0,0,0,0,0,0}, - {28,4,rr,S,S,0}, /* cvtw.d */ - {32,7,rr,S,S,0}, /* cvtd.w */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,S,S,0}, /* frint.s */ - {116,4,rr,S,S,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,V,V,0}, /* frint.s */ - {116,4,rr,V,V,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,11,rr,V,V,0}, /* frint.s.f */ - {116,12,rr,V,V,0}, /* frint.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,3,rr,V,V,0}, /* sqrt.s */ - {81,4,rr,V,V,0}, /* sqrt.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,11,rr,V,V,0}, /* sqrt.s.f */ - {81,12,rr,V,V,0}, /* sqrt.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format3[] = { - {32,11,rr,V,V,0}, /* cvtd.s.f */ - {31,12,rr,V,V,0}, /* cvts.d.f */ - {33,12,rr,V,V,0}, /* cvtl.d.f */ - {32,16,rr,V,V,0}, /* cvtd.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,2,rr,V,V,0}, /* tzc.f */ - {44,2,rr,V,V,0}, /* lop.f */ - {117,2,rr,V,V,0}, /* xpnd.f */ - {42,2,rr,V,V,0}, /* not.f */ - {8,2,rr,S,V,0}, /* shf.f */ - {35,17,rr,V,V,0}, /* plc.t.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,11,rr,V,V,0}, /* eq.s.f */ - {37,12,rr,V,V,0}, /* eq.d.f */ - {43,11,rr,V,V,0}, /* neg.s.f */ - {43,12,rr,V,V,0}, /* neg.d.f */ - {37,11,rr,S,V,0}, /* eq.s.f */ - {37,12,rr,S,V,0}, /* eq.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,11,rr,V,V,0}, /* le.s.f */ - {40,12,rr,V,V,0}, /* le.d.f */ - {41,11,rr,V,V,0}, /* lt.s.f */ - {41,12,rr,V,V,0}, /* lt.d.f */ - {40,11,rr,S,V,0}, /* le.s.f */ - {40,12,rr,S,V,0}, /* le.d.f */ - {41,11,rr,S,V,0}, /* lt.s.f */ - {41,12,rr,S,V,0}, /* lt.d.f */ - {37,13,rr,V,V,0}, /* eq.b.f */ - {37,14,rr,V,V,0}, /* eq.h.f */ - {37,15,rr,V,V,0}, /* eq.w.f */ - {37,16,rr,V,V,0}, /* eq.l.f */ - {37,13,rr,S,V,0}, /* eq.b.f */ - {37,14,rr,S,V,0}, /* eq.h.f */ - {37,15,rr,S,V,0}, /* eq.w.f */ - {37,16,rr,S,V,0}, /* eq.l.f */ - {40,13,rr,V,V,0}, /* le.b.f */ - {40,14,rr,V,V,0}, /* le.h.f */ - {40,15,rr,V,V,0}, /* le.w.f */ - {40,16,rr,V,V,0}, /* le.l.f */ - {40,13,rr,S,V,0}, /* le.b.f */ - {40,14,rr,S,V,0}, /* le.h.f */ - {40,15,rr,S,V,0}, /* le.w.f */ - {40,16,rr,S,V,0}, /* le.l.f */ - {41,13,rr,V,V,0}, /* lt.b.f */ - {41,14,rr,V,V,0}, /* lt.h.f */ - {41,15,rr,V,V,0}, /* lt.w.f */ - {41,16,rr,V,V,0}, /* lt.l.f */ - {41,13,rr,S,V,0}, /* lt.b.f */ - {41,14,rr,S,V,0}, /* lt.h.f */ - {41,15,rr,S,V,0}, /* lt.w.f */ - {41,16,rr,S,V,0}, /* lt.l.f */ - {43,13,rr,V,V,0}, /* neg.b.f */ - {43,14,rr,V,V,0}, /* neg.h.f */ - {43,15,rr,V,V,0}, /* neg.w.f */ - {43,16,rr,V,V,0}, /* neg.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format5[] = { - {51,13,rr,V,V,0}, /* ldvi.b.f */ - {51,14,rr,V,V,0}, /* ldvi.h.f */ - {51,15,rr,V,V,0}, /* ldvi.w.f */ - {51,16,rr,V,V,0}, /* ldvi.l.f */ - {28,11,rr,V,V,0}, /* cvtw.s.f */ - {31,15,rr,V,V,0}, /* cvts.w.f */ - {28,16,rr,V,V,0}, /* cvtw.l.f */ - {33,15,rr,V,V,0}, /* cvtl.w.f */ - {52,13,rxr,V,V,0}, /* stvi.b.f */ - {52,14,rxr,V,V,0}, /* stvi.h.f */ - {52,15,rxr,V,V,0}, /* stvi.w.f */ - {52,16,rxr,V,V,0}, /* stvi.l.f */ - {52,13,rxr,S,V,0}, /* stvi.b.f */ - {52,14,rxr,S,V,0}, /* stvi.h.f */ - {52,15,rxr,S,V,0}, /* stvi.w.f */ - {52,16,rxr,S,V,0}, /* stvi.l.f */ -}; - -const struct formstr e0_format6[] = { - {0,0,rxl,S,CIR,0}, /* mov */ - {0,0,lr,CIR,S,0}, /* mov */ - {0,0,lr,TOC,S,0}, /* mov */ - {0,0,lr,CPUID,S,0}, /* mov */ - {0,0,rxl,S,TTR,0}, /* mov */ - {0,0,lr,TTR,S,0}, /* mov */ - {118,0,nops,0,0,0}, /* ctrsl */ - {119,0,nops,0,0,0}, /* ctrsg */ - {0,0,rxl,S,VMU,0}, /* mov */ - {0,0,lr,VMU,S,0}, /* mov */ - {0,0,rxl,S,VML,0}, /* mov */ - {0,0,lr,VML,S,0}, /* mov */ - {0,0,rxl,S,ICR,0}, /* mov */ - {0,0,lr,ICR,S,0}, /* mov */ - {0,0,rxl,S,TCPU,0}, /* mov */ - {0,0,lr,TCPU,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {120,0,nops,0,0,0}, /* stop */ - {0,0,0,0,0,0}, - {0,0,rxl,S,TID,0}, /* mov */ - {0,0,lr,TID,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format7[] = { - {84,13,r,V,0,0}, /* sum.b.f */ - {84,14,r,V,0,0}, /* sum.h.f */ - {84,15,r,V,0,0}, /* sum.w.f */ - {84,16,r,V,0,0}, /* sum.l.f */ - {85,2,r,V,0,0}, /* all.f */ - {86,2,r,V,0,0}, /* any.f */ - {87,2,r,V,0,0}, /* parity.f */ - {0,0,0,0,0,0}, - {88,13,r,V,0,0}, /* max.b.f */ - {88,14,r,V,0,0}, /* max.h.f */ - {88,15,r,V,0,0}, /* max.w.f */ - {88,16,r,V,0,0}, /* max.l.f */ - {89,13,r,V,0,0}, /* min.b.f */ - {89,14,r,V,0,0}, /* min.h.f */ - {89,15,r,V,0,0}, /* min.w.f */ - {89,16,r,V,0,0}, /* min.l.f */ - {84,11,r,V,0,0}, /* sum.s.f */ - {84,12,r,V,0,0}, /* sum.d.f */ - {90,11,r,V,0,0}, /* prod.s.f */ - {90,12,r,V,0,0}, /* prod.d.f */ - {88,11,r,V,0,0}, /* max.s.f */ - {88,12,r,V,0,0}, /* max.d.f */ - {89,11,r,V,0,0}, /* min.s.f */ - {89,12,r,V,0,0}, /* min.d.f */ - {90,13,r,V,0,0}, /* prod.b.f */ - {90,14,r,V,0,0}, /* prod.h.f */ - {90,15,r,V,0,0}, /* prod.w.f */ - {90,16,r,V,0,0}, /* prod.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format0[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {10,18,rrr,S,V,V}, /* sub.s.t */ - {10,19,rrr,S,V,V}, /* sub.d.t */ - {4,18,rrr,S,V,V}, /* div.s.t */ - {4,19,rrr,S,V,V}, /* div.d.t */ - {3,18,rrr,V,V,V}, /* mul.s.t */ - {3,19,rrr,V,V,V}, /* mul.d.t */ - {4,18,rrr,V,V,V}, /* div.s.t */ - {4,19,rrr,V,V,V}, /* div.d.t */ - {3,18,rrr,V,S,V}, /* mul.s.t */ - {3,19,rrr,V,S,V}, /* mul.d.t */ - {4,18,rrr,V,S,V}, /* div.s.t */ - {4,19,rrr,V,S,V}, /* div.d.t */ - {5,1,rrr,V,V,V}, /* and.t */ - {6,1,rrr,V,V,V}, /* or.t */ - {7,1,rrr,V,V,V}, /* xor.t */ - {8,1,rrr,V,V,V}, /* shf.t */ - {5,1,rrr,V,S,V}, /* and.t */ - {6,1,rrr,V,S,V}, /* or.t */ - {7,1,rrr,V,S,V}, /* xor.t */ - {8,1,rrr,V,S,V}, /* shf.t */ - {9,18,rrr,V,V,V}, /* add.s.t */ - {9,19,rrr,V,V,V}, /* add.d.t */ - {10,18,rrr,V,V,V}, /* sub.s.t */ - {10,19,rrr,V,V,V}, /* sub.d.t */ - {9,18,rrr,V,S,V}, /* add.s.t */ - {9,19,rrr,V,S,V}, /* add.d.t */ - {10,18,rrr,V,S,V}, /* sub.s.t */ - {10,19,rrr,V,S,V}, /* sub.d.t */ - {9,20,rrr,V,V,V}, /* add.b.t */ - {9,21,rrr,V,V,V}, /* add.h.t */ - {9,22,rrr,V,V,V}, /* add.w.t */ - {9,23,rrr,V,V,V}, /* add.l.t */ - {9,20,rrr,V,S,V}, /* add.b.t */ - {9,21,rrr,V,S,V}, /* add.h.t */ - {9,22,rrr,V,S,V}, /* add.w.t */ - {9,23,rrr,V,S,V}, /* add.l.t */ - {10,20,rrr,V,V,V}, /* sub.b.t */ - {10,21,rrr,V,V,V}, /* sub.h.t */ - {10,22,rrr,V,V,V}, /* sub.w.t */ - {10,23,rrr,V,V,V}, /* sub.l.t */ - {10,20,rrr,V,S,V}, /* sub.b.t */ - {10,21,rrr,V,S,V}, /* sub.h.t */ - {10,22,rrr,V,S,V}, /* sub.w.t */ - {10,23,rrr,V,S,V}, /* sub.l.t */ - {3,20,rrr,V,V,V}, /* mul.b.t */ - {3,21,rrr,V,V,V}, /* mul.h.t */ - {3,22,rrr,V,V,V}, /* mul.w.t */ - {3,23,rrr,V,V,V}, /* mul.l.t */ - {3,20,rrr,V,S,V}, /* mul.b.t */ - {3,21,rrr,V,S,V}, /* mul.h.t */ - {3,22,rrr,V,S,V}, /* mul.w.t */ - {3,23,rrr,V,S,V}, /* mul.l.t */ - {4,20,rrr,V,V,V}, /* div.b.t */ - {4,21,rrr,V,V,V}, /* div.h.t */ - {4,22,rrr,V,V,V}, /* div.w.t */ - {4,23,rrr,V,V,V}, /* div.l.t */ - {4,20,rrr,V,S,V}, /* div.b.t */ - {4,21,rrr,V,S,V}, /* div.h.t */ - {4,22,rrr,V,S,V}, /* div.w.t */ - {4,23,rrr,V,S,V}, /* div.l.t */ -}; - -const struct formstr e1_format1[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {26,20,a2r,S,0,0}, /* ste.b.t */ - {26,21,a2r,S,0,0}, /* ste.h.t */ - {26,22,a2r,S,0,0}, /* ste.w.t */ - {26,23,a2r,S,0,0}, /* ste.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {18,20,a1r,V,0,0}, /* ld.b.t */ - {18,21,a1r,V,0,0}, /* ld.h.t */ - {18,22,a1r,V,0,0}, /* ld.w.t */ - {18,23,a1r,V,0,0}, /* ld.l.t */ - {21,20,a2r,V,0,0}, /* st.b.t */ - {21,21,a2r,V,0,0}, /* st.h.t */ - {21,22,a2r,V,0,0}, /* st.w.t */ - {21,23,a2r,V,0,0}, /* st.l.t */ -}; - -const struct formstr e1_format2[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {28,20,rr,V,V,0}, /* cvtw.b.t */ - {28,21,rr,V,V,0}, /* cvtw.h.t */ - {29,22,rr,V,V,0}, /* cvtb.w.t */ - {30,22,rr,V,V,0}, /* cvth.w.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {31,23,rr,V,V,0}, /* cvts.l.t */ - {32,22,rr,V,V,0}, /* cvtd.w.t */ - {33,18,rr,V,V,0}, /* cvtl.s.t */ - {28,19,rr,V,V,0}, /* cvtw.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,18,rr,V,V,0}, /* frint.s.t */ - {116,19,rr,V,V,0}, /* frint.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,18,rr,V,V,0}, /* sqrt.s.t */ - {81,19,rr,V,V,0}, /* sqrt.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format3[] = { - {32,18,rr,V,V,0}, /* cvtd.s.t */ - {31,19,rr,V,V,0}, /* cvts.d.t */ - {33,19,rr,V,V,0}, /* cvtl.d.t */ - {32,23,rr,V,V,0}, /* cvtd.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,1,rr,V,V,0}, /* tzc.t */ - {44,1,rr,V,V,0}, /* lop.t */ - {117,1,rr,V,V,0}, /* xpnd.t */ - {42,1,rr,V,V,0}, /* not.t */ - {8,1,rr,S,V,0}, /* shf.t */ - {35,24,rr,V,V,0}, /* plc.t.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,18,rr,V,V,0}, /* eq.s.t */ - {37,19,rr,V,V,0}, /* eq.d.t */ - {43,18,rr,V,V,0}, /* neg.s.t */ - {43,19,rr,V,V,0}, /* neg.d.t */ - {37,18,rr,S,V,0}, /* eq.s.t */ - {37,19,rr,S,V,0}, /* eq.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,18,rr,V,V,0}, /* le.s.t */ - {40,19,rr,V,V,0}, /* le.d.t */ - {41,18,rr,V,V,0}, /* lt.s.t */ - {41,19,rr,V,V,0}, /* lt.d.t */ - {40,18,rr,S,V,0}, /* le.s.t */ - {40,19,rr,S,V,0}, /* le.d.t */ - {41,18,rr,S,V,0}, /* lt.s.t */ - {41,19,rr,S,V,0}, /* lt.d.t */ - {37,20,rr,V,V,0}, /* eq.b.t */ - {37,21,rr,V,V,0}, /* eq.h.t */ - {37,22,rr,V,V,0}, /* eq.w.t */ - {37,23,rr,V,V,0}, /* eq.l.t */ - {37,20,rr,S,V,0}, /* eq.b.t */ - {37,21,rr,S,V,0}, /* eq.h.t */ - {37,22,rr,S,V,0}, /* eq.w.t */ - {37,23,rr,S,V,0}, /* eq.l.t */ - {40,20,rr,V,V,0}, /* le.b.t */ - {40,21,rr,V,V,0}, /* le.h.t */ - {40,22,rr,V,V,0}, /* le.w.t */ - {40,23,rr,V,V,0}, /* le.l.t */ - {40,20,rr,S,V,0}, /* le.b.t */ - {40,21,rr,S,V,0}, /* le.h.t */ - {40,22,rr,S,V,0}, /* le.w.t */ - {40,23,rr,S,V,0}, /* le.l.t */ - {41,20,rr,V,V,0}, /* lt.b.t */ - {41,21,rr,V,V,0}, /* lt.h.t */ - {41,22,rr,V,V,0}, /* lt.w.t */ - {41,23,rr,V,V,0}, /* lt.l.t */ - {41,20,rr,S,V,0}, /* lt.b.t */ - {41,21,rr,S,V,0}, /* lt.h.t */ - {41,22,rr,S,V,0}, /* lt.w.t */ - {41,23,rr,S,V,0}, /* lt.l.t */ - {43,20,rr,V,V,0}, /* neg.b.t */ - {43,21,rr,V,V,0}, /* neg.h.t */ - {43,22,rr,V,V,0}, /* neg.w.t */ - {43,23,rr,V,V,0}, /* neg.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format5[] = { - {51,20,rr,V,V,0}, /* ldvi.b.t */ - {51,21,rr,V,V,0}, /* ldvi.h.t */ - {51,22,rr,V,V,0}, /* ldvi.w.t */ - {51,23,rr,V,V,0}, /* ldvi.l.t */ - {28,18,rr,V,V,0}, /* cvtw.s.t */ - {31,22,rr,V,V,0}, /* cvts.w.t */ - {28,23,rr,V,V,0}, /* cvtw.l.t */ - {33,22,rr,V,V,0}, /* cvtl.w.t */ - {52,20,rxr,V,V,0}, /* stvi.b.t */ - {52,21,rxr,V,V,0}, /* stvi.h.t */ - {52,22,rxr,V,V,0}, /* stvi.w.t */ - {52,23,rxr,V,V,0}, /* stvi.l.t */ - {52,20,rxr,S,V,0}, /* stvi.b.t */ - {52,21,rxr,S,V,0}, /* stvi.h.t */ - {52,22,rxr,S,V,0}, /* stvi.w.t */ - {52,23,rxr,S,V,0}, /* stvi.l.t */ -}; - -const struct formstr e1_format6[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format7[] = { - {84,20,r,V,0,0}, /* sum.b.t */ - {84,21,r,V,0,0}, /* sum.h.t */ - {84,22,r,V,0,0}, /* sum.w.t */ - {84,23,r,V,0,0}, /* sum.l.t */ - {85,1,r,V,0,0}, /* all.t */ - {86,1,r,V,0,0}, /* any.t */ - {87,1,r,V,0,0}, /* parity.t */ - {0,0,0,0,0,0}, - {88,20,r,V,0,0}, /* max.b.t */ - {88,21,r,V,0,0}, /* max.h.t */ - {88,22,r,V,0,0}, /* max.w.t */ - {88,23,r,V,0,0}, /* max.l.t */ - {89,20,r,V,0,0}, /* min.b.t */ - {89,21,r,V,0,0}, /* min.h.t */ - {89,22,r,V,0,0}, /* min.w.t */ - {89,23,r,V,0,0}, /* min.l.t */ - {84,18,r,V,0,0}, /* sum.s.t */ - {84,19,r,V,0,0}, /* sum.d.t */ - {90,18,r,V,0,0}, /* prod.s.t */ - {90,19,r,V,0,0}, /* prod.d.t */ - {88,18,r,V,0,0}, /* max.s.t */ - {88,19,r,V,0,0}, /* max.d.t */ - {89,18,r,V,0,0}, /* min.s.t */ - {89,19,r,V,0,0}, /* min.d.t */ - {90,20,r,V,0,0}, /* prod.b.t */ - {90,21,r,V,0,0}, /* prod.h.t */ - {90,22,r,V,0,0}, /* prod.w.t */ - {90,23,r,V,0,0}, /* prod.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -char *lop[] = { - "mov", /* 0 */ - "merg", /* 1 */ - "mask", /* 2 */ - "mul", /* 3 */ - "div", /* 4 */ - "and", /* 5 */ - "or", /* 6 */ - "xor", /* 7 */ - "shf", /* 8 */ - "add", /* 9 */ - "sub", /* 10 */ - "exit", /* 11 */ - "jmp", /* 12 */ - "jmpi", /* 13 */ - "jmpa", /* 14 */ - "jmps", /* 15 */ - "tac", /* 16 */ - "ldea", /* 17 */ - "ld", /* 18 */ - "tas", /* 19 */ - "pshea", /* 20 */ - "st", /* 21 */ - "call", /* 22 */ - "calls", /* 23 */ - "callq", /* 24 */ - "pfork", /* 25 */ - "ste", /* 26 */ - "incr", /* 27 */ - "cvtw", /* 28 */ - "cvtb", /* 29 */ - "cvth", /* 30 */ - "cvts", /* 31 */ - "cvtd", /* 32 */ - "cvtl", /* 33 */ - "ldpa", /* 34 */ - "plc", /* 35 */ - "tzc", /* 36 */ - "eq", /* 37 */ - "leu", /* 38 */ - "ltu", /* 39 */ - "le", /* 40 */ - "lt", /* 41 */ - "not", /* 42 */ - "neg", /* 43 */ - "lop", /* 44 */ - "cprs", /* 45 */ - "nop", /* 46 */ - "br", /* 47 */ - "bri", /* 48 */ - "bra", /* 49 */ - "brs", /* 50 */ - "ldvi", /* 51 */ - "stvi", /* 52 */ - "ldsdr", /* 53 */ - "ldkdr", /* 54 */ - "ln", /* 55 */ - "patu", /* 56 */ - "pate", /* 57 */ - "pich", /* 58 */ - "plch", /* 59 */ - "idle", /* 60 */ - "rtnq", /* 61 */ - "cfork", /* 62 */ - "rtn", /* 63 */ - "wfork", /* 64 */ - "join", /* 65 */ - "rtnc", /* 66 */ - "exp", /* 67 */ - "sin", /* 68 */ - "cos", /* 69 */ - "psh", /* 70 */ - "pop", /* 71 */ - "eni", /* 72 */ - "dsi", /* 73 */ - "bkpt", /* 74 */ - "msync", /* 75 */ - "mski", /* 76 */ - "xmti", /* 77 */ - "tstvv", /* 78 */ - "diag", /* 79 */ - "pbkpt", /* 80 */ - "sqrt", /* 81 */ - "casr", /* 82 */ - "atan", /* 83 */ - "sum", /* 84 */ - "all", /* 85 */ - "any", /* 86 */ - "parity", /* 87 */ - "max", /* 88 */ - "min", /* 89 */ - "prod", /* 90 */ - "halt", /* 91 */ - "sysc", /* 92 */ - "trap", /* 93 */ - "tst", /* 94 */ - "lck", /* 95 */ - "ulk", /* 96 */ - "spawn", /* 97 */ - "ldcmr", /* 98 */ - "stcmr", /* 99 */ - "popr", /* 100 */ - "pshr", /* 101 */ - "rcvr", /* 102 */ - "matm", /* 103 */ - "sndr", /* 104 */ - "putr", /* 105 */ - "getr", /* 106 */ - "matr", /* 107 */ - "mat", /* 108 */ - "get", /* 109 */ - "rcv", /* 110 */ - "inc", /* 111 */ - "put", /* 112 */ - "snd", /* 113 */ - "enal", /* 114 */ - "enag", /* 115 */ - "frint", /* 116 */ - "xpnd", /* 117 */ - "ctrsl", /* 118 */ - "ctrsg", /* 119 */ - "stop", /* 120 */ -}; - -char *rop[] = { - "", /* 0 */ - ".t", /* 1 */ - ".f", /* 2 */ - ".s", /* 3 */ - ".d", /* 4 */ - ".b", /* 5 */ - ".h", /* 6 */ - ".w", /* 7 */ - ".l", /* 8 */ - ".x", /* 9 */ - ".u", /* 10 */ - ".s.f", /* 11 */ - ".d.f", /* 12 */ - ".b.f", /* 13 */ - ".h.f", /* 14 */ - ".w.f", /* 15 */ - ".l.f", /* 16 */ - ".t.f", /* 17 */ - ".s.t", /* 18 */ - ".d.t", /* 19 */ - ".b.t", /* 20 */ - ".h.t", /* 21 */ - ".w.t", /* 22 */ - ".l.t", /* 23 */ - ".t.t", /* 24 */ -}; diff --git a/contrib/binutils/include/opcode/cr16.h b/contrib/binutils/include/opcode/cr16.h deleted file mode 100644 index b7e3be554fcdc..0000000000000 --- a/contrib/binutils/include/opcode/cr16.h +++ /dev/null @@ -1,437 +0,0 @@ -/* cr16.h -- Header file for CR16 opcode and register tables. - Copyright 2007 Free Software Foundation, Inc. - Contributed by M R Swami Reddy - - This file is part of GAS, GDB and the GNU binutils. - - GAS, GDB, and GNU binutils is free software; you can redistribute it - and/or modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 2, or (at your - option) any later version. - - GAS, GDB, and GNU binutils are distributed in the hope that they will be - useful, but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _CR16_H_ -#define _CR16_H_ - -/* CR16 core Registers : - The enums are used as indices to CR16 registers table (cr16_regtab). - Therefore, order MUST be preserved. */ - -typedef enum - { - /* 16-bit general purpose registers. */ - r0, r1, r2, r3, - r4, r5, r6, r7, - r8, r9, r10, r11, - r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, - - /* 32-bit general purpose registers. */ - r12 = 12, r13 = 13, r14 = 14, r15 = 15, - era = 14, sp = 15, RA, - - /* Not a register. */ - nullregister, - MAX_REG - } -reg; - -/* CR16 processor registers and special registers : - The enums are used as indices to CR16 processor registers table - (cr16_pregtab). Therefore, order MUST be preserved. */ - -typedef enum - { - /* processor registers. */ - dbs = MAX_REG, - dsr, dcrl, dcrh, - car0l, car0h, car1l, car1h, - cfg, psr, intbasel, intbaseh, - ispl, isph, uspl, usph, - dcr = dcrl, - car0 = car0l, - car1 = car1l, - intbase = intbasel, - isp = ispl, - usp = uspl, - /* Not a processor register. */ - nullpregister = usph + 1, - MAX_PREG - } -preg; - -/* CR16 Register types. */ - -typedef enum - { - CR16_R_REGTYPE, /* r<N> */ - CR16_RP_REGTYPE, /* reg pair */ - CR16_P_REGTYPE /* Processor register */ - } -reg_type; - -/* CR16 argument types : - The argument types correspond to instructions operands - - Argument types : - r - register - rp - register pair - c - constant - i - immediate - idxr - index with register - idxrp - index with register pair - rbase - register base - rpbase - register pair base - pr - processor register */ - -typedef enum - { - arg_r, - arg_c, - arg_cr, - arg_crp, - arg_ic, - arg_icr, - arg_idxr, - arg_idxrp, - arg_rbase, - arg_rpbase, - arg_rp, - arg_pr, - arg_prp, - arg_cc, - arg_ra, - /* Not an argument. */ - nullargs - } -argtype; - -/* CR16 operand types:The operand types correspond to instructions operands.*/ - -typedef enum - { - dummy, - /* N-bit signed immediate. */ - imm3, imm4, imm5, imm6, imm16, imm20, imm32, - /* N-bit unsigned immediate. */ - uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, - /* N-bit signed displacement. */ - disps5, disps17, disps25, - /* N-bit unsigned displacement. */ - dispe9, - /* N-bit absolute address. */ - abs20, abs24, - /* Register relative. */ - rra, rbase, rbase_disps20, rbase_dispe20, - /* Register pair relative. */ - rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, - rpbase_disps20, rpbase_dispe20, - /* Register index. */ - rindex7_abs20, rindex8_abs20, - /* Register pair index. */ - rpindex_disps0, rpindex_disps14, rpindex_disps20, - /* register. */ - regr, - /* register pair. */ - regp, - /* processor register. */ - pregr, - /* processor register 32 bit. */ - pregrp, - /* condition code - 4 bit. */ - cc, - /* Not an operand. */ - nulloperand, - /* Maximum supported operand. */ - MAX_OPRD - } -operand_type; - -/* CR16 instruction types. */ - -#define NO_TYPE_INS 0 -#define ARITH_INS 1 -#define LD_STOR_INS 2 -#define BRANCH_INS 3 -#define ARITH_BYTE_INS 4 -#define SHIFT_INS 5 -#define BRANCH_NEQ_INS 6 -#define LD_STOR_INS_INC 7 -#define STOR_IMM_INS 8 -#define CSTBIT_INS 9 - -/* Maximum value supported for instruction types. */ -#define CR16_INS_MAX (1 << 4) -/* Mask to record an instruction type. */ -#define CR16_INS_MASK (CR16_INS_MAX - 1) -/* Return instruction type, given instruction's attributes. */ -#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) - -/* Indicates whether this instruction has a register list as parameter. */ -#define REG_LIST CR16_INS_MAX - -/* The operands in binary and assembly are placed in reverse order. - load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ -#define REVERSE_MATCH (1 << 5) - -/* Printing formats, where the instruction prefix isn't consecutive. */ -#define FMT_1 (1 << 9) /* 0xF0F00000 */ -#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ -#define FMT_3 (1 << 11) /* 0xFFF00F00 */ -#define FMT_4 (1 << 12) /* 0xFFF0F000 */ -#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ -#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) - -/* Indicates whether this instruction can be relaxed. */ -#define RELAXABLE (1 << 14) - -/* Indicates that instruction uses user registers (and not - general-purpose registers) as operands. */ -#define USER_REG (1 << 15) - - -/* Instruction shouldn't allow 'sp' usage. */ -#define NO_SP (1 << 17) - -/* Instruction shouldn't allow to push a register which is used as a rptr. */ -#define NO_RPTR (1 << 18) - -/* Maximum operands per instruction. */ -#define MAX_OPERANDS 5 -/* Maximum register name length. */ -#define MAX_REGNAME_LEN 10 -/* Maximum instruction length. */ -#define MAX_INST_LEN 256 - - -/* Values defined for the flags field of a struct operand_entry. */ - -/* Operand must be an unsigned number. */ -#define OP_UNSIGNED (1 << 0) -/* Operand must be a signed number. */ -#define OP_SIGNED (1 << 1) -/* Operand must be a negative number. */ -#define OP_NEG (1 << 2) -/* A special load/stor 4-bit unsigned displacement operand. */ -#define OP_DEC (1 << 3) -/* Operand must be an even number. */ -#define OP_EVEN (1 << 4) -/* Operand is shifted right. */ -#define OP_SHIFT (1 << 5) -/* Operand is shifted right and decremented. */ -#define OP_SHIFT_DEC (1 << 6) -/* Operand has reserved escape sequences. */ -#define OP_ESC (1 << 7) -/* Operand must be a ABS20 number. */ -#define OP_ABS20 (1 << 8) -/* Operand must be a ABS24 number. */ -#define OP_ABS24 (1 << 9) -/* Operand has reserved escape sequences type 1. */ -#define OP_ESC1 (1 << 10) - -/* Single operand description. */ - -typedef struct - { - /* Operand type. */ - operand_type op_type; - /* Operand location within the opcode. */ - unsigned int shift; - } -operand_desc; - -/* Instruction data structure used in instruction table. */ - -typedef struct - { - /* Name. */ - const char *mnemonic; - /* Size (in words). */ - unsigned int size; - /* Constant prefix (matched by the disassembler). */ - unsigned long match; /* ie opcode */ - /* Match size (in bits). */ - /* MASK: if( (i & match_bits) == match ) then match */ - int match_bits; - /* Attributes. */ - unsigned int flags; - /* Operands (always last, so unreferenced operands are initialized). */ - operand_desc operands[MAX_OPERANDS]; - } -inst; - -/* Data structure for a single instruction's arguments (Operands). */ - -typedef struct - { - /* Register or base register. */ - reg r; - /* Register pair register. */ - reg rp; - /* Index register. */ - reg i_r; - /* Processor register. */ - preg pr; - /* Processor register. 32 bit */ - preg prp; - /* Constant/immediate/absolute value. */ - long constant; - /* CC code. */ - unsigned int cc; - /* Scaled index mode. */ - unsigned int scale; - /* Argument type. */ - argtype type; - /* Size of the argument (in bits) required to represent. */ - int size; - /* The type of the expression. */ - unsigned char X_op; - } -argument; - -/* Internal structure to hold the various entities - corresponding to the current assembling instruction. */ - -typedef struct - { - /* Number of arguments. */ - int nargs; - /* The argument data structure for storing args (operands). */ - argument arg[MAX_OPERANDS]; -/* The following fields are required only by CR16-assembler. */ -#ifdef TC_CR16 - /* Expression used for setting the fixups (if any). */ - expressionS exp; - bfd_reloc_code_real_type rtype; -#endif /* TC_CR16 */ - /* Instruction size (in bytes). */ - int size; - } -ins; - -/* Structure to hold information about predefined operands. */ - -typedef struct - { - /* Size (in bits). */ - unsigned int bit_size; - /* Argument type. */ - argtype arg_type; - /* One bit syntax flags. */ - int flags; - } -operand_entry; - -/* Structure to hold trap handler information. */ - -typedef struct - { - /* Trap name. */ - char *name; - /* Index in dispatch table. */ - unsigned int entry; - } -trap_entry; - -/* Structure to hold information about predefined registers. */ - -typedef struct - { - /* Name (string representation). */ - char *name; - /* Value (enum representation). */ - union - { - /* Register. */ - reg reg_val; - /* processor register. */ - preg preg_val; - } value; - /* Register image. */ - int image; - /* Register type. */ - reg_type type; - } -reg_entry; - -/* CR16 opcode table. */ -extern const inst cr16_instruction[]; -extern const unsigned int cr16_num_opcodes; -#define NUMOPCODES cr16_num_opcodes - -/* CR16 operands table. */ -extern const operand_entry cr16_optab[]; - -/* CR16 registers table. */ -extern const reg_entry cr16_regtab[]; -extern const unsigned int cr16_num_regs; -#define NUMREGS cr16_num_regs - -/* CR16 register pair table. */ -extern const reg_entry cr16_regptab[]; -extern const unsigned int cr16_num_regps; -#define NUMREGPS cr16_num_regps - -/* CR16 processor registers table. */ -extern const reg_entry cr16_pregtab[]; -extern const unsigned int cr16_num_pregs; -#define NUMPREGS cr16_num_pregs - -/* CR16 processor registers - 32 bit table. */ -extern const reg_entry cr16_pregptab[]; -extern const unsigned int cr16_num_pregps; -#define NUMPREGPS cr16_num_pregps - -/* CR16 trap/interrupt table. */ -extern const trap_entry cr16_traps[]; -extern const unsigned int cr16_num_traps; -#define NUMTRAPS cr16_num_traps - -/* CR16 CC - codes bit table. */ -extern const char * cr16_b_cond_tab[]; -extern const unsigned int cr16_num_cc; -#define NUMCC cr16_num_cc; - - -/* Table of instructions with no operands. */ -extern const char * cr16_no_op_insn[]; - -/* Current instruction we're assembling. */ -extern const inst *instruction; - -/* A macro for representing the instruction "constant" opcode, that is, - the FIXED part of the instruction. The "constant" opcode is represented - as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) - over that range. */ -#define BIN(OPC,SHIFT) (OPC << SHIFT) - -/* Is the current instruction type is TYPE ? */ -#define IS_INSN_TYPE(TYPE) \ - (CR16_INS_TYPE (instruction->flags) == TYPE) - -/* Is the current instruction mnemonic is MNEMONIC ? */ -#define IS_INSN_MNEMONIC(MNEMONIC) \ - (strcmp (instruction->mnemonic, MNEMONIC) == 0) - -/* Does the current instruction has register list ? */ -#define INST_HAS_REG_LIST \ - (instruction->flags & REG_LIST) - - -/* Utility macros for string comparison. */ -#define streq(a, b) (strcmp (a, b) == 0) -#define strneq(a, b, c) (strncmp (a, b, c) == 0) - -/* Long long type handling. */ -/* Replace all appearances of 'long long int' with LONGLONG. */ -typedef long long int LONGLONG; -typedef unsigned long long ULONGLONG; - -#endif /* _CR16_H_ */ diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h deleted file mode 100644 index 4fe769a58bfcf..0000000000000 --- a/contrib/binutils/include/opcode/i386.h +++ /dev/null @@ -1,115 +0,0 @@ -/* opcode/i386.h -- Intel 80386 opcode macros - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 - Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived - ix86 Unix assemblers, generate floating point instructions with - reversed source and destination registers in certain cases. - Unfortunately, gcc and possibly many other programs use this - reversed syntax, so we're stuck with it. - - eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but - `fsub %st,%st(3)' results in st(3) = st - st(3), rather than - the expected st(3) = st(3) - st - - This happens with all the non-commutative arithmetic floating point - operations with two register operands, where the source register is - %st, and destination register is %st(i). - - The affected opcode map is dceX, dcfX, deeX, defX. */ - -#ifndef SYSV386_COMPAT -/* Set non-zero for broken, compatible instructions. Set to zero for - non-broken opcodes at your peril. gcc generates SystemV/386 - compatible instructions. */ -#define SYSV386_COMPAT 1 -#endif -#ifndef OLDGCC_COMPAT -/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could - generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands - reversed. */ -#define OLDGCC_COMPAT SYSV386_COMPAT -#endif - -#define MOV_AX_DISP32 0xa0 -#define POP_SEG_SHORT 0x07 -#define JUMP_PC_RELATIVE 0xeb -#define INT_OPCODE 0xcd -#define INT3_OPCODE 0xcc -/* The opcode for the fwait instruction, which disassembler treats as a - prefix when it can. */ -#define FWAIT_OPCODE 0x9b -#define ADDR_PREFIX_OPCODE 0x67 -#define DATA_PREFIX_OPCODE 0x66 -#define LOCK_PREFIX_OPCODE 0xf0 -#define CS_PREFIX_OPCODE 0x2e -#define DS_PREFIX_OPCODE 0x3e -#define ES_PREFIX_OPCODE 0x26 -#define FS_PREFIX_OPCODE 0x64 -#define GS_PREFIX_OPCODE 0x65 -#define SS_PREFIX_OPCODE 0x36 -#define REPNE_PREFIX_OPCODE 0xf2 -#define REPE_PREFIX_OPCODE 0xf3 - -#define TWO_BYTE_OPCODE_ESCAPE 0x0f -#define NOP_OPCODE (char) 0x90 - -/* register numbers */ -#define EBP_REG_NUM 5 -#define ESP_REG_NUM 4 - -/* modrm_byte.regmem for twobyte escape */ -#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM -/* index_base_byte.index for no index register addressing */ -#define NO_INDEX_REGISTER ESP_REG_NUM -/* index_base_byte.base for no base register addressing */ -#define NO_BASE_REGISTER EBP_REG_NUM -#define NO_BASE_REGISTER_16 6 - -/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ -#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ -#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) - -/* x86-64 extension prefix. */ -#define REX_OPCODE 0x40 - -/* Indicates 64 bit operand size. */ -#define REX_W 8 -/* High extension to reg field of modrm byte. */ -#define REX_R 4 -/* High extension to SIB index field. */ -#define REX_X 2 -/* High extension to base field of modrm or SIB, or reg field of opcode. */ -#define REX_B 1 - -/* max operands per insn */ -#define MAX_OPERANDS 4 - -/* max immediates per insn (lcall, ljmp, insertq, extrq) */ -#define MAX_IMMEDIATE_OPERANDS 2 - -/* max memory refs per insn (string ops) */ -#define MAX_MEMORY_OPERANDS 2 - -/* max size of insn mnemonics. */ -#define MAX_MNEM_SIZE 16 - -/* max size of register name in insn mnemonics. */ -#define MAX_REG_NAME_SIZE 8 diff --git a/contrib/binutils/include/opcode/ia64.h b/contrib/binutils/include/opcode/ia64.h deleted file mode 100644 index 447e50e1dbf7e..0000000000000 --- a/contrib/binutils/include/opcode/ia64.h +++ /dev/null @@ -1,396 +0,0 @@ -/* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2000, 2002, 2005, 2006 - Free Software Foundation, Inc. - Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ - -#ifndef opcode_ia64_h -#define opcode_ia64_h - -#include <sys/types.h> - -#include "bfd.h" - - -typedef BFD_HOST_U_64_BIT ia64_insn; - -enum ia64_insn_type - { - IA64_TYPE_NIL = 0, /* illegal type */ - IA64_TYPE_A, /* integer alu (I- or M-unit) */ - IA64_TYPE_I, /* non-alu integer (I-unit) */ - IA64_TYPE_M, /* memory (M-unit) */ - IA64_TYPE_B, /* branch (B-unit) */ - IA64_TYPE_F, /* floating-point (F-unit) */ - IA64_TYPE_X, /* long encoding (X-unit) */ - IA64_TYPE_DYN, /* Dynamic opcode */ - IA64_NUM_TYPES - }; - -enum ia64_unit - { - IA64_UNIT_NIL = 0, /* illegal unit */ - IA64_UNIT_I, /* integer unit */ - IA64_UNIT_M, /* memory unit */ - IA64_UNIT_B, /* branching unit */ - IA64_UNIT_F, /* floating-point unit */ - IA64_UNIT_L, /* long "unit" */ - IA64_UNIT_X, /* may be integer or branch unit */ - IA64_NUM_UNITS - }; - -/* Changes to this enumeration must be propagated to the operand table in - bfd/cpu-ia64-opc.c - */ -enum ia64_opnd - { - IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ - - /* constants */ - IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ - IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ - IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ - IA64_OPND_C1, /* the constant 1 */ - IA64_OPND_C8, /* the constant 8 */ - IA64_OPND_C16, /* the constant 16 */ - IA64_OPND_GR0, /* gr0 */ - IA64_OPND_IP, /* instruction pointer (ip) */ - IA64_OPND_PR, /* predicate register (pr) */ - IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ - IA64_OPND_PSR, /* processor status register (psr) */ - IA64_OPND_PSR_L, /* processor status register L (psr.l) */ - IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ - - /* register operands: */ - IA64_OPND_AR3, /* third application register # (bits 20-26) */ - IA64_OPND_B1, /* branch register # (bits 6-8) */ - IA64_OPND_B2, /* branch register # (bits 13-15) */ - IA64_OPND_CR3, /* third control register # (bits 20-26) */ - IA64_OPND_F1, /* first floating-point register # */ - IA64_OPND_F2, /* second floating-point register # */ - IA64_OPND_F3, /* third floating-point register # */ - IA64_OPND_F4, /* fourth floating-point register # */ - IA64_OPND_P1, /* first predicate # */ - IA64_OPND_P2, /* second predicate # */ - IA64_OPND_R1, /* first register # */ - IA64_OPND_R2, /* second register # */ - IA64_OPND_R3, /* third register # */ - IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ - - /* memory operands: */ - IA64_OPND_MR3, /* memory at addr of third register # */ - - /* indirect operands: */ - IA64_OPND_CPUID_R3, /* cpuid[reg] */ - IA64_OPND_DBR_R3, /* dbr[reg] */ - IA64_OPND_DTR_R3, /* dtr[reg] */ - IA64_OPND_ITR_R3, /* itr[reg] */ - IA64_OPND_IBR_R3, /* ibr[reg] */ - IA64_OPND_MSR_R3, /* msr[reg] */ - IA64_OPND_PKR_R3, /* pkr[reg] */ - IA64_OPND_PMC_R3, /* pmc[reg] */ - IA64_OPND_PMD_R3, /* pmd[reg] */ - IA64_OPND_RR_R3, /* rr[reg] */ - - /* immediate operands: */ - IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ - IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ - IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ - IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ - IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ - IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ - IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ - IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ - IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ - IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ - IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ - IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ - IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ - IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ - IA64_OPND_SOF, /* 8-bit stack frame size */ - IA64_OPND_SOL, /* 8-bit size of locals */ - IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ - IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ - IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ - IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ - IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ - IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ - IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ - IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ - IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ - IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ - IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ - IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ - IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ - IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ - IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ - IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ - IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ - IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ - IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ - IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ - IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ - IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ - IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ - IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ - IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ - IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ - IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ - IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ - - IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ - }; - -enum ia64_dependency_mode -{ - IA64_DV_RAW, - IA64_DV_WAW, - IA64_DV_WAR, -}; - -enum ia64_dependency_semantics -{ - IA64_DVS_NONE, - IA64_DVS_IMPLIED, - IA64_DVS_IMPLIEDF, - IA64_DVS_DATA, - IA64_DVS_INSTR, - IA64_DVS_SPECIFIC, - IA64_DVS_STOP, - IA64_DVS_OTHER, -}; - -enum ia64_resource_specifier -{ - IA64_RS_ANY, - IA64_RS_AR_K, - IA64_RS_AR_UNAT, - IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ - IA64_RS_ARb, /* 48-63, 112-127 */ - IA64_RS_BR, - IA64_RS_CFM, - IA64_RS_CPUID, - IA64_RS_CR_IRR, - IA64_RS_CR_LRR, - IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */ - IA64_RS_DBR, - IA64_RS_FR, - IA64_RS_FRb, - IA64_RS_GR0, - IA64_RS_GR, - IA64_RS_IBR, - IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ - IA64_RS_MSR, - IA64_RS_PKR, - IA64_RS_PMC, - IA64_RS_PMD, - IA64_RS_PR, /* non-rotating, 1-15 */ - IA64_RS_PRr, /* rotating, 16-62 */ - IA64_RS_PR63, - IA64_RS_RR, - - IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ - IA64_RS_CRX, /* CRs not in RS_CR */ - IA64_RS_PSR, /* PSR bits */ - IA64_RS_RSE, /* implementation-specific RSE resources */ - IA64_RS_AR_FPSR, -}; - -enum ia64_rse_resource -{ - IA64_RSE_N_STACKED_PHYS, - IA64_RSE_BOF, - IA64_RSE_STORE_REG, - IA64_RSE_LOAD_REG, - IA64_RSE_BSPLOAD, - IA64_RSE_RNATBITINDEX, - IA64_RSE_CFLE, - IA64_RSE_NDIRTY, -}; - -/* Information about a given resource dependency */ -struct ia64_dependency -{ - /* Name of the resource */ - const char *name; - /* Does this dependency need further specification? */ - enum ia64_resource_specifier specifier; - /* Mode of dependency */ - enum ia64_dependency_mode mode; - /* Dependency semantics */ - enum ia64_dependency_semantics semantics; - /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ -#define REG_NONE (-1) - int regindex; - /* Special info on semantics */ - const char *info; -}; - -/* Two arrays of indexes into the ia64_dependency table. - chks are dependencies to check for conflicts when an opcode is - encountered; regs are dependencies to register (mark as used) when an - opcode is used. chks correspond to readers (RAW) or writers (WAW or - WAR) of a resource, while regs correspond to writers (RAW or WAW) and - readers (WAR) of a resource. */ -struct ia64_opcode_dependency -{ - int nchks; - const unsigned short *chks; - int nregs; - const unsigned short *regs; -}; - -/* encode/extract the note/index for a dependency */ -#define RDEP(N,X) (((N)<<11)|(X)) -#define NOTE(X) (((X)>>11)&0x1F) -#define DEP(X) ((X)&0x7FF) - -/* A template descriptor describes the execution units that are active - for each of the three slots. It also specifies the location of - instruction group boundaries that may be present between two slots. */ -struct ia64_templ_desc - { - int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ - enum ia64_unit exec_unit[3]; - const char *name; - }; - -/* The opcode table is an array of struct ia64_opcode. */ - -struct ia64_opcode - { - /* The opcode name. */ - const char *name; - - /* The type of the instruction: */ - enum ia64_insn_type type; - - /* Number of output operands: */ - int num_outputs; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - ia64_insn opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - ia64_insn mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - enum ia64_opnd operands[5]; - - /* One bit flags for the opcode. These are primarily used to - indicate specific processors and environments support the - instructions. The defined values are listed below. */ - unsigned int flags; - - /* Used by ia64_find_next_opcode (). */ - short ent_index; - - /* Opcode dependencies. */ - const struct ia64_opcode_dependency *dependencies; - }; - -/* Values defined for the flags field of a struct ia64_opcode. */ - -#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ -#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ -#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ -#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ -#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ -#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ -#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ -#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ -#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ -#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ -#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ - -/* A macro to extract the major opcode from an instruction. */ -#define IA64_OP(i) (((i) >> 37) & 0xf) - -enum ia64_operand_class - { - IA64_OPND_CLASS_CST, /* constant */ - IA64_OPND_CLASS_REG, /* register */ - IA64_OPND_CLASS_IND, /* indirect register */ - IA64_OPND_CLASS_ABS, /* absolute value */ - IA64_OPND_CLASS_REL, /* IP-relative value */ - }; - -/* The operands table is an array of struct ia64_operand. */ - -struct ia64_operand -{ - enum ia64_operand_class class; - - /* Set VALUE as the operand bits for the operand of type SELF in the - instruction pointed to by CODE. If an error occurs, *CODE is not - modified and the returned string describes the cause of the - error. If no error occurs, NULL is returned. */ - const char *(*insert) (const struct ia64_operand *self, ia64_insn value, - ia64_insn *code); - - /* Extract the operand bits for an operand of type SELF from - instruction CODE store them in *VALUE. If an error occurs, the - cause of the error is described by the string returned. If no - error occurs, NULL is returned. */ - const char *(*extract) (const struct ia64_operand *self, ia64_insn code, - ia64_insn *value); - - /* A string whose meaning depends on the operand class. */ - - const char *str; - - struct bit_field - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - } - field[4]; /* no operand has more than this many bit-fields */ - - unsigned int flags; - - const char *desc; /* brief description */ -}; - -/* Values defined for the flags field of a struct ia64_operand. */ - -/* Disassemble as signed decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) -/* Disassemble as unsigned decimal (instead of hex): */ -#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) - -extern const struct ia64_templ_desc ia64_templ_desc[16]; - -/* The tables are sorted by major opcode number and are otherwise in - the order in which the disassembler should consider instructions. */ -extern struct ia64_opcode ia64_opcodes_a[]; -extern struct ia64_opcode ia64_opcodes_i[]; -extern struct ia64_opcode ia64_opcodes_m[]; -extern struct ia64_opcode ia64_opcodes_b[]; -extern struct ia64_opcode ia64_opcodes_f[]; -extern struct ia64_opcode ia64_opcodes_d[]; - - -extern struct ia64_opcode *ia64_find_opcode (const char *name); -extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent); - -extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn, - enum ia64_insn_type type); - -extern void ia64_free_opcode (struct ia64_opcode *ent); -extern const struct ia64_dependency *ia64_find_dependency (int index); - -/* To avoid circular library dependencies, this array is implemented - in bfd/cpu-ia64-opc.c: */ -extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; - -#endif /* opcode_ia64_h */ diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h deleted file mode 100644 index 2d321c8545bf5..0000000000000 --- a/contrib/binutils/include/opcode/mips.h +++ /dev/null @@ -1,1032 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005 - Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef _MIPS_H_ -#define _MIPS_H_ - -/* These are bit masks and shift counts to use to access the various - fields of an instruction. To retrieve the X field of an - instruction, use the expression - (i >> OP_SH_X) & OP_MASK_X - To set the same field (to j), use - i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) - - Make sure you use fields that are appropriate for the instruction, - of course. - - The 'i' format uses OP, RS, RT and IMMEDIATE. - - The 'j' format uses OP and TARGET. - - The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. - - The 'b' format uses OP, RS, RT and DELTA. - - The floating point 'i' format uses OP, RS, RT and IMMEDIATE. - - The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. - - A breakpoint instruction uses OP, CODE and SPEC (10 bits of the - breakpoint instruction are not defined; Kane says the breakpoint - code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too, and MIPS32 and later - architectures allow 20 bits to be set with a signal operand - (using CODE20). - - The syscall instruction uses CODE20. - - The general coprocessor instructions use COPZ. */ - -#define OP_MASK_OP 0x3f -#define OP_SH_OP 26 -#define OP_MASK_RS 0x1f -#define OP_SH_RS 21 -#define OP_MASK_FR 0x1f -#define OP_SH_FR 21 -#define OP_MASK_FMT 0x1f -#define OP_SH_FMT 21 -#define OP_MASK_BCC 0x7 -#define OP_SH_BCC 18 -#define OP_MASK_CODE 0x3ff -#define OP_SH_CODE 16 -#define OP_MASK_CODE2 0x3ff -#define OP_SH_CODE2 6 -#define OP_MASK_RT 0x1f -#define OP_SH_RT 16 -#define OP_MASK_FT 0x1f -#define OP_SH_FT 16 -#define OP_MASK_CACHE 0x1f -#define OP_SH_CACHE 16 -#define OP_MASK_RD 0x1f -#define OP_SH_RD 11 -#define OP_MASK_FS 0x1f -#define OP_SH_FS 11 -#define OP_MASK_PREFX 0x1f -#define OP_SH_PREFX 11 -#define OP_MASK_CCC 0x7 -#define OP_SH_CCC 8 -#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ -#define OP_SH_CODE20 6 -#define OP_MASK_SHAMT 0x1f -#define OP_SH_SHAMT 6 -#define OP_MASK_BITIND OP_MASK_RT -#define OP_SH_BITIND OP_SH_RT -#define OP_MASK_FD 0x1f -#define OP_SH_FD 6 -#define OP_MASK_TARGET 0x3ffffff -#define OP_SH_TARGET 0 -#define OP_MASK_COPZ 0x1ffffff -#define OP_SH_COPZ 0 -#define OP_MASK_IMMEDIATE 0xffff -#define OP_SH_IMMEDIATE 0 -#define OP_MASK_DELTA 0xffff -#define OP_SH_DELTA 0 -#define OP_MASK_FUNCT 0x3f -#define OP_SH_FUNCT 0 -#define OP_MASK_SPEC 0x3f -#define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code. */ -#define OP_SH_HICC 18 /* FP condition code. */ -#define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ -#define OP_MASK_COP1NORM 0x1 /* a single bit. */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ -#define OP_MASK_COP1SPEC 0xf -#define OP_MASK_COP1SCLR 0x4 -#define OP_MASK_COP1CMP 0x3 -#define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field. */ -#define OP_MASK_FORMAT 0x7 -#define OP_SH_TRUE 16 -#define OP_MASK_TRUE 0x1 -#define OP_SH_GE 17 -#define OP_MASK_GE 0x01 -#define OP_SH_UNSIGNED 16 -#define OP_MASK_UNSIGNED 0x1 -#define OP_SH_HINT 16 -#define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f -#define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ -#define OP_SH_PERFREG 1 -#define OP_SH_SEL 0 /* Coprocessor select field. */ -#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ -#define OP_SH_CODE19 6 /* 19 bit wait code. */ -#define OP_MASK_CODE19 0x7ffff -#define OP_SH_ALN 21 -#define OP_MASK_ALN 0x7 -#define OP_SH_VSEL 21 -#define OP_MASK_VSEL 0x1f -#define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, - but 0x8-0xf don't select bytes. */ -#define OP_SH_VECBYTE 22 -#define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ -#define OP_SH_VECALIGN 21 -#define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ -#define OP_SH_INSMSB 11 -#define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ -#define OP_SH_EXTMSBD 11 - -/* MIPS DSP ASE */ -#define OP_SH_DSPACC 11 -#define OP_MASK_DSPACC 0x3 -#define OP_SH_DSPACC_S 21 -#define OP_MASK_DSPACC_S 0x3 -#define OP_SH_DSPSFT 20 -#define OP_MASK_DSPSFT 0x3f -#define OP_SH_DSPSFT_7 19 -#define OP_MASK_DSPSFT_7 0x7f -#define OP_SH_SA3 21 -#define OP_MASK_SA3 0x7 -#define OP_SH_SA4 21 -#define OP_MASK_SA4 0xf -#define OP_SH_IMM8 16 -#define OP_MASK_IMM8 0xff -#define OP_SH_IMM10 16 -#define OP_MASK_IMM10 0x3ff -#define OP_SH_WRDSP 11 -#define OP_MASK_WRDSP 0x3f -#define OP_SH_RDDSP 16 -#define OP_MASK_RDDSP 0x3f -#define OP_SH_BP 11 -#define OP_MASK_BP 0x3 - -/* MIPS MT ASE */ -#define OP_SH_MT_U 5 -#define OP_MASK_MT_U 0x1 -#define OP_SH_MT_H 4 -#define OP_MASK_MT_H 0x1 -#define OP_SH_MTACC_T 18 -#define OP_MASK_MTACC_T 0x3 -#define OP_SH_MTACC_D 13 -#define OP_MASK_MTACC_D 0x3 - -#define OP_OP_COP0 0x10 -#define OP_OP_COP1 0x11 -#define OP_OP_COP2 0x12 -#define OP_OP_COP3 0x13 -#define OP_OP_LWC1 0x31 -#define OP_OP_LWC2 0x32 -#define OP_OP_LWC3 0x33 /* a.k.a. pref */ -#define OP_OP_LDC1 0x35 -#define OP_OP_LDC2 0x36 -#define OP_OP_LDC3 0x37 /* a.k.a. ld */ -#define OP_OP_SWC1 0x39 -#define OP_OP_SWC2 0x3a -#define OP_OP_SWC3 0x3b -#define OP_OP_SDC1 0x3d -#define OP_OP_SDC2 0x3e -#define OP_OP_SDC3 0x3f /* a.k.a. sd */ - -/* Values in the 'VSEL' field. */ -#define MDMX_FMTSEL_IMM_QH 0x1d -#define MDMX_FMTSEL_IMM_OB 0x1e -#define MDMX_FMTSEL_VEC_QH 0x15 -#define MDMX_FMTSEL_VEC_OB 0x16 - -/* UDI */ -#define OP_SH_UDI1 6 -#define OP_MASK_UDI1 0x1f -#define OP_SH_UDI2 6 -#define OP_MASK_UDI2 0x3ff -#define OP_SH_UDI3 6 -#define OP_MASK_UDI3 0x7fff -#define OP_SH_UDI4 6 -#define OP_MASK_UDI4 0xfffff - -/* This structure holds information for a particular instruction. */ - -struct mips_opcode -{ - /* The name of the instruction. */ - const char *name; - /* A string describing the arguments for this instruction. */ - const char *args; - /* The basic opcode for the instruction. When assembling, this - opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is 0. */ - unsigned long match; - /* If pinfo is not INSN_MACRO, then this is a bit mask for the - relevant portions of the opcode when disassembling. If the - actual opcode anded with the match field equals the opcode field, - then we have found the correct instruction. If pinfo is - INSN_MACRO, then this field is the macro identifier. */ - unsigned long mask; - /* For a macro, this is INSN_MACRO. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. */ - unsigned long pinfo; - /* A collection of additional bits describing the instruction. */ - unsigned long pinfo2; - /* A collection of bits describing the instruction sets of which this - instruction or macro is a member. */ - unsigned long membership; -}; - -/* These are the characters which may appear in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - Each of these characters corresponds to a mask field defined above. - - "<" 5 bit shift amount (OP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) - "^" 5 bit bit index amount (OP_*_BITIND) - "~" bit index between 32 and 63, stored after subtracting 32 (OP_*_BITIND) - "a" 26 bit target address (OP_*_TARGET) - "b" 5 bit base register (OP_*_RS) - "c" 10 bit breakpoint code (OP_*_CODE) - "d" 5 bit destination register specifier (OP_*_RD) - "h" 5 bit prefx hint (OP_*_PREFX) - "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) - "j" 16 bit signed immediate (OP_*_DELTA) - "k" 5 bit cache opcode in target register position (OP_*_CACHE) - Also used for immediate operands in vr5400 vector insns. - "o" 16 bit signed offset (OP_*_DELTA) - "p" 16 bit PC relative branch target address (OP_*_DELTA) - "q" 10 bit extra breakpoint code (OP_*_CODE2) - "r" 5 bit same register used as both source and target (OP_*_RS) - "s" 5 bit source register specifier (OP_*_RS) - "t" 5 bit target register (OP_*_RT) - "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) - "v" 5 bit same register used as both source and destination (OP_*_RS) - "w" 5 bit same register used as both target and destination (OP_*_RT) - "U" 5 bit same destination register in both OP_*_RD and OP_*_RT - (used by clo and clz) - "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) - "J" 19 bit wait function code (OP_*_CODE19) - "x" accept and ignore register name - "y" 10 bit signed const (OP_*_CODE2) - "z" must be zero register - "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) - "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes - LSB (OP_*_SHAMT). - Enforces: 0 <= pos < 32. - "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 0 < (pos+size) <= 32. - (Also used by "dext" w/ different limits, but limits for - that are checked by the M_DEXT macro.) - "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). - Enforces: 32 <= pos < 64. - "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). - Requires that "+A" or "+E" occur first to set position. - Enforces: 32 < (pos+size) <= 64. - - Floating point instructions: - "D" 5 bit destination register (OP_*_FD) - "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) - "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) - "S" 5 bit fs source 1 register (OP_*_FS) - "T" 5 bit ft source 2 register (OP_*_FT) - "R" 5 bit fr source 3 register (OP_*_FR) - "V" 5 bit same register used as floating source and destination (OP_*_FS) - "W" 5 bit same register used as floating target and destination (OP_*_FT) - - Coprocessor instructions: - "E" 5 bit target register (OP_*_RT) - "G" 5 bit destination register (OP_*_RD) - "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) - "P" 5 bit performance-monitor register (OP_*_PERFREG) - "e" 5 bit vector register byte specifier (OP_*_VECBYTE) - "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) - see also "k" above - "+D" Combined destination register ("G") and sel ("H") for CP0 ops, - for pretty-printing in disassembly only. - - Macro instructions: - "A" General 32 bit expression - "I" 32 bit immediate (value placed in imm_expr). - "+I" 32 bit immediate (value placed in imm2_expr). - "F" 64 bit floating point constant in .rdata - "L" 64 bit floating point constant in .lit8 - "f" 32 bit floating point constant - "l" 32 bit floating point constant in .lit4 - - MDMX instruction operands (note that while these use the FP register - fields, they accept both $fN and $vN names for the registers): - "O" MDMX alignment offset (OP_*_ALN) - "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) - "X" MDMX destination register (OP_*_FD) - "Y" MDMX source register (OP_*_FS) - "Z" MDMX source register (OP_*_FT) - - DSP ASE usage: - "2" 2 bit unsigned immediate for byte align (OP_*_BP) - "3" 3 bit unsigned immediate (OP_*_SA3) - "4" 4 bit unsigned immediate (OP_*_SA4) - "5" 8 bit unsigned immediate (OP_*_IMM8) - "6" 5 bit unsigned immediate (OP_*_RS) - "7" 2 bit dsp accumulator register (OP_*_DSPACC) - "8" 6 bit unsigned immediate (OP_*_WRDSP) - "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) - "0" 6 bit signed immediate (OP_*_DSPSFT) - ":" 7 bit signed immediate (OP_*_DSPSFT_7) - "'" 6 bit unsigned immediate (OP_*_RDDSP) - "@" 10 bit signed immediate (OP_*_IMM10) - - MT ASE usage: - "!" 1 bit usermode flag (OP_*_MT_U) - "$" 1 bit load high flag (OP_*_MT_H) - "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) - "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) - "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) - "+t" 5 bit coprocessor 0 destination register (OP_*_RT) - "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only - - UDI immediates: - "+1" UDI immediate bits 6-10 - "+2" UDI immediate bits 6-15 - "+3" UDI immediate bits 6-20 - "+4" UDI immediate bits 6-25 - - Other: - "()" parens surrounding optional value - "," separates operands - "[]" brackets around index for vector-op scalar operand specifier (vr5400) - "+" Start of extension sequence. - - Characters used so far, for quick reference when adding more: - "234567890" - "%[]<>(),+:'@!$*&^~" - "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdefghijklopqrstuvwxyz" - - Extension character sequences used so far ("+" followed by the - following), for quick reference when adding more: - "1234" - "ABCDEFGHIT" - "t" -*/ - -/* These are the bits which may be set in the pinfo field of an - instructions, if it is not equal to INSN_MACRO. */ - -/* Modifies the general purpose register in OP_*_RD. */ -#define INSN_WRITE_GPR_D 0x00000001 -/* Modifies the general purpose register in OP_*_RT. */ -#define INSN_WRITE_GPR_T 0x00000002 -/* Modifies general purpose register 31. */ -#define INSN_WRITE_GPR_31 0x00000004 -/* Modifies the floating point register in OP_*_FD. */ -#define INSN_WRITE_FPR_D 0x00000008 -/* Modifies the floating point register in OP_*_FS. */ -#define INSN_WRITE_FPR_S 0x00000010 -/* Modifies the floating point register in OP_*_FT. */ -#define INSN_WRITE_FPR_T 0x00000020 -/* Reads the general purpose register in OP_*_RS. */ -#define INSN_READ_GPR_S 0x00000040 -/* Reads the general purpose register in OP_*_RT. */ -#define INSN_READ_GPR_T 0x00000080 -/* Reads the floating point register in OP_*_FS. */ -#define INSN_READ_FPR_S 0x00000100 -/* Reads the floating point register in OP_*_FT. */ -#define INSN_READ_FPR_T 0x00000200 -/* Reads the floating point register in OP_*_FR. */ -#define INSN_READ_FPR_R 0x00000400 -/* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000800 -/* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00001000 -/* TLB operation. */ -#define INSN_TLB 0x00002000 -/* Reads coprocessor register other than floating point register. */ -#define INSN_COP 0x00004000 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00008000 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00010000 -/* Instruction has unconditional branch delay slot. */ -#define INSN_UNCOND_BRANCH_DELAY 0x00020000 -/* Instruction has conditional branch delay slot. */ -#define INSN_COND_BRANCH_DELAY 0x00040000 -/* Conditional branch likely: if branch not taken, insn nullified. */ -#define INSN_COND_BRANCH_LIKELY 0x00080000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00100000 -/* Loads coprocessor register from memory, requiring delay. */ -#define INSN_COPROC_MEMORY_DELAY 0x00200000 -/* Reads the HI register. */ -#define INSN_READ_HI 0x00400000 -/* Reads the LO register. */ -#define INSN_READ_LO 0x00800000 -/* Modifies the HI register. */ -#define INSN_WRITE_HI 0x01000000 -/* Modifies the LO register. */ -#define INSN_WRITE_LO 0x02000000 -/* Takes a trap (easier to keep out of delay slot). */ -#define INSN_TRAP 0x04000000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x08000000 -/* Instruction uses single precision floating point. */ -#define FP_S 0x10000000 -/* Instruction uses double precision floating point. */ -#define FP_D 0x20000000 -/* Instruction is part of the tx39's integer multiply family. */ -#define INSN_MULT 0x40000000 -/* Instruction synchronize shared memory. */ -#define INSN_SYNC 0x80000000 - -/* These are the bits which may be set in the pinfo2 field of an - instruction. */ - -/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ -#define INSN2_ALIAS 0x00000001 -/* Instruction reads MDMX accumulator. */ -#define INSN2_READ_MDMX_ACC 0x00000002 -/* Instruction writes MDMX accumulator. */ -#define INSN2_WRITE_MDMX_ACC 0x00000004 - -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff - -/* Masks used to mark instructions to indicate which MIPS ISA level - they were introduced in. ISAs, as defined below, are logical - ORs of these bits, indicating that they support the instructions - defined at the given level. */ - -#define INSN_ISA_MASK 0x00000fff -#define INSN_ISA1 0x00000001 -#define INSN_ISA2 0x00000002 -#define INSN_ISA3 0x00000004 -#define INSN_ISA4 0x00000008 -#define INSN_ISA5 0x00000010 -#define INSN_ISA32 0x00000020 -#define INSN_ISA64 0x00000040 -#define INSN_ISA32R2 0x00000080 -#define INSN_ISA64R2 0x00000100 - -/* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x3c00f000 - -/* DSP ASE */ -#define INSN_DSP 0x00001000 -#define INSN_DSP64 0x00002000 -/* MIPS 16 ASE */ -#define INSN_MIPS16 0x00004000 -/* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00008000 - -/* Chip specific instructions. These are bitmasks. */ - -/* MIPS R4650 instruction. */ -#define INSN_4650 0x00010000 -/* LSI R4010 instruction. */ -#define INSN_4010 0x00020000 -/* NEC VR4100 instruction. */ -#define INSN_4100 0x00040000 -/* Toshiba R3900 instruction. */ -#define INSN_3900 0x00080000 -/* MIPS R10000 instruction. */ -#define INSN_10000 0x00100000 -/* Broadcom SB-1 instruction. */ -#define INSN_SB1 0x00200000 -/* NEC VR4111/VR4181 instruction. */ -#define INSN_4111 0x00400000 -/* NEC VR4120 instruction. */ -#define INSN_4120 0x00800000 -/* NEC VR5400 instruction. */ -#define INSN_5400 0x01000000 -/* NEC VR5500 instruction. */ -#define INSN_5500 0x02000000 - -/* MDMX ASE */ -#define INSN_MDMX 0x04000000 -/* MT ASE */ -#define INSN_MT 0x08000000 -/* SmartMIPS ASE */ -#define INSN_SMARTMIPS 0x10000000 -/* DSP R2 ASE */ -#define INSN_DSPR2 0x20000000 -/* Cavium Networks Octeon instruction. */ -#define INSN_OCTEON 0x08000000 - -/* MIPS ISA defines, use instead of hardcoding ISA level. */ - -#define ISA_UNKNOWN 0 /* Gas internal use. */ -#define ISA_MIPS1 (INSN_ISA1) -#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) -#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) -#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) -#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) - -#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) -#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) - -#define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2) -#define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2) - - -/* CPU defines, use instead of hardcoding processor number. Keep this - in sync with bfd/archures.c in order for machine selection to work. */ -#define CPU_UNKNOWN 0 /* Gas internal use. */ -#define CPU_R3000 3000 -#define CPU_R3900 3900 -#define CPU_R4000 4000 -#define CPU_R4010 4010 -#define CPU_VR4100 4100 -#define CPU_R4111 4111 -#define CPU_VR4120 4120 -#define CPU_R4300 4300 -#define CPU_R4400 4400 -#define CPU_R4600 4600 -#define CPU_R4650 4650 -#define CPU_R5000 5000 -#define CPU_VR5400 5400 -#define CPU_VR5500 5500 -#define CPU_R6000 6000 -#define CPU_RM7000 7000 -#define CPU_R8000 8000 -#define CPU_RM9000 9000 -#define CPU_R10000 10000 -#define CPU_R12000 12000 -#define CPU_MIPS16 16 -#define CPU_MIPS32 32 -#define CPU_MIPS32R2 33 -#define CPU_MIPS5 5 -#define CPU_MIPS64 64 -#define CPU_MIPS64R2 65 -#define CPU_SB1 12310201 /* octal 'SB', 01. */ -#define CPU_OCTEON 6502 - -/* Test for membership in an ISA including chip specific ISAs. INSN - is pointer to an element of the opcode table; ISA is the specified - ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to - test, or zero if no CPU specific ISA test is desired. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu) \ - (((insn)->membership & isa) != 0 \ - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ - || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ - && ((insn)->membership & INSN_10000) != 0) \ - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ - || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \ - || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ - || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ - || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ - || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ - || 0) /* Please keep this term for easier source merging. */ - -/* This is a list of macro expanded instructions. - - _I appended means immediate - _A appended means address - _AB appended means address with base register - _D appended means 64 bit floating point constant - _S appended means 32 bit floating point constant. */ - -enum -{ - M_ABS, - M_ADD_I, - M_ADDU_I, - M_AND_I, - M_BALIGN, - M_BEQ, - M_BEQ_I, - M_BEQL_I, - M_BGE, - M_BGEL, - M_BGE_I, - M_BGEL_I, - M_BGEU, - M_BGEUL, - M_BGEU_I, - M_BGEUL_I, - M_BGT, - M_BGTL, - M_BGT_I, - M_BGTL_I, - M_BGTU, - M_BGTUL, - M_BGTU_I, - M_BGTUL_I, - M_BLE, - M_BLEL, - M_BLE_I, - M_BLEL_I, - M_BLEU, - M_BLEUL, - M_BLEU_I, - M_BLEUL_I, - M_BLT, - M_BLTL, - M_BLT_I, - M_BLTL_I, - M_BLTU, - M_BLTUL, - M_BLTU_I, - M_BLTUL_I, - M_BNE, - M_BNE_I, - M_BNEL_I, - M_CACHE_AB, - M_DABS, - M_DADD_I, - M_DADDU_I, - M_DDIV_3, - M_DDIV_3I, - M_DDIVU_3, - M_DDIVU_3I, - M_DEXT, - M_DINS, - M_DIV_3, - M_DIV_3I, - M_DIVU_3, - M_DIVU_3I, - M_DLA_AB, - M_DLCA_AB, - M_DLI, - M_DMUL, - M_DMUL_I, - M_DMULO, - M_DMULO_I, - M_DMULOU, - M_DMULOU_I, - M_DREM_3, - M_DREM_3I, - M_DREMU_3, - M_DREMU_3I, - M_DSUB_I, - M_DSUBU_I, - M_DSUBU_I_2, - M_J_A, - M_JAL_1, - M_JAL_2, - M_JAL_A, - M_L_DOB, - M_L_DAB, - M_LA_AB, - M_LB_A, - M_LB_AB, - M_LBU_A, - M_LBU_AB, - M_LCA_AB, - M_LD_A, - M_LD_OB, - M_LD_AB, - M_LDC1_AB, - M_LDC2_AB, - M_LDC3_AB, - M_LDL_AB, - M_LDR_AB, - M_LH_A, - M_LH_AB, - M_LHU_A, - M_LHU_AB, - M_LI, - M_LI_D, - M_LI_DD, - M_LI_S, - M_LI_SS, - M_LL_AB, - M_LLD_AB, - M_LS_A, - M_LW_A, - M_LW_AB, - M_LWC0_A, - M_LWC0_AB, - M_LWC1_A, - M_LWC1_AB, - M_LWC2_A, - M_LWC2_AB, - M_LWC3_A, - M_LWC3_AB, - M_LWL_A, - M_LWL_AB, - M_LWR_A, - M_LWR_AB, - M_LWU_AB, - M_MOVE, - M_MUL, - M_MUL_I, - M_MULO, - M_MULO_I, - M_MULOU, - M_MULOU_I, - M_NOR_I, - M_OR_I, - M_REM_3, - M_REM_3I, - M_REMU_3, - M_REMU_3I, - M_DROL, - M_ROL, - M_DROL_I, - M_ROL_I, - M_DROR, - M_ROR, - M_DROR_I, - M_ROR_I, - M_S_DA, - M_S_DOB, - M_S_DAB, - M_S_S, - M_SAA_AB, - M_SAAD_AB, - M_SC_AB, - M_SCD_AB, - M_SD_A, - M_SD_OB, - M_SD_AB, - M_SDC1_AB, - M_SDC2_AB, - M_SDC3_AB, - M_SDL_AB, - M_SDR_AB, - M_SEQ, - M_SEQ_I, - M_SGE, - M_SGE_I, - M_SGEU, - M_SGEU_I, - M_SGT, - M_SGT_I, - M_SGTU, - M_SGTU_I, - M_SLE, - M_SLE_I, - M_SLEU, - M_SLEU_I, - M_SLT_I, - M_SLTU_I, - M_SNE, - M_SNE_I, - M_SB_A, - M_SB_AB, - M_SH_A, - M_SH_AB, - M_SW_A, - M_SW_AB, - M_SWC0_A, - M_SWC0_AB, - M_SWC1_A, - M_SWC1_AB, - M_SWC2_A, - M_SWC2_AB, - M_SWC3_A, - M_SWC3_AB, - M_SWL_A, - M_SWL_AB, - M_SWR_A, - M_SWR_AB, - M_SUB_I, - M_SUBU_I, - M_SUBU_I_2, - M_TEQ_I, - M_TGE_I, - M_TGEU_I, - M_TLT_I, - M_TLTU_I, - M_TNE_I, - M_TRUNCWD, - M_TRUNCWS, - M_ULD, - M_ULD_A, - M_ULH, - M_ULH_A, - M_ULHU, - M_ULHU_A, - M_ULW, - M_ULW_A, - M_USH, - M_USH_A, - M_USW, - M_USW_A, - M_USD, - M_USD_A, - M_XOR_I, - M_COP0, - M_COP1, - M_COP2, - M_COP3, - M_NUM_MACROS -}; - - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -extern const struct mips_opcode mips_builtin_opcodes[]; -extern const int bfd_mips_num_builtin_opcodes; -extern struct mips_opcode *mips_opcodes; -extern int bfd_mips_num_opcodes; -#define NUMOPCODES bfd_mips_num_opcodes - - -/* The rest of this file adds definitions for the mips16 TinyRISC - processor. */ - -/* These are the bitmasks and shift counts used for the different - fields in the instruction formats. Other than OP, no masks are - provided for the fixed portions of an instruction, since they are - not needed. - - The I format uses IMM11. - - The RI format uses RX and IMM8. - - The RR format uses RX, and RY. - - The RRI format uses RX, RY, and IMM5. - - The RRR format uses RX, RY, and RZ. - - The RRI_A format uses RX, RY, and IMM4. - - The SHIFT format uses RX, RY, and SHAMT. - - The I8 format uses IMM8. - - The I8_MOVR32 format uses RY and REGR32. - - The IR_MOV32R format uses REG32R and MOV32Z. - - The I64 format uses IMM8. - - The RI64 format uses RY and IMM5. - */ - -#define MIPS16OP_MASK_OP 0x1f -#define MIPS16OP_SH_OP 11 -#define MIPS16OP_MASK_IMM11 0x7ff -#define MIPS16OP_SH_IMM11 0 -#define MIPS16OP_MASK_RX 0x7 -#define MIPS16OP_SH_RX 8 -#define MIPS16OP_MASK_IMM8 0xff -#define MIPS16OP_SH_IMM8 0 -#define MIPS16OP_MASK_RY 0x7 -#define MIPS16OP_SH_RY 5 -#define MIPS16OP_MASK_IMM5 0x1f -#define MIPS16OP_SH_IMM5 0 -#define MIPS16OP_MASK_RZ 0x7 -#define MIPS16OP_SH_RZ 2 -#define MIPS16OP_MASK_IMM4 0xf -#define MIPS16OP_SH_IMM4 0 -#define MIPS16OP_MASK_REGR32 0x1f -#define MIPS16OP_SH_REGR32 0 -#define MIPS16OP_MASK_REG32R 0x1f -#define MIPS16OP_SH_REG32R 3 -#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) -#define MIPS16OP_MASK_MOVE32Z 0x7 -#define MIPS16OP_SH_MOVE32Z 0 -#define MIPS16OP_MASK_IMM6 0x3f -#define MIPS16OP_SH_IMM6 5 - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - "y" 3 bit register (MIPS16OP_*_RY) - "x" 3 bit register (MIPS16OP_*_RX) - "z" 3 bit register (MIPS16OP_*_RZ) - "Z" 3 bit register (MIPS16OP_*_MOVE32Z) - "v" 3 bit same register as source and destination (MIPS16OP_*_RX) - "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) - "S" stack pointer ($sp or $29) - "P" program counter - "R" return address register ($ra or $31) - "X" 5 bit MIPS register (MIPS16OP_*_REGR32) - "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) - "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) - "a" 26 bit jump address - "e" 11 bit extension value - "l" register list for entry instruction - "L" register list for exit instruction - - The remaining codes may be extended. Except as otherwise noted, - the full extended operand is a 16 bit signed value. - "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) - "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) - "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) - "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) - "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) - "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) - "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) - "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) - "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) - "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) - "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) - "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) - "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) - "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) - "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) - "q" 11 bit branch address (MIPS16OP_*_IMM11) - "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) - "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) - "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - "m" 7 bit register list for save instruction (18 bit extended) - "M" 7 bit register list for restore instruction (18 bit extended) - */ - -/* Save/restore encoding for the args field when all 4 registers are - either saved as arguments or saved/restored as statics. */ -#define MIPS16_ALL_ARGS 0xe -#define MIPS16_ALL_STATICS 0xb - -/* For the mips16, we use the same opcode table format and a few of - the same flags. However, most of the flags are different. */ - -/* Modifies the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_WRITE_X 0x00000001 -/* Modifies the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_WRITE_Y 0x00000002 -/* Modifies the register in MIPS16OP_*_RZ. */ -#define MIPS16_INSN_WRITE_Z 0x00000004 -/* Modifies the T ($24) register. */ -#define MIPS16_INSN_WRITE_T 0x00000008 -/* Modifies the SP ($29) register. */ -#define MIPS16_INSN_WRITE_SP 0x00000010 -/* Modifies the RA ($31) register. */ -#define MIPS16_INSN_WRITE_31 0x00000020 -/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ -#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 -/* Reads the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_READ_X 0x00000080 -/* Reads the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_READ_Y 0x00000100 -/* Reads the register in MIPS16OP_*_MOVE32Z. */ -#define MIPS16_INSN_READ_Z 0x00000200 -/* Reads the T ($24) register. */ -#define MIPS16_INSN_READ_T 0x00000400 -/* Reads the SP ($29) register. */ -#define MIPS16_INSN_READ_SP 0x00000800 -/* Reads the RA ($31) register. */ -#define MIPS16_INSN_READ_31 0x00001000 -/* Reads the program counter. */ -#define MIPS16_INSN_READ_PC 0x00002000 -/* Reads the general purpose register in MIPS16OP_*_REGR32. */ -#define MIPS16_INSN_READ_GPR_X 0x00004000 -/* Is a branch insn. */ -#define MIPS16_INSN_BRANCH 0x00010000 - -/* The following flags have the same value for the mips16 opcode - table: - INSN_UNCOND_BRANCH_DELAY - INSN_COND_BRANCH_DELAY - INSN_COND_BRANCH_LIKELY (never used) - INSN_READ_HI - INSN_READ_LO - INSN_WRITE_HI - INSN_WRITE_LO - INSN_TRAP - INSN_ISA3 - */ - -extern const struct mips_opcode mips16_opcodes[]; -extern const int bfd_mips16_num_opcodes; - -#endif /* _MIPS_H_ */ diff --git a/contrib/binutils/include/opcode/np1.h b/contrib/binutils/include/opcode/np1.h deleted file mode 100644 index ebe37f5d2dfc7..0000000000000 --- a/contrib/binutils/include/opcode/np1.h +++ /dev/null @@ -1,422 +0,0 @@ -/* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, -{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, -{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, -{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, -{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, -{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, -{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, - -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, -{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, -{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, -{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, - -{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, -{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, -{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, -{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, -{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, -{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, -{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, - -{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, -{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, -{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, -{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, -{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, -{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, -{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, -{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, -{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, -{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, -{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, -{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, -{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, -{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, -{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, -{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, -{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, -{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, -{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, -{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, -{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, -{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, -{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, - -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, -{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, - -{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, -{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, -{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, -{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, -{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, -{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, - -{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, -{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, -{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, -{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, - -{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, -{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, -{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, -{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, -{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, - -{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, -{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, -{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, -{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, -{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, -{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, - -{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, -{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, -{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, - -{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, -{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, -{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, -{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, -{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, -{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, -{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, -{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, -{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, -{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, - -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, -{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, - -{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, -{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, -{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, -{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, -{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, -{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, -{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, -{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, -{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, -{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, -{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, -{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, -{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, -{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, - -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, - -{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, -{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, -{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, - -{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, -{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, -{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, -{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, -{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, -{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, -{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, -{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, -{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, -{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, -{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, - -{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, -{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, -{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, -{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, -{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, -{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, -{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, -{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, -{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, -{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, -{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, -{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, -{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, -{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, -{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, -{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, -{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, -{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, -{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, -{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, -{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, -{ "break", 0x28090000, 0xfc0f0000, "", 2 }, -{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, -{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, -{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, -{ "block", 0x04060000, 0xfc0f0000, "", 2 }, -{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, -{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, -{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, -{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, -{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, -{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, -{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, -{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, -{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, -{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, -{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, -{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, -{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, - -{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, -{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, -{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, - -{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, -{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, -{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, -{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, -{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/contrib/binutils/include/opcode/pn.h b/contrib/binutils/include/opcode/pn.h deleted file mode 100644 index f8d474f60a50f..0000000000000 --- a/contrib/binutils/include/opcode/pn.h +++ /dev/null @@ -1,282 +0,0 @@ -/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, -{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, -{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, -{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, -{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bei", 0x00060000, 0xffff0000, "", 2 }, -{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, -{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, -{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, -{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, -{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, -{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, -{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, -{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, -{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, -{ "call", 0x28080000, 0xfc0f0000, "", 2 }, -{ "callm", 0x5c080000, 0xff880000, "", 4 }, -{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, -{ "cea", 0x000f0000, 0xffff0000, "", 2 }, -{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, -{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, -{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, -{ "dae", 0x000e0000, 0xffff0000, "", 2 }, -{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, -{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, -{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, -{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, -{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "eae", 0x00080000, 0xffff0000, "", 2 }, -{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, -{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, -{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, -{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, -{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, -{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, -{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, -{ "halt", 0x00000000, 0xffff0000, "", 2 }, -{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, -{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, -{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, -{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, -{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, -{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, -{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, -{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, -{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "nop", 0x00020000, 0xffff0000, "", 2 }, -{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, -{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, -{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, -{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, -{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, -{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, -{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, -{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, -{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, -{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, -{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, -{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, -{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, -{ "sea", 0x000d0000, 0xffff0000, "", 2 }, -{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, -{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, -{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "smc", 0x04070000, 0xfc070000, "", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, -{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, -{ "svc", 0xc8060000, 0xffff0000, "", 4 }, -{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, -{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, -{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, -{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, -{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, -{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, -{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, -{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "uei", 0x00070000, 0xffff0000, "", 2 }, -{ "wait", 0x00010000, 0xffff0000, "", 2 }, -{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, -{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, -{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, -{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, -{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h deleted file mode 100644 index 6771856fd5f89..0000000000000 --- a/contrib/binutils/include/opcode/ppc.h +++ /dev/null @@ -1,326 +0,0 @@ -/* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, - 2007 Free Software Foundation, Inc. - Written by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -#ifndef PPC_H -#define PPC_H - -/* The opcode table is an array of struct powerpc_opcode. */ - -struct powerpc_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The defined values - are listed below. */ - unsigned long flags; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; -}; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct powerpc_opcode powerpc_opcodes[]; -extern const int powerpc_num_opcodes; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* Opcode is defined for the PowerPC architecture. */ -#define PPC_OPCODE_PPC 1 - -/* Opcode is defined for the POWER (RS/6000) architecture. */ -#define PPC_OPCODE_POWER 2 - -/* Opcode is defined for the POWER2 (Rios 2) architecture. */ -#define PPC_OPCODE_POWER2 4 - -/* Opcode is only defined on 32 bit architectures. */ -#define PPC_OPCODE_32 8 - -/* Opcode is only defined on 64 bit architectures. */ -#define PPC_OPCODE_64 0x10 - -/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 - is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, - but it also supports many additional POWER instructions. */ -#define PPC_OPCODE_601 0x20 - -/* Opcode is supported in both the Power and PowerPC architectures - (ie, compiler's -mcpu=common or assembler's -mcom). */ -#define PPC_OPCODE_COMMON 0x40 - -/* Opcode is supported for any Power or PowerPC platform (this is - for the assembler's -many option, and it eliminates duplicates). */ -#define PPC_OPCODE_ANY 0x80 - -/* Opcode is supported as part of the 64-bit bridge. */ -#define PPC_OPCODE_64_BRIDGE 0x100 - -/* Opcode is supported by Altivec Vector Unit */ -#define PPC_OPCODE_ALTIVEC 0x200 - -/* Opcode is supported by PowerPC 403 processor. */ -#define PPC_OPCODE_403 0x400 - -/* Opcode is supported by PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE 0x800 - -/* Opcode is only supported by 64-bit PowerPC BookE processor. */ -#define PPC_OPCODE_BOOKE64 0x1000 - -/* Opcode is supported by PowerPC 440 processor. */ -#define PPC_OPCODE_440 0x2000 - -/* Opcode is only supported by Power4 architecture. */ -#define PPC_OPCODE_POWER4 0x4000 - -/* Opcode isn't supported by Power4 architecture. */ -#define PPC_OPCODE_NOPOWER4 0x8000 - -/* Opcode is only supported by POWERPC Classic architecture. */ -#define PPC_OPCODE_CLASSIC 0x10000 - -/* Opcode is only supported by e500x2 Core. */ -#define PPC_OPCODE_SPE 0x20000 - -/* Opcode is supported by e500x2 Integer select APU. */ -#define PPC_OPCODE_ISEL 0x40000 - -/* Opcode is an e500 SPE floating point instruction. */ -#define PPC_OPCODE_EFS 0x80000 - -/* Opcode is supported by branch locking APU. */ -#define PPC_OPCODE_BRLOCK 0x100000 - -/* Opcode is supported by performance monitor APU. */ -#define PPC_OPCODE_PMR 0x200000 - -/* Opcode is supported by cache locking APU. */ -#define PPC_OPCODE_CACHELCK 0x400000 - -/* Opcode is supported by machine check APU. */ -#define PPC_OPCODE_RFMCI 0x800000 - -/* Opcode is only supported by Power5 architecture. */ -#define PPC_OPCODE_POWER5 0x1000000 - -/* Opcode is supported by PowerPC e300 family. */ -#define PPC_OPCODE_E300 0x2000000 - -/* Opcode is only supported by Power6 architecture. */ -#define PPC_OPCODE_POWER6 0x4000000 - -/* Opcode is only supported by PowerPC Cell family. */ -#define PPC_OPCODE_CELL 0x8000000 - -/* A macro to extract the major opcode from an instruction. */ -#define PPC_OP(i) (((i) >> 26) & 0x3f) - -/* The operands table is an array of struct powerpc_operand. */ - -struct powerpc_operand -{ - /* A bitmask of bits in the operand. */ - unsigned int bitm; - - /* How far the operand is left shifted in the instruction. - -1 to indicate that BITM and SHIFT cannot be used to determine - where the operand goes in the insn. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & o->bitm) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the operand value). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (*insert) - (unsigned long instruction, long op, int dialect, const char **errmsg); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = (i >> o->shift) & o->bitm; - if ((o->flags & PPC_OPERAND_SIGNED) != 0) - sign_extend (op); - (i is the instruction, o is a pointer to this structure, and op - is the result). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - long (*extract) (unsigned long instruction, int dialect, int *invalid); - - /* One bit syntax flags. */ - unsigned long flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct powerpc_operand powerpc_operands[]; -extern const unsigned int num_powerpc_operands; - -/* Values defined for the flags field of a struct powerpc_operand. */ - -/* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (0x1) - -/* This operand takes signed values, but also accepts a full positive - range of values when running in 32 bit mode. That is, if bits is - 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, - this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (0x2) - -/* This operand does not actually exist in the assembler input. This - is used to support extended mnemonics such as mr, for which two - operands fields are identical. The assembler should call the - insert function with any op value. The disassembler should call - the extract function, ignore the return value, and check the value - placed in the valid argument. */ -#define PPC_OPERAND_FAKE (0x4) - -/* The next operand should be wrapped in parentheses rather than - separated from this one by a comma. This is used for the load and - store instructions which want their operands to look like - reg,displacement(reg) - */ -#define PPC_OPERAND_PARENS (0x8) - -/* This operand may use the symbolic names for the CR fields, which - are - lt 0 gt 1 eq 2 so 3 un 3 - cr0 0 cr1 1 cr2 2 cr3 3 - cr4 4 cr5 5 cr6 6 cr7 7 - These may be combined arithmetically, as in cr2*4+gt. These are - only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR (0x10) - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (0x20) - -/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0x40) - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0x80) - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0x100) - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (0x200) - -/* This operand is optional, and is zero if omitted. This is used for - example, in the optional BF field in the comparison instructions. The - assembler must count the number of operands remaining on the line, - and the number of operands remaining for the opcode, and decide - whether this operand is present or not. The disassembler should - print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (0x400) - -/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand - is omitted, then for the next operand use this operand value plus - 1, ignoring the next operand field for the opcode. This wretched - hack is needed because the Power rotate instructions can take - either 4 or 5 operands. The disassembler should print this operand - out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (0x800) - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define PPC_OPERAND_NEGATIVE (0x1000) - -/* This operand names a vector unit register. The disassembler - prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (0x2000) - -/* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (0x4000) - -/* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0x8000) - -/* Valid range of operand is 0..n rather than 0..n-1. */ -#define PPC_OPERAND_PLUS1 (0x10000) - -/* The POWER and PowerPC assemblers use a few macros. We keep them - with the operands table for simplicity. The macro table is an - array of struct powerpc_macro. */ - -struct powerpc_macro -{ - /* The macro name. */ - const char *name; - - /* The number of operands the macro takes. */ - unsigned int operands; - - /* One bit flags for the opcode. These are used to indicate which - specific processors support the instructions. The values are the - same as those for the struct powerpc_opcode flags field. */ - unsigned long flags; - - /* A format string to turn the macro into a normal instruction. - Each %N in the string is replaced with operand number N (zero - based). */ - const char *format; -}; - -extern const struct powerpc_macro powerpc_macros[]; -extern const int powerpc_num_macros; - -#endif /* PPC_H */ diff --git a/contrib/binutils/include/opcode/s390.h b/contrib/binutils/include/opcode/s390.h deleted file mode 100644 index ae039efe0f27f..0000000000000 --- a/contrib/binutils/include/opcode/s390.h +++ /dev/null @@ -1,147 +0,0 @@ -/* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001, 2003 Free Software Foundation, Inc. - Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef S390_H -#define S390_H - -/* List of instruction sets variations. */ - -enum s390_opcode_mode_val - { - S390_OPCODE_ESA = 0, - S390_OPCODE_ZARCH - }; - -enum s390_opcode_cpu_val - { - S390_OPCODE_G5 = 0, - S390_OPCODE_G6, - S390_OPCODE_Z900, - S390_OPCODE_Z990, - S390_OPCODE_Z9_109, - S390_OPCODE_Z9_EC - }; - -/* The opcode table is an array of struct s390_opcode. */ - -struct s390_opcode - { - /* The opcode name. */ - const char * name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned char opcode[6]; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned char mask[6]; - - /* The opcode length in bytes. */ - int oplen; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[6]; - - /* Bitmask of execution modes this opcode is available for. */ - unsigned int modes; - - /* First cpu this opcode is available for. */ - enum s390_opcode_cpu_val min_cpu; - }; - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct s390_opcode s390_opcodes[]; -extern const int s390_num_opcodes; - -/* A opcode format table for the .insn pseudo mnemonic. */ -extern const struct s390_opcode s390_opformats[]; -extern const int s390_num_opformats; - -/* Values defined for the flags field of a struct powerpc_opcode. */ - -/* The operands table is an array of struct s390_operand. */ - -struct s390_operand - { - /* The number of bits in the operand. */ - int bits; - - /* How far the operand is left shifted in the instruction. */ - int shift; - - /* One bit syntax flags. */ - unsigned long flags; - }; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the powerpc_opcodes table. */ - -extern const struct s390_operand s390_operands[]; - -/* Values defined for the flags field of a struct s390_operand. */ - -/* This operand names a register. The disassembler uses this to print - register names with a leading 'r'. */ -#define S390_OPERAND_GPR 0x1 - -/* This operand names a floating point register. The disassembler - prints these with a leading 'f'. */ -#define S390_OPERAND_FPR 0x2 - -/* This operand names an access register. The disassembler - prints these with a leading 'a'. */ -#define S390_OPERAND_AR 0x4 - -/* This operand names a control register. The disassembler - prints these with a leading 'c'. */ -#define S390_OPERAND_CR 0x8 - -/* This operand is a displacement. */ -#define S390_OPERAND_DISP 0x10 - -/* This operand names a base register. */ -#define S390_OPERAND_BASE 0x20 - -/* This operand names an index register, it can be skipped. */ -#define S390_OPERAND_INDEX 0x40 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define S390_OPERAND_PCREL 0x80 - -/* This operand takes signed values. */ -#define S390_OPERAND_SIGNED 0x100 - -/* This operand is a length. */ -#define S390_OPERAND_LENGTH 0x200 - -/* This operand is optional. Only a single operand at the end of - the instruction may be optional. */ -#define S390_OPERAND_OPTIONAL 0x400 - - #endif /* S390_H */ diff --git a/contrib/binutils/include/opcode/score-datadep.h b/contrib/binutils/include/opcode/score-datadep.h deleted file mode 100644 index 8ef35adc807ef..0000000000000 --- a/contrib/binutils/include/opcode/score-datadep.h +++ /dev/null @@ -1,282 +0,0 @@ -/* score-datadep.h -- Score Instructions data dependency table - Copyright 2006 Free Software Foundation, Inc. - Contributed by: - Mei Ligang (ligang@sunnorth.com.cn) - Pei-Lin Tsai (pltsai@sunplus.com) - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#ifndef SCORE_DATA_DEPENDENCY_H -#define SCORE_DATA_DEPENDENCY_H - -#define INSN_NAME_LEN 16 - -enum insn_type_for_dependency -{ - D_pce, - D_cond_br, - D_cond_mv, - D_cached, - D_cachei, - D_ldst, - D_ldcombine, - D_mtcr, - D_mfcr, - D_mfsr, - D_mftlb, - D_mtptlb, - D_mtrtlb, - D_stlb, - D_all_insn -}; - -struct insn_to_dependency -{ - char *insn_name; - enum insn_type_for_dependency type; -}; - -struct data_dependency -{ - enum insn_type_for_dependency pre_insn_type; - char pre_reg[6]; - enum insn_type_for_dependency cur_insn_type; - char cur_reg[6]; - int bubblenum_7; - int bubblenum_5; - int warn_or_error; /* warning - 0; error - 1 */ -}; - -static const struct insn_to_dependency insn_to_dependency_table[] = -{ - /* pce instruction. */ - {"pce", D_pce}, - /* conditional branch instruction. */ - {"bcs", D_cond_br}, - {"bcc", D_cond_br}, - {"bgtu", D_cond_br}, - {"bleu", D_cond_br}, - {"beq", D_cond_br}, - {"bne", D_cond_br}, - {"bgt", D_cond_br}, - {"ble", D_cond_br}, - {"bge", D_cond_br}, - {"blt", D_cond_br}, - {"bmi", D_cond_br}, - {"bpl", D_cond_br}, - {"bvs", D_cond_br}, - {"bvc", D_cond_br}, - {"bcsl", D_cond_br}, - {"bccl", D_cond_br}, - {"bgtul", D_cond_br}, - {"bleul", D_cond_br}, - {"beql", D_cond_br}, - {"bnel", D_cond_br}, - {"bgtl", D_cond_br}, - {"blel", D_cond_br}, - {"bgel", D_cond_br}, - {"bltl", D_cond_br}, - {"bmil", D_cond_br}, - {"bpll", D_cond_br}, - {"bvsl", D_cond_br}, - {"bvcl", D_cond_br}, - {"bcs!", D_cond_br}, - {"bcc!", D_cond_br}, - {"bgtu!", D_cond_br}, - {"bleu!", D_cond_br}, - {"beq!", D_cond_br}, - {"bne!", D_cond_br}, - {"bgt!", D_cond_br}, - {"ble!", D_cond_br}, - {"bge!", D_cond_br}, - {"blt!", D_cond_br}, - {"bmi!", D_cond_br}, - {"bpl!", D_cond_br}, - {"bvs!", D_cond_br}, - {"bvc!", D_cond_br}, - {"brcs", D_cond_br}, - {"brcc", D_cond_br}, - {"brgtu", D_cond_br}, - {"brleu", D_cond_br}, - {"breq", D_cond_br}, - {"brne", D_cond_br}, - {"brgt", D_cond_br}, - {"brle", D_cond_br}, - {"brge", D_cond_br}, - {"brlt", D_cond_br}, - {"brmi", D_cond_br}, - {"brpl", D_cond_br}, - {"brvs", D_cond_br}, - {"brvc", D_cond_br}, - {"brcsl", D_cond_br}, - {"brccl", D_cond_br}, - {"brgtul", D_cond_br}, - {"brleul", D_cond_br}, - {"breql", D_cond_br}, - {"brnel", D_cond_br}, - {"brgtl", D_cond_br}, - {"brlel", D_cond_br}, - {"brgel", D_cond_br}, - {"brltl", D_cond_br}, - {"brmil", D_cond_br}, - {"brpll", D_cond_br}, - {"brvsl", D_cond_br}, - {"brvcl", D_cond_br}, - {"brcs!", D_cond_br}, - {"brcc!", D_cond_br}, - {"brgtu!", D_cond_br}, - {"brleu!", D_cond_br}, - {"breq!", D_cond_br}, - {"brne!", D_cond_br}, - {"brgt!", D_cond_br}, - {"brle!", D_cond_br}, - {"brge!", D_cond_br}, - {"brlt!", D_cond_br}, - {"brmi!", D_cond_br}, - {"brpl!", D_cond_br}, - {"brvs!", D_cond_br}, - {"brvc!", D_cond_br}, - {"brcsl!", D_cond_br}, - {"brccl!", D_cond_br}, - {"brgtul!", D_cond_br}, - {"brleul!", D_cond_br}, - {"breql!", D_cond_br}, - {"brnel!", D_cond_br}, - {"brgtl!", D_cond_br}, - {"brlel!", D_cond_br}, - {"brgel!", D_cond_br}, - {"brltl!", D_cond_br}, - {"brmil!", D_cond_br}, - {"brpll!", D_cond_br}, - {"brvsl!", D_cond_br}, - {"brvcl!", D_cond_br}, - /* conditional move instruction. */ - {"mvcs", D_cond_mv}, - {"mvcc", D_cond_mv}, - {"mvgtu", D_cond_mv}, - {"mvleu", D_cond_mv}, - {"mveq", D_cond_mv}, - {"mvne", D_cond_mv}, - {"mvgt", D_cond_mv}, - {"mvle", D_cond_mv}, - {"mvge", D_cond_mv}, - {"mvlt", D_cond_mv}, - {"mvmi", D_cond_mv}, - {"mvpl", D_cond_mv}, - {"mvvs", D_cond_mv}, - {"mvvc", D_cond_mv}, - /* move spectial instruction. */ - {"mtcr", D_mtcr}, - {"mftlb", D_mftlb}, - {"mtptlb", D_mtptlb}, - {"mtrtlb", D_mtrtlb}, - {"stlb", D_stlb}, - {"mfcr", D_mfcr}, - {"mfsr", D_mfsr}, - /* cache instruction. */ - {"cache 8", D_cached}, - {"cache 9", D_cached}, - {"cache 10", D_cached}, - {"cache 11", D_cached}, - {"cache 12", D_cached}, - {"cache 13", D_cached}, - {"cache 14", D_cached}, - {"cache 24", D_cached}, - {"cache 26", D_cached}, - {"cache 27", D_cached}, - {"cache 29", D_cached}, - {"cache 30", D_cached}, - {"cache 31", D_cached}, - {"cache 0", D_cachei}, - {"cache 1", D_cachei}, - {"cache 2", D_cachei}, - {"cache 3", D_cachei}, - {"cache 4", D_cachei}, - {"cache 16", D_cachei}, - {"cache 17", D_cachei}, - /* load/store instruction. */ - {"lb", D_ldst}, - {"lbu", D_ldst}, - {"lbu!", D_ldst}, - {"lbup!", D_ldst}, - {"lh", D_ldst}, - {"lhu", D_ldst}, - {"lh!", D_ldst}, - {"lhp!", D_ldst}, - {"lw", D_ldst}, - {"lw!", D_ldst}, - {"lwp!", D_ldst}, - {"sb", D_ldst}, - {"sb!", D_ldst}, - {"sbp!", D_ldst}, - {"sh", D_ldst}, - {"sh!", D_ldst}, - {"shp!", D_ldst}, - {"sw", D_ldst}, - {"sw!", D_ldst}, - {"swp!", D_ldst}, - {"alw", D_ldst}, - {"asw", D_ldst}, - {"push!", D_ldst}, - {"pushhi!", D_ldst}, - {"pop!", D_ldst}, - {"pophi!", D_ldst}, - {"ldc1", D_ldst}, - {"ldc2", D_ldst}, - {"ldc3", D_ldst}, - {"stc1", D_ldst}, - {"stc2", D_ldst}, - {"stc3", D_ldst}, - {"scb", D_ldst}, - {"scw", D_ldst}, - {"sce", D_ldst}, - /* load combine instruction. */ - {"lcb", D_ldcombine}, - {"lcw", D_ldcombine}, - {"lce", D_ldcombine}, -}; - -static const struct data_dependency data_dependency_table[] = -{ - /* Condition register. */ - {D_mtcr, "cr1", D_pce, "", 2, 1, 1}, - {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1}, - {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1}, - /* Status regiser. */ - {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0}, - /* CCR regiser. */ - {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0}, - /* EntryHi/EntryLo register. */ - {D_mftlb, "", D_mtptlb, "", 1, 1, 1}, - {D_mftlb, "", D_mtrtlb, "", 1, 1, 1}, - {D_mftlb, "", D_stlb, "", 1, 1,1}, - {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1}, - {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1}, - /* Index register. */ - {D_stlb, "", D_mtptlb, "", 1, 1, 1}, - {D_stlb, "", D_mftlb, "", 1, 1, 1}, - {D_stlb, "", D_mfcr, "cr8", 2, 2, 1}, - /* Cache. */ - {D_cached, "", D_ldst, "", 1, 1, 0}, - {D_cached, "", D_ldcombine, "", 1, 1, 0}, - {D_cachei, "", D_all_insn, "", 5, 4, 0}, - /* Load combine. */ - {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1}, -}; - -#endif diff --git a/contrib/binutils/include/opcode/score-inst.h b/contrib/binutils/include/opcode/score-inst.h deleted file mode 100644 index e87794f77442e..0000000000000 --- a/contrib/binutils/include/opcode/score-inst.h +++ /dev/null @@ -1,507 +0,0 @@ -/* score-inst.h -- Score Instructions Table - Copyright 2006 Free Software Foundation, Inc. - Contributed by: - Mei Ligang (ligang@sunnorth.com.cn) - Pei-Lin Tsai (pltsai@sunplus.com) - - This file is part of GAS, the GNU Assembler. - - GAS is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS; see the file COPYING. If not, write to the Free - Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA - 02110-1301, USA. */ - -#ifndef SCORE_INST_H -#define SCORE_INST_H - -#define LDST_UNALIGN_MASK 0x0000007f -#define UA_LCB 0x00000060 -#define UA_LCW 0x00000062 -#define UA_LCE 0x00000066 -#define UA_SCB 0x00000068 -#define UA_SCW 0x0000006a -#define UA_SCE 0x0000006e -#define UA_LL 0x0000000c -#define UA_SC 0x0000000e -#define LDST16_RR_MASK 0x0000000f -#define N16_LW 8 -#define N16_LH 9 -#define N16_POP 10 -#define N16_LBU 11 -#define N16_SW 12 -#define N16_SH 13 -#define N16_PUSH 14 -#define N16_SB 15 -#define LDST16_RI_MASK 0x7007 -#define N16_LWP 0x7000 -#define N16_LHP 0x7001 -#define N16_LBUP 0x7003 -#define N16_SWP 0x7004 -#define N16_SHP 0x7005 -#define N16_SBP 0x7007 -#define N16_LIU 0x5000 - -#define OPC_PSEUDOLDST_MASK 0x00000007 - -enum -{ - INSN_LW = 0, - INSN_LH = 1, - INSN_LHU = 2, - INSN_LB = 3, - INSN_SW = 4, - INSN_SH = 5, - INSN_LBU = 6, - INSN_SB = 7, -}; - -/* Sub opcdoe opcode. */ -enum -{ - INSN16_LBU = 11, - INSN16_LH = 9, - INSN16_LW = 8, - INSN16_SB = 15, - INSN16_SH = 13, - INSN16_SW = 12, -}; - -enum -{ - LDST_NOUPDATE = 0, - LDST_PRE = 1, - LDST_POST = 2, -}; - -enum score_insn_type -{ - Rd_I4, - Rd_I5, - Rd_rvalueBP_I5, - Rd_lvalueBP_I5, - Rd_Rs_I5, - x_Rs_I5, - x_I5_x, - Rd_I8, - Rd_Rs_I14, - I15, - Rd_I16, - Rd_rvalueRs_SI10, - Rd_lvalueRs_SI10, - Rd_rvalueRs_preSI12, - Rd_rvalueRs_postSI12, - Rd_lvalueRs_preSI12, - Rd_lvalueRs_postSI12, - Rd_Rs_SI14, - Rd_rvalueRs_SI15, - Rd_lvalueRs_SI15, - Rd_SI16, - PC_DISP8div2, - PC_DISP11div2, - PC_DISP19div2, - PC_DISP24div2, - Rd_Rs_Rs, - x_Rs_x, - x_Rs_Rs, - Rd_Rs_x, - Rd_x_Rs, - Rd_x_x, - Rd_Rs, - Rd_HighRs, - Rd_lvalueRs, - Rd_rvalueRs, - Rd_lvalue32Rs, - Rd_rvalue32Rs, - x_Rs, - NO_OPD, - NO16_OPD, - OP5_rvalueRs_SI15, - I5_Rs_Rs_I5_OP5, - x_rvalueRs_post4, - Rd_rvalueRs_post4, - Rd_x_I5, - Rd_lvalueRs_post4, - x_lvalueRs_post4, - Rd_LowRs, - Rd_Rs_Rs_imm, - Insn_Type_PCE, - Insn_Type_SYN, - Insn_GP, - Insn_PIC, - Insn_internal, -}; - -enum score_data_type -{ - _IMM4 = 0, - _IMM5, - _IMM8, - _IMM14, - _IMM15, - _IMM16, - _SIMM10 = 6, - _SIMM12, - _SIMM14, - _SIMM15, - _SIMM16, - _SIMM14_NEG = 11, - _IMM16_NEG, - _SIMM16_NEG, - _IMM20, - _IMM25, - _DISP8div2 = 16, - _DISP11div2, - _DISP19div2, - _DISP24div2, - _VALUE, - _VALUE_HI16, - _VALUE_LO16, - _VALUE_LDST_LO16 = 23, - _SIMM16_LA, - _IMM5_RSHIFT_1, - _IMM5_RSHIFT_2, - _SIMM16_LA_POS, - _IMM5_RANGE_8_31, - _IMM10_RSHIFT_2, - _GP_IMM15 = 30, - _GP_IMM14 = 31, - _SIMM16_pic = 42, /* Index in score_df_range. */ - _IMM16_LO16_pic = 43, - _IMM16_pic = 44, -}; - -#define REG_TMP 1 - -#define OP_REG_TYPE (1 << 6) -#define OP_IMM_TYPE (1 << 7) -#define OP_SH_REGD (OP_REG_TYPE |20) -#define OP_SH_REGS1 (OP_REG_TYPE |15) -#define OP_SH_REGS2 (OP_REG_TYPE |10) -#define OP_SH_I (OP_IMM_TYPE | 1) -#define OP_SH_RI15 (OP_IMM_TYPE | 0) -#define OP_SH_I12 (OP_IMM_TYPE | 3) -#define OP_SH_DISP24 (OP_IMM_TYPE | 1) -#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) -#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) -#define OP_SH_I5 (OP_IMM_TYPE |10) -#define OP_SH_I10 (OP_IMM_TYPE | 5) -#define OP_SH_COPID (OP_IMM_TYPE | 5) -#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) -#define OP_SH_I15 (OP_IMM_TYPE |10) - -#define OP16_SH_REGD (OP_REG_TYPE | 8) -#define OP16_SH_REGS1 (OP_REG_TYPE | 4) -#define OP16_SH_I45 (OP_IMM_TYPE | 3) -#define OP16_SH_I8 (OP_IMM_TYPE | 0) -#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) -#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) - -struct datafield_range -{ - int data_type; - int bits; - int range[2]; -}; - -struct datafield_range score_df_range[] = -{ - {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */ - {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */ - {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */ - {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */ - {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ - {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ - {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */ - {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */ - {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */ - {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */ - {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */ - {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */ - {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM20, 20, {0, (1 << 20) - 1}}, - {_IMM25, 25, {0, (1 << 25) - 1}}, - {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */ - {_DISP11div2, 11, {0, 0}}, - {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */ - {_DISP24div2, 24, {0, 0}}, - {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}}, - {_VALUE_HI16, 16, {0, (1 << 16) - 1}}, - {_VALUE_LO16, 16, {0, (1 << 16) - 1}}, - {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}}, - {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */ - {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */ - {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ - {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */ - {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */ - {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */ - {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */ - {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */ - {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */ - {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */ - {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */ - {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */ - {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */ - {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */ - {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */ - {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ - {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ - {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ -}; - -struct shift_bitmask -{ - int opd_type; - int opd_num; - struct datafield_range *df_range; - int sh[4]; - long fieldbits[4]; -}; - -struct shift_bitmask score_sh_bits_map[] = -{ - { - Rd_I4, 2, &score_df_range[_IMM4], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_rvalueBP_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_lvalueBP_I5, 2, &score_df_range[_IMM5], - {OP16_SH_REGD, OP16_SH_I45, 0, 0}, - {0xf, 0x1f, 0, 0}, - }, - { - Rd_Rs_I5, 3, &score_df_range[_IMM5], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0}, - {0x1f, 0x1f, 0x1f, 0}, - }, - { - x_Rs_I5, 2, &score_df_range[_IMM5], - {OP_SH_REGS1, OP_SH_I5, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_I5_x, 1, &score_df_range[_IMM5], - {OP_SH_TRAPI5, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - Rd_I8, 2, &score_df_range[_IMM8], - {OP16_SH_REGD, OP16_SH_I8, 0, 0}, - {0xf, 0xff, 0, 0}, - }, - { - Rd_Rs_I14, 3, &score_df_range[_IMM14], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, - {0x1f, 0x1f, 0x3fff, 0}, - }, - { - I15, 1, &score_df_range[_IMM15], - {OP_SH_I15, 0, 0, 0}, - {0x7fff, 0, 0, 0}, - }, - { - Rd_I16, 2, &score_df_range[_IMM16], - {OP_SH_REGD, OP_SH_I, 0, 0}, - {0x1f, 0xffff, 0, 0}, - }, - { - Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, - {0x1f, 0x1f, 0x3ff, 0}, - }, - { - Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, - {0x1f, 0x1f, 0x3ff, 0}, - }, - { - Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, - {0xf, 0xf, 0xfff, 0}, - }, - { - Rd_Rs_SI14, 3, &score_df_range[_SIMM14], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, - {0x1f, 0x1f, 0x3fff, 0}, - }, - { - Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, - {0x1f, 0x1f, 0x7fff, 0}, - }, - { - Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15], - {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, - {0x1f, 0x1f, 0x7fff, 0}, - }, - { - Rd_SI16, 2, &score_df_range[_SIMM16], - {OP_SH_REGD, OP_SH_I, 0, 0}, - {0x1f, 0xffff, 0, 0}, - }, - { - PC_DISP8div2, 1, &score_df_range[_DISP8div2], - {OP16_SH_DISP8, 0, 0, 0}, - {0xff, 0, 0, 0}, - }, - { - PC_DISP11div2, 1, &score_df_range[_DISP11div2], - {OP16_SH_DISP11, 0, 0, 0}, - {0x7ff, 0, 0, 0}, - }, - { - PC_DISP19div2, 2, &score_df_range[_DISP19div2], - {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0}, - {0x3ff, 0x1ff, 0, 0}, - }, - { - PC_DISP24div2, 1, &score_df_range[_DISP24div2], - {OP_SH_DISP24, 0, 0, 0}, - {0xffffff, 0, 0, 0}, - }, - { - Rd_Rs_Rs, 3, NULL, - {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0}, - {0x1f, 0x1f, 0x1f, 0} - }, - { - Rd_Rs_x, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_x_Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS2, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_x_x, 1, NULL, - {OP_SH_REGD, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - x_Rs_Rs, 2, NULL, - {OP_SH_REGS1, OP_SH_REGS2, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_Rs_x, 1, NULL, - {OP_SH_REGS1, 0, 0, 0}, - {0x1f, 0, 0, 0}, - }, - { - Rd_Rs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_HighRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0x1f, 0}, - }, - { - Rd_rvalueRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0}, - }, - { - Rd_lvalueRs, 2, NULL, - {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, - {0xf, 0xf, 0, 0} - }, - { - Rd_lvalue32Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - Rd_rvalue32Rs, 2, NULL, - {OP_SH_REGD, OP_SH_REGS1, 0, 0}, - {0x1f, 0x1f, 0, 0}, - }, - { - x_Rs, 1, NULL, - {OP16_SH_REGS1, 0, 0, 0}, - {0xf, 0, 0, 0}, - }, - { - NO_OPD, 0, NULL, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - }, - { - NO16_OPD, 0, NULL, - {0, 0, 0, 0}, - {0, 0, 0, 0}, - }, -}; - -struct asm_opcode -{ - /* Instruction name. */ - const char *template; - - /* Instruction Opcode. */ - unsigned long value; - - /* Instruction bit mask. */ - unsigned long bitmask; - - /* Relax instruction opcode. 0x8000 imply no relaxation. */ - unsigned long relax_value; - - /* Instruction type. */ - enum score_insn_type type; - - /* Function to call to parse args. */ - void (*parms) (char *); -}; - -enum insn_class -{ - INSN_CLASS_16, - INSN_CLASS_32, - INSN_CLASS_PCE, - INSN_CLASS_SYN -}; - -#endif diff --git a/contrib/binutils/include/opcode/sparc.h b/contrib/binutils/include/opcode/sparc.h deleted file mode 100644 index 9e238be93a630..0000000000000 --- a/contrib/binutils/include/opcode/sparc.h +++ /dev/null @@ -1,237 +0,0 @@ -/* Definitions for opcode table for the sparc. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002, - 2003, 2005 Free Software Foundation, Inc. - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ - -#include "ansidecl.h" - -/* The SPARC opcode table (and other related data) is defined in - the opcodes library in sparc-opc.c. If you change anything here, make - sure you fix up that file, and vice versa. */ - - /* FIXME-someday: perhaps the ,a's and such should be embedded in the - instruction's name rather than the args. This would make gas faster, pinsn - slower, but would mess up some macros a bit. xoxorich. */ - -/* List of instruction sets variations. - These values are such that each element is either a superset of a - preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P - returns non-zero. - The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. - Don't change this without updating sparc-opc.c. */ - -enum sparc_opcode_arch_val -{ - SPARC_OPCODE_ARCH_V6 = 0, - SPARC_OPCODE_ARCH_V7, - SPARC_OPCODE_ARCH_V8, - SPARC_OPCODE_ARCH_SPARCLET, - SPARC_OPCODE_ARCH_SPARCLITE, - /* V9 variants must appear last. */ - SPARC_OPCODE_ARCH_V9, - SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */ - SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */ - SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */ -}; - -/* The highest architecture in the table. */ -#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) - -/* Given an enum sparc_opcode_arch_val, return the bitmask to use in - insn encoding/decoding. */ -#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) - -/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ -#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) - -/* Table of cpu variants. */ - -typedef struct sparc_opcode_arch -{ - const char *name; - /* Mask of sparc_opcode_arch_val's supported. - EG: For v7 this would be - (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). - These are short's because sparc_opcode.architecture is. */ - short supported; -} sparc_opcode_arch; - -extern const struct sparc_opcode_arch sparc_opcode_archs[]; - -/* Given architecture name, look up it's sparc_opcode_arch_val value. */ -extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *); - -/* Return the bitmask of supported architectures for ARCH. */ -#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) - -/* Non-zero if ARCH1 conflicts with ARCH2. - IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ -#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ - (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH1)) \ - && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ - != SPARC_OPCODE_SUPPORTED (ARCH2))) - -/* Structure of an opcode table entry. */ - -typedef struct sparc_opcode -{ - const char *name; - unsigned long match; /* Bits that must be set. */ - unsigned long lose; /* Bits that must not be set. */ - const char *args; - /* This was called "delayed" in versions before the flags. */ - char flags; - short architecture; /* Bitmask of sparc_opcode_arch_val's. */ -} sparc_opcode; - -#define F_DELAYED 1 /* Delayed branch. */ -#define F_ALIAS 2 /* Alias for a "real" instruction. */ -#define F_UNBR 4 /* Unconditional branch. */ -#define F_CONDBR 8 /* Conditional branch. */ -#define F_JSR 16 /* Subroutine call. */ -#define F_FLOAT 32 /* Floating point instruction (not a branch). */ -#define F_FBR 64 /* Floating point branch. */ -/* FIXME: Add F_ANACHRONISTIC flag for v9. */ - -/* All sparc opcodes are 32 bits, except for the `set' instruction (really a - macro), which is 64 bits. It is handled as a special case. - - The match component is a mask saying which bits must match a particular - opcode in order for an instruction to be an instance of that opcode. - - The args component is a string containing one character for each operand of the - instruction. - - Kinds of operands: - # Number used by optimizer. It is ignored. - 1 rs1 register. - 2 rs2 register. - d rd register. - e frs1 floating point register. - v frs1 floating point register (double/even). - V frs1 floating point register (quad/multiple of 4). - f frs2 floating point register. - B frs2 floating point register (double/even). - R frs2 floating point register (quad/multiple of 4). - g frsd floating point register. - H frsd floating point register (double/even). - J frsd floating point register (quad/multiple of 4). - b crs1 coprocessor register - c crs2 coprocessor register - D crsd coprocessor register - m alternate space register (asr) in rd - M alternate space register (asr) in rs1 - h 22 high bits. - X 5 bit unsigned immediate - Y 6 bit unsigned immediate - 3 SIAM mode (3 bits). (v9b) - K MEMBAR mask (7 bits). (v9) - j 10 bit Immediate. (v9) - I 11 bit Immediate. (v9) - i 13 bit Immediate. - n 22 bit immediate. - k 2+14 bit PC relative immediate. (v9) - G 19 bit PC relative immediate. (v9) - l 22 bit PC relative immediate. - L 30 bit PC relative immediate. - a Annul. The annul bit is set. - A Alternate address space. Stored as 8 bits. - C Coprocessor state register. - F floating point state register. - p Processor state register. - N Branch predict clear ",pn" (v9) - T Branch predict set ",pt" (v9) - z %icc. (v9) - Z %xcc. (v9) - q Floating point queue. - r Single register that is both rs1 and rd. - O Single register that is both rs2 and rd. - Q Coprocessor queue. - S Special case. - t Trap base register. - w Window invalid mask register. - y Y register. - u sparclet coprocessor registers in rd position - U sparclet coprocessor registers in rs1 position - E %ccr. (v9) - s %fprs. (v9) - P %pc. (v9) - W %tick. (v9) - o %asi. (v9) - 6 %fcc0. (v9) - 7 %fcc1. (v9) - 8 %fcc2. (v9) - 9 %fcc3. (v9) - ! Privileged Register in rd (v9) - ? Privileged Register in rs1 (v9) - * Prefetch function constant. (v9) - x OPF field (v9 impdep). - 0 32/64 bit immediate for set or setx (v9) insns - _ Ancillary state register in rd (v9a) - / Ancillary state register in rs1 (v9a) - - The following chars are unused: (note: ,[] are used as punctuation) - [45]. */ - -#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */ -#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */ -#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */ -#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */ -#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */ -#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */ -#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */ -#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */ -#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */ -#define F1(x) (OP (x)) -#define DISP30(x) ((x) & 0x3fffffff) -#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */ -#define RS2(x) ((x) & 0x1f) /* Rs2 field. */ -#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */ -#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ -#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */ -#define ASI_RS2(x) (SIMM13 (x)) -#define MEMBAR(x) ((x) & 0x7f) -#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */ - -#define ANNUL (1 << 29) -#define BPRED (1 << 19) /* V9. */ -#define IMMED F3I (1) -#define RD_G0 RD (~0) -#define RS1_G0 RS1 (~0) -#define RS2_G0 RS2 (~0) - -extern const struct sparc_opcode sparc_opcodes[]; -extern const int sparc_num_opcodes; - -extern int sparc_encode_asi (const char *); -extern const char *sparc_decode_asi (int); -extern int sparc_encode_membar (const char *); -extern const char *sparc_decode_membar (int); -extern int sparc_encode_prefetch (const char *); -extern const char *sparc_decode_prefetch (int); -extern int sparc_encode_sparclet_cpreg (const char *); -extern const char *sparc_decode_sparclet_cpreg (int); - -/* Local Variables: - fill-column: 131 - comment-column: 0 - End: */ - diff --git a/contrib/binutils/include/opcode/spu-insns.h b/contrib/binutils/include/opcode/spu-insns.h deleted file mode 100644 index 237d8ab810552..0000000000000 --- a/contrib/binutils/include/opcode/spu-insns.h +++ /dev/null @@ -1,417 +0,0 @@ -/* SPU ELF support for BFD. - - Copyright 2006, 2007 Free Software Foundation, Inc. - - This file is part of BFD, the Binary File Descriptor library. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - -/* SPU Opcode Table - --=-=-= FORMAT =-=-=- - - +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ -RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT | - +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ - 0 3 1 1 2 3 0 1 1 2 3 - 0 7 4 1 0 7 4 1 - - +-----------+--------+-------+-------+ +---------+----------+-------+-------+ -RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT | - +-----------+--------+-------+-------+ +---------+----------+-------+-------+ - 0 9 1 2 3 0 7 1 2 3 - 7 4 1 7 4 1 - - +----------+-----------------+-------+ +--------+-------------------+-------+ -RI16 | op | I16 | RT | RI18 | op | I18 | RT | - +----------+-----------------+-------+ +--------+-------------------+-------+ - 0 8 2 3 0 6 2 3 - 4 1 4 1 - - +------------+-------+-------+-------+ +-------+--+-----------------+-------+ -RR | op | RB | RA | RT | LBT | op |RO| I16 | RO | - +------------+-------+-------+-------+ +-------+--+-----------------+-------+ - 0 1 1 2 3 0 6 8 2 3 - 0 7 4 1 4 1 - - +------------+----+--+-------+-------+ - LBTI | op | // |RO| RA | RO | - +------------+----+--+-------+-------+ - 0 1 1 1 2 3 - 0 5 7 4 1 - --=-=-= OPCODE =-=-=- - -OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this -case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700, -since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000. - --=-=-= ASM_FORMAT =-=-=- - -RRR category RI7 category - ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4 - ASM_RI7 mnemonic RT, RA, I7 - -RI8 category RI10 category - ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10 - ASM_RI10 mnemonic RT, RA, R10 - ASM_RI10IDX mnemonic RT, I10(RA) - -RI16 category RI18 category - ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18 - ASM_RI16 mnemonic RT, I16 - ASM_RI16W mnemonic RT, I16W - -RR category LBT category - ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg - ASM_MTSPR mnemonic SA, RT - ASM_NOOP mnemonic LBTI category - ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA - ASM_RAB mnemonic RA, RB - ASM_RDCH mnemonic RT, CA - ASM_RR mnemonic RT, RA, RB - ASM_RT mnemonic RT - ASM_RTA mnemonic RT, RA - ASM_WRCH mnemonic CA, RT - -Note that RRR instructions have the names for RC and RT reversed from -what's in the ISA, in order to put RT in the same position it appears -for other formats. - --=-=-= DEPENDENCY =-=-=- - -DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target. -The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits. -If the digit is 0, this means the corresponding register is not used in the instruction. -If the digit is 1, this means the corresponding register is used as a source in the instruction. -If the digit is 2, this means the corresponding register is used as a target in the instruction. -If the digit is 3, this means the corresponding register is used as both source and target in the instruction. -For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are -used as sources and RT is the target. - --=-=-= PIPE =-=-=- - -This field shows which execution pipe is used for the instruction - -pipe0 execution pipelines: - FP6 SP floating pipeline - FP7 integer operations executed in SP floating pipeline - FPD DP floating pipeline - FX2 FXU pipeline - FX3 Rotate/Shift pipeline - FXB Byte pipeline - NOP No pipeline - -pipe1 execution pipelines: - BR Branch pipeline - LNOP No pipeline - LS Load/Store pipeline - SHUF Shuffle pipeline - SPR SPR/CH pipeline - -*/ - -#define _A0() {0} -#define _A1(a) {1,a} -#define _A2(a,b) {2,a,b} -#define _A3(a,b,c) {3,a,b,c} -#define _A4(a,b,c,d) {4,a,b,c,d} - -/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */ -/* 0[RC][RB][RA][RT] */ -/* 1:src, 2:target */ - -APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ -APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ -APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ -APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ -APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */ -APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */ -APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */ -APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ -APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ -APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ -APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ -APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ -APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ -APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ -APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ -APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ -APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */ -APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */ -APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ -APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ -APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ -APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ -APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */ -APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */ -APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ -APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ -APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */ -APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ -APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ -APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ -APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ -APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ -APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ -APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */ -APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */ -APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */ -APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */ -APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */ -APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */ -APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */ -APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ -APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */ -APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */ -APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */ -APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */ -APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */ -APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */ -APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */ -APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */ -APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */ -APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */ -APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */ -APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */ -APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */ -APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */ -APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */ -APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */ -APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */ -APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */ -APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */ -APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ -APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ -APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ -APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ -APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ -APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ -APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ -APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ -APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ -APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ -APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ -APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ -APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ -APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ -APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ -APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ -APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */ -APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */ -APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */ -APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */ -APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */ -APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */ -APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ -APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ -APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ -APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ -APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ -APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ -APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ -APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ -APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ -APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ -APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ -APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ -APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ -APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */ -APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ -APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ -APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ -APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */ -APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ -APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ -APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ -APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ -APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ -APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ -APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ -APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ -APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ -APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ -APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ -APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ -APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ -APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ -APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ -APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */ -APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */ -APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */ -APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */ -APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */ -APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */ -APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */ -APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */ -APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */ -APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */ -APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */ -APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */ -APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */ -APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */ -APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */ -APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */ -APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */ -APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */ -APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */ -APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */ -APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */ -APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */ -APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */ -APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */ -APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ -APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ -APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ -APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ -APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ -APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ -APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ -APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ -APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ -APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ -APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */ -APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */ -APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */ -APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */ -APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */ -APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */ -APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */ -APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */ -APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */ -APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */ -APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */ -/* for system function call, this uses op-code of mtspr */ -APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */ -/* -pseudo instruction: -system call -value of I9 operation -0 halt -1 rt[0] = open(MEM[ra[0]], ra[1]) -2 rt[0] = close(ra[0]) -3 rt[0] = read(ra[0], MEM[ra[1]], ra[2]) -4 rt[0] = write(ra[0], MEM[ra[1]], ra[2]) -5 printf(MEM[ra[0]], ra[1], ra[2], ra[3]) -42 rt[0] = clock() -52 rt[0] = lseek(ra0, ra1, ra2) - -*/ - - -/* new multiprecision add/sub */ -APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ -APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ -APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ -APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ -APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ -APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ - -/* - -The following ops are a subset of above except with feature bits set. -Feature bits are bits 11-17 of the instruction: - - 11 - C & P feature bit - 12 - disable interrupts - 13 - enable interrupts - -*/ -APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ -APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ -APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ -APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ -APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ -APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ - -/* Synonyms required by the AS manual. */ -APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */ -APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ -APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ -APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ -APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ -APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ -APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ -APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ -APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ -APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ - -/* New soma double-float insns. */ -APUOP(M_DFCEQ, RR, 0x3c3, "dfceq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCEQ RT<-(RA=RB) */ -APUOP(M_DFCMEQ, RR, 0x3cb, "dfcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMEQ RT<-(|RA|=|RB|) */ -APUOP(M_DFCGT, RR, 0x2c3, "dfcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCGT RT<-(RA>RB) */ -APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */ -APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */ - -#undef _A0 -#undef _A1 -#undef _A2 -#undef _A3 -#undef _A4 diff --git a/contrib/binutils/include/opcode/spu.h b/contrib/binutils/include/opcode/spu.h deleted file mode 100644 index 975b1fdde4bd3..0000000000000 --- a/contrib/binutils/include/opcode/spu.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPU ELF support for BFD. - - Copyright 2006 Free Software Foundation, Inc. - - This file is part of GDB, GAS, and the GNU binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software Foundation, - Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ - - -/* These two enums are from rel_apu/common/spu_asm_format.h */ -/* definition of instruction format */ -typedef enum { - RRR, - RI18, - RI16, - RI10, - RI8, - RI7, - RR, - LBT, - LBTI, - IDATA, - UNKNOWN_IFORMAT -} spu_iformat; - -/* These values describe assembly instruction arguments. They indicate - * how to encode, range checking and which relocation to use. */ -typedef enum { - A_T, /* register at pos 0 */ - A_A, /* register at pos 7 */ - A_B, /* register at pos 14 */ - A_C, /* register at pos 21 */ - A_S, /* special purpose register at pos 7 */ - A_H, /* channel register at pos 7 */ - A_P, /* parenthesis, this has to separate regs from immediates */ - A_S3, - A_S6, - A_S7N, - A_S7, - A_U7A, - A_U7B, - A_S10B, - A_S10, - A_S11, - A_S11I, - A_S14, - A_S16, - A_S18, - A_R18, - A_U3, - A_U5, - A_U6, - A_U7, - A_U14, - A_X16, - A_U18, - A_MAX -} spu_aformat; - -enum spu_insns { -#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ - TAG, -#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ - TAG, -#include "opcode/spu-insns.h" -#undef APUOP -#undef APUOPFB - M_SPU_MAX -}; - -struct spu_opcode -{ - spu_iformat insn_type; - unsigned int opcode; - char *mnemonic; - int arg[5]; -}; - -#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) -#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) - -#define DECODE_INSN_RT(insn) (insn & 0x7f) -#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) -#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) -#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) - -#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) -#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) - -/* For branching, immediate loads, hbr and lqa/stqa. */ -#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) -#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) - -/* for stop */ -#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) - -/* For ila */ -#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) -#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) - -/* For rotate and shift and generate control mask */ -#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) -#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) - -/* For float <-> int conversion */ -#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) -#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) - -/* For hbr */ -#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) -#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) - |