diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-07-23 20:41:05 +0000 |
| commit | 01095a5d43bbfde13731688ddcf6048ebb8b7721 (patch) | |
| tree | 4def12e759965de927d963ac65840d663ef9d1ea /lib/Target/AMDGPU/SIInstrInfo.td | |
| parent | f0f4822ed4b66e3579e92a89f368f8fb860e218e (diff) | |
Notes
Diffstat (limited to 'lib/Target/AMDGPU/SIInstrInfo.td')
| -rw-r--r-- | lib/Target/AMDGPU/SIInstrInfo.td | 1852 |
1 files changed, 1309 insertions, 543 deletions
diff --git a/lib/Target/AMDGPU/SIInstrInfo.td b/lib/Target/AMDGPU/SIInstrInfo.td index 8735277149a63..253cc32b27e4b 100644 --- a/lib/Target/AMDGPU/SIInstrInfo.td +++ b/lib/Target/AMDGPU/SIInstrInfo.td @@ -7,9 +7,9 @@ // //===----------------------------------------------------------------------===// def isCI : Predicate<"Subtarget->getGeneration() " - ">= AMDGPUSubtarget::SEA_ISLANDS">; + ">= SISubtarget::SEA_ISLANDS">; def isCIOnly : Predicate<"Subtarget->getGeneration() ==" - "AMDGPUSubtarget::SEA_ISLANDS">, + "SISubtarget::SEA_ISLANDS">, AssemblerPredicate <"FeatureSeaIslands">; def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">; @@ -69,6 +69,11 @@ class sopk <bits<5> si, bits<5> vi = si> { field bits<5> VI = vi; } +class dsop <bits<8> si, bits<8> vi = si> { + field bits<8> SI = si; + field bits<8> VI = vi; +} + // Specify an SMRD opcode for SI and SMEM opcode for VI // FIXME: This should really be bits<5> si, Tablegen crashes if @@ -78,9 +83,9 @@ class smrd<bits<8> si, bits<8> vi = si> { field bits<8> VI = vi; } -// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum -// in AMDGPUInstrInfo.cpp -def SISubtarget { +// Execpt for the NONE field, this must be kept in sync with the +// SIEncodingFamily enum in AMDGPUInstrInfo.cpp +def SIEncodingFamily { int NONE = -1; int SI = 0; int VI = 1; @@ -95,6 +100,14 @@ def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT", [SDNPMayLoad, SDNPMemOperand] >; +def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2, + [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain] +>; + +def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2, + [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain] +>; + def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTypeProfile<0, 13, [SDTCisVT<0, v4i32>, // rsrc(SGPR) @@ -120,7 +133,7 @@ def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT", >; class SDSample<string opcode> : SDNode <opcode, - SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v32i8>, + SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>, SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]> >; @@ -129,9 +142,8 @@ def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">; def SIsampled : SDSample<"AMDGPUISD::SAMPLED">; def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">; -def SIconstdata_ptr : SDNode< - "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, i64>, - SDTCisVT<0, i64>]> +def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET", + SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>]> >; //===----------------------------------------------------------------------===// @@ -140,12 +152,14 @@ def SIconstdata_ptr : SDNode< class flat_ld <SDPatternOperator ld> : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ - return isFlatLoad(dyn_cast<LoadSDNode>(N)) || - isGlobalLoad(dyn_cast<LoadSDNode>(N)) || - isConstantLoad(cast<LoadSDNode>(N), -1); + const MemSDNode *LD = cast<MemSDNode>(N); + return LD->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS || + LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || + LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS; }]>; def flat_load : flat_ld <load>; +def atomic_flat_load : flat_ld<atomic_load>; def flat_az_extloadi8 : flat_ld <az_extloadi8>; def flat_sextloadi8 : flat_ld <sextloadi8>; def flat_az_extloadi16 : flat_ld <az_extloadi16>; @@ -153,26 +167,50 @@ def flat_sextloadi16 : flat_ld <sextloadi16>; class flat_st <SDPatternOperator st> : PatFrag<(ops node:$val, node:$ptr), (st node:$val, node:$ptr), [{ - return isFlatStore(dyn_cast<StoreSDNode>(N)) || - isGlobalStore(dyn_cast<StoreSDNode>(N)); + const MemSDNode *ST = cast<MemSDNode>(N); + return ST->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS || + ST->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS; }]>; def flat_store: flat_st <store>; +def atomic_flat_store: flat_st <atomic_store>; def flat_truncstorei8 : flat_st <truncstorei8>; def flat_truncstorei16 : flat_st <truncstorei16>; +class MubufLoad <SDPatternOperator op> : PatFrag < + (ops node:$ptr), (op node:$ptr), [{ -def mubuf_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ - return isGlobalLoad(cast<LoadSDNode>(N)) || - isConstantLoad(cast<LoadSDNode>(N), -1); + const MemSDNode *LD = cast<MemSDNode>(N); + return LD->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS || + LD->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS; }]>; +def mubuf_load : MubufLoad <load>; +def mubuf_az_extloadi8 : MubufLoad <az_extloadi8>; +def mubuf_sextloadi8 : MubufLoad <sextloadi8>; +def mubuf_az_extloadi16 : MubufLoad <az_extloadi16>; +def mubuf_sextloadi16 : MubufLoad <sextloadi16>; + +def mubuf_load_atomic : MubufLoad <atomic_load>; + def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ - return isConstantLoad(cast<LoadSDNode>(N), -1) && - static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N); + auto Ld = cast<LoadSDNode>(N); + return Ld->getAlignment() >= 4 && + Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS && + static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N); }]>; //===----------------------------------------------------------------------===// +// PatFrags for global memory operations +//===----------------------------------------------------------------------===// + +def atomic_inc_global : global_binary_atomic_op<SIatomic_inc>; +def atomic_dec_global : global_binary_atomic_op<SIatomic_dec>; + +def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>; +def atomic_dec_flat : flat_binary_atomic_op<SIatomic_dec>; + +//===----------------------------------------------------------------------===// // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1 // to be glued to the memory instructions. //===----------------------------------------------------------------------===// @@ -182,7 +220,7 @@ def SIld_local : SDNode <"ISD::LOAD", SDTLoad, >; def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{ - return isLocalLoad(cast<LoadSDNode>(N)); + return cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS; }]>; def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{ @@ -219,7 +257,7 @@ def SIst_local : SDNode <"ISD::STORE", SDTStore, def si_st_local : PatFrag < (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{ - return isLocalStore(cast<StoreSDNode>(N)); + return cast<StoreSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS; }]>; def si_store_local : PatFrag < @@ -247,9 +285,34 @@ def si_truncstore_local_i16 : PatFrag < return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16; }]>; -multiclass SIAtomicM0Glue2 <string op_name> { +def si_setcc_uniform : PatFrag < + (ops node:$lhs, node:$rhs, node:$cond), + (setcc node:$lhs, node:$rhs, node:$cond), [{ + for (SDNode *Use : N->uses()) { + if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg) + return false; + + unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg(); + if (Reg != AMDGPU::SCC) + return false; + } + return true; +}]>; + +def si_uniform_br : PatFrag < + (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{ + return isUniformBr(N); +}]>; + +def si_uniform_br_scc : PatFrag < + (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{ + return isCBranchSCC(N); +}]>; + +multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0> { - def _glue : SDNode <"ISD::ATOMIC_"#op_name, SDTAtomic2, + def _glue : SDNode < + !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, SDTAtomic2, [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue] >; @@ -257,11 +320,13 @@ multiclass SIAtomicM0Glue2 <string op_name> { } defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">; +defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">; +defm si_atomic_inc : SIAtomicM0Glue2 <"INC", 1>; +defm si_atomic_dec : SIAtomicM0Glue2 <"DEC", 1>; defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">; defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">; defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">; defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">; -defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">; defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">; defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">; defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">; @@ -347,6 +412,10 @@ def IMM16bit : PatLeaf <(imm), [{return isUInt<16>(N->getZExtValue());}] >; +def SIMM16bit : PatLeaf <(imm), + [{return isInt<16>(N->getSExtValue());}] +>; + def IMM20bit : PatLeaf <(imm), [{return isUInt<20>(N->getZExtValue());}] >; @@ -369,7 +438,7 @@ class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{ }]>; class SGPRImm <dag frag> : PatLeaf<frag, [{ - if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) { + if (Subtarget->getGeneration() < SISubtarget::SOUTHERN_ISLANDS) { return false; } const SIRegisterInfo *SIRI = @@ -402,188 +471,133 @@ def sopp_brtarget : Operand<OtherVT> { let ParserMatchClass = SoppBrTarget; } -def const_ga : Operand<iPTR>; +def si_ga : Operand<iPTR>; -include "SIInstrFormats.td" -include "VIInstrFormats.td" - -def MubufOffsetMatchClass : AsmOperandClass { - let Name = "MubufOffset"; - let ParserMethod = "parseMubufOptionalOps"; - let RenderMethod = "addImmOperands"; +def InterpSlot : Operand<i32> { + let PrintMethod = "printInterpSlot"; } -class DSOffsetBaseMatchClass <string parser> : AsmOperandClass { - let Name = "DSOffset"#parser; - let ParserMethod = parser; +def SendMsgMatchClass : AsmOperandClass { + let Name = "SendMsg"; + let PredicateMethod = "isSendMsg"; + let ParserMethod = "parseSendMsgOp"; let RenderMethod = "addImmOperands"; - let PredicateMethod = "isDSOffset"; } -def DSOffsetMatchClass : DSOffsetBaseMatchClass <"parseDSOptionalOps">; -def DSOffsetGDSMatchClass : DSOffsetBaseMatchClass <"parseDSOffsetOptional">; - -def DSOffset01MatchClass : AsmOperandClass { - let Name = "DSOffset1"; - let ParserMethod = "parseDSOff01OptionalOps"; - let RenderMethod = "addImmOperands"; - let PredicateMethod = "isDSOffset01"; +def SendMsgImm : Operand<i32> { + let PrintMethod = "printSendMsg"; + let ParserMatchClass = SendMsgMatchClass; } -class GDSBaseMatchClass <string parser> : AsmOperandClass { - let Name = "GDS"#parser; - let PredicateMethod = "isImm"; - let ParserMethod = parser; +def SWaitMatchClass : AsmOperandClass { + let Name = "SWaitCnt"; let RenderMethod = "addImmOperands"; + let ParserMethod = "parseSWaitCntOps"; } -def GDSMatchClass : GDSBaseMatchClass <"parseDSOptionalOps">; -def GDS01MatchClass : GDSBaseMatchClass <"parseDSOff01OptionalOps">; - -class GLCBaseMatchClass <string parser> : AsmOperandClass { - let Name = "GLC"#parser; - let PredicateMethod = "isImm"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; +def WAIT_FLAG : Operand <i32> { + let ParserMatchClass = SWaitMatchClass; + let PrintMethod = "printWaitFlag"; } -def GLCMubufMatchClass : GLCBaseMatchClass <"parseMubufOptionalOps">; -def GLCFlatMatchClass : GLCBaseMatchClass <"parseFlatOptionalOps">; +include "SIInstrFormats.td" +include "VIInstrFormats.td" -class SLCBaseMatchClass <string parser> : AsmOperandClass { - let Name = "SLC"#parser; - let PredicateMethod = "isImm"; - let ParserMethod = parser; +class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass { + let Name = "Imm"#CName; + let PredicateMethod = "is"#CName; + let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName); let RenderMethod = "addImmOperands"; + let IsOptional = Optional; + let DefaultMethod = !if(Optional, "default"#CName, ?); } -def SLCMubufMatchClass : SLCBaseMatchClass <"parseMubufOptionalOps">; -def SLCFlatMatchClass : SLCBaseMatchClass <"parseFlatOptionalOps">; -def SLCFlatAtomicMatchClass : SLCBaseMatchClass <"parseFlatAtomicOptionalOps">; - -class TFEBaseMatchClass <string parser> : AsmOperandClass { - let Name = "TFE"#parser; - let PredicateMethod = "isImm"; - let ParserMethod = parser; - let RenderMethod = "addImmOperands"; +class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -def TFEMubufMatchClass : TFEBaseMatchClass <"parseMubufOptionalOps">; -def TFEFlatMatchClass : TFEBaseMatchClass <"parseFlatOptionalOps">; -def TFEFlatAtomicMatchClass : TFEBaseMatchClass <"parseFlatAtomicOptionalOps">; - -def OModMatchClass : AsmOperandClass { - let Name = "OMod"; - let PredicateMethod = "isImm"; - let ParserMethod = "parseVOP3OptionalOps"; - let RenderMethod = "addImmOperands"; +class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -def ClampMatchClass : AsmOperandClass { - let Name = "Clamp"; - let PredicateMethod = "isImm"; - let ParserMethod = "parseVOP3OptionalOps"; - let RenderMethod = "addImmOperands"; +class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -class SMRDOffsetBaseMatchClass <string predicate> : AsmOperandClass { - let Name = "SMRDOffset"#predicate; - let PredicateMethod = predicate; - let RenderMethod = "addImmOperands"; +class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> { + let PrintMethod = "print"#Name; + let ParserMatchClass = MatchClass; } -def SMRDOffsetMatchClass : SMRDOffsetBaseMatchClass <"isSMRDOffset">; -def SMRDLiteralOffsetMatchClass : SMRDOffsetBaseMatchClass < - "isSMRDLiteralOffset" ->; - let OperandType = "OPERAND_IMMEDIATE" in { -def offen : Operand<i1> { - let PrintMethod = "printOffen"; -} -def idxen : Operand<i1> { - let PrintMethod = "printIdxen"; -} -def addr64 : Operand<i1> { - let PrintMethod = "printAddr64"; -} -def mbuf_offset : Operand<i16> { - let PrintMethod = "printMBUFOffset"; - let ParserMatchClass = MubufOffsetMatchClass; -} -class ds_offset_base <AsmOperandClass mc> : Operand<i16> { - let PrintMethod = "printDSOffset"; - let ParserMatchClass = mc; -} -def ds_offset : ds_offset_base <DSOffsetMatchClass>; -def ds_offset_gds : ds_offset_base <DSOffsetGDSMatchClass>; +def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>; +def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>; +def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>; -def ds_offset0 : Operand<i8> { - let PrintMethod = "printDSOffset0"; - let ParserMatchClass = DSOffset01MatchClass; -} -def ds_offset1 : Operand<i8> { - let PrintMethod = "printDSOffset1"; - let ParserMatchClass = DSOffset01MatchClass; -} -class gds_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printGDS"; - let ParserMatchClass = mc; -} -def gds : gds_base <GDSMatchClass>; +def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>; +def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>; +def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>; -def gds01 : gds_base <GDS01MatchClass>; +def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>; -class glc_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printGLC"; - let ParserMatchClass = mc; -} +def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>; +def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>; -def glc : glc_base <GLCMubufMatchClass>; -def glc_flat : glc_base <GLCFlatMatchClass>; +def smrd_offset : NamedOperandU32<"SMRDOffset", NamedMatchClass<"SMRDOffset">>; +def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", NamedMatchClass<"SMRDLiteralOffset">>; -class slc_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printSLC"; - let ParserMatchClass = mc; -} +def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>; +def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>; +def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>; +def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>; +def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>; +def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>; +def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>; -def slc : slc_base <SLCMubufMatchClass>; -def slc_flat : slc_base <SLCFlatMatchClass>; -def slc_flat_atomic : slc_base <SLCFlatAtomicMatchClass>; +def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>; -class tfe_base <AsmOperandClass mc> : Operand <i1> { - let PrintMethod = "printTFE"; - let ParserMatchClass = mc; -} +def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>; +def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>; +def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>; +def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>; -def tfe : tfe_base <TFEMubufMatchClass>; -def tfe_flat : tfe_base <TFEFlatMatchClass>; -def tfe_flat_atomic : tfe_base <TFEFlatAtomicMatchClass>; +def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>; +def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>; +def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>; +def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>; -def omod : Operand <i32> { - let PrintMethod = "printOModSI"; - let ParserMatchClass = OModMatchClass; -} +def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>; + +} // End OperandType = "OPERAND_IMMEDIATE" -def ClampMod : Operand <i1> { - let PrintMethod = "printClampSI"; - let ParserMatchClass = ClampMatchClass; -} -def smrd_offset : Operand <i32> { - let PrintMethod = "printU32ImmOperand"; - let ParserMatchClass = SMRDOffsetMatchClass; +def VOPDstS64 : VOPDstOperand <SReg_64>; + +def FPInputModsMatchClass : AsmOperandClass { + let Name = "RegOrImmWithFPInputMods"; + let ParserMethod = "parseRegOrImmWithFPInputMods"; + let PredicateMethod = "isRegOrImmWithInputMods"; } -def smrd_literal_offset : Operand <i32> { - let PrintMethod = "printU32ImmOperand"; - let ParserMatchClass = SMRDLiteralOffsetMatchClass; +def FPInputMods : Operand <i32> { + let PrintMethod = "printOperandAndFPInputMods"; + let ParserMatchClass = FPInputModsMatchClass; } -} // End OperandType = "OPERAND_IMMEDIATE" +def IntInputModsMatchClass : AsmOperandClass { + let Name = "RegOrImmWithIntInputMods"; + let ParserMethod = "parseRegOrImmWithIntInputMods"; + let PredicateMethod = "isRegOrImmWithInputMods"; +} -def VOPDstS64 : VOPDstOperand <SReg_64>; +def IntInputMods: Operand <i32> { + let PrintMethod = "printOperandAndIntInputMods"; + let ParserMatchClass = IntInputModsMatchClass; +} //===----------------------------------------------------------------------===// // Complex patterns @@ -595,9 +609,13 @@ def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">; def MUBUFAddr32 : ComplexPattern<i64, 9, "SelectMUBUFAddr32">; def MUBUFAddr64 : ComplexPattern<i64, 7, "SelectMUBUFAddr64">; def MUBUFAddr64Atomic : ComplexPattern<i64, 5, "SelectMUBUFAddr64">; +def FLATAtomic : ComplexPattern<i64, 3, "SelectFlat">; def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">; def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">; +def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">; def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">; +def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">; +def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">; def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">; def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">; @@ -606,6 +624,8 @@ def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">; def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">; def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">; +def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">; + def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">; def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">; def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">; @@ -670,17 +690,24 @@ class EXPCommon : InstSI< let EXP_CNT = 1; let Uses = [EXEC]; + let SchedRW = [WriteExport]; } multiclass EXP_m { let isPseudo = 1, isCodeGenOnly = 1 in { - def "" : EXPCommon, SIMCInstr <"exp", SISubtarget.NONE> ; + def "" : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.NONE> ; } - def _si : EXPCommon, SIMCInstr <"exp", SISubtarget.SI>, EXPe; + def _si : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.SI>, EXPe { + let DecoderNamespace="SICI"; + let DisableDecoder = DisableSIDecoder; + } - def _vi : EXPCommon, SIMCInstr <"exp", SISubtarget.VI>, EXPe_vi; + def _vi : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.VI>, EXPe_vi { + let DecoderNamespace="VI"; + let DisableDecoder = DisableVIDecoder; + } } //===----------------------------------------------------------------------===// @@ -689,7 +716,7 @@ multiclass EXP_m { class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : SOP1 <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -697,17 +724,21 @@ class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> : SOP1 <outs, ins, asm, []>, SOP1e <op.SI>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let isCodeGenOnly = 0; let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> : SOP1 <outs, ins, asm, []>, SOP1e <op.VI>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let isCodeGenOnly = 0; let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm, @@ -722,27 +753,27 @@ multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm, } multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m < - op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0), - opName#" $dst, $src0", pattern + op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0), + opName#" $sdst, $src0", pattern >; multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m < - op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0), - opName#" $dst, $src0", pattern + op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0), + opName#" $sdst, $src0", pattern >; // no input, 64-bit output. multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> { - def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>; + def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>; - def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins), - opName#" $dst"> { - let ssrc0 = 0; + def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins), + opName#" $sdst"> { + let src0 = 0; } - def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins), - opName#" $dst"> { - let ssrc0 = 0; + def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins), + opName#" $sdst"> { + let src0 = 0; } } @@ -763,13 +794,19 @@ multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> { // 64-bit input, 32-bit output. multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m < - op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0), - opName#" $dst, $src0", pattern + op, opName, (outs SReg_32:$sdst), (ins SSrc_64:$src0), + opName#" $sdst, $src0", pattern +>; + +// 32-bit input, 64-bit output. +multiclass SOP1_64_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m < + op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0), + opName#" $sdst, $src0", pattern >; class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> : SOP2<outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; let Size = 4; @@ -784,15 +821,19 @@ class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> : class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> : SOP2<outs, ins, asm, []>, SOP2e<op.SI>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } class SOP2_Real_vi<sop2 op, string opName, dag outs, dag ins, string asm> : SOP2<outs, ins, asm, []>, SOP2e<op.VI>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm, @@ -807,36 +848,49 @@ multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm, } multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m < - op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern + op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1), + opName#" $sdst, $src0, $src1", pattern >; multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m < - op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), - opName#" $dst, $src0, $src1", pattern + op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_64:$src1), + opName#" $sdst, $src0, $src1", pattern >; multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m < - op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1), - opName#" $dst, $src0, $src1", pattern + op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_32:$src1), + opName#" $sdst, $src0, $src1", pattern >; -class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt, - string opName, PatLeaf cond> : SOPC < - op, (outs), (ins rc:$src0, rc:$src1), - opName#" $src0, $src1", []> { +multiclass SOP2_64_32_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m < + op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1), + opName#" $sdst, $src0, $src1", pattern +>; + +class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1, + string opName, list<dag> pattern = []> : SOPC < + op, (outs), (ins rc0:$src0, rc1:$src1), + opName#" $src0, $src1", pattern > { let Defs = [SCC]; } +class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt, + string opName, PatLeaf cond> : SOPC_Base < + op, rc, rc, opName, + [(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > { +} -class SOPC_32<bits<7> op, string opName, PatLeaf cond = COND_NULL> +class SOPC_CMP_32<bits<7> op, string opName, PatLeaf cond = COND_NULL> : SOPC_Helper<op, SSrc_32, i32, opName, cond>; -class SOPC_64<bits<7> op, string opName, PatLeaf cond = COND_NULL> - : SOPC_Helper<op, SSrc_64, i64, opName, cond>; +class SOPC_32<bits<7> op, string opName, list<dag> pattern = []> + : SOPC_Base<op, SSrc_32, SSrc_32, opName, pattern>; + +class SOPC_64_32<bits<7> op, string opName, list<dag> pattern = []> + : SOPC_Base<op, SSrc_64, SSrc_32, opName, pattern>; class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : SOPK <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -844,16 +898,20 @@ class SOPK_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : class SOPK_Real_si <sopk op, string opName, dag outs, dag ins, string asm> : SOPK <outs, ins, asm, []>, SOPKe <op.SI>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; let isCodeGenOnly = 0; } class SOPK_Real_vi <sopk op, string opName, dag outs, dag ins, string asm> : SOPK <outs, ins, asm, []>, SOPKe <op.VI>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; let isCodeGenOnly = 0; } @@ -868,14 +926,14 @@ multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm, } multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> { - def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0), + def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16), pattern>; - def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0), - opName#" $dst, $src0">; + def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16), + opName#" $sdst, $simm16">; - def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0), - opName#" $dst, $src0">; + def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16), + opName#" $sdst, $simm16">; } multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> { @@ -908,15 +966,19 @@ multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins, def _si : SOPK <outs, ins, asm, []>, SOPK64e <op.SI>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; let isCodeGenOnly = 0; } def _vi : SOPK <outs, ins, asm, []>, SOPK64e <op.VI>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; let isCodeGenOnly = 0; } } @@ -926,86 +988,145 @@ multiclass SOPK_IMM32 <sopk op, string opName, dag outs, dag ins, class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : SMRD <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } -class SMRD_Real_si <bits<5> op, string opName, bit imm, dag outs, dag ins, - string asm> : +class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins, + string asm> : + SMRD <outs, ins, asm, []>, + SMRD_IMMe <op>, + SIMCInstr<opName, SIEncodingFamily.SI> { + let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} + +class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins, + string asm> : SMRD <outs, ins, asm, []>, - SMRDe <op, imm>, - SIMCInstr<opName, SISubtarget.SI> { + SMRD_SOFFe <op>, + SIMCInstr<opName, SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} + + +class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins, + string asm, list<dag> pattern = []> : + SMRD <outs, ins, asm, pattern>, + SMEM_IMMe_vi <op>, + SIMCInstr<opName, SIEncodingFamily.VI> { + let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } -class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins, - string asm, list<dag> pattern = []> : +class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins, + string asm, list<dag> pattern = []> : SMRD <outs, ins, asm, pattern>, - SMEMe_vi <op, imm>, - SIMCInstr<opName, SISubtarget.VI> { + SMEM_SOFFe_vi <op>, + SIMCInstr<opName, SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } -multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins, + +multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins, string asm, list<dag> pattern> { def "" : SMRD_Pseudo <opName, outs, ins, pattern>; - def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>; + def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>; // glc is only applicable to scalar stores, which are not yet // implemented. let glc = 0 in { - def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>; + def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>; } } -multiclass SMRD_Inval <smrd op, string opName, - SDPatternOperator node> { - let hasSideEffects = 1, mayStore = 1 in { - def "" : SMRD_Pseudo <opName, (outs), (ins), [(node)]>; +multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins, + string asm, list<dag> pattern> { - let sbase = 0, offset = 0 in { - let sdst = 0 in { - def _si : SMRD_Real_si <op.SI, opName, 0, (outs), (ins), opName>; - } + def "" : SMRD_Pseudo <opName, outs, ins, pattern>; + + def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>; - let glc = 0, sdata = 0 in { - def _vi : SMRD_Real_vi <op.VI, opName, 0, (outs), (ins), opName>; + // glc is only applicable to scalar stores, which are not yet + // implemented. + let glc = 0 in { + def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>; + } +} + +multiclass SMRD_Special <smrd op, string opName, dag outs, + int sdst_ = ?, + string opStr = "", + list<dag> pattern = []> { + let hasSideEffects = 1 in { + def "" : SMRD_Pseudo <opName, outs, (ins), pattern>; + + let sbase = 0, soff = 0, sdst = sdst_ in { + def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>; + + let glc = 0 in { + def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>; } } } } +multiclass SMRD_Inval <smrd op, string opName, + SDPatternOperator node> { + let mayStore = 1 in { + defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>; + } +} + class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> : - SMRD_Real_vi<op, opName, 0, (outs), (ins), opName, [(node)]> { + SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> { let hasSideEffects = 1; let mayStore = 1; let sbase = 0; - let sdata = 0; + let sdst = 0; + let glc = 0; + let soff = 0; +} + +class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> : + SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins), + opName#" $sdst", [(set i64:$sdst, (node))]> { + let hasSideEffects = 1; + let mayStore = ?; + let mayLoad = ?; + let sbase = 0; let glc = 0; - let offset = 0; + let soff = 0; } multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass, RegisterClass dstClass> { - defm _IMM : SMRD_m < - op, opName#"_IMM", 1, (outs dstClass:$dst), + defm _IMM : SMRD_IMM_m < + op, opName#"_IMM", (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_offset:$offset), - opName#" $dst, $sbase, $offset", [] + opName#" $sdst, $sbase, $offset", [] >; def _IMM_ci : SMRD < - (outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset), - opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> { + (outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset), + opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> { let AssemblerPredicates = [isCIOnly]; + let DecoderNamespace = "CI"; } - defm _SGPR : SMRD_m < - op, opName#"_SGPR", 0, (outs dstClass:$dst), + defm _SGPR : SMRD_SOFF_m < + op, opName#"_SGPR", (outs dstClass:$sdst), (ins baseClass:$sbase, SReg_32:$soff), - opName#" $dst, $sbase, $soff", [] + opName#" $sdst, $sbase, $soff", [] >; } @@ -1013,20 +1134,6 @@ multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass, // Vector ALU classes //===----------------------------------------------------------------------===// -// This must always be right before the operand being input modified. -def InputMods : OperandWithDefaultOps <i32, (ops (i32 0))> { - let PrintMethod = "printOperandAndMods"; -} - -def InputModsMatchClass : AsmOperandClass { - let Name = "RegWithInputMods"; -} - -def InputModsNoDefault : Operand <i32> { - let PrintMethod = "printOperandAndMods"; - let ParserMatchClass = InputModsMatchClass; -} - class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> { int ret = !if (!eq(Src0.Value, untyped.Value), 0, @@ -1050,12 +1157,12 @@ class getVOPSrc0ForVT<ValueType VT> { RegisterOperand ret = !if(!eq(VT.Size, 64), VSrc_64, VSrc_32); } -// Returns the register class to use for source 1 of VOP[12C] for the -// given VT. -class getVOPSrc1ForVT<ValueType VT> { +// Returns the vreg register class to use for source operand given VT +class getVregSrcForVT<ValueType VT> { RegisterClass ret = !if(!eq(VT.Size, 64), VReg_64, VGPR_32); } + // Returns the register class to use for sources of VOP3 instructions for the // given VT. class getVOP3SrcForVT<ValueType VT> { @@ -1072,8 +1179,10 @@ class getVOP3SrcForVT<ValueType VT> { // Returns 1 if the source arguments have modifiers, 0 if they do not. // XXX - do f16 instructions? class hasModifiers<ValueType SrcVT> { - bit ret = !if(!eq(SrcVT.Value, f32.Value), 1, - !if(!eq(SrcVT.Value, f64.Value), 1, 0)); + bit ret = + !if(!eq(SrcVT.Value, f32.Value), 1, + !if(!eq(SrcVT.Value, f64.Value), 1, + 0)); } // Returns the input arguments for VOP[12C] instructions for the given SrcVT. @@ -1089,11 +1198,15 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, bit HasModifiers> { dag ret = + !if (!eq(NumSrcArgs, 0), + // VOP1 without input operands (V_NOP, V_CLREXCP) + (ins), + /* else */ !if (!eq(NumSrcArgs, 1), !if (!eq(HasModifiers, 1), // VOP1 with modifiers - (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - ClampMod:$clamp, omod:$omod) + (ins FPInputMods:$src0_modifiers, Src0RC:$src0, + clampmod:$clamp, omod:$omod) /* else */, // VOP1 without modifiers (ins Src0RC:$src0) @@ -1101,9 +1214,9 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, !if (!eq(NumSrcArgs, 2), !if (!eq(HasModifiers, 1), // VOP 2 with modifiers - (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - InputModsNoDefault:$src1_modifiers, Src1RC:$src1, - ClampMod:$clamp, omod:$omod) + (ins FPInputMods:$src0_modifiers, Src0RC:$src0, + FPInputMods:$src1_modifiers, Src1RC:$src1, + clampmod:$clamp, omod:$omod) /* else */, // VOP2 without modifiers (ins Src0RC:$src0, Src1RC:$src1) @@ -1111,21 +1224,109 @@ class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC, /* NumSrcArgs == 3 */, !if (!eq(HasModifiers, 1), // VOP3 with modifiers - (ins InputModsNoDefault:$src0_modifiers, Src0RC:$src0, - InputModsNoDefault:$src1_modifiers, Src1RC:$src1, - InputModsNoDefault:$src2_modifiers, Src2RC:$src2, - ClampMod:$clamp, omod:$omod) + (ins FPInputMods:$src0_modifiers, Src0RC:$src0, + FPInputMods:$src1_modifiers, Src1RC:$src1, + FPInputMods:$src2_modifiers, Src2RC:$src2, + clampmod:$clamp, omod:$omod) /* else */, // VOP3 without modifiers (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2) - /* endif */ ))); + /* endif */ )))); +} + +class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs, + bit HasModifiers> { + + dag ret = !if (!eq(NumSrcArgs, 0), + // VOP1 without input operands (V_NOP) + (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl), + !if (!eq(NumSrcArgs, 1), + !if (!eq(HasModifiers, 1), + // VOP1_DPP with modifiers + (ins FPInputMods:$src0_modifiers, Src0RC:$src0, + dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) + /* else */, + // VOP1_DPP without modifiers + (ins Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) + /* endif */) + /* NumSrcArgs == 2 */, + !if (!eq(HasModifiers, 1), + // VOP2_DPP with modifiers + (ins FPInputMods:$src0_modifiers, Src0RC:$src0, + FPInputMods:$src1_modifiers, Src1RC:$src1, + dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl) + /* else */, + // VOP2_DPP without modifiers + (ins Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl, + row_mask:$row_mask, bank_mask:$bank_mask, + bound_ctrl:$bound_ctrl) + /* endif */))); +} + +class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs, + bit HasFloatModifiers, ValueType DstVT> { + + dag ret = !if(!eq(NumSrcArgs, 0), + // VOP1 without input operands (V_NOP) + (ins), + !if(!eq(NumSrcArgs, 1), + !if(HasFloatModifiers, + // VOP1_SDWA with float modifiers + (ins FPInputMods:$src0_fmodifiers, Src0RC:$src0, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + src0_sel:$src0_sel) + /* else */, + // VOP1_SDWA with sext modifier + (ins IntInputMods:$src0_imodifiers, Src0RC:$src0, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + src0_sel:$src0_sel) + /* endif */) + /* NumSrcArgs == 2 */, + !if(HasFloatModifiers, + !if(!eq(DstVT.Size, 1), + // VOPC_SDWA with float modifiers + (ins FPInputMods:$src0_fmodifiers, Src0RC:$src0, + FPInputMods:$src1_fmodifiers, Src1RC:$src1, + clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel), + // VOP2_SDWA or VOPC_SDWA with float modifiers + (ins FPInputMods:$src0_fmodifiers, Src0RC:$src0, + FPInputMods:$src1_fmodifiers, Src1RC:$src1, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + src0_sel:$src0_sel, src1_sel:$src1_sel) + ), + /* else */ + !if(!eq(DstVT.Size, 1), + // VOPC_SDWA with sext modifiers + (ins IntInputMods:$src0_imodifiers, Src0RC:$src0, + IntInputMods:$src1_imodifiers, Src1RC:$src1, + clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel), + // VOP2_SDWA or VOPC_SDWA with sext modifier + (ins IntInputMods:$src0_imodifiers, Src0RC:$src0, + IntInputMods:$src1_imodifiers, Src1RC:$src1, + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + src0_sel:$src0_sel, src1_sel:$src1_sel) + ) + /* endif */))); +} + +// Outs for DPP and SDWA +class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> { + dag ret = !if(HasDst, + !if(!eq(DstVT.Size, 1), + (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions + (outs DstRCDPP:$vdst)), + (outs)); // V_NOP } // Returns the assembly string for the inputs and outputs of a VOP[12C] // instruction. This does not add the _e32 suffix, so it can be reused // by getAsm64. -class getAsm32 <bit HasDst, int NumSrcArgs> { - string dst = "$dst"; +class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> { + string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string src0 = ", $src0"; string src1 = ", $src1"; string src2 = ", $src2"; @@ -1137,7 +1338,8 @@ class getAsm32 <bit HasDst, int NumSrcArgs> { // Returns the assembly string for the inputs and outputs of a VOP3 // instruction. -class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> { +class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { + string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); string src1 = !if(!eq(NumSrcArgs, 1), "", !if(!eq(NumSrcArgs, 2), " $src1_modifiers", @@ -1145,8 +1347,71 @@ class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers> { string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", ""); string ret = !if(!eq(HasModifiers, 0), - getAsm32<HasDst, NumSrcArgs>.ret, - "$dst, "#src0#src1#src2#"$clamp"#"$omod"); + getAsm32<HasDst, NumSrcArgs, DstVT>.ret, + dst#", "#src0#src1#src2#"$clamp"#"$omod"); +} + +class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> { + string dst = !if(HasDst, + !if(!eq(DstVT.Size, 1), + "$sdst", + "$vdst"), + ""); // use $sdst for VOPC + string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,"); + string src1 = !if(!eq(NumSrcArgs, 1), "", + !if(!eq(NumSrcArgs, 2), " $src1_modifiers", + " $src1_modifiers,")); + string args = !if(!eq(HasModifiers, 0), + getAsm32<0, NumSrcArgs, DstVT>.ret, + ", "#src0#src1); + string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl"; +} + +class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasFloatModifiers, + ValueType DstVT = i32> { + string dst = !if(HasDst, + !if(!eq(DstVT.Size, 1), + " vcc", // use vcc token as dst for VOPC instructioins + "$vdst"), + ""); + string src0 = !if(HasFloatModifiers, "$src0_fmodifiers", "$src0_imodifiers"); + string src1 = !if(HasFloatModifiers, "$src1_fmodifiers", "$src1_imodifiers"); + string args = !if(!eq(NumSrcArgs, 0), + "", + !if(!eq(NumSrcArgs, 1), + ", "#src0#"$clamp", + ", "#src0#", "#src1#"$clamp" + ) + ); + string sdwa = !if(!eq(NumSrcArgs, 0), + "", + !if(!eq(NumSrcArgs, 1), + " $dst_sel $dst_unused $src0_sel", + !if(!eq(DstVT.Size, 1), + " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC + " $dst_sel $dst_unused $src0_sel $src1_sel" + ) + ) + ); + string ret = dst#args#sdwa; +} + +// Function that checks if instruction supports DPP and SDWA +class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32, + ValueType Src1VT = i32> { + bit ret = !if(!eq(NumSrcArgs, 3), + 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3 + !if(!eq(DstVT.Size, 64), + 0, // 64-bit dst - No DPP or SDWA for 64-bit operands + !if(!eq(Src0VT.Size, 64), + 0, // 64-bit src0 + !if(!eq(Src0VT.Size, 64), + 0, // 64-bit src2 + 1 + ) + ) + ) + ); } class VOPProfile <list<ValueType> _ArgVT> { @@ -1158,30 +1423,48 @@ class VOPProfile <list<ValueType> _ArgVT> { field ValueType Src1VT = ArgVT[2]; field ValueType Src2VT = ArgVT[3]; field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret; + field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret; + field RegisterOperand DstRCSDWA = getVALUDstForVT<DstVT>.ret; field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret; - field RegisterClass Src1RC32 = getVOPSrc1ForVT<Src1VT>.ret; + field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret; field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret; field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret; field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret; + field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret; + field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret; + field RegisterClass Src0SDWA = getVregSrcForVT<Src0VT>.ret; + field RegisterClass Src1SDWA = getVregSrcForVT<Src1VT>.ret; field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1); field bit HasDst32 = HasDst; field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret; field bit HasModifiers = hasModifiers<Src0VT>.ret; - field dag Outs = !if(HasDst,(outs DstRC:$dst),(outs)); + field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret; + + field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs)); // VOP3b instructions are a special case with a second explicit // output. This is manually overridden for them. field dag Outs32 = Outs; field dag Outs64 = Outs; + field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret; + field dag OutsSDWA = getOutsExt<HasDst, DstVT, DstRCDPP>.ret; field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret; field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs, HasModifiers>.ret; + field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs, HasModifiers>.ret; + field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs, HasModifiers, DstVT>.ret; - field string Asm32 = getAsm32<HasDst, NumSrcArgs>.ret; - field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers>.ret; + field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret; + field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret; + field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret; + field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret; +} + +class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> { + let HasExt = 0; } // FIXME: I think these F16/I16 profiles will need to use f16/i16 types in order @@ -1194,6 +1477,9 @@ def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>; def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i32, untyped]>; def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>; +def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>; +def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>; + def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>; def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>; @@ -1216,10 +1502,10 @@ def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>; // Write out to vcc or arbitrary SGPR. def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> { - let Asm32 = "$dst, vcc, $src0, $src1"; - let Asm64 = "$dst, $sdst, $src0, $src1"; - let Outs32 = (outs DstRC:$dst); - let Outs64 = (outs DstRC:$dst, SReg_64:$sdst); + let Asm32 = "$vdst, vcc, $src0, $src1"; + let Asm64 = "$vdst, $sdst, $src0, $src1"; + let Outs32 = (outs DstRC:$vdst); + let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); } // Write out to vcc or arbitrary SGPR and read in from vcc or @@ -1231,10 +1517,23 @@ def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { // restriction. SGPRs are still allowed because it should // technically be possible to use VCC again as src0. let Src0RC32 = VCSrc_32; - let Asm32 = "$dst, vcc, $src0, $src1, vcc"; - let Asm64 = "$dst, $sdst, $src0, $src1, $src2"; - let Outs32 = (outs DstRC:$dst); - let Outs64 = (outs DstRC:$dst, SReg_64:$sdst); + let Asm32 = "$vdst, vcc, $src0, $src1, vcc"; + let Asm64 = "$vdst, $sdst, $src0, $src1, $src2"; + let Outs32 = (outs DstRC:$vdst); + let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst); + + // Suppress src2 implied by type since the 32-bit encoding uses an + // implicit VCC use. + let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); +} + +// Read in from vcc or arbitrary SGPR +def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> { + let Src0RC32 = VCSrc_32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above. + let Asm32 = "$vdst, $src0, $src1, vcc"; + let Asm64 = "$vdst, $src0, $src1, $src2"; + let Outs32 = (outs DstRC:$vdst); + let Outs64 = (outs DstRC:$vdst); // Suppress src2 implied by type since the 32-bit encoding uses an // implicit VCC use. @@ -1263,11 +1562,17 @@ class VOPC_Profile<ValueType vt0, ValueType vt1 = vt0> : VOPProfile <[i1, vt0, v let Asm32 = "vcc, $src0, $src1"; // The destination for 32-bit encoding is implicit. let HasDst32 = 0; + let Outs64 = (outs DstRC:$sdst); } class VOPC_Class_Profile<ValueType vt> : VOPC_Profile<vt, i32> { - let Ins64 = (ins InputModsNoDefault:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); - let Asm64 = "$dst, $src0_modifiers, $src1"; + let Ins64 = (ins FPInputMods:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); + let Asm64 = "$sdst, $src0_modifiers, $src1"; + let InsSDWA = (ins FPInputMods:$src0_fmodifiers, Src0RC64:$src0, + IntInputMods:$src1_imodifiers, Src1RC64:$src1, + clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel); + let AsmSDWA = " vcc, $src0_fmodifiers, $src1_imodifiers$clamp $src0_sel $src1_sel"; + } def VOPC_I1_F32_F32 : VOPC_Profile<f32>; @@ -1281,28 +1586,42 @@ def VOPC_I1_F64_I32 : VOPC_Class_Profile<f64>; def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>; def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>; def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>; -def VOP_CNDMASK : VOPProfile <[i32, i32, i32, untyped]> { - let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1); - let Ins64 = (ins Src0RC64:$src0, Src1RC64:$src1, SSrc_64:$src2); - let Asm64 = "$dst, $src0, $src1, $src2"; -} def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>; -def VOP_MADK : VOPProfile <[f32, f32, f32, f32]> { - field dag Ins = (ins VCSrc_32:$src0, VGPR_32:$vsrc1, u32imm:$src2); - field string Asm = "$dst, $src0, $vsrc1, $src2"; +def VOP_MADAK : VOPProfile <[f32, f32, f32, f32]> { + field dag Ins32 = (ins VCSrc_32:$src0, VGPR_32:$src1, u32kimm:$imm); + field string Asm32 = "$vdst, $src0, $src1, $imm"; + field bit HasExt = 0; +} +def VOP_MADMK : VOPProfile <[f32, f32, f32, f32]> { + field dag Ins32 = (ins VCSrc_32:$src0, u32kimm:$imm, VGPR_32:$src1); + field string Asm32 = "$vdst, $src0, $imm, $src1"; + field bit HasExt = 0; } def VOP_MAC : VOPProfile <[f32, f32, f32, f32]> { let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2); let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3, HasModifiers>.ret; - let Asm32 = getAsm32<1, 2>.ret; - let Asm64 = getAsm64<1, 2, HasModifiers>.ret; + let InsDPP = (ins FPInputMods:$src0_modifiers, Src0RC32:$src0, + FPInputMods:$src1_modifiers, Src1RC32:$src1, + VGPR_32:$src2, // stub argument + dpp_ctrl:$dpp_ctrl, row_mask:$row_mask, + bank_mask:$bank_mask, bound_ctrl:$bound_ctrl); + let InsSDWA = (ins FPInputMods:$src0_fmodifiers, Src0RC32:$src0, + FPInputMods:$src1_fmodifiers, Src1RC32:$src1, + VGPR_32:$src2, // stub argument + clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused, + src0_sel:$src0_sel, src1_sel:$src1_sel); + let Asm32 = getAsm32<1, 2, f32>.ret; + let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret; + let AsmDPP = getAsmDPP<1, 2, HasModifiers, f32>.ret; + let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, f32>.ret; } def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>; def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>; def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>; +// This class is used only with VOPC instructions. Use $sdst for out operand class SIInstAlias <string asm, Instruction inst, VOPProfile p> : InstAlias <asm, (inst)>, PredicateControl { @@ -1313,13 +1632,13 @@ class SIInstAlias <string asm, Instruction inst, VOPProfile p> : !if (p.HasDst32, !if (!eq(p.NumSrcArgs, 0), // 1 dst, 0 src - (inst p.DstRC:$dst), + (inst p.DstRC:$sdst), !if (!eq(p.NumSrcArgs, 1), // 1 dst, 1 src - (inst p.DstRC:$dst, p.Src0RC32:$src0), + (inst p.DstRC:$sdst, p.Src0RC32:$src0), !if (!eq(p.NumSrcArgs, 2), // 1 dst, 2 src - (inst p.DstRC:$dst, p.Src0RC32:$src0, p.Src1RC32:$src1), + (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), // else - unreachable (inst)))), // else @@ -1368,7 +1687,7 @@ class AtomicNoRet <string noRetOp, bit isRet> { class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : VOP1Common <outs, ins, "", pattern>, VOP <opName>, - SIMCInstr <opName#"_e32", SISubtarget.NONE>, + SIMCInstr <opName#"_e32", SIEncodingFamily.NONE>, MnemonicAlias<opName#"_e32", opName> { let isPseudo = 1; let isCodeGenOnly = 1; @@ -1379,14 +1698,18 @@ class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : class VOP1_Real_si <string opName, vop1 op, dag outs, dag ins, string asm> : VOP1<op.SI, outs, ins, asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.SI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.SI> { let AssemblerPredicate = SIAssemblerPredicate; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } class VOP1_Real_vi <string opName, vop1 op, dag outs, dag ins, string asm> : VOP1<op.VI, outs, ins, asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.VI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern, @@ -1399,6 +1722,49 @@ multiclass VOP1_m <vop1 op, string opName, VOPProfile p, list<dag> pattern, } +class VOP1_DPP <vop1 op, string opName, VOPProfile p> : + VOP1_DPPe <op.VI>, + VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> { + let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]); + let DecoderNamespace = "DPP"; + let DisableDecoder = DisableVIDecoder; + let src0_modifiers = !if(p.HasModifiers, ?, 0); + let src1_modifiers = 0; +} + +class SDWADisableFields <VOPProfile p> { + bits<8> src0 = !if(!eq(p.NumSrcArgs, 0), 0, ?); + bits<3> src0_sel = !if(!eq(p.NumSrcArgs, 0), 6, ?); + bits<2> src0_fmodifiers = !if(!eq(p.NumSrcArgs, 0), + 0, + !if(p.HasModifiers, ?, 0)); + bits<1> src0_imodifiers = !if(!eq(p.NumSrcArgs, 0), + 0, + !if(p.HasModifiers, 0, ?)); + bits<3> src1_sel = !if(!eq(p.NumSrcArgs, 0), 6, + !if(!eq(p.NumSrcArgs, 1), 6, + ?)); + bits<2> src1_fmodifiers = !if(!eq(p.NumSrcArgs, 0), 0, + !if(!eq(p.NumSrcArgs, 1), 0, + !if(p.HasModifiers, ?, 0))); + bits<1> src1_imodifiers = !if(!eq(p.NumSrcArgs, 0), 0, + !if(!eq(p.NumSrcArgs, 1), 0, + !if(p.HasModifiers, 0, ?))); + bits<3> dst_sel = !if(p.HasDst, ?, 6); + bits<2> dst_unused = !if(p.HasDst, ?, 2); + bits<1> clamp = !if(!eq(p.NumSrcArgs, 0), 0, ?); +} + +class VOP1_SDWA <vop1 op, string opName, VOPProfile p> : + VOP1_SDWAe <op.VI>, + VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>, + SDWADisableFields <p> { + let AsmMatchConverter = "cvtSdwaVOP1"; + let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]); + let DecoderNamespace = "SDWA"; + let DisableDecoder = DisableVIDecoder; +} + multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern, string asm = opName#p.Asm32> { @@ -1410,7 +1776,7 @@ multiclass VOP1SI_m <vop1 op, string opName, VOPProfile p, list<dag> pattern, class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : VOP2Common <outs, ins, "", pattern>, VOP <opName>, - SIMCInstr<opName#"_e32", SISubtarget.NONE>, + SIMCInstr<opName#"_e32", SIEncodingFamily.NONE>, MnemonicAlias<opName#"_e32", opName> { let isPseudo = 1; let isCodeGenOnly = 1; @@ -1418,14 +1784,18 @@ class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : class VOP2_Real_si <string opName, vop2 op, dag outs, dag ins, string asm> : VOP2 <op.SI, outs, ins, opName#asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.SI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } class VOP2_Real_vi <string opName, vop2 op, dag outs, dag ins, string asm> : VOP2 <op.VI, outs, ins, opName#asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.VI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } multiclass VOP2SI_m <vop2 op, string opName, VOPProfile p, list<dag> pattern, @@ -1449,6 +1819,26 @@ multiclass VOP2_m <vop2 op, string opName, VOPProfile p, list <dag> pattern, } +class VOP2_DPP <vop2 op, string opName, VOPProfile p> : + VOP2_DPPe <op.VI>, + VOP_DPP <p.OutsDPP, p.InsDPP, opName#p.AsmDPP, [], p.HasModifiers> { + let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]); + let DecoderNamespace = "DPP"; + let DisableDecoder = DisableVIDecoder; + let src0_modifiers = !if(p.HasModifiers, ?, 0); + let src1_modifiers = !if(p.HasModifiers, ?, 0); +} + +class VOP2_SDWA <vop2 op, string opName, VOPProfile p> : + VOP2_SDWAe <op.VI>, + VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>, + SDWADisableFields <p> { + let AsmMatchConverter = "cvtSdwaVOP2"; + let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]); + let DecoderNamespace = "SDWA"; + let DisableDecoder = DisableVIDecoder; +} + class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> { bits<2> src0_modifiers = !if(HasModifiers, ?, 0); @@ -1471,10 +1861,11 @@ class VOP3DisableModFields <bit HasSrc0Mods, bits<1> clamp = !if(HasOutputMods, ?, 0); } -class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : - VOP3Common <outs, ins, "", pattern>, +class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, "", pattern, HasMods, VOP3Only>, VOP <opName>, - SIMCInstr<opName#"_e64", SISubtarget.NONE>, + SIMCInstr<opName#"_e64", SIEncodingFamily.NONE>, MnemonicAlias<opName#"_e64", opName> { let isPseudo = 1; let isCodeGenOnly = 1; @@ -1483,44 +1874,96 @@ class VOP3_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> : field bit src0; } -class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> : - VOP3Common <outs, ins, asm, []>, +class VOP3_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, VOP3e <op>, - SIMCInstr<opName#"_e64", SISubtarget.SI> { + SIMCInstr<opName#"_e64", SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } -class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> : - VOP3Common <outs, ins, asm, []>, +class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, VOP3e_vi <op>, - SIMCInstr <opName#"_e64", SISubtarget.VI> { + SIMCInstr <opName#"_e64", SIEncodingFamily.VI> { + let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; +} + +class VOP3_C_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, + VOP3ce <op>, + SIMCInstr<opName#"_e64", SIEncodingFamily.SI> { + let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} + +class VOP3_C_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, + VOP3ce_vi <op>, + SIMCInstr <opName#"_e64", SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } -class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName> : - VOP3Common <outs, ins, asm, []>, +class VOP3b_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, VOP3be <op>, - SIMCInstr<opName#"_e64", SISubtarget.SI> { + SIMCInstr<opName#"_e64", SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } -class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> : - VOP3Common <outs, ins, asm, []>, +class VOP3b_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, VOP3be_vi <op>, - SIMCInstr <opName#"_e64", SISubtarget.VI> { + SIMCInstr <opName#"_e64", SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; +} + +class VOP3e_Real_si <bits<9> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, + VOP3e <op>, + SIMCInstr<opName#"_e64", SIEncodingFamily.SI> { + let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} + +class VOP3e_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName, + bit HasMods = 0, bit VOP3Only = 0> : + VOP3Common <outs, ins, asm, [], HasMods, VOP3Only>, + VOP3e_vi <op>, + SIMCInstr <opName#"_e64", SIEncodingFamily.VI> { + let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, - string opName, int NumSrcArgs, bit HasMods = 1> { + string opName, int NumSrcArgs, bit HasMods = 1, bit VOP3Only = 0> { def "" : VOP3_Pseudo <outs, ins, pattern, opName>; - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods, VOP3Only>, VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1), !if(!eq(NumSrcArgs, 2), 0, 1), HasMods>; - def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, + def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods, VOP3Only>, VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1), !if(!eq(NumSrcArgs, 2), 0, 1), HasMods>; @@ -1529,21 +1972,21 @@ multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, string opName, bit HasMods = 1> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>; + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>; - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<0, 0, HasMods>; - def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, + def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<0, 0, HasMods>; } multiclass VOP3SI_1_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, string opName, bit HasMods = 1> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>; + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>; - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<0, 0, HasMods>; // No VI instruction. This class is for SI only. } @@ -1552,13 +1995,13 @@ multiclass VOP3_2_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, string opName, string revOp, bit HasMods = 1> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>, + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<1, 0, HasMods>; - def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, + def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<1, 0, HasMods>; } @@ -1566,10 +2009,10 @@ multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, string opName, string revOp, bit HasMods = 1> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>, + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)>; - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<1, 0, HasMods>; // No VI instruction. This class is for SI only. @@ -1579,13 +2022,26 @@ multiclass VOP3SI_2_m <vop op, dag outs, dag ins, string asm, // instead of an implicit VCC as in the VOP2b format. multiclass VOP3b_2_3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern, string opName, string revOp, - bit HasMods = 1, bit useSrc2Input = 0> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>; + bit HasMods = 1, bit useSrc2Input = 0, bit VOP3Only = 0> { + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods, VOP3Only>; - def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3b_Real_si <op.SI3, outs, ins, asm, opName, HasMods, VOP3Only>, VOP3DisableFields<1, useSrc2Input, HasMods>; - def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName>, + def _vi : VOP3b_Real_vi <op.VI3, outs, ins, asm, opName, HasMods, VOP3Only>, + VOP3DisableFields<1, useSrc2Input, HasMods>; +} + +// Same as VOP3b_2_3_m but no 2nd destination (sdst), e.g. v_cndmask_b32. +multiclass VOP3e_2_3_m <vop op, dag outs, dag ins, string asm, + list<dag> pattern, string opName, string revOp, + bit HasMods = 1, bit useSrc2Input = 0, bit VOP3Only = 0> { + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods, VOP3Only>; + + def _si : VOP3e_Real_si <op.SI3, outs, ins, asm, opName, HasMods, VOP3Only>, + VOP3DisableFields<1, useSrc2Input, HasMods>; + + def _vi : VOP3e_Real_vi <op.VI3, outs, ins, asm, opName, HasMods, VOP3Only>, VOP3DisableFields<1, useSrc2Input, HasMods>; } @@ -1594,19 +2050,19 @@ multiclass VOP3_C_m <vop op, dag outs, dag ins, string asm, bit HasMods, bit defExec, string revOp, list<SchedReadWrite> sched> { - def "" : VOP3_Pseudo <outs, ins, pattern, opName>, + def "" : VOP3_Pseudo <outs, ins, pattern, opName, HasMods>, VOP2_REV<revOp#"_e64", !eq(revOp, opName)> { let Defs = !if(defExec, [EXEC], []); let SchedRW = sched; } - def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>, + def _si : VOP3_C_Real_si <op.SI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<1, 0, HasMods> { let Defs = !if(defExec, [EXEC], []); let SchedRW = sched; } - def _vi : VOP3_Real_vi <op.VI3, outs, ins, asm, opName>, + def _vi : VOP3_C_Real_vi <op.VI3, outs, ins, asm, opName, HasMods>, VOP3DisableFields<1, 0, HasMods> { let Defs = !if(defExec, [EXEC], []); let SchedRW = sched; @@ -1618,19 +2074,23 @@ multiclass VOP2SI_3VI_m <vop3 op, string opName, dag outs, dag ins, string asm, list<dag> pattern = []> { let isPseudo = 1, isCodeGenOnly = 1 in { def "" : VOPAnyCommon <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE>; + SIMCInstr<opName, SIEncodingFamily.NONE>; } def _si : VOP2 <op.SI3{5-0}, outs, ins, asm, []>, - SIMCInstr <opName, SISubtarget.SI> { + SIMCInstr <opName, SIEncodingFamily.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } def _vi : VOP3Common <outs, ins, asm, []>, VOP3e_vi <op.VI3>, VOP3DisableFields <1, 0, 0>, - SIMCInstr <opName, SISubtarget.VI> { + SIMCInstr <opName, SIEncodingFamily.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } } @@ -1641,15 +2101,19 @@ multiclass VOP1_Helper <vop1 op, string opName, VOPProfile p, list<dag> pat32, defm _e64 : VOP3_1_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName, p.HasModifiers>; + + def _dpp : VOP1_DPP <op, opName, p>; + + def _sdwa : VOP1_SDWA <op, opName, p>; } multiclass VOP1Inst <vop1 op, string opName, VOPProfile P, SDPatternOperator node = null_frag> : VOP1_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]) + [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]) >; multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P, @@ -1659,9 +2123,9 @@ multiclass VOP1InstSI <vop1 op, string opName, VOPProfile P, defm _e64 : VOP3SI_1_m <op, P.Outs, P.Ins64, opName#P.Asm64, !if(P.HasModifiers, - [(set P.DstVT:$dst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]), opName, P.HasModifiers>; } @@ -1672,6 +2136,10 @@ multiclass VOP2_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32, defm _e64 : VOP3_2_m <op, p.Outs, p.Ins64, opName#p.Asm64, pat64, opName, revOp, p.HasModifiers>; + + def _dpp : VOP2_DPP <op, opName, p>; + + def _sdwa : VOP2_SDWA <op, opName, p>; } multiclass VOP2Inst <vop2 op, string opName, VOPProfile P, @@ -1679,11 +2147,11 @@ multiclass VOP2Inst <vop2 op, string opName, VOPProfile P, string revOp = opName> : VOP2_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp >; @@ -1695,14 +2163,41 @@ multiclass VOP2InstSI <vop2 op, string opName, VOPProfile P, defm _e64 : VOP3SI_2_m <op, P.Outs, P.Ins64, opName#P.Asm64, !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), opName, revOp, P.HasModifiers>; } +multiclass VOP2e_Helper <vop2 op, string opName, VOPProfile p, + list<dag> pat32, list<dag> pat64, + string revOp, bit useSGPRInput> { + + let SchedRW = [Write32Bit] in { + let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in { + defm _e32 : VOP2_m <op, opName, p, pat32, revOp>; + } + + defm _e64 : VOP3e_2_3_m <op, p.Outs64, p.Ins64, opName#p.Asm64, pat64, + opName, revOp, p.HasModifiers, useSGPRInput>; + } +} + +multiclass VOP2eInst <vop2 op, string opName, VOPProfile P, + SDPatternOperator node = null_frag, + string revOp = opName> : VOP2e_Helper < + op, opName, P, [], + !if(P.HasModifiers, + [(set P.DstVT:$vdst, + (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, + i1:$clamp, i32:$omod)), + (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + revOp, !eq(P.NumSrcArgs, 3) +>; + multiclass VOP2b_Helper <vop2 op, string opName, VOPProfile p, list<dag> pat32, list<dag> pat64, string revOp, bit useSGPRInput> { @@ -1722,11 +2217,11 @@ multiclass VOP2bInst <vop2 op, string opName, VOPProfile P, string revOp = opName> : VOP2b_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp, !eq(P.NumSrcArgs, 3) >; @@ -1746,31 +2241,35 @@ multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P, : VOP2_VI3_Helper < op, opName, P, [], !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]), revOp >; -multiclass VOP2MADK <vop2 op, string opName, list<dag> pattern = []> { +multiclass VOP2MADK <vop2 op, string opName, VOPProfile P, list<dag> pattern = []> { - def "" : VOP2_Pseudo <VOP_MADK.Outs, VOP_MADK.Ins, pattern, opName>; + def "" : VOP2_Pseudo <P.Outs, P.Ins32, pattern, opName>; let isCodeGenOnly = 0 in { - def _si : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins, - !strconcat(opName, VOP_MADK.Asm), []>, - SIMCInstr <opName#"_e32", SISubtarget.SI>, + def _si : VOP2Common <P.Outs, P.Ins32, + !strconcat(opName, P.Asm32), []>, + SIMCInstr <opName#"_e32", SIEncodingFamily.SI>, VOP2_MADKe <op.SI> { let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } - def _vi : VOP2Common <VOP_MADK.Outs, VOP_MADK.Ins, - !strconcat(opName, VOP_MADK.Asm), []>, - SIMCInstr <opName#"_e32", SISubtarget.VI>, + def _vi : VOP2Common <P.Outs, P.Ins32, + !strconcat(opName, P.Asm32), []>, + SIMCInstr <opName#"_e32", SIEncodingFamily.VI>, VOP2_MADKe <op.VI> { let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } } // End isCodeGenOnly = 0 } @@ -1778,37 +2277,55 @@ let isCodeGenOnly = 0 in { class VOPC_Pseudo <dag ins, list<dag> pattern, string opName> : VOPCCommon <ins, "", pattern>, VOP <opName>, - SIMCInstr<opName#"_e32", SISubtarget.NONE> { + SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } +class VOPC_SDWA <vopc op, string opName, bit DefExec, VOPProfile p> : + VOPC_SDWAe <op.VI>, + VOP_SDWA <p.OutsSDWA, p.InsSDWA, opName#p.AsmSDWA, [], p.HasModifiers>, + SDWADisableFields <p> { + let Defs = !if(DefExec, [VCC, EXEC], [VCC]); + let hasSideEffects = DefExec; + let AsmMatchConverter = "cvtSdwaVOPC"; + let AssemblerPredicates = !if(p.HasExt, [isVI], [DisableInst]); + let DecoderNamespace = "SDWA"; + let DisableDecoder = DisableVIDecoder; +} + multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern, string opName, bit DefExec, VOPProfile p, list<SchedReadWrite> sched, string revOpName = "", string asm = opName#"_e32 "#op_asm, string alias_asm = opName#" "#op_asm> { - def "" : VOPC_Pseudo <ins, pattern, opName> { + def "" : VOPC_Pseudo <ins, pattern, opName>, + VOP2_REV<revOpName#"_e32", !eq(revOpName, opName)> { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); let SchedRW = sched; + let isConvergent = DefExec; } let AssemblerPredicates = [isSICI] in { def _si : VOPC<op.SI, ins, asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.SI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.SI> { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); - let hasSideEffects = DefExec; + let isConvergent = DefExec; let SchedRW = sched; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; } } // End AssemblerPredicates = [isSICI] let AssemblerPredicates = [isVI] in { def _vi : VOPC<op.VI, ins, asm, []>, - SIMCInstr <opName#"_e32", SISubtarget.VI> { + SIMCInstr <opName#"_e32", SIEncodingFamily.VI> { let Defs = !if(DefExec, [VCC, EXEC], [VCC]); - let hasSideEffects = DefExec; + let isConvergent = DefExec; let SchedRW = sched; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; } } // End AssemblerPredicates = [isVI] @@ -1819,10 +2336,13 @@ multiclass VOPC_m <vopc op, dag ins, string op_asm, list<dag> pattern, multiclass VOPC_Helper <vopc op, string opName, list<dag> pat32, list<dag> pat64, bit DefExec, string revOp, VOPProfile p, list<SchedReadWrite> sched> { - defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>; + defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched, + revOp>; - defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64, + defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64, opName, p.HasModifiers, DefExec, revOp, sched>; + + def _sdwa : VOPC_SDWA <op, opName, DefExec, p>; } // Special case for class instructions which only have modifiers on @@ -1832,9 +2352,14 @@ multiclass VOPC_Class_Helper <vopc op, string opName, list<dag> pat32, VOPProfile p, list<SchedReadWrite> sched> { defm _e32 : VOPC_m <op, p.Ins32, p.Asm32, pat32, opName, DefExec, p, sched>; - defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$dst), p.Ins64, opName#p.Asm64, pat64, + defm _e64 : VOP3_C_m <op, (outs VOPDstS64:$sdst), p.Ins64, opName#p.Asm64, pat64, opName, p.HasModifiers, DefExec, revOp, sched>, VOP3DisableModFields<1, 0, 0>; + + def _sdwa : VOPC_SDWA <op, opName, DefExec, p> { + let src1_fmodifiers = 0; + let src1_imodifiers = ?; + } } multiclass VOPCInst <vopc op, string opName, @@ -1845,12 +2370,12 @@ multiclass VOPCInst <vopc op, string opName, VOPC_Helper < op, opName, [], !if(P.HasModifiers, - [(set i1:$dst, + [(set i1:$sdst, (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), cond))], - [(set i1:$dst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), + [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))]), DefExec, revOp, P, sched >; @@ -1859,9 +2384,9 @@ multiclass VOPCClassInst <vopc op, string opName, VOPProfile P, list<SchedReadWrite> sched> : VOPC_Class_Helper < op, opName, [], !if(P.HasModifiers, - [(set i1:$dst, + [(set i1:$sdst, (AMDGPUfp_class (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), P.Src1VT:$src1))], - [(set i1:$dst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), + [(set i1:$sdst, (AMDGPUfp_class P.Src0VT:$src0, P.Src1VT:$src1))]), DefExec, opName, P, sched >; @@ -1897,10 +2422,6 @@ multiclass VOPCX_I32 <vopc op, string opName, string revOp = opName> : multiclass VOPCX_I64 <vopc op, string opName, string revOp = opName> : VOPCX <op, opName, VOPC_I1_I64_I64, COND_NULL, [Write64Bit], revOp>; -multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm, - list<dag> pat, int NumSrcArgs, bit HasMods> : VOP3_m < - op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods ->; multiclass VOPC_CLASS_F32 <vopc op, string opName> : VOPCClassInst <op, opName, VOPC_I1_F32_I32, 0, [Write32Bit]>; @@ -1914,32 +2435,40 @@ multiclass VOPC_CLASS_F64 <vopc op, string opName> : multiclass VOPCX_CLASS_F64 <vopc op, string opName> : VOPCClassInst <op, opName, VOPC_I1_F64_I32, 1, [WriteDoubleAdd]>; + +multiclass VOP3_Helper <vop3 op, string opName, dag outs, dag ins, string asm, + list<dag> pat, int NumSrcArgs, bit HasMods, + bit VOP3Only = 0> : VOP3_m < + op, outs, ins, opName#" "#asm, pat, opName, NumSrcArgs, HasMods, VOP3Only +>; + multiclass VOP3Inst <vop3 op, string opName, VOPProfile P, - SDPatternOperator node = null_frag> : VOP3_Helper < - op, opName, (outs P.DstRC.RegClass:$dst), P.Ins64, P.Asm64, + SDPatternOperator node = null_frag, bit VOP3Only = 0> : + VOP3_Helper < + op, opName, (outs P.DstRC.RegClass:$vdst), P.Ins64, P.Asm64, !if(!eq(P.NumSrcArgs, 3), !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1, + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))]), !if(!eq(P.NumSrcArgs, 2), !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) + [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]) /* P.NumSrcArgs == 1 */, !if(P.HasModifiers, - [(set P.DstVT:$dst, + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))], - [(set P.DstVT:$dst, (node P.Src0VT:$src0))]))), - P.NumSrcArgs, P.HasModifiers + [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]))), + P.NumSrcArgs, P.HasModifiers, VOP3Only >; // Special case for v_div_fmas_{f32|f64}, since it seems to be the @@ -1948,14 +2477,14 @@ multiclass VOP3_VCC_Inst <vop3 op, string opName, VOPProfile P, SDPatternOperator node = null_frag> : VOP3_Helper < op, opName, - (outs P.DstRC.RegClass:$dst), - (ins InputModsNoDefault:$src0_modifiers, P.Src0RC64:$src0, - InputModsNoDefault:$src1_modifiers, P.Src1RC64:$src1, - InputModsNoDefault:$src2_modifiers, P.Src2RC64:$src2, - ClampMod:$clamp, + (outs P.DstRC.RegClass:$vdst), + (ins FPInputMods:$src0_modifiers, P.Src0RC64:$src0, + FPInputMods:$src1_modifiers, P.Src1RC64:$src1, + FPInputMods:$src2_modifiers, P.Src2RC64:$src2, + clampmod:$clamp, omod:$omod), - "$dst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", - [(set P.DstVT:$dst, + "$vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod", + [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)), (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), @@ -1964,11 +2493,11 @@ multiclass VOP3_VCC_Inst <vop3 op, string opName, 3, 1 >; -multiclass VOP3bInst <vop op, string opName, VOPProfile P, list<dag> pattern = []> : +multiclass VOP3bInst <vop op, string opName, VOPProfile P, list<dag> pattern = [], bit VOP3Only = 0> : VOP3b_2_3_m < op, P.Outs64, P.Ins64, opName#" "#P.Asm64, pattern, - opName, "", 1, 1 + opName, "", 1, 1, VOP3Only >; class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat< @@ -1987,7 +2516,7 @@ class Vop3ModPat<Instruction Inst, VOPProfile P, SDPatternOperator node> : Pat< class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : VINTRPCommon <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -1996,13 +2525,21 @@ class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins, string asm> : VINTRPCommon <outs, ins, asm, []>, VINTRPe <op>, - SIMCInstr<opName, SISubtarget.SI>; + SIMCInstr<opName, SIEncodingFamily.SI> { + let AssemblerPredicate = SIAssemblerPredicate; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, string asm> : VINTRPCommon <outs, ins, asm, []>, VINTRPe_vi <op>, - SIMCInstr<opName, SISubtarget.VI>; + SIMCInstr<opName, SIEncodingFamily.VI> { + let AssemblerPredicate = VIAssemblerPredicate; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; +} multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern = []> { @@ -2019,7 +2556,7 @@ multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm, class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : DS <outs, ins, "", pattern>, - SIMCInstr <opName, SISubtarget.NONE> { + SIMCInstr <opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -2027,14 +2564,22 @@ class DS_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : class DS_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> : DS <outs, ins, asm, []>, DSe <op>, - SIMCInstr <opName, SISubtarget.SI> { + SIMCInstr <opName, SIEncodingFamily.SI> { let isCodeGenOnly = 0; + let AssemblerPredicates = [isSICI]; + let DecoderNamespace="SICI"; + let DisableDecoder = DisableSIDecoder; } class DS_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> : DS <outs, ins, asm, []>, DSe_vi <op>, - SIMCInstr <opName, SISubtarget.VI>; + SIMCInstr <opName, SIEncodingFamily.VI> { + let isCodeGenOnly = 0; + let AssemblerPredicates = [isVI]; + let DecoderNamespace="VI"; + let DisableDecoder = DisableVIDecoder; +} class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm> : DS_Real_si <op,opName, outs, ins, asm> { @@ -2043,7 +2588,6 @@ class DS_Off16_Real_si <bits<8> op, string opName, dag outs, dag ins, string asm bits<16> offset; let offset0 = offset{7-0}; let offset1 = offset{15-8}; - let isCodeGenOnly = 0; } class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm> : @@ -2055,9 +2599,24 @@ class DS_Off16_Real_vi <bits<8> op, string opName, dag outs, dag ins, string asm let offset1 = offset{15-8}; } +multiclass DS_1A_RET_ <dsop op, string opName, RegisterClass rc, + dag outs = (outs rc:$vdst), + dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds), + string asm = opName#" $vdst, $addr"#"$offset$gds"> { + + def "" : DS_Pseudo <opName, outs, ins, []>; + + let data0 = 0, data1 = 0 in { + def _si : DS_Off16_Real_si <op.SI, opName, outs, ins, asm>; + def _vi : DS_Off16_Real_vi <op.VI, opName, outs, ins, asm>; + } +} + +// TODO: DS_1A_RET can be inherited from DS_1A_RET_ but its not working +// for some reason. In fact we can remove this class if use dsop everywhere multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds), string asm = opName#" $vdst, $addr"#"$offset$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2070,8 +2629,8 @@ multiclass DS_1A_RET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1, - gds01:$gds), + dag ins = (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, + gds:$gds), string asm = opName#" $vdst, $addr"#"$offset0"#"$offset1$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2084,7 +2643,7 @@ multiclass DS_1A_Off8_RET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs), - dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), string asm = opName#" $addr, $data0"#"$offset$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>, @@ -2096,11 +2655,25 @@ multiclass DS_1A1D_NORET <bits<8> op, string opName, RegisterClass rc, } } -multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, +multiclass DS_1A_Off8_NORET <bits<8> op, string opName, + dag outs = (outs), + dag ins = (ins VGPR_32:$addr, + offset0:$offset0, offset1:$offset1, gds:$gds), + string asm = opName#" $addr $offset0"#"$offset1$gds"> { + + def "" : DS_Pseudo <opName, outs, ins, []>; + + let data0 = 0, data1 = 0, vdst = 0, AsmMatchConverter = "cvtDSOffset01" in { + def _si : DS_Real_si <op, opName, outs, ins, asm>; + def _vi : DS_Real_vi <op, opName, outs, ins, asm>; + } +} + +multiclass DS_1A2D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, dag outs = (outs), dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, - ds_offset0:$offset0, ds_offset1:$offset1, gds01:$gds), - string asm = opName#" $addr, $data0, $data1"#"$offset0"#"$offset1"#"$gds"> { + offset0:$offset0, offset1:$offset1, gds:$gds), + string asm = opName#" $addr, $data0, $data1$offset0$offset1$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2113,7 +2686,7 @@ multiclass DS_1A1D_Off8_NORET <bits<8> op, string opName, RegisterClass rc, multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc, string noRetOp = "", dag outs = (outs rc:$vdst), - dag ins = (ins VGPR_32:$addr, rc:$data0, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset, gds:$gds), string asm = opName#" $vdst, $addr, $data0"#"$offset$gds"> { let hasPostISelHook = 1 in { @@ -2127,6 +2700,23 @@ multiclass DS_1A1D_RET <bits<8> op, string opName, RegisterClass rc, } } +multiclass DS_1A1D_PERMUTE <bits<8> op, string opName, RegisterClass rc, + SDPatternOperator node = null_frag, + dag outs = (outs rc:$vdst), + dag ins = (ins VGPR_32:$addr, rc:$data0, offset:$offset), + string asm = opName#" $vdst, $addr, $data0"#"$offset"> { + + let mayLoad = 0, mayStore = 0, isConvergent = 1 in { + def "" : DS_Pseudo <opName, outs, ins, + [(set i32:$vdst, + (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))]>; + + let data1 = 0, gds = 0 in { + def "_vi" : DS_Off16_Real_vi <op, opName, outs, ins, asm>; + } + } +} + multiclass DS_1A2D_RET_m <bits<8> op, string opName, RegisterClass rc, string noRetOp = "", dag ins, dag outs = (outs rc:$vdst), @@ -2145,14 +2735,14 @@ multiclass DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = "", RegisterClass src = rc> : DS_1A2D_RET_m <op, asm, rc, noRetOp, (ins VGPR_32:$addr, src:$data0, src:$data1, - ds_offset:$offset, gds:$gds) + offset:$offset, gds:$gds) >; multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc, string noRetOp = opName, dag outs = (outs), dag ins = (ins VGPR_32:$addr, rc:$data0, rc:$data1, - ds_offset:$offset, gds:$gds), + offset:$offset, gds:$gds), string asm = opName#" $addr, $data0, $data1"#"$offset"#"$gds"> { def "" : DS_Pseudo <opName, outs, ins, []>, @@ -2166,7 +2756,7 @@ multiclass DS_1A2D_NORET <bits<8> op, string opName, RegisterClass rc, multiclass DS_0A_RET <bits<8> op, string opName, dag outs = (outs VGPR_32:$vdst), - dag ins = (ins ds_offset:$offset, gds:$gds), + dag ins = (ins offset:$offset, gds:$gds), string asm = opName#" $vdst"#"$offset"#"$gds"> { let mayLoad = 1, mayStore = 1 in { @@ -2181,7 +2771,7 @@ multiclass DS_0A_RET <bits<8> op, string opName, multiclass DS_1A_RET_GDS <bits<8> op, string opName, dag outs = (outs VGPR_32:$vdst), - dag ins = (ins VGPR_32:$addr, ds_offset_gds:$offset), + dag ins = (ins VGPR_32:$addr, offset:$offset), string asm = opName#" $vdst, $addr"#"$offset gds"> { def "" : DS_Pseudo <opName, outs, ins, []>; @@ -2207,7 +2797,7 @@ multiclass DS_1A_GDS <bits<8> op, string opName, multiclass DS_1A <bits<8> op, string opName, dag outs = (outs), - dag ins = (ins VGPR_32:$addr, ds_offset:$offset, gds:$gds), + dag ins = (ins VGPR_32:$addr, offset:$offset, gds:$gds), string asm = opName#" $addr"#"$offset"#"$gds"> { let mayLoad = 1, mayStore = 1 in { @@ -2226,7 +2816,7 @@ multiclass DS_1A <bits<8> op, string opName, class MTBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : MTBUF <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } @@ -2235,12 +2825,18 @@ class MTBUF_Real_si <bits<3> op, string opName, dag outs, dag ins, string asm> : MTBUF <outs, ins, asm, []>, MTBUFe <op>, - SIMCInstr<opName, SISubtarget.SI>; + SIMCInstr<opName, SIEncodingFamily.SI> { + let DecoderNamespace="SICI"; + let DisableDecoder = DisableSIDecoder; +} class MTBUF_Real_vi <bits<4> op, string opName, dag outs, dag ins, string asm> : MTBUF <outs, ins, asm, []>, MTBUFe_vi <op>, - SIMCInstr <opName, SISubtarget.VI>; + SIMCInstr <opName, SIEncodingFamily.VI> { + let DecoderNamespace="VI"; + let DisableDecoder = DisableVIDecoder; +} multiclass MTBUF_m <bits<3> op, string opName, dag outs, dag ins, string asm, list<dag> pattern> { @@ -2311,7 +2907,7 @@ class MUBUFAddr64Table <bit is_addr64, string suffix = ""> { class MUBUF_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : MUBUF <outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; @@ -2329,16 +2925,22 @@ class MUBUF_Real_si <mubuf op, string opName, dag outs, dag ins, string asm> : MUBUF <outs, ins, asm, []>, MUBUFe <op.SI>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let lds = 0; + let AssemblerPredicate = SIAssemblerPredicate; + let DecoderNamespace="SICI"; + let DisableDecoder = DisableSIDecoder; } class MUBUF_Real_vi <mubuf op, string opName, dag outs, dag ins, string asm> : MUBUF <outs, ins, asm, []>, MUBUFe_vi <op.VI>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let lds = 0; + let AssemblerPredicate = VIAssemblerPredicate; + let DecoderNamespace="VI"; + let DisableDecoder = DisableVIDecoder; } multiclass MUBUF_m <mubuf op, string opName, dag outs, dag ins, string asm, @@ -2399,38 +3001,82 @@ multiclass MUBUFAtomicAddr64_m <mubuf op, string opName, dag outs, dag ins, // for VI appropriately. } +multiclass MUBUFAtomicOther_m <mubuf op, string opName, dag outs, dag ins, + string asm, list<dag> pattern, bit is_return> { + + def "" : MUBUF_Pseudo <opName, outs, ins, pattern>, + AtomicNoRet<opName, is_return>; + + let tfe = 0 in { + let addr64 = 0 in { + def _si : MUBUF_Real_si <op, opName, outs, ins, asm>; + } + + def _vi : MUBUF_Real_vi <op, opName, outs, ins, asm>; + } +} + multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, ValueType vt, SDPatternOperator atomic> { - let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in { + let mayStore = 1, mayLoad = 1, hasPostISelHook = 1, hasSideEffects = 1 in { // No return variants - let glc = 0 in { + let glc = 0, AsmMatchConverter = "cvtMubufAtomic" in { defm _ADDR64 : MUBUFAtomicAddr64_m < op, name#"_addr64", (outs), (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#"$slc", [], 0 + SCSrc_32:$soffset, offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$slc", [], 0 >; defm _OFFSET : MUBUFAtomicOffset_m < op, name#"_offset", (outs), - (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, mbuf_offset:$offset, + (ins rc:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, offset:$offset, slc:$slc), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$slc", [], 0 + name#" $vdata, off, $srsrc, $soffset$offset$slc", [], 0 >; + + let offen = 1, idxen = 0 in { + defm _OFFEN : MUBUFAtomicOther_m < + op, name#"_offen", (outs), + (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$slc", [], 0 + >; + } + + let offen = 0, idxen = 1 in { + defm _IDXEN : MUBUFAtomicOther_m < + op, name#"_idxen", (outs), + (ins rc:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$slc", [], 0 + >; + } + + let offen = 1, idxen = 1 in { + defm _BOTHEN : MUBUFAtomicOther_m < + op, name#"_bothen", (outs), + (ins rc:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$slc", + [], 0 + >; + } } // glc = 0 // Variant that return values let glc = 1, Constraints = "$vdata = $vdata_in", + AsmMatchConverter = "cvtMubufAtomicReturn", DisableEncoding = "$vdata_in" in { defm _RTN_ADDR64 : MUBUFAtomicAddr64_m < op, name#"_rtn_addr64", (outs rc:$vdata), (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, slc:$slc), - name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"#" glc"#"$slc", + SCSrc_32:$soffset, offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset glc$slc", [(set vt:$vdata, (atomic (MUBUFAddr64Atomic v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$slc), vt:$vdata_in))], 1 @@ -2439,13 +3085,42 @@ multiclass MUBUF_Atomic <mubuf op, string name, RegisterClass rc, defm _RTN_OFFSET : MUBUFAtomicOffset_m < op, name#"_rtn_offset", (outs rc:$vdata), (ins rc:$vdata_in, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, slc:$slc), - name#" $vdata, $srsrc, $soffset"#"$offset"#" glc$slc", + offset:$offset, slc:$slc), + name#" $vdata, off, $srsrc, $soffset$offset glc$slc", [(set vt:$vdata, (atomic (MUBUFOffsetAtomic v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$slc), vt:$vdata_in))], 1 >; + let offen = 1, idxen = 0 in { + defm _RTN_OFFEN : MUBUFAtomicOther_m < + op, name#"_rtn_offen", (outs rc:$vdata), + (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset offen$offset glc$slc", + [], 1 + >; + } + + let offen = 0, idxen = 1 in { + defm _RTN_IDXEN : MUBUFAtomicOther_m < + op, name#"_rtn_idxen", (outs rc:$vdata), + (ins rc:$vdata_in, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset glc$slc", + [], 1 + >; + } + + let offen = 1, idxen = 1 in { + defm _RTN_BOTHEN : MUBUFAtomicOther_m < + op, name#"_rtn_bothen", (outs rc:$vdata), + (ins rc:$vdata_in, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, + offset:$offset, slc:$slc), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset glc$slc", + [], 1 + >; + } } // glc = 1 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1 @@ -2461,8 +3136,8 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, let offen = 0, idxen = 0, vaddr = 0 in { defm _OFFSET : MUBUF_m <op, name#"_offset", (outs regClass:$vdata), (ins SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe", [(set load_vt:$vdata, (ld (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe)))]>; @@ -2471,33 +3146,32 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, let offen = 1, idxen = 0 in { defm _OFFEN : MUBUF_m <op, name#"_offen", (outs regClass:$vdata), (ins VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, slc:$slc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 1 in { defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs regClass:$vdata), (ins VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>; } let offen = 1, idxen = 1 in { defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs regClass:$vdata), (ins VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 0 in { defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs regClass:$vdata), (ins VReg_64:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset addr64"#"$offset"# - "$glc"#"$slc"#"$tfe", + name#" $vdata, $vaddr, $srsrc, $soffset addr64$offset$glc$slc$tfe", [(set load_vt:$vdata, (ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, @@ -2509,18 +3183,11 @@ multiclass MUBUF_Load_Helper <mubuf op, string name, RegisterClass regClass, multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass, ValueType store_vt = i32, SDPatternOperator st = null_frag> { let mayLoad = 0, mayStore = 1 in { - defm : MUBUF_m <op, name, (outs), - (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, offen:$offen, idxen:$idxen, glc:$glc, slc:$slc, - tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset"#"$offen"#"$idxen"#"$offset"# - "$glc"#"$slc"#"$tfe", []>; - let offen = 0, idxen = 0, vaddr = 0 in { defm _OFFSET : MUBUF_m <op, name#"_offset",(outs), (ins vdataClass:$vdata, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $srsrc, $soffset"#"$offset"#"$glc"#"$slc"#"$tfe", + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, off, $srsrc, $soffset$offset$glc$slc$tfe", [(st store_vt:$vdata, (MUBUFOffset v4i32:$srsrc, i32:$soffset, i16:$offset, i1:$glc, i1:$slc, i1:$tfe))]>; } // offen = 0, idxen = 0, vaddr = 0 @@ -2528,35 +3195,35 @@ multiclass MUBUF_Store_Helper <mubuf op, string name, RegisterClass vdataClass, let offen = 1, idxen = 0 in { defm _OFFEN : MUBUF_m <op, name#"_offen", (outs), (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset offen"#"$offset"# - "$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset offen"# + "$offset$glc$slc$tfe", []>; } // end offen = 1, idxen = 0 let offen = 0, idxen = 1 in { defm _IDXEN : MUBUF_m <op, name#"_idxen", (outs), (ins vdataClass:$vdata, VGPR_32:$vaddr, SReg_128:$srsrc, - SCSrc_32:$soffset, mbuf_offset:$offset, glc:$glc, + SCSrc_32:$soffset, offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + name#" $vdata, $vaddr, $srsrc, $soffset idxen$offset$glc$slc$tfe", []>; } let offen = 1, idxen = 1 in { defm _BOTHEN : MUBUF_m <op, name#"_bothen", (outs), (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), - name#" $vdata, $vaddr, $srsrc, $soffset idxen offen"#"$offset"#"$glc"#"$slc"#"$tfe", []>; + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), + name#" $vdata, $vaddr, $srsrc, $soffset idxen offen$offset$glc$slc$tfe", []>; } let offen = 0, idxen = 0 in { defm _ADDR64 : MUBUFAddr64_m <op, name#"_addr64", (outs), (ins vdataClass:$vdata, VReg_64:$vaddr, SReg_128:$srsrc, SCSrc_32:$soffset, - mbuf_offset:$offset, glc:$glc, slc:$slc, + offset:$offset, glc:$glc, slc:$slc, tfe:$tfe), name#" $vdata, $vaddr, $srsrc, $soffset addr64"# - "$offset"#"$glc"#"$slc"#"$tfe", + "$offset$glc$slc$tfe", [(st store_vt:$vdata, (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, i16:$offset, @@ -2593,21 +3260,24 @@ class flat <bits<7> ci, bits<7> vi = ci> { class FLAT_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> : FLAT <0, outs, ins, "", pattern>, - SIMCInstr<opName, SISubtarget.NONE> { + SIMCInstr<opName, SIEncodingFamily.NONE> { let isPseudo = 1; let isCodeGenOnly = 1; } class FLAT_Real_ci <bits<7> op, string opName, dag outs, dag ins, string asm> : FLAT <op, outs, ins, asm, []>, - SIMCInstr<opName, SISubtarget.SI> { + SIMCInstr<opName, SIEncodingFamily.SI> { let AssemblerPredicate = isCIOnly; + let DecoderNamespace="CI"; } class FLAT_Real_vi <bits<7> op, string opName, dag outs, dag ins, string asm> : FLAT <op, outs, ins, asm, []>, - SIMCInstr<opName, SISubtarget.VI> { + SIMCInstr<opName, SIEncodingFamily.VI> { let AssemblerPredicate = VIAssemblerPredicate; + let DecoderNamespace="VI"; + let DisableDecoder = DisableVIDecoder; } multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm, @@ -2623,8 +3293,8 @@ multiclass FLAT_AtomicRet_m <flat op, dag outs, dag ins, string asm, multiclass FLAT_Load_Helper <flat op, string asm_name, RegisterClass regClass, dag outs = (outs regClass:$vdst), - dag ins = (ins VReg_64:$addr, glc_flat:$glc, slc_flat:$slc, tfe_flat:$tfe), - string asm = asm_name#" $vdst, $addr"#"$glc"#"$slc"#"$tfe"> { + dag ins = (ins VReg_64:$addr, glc:$glc, slc:$slc, tfe:$tfe), + string asm = asm_name#" $vdst, $addr$glc$slc$tfe"> { let data = 0, mayLoad = 1 in { @@ -2639,9 +3309,9 @@ multiclass FLAT_Load_Helper <flat op, string asm_name, multiclass FLAT_Store_Helper <flat op, string asm_name, RegisterClass vdataClass, dag outs = (outs), - dag ins = (ins vdataClass:$data, VReg_64:$addr, glc_flat:$glc, - slc_flat:$slc, tfe_flat:$tfe), - string asm = asm_name#" $data, $addr"#"$glc"#"$slc"#"$tfe"> { + dag ins = (ins VReg_64:$addr, vdataClass:$data, glc:$glc, + slc:$slc, tfe:$tfe), + string asm = asm_name#" $addr, $data$glc$slc$tfe"> { let mayLoad = 0, mayStore = 1, vdst = 0 in { @@ -2654,32 +3324,36 @@ multiclass FLAT_Store_Helper <flat op, string asm_name, } multiclass FLAT_ATOMIC <flat op, string asm_name, RegisterClass vdst_rc, + ValueType vt, SDPatternOperator atomic = null_frag, + ValueType data_vt = vt, RegisterClass data_rc = vdst_rc, - dag outs_noret = (outs), string asm_noret = asm_name#" $addr, $data"#"$slc"#"$tfe"> { let mayLoad = 1, mayStore = 1, glc = 0, vdst = 0 in { - def "" : FLAT_Pseudo <NAME, outs_noret, + def "" : FLAT_Pseudo <NAME, (outs), (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), []>, + slc:$slc, tfe:$tfe), []>, AtomicNoRet <NAME, 0>; - def _ci : FLAT_Real_ci <op.CI, NAME, outs_noret, + def _ci : FLAT_Real_ci <op.CI, NAME, (outs), (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), + slc:$slc, tfe:$tfe), asm_noret>; - def _vi : FLAT_Real_vi <op.VI, NAME, outs_noret, + def _vi : FLAT_Real_vi <op.VI, NAME, (outs), (ins VReg_64:$addr, data_rc:$data, - slc_flat_atomic:$slc, tfe_flat_atomic:$tfe), + slc:$slc, tfe:$tfe), asm_noret>; } let glc = 1, hasPostISelHook = 1 in { - defm _RTN : FLAT_AtomicRet_m <op, (outs vdst_rc:$vdst), - (ins VReg_64:$addr, data_rc:$data, slc_flat_atomic:$slc, - tfe_flat_atomic:$tfe), - asm_name#" $vdst, $addr, $data glc"#"$slc"#"$tfe", []>; + defm _RTN : FLAT_AtomicRet_m < + op, (outs vdst_rc:$vdst), + (ins VReg_64:$addr, data_rc:$data, slc:$slc, tfe:$tfe), + asm_name#" $vdst, $addr, $data glc$slc$tfe", + [(set vt:$vdst, + (atomic (FLATAtomic i64:$addr, i1:$slc, i1:$tfe), data_vt:$data))] + >; } } @@ -2688,27 +3362,39 @@ class MIMG_Mask <string op, int channels> { int Channels = channels; } +class mimg <bits<7> si, bits<7> vi = si> { + field bits<7> SI = si; + field bits<7> VI = vi; +} + +class MIMG_Helper <dag outs, dag ins, string asm, + string dns=""> : MIMG<outs, ins, asm,[]> { + let mayLoad = 1; + let mayStore = 0; + let hasPostISelHook = 1; + let DecoderNamespace = dns; + let isAsmParserOnly = !if(!eq(dns,""), 1, 0); + let AsmMatchConverter = "cvtMIMG"; +} + class MIMG_NoSampler_Helper <bits<7> op, string asm, RegisterClass dst_rc, - RegisterClass src_rc> : MIMG < - op, + RegisterClass addr_rc, + string dns=""> : MIMG_Helper < (outs dst_rc:$vdata), - (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, - i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, - SReg_256:$srsrc), - asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," - #" $tfe, $lwe, $slc, $vaddr, $srsrc", - []> { + (ins addr_rc:$vaddr, SReg_256:$srsrc, + dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, + r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), + asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da", + dns>, MIMGe<op> { let ssamp = 0; - let mayLoad = 1; - let mayStore = 0; - let hasPostISelHook = 1; } multiclass MIMG_NoSampler_Src_Helper <bits<7> op, string asm, RegisterClass dst_rc, int channels> { - def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32>, + def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32, + !if(!eq(channels, 1), "AMDGPU", "")>, MIMG_Mask<asm#"_V1", channels>; def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>, MIMG_Mask<asm#"_V2", channels>; @@ -2723,27 +3409,116 @@ multiclass MIMG_NoSampler <bits<7> op, string asm> { defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 4>; } +class MIMG_Store_Helper <bits<7> op, string asm, + RegisterClass data_rc, + RegisterClass addr_rc> : MIMG_Helper < + (outs), + (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, + dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, + r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), + asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" + >, MIMGe<op> { + let ssamp = 0; + let mayLoad = 1; // TableGen requires this for matching with the intrinsics + let mayStore = 1; + let hasSideEffects = 1; + let hasPostISelHook = 0; +} + +multiclass MIMG_Store_Addr_Helper <bits<7> op, string asm, + RegisterClass data_rc, + int channels> { + def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32>, + MIMG_Mask<asm#"_V1", channels>; + def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>, + MIMG_Mask<asm#"_V2", channels>; + def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>, + MIMG_Mask<asm#"_V4", channels>; +} + +multiclass MIMG_Store <bits<7> op, string asm> { + defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>; + defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 2>; + defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 3>; + defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 4>; +} + +class MIMG_Atomic_Helper <string asm, RegisterClass data_rc, + RegisterClass addr_rc> : MIMG_Helper < + (outs data_rc:$vdst), + (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc, + dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, + r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), + asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da" + > { + let mayStore = 1; + let hasSideEffects = 1; + let hasPostISelHook = 0; + let Constraints = "$vdst = $vdata"; + let AsmMatchConverter = "cvtMIMGAtomic"; +} + +class MIMG_Atomic_Real_si<mimg op, string name, string asm, + RegisterClass data_rc, RegisterClass addr_rc> : + MIMG_Atomic_Helper<asm, data_rc, addr_rc>, + SIMCInstr<name, SIEncodingFamily.SI>, + MIMGe<op.SI> { + let isCodeGenOnly = 0; + let AssemblerPredicates = [isSICI]; + let DecoderNamespace = "SICI"; + let DisableDecoder = DisableSIDecoder; +} + +class MIMG_Atomic_Real_vi<mimg op, string name, string asm, + RegisterClass data_rc, RegisterClass addr_rc> : + MIMG_Atomic_Helper<asm, data_rc, addr_rc>, + SIMCInstr<name, SIEncodingFamily.VI>, + MIMGe<op.VI> { + let isCodeGenOnly = 0; + let AssemblerPredicates = [isVI]; + let DecoderNamespace = "VI"; + let DisableDecoder = DisableVIDecoder; +} + +multiclass MIMG_Atomic_Helper_m <mimg op, string name, string asm, + RegisterClass data_rc, RegisterClass addr_rc> { + let isPseudo = 1, isCodeGenOnly = 1 in { + def "" : MIMG_Atomic_Helper<asm, data_rc, addr_rc>, + SIMCInstr<name, SIEncodingFamily.NONE>; + } + + let ssamp = 0 in { + def _si : MIMG_Atomic_Real_si<op, name, asm, data_rc, addr_rc>; + + def _vi : MIMG_Atomic_Real_vi<op, name, asm, data_rc, addr_rc>; + } +} + +multiclass MIMG_Atomic <mimg op, string asm, RegisterClass data_rc = VGPR_32> { + defm _V1 : MIMG_Atomic_Helper_m <op, asm # "_V1", asm, data_rc, VGPR_32>; + defm _V2 : MIMG_Atomic_Helper_m <op, asm # "_V2", asm, data_rc, VReg_64>; + defm _V4 : MIMG_Atomic_Helper_m <op, asm # "_V3", asm, data_rc, VReg_128>; +} + class MIMG_Sampler_Helper <bits<7> op, string asm, RegisterClass dst_rc, - RegisterClass src_rc, int wqm> : MIMG < - op, + RegisterClass src_rc, + int wqm, + string dns=""> : MIMG_Helper < (outs dst_rc:$vdata), - (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, - i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, - SReg_256:$srsrc, SReg_128:$ssamp), - asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," - #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp", - []> { - let mayLoad = 1; - let mayStore = 0; - let hasPostISelHook = 1; + (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, + dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, + r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), + asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da", + dns>, MIMGe<op> { let WQM = wqm; } multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, RegisterClass dst_rc, int channels, int wqm> { - def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm>, + def _V1 : MIMG_Sampler_Helper <op, asm, dst_rc, VGPR_32, wqm, + !if(!eq(channels, 1), "AMDGPU", "")>, MIMG_Mask<asm#"_V1", channels>; def _V2 : MIMG_Sampler_Helper <op, asm, dst_rc, VReg_64, wqm>, MIMG_Mask<asm#"_V2", channels>; @@ -2755,31 +3530,24 @@ multiclass MIMG_Sampler_Src_Helper <bits<7> op, string asm, MIMG_Mask<asm#"_V16", channels>; } -multiclass MIMG_Sampler <bits<7> op, string asm> { - defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 0>; - defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 0>; - defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 0>; - defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 0>; +multiclass MIMG_Sampler <bits<7> op, string asm, int wqm=0> { + defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, wqm>; + defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, wqm>; + defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, wqm>; + defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, wqm>; } -multiclass MIMG_Sampler_WQM <bits<7> op, string asm> { - defm _V1 : MIMG_Sampler_Src_Helper<op, asm, VGPR_32, 1, 1>; - defm _V2 : MIMG_Sampler_Src_Helper<op, asm, VReg_64, 2, 1>; - defm _V3 : MIMG_Sampler_Src_Helper<op, asm, VReg_96, 3, 1>; - defm _V4 : MIMG_Sampler_Src_Helper<op, asm, VReg_128, 4, 1>; -} +multiclass MIMG_Sampler_WQM <bits<7> op, string asm> : MIMG_Sampler<op, asm, 1>; class MIMG_Gather_Helper <bits<7> op, string asm, RegisterClass dst_rc, RegisterClass src_rc, int wqm> : MIMG < - op, (outs dst_rc:$vdata), - (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, - i1imm:$tfe, i1imm:$lwe, i1imm:$slc, src_rc:$vaddr, - SReg_256:$srsrc, SReg_128:$ssamp), - asm#" $vdata, $dmask, $unorm, $glc, $da, $r128," - #" $tfe, $lwe, $slc, $vaddr, $srsrc, $ssamp", - []> { + (ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp, + dmask:$dmask, unorm:$unorm, glc:$glc, slc:$slc, + r128:$r128, tfe:$tfe, lwe:$lwe, da:$da), + asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da", + []>, MIMGe<op> { let mayLoad = 1; let mayStore = 0; @@ -2789,10 +3557,12 @@ class MIMG_Gather_Helper <bits<7> op, string asm, // 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns // (red,red,red,red) etc.) The ISA document doesn't mention // this. - // Therefore, disable all code which updates DMASK by setting these two: - let MIMG = 0; + // Therefore, disable all code which updates DMASK by setting this: + let Gather4 = 1; let hasPostISelHook = 0; let WQM = wqm; + + let isAsmParserOnly = 1; // TBD: fix it later } multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm, @@ -2810,19 +3580,14 @@ multiclass MIMG_Gather_Src_Helper <bits<7> op, string asm, MIMG_Mask<asm#"_V16", channels>; } -multiclass MIMG_Gather <bits<7> op, string asm> { - defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 0>; - defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 0>; - defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 0>; - defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 0>; +multiclass MIMG_Gather <bits<7> op, string asm, int wqm=0> { + defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, wqm>; + defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, wqm>; + defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, wqm>; + defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, wqm>; } -multiclass MIMG_Gather_WQM <bits<7> op, string asm> { - defm _V1 : MIMG_Gather_Src_Helper<op, asm, VGPR_32, 1, 1>; - defm _V2 : MIMG_Gather_Src_Helper<op, asm, VReg_64, 2, 1>; - defm _V3 : MIMG_Gather_Src_Helper<op, asm, VReg_96, 3, 1>; - defm _V4 : MIMG_Gather_Src_Helper<op, asm, VReg_128, 4, 1>; -} +multiclass MIMG_Gather_WQM <bits<7> op, string asm> : MIMG_Gather<op, asm, 1>; //===----------------------------------------------------------------------===// // Vector instruction mappings @@ -2894,8 +3659,9 @@ def getMCOpcodeGen : InstrMapping { let FilterClass = "SIMCInstr"; let RowFields = ["PseudoInstr"]; let ColFields = ["Subtarget"]; - let KeyCol = [!cast<string>(SISubtarget.NONE)]; - let ValueCols = [[!cast<string>(SISubtarget.SI)],[!cast<string>(SISubtarget.VI)]]; + let KeyCol = [!cast<string>(SIEncodingFamily.NONE)]; + let ValueCols = [[!cast<string>(SIEncodingFamily.SI)], + [!cast<string>(SIEncodingFamily.VI)]]; } def getAddr64Inst : InstrMapping { |