diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2016-12-10 15:02:05 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2016-12-10 15:02:05 +0000 |
| commit | 6421cca32f69ac849537a3cff78c352195e99f1b (patch) | |
| tree | 419f8e5570d50a27957e4d3d80abb6639549126f /lib/Target/ARM/ARMExpandPseudoInsts.cpp | |
| parent | 2cf3bd4601bbc6fc1f3ffe845eb57c2da2dff02c (diff) | |
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 56f5728ecfb89..a7b299677c1cc 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -932,13 +932,10 @@ bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB, .addReg(DestLo, getKillRegState(Dest.isDead())) .addReg(DesiredLo, getKillRegState(Desired.isDead()))); - unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr; - MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr)) - .addReg(StatusReg, RegState::Define | RegState::Dead) - .addReg(DestHi, getKillRegState(Dest.isDead())) - .addReg(DesiredHi, getKillRegState(Desired.isDead())); - AddDefaultPred(MIB); - MIB.addReg(ARM::CPSR, RegState::Kill); + BuildMI(LoadCmpBB, DL, TII->get(CMPrr)) + .addReg(DestHi, getKillRegState(Dest.isDead())) + .addReg(DesiredHi, getKillRegState(Desired.isDead())) + .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc; BuildMI(LoadCmpBB, DL, TII->get(Bcc)) |